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s390.c (s390_gimplify_va_arg): Revert change from r187965.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48 #include "debug.h"
49 #include "langhooks.h"
50 #include "optabs.h"
51 #include "gimple.h"
52 #include "df.h"
53 #include "params.h"
54 #include "cfgloop.h"
55 #include "opts.h"
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (1) , /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (1), /* MADBR */
213 COSTS_N_INSNS (1), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 static const
225 struct processor_costs z196_cost =
226 {
227 COSTS_N_INSNS (7), /* M */
228 COSTS_N_INSNS (5), /* MGHI */
229 COSTS_N_INSNS (5), /* MH */
230 COSTS_N_INSNS (5), /* MHI */
231 COSTS_N_INSNS (7), /* ML */
232 COSTS_N_INSNS (7), /* MR */
233 COSTS_N_INSNS (6), /* MS */
234 COSTS_N_INSNS (8), /* MSG */
235 COSTS_N_INSNS (6), /* MSGF */
236 COSTS_N_INSNS (6), /* MSGFR */
237 COSTS_N_INSNS (8), /* MSGR */
238 COSTS_N_INSNS (6), /* MSR */
239 COSTS_N_INSNS (1) , /* multiplication in DFmode */
240 COSTS_N_INSNS (40), /* MXBR B+40 */
241 COSTS_N_INSNS (100), /* SQXBR B+100 */
242 COSTS_N_INSNS (42), /* SQDBR B+42 */
243 COSTS_N_INSNS (28), /* SQEBR B+28 */
244 COSTS_N_INSNS (1), /* MADBR B */
245 COSTS_N_INSNS (1), /* MAEBR B */
246 COSTS_N_INSNS (101), /* DXBR B+101 */
247 COSTS_N_INSNS (29), /* DDBR */
248 COSTS_N_INSNS (22), /* DEBR */
249 COSTS_N_INSNS (160), /* DLGR cracked */
250 COSTS_N_INSNS (160), /* DLR cracked */
251 COSTS_N_INSNS (160), /* DR expanded */
252 COSTS_N_INSNS (160), /* DSGFR cracked */
253 COSTS_N_INSNS (160), /* DSGR cracked */
254 };
255
256 extern int reload_completed;
257
258 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
259 static rtx last_scheduled_insn;
260
261 /* Structure used to hold the components of a S/390 memory
262 address. A legitimate address on S/390 is of the general
263 form
264 base + index + displacement
265 where any of the components is optional.
266
267 base and index are registers of the class ADDR_REGS,
268 displacement is an unsigned 12-bit immediate constant. */
269
270 struct s390_address
271 {
272 rtx base;
273 rtx indx;
274 rtx disp;
275 bool pointer;
276 bool literal_pool;
277 };
278
279 /* The following structure is embedded in the machine
280 specific part of struct function. */
281
282 struct GTY (()) s390_frame_layout
283 {
284 /* Offset within stack frame. */
285 HOST_WIDE_INT gprs_offset;
286 HOST_WIDE_INT f0_offset;
287 HOST_WIDE_INT f4_offset;
288 HOST_WIDE_INT f8_offset;
289 HOST_WIDE_INT backchain_offset;
290
291 /* Number of first and last gpr where slots in the register
292 save area are reserved for. */
293 int first_save_gpr_slot;
294 int last_save_gpr_slot;
295
296 /* Number of first and last gpr to be saved, restored. */
297 int first_save_gpr;
298 int first_restore_gpr;
299 int last_save_gpr;
300 int last_restore_gpr;
301
302 /* Bits standing for floating point registers. Set, if the
303 respective register has to be saved. Starting with reg 16 (f0)
304 at the rightmost bit.
305 Bit 15 - 8 7 6 5 4 3 2 1 0
306 fpr 15 - 8 7 5 3 1 6 4 2 0
307 reg 31 - 24 23 22 21 20 19 18 17 16 */
308 unsigned int fpr_bitmap;
309
310 /* Number of floating point registers f8-f15 which must be saved. */
311 int high_fprs;
312
313 /* Set if return address needs to be saved.
314 This flag is set by s390_return_addr_rtx if it could not use
315 the initial value of r14 and therefore depends on r14 saved
316 to the stack. */
317 bool save_return_addr_p;
318
319 /* Size of stack frame. */
320 HOST_WIDE_INT frame_size;
321 };
322
323 /* Define the structure for the machine field in struct function. */
324
325 struct GTY(()) machine_function
326 {
327 struct s390_frame_layout frame_layout;
328
329 /* Literal pool base register. */
330 rtx base_reg;
331
332 /* True if we may need to perform branch splitting. */
333 bool split_branches_pending_p;
334
335 /* Some local-dynamic TLS symbol name. */
336 const char *some_ld_name;
337
338 bool has_landing_pad_p;
339 };
340
341 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
342
343 #define cfun_frame_layout (cfun->machine->frame_layout)
344 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
345 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
346 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
347 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
348 (1 << (BITNUM)))
349 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
350 (1 << (BITNUM))))
351
352 /* Number of GPRs and FPRs used for argument passing. */
353 #define GP_ARG_NUM_REG 5
354 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
355
356 /* A couple of shortcuts. */
357 #define CONST_OK_FOR_J(x) \
358 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
359 #define CONST_OK_FOR_K(x) \
360 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
361 #define CONST_OK_FOR_Os(x) \
362 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
363 #define CONST_OK_FOR_Op(x) \
364 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
365 #define CONST_OK_FOR_On(x) \
366 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
367
368 #define REGNO_PAIR_OK(REGNO, MODE) \
369 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
370
371 /* That's the read ahead of the dynamic branch prediction unit in
372 bytes on a z10 (or higher) CPU. */
373 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
374
375 /* Return the alignment for LABEL. We default to the -falign-labels
376 value except for the literal pool base label. */
377 int
378 s390_label_align (rtx label)
379 {
380 rtx prev_insn = prev_active_insn (label);
381
382 if (prev_insn == NULL_RTX)
383 goto old;
384
385 prev_insn = single_set (prev_insn);
386
387 if (prev_insn == NULL_RTX)
388 goto old;
389
390 prev_insn = SET_SRC (prev_insn);
391
392 /* Don't align literal pool base labels. */
393 if (GET_CODE (prev_insn) == UNSPEC
394 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
395 return 0;
396
397 old:
398 return align_labels_log;
399 }
400
401 static enum machine_mode
402 s390_libgcc_cmp_return_mode (void)
403 {
404 return TARGET_64BIT ? DImode : SImode;
405 }
406
407 static enum machine_mode
408 s390_libgcc_shift_count_mode (void)
409 {
410 return TARGET_64BIT ? DImode : SImode;
411 }
412
413 static enum machine_mode
414 s390_unwind_word_mode (void)
415 {
416 return TARGET_64BIT ? DImode : SImode;
417 }
418
419 /* Return true if the back end supports mode MODE. */
420 static bool
421 s390_scalar_mode_supported_p (enum machine_mode mode)
422 {
423 /* In contrast to the default implementation reject TImode constants on 31bit
424 TARGET_ZARCH for ABI compliance. */
425 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
426 return false;
427
428 if (DECIMAL_FLOAT_MODE_P (mode))
429 return default_decimal_float_supported_p ();
430
431 return default_scalar_mode_supported_p (mode);
432 }
433
434 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
435
436 void
437 s390_set_has_landing_pad_p (bool value)
438 {
439 cfun->machine->has_landing_pad_p = value;
440 }
441
442 /* If two condition code modes are compatible, return a condition code
443 mode which is compatible with both. Otherwise, return
444 VOIDmode. */
445
446 static enum machine_mode
447 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
448 {
449 if (m1 == m2)
450 return m1;
451
452 switch (m1)
453 {
454 case CCZmode:
455 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
456 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
457 return m2;
458 return VOIDmode;
459
460 case CCSmode:
461 case CCUmode:
462 case CCTmode:
463 case CCSRmode:
464 case CCURmode:
465 case CCZ1mode:
466 if (m2 == CCZmode)
467 return m1;
468
469 return VOIDmode;
470
471 default:
472 return VOIDmode;
473 }
474 return VOIDmode;
475 }
476
477 /* Return true if SET either doesn't set the CC register, or else
478 the source and destination have matching CC modes and that
479 CC mode is at least as constrained as REQ_MODE. */
480
481 static bool
482 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
483 {
484 enum machine_mode set_mode;
485
486 gcc_assert (GET_CODE (set) == SET);
487
488 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
489 return 1;
490
491 set_mode = GET_MODE (SET_DEST (set));
492 switch (set_mode)
493 {
494 case CCSmode:
495 case CCSRmode:
496 case CCUmode:
497 case CCURmode:
498 case CCLmode:
499 case CCL1mode:
500 case CCL2mode:
501 case CCL3mode:
502 case CCT1mode:
503 case CCT2mode:
504 case CCT3mode:
505 if (req_mode != set_mode)
506 return 0;
507 break;
508
509 case CCZmode:
510 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
511 && req_mode != CCSRmode && req_mode != CCURmode)
512 return 0;
513 break;
514
515 case CCAPmode:
516 case CCANmode:
517 if (req_mode != CCAmode)
518 return 0;
519 break;
520
521 default:
522 gcc_unreachable ();
523 }
524
525 return (GET_MODE (SET_SRC (set)) == set_mode);
526 }
527
528 /* Return true if every SET in INSN that sets the CC register
529 has source and destination with matching CC modes and that
530 CC mode is at least as constrained as REQ_MODE.
531 If REQ_MODE is VOIDmode, always return false. */
532
533 bool
534 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
535 {
536 int i;
537
538 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
539 if (req_mode == VOIDmode)
540 return false;
541
542 if (GET_CODE (PATTERN (insn)) == SET)
543 return s390_match_ccmode_set (PATTERN (insn), req_mode);
544
545 if (GET_CODE (PATTERN (insn)) == PARALLEL)
546 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
547 {
548 rtx set = XVECEXP (PATTERN (insn), 0, i);
549 if (GET_CODE (set) == SET)
550 if (!s390_match_ccmode_set (set, req_mode))
551 return false;
552 }
553
554 return true;
555 }
556
557 /* If a test-under-mask instruction can be used to implement
558 (compare (and ... OP1) OP2), return the CC mode required
559 to do that. Otherwise, return VOIDmode.
560 MIXED is true if the instruction can distinguish between
561 CC1 and CC2 for mixed selected bits (TMxx), it is false
562 if the instruction cannot (TM). */
563
564 enum machine_mode
565 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
566 {
567 int bit0, bit1;
568
569 /* ??? Fixme: should work on CONST_DOUBLE as well. */
570 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
571 return VOIDmode;
572
573 /* Selected bits all zero: CC0.
574 e.g.: int a; if ((a & (16 + 128)) == 0) */
575 if (INTVAL (op2) == 0)
576 return CCTmode;
577
578 /* Selected bits all one: CC3.
579 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
580 if (INTVAL (op2) == INTVAL (op1))
581 return CCT3mode;
582
583 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
584 int a;
585 if ((a & (16 + 128)) == 16) -> CCT1
586 if ((a & (16 + 128)) == 128) -> CCT2 */
587 if (mixed)
588 {
589 bit1 = exact_log2 (INTVAL (op2));
590 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
591 if (bit0 != -1 && bit1 != -1)
592 return bit0 > bit1 ? CCT1mode : CCT2mode;
593 }
594
595 return VOIDmode;
596 }
597
598 /* Given a comparison code OP (EQ, NE, etc.) and the operands
599 OP0 and OP1 of a COMPARE, return the mode to be used for the
600 comparison. */
601
602 enum machine_mode
603 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
604 {
605 switch (code)
606 {
607 case EQ:
608 case NE:
609 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
610 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
611 return CCAPmode;
612 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
613 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
614 return CCAPmode;
615 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
616 || GET_CODE (op1) == NEG)
617 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
618 return CCLmode;
619
620 if (GET_CODE (op0) == AND)
621 {
622 /* Check whether we can potentially do it via TM. */
623 enum machine_mode ccmode;
624 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
625 if (ccmode != VOIDmode)
626 {
627 /* Relax CCTmode to CCZmode to allow fall-back to AND
628 if that turns out to be beneficial. */
629 return ccmode == CCTmode ? CCZmode : ccmode;
630 }
631 }
632
633 if (register_operand (op0, HImode)
634 && GET_CODE (op1) == CONST_INT
635 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
636 return CCT3mode;
637 if (register_operand (op0, QImode)
638 && GET_CODE (op1) == CONST_INT
639 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
640 return CCT3mode;
641
642 return CCZmode;
643
644 case LE:
645 case LT:
646 case GE:
647 case GT:
648 /* The only overflow condition of NEG and ABS happens when
649 -INT_MAX is used as parameter, which stays negative. So
650 we have an overflow from a positive value to a negative.
651 Using CCAP mode the resulting cc can be used for comparisons. */
652 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
653 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
654 return CCAPmode;
655
656 /* If constants are involved in an add instruction it is possible to use
657 the resulting cc for comparisons with zero. Knowing the sign of the
658 constant the overflow behavior gets predictable. e.g.:
659 int a, b; if ((b = a + c) > 0)
660 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
661 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
662 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
663 {
664 if (INTVAL (XEXP((op0), 1)) < 0)
665 return CCANmode;
666 else
667 return CCAPmode;
668 }
669 /* Fall through. */
670 case UNORDERED:
671 case ORDERED:
672 case UNEQ:
673 case UNLE:
674 case UNLT:
675 case UNGE:
676 case UNGT:
677 case LTGT:
678 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
679 && GET_CODE (op1) != CONST_INT)
680 return CCSRmode;
681 return CCSmode;
682
683 case LTU:
684 case GEU:
685 if (GET_CODE (op0) == PLUS
686 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
687 return CCL1mode;
688
689 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
690 && GET_CODE (op1) != CONST_INT)
691 return CCURmode;
692 return CCUmode;
693
694 case LEU:
695 case GTU:
696 if (GET_CODE (op0) == MINUS
697 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
698 return CCL2mode;
699
700 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
701 && GET_CODE (op1) != CONST_INT)
702 return CCURmode;
703 return CCUmode;
704
705 default:
706 gcc_unreachable ();
707 }
708 }
709
710 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
711 that we can implement more efficiently. */
712
713 void
714 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
715 {
716 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
717 if ((*code == EQ || *code == NE)
718 && *op1 == const0_rtx
719 && GET_CODE (*op0) == ZERO_EXTRACT
720 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
721 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
722 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
723 {
724 rtx inner = XEXP (*op0, 0);
725 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
726 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
727 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
728
729 if (len > 0 && len < modesize
730 && pos >= 0 && pos + len <= modesize
731 && modesize <= HOST_BITS_PER_WIDE_INT)
732 {
733 unsigned HOST_WIDE_INT block;
734 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
735 block <<= modesize - pos - len;
736
737 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
738 gen_int_mode (block, GET_MODE (inner)));
739 }
740 }
741
742 /* Narrow AND of memory against immediate to enable TM. */
743 if ((*code == EQ || *code == NE)
744 && *op1 == const0_rtx
745 && GET_CODE (*op0) == AND
746 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
747 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
748 {
749 rtx inner = XEXP (*op0, 0);
750 rtx mask = XEXP (*op0, 1);
751
752 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
753 if (GET_CODE (inner) == SUBREG
754 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
755 && (GET_MODE_SIZE (GET_MODE (inner))
756 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
757 && ((INTVAL (mask)
758 & GET_MODE_MASK (GET_MODE (inner))
759 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
760 == 0))
761 inner = SUBREG_REG (inner);
762
763 /* Do not change volatile MEMs. */
764 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
765 {
766 int part = s390_single_part (XEXP (*op0, 1),
767 GET_MODE (inner), QImode, 0);
768 if (part >= 0)
769 {
770 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
771 inner = adjust_address_nv (inner, QImode, part);
772 *op0 = gen_rtx_AND (QImode, inner, mask);
773 }
774 }
775 }
776
777 /* Narrow comparisons against 0xffff to HImode if possible. */
778 if ((*code == EQ || *code == NE)
779 && GET_CODE (*op1) == CONST_INT
780 && INTVAL (*op1) == 0xffff
781 && SCALAR_INT_MODE_P (GET_MODE (*op0))
782 && (nonzero_bits (*op0, GET_MODE (*op0))
783 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
784 {
785 *op0 = gen_lowpart (HImode, *op0);
786 *op1 = constm1_rtx;
787 }
788
789 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
790 if (GET_CODE (*op0) == UNSPEC
791 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
792 && XVECLEN (*op0, 0) == 1
793 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
794 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
795 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
796 && *op1 == const0_rtx)
797 {
798 enum rtx_code new_code = UNKNOWN;
799 switch (*code)
800 {
801 case EQ: new_code = EQ; break;
802 case NE: new_code = NE; break;
803 case LT: new_code = GTU; break;
804 case GT: new_code = LTU; break;
805 case LE: new_code = GEU; break;
806 case GE: new_code = LEU; break;
807 default: break;
808 }
809
810 if (new_code != UNKNOWN)
811 {
812 *op0 = XVECEXP (*op0, 0, 0);
813 *code = new_code;
814 }
815 }
816
817 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
818 if (GET_CODE (*op0) == UNSPEC
819 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
820 && XVECLEN (*op0, 0) == 1
821 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
822 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
823 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
824 && *op1 == const0_rtx)
825 {
826 enum rtx_code new_code = UNKNOWN;
827 switch (*code)
828 {
829 case EQ: new_code = EQ; break;
830 case NE: new_code = NE; break;
831 default: break;
832 }
833
834 if (new_code != UNKNOWN)
835 {
836 *op0 = XVECEXP (*op0, 0, 0);
837 *code = new_code;
838 }
839 }
840
841 /* Simplify cascaded EQ, NE with const0_rtx. */
842 if ((*code == NE || *code == EQ)
843 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
844 && GET_MODE (*op0) == SImode
845 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
846 && REG_P (XEXP (*op0, 0))
847 && XEXP (*op0, 1) == const0_rtx
848 && *op1 == const0_rtx)
849 {
850 if ((*code == EQ && GET_CODE (*op0) == NE)
851 || (*code == NE && GET_CODE (*op0) == EQ))
852 *code = EQ;
853 else
854 *code = NE;
855 *op0 = XEXP (*op0, 0);
856 }
857
858 /* Prefer register over memory as first operand. */
859 if (MEM_P (*op0) && REG_P (*op1))
860 {
861 rtx tem = *op0; *op0 = *op1; *op1 = tem;
862 *code = swap_condition (*code);
863 }
864 }
865
866 /* Emit a compare instruction suitable to implement the comparison
867 OP0 CODE OP1. Return the correct condition RTL to be placed in
868 the IF_THEN_ELSE of the conditional branch testing the result. */
869
870 rtx
871 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
872 {
873 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
874 rtx cc;
875
876 /* Do not output a redundant compare instruction if a compare_and_swap
877 pattern already computed the result and the machine modes are compatible. */
878 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
879 {
880 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
881 == GET_MODE (op0));
882 cc = op0;
883 }
884 else
885 {
886 cc = gen_rtx_REG (mode, CC_REGNUM);
887 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
888 }
889
890 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
891 }
892
893 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
894 matches CMP.
895 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
896 conditional branch testing the result. */
897
898 static rtx
899 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
900 {
901 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
902 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
903 }
904
905 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
906 unconditional jump, else a conditional jump under condition COND. */
907
908 void
909 s390_emit_jump (rtx target, rtx cond)
910 {
911 rtx insn;
912
913 target = gen_rtx_LABEL_REF (VOIDmode, target);
914 if (cond)
915 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
916
917 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
918 emit_jump_insn (insn);
919 }
920
921 /* Return branch condition mask to implement a branch
922 specified by CODE. Return -1 for invalid comparisons. */
923
924 int
925 s390_branch_condition_mask (rtx code)
926 {
927 const int CC0 = 1 << 3;
928 const int CC1 = 1 << 2;
929 const int CC2 = 1 << 1;
930 const int CC3 = 1 << 0;
931
932 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
933 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
934 gcc_assert (XEXP (code, 1) == const0_rtx);
935
936 switch (GET_MODE (XEXP (code, 0)))
937 {
938 case CCZmode:
939 case CCZ1mode:
940 switch (GET_CODE (code))
941 {
942 case EQ: return CC0;
943 case NE: return CC1 | CC2 | CC3;
944 default: return -1;
945 }
946 break;
947
948 case CCT1mode:
949 switch (GET_CODE (code))
950 {
951 case EQ: return CC1;
952 case NE: return CC0 | CC2 | CC3;
953 default: return -1;
954 }
955 break;
956
957 case CCT2mode:
958 switch (GET_CODE (code))
959 {
960 case EQ: return CC2;
961 case NE: return CC0 | CC1 | CC3;
962 default: return -1;
963 }
964 break;
965
966 case CCT3mode:
967 switch (GET_CODE (code))
968 {
969 case EQ: return CC3;
970 case NE: return CC0 | CC1 | CC2;
971 default: return -1;
972 }
973 break;
974
975 case CCLmode:
976 switch (GET_CODE (code))
977 {
978 case EQ: return CC0 | CC2;
979 case NE: return CC1 | CC3;
980 default: return -1;
981 }
982 break;
983
984 case CCL1mode:
985 switch (GET_CODE (code))
986 {
987 case LTU: return CC2 | CC3; /* carry */
988 case GEU: return CC0 | CC1; /* no carry */
989 default: return -1;
990 }
991 break;
992
993 case CCL2mode:
994 switch (GET_CODE (code))
995 {
996 case GTU: return CC0 | CC1; /* borrow */
997 case LEU: return CC2 | CC3; /* no borrow */
998 default: return -1;
999 }
1000 break;
1001
1002 case CCL3mode:
1003 switch (GET_CODE (code))
1004 {
1005 case EQ: return CC0 | CC2;
1006 case NE: return CC1 | CC3;
1007 case LTU: return CC1;
1008 case GTU: return CC3;
1009 case LEU: return CC1 | CC2;
1010 case GEU: return CC2 | CC3;
1011 default: return -1;
1012 }
1013
1014 case CCUmode:
1015 switch (GET_CODE (code))
1016 {
1017 case EQ: return CC0;
1018 case NE: return CC1 | CC2 | CC3;
1019 case LTU: return CC1;
1020 case GTU: return CC2;
1021 case LEU: return CC0 | CC1;
1022 case GEU: return CC0 | CC2;
1023 default: return -1;
1024 }
1025 break;
1026
1027 case CCURmode:
1028 switch (GET_CODE (code))
1029 {
1030 case EQ: return CC0;
1031 case NE: return CC2 | CC1 | CC3;
1032 case LTU: return CC2;
1033 case GTU: return CC1;
1034 case LEU: return CC0 | CC2;
1035 case GEU: return CC0 | CC1;
1036 default: return -1;
1037 }
1038 break;
1039
1040 case CCAPmode:
1041 switch (GET_CODE (code))
1042 {
1043 case EQ: return CC0;
1044 case NE: return CC1 | CC2 | CC3;
1045 case LT: return CC1 | CC3;
1046 case GT: return CC2;
1047 case LE: return CC0 | CC1 | CC3;
1048 case GE: return CC0 | CC2;
1049 default: return -1;
1050 }
1051 break;
1052
1053 case CCANmode:
1054 switch (GET_CODE (code))
1055 {
1056 case EQ: return CC0;
1057 case NE: return CC1 | CC2 | CC3;
1058 case LT: return CC1;
1059 case GT: return CC2 | CC3;
1060 case LE: return CC0 | CC1;
1061 case GE: return CC0 | CC2 | CC3;
1062 default: return -1;
1063 }
1064 break;
1065
1066 case CCSmode:
1067 switch (GET_CODE (code))
1068 {
1069 case EQ: return CC0;
1070 case NE: return CC1 | CC2 | CC3;
1071 case LT: return CC1;
1072 case GT: return CC2;
1073 case LE: return CC0 | CC1;
1074 case GE: return CC0 | CC2;
1075 case UNORDERED: return CC3;
1076 case ORDERED: return CC0 | CC1 | CC2;
1077 case UNEQ: return CC0 | CC3;
1078 case UNLT: return CC1 | CC3;
1079 case UNGT: return CC2 | CC3;
1080 case UNLE: return CC0 | CC1 | CC3;
1081 case UNGE: return CC0 | CC2 | CC3;
1082 case LTGT: return CC1 | CC2;
1083 default: return -1;
1084 }
1085 break;
1086
1087 case CCSRmode:
1088 switch (GET_CODE (code))
1089 {
1090 case EQ: return CC0;
1091 case NE: return CC2 | CC1 | CC3;
1092 case LT: return CC2;
1093 case GT: return CC1;
1094 case LE: return CC0 | CC2;
1095 case GE: return CC0 | CC1;
1096 case UNORDERED: return CC3;
1097 case ORDERED: return CC0 | CC2 | CC1;
1098 case UNEQ: return CC0 | CC3;
1099 case UNLT: return CC2 | CC3;
1100 case UNGT: return CC1 | CC3;
1101 case UNLE: return CC0 | CC2 | CC3;
1102 case UNGE: return CC0 | CC1 | CC3;
1103 case LTGT: return CC2 | CC1;
1104 default: return -1;
1105 }
1106 break;
1107
1108 default:
1109 return -1;
1110 }
1111 }
1112
1113
1114 /* Return branch condition mask to implement a compare and branch
1115 specified by CODE. Return -1 for invalid comparisons. */
1116
1117 int
1118 s390_compare_and_branch_condition_mask (rtx code)
1119 {
1120 const int CC0 = 1 << 3;
1121 const int CC1 = 1 << 2;
1122 const int CC2 = 1 << 1;
1123
1124 switch (GET_CODE (code))
1125 {
1126 case EQ:
1127 return CC0;
1128 case NE:
1129 return CC1 | CC2;
1130 case LT:
1131 case LTU:
1132 return CC1;
1133 case GT:
1134 case GTU:
1135 return CC2;
1136 case LE:
1137 case LEU:
1138 return CC0 | CC1;
1139 case GE:
1140 case GEU:
1141 return CC0 | CC2;
1142 default:
1143 gcc_unreachable ();
1144 }
1145 return -1;
1146 }
1147
1148 /* If INV is false, return assembler mnemonic string to implement
1149 a branch specified by CODE. If INV is true, return mnemonic
1150 for the corresponding inverted branch. */
1151
1152 static const char *
1153 s390_branch_condition_mnemonic (rtx code, int inv)
1154 {
1155 int mask;
1156
1157 static const char *const mnemonic[16] =
1158 {
1159 NULL, "o", "h", "nle",
1160 "l", "nhe", "lh", "ne",
1161 "e", "nlh", "he", "nl",
1162 "le", "nh", "no", NULL
1163 };
1164
1165 if (GET_CODE (XEXP (code, 0)) == REG
1166 && REGNO (XEXP (code, 0)) == CC_REGNUM
1167 && XEXP (code, 1) == const0_rtx)
1168 mask = s390_branch_condition_mask (code);
1169 else
1170 mask = s390_compare_and_branch_condition_mask (code);
1171
1172 gcc_assert (mask >= 0);
1173
1174 if (inv)
1175 mask ^= 15;
1176
1177 gcc_assert (mask >= 1 && mask <= 14);
1178
1179 return mnemonic[mask];
1180 }
1181
1182 /* Return the part of op which has a value different from def.
1183 The size of the part is determined by mode.
1184 Use this function only if you already know that op really
1185 contains such a part. */
1186
1187 unsigned HOST_WIDE_INT
1188 s390_extract_part (rtx op, enum machine_mode mode, int def)
1189 {
1190 unsigned HOST_WIDE_INT value = 0;
1191 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1192 int part_bits = GET_MODE_BITSIZE (mode);
1193 unsigned HOST_WIDE_INT part_mask
1194 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1195 int i;
1196
1197 for (i = 0; i < max_parts; i++)
1198 {
1199 if (i == 0)
1200 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1201 else
1202 value >>= part_bits;
1203
1204 if ((value & part_mask) != (def & part_mask))
1205 return value & part_mask;
1206 }
1207
1208 gcc_unreachable ();
1209 }
1210
1211 /* If OP is an integer constant of mode MODE with exactly one
1212 part of mode PART_MODE unequal to DEF, return the number of that
1213 part. Otherwise, return -1. */
1214
1215 int
1216 s390_single_part (rtx op,
1217 enum machine_mode mode,
1218 enum machine_mode part_mode,
1219 int def)
1220 {
1221 unsigned HOST_WIDE_INT value = 0;
1222 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1223 unsigned HOST_WIDE_INT part_mask
1224 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1225 int i, part = -1;
1226
1227 if (GET_CODE (op) != CONST_INT)
1228 return -1;
1229
1230 for (i = 0; i < n_parts; i++)
1231 {
1232 if (i == 0)
1233 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1234 else
1235 value >>= GET_MODE_BITSIZE (part_mode);
1236
1237 if ((value & part_mask) != (def & part_mask))
1238 {
1239 if (part != -1)
1240 return -1;
1241 else
1242 part = i;
1243 }
1244 }
1245 return part == -1 ? -1 : n_parts - 1 - part;
1246 }
1247
1248 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1249 bits and no other bits are set in IN. POS and LENGTH can be used
1250 to obtain the start position and the length of the bitfield.
1251
1252 POS gives the position of the first bit of the bitfield counting
1253 from the lowest order bit starting with zero. In order to use this
1254 value for S/390 instructions this has to be converted to "bits big
1255 endian" style. */
1256
1257 bool
1258 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1259 int *pos, int *length)
1260 {
1261 int tmp_pos = 0;
1262 int tmp_length = 0;
1263 int i;
1264 unsigned HOST_WIDE_INT mask = 1ULL;
1265 bool contiguous = false;
1266
1267 for (i = 0; i < size; mask <<= 1, i++)
1268 {
1269 if (contiguous)
1270 {
1271 if (mask & in)
1272 tmp_length++;
1273 else
1274 break;
1275 }
1276 else
1277 {
1278 if (mask & in)
1279 {
1280 contiguous = true;
1281 tmp_length++;
1282 }
1283 else
1284 tmp_pos++;
1285 }
1286 }
1287
1288 if (!tmp_length)
1289 return false;
1290
1291 /* Calculate a mask for all bits beyond the contiguous bits. */
1292 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1293
1294 if (mask & in)
1295 return false;
1296
1297 if (tmp_length + tmp_pos - 1 > size)
1298 return false;
1299
1300 if (length)
1301 *length = tmp_length;
1302
1303 if (pos)
1304 *pos = tmp_pos;
1305
1306 return true;
1307 }
1308
1309 /* Check whether we can (and want to) split a double-word
1310 move in mode MODE from SRC to DST into two single-word
1311 moves, moving the subword FIRST_SUBWORD first. */
1312
1313 bool
1314 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1315 {
1316 /* Floating point registers cannot be split. */
1317 if (FP_REG_P (src) || FP_REG_P (dst))
1318 return false;
1319
1320 /* We don't need to split if operands are directly accessible. */
1321 if (s_operand (src, mode) || s_operand (dst, mode))
1322 return false;
1323
1324 /* Non-offsettable memory references cannot be split. */
1325 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1326 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1327 return false;
1328
1329 /* Moving the first subword must not clobber a register
1330 needed to move the second subword. */
1331 if (register_operand (dst, mode))
1332 {
1333 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1334 if (reg_overlap_mentioned_p (subreg, src))
1335 return false;
1336 }
1337
1338 return true;
1339 }
1340
1341 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1342 and [MEM2, MEM2 + SIZE] do overlap and false
1343 otherwise. */
1344
1345 bool
1346 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1347 {
1348 rtx addr1, addr2, addr_delta;
1349 HOST_WIDE_INT delta;
1350
1351 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1352 return true;
1353
1354 if (size == 0)
1355 return false;
1356
1357 addr1 = XEXP (mem1, 0);
1358 addr2 = XEXP (mem2, 0);
1359
1360 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1361
1362 /* This overlapping check is used by peepholes merging memory block operations.
1363 Overlapping operations would otherwise be recognized by the S/390 hardware
1364 and would fall back to a slower implementation. Allowing overlapping
1365 operations would lead to slow code but not to wrong code. Therefore we are
1366 somewhat optimistic if we cannot prove that the memory blocks are
1367 overlapping.
1368 That's why we return false here although this may accept operations on
1369 overlapping memory areas. */
1370 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1371 return false;
1372
1373 delta = INTVAL (addr_delta);
1374
1375 if (delta == 0
1376 || (delta > 0 && delta < size)
1377 || (delta < 0 && -delta < size))
1378 return true;
1379
1380 return false;
1381 }
1382
1383 /* Check whether the address of memory reference MEM2 equals exactly
1384 the address of memory reference MEM1 plus DELTA. Return true if
1385 we can prove this to be the case, false otherwise. */
1386
1387 bool
1388 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1389 {
1390 rtx addr1, addr2, addr_delta;
1391
1392 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1393 return false;
1394
1395 addr1 = XEXP (mem1, 0);
1396 addr2 = XEXP (mem2, 0);
1397
1398 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1399 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1400 return false;
1401
1402 return true;
1403 }
1404
1405 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1406
1407 void
1408 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1409 rtx *operands)
1410 {
1411 enum machine_mode wmode = mode;
1412 rtx dst = operands[0];
1413 rtx src1 = operands[1];
1414 rtx src2 = operands[2];
1415 rtx op, clob, tem;
1416
1417 /* If we cannot handle the operation directly, use a temp register. */
1418 if (!s390_logical_operator_ok_p (operands))
1419 dst = gen_reg_rtx (mode);
1420
1421 /* QImode and HImode patterns make sense only if we have a destination
1422 in memory. Otherwise perform the operation in SImode. */
1423 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1424 wmode = SImode;
1425
1426 /* Widen operands if required. */
1427 if (mode != wmode)
1428 {
1429 if (GET_CODE (dst) == SUBREG
1430 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1431 dst = tem;
1432 else if (REG_P (dst))
1433 dst = gen_rtx_SUBREG (wmode, dst, 0);
1434 else
1435 dst = gen_reg_rtx (wmode);
1436
1437 if (GET_CODE (src1) == SUBREG
1438 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1439 src1 = tem;
1440 else if (GET_MODE (src1) != VOIDmode)
1441 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1442
1443 if (GET_CODE (src2) == SUBREG
1444 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1445 src2 = tem;
1446 else if (GET_MODE (src2) != VOIDmode)
1447 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1448 }
1449
1450 /* Emit the instruction. */
1451 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1452 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1453 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1454
1455 /* Fix up the destination if needed. */
1456 if (dst != operands[0])
1457 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1458 }
1459
1460 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1461
1462 bool
1463 s390_logical_operator_ok_p (rtx *operands)
1464 {
1465 /* If the destination operand is in memory, it needs to coincide
1466 with one of the source operands. After reload, it has to be
1467 the first source operand. */
1468 if (GET_CODE (operands[0]) == MEM)
1469 return rtx_equal_p (operands[0], operands[1])
1470 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1471
1472 return true;
1473 }
1474
1475 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1476 operand IMMOP to switch from SS to SI type instructions. */
1477
1478 void
1479 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1480 {
1481 int def = code == AND ? -1 : 0;
1482 HOST_WIDE_INT mask;
1483 int part;
1484
1485 gcc_assert (GET_CODE (*memop) == MEM);
1486 gcc_assert (!MEM_VOLATILE_P (*memop));
1487
1488 mask = s390_extract_part (*immop, QImode, def);
1489 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1490 gcc_assert (part >= 0);
1491
1492 *memop = adjust_address (*memop, QImode, part);
1493 *immop = gen_int_mode (mask, QImode);
1494 }
1495
1496
1497 /* How to allocate a 'struct machine_function'. */
1498
1499 static struct machine_function *
1500 s390_init_machine_status (void)
1501 {
1502 return ggc_alloc_cleared_machine_function ();
1503 }
1504
1505 static void
1506 s390_option_override (void)
1507 {
1508 /* Set up function hooks. */
1509 init_machine_status = s390_init_machine_status;
1510
1511 /* Architecture mode defaults according to ABI. */
1512 if (!(target_flags_explicit & MASK_ZARCH))
1513 {
1514 if (TARGET_64BIT)
1515 target_flags |= MASK_ZARCH;
1516 else
1517 target_flags &= ~MASK_ZARCH;
1518 }
1519
1520 /* Set the march default in case it hasn't been specified on
1521 cmdline. */
1522 if (s390_arch == PROCESSOR_max)
1523 {
1524 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1525 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1526 s390_arch_flags = processor_flags_table[(int)s390_arch];
1527 }
1528
1529 /* Determine processor to tune for. */
1530 if (s390_tune == PROCESSOR_max)
1531 {
1532 s390_tune = s390_arch;
1533 s390_tune_flags = s390_arch_flags;
1534 }
1535
1536 /* Sanity checks. */
1537 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1538 error ("z/Architecture mode not supported on %s", s390_arch_string);
1539 if (TARGET_64BIT && !TARGET_ZARCH)
1540 error ("64-bit ABI not supported in ESA/390 mode");
1541
1542 /* Use hardware DFP if available and not explicitly disabled by
1543 user. E.g. with -m31 -march=z10 -mzarch */
1544 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1545 target_flags |= MASK_HARD_DFP;
1546
1547 if (TARGET_HARD_DFP && !TARGET_DFP)
1548 {
1549 if (target_flags_explicit & MASK_HARD_DFP)
1550 {
1551 if (!TARGET_CPU_DFP)
1552 error ("hardware decimal floating point instructions"
1553 " not available on %s", s390_arch_string);
1554 if (!TARGET_ZARCH)
1555 error ("hardware decimal floating point instructions"
1556 " not available in ESA/390 mode");
1557 }
1558 else
1559 target_flags &= ~MASK_HARD_DFP;
1560 }
1561
1562 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1563 {
1564 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1565 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1566
1567 target_flags &= ~MASK_HARD_DFP;
1568 }
1569
1570 /* Set processor cost function. */
1571 switch (s390_tune)
1572 {
1573 case PROCESSOR_2084_Z990:
1574 s390_cost = &z990_cost;
1575 break;
1576 case PROCESSOR_2094_Z9_109:
1577 s390_cost = &z9_109_cost;
1578 break;
1579 case PROCESSOR_2097_Z10:
1580 s390_cost = &z10_cost;
1581 case PROCESSOR_2817_Z196:
1582 s390_cost = &z196_cost;
1583 break;
1584 default:
1585 s390_cost = &z900_cost;
1586 }
1587
1588 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1589 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1590 "in combination");
1591
1592 if (s390_stack_size)
1593 {
1594 if (s390_stack_guard >= s390_stack_size)
1595 error ("stack size must be greater than the stack guard value");
1596 else if (s390_stack_size > 1 << 16)
1597 error ("stack size must not be greater than 64k");
1598 }
1599 else if (s390_stack_guard)
1600 error ("-mstack-guard implies use of -mstack-size");
1601
1602 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1603 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1604 target_flags |= MASK_LONG_DOUBLE_128;
1605 #endif
1606
1607 if (s390_tune == PROCESSOR_2097_Z10
1608 || s390_tune == PROCESSOR_2817_Z196)
1609 {
1610 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1611 global_options.x_param_values,
1612 global_options_set.x_param_values);
1613 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1614 global_options.x_param_values,
1615 global_options_set.x_param_values);
1616 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1617 global_options.x_param_values,
1618 global_options_set.x_param_values);
1619 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1620 global_options.x_param_values,
1621 global_options_set.x_param_values);
1622 }
1623
1624 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1625 global_options.x_param_values,
1626 global_options_set.x_param_values);
1627 /* values for loop prefetching */
1628 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1629 global_options.x_param_values,
1630 global_options_set.x_param_values);
1631 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1632 global_options.x_param_values,
1633 global_options_set.x_param_values);
1634 /* s390 has more than 2 levels and the size is much larger. Since
1635 we are always running virtualized assume that we only get a small
1636 part of the caches above l1. */
1637 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1638 global_options.x_param_values,
1639 global_options_set.x_param_values);
1640 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1641 global_options.x_param_values,
1642 global_options_set.x_param_values);
1643 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1644 global_options.x_param_values,
1645 global_options_set.x_param_values);
1646
1647 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1648 requires the arch flags to be evaluated already. Since prefetching
1649 is beneficial on s390, we enable it if available. */
1650 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1651 flag_prefetch_loop_arrays = 1;
1652
1653 /* Use the alternative scheduling-pressure algorithm by default. */
1654 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
1655 global_options.x_param_values,
1656 global_options_set.x_param_values);
1657 }
1658
1659 /* Map for smallest class containing reg regno. */
1660
1661 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1662 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1663 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1664 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1665 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1666 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1667 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1668 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1669 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1670 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1671 ACCESS_REGS, ACCESS_REGS
1672 };
1673
1674 /* Return attribute type of insn. */
1675
1676 static enum attr_type
1677 s390_safe_attr_type (rtx insn)
1678 {
1679 if (recog_memoized (insn) >= 0)
1680 return get_attr_type (insn);
1681 else
1682 return TYPE_NONE;
1683 }
1684
1685 /* Return true if DISP is a valid short displacement. */
1686
1687 static bool
1688 s390_short_displacement (rtx disp)
1689 {
1690 /* No displacement is OK. */
1691 if (!disp)
1692 return true;
1693
1694 /* Without the long displacement facility we don't need to
1695 distingiush between long and short displacement. */
1696 if (!TARGET_LONG_DISPLACEMENT)
1697 return true;
1698
1699 /* Integer displacement in range. */
1700 if (GET_CODE (disp) == CONST_INT)
1701 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1702
1703 /* GOT offset is not OK, the GOT can be large. */
1704 if (GET_CODE (disp) == CONST
1705 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1706 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1707 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1708 return false;
1709
1710 /* All other symbolic constants are literal pool references,
1711 which are OK as the literal pool must be small. */
1712 if (GET_CODE (disp) == CONST)
1713 return true;
1714
1715 return false;
1716 }
1717
1718 /* Decompose a RTL expression ADDR for a memory address into
1719 its components, returned in OUT.
1720
1721 Returns false if ADDR is not a valid memory address, true
1722 otherwise. If OUT is NULL, don't return the components,
1723 but check for validity only.
1724
1725 Note: Only addresses in canonical form are recognized.
1726 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1727 canonical form so that they will be recognized. */
1728
1729 static int
1730 s390_decompose_address (rtx addr, struct s390_address *out)
1731 {
1732 HOST_WIDE_INT offset = 0;
1733 rtx base = NULL_RTX;
1734 rtx indx = NULL_RTX;
1735 rtx disp = NULL_RTX;
1736 rtx orig_disp;
1737 bool pointer = false;
1738 bool base_ptr = false;
1739 bool indx_ptr = false;
1740 bool literal_pool = false;
1741
1742 /* We may need to substitute the literal pool base register into the address
1743 below. However, at this point we do not know which register is going to
1744 be used as base, so we substitute the arg pointer register. This is going
1745 to be treated as holding a pointer below -- it shouldn't be used for any
1746 other purpose. */
1747 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1748
1749 /* Decompose address into base + index + displacement. */
1750
1751 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1752 base = addr;
1753
1754 else if (GET_CODE (addr) == PLUS)
1755 {
1756 rtx op0 = XEXP (addr, 0);
1757 rtx op1 = XEXP (addr, 1);
1758 enum rtx_code code0 = GET_CODE (op0);
1759 enum rtx_code code1 = GET_CODE (op1);
1760
1761 if (code0 == REG || code0 == UNSPEC)
1762 {
1763 if (code1 == REG || code1 == UNSPEC)
1764 {
1765 indx = op0; /* index + base */
1766 base = op1;
1767 }
1768
1769 else
1770 {
1771 base = op0; /* base + displacement */
1772 disp = op1;
1773 }
1774 }
1775
1776 else if (code0 == PLUS)
1777 {
1778 indx = XEXP (op0, 0); /* index + base + disp */
1779 base = XEXP (op0, 1);
1780 disp = op1;
1781 }
1782
1783 else
1784 {
1785 return false;
1786 }
1787 }
1788
1789 else
1790 disp = addr; /* displacement */
1791
1792 /* Extract integer part of displacement. */
1793 orig_disp = disp;
1794 if (disp)
1795 {
1796 if (GET_CODE (disp) == CONST_INT)
1797 {
1798 offset = INTVAL (disp);
1799 disp = NULL_RTX;
1800 }
1801 else if (GET_CODE (disp) == CONST
1802 && GET_CODE (XEXP (disp, 0)) == PLUS
1803 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1804 {
1805 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1806 disp = XEXP (XEXP (disp, 0), 0);
1807 }
1808 }
1809
1810 /* Strip off CONST here to avoid special case tests later. */
1811 if (disp && GET_CODE (disp) == CONST)
1812 disp = XEXP (disp, 0);
1813
1814 /* We can convert literal pool addresses to
1815 displacements by basing them off the base register. */
1816 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1817 {
1818 /* Either base or index must be free to hold the base register. */
1819 if (!base)
1820 base = fake_pool_base, literal_pool = true;
1821 else if (!indx)
1822 indx = fake_pool_base, literal_pool = true;
1823 else
1824 return false;
1825
1826 /* Mark up the displacement. */
1827 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1828 UNSPEC_LTREL_OFFSET);
1829 }
1830
1831 /* Validate base register. */
1832 if (base)
1833 {
1834 if (GET_CODE (base) == UNSPEC)
1835 switch (XINT (base, 1))
1836 {
1837 case UNSPEC_LTREF:
1838 if (!disp)
1839 disp = gen_rtx_UNSPEC (Pmode,
1840 gen_rtvec (1, XVECEXP (base, 0, 0)),
1841 UNSPEC_LTREL_OFFSET);
1842 else
1843 return false;
1844
1845 base = XVECEXP (base, 0, 1);
1846 break;
1847
1848 case UNSPEC_LTREL_BASE:
1849 if (XVECLEN (base, 0) == 1)
1850 base = fake_pool_base, literal_pool = true;
1851 else
1852 base = XVECEXP (base, 0, 1);
1853 break;
1854
1855 default:
1856 return false;
1857 }
1858
1859 if (!REG_P (base)
1860 || (GET_MODE (base) != SImode
1861 && GET_MODE (base) != Pmode))
1862 return false;
1863
1864 if (REGNO (base) == STACK_POINTER_REGNUM
1865 || REGNO (base) == FRAME_POINTER_REGNUM
1866 || ((reload_completed || reload_in_progress)
1867 && frame_pointer_needed
1868 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1869 || REGNO (base) == ARG_POINTER_REGNUM
1870 || (flag_pic
1871 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1872 pointer = base_ptr = true;
1873
1874 if ((reload_completed || reload_in_progress)
1875 && base == cfun->machine->base_reg)
1876 pointer = base_ptr = literal_pool = true;
1877 }
1878
1879 /* Validate index register. */
1880 if (indx)
1881 {
1882 if (GET_CODE (indx) == UNSPEC)
1883 switch (XINT (indx, 1))
1884 {
1885 case UNSPEC_LTREF:
1886 if (!disp)
1887 disp = gen_rtx_UNSPEC (Pmode,
1888 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1889 UNSPEC_LTREL_OFFSET);
1890 else
1891 return false;
1892
1893 indx = XVECEXP (indx, 0, 1);
1894 break;
1895
1896 case UNSPEC_LTREL_BASE:
1897 if (XVECLEN (indx, 0) == 1)
1898 indx = fake_pool_base, literal_pool = true;
1899 else
1900 indx = XVECEXP (indx, 0, 1);
1901 break;
1902
1903 default:
1904 return false;
1905 }
1906
1907 if (!REG_P (indx)
1908 || (GET_MODE (indx) != SImode
1909 && GET_MODE (indx) != Pmode))
1910 return false;
1911
1912 if (REGNO (indx) == STACK_POINTER_REGNUM
1913 || REGNO (indx) == FRAME_POINTER_REGNUM
1914 || ((reload_completed || reload_in_progress)
1915 && frame_pointer_needed
1916 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1917 || REGNO (indx) == ARG_POINTER_REGNUM
1918 || (flag_pic
1919 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1920 pointer = indx_ptr = true;
1921
1922 if ((reload_completed || reload_in_progress)
1923 && indx == cfun->machine->base_reg)
1924 pointer = indx_ptr = literal_pool = true;
1925 }
1926
1927 /* Prefer to use pointer as base, not index. */
1928 if (base && indx && !base_ptr
1929 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1930 {
1931 rtx tmp = base;
1932 base = indx;
1933 indx = tmp;
1934 }
1935
1936 /* Validate displacement. */
1937 if (!disp)
1938 {
1939 /* If virtual registers are involved, the displacement will change later
1940 anyway as the virtual registers get eliminated. This could make a
1941 valid displacement invalid, but it is more likely to make an invalid
1942 displacement valid, because we sometimes access the register save area
1943 via negative offsets to one of those registers.
1944 Thus we don't check the displacement for validity here. If after
1945 elimination the displacement turns out to be invalid after all,
1946 this is fixed up by reload in any case. */
1947 if (base != arg_pointer_rtx
1948 && indx != arg_pointer_rtx
1949 && base != return_address_pointer_rtx
1950 && indx != return_address_pointer_rtx
1951 && base != frame_pointer_rtx
1952 && indx != frame_pointer_rtx
1953 && base != virtual_stack_vars_rtx
1954 && indx != virtual_stack_vars_rtx)
1955 if (!DISP_IN_RANGE (offset))
1956 return false;
1957 }
1958 else
1959 {
1960 /* All the special cases are pointers. */
1961 pointer = true;
1962
1963 /* In the small-PIC case, the linker converts @GOT
1964 and @GOTNTPOFF offsets to possible displacements. */
1965 if (GET_CODE (disp) == UNSPEC
1966 && (XINT (disp, 1) == UNSPEC_GOT
1967 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1968 && flag_pic == 1)
1969 {
1970 ;
1971 }
1972
1973 /* Accept pool label offsets. */
1974 else if (GET_CODE (disp) == UNSPEC
1975 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1976 ;
1977
1978 /* Accept literal pool references. */
1979 else if (GET_CODE (disp) == UNSPEC
1980 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1981 {
1982 /* In case CSE pulled a non literal pool reference out of
1983 the pool we have to reject the address. This is
1984 especially important when loading the GOT pointer on non
1985 zarch CPUs. In this case the literal pool contains an lt
1986 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
1987 will most likely exceed the displacement. */
1988 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
1989 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
1990 return false;
1991
1992 orig_disp = gen_rtx_CONST (Pmode, disp);
1993 if (offset)
1994 {
1995 /* If we have an offset, make sure it does not
1996 exceed the size of the constant pool entry. */
1997 rtx sym = XVECEXP (disp, 0, 0);
1998 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1999 return false;
2000
2001 orig_disp = plus_constant (Pmode, orig_disp, offset);
2002 }
2003 }
2004
2005 else
2006 return false;
2007 }
2008
2009 if (!base && !indx)
2010 pointer = true;
2011
2012 if (out)
2013 {
2014 out->base = base;
2015 out->indx = indx;
2016 out->disp = orig_disp;
2017 out->pointer = pointer;
2018 out->literal_pool = literal_pool;
2019 }
2020
2021 return true;
2022 }
2023
2024 /* Decompose a RTL expression OP for a shift count into its components,
2025 and return the base register in BASE and the offset in OFFSET.
2026
2027 Return true if OP is a valid shift count, false if not. */
2028
2029 bool
2030 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2031 {
2032 HOST_WIDE_INT off = 0;
2033
2034 /* We can have an integer constant, an address register,
2035 or a sum of the two. */
2036 if (GET_CODE (op) == CONST_INT)
2037 {
2038 off = INTVAL (op);
2039 op = NULL_RTX;
2040 }
2041 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2042 {
2043 off = INTVAL (XEXP (op, 1));
2044 op = XEXP (op, 0);
2045 }
2046 while (op && GET_CODE (op) == SUBREG)
2047 op = SUBREG_REG (op);
2048
2049 if (op && GET_CODE (op) != REG)
2050 return false;
2051
2052 if (offset)
2053 *offset = off;
2054 if (base)
2055 *base = op;
2056
2057 return true;
2058 }
2059
2060
2061 /* Return true if CODE is a valid address without index. */
2062
2063 bool
2064 s390_legitimate_address_without_index_p (rtx op)
2065 {
2066 struct s390_address addr;
2067
2068 if (!s390_decompose_address (XEXP (op, 0), &addr))
2069 return false;
2070 if (addr.indx)
2071 return false;
2072
2073 return true;
2074 }
2075
2076
2077 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2078 and return these parts in SYMREF and ADDEND. You can pass NULL in
2079 SYMREF and/or ADDEND if you are not interested in these values.
2080 Literal pool references are *not* considered symbol references. */
2081
2082 static bool
2083 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2084 {
2085 HOST_WIDE_INT tmpaddend = 0;
2086
2087 if (GET_CODE (addr) == CONST)
2088 addr = XEXP (addr, 0);
2089
2090 if (GET_CODE (addr) == PLUS)
2091 {
2092 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2093 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2094 && CONST_INT_P (XEXP (addr, 1)))
2095 {
2096 tmpaddend = INTVAL (XEXP (addr, 1));
2097 addr = XEXP (addr, 0);
2098 }
2099 else
2100 return false;
2101 }
2102 else
2103 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2104 return false;
2105
2106 if (symref)
2107 *symref = addr;
2108 if (addend)
2109 *addend = tmpaddend;
2110
2111 return true;
2112 }
2113
2114
2115 /* Return true if the address in OP is valid for constraint letter C
2116 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2117 pool MEMs should be accepted. Only the Q, R, S, T constraint
2118 letters are allowed for C. */
2119
2120 static int
2121 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2122 {
2123 struct s390_address addr;
2124 bool decomposed = false;
2125
2126 /* This check makes sure that no symbolic address (except literal
2127 pool references) are accepted by the R or T constraints. */
2128 if (s390_symref_operand_p (op, NULL, NULL))
2129 return 0;
2130
2131 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2132 if (!lit_pool_ok)
2133 {
2134 if (!s390_decompose_address (op, &addr))
2135 return 0;
2136 if (addr.literal_pool)
2137 return 0;
2138 decomposed = true;
2139 }
2140
2141 switch (c)
2142 {
2143 case 'Q': /* no index short displacement */
2144 if (!decomposed && !s390_decompose_address (op, &addr))
2145 return 0;
2146 if (addr.indx)
2147 return 0;
2148 if (!s390_short_displacement (addr.disp))
2149 return 0;
2150 break;
2151
2152 case 'R': /* with index short displacement */
2153 if (TARGET_LONG_DISPLACEMENT)
2154 {
2155 if (!decomposed && !s390_decompose_address (op, &addr))
2156 return 0;
2157 if (!s390_short_displacement (addr.disp))
2158 return 0;
2159 }
2160 /* Any invalid address here will be fixed up by reload,
2161 so accept it for the most generic constraint. */
2162 break;
2163
2164 case 'S': /* no index long displacement */
2165 if (!TARGET_LONG_DISPLACEMENT)
2166 return 0;
2167 if (!decomposed && !s390_decompose_address (op, &addr))
2168 return 0;
2169 if (addr.indx)
2170 return 0;
2171 if (s390_short_displacement (addr.disp))
2172 return 0;
2173 break;
2174
2175 case 'T': /* with index long displacement */
2176 if (!TARGET_LONG_DISPLACEMENT)
2177 return 0;
2178 /* Any invalid address here will be fixed up by reload,
2179 so accept it for the most generic constraint. */
2180 if ((decomposed || s390_decompose_address (op, &addr))
2181 && s390_short_displacement (addr.disp))
2182 return 0;
2183 break;
2184 default:
2185 return 0;
2186 }
2187 return 1;
2188 }
2189
2190
2191 /* Evaluates constraint strings described by the regular expression
2192 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2193 the constraint given in STR, or 0 else. */
2194
2195 int
2196 s390_mem_constraint (const char *str, rtx op)
2197 {
2198 char c = str[0];
2199
2200 switch (c)
2201 {
2202 case 'A':
2203 /* Check for offsettable variants of memory constraints. */
2204 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2205 return 0;
2206 if ((reload_completed || reload_in_progress)
2207 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2208 return 0;
2209 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2210 case 'B':
2211 /* Check for non-literal-pool variants of memory constraints. */
2212 if (!MEM_P (op))
2213 return 0;
2214 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2215 case 'Q':
2216 case 'R':
2217 case 'S':
2218 case 'T':
2219 if (GET_CODE (op) != MEM)
2220 return 0;
2221 return s390_check_qrst_address (c, XEXP (op, 0), true);
2222 case 'U':
2223 return (s390_check_qrst_address ('Q', op, true)
2224 || s390_check_qrst_address ('R', op, true));
2225 case 'W':
2226 return (s390_check_qrst_address ('S', op, true)
2227 || s390_check_qrst_address ('T', op, true));
2228 case 'Y':
2229 /* Simply check for the basic form of a shift count. Reload will
2230 take care of making sure we have a proper base register. */
2231 if (!s390_decompose_shift_count (op, NULL, NULL))
2232 return 0;
2233 break;
2234 case 'Z':
2235 return s390_check_qrst_address (str[1], op, true);
2236 default:
2237 return 0;
2238 }
2239 return 1;
2240 }
2241
2242
2243 /* Evaluates constraint strings starting with letter O. Input
2244 parameter C is the second letter following the "O" in the constraint
2245 string. Returns 1 if VALUE meets the respective constraint and 0
2246 otherwise. */
2247
2248 int
2249 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2250 {
2251 if (!TARGET_EXTIMM)
2252 return 0;
2253
2254 switch (c)
2255 {
2256 case 's':
2257 return trunc_int_for_mode (value, SImode) == value;
2258
2259 case 'p':
2260 return value == 0
2261 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2262
2263 case 'n':
2264 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2265
2266 default:
2267 gcc_unreachable ();
2268 }
2269 }
2270
2271
2272 /* Evaluates constraint strings starting with letter N. Parameter STR
2273 contains the letters following letter "N" in the constraint string.
2274 Returns true if VALUE matches the constraint. */
2275
2276 int
2277 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2278 {
2279 enum machine_mode mode, part_mode;
2280 int def;
2281 int part, part_goal;
2282
2283
2284 if (str[0] == 'x')
2285 part_goal = -1;
2286 else
2287 part_goal = str[0] - '0';
2288
2289 switch (str[1])
2290 {
2291 case 'Q':
2292 part_mode = QImode;
2293 break;
2294 case 'H':
2295 part_mode = HImode;
2296 break;
2297 case 'S':
2298 part_mode = SImode;
2299 break;
2300 default:
2301 return 0;
2302 }
2303
2304 switch (str[2])
2305 {
2306 case 'H':
2307 mode = HImode;
2308 break;
2309 case 'S':
2310 mode = SImode;
2311 break;
2312 case 'D':
2313 mode = DImode;
2314 break;
2315 default:
2316 return 0;
2317 }
2318
2319 switch (str[3])
2320 {
2321 case '0':
2322 def = 0;
2323 break;
2324 case 'F':
2325 def = -1;
2326 break;
2327 default:
2328 return 0;
2329 }
2330
2331 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2332 return 0;
2333
2334 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2335 if (part < 0)
2336 return 0;
2337 if (part_goal != -1 && part_goal != part)
2338 return 0;
2339
2340 return 1;
2341 }
2342
2343
2344 /* Returns true if the input parameter VALUE is a float zero. */
2345
2346 int
2347 s390_float_const_zero_p (rtx value)
2348 {
2349 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2350 && value == CONST0_RTX (GET_MODE (value)));
2351 }
2352
2353 /* Implement TARGET_REGISTER_MOVE_COST. */
2354
2355 static int
2356 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2357 reg_class_t from, reg_class_t to)
2358 {
2359 /* On s390, copy between fprs and gprs is expensive. */
2360 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2361 && reg_classes_intersect_p (to, FP_REGS))
2362 || (reg_classes_intersect_p (from, FP_REGS)
2363 && reg_classes_intersect_p (to, GENERAL_REGS)))
2364 return 10;
2365
2366 return 1;
2367 }
2368
2369 /* Implement TARGET_MEMORY_MOVE_COST. */
2370
2371 static int
2372 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2373 reg_class_t rclass ATTRIBUTE_UNUSED,
2374 bool in ATTRIBUTE_UNUSED)
2375 {
2376 return 1;
2377 }
2378
2379 /* Compute a (partial) cost for rtx X. Return true if the complete
2380 cost has been computed, and false if subexpressions should be
2381 scanned. In either case, *TOTAL contains the cost result.
2382 CODE contains GET_CODE (x), OUTER_CODE contains the code
2383 of the superexpression of x. */
2384
2385 static bool
2386 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2387 int *total, bool speed ATTRIBUTE_UNUSED)
2388 {
2389 switch (code)
2390 {
2391 case CONST:
2392 case CONST_INT:
2393 case LABEL_REF:
2394 case SYMBOL_REF:
2395 case CONST_DOUBLE:
2396 case MEM:
2397 *total = 0;
2398 return true;
2399
2400 case ASHIFT:
2401 case ASHIFTRT:
2402 case LSHIFTRT:
2403 case ROTATE:
2404 case ROTATERT:
2405 case AND:
2406 case IOR:
2407 case XOR:
2408 case NEG:
2409 case NOT:
2410 *total = COSTS_N_INSNS (1);
2411 return false;
2412
2413 case PLUS:
2414 case MINUS:
2415 *total = COSTS_N_INSNS (1);
2416 return false;
2417
2418 case MULT:
2419 switch (GET_MODE (x))
2420 {
2421 case SImode:
2422 {
2423 rtx left = XEXP (x, 0);
2424 rtx right = XEXP (x, 1);
2425 if (GET_CODE (right) == CONST_INT
2426 && CONST_OK_FOR_K (INTVAL (right)))
2427 *total = s390_cost->mhi;
2428 else if (GET_CODE (left) == SIGN_EXTEND)
2429 *total = s390_cost->mh;
2430 else
2431 *total = s390_cost->ms; /* msr, ms, msy */
2432 break;
2433 }
2434 case DImode:
2435 {
2436 rtx left = XEXP (x, 0);
2437 rtx right = XEXP (x, 1);
2438 if (TARGET_ZARCH)
2439 {
2440 if (GET_CODE (right) == CONST_INT
2441 && CONST_OK_FOR_K (INTVAL (right)))
2442 *total = s390_cost->mghi;
2443 else if (GET_CODE (left) == SIGN_EXTEND)
2444 *total = s390_cost->msgf;
2445 else
2446 *total = s390_cost->msg; /* msgr, msg */
2447 }
2448 else /* TARGET_31BIT */
2449 {
2450 if (GET_CODE (left) == SIGN_EXTEND
2451 && GET_CODE (right) == SIGN_EXTEND)
2452 /* mulsidi case: mr, m */
2453 *total = s390_cost->m;
2454 else if (GET_CODE (left) == ZERO_EXTEND
2455 && GET_CODE (right) == ZERO_EXTEND
2456 && TARGET_CPU_ZARCH)
2457 /* umulsidi case: ml, mlr */
2458 *total = s390_cost->ml;
2459 else
2460 /* Complex calculation is required. */
2461 *total = COSTS_N_INSNS (40);
2462 }
2463 break;
2464 }
2465 case SFmode:
2466 case DFmode:
2467 *total = s390_cost->mult_df;
2468 break;
2469 case TFmode:
2470 *total = s390_cost->mxbr;
2471 break;
2472 default:
2473 return false;
2474 }
2475 return false;
2476
2477 case FMA:
2478 switch (GET_MODE (x))
2479 {
2480 case DFmode:
2481 *total = s390_cost->madbr;
2482 break;
2483 case SFmode:
2484 *total = s390_cost->maebr;
2485 break;
2486 default:
2487 return false;
2488 }
2489 /* Negate in the third argument is free: FMSUB. */
2490 if (GET_CODE (XEXP (x, 2)) == NEG)
2491 {
2492 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2493 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2494 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2495 return true;
2496 }
2497 return false;
2498
2499 case UDIV:
2500 case UMOD:
2501 if (GET_MODE (x) == TImode) /* 128 bit division */
2502 *total = s390_cost->dlgr;
2503 else if (GET_MODE (x) == DImode)
2504 {
2505 rtx right = XEXP (x, 1);
2506 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2507 *total = s390_cost->dlr;
2508 else /* 64 by 64 bit division */
2509 *total = s390_cost->dlgr;
2510 }
2511 else if (GET_MODE (x) == SImode) /* 32 bit division */
2512 *total = s390_cost->dlr;
2513 return false;
2514
2515 case DIV:
2516 case MOD:
2517 if (GET_MODE (x) == DImode)
2518 {
2519 rtx right = XEXP (x, 1);
2520 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2521 if (TARGET_ZARCH)
2522 *total = s390_cost->dsgfr;
2523 else
2524 *total = s390_cost->dr;
2525 else /* 64 by 64 bit division */
2526 *total = s390_cost->dsgr;
2527 }
2528 else if (GET_MODE (x) == SImode) /* 32 bit division */
2529 *total = s390_cost->dlr;
2530 else if (GET_MODE (x) == SFmode)
2531 {
2532 *total = s390_cost->debr;
2533 }
2534 else if (GET_MODE (x) == DFmode)
2535 {
2536 *total = s390_cost->ddbr;
2537 }
2538 else if (GET_MODE (x) == TFmode)
2539 {
2540 *total = s390_cost->dxbr;
2541 }
2542 return false;
2543
2544 case SQRT:
2545 if (GET_MODE (x) == SFmode)
2546 *total = s390_cost->sqebr;
2547 else if (GET_MODE (x) == DFmode)
2548 *total = s390_cost->sqdbr;
2549 else /* TFmode */
2550 *total = s390_cost->sqxbr;
2551 return false;
2552
2553 case SIGN_EXTEND:
2554 case ZERO_EXTEND:
2555 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2556 || outer_code == PLUS || outer_code == MINUS
2557 || outer_code == COMPARE)
2558 *total = 0;
2559 return false;
2560
2561 case COMPARE:
2562 *total = COSTS_N_INSNS (1);
2563 if (GET_CODE (XEXP (x, 0)) == AND
2564 && GET_CODE (XEXP (x, 1)) == CONST_INT
2565 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2566 {
2567 rtx op0 = XEXP (XEXP (x, 0), 0);
2568 rtx op1 = XEXP (XEXP (x, 0), 1);
2569 rtx op2 = XEXP (x, 1);
2570
2571 if (memory_operand (op0, GET_MODE (op0))
2572 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2573 return true;
2574 if (register_operand (op0, GET_MODE (op0))
2575 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2576 return true;
2577 }
2578 return false;
2579
2580 default:
2581 return false;
2582 }
2583 }
2584
2585 /* Return the cost of an address rtx ADDR. */
2586
2587 static int
2588 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2589 {
2590 struct s390_address ad;
2591 if (!s390_decompose_address (addr, &ad))
2592 return 1000;
2593
2594 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2595 }
2596
2597 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2598 otherwise return 0. */
2599
2600 int
2601 tls_symbolic_operand (rtx op)
2602 {
2603 if (GET_CODE (op) != SYMBOL_REF)
2604 return 0;
2605 return SYMBOL_REF_TLS_MODEL (op);
2606 }
2607 \f
2608 /* Split DImode access register reference REG (on 64-bit) into its constituent
2609 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2610 gen_highpart cannot be used as they assume all registers are word-sized,
2611 while our access registers have only half that size. */
2612
2613 void
2614 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2615 {
2616 gcc_assert (TARGET_64BIT);
2617 gcc_assert (ACCESS_REG_P (reg));
2618 gcc_assert (GET_MODE (reg) == DImode);
2619 gcc_assert (!(REGNO (reg) & 1));
2620
2621 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2622 *hi = gen_rtx_REG (SImode, REGNO (reg));
2623 }
2624
2625 /* Return true if OP contains a symbol reference */
2626
2627 bool
2628 symbolic_reference_mentioned_p (rtx op)
2629 {
2630 const char *fmt;
2631 int i;
2632
2633 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2634 return 1;
2635
2636 fmt = GET_RTX_FORMAT (GET_CODE (op));
2637 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2638 {
2639 if (fmt[i] == 'E')
2640 {
2641 int j;
2642
2643 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2644 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2645 return 1;
2646 }
2647
2648 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2649 return 1;
2650 }
2651
2652 return 0;
2653 }
2654
2655 /* Return true if OP contains a reference to a thread-local symbol. */
2656
2657 bool
2658 tls_symbolic_reference_mentioned_p (rtx op)
2659 {
2660 const char *fmt;
2661 int i;
2662
2663 if (GET_CODE (op) == SYMBOL_REF)
2664 return tls_symbolic_operand (op);
2665
2666 fmt = GET_RTX_FORMAT (GET_CODE (op));
2667 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2668 {
2669 if (fmt[i] == 'E')
2670 {
2671 int j;
2672
2673 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2674 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2675 return true;
2676 }
2677
2678 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2679 return true;
2680 }
2681
2682 return false;
2683 }
2684
2685
2686 /* Return true if OP is a legitimate general operand when
2687 generating PIC code. It is given that flag_pic is on
2688 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2689
2690 int
2691 legitimate_pic_operand_p (rtx op)
2692 {
2693 /* Accept all non-symbolic constants. */
2694 if (!SYMBOLIC_CONST (op))
2695 return 1;
2696
2697 /* Reject everything else; must be handled
2698 via emit_symbolic_move. */
2699 return 0;
2700 }
2701
2702 /* Returns true if the constant value OP is a legitimate general operand.
2703 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2704
2705 static bool
2706 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2707 {
2708 /* Accept all non-symbolic constants. */
2709 if (!SYMBOLIC_CONST (op))
2710 return 1;
2711
2712 /* Accept immediate LARL operands. */
2713 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2714 return 1;
2715
2716 /* Thread-local symbols are never legal constants. This is
2717 so that emit_call knows that computing such addresses
2718 might require a function call. */
2719 if (TLS_SYMBOLIC_CONST (op))
2720 return 0;
2721
2722 /* In the PIC case, symbolic constants must *not* be
2723 forced into the literal pool. We accept them here,
2724 so that they will be handled by emit_symbolic_move. */
2725 if (flag_pic)
2726 return 1;
2727
2728 /* All remaining non-PIC symbolic constants are
2729 forced into the literal pool. */
2730 return 0;
2731 }
2732
2733 /* Determine if it's legal to put X into the constant pool. This
2734 is not possible if X contains the address of a symbol that is
2735 not constant (TLS) or not known at final link time (PIC). */
2736
2737 static bool
2738 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2739 {
2740 switch (GET_CODE (x))
2741 {
2742 case CONST_INT:
2743 case CONST_DOUBLE:
2744 /* Accept all non-symbolic constants. */
2745 return false;
2746
2747 case LABEL_REF:
2748 /* Labels are OK iff we are non-PIC. */
2749 return flag_pic != 0;
2750
2751 case SYMBOL_REF:
2752 /* 'Naked' TLS symbol references are never OK,
2753 non-TLS symbols are OK iff we are non-PIC. */
2754 if (tls_symbolic_operand (x))
2755 return true;
2756 else
2757 return flag_pic != 0;
2758
2759 case CONST:
2760 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2761 case PLUS:
2762 case MINUS:
2763 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2764 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2765
2766 case UNSPEC:
2767 switch (XINT (x, 1))
2768 {
2769 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2770 case UNSPEC_LTREL_OFFSET:
2771 case UNSPEC_GOT:
2772 case UNSPEC_GOTOFF:
2773 case UNSPEC_PLTOFF:
2774 case UNSPEC_TLSGD:
2775 case UNSPEC_TLSLDM:
2776 case UNSPEC_NTPOFF:
2777 case UNSPEC_DTPOFF:
2778 case UNSPEC_GOTNTPOFF:
2779 case UNSPEC_INDNTPOFF:
2780 return false;
2781
2782 /* If the literal pool shares the code section, be put
2783 execute template placeholders into the pool as well. */
2784 case UNSPEC_INSN:
2785 return TARGET_CPU_ZARCH;
2786
2787 default:
2788 return true;
2789 }
2790 break;
2791
2792 default:
2793 gcc_unreachable ();
2794 }
2795 }
2796
2797 /* Returns true if the constant value OP is a legitimate general
2798 operand during and after reload. The difference to
2799 legitimate_constant_p is that this function will not accept
2800 a constant that would need to be forced to the literal pool
2801 before it can be used as operand.
2802 This function accepts all constants which can be loaded directly
2803 into a GPR. */
2804
2805 bool
2806 legitimate_reload_constant_p (rtx op)
2807 {
2808 /* Accept la(y) operands. */
2809 if (GET_CODE (op) == CONST_INT
2810 && DISP_IN_RANGE (INTVAL (op)))
2811 return true;
2812
2813 /* Accept l(g)hi/l(g)fi operands. */
2814 if (GET_CODE (op) == CONST_INT
2815 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2816 return true;
2817
2818 /* Accept lliXX operands. */
2819 if (TARGET_ZARCH
2820 && GET_CODE (op) == CONST_INT
2821 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2822 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2823 return true;
2824
2825 if (TARGET_EXTIMM
2826 && GET_CODE (op) == CONST_INT
2827 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2828 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2829 return true;
2830
2831 /* Accept larl operands. */
2832 if (TARGET_CPU_ZARCH
2833 && larl_operand (op, VOIDmode))
2834 return true;
2835
2836 /* Accept floating-point zero operands that fit into a single GPR. */
2837 if (GET_CODE (op) == CONST_DOUBLE
2838 && s390_float_const_zero_p (op)
2839 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2840 return true;
2841
2842 /* Accept double-word operands that can be split. */
2843 if (GET_CODE (op) == CONST_INT
2844 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2845 {
2846 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2847 rtx hi = operand_subword (op, 0, 0, dword_mode);
2848 rtx lo = operand_subword (op, 1, 0, dword_mode);
2849 return legitimate_reload_constant_p (hi)
2850 && legitimate_reload_constant_p (lo);
2851 }
2852
2853 /* Everything else cannot be handled without reload. */
2854 return false;
2855 }
2856
2857 /* Returns true if the constant value OP is a legitimate fp operand
2858 during and after reload.
2859 This function accepts all constants which can be loaded directly
2860 into an FPR. */
2861
2862 static bool
2863 legitimate_reload_fp_constant_p (rtx op)
2864 {
2865 /* Accept floating-point zero operands if the load zero instruction
2866 can be used. */
2867 if (TARGET_Z196
2868 && GET_CODE (op) == CONST_DOUBLE
2869 && s390_float_const_zero_p (op))
2870 return true;
2871
2872 return false;
2873 }
2874
2875 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2876 return the class of reg to actually use. */
2877
2878 static reg_class_t
2879 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2880 {
2881 switch (GET_CODE (op))
2882 {
2883 /* Constants we cannot reload into general registers
2884 must be forced into the literal pool. */
2885 case CONST_DOUBLE:
2886 case CONST_INT:
2887 if (reg_class_subset_p (GENERAL_REGS, rclass)
2888 && legitimate_reload_constant_p (op))
2889 return GENERAL_REGS;
2890 else if (reg_class_subset_p (ADDR_REGS, rclass)
2891 && legitimate_reload_constant_p (op))
2892 return ADDR_REGS;
2893 else if (reg_class_subset_p (FP_REGS, rclass)
2894 && legitimate_reload_fp_constant_p (op))
2895 return FP_REGS;
2896 return NO_REGS;
2897
2898 /* If a symbolic constant or a PLUS is reloaded,
2899 it is most likely being used as an address, so
2900 prefer ADDR_REGS. If 'class' is not a superset
2901 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2902 case LABEL_REF:
2903 case SYMBOL_REF:
2904 case CONST:
2905 if (!legitimate_reload_constant_p (op))
2906 return NO_REGS;
2907 /* fallthrough */
2908 case PLUS:
2909 /* load address will be used. */
2910 if (reg_class_subset_p (ADDR_REGS, rclass))
2911 return ADDR_REGS;
2912 else
2913 return NO_REGS;
2914
2915 default:
2916 break;
2917 }
2918
2919 return rclass;
2920 }
2921
2922 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2923 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2924 aligned. */
2925
2926 bool
2927 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2928 {
2929 HOST_WIDE_INT addend;
2930 rtx symref;
2931
2932 if (!s390_symref_operand_p (addr, &symref, &addend))
2933 return false;
2934
2935 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2936 && !(addend & (alignment - 1)));
2937 }
2938
2939 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2940 operand SCRATCH is used to reload the even part of the address and
2941 adding one. */
2942
2943 void
2944 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2945 {
2946 HOST_WIDE_INT addend;
2947 rtx symref;
2948
2949 if (!s390_symref_operand_p (addr, &symref, &addend))
2950 gcc_unreachable ();
2951
2952 if (!(addend & 1))
2953 /* Easy case. The addend is even so larl will do fine. */
2954 emit_move_insn (reg, addr);
2955 else
2956 {
2957 /* We can leave the scratch register untouched if the target
2958 register is a valid base register. */
2959 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2960 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2961 scratch = reg;
2962
2963 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2964 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2965
2966 if (addend != 1)
2967 emit_move_insn (scratch,
2968 gen_rtx_CONST (Pmode,
2969 gen_rtx_PLUS (Pmode, symref,
2970 GEN_INT (addend - 1))));
2971 else
2972 emit_move_insn (scratch, symref);
2973
2974 /* Increment the address using la in order to avoid clobbering cc. */
2975 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2976 }
2977 }
2978
2979 /* Generate what is necessary to move between REG and MEM using
2980 SCRATCH. The direction is given by TOMEM. */
2981
2982 void
2983 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2984 {
2985 /* Reload might have pulled a constant out of the literal pool.
2986 Force it back in. */
2987 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2988 || GET_CODE (mem) == CONST)
2989 mem = force_const_mem (GET_MODE (reg), mem);
2990
2991 gcc_assert (MEM_P (mem));
2992
2993 /* For a load from memory we can leave the scratch register
2994 untouched if the target register is a valid base register. */
2995 if (!tomem
2996 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2997 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2998 && GET_MODE (reg) == GET_MODE (scratch))
2999 scratch = reg;
3000
3001 /* Load address into scratch register. Since we can't have a
3002 secondary reload for a secondary reload we have to cover the case
3003 where larl would need a secondary reload here as well. */
3004 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3005
3006 /* Now we can use a standard load/store to do the move. */
3007 if (tomem)
3008 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3009 else
3010 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3011 }
3012
3013 /* Inform reload about cases where moving X with a mode MODE to a register in
3014 RCLASS requires an extra scratch or immediate register. Return the class
3015 needed for the immediate register. */
3016
3017 static reg_class_t
3018 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3019 enum machine_mode mode, secondary_reload_info *sri)
3020 {
3021 enum reg_class rclass = (enum reg_class) rclass_i;
3022
3023 /* Intermediate register needed. */
3024 if (reg_classes_intersect_p (CC_REGS, rclass))
3025 return GENERAL_REGS;
3026
3027 if (TARGET_Z10)
3028 {
3029 HOST_WIDE_INT offset;
3030 rtx symref;
3031
3032 /* On z10 several optimizer steps may generate larl operands with
3033 an odd addend. */
3034 if (in_p
3035 && s390_symref_operand_p (x, &symref, &offset)
3036 && mode == Pmode
3037 && !SYMBOL_REF_ALIGN1_P (symref)
3038 && (offset & 1) == 1)
3039 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3040 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3041
3042 /* On z10 we need a scratch register when moving QI, TI or floating
3043 point mode values from or to a memory location with a SYMBOL_REF
3044 or if the symref addend of a SI or DI move is not aligned to the
3045 width of the access. */
3046 if (MEM_P (x)
3047 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3048 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3049 || (!TARGET_ZARCH && mode == DImode)
3050 || ((mode == HImode || mode == SImode || mode == DImode)
3051 && (!s390_check_symref_alignment (XEXP (x, 0),
3052 GET_MODE_SIZE (mode))))))
3053 {
3054 #define __SECONDARY_RELOAD_CASE(M,m) \
3055 case M##mode: \
3056 if (TARGET_64BIT) \
3057 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3058 CODE_FOR_reload##m##di_tomem_z10; \
3059 else \
3060 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3061 CODE_FOR_reload##m##si_tomem_z10; \
3062 break;
3063
3064 switch (GET_MODE (x))
3065 {
3066 __SECONDARY_RELOAD_CASE (QI, qi);
3067 __SECONDARY_RELOAD_CASE (HI, hi);
3068 __SECONDARY_RELOAD_CASE (SI, si);
3069 __SECONDARY_RELOAD_CASE (DI, di);
3070 __SECONDARY_RELOAD_CASE (TI, ti);
3071 __SECONDARY_RELOAD_CASE (SF, sf);
3072 __SECONDARY_RELOAD_CASE (DF, df);
3073 __SECONDARY_RELOAD_CASE (TF, tf);
3074 __SECONDARY_RELOAD_CASE (SD, sd);
3075 __SECONDARY_RELOAD_CASE (DD, dd);
3076 __SECONDARY_RELOAD_CASE (TD, td);
3077
3078 default:
3079 gcc_unreachable ();
3080 }
3081 #undef __SECONDARY_RELOAD_CASE
3082 }
3083 }
3084
3085 /* We need a scratch register when loading a PLUS expression which
3086 is not a legitimate operand of the LOAD ADDRESS instruction. */
3087 if (in_p && s390_plus_operand (x, mode))
3088 sri->icode = (TARGET_64BIT ?
3089 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3090
3091 /* Performing a multiword move from or to memory we have to make sure the
3092 second chunk in memory is addressable without causing a displacement
3093 overflow. If that would be the case we calculate the address in
3094 a scratch register. */
3095 if (MEM_P (x)
3096 && GET_CODE (XEXP (x, 0)) == PLUS
3097 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3098 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3099 + GET_MODE_SIZE (mode) - 1))
3100 {
3101 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3102 in a s_operand address since we may fallback to lm/stm. So we only
3103 have to care about overflows in the b+i+d case. */
3104 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3105 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3106 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3107 /* For FP_REGS no lm/stm is available so this check is triggered
3108 for displacement overflows in b+i+d and b+d like addresses. */
3109 || (reg_classes_intersect_p (FP_REGS, rclass)
3110 && s390_class_max_nregs (FP_REGS, mode) > 1))
3111 {
3112 if (in_p)
3113 sri->icode = (TARGET_64BIT ?
3114 CODE_FOR_reloaddi_nonoffmem_in :
3115 CODE_FOR_reloadsi_nonoffmem_in);
3116 else
3117 sri->icode = (TARGET_64BIT ?
3118 CODE_FOR_reloaddi_nonoffmem_out :
3119 CODE_FOR_reloadsi_nonoffmem_out);
3120 }
3121 }
3122
3123 /* A scratch address register is needed when a symbolic constant is
3124 copied to r0 compiling with -fPIC. In other cases the target
3125 register might be used as temporary (see legitimize_pic_address). */
3126 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3127 sri->icode = (TARGET_64BIT ?
3128 CODE_FOR_reloaddi_PIC_addr :
3129 CODE_FOR_reloadsi_PIC_addr);
3130
3131 /* Either scratch or no register needed. */
3132 return NO_REGS;
3133 }
3134
3135 /* Generate code to load SRC, which is PLUS that is not a
3136 legitimate operand for the LA instruction, into TARGET.
3137 SCRATCH may be used as scratch register. */
3138
3139 void
3140 s390_expand_plus_operand (rtx target, rtx src,
3141 rtx scratch)
3142 {
3143 rtx sum1, sum2;
3144 struct s390_address ad;
3145
3146 /* src must be a PLUS; get its two operands. */
3147 gcc_assert (GET_CODE (src) == PLUS);
3148 gcc_assert (GET_MODE (src) == Pmode);
3149
3150 /* Check if any of the two operands is already scheduled
3151 for replacement by reload. This can happen e.g. when
3152 float registers occur in an address. */
3153 sum1 = find_replacement (&XEXP (src, 0));
3154 sum2 = find_replacement (&XEXP (src, 1));
3155 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3156
3157 /* If the address is already strictly valid, there's nothing to do. */
3158 if (!s390_decompose_address (src, &ad)
3159 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3160 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3161 {
3162 /* Otherwise, one of the operands cannot be an address register;
3163 we reload its value into the scratch register. */
3164 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3165 {
3166 emit_move_insn (scratch, sum1);
3167 sum1 = scratch;
3168 }
3169 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3170 {
3171 emit_move_insn (scratch, sum2);
3172 sum2 = scratch;
3173 }
3174
3175 /* According to the way these invalid addresses are generated
3176 in reload.c, it should never happen (at least on s390) that
3177 *neither* of the PLUS components, after find_replacements
3178 was applied, is an address register. */
3179 if (sum1 == scratch && sum2 == scratch)
3180 {
3181 debug_rtx (src);
3182 gcc_unreachable ();
3183 }
3184
3185 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3186 }
3187
3188 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3189 is only ever performed on addresses, so we can mark the
3190 sum as legitimate for LA in any case. */
3191 s390_load_address (target, src);
3192 }
3193
3194
3195 /* Return true if ADDR is a valid memory address.
3196 STRICT specifies whether strict register checking applies. */
3197
3198 static bool
3199 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3200 {
3201 struct s390_address ad;
3202
3203 if (TARGET_Z10
3204 && larl_operand (addr, VOIDmode)
3205 && (mode == VOIDmode
3206 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3207 return true;
3208
3209 if (!s390_decompose_address (addr, &ad))
3210 return false;
3211
3212 if (strict)
3213 {
3214 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3215 return false;
3216
3217 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3218 return false;
3219 }
3220 else
3221 {
3222 if (ad.base
3223 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3224 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3225 return false;
3226
3227 if (ad.indx
3228 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3229 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3230 return false;
3231 }
3232 return true;
3233 }
3234
3235 /* Return true if OP is a valid operand for the LA instruction.
3236 In 31-bit, we need to prove that the result is used as an
3237 address, as LA performs only a 31-bit addition. */
3238
3239 bool
3240 legitimate_la_operand_p (rtx op)
3241 {
3242 struct s390_address addr;
3243 if (!s390_decompose_address (op, &addr))
3244 return false;
3245
3246 return (TARGET_64BIT || addr.pointer);
3247 }
3248
3249 /* Return true if it is valid *and* preferable to use LA to
3250 compute the sum of OP1 and OP2. */
3251
3252 bool
3253 preferred_la_operand_p (rtx op1, rtx op2)
3254 {
3255 struct s390_address addr;
3256
3257 if (op2 != const0_rtx)
3258 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3259
3260 if (!s390_decompose_address (op1, &addr))
3261 return false;
3262 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3263 return false;
3264 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3265 return false;
3266
3267 /* Avoid LA instructions with index register on z196; it is
3268 preferable to use regular add instructions when possible. */
3269 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3270 return false;
3271
3272 if (!TARGET_64BIT && !addr.pointer)
3273 return false;
3274
3275 if (addr.pointer)
3276 return true;
3277
3278 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3279 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3280 return true;
3281
3282 return false;
3283 }
3284
3285 /* Emit a forced load-address operation to load SRC into DST.
3286 This will use the LOAD ADDRESS instruction even in situations
3287 where legitimate_la_operand_p (SRC) returns false. */
3288
3289 void
3290 s390_load_address (rtx dst, rtx src)
3291 {
3292 if (TARGET_64BIT)
3293 emit_move_insn (dst, src);
3294 else
3295 emit_insn (gen_force_la_31 (dst, src));
3296 }
3297
3298 /* Return a legitimate reference for ORIG (an address) using the
3299 register REG. If REG is 0, a new pseudo is generated.
3300
3301 There are two types of references that must be handled:
3302
3303 1. Global data references must load the address from the GOT, via
3304 the PIC reg. An insn is emitted to do this load, and the reg is
3305 returned.
3306
3307 2. Static data references, constant pool addresses, and code labels
3308 compute the address as an offset from the GOT, whose base is in
3309 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3310 differentiate them from global data objects. The returned
3311 address is the PIC reg + an unspec constant.
3312
3313 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3314 reg also appears in the address. */
3315
3316 rtx
3317 legitimize_pic_address (rtx orig, rtx reg)
3318 {
3319 rtx addr = orig;
3320 rtx new_rtx = orig;
3321 rtx base;
3322
3323 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3324
3325 if (GET_CODE (addr) == LABEL_REF
3326 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3327 {
3328 /* This is a local symbol. */
3329 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3330 {
3331 /* Access local symbols PC-relative via LARL.
3332 This is the same as in the non-PIC case, so it is
3333 handled automatically ... */
3334 }
3335 else
3336 {
3337 /* Access local symbols relative to the GOT. */
3338
3339 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3340
3341 if (reload_in_progress || reload_completed)
3342 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3343
3344 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3345 addr = gen_rtx_CONST (Pmode, addr);
3346 addr = force_const_mem (Pmode, addr);
3347 emit_move_insn (temp, addr);
3348
3349 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3350 if (reg != 0)
3351 {
3352 s390_load_address (reg, new_rtx);
3353 new_rtx = reg;
3354 }
3355 }
3356 }
3357 else if (GET_CODE (addr) == SYMBOL_REF)
3358 {
3359 if (reg == 0)
3360 reg = gen_reg_rtx (Pmode);
3361
3362 if (flag_pic == 1)
3363 {
3364 /* Assume GOT offset < 4k. This is handled the same way
3365 in both 31- and 64-bit code (@GOT). */
3366
3367 if (reload_in_progress || reload_completed)
3368 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3369
3370 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3371 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3372 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3373 new_rtx = gen_const_mem (Pmode, new_rtx);
3374 emit_move_insn (reg, new_rtx);
3375 new_rtx = reg;
3376 }
3377 else if (TARGET_CPU_ZARCH)
3378 {
3379 /* If the GOT offset might be >= 4k, we determine the position
3380 of the GOT entry via a PC-relative LARL (@GOTENT). */
3381
3382 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3383
3384 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3385 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3386
3387 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3388 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3389 emit_move_insn (temp, new_rtx);
3390
3391 new_rtx = gen_const_mem (Pmode, temp);
3392 emit_move_insn (reg, new_rtx);
3393 new_rtx = reg;
3394 }
3395 else
3396 {
3397 /* If the GOT offset might be >= 4k, we have to load it
3398 from the literal pool (@GOT). */
3399
3400 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3401
3402 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3403 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3404
3405 if (reload_in_progress || reload_completed)
3406 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3407
3408 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3409 addr = gen_rtx_CONST (Pmode, addr);
3410 addr = force_const_mem (Pmode, addr);
3411 emit_move_insn (temp, addr);
3412
3413 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3414 new_rtx = gen_const_mem (Pmode, new_rtx);
3415 emit_move_insn (reg, new_rtx);
3416 new_rtx = reg;
3417 }
3418 }
3419 else
3420 {
3421 if (GET_CODE (addr) == CONST)
3422 {
3423 addr = XEXP (addr, 0);
3424 if (GET_CODE (addr) == UNSPEC)
3425 {
3426 gcc_assert (XVECLEN (addr, 0) == 1);
3427 switch (XINT (addr, 1))
3428 {
3429 /* If someone moved a GOT-relative UNSPEC
3430 out of the literal pool, force them back in. */
3431 case UNSPEC_GOTOFF:
3432 case UNSPEC_PLTOFF:
3433 new_rtx = force_const_mem (Pmode, orig);
3434 break;
3435
3436 /* @GOT is OK as is if small. */
3437 case UNSPEC_GOT:
3438 if (flag_pic == 2)
3439 new_rtx = force_const_mem (Pmode, orig);
3440 break;
3441
3442 /* @GOTENT is OK as is. */
3443 case UNSPEC_GOTENT:
3444 break;
3445
3446 /* @PLT is OK as is on 64-bit, must be converted to
3447 GOT-relative @PLTOFF on 31-bit. */
3448 case UNSPEC_PLT:
3449 if (!TARGET_CPU_ZARCH)
3450 {
3451 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3452
3453 if (reload_in_progress || reload_completed)
3454 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3455
3456 addr = XVECEXP (addr, 0, 0);
3457 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3458 UNSPEC_PLTOFF);
3459 addr = gen_rtx_CONST (Pmode, addr);
3460 addr = force_const_mem (Pmode, addr);
3461 emit_move_insn (temp, addr);
3462
3463 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3464 if (reg != 0)
3465 {
3466 s390_load_address (reg, new_rtx);
3467 new_rtx = reg;
3468 }
3469 }
3470 break;
3471
3472 /* Everything else cannot happen. */
3473 default:
3474 gcc_unreachable ();
3475 }
3476 }
3477 else
3478 gcc_assert (GET_CODE (addr) == PLUS);
3479 }
3480 if (GET_CODE (addr) == PLUS)
3481 {
3482 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3483
3484 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3485 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3486
3487 /* Check first to see if this is a constant offset
3488 from a local symbol reference. */
3489 if ((GET_CODE (op0) == LABEL_REF
3490 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3491 && GET_CODE (op1) == CONST_INT)
3492 {
3493 if (TARGET_CPU_ZARCH
3494 && larl_operand (op0, VOIDmode)
3495 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3496 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3497 {
3498 if (INTVAL (op1) & 1)
3499 {
3500 /* LARL can't handle odd offsets, so emit a
3501 pair of LARL and LA. */
3502 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3503
3504 if (!DISP_IN_RANGE (INTVAL (op1)))
3505 {
3506 HOST_WIDE_INT even = INTVAL (op1) - 1;
3507 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3508 op0 = gen_rtx_CONST (Pmode, op0);
3509 op1 = const1_rtx;
3510 }
3511
3512 emit_move_insn (temp, op0);
3513 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3514
3515 if (reg != 0)
3516 {
3517 s390_load_address (reg, new_rtx);
3518 new_rtx = reg;
3519 }
3520 }
3521 else
3522 {
3523 /* If the offset is even, we can just use LARL.
3524 This will happen automatically. */
3525 }
3526 }
3527 else
3528 {
3529 /* Access local symbols relative to the GOT. */
3530
3531 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3532
3533 if (reload_in_progress || reload_completed)
3534 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3535
3536 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3537 UNSPEC_GOTOFF);
3538 addr = gen_rtx_PLUS (Pmode, addr, op1);
3539 addr = gen_rtx_CONST (Pmode, addr);
3540 addr = force_const_mem (Pmode, addr);
3541 emit_move_insn (temp, addr);
3542
3543 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3544 if (reg != 0)
3545 {
3546 s390_load_address (reg, new_rtx);
3547 new_rtx = reg;
3548 }
3549 }
3550 }
3551
3552 /* Now, check whether it is a GOT relative symbol plus offset
3553 that was pulled out of the literal pool. Force it back in. */
3554
3555 else if (GET_CODE (op0) == UNSPEC
3556 && GET_CODE (op1) == CONST_INT
3557 && XINT (op0, 1) == UNSPEC_GOTOFF)
3558 {
3559 gcc_assert (XVECLEN (op0, 0) == 1);
3560
3561 new_rtx = force_const_mem (Pmode, orig);
3562 }
3563
3564 /* Otherwise, compute the sum. */
3565 else
3566 {
3567 base = legitimize_pic_address (XEXP (addr, 0), reg);
3568 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3569 base == reg ? NULL_RTX : reg);
3570 if (GET_CODE (new_rtx) == CONST_INT)
3571 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3572 else
3573 {
3574 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3575 {
3576 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3577 new_rtx = XEXP (new_rtx, 1);
3578 }
3579 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3580 }
3581
3582 if (GET_CODE (new_rtx) == CONST)
3583 new_rtx = XEXP (new_rtx, 0);
3584 new_rtx = force_operand (new_rtx, 0);
3585 }
3586 }
3587 }
3588 return new_rtx;
3589 }
3590
3591 /* Load the thread pointer into a register. */
3592
3593 rtx
3594 s390_get_thread_pointer (void)
3595 {
3596 rtx tp = gen_reg_rtx (Pmode);
3597
3598 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3599 mark_reg_pointer (tp, BITS_PER_WORD);
3600
3601 return tp;
3602 }
3603
3604 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3605 in s390_tls_symbol which always refers to __tls_get_offset.
3606 The returned offset is written to RESULT_REG and an USE rtx is
3607 generated for TLS_CALL. */
3608
3609 static GTY(()) rtx s390_tls_symbol;
3610
3611 static void
3612 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3613 {
3614 rtx insn;
3615
3616 if (!flag_pic)
3617 emit_insn (s390_load_got ());
3618
3619 if (!s390_tls_symbol)
3620 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3621
3622 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3623 gen_rtx_REG (Pmode, RETURN_REGNUM));
3624
3625 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3626 RTL_CONST_CALL_P (insn) = 1;
3627 }
3628
3629 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3630 this (thread-local) address. REG may be used as temporary. */
3631
3632 static rtx
3633 legitimize_tls_address (rtx addr, rtx reg)
3634 {
3635 rtx new_rtx, tls_call, temp, base, r2, insn;
3636
3637 if (GET_CODE (addr) == SYMBOL_REF)
3638 switch (tls_symbolic_operand (addr))
3639 {
3640 case TLS_MODEL_GLOBAL_DYNAMIC:
3641 start_sequence ();
3642 r2 = gen_rtx_REG (Pmode, 2);
3643 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3644 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3645 new_rtx = force_const_mem (Pmode, new_rtx);
3646 emit_move_insn (r2, new_rtx);
3647 s390_emit_tls_call_insn (r2, tls_call);
3648 insn = get_insns ();
3649 end_sequence ();
3650
3651 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3652 temp = gen_reg_rtx (Pmode);
3653 emit_libcall_block (insn, temp, r2, new_rtx);
3654
3655 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3656 if (reg != 0)
3657 {
3658 s390_load_address (reg, new_rtx);
3659 new_rtx = reg;
3660 }
3661 break;
3662
3663 case TLS_MODEL_LOCAL_DYNAMIC:
3664 start_sequence ();
3665 r2 = gen_rtx_REG (Pmode, 2);
3666 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3667 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3668 new_rtx = force_const_mem (Pmode, new_rtx);
3669 emit_move_insn (r2, new_rtx);
3670 s390_emit_tls_call_insn (r2, tls_call);
3671 insn = get_insns ();
3672 end_sequence ();
3673
3674 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3675 temp = gen_reg_rtx (Pmode);
3676 emit_libcall_block (insn, temp, r2, new_rtx);
3677
3678 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3679 base = gen_reg_rtx (Pmode);
3680 s390_load_address (base, new_rtx);
3681
3682 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3683 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3684 new_rtx = force_const_mem (Pmode, new_rtx);
3685 temp = gen_reg_rtx (Pmode);
3686 emit_move_insn (temp, new_rtx);
3687
3688 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3689 if (reg != 0)
3690 {
3691 s390_load_address (reg, new_rtx);
3692 new_rtx = reg;
3693 }
3694 break;
3695
3696 case TLS_MODEL_INITIAL_EXEC:
3697 if (flag_pic == 1)
3698 {
3699 /* Assume GOT offset < 4k. This is handled the same way
3700 in both 31- and 64-bit code. */
3701
3702 if (reload_in_progress || reload_completed)
3703 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3704
3705 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3706 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3707 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3708 new_rtx = gen_const_mem (Pmode, new_rtx);
3709 temp = gen_reg_rtx (Pmode);
3710 emit_move_insn (temp, new_rtx);
3711 }
3712 else if (TARGET_CPU_ZARCH)
3713 {
3714 /* If the GOT offset might be >= 4k, we determine the position
3715 of the GOT entry via a PC-relative LARL. */
3716
3717 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3718 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3719 temp = gen_reg_rtx (Pmode);
3720 emit_move_insn (temp, new_rtx);
3721
3722 new_rtx = gen_const_mem (Pmode, temp);
3723 temp = gen_reg_rtx (Pmode);
3724 emit_move_insn (temp, new_rtx);
3725 }
3726 else if (flag_pic)
3727 {
3728 /* If the GOT offset might be >= 4k, we have to load it
3729 from the literal pool. */
3730
3731 if (reload_in_progress || reload_completed)
3732 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3733
3734 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3735 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3736 new_rtx = force_const_mem (Pmode, new_rtx);
3737 temp = gen_reg_rtx (Pmode);
3738 emit_move_insn (temp, new_rtx);
3739
3740 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3741 new_rtx = gen_const_mem (Pmode, new_rtx);
3742
3743 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3744 temp = gen_reg_rtx (Pmode);
3745 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3746 }
3747 else
3748 {
3749 /* In position-dependent code, load the absolute address of
3750 the GOT entry from the literal pool. */
3751
3752 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3753 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3754 new_rtx = force_const_mem (Pmode, new_rtx);
3755 temp = gen_reg_rtx (Pmode);
3756 emit_move_insn (temp, new_rtx);
3757
3758 new_rtx = temp;
3759 new_rtx = gen_const_mem (Pmode, new_rtx);
3760 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3761 temp = gen_reg_rtx (Pmode);
3762 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3763 }
3764
3765 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3766 if (reg != 0)
3767 {
3768 s390_load_address (reg, new_rtx);
3769 new_rtx = reg;
3770 }
3771 break;
3772
3773 case TLS_MODEL_LOCAL_EXEC:
3774 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3775 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3776 new_rtx = force_const_mem (Pmode, new_rtx);
3777 temp = gen_reg_rtx (Pmode);
3778 emit_move_insn (temp, new_rtx);
3779
3780 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3781 if (reg != 0)
3782 {
3783 s390_load_address (reg, new_rtx);
3784 new_rtx = reg;
3785 }
3786 break;
3787
3788 default:
3789 gcc_unreachable ();
3790 }
3791
3792 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3793 {
3794 switch (XINT (XEXP (addr, 0), 1))
3795 {
3796 case UNSPEC_INDNTPOFF:
3797 gcc_assert (TARGET_CPU_ZARCH);
3798 new_rtx = addr;
3799 break;
3800
3801 default:
3802 gcc_unreachable ();
3803 }
3804 }
3805
3806 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3807 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3808 {
3809 new_rtx = XEXP (XEXP (addr, 0), 0);
3810 if (GET_CODE (new_rtx) != SYMBOL_REF)
3811 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3812
3813 new_rtx = legitimize_tls_address (new_rtx, reg);
3814 new_rtx = plus_constant (Pmode, new_rtx,
3815 INTVAL (XEXP (XEXP (addr, 0), 1)));
3816 new_rtx = force_operand (new_rtx, 0);
3817 }
3818
3819 else
3820 gcc_unreachable (); /* for now ... */
3821
3822 return new_rtx;
3823 }
3824
3825 /* Emit insns making the address in operands[1] valid for a standard
3826 move to operands[0]. operands[1] is replaced by an address which
3827 should be used instead of the former RTX to emit the move
3828 pattern. */
3829
3830 void
3831 emit_symbolic_move (rtx *operands)
3832 {
3833 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3834
3835 if (GET_CODE (operands[0]) == MEM)
3836 operands[1] = force_reg (Pmode, operands[1]);
3837 else if (TLS_SYMBOLIC_CONST (operands[1]))
3838 operands[1] = legitimize_tls_address (operands[1], temp);
3839 else if (flag_pic)
3840 operands[1] = legitimize_pic_address (operands[1], temp);
3841 }
3842
3843 /* Try machine-dependent ways of modifying an illegitimate address X
3844 to be legitimate. If we find one, return the new, valid address.
3845
3846 OLDX is the address as it was before break_out_memory_refs was called.
3847 In some cases it is useful to look at this to decide what needs to be done.
3848
3849 MODE is the mode of the operand pointed to by X.
3850
3851 When -fpic is used, special handling is needed for symbolic references.
3852 See comments by legitimize_pic_address for details. */
3853
3854 static rtx
3855 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3856 enum machine_mode mode ATTRIBUTE_UNUSED)
3857 {
3858 rtx constant_term = const0_rtx;
3859
3860 if (TLS_SYMBOLIC_CONST (x))
3861 {
3862 x = legitimize_tls_address (x, 0);
3863
3864 if (s390_legitimate_address_p (mode, x, FALSE))
3865 return x;
3866 }
3867 else if (GET_CODE (x) == PLUS
3868 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3869 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3870 {
3871 return x;
3872 }
3873 else if (flag_pic)
3874 {
3875 if (SYMBOLIC_CONST (x)
3876 || (GET_CODE (x) == PLUS
3877 && (SYMBOLIC_CONST (XEXP (x, 0))
3878 || SYMBOLIC_CONST (XEXP (x, 1)))))
3879 x = legitimize_pic_address (x, 0);
3880
3881 if (s390_legitimate_address_p (mode, x, FALSE))
3882 return x;
3883 }
3884
3885 x = eliminate_constant_term (x, &constant_term);
3886
3887 /* Optimize loading of large displacements by splitting them
3888 into the multiple of 4K and the rest; this allows the
3889 former to be CSE'd if possible.
3890
3891 Don't do this if the displacement is added to a register
3892 pointing into the stack frame, as the offsets will
3893 change later anyway. */
3894
3895 if (GET_CODE (constant_term) == CONST_INT
3896 && !TARGET_LONG_DISPLACEMENT
3897 && !DISP_IN_RANGE (INTVAL (constant_term))
3898 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3899 {
3900 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3901 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3902
3903 rtx temp = gen_reg_rtx (Pmode);
3904 rtx val = force_operand (GEN_INT (upper), temp);
3905 if (val != temp)
3906 emit_move_insn (temp, val);
3907
3908 x = gen_rtx_PLUS (Pmode, x, temp);
3909 constant_term = GEN_INT (lower);
3910 }
3911
3912 if (GET_CODE (x) == PLUS)
3913 {
3914 if (GET_CODE (XEXP (x, 0)) == REG)
3915 {
3916 rtx temp = gen_reg_rtx (Pmode);
3917 rtx val = force_operand (XEXP (x, 1), temp);
3918 if (val != temp)
3919 emit_move_insn (temp, val);
3920
3921 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3922 }
3923
3924 else if (GET_CODE (XEXP (x, 1)) == REG)
3925 {
3926 rtx temp = gen_reg_rtx (Pmode);
3927 rtx val = force_operand (XEXP (x, 0), temp);
3928 if (val != temp)
3929 emit_move_insn (temp, val);
3930
3931 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3932 }
3933 }
3934
3935 if (constant_term != const0_rtx)
3936 x = gen_rtx_PLUS (Pmode, x, constant_term);
3937
3938 return x;
3939 }
3940
3941 /* Try a machine-dependent way of reloading an illegitimate address AD
3942 operand. If we find one, push the reload and return the new address.
3943
3944 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3945 and TYPE is the reload type of the current reload. */
3946
3947 rtx
3948 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3949 int opnum, int type)
3950 {
3951 if (!optimize || TARGET_LONG_DISPLACEMENT)
3952 return NULL_RTX;
3953
3954 if (GET_CODE (ad) == PLUS)
3955 {
3956 rtx tem = simplify_binary_operation (PLUS, Pmode,
3957 XEXP (ad, 0), XEXP (ad, 1));
3958 if (tem)
3959 ad = tem;
3960 }
3961
3962 if (GET_CODE (ad) == PLUS
3963 && GET_CODE (XEXP (ad, 0)) == REG
3964 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3965 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3966 {
3967 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3968 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3969 rtx cst, tem, new_rtx;
3970
3971 cst = GEN_INT (upper);
3972 if (!legitimate_reload_constant_p (cst))
3973 cst = force_const_mem (Pmode, cst);
3974
3975 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3976 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3977
3978 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3979 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3980 opnum, (enum reload_type) type);
3981 return new_rtx;
3982 }
3983
3984 return NULL_RTX;
3985 }
3986
3987 /* Emit code to move LEN bytes from DST to SRC. */
3988
3989 void
3990 s390_expand_movmem (rtx dst, rtx src, rtx len)
3991 {
3992 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3993 {
3994 if (INTVAL (len) > 0)
3995 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3996 }
3997
3998 else if (TARGET_MVCLE)
3999 {
4000 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4001 }
4002
4003 else
4004 {
4005 rtx dst_addr, src_addr, count, blocks, temp;
4006 rtx loop_start_label = gen_label_rtx ();
4007 rtx loop_end_label = gen_label_rtx ();
4008 rtx end_label = gen_label_rtx ();
4009 enum machine_mode mode;
4010
4011 mode = GET_MODE (len);
4012 if (mode == VOIDmode)
4013 mode = Pmode;
4014
4015 dst_addr = gen_reg_rtx (Pmode);
4016 src_addr = gen_reg_rtx (Pmode);
4017 count = gen_reg_rtx (mode);
4018 blocks = gen_reg_rtx (mode);
4019
4020 convert_move (count, len, 1);
4021 emit_cmp_and_jump_insns (count, const0_rtx,
4022 EQ, NULL_RTX, mode, 1, end_label);
4023
4024 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4025 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4026 dst = change_address (dst, VOIDmode, dst_addr);
4027 src = change_address (src, VOIDmode, src_addr);
4028
4029 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4030 OPTAB_DIRECT);
4031 if (temp != count)
4032 emit_move_insn (count, temp);
4033
4034 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4035 OPTAB_DIRECT);
4036 if (temp != blocks)
4037 emit_move_insn (blocks, temp);
4038
4039 emit_cmp_and_jump_insns (blocks, const0_rtx,
4040 EQ, NULL_RTX, mode, 1, loop_end_label);
4041
4042 emit_label (loop_start_label);
4043
4044 if (TARGET_Z10
4045 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4046 {
4047 rtx prefetch;
4048
4049 /* Issue a read prefetch for the +3 cache line. */
4050 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4051 const0_rtx, const0_rtx);
4052 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4053 emit_insn (prefetch);
4054
4055 /* Issue a write prefetch for the +3 cache line. */
4056 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4057 const1_rtx, const0_rtx);
4058 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4059 emit_insn (prefetch);
4060 }
4061
4062 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4063 s390_load_address (dst_addr,
4064 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4065 s390_load_address (src_addr,
4066 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4067
4068 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4069 OPTAB_DIRECT);
4070 if (temp != blocks)
4071 emit_move_insn (blocks, temp);
4072
4073 emit_cmp_and_jump_insns (blocks, const0_rtx,
4074 EQ, NULL_RTX, mode, 1, loop_end_label);
4075
4076 emit_jump (loop_start_label);
4077 emit_label (loop_end_label);
4078
4079 emit_insn (gen_movmem_short (dst, src,
4080 convert_to_mode (Pmode, count, 1)));
4081 emit_label (end_label);
4082 }
4083 }
4084
4085 /* Emit code to set LEN bytes at DST to VAL.
4086 Make use of clrmem if VAL is zero. */
4087
4088 void
4089 s390_expand_setmem (rtx dst, rtx len, rtx val)
4090 {
4091 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4092 return;
4093
4094 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4095
4096 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4097 {
4098 if (val == const0_rtx && INTVAL (len) <= 256)
4099 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4100 else
4101 {
4102 /* Initialize memory by storing the first byte. */
4103 emit_move_insn (adjust_address (dst, QImode, 0), val);
4104
4105 if (INTVAL (len) > 1)
4106 {
4107 /* Initiate 1 byte overlap move.
4108 The first byte of DST is propagated through DSTP1.
4109 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4110 DST is set to size 1 so the rest of the memory location
4111 does not count as source operand. */
4112 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4113 set_mem_size (dst, 1);
4114
4115 emit_insn (gen_movmem_short (dstp1, dst,
4116 GEN_INT (INTVAL (len) - 2)));
4117 }
4118 }
4119 }
4120
4121 else if (TARGET_MVCLE)
4122 {
4123 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4124 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4125 }
4126
4127 else
4128 {
4129 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4130 rtx loop_start_label = gen_label_rtx ();
4131 rtx loop_end_label = gen_label_rtx ();
4132 rtx end_label = gen_label_rtx ();
4133 enum machine_mode mode;
4134
4135 mode = GET_MODE (len);
4136 if (mode == VOIDmode)
4137 mode = Pmode;
4138
4139 dst_addr = gen_reg_rtx (Pmode);
4140 count = gen_reg_rtx (mode);
4141 blocks = gen_reg_rtx (mode);
4142
4143 convert_move (count, len, 1);
4144 emit_cmp_and_jump_insns (count, const0_rtx,
4145 EQ, NULL_RTX, mode, 1, end_label);
4146
4147 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4148 dst = change_address (dst, VOIDmode, dst_addr);
4149
4150 if (val == const0_rtx)
4151 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4152 OPTAB_DIRECT);
4153 else
4154 {
4155 dstp1 = adjust_address (dst, VOIDmode, 1);
4156 set_mem_size (dst, 1);
4157
4158 /* Initialize memory by storing the first byte. */
4159 emit_move_insn (adjust_address (dst, QImode, 0), val);
4160
4161 /* If count is 1 we are done. */
4162 emit_cmp_and_jump_insns (count, const1_rtx,
4163 EQ, NULL_RTX, mode, 1, end_label);
4164
4165 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4166 OPTAB_DIRECT);
4167 }
4168 if (temp != count)
4169 emit_move_insn (count, temp);
4170
4171 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4172 OPTAB_DIRECT);
4173 if (temp != blocks)
4174 emit_move_insn (blocks, temp);
4175
4176 emit_cmp_and_jump_insns (blocks, const0_rtx,
4177 EQ, NULL_RTX, mode, 1, loop_end_label);
4178
4179 emit_label (loop_start_label);
4180
4181 if (TARGET_Z10
4182 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4183 {
4184 /* Issue a write prefetch for the +4 cache line. */
4185 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4186 GEN_INT (1024)),
4187 const1_rtx, const0_rtx);
4188 emit_insn (prefetch);
4189 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4190 }
4191
4192 if (val == const0_rtx)
4193 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4194 else
4195 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4196 s390_load_address (dst_addr,
4197 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4198
4199 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4200 OPTAB_DIRECT);
4201 if (temp != blocks)
4202 emit_move_insn (blocks, temp);
4203
4204 emit_cmp_and_jump_insns (blocks, const0_rtx,
4205 EQ, NULL_RTX, mode, 1, loop_end_label);
4206
4207 emit_jump (loop_start_label);
4208 emit_label (loop_end_label);
4209
4210 if (val == const0_rtx)
4211 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4212 else
4213 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4214 emit_label (end_label);
4215 }
4216 }
4217
4218 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4219 and return the result in TARGET. */
4220
4221 void
4222 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4223 {
4224 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4225 rtx tmp;
4226
4227 /* As the result of CMPINT is inverted compared to what we need,
4228 we have to swap the operands. */
4229 tmp = op0; op0 = op1; op1 = tmp;
4230
4231 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4232 {
4233 if (INTVAL (len) > 0)
4234 {
4235 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4236 emit_insn (gen_cmpint (target, ccreg));
4237 }
4238 else
4239 emit_move_insn (target, const0_rtx);
4240 }
4241 else if (TARGET_MVCLE)
4242 {
4243 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4244 emit_insn (gen_cmpint (target, ccreg));
4245 }
4246 else
4247 {
4248 rtx addr0, addr1, count, blocks, temp;
4249 rtx loop_start_label = gen_label_rtx ();
4250 rtx loop_end_label = gen_label_rtx ();
4251 rtx end_label = gen_label_rtx ();
4252 enum machine_mode mode;
4253
4254 mode = GET_MODE (len);
4255 if (mode == VOIDmode)
4256 mode = Pmode;
4257
4258 addr0 = gen_reg_rtx (Pmode);
4259 addr1 = gen_reg_rtx (Pmode);
4260 count = gen_reg_rtx (mode);
4261 blocks = gen_reg_rtx (mode);
4262
4263 convert_move (count, len, 1);
4264 emit_cmp_and_jump_insns (count, const0_rtx,
4265 EQ, NULL_RTX, mode, 1, end_label);
4266
4267 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4268 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4269 op0 = change_address (op0, VOIDmode, addr0);
4270 op1 = change_address (op1, VOIDmode, addr1);
4271
4272 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4273 OPTAB_DIRECT);
4274 if (temp != count)
4275 emit_move_insn (count, temp);
4276
4277 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4278 OPTAB_DIRECT);
4279 if (temp != blocks)
4280 emit_move_insn (blocks, temp);
4281
4282 emit_cmp_and_jump_insns (blocks, const0_rtx,
4283 EQ, NULL_RTX, mode, 1, loop_end_label);
4284
4285 emit_label (loop_start_label);
4286
4287 if (TARGET_Z10
4288 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4289 {
4290 rtx prefetch;
4291
4292 /* Issue a read prefetch for the +2 cache line of operand 1. */
4293 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4294 const0_rtx, const0_rtx);
4295 emit_insn (prefetch);
4296 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4297
4298 /* Issue a read prefetch for the +2 cache line of operand 2. */
4299 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4300 const0_rtx, const0_rtx);
4301 emit_insn (prefetch);
4302 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4303 }
4304
4305 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4306 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4307 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4308 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4309 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4310 emit_jump_insn (temp);
4311
4312 s390_load_address (addr0,
4313 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4314 s390_load_address (addr1,
4315 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4316
4317 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4318 OPTAB_DIRECT);
4319 if (temp != blocks)
4320 emit_move_insn (blocks, temp);
4321
4322 emit_cmp_and_jump_insns (blocks, const0_rtx,
4323 EQ, NULL_RTX, mode, 1, loop_end_label);
4324
4325 emit_jump (loop_start_label);
4326 emit_label (loop_end_label);
4327
4328 emit_insn (gen_cmpmem_short (op0, op1,
4329 convert_to_mode (Pmode, count, 1)));
4330 emit_label (end_label);
4331
4332 emit_insn (gen_cmpint (target, ccreg));
4333 }
4334 }
4335
4336
4337 /* Expand conditional increment or decrement using alc/slb instructions.
4338 Should generate code setting DST to either SRC or SRC + INCREMENT,
4339 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4340 Returns true if successful, false otherwise.
4341
4342 That makes it possible to implement some if-constructs without jumps e.g.:
4343 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4344 unsigned int a, b, c;
4345 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4346 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4347 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4348 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4349
4350 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4351 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4352 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4353 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4354 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4355
4356 bool
4357 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4358 rtx dst, rtx src, rtx increment)
4359 {
4360 enum machine_mode cmp_mode;
4361 enum machine_mode cc_mode;
4362 rtx op_res;
4363 rtx insn;
4364 rtvec p;
4365 int ret;
4366
4367 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4368 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4369 cmp_mode = SImode;
4370 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4371 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4372 cmp_mode = DImode;
4373 else
4374 return false;
4375
4376 /* Try ADD LOGICAL WITH CARRY. */
4377 if (increment == const1_rtx)
4378 {
4379 /* Determine CC mode to use. */
4380 if (cmp_code == EQ || cmp_code == NE)
4381 {
4382 if (cmp_op1 != const0_rtx)
4383 {
4384 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4385 NULL_RTX, 0, OPTAB_WIDEN);
4386 cmp_op1 = const0_rtx;
4387 }
4388
4389 cmp_code = cmp_code == EQ ? LEU : GTU;
4390 }
4391
4392 if (cmp_code == LTU || cmp_code == LEU)
4393 {
4394 rtx tem = cmp_op0;
4395 cmp_op0 = cmp_op1;
4396 cmp_op1 = tem;
4397 cmp_code = swap_condition (cmp_code);
4398 }
4399
4400 switch (cmp_code)
4401 {
4402 case GTU:
4403 cc_mode = CCUmode;
4404 break;
4405
4406 case GEU:
4407 cc_mode = CCL3mode;
4408 break;
4409
4410 default:
4411 return false;
4412 }
4413
4414 /* Emit comparison instruction pattern. */
4415 if (!register_operand (cmp_op0, cmp_mode))
4416 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4417
4418 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4419 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4420 /* We use insn_invalid_p here to add clobbers if required. */
4421 ret = insn_invalid_p (emit_insn (insn), false);
4422 gcc_assert (!ret);
4423
4424 /* Emit ALC instruction pattern. */
4425 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4426 gen_rtx_REG (cc_mode, CC_REGNUM),
4427 const0_rtx);
4428
4429 if (src != const0_rtx)
4430 {
4431 if (!register_operand (src, GET_MODE (dst)))
4432 src = force_reg (GET_MODE (dst), src);
4433
4434 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4435 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4436 }
4437
4438 p = rtvec_alloc (2);
4439 RTVEC_ELT (p, 0) =
4440 gen_rtx_SET (VOIDmode, dst, op_res);
4441 RTVEC_ELT (p, 1) =
4442 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4443 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4444
4445 return true;
4446 }
4447
4448 /* Try SUBTRACT LOGICAL WITH BORROW. */
4449 if (increment == constm1_rtx)
4450 {
4451 /* Determine CC mode to use. */
4452 if (cmp_code == EQ || cmp_code == NE)
4453 {
4454 if (cmp_op1 != const0_rtx)
4455 {
4456 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4457 NULL_RTX, 0, OPTAB_WIDEN);
4458 cmp_op1 = const0_rtx;
4459 }
4460
4461 cmp_code = cmp_code == EQ ? LEU : GTU;
4462 }
4463
4464 if (cmp_code == GTU || cmp_code == GEU)
4465 {
4466 rtx tem = cmp_op0;
4467 cmp_op0 = cmp_op1;
4468 cmp_op1 = tem;
4469 cmp_code = swap_condition (cmp_code);
4470 }
4471
4472 switch (cmp_code)
4473 {
4474 case LEU:
4475 cc_mode = CCUmode;
4476 break;
4477
4478 case LTU:
4479 cc_mode = CCL3mode;
4480 break;
4481
4482 default:
4483 return false;
4484 }
4485
4486 /* Emit comparison instruction pattern. */
4487 if (!register_operand (cmp_op0, cmp_mode))
4488 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4489
4490 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4491 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4492 /* We use insn_invalid_p here to add clobbers if required. */
4493 ret = insn_invalid_p (emit_insn (insn), false);
4494 gcc_assert (!ret);
4495
4496 /* Emit SLB instruction pattern. */
4497 if (!register_operand (src, GET_MODE (dst)))
4498 src = force_reg (GET_MODE (dst), src);
4499
4500 op_res = gen_rtx_MINUS (GET_MODE (dst),
4501 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4502 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4503 gen_rtx_REG (cc_mode, CC_REGNUM),
4504 const0_rtx));
4505 p = rtvec_alloc (2);
4506 RTVEC_ELT (p, 0) =
4507 gen_rtx_SET (VOIDmode, dst, op_res);
4508 RTVEC_ELT (p, 1) =
4509 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4510 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4511
4512 return true;
4513 }
4514
4515 return false;
4516 }
4517
4518 /* Expand code for the insv template. Return true if successful. */
4519
4520 bool
4521 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4522 {
4523 int bitsize = INTVAL (op1);
4524 int bitpos = INTVAL (op2);
4525
4526 /* On z10 we can use the risbg instruction to implement insv. */
4527 if (TARGET_Z10
4528 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4529 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4530 {
4531 rtx op;
4532 rtx clobber;
4533
4534 op = gen_rtx_SET (GET_MODE(src),
4535 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4536 src);
4537 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4538 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4539
4540 return true;
4541 }
4542
4543 /* We need byte alignment. */
4544 if (bitsize % BITS_PER_UNIT)
4545 return false;
4546
4547 if (bitpos == 0
4548 && memory_operand (dest, VOIDmode)
4549 && (register_operand (src, word_mode)
4550 || const_int_operand (src, VOIDmode)))
4551 {
4552 /* Emit standard pattern if possible. */
4553 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4554 if (GET_MODE_BITSIZE (mode) == bitsize)
4555 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4556
4557 /* (set (ze (mem)) (const_int)). */
4558 else if (const_int_operand (src, VOIDmode))
4559 {
4560 int size = bitsize / BITS_PER_UNIT;
4561 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4562 GET_MODE_SIZE (word_mode) - size);
4563
4564 dest = adjust_address (dest, BLKmode, 0);
4565 set_mem_size (dest, size);
4566 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4567 }
4568
4569 /* (set (ze (mem)) (reg)). */
4570 else if (register_operand (src, word_mode))
4571 {
4572 if (bitsize <= GET_MODE_BITSIZE (SImode))
4573 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4574 const0_rtx), src);
4575 else
4576 {
4577 /* Emit st,stcmh sequence. */
4578 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4579 int size = stcmh_width / BITS_PER_UNIT;
4580
4581 emit_move_insn (adjust_address (dest, SImode, size),
4582 gen_lowpart (SImode, src));
4583 set_mem_size (dest, size);
4584 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4585 (stcmh_width), const0_rtx),
4586 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4587 (GET_MODE_BITSIZE (SImode))));
4588 }
4589 }
4590 else
4591 return false;
4592
4593 return true;
4594 }
4595
4596 /* (set (ze (reg)) (const_int)). */
4597 if (TARGET_ZARCH
4598 && register_operand (dest, word_mode)
4599 && (bitpos % 16) == 0
4600 && (bitsize % 16) == 0
4601 && const_int_operand (src, VOIDmode))
4602 {
4603 HOST_WIDE_INT val = INTVAL (src);
4604 int regpos = bitpos + bitsize;
4605
4606 while (regpos > bitpos)
4607 {
4608 enum machine_mode putmode;
4609 int putsize;
4610
4611 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4612 putmode = SImode;
4613 else
4614 putmode = HImode;
4615
4616 putsize = GET_MODE_BITSIZE (putmode);
4617 regpos -= putsize;
4618 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4619 GEN_INT (putsize),
4620 GEN_INT (regpos)),
4621 gen_int_mode (val, putmode));
4622 val >>= putsize;
4623 }
4624 gcc_assert (regpos == bitpos);
4625 return true;
4626 }
4627
4628 return false;
4629 }
4630
4631 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4632 register that holds VAL of mode MODE shifted by COUNT bits. */
4633
4634 static inline rtx
4635 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4636 {
4637 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4638 NULL_RTX, 1, OPTAB_DIRECT);
4639 return expand_simple_binop (SImode, ASHIFT, val, count,
4640 NULL_RTX, 1, OPTAB_DIRECT);
4641 }
4642
4643 /* Structure to hold the initial parameters for a compare_and_swap operation
4644 in HImode and QImode. */
4645
4646 struct alignment_context
4647 {
4648 rtx memsi; /* SI aligned memory location. */
4649 rtx shift; /* Bit offset with regard to lsb. */
4650 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4651 rtx modemaski; /* ~modemask */
4652 bool aligned; /* True if memory is aligned, false else. */
4653 };
4654
4655 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4656 structure AC for transparent simplifying, if the memory alignment is known
4657 to be at least 32bit. MEM is the memory location for the actual operation
4658 and MODE its mode. */
4659
4660 static void
4661 init_alignment_context (struct alignment_context *ac, rtx mem,
4662 enum machine_mode mode)
4663 {
4664 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4665 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4666
4667 if (ac->aligned)
4668 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4669 else
4670 {
4671 /* Alignment is unknown. */
4672 rtx byteoffset, addr, align;
4673
4674 /* Force the address into a register. */
4675 addr = force_reg (Pmode, XEXP (mem, 0));
4676
4677 /* Align it to SImode. */
4678 align = expand_simple_binop (Pmode, AND, addr,
4679 GEN_INT (-GET_MODE_SIZE (SImode)),
4680 NULL_RTX, 1, OPTAB_DIRECT);
4681 /* Generate MEM. */
4682 ac->memsi = gen_rtx_MEM (SImode, align);
4683 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4684 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4685 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4686
4687 /* Calculate shiftcount. */
4688 byteoffset = expand_simple_binop (Pmode, AND, addr,
4689 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4690 NULL_RTX, 1, OPTAB_DIRECT);
4691 /* As we already have some offset, evaluate the remaining distance. */
4692 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4693 NULL_RTX, 1, OPTAB_DIRECT);
4694
4695 }
4696 /* Shift is the byte count, but we need the bitcount. */
4697 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4698 NULL_RTX, 1, OPTAB_DIRECT);
4699 /* Calculate masks. */
4700 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4701 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4702 NULL_RTX, 1, OPTAB_DIRECT);
4703 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4704 }
4705
4706 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4707 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4708 to set if CMP == MEM.
4709 CMP is never in memory for compare_and_swap_cc because
4710 expand_bool_compare_and_swap puts it into a register for later compare. */
4711
4712 void
4713 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4714 {
4715 struct alignment_context ac;
4716 rtx cmpv, newv, val, resv, cc;
4717 rtx res = gen_reg_rtx (SImode);
4718 rtx csloop = gen_label_rtx ();
4719 rtx csend = gen_label_rtx ();
4720
4721 gcc_assert (register_operand (target, VOIDmode));
4722 gcc_assert (MEM_P (mem));
4723
4724 init_alignment_context (&ac, mem, mode);
4725
4726 /* Shift the values to the correct bit positions. */
4727 if (!(ac.aligned && MEM_P (cmp)))
4728 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4729 if (!(ac.aligned && MEM_P (new_rtx)))
4730 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4731
4732 /* Load full word. Subsequent loads are performed by CS. */
4733 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4734 NULL_RTX, 1, OPTAB_DIRECT);
4735
4736 /* Start CS loop. */
4737 emit_label (csloop);
4738 /* val = "<mem>00..0<mem>"
4739 * cmp = "00..0<cmp>00..0"
4740 * new = "00..0<new>00..0"
4741 */
4742
4743 /* Patch cmp and new with val at correct position. */
4744 if (ac.aligned && MEM_P (cmp))
4745 {
4746 cmpv = force_reg (SImode, val);
4747 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0,
4748 0, 0, SImode, cmp);
4749 }
4750 else
4751 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4752 NULL_RTX, 1, OPTAB_DIRECT));
4753 if (ac.aligned && MEM_P (new_rtx))
4754 {
4755 newv = force_reg (SImode, val);
4756 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0,
4757 0, 0, SImode, new_rtx);
4758 }
4759 else
4760 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4761 NULL_RTX, 1, OPTAB_DIRECT));
4762
4763 /* Jump to end if we're done (likely?). */
4764 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4765 cmpv, newv));
4766
4767 /* Check for changes outside mode. */
4768 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4769 NULL_RTX, 1, OPTAB_DIRECT);
4770 cc = s390_emit_compare (NE, resv, val);
4771 emit_move_insn (val, resv);
4772 /* Loop internal if so. */
4773 s390_emit_jump (csloop, cc);
4774
4775 emit_label (csend);
4776
4777 /* Return the correct part of the bitfield. */
4778 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4779 NULL_RTX, 1, OPTAB_DIRECT), 1);
4780 }
4781
4782 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4783 and VAL the value to play with. If AFTER is true then store the value
4784 MEM holds after the operation, if AFTER is false then store the value MEM
4785 holds before the operation. If TARGET is zero then discard that value, else
4786 store it to TARGET. */
4787
4788 void
4789 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4790 rtx target, rtx mem, rtx val, bool after)
4791 {
4792 struct alignment_context ac;
4793 rtx cmp;
4794 rtx new_rtx = gen_reg_rtx (SImode);
4795 rtx orig = gen_reg_rtx (SImode);
4796 rtx csloop = gen_label_rtx ();
4797
4798 gcc_assert (!target || register_operand (target, VOIDmode));
4799 gcc_assert (MEM_P (mem));
4800
4801 init_alignment_context (&ac, mem, mode);
4802
4803 /* Shift val to the correct bit positions.
4804 Preserve "icm", but prevent "ex icm". */
4805 if (!(ac.aligned && code == SET && MEM_P (val)))
4806 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4807
4808 /* Further preparation insns. */
4809 if (code == PLUS || code == MINUS)
4810 emit_move_insn (orig, val);
4811 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4812 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4813 NULL_RTX, 1, OPTAB_DIRECT);
4814
4815 /* Load full word. Subsequent loads are performed by CS. */
4816 cmp = force_reg (SImode, ac.memsi);
4817
4818 /* Start CS loop. */
4819 emit_label (csloop);
4820 emit_move_insn (new_rtx, cmp);
4821
4822 /* Patch new with val at correct position. */
4823 switch (code)
4824 {
4825 case PLUS:
4826 case MINUS:
4827 val = expand_simple_binop (SImode, code, new_rtx, orig,
4828 NULL_RTX, 1, OPTAB_DIRECT);
4829 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4830 NULL_RTX, 1, OPTAB_DIRECT);
4831 /* FALLTHRU */
4832 case SET:
4833 if (ac.aligned && MEM_P (val))
4834 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
4835 0, 0, SImode, val);
4836 else
4837 {
4838 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4839 NULL_RTX, 1, OPTAB_DIRECT);
4840 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4841 NULL_RTX, 1, OPTAB_DIRECT);
4842 }
4843 break;
4844 case AND:
4845 case IOR:
4846 case XOR:
4847 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4848 NULL_RTX, 1, OPTAB_DIRECT);
4849 break;
4850 case MULT: /* NAND */
4851 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4852 NULL_RTX, 1, OPTAB_DIRECT);
4853 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4854 NULL_RTX, 1, OPTAB_DIRECT);
4855 break;
4856 default:
4857 gcc_unreachable ();
4858 }
4859
4860 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4861 ac.memsi, cmp, new_rtx));
4862
4863 /* Return the correct part of the bitfield. */
4864 if (target)
4865 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4866 after ? new_rtx : cmp, ac.shift,
4867 NULL_RTX, 1, OPTAB_DIRECT), 1);
4868 }
4869
4870 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4871 We need to emit DTP-relative relocations. */
4872
4873 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4874
4875 static void
4876 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4877 {
4878 switch (size)
4879 {
4880 case 4:
4881 fputs ("\t.long\t", file);
4882 break;
4883 case 8:
4884 fputs ("\t.quad\t", file);
4885 break;
4886 default:
4887 gcc_unreachable ();
4888 }
4889 output_addr_const (file, x);
4890 fputs ("@DTPOFF", file);
4891 }
4892
4893 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4894 /* Implement TARGET_MANGLE_TYPE. */
4895
4896 static const char *
4897 s390_mangle_type (const_tree type)
4898 {
4899 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4900 && TARGET_LONG_DOUBLE_128)
4901 return "g";
4902
4903 /* For all other types, use normal C++ mangling. */
4904 return NULL;
4905 }
4906 #endif
4907
4908 /* In the name of slightly smaller debug output, and to cater to
4909 general assembler lossage, recognize various UNSPEC sequences
4910 and turn them back into a direct symbol reference. */
4911
4912 static rtx
4913 s390_delegitimize_address (rtx orig_x)
4914 {
4915 rtx x, y;
4916
4917 orig_x = delegitimize_mem_from_attrs (orig_x);
4918 x = orig_x;
4919
4920 /* Extract the symbol ref from:
4921 (plus:SI (reg:SI 12 %r12)
4922 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4923 UNSPEC_GOTOFF/PLTOFF)))
4924 and
4925 (plus:SI (reg:SI 12 %r12)
4926 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4927 UNSPEC_GOTOFF/PLTOFF)
4928 (const_int 4 [0x4])))) */
4929 if (GET_CODE (x) == PLUS
4930 && REG_P (XEXP (x, 0))
4931 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
4932 && GET_CODE (XEXP (x, 1)) == CONST)
4933 {
4934 HOST_WIDE_INT offset = 0;
4935
4936 /* The const operand. */
4937 y = XEXP (XEXP (x, 1), 0);
4938
4939 if (GET_CODE (y) == PLUS
4940 && GET_CODE (XEXP (y, 1)) == CONST_INT)
4941 {
4942 offset = INTVAL (XEXP (y, 1));
4943 y = XEXP (y, 0);
4944 }
4945
4946 if (GET_CODE (y) == UNSPEC
4947 && (XINT (y, 1) == UNSPEC_GOTOFF
4948 || XINT (y, 1) == UNSPEC_PLTOFF))
4949 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
4950 }
4951
4952 if (GET_CODE (x) != MEM)
4953 return orig_x;
4954
4955 x = XEXP (x, 0);
4956 if (GET_CODE (x) == PLUS
4957 && GET_CODE (XEXP (x, 1)) == CONST
4958 && GET_CODE (XEXP (x, 0)) == REG
4959 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4960 {
4961 y = XEXP (XEXP (x, 1), 0);
4962 if (GET_CODE (y) == UNSPEC
4963 && XINT (y, 1) == UNSPEC_GOT)
4964 y = XVECEXP (y, 0, 0);
4965 else
4966 return orig_x;
4967 }
4968 else if (GET_CODE (x) == CONST)
4969 {
4970 /* Extract the symbol ref from:
4971 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
4972 UNSPEC_PLT/GOTENT))) */
4973
4974 y = XEXP (x, 0);
4975 if (GET_CODE (y) == UNSPEC
4976 && (XINT (y, 1) == UNSPEC_GOTENT
4977 || XINT (y, 1) == UNSPEC_PLT))
4978 y = XVECEXP (y, 0, 0);
4979 else
4980 return orig_x;
4981 }
4982 else
4983 return orig_x;
4984
4985 if (GET_MODE (orig_x) != Pmode)
4986 {
4987 if (GET_MODE (orig_x) == BLKmode)
4988 return orig_x;
4989 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
4990 if (y == NULL_RTX)
4991 return orig_x;
4992 }
4993 return y;
4994 }
4995
4996 /* Output operand OP to stdio stream FILE.
4997 OP is an address (register + offset) which is not used to address data;
4998 instead the rightmost bits are interpreted as the value. */
4999
5000 static void
5001 print_shift_count_operand (FILE *file, rtx op)
5002 {
5003 HOST_WIDE_INT offset;
5004 rtx base;
5005
5006 /* Extract base register and offset. */
5007 if (!s390_decompose_shift_count (op, &base, &offset))
5008 gcc_unreachable ();
5009
5010 /* Sanity check. */
5011 if (base)
5012 {
5013 gcc_assert (GET_CODE (base) == REG);
5014 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5015 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5016 }
5017
5018 /* Offsets are constricted to twelve bits. */
5019 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5020 if (base)
5021 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5022 }
5023
5024 /* See 'get_some_local_dynamic_name'. */
5025
5026 static int
5027 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5028 {
5029 rtx x = *px;
5030
5031 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5032 {
5033 x = get_pool_constant (x);
5034 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5035 }
5036
5037 if (GET_CODE (x) == SYMBOL_REF
5038 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5039 {
5040 cfun->machine->some_ld_name = XSTR (x, 0);
5041 return 1;
5042 }
5043
5044 return 0;
5045 }
5046
5047 /* Locate some local-dynamic symbol still in use by this function
5048 so that we can print its name in local-dynamic base patterns. */
5049
5050 static const char *
5051 get_some_local_dynamic_name (void)
5052 {
5053 rtx insn;
5054
5055 if (cfun->machine->some_ld_name)
5056 return cfun->machine->some_ld_name;
5057
5058 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5059 if (INSN_P (insn)
5060 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5061 return cfun->machine->some_ld_name;
5062
5063 gcc_unreachable ();
5064 }
5065
5066 /* Output machine-dependent UNSPECs occurring in address constant X
5067 in assembler syntax to stdio stream FILE. Returns true if the
5068 constant X could be recognized, false otherwise. */
5069
5070 static bool
5071 s390_output_addr_const_extra (FILE *file, rtx x)
5072 {
5073 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5074 switch (XINT (x, 1))
5075 {
5076 case UNSPEC_GOTENT:
5077 output_addr_const (file, XVECEXP (x, 0, 0));
5078 fprintf (file, "@GOTENT");
5079 return true;
5080 case UNSPEC_GOT:
5081 output_addr_const (file, XVECEXP (x, 0, 0));
5082 fprintf (file, "@GOT");
5083 return true;
5084 case UNSPEC_GOTOFF:
5085 output_addr_const (file, XVECEXP (x, 0, 0));
5086 fprintf (file, "@GOTOFF");
5087 return true;
5088 case UNSPEC_PLT:
5089 output_addr_const (file, XVECEXP (x, 0, 0));
5090 fprintf (file, "@PLT");
5091 return true;
5092 case UNSPEC_PLTOFF:
5093 output_addr_const (file, XVECEXP (x, 0, 0));
5094 fprintf (file, "@PLTOFF");
5095 return true;
5096 case UNSPEC_TLSGD:
5097 output_addr_const (file, XVECEXP (x, 0, 0));
5098 fprintf (file, "@TLSGD");
5099 return true;
5100 case UNSPEC_TLSLDM:
5101 assemble_name (file, get_some_local_dynamic_name ());
5102 fprintf (file, "@TLSLDM");
5103 return true;
5104 case UNSPEC_DTPOFF:
5105 output_addr_const (file, XVECEXP (x, 0, 0));
5106 fprintf (file, "@DTPOFF");
5107 return true;
5108 case UNSPEC_NTPOFF:
5109 output_addr_const (file, XVECEXP (x, 0, 0));
5110 fprintf (file, "@NTPOFF");
5111 return true;
5112 case UNSPEC_GOTNTPOFF:
5113 output_addr_const (file, XVECEXP (x, 0, 0));
5114 fprintf (file, "@GOTNTPOFF");
5115 return true;
5116 case UNSPEC_INDNTPOFF:
5117 output_addr_const (file, XVECEXP (x, 0, 0));
5118 fprintf (file, "@INDNTPOFF");
5119 return true;
5120 }
5121
5122 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5123 switch (XINT (x, 1))
5124 {
5125 case UNSPEC_POOL_OFFSET:
5126 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5127 output_addr_const (file, x);
5128 return true;
5129 }
5130 return false;
5131 }
5132
5133 /* Output address operand ADDR in assembler syntax to
5134 stdio stream FILE. */
5135
5136 void
5137 print_operand_address (FILE *file, rtx addr)
5138 {
5139 struct s390_address ad;
5140
5141 if (s390_symref_operand_p (addr, NULL, NULL))
5142 {
5143 if (!TARGET_Z10)
5144 {
5145 output_operand_lossage ("symbolic memory references are "
5146 "only supported on z10 or later");
5147 return;
5148 }
5149 output_addr_const (file, addr);
5150 return;
5151 }
5152
5153 if (!s390_decompose_address (addr, &ad)
5154 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5155 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5156 output_operand_lossage ("cannot decompose address");
5157
5158 if (ad.disp)
5159 output_addr_const (file, ad.disp);
5160 else
5161 fprintf (file, "0");
5162
5163 if (ad.base && ad.indx)
5164 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5165 reg_names[REGNO (ad.base)]);
5166 else if (ad.base)
5167 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5168 }
5169
5170 /* Output operand X in assembler syntax to stdio stream FILE.
5171 CODE specified the format flag. The following format flags
5172 are recognized:
5173
5174 'C': print opcode suffix for branch condition.
5175 'D': print opcode suffix for inverse branch condition.
5176 'E': print opcode suffix for branch on index instruction.
5177 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5178 'G': print the size of the operand in bytes.
5179 'O': print only the displacement of a memory reference.
5180 'R': print only the base register of a memory reference.
5181 'S': print S-type memory reference (base+displacement).
5182 'N': print the second word of a DImode operand.
5183 'M': print the second word of a TImode operand.
5184 'Y': print shift count operand.
5185
5186 'b': print integer X as if it's an unsigned byte.
5187 'c': print integer X as if it's an signed byte.
5188 'x': print integer X as if it's an unsigned halfword.
5189 'h': print integer X as if it's a signed halfword.
5190 'i': print the first nonzero HImode part of X.
5191 'j': print the first HImode part unequal to -1 of X.
5192 'k': print the first nonzero SImode part of X.
5193 'm': print the first SImode part unequal to -1 of X.
5194 'o': print integer X as if it's an unsigned 32bit word. */
5195
5196 void
5197 print_operand (FILE *file, rtx x, int code)
5198 {
5199 switch (code)
5200 {
5201 case 'C':
5202 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5203 return;
5204
5205 case 'D':
5206 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5207 return;
5208
5209 case 'E':
5210 if (GET_CODE (x) == LE)
5211 fprintf (file, "l");
5212 else if (GET_CODE (x) == GT)
5213 fprintf (file, "h");
5214 else
5215 output_operand_lossage ("invalid comparison operator "
5216 "for 'E' output modifier");
5217 return;
5218
5219 case 'J':
5220 if (GET_CODE (x) == SYMBOL_REF)
5221 {
5222 fprintf (file, "%s", ":tls_load:");
5223 output_addr_const (file, x);
5224 }
5225 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5226 {
5227 fprintf (file, "%s", ":tls_gdcall:");
5228 output_addr_const (file, XVECEXP (x, 0, 0));
5229 }
5230 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5231 {
5232 fprintf (file, "%s", ":tls_ldcall:");
5233 assemble_name (file, get_some_local_dynamic_name ());
5234 }
5235 else
5236 output_operand_lossage ("invalid reference for 'J' output modifier");
5237 return;
5238
5239 case 'G':
5240 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5241 return;
5242
5243 case 'O':
5244 {
5245 struct s390_address ad;
5246 int ret;
5247
5248 if (!MEM_P (x))
5249 {
5250 output_operand_lossage ("memory reference expected for "
5251 "'O' output modifier");
5252 return;
5253 }
5254
5255 ret = s390_decompose_address (XEXP (x, 0), &ad);
5256
5257 if (!ret
5258 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5259 || ad.indx)
5260 {
5261 output_operand_lossage ("invalid address for 'O' output modifier");
5262 return;
5263 }
5264
5265 if (ad.disp)
5266 output_addr_const (file, ad.disp);
5267 else
5268 fprintf (file, "0");
5269 }
5270 return;
5271
5272 case 'R':
5273 {
5274 struct s390_address ad;
5275 int ret;
5276
5277 if (!MEM_P (x))
5278 {
5279 output_operand_lossage ("memory reference expected for "
5280 "'R' output modifier");
5281 return;
5282 }
5283
5284 ret = s390_decompose_address (XEXP (x, 0), &ad);
5285
5286 if (!ret
5287 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5288 || ad.indx)
5289 {
5290 output_operand_lossage ("invalid address for 'R' output modifier");
5291 return;
5292 }
5293
5294 if (ad.base)
5295 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5296 else
5297 fprintf (file, "0");
5298 }
5299 return;
5300
5301 case 'S':
5302 {
5303 struct s390_address ad;
5304 int ret;
5305
5306 if (!MEM_P (x))
5307 {
5308 output_operand_lossage ("memory reference expected for "
5309 "'S' output modifier");
5310 return;
5311 }
5312 ret = s390_decompose_address (XEXP (x, 0), &ad);
5313
5314 if (!ret
5315 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5316 || ad.indx)
5317 {
5318 output_operand_lossage ("invalid address for 'S' output modifier");
5319 return;
5320 }
5321
5322 if (ad.disp)
5323 output_addr_const (file, ad.disp);
5324 else
5325 fprintf (file, "0");
5326
5327 if (ad.base)
5328 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5329 }
5330 return;
5331
5332 case 'N':
5333 if (GET_CODE (x) == REG)
5334 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5335 else if (GET_CODE (x) == MEM)
5336 x = change_address (x, VOIDmode,
5337 plus_constant (Pmode, XEXP (x, 0), 4));
5338 else
5339 output_operand_lossage ("register or memory expression expected "
5340 "for 'N' output modifier");
5341 break;
5342
5343 case 'M':
5344 if (GET_CODE (x) == REG)
5345 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5346 else if (GET_CODE (x) == MEM)
5347 x = change_address (x, VOIDmode,
5348 plus_constant (Pmode, XEXP (x, 0), 8));
5349 else
5350 output_operand_lossage ("register or memory expression expected "
5351 "for 'M' output modifier");
5352 break;
5353
5354 case 'Y':
5355 print_shift_count_operand (file, x);
5356 return;
5357 }
5358
5359 switch (GET_CODE (x))
5360 {
5361 case REG:
5362 fprintf (file, "%s", reg_names[REGNO (x)]);
5363 break;
5364
5365 case MEM:
5366 output_address (XEXP (x, 0));
5367 break;
5368
5369 case CONST:
5370 case CODE_LABEL:
5371 case LABEL_REF:
5372 case SYMBOL_REF:
5373 output_addr_const (file, x);
5374 break;
5375
5376 case CONST_INT:
5377 if (code == 'b')
5378 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5379 else if (code == 'c')
5380 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5381 else if (code == 'x')
5382 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5383 else if (code == 'h')
5384 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5385 else if (code == 'i')
5386 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5387 s390_extract_part (x, HImode, 0));
5388 else if (code == 'j')
5389 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5390 s390_extract_part (x, HImode, -1));
5391 else if (code == 'k')
5392 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5393 s390_extract_part (x, SImode, 0));
5394 else if (code == 'm')
5395 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5396 s390_extract_part (x, SImode, -1));
5397 else if (code == 'o')
5398 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5399 else
5400 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5401 break;
5402
5403 case CONST_DOUBLE:
5404 gcc_assert (GET_MODE (x) == VOIDmode);
5405 if (code == 'b')
5406 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5407 else if (code == 'x')
5408 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5409 else if (code == 'h')
5410 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5411 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5412 else
5413 {
5414 if (code == 0)
5415 output_operand_lossage ("invalid constant - try using "
5416 "an output modifier");
5417 else
5418 output_operand_lossage ("invalid constant for output modifier '%c'",
5419 code);
5420 }
5421 break;
5422
5423 default:
5424 if (code == 0)
5425 output_operand_lossage ("invalid expression - try using "
5426 "an output modifier");
5427 else
5428 output_operand_lossage ("invalid expression for output "
5429 "modifier '%c'", code);
5430 break;
5431 }
5432 }
5433
5434 /* Target hook for assembling integer objects. We need to define it
5435 here to work a round a bug in some versions of GAS, which couldn't
5436 handle values smaller than INT_MIN when printed in decimal. */
5437
5438 static bool
5439 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5440 {
5441 if (size == 8 && aligned_p
5442 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5443 {
5444 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5445 INTVAL (x));
5446 return true;
5447 }
5448 return default_assemble_integer (x, size, aligned_p);
5449 }
5450
5451 /* Returns true if register REGNO is used for forming
5452 a memory address in expression X. */
5453
5454 static bool
5455 reg_used_in_mem_p (int regno, rtx x)
5456 {
5457 enum rtx_code code = GET_CODE (x);
5458 int i, j;
5459 const char *fmt;
5460
5461 if (code == MEM)
5462 {
5463 if (refers_to_regno_p (regno, regno+1,
5464 XEXP (x, 0), 0))
5465 return true;
5466 }
5467 else if (code == SET
5468 && GET_CODE (SET_DEST (x)) == PC)
5469 {
5470 if (refers_to_regno_p (regno, regno+1,
5471 SET_SRC (x), 0))
5472 return true;
5473 }
5474
5475 fmt = GET_RTX_FORMAT (code);
5476 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5477 {
5478 if (fmt[i] == 'e'
5479 && reg_used_in_mem_p (regno, XEXP (x, i)))
5480 return true;
5481
5482 else if (fmt[i] == 'E')
5483 for (j = 0; j < XVECLEN (x, i); j++)
5484 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5485 return true;
5486 }
5487 return false;
5488 }
5489
5490 /* Returns true if expression DEP_RTX sets an address register
5491 used by instruction INSN to address memory. */
5492
5493 static bool
5494 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5495 {
5496 rtx target, pat;
5497
5498 if (GET_CODE (dep_rtx) == INSN)
5499 dep_rtx = PATTERN (dep_rtx);
5500
5501 if (GET_CODE (dep_rtx) == SET)
5502 {
5503 target = SET_DEST (dep_rtx);
5504 if (GET_CODE (target) == STRICT_LOW_PART)
5505 target = XEXP (target, 0);
5506 while (GET_CODE (target) == SUBREG)
5507 target = SUBREG_REG (target);
5508
5509 if (GET_CODE (target) == REG)
5510 {
5511 int regno = REGNO (target);
5512
5513 if (s390_safe_attr_type (insn) == TYPE_LA)
5514 {
5515 pat = PATTERN (insn);
5516 if (GET_CODE (pat) == PARALLEL)
5517 {
5518 gcc_assert (XVECLEN (pat, 0) == 2);
5519 pat = XVECEXP (pat, 0, 0);
5520 }
5521 gcc_assert (GET_CODE (pat) == SET);
5522 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5523 }
5524 else if (get_attr_atype (insn) == ATYPE_AGEN)
5525 return reg_used_in_mem_p (regno, PATTERN (insn));
5526 }
5527 }
5528 return false;
5529 }
5530
5531 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5532
5533 int
5534 s390_agen_dep_p (rtx dep_insn, rtx insn)
5535 {
5536 rtx dep_rtx = PATTERN (dep_insn);
5537 int i;
5538
5539 if (GET_CODE (dep_rtx) == SET
5540 && addr_generation_dependency_p (dep_rtx, insn))
5541 return 1;
5542 else if (GET_CODE (dep_rtx) == PARALLEL)
5543 {
5544 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5545 {
5546 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5547 return 1;
5548 }
5549 }
5550 return 0;
5551 }
5552
5553
5554 /* A C statement (sans semicolon) to update the integer scheduling priority
5555 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5556 reduce the priority to execute INSN later. Do not define this macro if
5557 you do not need to adjust the scheduling priorities of insns.
5558
5559 A STD instruction should be scheduled earlier,
5560 in order to use the bypass. */
5561 static int
5562 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5563 {
5564 if (! INSN_P (insn))
5565 return priority;
5566
5567 if (s390_tune != PROCESSOR_2084_Z990
5568 && s390_tune != PROCESSOR_2094_Z9_109
5569 && s390_tune != PROCESSOR_2097_Z10
5570 && s390_tune != PROCESSOR_2817_Z196)
5571 return priority;
5572
5573 switch (s390_safe_attr_type (insn))
5574 {
5575 case TYPE_FSTOREDF:
5576 case TYPE_FSTORESF:
5577 priority = priority << 3;
5578 break;
5579 case TYPE_STORE:
5580 case TYPE_STM:
5581 priority = priority << 1;
5582 break;
5583 default:
5584 break;
5585 }
5586 return priority;
5587 }
5588
5589
5590 /* The number of instructions that can be issued per cycle. */
5591
5592 static int
5593 s390_issue_rate (void)
5594 {
5595 switch (s390_tune)
5596 {
5597 case PROCESSOR_2084_Z990:
5598 case PROCESSOR_2094_Z9_109:
5599 case PROCESSOR_2817_Z196:
5600 return 3;
5601 case PROCESSOR_2097_Z10:
5602 return 2;
5603 default:
5604 return 1;
5605 }
5606 }
5607
5608 static int
5609 s390_first_cycle_multipass_dfa_lookahead (void)
5610 {
5611 return 4;
5612 }
5613
5614 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5615 Fix up MEMs as required. */
5616
5617 static void
5618 annotate_constant_pool_refs (rtx *x)
5619 {
5620 int i, j;
5621 const char *fmt;
5622
5623 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5624 || !CONSTANT_POOL_ADDRESS_P (*x));
5625
5626 /* Literal pool references can only occur inside a MEM ... */
5627 if (GET_CODE (*x) == MEM)
5628 {
5629 rtx memref = XEXP (*x, 0);
5630
5631 if (GET_CODE (memref) == SYMBOL_REF
5632 && CONSTANT_POOL_ADDRESS_P (memref))
5633 {
5634 rtx base = cfun->machine->base_reg;
5635 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5636 UNSPEC_LTREF);
5637
5638 *x = replace_equiv_address (*x, addr);
5639 return;
5640 }
5641
5642 if (GET_CODE (memref) == CONST
5643 && GET_CODE (XEXP (memref, 0)) == PLUS
5644 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5645 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5646 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5647 {
5648 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5649 rtx sym = XEXP (XEXP (memref, 0), 0);
5650 rtx base = cfun->machine->base_reg;
5651 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5652 UNSPEC_LTREF);
5653
5654 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5655 return;
5656 }
5657 }
5658
5659 /* ... or a load-address type pattern. */
5660 if (GET_CODE (*x) == SET)
5661 {
5662 rtx addrref = SET_SRC (*x);
5663
5664 if (GET_CODE (addrref) == SYMBOL_REF
5665 && CONSTANT_POOL_ADDRESS_P (addrref))
5666 {
5667 rtx base = cfun->machine->base_reg;
5668 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5669 UNSPEC_LTREF);
5670
5671 SET_SRC (*x) = addr;
5672 return;
5673 }
5674
5675 if (GET_CODE (addrref) == CONST
5676 && GET_CODE (XEXP (addrref, 0)) == PLUS
5677 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5678 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5679 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5680 {
5681 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5682 rtx sym = XEXP (XEXP (addrref, 0), 0);
5683 rtx base = cfun->machine->base_reg;
5684 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5685 UNSPEC_LTREF);
5686
5687 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5688 return;
5689 }
5690 }
5691
5692 /* Annotate LTREL_BASE as well. */
5693 if (GET_CODE (*x) == UNSPEC
5694 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5695 {
5696 rtx base = cfun->machine->base_reg;
5697 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5698 UNSPEC_LTREL_BASE);
5699 return;
5700 }
5701
5702 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5703 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5704 {
5705 if (fmt[i] == 'e')
5706 {
5707 annotate_constant_pool_refs (&XEXP (*x, i));
5708 }
5709 else if (fmt[i] == 'E')
5710 {
5711 for (j = 0; j < XVECLEN (*x, i); j++)
5712 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5713 }
5714 }
5715 }
5716
5717 /* Split all branches that exceed the maximum distance.
5718 Returns true if this created a new literal pool entry. */
5719
5720 static int
5721 s390_split_branches (void)
5722 {
5723 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5724 int new_literal = 0, ret;
5725 rtx insn, pat, tmp, target;
5726 rtx *label;
5727
5728 /* We need correct insn addresses. */
5729
5730 shorten_branches (get_insns ());
5731
5732 /* Find all branches that exceed 64KB, and split them. */
5733
5734 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5735 {
5736 if (GET_CODE (insn) != JUMP_INSN)
5737 continue;
5738
5739 pat = PATTERN (insn);
5740 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5741 pat = XVECEXP (pat, 0, 0);
5742 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5743 continue;
5744
5745 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5746 {
5747 label = &SET_SRC (pat);
5748 }
5749 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5750 {
5751 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5752 label = &XEXP (SET_SRC (pat), 1);
5753 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5754 label = &XEXP (SET_SRC (pat), 2);
5755 else
5756 continue;
5757 }
5758 else
5759 continue;
5760
5761 if (get_attr_length (insn) <= 4)
5762 continue;
5763
5764 /* We are going to use the return register as scratch register,
5765 make sure it will be saved/restored by the prologue/epilogue. */
5766 cfun_frame_layout.save_return_addr_p = 1;
5767
5768 if (!flag_pic)
5769 {
5770 new_literal = 1;
5771 tmp = force_const_mem (Pmode, *label);
5772 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5773 INSN_ADDRESSES_NEW (tmp, -1);
5774 annotate_constant_pool_refs (&PATTERN (tmp));
5775
5776 target = temp_reg;
5777 }
5778 else
5779 {
5780 new_literal = 1;
5781 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5782 UNSPEC_LTREL_OFFSET);
5783 target = gen_rtx_CONST (Pmode, target);
5784 target = force_const_mem (Pmode, target);
5785 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5786 INSN_ADDRESSES_NEW (tmp, -1);
5787 annotate_constant_pool_refs (&PATTERN (tmp));
5788
5789 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5790 cfun->machine->base_reg),
5791 UNSPEC_LTREL_BASE);
5792 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5793 }
5794
5795 ret = validate_change (insn, label, target, 0);
5796 gcc_assert (ret);
5797 }
5798
5799 return new_literal;
5800 }
5801
5802
5803 /* Find an annotated literal pool symbol referenced in RTX X,
5804 and store it at REF. Will abort if X contains references to
5805 more than one such pool symbol; multiple references to the same
5806 symbol are allowed, however.
5807
5808 The rtx pointed to by REF must be initialized to NULL_RTX
5809 by the caller before calling this routine. */
5810
5811 static void
5812 find_constant_pool_ref (rtx x, rtx *ref)
5813 {
5814 int i, j;
5815 const char *fmt;
5816
5817 /* Ignore LTREL_BASE references. */
5818 if (GET_CODE (x) == UNSPEC
5819 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5820 return;
5821 /* Likewise POOL_ENTRY insns. */
5822 if (GET_CODE (x) == UNSPEC_VOLATILE
5823 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5824 return;
5825
5826 gcc_assert (GET_CODE (x) != SYMBOL_REF
5827 || !CONSTANT_POOL_ADDRESS_P (x));
5828
5829 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5830 {
5831 rtx sym = XVECEXP (x, 0, 0);
5832 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5833 && CONSTANT_POOL_ADDRESS_P (sym));
5834
5835 if (*ref == NULL_RTX)
5836 *ref = sym;
5837 else
5838 gcc_assert (*ref == sym);
5839
5840 return;
5841 }
5842
5843 fmt = GET_RTX_FORMAT (GET_CODE (x));
5844 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5845 {
5846 if (fmt[i] == 'e')
5847 {
5848 find_constant_pool_ref (XEXP (x, i), ref);
5849 }
5850 else if (fmt[i] == 'E')
5851 {
5852 for (j = 0; j < XVECLEN (x, i); j++)
5853 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5854 }
5855 }
5856 }
5857
5858 /* Replace every reference to the annotated literal pool
5859 symbol REF in X by its base plus OFFSET. */
5860
5861 static void
5862 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5863 {
5864 int i, j;
5865 const char *fmt;
5866
5867 gcc_assert (*x != ref);
5868
5869 if (GET_CODE (*x) == UNSPEC
5870 && XINT (*x, 1) == UNSPEC_LTREF
5871 && XVECEXP (*x, 0, 0) == ref)
5872 {
5873 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5874 return;
5875 }
5876
5877 if (GET_CODE (*x) == PLUS
5878 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5879 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5880 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5881 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5882 {
5883 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5884 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
5885 return;
5886 }
5887
5888 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5889 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5890 {
5891 if (fmt[i] == 'e')
5892 {
5893 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5894 }
5895 else if (fmt[i] == 'E')
5896 {
5897 for (j = 0; j < XVECLEN (*x, i); j++)
5898 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5899 }
5900 }
5901 }
5902
5903 /* Check whether X contains an UNSPEC_LTREL_BASE.
5904 Return its constant pool symbol if found, NULL_RTX otherwise. */
5905
5906 static rtx
5907 find_ltrel_base (rtx x)
5908 {
5909 int i, j;
5910 const char *fmt;
5911
5912 if (GET_CODE (x) == UNSPEC
5913 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5914 return XVECEXP (x, 0, 0);
5915
5916 fmt = GET_RTX_FORMAT (GET_CODE (x));
5917 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5918 {
5919 if (fmt[i] == 'e')
5920 {
5921 rtx fnd = find_ltrel_base (XEXP (x, i));
5922 if (fnd)
5923 return fnd;
5924 }
5925 else if (fmt[i] == 'E')
5926 {
5927 for (j = 0; j < XVECLEN (x, i); j++)
5928 {
5929 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5930 if (fnd)
5931 return fnd;
5932 }
5933 }
5934 }
5935
5936 return NULL_RTX;
5937 }
5938
5939 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5940
5941 static void
5942 replace_ltrel_base (rtx *x)
5943 {
5944 int i, j;
5945 const char *fmt;
5946
5947 if (GET_CODE (*x) == UNSPEC
5948 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5949 {
5950 *x = XVECEXP (*x, 0, 1);
5951 return;
5952 }
5953
5954 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5955 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5956 {
5957 if (fmt[i] == 'e')
5958 {
5959 replace_ltrel_base (&XEXP (*x, i));
5960 }
5961 else if (fmt[i] == 'E')
5962 {
5963 for (j = 0; j < XVECLEN (*x, i); j++)
5964 replace_ltrel_base (&XVECEXP (*x, i, j));
5965 }
5966 }
5967 }
5968
5969
5970 /* We keep a list of constants which we have to add to internal
5971 constant tables in the middle of large functions. */
5972
5973 #define NR_C_MODES 11
5974 enum machine_mode constant_modes[NR_C_MODES] =
5975 {
5976 TFmode, TImode, TDmode,
5977 DFmode, DImode, DDmode,
5978 SFmode, SImode, SDmode,
5979 HImode,
5980 QImode
5981 };
5982
5983 struct constant
5984 {
5985 struct constant *next;
5986 rtx value;
5987 rtx label;
5988 };
5989
5990 struct constant_pool
5991 {
5992 struct constant_pool *next;
5993 rtx first_insn;
5994 rtx pool_insn;
5995 bitmap insns;
5996 rtx emit_pool_after;
5997
5998 struct constant *constants[NR_C_MODES];
5999 struct constant *execute;
6000 rtx label;
6001 int size;
6002 };
6003
6004 /* Allocate new constant_pool structure. */
6005
6006 static struct constant_pool *
6007 s390_alloc_pool (void)
6008 {
6009 struct constant_pool *pool;
6010 int i;
6011
6012 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6013 pool->next = NULL;
6014 for (i = 0; i < NR_C_MODES; i++)
6015 pool->constants[i] = NULL;
6016
6017 pool->execute = NULL;
6018 pool->label = gen_label_rtx ();
6019 pool->first_insn = NULL_RTX;
6020 pool->pool_insn = NULL_RTX;
6021 pool->insns = BITMAP_ALLOC (NULL);
6022 pool->size = 0;
6023 pool->emit_pool_after = NULL_RTX;
6024
6025 return pool;
6026 }
6027
6028 /* Create new constant pool covering instructions starting at INSN
6029 and chain it to the end of POOL_LIST. */
6030
6031 static struct constant_pool *
6032 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6033 {
6034 struct constant_pool *pool, **prev;
6035
6036 pool = s390_alloc_pool ();
6037 pool->first_insn = insn;
6038
6039 for (prev = pool_list; *prev; prev = &(*prev)->next)
6040 ;
6041 *prev = pool;
6042
6043 return pool;
6044 }
6045
6046 /* End range of instructions covered by POOL at INSN and emit
6047 placeholder insn representing the pool. */
6048
6049 static void
6050 s390_end_pool (struct constant_pool *pool, rtx insn)
6051 {
6052 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6053
6054 if (!insn)
6055 insn = get_last_insn ();
6056
6057 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6058 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6059 }
6060
6061 /* Add INSN to the list of insns covered by POOL. */
6062
6063 static void
6064 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6065 {
6066 bitmap_set_bit (pool->insns, INSN_UID (insn));
6067 }
6068
6069 /* Return pool out of POOL_LIST that covers INSN. */
6070
6071 static struct constant_pool *
6072 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6073 {
6074 struct constant_pool *pool;
6075
6076 for (pool = pool_list; pool; pool = pool->next)
6077 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6078 break;
6079
6080 return pool;
6081 }
6082
6083 /* Add constant VAL of mode MODE to the constant pool POOL. */
6084
6085 static void
6086 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6087 {
6088 struct constant *c;
6089 int i;
6090
6091 for (i = 0; i < NR_C_MODES; i++)
6092 if (constant_modes[i] == mode)
6093 break;
6094 gcc_assert (i != NR_C_MODES);
6095
6096 for (c = pool->constants[i]; c != NULL; c = c->next)
6097 if (rtx_equal_p (val, c->value))
6098 break;
6099
6100 if (c == NULL)
6101 {
6102 c = (struct constant *) xmalloc (sizeof *c);
6103 c->value = val;
6104 c->label = gen_label_rtx ();
6105 c->next = pool->constants[i];
6106 pool->constants[i] = c;
6107 pool->size += GET_MODE_SIZE (mode);
6108 }
6109 }
6110
6111 /* Return an rtx that represents the offset of X from the start of
6112 pool POOL. */
6113
6114 static rtx
6115 s390_pool_offset (struct constant_pool *pool, rtx x)
6116 {
6117 rtx label;
6118
6119 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6120 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6121 UNSPEC_POOL_OFFSET);
6122 return gen_rtx_CONST (GET_MODE (x), x);
6123 }
6124
6125 /* Find constant VAL of mode MODE in the constant pool POOL.
6126 Return an RTX describing the distance from the start of
6127 the pool to the location of the new constant. */
6128
6129 static rtx
6130 s390_find_constant (struct constant_pool *pool, rtx val,
6131 enum machine_mode mode)
6132 {
6133 struct constant *c;
6134 int i;
6135
6136 for (i = 0; i < NR_C_MODES; i++)
6137 if (constant_modes[i] == mode)
6138 break;
6139 gcc_assert (i != NR_C_MODES);
6140
6141 for (c = pool->constants[i]; c != NULL; c = c->next)
6142 if (rtx_equal_p (val, c->value))
6143 break;
6144
6145 gcc_assert (c);
6146
6147 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6148 }
6149
6150 /* Check whether INSN is an execute. Return the label_ref to its
6151 execute target template if so, NULL_RTX otherwise. */
6152
6153 static rtx
6154 s390_execute_label (rtx insn)
6155 {
6156 if (GET_CODE (insn) == INSN
6157 && GET_CODE (PATTERN (insn)) == PARALLEL
6158 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6159 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6160 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6161
6162 return NULL_RTX;
6163 }
6164
6165 /* Add execute target for INSN to the constant pool POOL. */
6166
6167 static void
6168 s390_add_execute (struct constant_pool *pool, rtx insn)
6169 {
6170 struct constant *c;
6171
6172 for (c = pool->execute; c != NULL; c = c->next)
6173 if (INSN_UID (insn) == INSN_UID (c->value))
6174 break;
6175
6176 if (c == NULL)
6177 {
6178 c = (struct constant *) xmalloc (sizeof *c);
6179 c->value = insn;
6180 c->label = gen_label_rtx ();
6181 c->next = pool->execute;
6182 pool->execute = c;
6183 pool->size += 6;
6184 }
6185 }
6186
6187 /* Find execute target for INSN in the constant pool POOL.
6188 Return an RTX describing the distance from the start of
6189 the pool to the location of the execute target. */
6190
6191 static rtx
6192 s390_find_execute (struct constant_pool *pool, rtx insn)
6193 {
6194 struct constant *c;
6195
6196 for (c = pool->execute; c != NULL; c = c->next)
6197 if (INSN_UID (insn) == INSN_UID (c->value))
6198 break;
6199
6200 gcc_assert (c);
6201
6202 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6203 }
6204
6205 /* For an execute INSN, extract the execute target template. */
6206
6207 static rtx
6208 s390_execute_target (rtx insn)
6209 {
6210 rtx pattern = PATTERN (insn);
6211 gcc_assert (s390_execute_label (insn));
6212
6213 if (XVECLEN (pattern, 0) == 2)
6214 {
6215 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6216 }
6217 else
6218 {
6219 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6220 int i;
6221
6222 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6223 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6224
6225 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6226 }
6227
6228 return pattern;
6229 }
6230
6231 /* Indicate that INSN cannot be duplicated. This is the case for
6232 execute insns that carry a unique label. */
6233
6234 static bool
6235 s390_cannot_copy_insn_p (rtx insn)
6236 {
6237 rtx label = s390_execute_label (insn);
6238 return label && label != const0_rtx;
6239 }
6240
6241 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6242 do not emit the pool base label. */
6243
6244 static void
6245 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6246 {
6247 struct constant *c;
6248 rtx insn = pool->pool_insn;
6249 int i;
6250
6251 /* Switch to rodata section. */
6252 if (TARGET_CPU_ZARCH)
6253 {
6254 insn = emit_insn_after (gen_pool_section_start (), insn);
6255 INSN_ADDRESSES_NEW (insn, -1);
6256 }
6257
6258 /* Ensure minimum pool alignment. */
6259 if (TARGET_CPU_ZARCH)
6260 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6261 else
6262 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6263 INSN_ADDRESSES_NEW (insn, -1);
6264
6265 /* Emit pool base label. */
6266 if (!remote_label)
6267 {
6268 insn = emit_label_after (pool->label, insn);
6269 INSN_ADDRESSES_NEW (insn, -1);
6270 }
6271
6272 /* Dump constants in descending alignment requirement order,
6273 ensuring proper alignment for every constant. */
6274 for (i = 0; i < NR_C_MODES; i++)
6275 for (c = pool->constants[i]; c; c = c->next)
6276 {
6277 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6278 rtx value = copy_rtx (c->value);
6279 if (GET_CODE (value) == CONST
6280 && GET_CODE (XEXP (value, 0)) == UNSPEC
6281 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6282 && XVECLEN (XEXP (value, 0), 0) == 1)
6283 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6284
6285 insn = emit_label_after (c->label, insn);
6286 INSN_ADDRESSES_NEW (insn, -1);
6287
6288 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6289 gen_rtvec (1, value),
6290 UNSPECV_POOL_ENTRY);
6291 insn = emit_insn_after (value, insn);
6292 INSN_ADDRESSES_NEW (insn, -1);
6293 }
6294
6295 /* Ensure minimum alignment for instructions. */
6296 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6297 INSN_ADDRESSES_NEW (insn, -1);
6298
6299 /* Output in-pool execute template insns. */
6300 for (c = pool->execute; c; c = c->next)
6301 {
6302 insn = emit_label_after (c->label, insn);
6303 INSN_ADDRESSES_NEW (insn, -1);
6304
6305 insn = emit_insn_after (s390_execute_target (c->value), insn);
6306 INSN_ADDRESSES_NEW (insn, -1);
6307 }
6308
6309 /* Switch back to previous section. */
6310 if (TARGET_CPU_ZARCH)
6311 {
6312 insn = emit_insn_after (gen_pool_section_end (), insn);
6313 INSN_ADDRESSES_NEW (insn, -1);
6314 }
6315
6316 insn = emit_barrier_after (insn);
6317 INSN_ADDRESSES_NEW (insn, -1);
6318
6319 /* Remove placeholder insn. */
6320 remove_insn (pool->pool_insn);
6321 }
6322
6323 /* Free all memory used by POOL. */
6324
6325 static void
6326 s390_free_pool (struct constant_pool *pool)
6327 {
6328 struct constant *c, *next;
6329 int i;
6330
6331 for (i = 0; i < NR_C_MODES; i++)
6332 for (c = pool->constants[i]; c; c = next)
6333 {
6334 next = c->next;
6335 free (c);
6336 }
6337
6338 for (c = pool->execute; c; c = next)
6339 {
6340 next = c->next;
6341 free (c);
6342 }
6343
6344 BITMAP_FREE (pool->insns);
6345 free (pool);
6346 }
6347
6348
6349 /* Collect main literal pool. Return NULL on overflow. */
6350
6351 static struct constant_pool *
6352 s390_mainpool_start (void)
6353 {
6354 struct constant_pool *pool;
6355 rtx insn;
6356
6357 pool = s390_alloc_pool ();
6358
6359 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6360 {
6361 if (GET_CODE (insn) == INSN
6362 && GET_CODE (PATTERN (insn)) == SET
6363 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6364 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6365 {
6366 gcc_assert (!pool->pool_insn);
6367 pool->pool_insn = insn;
6368 }
6369
6370 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6371 {
6372 s390_add_execute (pool, insn);
6373 }
6374 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6375 {
6376 rtx pool_ref = NULL_RTX;
6377 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6378 if (pool_ref)
6379 {
6380 rtx constant = get_pool_constant (pool_ref);
6381 enum machine_mode mode = get_pool_mode (pool_ref);
6382 s390_add_constant (pool, constant, mode);
6383 }
6384 }
6385
6386 /* If hot/cold partitioning is enabled we have to make sure that
6387 the literal pool is emitted in the same section where the
6388 initialization of the literal pool base pointer takes place.
6389 emit_pool_after is only used in the non-overflow case on non
6390 Z cpus where we can emit the literal pool at the end of the
6391 function body within the text section. */
6392 if (NOTE_P (insn)
6393 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6394 && !pool->emit_pool_after)
6395 pool->emit_pool_after = PREV_INSN (insn);
6396 }
6397
6398 gcc_assert (pool->pool_insn || pool->size == 0);
6399
6400 if (pool->size >= 4096)
6401 {
6402 /* We're going to chunkify the pool, so remove the main
6403 pool placeholder insn. */
6404 remove_insn (pool->pool_insn);
6405
6406 s390_free_pool (pool);
6407 pool = NULL;
6408 }
6409
6410 /* If the functions ends with the section where the literal pool
6411 should be emitted set the marker to its end. */
6412 if (pool && !pool->emit_pool_after)
6413 pool->emit_pool_after = get_last_insn ();
6414
6415 return pool;
6416 }
6417
6418 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6419 Modify the current function to output the pool constants as well as
6420 the pool register setup instruction. */
6421
6422 static void
6423 s390_mainpool_finish (struct constant_pool *pool)
6424 {
6425 rtx base_reg = cfun->machine->base_reg;
6426 rtx insn;
6427
6428 /* If the pool is empty, we're done. */
6429 if (pool->size == 0)
6430 {
6431 /* We don't actually need a base register after all. */
6432 cfun->machine->base_reg = NULL_RTX;
6433
6434 if (pool->pool_insn)
6435 remove_insn (pool->pool_insn);
6436 s390_free_pool (pool);
6437 return;
6438 }
6439
6440 /* We need correct insn addresses. */
6441 shorten_branches (get_insns ());
6442
6443 /* On zSeries, we use a LARL to load the pool register. The pool is
6444 located in the .rodata section, so we emit it after the function. */
6445 if (TARGET_CPU_ZARCH)
6446 {
6447 insn = gen_main_base_64 (base_reg, pool->label);
6448 insn = emit_insn_after (insn, pool->pool_insn);
6449 INSN_ADDRESSES_NEW (insn, -1);
6450 remove_insn (pool->pool_insn);
6451
6452 insn = get_last_insn ();
6453 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6454 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6455
6456 s390_dump_pool (pool, 0);
6457 }
6458
6459 /* On S/390, if the total size of the function's code plus literal pool
6460 does not exceed 4096 bytes, we use BASR to set up a function base
6461 pointer, and emit the literal pool at the end of the function. */
6462 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6463 + pool->size + 8 /* alignment slop */ < 4096)
6464 {
6465 insn = gen_main_base_31_small (base_reg, pool->label);
6466 insn = emit_insn_after (insn, pool->pool_insn);
6467 INSN_ADDRESSES_NEW (insn, -1);
6468 remove_insn (pool->pool_insn);
6469
6470 insn = emit_label_after (pool->label, insn);
6471 INSN_ADDRESSES_NEW (insn, -1);
6472
6473 /* emit_pool_after will be set by s390_mainpool_start to the
6474 last insn of the section where the literal pool should be
6475 emitted. */
6476 insn = pool->emit_pool_after;
6477
6478 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6479 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6480
6481 s390_dump_pool (pool, 1);
6482 }
6483
6484 /* Otherwise, we emit an inline literal pool and use BASR to branch
6485 over it, setting up the pool register at the same time. */
6486 else
6487 {
6488 rtx pool_end = gen_label_rtx ();
6489
6490 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6491 insn = emit_jump_insn_after (insn, pool->pool_insn);
6492 JUMP_LABEL (insn) = pool_end;
6493 INSN_ADDRESSES_NEW (insn, -1);
6494 remove_insn (pool->pool_insn);
6495
6496 insn = emit_label_after (pool->label, insn);
6497 INSN_ADDRESSES_NEW (insn, -1);
6498
6499 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6500 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6501
6502 insn = emit_label_after (pool_end, pool->pool_insn);
6503 INSN_ADDRESSES_NEW (insn, -1);
6504
6505 s390_dump_pool (pool, 1);
6506 }
6507
6508
6509 /* Replace all literal pool references. */
6510
6511 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6512 {
6513 if (INSN_P (insn))
6514 replace_ltrel_base (&PATTERN (insn));
6515
6516 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6517 {
6518 rtx addr, pool_ref = NULL_RTX;
6519 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6520 if (pool_ref)
6521 {
6522 if (s390_execute_label (insn))
6523 addr = s390_find_execute (pool, insn);
6524 else
6525 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6526 get_pool_mode (pool_ref));
6527
6528 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6529 INSN_CODE (insn) = -1;
6530 }
6531 }
6532 }
6533
6534
6535 /* Free the pool. */
6536 s390_free_pool (pool);
6537 }
6538
6539 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6540 We have decided we cannot use this pool, so revert all changes
6541 to the current function that were done by s390_mainpool_start. */
6542 static void
6543 s390_mainpool_cancel (struct constant_pool *pool)
6544 {
6545 /* We didn't actually change the instruction stream, so simply
6546 free the pool memory. */
6547 s390_free_pool (pool);
6548 }
6549
6550
6551 /* Chunkify the literal pool. */
6552
6553 #define S390_POOL_CHUNK_MIN 0xc00
6554 #define S390_POOL_CHUNK_MAX 0xe00
6555
6556 static struct constant_pool *
6557 s390_chunkify_start (void)
6558 {
6559 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6560 int extra_size = 0;
6561 bitmap far_labels;
6562 rtx pending_ltrel = NULL_RTX;
6563 rtx insn;
6564
6565 rtx (*gen_reload_base) (rtx, rtx) =
6566 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6567
6568
6569 /* We need correct insn addresses. */
6570
6571 shorten_branches (get_insns ());
6572
6573 /* Scan all insns and move literals to pool chunks. */
6574
6575 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6576 {
6577 bool section_switch_p = false;
6578
6579 /* Check for pending LTREL_BASE. */
6580 if (INSN_P (insn))
6581 {
6582 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6583 if (ltrel_base)
6584 {
6585 gcc_assert (ltrel_base == pending_ltrel);
6586 pending_ltrel = NULL_RTX;
6587 }
6588 }
6589
6590 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6591 {
6592 if (!curr_pool)
6593 curr_pool = s390_start_pool (&pool_list, insn);
6594
6595 s390_add_execute (curr_pool, insn);
6596 s390_add_pool_insn (curr_pool, insn);
6597 }
6598 else if (GET_CODE (insn) == INSN || CALL_P (insn))
6599 {
6600 rtx pool_ref = NULL_RTX;
6601 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6602 if (pool_ref)
6603 {
6604 rtx constant = get_pool_constant (pool_ref);
6605 enum machine_mode mode = get_pool_mode (pool_ref);
6606
6607 if (!curr_pool)
6608 curr_pool = s390_start_pool (&pool_list, insn);
6609
6610 s390_add_constant (curr_pool, constant, mode);
6611 s390_add_pool_insn (curr_pool, insn);
6612
6613 /* Don't split the pool chunk between a LTREL_OFFSET load
6614 and the corresponding LTREL_BASE. */
6615 if (GET_CODE (constant) == CONST
6616 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6617 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6618 {
6619 gcc_assert (!pending_ltrel);
6620 pending_ltrel = pool_ref;
6621 }
6622 }
6623 }
6624
6625 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6626 {
6627 if (curr_pool)
6628 s390_add_pool_insn (curr_pool, insn);
6629 /* An LTREL_BASE must follow within the same basic block. */
6630 gcc_assert (!pending_ltrel);
6631 }
6632
6633 if (NOTE_P (insn))
6634 switch (NOTE_KIND (insn))
6635 {
6636 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6637 section_switch_p = true;
6638 break;
6639 case NOTE_INSN_VAR_LOCATION:
6640 case NOTE_INSN_CALL_ARG_LOCATION:
6641 continue;
6642 default:
6643 break;
6644 }
6645
6646 if (!curr_pool
6647 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6648 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6649 continue;
6650
6651 if (TARGET_CPU_ZARCH)
6652 {
6653 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6654 continue;
6655
6656 s390_end_pool (curr_pool, NULL_RTX);
6657 curr_pool = NULL;
6658 }
6659 else
6660 {
6661 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6662 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6663 + extra_size;
6664
6665 /* We will later have to insert base register reload insns.
6666 Those will have an effect on code size, which we need to
6667 consider here. This calculation makes rather pessimistic
6668 worst-case assumptions. */
6669 if (GET_CODE (insn) == CODE_LABEL)
6670 extra_size += 6;
6671
6672 if (chunk_size < S390_POOL_CHUNK_MIN
6673 && curr_pool->size < S390_POOL_CHUNK_MIN
6674 && !section_switch_p)
6675 continue;
6676
6677 /* Pool chunks can only be inserted after BARRIERs ... */
6678 if (GET_CODE (insn) == BARRIER)
6679 {
6680 s390_end_pool (curr_pool, insn);
6681 curr_pool = NULL;
6682 extra_size = 0;
6683 }
6684
6685 /* ... so if we don't find one in time, create one. */
6686 else if (chunk_size > S390_POOL_CHUNK_MAX
6687 || curr_pool->size > S390_POOL_CHUNK_MAX
6688 || section_switch_p)
6689 {
6690 rtx label, jump, barrier, next, prev;
6691
6692 if (!section_switch_p)
6693 {
6694 /* We can insert the barrier only after a 'real' insn. */
6695 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6696 continue;
6697 if (get_attr_length (insn) == 0)
6698 continue;
6699 /* Don't separate LTREL_BASE from the corresponding
6700 LTREL_OFFSET load. */
6701 if (pending_ltrel)
6702 continue;
6703 next = insn;
6704 do
6705 {
6706 insn = next;
6707 next = NEXT_INSN (insn);
6708 }
6709 while (next
6710 && NOTE_P (next)
6711 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6712 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6713 }
6714 else
6715 {
6716 gcc_assert (!pending_ltrel);
6717
6718 /* The old pool has to end before the section switch
6719 note in order to make it part of the current
6720 section. */
6721 insn = PREV_INSN (insn);
6722 }
6723
6724 label = gen_label_rtx ();
6725 prev = insn;
6726 if (prev && NOTE_P (prev))
6727 prev = prev_nonnote_insn (prev);
6728 if (prev)
6729 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
6730 INSN_LOCATOR (prev));
6731 else
6732 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
6733 barrier = emit_barrier_after (jump);
6734 insn = emit_label_after (label, barrier);
6735 JUMP_LABEL (jump) = label;
6736 LABEL_NUSES (label) = 1;
6737
6738 INSN_ADDRESSES_NEW (jump, -1);
6739 INSN_ADDRESSES_NEW (barrier, -1);
6740 INSN_ADDRESSES_NEW (insn, -1);
6741
6742 s390_end_pool (curr_pool, barrier);
6743 curr_pool = NULL;
6744 extra_size = 0;
6745 }
6746 }
6747 }
6748
6749 if (curr_pool)
6750 s390_end_pool (curr_pool, NULL_RTX);
6751 gcc_assert (!pending_ltrel);
6752
6753 /* Find all labels that are branched into
6754 from an insn belonging to a different chunk. */
6755
6756 far_labels = BITMAP_ALLOC (NULL);
6757
6758 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6759 {
6760 /* Labels marked with LABEL_PRESERVE_P can be target
6761 of non-local jumps, so we have to mark them.
6762 The same holds for named labels.
6763
6764 Don't do that, however, if it is the label before
6765 a jump table. */
6766
6767 if (GET_CODE (insn) == CODE_LABEL
6768 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6769 {
6770 rtx vec_insn = next_real_insn (insn);
6771 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6772 PATTERN (vec_insn) : NULL_RTX;
6773 if (!vec_pat
6774 || !(GET_CODE (vec_pat) == ADDR_VEC
6775 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6776 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6777 }
6778
6779 /* If we have a direct jump (conditional or unconditional)
6780 or a casesi jump, check all potential targets. */
6781 else if (GET_CODE (insn) == JUMP_INSN)
6782 {
6783 rtx pat = PATTERN (insn);
6784 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6785 pat = XVECEXP (pat, 0, 0);
6786
6787 if (GET_CODE (pat) == SET)
6788 {
6789 rtx label = JUMP_LABEL (insn);
6790 if (label)
6791 {
6792 if (s390_find_pool (pool_list, label)
6793 != s390_find_pool (pool_list, insn))
6794 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6795 }
6796 }
6797 else if (GET_CODE (pat) == PARALLEL
6798 && XVECLEN (pat, 0) == 2
6799 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6800 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6801 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6802 {
6803 /* Find the jump table used by this casesi jump. */
6804 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6805 rtx vec_insn = next_real_insn (vec_label);
6806 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6807 PATTERN (vec_insn) : NULL_RTX;
6808 if (vec_pat
6809 && (GET_CODE (vec_pat) == ADDR_VEC
6810 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6811 {
6812 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6813
6814 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6815 {
6816 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6817
6818 if (s390_find_pool (pool_list, label)
6819 != s390_find_pool (pool_list, insn))
6820 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6821 }
6822 }
6823 }
6824 }
6825 }
6826
6827 /* Insert base register reload insns before every pool. */
6828
6829 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6830 {
6831 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6832 curr_pool->label);
6833 rtx insn = curr_pool->first_insn;
6834 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6835 }
6836
6837 /* Insert base register reload insns at every far label. */
6838
6839 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6840 if (GET_CODE (insn) == CODE_LABEL
6841 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6842 {
6843 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6844 if (pool)
6845 {
6846 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6847 pool->label);
6848 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6849 }
6850 }
6851
6852
6853 BITMAP_FREE (far_labels);
6854
6855
6856 /* Recompute insn addresses. */
6857
6858 init_insn_lengths ();
6859 shorten_branches (get_insns ());
6860
6861 return pool_list;
6862 }
6863
6864 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6865 After we have decided to use this list, finish implementing
6866 all changes to the current function as required. */
6867
6868 static void
6869 s390_chunkify_finish (struct constant_pool *pool_list)
6870 {
6871 struct constant_pool *curr_pool = NULL;
6872 rtx insn;
6873
6874
6875 /* Replace all literal pool references. */
6876
6877 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6878 {
6879 if (INSN_P (insn))
6880 replace_ltrel_base (&PATTERN (insn));
6881
6882 curr_pool = s390_find_pool (pool_list, insn);
6883 if (!curr_pool)
6884 continue;
6885
6886 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6887 {
6888 rtx addr, pool_ref = NULL_RTX;
6889 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6890 if (pool_ref)
6891 {
6892 if (s390_execute_label (insn))
6893 addr = s390_find_execute (curr_pool, insn);
6894 else
6895 addr = s390_find_constant (curr_pool,
6896 get_pool_constant (pool_ref),
6897 get_pool_mode (pool_ref));
6898
6899 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6900 INSN_CODE (insn) = -1;
6901 }
6902 }
6903 }
6904
6905 /* Dump out all literal pools. */
6906
6907 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6908 s390_dump_pool (curr_pool, 0);
6909
6910 /* Free pool list. */
6911
6912 while (pool_list)
6913 {
6914 struct constant_pool *next = pool_list->next;
6915 s390_free_pool (pool_list);
6916 pool_list = next;
6917 }
6918 }
6919
6920 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6921 We have decided we cannot use this list, so revert all changes
6922 to the current function that were done by s390_chunkify_start. */
6923
6924 static void
6925 s390_chunkify_cancel (struct constant_pool *pool_list)
6926 {
6927 struct constant_pool *curr_pool = NULL;
6928 rtx insn;
6929
6930 /* Remove all pool placeholder insns. */
6931
6932 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6933 {
6934 /* Did we insert an extra barrier? Remove it. */
6935 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6936 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6937 rtx label = NEXT_INSN (curr_pool->pool_insn);
6938
6939 if (jump && GET_CODE (jump) == JUMP_INSN
6940 && barrier && GET_CODE (barrier) == BARRIER
6941 && label && GET_CODE (label) == CODE_LABEL
6942 && GET_CODE (PATTERN (jump)) == SET
6943 && SET_DEST (PATTERN (jump)) == pc_rtx
6944 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6945 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6946 {
6947 remove_insn (jump);
6948 remove_insn (barrier);
6949 remove_insn (label);
6950 }
6951
6952 remove_insn (curr_pool->pool_insn);
6953 }
6954
6955 /* Remove all base register reload insns. */
6956
6957 for (insn = get_insns (); insn; )
6958 {
6959 rtx next_insn = NEXT_INSN (insn);
6960
6961 if (GET_CODE (insn) == INSN
6962 && GET_CODE (PATTERN (insn)) == SET
6963 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6964 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6965 remove_insn (insn);
6966
6967 insn = next_insn;
6968 }
6969
6970 /* Free pool list. */
6971
6972 while (pool_list)
6973 {
6974 struct constant_pool *next = pool_list->next;
6975 s390_free_pool (pool_list);
6976 pool_list = next;
6977 }
6978 }
6979
6980 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6981
6982 void
6983 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6984 {
6985 REAL_VALUE_TYPE r;
6986
6987 switch (GET_MODE_CLASS (mode))
6988 {
6989 case MODE_FLOAT:
6990 case MODE_DECIMAL_FLOAT:
6991 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6992
6993 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6994 assemble_real (r, mode, align);
6995 break;
6996
6997 case MODE_INT:
6998 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6999 mark_symbol_refs_as_used (exp);
7000 break;
7001
7002 default:
7003 gcc_unreachable ();
7004 }
7005 }
7006
7007
7008 /* Return an RTL expression representing the value of the return address
7009 for the frame COUNT steps up from the current frame. FRAME is the
7010 frame pointer of that frame. */
7011
7012 rtx
7013 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7014 {
7015 int offset;
7016 rtx addr;
7017
7018 /* Without backchain, we fail for all but the current frame. */
7019
7020 if (!TARGET_BACKCHAIN && count > 0)
7021 return NULL_RTX;
7022
7023 /* For the current frame, we need to make sure the initial
7024 value of RETURN_REGNUM is actually saved. */
7025
7026 if (count == 0)
7027 {
7028 /* On non-z architectures branch splitting could overwrite r14. */
7029 if (TARGET_CPU_ZARCH)
7030 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7031 else
7032 {
7033 cfun_frame_layout.save_return_addr_p = true;
7034 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7035 }
7036 }
7037
7038 if (TARGET_PACKED_STACK)
7039 offset = -2 * UNITS_PER_LONG;
7040 else
7041 offset = RETURN_REGNUM * UNITS_PER_LONG;
7042
7043 addr = plus_constant (Pmode, frame, offset);
7044 addr = memory_address (Pmode, addr);
7045 return gen_rtx_MEM (Pmode, addr);
7046 }
7047
7048 /* Return an RTL expression representing the back chain stored in
7049 the current stack frame. */
7050
7051 rtx
7052 s390_back_chain_rtx (void)
7053 {
7054 rtx chain;
7055
7056 gcc_assert (TARGET_BACKCHAIN);
7057
7058 if (TARGET_PACKED_STACK)
7059 chain = plus_constant (Pmode, stack_pointer_rtx,
7060 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7061 else
7062 chain = stack_pointer_rtx;
7063
7064 chain = gen_rtx_MEM (Pmode, chain);
7065 return chain;
7066 }
7067
7068 /* Find first call clobbered register unused in a function.
7069 This could be used as base register in a leaf function
7070 or for holding the return address before epilogue. */
7071
7072 static int
7073 find_unused_clobbered_reg (void)
7074 {
7075 int i;
7076 for (i = 0; i < 6; i++)
7077 if (!df_regs_ever_live_p (i))
7078 return i;
7079 return 0;
7080 }
7081
7082
7083 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7084 clobbered hard regs in SETREG. */
7085
7086 static void
7087 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7088 {
7089 int *regs_ever_clobbered = (int *)data;
7090 unsigned int i, regno;
7091 enum machine_mode mode = GET_MODE (setreg);
7092
7093 if (GET_CODE (setreg) == SUBREG)
7094 {
7095 rtx inner = SUBREG_REG (setreg);
7096 if (!GENERAL_REG_P (inner))
7097 return;
7098 regno = subreg_regno (setreg);
7099 }
7100 else if (GENERAL_REG_P (setreg))
7101 regno = REGNO (setreg);
7102 else
7103 return;
7104
7105 for (i = regno;
7106 i < regno + HARD_REGNO_NREGS (regno, mode);
7107 i++)
7108 regs_ever_clobbered[i] = 1;
7109 }
7110
7111 /* Walks through all basic blocks of the current function looking
7112 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7113 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7114 each of those regs. */
7115
7116 static void
7117 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7118 {
7119 basic_block cur_bb;
7120 rtx cur_insn;
7121 unsigned int i;
7122
7123 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7124
7125 /* For non-leaf functions we have to consider all call clobbered regs to be
7126 clobbered. */
7127 if (!current_function_is_leaf)
7128 {
7129 for (i = 0; i < 16; i++)
7130 regs_ever_clobbered[i] = call_really_used_regs[i];
7131 }
7132
7133 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7134 this work is done by liveness analysis (mark_regs_live_at_end).
7135 Special care is needed for functions containing landing pads. Landing pads
7136 may use the eh registers, but the code which sets these registers is not
7137 contained in that function. Hence s390_regs_ever_clobbered is not able to
7138 deal with this automatically. */
7139 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7140 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7141 if (crtl->calls_eh_return
7142 || (cfun->machine->has_landing_pad_p
7143 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7144 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7145
7146 /* For nonlocal gotos all call-saved registers have to be saved.
7147 This flag is also set for the unwinding code in libgcc.
7148 See expand_builtin_unwind_init. For regs_ever_live this is done by
7149 reload. */
7150 if (cfun->has_nonlocal_label)
7151 for (i = 0; i < 16; i++)
7152 if (!call_really_used_regs[i])
7153 regs_ever_clobbered[i] = 1;
7154
7155 FOR_EACH_BB (cur_bb)
7156 {
7157 FOR_BB_INSNS (cur_bb, cur_insn)
7158 {
7159 if (INSN_P (cur_insn))
7160 note_stores (PATTERN (cur_insn),
7161 s390_reg_clobbered_rtx,
7162 regs_ever_clobbered);
7163 }
7164 }
7165 }
7166
7167 /* Determine the frame area which actually has to be accessed
7168 in the function epilogue. The values are stored at the
7169 given pointers AREA_BOTTOM (address of the lowest used stack
7170 address) and AREA_TOP (address of the first item which does
7171 not belong to the stack frame). */
7172
7173 static void
7174 s390_frame_area (int *area_bottom, int *area_top)
7175 {
7176 int b, t;
7177 int i;
7178
7179 b = INT_MAX;
7180 t = INT_MIN;
7181
7182 if (cfun_frame_layout.first_restore_gpr != -1)
7183 {
7184 b = (cfun_frame_layout.gprs_offset
7185 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7186 t = b + (cfun_frame_layout.last_restore_gpr
7187 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7188 }
7189
7190 if (TARGET_64BIT && cfun_save_high_fprs_p)
7191 {
7192 b = MIN (b, cfun_frame_layout.f8_offset);
7193 t = MAX (t, (cfun_frame_layout.f8_offset
7194 + cfun_frame_layout.high_fprs * 8));
7195 }
7196
7197 if (!TARGET_64BIT)
7198 for (i = 2; i < 4; i++)
7199 if (cfun_fpr_bit_p (i))
7200 {
7201 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7202 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7203 }
7204
7205 *area_bottom = b;
7206 *area_top = t;
7207 }
7208
7209 /* Fill cfun->machine with info about register usage of current function.
7210 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7211
7212 static void
7213 s390_register_info (int clobbered_regs[])
7214 {
7215 int i, j;
7216
7217 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7218 cfun_frame_layout.fpr_bitmap = 0;
7219 cfun_frame_layout.high_fprs = 0;
7220 if (TARGET_64BIT)
7221 for (i = 24; i < 32; i++)
7222 if (df_regs_ever_live_p (i) && !global_regs[i])
7223 {
7224 cfun_set_fpr_bit (i - 16);
7225 cfun_frame_layout.high_fprs++;
7226 }
7227
7228 /* Find first and last gpr to be saved. We trust regs_ever_live
7229 data, except that we don't save and restore global registers.
7230
7231 Also, all registers with special meaning to the compiler need
7232 to be handled extra. */
7233
7234 s390_regs_ever_clobbered (clobbered_regs);
7235
7236 for (i = 0; i < 16; i++)
7237 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7238
7239 if (frame_pointer_needed)
7240 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7241
7242 if (flag_pic)
7243 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7244 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7245
7246 clobbered_regs[BASE_REGNUM]
7247 |= (cfun->machine->base_reg
7248 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7249
7250 clobbered_regs[RETURN_REGNUM]
7251 |= (!current_function_is_leaf
7252 || TARGET_TPF_PROFILING
7253 || cfun->machine->split_branches_pending_p
7254 || cfun_frame_layout.save_return_addr_p
7255 || crtl->calls_eh_return
7256 || cfun->stdarg);
7257
7258 clobbered_regs[STACK_POINTER_REGNUM]
7259 |= (!current_function_is_leaf
7260 || TARGET_TPF_PROFILING
7261 || cfun_save_high_fprs_p
7262 || get_frame_size () > 0
7263 || cfun->calls_alloca
7264 || cfun->stdarg);
7265
7266 for (i = 6; i < 16; i++)
7267 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7268 break;
7269 for (j = 15; j > i; j--)
7270 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7271 break;
7272
7273 if (i == 16)
7274 {
7275 /* Nothing to save/restore. */
7276 cfun_frame_layout.first_save_gpr_slot = -1;
7277 cfun_frame_layout.last_save_gpr_slot = -1;
7278 cfun_frame_layout.first_save_gpr = -1;
7279 cfun_frame_layout.first_restore_gpr = -1;
7280 cfun_frame_layout.last_save_gpr = -1;
7281 cfun_frame_layout.last_restore_gpr = -1;
7282 }
7283 else
7284 {
7285 /* Save slots for gprs from i to j. */
7286 cfun_frame_layout.first_save_gpr_slot = i;
7287 cfun_frame_layout.last_save_gpr_slot = j;
7288
7289 for (i = cfun_frame_layout.first_save_gpr_slot;
7290 i < cfun_frame_layout.last_save_gpr_slot + 1;
7291 i++)
7292 if (clobbered_regs[i])
7293 break;
7294
7295 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7296 if (clobbered_regs[j])
7297 break;
7298
7299 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7300 {
7301 /* Nothing to save/restore. */
7302 cfun_frame_layout.first_save_gpr = -1;
7303 cfun_frame_layout.first_restore_gpr = -1;
7304 cfun_frame_layout.last_save_gpr = -1;
7305 cfun_frame_layout.last_restore_gpr = -1;
7306 }
7307 else
7308 {
7309 /* Save / Restore from gpr i to j. */
7310 cfun_frame_layout.first_save_gpr = i;
7311 cfun_frame_layout.first_restore_gpr = i;
7312 cfun_frame_layout.last_save_gpr = j;
7313 cfun_frame_layout.last_restore_gpr = j;
7314 }
7315 }
7316
7317 if (cfun->stdarg)
7318 {
7319 /* Varargs functions need to save gprs 2 to 6. */
7320 if (cfun->va_list_gpr_size
7321 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7322 {
7323 int min_gpr = crtl->args.info.gprs;
7324 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7325 if (max_gpr > GP_ARG_NUM_REG)
7326 max_gpr = GP_ARG_NUM_REG;
7327
7328 if (cfun_frame_layout.first_save_gpr == -1
7329 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7330 {
7331 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7332 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7333 }
7334
7335 if (cfun_frame_layout.last_save_gpr == -1
7336 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7337 {
7338 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7339 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7340 }
7341 }
7342
7343 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7344 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7345 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7346 {
7347 int min_fpr = crtl->args.info.fprs;
7348 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7349 if (max_fpr > FP_ARG_NUM_REG)
7350 max_fpr = FP_ARG_NUM_REG;
7351
7352 /* ??? This is currently required to ensure proper location
7353 of the fpr save slots within the va_list save area. */
7354 if (TARGET_PACKED_STACK)
7355 min_fpr = 0;
7356
7357 for (i = min_fpr; i < max_fpr; i++)
7358 cfun_set_fpr_bit (i);
7359 }
7360 }
7361
7362 if (!TARGET_64BIT)
7363 for (i = 2; i < 4; i++)
7364 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7365 cfun_set_fpr_bit (i);
7366 }
7367
7368 /* Fill cfun->machine with info about frame of current function. */
7369
7370 static void
7371 s390_frame_info (void)
7372 {
7373 int i;
7374
7375 cfun_frame_layout.frame_size = get_frame_size ();
7376 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7377 fatal_error ("total size of local variables exceeds architecture limit");
7378
7379 if (!TARGET_PACKED_STACK)
7380 {
7381 cfun_frame_layout.backchain_offset = 0;
7382 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7383 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7384 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7385 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7386 * UNITS_PER_LONG);
7387 }
7388 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7389 {
7390 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7391 - UNITS_PER_LONG);
7392 cfun_frame_layout.gprs_offset
7393 = (cfun_frame_layout.backchain_offset
7394 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7395 * UNITS_PER_LONG);
7396
7397 if (TARGET_64BIT)
7398 {
7399 cfun_frame_layout.f4_offset
7400 = (cfun_frame_layout.gprs_offset
7401 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7402
7403 cfun_frame_layout.f0_offset
7404 = (cfun_frame_layout.f4_offset
7405 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7406 }
7407 else
7408 {
7409 /* On 31 bit we have to care about alignment of the
7410 floating point regs to provide fastest access. */
7411 cfun_frame_layout.f0_offset
7412 = ((cfun_frame_layout.gprs_offset
7413 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7414 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7415
7416 cfun_frame_layout.f4_offset
7417 = (cfun_frame_layout.f0_offset
7418 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7419 }
7420 }
7421 else /* no backchain */
7422 {
7423 cfun_frame_layout.f4_offset
7424 = (STACK_POINTER_OFFSET
7425 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7426
7427 cfun_frame_layout.f0_offset
7428 = (cfun_frame_layout.f4_offset
7429 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7430
7431 cfun_frame_layout.gprs_offset
7432 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7433 }
7434
7435 if (current_function_is_leaf
7436 && !TARGET_TPF_PROFILING
7437 && cfun_frame_layout.frame_size == 0
7438 && !cfun_save_high_fprs_p
7439 && !cfun->calls_alloca
7440 && !cfun->stdarg)
7441 return;
7442
7443 if (!TARGET_PACKED_STACK)
7444 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7445 + crtl->outgoing_args_size
7446 + cfun_frame_layout.high_fprs * 8);
7447 else
7448 {
7449 if (TARGET_BACKCHAIN)
7450 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7451
7452 /* No alignment trouble here because f8-f15 are only saved under
7453 64 bit. */
7454 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7455 cfun_frame_layout.f4_offset),
7456 cfun_frame_layout.gprs_offset)
7457 - cfun_frame_layout.high_fprs * 8);
7458
7459 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7460
7461 for (i = 0; i < 8; i++)
7462 if (cfun_fpr_bit_p (i))
7463 cfun_frame_layout.frame_size += 8;
7464
7465 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7466
7467 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7468 the frame size to sustain 8 byte alignment of stack frames. */
7469 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7470 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7471 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7472
7473 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7474 }
7475 }
7476
7477 /* Generate frame layout. Fills in register and frame data for the current
7478 function in cfun->machine. This routine can be called multiple times;
7479 it will re-do the complete frame layout every time. */
7480
7481 static void
7482 s390_init_frame_layout (void)
7483 {
7484 HOST_WIDE_INT frame_size;
7485 int base_used;
7486 int clobbered_regs[16];
7487
7488 /* On S/390 machines, we may need to perform branch splitting, which
7489 will require both base and return address register. We have no
7490 choice but to assume we're going to need them until right at the
7491 end of the machine dependent reorg phase. */
7492 if (!TARGET_CPU_ZARCH)
7493 cfun->machine->split_branches_pending_p = true;
7494
7495 do
7496 {
7497 frame_size = cfun_frame_layout.frame_size;
7498
7499 /* Try to predict whether we'll need the base register. */
7500 base_used = cfun->machine->split_branches_pending_p
7501 || crtl->uses_const_pool
7502 || (!DISP_IN_RANGE (frame_size)
7503 && !CONST_OK_FOR_K (frame_size));
7504
7505 /* Decide which register to use as literal pool base. In small
7506 leaf functions, try to use an unused call-clobbered register
7507 as base register to avoid save/restore overhead. */
7508 if (!base_used)
7509 cfun->machine->base_reg = NULL_RTX;
7510 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7511 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7512 else
7513 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7514
7515 s390_register_info (clobbered_regs);
7516 s390_frame_info ();
7517 }
7518 while (frame_size != cfun_frame_layout.frame_size);
7519 }
7520
7521 /* Update frame layout. Recompute actual register save data based on
7522 current info and update regs_ever_live for the special registers.
7523 May be called multiple times, but may never cause *more* registers
7524 to be saved than s390_init_frame_layout allocated room for. */
7525
7526 static void
7527 s390_update_frame_layout (void)
7528 {
7529 int clobbered_regs[16];
7530
7531 s390_register_info (clobbered_regs);
7532
7533 df_set_regs_ever_live (BASE_REGNUM,
7534 clobbered_regs[BASE_REGNUM] ? true : false);
7535 df_set_regs_ever_live (RETURN_REGNUM,
7536 clobbered_regs[RETURN_REGNUM] ? true : false);
7537 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7538 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7539
7540 if (cfun->machine->base_reg)
7541 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7542 }
7543
7544 /* Return true if it is legal to put a value with MODE into REGNO. */
7545
7546 bool
7547 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7548 {
7549 switch (REGNO_REG_CLASS (regno))
7550 {
7551 case FP_REGS:
7552 if (REGNO_PAIR_OK (regno, mode))
7553 {
7554 if (mode == SImode || mode == DImode)
7555 return true;
7556
7557 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7558 return true;
7559 }
7560 break;
7561 case ADDR_REGS:
7562 if (FRAME_REGNO_P (regno) && mode == Pmode)
7563 return true;
7564
7565 /* fallthrough */
7566 case GENERAL_REGS:
7567 if (REGNO_PAIR_OK (regno, mode))
7568 {
7569 if (TARGET_ZARCH
7570 || (mode != TFmode && mode != TCmode && mode != TDmode))
7571 return true;
7572 }
7573 break;
7574 case CC_REGS:
7575 if (GET_MODE_CLASS (mode) == MODE_CC)
7576 return true;
7577 break;
7578 case ACCESS_REGS:
7579 if (REGNO_PAIR_OK (regno, mode))
7580 {
7581 if (mode == SImode || mode == Pmode)
7582 return true;
7583 }
7584 break;
7585 default:
7586 return false;
7587 }
7588
7589 return false;
7590 }
7591
7592 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7593
7594 bool
7595 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7596 {
7597 /* Once we've decided upon a register to use as base register, it must
7598 no longer be used for any other purpose. */
7599 if (cfun->machine->base_reg)
7600 if (REGNO (cfun->machine->base_reg) == old_reg
7601 || REGNO (cfun->machine->base_reg) == new_reg)
7602 return false;
7603
7604 return true;
7605 }
7606
7607 /* Maximum number of registers to represent a value of mode MODE
7608 in a register of class RCLASS. */
7609
7610 int
7611 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7612 {
7613 switch (rclass)
7614 {
7615 case FP_REGS:
7616 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7617 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7618 else
7619 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7620 case ACCESS_REGS:
7621 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7622 default:
7623 break;
7624 }
7625 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7626 }
7627
7628 /* Return true if register FROM can be eliminated via register TO. */
7629
7630 static bool
7631 s390_can_eliminate (const int from, const int to)
7632 {
7633 /* On zSeries machines, we have not marked the base register as fixed.
7634 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7635 If a function requires the base register, we say here that this
7636 elimination cannot be performed. This will cause reload to free
7637 up the base register (as if it were fixed). On the other hand,
7638 if the current function does *not* require the base register, we
7639 say here the elimination succeeds, which in turn allows reload
7640 to allocate the base register for any other purpose. */
7641 if (from == BASE_REGNUM && to == BASE_REGNUM)
7642 {
7643 if (TARGET_CPU_ZARCH)
7644 {
7645 s390_init_frame_layout ();
7646 return cfun->machine->base_reg == NULL_RTX;
7647 }
7648
7649 return false;
7650 }
7651
7652 /* Everything else must point into the stack frame. */
7653 gcc_assert (to == STACK_POINTER_REGNUM
7654 || to == HARD_FRAME_POINTER_REGNUM);
7655
7656 gcc_assert (from == FRAME_POINTER_REGNUM
7657 || from == ARG_POINTER_REGNUM
7658 || from == RETURN_ADDRESS_POINTER_REGNUM);
7659
7660 /* Make sure we actually saved the return address. */
7661 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7662 if (!crtl->calls_eh_return
7663 && !cfun->stdarg
7664 && !cfun_frame_layout.save_return_addr_p)
7665 return false;
7666
7667 return true;
7668 }
7669
7670 /* Return offset between register FROM and TO initially after prolog. */
7671
7672 HOST_WIDE_INT
7673 s390_initial_elimination_offset (int from, int to)
7674 {
7675 HOST_WIDE_INT offset;
7676 int index;
7677
7678 /* ??? Why are we called for non-eliminable pairs? */
7679 if (!s390_can_eliminate (from, to))
7680 return 0;
7681
7682 switch (from)
7683 {
7684 case FRAME_POINTER_REGNUM:
7685 offset = (get_frame_size()
7686 + STACK_POINTER_OFFSET
7687 + crtl->outgoing_args_size);
7688 break;
7689
7690 case ARG_POINTER_REGNUM:
7691 s390_init_frame_layout ();
7692 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7693 break;
7694
7695 case RETURN_ADDRESS_POINTER_REGNUM:
7696 s390_init_frame_layout ();
7697 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7698 gcc_assert (index >= 0);
7699 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7700 offset += index * UNITS_PER_LONG;
7701 break;
7702
7703 case BASE_REGNUM:
7704 offset = 0;
7705 break;
7706
7707 default:
7708 gcc_unreachable ();
7709 }
7710
7711 return offset;
7712 }
7713
7714 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7715 to register BASE. Return generated insn. */
7716
7717 static rtx
7718 save_fpr (rtx base, int offset, int regnum)
7719 {
7720 rtx addr;
7721 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7722
7723 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7724 set_mem_alias_set (addr, get_varargs_alias_set ());
7725 else
7726 set_mem_alias_set (addr, get_frame_alias_set ());
7727
7728 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7729 }
7730
7731 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7732 to register BASE. Return generated insn. */
7733
7734 static rtx
7735 restore_fpr (rtx base, int offset, int regnum)
7736 {
7737 rtx addr;
7738 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7739 set_mem_alias_set (addr, get_frame_alias_set ());
7740
7741 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7742 }
7743
7744 /* Return true if REGNO is a global register, but not one
7745 of the special ones that need to be saved/restored in anyway. */
7746
7747 static inline bool
7748 global_not_special_regno_p (int regno)
7749 {
7750 return (global_regs[regno]
7751 /* These registers are special and need to be
7752 restored in any case. */
7753 && !(regno == STACK_POINTER_REGNUM
7754 || regno == RETURN_REGNUM
7755 || regno == BASE_REGNUM
7756 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7757 }
7758
7759 /* Generate insn to save registers FIRST to LAST into
7760 the register save area located at offset OFFSET
7761 relative to register BASE. */
7762
7763 static rtx
7764 save_gprs (rtx base, int offset, int first, int last)
7765 {
7766 rtx addr, insn, note;
7767 int i;
7768
7769 addr = plus_constant (Pmode, base, offset);
7770 addr = gen_rtx_MEM (Pmode, addr);
7771
7772 set_mem_alias_set (addr, get_frame_alias_set ());
7773
7774 /* Special-case single register. */
7775 if (first == last)
7776 {
7777 if (TARGET_64BIT)
7778 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7779 else
7780 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7781
7782 if (!global_not_special_regno_p (first))
7783 RTX_FRAME_RELATED_P (insn) = 1;
7784 return insn;
7785 }
7786
7787
7788 insn = gen_store_multiple (addr,
7789 gen_rtx_REG (Pmode, first),
7790 GEN_INT (last - first + 1));
7791
7792 if (first <= 6 && cfun->stdarg)
7793 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7794 {
7795 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7796
7797 if (first + i <= 6)
7798 set_mem_alias_set (mem, get_varargs_alias_set ());
7799 }
7800
7801 /* We need to set the FRAME_RELATED flag on all SETs
7802 inside the store-multiple pattern.
7803
7804 However, we must not emit DWARF records for registers 2..5
7805 if they are stored for use by variable arguments ...
7806
7807 ??? Unfortunately, it is not enough to simply not the
7808 FRAME_RELATED flags for those SETs, because the first SET
7809 of the PARALLEL is always treated as if it had the flag
7810 set, even if it does not. Therefore we emit a new pattern
7811 without those registers as REG_FRAME_RELATED_EXPR note. */
7812
7813 if (first >= 6 && !global_not_special_regno_p (first))
7814 {
7815 rtx pat = PATTERN (insn);
7816
7817 for (i = 0; i < XVECLEN (pat, 0); i++)
7818 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7819 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7820 0, i)))))
7821 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7822
7823 RTX_FRAME_RELATED_P (insn) = 1;
7824 }
7825 else if (last >= 6)
7826 {
7827 int start;
7828
7829 for (start = first >= 6 ? first : 6; start <= last; start++)
7830 if (!global_not_special_regno_p (start))
7831 break;
7832
7833 if (start > last)
7834 return insn;
7835
7836 addr = plus_constant (Pmode, base,
7837 offset + (start - first) * UNITS_PER_LONG);
7838 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7839 gen_rtx_REG (Pmode, start),
7840 GEN_INT (last - start + 1));
7841 note = PATTERN (note);
7842
7843 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7844
7845 for (i = 0; i < XVECLEN (note, 0); i++)
7846 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7847 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7848 0, i)))))
7849 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7850
7851 RTX_FRAME_RELATED_P (insn) = 1;
7852 }
7853
7854 return insn;
7855 }
7856
7857 /* Generate insn to restore registers FIRST to LAST from
7858 the register save area located at offset OFFSET
7859 relative to register BASE. */
7860
7861 static rtx
7862 restore_gprs (rtx base, int offset, int first, int last)
7863 {
7864 rtx addr, insn;
7865
7866 addr = plus_constant (Pmode, base, offset);
7867 addr = gen_rtx_MEM (Pmode, addr);
7868 set_mem_alias_set (addr, get_frame_alias_set ());
7869
7870 /* Special-case single register. */
7871 if (first == last)
7872 {
7873 if (TARGET_64BIT)
7874 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7875 else
7876 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7877
7878 return insn;
7879 }
7880
7881 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7882 addr,
7883 GEN_INT (last - first + 1));
7884 return insn;
7885 }
7886
7887 /* Return insn sequence to load the GOT register. */
7888
7889 static GTY(()) rtx got_symbol;
7890 rtx
7891 s390_load_got (void)
7892 {
7893 rtx insns;
7894
7895 /* We cannot use pic_offset_table_rtx here since we use this
7896 function also for non-pic if __tls_get_offset is called and in
7897 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
7898 aren't usable. */
7899 rtx got_rtx = gen_rtx_REG (Pmode, 12);
7900
7901 if (!got_symbol)
7902 {
7903 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7904 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7905 }
7906
7907 start_sequence ();
7908
7909 if (TARGET_CPU_ZARCH)
7910 {
7911 emit_move_insn (got_rtx, got_symbol);
7912 }
7913 else
7914 {
7915 rtx offset;
7916
7917 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7918 UNSPEC_LTREL_OFFSET);
7919 offset = gen_rtx_CONST (Pmode, offset);
7920 offset = force_const_mem (Pmode, offset);
7921
7922 emit_move_insn (got_rtx, offset);
7923
7924 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7925 UNSPEC_LTREL_BASE);
7926 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
7927
7928 emit_move_insn (got_rtx, offset);
7929 }
7930
7931 insns = get_insns ();
7932 end_sequence ();
7933 return insns;
7934 }
7935
7936 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7937 and the change to the stack pointer. */
7938
7939 static void
7940 s390_emit_stack_tie (void)
7941 {
7942 rtx mem = gen_frame_mem (BLKmode,
7943 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7944
7945 emit_insn (gen_stack_tie (mem));
7946 }
7947
7948 /* Expand the prologue into a bunch of separate insns. */
7949
7950 void
7951 s390_emit_prologue (void)
7952 {
7953 rtx insn, addr;
7954 rtx temp_reg;
7955 int i;
7956 int offset;
7957 int next_fpr = 0;
7958
7959 /* Complete frame layout. */
7960
7961 s390_update_frame_layout ();
7962
7963 /* Annotate all constant pool references to let the scheduler know
7964 they implicitly use the base register. */
7965
7966 push_topmost_sequence ();
7967
7968 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7969 if (INSN_P (insn))
7970 {
7971 annotate_constant_pool_refs (&PATTERN (insn));
7972 df_insn_rescan (insn);
7973 }
7974
7975 pop_topmost_sequence ();
7976
7977 /* Choose best register to use for temp use within prologue.
7978 See below for why TPF must use the register 1. */
7979
7980 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7981 && !current_function_is_leaf
7982 && !TARGET_TPF_PROFILING)
7983 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7984 else
7985 temp_reg = gen_rtx_REG (Pmode, 1);
7986
7987 /* Save call saved gprs. */
7988 if (cfun_frame_layout.first_save_gpr != -1)
7989 {
7990 insn = save_gprs (stack_pointer_rtx,
7991 cfun_frame_layout.gprs_offset +
7992 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7993 - cfun_frame_layout.first_save_gpr_slot),
7994 cfun_frame_layout.first_save_gpr,
7995 cfun_frame_layout.last_save_gpr);
7996 emit_insn (insn);
7997 }
7998
7999 /* Dummy insn to mark literal pool slot. */
8000
8001 if (cfun->machine->base_reg)
8002 emit_insn (gen_main_pool (cfun->machine->base_reg));
8003
8004 offset = cfun_frame_layout.f0_offset;
8005
8006 /* Save f0 and f2. */
8007 for (i = 0; i < 2; i++)
8008 {
8009 if (cfun_fpr_bit_p (i))
8010 {
8011 save_fpr (stack_pointer_rtx, offset, i + 16);
8012 offset += 8;
8013 }
8014 else if (!TARGET_PACKED_STACK)
8015 offset += 8;
8016 }
8017
8018 /* Save f4 and f6. */
8019 offset = cfun_frame_layout.f4_offset;
8020 for (i = 2; i < 4; i++)
8021 {
8022 if (cfun_fpr_bit_p (i))
8023 {
8024 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8025 offset += 8;
8026
8027 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8028 therefore are not frame related. */
8029 if (!call_really_used_regs[i + 16])
8030 RTX_FRAME_RELATED_P (insn) = 1;
8031 }
8032 else if (!TARGET_PACKED_STACK)
8033 offset += 8;
8034 }
8035
8036 if (TARGET_PACKED_STACK
8037 && cfun_save_high_fprs_p
8038 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8039 {
8040 offset = (cfun_frame_layout.f8_offset
8041 + (cfun_frame_layout.high_fprs - 1) * 8);
8042
8043 for (i = 15; i > 7 && offset >= 0; i--)
8044 if (cfun_fpr_bit_p (i))
8045 {
8046 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8047
8048 RTX_FRAME_RELATED_P (insn) = 1;
8049 offset -= 8;
8050 }
8051 if (offset >= cfun_frame_layout.f8_offset)
8052 next_fpr = i + 16;
8053 }
8054
8055 if (!TARGET_PACKED_STACK)
8056 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8057
8058 if (flag_stack_usage_info)
8059 current_function_static_stack_size = cfun_frame_layout.frame_size;
8060
8061 /* Decrement stack pointer. */
8062
8063 if (cfun_frame_layout.frame_size > 0)
8064 {
8065 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8066 rtx real_frame_off;
8067
8068 if (s390_stack_size)
8069 {
8070 HOST_WIDE_INT stack_guard;
8071
8072 if (s390_stack_guard)
8073 stack_guard = s390_stack_guard;
8074 else
8075 {
8076 /* If no value for stack guard is provided the smallest power of 2
8077 larger than the current frame size is chosen. */
8078 stack_guard = 1;
8079 while (stack_guard < cfun_frame_layout.frame_size)
8080 stack_guard <<= 1;
8081 }
8082
8083 if (cfun_frame_layout.frame_size >= s390_stack_size)
8084 {
8085 warning (0, "frame size of function %qs is %wd"
8086 " bytes exceeding user provided stack limit of "
8087 "%d bytes. "
8088 "An unconditional trap is added.",
8089 current_function_name(), cfun_frame_layout.frame_size,
8090 s390_stack_size);
8091 emit_insn (gen_trap ());
8092 }
8093 else
8094 {
8095 /* stack_guard has to be smaller than s390_stack_size.
8096 Otherwise we would emit an AND with zero which would
8097 not match the test under mask pattern. */
8098 if (stack_guard >= s390_stack_size)
8099 {
8100 warning (0, "frame size of function %qs is %wd"
8101 " bytes which is more than half the stack size. "
8102 "The dynamic check would not be reliable. "
8103 "No check emitted for this function.",
8104 current_function_name(),
8105 cfun_frame_layout.frame_size);
8106 }
8107 else
8108 {
8109 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8110 & ~(stack_guard - 1));
8111
8112 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8113 GEN_INT (stack_check_mask));
8114 if (TARGET_64BIT)
8115 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8116 t, const0_rtx),
8117 t, const0_rtx, const0_rtx));
8118 else
8119 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8120 t, const0_rtx),
8121 t, const0_rtx, const0_rtx));
8122 }
8123 }
8124 }
8125
8126 if (s390_warn_framesize > 0
8127 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8128 warning (0, "frame size of %qs is %wd bytes",
8129 current_function_name (), cfun_frame_layout.frame_size);
8130
8131 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8132 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8133
8134 /* Save incoming stack pointer into temp reg. */
8135 if (TARGET_BACKCHAIN || next_fpr)
8136 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8137
8138 /* Subtract frame size from stack pointer. */
8139
8140 if (DISP_IN_RANGE (INTVAL (frame_off)))
8141 {
8142 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8143 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8144 frame_off));
8145 insn = emit_insn (insn);
8146 }
8147 else
8148 {
8149 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8150 frame_off = force_const_mem (Pmode, frame_off);
8151
8152 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8153 annotate_constant_pool_refs (&PATTERN (insn));
8154 }
8155
8156 RTX_FRAME_RELATED_P (insn) = 1;
8157 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8158 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8159 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8160 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8161 real_frame_off)));
8162
8163 /* Set backchain. */
8164
8165 if (TARGET_BACKCHAIN)
8166 {
8167 if (cfun_frame_layout.backchain_offset)
8168 addr = gen_rtx_MEM (Pmode,
8169 plus_constant (Pmode, stack_pointer_rtx,
8170 cfun_frame_layout.backchain_offset));
8171 else
8172 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8173 set_mem_alias_set (addr, get_frame_alias_set ());
8174 insn = emit_insn (gen_move_insn (addr, temp_reg));
8175 }
8176
8177 /* If we support non-call exceptions (e.g. for Java),
8178 we need to make sure the backchain pointer is set up
8179 before any possibly trapping memory access. */
8180 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8181 {
8182 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8183 emit_clobber (addr);
8184 }
8185 }
8186
8187 /* Save fprs 8 - 15 (64 bit ABI). */
8188
8189 if (cfun_save_high_fprs_p && next_fpr)
8190 {
8191 /* If the stack might be accessed through a different register
8192 we have to make sure that the stack pointer decrement is not
8193 moved below the use of the stack slots. */
8194 s390_emit_stack_tie ();
8195
8196 insn = emit_insn (gen_add2_insn (temp_reg,
8197 GEN_INT (cfun_frame_layout.f8_offset)));
8198
8199 offset = 0;
8200
8201 for (i = 24; i <= next_fpr; i++)
8202 if (cfun_fpr_bit_p (i - 16))
8203 {
8204 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8205 cfun_frame_layout.frame_size
8206 + cfun_frame_layout.f8_offset
8207 + offset);
8208
8209 insn = save_fpr (temp_reg, offset, i);
8210 offset += 8;
8211 RTX_FRAME_RELATED_P (insn) = 1;
8212 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8213 gen_rtx_SET (VOIDmode,
8214 gen_rtx_MEM (DFmode, addr),
8215 gen_rtx_REG (DFmode, i)));
8216 }
8217 }
8218
8219 /* Set frame pointer, if needed. */
8220
8221 if (frame_pointer_needed)
8222 {
8223 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8224 RTX_FRAME_RELATED_P (insn) = 1;
8225 }
8226
8227 /* Set up got pointer, if needed. */
8228
8229 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8230 {
8231 rtx insns = s390_load_got ();
8232
8233 for (insn = insns; insn; insn = NEXT_INSN (insn))
8234 annotate_constant_pool_refs (&PATTERN (insn));
8235
8236 emit_insn (insns);
8237 }
8238
8239 if (TARGET_TPF_PROFILING)
8240 {
8241 /* Generate a BAS instruction to serve as a function
8242 entry intercept to facilitate the use of tracing
8243 algorithms located at the branch target. */
8244 emit_insn (gen_prologue_tpf ());
8245
8246 /* Emit a blockage here so that all code
8247 lies between the profiling mechanisms. */
8248 emit_insn (gen_blockage ());
8249 }
8250 }
8251
8252 /* Expand the epilogue into a bunch of separate insns. */
8253
8254 void
8255 s390_emit_epilogue (bool sibcall)
8256 {
8257 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8258 int area_bottom, area_top, offset = 0;
8259 int next_offset;
8260 rtvec p;
8261 int i;
8262
8263 if (TARGET_TPF_PROFILING)
8264 {
8265
8266 /* Generate a BAS instruction to serve as a function
8267 entry intercept to facilitate the use of tracing
8268 algorithms located at the branch target. */
8269
8270 /* Emit a blockage here so that all code
8271 lies between the profiling mechanisms. */
8272 emit_insn (gen_blockage ());
8273
8274 emit_insn (gen_epilogue_tpf ());
8275 }
8276
8277 /* Check whether to use frame or stack pointer for restore. */
8278
8279 frame_pointer = (frame_pointer_needed
8280 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8281
8282 s390_frame_area (&area_bottom, &area_top);
8283
8284 /* Check whether we can access the register save area.
8285 If not, increment the frame pointer as required. */
8286
8287 if (area_top <= area_bottom)
8288 {
8289 /* Nothing to restore. */
8290 }
8291 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8292 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8293 {
8294 /* Area is in range. */
8295 offset = cfun_frame_layout.frame_size;
8296 }
8297 else
8298 {
8299 rtx insn, frame_off, cfa;
8300
8301 offset = area_bottom < 0 ? -area_bottom : 0;
8302 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8303
8304 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8305 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8306 if (DISP_IN_RANGE (INTVAL (frame_off)))
8307 {
8308 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8309 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8310 insn = emit_insn (insn);
8311 }
8312 else
8313 {
8314 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8315 frame_off = force_const_mem (Pmode, frame_off);
8316
8317 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8318 annotate_constant_pool_refs (&PATTERN (insn));
8319 }
8320 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8321 RTX_FRAME_RELATED_P (insn) = 1;
8322 }
8323
8324 /* Restore call saved fprs. */
8325
8326 if (TARGET_64BIT)
8327 {
8328 if (cfun_save_high_fprs_p)
8329 {
8330 next_offset = cfun_frame_layout.f8_offset;
8331 for (i = 24; i < 32; i++)
8332 {
8333 if (cfun_fpr_bit_p (i - 16))
8334 {
8335 restore_fpr (frame_pointer,
8336 offset + next_offset, i);
8337 cfa_restores
8338 = alloc_reg_note (REG_CFA_RESTORE,
8339 gen_rtx_REG (DFmode, i), cfa_restores);
8340 next_offset += 8;
8341 }
8342 }
8343 }
8344
8345 }
8346 else
8347 {
8348 next_offset = cfun_frame_layout.f4_offset;
8349 for (i = 18; i < 20; i++)
8350 {
8351 if (cfun_fpr_bit_p (i - 16))
8352 {
8353 restore_fpr (frame_pointer,
8354 offset + next_offset, i);
8355 cfa_restores
8356 = alloc_reg_note (REG_CFA_RESTORE,
8357 gen_rtx_REG (DFmode, i), cfa_restores);
8358 next_offset += 8;
8359 }
8360 else if (!TARGET_PACKED_STACK)
8361 next_offset += 8;
8362 }
8363
8364 }
8365
8366 /* Return register. */
8367
8368 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8369
8370 /* Restore call saved gprs. */
8371
8372 if (cfun_frame_layout.first_restore_gpr != -1)
8373 {
8374 rtx insn, addr;
8375 int i;
8376
8377 /* Check for global register and save them
8378 to stack location from where they get restored. */
8379
8380 for (i = cfun_frame_layout.first_restore_gpr;
8381 i <= cfun_frame_layout.last_restore_gpr;
8382 i++)
8383 {
8384 if (global_not_special_regno_p (i))
8385 {
8386 addr = plus_constant (Pmode, frame_pointer,
8387 offset + cfun_frame_layout.gprs_offset
8388 + (i - cfun_frame_layout.first_save_gpr_slot)
8389 * UNITS_PER_LONG);
8390 addr = gen_rtx_MEM (Pmode, addr);
8391 set_mem_alias_set (addr, get_frame_alias_set ());
8392 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8393 }
8394 else
8395 cfa_restores
8396 = alloc_reg_note (REG_CFA_RESTORE,
8397 gen_rtx_REG (Pmode, i), cfa_restores);
8398 }
8399
8400 if (! sibcall)
8401 {
8402 /* Fetch return address from stack before load multiple,
8403 this will do good for scheduling. */
8404
8405 if (cfun_frame_layout.save_return_addr_p
8406 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8407 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8408 {
8409 int return_regnum = find_unused_clobbered_reg();
8410 if (!return_regnum)
8411 return_regnum = 4;
8412 return_reg = gen_rtx_REG (Pmode, return_regnum);
8413
8414 addr = plus_constant (Pmode, frame_pointer,
8415 offset + cfun_frame_layout.gprs_offset
8416 + (RETURN_REGNUM
8417 - cfun_frame_layout.first_save_gpr_slot)
8418 * UNITS_PER_LONG);
8419 addr = gen_rtx_MEM (Pmode, addr);
8420 set_mem_alias_set (addr, get_frame_alias_set ());
8421 emit_move_insn (return_reg, addr);
8422 }
8423 }
8424
8425 insn = restore_gprs (frame_pointer,
8426 offset + cfun_frame_layout.gprs_offset
8427 + (cfun_frame_layout.first_restore_gpr
8428 - cfun_frame_layout.first_save_gpr_slot)
8429 * UNITS_PER_LONG,
8430 cfun_frame_layout.first_restore_gpr,
8431 cfun_frame_layout.last_restore_gpr);
8432 insn = emit_insn (insn);
8433 REG_NOTES (insn) = cfa_restores;
8434 add_reg_note (insn, REG_CFA_DEF_CFA,
8435 plus_constant (Pmode, stack_pointer_rtx,
8436 STACK_POINTER_OFFSET));
8437 RTX_FRAME_RELATED_P (insn) = 1;
8438 }
8439
8440 if (! sibcall)
8441 {
8442
8443 /* Return to caller. */
8444
8445 p = rtvec_alloc (2);
8446
8447 RTVEC_ELT (p, 0) = ret_rtx;
8448 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8449 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8450 }
8451 }
8452
8453
8454 /* Return the size in bytes of a function argument of
8455 type TYPE and/or mode MODE. At least one of TYPE or
8456 MODE must be specified. */
8457
8458 static int
8459 s390_function_arg_size (enum machine_mode mode, const_tree type)
8460 {
8461 if (type)
8462 return int_size_in_bytes (type);
8463
8464 /* No type info available for some library calls ... */
8465 if (mode != BLKmode)
8466 return GET_MODE_SIZE (mode);
8467
8468 /* If we have neither type nor mode, abort */
8469 gcc_unreachable ();
8470 }
8471
8472 /* Return true if a function argument of type TYPE and mode MODE
8473 is to be passed in a floating-point register, if available. */
8474
8475 static bool
8476 s390_function_arg_float (enum machine_mode mode, const_tree type)
8477 {
8478 int size = s390_function_arg_size (mode, type);
8479 if (size > 8)
8480 return false;
8481
8482 /* Soft-float changes the ABI: no floating-point registers are used. */
8483 if (TARGET_SOFT_FLOAT)
8484 return false;
8485
8486 /* No type info available for some library calls ... */
8487 if (!type)
8488 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8489
8490 /* The ABI says that record types with a single member are treated
8491 just like that member would be. */
8492 while (TREE_CODE (type) == RECORD_TYPE)
8493 {
8494 tree field, single = NULL_TREE;
8495
8496 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8497 {
8498 if (TREE_CODE (field) != FIELD_DECL)
8499 continue;
8500
8501 if (single == NULL_TREE)
8502 single = TREE_TYPE (field);
8503 else
8504 return false;
8505 }
8506
8507 if (single == NULL_TREE)
8508 return false;
8509 else
8510 type = single;
8511 }
8512
8513 return TREE_CODE (type) == REAL_TYPE;
8514 }
8515
8516 /* Return true if a function argument of type TYPE and mode MODE
8517 is to be passed in an integer register, or a pair of integer
8518 registers, if available. */
8519
8520 static bool
8521 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8522 {
8523 int size = s390_function_arg_size (mode, type);
8524 if (size > 8)
8525 return false;
8526
8527 /* No type info available for some library calls ... */
8528 if (!type)
8529 return GET_MODE_CLASS (mode) == MODE_INT
8530 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8531
8532 /* We accept small integral (and similar) types. */
8533 if (INTEGRAL_TYPE_P (type)
8534 || POINTER_TYPE_P (type)
8535 || TREE_CODE (type) == NULLPTR_TYPE
8536 || TREE_CODE (type) == OFFSET_TYPE
8537 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8538 return true;
8539
8540 /* We also accept structs of size 1, 2, 4, 8 that are not
8541 passed in floating-point registers. */
8542 if (AGGREGATE_TYPE_P (type)
8543 && exact_log2 (size) >= 0
8544 && !s390_function_arg_float (mode, type))
8545 return true;
8546
8547 return false;
8548 }
8549
8550 /* Return 1 if a function argument of type TYPE and mode MODE
8551 is to be passed by reference. The ABI specifies that only
8552 structures of size 1, 2, 4, or 8 bytes are passed by value,
8553 all other structures (and complex numbers) are passed by
8554 reference. */
8555
8556 static bool
8557 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
8558 enum machine_mode mode, const_tree type,
8559 bool named ATTRIBUTE_UNUSED)
8560 {
8561 int size = s390_function_arg_size (mode, type);
8562 if (size > 8)
8563 return true;
8564
8565 if (type)
8566 {
8567 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8568 return 1;
8569
8570 if (TREE_CODE (type) == COMPLEX_TYPE
8571 || TREE_CODE (type) == VECTOR_TYPE)
8572 return 1;
8573 }
8574
8575 return 0;
8576 }
8577
8578 /* Update the data in CUM to advance over an argument of mode MODE and
8579 data type TYPE. (TYPE is null for libcalls where that information
8580 may not be available.). The boolean NAMED specifies whether the
8581 argument is a named argument (as opposed to an unnamed argument
8582 matching an ellipsis). */
8583
8584 static void
8585 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
8586 const_tree type, bool named ATTRIBUTE_UNUSED)
8587 {
8588 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8589
8590 if (s390_function_arg_float (mode, type))
8591 {
8592 cum->fprs += 1;
8593 }
8594 else if (s390_function_arg_integer (mode, type))
8595 {
8596 int size = s390_function_arg_size (mode, type);
8597 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8598 }
8599 else
8600 gcc_unreachable ();
8601 }
8602
8603 /* Define where to put the arguments to a function.
8604 Value is zero to push the argument on the stack,
8605 or a hard register in which to store the argument.
8606
8607 MODE is the argument's machine mode.
8608 TYPE is the data type of the argument (as a tree).
8609 This is null for libcalls where that information may
8610 not be available.
8611 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8612 the preceding args and about the function being called.
8613 NAMED is nonzero if this argument is a named parameter
8614 (otherwise it is an extra parameter matching an ellipsis).
8615
8616 On S/390, we use general purpose registers 2 through 6 to
8617 pass integer, pointer, and certain structure arguments, and
8618 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8619 to pass floating point arguments. All remaining arguments
8620 are pushed to the stack. */
8621
8622 static rtx
8623 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8624 const_tree type, bool named ATTRIBUTE_UNUSED)
8625 {
8626 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8627
8628 if (s390_function_arg_float (mode, type))
8629 {
8630 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8631 return 0;
8632 else
8633 return gen_rtx_REG (mode, cum->fprs + 16);
8634 }
8635 else if (s390_function_arg_integer (mode, type))
8636 {
8637 int size = s390_function_arg_size (mode, type);
8638 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8639
8640 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8641 return 0;
8642 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8643 return gen_rtx_REG (mode, cum->gprs + 2);
8644 else if (n_gprs == 2)
8645 {
8646 rtvec p = rtvec_alloc (2);
8647
8648 RTVEC_ELT (p, 0)
8649 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8650 const0_rtx);
8651 RTVEC_ELT (p, 1)
8652 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8653 GEN_INT (4));
8654
8655 return gen_rtx_PARALLEL (mode, p);
8656 }
8657 }
8658
8659 /* After the real arguments, expand_call calls us once again
8660 with a void_type_node type. Whatever we return here is
8661 passed as operand 2 to the call expanders.
8662
8663 We don't need this feature ... */
8664 else if (type == void_type_node)
8665 return const0_rtx;
8666
8667 gcc_unreachable ();
8668 }
8669
8670 /* Return true if return values of type TYPE should be returned
8671 in a memory buffer whose address is passed by the caller as
8672 hidden first argument. */
8673
8674 static bool
8675 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8676 {
8677 /* We accept small integral (and similar) types. */
8678 if (INTEGRAL_TYPE_P (type)
8679 || POINTER_TYPE_P (type)
8680 || TREE_CODE (type) == OFFSET_TYPE
8681 || TREE_CODE (type) == REAL_TYPE)
8682 return int_size_in_bytes (type) > 8;
8683
8684 /* Aggregates and similar constructs are always returned
8685 in memory. */
8686 if (AGGREGATE_TYPE_P (type)
8687 || TREE_CODE (type) == COMPLEX_TYPE
8688 || TREE_CODE (type) == VECTOR_TYPE)
8689 return true;
8690
8691 /* ??? We get called on all sorts of random stuff from
8692 aggregate_value_p. We can't abort, but it's not clear
8693 what's safe to return. Pretend it's a struct I guess. */
8694 return true;
8695 }
8696
8697 /* Function arguments and return values are promoted to word size. */
8698
8699 static enum machine_mode
8700 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8701 int *punsignedp,
8702 const_tree fntype ATTRIBUTE_UNUSED,
8703 int for_return ATTRIBUTE_UNUSED)
8704 {
8705 if (INTEGRAL_MODE_P (mode)
8706 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8707 {
8708 if (type != NULL_TREE && POINTER_TYPE_P (type))
8709 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8710 return Pmode;
8711 }
8712
8713 return mode;
8714 }
8715
8716 /* Define where to return a (scalar) value of type RET_TYPE.
8717 If RET_TYPE is null, define where to return a (scalar)
8718 value of mode MODE from a libcall. */
8719
8720 static rtx
8721 s390_function_and_libcall_value (enum machine_mode mode,
8722 const_tree ret_type,
8723 const_tree fntype_or_decl,
8724 bool outgoing ATTRIBUTE_UNUSED)
8725 {
8726 /* For normal functions perform the promotion as
8727 promote_function_mode would do. */
8728 if (ret_type)
8729 {
8730 int unsignedp = TYPE_UNSIGNED (ret_type);
8731 mode = promote_function_mode (ret_type, mode, &unsignedp,
8732 fntype_or_decl, 1);
8733 }
8734
8735 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8736 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8737
8738 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8739 return gen_rtx_REG (mode, 16);
8740 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8741 || UNITS_PER_LONG == UNITS_PER_WORD)
8742 return gen_rtx_REG (mode, 2);
8743 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8744 {
8745 /* This case is triggered when returning a 64 bit value with
8746 -m31 -mzarch. Although the value would fit into a single
8747 register it has to be forced into a 32 bit register pair in
8748 order to match the ABI. */
8749 rtvec p = rtvec_alloc (2);
8750
8751 RTVEC_ELT (p, 0)
8752 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8753 RTVEC_ELT (p, 1)
8754 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8755
8756 return gen_rtx_PARALLEL (mode, p);
8757 }
8758
8759 gcc_unreachable ();
8760 }
8761
8762 /* Define where to return a scalar return value of type RET_TYPE. */
8763
8764 static rtx
8765 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8766 bool outgoing)
8767 {
8768 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8769 fn_decl_or_type, outgoing);
8770 }
8771
8772 /* Define where to return a scalar libcall return value of mode
8773 MODE. */
8774
8775 static rtx
8776 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8777 {
8778 return s390_function_and_libcall_value (mode, NULL_TREE,
8779 NULL_TREE, true);
8780 }
8781
8782
8783 /* Create and return the va_list datatype.
8784
8785 On S/390, va_list is an array type equivalent to
8786
8787 typedef struct __va_list_tag
8788 {
8789 long __gpr;
8790 long __fpr;
8791 void *__overflow_arg_area;
8792 void *__reg_save_area;
8793 } va_list[1];
8794
8795 where __gpr and __fpr hold the number of general purpose
8796 or floating point arguments used up to now, respectively,
8797 __overflow_arg_area points to the stack location of the
8798 next argument passed on the stack, and __reg_save_area
8799 always points to the start of the register area in the
8800 call frame of the current function. The function prologue
8801 saves all registers used for argument passing into this
8802 area if the function uses variable arguments. */
8803
8804 static tree
8805 s390_build_builtin_va_list (void)
8806 {
8807 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8808
8809 record = lang_hooks.types.make_type (RECORD_TYPE);
8810
8811 type_decl =
8812 build_decl (BUILTINS_LOCATION,
8813 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8814
8815 f_gpr = build_decl (BUILTINS_LOCATION,
8816 FIELD_DECL, get_identifier ("__gpr"),
8817 long_integer_type_node);
8818 f_fpr = build_decl (BUILTINS_LOCATION,
8819 FIELD_DECL, get_identifier ("__fpr"),
8820 long_integer_type_node);
8821 f_ovf = build_decl (BUILTINS_LOCATION,
8822 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8823 ptr_type_node);
8824 f_sav = build_decl (BUILTINS_LOCATION,
8825 FIELD_DECL, get_identifier ("__reg_save_area"),
8826 ptr_type_node);
8827
8828 va_list_gpr_counter_field = f_gpr;
8829 va_list_fpr_counter_field = f_fpr;
8830
8831 DECL_FIELD_CONTEXT (f_gpr) = record;
8832 DECL_FIELD_CONTEXT (f_fpr) = record;
8833 DECL_FIELD_CONTEXT (f_ovf) = record;
8834 DECL_FIELD_CONTEXT (f_sav) = record;
8835
8836 TYPE_STUB_DECL (record) = type_decl;
8837 TYPE_NAME (record) = type_decl;
8838 TYPE_FIELDS (record) = f_gpr;
8839 DECL_CHAIN (f_gpr) = f_fpr;
8840 DECL_CHAIN (f_fpr) = f_ovf;
8841 DECL_CHAIN (f_ovf) = f_sav;
8842
8843 layout_type (record);
8844
8845 /* The correct type is an array type of one element. */
8846 return build_array_type (record, build_index_type (size_zero_node));
8847 }
8848
8849 /* Implement va_start by filling the va_list structure VALIST.
8850 STDARG_P is always true, and ignored.
8851 NEXTARG points to the first anonymous stack argument.
8852
8853 The following global variables are used to initialize
8854 the va_list structure:
8855
8856 crtl->args.info:
8857 holds number of gprs and fprs used for named arguments.
8858 crtl->args.arg_offset_rtx:
8859 holds the offset of the first anonymous stack argument
8860 (relative to the virtual arg pointer). */
8861
8862 static void
8863 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8864 {
8865 HOST_WIDE_INT n_gpr, n_fpr;
8866 int off;
8867 tree f_gpr, f_fpr, f_ovf, f_sav;
8868 tree gpr, fpr, ovf, sav, t;
8869
8870 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8871 f_fpr = DECL_CHAIN (f_gpr);
8872 f_ovf = DECL_CHAIN (f_fpr);
8873 f_sav = DECL_CHAIN (f_ovf);
8874
8875 valist = build_simple_mem_ref (valist);
8876 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8877 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8878 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8879 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8880
8881 /* Count number of gp and fp argument registers used. */
8882
8883 n_gpr = crtl->args.info.gprs;
8884 n_fpr = crtl->args.info.fprs;
8885
8886 if (cfun->va_list_gpr_size)
8887 {
8888 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8889 build_int_cst (NULL_TREE, n_gpr));
8890 TREE_SIDE_EFFECTS (t) = 1;
8891 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8892 }
8893
8894 if (cfun->va_list_fpr_size)
8895 {
8896 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8897 build_int_cst (NULL_TREE, n_fpr));
8898 TREE_SIDE_EFFECTS (t) = 1;
8899 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8900 }
8901
8902 /* Find the overflow area. */
8903 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8904 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8905 {
8906 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8907
8908 off = INTVAL (crtl->args.arg_offset_rtx);
8909 off = off < 0 ? 0 : off;
8910 if (TARGET_DEBUG_ARG)
8911 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8912 (int)n_gpr, (int)n_fpr, off);
8913
8914 t = fold_build_pointer_plus_hwi (t, off);
8915
8916 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8917 TREE_SIDE_EFFECTS (t) = 1;
8918 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8919 }
8920
8921 /* Find the register save area. */
8922 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8923 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8924 {
8925 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8926 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
8927
8928 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8929 TREE_SIDE_EFFECTS (t) = 1;
8930 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8931 }
8932 }
8933
8934 /* Implement va_arg by updating the va_list structure
8935 VALIST as required to retrieve an argument of type
8936 TYPE, and returning that argument.
8937
8938 Generates code equivalent to:
8939
8940 if (integral value) {
8941 if (size <= 4 && args.gpr < 5 ||
8942 size > 4 && args.gpr < 4 )
8943 ret = args.reg_save_area[args.gpr+8]
8944 else
8945 ret = *args.overflow_arg_area++;
8946 } else if (float value) {
8947 if (args.fgpr < 2)
8948 ret = args.reg_save_area[args.fpr+64]
8949 else
8950 ret = *args.overflow_arg_area++;
8951 } else if (aggregate value) {
8952 if (args.gpr < 5)
8953 ret = *args.reg_save_area[args.gpr]
8954 else
8955 ret = **args.overflow_arg_area++;
8956 } */
8957
8958 static tree
8959 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8960 gimple_seq *post_p ATTRIBUTE_UNUSED)
8961 {
8962 tree f_gpr, f_fpr, f_ovf, f_sav;
8963 tree gpr, fpr, ovf, sav, reg, t, u;
8964 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8965 tree lab_false, lab_over, addr;
8966
8967 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8968 f_fpr = DECL_CHAIN (f_gpr);
8969 f_ovf = DECL_CHAIN (f_fpr);
8970 f_sav = DECL_CHAIN (f_ovf);
8971
8972 valist = build_va_arg_indirect_ref (valist);
8973 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8974 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8975 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8976
8977 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8978 both appear on a lhs. */
8979 valist = unshare_expr (valist);
8980 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8981
8982 size = int_size_in_bytes (type);
8983
8984 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8985 {
8986 if (TARGET_DEBUG_ARG)
8987 {
8988 fprintf (stderr, "va_arg: aggregate type");
8989 debug_tree (type);
8990 }
8991
8992 /* Aggregates are passed by reference. */
8993 indirect_p = 1;
8994 reg = gpr;
8995 n_reg = 1;
8996
8997 /* kernel stack layout on 31 bit: It is assumed here that no padding
8998 will be added by s390_frame_info because for va_args always an even
8999 number of gprs has to be saved r15-r2 = 14 regs. */
9000 sav_ofs = 2 * UNITS_PER_LONG;
9001 sav_scale = UNITS_PER_LONG;
9002 size = UNITS_PER_LONG;
9003 max_reg = GP_ARG_NUM_REG - n_reg;
9004 }
9005 else if (s390_function_arg_float (TYPE_MODE (type), type))
9006 {
9007 if (TARGET_DEBUG_ARG)
9008 {
9009 fprintf (stderr, "va_arg: float type");
9010 debug_tree (type);
9011 }
9012
9013 /* FP args go in FP registers, if present. */
9014 indirect_p = 0;
9015 reg = fpr;
9016 n_reg = 1;
9017 sav_ofs = 16 * UNITS_PER_LONG;
9018 sav_scale = 8;
9019 max_reg = FP_ARG_NUM_REG - n_reg;
9020 }
9021 else
9022 {
9023 if (TARGET_DEBUG_ARG)
9024 {
9025 fprintf (stderr, "va_arg: other type");
9026 debug_tree (type);
9027 }
9028
9029 /* Otherwise into GP registers. */
9030 indirect_p = 0;
9031 reg = gpr;
9032 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9033
9034 /* kernel stack layout on 31 bit: It is assumed here that no padding
9035 will be added by s390_frame_info because for va_args always an even
9036 number of gprs has to be saved r15-r2 = 14 regs. */
9037 sav_ofs = 2 * UNITS_PER_LONG;
9038
9039 if (size < UNITS_PER_LONG)
9040 sav_ofs += UNITS_PER_LONG - size;
9041
9042 sav_scale = UNITS_PER_LONG;
9043 max_reg = GP_ARG_NUM_REG - n_reg;
9044 }
9045
9046 /* Pull the value out of the saved registers ... */
9047
9048 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9049 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9050 addr = create_tmp_var (ptr_type_node, "addr");
9051
9052 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9053 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9054 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9055 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9056 gimplify_and_add (t, pre_p);
9057
9058 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9059 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9060 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9061 t = fold_build_pointer_plus (t, u);
9062
9063 gimplify_assign (addr, t, pre_p);
9064
9065 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9066
9067 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9068
9069
9070 /* ... Otherwise out of the overflow area. */
9071
9072 t = ovf;
9073 if (size < UNITS_PER_LONG)
9074 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9075
9076 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9077
9078 gimplify_assign (addr, t, pre_p);
9079
9080 t = fold_build_pointer_plus_hwi (t, size);
9081 gimplify_assign (ovf, t, pre_p);
9082
9083 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9084
9085
9086 /* Increment register save count. */
9087
9088 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9089 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9090 gimplify_and_add (u, pre_p);
9091
9092 if (indirect_p)
9093 {
9094 t = build_pointer_type_for_mode (build_pointer_type (type),
9095 ptr_mode, true);
9096 addr = fold_convert (t, addr);
9097 addr = build_va_arg_indirect_ref (addr);
9098 }
9099 else
9100 {
9101 t = build_pointer_type_for_mode (type, ptr_mode, true);
9102 addr = fold_convert (t, addr);
9103 }
9104
9105 return build_va_arg_indirect_ref (addr);
9106 }
9107
9108
9109 /* Builtins. */
9110
9111 enum s390_builtin
9112 {
9113 S390_BUILTIN_THREAD_POINTER,
9114 S390_BUILTIN_SET_THREAD_POINTER,
9115
9116 S390_BUILTIN_max
9117 };
9118
9119 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9120 CODE_FOR_get_tp_64,
9121 CODE_FOR_set_tp_64
9122 };
9123
9124 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9125 CODE_FOR_get_tp_31,
9126 CODE_FOR_set_tp_31
9127 };
9128
9129 static void
9130 s390_init_builtins (void)
9131 {
9132 tree ftype;
9133
9134 ftype = build_function_type_list (ptr_type_node, NULL_TREE);
9135 add_builtin_function ("__builtin_thread_pointer", ftype,
9136 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9137 NULL, NULL_TREE);
9138
9139 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9140 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9141 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9142 NULL, NULL_TREE);
9143 }
9144
9145 /* Expand an expression EXP that calls a built-in function,
9146 with result going to TARGET if that's convenient
9147 (and in mode MODE if that's convenient).
9148 SUBTARGET may be used as the target for computing one of EXP's operands.
9149 IGNORE is nonzero if the value is to be ignored. */
9150
9151 static rtx
9152 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9153 enum machine_mode mode ATTRIBUTE_UNUSED,
9154 int ignore ATTRIBUTE_UNUSED)
9155 {
9156 #define MAX_ARGS 2
9157
9158 enum insn_code const *code_for_builtin =
9159 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9160
9161 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9162 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9163 enum insn_code icode;
9164 rtx op[MAX_ARGS], pat;
9165 int arity;
9166 bool nonvoid;
9167 tree arg;
9168 call_expr_arg_iterator iter;
9169
9170 if (fcode >= S390_BUILTIN_max)
9171 internal_error ("bad builtin fcode");
9172 icode = code_for_builtin[fcode];
9173 if (icode == 0)
9174 internal_error ("bad builtin fcode");
9175
9176 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9177
9178 arity = 0;
9179 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9180 {
9181 const struct insn_operand_data *insn_op;
9182
9183 if (arg == error_mark_node)
9184 return NULL_RTX;
9185 if (arity > MAX_ARGS)
9186 return NULL_RTX;
9187
9188 insn_op = &insn_data[icode].operand[arity + nonvoid];
9189
9190 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9191
9192 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9193 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9194 arity++;
9195 }
9196
9197 if (nonvoid)
9198 {
9199 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9200 if (!target
9201 || GET_MODE (target) != tmode
9202 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9203 target = gen_reg_rtx (tmode);
9204 }
9205
9206 switch (arity)
9207 {
9208 case 0:
9209 pat = GEN_FCN (icode) (target);
9210 break;
9211 case 1:
9212 if (nonvoid)
9213 pat = GEN_FCN (icode) (target, op[0]);
9214 else
9215 pat = GEN_FCN (icode) (op[0]);
9216 break;
9217 case 2:
9218 pat = GEN_FCN (icode) (target, op[0], op[1]);
9219 break;
9220 default:
9221 gcc_unreachable ();
9222 }
9223 if (!pat)
9224 return NULL_RTX;
9225 emit_insn (pat);
9226
9227 if (nonvoid)
9228 return target;
9229 else
9230 return const0_rtx;
9231 }
9232
9233
9234 /* Output assembly code for the trampoline template to
9235 stdio stream FILE.
9236
9237 On S/390, we use gpr 1 internally in the trampoline code;
9238 gpr 0 is used to hold the static chain. */
9239
9240 static void
9241 s390_asm_trampoline_template (FILE *file)
9242 {
9243 rtx op[2];
9244 op[0] = gen_rtx_REG (Pmode, 0);
9245 op[1] = gen_rtx_REG (Pmode, 1);
9246
9247 if (TARGET_64BIT)
9248 {
9249 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9250 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
9251 output_asm_insn ("br\t%1", op); /* 2 byte */
9252 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9253 }
9254 else
9255 {
9256 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9257 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
9258 output_asm_insn ("br\t%1", op); /* 2 byte */
9259 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9260 }
9261 }
9262
9263 /* Emit RTL insns to initialize the variable parts of a trampoline.
9264 FNADDR is an RTX for the address of the function's pure code.
9265 CXT is an RTX for the static chain value for the function. */
9266
9267 static void
9268 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9269 {
9270 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9271 rtx mem;
9272
9273 emit_block_move (m_tramp, assemble_trampoline_template (),
9274 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9275
9276 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9277 emit_move_insn (mem, cxt);
9278 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9279 emit_move_insn (mem, fnaddr);
9280 }
9281
9282 /* Output assembler code to FILE to increment profiler label # LABELNO
9283 for profiling a function entry. */
9284
9285 void
9286 s390_function_profiler (FILE *file, int labelno)
9287 {
9288 rtx op[7];
9289
9290 char label[128];
9291 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9292
9293 fprintf (file, "# function profiler \n");
9294
9295 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9296 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9297 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
9298
9299 op[2] = gen_rtx_REG (Pmode, 1);
9300 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9301 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9302
9303 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9304 if (flag_pic)
9305 {
9306 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9307 op[4] = gen_rtx_CONST (Pmode, op[4]);
9308 }
9309
9310 if (TARGET_64BIT)
9311 {
9312 output_asm_insn ("stg\t%0,%1", op);
9313 output_asm_insn ("larl\t%2,%3", op);
9314 output_asm_insn ("brasl\t%0,%4", op);
9315 output_asm_insn ("lg\t%0,%1", op);
9316 }
9317 else if (!flag_pic)
9318 {
9319 op[6] = gen_label_rtx ();
9320
9321 output_asm_insn ("st\t%0,%1", op);
9322 output_asm_insn ("bras\t%2,%l6", op);
9323 output_asm_insn (".long\t%4", op);
9324 output_asm_insn (".long\t%3", op);
9325 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9326 output_asm_insn ("l\t%0,0(%2)", op);
9327 output_asm_insn ("l\t%2,4(%2)", op);
9328 output_asm_insn ("basr\t%0,%0", op);
9329 output_asm_insn ("l\t%0,%1", op);
9330 }
9331 else
9332 {
9333 op[5] = gen_label_rtx ();
9334 op[6] = gen_label_rtx ();
9335
9336 output_asm_insn ("st\t%0,%1", op);
9337 output_asm_insn ("bras\t%2,%l6", op);
9338 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9339 output_asm_insn (".long\t%4-%l5", op);
9340 output_asm_insn (".long\t%3-%l5", op);
9341 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9342 output_asm_insn ("lr\t%0,%2", op);
9343 output_asm_insn ("a\t%0,0(%2)", op);
9344 output_asm_insn ("a\t%2,4(%2)", op);
9345 output_asm_insn ("basr\t%0,%0", op);
9346 output_asm_insn ("l\t%0,%1", op);
9347 }
9348 }
9349
9350 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9351 into its SYMBOL_REF_FLAGS. */
9352
9353 static void
9354 s390_encode_section_info (tree decl, rtx rtl, int first)
9355 {
9356 default_encode_section_info (decl, rtl, first);
9357
9358 if (TREE_CODE (decl) == VAR_DECL)
9359 {
9360 /* If a variable has a forced alignment to < 2 bytes, mark it
9361 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9362 operand. */
9363 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9364 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9365 if (!DECL_SIZE (decl)
9366 || !DECL_ALIGN (decl)
9367 || !host_integerp (DECL_SIZE (decl), 0)
9368 || (DECL_ALIGN (decl) <= 64
9369 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9370 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9371 }
9372
9373 /* Literal pool references don't have a decl so they are handled
9374 differently here. We rely on the information in the MEM_ALIGN
9375 entry to decide upon natural alignment. */
9376 if (MEM_P (rtl)
9377 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9378 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9379 && (MEM_ALIGN (rtl) == 0
9380 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9381 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9382 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9383 }
9384
9385 /* Output thunk to FILE that implements a C++ virtual function call (with
9386 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9387 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9388 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9389 relative to the resulting this pointer. */
9390
9391 static void
9392 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9393 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9394 tree function)
9395 {
9396 rtx op[10];
9397 int nonlocal = 0;
9398
9399 /* Make sure unwind info is emitted for the thunk if needed. */
9400 final_start_function (emit_barrier (), file, 1);
9401
9402 /* Operand 0 is the target function. */
9403 op[0] = XEXP (DECL_RTL (function), 0);
9404 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9405 {
9406 nonlocal = 1;
9407 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9408 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9409 op[0] = gen_rtx_CONST (Pmode, op[0]);
9410 }
9411
9412 /* Operand 1 is the 'this' pointer. */
9413 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9414 op[1] = gen_rtx_REG (Pmode, 3);
9415 else
9416 op[1] = gen_rtx_REG (Pmode, 2);
9417
9418 /* Operand 2 is the delta. */
9419 op[2] = GEN_INT (delta);
9420
9421 /* Operand 3 is the vcall_offset. */
9422 op[3] = GEN_INT (vcall_offset);
9423
9424 /* Operand 4 is the temporary register. */
9425 op[4] = gen_rtx_REG (Pmode, 1);
9426
9427 /* Operands 5 to 8 can be used as labels. */
9428 op[5] = NULL_RTX;
9429 op[6] = NULL_RTX;
9430 op[7] = NULL_RTX;
9431 op[8] = NULL_RTX;
9432
9433 /* Operand 9 can be used for temporary register. */
9434 op[9] = NULL_RTX;
9435
9436 /* Generate code. */
9437 if (TARGET_64BIT)
9438 {
9439 /* Setup literal pool pointer if required. */
9440 if ((!DISP_IN_RANGE (delta)
9441 && !CONST_OK_FOR_K (delta)
9442 && !CONST_OK_FOR_Os (delta))
9443 || (!DISP_IN_RANGE (vcall_offset)
9444 && !CONST_OK_FOR_K (vcall_offset)
9445 && !CONST_OK_FOR_Os (vcall_offset)))
9446 {
9447 op[5] = gen_label_rtx ();
9448 output_asm_insn ("larl\t%4,%5", op);
9449 }
9450
9451 /* Add DELTA to this pointer. */
9452 if (delta)
9453 {
9454 if (CONST_OK_FOR_J (delta))
9455 output_asm_insn ("la\t%1,%2(%1)", op);
9456 else if (DISP_IN_RANGE (delta))
9457 output_asm_insn ("lay\t%1,%2(%1)", op);
9458 else if (CONST_OK_FOR_K (delta))
9459 output_asm_insn ("aghi\t%1,%2", op);
9460 else if (CONST_OK_FOR_Os (delta))
9461 output_asm_insn ("agfi\t%1,%2", op);
9462 else
9463 {
9464 op[6] = gen_label_rtx ();
9465 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9466 }
9467 }
9468
9469 /* Perform vcall adjustment. */
9470 if (vcall_offset)
9471 {
9472 if (DISP_IN_RANGE (vcall_offset))
9473 {
9474 output_asm_insn ("lg\t%4,0(%1)", op);
9475 output_asm_insn ("ag\t%1,%3(%4)", op);
9476 }
9477 else if (CONST_OK_FOR_K (vcall_offset))
9478 {
9479 output_asm_insn ("lghi\t%4,%3", op);
9480 output_asm_insn ("ag\t%4,0(%1)", op);
9481 output_asm_insn ("ag\t%1,0(%4)", op);
9482 }
9483 else if (CONST_OK_FOR_Os (vcall_offset))
9484 {
9485 output_asm_insn ("lgfi\t%4,%3", op);
9486 output_asm_insn ("ag\t%4,0(%1)", op);
9487 output_asm_insn ("ag\t%1,0(%4)", op);
9488 }
9489 else
9490 {
9491 op[7] = gen_label_rtx ();
9492 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9493 output_asm_insn ("ag\t%4,0(%1)", op);
9494 output_asm_insn ("ag\t%1,0(%4)", op);
9495 }
9496 }
9497
9498 /* Jump to target. */
9499 output_asm_insn ("jg\t%0", op);
9500
9501 /* Output literal pool if required. */
9502 if (op[5])
9503 {
9504 output_asm_insn (".align\t4", op);
9505 targetm.asm_out.internal_label (file, "L",
9506 CODE_LABEL_NUMBER (op[5]));
9507 }
9508 if (op[6])
9509 {
9510 targetm.asm_out.internal_label (file, "L",
9511 CODE_LABEL_NUMBER (op[6]));
9512 output_asm_insn (".long\t%2", op);
9513 }
9514 if (op[7])
9515 {
9516 targetm.asm_out.internal_label (file, "L",
9517 CODE_LABEL_NUMBER (op[7]));
9518 output_asm_insn (".long\t%3", op);
9519 }
9520 }
9521 else
9522 {
9523 /* Setup base pointer if required. */
9524 if (!vcall_offset
9525 || (!DISP_IN_RANGE (delta)
9526 && !CONST_OK_FOR_K (delta)
9527 && !CONST_OK_FOR_Os (delta))
9528 || (!DISP_IN_RANGE (delta)
9529 && !CONST_OK_FOR_K (vcall_offset)
9530 && !CONST_OK_FOR_Os (vcall_offset)))
9531 {
9532 op[5] = gen_label_rtx ();
9533 output_asm_insn ("basr\t%4,0", op);
9534 targetm.asm_out.internal_label (file, "L",
9535 CODE_LABEL_NUMBER (op[5]));
9536 }
9537
9538 /* Add DELTA to this pointer. */
9539 if (delta)
9540 {
9541 if (CONST_OK_FOR_J (delta))
9542 output_asm_insn ("la\t%1,%2(%1)", op);
9543 else if (DISP_IN_RANGE (delta))
9544 output_asm_insn ("lay\t%1,%2(%1)", op);
9545 else if (CONST_OK_FOR_K (delta))
9546 output_asm_insn ("ahi\t%1,%2", op);
9547 else if (CONST_OK_FOR_Os (delta))
9548 output_asm_insn ("afi\t%1,%2", op);
9549 else
9550 {
9551 op[6] = gen_label_rtx ();
9552 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9553 }
9554 }
9555
9556 /* Perform vcall adjustment. */
9557 if (vcall_offset)
9558 {
9559 if (CONST_OK_FOR_J (vcall_offset))
9560 {
9561 output_asm_insn ("l\t%4,0(%1)", op);
9562 output_asm_insn ("a\t%1,%3(%4)", op);
9563 }
9564 else if (DISP_IN_RANGE (vcall_offset))
9565 {
9566 output_asm_insn ("l\t%4,0(%1)", op);
9567 output_asm_insn ("ay\t%1,%3(%4)", op);
9568 }
9569 else if (CONST_OK_FOR_K (vcall_offset))
9570 {
9571 output_asm_insn ("lhi\t%4,%3", op);
9572 output_asm_insn ("a\t%4,0(%1)", op);
9573 output_asm_insn ("a\t%1,0(%4)", op);
9574 }
9575 else if (CONST_OK_FOR_Os (vcall_offset))
9576 {
9577 output_asm_insn ("iilf\t%4,%3", op);
9578 output_asm_insn ("a\t%4,0(%1)", op);
9579 output_asm_insn ("a\t%1,0(%4)", op);
9580 }
9581 else
9582 {
9583 op[7] = gen_label_rtx ();
9584 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9585 output_asm_insn ("a\t%4,0(%1)", op);
9586 output_asm_insn ("a\t%1,0(%4)", op);
9587 }
9588
9589 /* We had to clobber the base pointer register.
9590 Re-setup the base pointer (with a different base). */
9591 op[5] = gen_label_rtx ();
9592 output_asm_insn ("basr\t%4,0", op);
9593 targetm.asm_out.internal_label (file, "L",
9594 CODE_LABEL_NUMBER (op[5]));
9595 }
9596
9597 /* Jump to target. */
9598 op[8] = gen_label_rtx ();
9599
9600 if (!flag_pic)
9601 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9602 else if (!nonlocal)
9603 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9604 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9605 else if (flag_pic == 1)
9606 {
9607 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9608 output_asm_insn ("l\t%4,%0(%4)", op);
9609 }
9610 else if (flag_pic == 2)
9611 {
9612 op[9] = gen_rtx_REG (Pmode, 0);
9613 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9614 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9615 output_asm_insn ("ar\t%4,%9", op);
9616 output_asm_insn ("l\t%4,0(%4)", op);
9617 }
9618
9619 output_asm_insn ("br\t%4", op);
9620
9621 /* Output literal pool. */
9622 output_asm_insn (".align\t4", op);
9623
9624 if (nonlocal && flag_pic == 2)
9625 output_asm_insn (".long\t%0", op);
9626 if (nonlocal)
9627 {
9628 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9629 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9630 }
9631
9632 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9633 if (!flag_pic)
9634 output_asm_insn (".long\t%0", op);
9635 else
9636 output_asm_insn (".long\t%0-%5", op);
9637
9638 if (op[6])
9639 {
9640 targetm.asm_out.internal_label (file, "L",
9641 CODE_LABEL_NUMBER (op[6]));
9642 output_asm_insn (".long\t%2", op);
9643 }
9644 if (op[7])
9645 {
9646 targetm.asm_out.internal_label (file, "L",
9647 CODE_LABEL_NUMBER (op[7]));
9648 output_asm_insn (".long\t%3", op);
9649 }
9650 }
9651 final_end_function ();
9652 }
9653
9654 static bool
9655 s390_valid_pointer_mode (enum machine_mode mode)
9656 {
9657 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9658 }
9659
9660 /* Checks whether the given CALL_EXPR would use a caller
9661 saved register. This is used to decide whether sibling call
9662 optimization could be performed on the respective function
9663 call. */
9664
9665 static bool
9666 s390_call_saved_register_used (tree call_expr)
9667 {
9668 CUMULATIVE_ARGS cum_v;
9669 cumulative_args_t cum;
9670 tree parameter;
9671 enum machine_mode mode;
9672 tree type;
9673 rtx parm_rtx;
9674 int reg, i;
9675
9676 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
9677 cum = pack_cumulative_args (&cum_v);
9678
9679 for (i = 0; i < call_expr_nargs (call_expr); i++)
9680 {
9681 parameter = CALL_EXPR_ARG (call_expr, i);
9682 gcc_assert (parameter);
9683
9684 /* For an undeclared variable passed as parameter we will get
9685 an ERROR_MARK node here. */
9686 if (TREE_CODE (parameter) == ERROR_MARK)
9687 return true;
9688
9689 type = TREE_TYPE (parameter);
9690 gcc_assert (type);
9691
9692 mode = TYPE_MODE (type);
9693 gcc_assert (mode);
9694
9695 if (pass_by_reference (&cum_v, mode, type, true))
9696 {
9697 mode = Pmode;
9698 type = build_pointer_type (type);
9699 }
9700
9701 parm_rtx = s390_function_arg (cum, mode, type, 0);
9702
9703 s390_function_arg_advance (cum, mode, type, 0);
9704
9705 if (!parm_rtx)
9706 continue;
9707
9708 if (REG_P (parm_rtx))
9709 {
9710 for (reg = 0;
9711 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9712 reg++)
9713 if (!call_used_regs[reg + REGNO (parm_rtx)])
9714 return true;
9715 }
9716
9717 if (GET_CODE (parm_rtx) == PARALLEL)
9718 {
9719 int i;
9720
9721 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9722 {
9723 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9724
9725 gcc_assert (REG_P (r));
9726
9727 for (reg = 0;
9728 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9729 reg++)
9730 if (!call_used_regs[reg + REGNO (r)])
9731 return true;
9732 }
9733 }
9734
9735 }
9736 return false;
9737 }
9738
9739 /* Return true if the given call expression can be
9740 turned into a sibling call.
9741 DECL holds the declaration of the function to be called whereas
9742 EXP is the call expression itself. */
9743
9744 static bool
9745 s390_function_ok_for_sibcall (tree decl, tree exp)
9746 {
9747 /* The TPF epilogue uses register 1. */
9748 if (TARGET_TPF_PROFILING)
9749 return false;
9750
9751 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9752 which would have to be restored before the sibcall. */
9753 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9754 return false;
9755
9756 /* Register 6 on s390 is available as an argument register but unfortunately
9757 "caller saved". This makes functions needing this register for arguments
9758 not suitable for sibcalls. */
9759 return !s390_call_saved_register_used (exp);
9760 }
9761
9762 /* Return the fixed registers used for condition codes. */
9763
9764 static bool
9765 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9766 {
9767 *p1 = CC_REGNUM;
9768 *p2 = INVALID_REGNUM;
9769
9770 return true;
9771 }
9772
9773 /* This function is used by the call expanders of the machine description.
9774 It emits the call insn itself together with the necessary operations
9775 to adjust the target address and returns the emitted insn.
9776 ADDR_LOCATION is the target address rtx
9777 TLS_CALL the location of the thread-local symbol
9778 RESULT_REG the register where the result of the call should be stored
9779 RETADDR_REG the register where the return address should be stored
9780 If this parameter is NULL_RTX the call is considered
9781 to be a sibling call. */
9782
9783 rtx
9784 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9785 rtx retaddr_reg)
9786 {
9787 bool plt_call = false;
9788 rtx insn;
9789 rtx call;
9790 rtx clobber;
9791 rtvec vec;
9792
9793 /* Direct function calls need special treatment. */
9794 if (GET_CODE (addr_location) == SYMBOL_REF)
9795 {
9796 /* When calling a global routine in PIC mode, we must
9797 replace the symbol itself with the PLT stub. */
9798 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9799 {
9800 if (retaddr_reg != NULL_RTX)
9801 {
9802 addr_location = gen_rtx_UNSPEC (Pmode,
9803 gen_rtvec (1, addr_location),
9804 UNSPEC_PLT);
9805 addr_location = gen_rtx_CONST (Pmode, addr_location);
9806 plt_call = true;
9807 }
9808 else
9809 /* For -fpic code the PLT entries might use r12 which is
9810 call-saved. Therefore we cannot do a sibcall when
9811 calling directly using a symbol ref. When reaching
9812 this point we decided (in s390_function_ok_for_sibcall)
9813 to do a sibcall for a function pointer but one of the
9814 optimizers was able to get rid of the function pointer
9815 by propagating the symbol ref into the call. This
9816 optimization is illegal for S/390 so we turn the direct
9817 call into a indirect call again. */
9818 addr_location = force_reg (Pmode, addr_location);
9819 }
9820
9821 /* Unless we can use the bras(l) insn, force the
9822 routine address into a register. */
9823 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9824 {
9825 if (flag_pic)
9826 addr_location = legitimize_pic_address (addr_location, 0);
9827 else
9828 addr_location = force_reg (Pmode, addr_location);
9829 }
9830 }
9831
9832 /* If it is already an indirect call or the code above moved the
9833 SYMBOL_REF to somewhere else make sure the address can be found in
9834 register 1. */
9835 if (retaddr_reg == NULL_RTX
9836 && GET_CODE (addr_location) != SYMBOL_REF
9837 && !plt_call)
9838 {
9839 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9840 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9841 }
9842
9843 addr_location = gen_rtx_MEM (QImode, addr_location);
9844 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9845
9846 if (result_reg != NULL_RTX)
9847 call = gen_rtx_SET (VOIDmode, result_reg, call);
9848
9849 if (retaddr_reg != NULL_RTX)
9850 {
9851 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9852
9853 if (tls_call != NULL_RTX)
9854 vec = gen_rtvec (3, call, clobber,
9855 gen_rtx_USE (VOIDmode, tls_call));
9856 else
9857 vec = gen_rtvec (2, call, clobber);
9858
9859 call = gen_rtx_PARALLEL (VOIDmode, vec);
9860 }
9861
9862 insn = emit_call_insn (call);
9863
9864 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9865 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9866 {
9867 /* s390_function_ok_for_sibcall should
9868 have denied sibcalls in this case. */
9869 gcc_assert (retaddr_reg != NULL_RTX);
9870 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
9871 }
9872 return insn;
9873 }
9874
9875 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9876
9877 static void
9878 s390_conditional_register_usage (void)
9879 {
9880 int i;
9881
9882 if (flag_pic)
9883 {
9884 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9885 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9886 }
9887 if (TARGET_CPU_ZARCH)
9888 {
9889 fixed_regs[BASE_REGNUM] = 0;
9890 call_used_regs[BASE_REGNUM] = 0;
9891 fixed_regs[RETURN_REGNUM] = 0;
9892 call_used_regs[RETURN_REGNUM] = 0;
9893 }
9894 if (TARGET_64BIT)
9895 {
9896 for (i = 24; i < 32; i++)
9897 call_used_regs[i] = call_really_used_regs[i] = 0;
9898 }
9899 else
9900 {
9901 for (i = 18; i < 20; i++)
9902 call_used_regs[i] = call_really_used_regs[i] = 0;
9903 }
9904
9905 if (TARGET_SOFT_FLOAT)
9906 {
9907 for (i = 16; i < 32; i++)
9908 call_used_regs[i] = fixed_regs[i] = 1;
9909 }
9910 }
9911
9912 /* Corresponding function to eh_return expander. */
9913
9914 static GTY(()) rtx s390_tpf_eh_return_symbol;
9915 void
9916 s390_emit_tpf_eh_return (rtx target)
9917 {
9918 rtx insn, reg;
9919
9920 if (!s390_tpf_eh_return_symbol)
9921 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9922
9923 reg = gen_rtx_REG (Pmode, 2);
9924
9925 emit_move_insn (reg, target);
9926 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9927 gen_rtx_REG (Pmode, RETURN_REGNUM));
9928 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9929
9930 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9931 }
9932
9933 /* Rework the prologue/epilogue to avoid saving/restoring
9934 registers unnecessarily. */
9935
9936 static void
9937 s390_optimize_prologue (void)
9938 {
9939 rtx insn, new_insn, next_insn;
9940
9941 /* Do a final recompute of the frame-related data. */
9942
9943 s390_update_frame_layout ();
9944
9945 /* If all special registers are in fact used, there's nothing we
9946 can do, so no point in walking the insn list. */
9947
9948 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9949 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9950 && (TARGET_CPU_ZARCH
9951 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9952 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9953 return;
9954
9955 /* Search for prologue/epilogue insns and replace them. */
9956
9957 for (insn = get_insns (); insn; insn = next_insn)
9958 {
9959 int first, last, off;
9960 rtx set, base, offset;
9961
9962 next_insn = NEXT_INSN (insn);
9963
9964 if (GET_CODE (insn) != INSN)
9965 continue;
9966
9967 if (GET_CODE (PATTERN (insn)) == PARALLEL
9968 && store_multiple_operation (PATTERN (insn), VOIDmode))
9969 {
9970 set = XVECEXP (PATTERN (insn), 0, 0);
9971 first = REGNO (SET_SRC (set));
9972 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9973 offset = const0_rtx;
9974 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9975 off = INTVAL (offset);
9976
9977 if (GET_CODE (base) != REG || off < 0)
9978 continue;
9979 if (cfun_frame_layout.first_save_gpr != -1
9980 && (cfun_frame_layout.first_save_gpr < first
9981 || cfun_frame_layout.last_save_gpr > last))
9982 continue;
9983 if (REGNO (base) != STACK_POINTER_REGNUM
9984 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9985 continue;
9986 if (first > BASE_REGNUM || last < BASE_REGNUM)
9987 continue;
9988
9989 if (cfun_frame_layout.first_save_gpr != -1)
9990 {
9991 new_insn = save_gprs (base,
9992 off + (cfun_frame_layout.first_save_gpr
9993 - first) * UNITS_PER_LONG,
9994 cfun_frame_layout.first_save_gpr,
9995 cfun_frame_layout.last_save_gpr);
9996 new_insn = emit_insn_before (new_insn, insn);
9997 INSN_ADDRESSES_NEW (new_insn, -1);
9998 }
9999
10000 remove_insn (insn);
10001 continue;
10002 }
10003
10004 if (cfun_frame_layout.first_save_gpr == -1
10005 && GET_CODE (PATTERN (insn)) == SET
10006 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10007 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10008 || (!TARGET_CPU_ZARCH
10009 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10010 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10011 {
10012 set = PATTERN (insn);
10013 first = REGNO (SET_SRC (set));
10014 offset = const0_rtx;
10015 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10016 off = INTVAL (offset);
10017
10018 if (GET_CODE (base) != REG || off < 0)
10019 continue;
10020 if (REGNO (base) != STACK_POINTER_REGNUM
10021 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10022 continue;
10023
10024 remove_insn (insn);
10025 continue;
10026 }
10027
10028 if (GET_CODE (PATTERN (insn)) == PARALLEL
10029 && load_multiple_operation (PATTERN (insn), VOIDmode))
10030 {
10031 set = XVECEXP (PATTERN (insn), 0, 0);
10032 first = REGNO (SET_DEST (set));
10033 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10034 offset = const0_rtx;
10035 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10036 off = INTVAL (offset);
10037
10038 if (GET_CODE (base) != REG || off < 0)
10039 continue;
10040 if (cfun_frame_layout.first_restore_gpr != -1
10041 && (cfun_frame_layout.first_restore_gpr < first
10042 || cfun_frame_layout.last_restore_gpr > last))
10043 continue;
10044 if (REGNO (base) != STACK_POINTER_REGNUM
10045 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10046 continue;
10047 if (first > BASE_REGNUM || last < BASE_REGNUM)
10048 continue;
10049
10050 if (cfun_frame_layout.first_restore_gpr != -1)
10051 {
10052 new_insn = restore_gprs (base,
10053 off + (cfun_frame_layout.first_restore_gpr
10054 - first) * UNITS_PER_LONG,
10055 cfun_frame_layout.first_restore_gpr,
10056 cfun_frame_layout.last_restore_gpr);
10057 new_insn = emit_insn_before (new_insn, insn);
10058 INSN_ADDRESSES_NEW (new_insn, -1);
10059 }
10060
10061 remove_insn (insn);
10062 continue;
10063 }
10064
10065 if (cfun_frame_layout.first_restore_gpr == -1
10066 && GET_CODE (PATTERN (insn)) == SET
10067 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10068 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10069 || (!TARGET_CPU_ZARCH
10070 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10071 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10072 {
10073 set = PATTERN (insn);
10074 first = REGNO (SET_DEST (set));
10075 offset = const0_rtx;
10076 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10077 off = INTVAL (offset);
10078
10079 if (GET_CODE (base) != REG || off < 0)
10080 continue;
10081 if (REGNO (base) != STACK_POINTER_REGNUM
10082 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10083 continue;
10084
10085 remove_insn (insn);
10086 continue;
10087 }
10088 }
10089 }
10090
10091 /* On z10 and later the dynamic branch prediction must see the
10092 backward jump within a certain windows. If not it falls back to
10093 the static prediction. This function rearranges the loop backward
10094 branch in a way which makes the static prediction always correct.
10095 The function returns true if it added an instruction. */
10096 static bool
10097 s390_fix_long_loop_prediction (rtx insn)
10098 {
10099 rtx set = single_set (insn);
10100 rtx code_label, label_ref, new_label;
10101 rtx uncond_jump;
10102 rtx cur_insn;
10103 rtx tmp;
10104 int distance;
10105
10106 /* This will exclude branch on count and branch on index patterns
10107 since these are correctly statically predicted. */
10108 if (!set
10109 || SET_DEST (set) != pc_rtx
10110 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10111 return false;
10112
10113 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10114 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10115
10116 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10117
10118 code_label = XEXP (label_ref, 0);
10119
10120 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10121 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10122 || (INSN_ADDRESSES (INSN_UID (insn))
10123 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10124 return false;
10125
10126 for (distance = 0, cur_insn = PREV_INSN (insn);
10127 distance < PREDICT_DISTANCE - 6;
10128 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10129 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10130 return false;
10131
10132 new_label = gen_label_rtx ();
10133 uncond_jump = emit_jump_insn_after (
10134 gen_rtx_SET (VOIDmode, pc_rtx,
10135 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10136 insn);
10137 emit_label_after (new_label, uncond_jump);
10138
10139 tmp = XEXP (SET_SRC (set), 1);
10140 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10141 XEXP (SET_SRC (set), 2) = tmp;
10142 INSN_CODE (insn) = -1;
10143
10144 XEXP (label_ref, 0) = new_label;
10145 JUMP_LABEL (insn) = new_label;
10146 JUMP_LABEL (uncond_jump) = code_label;
10147
10148 return true;
10149 }
10150
10151 /* Returns 1 if INSN reads the value of REG for purposes not related
10152 to addressing of memory, and 0 otherwise. */
10153 static int
10154 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10155 {
10156 return reg_referenced_p (reg, PATTERN (insn))
10157 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10158 }
10159
10160 /* Starting from INSN find_cond_jump looks downwards in the insn
10161 stream for a single jump insn which is the last user of the
10162 condition code set in INSN. */
10163 static rtx
10164 find_cond_jump (rtx insn)
10165 {
10166 for (; insn; insn = NEXT_INSN (insn))
10167 {
10168 rtx ite, cc;
10169
10170 if (LABEL_P (insn))
10171 break;
10172
10173 if (!JUMP_P (insn))
10174 {
10175 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10176 break;
10177 continue;
10178 }
10179
10180 /* This will be triggered by a return. */
10181 if (GET_CODE (PATTERN (insn)) != SET)
10182 break;
10183
10184 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10185 ite = SET_SRC (PATTERN (insn));
10186
10187 if (GET_CODE (ite) != IF_THEN_ELSE)
10188 break;
10189
10190 cc = XEXP (XEXP (ite, 0), 0);
10191 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10192 break;
10193
10194 if (find_reg_note (insn, REG_DEAD, cc))
10195 return insn;
10196 break;
10197 }
10198
10199 return NULL_RTX;
10200 }
10201
10202 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10203 the semantics does not change. If NULL_RTX is passed as COND the
10204 function tries to find the conditional jump starting with INSN. */
10205 static void
10206 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10207 {
10208 rtx tmp = *op0;
10209
10210 if (cond == NULL_RTX)
10211 {
10212 rtx jump = find_cond_jump (NEXT_INSN (insn));
10213 jump = jump ? single_set (jump) : NULL_RTX;
10214
10215 if (jump == NULL_RTX)
10216 return;
10217
10218 cond = XEXP (XEXP (jump, 1), 0);
10219 }
10220
10221 *op0 = *op1;
10222 *op1 = tmp;
10223 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10224 }
10225
10226 /* On z10, instructions of the compare-and-branch family have the
10227 property to access the register occurring as second operand with
10228 its bits complemented. If such a compare is grouped with a second
10229 instruction that accesses the same register non-complemented, and
10230 if that register's value is delivered via a bypass, then the
10231 pipeline recycles, thereby causing significant performance decline.
10232 This function locates such situations and exchanges the two
10233 operands of the compare. The function return true whenever it
10234 added an insn. */
10235 static bool
10236 s390_z10_optimize_cmp (rtx insn)
10237 {
10238 rtx prev_insn, next_insn;
10239 bool insn_added_p = false;
10240 rtx cond, *op0, *op1;
10241
10242 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10243 {
10244 /* Handle compare and branch and branch on count
10245 instructions. */
10246 rtx pattern = single_set (insn);
10247
10248 if (!pattern
10249 || SET_DEST (pattern) != pc_rtx
10250 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10251 return false;
10252
10253 cond = XEXP (SET_SRC (pattern), 0);
10254 op0 = &XEXP (cond, 0);
10255 op1 = &XEXP (cond, 1);
10256 }
10257 else if (GET_CODE (PATTERN (insn)) == SET)
10258 {
10259 rtx src, dest;
10260
10261 /* Handle normal compare instructions. */
10262 src = SET_SRC (PATTERN (insn));
10263 dest = SET_DEST (PATTERN (insn));
10264
10265 if (!REG_P (dest)
10266 || !CC_REGNO_P (REGNO (dest))
10267 || GET_CODE (src) != COMPARE)
10268 return false;
10269
10270 /* s390_swap_cmp will try to find the conditional
10271 jump when passing NULL_RTX as condition. */
10272 cond = NULL_RTX;
10273 op0 = &XEXP (src, 0);
10274 op1 = &XEXP (src, 1);
10275 }
10276 else
10277 return false;
10278
10279 if (!REG_P (*op0) || !REG_P (*op1))
10280 return false;
10281
10282 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10283 return false;
10284
10285 /* Swap the COMPARE arguments and its mask if there is a
10286 conflicting access in the previous insn. */
10287 prev_insn = prev_active_insn (insn);
10288 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10289 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10290 s390_swap_cmp (cond, op0, op1, insn);
10291
10292 /* Check if there is a conflict with the next insn. If there
10293 was no conflict with the previous insn, then swap the
10294 COMPARE arguments and its mask. If we already swapped
10295 the operands, or if swapping them would cause a conflict
10296 with the previous insn, issue a NOP after the COMPARE in
10297 order to separate the two instuctions. */
10298 next_insn = next_active_insn (insn);
10299 if (next_insn != NULL_RTX && INSN_P (next_insn)
10300 && s390_non_addr_reg_read_p (*op1, next_insn))
10301 {
10302 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10303 && s390_non_addr_reg_read_p (*op0, prev_insn))
10304 {
10305 if (REGNO (*op1) == 0)
10306 emit_insn_after (gen_nop1 (), insn);
10307 else
10308 emit_insn_after (gen_nop (), insn);
10309 insn_added_p = true;
10310 }
10311 else
10312 s390_swap_cmp (cond, op0, op1, insn);
10313 }
10314 return insn_added_p;
10315 }
10316
10317 /* Perform machine-dependent processing. */
10318
10319 static void
10320 s390_reorg (void)
10321 {
10322 bool pool_overflow = false;
10323
10324 /* Make sure all splits have been performed; splits after
10325 machine_dependent_reorg might confuse insn length counts. */
10326 split_all_insns_noflow ();
10327
10328 /* Install the main literal pool and the associated base
10329 register load insns.
10330
10331 In addition, there are two problematic situations we need
10332 to correct:
10333
10334 - the literal pool might be > 4096 bytes in size, so that
10335 some of its elements cannot be directly accessed
10336
10337 - a branch target might be > 64K away from the branch, so that
10338 it is not possible to use a PC-relative instruction.
10339
10340 To fix those, we split the single literal pool into multiple
10341 pool chunks, reloading the pool base register at various
10342 points throughout the function to ensure it always points to
10343 the pool chunk the following code expects, and / or replace
10344 PC-relative branches by absolute branches.
10345
10346 However, the two problems are interdependent: splitting the
10347 literal pool can move a branch further away from its target,
10348 causing the 64K limit to overflow, and on the other hand,
10349 replacing a PC-relative branch by an absolute branch means
10350 we need to put the branch target address into the literal
10351 pool, possibly causing it to overflow.
10352
10353 So, we loop trying to fix up both problems until we manage
10354 to satisfy both conditions at the same time. Note that the
10355 loop is guaranteed to terminate as every pass of the loop
10356 strictly decreases the total number of PC-relative branches
10357 in the function. (This is not completely true as there
10358 might be branch-over-pool insns introduced by chunkify_start.
10359 Those never need to be split however.) */
10360
10361 for (;;)
10362 {
10363 struct constant_pool *pool = NULL;
10364
10365 /* Collect the literal pool. */
10366 if (!pool_overflow)
10367 {
10368 pool = s390_mainpool_start ();
10369 if (!pool)
10370 pool_overflow = true;
10371 }
10372
10373 /* If literal pool overflowed, start to chunkify it. */
10374 if (pool_overflow)
10375 pool = s390_chunkify_start ();
10376
10377 /* Split out-of-range branches. If this has created new
10378 literal pool entries, cancel current chunk list and
10379 recompute it. zSeries machines have large branch
10380 instructions, so we never need to split a branch. */
10381 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10382 {
10383 if (pool_overflow)
10384 s390_chunkify_cancel (pool);
10385 else
10386 s390_mainpool_cancel (pool);
10387
10388 continue;
10389 }
10390
10391 /* If we made it up to here, both conditions are satisfied.
10392 Finish up literal pool related changes. */
10393 if (pool_overflow)
10394 s390_chunkify_finish (pool);
10395 else
10396 s390_mainpool_finish (pool);
10397
10398 /* We're done splitting branches. */
10399 cfun->machine->split_branches_pending_p = false;
10400 break;
10401 }
10402
10403 /* Generate out-of-pool execute target insns. */
10404 if (TARGET_CPU_ZARCH)
10405 {
10406 rtx insn, label, target;
10407
10408 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10409 {
10410 label = s390_execute_label (insn);
10411 if (!label)
10412 continue;
10413
10414 gcc_assert (label != const0_rtx);
10415
10416 target = emit_label (XEXP (label, 0));
10417 INSN_ADDRESSES_NEW (target, -1);
10418
10419 target = emit_insn (s390_execute_target (insn));
10420 INSN_ADDRESSES_NEW (target, -1);
10421 }
10422 }
10423
10424 /* Try to optimize prologue and epilogue further. */
10425 s390_optimize_prologue ();
10426
10427 /* Walk over the insns and do some >=z10 specific changes. */
10428 if (s390_tune == PROCESSOR_2097_Z10
10429 || s390_tune == PROCESSOR_2817_Z196)
10430 {
10431 rtx insn;
10432 bool insn_added_p = false;
10433
10434 /* The insn lengths and addresses have to be up to date for the
10435 following manipulations. */
10436 shorten_branches (get_insns ());
10437
10438 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10439 {
10440 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10441 continue;
10442
10443 if (JUMP_P (insn))
10444 insn_added_p |= s390_fix_long_loop_prediction (insn);
10445
10446 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10447 || GET_CODE (PATTERN (insn)) == SET)
10448 && s390_tune == PROCESSOR_2097_Z10)
10449 insn_added_p |= s390_z10_optimize_cmp (insn);
10450 }
10451
10452 /* Adjust branches if we added new instructions. */
10453 if (insn_added_p)
10454 shorten_branches (get_insns ());
10455 }
10456 }
10457
10458 /* Return true if INSN is a fp load insn writing register REGNO. */
10459 static inline bool
10460 s390_fpload_toreg (rtx insn, unsigned int regno)
10461 {
10462 rtx set;
10463 enum attr_type flag = s390_safe_attr_type (insn);
10464
10465 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10466 return false;
10467
10468 set = single_set (insn);
10469
10470 if (set == NULL_RTX)
10471 return false;
10472
10473 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10474 return false;
10475
10476 if (REGNO (SET_DEST (set)) != regno)
10477 return false;
10478
10479 return true;
10480 }
10481
10482 /* This value describes the distance to be avoided between an
10483 aritmetic fp instruction and an fp load writing the same register.
10484 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10485 fine but the exact value has to be avoided. Otherwise the FP
10486 pipeline will throw an exception causing a major penalty. */
10487 #define Z10_EARLYLOAD_DISTANCE 7
10488
10489 /* Rearrange the ready list in order to avoid the situation described
10490 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10491 moved to the very end of the ready list. */
10492 static void
10493 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10494 {
10495 unsigned int regno;
10496 int nready = *nready_p;
10497 rtx tmp;
10498 int i;
10499 rtx insn;
10500 rtx set;
10501 enum attr_type flag;
10502 int distance;
10503
10504 /* Skip DISTANCE - 1 active insns. */
10505 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10506 distance > 0 && insn != NULL_RTX;
10507 distance--, insn = prev_active_insn (insn))
10508 if (CALL_P (insn) || JUMP_P (insn))
10509 return;
10510
10511 if (insn == NULL_RTX)
10512 return;
10513
10514 set = single_set (insn);
10515
10516 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10517 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10518 return;
10519
10520 flag = s390_safe_attr_type (insn);
10521
10522 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10523 return;
10524
10525 regno = REGNO (SET_DEST (set));
10526 i = nready - 1;
10527
10528 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10529 i--;
10530
10531 if (!i)
10532 return;
10533
10534 tmp = ready[i];
10535 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10536 ready[0] = tmp;
10537 }
10538
10539 /* This function is called via hook TARGET_SCHED_REORDER before
10540 issuing one insn from list READY which contains *NREADYP entries.
10541 For target z10 it reorders load instructions to avoid early load
10542 conflicts in the floating point pipeline */
10543 static int
10544 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10545 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10546 {
10547 if (s390_tune == PROCESSOR_2097_Z10)
10548 if (reload_completed && *nreadyp > 1)
10549 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10550
10551 return s390_issue_rate ();
10552 }
10553
10554 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10555 the scheduler has issued INSN. It stores the last issued insn into
10556 last_scheduled_insn in order to make it available for
10557 s390_sched_reorder. */
10558 static int
10559 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10560 int verbose ATTRIBUTE_UNUSED,
10561 rtx insn, int more)
10562 {
10563 last_scheduled_insn = insn;
10564
10565 if (GET_CODE (PATTERN (insn)) != USE
10566 && GET_CODE (PATTERN (insn)) != CLOBBER)
10567 return more - 1;
10568 else
10569 return more;
10570 }
10571
10572 static void
10573 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10574 int verbose ATTRIBUTE_UNUSED,
10575 int max_ready ATTRIBUTE_UNUSED)
10576 {
10577 last_scheduled_insn = NULL_RTX;
10578 }
10579
10580 /* This function checks the whole of insn X for memory references. The
10581 function always returns zero because the framework it is called
10582 from would stop recursively analyzing the insn upon a return value
10583 other than zero. The real result of this function is updating
10584 counter variable MEM_COUNT. */
10585 static int
10586 check_dpu (rtx *x, unsigned *mem_count)
10587 {
10588 if (*x != NULL_RTX && MEM_P (*x))
10589 (*mem_count)++;
10590 return 0;
10591 }
10592
10593 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10594 a new number struct loop *loop should be unrolled if tuned for cpus with
10595 a built-in stride prefetcher.
10596 The loop is analyzed for memory accesses by calling check_dpu for
10597 each rtx of the loop. Depending on the loop_depth and the amount of
10598 memory accesses a new number <=nunroll is returned to improve the
10599 behaviour of the hardware prefetch unit. */
10600 static unsigned
10601 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10602 {
10603 basic_block *bbs;
10604 rtx insn;
10605 unsigned i;
10606 unsigned mem_count = 0;
10607
10608 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10609 return nunroll;
10610
10611 /* Count the number of memory references within the loop body. */
10612 bbs = get_loop_body (loop);
10613 for (i = 0; i < loop->num_nodes; i++)
10614 {
10615 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10616 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10617 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10618 }
10619 free (bbs);
10620
10621 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10622 if (mem_count == 0)
10623 return nunroll;
10624
10625 switch (loop_depth(loop))
10626 {
10627 case 1:
10628 return MIN (nunroll, 28 / mem_count);
10629 case 2:
10630 return MIN (nunroll, 22 / mem_count);
10631 default:
10632 return MIN (nunroll, 16 / mem_count);
10633 }
10634 }
10635
10636 /* Initialize GCC target structure. */
10637
10638 #undef TARGET_ASM_ALIGNED_HI_OP
10639 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10640 #undef TARGET_ASM_ALIGNED_DI_OP
10641 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10642 #undef TARGET_ASM_INTEGER
10643 #define TARGET_ASM_INTEGER s390_assemble_integer
10644
10645 #undef TARGET_ASM_OPEN_PAREN
10646 #define TARGET_ASM_OPEN_PAREN ""
10647
10648 #undef TARGET_ASM_CLOSE_PAREN
10649 #define TARGET_ASM_CLOSE_PAREN ""
10650
10651 #undef TARGET_OPTION_OVERRIDE
10652 #define TARGET_OPTION_OVERRIDE s390_option_override
10653
10654 #undef TARGET_ENCODE_SECTION_INFO
10655 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10656
10657 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10658 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10659
10660 #ifdef HAVE_AS_TLS
10661 #undef TARGET_HAVE_TLS
10662 #define TARGET_HAVE_TLS true
10663 #endif
10664 #undef TARGET_CANNOT_FORCE_CONST_MEM
10665 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10666
10667 #undef TARGET_DELEGITIMIZE_ADDRESS
10668 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10669
10670 #undef TARGET_LEGITIMIZE_ADDRESS
10671 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10672
10673 #undef TARGET_RETURN_IN_MEMORY
10674 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10675
10676 #undef TARGET_INIT_BUILTINS
10677 #define TARGET_INIT_BUILTINS s390_init_builtins
10678 #undef TARGET_EXPAND_BUILTIN
10679 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10680
10681 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10682 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10683
10684 #undef TARGET_ASM_OUTPUT_MI_THUNK
10685 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10686 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10687 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10688
10689 #undef TARGET_SCHED_ADJUST_PRIORITY
10690 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10691 #undef TARGET_SCHED_ISSUE_RATE
10692 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10693 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10694 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10695
10696 #undef TARGET_SCHED_VARIABLE_ISSUE
10697 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10698 #undef TARGET_SCHED_REORDER
10699 #define TARGET_SCHED_REORDER s390_sched_reorder
10700 #undef TARGET_SCHED_INIT
10701 #define TARGET_SCHED_INIT s390_sched_init
10702
10703 #undef TARGET_CANNOT_COPY_INSN_P
10704 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10705 #undef TARGET_RTX_COSTS
10706 #define TARGET_RTX_COSTS s390_rtx_costs
10707 #undef TARGET_ADDRESS_COST
10708 #define TARGET_ADDRESS_COST s390_address_cost
10709 #undef TARGET_REGISTER_MOVE_COST
10710 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10711 #undef TARGET_MEMORY_MOVE_COST
10712 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10713
10714 #undef TARGET_MACHINE_DEPENDENT_REORG
10715 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10716
10717 #undef TARGET_VALID_POINTER_MODE
10718 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10719
10720 #undef TARGET_BUILD_BUILTIN_VA_LIST
10721 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10722 #undef TARGET_EXPAND_BUILTIN_VA_START
10723 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10724 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10725 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10726
10727 #undef TARGET_PROMOTE_FUNCTION_MODE
10728 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10729 #undef TARGET_PASS_BY_REFERENCE
10730 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10731
10732 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10733 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10734 #undef TARGET_FUNCTION_ARG
10735 #define TARGET_FUNCTION_ARG s390_function_arg
10736 #undef TARGET_FUNCTION_ARG_ADVANCE
10737 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10738 #undef TARGET_FUNCTION_VALUE
10739 #define TARGET_FUNCTION_VALUE s390_function_value
10740 #undef TARGET_LIBCALL_VALUE
10741 #define TARGET_LIBCALL_VALUE s390_libcall_value
10742
10743 #undef TARGET_FIXED_CONDITION_CODE_REGS
10744 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10745
10746 #undef TARGET_CC_MODES_COMPATIBLE
10747 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10748
10749 #undef TARGET_INVALID_WITHIN_DOLOOP
10750 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10751
10752 #ifdef HAVE_AS_TLS
10753 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10754 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10755 #endif
10756
10757 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10758 #undef TARGET_MANGLE_TYPE
10759 #define TARGET_MANGLE_TYPE s390_mangle_type
10760 #endif
10761
10762 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10763 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10764
10765 #undef TARGET_PREFERRED_RELOAD_CLASS
10766 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10767
10768 #undef TARGET_SECONDARY_RELOAD
10769 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10770
10771 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10772 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10773
10774 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10775 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10776
10777 #undef TARGET_LEGITIMATE_ADDRESS_P
10778 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10779
10780 #undef TARGET_LEGITIMATE_CONSTANT_P
10781 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
10782
10783 #undef TARGET_CAN_ELIMINATE
10784 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10785
10786 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10787 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10788
10789 #undef TARGET_LOOP_UNROLL_ADJUST
10790 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10791
10792 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10793 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10794 #undef TARGET_TRAMPOLINE_INIT
10795 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10796
10797 #undef TARGET_UNWIND_WORD_MODE
10798 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10799
10800 struct gcc_target targetm = TARGET_INITIALIZER;
10801
10802 #include "gt-s390.h"