projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
s390.c (s390_option_override): Disable DWARF 3/4 extensions for TPF, unless specifica...
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48 #include "debug.h"
49 #include "langhooks.h"
50 #include "optabs.h"
51 #include "gimple.h"
52 #include "df.h"
53 #include "params.h"
54 #include "cfgloop.h"
55 #include "opts.h"
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (1) , /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (1), /* MADBR */
213 COSTS_N_INSNS (1), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 static const
225 struct processor_costs z196_cost =
226 {
227 COSTS_N_INSNS (7), /* M */
228 COSTS_N_INSNS (5), /* MGHI */
229 COSTS_N_INSNS (5), /* MH */
230 COSTS_N_INSNS (5), /* MHI */
231 COSTS_N_INSNS (7), /* ML */
232 COSTS_N_INSNS (7), /* MR */
233 COSTS_N_INSNS (6), /* MS */
234 COSTS_N_INSNS (8), /* MSG */
235 COSTS_N_INSNS (6), /* MSGF */
236 COSTS_N_INSNS (6), /* MSGFR */
237 COSTS_N_INSNS (8), /* MSGR */
238 COSTS_N_INSNS (6), /* MSR */
239 COSTS_N_INSNS (1) , /* multiplication in DFmode */
240 COSTS_N_INSNS (40), /* MXBR B+40 */
241 COSTS_N_INSNS (100), /* SQXBR B+100 */
242 COSTS_N_INSNS (42), /* SQDBR B+42 */
243 COSTS_N_INSNS (28), /* SQEBR B+28 */
244 COSTS_N_INSNS (1), /* MADBR B */
245 COSTS_N_INSNS (1), /* MAEBR B */
246 COSTS_N_INSNS (101), /* DXBR B+101 */
247 COSTS_N_INSNS (29), /* DDBR */
248 COSTS_N_INSNS (22), /* DEBR */
249 COSTS_N_INSNS (160), /* DLGR cracked */
250 COSTS_N_INSNS (160), /* DLR cracked */
251 COSTS_N_INSNS (160), /* DR expanded */
252 COSTS_N_INSNS (160), /* DSGFR cracked */
253 COSTS_N_INSNS (160), /* DSGR cracked */
254 };
255
256 extern int reload_completed;
257
258 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
259 static rtx last_scheduled_insn;
260
261 /* Structure used to hold the components of a S/390 memory
262 address. A legitimate address on S/390 is of the general
263 form
264 base + index + displacement
265 where any of the components is optional.
266
267 base and index are registers of the class ADDR_REGS,
268 displacement is an unsigned 12-bit immediate constant. */
269
270 struct s390_address
271 {
272 rtx base;
273 rtx indx;
274 rtx disp;
275 bool pointer;
276 bool literal_pool;
277 };
278
279 /* The following structure is embedded in the machine
280 specific part of struct function. */
281
282 struct GTY (()) s390_frame_layout
283 {
284 /* Offset within stack frame. */
285 HOST_WIDE_INT gprs_offset;
286 HOST_WIDE_INT f0_offset;
287 HOST_WIDE_INT f4_offset;
288 HOST_WIDE_INT f8_offset;
289 HOST_WIDE_INT backchain_offset;
290
291 /* Number of first and last gpr where slots in the register
292 save area are reserved for. */
293 int first_save_gpr_slot;
294 int last_save_gpr_slot;
295
296 /* Number of first and last gpr to be saved, restored. */
297 int first_save_gpr;
298 int first_restore_gpr;
299 int last_save_gpr;
300 int last_restore_gpr;
301
302 /* Bits standing for floating point registers. Set, if the
303 respective register has to be saved. Starting with reg 16 (f0)
304 at the rightmost bit.
305 Bit 15 - 8 7 6 5 4 3 2 1 0
306 fpr 15 - 8 7 5 3 1 6 4 2 0
307 reg 31 - 24 23 22 21 20 19 18 17 16 */
308 unsigned int fpr_bitmap;
309
310 /* Number of floating point registers f8-f15 which must be saved. */
311 int high_fprs;
312
313 /* Set if return address needs to be saved.
314 This flag is set by s390_return_addr_rtx if it could not use
315 the initial value of r14 and therefore depends on r14 saved
316 to the stack. */
317 bool save_return_addr_p;
318
319 /* Size of stack frame. */
320 HOST_WIDE_INT frame_size;
321 };
322
323 /* Define the structure for the machine field in struct function. */
324
325 struct GTY(()) machine_function
326 {
327 struct s390_frame_layout frame_layout;
328
329 /* Literal pool base register. */
330 rtx base_reg;
331
332 /* True if we may need to perform branch splitting. */
333 bool split_branches_pending_p;
334
335 /* Some local-dynamic TLS symbol name. */
336 const char *some_ld_name;
337
338 bool has_landing_pad_p;
339 };
340
341 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
342
343 #define cfun_frame_layout (cfun->machine->frame_layout)
344 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
345 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
346 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
347 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
348 (1 << (BITNUM)))
349 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
350 (1 << (BITNUM))))
351
352 /* Number of GPRs and FPRs used for argument passing. */
353 #define GP_ARG_NUM_REG 5
354 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
355
356 /* A couple of shortcuts. */
357 #define CONST_OK_FOR_J(x) \
358 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
359 #define CONST_OK_FOR_K(x) \
360 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
361 #define CONST_OK_FOR_Os(x) \
362 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
363 #define CONST_OK_FOR_Op(x) \
364 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
365 #define CONST_OK_FOR_On(x) \
366 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
367
368 #define REGNO_PAIR_OK(REGNO, MODE) \
369 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
370
371 /* That's the read ahead of the dynamic branch prediction unit in
372 bytes on a z10 (or higher) CPU. */
373 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
374
375 /* Return the alignment for LABEL. We default to the -falign-labels
376 value except for the literal pool base label. */
377 int
378 s390_label_align (rtx label)
379 {
380 rtx prev_insn = prev_active_insn (label);
381
382 if (prev_insn == NULL_RTX)
383 goto old;
384
385 prev_insn = single_set (prev_insn);
386
387 if (prev_insn == NULL_RTX)
388 goto old;
389
390 prev_insn = SET_SRC (prev_insn);
391
392 /* Don't align literal pool base labels. */
393 if (GET_CODE (prev_insn) == UNSPEC
394 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
395 return 0;
396
397 old:
398 return align_labels_log;
399 }
400
401 static enum machine_mode
402 s390_libgcc_cmp_return_mode (void)
403 {
404 return TARGET_64BIT ? DImode : SImode;
405 }
406
407 static enum machine_mode
408 s390_libgcc_shift_count_mode (void)
409 {
410 return TARGET_64BIT ? DImode : SImode;
411 }
412
413 static enum machine_mode
414 s390_unwind_word_mode (void)
415 {
416 return TARGET_64BIT ? DImode : SImode;
417 }
418
419 /* Return true if the back end supports mode MODE. */
420 static bool
421 s390_scalar_mode_supported_p (enum machine_mode mode)
422 {
423 /* In contrast to the default implementation reject TImode constants on 31bit
424 TARGET_ZARCH for ABI compliance. */
425 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
426 return false;
427
428 if (DECIMAL_FLOAT_MODE_P (mode))
429 return default_decimal_float_supported_p ();
430
431 return default_scalar_mode_supported_p (mode);
432 }
433
434 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
435
436 void
437 s390_set_has_landing_pad_p (bool value)
438 {
439 cfun->machine->has_landing_pad_p = value;
440 }
441
442 /* If two condition code modes are compatible, return a condition code
443 mode which is compatible with both. Otherwise, return
444 VOIDmode. */
445
446 static enum machine_mode
447 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
448 {
449 if (m1 == m2)
450 return m1;
451
452 switch (m1)
453 {
454 case CCZmode:
455 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
456 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
457 return m2;
458 return VOIDmode;
459
460 case CCSmode:
461 case CCUmode:
462 case CCTmode:
463 case CCSRmode:
464 case CCURmode:
465 case CCZ1mode:
466 if (m2 == CCZmode)
467 return m1;
468
469 return VOIDmode;
470
471 default:
472 return VOIDmode;
473 }
474 return VOIDmode;
475 }
476
477 /* Return true if SET either doesn't set the CC register, or else
478 the source and destination have matching CC modes and that
479 CC mode is at least as constrained as REQ_MODE. */
480
481 static bool
482 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
483 {
484 enum machine_mode set_mode;
485
486 gcc_assert (GET_CODE (set) == SET);
487
488 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
489 return 1;
490
491 set_mode = GET_MODE (SET_DEST (set));
492 switch (set_mode)
493 {
494 case CCSmode:
495 case CCSRmode:
496 case CCUmode:
497 case CCURmode:
498 case CCLmode:
499 case CCL1mode:
500 case CCL2mode:
501 case CCL3mode:
502 case CCT1mode:
503 case CCT2mode:
504 case CCT3mode:
505 if (req_mode != set_mode)
506 return 0;
507 break;
508
509 case CCZmode:
510 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
511 && req_mode != CCSRmode && req_mode != CCURmode)
512 return 0;
513 break;
514
515 case CCAPmode:
516 case CCANmode:
517 if (req_mode != CCAmode)
518 return 0;
519 break;
520
521 default:
522 gcc_unreachable ();
523 }
524
525 return (GET_MODE (SET_SRC (set)) == set_mode);
526 }
527
528 /* Return true if every SET in INSN that sets the CC register
529 has source and destination with matching CC modes and that
530 CC mode is at least as constrained as REQ_MODE.
531 If REQ_MODE is VOIDmode, always return false. */
532
533 bool
534 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
535 {
536 int i;
537
538 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
539 if (req_mode == VOIDmode)
540 return false;
541
542 if (GET_CODE (PATTERN (insn)) == SET)
543 return s390_match_ccmode_set (PATTERN (insn), req_mode);
544
545 if (GET_CODE (PATTERN (insn)) == PARALLEL)
546 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
547 {
548 rtx set = XVECEXP (PATTERN (insn), 0, i);
549 if (GET_CODE (set) == SET)
550 if (!s390_match_ccmode_set (set, req_mode))
551 return false;
552 }
553
554 return true;
555 }
556
557 /* If a test-under-mask instruction can be used to implement
558 (compare (and ... OP1) OP2), return the CC mode required
559 to do that. Otherwise, return VOIDmode.
560 MIXED is true if the instruction can distinguish between
561 CC1 and CC2 for mixed selected bits (TMxx), it is false
562 if the instruction cannot (TM). */
563
564 enum machine_mode
565 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
566 {
567 int bit0, bit1;
568
569 /* ??? Fixme: should work on CONST_DOUBLE as well. */
570 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
571 return VOIDmode;
572
573 /* Selected bits all zero: CC0.
574 e.g.: int a; if ((a & (16 + 128)) == 0) */
575 if (INTVAL (op2) == 0)
576 return CCTmode;
577
578 /* Selected bits all one: CC3.
579 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
580 if (INTVAL (op2) == INTVAL (op1))
581 return CCT3mode;
582
583 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
584 int a;
585 if ((a & (16 + 128)) == 16) -> CCT1
586 if ((a & (16 + 128)) == 128) -> CCT2 */
587 if (mixed)
588 {
589 bit1 = exact_log2 (INTVAL (op2));
590 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
591 if (bit0 != -1 && bit1 != -1)
592 return bit0 > bit1 ? CCT1mode : CCT2mode;
593 }
594
595 return VOIDmode;
596 }
597
598 /* Given a comparison code OP (EQ, NE, etc.) and the operands
599 OP0 and OP1 of a COMPARE, return the mode to be used for the
600 comparison. */
601
602 enum machine_mode
603 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
604 {
605 switch (code)
606 {
607 case EQ:
608 case NE:
609 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
610 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
611 return CCAPmode;
612 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
613 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
614 return CCAPmode;
615 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
616 || GET_CODE (op1) == NEG)
617 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
618 return CCLmode;
619
620 if (GET_CODE (op0) == AND)
621 {
622 /* Check whether we can potentially do it via TM. */
623 enum machine_mode ccmode;
624 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
625 if (ccmode != VOIDmode)
626 {
627 /* Relax CCTmode to CCZmode to allow fall-back to AND
628 if that turns out to be beneficial. */
629 return ccmode == CCTmode ? CCZmode : ccmode;
630 }
631 }
632
633 if (register_operand (op0, HImode)
634 && GET_CODE (op1) == CONST_INT
635 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
636 return CCT3mode;
637 if (register_operand (op0, QImode)
638 && GET_CODE (op1) == CONST_INT
639 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
640 return CCT3mode;
641
642 return CCZmode;
643
644 case LE:
645 case LT:
646 case GE:
647 case GT:
648 /* The only overflow condition of NEG and ABS happens when
649 -INT_MAX is used as parameter, which stays negative. So
650 we have an overflow from a positive value to a negative.
651 Using CCAP mode the resulting cc can be used for comparisons. */
652 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
653 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
654 return CCAPmode;
655
656 /* If constants are involved in an add instruction it is possible to use
657 the resulting cc for comparisons with zero. Knowing the sign of the
658 constant the overflow behavior gets predictable. e.g.:
659 int a, b; if ((b = a + c) > 0)
660 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
661 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
662 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
663 {
664 if (INTVAL (XEXP((op0), 1)) < 0)
665 return CCANmode;
666 else
667 return CCAPmode;
668 }
669 /* Fall through. */
670 case UNORDERED:
671 case ORDERED:
672 case UNEQ:
673 case UNLE:
674 case UNLT:
675 case UNGE:
676 case UNGT:
677 case LTGT:
678 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
679 && GET_CODE (op1) != CONST_INT)
680 return CCSRmode;
681 return CCSmode;
682
683 case LTU:
684 case GEU:
685 if (GET_CODE (op0) == PLUS
686 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
687 return CCL1mode;
688
689 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
690 && GET_CODE (op1) != CONST_INT)
691 return CCURmode;
692 return CCUmode;
693
694 case LEU:
695 case GTU:
696 if (GET_CODE (op0) == MINUS
697 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
698 return CCL2mode;
699
700 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
701 && GET_CODE (op1) != CONST_INT)
702 return CCURmode;
703 return CCUmode;
704
705 default:
706 gcc_unreachable ();
707 }
708 }
709
710 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
711 that we can implement more efficiently. */
712
713 void
714 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
715 {
716 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
717 if ((*code == EQ || *code == NE)
718 && *op1 == const0_rtx
719 && GET_CODE (*op0) == ZERO_EXTRACT
720 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
721 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
722 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
723 {
724 rtx inner = XEXP (*op0, 0);
725 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
726 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
727 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
728
729 if (len > 0 && len < modesize
730 && pos >= 0 && pos + len <= modesize
731 && modesize <= HOST_BITS_PER_WIDE_INT)
732 {
733 unsigned HOST_WIDE_INT block;
734 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
735 block <<= modesize - pos - len;
736
737 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
738 gen_int_mode (block, GET_MODE (inner)));
739 }
740 }
741
742 /* Narrow AND of memory against immediate to enable TM. */
743 if ((*code == EQ || *code == NE)
744 && *op1 == const0_rtx
745 && GET_CODE (*op0) == AND
746 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
747 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
748 {
749 rtx inner = XEXP (*op0, 0);
750 rtx mask = XEXP (*op0, 1);
751
752 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
753 if (GET_CODE (inner) == SUBREG
754 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
755 && (GET_MODE_SIZE (GET_MODE (inner))
756 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
757 && ((INTVAL (mask)
758 & GET_MODE_MASK (GET_MODE (inner))
759 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
760 == 0))
761 inner = SUBREG_REG (inner);
762
763 /* Do not change volatile MEMs. */
764 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
765 {
766 int part = s390_single_part (XEXP (*op0, 1),
767 GET_MODE (inner), QImode, 0);
768 if (part >= 0)
769 {
770 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
771 inner = adjust_address_nv (inner, QImode, part);
772 *op0 = gen_rtx_AND (QImode, inner, mask);
773 }
774 }
775 }
776
777 /* Narrow comparisons against 0xffff to HImode if possible. */
778 if ((*code == EQ || *code == NE)
779 && GET_CODE (*op1) == CONST_INT
780 && INTVAL (*op1) == 0xffff
781 && SCALAR_INT_MODE_P (GET_MODE (*op0))
782 && (nonzero_bits (*op0, GET_MODE (*op0))
783 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
784 {
785 *op0 = gen_lowpart (HImode, *op0);
786 *op1 = constm1_rtx;
787 }
788
789 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
790 if (GET_CODE (*op0) == UNSPEC
791 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
792 && XVECLEN (*op0, 0) == 1
793 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
794 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
795 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
796 && *op1 == const0_rtx)
797 {
798 enum rtx_code new_code = UNKNOWN;
799 switch (*code)
800 {
801 case EQ: new_code = EQ; break;
802 case NE: new_code = NE; break;
803 case LT: new_code = GTU; break;
804 case GT: new_code = LTU; break;
805 case LE: new_code = GEU; break;
806 case GE: new_code = LEU; break;
807 default: break;
808 }
809
810 if (new_code != UNKNOWN)
811 {
812 *op0 = XVECEXP (*op0, 0, 0);
813 *code = new_code;
814 }
815 }
816
817 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
818 if (GET_CODE (*op0) == UNSPEC
819 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
820 && XVECLEN (*op0, 0) == 1
821 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
822 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
823 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
824 && *op1 == const0_rtx)
825 {
826 enum rtx_code new_code = UNKNOWN;
827 switch (*code)
828 {
829 case EQ: new_code = EQ; break;
830 case NE: new_code = NE; break;
831 default: break;
832 }
833
834 if (new_code != UNKNOWN)
835 {
836 *op0 = XVECEXP (*op0, 0, 0);
837 *code = new_code;
838 }
839 }
840
841 /* Simplify cascaded EQ, NE with const0_rtx. */
842 if ((*code == NE || *code == EQ)
843 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
844 && GET_MODE (*op0) == SImode
845 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
846 && REG_P (XEXP (*op0, 0))
847 && XEXP (*op0, 1) == const0_rtx
848 && *op1 == const0_rtx)
849 {
850 if ((*code == EQ && GET_CODE (*op0) == NE)
851 || (*code == NE && GET_CODE (*op0) == EQ))
852 *code = EQ;
853 else
854 *code = NE;
855 *op0 = XEXP (*op0, 0);
856 }
857
858 /* Prefer register over memory as first operand. */
859 if (MEM_P (*op0) && REG_P (*op1))
860 {
861 rtx tem = *op0; *op0 = *op1; *op1 = tem;
862 *code = swap_condition (*code);
863 }
864 }
865
866 /* Emit a compare instruction suitable to implement the comparison
867 OP0 CODE OP1. Return the correct condition RTL to be placed in
868 the IF_THEN_ELSE of the conditional branch testing the result. */
869
870 rtx
871 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
872 {
873 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
874 rtx cc;
875
876 /* Do not output a redundant compare instruction if a compare_and_swap
877 pattern already computed the result and the machine modes are compatible. */
878 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
879 {
880 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
881 == GET_MODE (op0));
882 cc = op0;
883 }
884 else
885 {
886 cc = gen_rtx_REG (mode, CC_REGNUM);
887 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
888 }
889
890 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
891 }
892
893 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
894 matches CMP.
895 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
896 conditional branch testing the result. */
897
898 static rtx
899 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
900 {
901 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
902 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
903 }
904
905 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
906 unconditional jump, else a conditional jump under condition COND. */
907
908 void
909 s390_emit_jump (rtx target, rtx cond)
910 {
911 rtx insn;
912
913 target = gen_rtx_LABEL_REF (VOIDmode, target);
914 if (cond)
915 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
916
917 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
918 emit_jump_insn (insn);
919 }
920
921 /* Return branch condition mask to implement a branch
922 specified by CODE. Return -1 for invalid comparisons. */
923
924 int
925 s390_branch_condition_mask (rtx code)
926 {
927 const int CC0 = 1 << 3;
928 const int CC1 = 1 << 2;
929 const int CC2 = 1 << 1;
930 const int CC3 = 1 << 0;
931
932 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
933 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
934 gcc_assert (XEXP (code, 1) == const0_rtx);
935
936 switch (GET_MODE (XEXP (code, 0)))
937 {
938 case CCZmode:
939 case CCZ1mode:
940 switch (GET_CODE (code))
941 {
942 case EQ: return CC0;
943 case NE: return CC1 | CC2 | CC3;
944 default: return -1;
945 }
946 break;
947
948 case CCT1mode:
949 switch (GET_CODE (code))
950 {
951 case EQ: return CC1;
952 case NE: return CC0 | CC2 | CC3;
953 default: return -1;
954 }
955 break;
956
957 case CCT2mode:
958 switch (GET_CODE (code))
959 {
960 case EQ: return CC2;
961 case NE: return CC0 | CC1 | CC3;
962 default: return -1;
963 }
964 break;
965
966 case CCT3mode:
967 switch (GET_CODE (code))
968 {
969 case EQ: return CC3;
970 case NE: return CC0 | CC1 | CC2;
971 default: return -1;
972 }
973 break;
974
975 case CCLmode:
976 switch (GET_CODE (code))
977 {
978 case EQ: return CC0 | CC2;
979 case NE: return CC1 | CC3;
980 default: return -1;
981 }
982 break;
983
984 case CCL1mode:
985 switch (GET_CODE (code))
986 {
987 case LTU: return CC2 | CC3; /* carry */
988 case GEU: return CC0 | CC1; /* no carry */
989 default: return -1;
990 }
991 break;
992
993 case CCL2mode:
994 switch (GET_CODE (code))
995 {
996 case GTU: return CC0 | CC1; /* borrow */
997 case LEU: return CC2 | CC3; /* no borrow */
998 default: return -1;
999 }
1000 break;
1001
1002 case CCL3mode:
1003 switch (GET_CODE (code))
1004 {
1005 case EQ: return CC0 | CC2;
1006 case NE: return CC1 | CC3;
1007 case LTU: return CC1;
1008 case GTU: return CC3;
1009 case LEU: return CC1 | CC2;
1010 case GEU: return CC2 | CC3;
1011 default: return -1;
1012 }
1013
1014 case CCUmode:
1015 switch (GET_CODE (code))
1016 {
1017 case EQ: return CC0;
1018 case NE: return CC1 | CC2 | CC3;
1019 case LTU: return CC1;
1020 case GTU: return CC2;
1021 case LEU: return CC0 | CC1;
1022 case GEU: return CC0 | CC2;
1023 default: return -1;
1024 }
1025 break;
1026
1027 case CCURmode:
1028 switch (GET_CODE (code))
1029 {
1030 case EQ: return CC0;
1031 case NE: return CC2 | CC1 | CC3;
1032 case LTU: return CC2;
1033 case GTU: return CC1;
1034 case LEU: return CC0 | CC2;
1035 case GEU: return CC0 | CC1;
1036 default: return -1;
1037 }
1038 break;
1039
1040 case CCAPmode:
1041 switch (GET_CODE (code))
1042 {
1043 case EQ: return CC0;
1044 case NE: return CC1 | CC2 | CC3;
1045 case LT: return CC1 | CC3;
1046 case GT: return CC2;
1047 case LE: return CC0 | CC1 | CC3;
1048 case GE: return CC0 | CC2;
1049 default: return -1;
1050 }
1051 break;
1052
1053 case CCANmode:
1054 switch (GET_CODE (code))
1055 {
1056 case EQ: return CC0;
1057 case NE: return CC1 | CC2 | CC3;
1058 case LT: return CC1;
1059 case GT: return CC2 | CC3;
1060 case LE: return CC0 | CC1;
1061 case GE: return CC0 | CC2 | CC3;
1062 default: return -1;
1063 }
1064 break;
1065
1066 case CCSmode:
1067 switch (GET_CODE (code))
1068 {
1069 case EQ: return CC0;
1070 case NE: return CC1 | CC2 | CC3;
1071 case LT: return CC1;
1072 case GT: return CC2;
1073 case LE: return CC0 | CC1;
1074 case GE: return CC0 | CC2;
1075 case UNORDERED: return CC3;
1076 case ORDERED: return CC0 | CC1 | CC2;
1077 case UNEQ: return CC0 | CC3;
1078 case UNLT: return CC1 | CC3;
1079 case UNGT: return CC2 | CC3;
1080 case UNLE: return CC0 | CC1 | CC3;
1081 case UNGE: return CC0 | CC2 | CC3;
1082 case LTGT: return CC1 | CC2;
1083 default: return -1;
1084 }
1085 break;
1086
1087 case CCSRmode:
1088 switch (GET_CODE (code))
1089 {
1090 case EQ: return CC0;
1091 case NE: return CC2 | CC1 | CC3;
1092 case LT: return CC2;
1093 case GT: return CC1;
1094 case LE: return CC0 | CC2;
1095 case GE: return CC0 | CC1;
1096 case UNORDERED: return CC3;
1097 case ORDERED: return CC0 | CC2 | CC1;
1098 case UNEQ: return CC0 | CC3;
1099 case UNLT: return CC2 | CC3;
1100 case UNGT: return CC1 | CC3;
1101 case UNLE: return CC0 | CC2 | CC3;
1102 case UNGE: return CC0 | CC1 | CC3;
1103 case LTGT: return CC2 | CC1;
1104 default: return -1;
1105 }
1106 break;
1107
1108 default:
1109 return -1;
1110 }
1111 }
1112
1113
1114 /* Return branch condition mask to implement a compare and branch
1115 specified by CODE. Return -1 for invalid comparisons. */
1116
1117 int
1118 s390_compare_and_branch_condition_mask (rtx code)
1119 {
1120 const int CC0 = 1 << 3;
1121 const int CC1 = 1 << 2;
1122 const int CC2 = 1 << 1;
1123
1124 switch (GET_CODE (code))
1125 {
1126 case EQ:
1127 return CC0;
1128 case NE:
1129 return CC1 | CC2;
1130 case LT:
1131 case LTU:
1132 return CC1;
1133 case GT:
1134 case GTU:
1135 return CC2;
1136 case LE:
1137 case LEU:
1138 return CC0 | CC1;
1139 case GE:
1140 case GEU:
1141 return CC0 | CC2;
1142 default:
1143 gcc_unreachable ();
1144 }
1145 return -1;
1146 }
1147
1148 /* If INV is false, return assembler mnemonic string to implement
1149 a branch specified by CODE. If INV is true, return mnemonic
1150 for the corresponding inverted branch. */
1151
1152 static const char *
1153 s390_branch_condition_mnemonic (rtx code, int inv)
1154 {
1155 int mask;
1156
1157 static const char *const mnemonic[16] =
1158 {
1159 NULL, "o", "h", "nle",
1160 "l", "nhe", "lh", "ne",
1161 "e", "nlh", "he", "nl",
1162 "le", "nh", "no", NULL
1163 };
1164
1165 if (GET_CODE (XEXP (code, 0)) == REG
1166 && REGNO (XEXP (code, 0)) == CC_REGNUM
1167 && XEXP (code, 1) == const0_rtx)
1168 mask = s390_branch_condition_mask (code);
1169 else
1170 mask = s390_compare_and_branch_condition_mask (code);
1171
1172 gcc_assert (mask >= 0);
1173
1174 if (inv)
1175 mask ^= 15;
1176
1177 gcc_assert (mask >= 1 && mask <= 14);
1178
1179 return mnemonic[mask];
1180 }
1181
1182 /* Return the part of op which has a value different from def.
1183 The size of the part is determined by mode.
1184 Use this function only if you already know that op really
1185 contains such a part. */
1186
1187 unsigned HOST_WIDE_INT
1188 s390_extract_part (rtx op, enum machine_mode mode, int def)
1189 {
1190 unsigned HOST_WIDE_INT value = 0;
1191 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1192 int part_bits = GET_MODE_BITSIZE (mode);
1193 unsigned HOST_WIDE_INT part_mask
1194 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1195 int i;
1196
1197 for (i = 0; i < max_parts; i++)
1198 {
1199 if (i == 0)
1200 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1201 else
1202 value >>= part_bits;
1203
1204 if ((value & part_mask) != (def & part_mask))
1205 return value & part_mask;
1206 }
1207
1208 gcc_unreachable ();
1209 }
1210
1211 /* If OP is an integer constant of mode MODE with exactly one
1212 part of mode PART_MODE unequal to DEF, return the number of that
1213 part. Otherwise, return -1. */
1214
1215 int
1216 s390_single_part (rtx op,
1217 enum machine_mode mode,
1218 enum machine_mode part_mode,
1219 int def)
1220 {
1221 unsigned HOST_WIDE_INT value = 0;
1222 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1223 unsigned HOST_WIDE_INT part_mask
1224 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1225 int i, part = -1;
1226
1227 if (GET_CODE (op) != CONST_INT)
1228 return -1;
1229
1230 for (i = 0; i < n_parts; i++)
1231 {
1232 if (i == 0)
1233 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1234 else
1235 value >>= GET_MODE_BITSIZE (part_mode);
1236
1237 if ((value & part_mask) != (def & part_mask))
1238 {
1239 if (part != -1)
1240 return -1;
1241 else
1242 part = i;
1243 }
1244 }
1245 return part == -1 ? -1 : n_parts - 1 - part;
1246 }
1247
1248 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1249 bits and no other bits are set in IN. POS and LENGTH can be used
1250 to obtain the start position and the length of the bitfield.
1251
1252 POS gives the position of the first bit of the bitfield counting
1253 from the lowest order bit starting with zero. In order to use this
1254 value for S/390 instructions this has to be converted to "bits big
1255 endian" style. */
1256
1257 bool
1258 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1259 int *pos, int *length)
1260 {
1261 int tmp_pos = 0;
1262 int tmp_length = 0;
1263 int i;
1264 unsigned HOST_WIDE_INT mask = 1ULL;
1265 bool contiguous = false;
1266
1267 for (i = 0; i < size; mask <<= 1, i++)
1268 {
1269 if (contiguous)
1270 {
1271 if (mask & in)
1272 tmp_length++;
1273 else
1274 break;
1275 }
1276 else
1277 {
1278 if (mask & in)
1279 {
1280 contiguous = true;
1281 tmp_length++;
1282 }
1283 else
1284 tmp_pos++;
1285 }
1286 }
1287
1288 if (!tmp_length)
1289 return false;
1290
1291 /* Calculate a mask for all bits beyond the contiguous bits. */
1292 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1293
1294 if (mask & in)
1295 return false;
1296
1297 if (tmp_length + tmp_pos - 1 > size)
1298 return false;
1299
1300 if (length)
1301 *length = tmp_length;
1302
1303 if (pos)
1304 *pos = tmp_pos;
1305
1306 return true;
1307 }
1308
1309 /* Check whether we can (and want to) split a double-word
1310 move in mode MODE from SRC to DST into two single-word
1311 moves, moving the subword FIRST_SUBWORD first. */
1312
1313 bool
1314 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1315 {
1316 /* Floating point registers cannot be split. */
1317 if (FP_REG_P (src) || FP_REG_P (dst))
1318 return false;
1319
1320 /* We don't need to split if operands are directly accessible. */
1321 if (s_operand (src, mode) || s_operand (dst, mode))
1322 return false;
1323
1324 /* Non-offsettable memory references cannot be split. */
1325 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1326 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1327 return false;
1328
1329 /* Moving the first subword must not clobber a register
1330 needed to move the second subword. */
1331 if (register_operand (dst, mode))
1332 {
1333 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1334 if (reg_overlap_mentioned_p (subreg, src))
1335 return false;
1336 }
1337
1338 return true;
1339 }
1340
1341 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1342 and [MEM2, MEM2 + SIZE] do overlap and false
1343 otherwise. */
1344
1345 bool
1346 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1347 {
1348 rtx addr1, addr2, addr_delta;
1349 HOST_WIDE_INT delta;
1350
1351 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1352 return true;
1353
1354 if (size == 0)
1355 return false;
1356
1357 addr1 = XEXP (mem1, 0);
1358 addr2 = XEXP (mem2, 0);
1359
1360 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1361
1362 /* This overlapping check is used by peepholes merging memory block operations.
1363 Overlapping operations would otherwise be recognized by the S/390 hardware
1364 and would fall back to a slower implementation. Allowing overlapping
1365 operations would lead to slow code but not to wrong code. Therefore we are
1366 somewhat optimistic if we cannot prove that the memory blocks are
1367 overlapping.
1368 That's why we return false here although this may accept operations on
1369 overlapping memory areas. */
1370 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1371 return false;
1372
1373 delta = INTVAL (addr_delta);
1374
1375 if (delta == 0
1376 || (delta > 0 && delta < size)
1377 || (delta < 0 && -delta < size))
1378 return true;
1379
1380 return false;
1381 }
1382
1383 /* Check whether the address of memory reference MEM2 equals exactly
1384 the address of memory reference MEM1 plus DELTA. Return true if
1385 we can prove this to be the case, false otherwise. */
1386
1387 bool
1388 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1389 {
1390 rtx addr1, addr2, addr_delta;
1391
1392 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1393 return false;
1394
1395 addr1 = XEXP (mem1, 0);
1396 addr2 = XEXP (mem2, 0);
1397
1398 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1399 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1400 return false;
1401
1402 return true;
1403 }
1404
1405 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1406
1407 void
1408 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1409 rtx *operands)
1410 {
1411 enum machine_mode wmode = mode;
1412 rtx dst = operands[0];
1413 rtx src1 = operands[1];
1414 rtx src2 = operands[2];
1415 rtx op, clob, tem;
1416
1417 /* If we cannot handle the operation directly, use a temp register. */
1418 if (!s390_logical_operator_ok_p (operands))
1419 dst = gen_reg_rtx (mode);
1420
1421 /* QImode and HImode patterns make sense only if we have a destination
1422 in memory. Otherwise perform the operation in SImode. */
1423 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1424 wmode = SImode;
1425
1426 /* Widen operands if required. */
1427 if (mode != wmode)
1428 {
1429 if (GET_CODE (dst) == SUBREG
1430 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1431 dst = tem;
1432 else if (REG_P (dst))
1433 dst = gen_rtx_SUBREG (wmode, dst, 0);
1434 else
1435 dst = gen_reg_rtx (wmode);
1436
1437 if (GET_CODE (src1) == SUBREG
1438 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1439 src1 = tem;
1440 else if (GET_MODE (src1) != VOIDmode)
1441 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1442
1443 if (GET_CODE (src2) == SUBREG
1444 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1445 src2 = tem;
1446 else if (GET_MODE (src2) != VOIDmode)
1447 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1448 }
1449
1450 /* Emit the instruction. */
1451 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1452 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1453 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1454
1455 /* Fix up the destination if needed. */
1456 if (dst != operands[0])
1457 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1458 }
1459
1460 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1461
1462 bool
1463 s390_logical_operator_ok_p (rtx *operands)
1464 {
1465 /* If the destination operand is in memory, it needs to coincide
1466 with one of the source operands. After reload, it has to be
1467 the first source operand. */
1468 if (GET_CODE (operands[0]) == MEM)
1469 return rtx_equal_p (operands[0], operands[1])
1470 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1471
1472 return true;
1473 }
1474
1475 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1476 operand IMMOP to switch from SS to SI type instructions. */
1477
1478 void
1479 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1480 {
1481 int def = code == AND ? -1 : 0;
1482 HOST_WIDE_INT mask;
1483 int part;
1484
1485 gcc_assert (GET_CODE (*memop) == MEM);
1486 gcc_assert (!MEM_VOLATILE_P (*memop));
1487
1488 mask = s390_extract_part (*immop, QImode, def);
1489 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1490 gcc_assert (part >= 0);
1491
1492 *memop = adjust_address (*memop, QImode, part);
1493 *immop = gen_int_mode (mask, QImode);
1494 }
1495
1496
1497 /* How to allocate a 'struct machine_function'. */
1498
1499 static struct machine_function *
1500 s390_init_machine_status (void)
1501 {
1502 return ggc_alloc_cleared_machine_function ();
1503 }
1504
1505 static void
1506 s390_option_override (void)
1507 {
1508 /* Set up function hooks. */
1509 init_machine_status = s390_init_machine_status;
1510
1511 /* Architecture mode defaults according to ABI. */
1512 if (!(target_flags_explicit & MASK_ZARCH))
1513 {
1514 if (TARGET_64BIT)
1515 target_flags |= MASK_ZARCH;
1516 else
1517 target_flags &= ~MASK_ZARCH;
1518 }
1519
1520 /* Set the march default in case it hasn't been specified on
1521 cmdline. */
1522 if (s390_arch == PROCESSOR_max)
1523 {
1524 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1525 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1526 s390_arch_flags = processor_flags_table[(int)s390_arch];
1527 }
1528
1529 /* Determine processor to tune for. */
1530 if (s390_tune == PROCESSOR_max)
1531 {
1532 s390_tune = s390_arch;
1533 s390_tune_flags = s390_arch_flags;
1534 }
1535
1536 /* Sanity checks. */
1537 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1538 error ("z/Architecture mode not supported on %s", s390_arch_string);
1539 if (TARGET_64BIT && !TARGET_ZARCH)
1540 error ("64-bit ABI not supported in ESA/390 mode");
1541
1542 /* Use hardware DFP if available and not explicitly disabled by
1543 user. E.g. with -m31 -march=z10 -mzarch */
1544 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1545 target_flags |= MASK_HARD_DFP;
1546
1547 if (TARGET_HARD_DFP && !TARGET_DFP)
1548 {
1549 if (target_flags_explicit & MASK_HARD_DFP)
1550 {
1551 if (!TARGET_CPU_DFP)
1552 error ("hardware decimal floating point instructions"
1553 " not available on %s", s390_arch_string);
1554 if (!TARGET_ZARCH)
1555 error ("hardware decimal floating point instructions"
1556 " not available in ESA/390 mode");
1557 }
1558 else
1559 target_flags &= ~MASK_HARD_DFP;
1560 }
1561
1562 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1563 {
1564 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1565 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1566
1567 target_flags &= ~MASK_HARD_DFP;
1568 }
1569
1570 /* Set processor cost function. */
1571 switch (s390_tune)
1572 {
1573 case PROCESSOR_2084_Z990:
1574 s390_cost = &z990_cost;
1575 break;
1576 case PROCESSOR_2094_Z9_109:
1577 s390_cost = &z9_109_cost;
1578 break;
1579 case PROCESSOR_2097_Z10:
1580 s390_cost = &z10_cost;
1581 case PROCESSOR_2817_Z196:
1582 s390_cost = &z196_cost;
1583 break;
1584 default:
1585 s390_cost = &z900_cost;
1586 }
1587
1588 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1589 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1590 "in combination");
1591
1592 if (s390_stack_size)
1593 {
1594 if (s390_stack_guard >= s390_stack_size)
1595 error ("stack size must be greater than the stack guard value");
1596 else if (s390_stack_size > 1 << 16)
1597 error ("stack size must not be greater than 64k");
1598 }
1599 else if (s390_stack_guard)
1600 error ("-mstack-guard implies use of -mstack-size");
1601
1602 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1603 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1604 target_flags |= MASK_LONG_DOUBLE_128;
1605 #endif
1606
1607 if (s390_tune == PROCESSOR_2097_Z10
1608 || s390_tune == PROCESSOR_2817_Z196)
1609 {
1610 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1611 global_options.x_param_values,
1612 global_options_set.x_param_values);
1613 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1614 global_options.x_param_values,
1615 global_options_set.x_param_values);
1616 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1617 global_options.x_param_values,
1618 global_options_set.x_param_values);
1619 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1620 global_options.x_param_values,
1621 global_options_set.x_param_values);
1622 }
1623
1624 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1625 global_options.x_param_values,
1626 global_options_set.x_param_values);
1627 /* values for loop prefetching */
1628 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1629 global_options.x_param_values,
1630 global_options_set.x_param_values);
1631 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1632 global_options.x_param_values,
1633 global_options_set.x_param_values);
1634 /* s390 has more than 2 levels and the size is much larger. Since
1635 we are always running virtualized assume that we only get a small
1636 part of the caches above l1. */
1637 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1638 global_options.x_param_values,
1639 global_options_set.x_param_values);
1640 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1641 global_options.x_param_values,
1642 global_options_set.x_param_values);
1643 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1644 global_options.x_param_values,
1645 global_options_set.x_param_values);
1646
1647 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1648 requires the arch flags to be evaluated already. Since prefetching
1649 is beneficial on s390, we enable it if available. */
1650 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1651 flag_prefetch_loop_arrays = 1;
1652
1653 /* Use the alternative scheduling-pressure algorithm by default. */
1654 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
1655 global_options.x_param_values,
1656 global_options_set.x_param_values);
1657
1658 if (TARGET_TPF)
1659 {
1660 /* Don't emit DWARF3/4 unless specifically selected. The TPF
1661 debuggers do not yet support DWARF 3/4. */
1662 if (!global_options_set.x_dwarf_strict)
1663 dwarf_strict = 1;
1664 if (!global_options_set.x_dwarf_version)
1665 dwarf_version = 2;
1666 }
1667 }
1668
1669 /* Map for smallest class containing reg regno. */
1670
1671 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1672 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1673 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1674 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1675 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1676 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1677 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1678 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1679 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1680 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1681 ACCESS_REGS, ACCESS_REGS
1682 };
1683
1684 /* Return attribute type of insn. */
1685
1686 static enum attr_type
1687 s390_safe_attr_type (rtx insn)
1688 {
1689 if (recog_memoized (insn) >= 0)
1690 return get_attr_type (insn);
1691 else
1692 return TYPE_NONE;
1693 }
1694
1695 /* Return true if DISP is a valid short displacement. */
1696
1697 static bool
1698 s390_short_displacement (rtx disp)
1699 {
1700 /* No displacement is OK. */
1701 if (!disp)
1702 return true;
1703
1704 /* Without the long displacement facility we don't need to
1705 distingiush between long and short displacement. */
1706 if (!TARGET_LONG_DISPLACEMENT)
1707 return true;
1708
1709 /* Integer displacement in range. */
1710 if (GET_CODE (disp) == CONST_INT)
1711 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1712
1713 /* GOT offset is not OK, the GOT can be large. */
1714 if (GET_CODE (disp) == CONST
1715 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1716 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1717 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1718 return false;
1719
1720 /* All other symbolic constants are literal pool references,
1721 which are OK as the literal pool must be small. */
1722 if (GET_CODE (disp) == CONST)
1723 return true;
1724
1725 return false;
1726 }
1727
1728 /* Decompose a RTL expression ADDR for a memory address into
1729 its components, returned in OUT.
1730
1731 Returns false if ADDR is not a valid memory address, true
1732 otherwise. If OUT is NULL, don't return the components,
1733 but check for validity only.
1734
1735 Note: Only addresses in canonical form are recognized.
1736 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1737 canonical form so that they will be recognized. */
1738
1739 static int
1740 s390_decompose_address (rtx addr, struct s390_address *out)
1741 {
1742 HOST_WIDE_INT offset = 0;
1743 rtx base = NULL_RTX;
1744 rtx indx = NULL_RTX;
1745 rtx disp = NULL_RTX;
1746 rtx orig_disp;
1747 bool pointer = false;
1748 bool base_ptr = false;
1749 bool indx_ptr = false;
1750 bool literal_pool = false;
1751
1752 /* We may need to substitute the literal pool base register into the address
1753 below. However, at this point we do not know which register is going to
1754 be used as base, so we substitute the arg pointer register. This is going
1755 to be treated as holding a pointer below -- it shouldn't be used for any
1756 other purpose. */
1757 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1758
1759 /* Decompose address into base + index + displacement. */
1760
1761 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1762 base = addr;
1763
1764 else if (GET_CODE (addr) == PLUS)
1765 {
1766 rtx op0 = XEXP (addr, 0);
1767 rtx op1 = XEXP (addr, 1);
1768 enum rtx_code code0 = GET_CODE (op0);
1769 enum rtx_code code1 = GET_CODE (op1);
1770
1771 if (code0 == REG || code0 == UNSPEC)
1772 {
1773 if (code1 == REG || code1 == UNSPEC)
1774 {
1775 indx = op0; /* index + base */
1776 base = op1;
1777 }
1778
1779 else
1780 {
1781 base = op0; /* base + displacement */
1782 disp = op1;
1783 }
1784 }
1785
1786 else if (code0 == PLUS)
1787 {
1788 indx = XEXP (op0, 0); /* index + base + disp */
1789 base = XEXP (op0, 1);
1790 disp = op1;
1791 }
1792
1793 else
1794 {
1795 return false;
1796 }
1797 }
1798
1799 else
1800 disp = addr; /* displacement */
1801
1802 /* Extract integer part of displacement. */
1803 orig_disp = disp;
1804 if (disp)
1805 {
1806 if (GET_CODE (disp) == CONST_INT)
1807 {
1808 offset = INTVAL (disp);
1809 disp = NULL_RTX;
1810 }
1811 else if (GET_CODE (disp) == CONST
1812 && GET_CODE (XEXP (disp, 0)) == PLUS
1813 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1814 {
1815 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1816 disp = XEXP (XEXP (disp, 0), 0);
1817 }
1818 }
1819
1820 /* Strip off CONST here to avoid special case tests later. */
1821 if (disp && GET_CODE (disp) == CONST)
1822 disp = XEXP (disp, 0);
1823
1824 /* We can convert literal pool addresses to
1825 displacements by basing them off the base register. */
1826 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1827 {
1828 /* Either base or index must be free to hold the base register. */
1829 if (!base)
1830 base = fake_pool_base, literal_pool = true;
1831 else if (!indx)
1832 indx = fake_pool_base, literal_pool = true;
1833 else
1834 return false;
1835
1836 /* Mark up the displacement. */
1837 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1838 UNSPEC_LTREL_OFFSET);
1839 }
1840
1841 /* Validate base register. */
1842 if (base)
1843 {
1844 if (GET_CODE (base) == UNSPEC)
1845 switch (XINT (base, 1))
1846 {
1847 case UNSPEC_LTREF:
1848 if (!disp)
1849 disp = gen_rtx_UNSPEC (Pmode,
1850 gen_rtvec (1, XVECEXP (base, 0, 0)),
1851 UNSPEC_LTREL_OFFSET);
1852 else
1853 return false;
1854
1855 base = XVECEXP (base, 0, 1);
1856 break;
1857
1858 case UNSPEC_LTREL_BASE:
1859 if (XVECLEN (base, 0) == 1)
1860 base = fake_pool_base, literal_pool = true;
1861 else
1862 base = XVECEXP (base, 0, 1);
1863 break;
1864
1865 default:
1866 return false;
1867 }
1868
1869 if (!REG_P (base)
1870 || (GET_MODE (base) != SImode
1871 && GET_MODE (base) != Pmode))
1872 return false;
1873
1874 if (REGNO (base) == STACK_POINTER_REGNUM
1875 || REGNO (base) == FRAME_POINTER_REGNUM
1876 || ((reload_completed || reload_in_progress)
1877 && frame_pointer_needed
1878 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1879 || REGNO (base) == ARG_POINTER_REGNUM
1880 || (flag_pic
1881 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1882 pointer = base_ptr = true;
1883
1884 if ((reload_completed || reload_in_progress)
1885 && base == cfun->machine->base_reg)
1886 pointer = base_ptr = literal_pool = true;
1887 }
1888
1889 /* Validate index register. */
1890 if (indx)
1891 {
1892 if (GET_CODE (indx) == UNSPEC)
1893 switch (XINT (indx, 1))
1894 {
1895 case UNSPEC_LTREF:
1896 if (!disp)
1897 disp = gen_rtx_UNSPEC (Pmode,
1898 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1899 UNSPEC_LTREL_OFFSET);
1900 else
1901 return false;
1902
1903 indx = XVECEXP (indx, 0, 1);
1904 break;
1905
1906 case UNSPEC_LTREL_BASE:
1907 if (XVECLEN (indx, 0) == 1)
1908 indx = fake_pool_base, literal_pool = true;
1909 else
1910 indx = XVECEXP (indx, 0, 1);
1911 break;
1912
1913 default:
1914 return false;
1915 }
1916
1917 if (!REG_P (indx)
1918 || (GET_MODE (indx) != SImode
1919 && GET_MODE (indx) != Pmode))
1920 return false;
1921
1922 if (REGNO (indx) == STACK_POINTER_REGNUM
1923 || REGNO (indx) == FRAME_POINTER_REGNUM
1924 || ((reload_completed || reload_in_progress)
1925 && frame_pointer_needed
1926 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1927 || REGNO (indx) == ARG_POINTER_REGNUM
1928 || (flag_pic
1929 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1930 pointer = indx_ptr = true;
1931
1932 if ((reload_completed || reload_in_progress)
1933 && indx == cfun->machine->base_reg)
1934 pointer = indx_ptr = literal_pool = true;
1935 }
1936
1937 /* Prefer to use pointer as base, not index. */
1938 if (base && indx && !base_ptr
1939 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1940 {
1941 rtx tmp = base;
1942 base = indx;
1943 indx = tmp;
1944 }
1945
1946 /* Validate displacement. */
1947 if (!disp)
1948 {
1949 /* If virtual registers are involved, the displacement will change later
1950 anyway as the virtual registers get eliminated. This could make a
1951 valid displacement invalid, but it is more likely to make an invalid
1952 displacement valid, because we sometimes access the register save area
1953 via negative offsets to one of those registers.
1954 Thus we don't check the displacement for validity here. If after
1955 elimination the displacement turns out to be invalid after all,
1956 this is fixed up by reload in any case. */
1957 if (base != arg_pointer_rtx
1958 && indx != arg_pointer_rtx
1959 && base != return_address_pointer_rtx
1960 && indx != return_address_pointer_rtx
1961 && base != frame_pointer_rtx
1962 && indx != frame_pointer_rtx
1963 && base != virtual_stack_vars_rtx
1964 && indx != virtual_stack_vars_rtx)
1965 if (!DISP_IN_RANGE (offset))
1966 return false;
1967 }
1968 else
1969 {
1970 /* All the special cases are pointers. */
1971 pointer = true;
1972
1973 /* In the small-PIC case, the linker converts @GOT
1974 and @GOTNTPOFF offsets to possible displacements. */
1975 if (GET_CODE (disp) == UNSPEC
1976 && (XINT (disp, 1) == UNSPEC_GOT
1977 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1978 && flag_pic == 1)
1979 {
1980 ;
1981 }
1982
1983 /* Accept pool label offsets. */
1984 else if (GET_CODE (disp) == UNSPEC
1985 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1986 ;
1987
1988 /* Accept literal pool references. */
1989 else if (GET_CODE (disp) == UNSPEC
1990 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1991 {
1992 /* In case CSE pulled a non literal pool reference out of
1993 the pool we have to reject the address. This is
1994 especially important when loading the GOT pointer on non
1995 zarch CPUs. In this case the literal pool contains an lt
1996 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
1997 will most likely exceed the displacement. */
1998 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
1999 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2000 return false;
2001
2002 orig_disp = gen_rtx_CONST (Pmode, disp);
2003 if (offset)
2004 {
2005 /* If we have an offset, make sure it does not
2006 exceed the size of the constant pool entry. */
2007 rtx sym = XVECEXP (disp, 0, 0);
2008 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2009 return false;
2010
2011 orig_disp = plus_constant (Pmode, orig_disp, offset);
2012 }
2013 }
2014
2015 else
2016 return false;
2017 }
2018
2019 if (!base && !indx)
2020 pointer = true;
2021
2022 if (out)
2023 {
2024 out->base = base;
2025 out->indx = indx;
2026 out->disp = orig_disp;
2027 out->pointer = pointer;
2028 out->literal_pool = literal_pool;
2029 }
2030
2031 return true;
2032 }
2033
2034 /* Decompose a RTL expression OP for a shift count into its components,
2035 and return the base register in BASE and the offset in OFFSET.
2036
2037 Return true if OP is a valid shift count, false if not. */
2038
2039 bool
2040 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2041 {
2042 HOST_WIDE_INT off = 0;
2043
2044 /* We can have an integer constant, an address register,
2045 or a sum of the two. */
2046 if (GET_CODE (op) == CONST_INT)
2047 {
2048 off = INTVAL (op);
2049 op = NULL_RTX;
2050 }
2051 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2052 {
2053 off = INTVAL (XEXP (op, 1));
2054 op = XEXP (op, 0);
2055 }
2056 while (op && GET_CODE (op) == SUBREG)
2057 op = SUBREG_REG (op);
2058
2059 if (op && GET_CODE (op) != REG)
2060 return false;
2061
2062 if (offset)
2063 *offset = off;
2064 if (base)
2065 *base = op;
2066
2067 return true;
2068 }
2069
2070
2071 /* Return true if CODE is a valid address without index. */
2072
2073 bool
2074 s390_legitimate_address_without_index_p (rtx op)
2075 {
2076 struct s390_address addr;
2077
2078 if (!s390_decompose_address (XEXP (op, 0), &addr))
2079 return false;
2080 if (addr.indx)
2081 return false;
2082
2083 return true;
2084 }
2085
2086
2087 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2088 and return these parts in SYMREF and ADDEND. You can pass NULL in
2089 SYMREF and/or ADDEND if you are not interested in these values.
2090 Literal pool references are *not* considered symbol references. */
2091
2092 static bool
2093 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2094 {
2095 HOST_WIDE_INT tmpaddend = 0;
2096
2097 if (GET_CODE (addr) == CONST)
2098 addr = XEXP (addr, 0);
2099
2100 if (GET_CODE (addr) == PLUS)
2101 {
2102 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2103 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2104 && CONST_INT_P (XEXP (addr, 1)))
2105 {
2106 tmpaddend = INTVAL (XEXP (addr, 1));
2107 addr = XEXP (addr, 0);
2108 }
2109 else
2110 return false;
2111 }
2112 else
2113 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2114 return false;
2115
2116 if (symref)
2117 *symref = addr;
2118 if (addend)
2119 *addend = tmpaddend;
2120
2121 return true;
2122 }
2123
2124
2125 /* Return true if the address in OP is valid for constraint letter C
2126 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2127 pool MEMs should be accepted. Only the Q, R, S, T constraint
2128 letters are allowed for C. */
2129
2130 static int
2131 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2132 {
2133 struct s390_address addr;
2134 bool decomposed = false;
2135
2136 /* This check makes sure that no symbolic address (except literal
2137 pool references) are accepted by the R or T constraints. */
2138 if (s390_symref_operand_p (op, NULL, NULL))
2139 return 0;
2140
2141 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2142 if (!lit_pool_ok)
2143 {
2144 if (!s390_decompose_address (op, &addr))
2145 return 0;
2146 if (addr.literal_pool)
2147 return 0;
2148 decomposed = true;
2149 }
2150
2151 switch (c)
2152 {
2153 case 'Q': /* no index short displacement */
2154 if (!decomposed && !s390_decompose_address (op, &addr))
2155 return 0;
2156 if (addr.indx)
2157 return 0;
2158 if (!s390_short_displacement (addr.disp))
2159 return 0;
2160 break;
2161
2162 case 'R': /* with index short displacement */
2163 if (TARGET_LONG_DISPLACEMENT)
2164 {
2165 if (!decomposed && !s390_decompose_address (op, &addr))
2166 return 0;
2167 if (!s390_short_displacement (addr.disp))
2168 return 0;
2169 }
2170 /* Any invalid address here will be fixed up by reload,
2171 so accept it for the most generic constraint. */
2172 break;
2173
2174 case 'S': /* no index long displacement */
2175 if (!TARGET_LONG_DISPLACEMENT)
2176 return 0;
2177 if (!decomposed && !s390_decompose_address (op, &addr))
2178 return 0;
2179 if (addr.indx)
2180 return 0;
2181 if (s390_short_displacement (addr.disp))
2182 return 0;
2183 break;
2184
2185 case 'T': /* with index long displacement */
2186 if (!TARGET_LONG_DISPLACEMENT)
2187 return 0;
2188 /* Any invalid address here will be fixed up by reload,
2189 so accept it for the most generic constraint. */
2190 if ((decomposed || s390_decompose_address (op, &addr))
2191 && s390_short_displacement (addr.disp))
2192 return 0;
2193 break;
2194 default:
2195 return 0;
2196 }
2197 return 1;
2198 }
2199
2200
2201 /* Evaluates constraint strings described by the regular expression
2202 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2203 the constraint given in STR, or 0 else. */
2204
2205 int
2206 s390_mem_constraint (const char *str, rtx op)
2207 {
2208 char c = str[0];
2209
2210 switch (c)
2211 {
2212 case 'A':
2213 /* Check for offsettable variants of memory constraints. */
2214 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2215 return 0;
2216 if ((reload_completed || reload_in_progress)
2217 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2218 return 0;
2219 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2220 case 'B':
2221 /* Check for non-literal-pool variants of memory constraints. */
2222 if (!MEM_P (op))
2223 return 0;
2224 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2225 case 'Q':
2226 case 'R':
2227 case 'S':
2228 case 'T':
2229 if (GET_CODE (op) != MEM)
2230 return 0;
2231 return s390_check_qrst_address (c, XEXP (op, 0), true);
2232 case 'U':
2233 return (s390_check_qrst_address ('Q', op, true)
2234 || s390_check_qrst_address ('R', op, true));
2235 case 'W':
2236 return (s390_check_qrst_address ('S', op, true)
2237 || s390_check_qrst_address ('T', op, true));
2238 case 'Y':
2239 /* Simply check for the basic form of a shift count. Reload will
2240 take care of making sure we have a proper base register. */
2241 if (!s390_decompose_shift_count (op, NULL, NULL))
2242 return 0;
2243 break;
2244 case 'Z':
2245 return s390_check_qrst_address (str[1], op, true);
2246 default:
2247 return 0;
2248 }
2249 return 1;
2250 }
2251
2252
2253 /* Evaluates constraint strings starting with letter O. Input
2254 parameter C is the second letter following the "O" in the constraint
2255 string. Returns 1 if VALUE meets the respective constraint and 0
2256 otherwise. */
2257
2258 int
2259 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2260 {
2261 if (!TARGET_EXTIMM)
2262 return 0;
2263
2264 switch (c)
2265 {
2266 case 's':
2267 return trunc_int_for_mode (value, SImode) == value;
2268
2269 case 'p':
2270 return value == 0
2271 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2272
2273 case 'n':
2274 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2275
2276 default:
2277 gcc_unreachable ();
2278 }
2279 }
2280
2281
2282 /* Evaluates constraint strings starting with letter N. Parameter STR
2283 contains the letters following letter "N" in the constraint string.
2284 Returns true if VALUE matches the constraint. */
2285
2286 int
2287 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2288 {
2289 enum machine_mode mode, part_mode;
2290 int def;
2291 int part, part_goal;
2292
2293
2294 if (str[0] == 'x')
2295 part_goal = -1;
2296 else
2297 part_goal = str[0] - '0';
2298
2299 switch (str[1])
2300 {
2301 case 'Q':
2302 part_mode = QImode;
2303 break;
2304 case 'H':
2305 part_mode = HImode;
2306 break;
2307 case 'S':
2308 part_mode = SImode;
2309 break;
2310 default:
2311 return 0;
2312 }
2313
2314 switch (str[2])
2315 {
2316 case 'H':
2317 mode = HImode;
2318 break;
2319 case 'S':
2320 mode = SImode;
2321 break;
2322 case 'D':
2323 mode = DImode;
2324 break;
2325 default:
2326 return 0;
2327 }
2328
2329 switch (str[3])
2330 {
2331 case '0':
2332 def = 0;
2333 break;
2334 case 'F':
2335 def = -1;
2336 break;
2337 default:
2338 return 0;
2339 }
2340
2341 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2342 return 0;
2343
2344 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2345 if (part < 0)
2346 return 0;
2347 if (part_goal != -1 && part_goal != part)
2348 return 0;
2349
2350 return 1;
2351 }
2352
2353
2354 /* Returns true if the input parameter VALUE is a float zero. */
2355
2356 int
2357 s390_float_const_zero_p (rtx value)
2358 {
2359 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2360 && value == CONST0_RTX (GET_MODE (value)));
2361 }
2362
2363 /* Implement TARGET_REGISTER_MOVE_COST. */
2364
2365 static int
2366 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2367 reg_class_t from, reg_class_t to)
2368 {
2369 /* On s390, copy between fprs and gprs is expensive. */
2370 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2371 && reg_classes_intersect_p (to, FP_REGS))
2372 || (reg_classes_intersect_p (from, FP_REGS)
2373 && reg_classes_intersect_p (to, GENERAL_REGS)))
2374 return 10;
2375
2376 return 1;
2377 }
2378
2379 /* Implement TARGET_MEMORY_MOVE_COST. */
2380
2381 static int
2382 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2383 reg_class_t rclass ATTRIBUTE_UNUSED,
2384 bool in ATTRIBUTE_UNUSED)
2385 {
2386 return 1;
2387 }
2388
2389 /* Compute a (partial) cost for rtx X. Return true if the complete
2390 cost has been computed, and false if subexpressions should be
2391 scanned. In either case, *TOTAL contains the cost result.
2392 CODE contains GET_CODE (x), OUTER_CODE contains the code
2393 of the superexpression of x. */
2394
2395 static bool
2396 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2397 int *total, bool speed ATTRIBUTE_UNUSED)
2398 {
2399 switch (code)
2400 {
2401 case CONST:
2402 case CONST_INT:
2403 case LABEL_REF:
2404 case SYMBOL_REF:
2405 case CONST_DOUBLE:
2406 case MEM:
2407 *total = 0;
2408 return true;
2409
2410 case ASHIFT:
2411 case ASHIFTRT:
2412 case LSHIFTRT:
2413 case ROTATE:
2414 case ROTATERT:
2415 case AND:
2416 case IOR:
2417 case XOR:
2418 case NEG:
2419 case NOT:
2420 *total = COSTS_N_INSNS (1);
2421 return false;
2422
2423 case PLUS:
2424 case MINUS:
2425 *total = COSTS_N_INSNS (1);
2426 return false;
2427
2428 case MULT:
2429 switch (GET_MODE (x))
2430 {
2431 case SImode:
2432 {
2433 rtx left = XEXP (x, 0);
2434 rtx right = XEXP (x, 1);
2435 if (GET_CODE (right) == CONST_INT
2436 && CONST_OK_FOR_K (INTVAL (right)))
2437 *total = s390_cost->mhi;
2438 else if (GET_CODE (left) == SIGN_EXTEND)
2439 *total = s390_cost->mh;
2440 else
2441 *total = s390_cost->ms; /* msr, ms, msy */
2442 break;
2443 }
2444 case DImode:
2445 {
2446 rtx left = XEXP (x, 0);
2447 rtx right = XEXP (x, 1);
2448 if (TARGET_ZARCH)
2449 {
2450 if (GET_CODE (right) == CONST_INT
2451 && CONST_OK_FOR_K (INTVAL (right)))
2452 *total = s390_cost->mghi;
2453 else if (GET_CODE (left) == SIGN_EXTEND)
2454 *total = s390_cost->msgf;
2455 else
2456 *total = s390_cost->msg; /* msgr, msg */
2457 }
2458 else /* TARGET_31BIT */
2459 {
2460 if (GET_CODE (left) == SIGN_EXTEND
2461 && GET_CODE (right) == SIGN_EXTEND)
2462 /* mulsidi case: mr, m */
2463 *total = s390_cost->m;
2464 else if (GET_CODE (left) == ZERO_EXTEND
2465 && GET_CODE (right) == ZERO_EXTEND
2466 && TARGET_CPU_ZARCH)
2467 /* umulsidi case: ml, mlr */
2468 *total = s390_cost->ml;
2469 else
2470 /* Complex calculation is required. */
2471 *total = COSTS_N_INSNS (40);
2472 }
2473 break;
2474 }
2475 case SFmode:
2476 case DFmode:
2477 *total = s390_cost->mult_df;
2478 break;
2479 case TFmode:
2480 *total = s390_cost->mxbr;
2481 break;
2482 default:
2483 return false;
2484 }
2485 return false;
2486
2487 case FMA:
2488 switch (GET_MODE (x))
2489 {
2490 case DFmode:
2491 *total = s390_cost->madbr;
2492 break;
2493 case SFmode:
2494 *total = s390_cost->maebr;
2495 break;
2496 default:
2497 return false;
2498 }
2499 /* Negate in the third argument is free: FMSUB. */
2500 if (GET_CODE (XEXP (x, 2)) == NEG)
2501 {
2502 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2503 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2504 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2505 return true;
2506 }
2507 return false;
2508
2509 case UDIV:
2510 case UMOD:
2511 if (GET_MODE (x) == TImode) /* 128 bit division */
2512 *total = s390_cost->dlgr;
2513 else if (GET_MODE (x) == DImode)
2514 {
2515 rtx right = XEXP (x, 1);
2516 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2517 *total = s390_cost->dlr;
2518 else /* 64 by 64 bit division */
2519 *total = s390_cost->dlgr;
2520 }
2521 else if (GET_MODE (x) == SImode) /* 32 bit division */
2522 *total = s390_cost->dlr;
2523 return false;
2524
2525 case DIV:
2526 case MOD:
2527 if (GET_MODE (x) == DImode)
2528 {
2529 rtx right = XEXP (x, 1);
2530 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2531 if (TARGET_ZARCH)
2532 *total = s390_cost->dsgfr;
2533 else
2534 *total = s390_cost->dr;
2535 else /* 64 by 64 bit division */
2536 *total = s390_cost->dsgr;
2537 }
2538 else if (GET_MODE (x) == SImode) /* 32 bit division */
2539 *total = s390_cost->dlr;
2540 else if (GET_MODE (x) == SFmode)
2541 {
2542 *total = s390_cost->debr;
2543 }
2544 else if (GET_MODE (x) == DFmode)
2545 {
2546 *total = s390_cost->ddbr;
2547 }
2548 else if (GET_MODE (x) == TFmode)
2549 {
2550 *total = s390_cost->dxbr;
2551 }
2552 return false;
2553
2554 case SQRT:
2555 if (GET_MODE (x) == SFmode)
2556 *total = s390_cost->sqebr;
2557 else if (GET_MODE (x) == DFmode)
2558 *total = s390_cost->sqdbr;
2559 else /* TFmode */
2560 *total = s390_cost->sqxbr;
2561 return false;
2562
2563 case SIGN_EXTEND:
2564 case ZERO_EXTEND:
2565 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2566 || outer_code == PLUS || outer_code == MINUS
2567 || outer_code == COMPARE)
2568 *total = 0;
2569 return false;
2570
2571 case COMPARE:
2572 *total = COSTS_N_INSNS (1);
2573 if (GET_CODE (XEXP (x, 0)) == AND
2574 && GET_CODE (XEXP (x, 1)) == CONST_INT
2575 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2576 {
2577 rtx op0 = XEXP (XEXP (x, 0), 0);
2578 rtx op1 = XEXP (XEXP (x, 0), 1);
2579 rtx op2 = XEXP (x, 1);
2580
2581 if (memory_operand (op0, GET_MODE (op0))
2582 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2583 return true;
2584 if (register_operand (op0, GET_MODE (op0))
2585 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2586 return true;
2587 }
2588 return false;
2589
2590 default:
2591 return false;
2592 }
2593 }
2594
2595 /* Return the cost of an address rtx ADDR. */
2596
2597 static int
2598 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2599 {
2600 struct s390_address ad;
2601 if (!s390_decompose_address (addr, &ad))
2602 return 1000;
2603
2604 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2605 }
2606
2607 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2608 otherwise return 0. */
2609
2610 int
2611 tls_symbolic_operand (rtx op)
2612 {
2613 if (GET_CODE (op) != SYMBOL_REF)
2614 return 0;
2615 return SYMBOL_REF_TLS_MODEL (op);
2616 }
2617 \f
2618 /* Split DImode access register reference REG (on 64-bit) into its constituent
2619 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2620 gen_highpart cannot be used as they assume all registers are word-sized,
2621 while our access registers have only half that size. */
2622
2623 void
2624 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2625 {
2626 gcc_assert (TARGET_64BIT);
2627 gcc_assert (ACCESS_REG_P (reg));
2628 gcc_assert (GET_MODE (reg) == DImode);
2629 gcc_assert (!(REGNO (reg) & 1));
2630
2631 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2632 *hi = gen_rtx_REG (SImode, REGNO (reg));
2633 }
2634
2635 /* Return true if OP contains a symbol reference */
2636
2637 bool
2638 symbolic_reference_mentioned_p (rtx op)
2639 {
2640 const char *fmt;
2641 int i;
2642
2643 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2644 return 1;
2645
2646 fmt = GET_RTX_FORMAT (GET_CODE (op));
2647 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2648 {
2649 if (fmt[i] == 'E')
2650 {
2651 int j;
2652
2653 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2654 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2655 return 1;
2656 }
2657
2658 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2659 return 1;
2660 }
2661
2662 return 0;
2663 }
2664
2665 /* Return true if OP contains a reference to a thread-local symbol. */
2666
2667 bool
2668 tls_symbolic_reference_mentioned_p (rtx op)
2669 {
2670 const char *fmt;
2671 int i;
2672
2673 if (GET_CODE (op) == SYMBOL_REF)
2674 return tls_symbolic_operand (op);
2675
2676 fmt = GET_RTX_FORMAT (GET_CODE (op));
2677 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2678 {
2679 if (fmt[i] == 'E')
2680 {
2681 int j;
2682
2683 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2684 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2685 return true;
2686 }
2687
2688 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2689 return true;
2690 }
2691
2692 return false;
2693 }
2694
2695
2696 /* Return true if OP is a legitimate general operand when
2697 generating PIC code. It is given that flag_pic is on
2698 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2699
2700 int
2701 legitimate_pic_operand_p (rtx op)
2702 {
2703 /* Accept all non-symbolic constants. */
2704 if (!SYMBOLIC_CONST (op))
2705 return 1;
2706
2707 /* Reject everything else; must be handled
2708 via emit_symbolic_move. */
2709 return 0;
2710 }
2711
2712 /* Returns true if the constant value OP is a legitimate general operand.
2713 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2714
2715 static bool
2716 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2717 {
2718 /* Accept all non-symbolic constants. */
2719 if (!SYMBOLIC_CONST (op))
2720 return 1;
2721
2722 /* Accept immediate LARL operands. */
2723 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2724 return 1;
2725
2726 /* Thread-local symbols are never legal constants. This is
2727 so that emit_call knows that computing such addresses
2728 might require a function call. */
2729 if (TLS_SYMBOLIC_CONST (op))
2730 return 0;
2731
2732 /* In the PIC case, symbolic constants must *not* be
2733 forced into the literal pool. We accept them here,
2734 so that they will be handled by emit_symbolic_move. */
2735 if (flag_pic)
2736 return 1;
2737
2738 /* All remaining non-PIC symbolic constants are
2739 forced into the literal pool. */
2740 return 0;
2741 }
2742
2743 /* Determine if it's legal to put X into the constant pool. This
2744 is not possible if X contains the address of a symbol that is
2745 not constant (TLS) or not known at final link time (PIC). */
2746
2747 static bool
2748 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2749 {
2750 switch (GET_CODE (x))
2751 {
2752 case CONST_INT:
2753 case CONST_DOUBLE:
2754 /* Accept all non-symbolic constants. */
2755 return false;
2756
2757 case LABEL_REF:
2758 /* Labels are OK iff we are non-PIC. */
2759 return flag_pic != 0;
2760
2761 case SYMBOL_REF:
2762 /* 'Naked' TLS symbol references are never OK,
2763 non-TLS symbols are OK iff we are non-PIC. */
2764 if (tls_symbolic_operand (x))
2765 return true;
2766 else
2767 return flag_pic != 0;
2768
2769 case CONST:
2770 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2771 case PLUS:
2772 case MINUS:
2773 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2774 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2775
2776 case UNSPEC:
2777 switch (XINT (x, 1))
2778 {
2779 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2780 case UNSPEC_LTREL_OFFSET:
2781 case UNSPEC_GOT:
2782 case UNSPEC_GOTOFF:
2783 case UNSPEC_PLTOFF:
2784 case UNSPEC_TLSGD:
2785 case UNSPEC_TLSLDM:
2786 case UNSPEC_NTPOFF:
2787 case UNSPEC_DTPOFF:
2788 case UNSPEC_GOTNTPOFF:
2789 case UNSPEC_INDNTPOFF:
2790 return false;
2791
2792 /* If the literal pool shares the code section, be put
2793 execute template placeholders into the pool as well. */
2794 case UNSPEC_INSN:
2795 return TARGET_CPU_ZARCH;
2796
2797 default:
2798 return true;
2799 }
2800 break;
2801
2802 default:
2803 gcc_unreachable ();
2804 }
2805 }
2806
2807 /* Returns true if the constant value OP is a legitimate general
2808 operand during and after reload. The difference to
2809 legitimate_constant_p is that this function will not accept
2810 a constant that would need to be forced to the literal pool
2811 before it can be used as operand.
2812 This function accepts all constants which can be loaded directly
2813 into a GPR. */
2814
2815 bool
2816 legitimate_reload_constant_p (rtx op)
2817 {
2818 /* Accept la(y) operands. */
2819 if (GET_CODE (op) == CONST_INT
2820 && DISP_IN_RANGE (INTVAL (op)))
2821 return true;
2822
2823 /* Accept l(g)hi/l(g)fi operands. */
2824 if (GET_CODE (op) == CONST_INT
2825 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2826 return true;
2827
2828 /* Accept lliXX operands. */
2829 if (TARGET_ZARCH
2830 && GET_CODE (op) == CONST_INT
2831 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2832 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2833 return true;
2834
2835 if (TARGET_EXTIMM
2836 && GET_CODE (op) == CONST_INT
2837 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2838 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2839 return true;
2840
2841 /* Accept larl operands. */
2842 if (TARGET_CPU_ZARCH
2843 && larl_operand (op, VOIDmode))
2844 return true;
2845
2846 /* Accept floating-point zero operands that fit into a single GPR. */
2847 if (GET_CODE (op) == CONST_DOUBLE
2848 && s390_float_const_zero_p (op)
2849 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2850 return true;
2851
2852 /* Accept double-word operands that can be split. */
2853 if (GET_CODE (op) == CONST_INT
2854 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2855 {
2856 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2857 rtx hi = operand_subword (op, 0, 0, dword_mode);
2858 rtx lo = operand_subword (op, 1, 0, dword_mode);
2859 return legitimate_reload_constant_p (hi)
2860 && legitimate_reload_constant_p (lo);
2861 }
2862
2863 /* Everything else cannot be handled without reload. */
2864 return false;
2865 }
2866
2867 /* Returns true if the constant value OP is a legitimate fp operand
2868 during and after reload.
2869 This function accepts all constants which can be loaded directly
2870 into an FPR. */
2871
2872 static bool
2873 legitimate_reload_fp_constant_p (rtx op)
2874 {
2875 /* Accept floating-point zero operands if the load zero instruction
2876 can be used. */
2877 if (TARGET_Z196
2878 && GET_CODE (op) == CONST_DOUBLE
2879 && s390_float_const_zero_p (op))
2880 return true;
2881
2882 return false;
2883 }
2884
2885 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2886 return the class of reg to actually use. */
2887
2888 static reg_class_t
2889 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2890 {
2891 switch (GET_CODE (op))
2892 {
2893 /* Constants we cannot reload into general registers
2894 must be forced into the literal pool. */
2895 case CONST_DOUBLE:
2896 case CONST_INT:
2897 if (reg_class_subset_p (GENERAL_REGS, rclass)
2898 && legitimate_reload_constant_p (op))
2899 return GENERAL_REGS;
2900 else if (reg_class_subset_p (ADDR_REGS, rclass)
2901 && legitimate_reload_constant_p (op))
2902 return ADDR_REGS;
2903 else if (reg_class_subset_p (FP_REGS, rclass)
2904 && legitimate_reload_fp_constant_p (op))
2905 return FP_REGS;
2906 return NO_REGS;
2907
2908 /* If a symbolic constant or a PLUS is reloaded,
2909 it is most likely being used as an address, so
2910 prefer ADDR_REGS. If 'class' is not a superset
2911 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2912 case LABEL_REF:
2913 case SYMBOL_REF:
2914 case CONST:
2915 if (!legitimate_reload_constant_p (op))
2916 return NO_REGS;
2917 /* fallthrough */
2918 case PLUS:
2919 /* load address will be used. */
2920 if (reg_class_subset_p (ADDR_REGS, rclass))
2921 return ADDR_REGS;
2922 else
2923 return NO_REGS;
2924
2925 default:
2926 break;
2927 }
2928
2929 return rclass;
2930 }
2931
2932 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2933 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2934 aligned. */
2935
2936 bool
2937 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2938 {
2939 HOST_WIDE_INT addend;
2940 rtx symref;
2941
2942 if (!s390_symref_operand_p (addr, &symref, &addend))
2943 return false;
2944
2945 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2946 && !(addend & (alignment - 1)));
2947 }
2948
2949 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2950 operand SCRATCH is used to reload the even part of the address and
2951 adding one. */
2952
2953 void
2954 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2955 {
2956 HOST_WIDE_INT addend;
2957 rtx symref;
2958
2959 if (!s390_symref_operand_p (addr, &symref, &addend))
2960 gcc_unreachable ();
2961
2962 if (!(addend & 1))
2963 /* Easy case. The addend is even so larl will do fine. */
2964 emit_move_insn (reg, addr);
2965 else
2966 {
2967 /* We can leave the scratch register untouched if the target
2968 register is a valid base register. */
2969 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2970 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2971 scratch = reg;
2972
2973 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2974 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2975
2976 if (addend != 1)
2977 emit_move_insn (scratch,
2978 gen_rtx_CONST (Pmode,
2979 gen_rtx_PLUS (Pmode, symref,
2980 GEN_INT (addend - 1))));
2981 else
2982 emit_move_insn (scratch, symref);
2983
2984 /* Increment the address using la in order to avoid clobbering cc. */
2985 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2986 }
2987 }
2988
2989 /* Generate what is necessary to move between REG and MEM using
2990 SCRATCH. The direction is given by TOMEM. */
2991
2992 void
2993 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2994 {
2995 /* Reload might have pulled a constant out of the literal pool.
2996 Force it back in. */
2997 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2998 || GET_CODE (mem) == CONST)
2999 mem = force_const_mem (GET_MODE (reg), mem);
3000
3001 gcc_assert (MEM_P (mem));
3002
3003 /* For a load from memory we can leave the scratch register
3004 untouched if the target register is a valid base register. */
3005 if (!tomem
3006 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3007 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3008 && GET_MODE (reg) == GET_MODE (scratch))
3009 scratch = reg;
3010
3011 /* Load address into scratch register. Since we can't have a
3012 secondary reload for a secondary reload we have to cover the case
3013 where larl would need a secondary reload here as well. */
3014 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3015
3016 /* Now we can use a standard load/store to do the move. */
3017 if (tomem)
3018 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3019 else
3020 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3021 }
3022
3023 /* Inform reload about cases where moving X with a mode MODE to a register in
3024 RCLASS requires an extra scratch or immediate register. Return the class
3025 needed for the immediate register. */
3026
3027 static reg_class_t
3028 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3029 enum machine_mode mode, secondary_reload_info *sri)
3030 {
3031 enum reg_class rclass = (enum reg_class) rclass_i;
3032
3033 /* Intermediate register needed. */
3034 if (reg_classes_intersect_p (CC_REGS, rclass))
3035 return GENERAL_REGS;
3036
3037 if (TARGET_Z10)
3038 {
3039 HOST_WIDE_INT offset;
3040 rtx symref;
3041
3042 /* On z10 several optimizer steps may generate larl operands with
3043 an odd addend. */
3044 if (in_p
3045 && s390_symref_operand_p (x, &symref, &offset)
3046 && mode == Pmode
3047 && !SYMBOL_REF_ALIGN1_P (symref)
3048 && (offset & 1) == 1)
3049 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3050 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3051
3052 /* On z10 we need a scratch register when moving QI, TI or floating
3053 point mode values from or to a memory location with a SYMBOL_REF
3054 or if the symref addend of a SI or DI move is not aligned to the
3055 width of the access. */
3056 if (MEM_P (x)
3057 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3058 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3059 || (!TARGET_ZARCH && mode == DImode)
3060 || ((mode == HImode || mode == SImode || mode == DImode)
3061 && (!s390_check_symref_alignment (XEXP (x, 0),
3062 GET_MODE_SIZE (mode))))))
3063 {
3064 #define __SECONDARY_RELOAD_CASE(M,m) \
3065 case M##mode: \
3066 if (TARGET_64BIT) \
3067 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3068 CODE_FOR_reload##m##di_tomem_z10; \
3069 else \
3070 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3071 CODE_FOR_reload##m##si_tomem_z10; \
3072 break;
3073
3074 switch (GET_MODE (x))
3075 {
3076 __SECONDARY_RELOAD_CASE (QI, qi);
3077 __SECONDARY_RELOAD_CASE (HI, hi);
3078 __SECONDARY_RELOAD_CASE (SI, si);
3079 __SECONDARY_RELOAD_CASE (DI, di);
3080 __SECONDARY_RELOAD_CASE (TI, ti);
3081 __SECONDARY_RELOAD_CASE (SF, sf);
3082 __SECONDARY_RELOAD_CASE (DF, df);
3083 __SECONDARY_RELOAD_CASE (TF, tf);
3084 __SECONDARY_RELOAD_CASE (SD, sd);
3085 __SECONDARY_RELOAD_CASE (DD, dd);
3086 __SECONDARY_RELOAD_CASE (TD, td);
3087
3088 default:
3089 gcc_unreachable ();
3090 }
3091 #undef __SECONDARY_RELOAD_CASE
3092 }
3093 }
3094
3095 /* We need a scratch register when loading a PLUS expression which
3096 is not a legitimate operand of the LOAD ADDRESS instruction. */
3097 if (in_p && s390_plus_operand (x, mode))
3098 sri->icode = (TARGET_64BIT ?
3099 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3100
3101 /* Performing a multiword move from or to memory we have to make sure the
3102 second chunk in memory is addressable without causing a displacement
3103 overflow. If that would be the case we calculate the address in
3104 a scratch register. */
3105 if (MEM_P (x)
3106 && GET_CODE (XEXP (x, 0)) == PLUS
3107 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3108 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3109 + GET_MODE_SIZE (mode) - 1))
3110 {
3111 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3112 in a s_operand address since we may fallback to lm/stm. So we only
3113 have to care about overflows in the b+i+d case. */
3114 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3115 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3116 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3117 /* For FP_REGS no lm/stm is available so this check is triggered
3118 for displacement overflows in b+i+d and b+d like addresses. */
3119 || (reg_classes_intersect_p (FP_REGS, rclass)
3120 && s390_class_max_nregs (FP_REGS, mode) > 1))
3121 {
3122 if (in_p)
3123 sri->icode = (TARGET_64BIT ?
3124 CODE_FOR_reloaddi_nonoffmem_in :
3125 CODE_FOR_reloadsi_nonoffmem_in);
3126 else
3127 sri->icode = (TARGET_64BIT ?
3128 CODE_FOR_reloaddi_nonoffmem_out :
3129 CODE_FOR_reloadsi_nonoffmem_out);
3130 }
3131 }
3132
3133 /* A scratch address register is needed when a symbolic constant is
3134 copied to r0 compiling with -fPIC. In other cases the target
3135 register might be used as temporary (see legitimize_pic_address). */
3136 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3137 sri->icode = (TARGET_64BIT ?
3138 CODE_FOR_reloaddi_PIC_addr :
3139 CODE_FOR_reloadsi_PIC_addr);
3140
3141 /* Either scratch or no register needed. */
3142 return NO_REGS;
3143 }
3144
3145 /* Generate code to load SRC, which is PLUS that is not a
3146 legitimate operand for the LA instruction, into TARGET.
3147 SCRATCH may be used as scratch register. */
3148
3149 void
3150 s390_expand_plus_operand (rtx target, rtx src,
3151 rtx scratch)
3152 {
3153 rtx sum1, sum2;
3154 struct s390_address ad;
3155
3156 /* src must be a PLUS; get its two operands. */
3157 gcc_assert (GET_CODE (src) == PLUS);
3158 gcc_assert (GET_MODE (src) == Pmode);
3159
3160 /* Check if any of the two operands is already scheduled
3161 for replacement by reload. This can happen e.g. when
3162 float registers occur in an address. */
3163 sum1 = find_replacement (&XEXP (src, 0));
3164 sum2 = find_replacement (&XEXP (src, 1));
3165 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3166
3167 /* If the address is already strictly valid, there's nothing to do. */
3168 if (!s390_decompose_address (src, &ad)
3169 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3170 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3171 {
3172 /* Otherwise, one of the operands cannot be an address register;
3173 we reload its value into the scratch register. */
3174 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3175 {
3176 emit_move_insn (scratch, sum1);
3177 sum1 = scratch;
3178 }
3179 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3180 {
3181 emit_move_insn (scratch, sum2);
3182 sum2 = scratch;
3183 }
3184
3185 /* According to the way these invalid addresses are generated
3186 in reload.c, it should never happen (at least on s390) that
3187 *neither* of the PLUS components, after find_replacements
3188 was applied, is an address register. */
3189 if (sum1 == scratch && sum2 == scratch)
3190 {
3191 debug_rtx (src);
3192 gcc_unreachable ();
3193 }
3194
3195 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3196 }
3197
3198 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3199 is only ever performed on addresses, so we can mark the
3200 sum as legitimate for LA in any case. */
3201 s390_load_address (target, src);
3202 }
3203
3204
3205 /* Return true if ADDR is a valid memory address.
3206 STRICT specifies whether strict register checking applies. */
3207
3208 static bool
3209 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3210 {
3211 struct s390_address ad;
3212
3213 if (TARGET_Z10
3214 && larl_operand (addr, VOIDmode)
3215 && (mode == VOIDmode
3216 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3217 return true;
3218
3219 if (!s390_decompose_address (addr, &ad))
3220 return false;
3221
3222 if (strict)
3223 {
3224 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3225 return false;
3226
3227 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3228 return false;
3229 }
3230 else
3231 {
3232 if (ad.base
3233 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3234 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3235 return false;
3236
3237 if (ad.indx
3238 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3239 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3240 return false;
3241 }
3242 return true;
3243 }
3244
3245 /* Return true if OP is a valid operand for the LA instruction.
3246 In 31-bit, we need to prove that the result is used as an
3247 address, as LA performs only a 31-bit addition. */
3248
3249 bool
3250 legitimate_la_operand_p (rtx op)
3251 {
3252 struct s390_address addr;
3253 if (!s390_decompose_address (op, &addr))
3254 return false;
3255
3256 return (TARGET_64BIT || addr.pointer);
3257 }
3258
3259 /* Return true if it is valid *and* preferable to use LA to
3260 compute the sum of OP1 and OP2. */
3261
3262 bool
3263 preferred_la_operand_p (rtx op1, rtx op2)
3264 {
3265 struct s390_address addr;
3266
3267 if (op2 != const0_rtx)
3268 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3269
3270 if (!s390_decompose_address (op1, &addr))
3271 return false;
3272 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3273 return false;
3274 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3275 return false;
3276
3277 /* Avoid LA instructions with index register on z196; it is
3278 preferable to use regular add instructions when possible. */
3279 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3280 return false;
3281
3282 if (!TARGET_64BIT && !addr.pointer)
3283 return false;
3284
3285 if (addr.pointer)
3286 return true;
3287
3288 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3289 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3290 return true;
3291
3292 return false;
3293 }
3294
3295 /* Emit a forced load-address operation to load SRC into DST.
3296 This will use the LOAD ADDRESS instruction even in situations
3297 where legitimate_la_operand_p (SRC) returns false. */
3298
3299 void
3300 s390_load_address (rtx dst, rtx src)
3301 {
3302 if (TARGET_64BIT)
3303 emit_move_insn (dst, src);
3304 else
3305 emit_insn (gen_force_la_31 (dst, src));
3306 }
3307
3308 /* Return a legitimate reference for ORIG (an address) using the
3309 register REG. If REG is 0, a new pseudo is generated.
3310
3311 There are two types of references that must be handled:
3312
3313 1. Global data references must load the address from the GOT, via
3314 the PIC reg. An insn is emitted to do this load, and the reg is
3315 returned.
3316
3317 2. Static data references, constant pool addresses, and code labels
3318 compute the address as an offset from the GOT, whose base is in
3319 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3320 differentiate them from global data objects. The returned
3321 address is the PIC reg + an unspec constant.
3322
3323 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3324 reg also appears in the address. */
3325
3326 rtx
3327 legitimize_pic_address (rtx orig, rtx reg)
3328 {
3329 rtx addr = orig;
3330 rtx new_rtx = orig;
3331 rtx base;
3332
3333 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3334
3335 if (GET_CODE (addr) == LABEL_REF
3336 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3337 {
3338 /* This is a local symbol. */
3339 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3340 {
3341 /* Access local symbols PC-relative via LARL.
3342 This is the same as in the non-PIC case, so it is
3343 handled automatically ... */
3344 }
3345 else
3346 {
3347 /* Access local symbols relative to the GOT. */
3348
3349 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3350
3351 if (reload_in_progress || reload_completed)
3352 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3353
3354 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3355 addr = gen_rtx_CONST (Pmode, addr);
3356 addr = force_const_mem (Pmode, addr);
3357 emit_move_insn (temp, addr);
3358
3359 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3360 if (reg != 0)
3361 {
3362 s390_load_address (reg, new_rtx);
3363 new_rtx = reg;
3364 }
3365 }
3366 }
3367 else if (GET_CODE (addr) == SYMBOL_REF)
3368 {
3369 if (reg == 0)
3370 reg = gen_reg_rtx (Pmode);
3371
3372 if (flag_pic == 1)
3373 {
3374 /* Assume GOT offset < 4k. This is handled the same way
3375 in both 31- and 64-bit code (@GOT). */
3376
3377 if (reload_in_progress || reload_completed)
3378 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3379
3380 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3381 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3382 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3383 new_rtx = gen_const_mem (Pmode, new_rtx);
3384 emit_move_insn (reg, new_rtx);
3385 new_rtx = reg;
3386 }
3387 else if (TARGET_CPU_ZARCH)
3388 {
3389 /* If the GOT offset might be >= 4k, we determine the position
3390 of the GOT entry via a PC-relative LARL (@GOTENT). */
3391
3392 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3393
3394 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3395 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3396
3397 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3398 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3399 emit_move_insn (temp, new_rtx);
3400
3401 new_rtx = gen_const_mem (Pmode, temp);
3402 emit_move_insn (reg, new_rtx);
3403 new_rtx = reg;
3404 }
3405 else
3406 {
3407 /* If the GOT offset might be >= 4k, we have to load it
3408 from the literal pool (@GOT). */
3409
3410 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3411
3412 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3413 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3414
3415 if (reload_in_progress || reload_completed)
3416 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3417
3418 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3419 addr = gen_rtx_CONST (Pmode, addr);
3420 addr = force_const_mem (Pmode, addr);
3421 emit_move_insn (temp, addr);
3422
3423 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3424 new_rtx = gen_const_mem (Pmode, new_rtx);
3425 emit_move_insn (reg, new_rtx);
3426 new_rtx = reg;
3427 }
3428 }
3429 else
3430 {
3431 if (GET_CODE (addr) == CONST)
3432 {
3433 addr = XEXP (addr, 0);
3434 if (GET_CODE (addr) == UNSPEC)
3435 {
3436 gcc_assert (XVECLEN (addr, 0) == 1);
3437 switch (XINT (addr, 1))
3438 {
3439 /* If someone moved a GOT-relative UNSPEC
3440 out of the literal pool, force them back in. */
3441 case UNSPEC_GOTOFF:
3442 case UNSPEC_PLTOFF:
3443 new_rtx = force_const_mem (Pmode, orig);
3444 break;
3445
3446 /* @GOT is OK as is if small. */
3447 case UNSPEC_GOT:
3448 if (flag_pic == 2)
3449 new_rtx = force_const_mem (Pmode, orig);
3450 break;
3451
3452 /* @GOTENT is OK as is. */
3453 case UNSPEC_GOTENT:
3454 break;
3455
3456 /* @PLT is OK as is on 64-bit, must be converted to
3457 GOT-relative @PLTOFF on 31-bit. */
3458 case UNSPEC_PLT:
3459 if (!TARGET_CPU_ZARCH)
3460 {
3461 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3462
3463 if (reload_in_progress || reload_completed)
3464 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3465
3466 addr = XVECEXP (addr, 0, 0);
3467 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3468 UNSPEC_PLTOFF);
3469 addr = gen_rtx_CONST (Pmode, addr);
3470 addr = force_const_mem (Pmode, addr);
3471 emit_move_insn (temp, addr);
3472
3473 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3474 if (reg != 0)
3475 {
3476 s390_load_address (reg, new_rtx);
3477 new_rtx = reg;
3478 }
3479 }
3480 break;
3481
3482 /* Everything else cannot happen. */
3483 default:
3484 gcc_unreachable ();
3485 }
3486 }
3487 else
3488 gcc_assert (GET_CODE (addr) == PLUS);
3489 }
3490 if (GET_CODE (addr) == PLUS)
3491 {
3492 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3493
3494 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3495 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3496
3497 /* Check first to see if this is a constant offset
3498 from a local symbol reference. */
3499 if ((GET_CODE (op0) == LABEL_REF
3500 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3501 && GET_CODE (op1) == CONST_INT)
3502 {
3503 if (TARGET_CPU_ZARCH
3504 && larl_operand (op0, VOIDmode)
3505 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3506 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3507 {
3508 if (INTVAL (op1) & 1)
3509 {
3510 /* LARL can't handle odd offsets, so emit a
3511 pair of LARL and LA. */
3512 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3513
3514 if (!DISP_IN_RANGE (INTVAL (op1)))
3515 {
3516 HOST_WIDE_INT even = INTVAL (op1) - 1;
3517 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3518 op0 = gen_rtx_CONST (Pmode, op0);
3519 op1 = const1_rtx;
3520 }
3521
3522 emit_move_insn (temp, op0);
3523 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3524
3525 if (reg != 0)
3526 {
3527 s390_load_address (reg, new_rtx);
3528 new_rtx = reg;
3529 }
3530 }
3531 else
3532 {
3533 /* If the offset is even, we can just use LARL.
3534 This will happen automatically. */
3535 }
3536 }
3537 else
3538 {
3539 /* Access local symbols relative to the GOT. */
3540
3541 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3542
3543 if (reload_in_progress || reload_completed)
3544 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3545
3546 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3547 UNSPEC_GOTOFF);
3548 addr = gen_rtx_PLUS (Pmode, addr, op1);
3549 addr = gen_rtx_CONST (Pmode, addr);
3550 addr = force_const_mem (Pmode, addr);
3551 emit_move_insn (temp, addr);
3552
3553 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3554 if (reg != 0)
3555 {
3556 s390_load_address (reg, new_rtx);
3557 new_rtx = reg;
3558 }
3559 }
3560 }
3561
3562 /* Now, check whether it is a GOT relative symbol plus offset
3563 that was pulled out of the literal pool. Force it back in. */
3564
3565 else if (GET_CODE (op0) == UNSPEC
3566 && GET_CODE (op1) == CONST_INT
3567 && XINT (op0, 1) == UNSPEC_GOTOFF)
3568 {
3569 gcc_assert (XVECLEN (op0, 0) == 1);
3570
3571 new_rtx = force_const_mem (Pmode, orig);
3572 }
3573
3574 /* Otherwise, compute the sum. */
3575 else
3576 {
3577 base = legitimize_pic_address (XEXP (addr, 0), reg);
3578 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3579 base == reg ? NULL_RTX : reg);
3580 if (GET_CODE (new_rtx) == CONST_INT)
3581 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3582 else
3583 {
3584 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3585 {
3586 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3587 new_rtx = XEXP (new_rtx, 1);
3588 }
3589 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3590 }
3591
3592 if (GET_CODE (new_rtx) == CONST)
3593 new_rtx = XEXP (new_rtx, 0);
3594 new_rtx = force_operand (new_rtx, 0);
3595 }
3596 }
3597 }
3598 return new_rtx;
3599 }
3600
3601 /* Load the thread pointer into a register. */
3602
3603 rtx
3604 s390_get_thread_pointer (void)
3605 {
3606 rtx tp = gen_reg_rtx (Pmode);
3607
3608 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3609 mark_reg_pointer (tp, BITS_PER_WORD);
3610
3611 return tp;
3612 }
3613
3614 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3615 in s390_tls_symbol which always refers to __tls_get_offset.
3616 The returned offset is written to RESULT_REG and an USE rtx is
3617 generated for TLS_CALL. */
3618
3619 static GTY(()) rtx s390_tls_symbol;
3620
3621 static void
3622 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3623 {
3624 rtx insn;
3625
3626 if (!flag_pic)
3627 emit_insn (s390_load_got ());
3628
3629 if (!s390_tls_symbol)
3630 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3631
3632 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3633 gen_rtx_REG (Pmode, RETURN_REGNUM));
3634
3635 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3636 RTL_CONST_CALL_P (insn) = 1;
3637 }
3638
3639 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3640 this (thread-local) address. REG may be used as temporary. */
3641
3642 static rtx
3643 legitimize_tls_address (rtx addr, rtx reg)
3644 {
3645 rtx new_rtx, tls_call, temp, base, r2, insn;
3646
3647 if (GET_CODE (addr) == SYMBOL_REF)
3648 switch (tls_symbolic_operand (addr))
3649 {
3650 case TLS_MODEL_GLOBAL_DYNAMIC:
3651 start_sequence ();
3652 r2 = gen_rtx_REG (Pmode, 2);
3653 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3654 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3655 new_rtx = force_const_mem (Pmode, new_rtx);
3656 emit_move_insn (r2, new_rtx);
3657 s390_emit_tls_call_insn (r2, tls_call);
3658 insn = get_insns ();
3659 end_sequence ();
3660
3661 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3662 temp = gen_reg_rtx (Pmode);
3663 emit_libcall_block (insn, temp, r2, new_rtx);
3664
3665 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3666 if (reg != 0)
3667 {
3668 s390_load_address (reg, new_rtx);
3669 new_rtx = reg;
3670 }
3671 break;
3672
3673 case TLS_MODEL_LOCAL_DYNAMIC:
3674 start_sequence ();
3675 r2 = gen_rtx_REG (Pmode, 2);
3676 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3677 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3678 new_rtx = force_const_mem (Pmode, new_rtx);
3679 emit_move_insn (r2, new_rtx);
3680 s390_emit_tls_call_insn (r2, tls_call);
3681 insn = get_insns ();
3682 end_sequence ();
3683
3684 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3685 temp = gen_reg_rtx (Pmode);
3686 emit_libcall_block (insn, temp, r2, new_rtx);
3687
3688 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3689 base = gen_reg_rtx (Pmode);
3690 s390_load_address (base, new_rtx);
3691
3692 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3693 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3694 new_rtx = force_const_mem (Pmode, new_rtx);
3695 temp = gen_reg_rtx (Pmode);
3696 emit_move_insn (temp, new_rtx);
3697
3698 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3699 if (reg != 0)
3700 {
3701 s390_load_address (reg, new_rtx);
3702 new_rtx = reg;
3703 }
3704 break;
3705
3706 case TLS_MODEL_INITIAL_EXEC:
3707 if (flag_pic == 1)
3708 {
3709 /* Assume GOT offset < 4k. This is handled the same way
3710 in both 31- and 64-bit code. */
3711
3712 if (reload_in_progress || reload_completed)
3713 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3714
3715 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3716 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3717 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3718 new_rtx = gen_const_mem (Pmode, new_rtx);
3719 temp = gen_reg_rtx (Pmode);
3720 emit_move_insn (temp, new_rtx);
3721 }
3722 else if (TARGET_CPU_ZARCH)
3723 {
3724 /* If the GOT offset might be >= 4k, we determine the position
3725 of the GOT entry via a PC-relative LARL. */
3726
3727 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3728 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3729 temp = gen_reg_rtx (Pmode);
3730 emit_move_insn (temp, new_rtx);
3731
3732 new_rtx = gen_const_mem (Pmode, temp);
3733 temp = gen_reg_rtx (Pmode);
3734 emit_move_insn (temp, new_rtx);
3735 }
3736 else if (flag_pic)
3737 {
3738 /* If the GOT offset might be >= 4k, we have to load it
3739 from the literal pool. */
3740
3741 if (reload_in_progress || reload_completed)
3742 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3743
3744 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3745 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3746 new_rtx = force_const_mem (Pmode, new_rtx);
3747 temp = gen_reg_rtx (Pmode);
3748 emit_move_insn (temp, new_rtx);
3749
3750 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3751 new_rtx = gen_const_mem (Pmode, new_rtx);
3752
3753 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3754 temp = gen_reg_rtx (Pmode);
3755 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3756 }
3757 else
3758 {
3759 /* In position-dependent code, load the absolute address of
3760 the GOT entry from the literal pool. */
3761
3762 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3763 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3764 new_rtx = force_const_mem (Pmode, new_rtx);
3765 temp = gen_reg_rtx (Pmode);
3766 emit_move_insn (temp, new_rtx);
3767
3768 new_rtx = temp;
3769 new_rtx = gen_const_mem (Pmode, new_rtx);
3770 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3771 temp = gen_reg_rtx (Pmode);
3772 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3773 }
3774
3775 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3776 if (reg != 0)
3777 {
3778 s390_load_address (reg, new_rtx);
3779 new_rtx = reg;
3780 }
3781 break;
3782
3783 case TLS_MODEL_LOCAL_EXEC:
3784 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3785 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3786 new_rtx = force_const_mem (Pmode, new_rtx);
3787 temp = gen_reg_rtx (Pmode);
3788 emit_move_insn (temp, new_rtx);
3789
3790 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3791 if (reg != 0)
3792 {
3793 s390_load_address (reg, new_rtx);
3794 new_rtx = reg;
3795 }
3796 break;
3797
3798 default:
3799 gcc_unreachable ();
3800 }
3801
3802 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3803 {
3804 switch (XINT (XEXP (addr, 0), 1))
3805 {
3806 case UNSPEC_INDNTPOFF:
3807 gcc_assert (TARGET_CPU_ZARCH);
3808 new_rtx = addr;
3809 break;
3810
3811 default:
3812 gcc_unreachable ();
3813 }
3814 }
3815
3816 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3817 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3818 {
3819 new_rtx = XEXP (XEXP (addr, 0), 0);
3820 if (GET_CODE (new_rtx) != SYMBOL_REF)
3821 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3822
3823 new_rtx = legitimize_tls_address (new_rtx, reg);
3824 new_rtx = plus_constant (Pmode, new_rtx,
3825 INTVAL (XEXP (XEXP (addr, 0), 1)));
3826 new_rtx = force_operand (new_rtx, 0);
3827 }
3828
3829 else
3830 gcc_unreachable (); /* for now ... */
3831
3832 return new_rtx;
3833 }
3834
3835 /* Emit insns making the address in operands[1] valid for a standard
3836 move to operands[0]. operands[1] is replaced by an address which
3837 should be used instead of the former RTX to emit the move
3838 pattern. */
3839
3840 void
3841 emit_symbolic_move (rtx *operands)
3842 {
3843 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3844
3845 if (GET_CODE (operands[0]) == MEM)
3846 operands[1] = force_reg (Pmode, operands[1]);
3847 else if (TLS_SYMBOLIC_CONST (operands[1]))
3848 operands[1] = legitimize_tls_address (operands[1], temp);
3849 else if (flag_pic)
3850 operands[1] = legitimize_pic_address (operands[1], temp);
3851 }
3852
3853 /* Try machine-dependent ways of modifying an illegitimate address X
3854 to be legitimate. If we find one, return the new, valid address.
3855
3856 OLDX is the address as it was before break_out_memory_refs was called.
3857 In some cases it is useful to look at this to decide what needs to be done.
3858
3859 MODE is the mode of the operand pointed to by X.
3860
3861 When -fpic is used, special handling is needed for symbolic references.
3862 See comments by legitimize_pic_address for details. */
3863
3864 static rtx
3865 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3866 enum machine_mode mode ATTRIBUTE_UNUSED)
3867 {
3868 rtx constant_term = const0_rtx;
3869
3870 if (TLS_SYMBOLIC_CONST (x))
3871 {
3872 x = legitimize_tls_address (x, 0);
3873
3874 if (s390_legitimate_address_p (mode, x, FALSE))
3875 return x;
3876 }
3877 else if (GET_CODE (x) == PLUS
3878 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3879 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3880 {
3881 return x;
3882 }
3883 else if (flag_pic)
3884 {
3885 if (SYMBOLIC_CONST (x)
3886 || (GET_CODE (x) == PLUS
3887 && (SYMBOLIC_CONST (XEXP (x, 0))
3888 || SYMBOLIC_CONST (XEXP (x, 1)))))
3889 x = legitimize_pic_address (x, 0);
3890
3891 if (s390_legitimate_address_p (mode, x, FALSE))
3892 return x;
3893 }
3894
3895 x = eliminate_constant_term (x, &constant_term);
3896
3897 /* Optimize loading of large displacements by splitting them
3898 into the multiple of 4K and the rest; this allows the
3899 former to be CSE'd if possible.
3900
3901 Don't do this if the displacement is added to a register
3902 pointing into the stack frame, as the offsets will
3903 change later anyway. */
3904
3905 if (GET_CODE (constant_term) == CONST_INT
3906 && !TARGET_LONG_DISPLACEMENT
3907 && !DISP_IN_RANGE (INTVAL (constant_term))
3908 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3909 {
3910 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3911 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3912
3913 rtx temp = gen_reg_rtx (Pmode);
3914 rtx val = force_operand (GEN_INT (upper), temp);
3915 if (val != temp)
3916 emit_move_insn (temp, val);
3917
3918 x = gen_rtx_PLUS (Pmode, x, temp);
3919 constant_term = GEN_INT (lower);
3920 }
3921
3922 if (GET_CODE (x) == PLUS)
3923 {
3924 if (GET_CODE (XEXP (x, 0)) == REG)
3925 {
3926 rtx temp = gen_reg_rtx (Pmode);
3927 rtx val = force_operand (XEXP (x, 1), temp);
3928 if (val != temp)
3929 emit_move_insn (temp, val);
3930
3931 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3932 }
3933
3934 else if (GET_CODE (XEXP (x, 1)) == REG)
3935 {
3936 rtx temp = gen_reg_rtx (Pmode);
3937 rtx val = force_operand (XEXP (x, 0), temp);
3938 if (val != temp)
3939 emit_move_insn (temp, val);
3940
3941 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3942 }
3943 }
3944
3945 if (constant_term != const0_rtx)
3946 x = gen_rtx_PLUS (Pmode, x, constant_term);
3947
3948 return x;
3949 }
3950
3951 /* Try a machine-dependent way of reloading an illegitimate address AD
3952 operand. If we find one, push the reload and return the new address.
3953
3954 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3955 and TYPE is the reload type of the current reload. */
3956
3957 rtx
3958 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3959 int opnum, int type)
3960 {
3961 if (!optimize || TARGET_LONG_DISPLACEMENT)
3962 return NULL_RTX;
3963
3964 if (GET_CODE (ad) == PLUS)
3965 {
3966 rtx tem = simplify_binary_operation (PLUS, Pmode,
3967 XEXP (ad, 0), XEXP (ad, 1));
3968 if (tem)
3969 ad = tem;
3970 }
3971
3972 if (GET_CODE (ad) == PLUS
3973 && GET_CODE (XEXP (ad, 0)) == REG
3974 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3975 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3976 {
3977 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3978 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3979 rtx cst, tem, new_rtx;
3980
3981 cst = GEN_INT (upper);
3982 if (!legitimate_reload_constant_p (cst))
3983 cst = force_const_mem (Pmode, cst);
3984
3985 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3986 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3987
3988 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3989 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3990 opnum, (enum reload_type) type);
3991 return new_rtx;
3992 }
3993
3994 return NULL_RTX;
3995 }
3996
3997 /* Emit code to move LEN bytes from DST to SRC. */
3998
3999 bool
4000 s390_expand_movmem (rtx dst, rtx src, rtx len)
4001 {
4002 /* When tuning for z10 or higher we rely on the Glibc functions to
4003 do the right thing. Only for constant lengths below 64k we will
4004 generate inline code. */
4005 if (s390_tune >= PROCESSOR_2097_Z10
4006 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4007 return false;
4008
4009 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4010 {
4011 if (INTVAL (len) > 0)
4012 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4013 }
4014
4015 else if (TARGET_MVCLE)
4016 {
4017 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4018 }
4019
4020 else
4021 {
4022 rtx dst_addr, src_addr, count, blocks, temp;
4023 rtx loop_start_label = gen_label_rtx ();
4024 rtx loop_end_label = gen_label_rtx ();
4025 rtx end_label = gen_label_rtx ();
4026 enum machine_mode mode;
4027
4028 mode = GET_MODE (len);
4029 if (mode == VOIDmode)
4030 mode = Pmode;
4031
4032 dst_addr = gen_reg_rtx (Pmode);
4033 src_addr = gen_reg_rtx (Pmode);
4034 count = gen_reg_rtx (mode);
4035 blocks = gen_reg_rtx (mode);
4036
4037 convert_move (count, len, 1);
4038 emit_cmp_and_jump_insns (count, const0_rtx,
4039 EQ, NULL_RTX, mode, 1, end_label);
4040
4041 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4042 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4043 dst = change_address (dst, VOIDmode, dst_addr);
4044 src = change_address (src, VOIDmode, src_addr);
4045
4046 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4047 OPTAB_DIRECT);
4048 if (temp != count)
4049 emit_move_insn (count, temp);
4050
4051 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4052 OPTAB_DIRECT);
4053 if (temp != blocks)
4054 emit_move_insn (blocks, temp);
4055
4056 emit_cmp_and_jump_insns (blocks, const0_rtx,
4057 EQ, NULL_RTX, mode, 1, loop_end_label);
4058
4059 emit_label (loop_start_label);
4060
4061 if (TARGET_Z10
4062 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4063 {
4064 rtx prefetch;
4065
4066 /* Issue a read prefetch for the +3 cache line. */
4067 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4068 const0_rtx, const0_rtx);
4069 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4070 emit_insn (prefetch);
4071
4072 /* Issue a write prefetch for the +3 cache line. */
4073 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4074 const1_rtx, const0_rtx);
4075 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4076 emit_insn (prefetch);
4077 }
4078
4079 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4080 s390_load_address (dst_addr,
4081 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4082 s390_load_address (src_addr,
4083 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4084
4085 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4086 OPTAB_DIRECT);
4087 if (temp != blocks)
4088 emit_move_insn (blocks, temp);
4089
4090 emit_cmp_and_jump_insns (blocks, const0_rtx,
4091 EQ, NULL_RTX, mode, 1, loop_end_label);
4092
4093 emit_jump (loop_start_label);
4094 emit_label (loop_end_label);
4095
4096 emit_insn (gen_movmem_short (dst, src,
4097 convert_to_mode (Pmode, count, 1)));
4098 emit_label (end_label);
4099 }
4100 return true;
4101 }
4102
4103 /* Emit code to set LEN bytes at DST to VAL.
4104 Make use of clrmem if VAL is zero. */
4105
4106 void
4107 s390_expand_setmem (rtx dst, rtx len, rtx val)
4108 {
4109 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4110 return;
4111
4112 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4113
4114 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4115 {
4116 if (val == const0_rtx && INTVAL (len) <= 256)
4117 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4118 else
4119 {
4120 /* Initialize memory by storing the first byte. */
4121 emit_move_insn (adjust_address (dst, QImode, 0), val);
4122
4123 if (INTVAL (len) > 1)
4124 {
4125 /* Initiate 1 byte overlap move.
4126 The first byte of DST is propagated through DSTP1.
4127 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4128 DST is set to size 1 so the rest of the memory location
4129 does not count as source operand. */
4130 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4131 set_mem_size (dst, 1);
4132
4133 emit_insn (gen_movmem_short (dstp1, dst,
4134 GEN_INT (INTVAL (len) - 2)));
4135 }
4136 }
4137 }
4138
4139 else if (TARGET_MVCLE)
4140 {
4141 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4142 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4143 }
4144
4145 else
4146 {
4147 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4148 rtx loop_start_label = gen_label_rtx ();
4149 rtx loop_end_label = gen_label_rtx ();
4150 rtx end_label = gen_label_rtx ();
4151 enum machine_mode mode;
4152
4153 mode = GET_MODE (len);
4154 if (mode == VOIDmode)
4155 mode = Pmode;
4156
4157 dst_addr = gen_reg_rtx (Pmode);
4158 count = gen_reg_rtx (mode);
4159 blocks = gen_reg_rtx (mode);
4160
4161 convert_move (count, len, 1);
4162 emit_cmp_and_jump_insns (count, const0_rtx,
4163 EQ, NULL_RTX, mode, 1, end_label);
4164
4165 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4166 dst = change_address (dst, VOIDmode, dst_addr);
4167
4168 if (val == const0_rtx)
4169 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4170 OPTAB_DIRECT);
4171 else
4172 {
4173 dstp1 = adjust_address (dst, VOIDmode, 1);
4174 set_mem_size (dst, 1);
4175
4176 /* Initialize memory by storing the first byte. */
4177 emit_move_insn (adjust_address (dst, QImode, 0), val);
4178
4179 /* If count is 1 we are done. */
4180 emit_cmp_and_jump_insns (count, const1_rtx,
4181 EQ, NULL_RTX, mode, 1, end_label);
4182
4183 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4184 OPTAB_DIRECT);
4185 }
4186 if (temp != count)
4187 emit_move_insn (count, temp);
4188
4189 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4190 OPTAB_DIRECT);
4191 if (temp != blocks)
4192 emit_move_insn (blocks, temp);
4193
4194 emit_cmp_and_jump_insns (blocks, const0_rtx,
4195 EQ, NULL_RTX, mode, 1, loop_end_label);
4196
4197 emit_label (loop_start_label);
4198
4199 if (TARGET_Z10
4200 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4201 {
4202 /* Issue a write prefetch for the +4 cache line. */
4203 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4204 GEN_INT (1024)),
4205 const1_rtx, const0_rtx);
4206 emit_insn (prefetch);
4207 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4208 }
4209
4210 if (val == const0_rtx)
4211 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4212 else
4213 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4214 s390_load_address (dst_addr,
4215 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4216
4217 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4218 OPTAB_DIRECT);
4219 if (temp != blocks)
4220 emit_move_insn (blocks, temp);
4221
4222 emit_cmp_and_jump_insns (blocks, const0_rtx,
4223 EQ, NULL_RTX, mode, 1, loop_end_label);
4224
4225 emit_jump (loop_start_label);
4226 emit_label (loop_end_label);
4227
4228 if (val == const0_rtx)
4229 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4230 else
4231 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4232 emit_label (end_label);
4233 }
4234 }
4235
4236 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4237 and return the result in TARGET. */
4238
4239 bool
4240 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4241 {
4242 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4243 rtx tmp;
4244
4245 /* When tuning for z10 or higher we rely on the Glibc functions to
4246 do the right thing. Only for constant lengths below 64k we will
4247 generate inline code. */
4248 if (s390_tune >= PROCESSOR_2097_Z10
4249 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4250 return false;
4251
4252 /* As the result of CMPINT is inverted compared to what we need,
4253 we have to swap the operands. */
4254 tmp = op0; op0 = op1; op1 = tmp;
4255
4256 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4257 {
4258 if (INTVAL (len) > 0)
4259 {
4260 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4261 emit_insn (gen_cmpint (target, ccreg));
4262 }
4263 else
4264 emit_move_insn (target, const0_rtx);
4265 }
4266 else if (TARGET_MVCLE)
4267 {
4268 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4269 emit_insn (gen_cmpint (target, ccreg));
4270 }
4271 else
4272 {
4273 rtx addr0, addr1, count, blocks, temp;
4274 rtx loop_start_label = gen_label_rtx ();
4275 rtx loop_end_label = gen_label_rtx ();
4276 rtx end_label = gen_label_rtx ();
4277 enum machine_mode mode;
4278
4279 mode = GET_MODE (len);
4280 if (mode == VOIDmode)
4281 mode = Pmode;
4282
4283 addr0 = gen_reg_rtx (Pmode);
4284 addr1 = gen_reg_rtx (Pmode);
4285 count = gen_reg_rtx (mode);
4286 blocks = gen_reg_rtx (mode);
4287
4288 convert_move (count, len, 1);
4289 emit_cmp_and_jump_insns (count, const0_rtx,
4290 EQ, NULL_RTX, mode, 1, end_label);
4291
4292 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4293 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4294 op0 = change_address (op0, VOIDmode, addr0);
4295 op1 = change_address (op1, VOIDmode, addr1);
4296
4297 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4298 OPTAB_DIRECT);
4299 if (temp != count)
4300 emit_move_insn (count, temp);
4301
4302 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4303 OPTAB_DIRECT);
4304 if (temp != blocks)
4305 emit_move_insn (blocks, temp);
4306
4307 emit_cmp_and_jump_insns (blocks, const0_rtx,
4308 EQ, NULL_RTX, mode, 1, loop_end_label);
4309
4310 emit_label (loop_start_label);
4311
4312 if (TARGET_Z10
4313 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4314 {
4315 rtx prefetch;
4316
4317 /* Issue a read prefetch for the +2 cache line of operand 1. */
4318 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4319 const0_rtx, const0_rtx);
4320 emit_insn (prefetch);
4321 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4322
4323 /* Issue a read prefetch for the +2 cache line of operand 2. */
4324 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4325 const0_rtx, const0_rtx);
4326 emit_insn (prefetch);
4327 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4328 }
4329
4330 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4331 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4332 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4333 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4334 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4335 emit_jump_insn (temp);
4336
4337 s390_load_address (addr0,
4338 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4339 s390_load_address (addr1,
4340 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4341
4342 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4343 OPTAB_DIRECT);
4344 if (temp != blocks)
4345 emit_move_insn (blocks, temp);
4346
4347 emit_cmp_and_jump_insns (blocks, const0_rtx,
4348 EQ, NULL_RTX, mode, 1, loop_end_label);
4349
4350 emit_jump (loop_start_label);
4351 emit_label (loop_end_label);
4352
4353 emit_insn (gen_cmpmem_short (op0, op1,
4354 convert_to_mode (Pmode, count, 1)));
4355 emit_label (end_label);
4356
4357 emit_insn (gen_cmpint (target, ccreg));
4358 }
4359 return true;
4360 }
4361
4362
4363 /* Expand conditional increment or decrement using alc/slb instructions.
4364 Should generate code setting DST to either SRC or SRC + INCREMENT,
4365 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4366 Returns true if successful, false otherwise.
4367
4368 That makes it possible to implement some if-constructs without jumps e.g.:
4369 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4370 unsigned int a, b, c;
4371 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4372 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4373 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4374 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4375
4376 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4377 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4378 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4379 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4380 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4381
4382 bool
4383 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4384 rtx dst, rtx src, rtx increment)
4385 {
4386 enum machine_mode cmp_mode;
4387 enum machine_mode cc_mode;
4388 rtx op_res;
4389 rtx insn;
4390 rtvec p;
4391 int ret;
4392
4393 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4394 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4395 cmp_mode = SImode;
4396 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4397 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4398 cmp_mode = DImode;
4399 else
4400 return false;
4401
4402 /* Try ADD LOGICAL WITH CARRY. */
4403 if (increment == const1_rtx)
4404 {
4405 /* Determine CC mode to use. */
4406 if (cmp_code == EQ || cmp_code == NE)
4407 {
4408 if (cmp_op1 != const0_rtx)
4409 {
4410 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4411 NULL_RTX, 0, OPTAB_WIDEN);
4412 cmp_op1 = const0_rtx;
4413 }
4414
4415 cmp_code = cmp_code == EQ ? LEU : GTU;
4416 }
4417
4418 if (cmp_code == LTU || cmp_code == LEU)
4419 {
4420 rtx tem = cmp_op0;
4421 cmp_op0 = cmp_op1;
4422 cmp_op1 = tem;
4423 cmp_code = swap_condition (cmp_code);
4424 }
4425
4426 switch (cmp_code)
4427 {
4428 case GTU:
4429 cc_mode = CCUmode;
4430 break;
4431
4432 case GEU:
4433 cc_mode = CCL3mode;
4434 break;
4435
4436 default:
4437 return false;
4438 }
4439
4440 /* Emit comparison instruction pattern. */
4441 if (!register_operand (cmp_op0, cmp_mode))
4442 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4443
4444 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4445 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4446 /* We use insn_invalid_p here to add clobbers if required. */
4447 ret = insn_invalid_p (emit_insn (insn), false);
4448 gcc_assert (!ret);
4449
4450 /* Emit ALC instruction pattern. */
4451 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4452 gen_rtx_REG (cc_mode, CC_REGNUM),
4453 const0_rtx);
4454
4455 if (src != const0_rtx)
4456 {
4457 if (!register_operand (src, GET_MODE (dst)))
4458 src = force_reg (GET_MODE (dst), src);
4459
4460 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4461 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4462 }
4463
4464 p = rtvec_alloc (2);
4465 RTVEC_ELT (p, 0) =
4466 gen_rtx_SET (VOIDmode, dst, op_res);
4467 RTVEC_ELT (p, 1) =
4468 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4469 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4470
4471 return true;
4472 }
4473
4474 /* Try SUBTRACT LOGICAL WITH BORROW. */
4475 if (increment == constm1_rtx)
4476 {
4477 /* Determine CC mode to use. */
4478 if (cmp_code == EQ || cmp_code == NE)
4479 {
4480 if (cmp_op1 != const0_rtx)
4481 {
4482 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4483 NULL_RTX, 0, OPTAB_WIDEN);
4484 cmp_op1 = const0_rtx;
4485 }
4486
4487 cmp_code = cmp_code == EQ ? LEU : GTU;
4488 }
4489
4490 if (cmp_code == GTU || cmp_code == GEU)
4491 {
4492 rtx tem = cmp_op0;
4493 cmp_op0 = cmp_op1;
4494 cmp_op1 = tem;
4495 cmp_code = swap_condition (cmp_code);
4496 }
4497
4498 switch (cmp_code)
4499 {
4500 case LEU:
4501 cc_mode = CCUmode;
4502 break;
4503
4504 case LTU:
4505 cc_mode = CCL3mode;
4506 break;
4507
4508 default:
4509 return false;
4510 }
4511
4512 /* Emit comparison instruction pattern. */
4513 if (!register_operand (cmp_op0, cmp_mode))
4514 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4515
4516 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4517 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4518 /* We use insn_invalid_p here to add clobbers if required. */
4519 ret = insn_invalid_p (emit_insn (insn), false);
4520 gcc_assert (!ret);
4521
4522 /* Emit SLB instruction pattern. */
4523 if (!register_operand (src, GET_MODE (dst)))
4524 src = force_reg (GET_MODE (dst), src);
4525
4526 op_res = gen_rtx_MINUS (GET_MODE (dst),
4527 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4528 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4529 gen_rtx_REG (cc_mode, CC_REGNUM),
4530 const0_rtx));
4531 p = rtvec_alloc (2);
4532 RTVEC_ELT (p, 0) =
4533 gen_rtx_SET (VOIDmode, dst, op_res);
4534 RTVEC_ELT (p, 1) =
4535 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4536 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4537
4538 return true;
4539 }
4540
4541 return false;
4542 }
4543
4544 /* Expand code for the insv template. Return true if successful. */
4545
4546 bool
4547 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4548 {
4549 int bitsize = INTVAL (op1);
4550 int bitpos = INTVAL (op2);
4551
4552 /* On z10 we can use the risbg instruction to implement insv. */
4553 if (TARGET_Z10
4554 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4555 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4556 {
4557 rtx op;
4558 rtx clobber;
4559
4560 op = gen_rtx_SET (GET_MODE(src),
4561 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4562 src);
4563 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4564 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4565
4566 return true;
4567 }
4568
4569 /* We need byte alignment. */
4570 if (bitsize % BITS_PER_UNIT)
4571 return false;
4572
4573 if (bitpos == 0
4574 && memory_operand (dest, VOIDmode)
4575 && (register_operand (src, word_mode)
4576 || const_int_operand (src, VOIDmode)))
4577 {
4578 /* Emit standard pattern if possible. */
4579 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4580 if (GET_MODE_BITSIZE (mode) == bitsize)
4581 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4582
4583 /* (set (ze (mem)) (const_int)). */
4584 else if (const_int_operand (src, VOIDmode))
4585 {
4586 int size = bitsize / BITS_PER_UNIT;
4587 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4588 GET_MODE_SIZE (word_mode) - size);
4589
4590 dest = adjust_address (dest, BLKmode, 0);
4591 set_mem_size (dest, size);
4592 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4593 }
4594
4595 /* (set (ze (mem)) (reg)). */
4596 else if (register_operand (src, word_mode))
4597 {
4598 if (bitsize <= GET_MODE_BITSIZE (SImode))
4599 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4600 const0_rtx), src);
4601 else
4602 {
4603 /* Emit st,stcmh sequence. */
4604 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4605 int size = stcmh_width / BITS_PER_UNIT;
4606
4607 emit_move_insn (adjust_address (dest, SImode, size),
4608 gen_lowpart (SImode, src));
4609 set_mem_size (dest, size);
4610 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4611 (stcmh_width), const0_rtx),
4612 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4613 (GET_MODE_BITSIZE (SImode))));
4614 }
4615 }
4616 else
4617 return false;
4618
4619 return true;
4620 }
4621
4622 /* (set (ze (reg)) (const_int)). */
4623 if (TARGET_ZARCH
4624 && register_operand (dest, word_mode)
4625 && (bitpos % 16) == 0
4626 && (bitsize % 16) == 0
4627 && const_int_operand (src, VOIDmode))
4628 {
4629 HOST_WIDE_INT val = INTVAL (src);
4630 int regpos = bitpos + bitsize;
4631
4632 while (regpos > bitpos)
4633 {
4634 enum machine_mode putmode;
4635 int putsize;
4636
4637 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4638 putmode = SImode;
4639 else
4640 putmode = HImode;
4641
4642 putsize = GET_MODE_BITSIZE (putmode);
4643 regpos -= putsize;
4644 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4645 GEN_INT (putsize),
4646 GEN_INT (regpos)),
4647 gen_int_mode (val, putmode));
4648 val >>= putsize;
4649 }
4650 gcc_assert (regpos == bitpos);
4651 return true;
4652 }
4653
4654 return false;
4655 }
4656
4657 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4658 register that holds VAL of mode MODE shifted by COUNT bits. */
4659
4660 static inline rtx
4661 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4662 {
4663 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4664 NULL_RTX, 1, OPTAB_DIRECT);
4665 return expand_simple_binop (SImode, ASHIFT, val, count,
4666 NULL_RTX, 1, OPTAB_DIRECT);
4667 }
4668
4669 /* Structure to hold the initial parameters for a compare_and_swap operation
4670 in HImode and QImode. */
4671
4672 struct alignment_context
4673 {
4674 rtx memsi; /* SI aligned memory location. */
4675 rtx shift; /* Bit offset with regard to lsb. */
4676 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4677 rtx modemaski; /* ~modemask */
4678 bool aligned; /* True if memory is aligned, false else. */
4679 };
4680
4681 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4682 structure AC for transparent simplifying, if the memory alignment is known
4683 to be at least 32bit. MEM is the memory location for the actual operation
4684 and MODE its mode. */
4685
4686 static void
4687 init_alignment_context (struct alignment_context *ac, rtx mem,
4688 enum machine_mode mode)
4689 {
4690 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4691 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4692
4693 if (ac->aligned)
4694 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4695 else
4696 {
4697 /* Alignment is unknown. */
4698 rtx byteoffset, addr, align;
4699
4700 /* Force the address into a register. */
4701 addr = force_reg (Pmode, XEXP (mem, 0));
4702
4703 /* Align it to SImode. */
4704 align = expand_simple_binop (Pmode, AND, addr,
4705 GEN_INT (-GET_MODE_SIZE (SImode)),
4706 NULL_RTX, 1, OPTAB_DIRECT);
4707 /* Generate MEM. */
4708 ac->memsi = gen_rtx_MEM (SImode, align);
4709 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4710 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4711 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4712
4713 /* Calculate shiftcount. */
4714 byteoffset = expand_simple_binop (Pmode, AND, addr,
4715 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4716 NULL_RTX, 1, OPTAB_DIRECT);
4717 /* As we already have some offset, evaluate the remaining distance. */
4718 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4719 NULL_RTX, 1, OPTAB_DIRECT);
4720
4721 }
4722 /* Shift is the byte count, but we need the bitcount. */
4723 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4724 NULL_RTX, 1, OPTAB_DIRECT);
4725 /* Calculate masks. */
4726 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4727 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4728 NULL_RTX, 1, OPTAB_DIRECT);
4729 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4730 }
4731
4732 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4733 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4734 to set if CMP == MEM.
4735 CMP is never in memory for compare_and_swap_cc because
4736 expand_bool_compare_and_swap puts it into a register for later compare. */
4737
4738 void
4739 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4740 {
4741 struct alignment_context ac;
4742 rtx cmpv, newv, val, resv, cc;
4743 rtx res = gen_reg_rtx (SImode);
4744 rtx csloop = gen_label_rtx ();
4745 rtx csend = gen_label_rtx ();
4746
4747 gcc_assert (register_operand (target, VOIDmode));
4748 gcc_assert (MEM_P (mem));
4749
4750 init_alignment_context (&ac, mem, mode);
4751
4752 /* Shift the values to the correct bit positions. */
4753 if (!(ac.aligned && MEM_P (cmp)))
4754 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4755 if (!(ac.aligned && MEM_P (new_rtx)))
4756 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4757
4758 /* Load full word. Subsequent loads are performed by CS. */
4759 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4760 NULL_RTX, 1, OPTAB_DIRECT);
4761
4762 /* Start CS loop. */
4763 emit_label (csloop);
4764 /* val = "<mem>00..0<mem>"
4765 * cmp = "00..0<cmp>00..0"
4766 * new = "00..0<new>00..0"
4767 */
4768
4769 /* Patch cmp and new with val at correct position. */
4770 if (ac.aligned && MEM_P (cmp))
4771 {
4772 cmpv = force_reg (SImode, val);
4773 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0,
4774 0, 0, SImode, cmp);
4775 }
4776 else
4777 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4778 NULL_RTX, 1, OPTAB_DIRECT));
4779 if (ac.aligned && MEM_P (new_rtx))
4780 {
4781 newv = force_reg (SImode, val);
4782 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0,
4783 0, 0, SImode, new_rtx);
4784 }
4785 else
4786 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4787 NULL_RTX, 1, OPTAB_DIRECT));
4788
4789 /* Jump to end if we're done (likely?). */
4790 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4791 cmpv, newv));
4792
4793 /* Check for changes outside mode. */
4794 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4795 NULL_RTX, 1, OPTAB_DIRECT);
4796 cc = s390_emit_compare (NE, resv, val);
4797 emit_move_insn (val, resv);
4798 /* Loop internal if so. */
4799 s390_emit_jump (csloop, cc);
4800
4801 emit_label (csend);
4802
4803 /* Return the correct part of the bitfield. */
4804 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4805 NULL_RTX, 1, OPTAB_DIRECT), 1);
4806 }
4807
4808 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4809 and VAL the value to play with. If AFTER is true then store the value
4810 MEM holds after the operation, if AFTER is false then store the value MEM
4811 holds before the operation. If TARGET is zero then discard that value, else
4812 store it to TARGET. */
4813
4814 void
4815 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4816 rtx target, rtx mem, rtx val, bool after)
4817 {
4818 struct alignment_context ac;
4819 rtx cmp;
4820 rtx new_rtx = gen_reg_rtx (SImode);
4821 rtx orig = gen_reg_rtx (SImode);
4822 rtx csloop = gen_label_rtx ();
4823
4824 gcc_assert (!target || register_operand (target, VOIDmode));
4825 gcc_assert (MEM_P (mem));
4826
4827 init_alignment_context (&ac, mem, mode);
4828
4829 /* Shift val to the correct bit positions.
4830 Preserve "icm", but prevent "ex icm". */
4831 if (!(ac.aligned && code == SET && MEM_P (val)))
4832 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4833
4834 /* Further preparation insns. */
4835 if (code == PLUS || code == MINUS)
4836 emit_move_insn (orig, val);
4837 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4838 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4839 NULL_RTX, 1, OPTAB_DIRECT);
4840
4841 /* Load full word. Subsequent loads are performed by CS. */
4842 cmp = force_reg (SImode, ac.memsi);
4843
4844 /* Start CS loop. */
4845 emit_label (csloop);
4846 emit_move_insn (new_rtx, cmp);
4847
4848 /* Patch new with val at correct position. */
4849 switch (code)
4850 {
4851 case PLUS:
4852 case MINUS:
4853 val = expand_simple_binop (SImode, code, new_rtx, orig,
4854 NULL_RTX, 1, OPTAB_DIRECT);
4855 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4856 NULL_RTX, 1, OPTAB_DIRECT);
4857 /* FALLTHRU */
4858 case SET:
4859 if (ac.aligned && MEM_P (val))
4860 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
4861 0, 0, SImode, val);
4862 else
4863 {
4864 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4865 NULL_RTX, 1, OPTAB_DIRECT);
4866 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4867 NULL_RTX, 1, OPTAB_DIRECT);
4868 }
4869 break;
4870 case AND:
4871 case IOR:
4872 case XOR:
4873 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4874 NULL_RTX, 1, OPTAB_DIRECT);
4875 break;
4876 case MULT: /* NAND */
4877 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4878 NULL_RTX, 1, OPTAB_DIRECT);
4879 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4880 NULL_RTX, 1, OPTAB_DIRECT);
4881 break;
4882 default:
4883 gcc_unreachable ();
4884 }
4885
4886 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4887 ac.memsi, cmp, new_rtx));
4888
4889 /* Return the correct part of the bitfield. */
4890 if (target)
4891 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4892 after ? new_rtx : cmp, ac.shift,
4893 NULL_RTX, 1, OPTAB_DIRECT), 1);
4894 }
4895
4896 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4897 We need to emit DTP-relative relocations. */
4898
4899 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4900
4901 static void
4902 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4903 {
4904 switch (size)
4905 {
4906 case 4:
4907 fputs ("\t.long\t", file);
4908 break;
4909 case 8:
4910 fputs ("\t.quad\t", file);
4911 break;
4912 default:
4913 gcc_unreachable ();
4914 }
4915 output_addr_const (file, x);
4916 fputs ("@DTPOFF", file);
4917 }
4918
4919 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4920 /* Implement TARGET_MANGLE_TYPE. */
4921
4922 static const char *
4923 s390_mangle_type (const_tree type)
4924 {
4925 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4926 && TARGET_LONG_DOUBLE_128)
4927 return "g";
4928
4929 /* For all other types, use normal C++ mangling. */
4930 return NULL;
4931 }
4932 #endif
4933
4934 /* In the name of slightly smaller debug output, and to cater to
4935 general assembler lossage, recognize various UNSPEC sequences
4936 and turn them back into a direct symbol reference. */
4937
4938 static rtx
4939 s390_delegitimize_address (rtx orig_x)
4940 {
4941 rtx x, y;
4942
4943 orig_x = delegitimize_mem_from_attrs (orig_x);
4944 x = orig_x;
4945
4946 /* Extract the symbol ref from:
4947 (plus:SI (reg:SI 12 %r12)
4948 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4949 UNSPEC_GOTOFF/PLTOFF)))
4950 and
4951 (plus:SI (reg:SI 12 %r12)
4952 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4953 UNSPEC_GOTOFF/PLTOFF)
4954 (const_int 4 [0x4])))) */
4955 if (GET_CODE (x) == PLUS
4956 && REG_P (XEXP (x, 0))
4957 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
4958 && GET_CODE (XEXP (x, 1)) == CONST)
4959 {
4960 HOST_WIDE_INT offset = 0;
4961
4962 /* The const operand. */
4963 y = XEXP (XEXP (x, 1), 0);
4964
4965 if (GET_CODE (y) == PLUS
4966 && GET_CODE (XEXP (y, 1)) == CONST_INT)
4967 {
4968 offset = INTVAL (XEXP (y, 1));
4969 y = XEXP (y, 0);
4970 }
4971
4972 if (GET_CODE (y) == UNSPEC
4973 && (XINT (y, 1) == UNSPEC_GOTOFF
4974 || XINT (y, 1) == UNSPEC_PLTOFF))
4975 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
4976 }
4977
4978 if (GET_CODE (x) != MEM)
4979 return orig_x;
4980
4981 x = XEXP (x, 0);
4982 if (GET_CODE (x) == PLUS
4983 && GET_CODE (XEXP (x, 1)) == CONST
4984 && GET_CODE (XEXP (x, 0)) == REG
4985 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4986 {
4987 y = XEXP (XEXP (x, 1), 0);
4988 if (GET_CODE (y) == UNSPEC
4989 && XINT (y, 1) == UNSPEC_GOT)
4990 y = XVECEXP (y, 0, 0);
4991 else
4992 return orig_x;
4993 }
4994 else if (GET_CODE (x) == CONST)
4995 {
4996 /* Extract the symbol ref from:
4997 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
4998 UNSPEC_PLT/GOTENT))) */
4999
5000 y = XEXP (x, 0);
5001 if (GET_CODE (y) == UNSPEC
5002 && (XINT (y, 1) == UNSPEC_GOTENT
5003 || XINT (y, 1) == UNSPEC_PLT))
5004 y = XVECEXP (y, 0, 0);
5005 else
5006 return orig_x;
5007 }
5008 else
5009 return orig_x;
5010
5011 if (GET_MODE (orig_x) != Pmode)
5012 {
5013 if (GET_MODE (orig_x) == BLKmode)
5014 return orig_x;
5015 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5016 if (y == NULL_RTX)
5017 return orig_x;
5018 }
5019 return y;
5020 }
5021
5022 /* Output operand OP to stdio stream FILE.
5023 OP is an address (register + offset) which is not used to address data;
5024 instead the rightmost bits are interpreted as the value. */
5025
5026 static void
5027 print_shift_count_operand (FILE *file, rtx op)
5028 {
5029 HOST_WIDE_INT offset;
5030 rtx base;
5031
5032 /* Extract base register and offset. */
5033 if (!s390_decompose_shift_count (op, &base, &offset))
5034 gcc_unreachable ();
5035
5036 /* Sanity check. */
5037 if (base)
5038 {
5039 gcc_assert (GET_CODE (base) == REG);
5040 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5041 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5042 }
5043
5044 /* Offsets are constricted to twelve bits. */
5045 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5046 if (base)
5047 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5048 }
5049
5050 /* See 'get_some_local_dynamic_name'. */
5051
5052 static int
5053 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5054 {
5055 rtx x = *px;
5056
5057 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5058 {
5059 x = get_pool_constant (x);
5060 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5061 }
5062
5063 if (GET_CODE (x) == SYMBOL_REF
5064 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5065 {
5066 cfun->machine->some_ld_name = XSTR (x, 0);
5067 return 1;
5068 }
5069
5070 return 0;
5071 }
5072
5073 /* Locate some local-dynamic symbol still in use by this function
5074 so that we can print its name in local-dynamic base patterns. */
5075
5076 static const char *
5077 get_some_local_dynamic_name (void)
5078 {
5079 rtx insn;
5080
5081 if (cfun->machine->some_ld_name)
5082 return cfun->machine->some_ld_name;
5083
5084 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5085 if (INSN_P (insn)
5086 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5087 return cfun->machine->some_ld_name;
5088
5089 gcc_unreachable ();
5090 }
5091
5092 /* Output machine-dependent UNSPECs occurring in address constant X
5093 in assembler syntax to stdio stream FILE. Returns true if the
5094 constant X could be recognized, false otherwise. */
5095
5096 static bool
5097 s390_output_addr_const_extra (FILE *file, rtx x)
5098 {
5099 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5100 switch (XINT (x, 1))
5101 {
5102 case UNSPEC_GOTENT:
5103 output_addr_const (file, XVECEXP (x, 0, 0));
5104 fprintf (file, "@GOTENT");
5105 return true;
5106 case UNSPEC_GOT:
5107 output_addr_const (file, XVECEXP (x, 0, 0));
5108 fprintf (file, "@GOT");
5109 return true;
5110 case UNSPEC_GOTOFF:
5111 output_addr_const (file, XVECEXP (x, 0, 0));
5112 fprintf (file, "@GOTOFF");
5113 return true;
5114 case UNSPEC_PLT:
5115 output_addr_const (file, XVECEXP (x, 0, 0));
5116 fprintf (file, "@PLT");
5117 return true;
5118 case UNSPEC_PLTOFF:
5119 output_addr_const (file, XVECEXP (x, 0, 0));
5120 fprintf (file, "@PLTOFF");
5121 return true;
5122 case UNSPEC_TLSGD:
5123 output_addr_const (file, XVECEXP (x, 0, 0));
5124 fprintf (file, "@TLSGD");
5125 return true;
5126 case UNSPEC_TLSLDM:
5127 assemble_name (file, get_some_local_dynamic_name ());
5128 fprintf (file, "@TLSLDM");
5129 return true;
5130 case UNSPEC_DTPOFF:
5131 output_addr_const (file, XVECEXP (x, 0, 0));
5132 fprintf (file, "@DTPOFF");
5133 return true;
5134 case UNSPEC_NTPOFF:
5135 output_addr_const (file, XVECEXP (x, 0, 0));
5136 fprintf (file, "@NTPOFF");
5137 return true;
5138 case UNSPEC_GOTNTPOFF:
5139 output_addr_const (file, XVECEXP (x, 0, 0));
5140 fprintf (file, "@GOTNTPOFF");
5141 return true;
5142 case UNSPEC_INDNTPOFF:
5143 output_addr_const (file, XVECEXP (x, 0, 0));
5144 fprintf (file, "@INDNTPOFF");
5145 return true;
5146 }
5147
5148 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5149 switch (XINT (x, 1))
5150 {
5151 case UNSPEC_POOL_OFFSET:
5152 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5153 output_addr_const (file, x);
5154 return true;
5155 }
5156 return false;
5157 }
5158
5159 /* Output address operand ADDR in assembler syntax to
5160 stdio stream FILE. */
5161
5162 void
5163 print_operand_address (FILE *file, rtx addr)
5164 {
5165 struct s390_address ad;
5166
5167 if (s390_symref_operand_p (addr, NULL, NULL))
5168 {
5169 if (!TARGET_Z10)
5170 {
5171 output_operand_lossage ("symbolic memory references are "
5172 "only supported on z10 or later");
5173 return;
5174 }
5175 output_addr_const (file, addr);
5176 return;
5177 }
5178
5179 if (!s390_decompose_address (addr, &ad)
5180 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5181 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5182 output_operand_lossage ("cannot decompose address");
5183
5184 if (ad.disp)
5185 output_addr_const (file, ad.disp);
5186 else
5187 fprintf (file, "0");
5188
5189 if (ad.base && ad.indx)
5190 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5191 reg_names[REGNO (ad.base)]);
5192 else if (ad.base)
5193 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5194 }
5195
5196 /* Output operand X in assembler syntax to stdio stream FILE.
5197 CODE specified the format flag. The following format flags
5198 are recognized:
5199
5200 'C': print opcode suffix for branch condition.
5201 'D': print opcode suffix for inverse branch condition.
5202 'E': print opcode suffix for branch on index instruction.
5203 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5204 'G': print the size of the operand in bytes.
5205 'O': print only the displacement of a memory reference.
5206 'R': print only the base register of a memory reference.
5207 'S': print S-type memory reference (base+displacement).
5208 'N': print the second word of a DImode operand.
5209 'M': print the second word of a TImode operand.
5210 'Y': print shift count operand.
5211
5212 'b': print integer X as if it's an unsigned byte.
5213 'c': print integer X as if it's an signed byte.
5214 'x': print integer X as if it's an unsigned halfword.
5215 'h': print integer X as if it's a signed halfword.
5216 'i': print the first nonzero HImode part of X.
5217 'j': print the first HImode part unequal to -1 of X.
5218 'k': print the first nonzero SImode part of X.
5219 'm': print the first SImode part unequal to -1 of X.
5220 'o': print integer X as if it's an unsigned 32bit word. */
5221
5222 void
5223 print_operand (FILE *file, rtx x, int code)
5224 {
5225 switch (code)
5226 {
5227 case 'C':
5228 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5229 return;
5230
5231 case 'D':
5232 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5233 return;
5234
5235 case 'E':
5236 if (GET_CODE (x) == LE)
5237 fprintf (file, "l");
5238 else if (GET_CODE (x) == GT)
5239 fprintf (file, "h");
5240 else
5241 output_operand_lossage ("invalid comparison operator "
5242 "for 'E' output modifier");
5243 return;
5244
5245 case 'J':
5246 if (GET_CODE (x) == SYMBOL_REF)
5247 {
5248 fprintf (file, "%s", ":tls_load:");
5249 output_addr_const (file, x);
5250 }
5251 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5252 {
5253 fprintf (file, "%s", ":tls_gdcall:");
5254 output_addr_const (file, XVECEXP (x, 0, 0));
5255 }
5256 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5257 {
5258 fprintf (file, "%s", ":tls_ldcall:");
5259 assemble_name (file, get_some_local_dynamic_name ());
5260 }
5261 else
5262 output_operand_lossage ("invalid reference for 'J' output modifier");
5263 return;
5264
5265 case 'G':
5266 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5267 return;
5268
5269 case 'O':
5270 {
5271 struct s390_address ad;
5272 int ret;
5273
5274 if (!MEM_P (x))
5275 {
5276 output_operand_lossage ("memory reference expected for "
5277 "'O' output modifier");
5278 return;
5279 }
5280
5281 ret = s390_decompose_address (XEXP (x, 0), &ad);
5282
5283 if (!ret
5284 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5285 || ad.indx)
5286 {
5287 output_operand_lossage ("invalid address for 'O' output modifier");
5288 return;
5289 }
5290
5291 if (ad.disp)
5292 output_addr_const (file, ad.disp);
5293 else
5294 fprintf (file, "0");
5295 }
5296 return;
5297
5298 case 'R':
5299 {
5300 struct s390_address ad;
5301 int ret;
5302
5303 if (!MEM_P (x))
5304 {
5305 output_operand_lossage ("memory reference expected for "
5306 "'R' output modifier");
5307 return;
5308 }
5309
5310 ret = s390_decompose_address (XEXP (x, 0), &ad);
5311
5312 if (!ret
5313 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5314 || ad.indx)
5315 {
5316 output_operand_lossage ("invalid address for 'R' output modifier");
5317 return;
5318 }
5319
5320 if (ad.base)
5321 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5322 else
5323 fprintf (file, "0");
5324 }
5325 return;
5326
5327 case 'S':
5328 {
5329 struct s390_address ad;
5330 int ret;
5331
5332 if (!MEM_P (x))
5333 {
5334 output_operand_lossage ("memory reference expected for "
5335 "'S' output modifier");
5336 return;
5337 }
5338 ret = s390_decompose_address (XEXP (x, 0), &ad);
5339
5340 if (!ret
5341 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5342 || ad.indx)
5343 {
5344 output_operand_lossage ("invalid address for 'S' output modifier");
5345 return;
5346 }
5347
5348 if (ad.disp)
5349 output_addr_const (file, ad.disp);
5350 else
5351 fprintf (file, "0");
5352
5353 if (ad.base)
5354 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5355 }
5356 return;
5357
5358 case 'N':
5359 if (GET_CODE (x) == REG)
5360 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5361 else if (GET_CODE (x) == MEM)
5362 x = change_address (x, VOIDmode,
5363 plus_constant (Pmode, XEXP (x, 0), 4));
5364 else
5365 output_operand_lossage ("register or memory expression expected "
5366 "for 'N' output modifier");
5367 break;
5368
5369 case 'M':
5370 if (GET_CODE (x) == REG)
5371 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5372 else if (GET_CODE (x) == MEM)
5373 x = change_address (x, VOIDmode,
5374 plus_constant (Pmode, XEXP (x, 0), 8));
5375 else
5376 output_operand_lossage ("register or memory expression expected "
5377 "for 'M' output modifier");
5378 break;
5379
5380 case 'Y':
5381 print_shift_count_operand (file, x);
5382 return;
5383 }
5384
5385 switch (GET_CODE (x))
5386 {
5387 case REG:
5388 fprintf (file, "%s", reg_names[REGNO (x)]);
5389 break;
5390
5391 case MEM:
5392 output_address (XEXP (x, 0));
5393 break;
5394
5395 case CONST:
5396 case CODE_LABEL:
5397 case LABEL_REF:
5398 case SYMBOL_REF:
5399 output_addr_const (file, x);
5400 break;
5401
5402 case CONST_INT:
5403 if (code == 'b')
5404 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5405 else if (code == 'c')
5406 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5407 else if (code == 'x')
5408 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5409 else if (code == 'h')
5410 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5411 else if (code == 'i')
5412 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5413 s390_extract_part (x, HImode, 0));
5414 else if (code == 'j')
5415 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5416 s390_extract_part (x, HImode, -1));
5417 else if (code == 'k')
5418 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5419 s390_extract_part (x, SImode, 0));
5420 else if (code == 'm')
5421 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5422 s390_extract_part (x, SImode, -1));
5423 else if (code == 'o')
5424 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5425 else
5426 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5427 break;
5428
5429 case CONST_DOUBLE:
5430 gcc_assert (GET_MODE (x) == VOIDmode);
5431 if (code == 'b')
5432 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5433 else if (code == 'x')
5434 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5435 else if (code == 'h')
5436 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5437 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5438 else
5439 {
5440 if (code == 0)
5441 output_operand_lossage ("invalid constant - try using "
5442 "an output modifier");
5443 else
5444 output_operand_lossage ("invalid constant for output modifier '%c'",
5445 code);
5446 }
5447 break;
5448
5449 default:
5450 if (code == 0)
5451 output_operand_lossage ("invalid expression - try using "
5452 "an output modifier");
5453 else
5454 output_operand_lossage ("invalid expression for output "
5455 "modifier '%c'", code);
5456 break;
5457 }
5458 }
5459
5460 /* Target hook for assembling integer objects. We need to define it
5461 here to work a round a bug in some versions of GAS, which couldn't
5462 handle values smaller than INT_MIN when printed in decimal. */
5463
5464 static bool
5465 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5466 {
5467 if (size == 8 && aligned_p
5468 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5469 {
5470 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5471 INTVAL (x));
5472 return true;
5473 }
5474 return default_assemble_integer (x, size, aligned_p);
5475 }
5476
5477 /* Returns true if register REGNO is used for forming
5478 a memory address in expression X. */
5479
5480 static bool
5481 reg_used_in_mem_p (int regno, rtx x)
5482 {
5483 enum rtx_code code = GET_CODE (x);
5484 int i, j;
5485 const char *fmt;
5486
5487 if (code == MEM)
5488 {
5489 if (refers_to_regno_p (regno, regno+1,
5490 XEXP (x, 0), 0))
5491 return true;
5492 }
5493 else if (code == SET
5494 && GET_CODE (SET_DEST (x)) == PC)
5495 {
5496 if (refers_to_regno_p (regno, regno+1,
5497 SET_SRC (x), 0))
5498 return true;
5499 }
5500
5501 fmt = GET_RTX_FORMAT (code);
5502 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5503 {
5504 if (fmt[i] == 'e'
5505 && reg_used_in_mem_p (regno, XEXP (x, i)))
5506 return true;
5507
5508 else if (fmt[i] == 'E')
5509 for (j = 0; j < XVECLEN (x, i); j++)
5510 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5511 return true;
5512 }
5513 return false;
5514 }
5515
5516 /* Returns true if expression DEP_RTX sets an address register
5517 used by instruction INSN to address memory. */
5518
5519 static bool
5520 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5521 {
5522 rtx target, pat;
5523
5524 if (GET_CODE (dep_rtx) == INSN)
5525 dep_rtx = PATTERN (dep_rtx);
5526
5527 if (GET_CODE (dep_rtx) == SET)
5528 {
5529 target = SET_DEST (dep_rtx);
5530 if (GET_CODE (target) == STRICT_LOW_PART)
5531 target = XEXP (target, 0);
5532 while (GET_CODE (target) == SUBREG)
5533 target = SUBREG_REG (target);
5534
5535 if (GET_CODE (target) == REG)
5536 {
5537 int regno = REGNO (target);
5538
5539 if (s390_safe_attr_type (insn) == TYPE_LA)
5540 {
5541 pat = PATTERN (insn);
5542 if (GET_CODE (pat) == PARALLEL)
5543 {
5544 gcc_assert (XVECLEN (pat, 0) == 2);
5545 pat = XVECEXP (pat, 0, 0);
5546 }
5547 gcc_assert (GET_CODE (pat) == SET);
5548 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5549 }
5550 else if (get_attr_atype (insn) == ATYPE_AGEN)
5551 return reg_used_in_mem_p (regno, PATTERN (insn));
5552 }
5553 }
5554 return false;
5555 }
5556
5557 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5558
5559 int
5560 s390_agen_dep_p (rtx dep_insn, rtx insn)
5561 {
5562 rtx dep_rtx = PATTERN (dep_insn);
5563 int i;
5564
5565 if (GET_CODE (dep_rtx) == SET
5566 && addr_generation_dependency_p (dep_rtx, insn))
5567 return 1;
5568 else if (GET_CODE (dep_rtx) == PARALLEL)
5569 {
5570 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5571 {
5572 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5573 return 1;
5574 }
5575 }
5576 return 0;
5577 }
5578
5579
5580 /* A C statement (sans semicolon) to update the integer scheduling priority
5581 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5582 reduce the priority to execute INSN later. Do not define this macro if
5583 you do not need to adjust the scheduling priorities of insns.
5584
5585 A STD instruction should be scheduled earlier,
5586 in order to use the bypass. */
5587 static int
5588 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5589 {
5590 if (! INSN_P (insn))
5591 return priority;
5592
5593 if (s390_tune != PROCESSOR_2084_Z990
5594 && s390_tune != PROCESSOR_2094_Z9_109
5595 && s390_tune != PROCESSOR_2097_Z10
5596 && s390_tune != PROCESSOR_2817_Z196)
5597 return priority;
5598
5599 switch (s390_safe_attr_type (insn))
5600 {
5601 case TYPE_FSTOREDF:
5602 case TYPE_FSTORESF:
5603 priority = priority << 3;
5604 break;
5605 case TYPE_STORE:
5606 case TYPE_STM:
5607 priority = priority << 1;
5608 break;
5609 default:
5610 break;
5611 }
5612 return priority;
5613 }
5614
5615
5616 /* The number of instructions that can be issued per cycle. */
5617
5618 static int
5619 s390_issue_rate (void)
5620 {
5621 switch (s390_tune)
5622 {
5623 case PROCESSOR_2084_Z990:
5624 case PROCESSOR_2094_Z9_109:
5625 case PROCESSOR_2817_Z196:
5626 return 3;
5627 case PROCESSOR_2097_Z10:
5628 return 2;
5629 default:
5630 return 1;
5631 }
5632 }
5633
5634 static int
5635 s390_first_cycle_multipass_dfa_lookahead (void)
5636 {
5637 return 4;
5638 }
5639
5640 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5641 Fix up MEMs as required. */
5642
5643 static void
5644 annotate_constant_pool_refs (rtx *x)
5645 {
5646 int i, j;
5647 const char *fmt;
5648
5649 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5650 || !CONSTANT_POOL_ADDRESS_P (*x));
5651
5652 /* Literal pool references can only occur inside a MEM ... */
5653 if (GET_CODE (*x) == MEM)
5654 {
5655 rtx memref = XEXP (*x, 0);
5656
5657 if (GET_CODE (memref) == SYMBOL_REF
5658 && CONSTANT_POOL_ADDRESS_P (memref))
5659 {
5660 rtx base = cfun->machine->base_reg;
5661 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5662 UNSPEC_LTREF);
5663
5664 *x = replace_equiv_address (*x, addr);
5665 return;
5666 }
5667
5668 if (GET_CODE (memref) == CONST
5669 && GET_CODE (XEXP (memref, 0)) == PLUS
5670 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5671 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5672 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5673 {
5674 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5675 rtx sym = XEXP (XEXP (memref, 0), 0);
5676 rtx base = cfun->machine->base_reg;
5677 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5678 UNSPEC_LTREF);
5679
5680 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5681 return;
5682 }
5683 }
5684
5685 /* ... or a load-address type pattern. */
5686 if (GET_CODE (*x) == SET)
5687 {
5688 rtx addrref = SET_SRC (*x);
5689
5690 if (GET_CODE (addrref) == SYMBOL_REF
5691 && CONSTANT_POOL_ADDRESS_P (addrref))
5692 {
5693 rtx base = cfun->machine->base_reg;
5694 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5695 UNSPEC_LTREF);
5696
5697 SET_SRC (*x) = addr;
5698 return;
5699 }
5700
5701 if (GET_CODE (addrref) == CONST
5702 && GET_CODE (XEXP (addrref, 0)) == PLUS
5703 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5704 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5705 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5706 {
5707 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5708 rtx sym = XEXP (XEXP (addrref, 0), 0);
5709 rtx base = cfun->machine->base_reg;
5710 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5711 UNSPEC_LTREF);
5712
5713 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5714 return;
5715 }
5716 }
5717
5718 /* Annotate LTREL_BASE as well. */
5719 if (GET_CODE (*x) == UNSPEC
5720 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5721 {
5722 rtx base = cfun->machine->base_reg;
5723 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5724 UNSPEC_LTREL_BASE);
5725 return;
5726 }
5727
5728 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5729 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5730 {
5731 if (fmt[i] == 'e')
5732 {
5733 annotate_constant_pool_refs (&XEXP (*x, i));
5734 }
5735 else if (fmt[i] == 'E')
5736 {
5737 for (j = 0; j < XVECLEN (*x, i); j++)
5738 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5739 }
5740 }
5741 }
5742
5743 /* Split all branches that exceed the maximum distance.
5744 Returns true if this created a new literal pool entry. */
5745
5746 static int
5747 s390_split_branches (void)
5748 {
5749 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5750 int new_literal = 0, ret;
5751 rtx insn, pat, tmp, target;
5752 rtx *label;
5753
5754 /* We need correct insn addresses. */
5755
5756 shorten_branches (get_insns ());
5757
5758 /* Find all branches that exceed 64KB, and split them. */
5759
5760 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5761 {
5762 if (GET_CODE (insn) != JUMP_INSN)
5763 continue;
5764
5765 pat = PATTERN (insn);
5766 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5767 pat = XVECEXP (pat, 0, 0);
5768 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5769 continue;
5770
5771 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5772 {
5773 label = &SET_SRC (pat);
5774 }
5775 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5776 {
5777 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5778 label = &XEXP (SET_SRC (pat), 1);
5779 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5780 label = &XEXP (SET_SRC (pat), 2);
5781 else
5782 continue;
5783 }
5784 else
5785 continue;
5786
5787 if (get_attr_length (insn) <= 4)
5788 continue;
5789
5790 /* We are going to use the return register as scratch register,
5791 make sure it will be saved/restored by the prologue/epilogue. */
5792 cfun_frame_layout.save_return_addr_p = 1;
5793
5794 if (!flag_pic)
5795 {
5796 new_literal = 1;
5797 tmp = force_const_mem (Pmode, *label);
5798 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5799 INSN_ADDRESSES_NEW (tmp, -1);
5800 annotate_constant_pool_refs (&PATTERN (tmp));
5801
5802 target = temp_reg;
5803 }
5804 else
5805 {
5806 new_literal = 1;
5807 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5808 UNSPEC_LTREL_OFFSET);
5809 target = gen_rtx_CONST (Pmode, target);
5810 target = force_const_mem (Pmode, target);
5811 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5812 INSN_ADDRESSES_NEW (tmp, -1);
5813 annotate_constant_pool_refs (&PATTERN (tmp));
5814
5815 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5816 cfun->machine->base_reg),
5817 UNSPEC_LTREL_BASE);
5818 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5819 }
5820
5821 ret = validate_change (insn, label, target, 0);
5822 gcc_assert (ret);
5823 }
5824
5825 return new_literal;
5826 }
5827
5828
5829 /* Find an annotated literal pool symbol referenced in RTX X,
5830 and store it at REF. Will abort if X contains references to
5831 more than one such pool symbol; multiple references to the same
5832 symbol are allowed, however.
5833
5834 The rtx pointed to by REF must be initialized to NULL_RTX
5835 by the caller before calling this routine. */
5836
5837 static void
5838 find_constant_pool_ref (rtx x, rtx *ref)
5839 {
5840 int i, j;
5841 const char *fmt;
5842
5843 /* Ignore LTREL_BASE references. */
5844 if (GET_CODE (x) == UNSPEC
5845 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5846 return;
5847 /* Likewise POOL_ENTRY insns. */
5848 if (GET_CODE (x) == UNSPEC_VOLATILE
5849 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5850 return;
5851
5852 gcc_assert (GET_CODE (x) != SYMBOL_REF
5853 || !CONSTANT_POOL_ADDRESS_P (x));
5854
5855 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5856 {
5857 rtx sym = XVECEXP (x, 0, 0);
5858 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5859 && CONSTANT_POOL_ADDRESS_P (sym));
5860
5861 if (*ref == NULL_RTX)
5862 *ref = sym;
5863 else
5864 gcc_assert (*ref == sym);
5865
5866 return;
5867 }
5868
5869 fmt = GET_RTX_FORMAT (GET_CODE (x));
5870 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5871 {
5872 if (fmt[i] == 'e')
5873 {
5874 find_constant_pool_ref (XEXP (x, i), ref);
5875 }
5876 else if (fmt[i] == 'E')
5877 {
5878 for (j = 0; j < XVECLEN (x, i); j++)
5879 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5880 }
5881 }
5882 }
5883
5884 /* Replace every reference to the annotated literal pool
5885 symbol REF in X by its base plus OFFSET. */
5886
5887 static void
5888 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5889 {
5890 int i, j;
5891 const char *fmt;
5892
5893 gcc_assert (*x != ref);
5894
5895 if (GET_CODE (*x) == UNSPEC
5896 && XINT (*x, 1) == UNSPEC_LTREF
5897 && XVECEXP (*x, 0, 0) == ref)
5898 {
5899 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5900 return;
5901 }
5902
5903 if (GET_CODE (*x) == PLUS
5904 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5905 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5906 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5907 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5908 {
5909 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5910 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
5911 return;
5912 }
5913
5914 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5915 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5916 {
5917 if (fmt[i] == 'e')
5918 {
5919 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5920 }
5921 else if (fmt[i] == 'E')
5922 {
5923 for (j = 0; j < XVECLEN (*x, i); j++)
5924 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5925 }
5926 }
5927 }
5928
5929 /* Check whether X contains an UNSPEC_LTREL_BASE.
5930 Return its constant pool symbol if found, NULL_RTX otherwise. */
5931
5932 static rtx
5933 find_ltrel_base (rtx x)
5934 {
5935 int i, j;
5936 const char *fmt;
5937
5938 if (GET_CODE (x) == UNSPEC
5939 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5940 return XVECEXP (x, 0, 0);
5941
5942 fmt = GET_RTX_FORMAT (GET_CODE (x));
5943 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5944 {
5945 if (fmt[i] == 'e')
5946 {
5947 rtx fnd = find_ltrel_base (XEXP (x, i));
5948 if (fnd)
5949 return fnd;
5950 }
5951 else if (fmt[i] == 'E')
5952 {
5953 for (j = 0; j < XVECLEN (x, i); j++)
5954 {
5955 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5956 if (fnd)
5957 return fnd;
5958 }
5959 }
5960 }
5961
5962 return NULL_RTX;
5963 }
5964
5965 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5966
5967 static void
5968 replace_ltrel_base (rtx *x)
5969 {
5970 int i, j;
5971 const char *fmt;
5972
5973 if (GET_CODE (*x) == UNSPEC
5974 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5975 {
5976 *x = XVECEXP (*x, 0, 1);
5977 return;
5978 }
5979
5980 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5981 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5982 {
5983 if (fmt[i] == 'e')
5984 {
5985 replace_ltrel_base (&XEXP (*x, i));
5986 }
5987 else if (fmt[i] == 'E')
5988 {
5989 for (j = 0; j < XVECLEN (*x, i); j++)
5990 replace_ltrel_base (&XVECEXP (*x, i, j));
5991 }
5992 }
5993 }
5994
5995
5996 /* We keep a list of constants which we have to add to internal
5997 constant tables in the middle of large functions. */
5998
5999 #define NR_C_MODES 11
6000 enum machine_mode constant_modes[NR_C_MODES] =
6001 {
6002 TFmode, TImode, TDmode,
6003 DFmode, DImode, DDmode,
6004 SFmode, SImode, SDmode,
6005 HImode,
6006 QImode
6007 };
6008
6009 struct constant
6010 {
6011 struct constant *next;
6012 rtx value;
6013 rtx label;
6014 };
6015
6016 struct constant_pool
6017 {
6018 struct constant_pool *next;
6019 rtx first_insn;
6020 rtx pool_insn;
6021 bitmap insns;
6022 rtx emit_pool_after;
6023
6024 struct constant *constants[NR_C_MODES];
6025 struct constant *execute;
6026 rtx label;
6027 int size;
6028 };
6029
6030 /* Allocate new constant_pool structure. */
6031
6032 static struct constant_pool *
6033 s390_alloc_pool (void)
6034 {
6035 struct constant_pool *pool;
6036 int i;
6037
6038 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6039 pool->next = NULL;
6040 for (i = 0; i < NR_C_MODES; i++)
6041 pool->constants[i] = NULL;
6042
6043 pool->execute = NULL;
6044 pool->label = gen_label_rtx ();
6045 pool->first_insn = NULL_RTX;
6046 pool->pool_insn = NULL_RTX;
6047 pool->insns = BITMAP_ALLOC (NULL);
6048 pool->size = 0;
6049 pool->emit_pool_after = NULL_RTX;
6050
6051 return pool;
6052 }
6053
6054 /* Create new constant pool covering instructions starting at INSN
6055 and chain it to the end of POOL_LIST. */
6056
6057 static struct constant_pool *
6058 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6059 {
6060 struct constant_pool *pool, **prev;
6061
6062 pool = s390_alloc_pool ();
6063 pool->first_insn = insn;
6064
6065 for (prev = pool_list; *prev; prev = &(*prev)->next)
6066 ;
6067 *prev = pool;
6068
6069 return pool;
6070 }
6071
6072 /* End range of instructions covered by POOL at INSN and emit
6073 placeholder insn representing the pool. */
6074
6075 static void
6076 s390_end_pool (struct constant_pool *pool, rtx insn)
6077 {
6078 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6079
6080 if (!insn)
6081 insn = get_last_insn ();
6082
6083 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6084 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6085 }
6086
6087 /* Add INSN to the list of insns covered by POOL. */
6088
6089 static void
6090 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6091 {
6092 bitmap_set_bit (pool->insns, INSN_UID (insn));
6093 }
6094
6095 /* Return pool out of POOL_LIST that covers INSN. */
6096
6097 static struct constant_pool *
6098 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6099 {
6100 struct constant_pool *pool;
6101
6102 for (pool = pool_list; pool; pool = pool->next)
6103 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6104 break;
6105
6106 return pool;
6107 }
6108
6109 /* Add constant VAL of mode MODE to the constant pool POOL. */
6110
6111 static void
6112 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6113 {
6114 struct constant *c;
6115 int i;
6116
6117 for (i = 0; i < NR_C_MODES; i++)
6118 if (constant_modes[i] == mode)
6119 break;
6120 gcc_assert (i != NR_C_MODES);
6121
6122 for (c = pool->constants[i]; c != NULL; c = c->next)
6123 if (rtx_equal_p (val, c->value))
6124 break;
6125
6126 if (c == NULL)
6127 {
6128 c = (struct constant *) xmalloc (sizeof *c);
6129 c->value = val;
6130 c->label = gen_label_rtx ();
6131 c->next = pool->constants[i];
6132 pool->constants[i] = c;
6133 pool->size += GET_MODE_SIZE (mode);
6134 }
6135 }
6136
6137 /* Return an rtx that represents the offset of X from the start of
6138 pool POOL. */
6139
6140 static rtx
6141 s390_pool_offset (struct constant_pool *pool, rtx x)
6142 {
6143 rtx label;
6144
6145 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6146 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6147 UNSPEC_POOL_OFFSET);
6148 return gen_rtx_CONST (GET_MODE (x), x);
6149 }
6150
6151 /* Find constant VAL of mode MODE in the constant pool POOL.
6152 Return an RTX describing the distance from the start of
6153 the pool to the location of the new constant. */
6154
6155 static rtx
6156 s390_find_constant (struct constant_pool *pool, rtx val,
6157 enum machine_mode mode)
6158 {
6159 struct constant *c;
6160 int i;
6161
6162 for (i = 0; i < NR_C_MODES; i++)
6163 if (constant_modes[i] == mode)
6164 break;
6165 gcc_assert (i != NR_C_MODES);
6166
6167 for (c = pool->constants[i]; c != NULL; c = c->next)
6168 if (rtx_equal_p (val, c->value))
6169 break;
6170
6171 gcc_assert (c);
6172
6173 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6174 }
6175
6176 /* Check whether INSN is an execute. Return the label_ref to its
6177 execute target template if so, NULL_RTX otherwise. */
6178
6179 static rtx
6180 s390_execute_label (rtx insn)
6181 {
6182 if (GET_CODE (insn) == INSN
6183 && GET_CODE (PATTERN (insn)) == PARALLEL
6184 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6185 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6186 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6187
6188 return NULL_RTX;
6189 }
6190
6191 /* Add execute target for INSN to the constant pool POOL. */
6192
6193 static void
6194 s390_add_execute (struct constant_pool *pool, rtx insn)
6195 {
6196 struct constant *c;
6197
6198 for (c = pool->execute; c != NULL; c = c->next)
6199 if (INSN_UID (insn) == INSN_UID (c->value))
6200 break;
6201
6202 if (c == NULL)
6203 {
6204 c = (struct constant *) xmalloc (sizeof *c);
6205 c->value = insn;
6206 c->label = gen_label_rtx ();
6207 c->next = pool->execute;
6208 pool->execute = c;
6209 pool->size += 6;
6210 }
6211 }
6212
6213 /* Find execute target for INSN in the constant pool POOL.
6214 Return an RTX describing the distance from the start of
6215 the pool to the location of the execute target. */
6216
6217 static rtx
6218 s390_find_execute (struct constant_pool *pool, rtx insn)
6219 {
6220 struct constant *c;
6221
6222 for (c = pool->execute; c != NULL; c = c->next)
6223 if (INSN_UID (insn) == INSN_UID (c->value))
6224 break;
6225
6226 gcc_assert (c);
6227
6228 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6229 }
6230
6231 /* For an execute INSN, extract the execute target template. */
6232
6233 static rtx
6234 s390_execute_target (rtx insn)
6235 {
6236 rtx pattern = PATTERN (insn);
6237 gcc_assert (s390_execute_label (insn));
6238
6239 if (XVECLEN (pattern, 0) == 2)
6240 {
6241 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6242 }
6243 else
6244 {
6245 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6246 int i;
6247
6248 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6249 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6250
6251 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6252 }
6253
6254 return pattern;
6255 }
6256
6257 /* Indicate that INSN cannot be duplicated. This is the case for
6258 execute insns that carry a unique label. */
6259
6260 static bool
6261 s390_cannot_copy_insn_p (rtx insn)
6262 {
6263 rtx label = s390_execute_label (insn);
6264 return label && label != const0_rtx;
6265 }
6266
6267 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6268 do not emit the pool base label. */
6269
6270 static void
6271 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6272 {
6273 struct constant *c;
6274 rtx insn = pool->pool_insn;
6275 int i;
6276
6277 /* Switch to rodata section. */
6278 if (TARGET_CPU_ZARCH)
6279 {
6280 insn = emit_insn_after (gen_pool_section_start (), insn);
6281 INSN_ADDRESSES_NEW (insn, -1);
6282 }
6283
6284 /* Ensure minimum pool alignment. */
6285 if (TARGET_CPU_ZARCH)
6286 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6287 else
6288 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6289 INSN_ADDRESSES_NEW (insn, -1);
6290
6291 /* Emit pool base label. */
6292 if (!remote_label)
6293 {
6294 insn = emit_label_after (pool->label, insn);
6295 INSN_ADDRESSES_NEW (insn, -1);
6296 }
6297
6298 /* Dump constants in descending alignment requirement order,
6299 ensuring proper alignment for every constant. */
6300 for (i = 0; i < NR_C_MODES; i++)
6301 for (c = pool->constants[i]; c; c = c->next)
6302 {
6303 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6304 rtx value = copy_rtx (c->value);
6305 if (GET_CODE (value) == CONST
6306 && GET_CODE (XEXP (value, 0)) == UNSPEC
6307 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6308 && XVECLEN (XEXP (value, 0), 0) == 1)
6309 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6310
6311 insn = emit_label_after (c->label, insn);
6312 INSN_ADDRESSES_NEW (insn, -1);
6313
6314 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6315 gen_rtvec (1, value),
6316 UNSPECV_POOL_ENTRY);
6317 insn = emit_insn_after (value, insn);
6318 INSN_ADDRESSES_NEW (insn, -1);
6319 }
6320
6321 /* Ensure minimum alignment for instructions. */
6322 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6323 INSN_ADDRESSES_NEW (insn, -1);
6324
6325 /* Output in-pool execute template insns. */
6326 for (c = pool->execute; c; c = c->next)
6327 {
6328 insn = emit_label_after (c->label, insn);
6329 INSN_ADDRESSES_NEW (insn, -1);
6330
6331 insn = emit_insn_after (s390_execute_target (c->value), insn);
6332 INSN_ADDRESSES_NEW (insn, -1);
6333 }
6334
6335 /* Switch back to previous section. */
6336 if (TARGET_CPU_ZARCH)
6337 {
6338 insn = emit_insn_after (gen_pool_section_end (), insn);
6339 INSN_ADDRESSES_NEW (insn, -1);
6340 }
6341
6342 insn = emit_barrier_after (insn);
6343 INSN_ADDRESSES_NEW (insn, -1);
6344
6345 /* Remove placeholder insn. */
6346 remove_insn (pool->pool_insn);
6347 }
6348
6349 /* Free all memory used by POOL. */
6350
6351 static void
6352 s390_free_pool (struct constant_pool *pool)
6353 {
6354 struct constant *c, *next;
6355 int i;
6356
6357 for (i = 0; i < NR_C_MODES; i++)
6358 for (c = pool->constants[i]; c; c = next)
6359 {
6360 next = c->next;
6361 free (c);
6362 }
6363
6364 for (c = pool->execute; c; c = next)
6365 {
6366 next = c->next;
6367 free (c);
6368 }
6369
6370 BITMAP_FREE (pool->insns);
6371 free (pool);
6372 }
6373
6374
6375 /* Collect main literal pool. Return NULL on overflow. */
6376
6377 static struct constant_pool *
6378 s390_mainpool_start (void)
6379 {
6380 struct constant_pool *pool;
6381 rtx insn;
6382
6383 pool = s390_alloc_pool ();
6384
6385 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6386 {
6387 if (GET_CODE (insn) == INSN
6388 && GET_CODE (PATTERN (insn)) == SET
6389 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6390 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6391 {
6392 gcc_assert (!pool->pool_insn);
6393 pool->pool_insn = insn;
6394 }
6395
6396 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6397 {
6398 s390_add_execute (pool, insn);
6399 }
6400 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6401 {
6402 rtx pool_ref = NULL_RTX;
6403 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6404 if (pool_ref)
6405 {
6406 rtx constant = get_pool_constant (pool_ref);
6407 enum machine_mode mode = get_pool_mode (pool_ref);
6408 s390_add_constant (pool, constant, mode);
6409 }
6410 }
6411
6412 /* If hot/cold partitioning is enabled we have to make sure that
6413 the literal pool is emitted in the same section where the
6414 initialization of the literal pool base pointer takes place.
6415 emit_pool_after is only used in the non-overflow case on non
6416 Z cpus where we can emit the literal pool at the end of the
6417 function body within the text section. */
6418 if (NOTE_P (insn)
6419 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6420 && !pool->emit_pool_after)
6421 pool->emit_pool_after = PREV_INSN (insn);
6422 }
6423
6424 gcc_assert (pool->pool_insn || pool->size == 0);
6425
6426 if (pool->size >= 4096)
6427 {
6428 /* We're going to chunkify the pool, so remove the main
6429 pool placeholder insn. */
6430 remove_insn (pool->pool_insn);
6431
6432 s390_free_pool (pool);
6433 pool = NULL;
6434 }
6435
6436 /* If the functions ends with the section where the literal pool
6437 should be emitted set the marker to its end. */
6438 if (pool && !pool->emit_pool_after)
6439 pool->emit_pool_after = get_last_insn ();
6440
6441 return pool;
6442 }
6443
6444 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6445 Modify the current function to output the pool constants as well as
6446 the pool register setup instruction. */
6447
6448 static void
6449 s390_mainpool_finish (struct constant_pool *pool)
6450 {
6451 rtx base_reg = cfun->machine->base_reg;
6452 rtx insn;
6453
6454 /* If the pool is empty, we're done. */
6455 if (pool->size == 0)
6456 {
6457 /* We don't actually need a base register after all. */
6458 cfun->machine->base_reg = NULL_RTX;
6459
6460 if (pool->pool_insn)
6461 remove_insn (pool->pool_insn);
6462 s390_free_pool (pool);
6463 return;
6464 }
6465
6466 /* We need correct insn addresses. */
6467 shorten_branches (get_insns ());
6468
6469 /* On zSeries, we use a LARL to load the pool register. The pool is
6470 located in the .rodata section, so we emit it after the function. */
6471 if (TARGET_CPU_ZARCH)
6472 {
6473 insn = gen_main_base_64 (base_reg, pool->label);
6474 insn = emit_insn_after (insn, pool->pool_insn);
6475 INSN_ADDRESSES_NEW (insn, -1);
6476 remove_insn (pool->pool_insn);
6477
6478 insn = get_last_insn ();
6479 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6480 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6481
6482 s390_dump_pool (pool, 0);
6483 }
6484
6485 /* On S/390, if the total size of the function's code plus literal pool
6486 does not exceed 4096 bytes, we use BASR to set up a function base
6487 pointer, and emit the literal pool at the end of the function. */
6488 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6489 + pool->size + 8 /* alignment slop */ < 4096)
6490 {
6491 insn = gen_main_base_31_small (base_reg, pool->label);
6492 insn = emit_insn_after (insn, pool->pool_insn);
6493 INSN_ADDRESSES_NEW (insn, -1);
6494 remove_insn (pool->pool_insn);
6495
6496 insn = emit_label_after (pool->label, insn);
6497 INSN_ADDRESSES_NEW (insn, -1);
6498
6499 /* emit_pool_after will be set by s390_mainpool_start to the
6500 last insn of the section where the literal pool should be
6501 emitted. */
6502 insn = pool->emit_pool_after;
6503
6504 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6505 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6506
6507 s390_dump_pool (pool, 1);
6508 }
6509
6510 /* Otherwise, we emit an inline literal pool and use BASR to branch
6511 over it, setting up the pool register at the same time. */
6512 else
6513 {
6514 rtx pool_end = gen_label_rtx ();
6515
6516 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6517 insn = emit_jump_insn_after (insn, pool->pool_insn);
6518 JUMP_LABEL (insn) = pool_end;
6519 INSN_ADDRESSES_NEW (insn, -1);
6520 remove_insn (pool->pool_insn);
6521
6522 insn = emit_label_after (pool->label, insn);
6523 INSN_ADDRESSES_NEW (insn, -1);
6524
6525 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6526 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6527
6528 insn = emit_label_after (pool_end, pool->pool_insn);
6529 INSN_ADDRESSES_NEW (insn, -1);
6530
6531 s390_dump_pool (pool, 1);
6532 }
6533
6534
6535 /* Replace all literal pool references. */
6536
6537 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6538 {
6539 if (INSN_P (insn))
6540 replace_ltrel_base (&PATTERN (insn));
6541
6542 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6543 {
6544 rtx addr, pool_ref = NULL_RTX;
6545 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6546 if (pool_ref)
6547 {
6548 if (s390_execute_label (insn))
6549 addr = s390_find_execute (pool, insn);
6550 else
6551 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6552 get_pool_mode (pool_ref));
6553
6554 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6555 INSN_CODE (insn) = -1;
6556 }
6557 }
6558 }
6559
6560
6561 /* Free the pool. */
6562 s390_free_pool (pool);
6563 }
6564
6565 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6566 We have decided we cannot use this pool, so revert all changes
6567 to the current function that were done by s390_mainpool_start. */
6568 static void
6569 s390_mainpool_cancel (struct constant_pool *pool)
6570 {
6571 /* We didn't actually change the instruction stream, so simply
6572 free the pool memory. */
6573 s390_free_pool (pool);
6574 }
6575
6576
6577 /* Chunkify the literal pool. */
6578
6579 #define S390_POOL_CHUNK_MIN 0xc00
6580 #define S390_POOL_CHUNK_MAX 0xe00
6581
6582 static struct constant_pool *
6583 s390_chunkify_start (void)
6584 {
6585 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6586 int extra_size = 0;
6587 bitmap far_labels;
6588 rtx pending_ltrel = NULL_RTX;
6589 rtx insn;
6590
6591 rtx (*gen_reload_base) (rtx, rtx) =
6592 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6593
6594
6595 /* We need correct insn addresses. */
6596
6597 shorten_branches (get_insns ());
6598
6599 /* Scan all insns and move literals to pool chunks. */
6600
6601 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6602 {
6603 bool section_switch_p = false;
6604
6605 /* Check for pending LTREL_BASE. */
6606 if (INSN_P (insn))
6607 {
6608 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6609 if (ltrel_base)
6610 {
6611 gcc_assert (ltrel_base == pending_ltrel);
6612 pending_ltrel = NULL_RTX;
6613 }
6614 }
6615
6616 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6617 {
6618 if (!curr_pool)
6619 curr_pool = s390_start_pool (&pool_list, insn);
6620
6621 s390_add_execute (curr_pool, insn);
6622 s390_add_pool_insn (curr_pool, insn);
6623 }
6624 else if (GET_CODE (insn) == INSN || CALL_P (insn))
6625 {
6626 rtx pool_ref = NULL_RTX;
6627 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6628 if (pool_ref)
6629 {
6630 rtx constant = get_pool_constant (pool_ref);
6631 enum machine_mode mode = get_pool_mode (pool_ref);
6632
6633 if (!curr_pool)
6634 curr_pool = s390_start_pool (&pool_list, insn);
6635
6636 s390_add_constant (curr_pool, constant, mode);
6637 s390_add_pool_insn (curr_pool, insn);
6638
6639 /* Don't split the pool chunk between a LTREL_OFFSET load
6640 and the corresponding LTREL_BASE. */
6641 if (GET_CODE (constant) == CONST
6642 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6643 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6644 {
6645 gcc_assert (!pending_ltrel);
6646 pending_ltrel = pool_ref;
6647 }
6648 }
6649 }
6650
6651 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6652 {
6653 if (curr_pool)
6654 s390_add_pool_insn (curr_pool, insn);
6655 /* An LTREL_BASE must follow within the same basic block. */
6656 gcc_assert (!pending_ltrel);
6657 }
6658
6659 if (NOTE_P (insn))
6660 switch (NOTE_KIND (insn))
6661 {
6662 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6663 section_switch_p = true;
6664 break;
6665 case NOTE_INSN_VAR_LOCATION:
6666 case NOTE_INSN_CALL_ARG_LOCATION:
6667 continue;
6668 default:
6669 break;
6670 }
6671
6672 if (!curr_pool
6673 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6674 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6675 continue;
6676
6677 if (TARGET_CPU_ZARCH)
6678 {
6679 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6680 continue;
6681
6682 s390_end_pool (curr_pool, NULL_RTX);
6683 curr_pool = NULL;
6684 }
6685 else
6686 {
6687 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6688 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6689 + extra_size;
6690
6691 /* We will later have to insert base register reload insns.
6692 Those will have an effect on code size, which we need to
6693 consider here. This calculation makes rather pessimistic
6694 worst-case assumptions. */
6695 if (GET_CODE (insn) == CODE_LABEL)
6696 extra_size += 6;
6697
6698 if (chunk_size < S390_POOL_CHUNK_MIN
6699 && curr_pool->size < S390_POOL_CHUNK_MIN
6700 && !section_switch_p)
6701 continue;
6702
6703 /* Pool chunks can only be inserted after BARRIERs ... */
6704 if (GET_CODE (insn) == BARRIER)
6705 {
6706 s390_end_pool (curr_pool, insn);
6707 curr_pool = NULL;
6708 extra_size = 0;
6709 }
6710
6711 /* ... so if we don't find one in time, create one. */
6712 else if (chunk_size > S390_POOL_CHUNK_MAX
6713 || curr_pool->size > S390_POOL_CHUNK_MAX
6714 || section_switch_p)
6715 {
6716 rtx label, jump, barrier, next, prev;
6717
6718 if (!section_switch_p)
6719 {
6720 /* We can insert the barrier only after a 'real' insn. */
6721 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6722 continue;
6723 if (get_attr_length (insn) == 0)
6724 continue;
6725 /* Don't separate LTREL_BASE from the corresponding
6726 LTREL_OFFSET load. */
6727 if (pending_ltrel)
6728 continue;
6729 next = insn;
6730 do
6731 {
6732 insn = next;
6733 next = NEXT_INSN (insn);
6734 }
6735 while (next
6736 && NOTE_P (next)
6737 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6738 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6739 }
6740 else
6741 {
6742 gcc_assert (!pending_ltrel);
6743
6744 /* The old pool has to end before the section switch
6745 note in order to make it part of the current
6746 section. */
6747 insn = PREV_INSN (insn);
6748 }
6749
6750 label = gen_label_rtx ();
6751 prev = insn;
6752 if (prev && NOTE_P (prev))
6753 prev = prev_nonnote_insn (prev);
6754 if (prev)
6755 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
6756 INSN_LOCATOR (prev));
6757 else
6758 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
6759 barrier = emit_barrier_after (jump);
6760 insn = emit_label_after (label, barrier);
6761 JUMP_LABEL (jump) = label;
6762 LABEL_NUSES (label) = 1;
6763
6764 INSN_ADDRESSES_NEW (jump, -1);
6765 INSN_ADDRESSES_NEW (barrier, -1);
6766 INSN_ADDRESSES_NEW (insn, -1);
6767
6768 s390_end_pool (curr_pool, barrier);
6769 curr_pool = NULL;
6770 extra_size = 0;
6771 }
6772 }
6773 }
6774
6775 if (curr_pool)
6776 s390_end_pool (curr_pool, NULL_RTX);
6777 gcc_assert (!pending_ltrel);
6778
6779 /* Find all labels that are branched into
6780 from an insn belonging to a different chunk. */
6781
6782 far_labels = BITMAP_ALLOC (NULL);
6783
6784 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6785 {
6786 /* Labels marked with LABEL_PRESERVE_P can be target
6787 of non-local jumps, so we have to mark them.
6788 The same holds for named labels.
6789
6790 Don't do that, however, if it is the label before
6791 a jump table. */
6792
6793 if (GET_CODE (insn) == CODE_LABEL
6794 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6795 {
6796 rtx vec_insn = next_real_insn (insn);
6797 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6798 PATTERN (vec_insn) : NULL_RTX;
6799 if (!vec_pat
6800 || !(GET_CODE (vec_pat) == ADDR_VEC
6801 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6802 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6803 }
6804
6805 /* If we have a direct jump (conditional or unconditional)
6806 or a casesi jump, check all potential targets. */
6807 else if (GET_CODE (insn) == JUMP_INSN)
6808 {
6809 rtx pat = PATTERN (insn);
6810 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6811 pat = XVECEXP (pat, 0, 0);
6812
6813 if (GET_CODE (pat) == SET)
6814 {
6815 rtx label = JUMP_LABEL (insn);
6816 if (label)
6817 {
6818 if (s390_find_pool (pool_list, label)
6819 != s390_find_pool (pool_list, insn))
6820 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6821 }
6822 }
6823 else if (GET_CODE (pat) == PARALLEL
6824 && XVECLEN (pat, 0) == 2
6825 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6826 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6827 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6828 {
6829 /* Find the jump table used by this casesi jump. */
6830 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6831 rtx vec_insn = next_real_insn (vec_label);
6832 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6833 PATTERN (vec_insn) : NULL_RTX;
6834 if (vec_pat
6835 && (GET_CODE (vec_pat) == ADDR_VEC
6836 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6837 {
6838 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6839
6840 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6841 {
6842 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6843
6844 if (s390_find_pool (pool_list, label)
6845 != s390_find_pool (pool_list, insn))
6846 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6847 }
6848 }
6849 }
6850 }
6851 }
6852
6853 /* Insert base register reload insns before every pool. */
6854
6855 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6856 {
6857 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6858 curr_pool->label);
6859 rtx insn = curr_pool->first_insn;
6860 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6861 }
6862
6863 /* Insert base register reload insns at every far label. */
6864
6865 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6866 if (GET_CODE (insn) == CODE_LABEL
6867 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6868 {
6869 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6870 if (pool)
6871 {
6872 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6873 pool->label);
6874 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6875 }
6876 }
6877
6878
6879 BITMAP_FREE (far_labels);
6880
6881
6882 /* Recompute insn addresses. */
6883
6884 init_insn_lengths ();
6885 shorten_branches (get_insns ());
6886
6887 return pool_list;
6888 }
6889
6890 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6891 After we have decided to use this list, finish implementing
6892 all changes to the current function as required. */
6893
6894 static void
6895 s390_chunkify_finish (struct constant_pool *pool_list)
6896 {
6897 struct constant_pool *curr_pool = NULL;
6898 rtx insn;
6899
6900
6901 /* Replace all literal pool references. */
6902
6903 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6904 {
6905 if (INSN_P (insn))
6906 replace_ltrel_base (&PATTERN (insn));
6907
6908 curr_pool = s390_find_pool (pool_list, insn);
6909 if (!curr_pool)
6910 continue;
6911
6912 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6913 {
6914 rtx addr, pool_ref = NULL_RTX;
6915 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6916 if (pool_ref)
6917 {
6918 if (s390_execute_label (insn))
6919 addr = s390_find_execute (curr_pool, insn);
6920 else
6921 addr = s390_find_constant (curr_pool,
6922 get_pool_constant (pool_ref),
6923 get_pool_mode (pool_ref));
6924
6925 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6926 INSN_CODE (insn) = -1;
6927 }
6928 }
6929 }
6930
6931 /* Dump out all literal pools. */
6932
6933 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6934 s390_dump_pool (curr_pool, 0);
6935
6936 /* Free pool list. */
6937
6938 while (pool_list)
6939 {
6940 struct constant_pool *next = pool_list->next;
6941 s390_free_pool (pool_list);
6942 pool_list = next;
6943 }
6944 }
6945
6946 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6947 We have decided we cannot use this list, so revert all changes
6948 to the current function that were done by s390_chunkify_start. */
6949
6950 static void
6951 s390_chunkify_cancel (struct constant_pool *pool_list)
6952 {
6953 struct constant_pool *curr_pool = NULL;
6954 rtx insn;
6955
6956 /* Remove all pool placeholder insns. */
6957
6958 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6959 {
6960 /* Did we insert an extra barrier? Remove it. */
6961 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6962 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6963 rtx label = NEXT_INSN (curr_pool->pool_insn);
6964
6965 if (jump && GET_CODE (jump) == JUMP_INSN
6966 && barrier && GET_CODE (barrier) == BARRIER
6967 && label && GET_CODE (label) == CODE_LABEL
6968 && GET_CODE (PATTERN (jump)) == SET
6969 && SET_DEST (PATTERN (jump)) == pc_rtx
6970 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6971 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6972 {
6973 remove_insn (jump);
6974 remove_insn (barrier);
6975 remove_insn (label);
6976 }
6977
6978 remove_insn (curr_pool->pool_insn);
6979 }
6980
6981 /* Remove all base register reload insns. */
6982
6983 for (insn = get_insns (); insn; )
6984 {
6985 rtx next_insn = NEXT_INSN (insn);
6986
6987 if (GET_CODE (insn) == INSN
6988 && GET_CODE (PATTERN (insn)) == SET
6989 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6990 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6991 remove_insn (insn);
6992
6993 insn = next_insn;
6994 }
6995
6996 /* Free pool list. */
6997
6998 while (pool_list)
6999 {
7000 struct constant_pool *next = pool_list->next;
7001 s390_free_pool (pool_list);
7002 pool_list = next;
7003 }
7004 }
7005
7006 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7007
7008 void
7009 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
7010 {
7011 REAL_VALUE_TYPE r;
7012
7013 switch (GET_MODE_CLASS (mode))
7014 {
7015 case MODE_FLOAT:
7016 case MODE_DECIMAL_FLOAT:
7017 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7018
7019 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7020 assemble_real (r, mode, align);
7021 break;
7022
7023 case MODE_INT:
7024 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7025 mark_symbol_refs_as_used (exp);
7026 break;
7027
7028 default:
7029 gcc_unreachable ();
7030 }
7031 }
7032
7033
7034 /* Return an RTL expression representing the value of the return address
7035 for the frame COUNT steps up from the current frame. FRAME is the
7036 frame pointer of that frame. */
7037
7038 rtx
7039 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7040 {
7041 int offset;
7042 rtx addr;
7043
7044 /* Without backchain, we fail for all but the current frame. */
7045
7046 if (!TARGET_BACKCHAIN && count > 0)
7047 return NULL_RTX;
7048
7049 /* For the current frame, we need to make sure the initial
7050 value of RETURN_REGNUM is actually saved. */
7051
7052 if (count == 0)
7053 {
7054 /* On non-z architectures branch splitting could overwrite r14. */
7055 if (TARGET_CPU_ZARCH)
7056 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7057 else
7058 {
7059 cfun_frame_layout.save_return_addr_p = true;
7060 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7061 }
7062 }
7063
7064 if (TARGET_PACKED_STACK)
7065 offset = -2 * UNITS_PER_LONG;
7066 else
7067 offset = RETURN_REGNUM * UNITS_PER_LONG;
7068
7069 addr = plus_constant (Pmode, frame, offset);
7070 addr = memory_address (Pmode, addr);
7071 return gen_rtx_MEM (Pmode, addr);
7072 }
7073
7074 /* Return an RTL expression representing the back chain stored in
7075 the current stack frame. */
7076
7077 rtx
7078 s390_back_chain_rtx (void)
7079 {
7080 rtx chain;
7081
7082 gcc_assert (TARGET_BACKCHAIN);
7083
7084 if (TARGET_PACKED_STACK)
7085 chain = plus_constant (Pmode, stack_pointer_rtx,
7086 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7087 else
7088 chain = stack_pointer_rtx;
7089
7090 chain = gen_rtx_MEM (Pmode, chain);
7091 return chain;
7092 }
7093
7094 /* Find first call clobbered register unused in a function.
7095 This could be used as base register in a leaf function
7096 or for holding the return address before epilogue. */
7097
7098 static int
7099 find_unused_clobbered_reg (void)
7100 {
7101 int i;
7102 for (i = 0; i < 6; i++)
7103 if (!df_regs_ever_live_p (i))
7104 return i;
7105 return 0;
7106 }
7107
7108
7109 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7110 clobbered hard regs in SETREG. */
7111
7112 static void
7113 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7114 {
7115 int *regs_ever_clobbered = (int *)data;
7116 unsigned int i, regno;
7117 enum machine_mode mode = GET_MODE (setreg);
7118
7119 if (GET_CODE (setreg) == SUBREG)
7120 {
7121 rtx inner = SUBREG_REG (setreg);
7122 if (!GENERAL_REG_P (inner))
7123 return;
7124 regno = subreg_regno (setreg);
7125 }
7126 else if (GENERAL_REG_P (setreg))
7127 regno = REGNO (setreg);
7128 else
7129 return;
7130
7131 for (i = regno;
7132 i < regno + HARD_REGNO_NREGS (regno, mode);
7133 i++)
7134 regs_ever_clobbered[i] = 1;
7135 }
7136
7137 /* Walks through all basic blocks of the current function looking
7138 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7139 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7140 each of those regs. */
7141
7142 static void
7143 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7144 {
7145 basic_block cur_bb;
7146 rtx cur_insn;
7147 unsigned int i;
7148
7149 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7150
7151 /* For non-leaf functions we have to consider all call clobbered regs to be
7152 clobbered. */
7153 if (!crtl->is_leaf)
7154 {
7155 for (i = 0; i < 16; i++)
7156 regs_ever_clobbered[i] = call_really_used_regs[i];
7157 }
7158
7159 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7160 this work is done by liveness analysis (mark_regs_live_at_end).
7161 Special care is needed for functions containing landing pads. Landing pads
7162 may use the eh registers, but the code which sets these registers is not
7163 contained in that function. Hence s390_regs_ever_clobbered is not able to
7164 deal with this automatically. */
7165 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7166 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7167 if (crtl->calls_eh_return
7168 || (cfun->machine->has_landing_pad_p
7169 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7170 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7171
7172 /* For nonlocal gotos all call-saved registers have to be saved.
7173 This flag is also set for the unwinding code in libgcc.
7174 See expand_builtin_unwind_init. For regs_ever_live this is done by
7175 reload. */
7176 if (cfun->has_nonlocal_label)
7177 for (i = 0; i < 16; i++)
7178 if (!call_really_used_regs[i])
7179 regs_ever_clobbered[i] = 1;
7180
7181 FOR_EACH_BB (cur_bb)
7182 {
7183 FOR_BB_INSNS (cur_bb, cur_insn)
7184 {
7185 if (INSN_P (cur_insn))
7186 note_stores (PATTERN (cur_insn),
7187 s390_reg_clobbered_rtx,
7188 regs_ever_clobbered);
7189 }
7190 }
7191 }
7192
7193 /* Determine the frame area which actually has to be accessed
7194 in the function epilogue. The values are stored at the
7195 given pointers AREA_BOTTOM (address of the lowest used stack
7196 address) and AREA_TOP (address of the first item which does
7197 not belong to the stack frame). */
7198
7199 static void
7200 s390_frame_area (int *area_bottom, int *area_top)
7201 {
7202 int b, t;
7203 int i;
7204
7205 b = INT_MAX;
7206 t = INT_MIN;
7207
7208 if (cfun_frame_layout.first_restore_gpr != -1)
7209 {
7210 b = (cfun_frame_layout.gprs_offset
7211 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7212 t = b + (cfun_frame_layout.last_restore_gpr
7213 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7214 }
7215
7216 if (TARGET_64BIT && cfun_save_high_fprs_p)
7217 {
7218 b = MIN (b, cfun_frame_layout.f8_offset);
7219 t = MAX (t, (cfun_frame_layout.f8_offset
7220 + cfun_frame_layout.high_fprs * 8));
7221 }
7222
7223 if (!TARGET_64BIT)
7224 for (i = 2; i < 4; i++)
7225 if (cfun_fpr_bit_p (i))
7226 {
7227 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7228 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7229 }
7230
7231 *area_bottom = b;
7232 *area_top = t;
7233 }
7234
7235 /* Fill cfun->machine with info about register usage of current function.
7236 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7237
7238 static void
7239 s390_register_info (int clobbered_regs[])
7240 {
7241 int i, j;
7242
7243 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7244 cfun_frame_layout.fpr_bitmap = 0;
7245 cfun_frame_layout.high_fprs = 0;
7246 if (TARGET_64BIT)
7247 for (i = 24; i < 32; i++)
7248 if (df_regs_ever_live_p (i) && !global_regs[i])
7249 {
7250 cfun_set_fpr_bit (i - 16);
7251 cfun_frame_layout.high_fprs++;
7252 }
7253
7254 /* Find first and last gpr to be saved. We trust regs_ever_live
7255 data, except that we don't save and restore global registers.
7256
7257 Also, all registers with special meaning to the compiler need
7258 to be handled extra. */
7259
7260 s390_regs_ever_clobbered (clobbered_regs);
7261
7262 for (i = 0; i < 16; i++)
7263 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7264
7265 if (frame_pointer_needed)
7266 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7267
7268 if (flag_pic)
7269 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7270 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7271
7272 clobbered_regs[BASE_REGNUM]
7273 |= (cfun->machine->base_reg
7274 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7275
7276 clobbered_regs[RETURN_REGNUM]
7277 |= (!crtl->is_leaf
7278 || TARGET_TPF_PROFILING
7279 || cfun->machine->split_branches_pending_p
7280 || cfun_frame_layout.save_return_addr_p
7281 || crtl->calls_eh_return
7282 || cfun->stdarg);
7283
7284 clobbered_regs[STACK_POINTER_REGNUM]
7285 |= (!crtl->is_leaf
7286 || TARGET_TPF_PROFILING
7287 || cfun_save_high_fprs_p
7288 || get_frame_size () > 0
7289 || cfun->calls_alloca
7290 || cfun->stdarg);
7291
7292 for (i = 6; i < 16; i++)
7293 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7294 break;
7295 for (j = 15; j > i; j--)
7296 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7297 break;
7298
7299 if (i == 16)
7300 {
7301 /* Nothing to save/restore. */
7302 cfun_frame_layout.first_save_gpr_slot = -1;
7303 cfun_frame_layout.last_save_gpr_slot = -1;
7304 cfun_frame_layout.first_save_gpr = -1;
7305 cfun_frame_layout.first_restore_gpr = -1;
7306 cfun_frame_layout.last_save_gpr = -1;
7307 cfun_frame_layout.last_restore_gpr = -1;
7308 }
7309 else
7310 {
7311 /* Save slots for gprs from i to j. */
7312 cfun_frame_layout.first_save_gpr_slot = i;
7313 cfun_frame_layout.last_save_gpr_slot = j;
7314
7315 for (i = cfun_frame_layout.first_save_gpr_slot;
7316 i < cfun_frame_layout.last_save_gpr_slot + 1;
7317 i++)
7318 if (clobbered_regs[i])
7319 break;
7320
7321 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7322 if (clobbered_regs[j])
7323 break;
7324
7325 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7326 {
7327 /* Nothing to save/restore. */
7328 cfun_frame_layout.first_save_gpr = -1;
7329 cfun_frame_layout.first_restore_gpr = -1;
7330 cfun_frame_layout.last_save_gpr = -1;
7331 cfun_frame_layout.last_restore_gpr = -1;
7332 }
7333 else
7334 {
7335 /* Save / Restore from gpr i to j. */
7336 cfun_frame_layout.first_save_gpr = i;
7337 cfun_frame_layout.first_restore_gpr = i;
7338 cfun_frame_layout.last_save_gpr = j;
7339 cfun_frame_layout.last_restore_gpr = j;
7340 }
7341 }
7342
7343 if (cfun->stdarg)
7344 {
7345 /* Varargs functions need to save gprs 2 to 6. */
7346 if (cfun->va_list_gpr_size
7347 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7348 {
7349 int min_gpr = crtl->args.info.gprs;
7350 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7351 if (max_gpr > GP_ARG_NUM_REG)
7352 max_gpr = GP_ARG_NUM_REG;
7353
7354 if (cfun_frame_layout.first_save_gpr == -1
7355 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7356 {
7357 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7358 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7359 }
7360
7361 if (cfun_frame_layout.last_save_gpr == -1
7362 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7363 {
7364 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7365 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7366 }
7367 }
7368
7369 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7370 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7371 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7372 {
7373 int min_fpr = crtl->args.info.fprs;
7374 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7375 if (max_fpr > FP_ARG_NUM_REG)
7376 max_fpr = FP_ARG_NUM_REG;
7377
7378 /* ??? This is currently required to ensure proper location
7379 of the fpr save slots within the va_list save area. */
7380 if (TARGET_PACKED_STACK)
7381 min_fpr = 0;
7382
7383 for (i = min_fpr; i < max_fpr; i++)
7384 cfun_set_fpr_bit (i);
7385 }
7386 }
7387
7388 if (!TARGET_64BIT)
7389 for (i = 2; i < 4; i++)
7390 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7391 cfun_set_fpr_bit (i);
7392 }
7393
7394 /* Fill cfun->machine with info about frame of current function. */
7395
7396 static void
7397 s390_frame_info (void)
7398 {
7399 int i;
7400
7401 cfun_frame_layout.frame_size = get_frame_size ();
7402 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7403 fatal_error ("total size of local variables exceeds architecture limit");
7404
7405 if (!TARGET_PACKED_STACK)
7406 {
7407 cfun_frame_layout.backchain_offset = 0;
7408 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7409 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7410 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7411 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7412 * UNITS_PER_LONG);
7413 }
7414 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7415 {
7416 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7417 - UNITS_PER_LONG);
7418 cfun_frame_layout.gprs_offset
7419 = (cfun_frame_layout.backchain_offset
7420 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7421 * UNITS_PER_LONG);
7422
7423 if (TARGET_64BIT)
7424 {
7425 cfun_frame_layout.f4_offset
7426 = (cfun_frame_layout.gprs_offset
7427 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7428
7429 cfun_frame_layout.f0_offset
7430 = (cfun_frame_layout.f4_offset
7431 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7432 }
7433 else
7434 {
7435 /* On 31 bit we have to care about alignment of the
7436 floating point regs to provide fastest access. */
7437 cfun_frame_layout.f0_offset
7438 = ((cfun_frame_layout.gprs_offset
7439 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7440 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7441
7442 cfun_frame_layout.f4_offset
7443 = (cfun_frame_layout.f0_offset
7444 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7445 }
7446 }
7447 else /* no backchain */
7448 {
7449 cfun_frame_layout.f4_offset
7450 = (STACK_POINTER_OFFSET
7451 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7452
7453 cfun_frame_layout.f0_offset
7454 = (cfun_frame_layout.f4_offset
7455 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7456
7457 cfun_frame_layout.gprs_offset
7458 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7459 }
7460
7461 if (crtl->is_leaf
7462 && !TARGET_TPF_PROFILING
7463 && cfun_frame_layout.frame_size == 0
7464 && !cfun_save_high_fprs_p
7465 && !cfun->calls_alloca
7466 && !cfun->stdarg)
7467 return;
7468
7469 if (!TARGET_PACKED_STACK)
7470 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7471 + crtl->outgoing_args_size
7472 + cfun_frame_layout.high_fprs * 8);
7473 else
7474 {
7475 if (TARGET_BACKCHAIN)
7476 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7477
7478 /* No alignment trouble here because f8-f15 are only saved under
7479 64 bit. */
7480 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7481 cfun_frame_layout.f4_offset),
7482 cfun_frame_layout.gprs_offset)
7483 - cfun_frame_layout.high_fprs * 8);
7484
7485 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7486
7487 for (i = 0; i < 8; i++)
7488 if (cfun_fpr_bit_p (i))
7489 cfun_frame_layout.frame_size += 8;
7490
7491 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7492
7493 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7494 the frame size to sustain 8 byte alignment of stack frames. */
7495 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7496 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7497 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7498
7499 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7500 }
7501 }
7502
7503 /* Generate frame layout. Fills in register and frame data for the current
7504 function in cfun->machine. This routine can be called multiple times;
7505 it will re-do the complete frame layout every time. */
7506
7507 static void
7508 s390_init_frame_layout (void)
7509 {
7510 HOST_WIDE_INT frame_size;
7511 int base_used;
7512 int clobbered_regs[16];
7513
7514 /* On S/390 machines, we may need to perform branch splitting, which
7515 will require both base and return address register. We have no
7516 choice but to assume we're going to need them until right at the
7517 end of the machine dependent reorg phase. */
7518 if (!TARGET_CPU_ZARCH)
7519 cfun->machine->split_branches_pending_p = true;
7520
7521 do
7522 {
7523 frame_size = cfun_frame_layout.frame_size;
7524
7525 /* Try to predict whether we'll need the base register. */
7526 base_used = cfun->machine->split_branches_pending_p
7527 || crtl->uses_const_pool
7528 || (!DISP_IN_RANGE (frame_size)
7529 && !CONST_OK_FOR_K (frame_size));
7530
7531 /* Decide which register to use as literal pool base. In small
7532 leaf functions, try to use an unused call-clobbered register
7533 as base register to avoid save/restore overhead. */
7534 if (!base_used)
7535 cfun->machine->base_reg = NULL_RTX;
7536 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
7537 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7538 else
7539 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7540
7541 s390_register_info (clobbered_regs);
7542 s390_frame_info ();
7543 }
7544 while (frame_size != cfun_frame_layout.frame_size);
7545 }
7546
7547 /* Update frame layout. Recompute actual register save data based on
7548 current info and update regs_ever_live for the special registers.
7549 May be called multiple times, but may never cause *more* registers
7550 to be saved than s390_init_frame_layout allocated room for. */
7551
7552 static void
7553 s390_update_frame_layout (void)
7554 {
7555 int clobbered_regs[16];
7556
7557 s390_register_info (clobbered_regs);
7558
7559 df_set_regs_ever_live (BASE_REGNUM,
7560 clobbered_regs[BASE_REGNUM] ? true : false);
7561 df_set_regs_ever_live (RETURN_REGNUM,
7562 clobbered_regs[RETURN_REGNUM] ? true : false);
7563 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7564 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7565
7566 if (cfun->machine->base_reg)
7567 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7568 }
7569
7570 /* Return true if it is legal to put a value with MODE into REGNO. */
7571
7572 bool
7573 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7574 {
7575 switch (REGNO_REG_CLASS (regno))
7576 {
7577 case FP_REGS:
7578 if (REGNO_PAIR_OK (regno, mode))
7579 {
7580 if (mode == SImode || mode == DImode)
7581 return true;
7582
7583 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7584 return true;
7585 }
7586 break;
7587 case ADDR_REGS:
7588 if (FRAME_REGNO_P (regno) && mode == Pmode)
7589 return true;
7590
7591 /* fallthrough */
7592 case GENERAL_REGS:
7593 if (REGNO_PAIR_OK (regno, mode))
7594 {
7595 if (TARGET_ZARCH
7596 || (mode != TFmode && mode != TCmode && mode != TDmode))
7597 return true;
7598 }
7599 break;
7600 case CC_REGS:
7601 if (GET_MODE_CLASS (mode) == MODE_CC)
7602 return true;
7603 break;
7604 case ACCESS_REGS:
7605 if (REGNO_PAIR_OK (regno, mode))
7606 {
7607 if (mode == SImode || mode == Pmode)
7608 return true;
7609 }
7610 break;
7611 default:
7612 return false;
7613 }
7614
7615 return false;
7616 }
7617
7618 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7619
7620 bool
7621 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7622 {
7623 /* Once we've decided upon a register to use as base register, it must
7624 no longer be used for any other purpose. */
7625 if (cfun->machine->base_reg)
7626 if (REGNO (cfun->machine->base_reg) == old_reg
7627 || REGNO (cfun->machine->base_reg) == new_reg)
7628 return false;
7629
7630 return true;
7631 }
7632
7633 /* Maximum number of registers to represent a value of mode MODE
7634 in a register of class RCLASS. */
7635
7636 int
7637 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7638 {
7639 switch (rclass)
7640 {
7641 case FP_REGS:
7642 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7643 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7644 else
7645 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7646 case ACCESS_REGS:
7647 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7648 default:
7649 break;
7650 }
7651 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7652 }
7653
7654 /* Return true if register FROM can be eliminated via register TO. */
7655
7656 static bool
7657 s390_can_eliminate (const int from, const int to)
7658 {
7659 /* On zSeries machines, we have not marked the base register as fixed.
7660 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7661 If a function requires the base register, we say here that this
7662 elimination cannot be performed. This will cause reload to free
7663 up the base register (as if it were fixed). On the other hand,
7664 if the current function does *not* require the base register, we
7665 say here the elimination succeeds, which in turn allows reload
7666 to allocate the base register for any other purpose. */
7667 if (from == BASE_REGNUM && to == BASE_REGNUM)
7668 {
7669 if (TARGET_CPU_ZARCH)
7670 {
7671 s390_init_frame_layout ();
7672 return cfun->machine->base_reg == NULL_RTX;
7673 }
7674
7675 return false;
7676 }
7677
7678 /* Everything else must point into the stack frame. */
7679 gcc_assert (to == STACK_POINTER_REGNUM
7680 || to == HARD_FRAME_POINTER_REGNUM);
7681
7682 gcc_assert (from == FRAME_POINTER_REGNUM
7683 || from == ARG_POINTER_REGNUM
7684 || from == RETURN_ADDRESS_POINTER_REGNUM);
7685
7686 /* Make sure we actually saved the return address. */
7687 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7688 if (!crtl->calls_eh_return
7689 && !cfun->stdarg
7690 && !cfun_frame_layout.save_return_addr_p)
7691 return false;
7692
7693 return true;
7694 }
7695
7696 /* Return offset between register FROM and TO initially after prolog. */
7697
7698 HOST_WIDE_INT
7699 s390_initial_elimination_offset (int from, int to)
7700 {
7701 HOST_WIDE_INT offset;
7702 int index;
7703
7704 /* ??? Why are we called for non-eliminable pairs? */
7705 if (!s390_can_eliminate (from, to))
7706 return 0;
7707
7708 switch (from)
7709 {
7710 case FRAME_POINTER_REGNUM:
7711 offset = (get_frame_size()
7712 + STACK_POINTER_OFFSET
7713 + crtl->outgoing_args_size);
7714 break;
7715
7716 case ARG_POINTER_REGNUM:
7717 s390_init_frame_layout ();
7718 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7719 break;
7720
7721 case RETURN_ADDRESS_POINTER_REGNUM:
7722 s390_init_frame_layout ();
7723 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7724 gcc_assert (index >= 0);
7725 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7726 offset += index * UNITS_PER_LONG;
7727 break;
7728
7729 case BASE_REGNUM:
7730 offset = 0;
7731 break;
7732
7733 default:
7734 gcc_unreachable ();
7735 }
7736
7737 return offset;
7738 }
7739
7740 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7741 to register BASE. Return generated insn. */
7742
7743 static rtx
7744 save_fpr (rtx base, int offset, int regnum)
7745 {
7746 rtx addr;
7747 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7748
7749 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7750 set_mem_alias_set (addr, get_varargs_alias_set ());
7751 else
7752 set_mem_alias_set (addr, get_frame_alias_set ());
7753
7754 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7755 }
7756
7757 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7758 to register BASE. Return generated insn. */
7759
7760 static rtx
7761 restore_fpr (rtx base, int offset, int regnum)
7762 {
7763 rtx addr;
7764 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7765 set_mem_alias_set (addr, get_frame_alias_set ());
7766
7767 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7768 }
7769
7770 /* Return true if REGNO is a global register, but not one
7771 of the special ones that need to be saved/restored in anyway. */
7772
7773 static inline bool
7774 global_not_special_regno_p (int regno)
7775 {
7776 return (global_regs[regno]
7777 /* These registers are special and need to be
7778 restored in any case. */
7779 && !(regno == STACK_POINTER_REGNUM
7780 || regno == RETURN_REGNUM
7781 || regno == BASE_REGNUM
7782 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7783 }
7784
7785 /* Generate insn to save registers FIRST to LAST into
7786 the register save area located at offset OFFSET
7787 relative to register BASE. */
7788
7789 static rtx
7790 save_gprs (rtx base, int offset, int first, int last)
7791 {
7792 rtx addr, insn, note;
7793 int i;
7794
7795 addr = plus_constant (Pmode, base, offset);
7796 addr = gen_rtx_MEM (Pmode, addr);
7797
7798 set_mem_alias_set (addr, get_frame_alias_set ());
7799
7800 /* Special-case single register. */
7801 if (first == last)
7802 {
7803 if (TARGET_64BIT)
7804 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7805 else
7806 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7807
7808 if (!global_not_special_regno_p (first))
7809 RTX_FRAME_RELATED_P (insn) = 1;
7810 return insn;
7811 }
7812
7813
7814 insn = gen_store_multiple (addr,
7815 gen_rtx_REG (Pmode, first),
7816 GEN_INT (last - first + 1));
7817
7818 if (first <= 6 && cfun->stdarg)
7819 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7820 {
7821 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7822
7823 if (first + i <= 6)
7824 set_mem_alias_set (mem, get_varargs_alias_set ());
7825 }
7826
7827 /* We need to set the FRAME_RELATED flag on all SETs
7828 inside the store-multiple pattern.
7829
7830 However, we must not emit DWARF records for registers 2..5
7831 if they are stored for use by variable arguments ...
7832
7833 ??? Unfortunately, it is not enough to simply not the
7834 FRAME_RELATED flags for those SETs, because the first SET
7835 of the PARALLEL is always treated as if it had the flag
7836 set, even if it does not. Therefore we emit a new pattern
7837 without those registers as REG_FRAME_RELATED_EXPR note. */
7838
7839 if (first >= 6 && !global_not_special_regno_p (first))
7840 {
7841 rtx pat = PATTERN (insn);
7842
7843 for (i = 0; i < XVECLEN (pat, 0); i++)
7844 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7845 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7846 0, i)))))
7847 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7848
7849 RTX_FRAME_RELATED_P (insn) = 1;
7850 }
7851 else if (last >= 6)
7852 {
7853 int start;
7854
7855 for (start = first >= 6 ? first : 6; start <= last; start++)
7856 if (!global_not_special_regno_p (start))
7857 break;
7858
7859 if (start > last)
7860 return insn;
7861
7862 addr = plus_constant (Pmode, base,
7863 offset + (start - first) * UNITS_PER_LONG);
7864 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7865 gen_rtx_REG (Pmode, start),
7866 GEN_INT (last - start + 1));
7867 note = PATTERN (note);
7868
7869 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7870
7871 for (i = 0; i < XVECLEN (note, 0); i++)
7872 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7873 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7874 0, i)))))
7875 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7876
7877 RTX_FRAME_RELATED_P (insn) = 1;
7878 }
7879
7880 return insn;
7881 }
7882
7883 /* Generate insn to restore registers FIRST to LAST from
7884 the register save area located at offset OFFSET
7885 relative to register BASE. */
7886
7887 static rtx
7888 restore_gprs (rtx base, int offset, int first, int last)
7889 {
7890 rtx addr, insn;
7891
7892 addr = plus_constant (Pmode, base, offset);
7893 addr = gen_rtx_MEM (Pmode, addr);
7894 set_mem_alias_set (addr, get_frame_alias_set ());
7895
7896 /* Special-case single register. */
7897 if (first == last)
7898 {
7899 if (TARGET_64BIT)
7900 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7901 else
7902 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7903
7904 return insn;
7905 }
7906
7907 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7908 addr,
7909 GEN_INT (last - first + 1));
7910 return insn;
7911 }
7912
7913 /* Return insn sequence to load the GOT register. */
7914
7915 static GTY(()) rtx got_symbol;
7916 rtx
7917 s390_load_got (void)
7918 {
7919 rtx insns;
7920
7921 /* We cannot use pic_offset_table_rtx here since we use this
7922 function also for non-pic if __tls_get_offset is called and in
7923 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
7924 aren't usable. */
7925 rtx got_rtx = gen_rtx_REG (Pmode, 12);
7926
7927 if (!got_symbol)
7928 {
7929 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7930 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7931 }
7932
7933 start_sequence ();
7934
7935 if (TARGET_CPU_ZARCH)
7936 {
7937 emit_move_insn (got_rtx, got_symbol);
7938 }
7939 else
7940 {
7941 rtx offset;
7942
7943 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7944 UNSPEC_LTREL_OFFSET);
7945 offset = gen_rtx_CONST (Pmode, offset);
7946 offset = force_const_mem (Pmode, offset);
7947
7948 emit_move_insn (got_rtx, offset);
7949
7950 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7951 UNSPEC_LTREL_BASE);
7952 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
7953
7954 emit_move_insn (got_rtx, offset);
7955 }
7956
7957 insns = get_insns ();
7958 end_sequence ();
7959 return insns;
7960 }
7961
7962 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7963 and the change to the stack pointer. */
7964
7965 static void
7966 s390_emit_stack_tie (void)
7967 {
7968 rtx mem = gen_frame_mem (BLKmode,
7969 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7970
7971 emit_insn (gen_stack_tie (mem));
7972 }
7973
7974 /* Expand the prologue into a bunch of separate insns. */
7975
7976 void
7977 s390_emit_prologue (void)
7978 {
7979 rtx insn, addr;
7980 rtx temp_reg;
7981 int i;
7982 int offset;
7983 int next_fpr = 0;
7984
7985 /* Complete frame layout. */
7986
7987 s390_update_frame_layout ();
7988
7989 /* Annotate all constant pool references to let the scheduler know
7990 they implicitly use the base register. */
7991
7992 push_topmost_sequence ();
7993
7994 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7995 if (INSN_P (insn))
7996 {
7997 annotate_constant_pool_refs (&PATTERN (insn));
7998 df_insn_rescan (insn);
7999 }
8000
8001 pop_topmost_sequence ();
8002
8003 /* Choose best register to use for temp use within prologue.
8004 See below for why TPF must use the register 1. */
8005
8006 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8007 && !crtl->is_leaf
8008 && !TARGET_TPF_PROFILING)
8009 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8010 else
8011 temp_reg = gen_rtx_REG (Pmode, 1);
8012
8013 /* Save call saved gprs. */
8014 if (cfun_frame_layout.first_save_gpr != -1)
8015 {
8016 insn = save_gprs (stack_pointer_rtx,
8017 cfun_frame_layout.gprs_offset +
8018 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8019 - cfun_frame_layout.first_save_gpr_slot),
8020 cfun_frame_layout.first_save_gpr,
8021 cfun_frame_layout.last_save_gpr);
8022 emit_insn (insn);
8023 }
8024
8025 /* Dummy insn to mark literal pool slot. */
8026
8027 if (cfun->machine->base_reg)
8028 emit_insn (gen_main_pool (cfun->machine->base_reg));
8029
8030 offset = cfun_frame_layout.f0_offset;
8031
8032 /* Save f0 and f2. */
8033 for (i = 0; i < 2; i++)
8034 {
8035 if (cfun_fpr_bit_p (i))
8036 {
8037 save_fpr (stack_pointer_rtx, offset, i + 16);
8038 offset += 8;
8039 }
8040 else if (!TARGET_PACKED_STACK)
8041 offset += 8;
8042 }
8043
8044 /* Save f4 and f6. */
8045 offset = cfun_frame_layout.f4_offset;
8046 for (i = 2; i < 4; i++)
8047 {
8048 if (cfun_fpr_bit_p (i))
8049 {
8050 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8051 offset += 8;
8052
8053 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8054 therefore are not frame related. */
8055 if (!call_really_used_regs[i + 16])
8056 RTX_FRAME_RELATED_P (insn) = 1;
8057 }
8058 else if (!TARGET_PACKED_STACK)
8059 offset += 8;
8060 }
8061
8062 if (TARGET_PACKED_STACK
8063 && cfun_save_high_fprs_p
8064 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8065 {
8066 offset = (cfun_frame_layout.f8_offset
8067 + (cfun_frame_layout.high_fprs - 1) * 8);
8068
8069 for (i = 15; i > 7 && offset >= 0; i--)
8070 if (cfun_fpr_bit_p (i))
8071 {
8072 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8073
8074 RTX_FRAME_RELATED_P (insn) = 1;
8075 offset -= 8;
8076 }
8077 if (offset >= cfun_frame_layout.f8_offset)
8078 next_fpr = i + 16;
8079 }
8080
8081 if (!TARGET_PACKED_STACK)
8082 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8083
8084 if (flag_stack_usage_info)
8085 current_function_static_stack_size = cfun_frame_layout.frame_size;
8086
8087 /* Decrement stack pointer. */
8088
8089 if (cfun_frame_layout.frame_size > 0)
8090 {
8091 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8092 rtx real_frame_off;
8093
8094 if (s390_stack_size)
8095 {
8096 HOST_WIDE_INT stack_guard;
8097
8098 if (s390_stack_guard)
8099 stack_guard = s390_stack_guard;
8100 else
8101 {
8102 /* If no value for stack guard is provided the smallest power of 2
8103 larger than the current frame size is chosen. */
8104 stack_guard = 1;
8105 while (stack_guard < cfun_frame_layout.frame_size)
8106 stack_guard <<= 1;
8107 }
8108
8109 if (cfun_frame_layout.frame_size >= s390_stack_size)
8110 {
8111 warning (0, "frame size of function %qs is %wd"
8112 " bytes exceeding user provided stack limit of "
8113 "%d bytes. "
8114 "An unconditional trap is added.",
8115 current_function_name(), cfun_frame_layout.frame_size,
8116 s390_stack_size);
8117 emit_insn (gen_trap ());
8118 }
8119 else
8120 {
8121 /* stack_guard has to be smaller than s390_stack_size.
8122 Otherwise we would emit an AND with zero which would
8123 not match the test under mask pattern. */
8124 if (stack_guard >= s390_stack_size)
8125 {
8126 warning (0, "frame size of function %qs is %wd"
8127 " bytes which is more than half the stack size. "
8128 "The dynamic check would not be reliable. "
8129 "No check emitted for this function.",
8130 current_function_name(),
8131 cfun_frame_layout.frame_size);
8132 }
8133 else
8134 {
8135 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8136 & ~(stack_guard - 1));
8137
8138 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8139 GEN_INT (stack_check_mask));
8140 if (TARGET_64BIT)
8141 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8142 t, const0_rtx),
8143 t, const0_rtx, const0_rtx));
8144 else
8145 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8146 t, const0_rtx),
8147 t, const0_rtx, const0_rtx));
8148 }
8149 }
8150 }
8151
8152 if (s390_warn_framesize > 0
8153 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8154 warning (0, "frame size of %qs is %wd bytes",
8155 current_function_name (), cfun_frame_layout.frame_size);
8156
8157 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8158 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8159
8160 /* Save incoming stack pointer into temp reg. */
8161 if (TARGET_BACKCHAIN || next_fpr)
8162 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8163
8164 /* Subtract frame size from stack pointer. */
8165
8166 if (DISP_IN_RANGE (INTVAL (frame_off)))
8167 {
8168 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8169 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8170 frame_off));
8171 insn = emit_insn (insn);
8172 }
8173 else
8174 {
8175 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8176 frame_off = force_const_mem (Pmode, frame_off);
8177
8178 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8179 annotate_constant_pool_refs (&PATTERN (insn));
8180 }
8181
8182 RTX_FRAME_RELATED_P (insn) = 1;
8183 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8184 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8185 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8186 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8187 real_frame_off)));
8188
8189 /* Set backchain. */
8190
8191 if (TARGET_BACKCHAIN)
8192 {
8193 if (cfun_frame_layout.backchain_offset)
8194 addr = gen_rtx_MEM (Pmode,
8195 plus_constant (Pmode, stack_pointer_rtx,
8196 cfun_frame_layout.backchain_offset));
8197 else
8198 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8199 set_mem_alias_set (addr, get_frame_alias_set ());
8200 insn = emit_insn (gen_move_insn (addr, temp_reg));
8201 }
8202
8203 /* If we support non-call exceptions (e.g. for Java),
8204 we need to make sure the backchain pointer is set up
8205 before any possibly trapping memory access. */
8206 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8207 {
8208 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8209 emit_clobber (addr);
8210 }
8211 }
8212
8213 /* Save fprs 8 - 15 (64 bit ABI). */
8214
8215 if (cfun_save_high_fprs_p && next_fpr)
8216 {
8217 /* If the stack might be accessed through a different register
8218 we have to make sure that the stack pointer decrement is not
8219 moved below the use of the stack slots. */
8220 s390_emit_stack_tie ();
8221
8222 insn = emit_insn (gen_add2_insn (temp_reg,
8223 GEN_INT (cfun_frame_layout.f8_offset)));
8224
8225 offset = 0;
8226
8227 for (i = 24; i <= next_fpr; i++)
8228 if (cfun_fpr_bit_p (i - 16))
8229 {
8230 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8231 cfun_frame_layout.frame_size
8232 + cfun_frame_layout.f8_offset
8233 + offset);
8234
8235 insn = save_fpr (temp_reg, offset, i);
8236 offset += 8;
8237 RTX_FRAME_RELATED_P (insn) = 1;
8238 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8239 gen_rtx_SET (VOIDmode,
8240 gen_rtx_MEM (DFmode, addr),
8241 gen_rtx_REG (DFmode, i)));
8242 }
8243 }
8244
8245 /* Set frame pointer, if needed. */
8246
8247 if (frame_pointer_needed)
8248 {
8249 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8250 RTX_FRAME_RELATED_P (insn) = 1;
8251 }
8252
8253 /* Set up got pointer, if needed. */
8254
8255 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8256 {
8257 rtx insns = s390_load_got ();
8258
8259 for (insn = insns; insn; insn = NEXT_INSN (insn))
8260 annotate_constant_pool_refs (&PATTERN (insn));
8261
8262 emit_insn (insns);
8263 }
8264
8265 if (TARGET_TPF_PROFILING)
8266 {
8267 /* Generate a BAS instruction to serve as a function
8268 entry intercept to facilitate the use of tracing
8269 algorithms located at the branch target. */
8270 emit_insn (gen_prologue_tpf ());
8271
8272 /* Emit a blockage here so that all code
8273 lies between the profiling mechanisms. */
8274 emit_insn (gen_blockage ());
8275 }
8276 }
8277
8278 /* Expand the epilogue into a bunch of separate insns. */
8279
8280 void
8281 s390_emit_epilogue (bool sibcall)
8282 {
8283 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8284 int area_bottom, area_top, offset = 0;
8285 int next_offset;
8286 rtvec p;
8287 int i;
8288
8289 if (TARGET_TPF_PROFILING)
8290 {
8291
8292 /* Generate a BAS instruction to serve as a function
8293 entry intercept to facilitate the use of tracing
8294 algorithms located at the branch target. */
8295
8296 /* Emit a blockage here so that all code
8297 lies between the profiling mechanisms. */
8298 emit_insn (gen_blockage ());
8299
8300 emit_insn (gen_epilogue_tpf ());
8301 }
8302
8303 /* Check whether to use frame or stack pointer for restore. */
8304
8305 frame_pointer = (frame_pointer_needed
8306 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8307
8308 s390_frame_area (&area_bottom, &area_top);
8309
8310 /* Check whether we can access the register save area.
8311 If not, increment the frame pointer as required. */
8312
8313 if (area_top <= area_bottom)
8314 {
8315 /* Nothing to restore. */
8316 }
8317 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8318 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8319 {
8320 /* Area is in range. */
8321 offset = cfun_frame_layout.frame_size;
8322 }
8323 else
8324 {
8325 rtx insn, frame_off, cfa;
8326
8327 offset = area_bottom < 0 ? -area_bottom : 0;
8328 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8329
8330 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8331 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8332 if (DISP_IN_RANGE (INTVAL (frame_off)))
8333 {
8334 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8335 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8336 insn = emit_insn (insn);
8337 }
8338 else
8339 {
8340 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8341 frame_off = force_const_mem (Pmode, frame_off);
8342
8343 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8344 annotate_constant_pool_refs (&PATTERN (insn));
8345 }
8346 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8347 RTX_FRAME_RELATED_P (insn) = 1;
8348 }
8349
8350 /* Restore call saved fprs. */
8351
8352 if (TARGET_64BIT)
8353 {
8354 if (cfun_save_high_fprs_p)
8355 {
8356 next_offset = cfun_frame_layout.f8_offset;
8357 for (i = 24; i < 32; i++)
8358 {
8359 if (cfun_fpr_bit_p (i - 16))
8360 {
8361 restore_fpr (frame_pointer,
8362 offset + next_offset, i);
8363 cfa_restores
8364 = alloc_reg_note (REG_CFA_RESTORE,
8365 gen_rtx_REG (DFmode, i), cfa_restores);
8366 next_offset += 8;
8367 }
8368 }
8369 }
8370
8371 }
8372 else
8373 {
8374 next_offset = cfun_frame_layout.f4_offset;
8375 for (i = 18; i < 20; i++)
8376 {
8377 if (cfun_fpr_bit_p (i - 16))
8378 {
8379 restore_fpr (frame_pointer,
8380 offset + next_offset, i);
8381 cfa_restores
8382 = alloc_reg_note (REG_CFA_RESTORE,
8383 gen_rtx_REG (DFmode, i), cfa_restores);
8384 next_offset += 8;
8385 }
8386 else if (!TARGET_PACKED_STACK)
8387 next_offset += 8;
8388 }
8389
8390 }
8391
8392 /* Return register. */
8393
8394 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8395
8396 /* Restore call saved gprs. */
8397
8398 if (cfun_frame_layout.first_restore_gpr != -1)
8399 {
8400 rtx insn, addr;
8401 int i;
8402
8403 /* Check for global register and save them
8404 to stack location from where they get restored. */
8405
8406 for (i = cfun_frame_layout.first_restore_gpr;
8407 i <= cfun_frame_layout.last_restore_gpr;
8408 i++)
8409 {
8410 if (global_not_special_regno_p (i))
8411 {
8412 addr = plus_constant (Pmode, frame_pointer,
8413 offset + cfun_frame_layout.gprs_offset
8414 + (i - cfun_frame_layout.first_save_gpr_slot)
8415 * UNITS_PER_LONG);
8416 addr = gen_rtx_MEM (Pmode, addr);
8417 set_mem_alias_set (addr, get_frame_alias_set ());
8418 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8419 }
8420 else
8421 cfa_restores
8422 = alloc_reg_note (REG_CFA_RESTORE,
8423 gen_rtx_REG (Pmode, i), cfa_restores);
8424 }
8425
8426 if (! sibcall)
8427 {
8428 /* Fetch return address from stack before load multiple,
8429 this will do good for scheduling. */
8430
8431 if (cfun_frame_layout.save_return_addr_p
8432 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8433 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8434 {
8435 int return_regnum = find_unused_clobbered_reg();
8436 if (!return_regnum)
8437 return_regnum = 4;
8438 return_reg = gen_rtx_REG (Pmode, return_regnum);
8439
8440 addr = plus_constant (Pmode, frame_pointer,
8441 offset + cfun_frame_layout.gprs_offset
8442 + (RETURN_REGNUM
8443 - cfun_frame_layout.first_save_gpr_slot)
8444 * UNITS_PER_LONG);
8445 addr = gen_rtx_MEM (Pmode, addr);
8446 set_mem_alias_set (addr, get_frame_alias_set ());
8447 emit_move_insn (return_reg, addr);
8448 }
8449 }
8450
8451 insn = restore_gprs (frame_pointer,
8452 offset + cfun_frame_layout.gprs_offset
8453 + (cfun_frame_layout.first_restore_gpr
8454 - cfun_frame_layout.first_save_gpr_slot)
8455 * UNITS_PER_LONG,
8456 cfun_frame_layout.first_restore_gpr,
8457 cfun_frame_layout.last_restore_gpr);
8458 insn = emit_insn (insn);
8459 REG_NOTES (insn) = cfa_restores;
8460 add_reg_note (insn, REG_CFA_DEF_CFA,
8461 plus_constant (Pmode, stack_pointer_rtx,
8462 STACK_POINTER_OFFSET));
8463 RTX_FRAME_RELATED_P (insn) = 1;
8464 }
8465
8466 if (! sibcall)
8467 {
8468
8469 /* Return to caller. */
8470
8471 p = rtvec_alloc (2);
8472
8473 RTVEC_ELT (p, 0) = ret_rtx;
8474 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8475 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8476 }
8477 }
8478
8479
8480 /* Return the size in bytes of a function argument of
8481 type TYPE and/or mode MODE. At least one of TYPE or
8482 MODE must be specified. */
8483
8484 static int
8485 s390_function_arg_size (enum machine_mode mode, const_tree type)
8486 {
8487 if (type)
8488 return int_size_in_bytes (type);
8489
8490 /* No type info available for some library calls ... */
8491 if (mode != BLKmode)
8492 return GET_MODE_SIZE (mode);
8493
8494 /* If we have neither type nor mode, abort */
8495 gcc_unreachable ();
8496 }
8497
8498 /* Return true if a function argument of type TYPE and mode MODE
8499 is to be passed in a floating-point register, if available. */
8500
8501 static bool
8502 s390_function_arg_float (enum machine_mode mode, const_tree type)
8503 {
8504 int size = s390_function_arg_size (mode, type);
8505 if (size > 8)
8506 return false;
8507
8508 /* Soft-float changes the ABI: no floating-point registers are used. */
8509 if (TARGET_SOFT_FLOAT)
8510 return false;
8511
8512 /* No type info available for some library calls ... */
8513 if (!type)
8514 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8515
8516 /* The ABI says that record types with a single member are treated
8517 just like that member would be. */
8518 while (TREE_CODE (type) == RECORD_TYPE)
8519 {
8520 tree field, single = NULL_TREE;
8521
8522 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8523 {
8524 if (TREE_CODE (field) != FIELD_DECL)
8525 continue;
8526
8527 if (single == NULL_TREE)
8528 single = TREE_TYPE (field);
8529 else
8530 return false;
8531 }
8532
8533 if (single == NULL_TREE)
8534 return false;
8535 else
8536 type = single;
8537 }
8538
8539 return TREE_CODE (type) == REAL_TYPE;
8540 }
8541
8542 /* Return true if a function argument of type TYPE and mode MODE
8543 is to be passed in an integer register, or a pair of integer
8544 registers, if available. */
8545
8546 static bool
8547 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8548 {
8549 int size = s390_function_arg_size (mode, type);
8550 if (size > 8)
8551 return false;
8552
8553 /* No type info available for some library calls ... */
8554 if (!type)
8555 return GET_MODE_CLASS (mode) == MODE_INT
8556 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8557
8558 /* We accept small integral (and similar) types. */
8559 if (INTEGRAL_TYPE_P (type)
8560 || POINTER_TYPE_P (type)
8561 || TREE_CODE (type) == NULLPTR_TYPE
8562 || TREE_CODE (type) == OFFSET_TYPE
8563 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8564 return true;
8565
8566 /* We also accept structs of size 1, 2, 4, 8 that are not
8567 passed in floating-point registers. */
8568 if (AGGREGATE_TYPE_P (type)
8569 && exact_log2 (size) >= 0
8570 && !s390_function_arg_float (mode, type))
8571 return true;
8572
8573 return false;
8574 }
8575
8576 /* Return 1 if a function argument of type TYPE and mode MODE
8577 is to be passed by reference. The ABI specifies that only
8578 structures of size 1, 2, 4, or 8 bytes are passed by value,
8579 all other structures (and complex numbers) are passed by
8580 reference. */
8581
8582 static bool
8583 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
8584 enum machine_mode mode, const_tree type,
8585 bool named ATTRIBUTE_UNUSED)
8586 {
8587 int size = s390_function_arg_size (mode, type);
8588 if (size > 8)
8589 return true;
8590
8591 if (type)
8592 {
8593 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8594 return 1;
8595
8596 if (TREE_CODE (type) == COMPLEX_TYPE
8597 || TREE_CODE (type) == VECTOR_TYPE)
8598 return 1;
8599 }
8600
8601 return 0;
8602 }
8603
8604 /* Update the data in CUM to advance over an argument of mode MODE and
8605 data type TYPE. (TYPE is null for libcalls where that information
8606 may not be available.). The boolean NAMED specifies whether the
8607 argument is a named argument (as opposed to an unnamed argument
8608 matching an ellipsis). */
8609
8610 static void
8611 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
8612 const_tree type, bool named ATTRIBUTE_UNUSED)
8613 {
8614 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8615
8616 if (s390_function_arg_float (mode, type))
8617 {
8618 cum->fprs += 1;
8619 }
8620 else if (s390_function_arg_integer (mode, type))
8621 {
8622 int size = s390_function_arg_size (mode, type);
8623 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8624 }
8625 else
8626 gcc_unreachable ();
8627 }
8628
8629 /* Define where to put the arguments to a function.
8630 Value is zero to push the argument on the stack,
8631 or a hard register in which to store the argument.
8632
8633 MODE is the argument's machine mode.
8634 TYPE is the data type of the argument (as a tree).
8635 This is null for libcalls where that information may
8636 not be available.
8637 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8638 the preceding args and about the function being called.
8639 NAMED is nonzero if this argument is a named parameter
8640 (otherwise it is an extra parameter matching an ellipsis).
8641
8642 On S/390, we use general purpose registers 2 through 6 to
8643 pass integer, pointer, and certain structure arguments, and
8644 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8645 to pass floating point arguments. All remaining arguments
8646 are pushed to the stack. */
8647
8648 static rtx
8649 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8650 const_tree type, bool named ATTRIBUTE_UNUSED)
8651 {
8652 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8653
8654 if (s390_function_arg_float (mode, type))
8655 {
8656 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8657 return 0;
8658 else
8659 return gen_rtx_REG (mode, cum->fprs + 16);
8660 }
8661 else if (s390_function_arg_integer (mode, type))
8662 {
8663 int size = s390_function_arg_size (mode, type);
8664 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8665
8666 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8667 return 0;
8668 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8669 return gen_rtx_REG (mode, cum->gprs + 2);
8670 else if (n_gprs == 2)
8671 {
8672 rtvec p = rtvec_alloc (2);
8673
8674 RTVEC_ELT (p, 0)
8675 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8676 const0_rtx);
8677 RTVEC_ELT (p, 1)
8678 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8679 GEN_INT (4));
8680
8681 return gen_rtx_PARALLEL (mode, p);
8682 }
8683 }
8684
8685 /* After the real arguments, expand_call calls us once again
8686 with a void_type_node type. Whatever we return here is
8687 passed as operand 2 to the call expanders.
8688
8689 We don't need this feature ... */
8690 else if (type == void_type_node)
8691 return const0_rtx;
8692
8693 gcc_unreachable ();
8694 }
8695
8696 /* Return true if return values of type TYPE should be returned
8697 in a memory buffer whose address is passed by the caller as
8698 hidden first argument. */
8699
8700 static bool
8701 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8702 {
8703 /* We accept small integral (and similar) types. */
8704 if (INTEGRAL_TYPE_P (type)
8705 || POINTER_TYPE_P (type)
8706 || TREE_CODE (type) == OFFSET_TYPE
8707 || TREE_CODE (type) == REAL_TYPE)
8708 return int_size_in_bytes (type) > 8;
8709
8710 /* Aggregates and similar constructs are always returned
8711 in memory. */
8712 if (AGGREGATE_TYPE_P (type)
8713 || TREE_CODE (type) == COMPLEX_TYPE
8714 || TREE_CODE (type) == VECTOR_TYPE)
8715 return true;
8716
8717 /* ??? We get called on all sorts of random stuff from
8718 aggregate_value_p. We can't abort, but it's not clear
8719 what's safe to return. Pretend it's a struct I guess. */
8720 return true;
8721 }
8722
8723 /* Function arguments and return values are promoted to word size. */
8724
8725 static enum machine_mode
8726 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8727 int *punsignedp,
8728 const_tree fntype ATTRIBUTE_UNUSED,
8729 int for_return ATTRIBUTE_UNUSED)
8730 {
8731 if (INTEGRAL_MODE_P (mode)
8732 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8733 {
8734 if (type != NULL_TREE && POINTER_TYPE_P (type))
8735 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8736 return Pmode;
8737 }
8738
8739 return mode;
8740 }
8741
8742 /* Define where to return a (scalar) value of type RET_TYPE.
8743 If RET_TYPE is null, define where to return a (scalar)
8744 value of mode MODE from a libcall. */
8745
8746 static rtx
8747 s390_function_and_libcall_value (enum machine_mode mode,
8748 const_tree ret_type,
8749 const_tree fntype_or_decl,
8750 bool outgoing ATTRIBUTE_UNUSED)
8751 {
8752 /* For normal functions perform the promotion as
8753 promote_function_mode would do. */
8754 if (ret_type)
8755 {
8756 int unsignedp = TYPE_UNSIGNED (ret_type);
8757 mode = promote_function_mode (ret_type, mode, &unsignedp,
8758 fntype_or_decl, 1);
8759 }
8760
8761 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8762 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8763
8764 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8765 return gen_rtx_REG (mode, 16);
8766 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8767 || UNITS_PER_LONG == UNITS_PER_WORD)
8768 return gen_rtx_REG (mode, 2);
8769 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8770 {
8771 /* This case is triggered when returning a 64 bit value with
8772 -m31 -mzarch. Although the value would fit into a single
8773 register it has to be forced into a 32 bit register pair in
8774 order to match the ABI. */
8775 rtvec p = rtvec_alloc (2);
8776
8777 RTVEC_ELT (p, 0)
8778 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8779 RTVEC_ELT (p, 1)
8780 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8781
8782 return gen_rtx_PARALLEL (mode, p);
8783 }
8784
8785 gcc_unreachable ();
8786 }
8787
8788 /* Define where to return a scalar return value of type RET_TYPE. */
8789
8790 static rtx
8791 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8792 bool outgoing)
8793 {
8794 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8795 fn_decl_or_type, outgoing);
8796 }
8797
8798 /* Define where to return a scalar libcall return value of mode
8799 MODE. */
8800
8801 static rtx
8802 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8803 {
8804 return s390_function_and_libcall_value (mode, NULL_TREE,
8805 NULL_TREE, true);
8806 }
8807
8808
8809 /* Create and return the va_list datatype.
8810
8811 On S/390, va_list is an array type equivalent to
8812
8813 typedef struct __va_list_tag
8814 {
8815 long __gpr;
8816 long __fpr;
8817 void *__overflow_arg_area;
8818 void *__reg_save_area;
8819 } va_list[1];
8820
8821 where __gpr and __fpr hold the number of general purpose
8822 or floating point arguments used up to now, respectively,
8823 __overflow_arg_area points to the stack location of the
8824 next argument passed on the stack, and __reg_save_area
8825 always points to the start of the register area in the
8826 call frame of the current function. The function prologue
8827 saves all registers used for argument passing into this
8828 area if the function uses variable arguments. */
8829
8830 static tree
8831 s390_build_builtin_va_list (void)
8832 {
8833 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8834
8835 record = lang_hooks.types.make_type (RECORD_TYPE);
8836
8837 type_decl =
8838 build_decl (BUILTINS_LOCATION,
8839 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8840
8841 f_gpr = build_decl (BUILTINS_LOCATION,
8842 FIELD_DECL, get_identifier ("__gpr"),
8843 long_integer_type_node);
8844 f_fpr = build_decl (BUILTINS_LOCATION,
8845 FIELD_DECL, get_identifier ("__fpr"),
8846 long_integer_type_node);
8847 f_ovf = build_decl (BUILTINS_LOCATION,
8848 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8849 ptr_type_node);
8850 f_sav = build_decl (BUILTINS_LOCATION,
8851 FIELD_DECL, get_identifier ("__reg_save_area"),
8852 ptr_type_node);
8853
8854 va_list_gpr_counter_field = f_gpr;
8855 va_list_fpr_counter_field = f_fpr;
8856
8857 DECL_FIELD_CONTEXT (f_gpr) = record;
8858 DECL_FIELD_CONTEXT (f_fpr) = record;
8859 DECL_FIELD_CONTEXT (f_ovf) = record;
8860 DECL_FIELD_CONTEXT (f_sav) = record;
8861
8862 TYPE_STUB_DECL (record) = type_decl;
8863 TYPE_NAME (record) = type_decl;
8864 TYPE_FIELDS (record) = f_gpr;
8865 DECL_CHAIN (f_gpr) = f_fpr;
8866 DECL_CHAIN (f_fpr) = f_ovf;
8867 DECL_CHAIN (f_ovf) = f_sav;
8868
8869 layout_type (record);
8870
8871 /* The correct type is an array type of one element. */
8872 return build_array_type (record, build_index_type (size_zero_node));
8873 }
8874
8875 /* Implement va_start by filling the va_list structure VALIST.
8876 STDARG_P is always true, and ignored.
8877 NEXTARG points to the first anonymous stack argument.
8878
8879 The following global variables are used to initialize
8880 the va_list structure:
8881
8882 crtl->args.info:
8883 holds number of gprs and fprs used for named arguments.
8884 crtl->args.arg_offset_rtx:
8885 holds the offset of the first anonymous stack argument
8886 (relative to the virtual arg pointer). */
8887
8888 static void
8889 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8890 {
8891 HOST_WIDE_INT n_gpr, n_fpr;
8892 int off;
8893 tree f_gpr, f_fpr, f_ovf, f_sav;
8894 tree gpr, fpr, ovf, sav, t;
8895
8896 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8897 f_fpr = DECL_CHAIN (f_gpr);
8898 f_ovf = DECL_CHAIN (f_fpr);
8899 f_sav = DECL_CHAIN (f_ovf);
8900
8901 valist = build_simple_mem_ref (valist);
8902 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8903 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8904 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8905 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8906
8907 /* Count number of gp and fp argument registers used. */
8908
8909 n_gpr = crtl->args.info.gprs;
8910 n_fpr = crtl->args.info.fprs;
8911
8912 if (cfun->va_list_gpr_size)
8913 {
8914 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8915 build_int_cst (NULL_TREE, n_gpr));
8916 TREE_SIDE_EFFECTS (t) = 1;
8917 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8918 }
8919
8920 if (cfun->va_list_fpr_size)
8921 {
8922 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8923 build_int_cst (NULL_TREE, n_fpr));
8924 TREE_SIDE_EFFECTS (t) = 1;
8925 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8926 }
8927
8928 /* Find the overflow area. */
8929 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8930 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8931 {
8932 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8933
8934 off = INTVAL (crtl->args.arg_offset_rtx);
8935 off = off < 0 ? 0 : off;
8936 if (TARGET_DEBUG_ARG)
8937 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8938 (int)n_gpr, (int)n_fpr, off);
8939
8940 t = fold_build_pointer_plus_hwi (t, off);
8941
8942 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8943 TREE_SIDE_EFFECTS (t) = 1;
8944 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8945 }
8946
8947 /* Find the register save area. */
8948 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8949 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8950 {
8951 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8952 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
8953
8954 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8955 TREE_SIDE_EFFECTS (t) = 1;
8956 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8957 }
8958 }
8959
8960 /* Implement va_arg by updating the va_list structure
8961 VALIST as required to retrieve an argument of type
8962 TYPE, and returning that argument.
8963
8964 Generates code equivalent to:
8965
8966 if (integral value) {
8967 if (size <= 4 && args.gpr < 5 ||
8968 size > 4 && args.gpr < 4 )
8969 ret = args.reg_save_area[args.gpr+8]
8970 else
8971 ret = *args.overflow_arg_area++;
8972 } else if (float value) {
8973 if (args.fgpr < 2)
8974 ret = args.reg_save_area[args.fpr+64]
8975 else
8976 ret = *args.overflow_arg_area++;
8977 } else if (aggregate value) {
8978 if (args.gpr < 5)
8979 ret = *args.reg_save_area[args.gpr]
8980 else
8981 ret = **args.overflow_arg_area++;
8982 } */
8983
8984 static tree
8985 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8986 gimple_seq *post_p ATTRIBUTE_UNUSED)
8987 {
8988 tree f_gpr, f_fpr, f_ovf, f_sav;
8989 tree gpr, fpr, ovf, sav, reg, t, u;
8990 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8991 tree lab_false, lab_over, addr;
8992
8993 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8994 f_fpr = DECL_CHAIN (f_gpr);
8995 f_ovf = DECL_CHAIN (f_fpr);
8996 f_sav = DECL_CHAIN (f_ovf);
8997
8998 valist = build_va_arg_indirect_ref (valist);
8999 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9000 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9001 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9002
9003 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9004 both appear on a lhs. */
9005 valist = unshare_expr (valist);
9006 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9007
9008 size = int_size_in_bytes (type);
9009
9010 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9011 {
9012 if (TARGET_DEBUG_ARG)
9013 {
9014 fprintf (stderr, "va_arg: aggregate type");
9015 debug_tree (type);
9016 }
9017
9018 /* Aggregates are passed by reference. */
9019 indirect_p = 1;
9020 reg = gpr;
9021 n_reg = 1;
9022
9023 /* kernel stack layout on 31 bit: It is assumed here that no padding
9024 will be added by s390_frame_info because for va_args always an even
9025 number of gprs has to be saved r15-r2 = 14 regs. */
9026 sav_ofs = 2 * UNITS_PER_LONG;
9027 sav_scale = UNITS_PER_LONG;
9028 size = UNITS_PER_LONG;
9029 max_reg = GP_ARG_NUM_REG - n_reg;
9030 }
9031 else if (s390_function_arg_float (TYPE_MODE (type), type))
9032 {
9033 if (TARGET_DEBUG_ARG)
9034 {
9035 fprintf (stderr, "va_arg: float type");
9036 debug_tree (type);
9037 }
9038
9039 /* FP args go in FP registers, if present. */
9040 indirect_p = 0;
9041 reg = fpr;
9042 n_reg = 1;
9043 sav_ofs = 16 * UNITS_PER_LONG;
9044 sav_scale = 8;
9045 max_reg = FP_ARG_NUM_REG - n_reg;
9046 }
9047 else
9048 {
9049 if (TARGET_DEBUG_ARG)
9050 {
9051 fprintf (stderr, "va_arg: other type");
9052 debug_tree (type);
9053 }
9054
9055 /* Otherwise into GP registers. */
9056 indirect_p = 0;
9057 reg = gpr;
9058 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9059
9060 /* kernel stack layout on 31 bit: It is assumed here that no padding
9061 will be added by s390_frame_info because for va_args always an even
9062 number of gprs has to be saved r15-r2 = 14 regs. */
9063 sav_ofs = 2 * UNITS_PER_LONG;
9064
9065 if (size < UNITS_PER_LONG)
9066 sav_ofs += UNITS_PER_LONG - size;
9067
9068 sav_scale = UNITS_PER_LONG;
9069 max_reg = GP_ARG_NUM_REG - n_reg;
9070 }
9071
9072 /* Pull the value out of the saved registers ... */
9073
9074 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9075 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9076 addr = create_tmp_var (ptr_type_node, "addr");
9077
9078 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9079 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9080 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9081 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9082 gimplify_and_add (t, pre_p);
9083
9084 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9085 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9086 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9087 t = fold_build_pointer_plus (t, u);
9088
9089 gimplify_assign (addr, t, pre_p);
9090
9091 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9092
9093 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9094
9095
9096 /* ... Otherwise out of the overflow area. */
9097
9098 t = ovf;
9099 if (size < UNITS_PER_LONG)
9100 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9101
9102 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9103
9104 gimplify_assign (addr, t, pre_p);
9105
9106 t = fold_build_pointer_plus_hwi (t, size);
9107 gimplify_assign (ovf, t, pre_p);
9108
9109 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9110
9111
9112 /* Increment register save count. */
9113
9114 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9115 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9116 gimplify_and_add (u, pre_p);
9117
9118 if (indirect_p)
9119 {
9120 t = build_pointer_type_for_mode (build_pointer_type (type),
9121 ptr_mode, true);
9122 addr = fold_convert (t, addr);
9123 addr = build_va_arg_indirect_ref (addr);
9124 }
9125 else
9126 {
9127 t = build_pointer_type_for_mode (type, ptr_mode, true);
9128 addr = fold_convert (t, addr);
9129 }
9130
9131 return build_va_arg_indirect_ref (addr);
9132 }
9133
9134
9135 /* Builtins. */
9136
9137 enum s390_builtin
9138 {
9139 S390_BUILTIN_THREAD_POINTER,
9140 S390_BUILTIN_SET_THREAD_POINTER,
9141
9142 S390_BUILTIN_max
9143 };
9144
9145 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9146 CODE_FOR_get_tp_64,
9147 CODE_FOR_set_tp_64
9148 };
9149
9150 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9151 CODE_FOR_get_tp_31,
9152 CODE_FOR_set_tp_31
9153 };
9154
9155 static void
9156 s390_init_builtins (void)
9157 {
9158 tree ftype;
9159
9160 ftype = build_function_type_list (ptr_type_node, NULL_TREE);
9161 add_builtin_function ("__builtin_thread_pointer", ftype,
9162 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9163 NULL, NULL_TREE);
9164
9165 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9166 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9167 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9168 NULL, NULL_TREE);
9169 }
9170
9171 /* Expand an expression EXP that calls a built-in function,
9172 with result going to TARGET if that's convenient
9173 (and in mode MODE if that's convenient).
9174 SUBTARGET may be used as the target for computing one of EXP's operands.
9175 IGNORE is nonzero if the value is to be ignored. */
9176
9177 static rtx
9178 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9179 enum machine_mode mode ATTRIBUTE_UNUSED,
9180 int ignore ATTRIBUTE_UNUSED)
9181 {
9182 #define MAX_ARGS 2
9183
9184 enum insn_code const *code_for_builtin =
9185 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9186
9187 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9188 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9189 enum insn_code icode;
9190 rtx op[MAX_ARGS], pat;
9191 int arity;
9192 bool nonvoid;
9193 tree arg;
9194 call_expr_arg_iterator iter;
9195
9196 if (fcode >= S390_BUILTIN_max)
9197 internal_error ("bad builtin fcode");
9198 icode = code_for_builtin[fcode];
9199 if (icode == 0)
9200 internal_error ("bad builtin fcode");
9201
9202 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9203
9204 arity = 0;
9205 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9206 {
9207 const struct insn_operand_data *insn_op;
9208
9209 if (arg == error_mark_node)
9210 return NULL_RTX;
9211 if (arity > MAX_ARGS)
9212 return NULL_RTX;
9213
9214 insn_op = &insn_data[icode].operand[arity + nonvoid];
9215
9216 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9217
9218 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9219 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9220 arity++;
9221 }
9222
9223 if (nonvoid)
9224 {
9225 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9226 if (!target
9227 || GET_MODE (target) != tmode
9228 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9229 target = gen_reg_rtx (tmode);
9230 }
9231
9232 switch (arity)
9233 {
9234 case 0:
9235 pat = GEN_FCN (icode) (target);
9236 break;
9237 case 1:
9238 if (nonvoid)
9239 pat = GEN_FCN (icode) (target, op[0]);
9240 else
9241 pat = GEN_FCN (icode) (op[0]);
9242 break;
9243 case 2:
9244 pat = GEN_FCN (icode) (target, op[0], op[1]);
9245 break;
9246 default:
9247 gcc_unreachable ();
9248 }
9249 if (!pat)
9250 return NULL_RTX;
9251 emit_insn (pat);
9252
9253 if (nonvoid)
9254 return target;
9255 else
9256 return const0_rtx;
9257 }
9258
9259
9260 /* Output assembly code for the trampoline template to
9261 stdio stream FILE.
9262
9263 On S/390, we use gpr 1 internally in the trampoline code;
9264 gpr 0 is used to hold the static chain. */
9265
9266 static void
9267 s390_asm_trampoline_template (FILE *file)
9268 {
9269 rtx op[2];
9270 op[0] = gen_rtx_REG (Pmode, 0);
9271 op[1] = gen_rtx_REG (Pmode, 1);
9272
9273 if (TARGET_64BIT)
9274 {
9275 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9276 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
9277 output_asm_insn ("br\t%1", op); /* 2 byte */
9278 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9279 }
9280 else
9281 {
9282 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9283 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
9284 output_asm_insn ("br\t%1", op); /* 2 byte */
9285 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9286 }
9287 }
9288
9289 /* Emit RTL insns to initialize the variable parts of a trampoline.
9290 FNADDR is an RTX for the address of the function's pure code.
9291 CXT is an RTX for the static chain value for the function. */
9292
9293 static void
9294 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9295 {
9296 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9297 rtx mem;
9298
9299 emit_block_move (m_tramp, assemble_trampoline_template (),
9300 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9301
9302 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9303 emit_move_insn (mem, cxt);
9304 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9305 emit_move_insn (mem, fnaddr);
9306 }
9307
9308 /* Output assembler code to FILE to increment profiler label # LABELNO
9309 for profiling a function entry. */
9310
9311 void
9312 s390_function_profiler (FILE *file, int labelno)
9313 {
9314 rtx op[7];
9315
9316 char label[128];
9317 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9318
9319 fprintf (file, "# function profiler \n");
9320
9321 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9322 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9323 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
9324
9325 op[2] = gen_rtx_REG (Pmode, 1);
9326 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9327 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9328
9329 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9330 if (flag_pic)
9331 {
9332 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9333 op[4] = gen_rtx_CONST (Pmode, op[4]);
9334 }
9335
9336 if (TARGET_64BIT)
9337 {
9338 output_asm_insn ("stg\t%0,%1", op);
9339 output_asm_insn ("larl\t%2,%3", op);
9340 output_asm_insn ("brasl\t%0,%4", op);
9341 output_asm_insn ("lg\t%0,%1", op);
9342 }
9343 else if (!flag_pic)
9344 {
9345 op[6] = gen_label_rtx ();
9346
9347 output_asm_insn ("st\t%0,%1", op);
9348 output_asm_insn ("bras\t%2,%l6", op);
9349 output_asm_insn (".long\t%4", op);
9350 output_asm_insn (".long\t%3", op);
9351 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9352 output_asm_insn ("l\t%0,0(%2)", op);
9353 output_asm_insn ("l\t%2,4(%2)", op);
9354 output_asm_insn ("basr\t%0,%0", op);
9355 output_asm_insn ("l\t%0,%1", op);
9356 }
9357 else
9358 {
9359 op[5] = gen_label_rtx ();
9360 op[6] = gen_label_rtx ();
9361
9362 output_asm_insn ("st\t%0,%1", op);
9363 output_asm_insn ("bras\t%2,%l6", op);
9364 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9365 output_asm_insn (".long\t%4-%l5", op);
9366 output_asm_insn (".long\t%3-%l5", op);
9367 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9368 output_asm_insn ("lr\t%0,%2", op);
9369 output_asm_insn ("a\t%0,0(%2)", op);
9370 output_asm_insn ("a\t%2,4(%2)", op);
9371 output_asm_insn ("basr\t%0,%0", op);
9372 output_asm_insn ("l\t%0,%1", op);
9373 }
9374 }
9375
9376 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9377 into its SYMBOL_REF_FLAGS. */
9378
9379 static void
9380 s390_encode_section_info (tree decl, rtx rtl, int first)
9381 {
9382 default_encode_section_info (decl, rtl, first);
9383
9384 if (TREE_CODE (decl) == VAR_DECL)
9385 {
9386 /* If a variable has a forced alignment to < 2 bytes, mark it
9387 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9388 operand. */
9389 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9390 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9391 if (!DECL_SIZE (decl)
9392 || !DECL_ALIGN (decl)
9393 || !host_integerp (DECL_SIZE (decl), 0)
9394 || (DECL_ALIGN (decl) <= 64
9395 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9396 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9397 }
9398
9399 /* Literal pool references don't have a decl so they are handled
9400 differently here. We rely on the information in the MEM_ALIGN
9401 entry to decide upon natural alignment. */
9402 if (MEM_P (rtl)
9403 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9404 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9405 && (MEM_ALIGN (rtl) == 0
9406 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9407 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9408 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9409 }
9410
9411 /* Output thunk to FILE that implements a C++ virtual function call (with
9412 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9413 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9414 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9415 relative to the resulting this pointer. */
9416
9417 static void
9418 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9419 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9420 tree function)
9421 {
9422 rtx op[10];
9423 int nonlocal = 0;
9424
9425 /* Make sure unwind info is emitted for the thunk if needed. */
9426 final_start_function (emit_barrier (), file, 1);
9427
9428 /* Operand 0 is the target function. */
9429 op[0] = XEXP (DECL_RTL (function), 0);
9430 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9431 {
9432 nonlocal = 1;
9433 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9434 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9435 op[0] = gen_rtx_CONST (Pmode, op[0]);
9436 }
9437
9438 /* Operand 1 is the 'this' pointer. */
9439 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9440 op[1] = gen_rtx_REG (Pmode, 3);
9441 else
9442 op[1] = gen_rtx_REG (Pmode, 2);
9443
9444 /* Operand 2 is the delta. */
9445 op[2] = GEN_INT (delta);
9446
9447 /* Operand 3 is the vcall_offset. */
9448 op[3] = GEN_INT (vcall_offset);
9449
9450 /* Operand 4 is the temporary register. */
9451 op[4] = gen_rtx_REG (Pmode, 1);
9452
9453 /* Operands 5 to 8 can be used as labels. */
9454 op[5] = NULL_RTX;
9455 op[6] = NULL_RTX;
9456 op[7] = NULL_RTX;
9457 op[8] = NULL_RTX;
9458
9459 /* Operand 9 can be used for temporary register. */
9460 op[9] = NULL_RTX;
9461
9462 /* Generate code. */
9463 if (TARGET_64BIT)
9464 {
9465 /* Setup literal pool pointer if required. */
9466 if ((!DISP_IN_RANGE (delta)
9467 && !CONST_OK_FOR_K (delta)
9468 && !CONST_OK_FOR_Os (delta))
9469 || (!DISP_IN_RANGE (vcall_offset)
9470 && !CONST_OK_FOR_K (vcall_offset)
9471 && !CONST_OK_FOR_Os (vcall_offset)))
9472 {
9473 op[5] = gen_label_rtx ();
9474 output_asm_insn ("larl\t%4,%5", op);
9475 }
9476
9477 /* Add DELTA to this pointer. */
9478 if (delta)
9479 {
9480 if (CONST_OK_FOR_J (delta))
9481 output_asm_insn ("la\t%1,%2(%1)", op);
9482 else if (DISP_IN_RANGE (delta))
9483 output_asm_insn ("lay\t%1,%2(%1)", op);
9484 else if (CONST_OK_FOR_K (delta))
9485 output_asm_insn ("aghi\t%1,%2", op);
9486 else if (CONST_OK_FOR_Os (delta))
9487 output_asm_insn ("agfi\t%1,%2", op);
9488 else
9489 {
9490 op[6] = gen_label_rtx ();
9491 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9492 }
9493 }
9494
9495 /* Perform vcall adjustment. */
9496 if (vcall_offset)
9497 {
9498 if (DISP_IN_RANGE (vcall_offset))
9499 {
9500 output_asm_insn ("lg\t%4,0(%1)", op);
9501 output_asm_insn ("ag\t%1,%3(%4)", op);
9502 }
9503 else if (CONST_OK_FOR_K (vcall_offset))
9504 {
9505 output_asm_insn ("lghi\t%4,%3", op);
9506 output_asm_insn ("ag\t%4,0(%1)", op);
9507 output_asm_insn ("ag\t%1,0(%4)", op);
9508 }
9509 else if (CONST_OK_FOR_Os (vcall_offset))
9510 {
9511 output_asm_insn ("lgfi\t%4,%3", op);
9512 output_asm_insn ("ag\t%4,0(%1)", op);
9513 output_asm_insn ("ag\t%1,0(%4)", op);
9514 }
9515 else
9516 {
9517 op[7] = gen_label_rtx ();
9518 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9519 output_asm_insn ("ag\t%4,0(%1)", op);
9520 output_asm_insn ("ag\t%1,0(%4)", op);
9521 }
9522 }
9523
9524 /* Jump to target. */
9525 output_asm_insn ("jg\t%0", op);
9526
9527 /* Output literal pool if required. */
9528 if (op[5])
9529 {
9530 output_asm_insn (".align\t4", op);
9531 targetm.asm_out.internal_label (file, "L",
9532 CODE_LABEL_NUMBER (op[5]));
9533 }
9534 if (op[6])
9535 {
9536 targetm.asm_out.internal_label (file, "L",
9537 CODE_LABEL_NUMBER (op[6]));
9538 output_asm_insn (".long\t%2", op);
9539 }
9540 if (op[7])
9541 {
9542 targetm.asm_out.internal_label (file, "L",
9543 CODE_LABEL_NUMBER (op[7]));
9544 output_asm_insn (".long\t%3", op);
9545 }
9546 }
9547 else
9548 {
9549 /* Setup base pointer if required. */
9550 if (!vcall_offset
9551 || (!DISP_IN_RANGE (delta)
9552 && !CONST_OK_FOR_K (delta)
9553 && !CONST_OK_FOR_Os (delta))
9554 || (!DISP_IN_RANGE (delta)
9555 && !CONST_OK_FOR_K (vcall_offset)
9556 && !CONST_OK_FOR_Os (vcall_offset)))
9557 {
9558 op[5] = gen_label_rtx ();
9559 output_asm_insn ("basr\t%4,0", op);
9560 targetm.asm_out.internal_label (file, "L",
9561 CODE_LABEL_NUMBER (op[5]));
9562 }
9563
9564 /* Add DELTA to this pointer. */
9565 if (delta)
9566 {
9567 if (CONST_OK_FOR_J (delta))
9568 output_asm_insn ("la\t%1,%2(%1)", op);
9569 else if (DISP_IN_RANGE (delta))
9570 output_asm_insn ("lay\t%1,%2(%1)", op);
9571 else if (CONST_OK_FOR_K (delta))
9572 output_asm_insn ("ahi\t%1,%2", op);
9573 else if (CONST_OK_FOR_Os (delta))
9574 output_asm_insn ("afi\t%1,%2", op);
9575 else
9576 {
9577 op[6] = gen_label_rtx ();
9578 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9579 }
9580 }
9581
9582 /* Perform vcall adjustment. */
9583 if (vcall_offset)
9584 {
9585 if (CONST_OK_FOR_J (vcall_offset))
9586 {
9587 output_asm_insn ("l\t%4,0(%1)", op);
9588 output_asm_insn ("a\t%1,%3(%4)", op);
9589 }
9590 else if (DISP_IN_RANGE (vcall_offset))
9591 {
9592 output_asm_insn ("l\t%4,0(%1)", op);
9593 output_asm_insn ("ay\t%1,%3(%4)", op);
9594 }
9595 else if (CONST_OK_FOR_K (vcall_offset))
9596 {
9597 output_asm_insn ("lhi\t%4,%3", op);
9598 output_asm_insn ("a\t%4,0(%1)", op);
9599 output_asm_insn ("a\t%1,0(%4)", op);
9600 }
9601 else if (CONST_OK_FOR_Os (vcall_offset))
9602 {
9603 output_asm_insn ("iilf\t%4,%3", op);
9604 output_asm_insn ("a\t%4,0(%1)", op);
9605 output_asm_insn ("a\t%1,0(%4)", op);
9606 }
9607 else
9608 {
9609 op[7] = gen_label_rtx ();
9610 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9611 output_asm_insn ("a\t%4,0(%1)", op);
9612 output_asm_insn ("a\t%1,0(%4)", op);
9613 }
9614
9615 /* We had to clobber the base pointer register.
9616 Re-setup the base pointer (with a different base). */
9617 op[5] = gen_label_rtx ();
9618 output_asm_insn ("basr\t%4,0", op);
9619 targetm.asm_out.internal_label (file, "L",
9620 CODE_LABEL_NUMBER (op[5]));
9621 }
9622
9623 /* Jump to target. */
9624 op[8] = gen_label_rtx ();
9625
9626 if (!flag_pic)
9627 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9628 else if (!nonlocal)
9629 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9630 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9631 else if (flag_pic == 1)
9632 {
9633 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9634 output_asm_insn ("l\t%4,%0(%4)", op);
9635 }
9636 else if (flag_pic == 2)
9637 {
9638 op[9] = gen_rtx_REG (Pmode, 0);
9639 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9640 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9641 output_asm_insn ("ar\t%4,%9", op);
9642 output_asm_insn ("l\t%4,0(%4)", op);
9643 }
9644
9645 output_asm_insn ("br\t%4", op);
9646
9647 /* Output literal pool. */
9648 output_asm_insn (".align\t4", op);
9649
9650 if (nonlocal && flag_pic == 2)
9651 output_asm_insn (".long\t%0", op);
9652 if (nonlocal)
9653 {
9654 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9655 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9656 }
9657
9658 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9659 if (!flag_pic)
9660 output_asm_insn (".long\t%0", op);
9661 else
9662 output_asm_insn (".long\t%0-%5", op);
9663
9664 if (op[6])
9665 {
9666 targetm.asm_out.internal_label (file, "L",
9667 CODE_LABEL_NUMBER (op[6]));
9668 output_asm_insn (".long\t%2", op);
9669 }
9670 if (op[7])
9671 {
9672 targetm.asm_out.internal_label (file, "L",
9673 CODE_LABEL_NUMBER (op[7]));
9674 output_asm_insn (".long\t%3", op);
9675 }
9676 }
9677 final_end_function ();
9678 }
9679
9680 static bool
9681 s390_valid_pointer_mode (enum machine_mode mode)
9682 {
9683 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9684 }
9685
9686 /* Checks whether the given CALL_EXPR would use a caller
9687 saved register. This is used to decide whether sibling call
9688 optimization could be performed on the respective function
9689 call. */
9690
9691 static bool
9692 s390_call_saved_register_used (tree call_expr)
9693 {
9694 CUMULATIVE_ARGS cum_v;
9695 cumulative_args_t cum;
9696 tree parameter;
9697 enum machine_mode mode;
9698 tree type;
9699 rtx parm_rtx;
9700 int reg, i;
9701
9702 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
9703 cum = pack_cumulative_args (&cum_v);
9704
9705 for (i = 0; i < call_expr_nargs (call_expr); i++)
9706 {
9707 parameter = CALL_EXPR_ARG (call_expr, i);
9708 gcc_assert (parameter);
9709
9710 /* For an undeclared variable passed as parameter we will get
9711 an ERROR_MARK node here. */
9712 if (TREE_CODE (parameter) == ERROR_MARK)
9713 return true;
9714
9715 type = TREE_TYPE (parameter);
9716 gcc_assert (type);
9717
9718 mode = TYPE_MODE (type);
9719 gcc_assert (mode);
9720
9721 if (pass_by_reference (&cum_v, mode, type, true))
9722 {
9723 mode = Pmode;
9724 type = build_pointer_type (type);
9725 }
9726
9727 parm_rtx = s390_function_arg (cum, mode, type, 0);
9728
9729 s390_function_arg_advance (cum, mode, type, 0);
9730
9731 if (!parm_rtx)
9732 continue;
9733
9734 if (REG_P (parm_rtx))
9735 {
9736 for (reg = 0;
9737 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9738 reg++)
9739 if (!call_used_regs[reg + REGNO (parm_rtx)])
9740 return true;
9741 }
9742
9743 if (GET_CODE (parm_rtx) == PARALLEL)
9744 {
9745 int i;
9746
9747 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9748 {
9749 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9750
9751 gcc_assert (REG_P (r));
9752
9753 for (reg = 0;
9754 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9755 reg++)
9756 if (!call_used_regs[reg + REGNO (r)])
9757 return true;
9758 }
9759 }
9760
9761 }
9762 return false;
9763 }
9764
9765 /* Return true if the given call expression can be
9766 turned into a sibling call.
9767 DECL holds the declaration of the function to be called whereas
9768 EXP is the call expression itself. */
9769
9770 static bool
9771 s390_function_ok_for_sibcall (tree decl, tree exp)
9772 {
9773 /* The TPF epilogue uses register 1. */
9774 if (TARGET_TPF_PROFILING)
9775 return false;
9776
9777 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9778 which would have to be restored before the sibcall. */
9779 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9780 return false;
9781
9782 /* Register 6 on s390 is available as an argument register but unfortunately
9783 "caller saved". This makes functions needing this register for arguments
9784 not suitable for sibcalls. */
9785 return !s390_call_saved_register_used (exp);
9786 }
9787
9788 /* Return the fixed registers used for condition codes. */
9789
9790 static bool
9791 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9792 {
9793 *p1 = CC_REGNUM;
9794 *p2 = INVALID_REGNUM;
9795
9796 return true;
9797 }
9798
9799 /* This function is used by the call expanders of the machine description.
9800 It emits the call insn itself together with the necessary operations
9801 to adjust the target address and returns the emitted insn.
9802 ADDR_LOCATION is the target address rtx
9803 TLS_CALL the location of the thread-local symbol
9804 RESULT_REG the register where the result of the call should be stored
9805 RETADDR_REG the register where the return address should be stored
9806 If this parameter is NULL_RTX the call is considered
9807 to be a sibling call. */
9808
9809 rtx
9810 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9811 rtx retaddr_reg)
9812 {
9813 bool plt_call = false;
9814 rtx insn;
9815 rtx call;
9816 rtx clobber;
9817 rtvec vec;
9818
9819 /* Direct function calls need special treatment. */
9820 if (GET_CODE (addr_location) == SYMBOL_REF)
9821 {
9822 /* When calling a global routine in PIC mode, we must
9823 replace the symbol itself with the PLT stub. */
9824 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9825 {
9826 if (retaddr_reg != NULL_RTX)
9827 {
9828 addr_location = gen_rtx_UNSPEC (Pmode,
9829 gen_rtvec (1, addr_location),
9830 UNSPEC_PLT);
9831 addr_location = gen_rtx_CONST (Pmode, addr_location);
9832 plt_call = true;
9833 }
9834 else
9835 /* For -fpic code the PLT entries might use r12 which is
9836 call-saved. Therefore we cannot do a sibcall when
9837 calling directly using a symbol ref. When reaching
9838 this point we decided (in s390_function_ok_for_sibcall)
9839 to do a sibcall for a function pointer but one of the
9840 optimizers was able to get rid of the function pointer
9841 by propagating the symbol ref into the call. This
9842 optimization is illegal for S/390 so we turn the direct
9843 call into a indirect call again. */
9844 addr_location = force_reg (Pmode, addr_location);
9845 }
9846
9847 /* Unless we can use the bras(l) insn, force the
9848 routine address into a register. */
9849 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9850 {
9851 if (flag_pic)
9852 addr_location = legitimize_pic_address (addr_location, 0);
9853 else
9854 addr_location = force_reg (Pmode, addr_location);
9855 }
9856 }
9857
9858 /* If it is already an indirect call or the code above moved the
9859 SYMBOL_REF to somewhere else make sure the address can be found in
9860 register 1. */
9861 if (retaddr_reg == NULL_RTX
9862 && GET_CODE (addr_location) != SYMBOL_REF
9863 && !plt_call)
9864 {
9865 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9866 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9867 }
9868
9869 addr_location = gen_rtx_MEM (QImode, addr_location);
9870 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9871
9872 if (result_reg != NULL_RTX)
9873 call = gen_rtx_SET (VOIDmode, result_reg, call);
9874
9875 if (retaddr_reg != NULL_RTX)
9876 {
9877 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9878
9879 if (tls_call != NULL_RTX)
9880 vec = gen_rtvec (3, call, clobber,
9881 gen_rtx_USE (VOIDmode, tls_call));
9882 else
9883 vec = gen_rtvec (2, call, clobber);
9884
9885 call = gen_rtx_PARALLEL (VOIDmode, vec);
9886 }
9887
9888 insn = emit_call_insn (call);
9889
9890 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9891 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9892 {
9893 /* s390_function_ok_for_sibcall should
9894 have denied sibcalls in this case. */
9895 gcc_assert (retaddr_reg != NULL_RTX);
9896 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
9897 }
9898 return insn;
9899 }
9900
9901 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9902
9903 static void
9904 s390_conditional_register_usage (void)
9905 {
9906 int i;
9907
9908 if (flag_pic)
9909 {
9910 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9911 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9912 }
9913 if (TARGET_CPU_ZARCH)
9914 {
9915 fixed_regs[BASE_REGNUM] = 0;
9916 call_used_regs[BASE_REGNUM] = 0;
9917 fixed_regs[RETURN_REGNUM] = 0;
9918 call_used_regs[RETURN_REGNUM] = 0;
9919 }
9920 if (TARGET_64BIT)
9921 {
9922 for (i = 24; i < 32; i++)
9923 call_used_regs[i] = call_really_used_regs[i] = 0;
9924 }
9925 else
9926 {
9927 for (i = 18; i < 20; i++)
9928 call_used_regs[i] = call_really_used_regs[i] = 0;
9929 }
9930
9931 if (TARGET_SOFT_FLOAT)
9932 {
9933 for (i = 16; i < 32; i++)
9934 call_used_regs[i] = fixed_regs[i] = 1;
9935 }
9936 }
9937
9938 /* Corresponding function to eh_return expander. */
9939
9940 static GTY(()) rtx s390_tpf_eh_return_symbol;
9941 void
9942 s390_emit_tpf_eh_return (rtx target)
9943 {
9944 rtx insn, reg;
9945
9946 if (!s390_tpf_eh_return_symbol)
9947 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9948
9949 reg = gen_rtx_REG (Pmode, 2);
9950
9951 emit_move_insn (reg, target);
9952 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9953 gen_rtx_REG (Pmode, RETURN_REGNUM));
9954 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9955
9956 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9957 }
9958
9959 /* Rework the prologue/epilogue to avoid saving/restoring
9960 registers unnecessarily. */
9961
9962 static void
9963 s390_optimize_prologue (void)
9964 {
9965 rtx insn, new_insn, next_insn;
9966
9967 /* Do a final recompute of the frame-related data. */
9968
9969 s390_update_frame_layout ();
9970
9971 /* If all special registers are in fact used, there's nothing we
9972 can do, so no point in walking the insn list. */
9973
9974 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9975 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9976 && (TARGET_CPU_ZARCH
9977 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9978 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9979 return;
9980
9981 /* Search for prologue/epilogue insns and replace them. */
9982
9983 for (insn = get_insns (); insn; insn = next_insn)
9984 {
9985 int first, last, off;
9986 rtx set, base, offset;
9987
9988 next_insn = NEXT_INSN (insn);
9989
9990 if (GET_CODE (insn) != INSN)
9991 continue;
9992
9993 if (GET_CODE (PATTERN (insn)) == PARALLEL
9994 && store_multiple_operation (PATTERN (insn), VOIDmode))
9995 {
9996 set = XVECEXP (PATTERN (insn), 0, 0);
9997 first = REGNO (SET_SRC (set));
9998 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9999 offset = const0_rtx;
10000 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10001 off = INTVAL (offset);
10002
10003 if (GET_CODE (base) != REG || off < 0)
10004 continue;
10005 if (cfun_frame_layout.first_save_gpr != -1
10006 && (cfun_frame_layout.first_save_gpr < first
10007 || cfun_frame_layout.last_save_gpr > last))
10008 continue;
10009 if (REGNO (base) != STACK_POINTER_REGNUM
10010 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10011 continue;
10012 if (first > BASE_REGNUM || last < BASE_REGNUM)
10013 continue;
10014
10015 if (cfun_frame_layout.first_save_gpr != -1)
10016 {
10017 new_insn = save_gprs (base,
10018 off + (cfun_frame_layout.first_save_gpr
10019 - first) * UNITS_PER_LONG,
10020 cfun_frame_layout.first_save_gpr,
10021 cfun_frame_layout.last_save_gpr);
10022 new_insn = emit_insn_before (new_insn, insn);
10023 INSN_ADDRESSES_NEW (new_insn, -1);
10024 }
10025
10026 remove_insn (insn);
10027 continue;
10028 }
10029
10030 if (cfun_frame_layout.first_save_gpr == -1
10031 && GET_CODE (PATTERN (insn)) == SET
10032 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10033 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10034 || (!TARGET_CPU_ZARCH
10035 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10036 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10037 {
10038 set = PATTERN (insn);
10039 first = REGNO (SET_SRC (set));
10040 offset = const0_rtx;
10041 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10042 off = INTVAL (offset);
10043
10044 if (GET_CODE (base) != REG || off < 0)
10045 continue;
10046 if (REGNO (base) != STACK_POINTER_REGNUM
10047 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10048 continue;
10049
10050 remove_insn (insn);
10051 continue;
10052 }
10053
10054 if (GET_CODE (PATTERN (insn)) == PARALLEL
10055 && load_multiple_operation (PATTERN (insn), VOIDmode))
10056 {
10057 set = XVECEXP (PATTERN (insn), 0, 0);
10058 first = REGNO (SET_DEST (set));
10059 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10060 offset = const0_rtx;
10061 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10062 off = INTVAL (offset);
10063
10064 if (GET_CODE (base) != REG || off < 0)
10065 continue;
10066 if (cfun_frame_layout.first_restore_gpr != -1
10067 && (cfun_frame_layout.first_restore_gpr < first
10068 || cfun_frame_layout.last_restore_gpr > last))
10069 continue;
10070 if (REGNO (base) != STACK_POINTER_REGNUM
10071 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10072 continue;
10073 if (first > BASE_REGNUM || last < BASE_REGNUM)
10074 continue;
10075
10076 if (cfun_frame_layout.first_restore_gpr != -1)
10077 {
10078 new_insn = restore_gprs (base,
10079 off + (cfun_frame_layout.first_restore_gpr
10080 - first) * UNITS_PER_LONG,
10081 cfun_frame_layout.first_restore_gpr,
10082 cfun_frame_layout.last_restore_gpr);
10083 new_insn = emit_insn_before (new_insn, insn);
10084 INSN_ADDRESSES_NEW (new_insn, -1);
10085 }
10086
10087 remove_insn (insn);
10088 continue;
10089 }
10090
10091 if (cfun_frame_layout.first_restore_gpr == -1
10092 && GET_CODE (PATTERN (insn)) == SET
10093 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10094 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10095 || (!TARGET_CPU_ZARCH
10096 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10097 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10098 {
10099 set = PATTERN (insn);
10100 first = REGNO (SET_DEST (set));
10101 offset = const0_rtx;
10102 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10103 off = INTVAL (offset);
10104
10105 if (GET_CODE (base) != REG || off < 0)
10106 continue;
10107 if (REGNO (base) != STACK_POINTER_REGNUM
10108 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10109 continue;
10110
10111 remove_insn (insn);
10112 continue;
10113 }
10114 }
10115 }
10116
10117 /* On z10 and later the dynamic branch prediction must see the
10118 backward jump within a certain windows. If not it falls back to
10119 the static prediction. This function rearranges the loop backward
10120 branch in a way which makes the static prediction always correct.
10121 The function returns true if it added an instruction. */
10122 static bool
10123 s390_fix_long_loop_prediction (rtx insn)
10124 {
10125 rtx set = single_set (insn);
10126 rtx code_label, label_ref, new_label;
10127 rtx uncond_jump;
10128 rtx cur_insn;
10129 rtx tmp;
10130 int distance;
10131
10132 /* This will exclude branch on count and branch on index patterns
10133 since these are correctly statically predicted. */
10134 if (!set
10135 || SET_DEST (set) != pc_rtx
10136 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10137 return false;
10138
10139 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10140 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10141
10142 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10143
10144 code_label = XEXP (label_ref, 0);
10145
10146 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10147 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10148 || (INSN_ADDRESSES (INSN_UID (insn))
10149 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10150 return false;
10151
10152 for (distance = 0, cur_insn = PREV_INSN (insn);
10153 distance < PREDICT_DISTANCE - 6;
10154 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10155 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10156 return false;
10157
10158 new_label = gen_label_rtx ();
10159 uncond_jump = emit_jump_insn_after (
10160 gen_rtx_SET (VOIDmode, pc_rtx,
10161 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10162 insn);
10163 emit_label_after (new_label, uncond_jump);
10164
10165 tmp = XEXP (SET_SRC (set), 1);
10166 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10167 XEXP (SET_SRC (set), 2) = tmp;
10168 INSN_CODE (insn) = -1;
10169
10170 XEXP (label_ref, 0) = new_label;
10171 JUMP_LABEL (insn) = new_label;
10172 JUMP_LABEL (uncond_jump) = code_label;
10173
10174 return true;
10175 }
10176
10177 /* Returns 1 if INSN reads the value of REG for purposes not related
10178 to addressing of memory, and 0 otherwise. */
10179 static int
10180 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10181 {
10182 return reg_referenced_p (reg, PATTERN (insn))
10183 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10184 }
10185
10186 /* Starting from INSN find_cond_jump looks downwards in the insn
10187 stream for a single jump insn which is the last user of the
10188 condition code set in INSN. */
10189 static rtx
10190 find_cond_jump (rtx insn)
10191 {
10192 for (; insn; insn = NEXT_INSN (insn))
10193 {
10194 rtx ite, cc;
10195
10196 if (LABEL_P (insn))
10197 break;
10198
10199 if (!JUMP_P (insn))
10200 {
10201 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10202 break;
10203 continue;
10204 }
10205
10206 /* This will be triggered by a return. */
10207 if (GET_CODE (PATTERN (insn)) != SET)
10208 break;
10209
10210 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10211 ite = SET_SRC (PATTERN (insn));
10212
10213 if (GET_CODE (ite) != IF_THEN_ELSE)
10214 break;
10215
10216 cc = XEXP (XEXP (ite, 0), 0);
10217 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10218 break;
10219
10220 if (find_reg_note (insn, REG_DEAD, cc))
10221 return insn;
10222 break;
10223 }
10224
10225 return NULL_RTX;
10226 }
10227
10228 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10229 the semantics does not change. If NULL_RTX is passed as COND the
10230 function tries to find the conditional jump starting with INSN. */
10231 static void
10232 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10233 {
10234 rtx tmp = *op0;
10235
10236 if (cond == NULL_RTX)
10237 {
10238 rtx jump = find_cond_jump (NEXT_INSN (insn));
10239 jump = jump ? single_set (jump) : NULL_RTX;
10240
10241 if (jump == NULL_RTX)
10242 return;
10243
10244 cond = XEXP (XEXP (jump, 1), 0);
10245 }
10246
10247 *op0 = *op1;
10248 *op1 = tmp;
10249 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10250 }
10251
10252 /* On z10, instructions of the compare-and-branch family have the
10253 property to access the register occurring as second operand with
10254 its bits complemented. If such a compare is grouped with a second
10255 instruction that accesses the same register non-complemented, and
10256 if that register's value is delivered via a bypass, then the
10257 pipeline recycles, thereby causing significant performance decline.
10258 This function locates such situations and exchanges the two
10259 operands of the compare. The function return true whenever it
10260 added an insn. */
10261 static bool
10262 s390_z10_optimize_cmp (rtx insn)
10263 {
10264 rtx prev_insn, next_insn;
10265 bool insn_added_p = false;
10266 rtx cond, *op0, *op1;
10267
10268 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10269 {
10270 /* Handle compare and branch and branch on count
10271 instructions. */
10272 rtx pattern = single_set (insn);
10273
10274 if (!pattern
10275 || SET_DEST (pattern) != pc_rtx
10276 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10277 return false;
10278
10279 cond = XEXP (SET_SRC (pattern), 0);
10280 op0 = &XEXP (cond, 0);
10281 op1 = &XEXP (cond, 1);
10282 }
10283 else if (GET_CODE (PATTERN (insn)) == SET)
10284 {
10285 rtx src, dest;
10286
10287 /* Handle normal compare instructions. */
10288 src = SET_SRC (PATTERN (insn));
10289 dest = SET_DEST (PATTERN (insn));
10290
10291 if (!REG_P (dest)
10292 || !CC_REGNO_P (REGNO (dest))
10293 || GET_CODE (src) != COMPARE)
10294 return false;
10295
10296 /* s390_swap_cmp will try to find the conditional
10297 jump when passing NULL_RTX as condition. */
10298 cond = NULL_RTX;
10299 op0 = &XEXP (src, 0);
10300 op1 = &XEXP (src, 1);
10301 }
10302 else
10303 return false;
10304
10305 if (!REG_P (*op0) || !REG_P (*op1))
10306 return false;
10307
10308 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10309 return false;
10310
10311 /* Swap the COMPARE arguments and its mask if there is a
10312 conflicting access in the previous insn. */
10313 prev_insn = prev_active_insn (insn);
10314 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10315 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10316 s390_swap_cmp (cond, op0, op1, insn);
10317
10318 /* Check if there is a conflict with the next insn. If there
10319 was no conflict with the previous insn, then swap the
10320 COMPARE arguments and its mask. If we already swapped
10321 the operands, or if swapping them would cause a conflict
10322 with the previous insn, issue a NOP after the COMPARE in
10323 order to separate the two instuctions. */
10324 next_insn = next_active_insn (insn);
10325 if (next_insn != NULL_RTX && INSN_P (next_insn)
10326 && s390_non_addr_reg_read_p (*op1, next_insn))
10327 {
10328 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10329 && s390_non_addr_reg_read_p (*op0, prev_insn))
10330 {
10331 if (REGNO (*op1) == 0)
10332 emit_insn_after (gen_nop1 (), insn);
10333 else
10334 emit_insn_after (gen_nop (), insn);
10335 insn_added_p = true;
10336 }
10337 else
10338 s390_swap_cmp (cond, op0, op1, insn);
10339 }
10340 return insn_added_p;
10341 }
10342
10343 /* Perform machine-dependent processing. */
10344
10345 static void
10346 s390_reorg (void)
10347 {
10348 bool pool_overflow = false;
10349
10350 /* Make sure all splits have been performed; splits after
10351 machine_dependent_reorg might confuse insn length counts. */
10352 split_all_insns_noflow ();
10353
10354 /* Install the main literal pool and the associated base
10355 register load insns.
10356
10357 In addition, there are two problematic situations we need
10358 to correct:
10359
10360 - the literal pool might be > 4096 bytes in size, so that
10361 some of its elements cannot be directly accessed
10362
10363 - a branch target might be > 64K away from the branch, so that
10364 it is not possible to use a PC-relative instruction.
10365
10366 To fix those, we split the single literal pool into multiple
10367 pool chunks, reloading the pool base register at various
10368 points throughout the function to ensure it always points to
10369 the pool chunk the following code expects, and / or replace
10370 PC-relative branches by absolute branches.
10371
10372 However, the two problems are interdependent: splitting the
10373 literal pool can move a branch further away from its target,
10374 causing the 64K limit to overflow, and on the other hand,
10375 replacing a PC-relative branch by an absolute branch means
10376 we need to put the branch target address into the literal
10377 pool, possibly causing it to overflow.
10378
10379 So, we loop trying to fix up both problems until we manage
10380 to satisfy both conditions at the same time. Note that the
10381 loop is guaranteed to terminate as every pass of the loop
10382 strictly decreases the total number of PC-relative branches
10383 in the function. (This is not completely true as there
10384 might be branch-over-pool insns introduced by chunkify_start.
10385 Those never need to be split however.) */
10386
10387 for (;;)
10388 {
10389 struct constant_pool *pool = NULL;
10390
10391 /* Collect the literal pool. */
10392 if (!pool_overflow)
10393 {
10394 pool = s390_mainpool_start ();
10395 if (!pool)
10396 pool_overflow = true;
10397 }
10398
10399 /* If literal pool overflowed, start to chunkify it. */
10400 if (pool_overflow)
10401 pool = s390_chunkify_start ();
10402
10403 /* Split out-of-range branches. If this has created new
10404 literal pool entries, cancel current chunk list and
10405 recompute it. zSeries machines have large branch
10406 instructions, so we never need to split a branch. */
10407 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10408 {
10409 if (pool_overflow)
10410 s390_chunkify_cancel (pool);
10411 else
10412 s390_mainpool_cancel (pool);
10413
10414 continue;
10415 }
10416
10417 /* If we made it up to here, both conditions are satisfied.
10418 Finish up literal pool related changes. */
10419 if (pool_overflow)
10420 s390_chunkify_finish (pool);
10421 else
10422 s390_mainpool_finish (pool);
10423
10424 /* We're done splitting branches. */
10425 cfun->machine->split_branches_pending_p = false;
10426 break;
10427 }
10428
10429 /* Generate out-of-pool execute target insns. */
10430 if (TARGET_CPU_ZARCH)
10431 {
10432 rtx insn, label, target;
10433
10434 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10435 {
10436 label = s390_execute_label (insn);
10437 if (!label)
10438 continue;
10439
10440 gcc_assert (label != const0_rtx);
10441
10442 target = emit_label (XEXP (label, 0));
10443 INSN_ADDRESSES_NEW (target, -1);
10444
10445 target = emit_insn (s390_execute_target (insn));
10446 INSN_ADDRESSES_NEW (target, -1);
10447 }
10448 }
10449
10450 /* Try to optimize prologue and epilogue further. */
10451 s390_optimize_prologue ();
10452
10453 /* Walk over the insns and do some >=z10 specific changes. */
10454 if (s390_tune == PROCESSOR_2097_Z10
10455 || s390_tune == PROCESSOR_2817_Z196)
10456 {
10457 rtx insn;
10458 bool insn_added_p = false;
10459
10460 /* The insn lengths and addresses have to be up to date for the
10461 following manipulations. */
10462 shorten_branches (get_insns ());
10463
10464 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10465 {
10466 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10467 continue;
10468
10469 if (JUMP_P (insn))
10470 insn_added_p |= s390_fix_long_loop_prediction (insn);
10471
10472 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10473 || GET_CODE (PATTERN (insn)) == SET)
10474 && s390_tune == PROCESSOR_2097_Z10)
10475 insn_added_p |= s390_z10_optimize_cmp (insn);
10476 }
10477
10478 /* Adjust branches if we added new instructions. */
10479 if (insn_added_p)
10480 shorten_branches (get_insns ());
10481 }
10482 }
10483
10484 /* Return true if INSN is a fp load insn writing register REGNO. */
10485 static inline bool
10486 s390_fpload_toreg (rtx insn, unsigned int regno)
10487 {
10488 rtx set;
10489 enum attr_type flag = s390_safe_attr_type (insn);
10490
10491 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10492 return false;
10493
10494 set = single_set (insn);
10495
10496 if (set == NULL_RTX)
10497 return false;
10498
10499 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10500 return false;
10501
10502 if (REGNO (SET_DEST (set)) != regno)
10503 return false;
10504
10505 return true;
10506 }
10507
10508 /* This value describes the distance to be avoided between an
10509 aritmetic fp instruction and an fp load writing the same register.
10510 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10511 fine but the exact value has to be avoided. Otherwise the FP
10512 pipeline will throw an exception causing a major penalty. */
10513 #define Z10_EARLYLOAD_DISTANCE 7
10514
10515 /* Rearrange the ready list in order to avoid the situation described
10516 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10517 moved to the very end of the ready list. */
10518 static void
10519 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10520 {
10521 unsigned int regno;
10522 int nready = *nready_p;
10523 rtx tmp;
10524 int i;
10525 rtx insn;
10526 rtx set;
10527 enum attr_type flag;
10528 int distance;
10529
10530 /* Skip DISTANCE - 1 active insns. */
10531 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10532 distance > 0 && insn != NULL_RTX;
10533 distance--, insn = prev_active_insn (insn))
10534 if (CALL_P (insn) || JUMP_P (insn))
10535 return;
10536
10537 if (insn == NULL_RTX)
10538 return;
10539
10540 set = single_set (insn);
10541
10542 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10543 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10544 return;
10545
10546 flag = s390_safe_attr_type (insn);
10547
10548 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10549 return;
10550
10551 regno = REGNO (SET_DEST (set));
10552 i = nready - 1;
10553
10554 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10555 i--;
10556
10557 if (!i)
10558 return;
10559
10560 tmp = ready[i];
10561 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10562 ready[0] = tmp;
10563 }
10564
10565 /* This function is called via hook TARGET_SCHED_REORDER before
10566 issuing one insn from list READY which contains *NREADYP entries.
10567 For target z10 it reorders load instructions to avoid early load
10568 conflicts in the floating point pipeline */
10569 static int
10570 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10571 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10572 {
10573 if (s390_tune == PROCESSOR_2097_Z10)
10574 if (reload_completed && *nreadyp > 1)
10575 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10576
10577 return s390_issue_rate ();
10578 }
10579
10580 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10581 the scheduler has issued INSN. It stores the last issued insn into
10582 last_scheduled_insn in order to make it available for
10583 s390_sched_reorder. */
10584 static int
10585 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10586 int verbose ATTRIBUTE_UNUSED,
10587 rtx insn, int more)
10588 {
10589 last_scheduled_insn = insn;
10590
10591 if (GET_CODE (PATTERN (insn)) != USE
10592 && GET_CODE (PATTERN (insn)) != CLOBBER)
10593 return more - 1;
10594 else
10595 return more;
10596 }
10597
10598 static void
10599 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10600 int verbose ATTRIBUTE_UNUSED,
10601 int max_ready ATTRIBUTE_UNUSED)
10602 {
10603 last_scheduled_insn = NULL_RTX;
10604 }
10605
10606 /* This function checks the whole of insn X for memory references. The
10607 function always returns zero because the framework it is called
10608 from would stop recursively analyzing the insn upon a return value
10609 other than zero. The real result of this function is updating
10610 counter variable MEM_COUNT. */
10611 static int
10612 check_dpu (rtx *x, unsigned *mem_count)
10613 {
10614 if (*x != NULL_RTX && MEM_P (*x))
10615 (*mem_count)++;
10616 return 0;
10617 }
10618
10619 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10620 a new number struct loop *loop should be unrolled if tuned for cpus with
10621 a built-in stride prefetcher.
10622 The loop is analyzed for memory accesses by calling check_dpu for
10623 each rtx of the loop. Depending on the loop_depth and the amount of
10624 memory accesses a new number <=nunroll is returned to improve the
10625 behaviour of the hardware prefetch unit. */
10626 static unsigned
10627 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10628 {
10629 basic_block *bbs;
10630 rtx insn;
10631 unsigned i;
10632 unsigned mem_count = 0;
10633
10634 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10635 return nunroll;
10636
10637 /* Count the number of memory references within the loop body. */
10638 bbs = get_loop_body (loop);
10639 for (i = 0; i < loop->num_nodes; i++)
10640 {
10641 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10642 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10643 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10644 }
10645 free (bbs);
10646
10647 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10648 if (mem_count == 0)
10649 return nunroll;
10650
10651 switch (loop_depth(loop))
10652 {
10653 case 1:
10654 return MIN (nunroll, 28 / mem_count);
10655 case 2:
10656 return MIN (nunroll, 22 / mem_count);
10657 default:
10658 return MIN (nunroll, 16 / mem_count);
10659 }
10660 }
10661
10662 /* Initialize GCC target structure. */
10663
10664 #undef TARGET_ASM_ALIGNED_HI_OP
10665 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10666 #undef TARGET_ASM_ALIGNED_DI_OP
10667 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10668 #undef TARGET_ASM_INTEGER
10669 #define TARGET_ASM_INTEGER s390_assemble_integer
10670
10671 #undef TARGET_ASM_OPEN_PAREN
10672 #define TARGET_ASM_OPEN_PAREN ""
10673
10674 #undef TARGET_ASM_CLOSE_PAREN
10675 #define TARGET_ASM_CLOSE_PAREN ""
10676
10677 #undef TARGET_OPTION_OVERRIDE
10678 #define TARGET_OPTION_OVERRIDE s390_option_override
10679
10680 #undef TARGET_ENCODE_SECTION_INFO
10681 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10682
10683 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10684 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10685
10686 #ifdef HAVE_AS_TLS
10687 #undef TARGET_HAVE_TLS
10688 #define TARGET_HAVE_TLS true
10689 #endif
10690 #undef TARGET_CANNOT_FORCE_CONST_MEM
10691 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10692
10693 #undef TARGET_DELEGITIMIZE_ADDRESS
10694 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10695
10696 #undef TARGET_LEGITIMIZE_ADDRESS
10697 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10698
10699 #undef TARGET_RETURN_IN_MEMORY
10700 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10701
10702 #undef TARGET_INIT_BUILTINS
10703 #define TARGET_INIT_BUILTINS s390_init_builtins
10704 #undef TARGET_EXPAND_BUILTIN
10705 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10706
10707 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10708 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10709
10710 #undef TARGET_ASM_OUTPUT_MI_THUNK
10711 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10712 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10713 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10714
10715 #undef TARGET_SCHED_ADJUST_PRIORITY
10716 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10717 #undef TARGET_SCHED_ISSUE_RATE
10718 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10719 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10720 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10721
10722 #undef TARGET_SCHED_VARIABLE_ISSUE
10723 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10724 #undef TARGET_SCHED_REORDER
10725 #define TARGET_SCHED_REORDER s390_sched_reorder
10726 #undef TARGET_SCHED_INIT
10727 #define TARGET_SCHED_INIT s390_sched_init
10728
10729 #undef TARGET_CANNOT_COPY_INSN_P
10730 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10731 #undef TARGET_RTX_COSTS
10732 #define TARGET_RTX_COSTS s390_rtx_costs
10733 #undef TARGET_ADDRESS_COST
10734 #define TARGET_ADDRESS_COST s390_address_cost
10735 #undef TARGET_REGISTER_MOVE_COST
10736 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10737 #undef TARGET_MEMORY_MOVE_COST
10738 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10739
10740 #undef TARGET_MACHINE_DEPENDENT_REORG
10741 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10742
10743 #undef TARGET_VALID_POINTER_MODE
10744 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10745
10746 #undef TARGET_BUILD_BUILTIN_VA_LIST
10747 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10748 #undef TARGET_EXPAND_BUILTIN_VA_START
10749 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10750 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10751 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10752
10753 #undef TARGET_PROMOTE_FUNCTION_MODE
10754 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10755 #undef TARGET_PASS_BY_REFERENCE
10756 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10757
10758 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10759 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10760 #undef TARGET_FUNCTION_ARG
10761 #define TARGET_FUNCTION_ARG s390_function_arg
10762 #undef TARGET_FUNCTION_ARG_ADVANCE
10763 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10764 #undef TARGET_FUNCTION_VALUE
10765 #define TARGET_FUNCTION_VALUE s390_function_value
10766 #undef TARGET_LIBCALL_VALUE
10767 #define TARGET_LIBCALL_VALUE s390_libcall_value
10768
10769 #undef TARGET_FIXED_CONDITION_CODE_REGS
10770 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10771
10772 #undef TARGET_CC_MODES_COMPATIBLE
10773 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10774
10775 #undef TARGET_INVALID_WITHIN_DOLOOP
10776 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10777
10778 #ifdef HAVE_AS_TLS
10779 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10780 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10781 #endif
10782
10783 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10784 #undef TARGET_MANGLE_TYPE
10785 #define TARGET_MANGLE_TYPE s390_mangle_type
10786 #endif
10787
10788 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10789 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10790
10791 #undef TARGET_PREFERRED_RELOAD_CLASS
10792 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10793
10794 #undef TARGET_SECONDARY_RELOAD
10795 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10796
10797 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10798 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10799
10800 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10801 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10802
10803 #undef TARGET_LEGITIMATE_ADDRESS_P
10804 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10805
10806 #undef TARGET_LEGITIMATE_CONSTANT_P
10807 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
10808
10809 #undef TARGET_CAN_ELIMINATE
10810 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10811
10812 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10813 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10814
10815 #undef TARGET_LOOP_UNROLL_ADJUST
10816 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10817
10818 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10819 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10820 #undef TARGET_TRAMPOLINE_INIT
10821 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10822
10823 #undef TARGET_UNWIND_WORD_MODE
10824 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10825
10826 struct gcc_target targetm = TARGET_INITIALIZER;
10827
10828 #include "gt-s390.h"