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s390.c (override_options): Adopt prefetching at -O3 to handle flag_prefetch_loop_arra...
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "toplev.h"
44 #include "basic-block.h"
45 #include "integrate.h"
46 #include "ggc.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "debug.h"
50 #include "langhooks.h"
51 #include "optabs.h"
52 #include "gimple.h"
53 #include "df.h"
54 #include "params.h"
55 #include "cfgloop.h"
56
57
58 /* Define the specific costs for a given cpu. */
59
60 struct processor_costs
61 {
62 /* multiplication */
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
76 const int mxbr;
77 /* square root */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
84 /* division */
85 const int dxbr;
86 const int ddbr;
87 const int debr;
88 const int dlgr;
89 const int dlr;
90 const int dr;
91 const int dsgfr;
92 const int dsgr;
93 };
94
95 const struct processor_costs *s390_cost;
96
97 static const
98 struct processor_costs z900_cost =
99 {
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
127 };
128
129 static const
130 struct processor_costs z990_cost =
131 {
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
159 };
160
161 static const
162 struct processor_costs z9_109_cost =
163 {
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
191 };
192
193 static const
194 struct processor_costs z10_cost =
195 {
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (1) , /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (1), /* MADBR */
214 COSTS_N_INSNS (1), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
223 };
224
225 extern int reload_completed;
226
227 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
228 static rtx last_scheduled_insn;
229
230 /* Structure used to hold the components of a S/390 memory
231 address. A legitimate address on S/390 is of the general
232 form
233 base + index + displacement
234 where any of the components is optional.
235
236 base and index are registers of the class ADDR_REGS,
237 displacement is an unsigned 12-bit immediate constant. */
238
239 struct s390_address
240 {
241 rtx base;
242 rtx indx;
243 rtx disp;
244 bool pointer;
245 bool literal_pool;
246 };
247
248 /* Which cpu are we tuning for. */
249 enum processor_type s390_tune = PROCESSOR_max;
250 int s390_tune_flags;
251 /* Which instruction set architecture to use. */
252 enum processor_type s390_arch;
253 int s390_arch_flags;
254
255 HOST_WIDE_INT s390_warn_framesize = 0;
256 HOST_WIDE_INT s390_stack_size = 0;
257 HOST_WIDE_INT s390_stack_guard = 0;
258
259 /* The following structure is embedded in the machine
260 specific part of struct function. */
261
262 struct GTY (()) s390_frame_layout
263 {
264 /* Offset within stack frame. */
265 HOST_WIDE_INT gprs_offset;
266 HOST_WIDE_INT f0_offset;
267 HOST_WIDE_INT f4_offset;
268 HOST_WIDE_INT f8_offset;
269 HOST_WIDE_INT backchain_offset;
270
271 /* Number of first and last gpr where slots in the register
272 save area are reserved for. */
273 int first_save_gpr_slot;
274 int last_save_gpr_slot;
275
276 /* Number of first and last gpr to be saved, restored. */
277 int first_save_gpr;
278 int first_restore_gpr;
279 int last_save_gpr;
280 int last_restore_gpr;
281
282 /* Bits standing for floating point registers. Set, if the
283 respective register has to be saved. Starting with reg 16 (f0)
284 at the rightmost bit.
285 Bit 15 - 8 7 6 5 4 3 2 1 0
286 fpr 15 - 8 7 5 3 1 6 4 2 0
287 reg 31 - 24 23 22 21 20 19 18 17 16 */
288 unsigned int fpr_bitmap;
289
290 /* Number of floating point registers f8-f15 which must be saved. */
291 int high_fprs;
292
293 /* Set if return address needs to be saved.
294 This flag is set by s390_return_addr_rtx if it could not use
295 the initial value of r14 and therefore depends on r14 saved
296 to the stack. */
297 bool save_return_addr_p;
298
299 /* Size of stack frame. */
300 HOST_WIDE_INT frame_size;
301 };
302
303 /* Define the structure for the machine field in struct function. */
304
305 struct GTY(()) machine_function
306 {
307 struct s390_frame_layout frame_layout;
308
309 /* Literal pool base register. */
310 rtx base_reg;
311
312 /* True if we may need to perform branch splitting. */
313 bool split_branches_pending_p;
314
315 /* Some local-dynamic TLS symbol name. */
316 const char *some_ld_name;
317
318 bool has_landing_pad_p;
319 };
320
321 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
322
323 #define cfun_frame_layout (cfun->machine->frame_layout)
324 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
325 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
326 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
327 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
328 (1 << (BITNUM)))
329 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
330 (1 << (BITNUM))))
331
332 /* Number of GPRs and FPRs used for argument passing. */
333 #define GP_ARG_NUM_REG 5
334 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
335
336 /* A couple of shortcuts. */
337 #define CONST_OK_FOR_J(x) \
338 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
339 #define CONST_OK_FOR_K(x) \
340 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
341 #define CONST_OK_FOR_Os(x) \
342 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
343 #define CONST_OK_FOR_Op(x) \
344 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
345 #define CONST_OK_FOR_On(x) \
346 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
347
348 #define REGNO_PAIR_OK(REGNO, MODE) \
349 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
350
351 /* That's the read ahead of the dynamic branch prediction unit in
352 bytes on a z10 CPU. */
353 #define Z10_PREDICT_DISTANCE 384
354
355 static enum machine_mode
356 s390_libgcc_cmp_return_mode (void)
357 {
358 return TARGET_64BIT ? DImode : SImode;
359 }
360
361 static enum machine_mode
362 s390_libgcc_shift_count_mode (void)
363 {
364 return TARGET_64BIT ? DImode : SImode;
365 }
366
367 static enum machine_mode
368 s390_unwind_word_mode (void)
369 {
370 return TARGET_64BIT ? DImode : SImode;
371 }
372
373 /* Return true if the back end supports mode MODE. */
374 static bool
375 s390_scalar_mode_supported_p (enum machine_mode mode)
376 {
377 /* In contrast to the default implementation reject TImode constants on 31bit
378 TARGET_ZARCH for ABI compliance. */
379 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
380 return false;
381
382 if (DECIMAL_FLOAT_MODE_P (mode))
383 return default_decimal_float_supported_p ();
384
385 return default_scalar_mode_supported_p (mode);
386 }
387
388 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
389
390 void
391 s390_set_has_landing_pad_p (bool value)
392 {
393 cfun->machine->has_landing_pad_p = value;
394 }
395
396 /* If two condition code modes are compatible, return a condition code
397 mode which is compatible with both. Otherwise, return
398 VOIDmode. */
399
400 static enum machine_mode
401 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
402 {
403 if (m1 == m2)
404 return m1;
405
406 switch (m1)
407 {
408 case CCZmode:
409 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
410 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
411 return m2;
412 return VOIDmode;
413
414 case CCSmode:
415 case CCUmode:
416 case CCTmode:
417 case CCSRmode:
418 case CCURmode:
419 case CCZ1mode:
420 if (m2 == CCZmode)
421 return m1;
422
423 return VOIDmode;
424
425 default:
426 return VOIDmode;
427 }
428 return VOIDmode;
429 }
430
431 /* Return true if SET either doesn't set the CC register, or else
432 the source and destination have matching CC modes and that
433 CC mode is at least as constrained as REQ_MODE. */
434
435 static bool
436 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
437 {
438 enum machine_mode set_mode;
439
440 gcc_assert (GET_CODE (set) == SET);
441
442 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
443 return 1;
444
445 set_mode = GET_MODE (SET_DEST (set));
446 switch (set_mode)
447 {
448 case CCSmode:
449 case CCSRmode:
450 case CCUmode:
451 case CCURmode:
452 case CCLmode:
453 case CCL1mode:
454 case CCL2mode:
455 case CCL3mode:
456 case CCT1mode:
457 case CCT2mode:
458 case CCT3mode:
459 if (req_mode != set_mode)
460 return 0;
461 break;
462
463 case CCZmode:
464 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
465 && req_mode != CCSRmode && req_mode != CCURmode)
466 return 0;
467 break;
468
469 case CCAPmode:
470 case CCANmode:
471 if (req_mode != CCAmode)
472 return 0;
473 break;
474
475 default:
476 gcc_unreachable ();
477 }
478
479 return (GET_MODE (SET_SRC (set)) == set_mode);
480 }
481
482 /* Return true if every SET in INSN that sets the CC register
483 has source and destination with matching CC modes and that
484 CC mode is at least as constrained as REQ_MODE.
485 If REQ_MODE is VOIDmode, always return false. */
486
487 bool
488 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
489 {
490 int i;
491
492 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
493 if (req_mode == VOIDmode)
494 return false;
495
496 if (GET_CODE (PATTERN (insn)) == SET)
497 return s390_match_ccmode_set (PATTERN (insn), req_mode);
498
499 if (GET_CODE (PATTERN (insn)) == PARALLEL)
500 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
501 {
502 rtx set = XVECEXP (PATTERN (insn), 0, i);
503 if (GET_CODE (set) == SET)
504 if (!s390_match_ccmode_set (set, req_mode))
505 return false;
506 }
507
508 return true;
509 }
510
511 /* If a test-under-mask instruction can be used to implement
512 (compare (and ... OP1) OP2), return the CC mode required
513 to do that. Otherwise, return VOIDmode.
514 MIXED is true if the instruction can distinguish between
515 CC1 and CC2 for mixed selected bits (TMxx), it is false
516 if the instruction cannot (TM). */
517
518 enum machine_mode
519 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
520 {
521 int bit0, bit1;
522
523 /* ??? Fixme: should work on CONST_DOUBLE as well. */
524 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
525 return VOIDmode;
526
527 /* Selected bits all zero: CC0.
528 e.g.: int a; if ((a & (16 + 128)) == 0) */
529 if (INTVAL (op2) == 0)
530 return CCTmode;
531
532 /* Selected bits all one: CC3.
533 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
534 if (INTVAL (op2) == INTVAL (op1))
535 return CCT3mode;
536
537 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
538 int a;
539 if ((a & (16 + 128)) == 16) -> CCT1
540 if ((a & (16 + 128)) == 128) -> CCT2 */
541 if (mixed)
542 {
543 bit1 = exact_log2 (INTVAL (op2));
544 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
545 if (bit0 != -1 && bit1 != -1)
546 return bit0 > bit1 ? CCT1mode : CCT2mode;
547 }
548
549 return VOIDmode;
550 }
551
552 /* Given a comparison code OP (EQ, NE, etc.) and the operands
553 OP0 and OP1 of a COMPARE, return the mode to be used for the
554 comparison. */
555
556 enum machine_mode
557 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
558 {
559 switch (code)
560 {
561 case EQ:
562 case NE:
563 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
564 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
565 return CCAPmode;
566 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
567 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
568 return CCAPmode;
569 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
570 || GET_CODE (op1) == NEG)
571 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
572 return CCLmode;
573
574 if (GET_CODE (op0) == AND)
575 {
576 /* Check whether we can potentially do it via TM. */
577 enum machine_mode ccmode;
578 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
579 if (ccmode != VOIDmode)
580 {
581 /* Relax CCTmode to CCZmode to allow fall-back to AND
582 if that turns out to be beneficial. */
583 return ccmode == CCTmode ? CCZmode : ccmode;
584 }
585 }
586
587 if (register_operand (op0, HImode)
588 && GET_CODE (op1) == CONST_INT
589 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
590 return CCT3mode;
591 if (register_operand (op0, QImode)
592 && GET_CODE (op1) == CONST_INT
593 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
594 return CCT3mode;
595
596 return CCZmode;
597
598 case LE:
599 case LT:
600 case GE:
601 case GT:
602 /* The only overflow condition of NEG and ABS happens when
603 -INT_MAX is used as parameter, which stays negative. So
604 we have an overflow from a positive value to a negative.
605 Using CCAP mode the resulting cc can be used for comparisons. */
606 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
607 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
608 return CCAPmode;
609
610 /* If constants are involved in an add instruction it is possible to use
611 the resulting cc for comparisons with zero. Knowing the sign of the
612 constant the overflow behavior gets predictable. e.g.:
613 int a, b; if ((b = a + c) > 0)
614 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
615 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
616 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
617 {
618 if (INTVAL (XEXP((op0), 1)) < 0)
619 return CCANmode;
620 else
621 return CCAPmode;
622 }
623 /* Fall through. */
624 case UNORDERED:
625 case ORDERED:
626 case UNEQ:
627 case UNLE:
628 case UNLT:
629 case UNGE:
630 case UNGT:
631 case LTGT:
632 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
633 && GET_CODE (op1) != CONST_INT)
634 return CCSRmode;
635 return CCSmode;
636
637 case LTU:
638 case GEU:
639 if (GET_CODE (op0) == PLUS
640 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
641 return CCL1mode;
642
643 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
644 && GET_CODE (op1) != CONST_INT)
645 return CCURmode;
646 return CCUmode;
647
648 case LEU:
649 case GTU:
650 if (GET_CODE (op0) == MINUS
651 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
652 return CCL2mode;
653
654 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
655 && GET_CODE (op1) != CONST_INT)
656 return CCURmode;
657 return CCUmode;
658
659 default:
660 gcc_unreachable ();
661 }
662 }
663
664 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
665 that we can implement more efficiently. */
666
667 void
668 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
669 {
670 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
671 if ((*code == EQ || *code == NE)
672 && *op1 == const0_rtx
673 && GET_CODE (*op0) == ZERO_EXTRACT
674 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
675 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
676 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
677 {
678 rtx inner = XEXP (*op0, 0);
679 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
680 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
681 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
682
683 if (len > 0 && len < modesize
684 && pos >= 0 && pos + len <= modesize
685 && modesize <= HOST_BITS_PER_WIDE_INT)
686 {
687 unsigned HOST_WIDE_INT block;
688 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
689 block <<= modesize - pos - len;
690
691 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
692 gen_int_mode (block, GET_MODE (inner)));
693 }
694 }
695
696 /* Narrow AND of memory against immediate to enable TM. */
697 if ((*code == EQ || *code == NE)
698 && *op1 == const0_rtx
699 && GET_CODE (*op0) == AND
700 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
701 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
702 {
703 rtx inner = XEXP (*op0, 0);
704 rtx mask = XEXP (*op0, 1);
705
706 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
707 if (GET_CODE (inner) == SUBREG
708 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
709 && (GET_MODE_SIZE (GET_MODE (inner))
710 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
711 && ((INTVAL (mask)
712 & GET_MODE_MASK (GET_MODE (inner))
713 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
714 == 0))
715 inner = SUBREG_REG (inner);
716
717 /* Do not change volatile MEMs. */
718 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
719 {
720 int part = s390_single_part (XEXP (*op0, 1),
721 GET_MODE (inner), QImode, 0);
722 if (part >= 0)
723 {
724 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
725 inner = adjust_address_nv (inner, QImode, part);
726 *op0 = gen_rtx_AND (QImode, inner, mask);
727 }
728 }
729 }
730
731 /* Narrow comparisons against 0xffff to HImode if possible. */
732 if ((*code == EQ || *code == NE)
733 && GET_CODE (*op1) == CONST_INT
734 && INTVAL (*op1) == 0xffff
735 && SCALAR_INT_MODE_P (GET_MODE (*op0))
736 && (nonzero_bits (*op0, GET_MODE (*op0))
737 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
738 {
739 *op0 = gen_lowpart (HImode, *op0);
740 *op1 = constm1_rtx;
741 }
742
743 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
744 if (GET_CODE (*op0) == UNSPEC
745 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
746 && XVECLEN (*op0, 0) == 1
747 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
748 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
749 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
750 && *op1 == const0_rtx)
751 {
752 enum rtx_code new_code = UNKNOWN;
753 switch (*code)
754 {
755 case EQ: new_code = EQ; break;
756 case NE: new_code = NE; break;
757 case LT: new_code = GTU; break;
758 case GT: new_code = LTU; break;
759 case LE: new_code = GEU; break;
760 case GE: new_code = LEU; break;
761 default: break;
762 }
763
764 if (new_code != UNKNOWN)
765 {
766 *op0 = XVECEXP (*op0, 0, 0);
767 *code = new_code;
768 }
769 }
770
771 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
772 if (GET_CODE (*op0) == UNSPEC
773 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
774 && XVECLEN (*op0, 0) == 1
775 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
776 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
777 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
778 && *op1 == const0_rtx)
779 {
780 enum rtx_code new_code = UNKNOWN;
781 switch (*code)
782 {
783 case EQ: new_code = EQ; break;
784 case NE: new_code = NE; break;
785 default: break;
786 }
787
788 if (new_code != UNKNOWN)
789 {
790 *op0 = XVECEXP (*op0, 0, 0);
791 *code = new_code;
792 }
793 }
794
795 /* Simplify cascaded EQ, NE with const0_rtx. */
796 if ((*code == NE || *code == EQ)
797 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
798 && GET_MODE (*op0) == SImode
799 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
800 && REG_P (XEXP (*op0, 0))
801 && XEXP (*op0, 1) == const0_rtx
802 && *op1 == const0_rtx)
803 {
804 if ((*code == EQ && GET_CODE (*op0) == NE)
805 || (*code == NE && GET_CODE (*op0) == EQ))
806 *code = EQ;
807 else
808 *code = NE;
809 *op0 = XEXP (*op0, 0);
810 }
811
812 /* Prefer register over memory as first operand. */
813 if (MEM_P (*op0) && REG_P (*op1))
814 {
815 rtx tem = *op0; *op0 = *op1; *op1 = tem;
816 *code = swap_condition (*code);
817 }
818 }
819
820 /* Emit a compare instruction suitable to implement the comparison
821 OP0 CODE OP1. Return the correct condition RTL to be placed in
822 the IF_THEN_ELSE of the conditional branch testing the result. */
823
824 rtx
825 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
826 {
827 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
828 rtx cc;
829
830 /* Do not output a redundant compare instruction if a compare_and_swap
831 pattern already computed the result and the machine modes are compatible. */
832 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
833 {
834 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
835 == GET_MODE (op0));
836 cc = op0;
837 }
838 else
839 {
840 cc = gen_rtx_REG (mode, CC_REGNUM);
841 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
842 }
843
844 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
845 }
846
847 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
848 matches CMP.
849 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
850 conditional branch testing the result. */
851
852 static rtx
853 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
854 {
855 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
856 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
857 }
858
859 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
860 unconditional jump, else a conditional jump under condition COND. */
861
862 void
863 s390_emit_jump (rtx target, rtx cond)
864 {
865 rtx insn;
866
867 target = gen_rtx_LABEL_REF (VOIDmode, target);
868 if (cond)
869 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
870
871 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
872 emit_jump_insn (insn);
873 }
874
875 /* Return branch condition mask to implement a branch
876 specified by CODE. Return -1 for invalid comparisons. */
877
878 int
879 s390_branch_condition_mask (rtx code)
880 {
881 const int CC0 = 1 << 3;
882 const int CC1 = 1 << 2;
883 const int CC2 = 1 << 1;
884 const int CC3 = 1 << 0;
885
886 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
887 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
888 gcc_assert (XEXP (code, 1) == const0_rtx);
889
890 switch (GET_MODE (XEXP (code, 0)))
891 {
892 case CCZmode:
893 case CCZ1mode:
894 switch (GET_CODE (code))
895 {
896 case EQ: return CC0;
897 case NE: return CC1 | CC2 | CC3;
898 default: return -1;
899 }
900 break;
901
902 case CCT1mode:
903 switch (GET_CODE (code))
904 {
905 case EQ: return CC1;
906 case NE: return CC0 | CC2 | CC3;
907 default: return -1;
908 }
909 break;
910
911 case CCT2mode:
912 switch (GET_CODE (code))
913 {
914 case EQ: return CC2;
915 case NE: return CC0 | CC1 | CC3;
916 default: return -1;
917 }
918 break;
919
920 case CCT3mode:
921 switch (GET_CODE (code))
922 {
923 case EQ: return CC3;
924 case NE: return CC0 | CC1 | CC2;
925 default: return -1;
926 }
927 break;
928
929 case CCLmode:
930 switch (GET_CODE (code))
931 {
932 case EQ: return CC0 | CC2;
933 case NE: return CC1 | CC3;
934 default: return -1;
935 }
936 break;
937
938 case CCL1mode:
939 switch (GET_CODE (code))
940 {
941 case LTU: return CC2 | CC3; /* carry */
942 case GEU: return CC0 | CC1; /* no carry */
943 default: return -1;
944 }
945 break;
946
947 case CCL2mode:
948 switch (GET_CODE (code))
949 {
950 case GTU: return CC0 | CC1; /* borrow */
951 case LEU: return CC2 | CC3; /* no borrow */
952 default: return -1;
953 }
954 break;
955
956 case CCL3mode:
957 switch (GET_CODE (code))
958 {
959 case EQ: return CC0 | CC2;
960 case NE: return CC1 | CC3;
961 case LTU: return CC1;
962 case GTU: return CC3;
963 case LEU: return CC1 | CC2;
964 case GEU: return CC2 | CC3;
965 default: return -1;
966 }
967
968 case CCUmode:
969 switch (GET_CODE (code))
970 {
971 case EQ: return CC0;
972 case NE: return CC1 | CC2 | CC3;
973 case LTU: return CC1;
974 case GTU: return CC2;
975 case LEU: return CC0 | CC1;
976 case GEU: return CC0 | CC2;
977 default: return -1;
978 }
979 break;
980
981 case CCURmode:
982 switch (GET_CODE (code))
983 {
984 case EQ: return CC0;
985 case NE: return CC2 | CC1 | CC3;
986 case LTU: return CC2;
987 case GTU: return CC1;
988 case LEU: return CC0 | CC2;
989 case GEU: return CC0 | CC1;
990 default: return -1;
991 }
992 break;
993
994 case CCAPmode:
995 switch (GET_CODE (code))
996 {
997 case EQ: return CC0;
998 case NE: return CC1 | CC2 | CC3;
999 case LT: return CC1 | CC3;
1000 case GT: return CC2;
1001 case LE: return CC0 | CC1 | CC3;
1002 case GE: return CC0 | CC2;
1003 default: return -1;
1004 }
1005 break;
1006
1007 case CCANmode:
1008 switch (GET_CODE (code))
1009 {
1010 case EQ: return CC0;
1011 case NE: return CC1 | CC2 | CC3;
1012 case LT: return CC1;
1013 case GT: return CC2 | CC3;
1014 case LE: return CC0 | CC1;
1015 case GE: return CC0 | CC2 | CC3;
1016 default: return -1;
1017 }
1018 break;
1019
1020 case CCSmode:
1021 switch (GET_CODE (code))
1022 {
1023 case EQ: return CC0;
1024 case NE: return CC1 | CC2 | CC3;
1025 case LT: return CC1;
1026 case GT: return CC2;
1027 case LE: return CC0 | CC1;
1028 case GE: return CC0 | CC2;
1029 case UNORDERED: return CC3;
1030 case ORDERED: return CC0 | CC1 | CC2;
1031 case UNEQ: return CC0 | CC3;
1032 case UNLT: return CC1 | CC3;
1033 case UNGT: return CC2 | CC3;
1034 case UNLE: return CC0 | CC1 | CC3;
1035 case UNGE: return CC0 | CC2 | CC3;
1036 case LTGT: return CC1 | CC2;
1037 default: return -1;
1038 }
1039 break;
1040
1041 case CCSRmode:
1042 switch (GET_CODE (code))
1043 {
1044 case EQ: return CC0;
1045 case NE: return CC2 | CC1 | CC3;
1046 case LT: return CC2;
1047 case GT: return CC1;
1048 case LE: return CC0 | CC2;
1049 case GE: return CC0 | CC1;
1050 case UNORDERED: return CC3;
1051 case ORDERED: return CC0 | CC2 | CC1;
1052 case UNEQ: return CC0 | CC3;
1053 case UNLT: return CC2 | CC3;
1054 case UNGT: return CC1 | CC3;
1055 case UNLE: return CC0 | CC2 | CC3;
1056 case UNGE: return CC0 | CC1 | CC3;
1057 case LTGT: return CC2 | CC1;
1058 default: return -1;
1059 }
1060 break;
1061
1062 default:
1063 return -1;
1064 }
1065 }
1066
1067
1068 /* Return branch condition mask to implement a compare and branch
1069 specified by CODE. Return -1 for invalid comparisons. */
1070
1071 int
1072 s390_compare_and_branch_condition_mask (rtx code)
1073 {
1074 const int CC0 = 1 << 3;
1075 const int CC1 = 1 << 2;
1076 const int CC2 = 1 << 1;
1077
1078 switch (GET_CODE (code))
1079 {
1080 case EQ:
1081 return CC0;
1082 case NE:
1083 return CC1 | CC2;
1084 case LT:
1085 case LTU:
1086 return CC1;
1087 case GT:
1088 case GTU:
1089 return CC2;
1090 case LE:
1091 case LEU:
1092 return CC0 | CC1;
1093 case GE:
1094 case GEU:
1095 return CC0 | CC2;
1096 default:
1097 gcc_unreachable ();
1098 }
1099 return -1;
1100 }
1101
1102 /* If INV is false, return assembler mnemonic string to implement
1103 a branch specified by CODE. If INV is true, return mnemonic
1104 for the corresponding inverted branch. */
1105
1106 static const char *
1107 s390_branch_condition_mnemonic (rtx code, int inv)
1108 {
1109 int mask;
1110
1111 static const char *const mnemonic[16] =
1112 {
1113 NULL, "o", "h", "nle",
1114 "l", "nhe", "lh", "ne",
1115 "e", "nlh", "he", "nl",
1116 "le", "nh", "no", NULL
1117 };
1118
1119 if (GET_CODE (XEXP (code, 0)) == REG
1120 && REGNO (XEXP (code, 0)) == CC_REGNUM
1121 && XEXP (code, 1) == const0_rtx)
1122 mask = s390_branch_condition_mask (code);
1123 else
1124 mask = s390_compare_and_branch_condition_mask (code);
1125
1126 gcc_assert (mask >= 0);
1127
1128 if (inv)
1129 mask ^= 15;
1130
1131 gcc_assert (mask >= 1 && mask <= 14);
1132
1133 return mnemonic[mask];
1134 }
1135
1136 /* Return the part of op which has a value different from def.
1137 The size of the part is determined by mode.
1138 Use this function only if you already know that op really
1139 contains such a part. */
1140
1141 unsigned HOST_WIDE_INT
1142 s390_extract_part (rtx op, enum machine_mode mode, int def)
1143 {
1144 unsigned HOST_WIDE_INT value = 0;
1145 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1146 int part_bits = GET_MODE_BITSIZE (mode);
1147 unsigned HOST_WIDE_INT part_mask
1148 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1149 int i;
1150
1151 for (i = 0; i < max_parts; i++)
1152 {
1153 if (i == 0)
1154 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1155 else
1156 value >>= part_bits;
1157
1158 if ((value & part_mask) != (def & part_mask))
1159 return value & part_mask;
1160 }
1161
1162 gcc_unreachable ();
1163 }
1164
1165 /* If OP is an integer constant of mode MODE with exactly one
1166 part of mode PART_MODE unequal to DEF, return the number of that
1167 part. Otherwise, return -1. */
1168
1169 int
1170 s390_single_part (rtx op,
1171 enum machine_mode mode,
1172 enum machine_mode part_mode,
1173 int def)
1174 {
1175 unsigned HOST_WIDE_INT value = 0;
1176 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1177 unsigned HOST_WIDE_INT part_mask
1178 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1179 int i, part = -1;
1180
1181 if (GET_CODE (op) != CONST_INT)
1182 return -1;
1183
1184 for (i = 0; i < n_parts; i++)
1185 {
1186 if (i == 0)
1187 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1188 else
1189 value >>= GET_MODE_BITSIZE (part_mode);
1190
1191 if ((value & part_mask) != (def & part_mask))
1192 {
1193 if (part != -1)
1194 return -1;
1195 else
1196 part = i;
1197 }
1198 }
1199 return part == -1 ? -1 : n_parts - 1 - part;
1200 }
1201
1202 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1203 bits and no other bits are set in IN. POS and LENGTH can be used
1204 to obtain the start position and the length of the bitfield.
1205
1206 POS gives the position of the first bit of the bitfield counting
1207 from the lowest order bit starting with zero. In order to use this
1208 value for S/390 instructions this has to be converted to "bits big
1209 endian" style. */
1210
1211 bool
1212 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1213 int *pos, int *length)
1214 {
1215 int tmp_pos = 0;
1216 int tmp_length = 0;
1217 int i;
1218 unsigned HOST_WIDE_INT mask = 1ULL;
1219 bool contiguous = false;
1220
1221 for (i = 0; i < size; mask <<= 1, i++)
1222 {
1223 if (contiguous)
1224 {
1225 if (mask & in)
1226 tmp_length++;
1227 else
1228 break;
1229 }
1230 else
1231 {
1232 if (mask & in)
1233 {
1234 contiguous = true;
1235 tmp_length++;
1236 }
1237 else
1238 tmp_pos++;
1239 }
1240 }
1241
1242 if (!tmp_length)
1243 return false;
1244
1245 /* Calculate a mask for all bits beyond the contiguous bits. */
1246 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1247
1248 if (mask & in)
1249 return false;
1250
1251 if (tmp_length + tmp_pos - 1 > size)
1252 return false;
1253
1254 if (length)
1255 *length = tmp_length;
1256
1257 if (pos)
1258 *pos = tmp_pos;
1259
1260 return true;
1261 }
1262
1263 /* Check whether we can (and want to) split a double-word
1264 move in mode MODE from SRC to DST into two single-word
1265 moves, moving the subword FIRST_SUBWORD first. */
1266
1267 bool
1268 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1269 {
1270 /* Floating point registers cannot be split. */
1271 if (FP_REG_P (src) || FP_REG_P (dst))
1272 return false;
1273
1274 /* We don't need to split if operands are directly accessible. */
1275 if (s_operand (src, mode) || s_operand (dst, mode))
1276 return false;
1277
1278 /* Non-offsettable memory references cannot be split. */
1279 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1280 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1281 return false;
1282
1283 /* Moving the first subword must not clobber a register
1284 needed to move the second subword. */
1285 if (register_operand (dst, mode))
1286 {
1287 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1288 if (reg_overlap_mentioned_p (subreg, src))
1289 return false;
1290 }
1291
1292 return true;
1293 }
1294
1295 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1296 and [MEM2, MEM2 + SIZE] do overlap and false
1297 otherwise. */
1298
1299 bool
1300 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1301 {
1302 rtx addr1, addr2, addr_delta;
1303 HOST_WIDE_INT delta;
1304
1305 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1306 return true;
1307
1308 if (size == 0)
1309 return false;
1310
1311 addr1 = XEXP (mem1, 0);
1312 addr2 = XEXP (mem2, 0);
1313
1314 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1315
1316 /* This overlapping check is used by peepholes merging memory block operations.
1317 Overlapping operations would otherwise be recognized by the S/390 hardware
1318 and would fall back to a slower implementation. Allowing overlapping
1319 operations would lead to slow code but not to wrong code. Therefore we are
1320 somewhat optimistic if we cannot prove that the memory blocks are
1321 overlapping.
1322 That's why we return false here although this may accept operations on
1323 overlapping memory areas. */
1324 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1325 return false;
1326
1327 delta = INTVAL (addr_delta);
1328
1329 if (delta == 0
1330 || (delta > 0 && delta < size)
1331 || (delta < 0 && -delta < size))
1332 return true;
1333
1334 return false;
1335 }
1336
1337 /* Check whether the address of memory reference MEM2 equals exactly
1338 the address of memory reference MEM1 plus DELTA. Return true if
1339 we can prove this to be the case, false otherwise. */
1340
1341 bool
1342 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1343 {
1344 rtx addr1, addr2, addr_delta;
1345
1346 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1347 return false;
1348
1349 addr1 = XEXP (mem1, 0);
1350 addr2 = XEXP (mem2, 0);
1351
1352 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1353 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1354 return false;
1355
1356 return true;
1357 }
1358
1359 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1360
1361 void
1362 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1363 rtx *operands)
1364 {
1365 enum machine_mode wmode = mode;
1366 rtx dst = operands[0];
1367 rtx src1 = operands[1];
1368 rtx src2 = operands[2];
1369 rtx op, clob, tem;
1370
1371 /* If we cannot handle the operation directly, use a temp register. */
1372 if (!s390_logical_operator_ok_p (operands))
1373 dst = gen_reg_rtx (mode);
1374
1375 /* QImode and HImode patterns make sense only if we have a destination
1376 in memory. Otherwise perform the operation in SImode. */
1377 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1378 wmode = SImode;
1379
1380 /* Widen operands if required. */
1381 if (mode != wmode)
1382 {
1383 if (GET_CODE (dst) == SUBREG
1384 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1385 dst = tem;
1386 else if (REG_P (dst))
1387 dst = gen_rtx_SUBREG (wmode, dst, 0);
1388 else
1389 dst = gen_reg_rtx (wmode);
1390
1391 if (GET_CODE (src1) == SUBREG
1392 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1393 src1 = tem;
1394 else if (GET_MODE (src1) != VOIDmode)
1395 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1396
1397 if (GET_CODE (src2) == SUBREG
1398 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1399 src2 = tem;
1400 else if (GET_MODE (src2) != VOIDmode)
1401 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1402 }
1403
1404 /* Emit the instruction. */
1405 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1406 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1407 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1408
1409 /* Fix up the destination if needed. */
1410 if (dst != operands[0])
1411 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1412 }
1413
1414 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1415
1416 bool
1417 s390_logical_operator_ok_p (rtx *operands)
1418 {
1419 /* If the destination operand is in memory, it needs to coincide
1420 with one of the source operands. After reload, it has to be
1421 the first source operand. */
1422 if (GET_CODE (operands[0]) == MEM)
1423 return rtx_equal_p (operands[0], operands[1])
1424 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1425
1426 return true;
1427 }
1428
1429 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1430 operand IMMOP to switch from SS to SI type instructions. */
1431
1432 void
1433 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1434 {
1435 int def = code == AND ? -1 : 0;
1436 HOST_WIDE_INT mask;
1437 int part;
1438
1439 gcc_assert (GET_CODE (*memop) == MEM);
1440 gcc_assert (!MEM_VOLATILE_P (*memop));
1441
1442 mask = s390_extract_part (*immop, QImode, def);
1443 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1444 gcc_assert (part >= 0);
1445
1446 *memop = adjust_address (*memop, QImode, part);
1447 *immop = gen_int_mode (mask, QImode);
1448 }
1449
1450
1451 /* How to allocate a 'struct machine_function'. */
1452
1453 static struct machine_function *
1454 s390_init_machine_status (void)
1455 {
1456 return ggc_alloc_cleared_machine_function ();
1457 }
1458
1459 /* Change optimizations to be performed, depending on the
1460 optimization level.
1461
1462 LEVEL is the optimization level specified; 2 if `-O2' is
1463 specified, 1 if `-O' is specified, and 0 if neither is specified.
1464
1465 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1466
1467 void
1468 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1469 {
1470 /* ??? There are apparently still problems with -fcaller-saves. */
1471 flag_caller_saves = 0;
1472
1473 /* By default, always emit DWARF-2 unwind info. This allows debugging
1474 without maintaining a stack frame back-chain. */
1475 flag_asynchronous_unwind_tables = 1;
1476
1477 /* Use MVCLE instructions to decrease code size if requested. */
1478 if (size != 0)
1479 target_flags |= MASK_MVCLE;
1480 }
1481
1482 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1483 to the associated processor_type and processor_flags if so. */
1484
1485 static bool
1486 s390_handle_arch_option (const char *arg,
1487 enum processor_type *type,
1488 int *flags)
1489 {
1490 static struct pta
1491 {
1492 const char *const name; /* processor name or nickname. */
1493 const enum processor_type processor;
1494 const int flags; /* From enum processor_flags. */
1495 }
1496 const processor_alias_table[] =
1497 {
1498 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1499 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1500 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1501 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1502 | PF_LONG_DISPLACEMENT},
1503 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1504 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1505 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1506 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1507 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1508 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1509 };
1510 size_t i;
1511
1512 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1513 if (strcmp (arg, processor_alias_table[i].name) == 0)
1514 {
1515 *type = processor_alias_table[i].processor;
1516 *flags = processor_alias_table[i].flags;
1517 return true;
1518 }
1519 return false;
1520 }
1521
1522 /* Implement TARGET_HANDLE_OPTION. */
1523
1524 static bool
1525 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1526 {
1527 switch (code)
1528 {
1529 case OPT_march_:
1530 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1531
1532 case OPT_mstack_guard_:
1533 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1534 return false;
1535 if (exact_log2 (s390_stack_guard) == -1)
1536 error ("stack guard value must be an exact power of 2");
1537 return true;
1538
1539 case OPT_mstack_size_:
1540 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1541 return false;
1542 if (exact_log2 (s390_stack_size) == -1)
1543 error ("stack size must be an exact power of 2");
1544 return true;
1545
1546 case OPT_mtune_:
1547 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1548
1549 case OPT_mwarn_framesize_:
1550 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1551
1552 default:
1553 return true;
1554 }
1555 }
1556
1557 void
1558 override_options (void)
1559 {
1560 /* Set up function hooks. */
1561 init_machine_status = s390_init_machine_status;
1562
1563 /* Architecture mode defaults according to ABI. */
1564 if (!(target_flags_explicit & MASK_ZARCH))
1565 {
1566 if (TARGET_64BIT)
1567 target_flags |= MASK_ZARCH;
1568 else
1569 target_flags &= ~MASK_ZARCH;
1570 }
1571
1572 /* Determine processor architectural level. */
1573 if (!s390_arch_string)
1574 {
1575 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1576 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1577 }
1578
1579 /* Determine processor to tune for. */
1580 if (s390_tune == PROCESSOR_max)
1581 {
1582 s390_tune = s390_arch;
1583 s390_tune_flags = s390_arch_flags;
1584 }
1585
1586 /* Sanity checks. */
1587 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1588 error ("z/Architecture mode not supported on %s", s390_arch_string);
1589 if (TARGET_64BIT && !TARGET_ZARCH)
1590 error ("64-bit ABI not supported in ESA/390 mode");
1591
1592 if (TARGET_HARD_DFP && !TARGET_DFP)
1593 {
1594 if (target_flags_explicit & MASK_HARD_DFP)
1595 {
1596 if (!TARGET_CPU_DFP)
1597 error ("Hardware decimal floating point instructions"
1598 " not available on %s", s390_arch_string);
1599 if (!TARGET_ZARCH)
1600 error ("Hardware decimal floating point instructions"
1601 " not available in ESA/390 mode");
1602 }
1603 else
1604 target_flags &= ~MASK_HARD_DFP;
1605 }
1606
1607 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1608 {
1609 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1610 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1611
1612 target_flags &= ~MASK_HARD_DFP;
1613 }
1614
1615 /* Set processor cost function. */
1616 switch (s390_tune)
1617 {
1618 case PROCESSOR_2084_Z990:
1619 s390_cost = &z990_cost;
1620 break;
1621 case PROCESSOR_2094_Z9_109:
1622 s390_cost = &z9_109_cost;
1623 break;
1624 case PROCESSOR_2097_Z10:
1625 s390_cost = &z10_cost;
1626 break;
1627 default:
1628 s390_cost = &z900_cost;
1629 }
1630
1631 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1632 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1633 "in combination");
1634
1635 if (s390_stack_size)
1636 {
1637 if (s390_stack_guard >= s390_stack_size)
1638 error ("stack size must be greater than the stack guard value");
1639 else if (s390_stack_size > 1 << 16)
1640 error ("stack size must not be greater than 64k");
1641 }
1642 else if (s390_stack_guard)
1643 error ("-mstack-guard implies use of -mstack-size");
1644
1645 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1646 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1647 target_flags |= MASK_LONG_DOUBLE_128;
1648 #endif
1649
1650 if (s390_tune == PROCESSOR_2097_Z10)
1651 {
1652 if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
1653 set_param_value ("max-unrolled-insns", 100);
1654 if (!PARAM_SET_P (PARAM_MAX_UNROLL_TIMES))
1655 set_param_value ("max-unroll-times", 32);
1656 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEELED_INSNS))
1657 set_param_value ("max-completely-peeled-insns", 2000);
1658 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEEL_TIMES))
1659 set_param_value ("max-completely-peel-times", 64);
1660 }
1661
1662 set_param_value ("max-pending-list-length", 256);
1663 /* values for loop prefetching */
1664 set_param_value ("l1-cache-line-size", 256);
1665 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1666 set_param_value ("l1-cache-size", 128);
1667 /* s390 has more than 2 levels and the size is much larger. Since
1668 we are always running virtualized assume that we only get a small
1669 part of the caches above l1. */
1670 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1671 set_param_value ("l2-cache-size", 1500);
1672 if (!PARAM_SET_P (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO))
1673 set_param_value ("prefetch-min-insn-to-mem-ratio", 2);
1674 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1675 set_param_value ("simultaneous-prefetches", 6);
1676
1677 /* This cannot reside in optimization_options since HAVE_prefetch
1678 requires the arch flags to be evaluated already. Since prefetching
1679 is beneficial on s390, we enable it if available. */
1680 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1681 flag_prefetch_loop_arrays = 1;
1682 }
1683
1684 /* Map for smallest class containing reg regno. */
1685
1686 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1687 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1688 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1689 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1690 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1691 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1692 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1693 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1694 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1695 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1696 ACCESS_REGS, ACCESS_REGS
1697 };
1698
1699 /* Return attribute type of insn. */
1700
1701 static enum attr_type
1702 s390_safe_attr_type (rtx insn)
1703 {
1704 if (recog_memoized (insn) >= 0)
1705 return get_attr_type (insn);
1706 else
1707 return TYPE_NONE;
1708 }
1709
1710 /* Return true if DISP is a valid short displacement. */
1711
1712 static bool
1713 s390_short_displacement (rtx disp)
1714 {
1715 /* No displacement is OK. */
1716 if (!disp)
1717 return true;
1718
1719 /* Without the long displacement facility we don't need to
1720 distingiush between long and short displacement. */
1721 if (!TARGET_LONG_DISPLACEMENT)
1722 return true;
1723
1724 /* Integer displacement in range. */
1725 if (GET_CODE (disp) == CONST_INT)
1726 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1727
1728 /* GOT offset is not OK, the GOT can be large. */
1729 if (GET_CODE (disp) == CONST
1730 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1731 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1732 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1733 return false;
1734
1735 /* All other symbolic constants are literal pool references,
1736 which are OK as the literal pool must be small. */
1737 if (GET_CODE (disp) == CONST)
1738 return true;
1739
1740 return false;
1741 }
1742
1743 /* Decompose a RTL expression ADDR for a memory address into
1744 its components, returned in OUT.
1745
1746 Returns false if ADDR is not a valid memory address, true
1747 otherwise. If OUT is NULL, don't return the components,
1748 but check for validity only.
1749
1750 Note: Only addresses in canonical form are recognized.
1751 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1752 canonical form so that they will be recognized. */
1753
1754 static int
1755 s390_decompose_address (rtx addr, struct s390_address *out)
1756 {
1757 HOST_WIDE_INT offset = 0;
1758 rtx base = NULL_RTX;
1759 rtx indx = NULL_RTX;
1760 rtx disp = NULL_RTX;
1761 rtx orig_disp;
1762 bool pointer = false;
1763 bool base_ptr = false;
1764 bool indx_ptr = false;
1765 bool literal_pool = false;
1766
1767 /* We may need to substitute the literal pool base register into the address
1768 below. However, at this point we do not know which register is going to
1769 be used as base, so we substitute the arg pointer register. This is going
1770 to be treated as holding a pointer below -- it shouldn't be used for any
1771 other purpose. */
1772 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1773
1774 /* Decompose address into base + index + displacement. */
1775
1776 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1777 base = addr;
1778
1779 else if (GET_CODE (addr) == PLUS)
1780 {
1781 rtx op0 = XEXP (addr, 0);
1782 rtx op1 = XEXP (addr, 1);
1783 enum rtx_code code0 = GET_CODE (op0);
1784 enum rtx_code code1 = GET_CODE (op1);
1785
1786 if (code0 == REG || code0 == UNSPEC)
1787 {
1788 if (code1 == REG || code1 == UNSPEC)
1789 {
1790 indx = op0; /* index + base */
1791 base = op1;
1792 }
1793
1794 else
1795 {
1796 base = op0; /* base + displacement */
1797 disp = op1;
1798 }
1799 }
1800
1801 else if (code0 == PLUS)
1802 {
1803 indx = XEXP (op0, 0); /* index + base + disp */
1804 base = XEXP (op0, 1);
1805 disp = op1;
1806 }
1807
1808 else
1809 {
1810 return false;
1811 }
1812 }
1813
1814 else
1815 disp = addr; /* displacement */
1816
1817 /* Extract integer part of displacement. */
1818 orig_disp = disp;
1819 if (disp)
1820 {
1821 if (GET_CODE (disp) == CONST_INT)
1822 {
1823 offset = INTVAL (disp);
1824 disp = NULL_RTX;
1825 }
1826 else if (GET_CODE (disp) == CONST
1827 && GET_CODE (XEXP (disp, 0)) == PLUS
1828 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1829 {
1830 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1831 disp = XEXP (XEXP (disp, 0), 0);
1832 }
1833 }
1834
1835 /* Strip off CONST here to avoid special case tests later. */
1836 if (disp && GET_CODE (disp) == CONST)
1837 disp = XEXP (disp, 0);
1838
1839 /* We can convert literal pool addresses to
1840 displacements by basing them off the base register. */
1841 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1842 {
1843 /* Either base or index must be free to hold the base register. */
1844 if (!base)
1845 base = fake_pool_base, literal_pool = true;
1846 else if (!indx)
1847 indx = fake_pool_base, literal_pool = true;
1848 else
1849 return false;
1850
1851 /* Mark up the displacement. */
1852 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1853 UNSPEC_LTREL_OFFSET);
1854 }
1855
1856 /* Validate base register. */
1857 if (base)
1858 {
1859 if (GET_CODE (base) == UNSPEC)
1860 switch (XINT (base, 1))
1861 {
1862 case UNSPEC_LTREF:
1863 if (!disp)
1864 disp = gen_rtx_UNSPEC (Pmode,
1865 gen_rtvec (1, XVECEXP (base, 0, 0)),
1866 UNSPEC_LTREL_OFFSET);
1867 else
1868 return false;
1869
1870 base = XVECEXP (base, 0, 1);
1871 break;
1872
1873 case UNSPEC_LTREL_BASE:
1874 if (XVECLEN (base, 0) == 1)
1875 base = fake_pool_base, literal_pool = true;
1876 else
1877 base = XVECEXP (base, 0, 1);
1878 break;
1879
1880 default:
1881 return false;
1882 }
1883
1884 if (!REG_P (base)
1885 || (GET_MODE (base) != SImode
1886 && GET_MODE (base) != Pmode))
1887 return false;
1888
1889 if (REGNO (base) == STACK_POINTER_REGNUM
1890 || REGNO (base) == FRAME_POINTER_REGNUM
1891 || ((reload_completed || reload_in_progress)
1892 && frame_pointer_needed
1893 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1894 || REGNO (base) == ARG_POINTER_REGNUM
1895 || (flag_pic
1896 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1897 pointer = base_ptr = true;
1898
1899 if ((reload_completed || reload_in_progress)
1900 && base == cfun->machine->base_reg)
1901 pointer = base_ptr = literal_pool = true;
1902 }
1903
1904 /* Validate index register. */
1905 if (indx)
1906 {
1907 if (GET_CODE (indx) == UNSPEC)
1908 switch (XINT (indx, 1))
1909 {
1910 case UNSPEC_LTREF:
1911 if (!disp)
1912 disp = gen_rtx_UNSPEC (Pmode,
1913 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1914 UNSPEC_LTREL_OFFSET);
1915 else
1916 return false;
1917
1918 indx = XVECEXP (indx, 0, 1);
1919 break;
1920
1921 case UNSPEC_LTREL_BASE:
1922 if (XVECLEN (indx, 0) == 1)
1923 indx = fake_pool_base, literal_pool = true;
1924 else
1925 indx = XVECEXP (indx, 0, 1);
1926 break;
1927
1928 default:
1929 return false;
1930 }
1931
1932 if (!REG_P (indx)
1933 || (GET_MODE (indx) != SImode
1934 && GET_MODE (indx) != Pmode))
1935 return false;
1936
1937 if (REGNO (indx) == STACK_POINTER_REGNUM
1938 || REGNO (indx) == FRAME_POINTER_REGNUM
1939 || ((reload_completed || reload_in_progress)
1940 && frame_pointer_needed
1941 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1942 || REGNO (indx) == ARG_POINTER_REGNUM
1943 || (flag_pic
1944 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1945 pointer = indx_ptr = true;
1946
1947 if ((reload_completed || reload_in_progress)
1948 && indx == cfun->machine->base_reg)
1949 pointer = indx_ptr = literal_pool = true;
1950 }
1951
1952 /* Prefer to use pointer as base, not index. */
1953 if (base && indx && !base_ptr
1954 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1955 {
1956 rtx tmp = base;
1957 base = indx;
1958 indx = tmp;
1959 }
1960
1961 /* Validate displacement. */
1962 if (!disp)
1963 {
1964 /* If virtual registers are involved, the displacement will change later
1965 anyway as the virtual registers get eliminated. This could make a
1966 valid displacement invalid, but it is more likely to make an invalid
1967 displacement valid, because we sometimes access the register save area
1968 via negative offsets to one of those registers.
1969 Thus we don't check the displacement for validity here. If after
1970 elimination the displacement turns out to be invalid after all,
1971 this is fixed up by reload in any case. */
1972 if (base != arg_pointer_rtx
1973 && indx != arg_pointer_rtx
1974 && base != return_address_pointer_rtx
1975 && indx != return_address_pointer_rtx
1976 && base != frame_pointer_rtx
1977 && indx != frame_pointer_rtx
1978 && base != virtual_stack_vars_rtx
1979 && indx != virtual_stack_vars_rtx)
1980 if (!DISP_IN_RANGE (offset))
1981 return false;
1982 }
1983 else
1984 {
1985 /* All the special cases are pointers. */
1986 pointer = true;
1987
1988 /* In the small-PIC case, the linker converts @GOT
1989 and @GOTNTPOFF offsets to possible displacements. */
1990 if (GET_CODE (disp) == UNSPEC
1991 && (XINT (disp, 1) == UNSPEC_GOT
1992 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1993 && flag_pic == 1)
1994 {
1995 ;
1996 }
1997
1998 /* Accept pool label offsets. */
1999 else if (GET_CODE (disp) == UNSPEC
2000 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2001 ;
2002
2003 /* Accept literal pool references. */
2004 else if (GET_CODE (disp) == UNSPEC
2005 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2006 {
2007 orig_disp = gen_rtx_CONST (Pmode, disp);
2008 if (offset)
2009 {
2010 /* If we have an offset, make sure it does not
2011 exceed the size of the constant pool entry. */
2012 rtx sym = XVECEXP (disp, 0, 0);
2013 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2014 return false;
2015
2016 orig_disp = plus_constant (orig_disp, offset);
2017 }
2018 }
2019
2020 else
2021 return false;
2022 }
2023
2024 if (!base && !indx)
2025 pointer = true;
2026
2027 if (out)
2028 {
2029 out->base = base;
2030 out->indx = indx;
2031 out->disp = orig_disp;
2032 out->pointer = pointer;
2033 out->literal_pool = literal_pool;
2034 }
2035
2036 return true;
2037 }
2038
2039 /* Decompose a RTL expression OP for a shift count into its components,
2040 and return the base register in BASE and the offset in OFFSET.
2041
2042 Return true if OP is a valid shift count, false if not. */
2043
2044 bool
2045 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2046 {
2047 HOST_WIDE_INT off = 0;
2048
2049 /* We can have an integer constant, an address register,
2050 or a sum of the two. */
2051 if (GET_CODE (op) == CONST_INT)
2052 {
2053 off = INTVAL (op);
2054 op = NULL_RTX;
2055 }
2056 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2057 {
2058 off = INTVAL (XEXP (op, 1));
2059 op = XEXP (op, 0);
2060 }
2061 while (op && GET_CODE (op) == SUBREG)
2062 op = SUBREG_REG (op);
2063
2064 if (op && GET_CODE (op) != REG)
2065 return false;
2066
2067 if (offset)
2068 *offset = off;
2069 if (base)
2070 *base = op;
2071
2072 return true;
2073 }
2074
2075
2076 /* Return true if CODE is a valid address without index. */
2077
2078 bool
2079 s390_legitimate_address_without_index_p (rtx op)
2080 {
2081 struct s390_address addr;
2082
2083 if (!s390_decompose_address (XEXP (op, 0), &addr))
2084 return false;
2085 if (addr.indx)
2086 return false;
2087
2088 return true;
2089 }
2090
2091
2092 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2093 and return these parts in SYMREF and ADDEND. You can pass NULL in
2094 SYMREF and/or ADDEND if you are not interested in these values. */
2095
2096 static bool
2097 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2098 {
2099 HOST_WIDE_INT tmpaddend = 0;
2100
2101 if (GET_CODE (addr) == CONST)
2102 addr = XEXP (addr, 0);
2103
2104 if (GET_CODE (addr) == PLUS)
2105 {
2106 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2107 && CONST_INT_P (XEXP (addr, 1)))
2108 {
2109 tmpaddend = INTVAL (XEXP (addr, 1));
2110 addr = XEXP (addr, 0);
2111 }
2112 else
2113 return false;
2114 }
2115 else
2116 if (GET_CODE (addr) != SYMBOL_REF)
2117 return false;
2118
2119 if (symref)
2120 *symref = addr;
2121 if (addend)
2122 *addend = tmpaddend;
2123
2124 return true;
2125 }
2126
2127
2128 /* Return true if the address in OP is valid for constraint letter C
2129 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2130 pool MEMs should be accepted. Only the Q, R, S, T constraint
2131 letters are allowed for C. */
2132
2133 static int
2134 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2135 {
2136 struct s390_address addr;
2137 bool decomposed = false;
2138
2139 /* This check makes sure that no symbolic address (except literal
2140 pool references) are accepted by the R or T constraints. */
2141 if (s390_symref_operand_p (op, NULL, NULL))
2142 {
2143 if (!lit_pool_ok)
2144 return 0;
2145 if (!s390_decompose_address (op, &addr))
2146 return 0;
2147 if (!addr.literal_pool)
2148 return 0;
2149 decomposed = true;
2150 }
2151
2152 switch (c)
2153 {
2154 case 'Q': /* no index short displacement */
2155 if (!decomposed && !s390_decompose_address (op, &addr))
2156 return 0;
2157 if (addr.indx)
2158 return 0;
2159 if (!s390_short_displacement (addr.disp))
2160 return 0;
2161 break;
2162
2163 case 'R': /* with index short displacement */
2164 if (TARGET_LONG_DISPLACEMENT)
2165 {
2166 if (!decomposed && !s390_decompose_address (op, &addr))
2167 return 0;
2168 if (!s390_short_displacement (addr.disp))
2169 return 0;
2170 }
2171 /* Any invalid address here will be fixed up by reload,
2172 so accept it for the most generic constraint. */
2173 break;
2174
2175 case 'S': /* no index long displacement */
2176 if (!TARGET_LONG_DISPLACEMENT)
2177 return 0;
2178 if (!decomposed && !s390_decompose_address (op, &addr))
2179 return 0;
2180 if (addr.indx)
2181 return 0;
2182 if (s390_short_displacement (addr.disp))
2183 return 0;
2184 break;
2185
2186 case 'T': /* with index long displacement */
2187 if (!TARGET_LONG_DISPLACEMENT)
2188 return 0;
2189 /* Any invalid address here will be fixed up by reload,
2190 so accept it for the most generic constraint. */
2191 if ((decomposed || s390_decompose_address (op, &addr))
2192 && s390_short_displacement (addr.disp))
2193 return 0;
2194 break;
2195 default:
2196 return 0;
2197 }
2198 return 1;
2199 }
2200
2201
2202 /* Evaluates constraint strings described by the regular expression
2203 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2204 the constraint given in STR, or 0 else. */
2205
2206 int
2207 s390_mem_constraint (const char *str, rtx op)
2208 {
2209 char c = str[0];
2210
2211 switch (c)
2212 {
2213 case 'A':
2214 /* Check for offsettable variants of memory constraints. */
2215 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2216 return 0;
2217 if ((reload_completed || reload_in_progress)
2218 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2219 return 0;
2220 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2221 case 'B':
2222 /* Check for non-literal-pool variants of memory constraints. */
2223 if (!MEM_P (op))
2224 return 0;
2225 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2226 case 'Q':
2227 case 'R':
2228 case 'S':
2229 case 'T':
2230 if (GET_CODE (op) != MEM)
2231 return 0;
2232 return s390_check_qrst_address (c, XEXP (op, 0), true);
2233 case 'U':
2234 return (s390_check_qrst_address ('Q', op, true)
2235 || s390_check_qrst_address ('R', op, true));
2236 case 'W':
2237 return (s390_check_qrst_address ('S', op, true)
2238 || s390_check_qrst_address ('T', op, true));
2239 case 'Y':
2240 /* Simply check for the basic form of a shift count. Reload will
2241 take care of making sure we have a proper base register. */
2242 if (!s390_decompose_shift_count (op, NULL, NULL))
2243 return 0;
2244 break;
2245 case 'Z':
2246 return s390_check_qrst_address (str[1], op, true);
2247 default:
2248 return 0;
2249 }
2250 return 1;
2251 }
2252
2253
2254 /* Evaluates constraint strings starting with letter O. Input
2255 parameter C is the second letter following the "O" in the constraint
2256 string. Returns 1 if VALUE meets the respective constraint and 0
2257 otherwise. */
2258
2259 int
2260 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2261 {
2262 if (!TARGET_EXTIMM)
2263 return 0;
2264
2265 switch (c)
2266 {
2267 case 's':
2268 return trunc_int_for_mode (value, SImode) == value;
2269
2270 case 'p':
2271 return value == 0
2272 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2273
2274 case 'n':
2275 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2276
2277 default:
2278 gcc_unreachable ();
2279 }
2280 }
2281
2282
2283 /* Evaluates constraint strings starting with letter N. Parameter STR
2284 contains the letters following letter "N" in the constraint string.
2285 Returns true if VALUE matches the constraint. */
2286
2287 int
2288 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2289 {
2290 enum machine_mode mode, part_mode;
2291 int def;
2292 int part, part_goal;
2293
2294
2295 if (str[0] == 'x')
2296 part_goal = -1;
2297 else
2298 part_goal = str[0] - '0';
2299
2300 switch (str[1])
2301 {
2302 case 'Q':
2303 part_mode = QImode;
2304 break;
2305 case 'H':
2306 part_mode = HImode;
2307 break;
2308 case 'S':
2309 part_mode = SImode;
2310 break;
2311 default:
2312 return 0;
2313 }
2314
2315 switch (str[2])
2316 {
2317 case 'H':
2318 mode = HImode;
2319 break;
2320 case 'S':
2321 mode = SImode;
2322 break;
2323 case 'D':
2324 mode = DImode;
2325 break;
2326 default:
2327 return 0;
2328 }
2329
2330 switch (str[3])
2331 {
2332 case '0':
2333 def = 0;
2334 break;
2335 case 'F':
2336 def = -1;
2337 break;
2338 default:
2339 return 0;
2340 }
2341
2342 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2343 return 0;
2344
2345 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2346 if (part < 0)
2347 return 0;
2348 if (part_goal != -1 && part_goal != part)
2349 return 0;
2350
2351 return 1;
2352 }
2353
2354
2355 /* Returns true if the input parameter VALUE is a float zero. */
2356
2357 int
2358 s390_float_const_zero_p (rtx value)
2359 {
2360 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2361 && value == CONST0_RTX (GET_MODE (value)));
2362 }
2363
2364
2365 /* Compute a (partial) cost for rtx X. Return true if the complete
2366 cost has been computed, and false if subexpressions should be
2367 scanned. In either case, *TOTAL contains the cost result.
2368 CODE contains GET_CODE (x), OUTER_CODE contains the code
2369 of the superexpression of x. */
2370
2371 static bool
2372 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2373 bool speed ATTRIBUTE_UNUSED)
2374 {
2375 switch (code)
2376 {
2377 case CONST:
2378 case CONST_INT:
2379 case LABEL_REF:
2380 case SYMBOL_REF:
2381 case CONST_DOUBLE:
2382 case MEM:
2383 *total = 0;
2384 return true;
2385
2386 case ASHIFT:
2387 case ASHIFTRT:
2388 case LSHIFTRT:
2389 case ROTATE:
2390 case ROTATERT:
2391 case AND:
2392 case IOR:
2393 case XOR:
2394 case NEG:
2395 case NOT:
2396 *total = COSTS_N_INSNS (1);
2397 return false;
2398
2399 case PLUS:
2400 case MINUS:
2401 /* Check for multiply and add. */
2402 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2403 && GET_CODE (XEXP (x, 0)) == MULT
2404 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2405 {
2406 /* This is the multiply and add case. */
2407 if (GET_MODE (x) == DFmode)
2408 *total = s390_cost->madbr;
2409 else
2410 *total = s390_cost->maebr;
2411 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2412 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2413 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2414 return true; /* Do not do an additional recursive descent. */
2415 }
2416 *total = COSTS_N_INSNS (1);
2417 return false;
2418
2419 case MULT:
2420 switch (GET_MODE (x))
2421 {
2422 case SImode:
2423 {
2424 rtx left = XEXP (x, 0);
2425 rtx right = XEXP (x, 1);
2426 if (GET_CODE (right) == CONST_INT
2427 && CONST_OK_FOR_K (INTVAL (right)))
2428 *total = s390_cost->mhi;
2429 else if (GET_CODE (left) == SIGN_EXTEND)
2430 *total = s390_cost->mh;
2431 else
2432 *total = s390_cost->ms; /* msr, ms, msy */
2433 break;
2434 }
2435 case DImode:
2436 {
2437 rtx left = XEXP (x, 0);
2438 rtx right = XEXP (x, 1);
2439 if (TARGET_ZARCH)
2440 {
2441 if (GET_CODE (right) == CONST_INT
2442 && CONST_OK_FOR_K (INTVAL (right)))
2443 *total = s390_cost->mghi;
2444 else if (GET_CODE (left) == SIGN_EXTEND)
2445 *total = s390_cost->msgf;
2446 else
2447 *total = s390_cost->msg; /* msgr, msg */
2448 }
2449 else /* TARGET_31BIT */
2450 {
2451 if (GET_CODE (left) == SIGN_EXTEND
2452 && GET_CODE (right) == SIGN_EXTEND)
2453 /* mulsidi case: mr, m */
2454 *total = s390_cost->m;
2455 else if (GET_CODE (left) == ZERO_EXTEND
2456 && GET_CODE (right) == ZERO_EXTEND
2457 && TARGET_CPU_ZARCH)
2458 /* umulsidi case: ml, mlr */
2459 *total = s390_cost->ml;
2460 else
2461 /* Complex calculation is required. */
2462 *total = COSTS_N_INSNS (40);
2463 }
2464 break;
2465 }
2466 case SFmode:
2467 case DFmode:
2468 *total = s390_cost->mult_df;
2469 break;
2470 case TFmode:
2471 *total = s390_cost->mxbr;
2472 break;
2473 default:
2474 return false;
2475 }
2476 return false;
2477
2478 case UDIV:
2479 case UMOD:
2480 if (GET_MODE (x) == TImode) /* 128 bit division */
2481 *total = s390_cost->dlgr;
2482 else if (GET_MODE (x) == DImode)
2483 {
2484 rtx right = XEXP (x, 1);
2485 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2486 *total = s390_cost->dlr;
2487 else /* 64 by 64 bit division */
2488 *total = s390_cost->dlgr;
2489 }
2490 else if (GET_MODE (x) == SImode) /* 32 bit division */
2491 *total = s390_cost->dlr;
2492 return false;
2493
2494 case DIV:
2495 case MOD:
2496 if (GET_MODE (x) == DImode)
2497 {
2498 rtx right = XEXP (x, 1);
2499 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2500 if (TARGET_ZARCH)
2501 *total = s390_cost->dsgfr;
2502 else
2503 *total = s390_cost->dr;
2504 else /* 64 by 64 bit division */
2505 *total = s390_cost->dsgr;
2506 }
2507 else if (GET_MODE (x) == SImode) /* 32 bit division */
2508 *total = s390_cost->dlr;
2509 else if (GET_MODE (x) == SFmode)
2510 {
2511 *total = s390_cost->debr;
2512 }
2513 else if (GET_MODE (x) == DFmode)
2514 {
2515 *total = s390_cost->ddbr;
2516 }
2517 else if (GET_MODE (x) == TFmode)
2518 {
2519 *total = s390_cost->dxbr;
2520 }
2521 return false;
2522
2523 case SQRT:
2524 if (GET_MODE (x) == SFmode)
2525 *total = s390_cost->sqebr;
2526 else if (GET_MODE (x) == DFmode)
2527 *total = s390_cost->sqdbr;
2528 else /* TFmode */
2529 *total = s390_cost->sqxbr;
2530 return false;
2531
2532 case SIGN_EXTEND:
2533 case ZERO_EXTEND:
2534 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2535 || outer_code == PLUS || outer_code == MINUS
2536 || outer_code == COMPARE)
2537 *total = 0;
2538 return false;
2539
2540 case COMPARE:
2541 *total = COSTS_N_INSNS (1);
2542 if (GET_CODE (XEXP (x, 0)) == AND
2543 && GET_CODE (XEXP (x, 1)) == CONST_INT
2544 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2545 {
2546 rtx op0 = XEXP (XEXP (x, 0), 0);
2547 rtx op1 = XEXP (XEXP (x, 0), 1);
2548 rtx op2 = XEXP (x, 1);
2549
2550 if (memory_operand (op0, GET_MODE (op0))
2551 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2552 return true;
2553 if (register_operand (op0, GET_MODE (op0))
2554 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2555 return true;
2556 }
2557 return false;
2558
2559 default:
2560 return false;
2561 }
2562 }
2563
2564 /* Return the cost of an address rtx ADDR. */
2565
2566 static int
2567 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2568 {
2569 struct s390_address ad;
2570 if (!s390_decompose_address (addr, &ad))
2571 return 1000;
2572
2573 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2574 }
2575
2576 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2577 otherwise return 0. */
2578
2579 int
2580 tls_symbolic_operand (rtx op)
2581 {
2582 if (GET_CODE (op) != SYMBOL_REF)
2583 return 0;
2584 return SYMBOL_REF_TLS_MODEL (op);
2585 }
2586 \f
2587 /* Split DImode access register reference REG (on 64-bit) into its constituent
2588 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2589 gen_highpart cannot be used as they assume all registers are word-sized,
2590 while our access registers have only half that size. */
2591
2592 void
2593 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2594 {
2595 gcc_assert (TARGET_64BIT);
2596 gcc_assert (ACCESS_REG_P (reg));
2597 gcc_assert (GET_MODE (reg) == DImode);
2598 gcc_assert (!(REGNO (reg) & 1));
2599
2600 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2601 *hi = gen_rtx_REG (SImode, REGNO (reg));
2602 }
2603
2604 /* Return true if OP contains a symbol reference */
2605
2606 bool
2607 symbolic_reference_mentioned_p (rtx op)
2608 {
2609 const char *fmt;
2610 int i;
2611
2612 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2613 return 1;
2614
2615 fmt = GET_RTX_FORMAT (GET_CODE (op));
2616 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2617 {
2618 if (fmt[i] == 'E')
2619 {
2620 int j;
2621
2622 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2623 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2624 return 1;
2625 }
2626
2627 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2628 return 1;
2629 }
2630
2631 return 0;
2632 }
2633
2634 /* Return true if OP contains a reference to a thread-local symbol. */
2635
2636 bool
2637 tls_symbolic_reference_mentioned_p (rtx op)
2638 {
2639 const char *fmt;
2640 int i;
2641
2642 if (GET_CODE (op) == SYMBOL_REF)
2643 return tls_symbolic_operand (op);
2644
2645 fmt = GET_RTX_FORMAT (GET_CODE (op));
2646 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2647 {
2648 if (fmt[i] == 'E')
2649 {
2650 int j;
2651
2652 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2653 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2654 return true;
2655 }
2656
2657 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2658 return true;
2659 }
2660
2661 return false;
2662 }
2663
2664
2665 /* Return true if OP is a legitimate general operand when
2666 generating PIC code. It is given that flag_pic is on
2667 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2668
2669 int
2670 legitimate_pic_operand_p (rtx op)
2671 {
2672 /* Accept all non-symbolic constants. */
2673 if (!SYMBOLIC_CONST (op))
2674 return 1;
2675
2676 /* Reject everything else; must be handled
2677 via emit_symbolic_move. */
2678 return 0;
2679 }
2680
2681 /* Returns true if the constant value OP is a legitimate general operand.
2682 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2683
2684 int
2685 legitimate_constant_p (rtx op)
2686 {
2687 /* Accept all non-symbolic constants. */
2688 if (!SYMBOLIC_CONST (op))
2689 return 1;
2690
2691 /* Accept immediate LARL operands. */
2692 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2693 return 1;
2694
2695 /* Thread-local symbols are never legal constants. This is
2696 so that emit_call knows that computing such addresses
2697 might require a function call. */
2698 if (TLS_SYMBOLIC_CONST (op))
2699 return 0;
2700
2701 /* In the PIC case, symbolic constants must *not* be
2702 forced into the literal pool. We accept them here,
2703 so that they will be handled by emit_symbolic_move. */
2704 if (flag_pic)
2705 return 1;
2706
2707 /* All remaining non-PIC symbolic constants are
2708 forced into the literal pool. */
2709 return 0;
2710 }
2711
2712 /* Determine if it's legal to put X into the constant pool. This
2713 is not possible if X contains the address of a symbol that is
2714 not constant (TLS) or not known at final link time (PIC). */
2715
2716 static bool
2717 s390_cannot_force_const_mem (rtx x)
2718 {
2719 switch (GET_CODE (x))
2720 {
2721 case CONST_INT:
2722 case CONST_DOUBLE:
2723 /* Accept all non-symbolic constants. */
2724 return false;
2725
2726 case LABEL_REF:
2727 /* Labels are OK iff we are non-PIC. */
2728 return flag_pic != 0;
2729
2730 case SYMBOL_REF:
2731 /* 'Naked' TLS symbol references are never OK,
2732 non-TLS symbols are OK iff we are non-PIC. */
2733 if (tls_symbolic_operand (x))
2734 return true;
2735 else
2736 return flag_pic != 0;
2737
2738 case CONST:
2739 return s390_cannot_force_const_mem (XEXP (x, 0));
2740 case PLUS:
2741 case MINUS:
2742 return s390_cannot_force_const_mem (XEXP (x, 0))
2743 || s390_cannot_force_const_mem (XEXP (x, 1));
2744
2745 case UNSPEC:
2746 switch (XINT (x, 1))
2747 {
2748 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2749 case UNSPEC_LTREL_OFFSET:
2750 case UNSPEC_GOT:
2751 case UNSPEC_GOTOFF:
2752 case UNSPEC_PLTOFF:
2753 case UNSPEC_TLSGD:
2754 case UNSPEC_TLSLDM:
2755 case UNSPEC_NTPOFF:
2756 case UNSPEC_DTPOFF:
2757 case UNSPEC_GOTNTPOFF:
2758 case UNSPEC_INDNTPOFF:
2759 return false;
2760
2761 /* If the literal pool shares the code section, be put
2762 execute template placeholders into the pool as well. */
2763 case UNSPEC_INSN:
2764 return TARGET_CPU_ZARCH;
2765
2766 default:
2767 return true;
2768 }
2769 break;
2770
2771 default:
2772 gcc_unreachable ();
2773 }
2774 }
2775
2776 /* Returns true if the constant value OP is a legitimate general
2777 operand during and after reload. The difference to
2778 legitimate_constant_p is that this function will not accept
2779 a constant that would need to be forced to the literal pool
2780 before it can be used as operand. */
2781
2782 bool
2783 legitimate_reload_constant_p (rtx op)
2784 {
2785 /* Accept la(y) operands. */
2786 if (GET_CODE (op) == CONST_INT
2787 && DISP_IN_RANGE (INTVAL (op)))
2788 return true;
2789
2790 /* Accept l(g)hi/l(g)fi operands. */
2791 if (GET_CODE (op) == CONST_INT
2792 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2793 return true;
2794
2795 /* Accept lliXX operands. */
2796 if (TARGET_ZARCH
2797 && GET_CODE (op) == CONST_INT
2798 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2799 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2800 return true;
2801
2802 if (TARGET_EXTIMM
2803 && GET_CODE (op) == CONST_INT
2804 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2805 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2806 return true;
2807
2808 /* Accept larl operands. */
2809 if (TARGET_CPU_ZARCH
2810 && larl_operand (op, VOIDmode))
2811 return true;
2812
2813 /* Accept double-word operands that can be split. */
2814 if (GET_CODE (op) == CONST_INT
2815 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2816 {
2817 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2818 rtx hi = operand_subword (op, 0, 0, dword_mode);
2819 rtx lo = operand_subword (op, 1, 0, dword_mode);
2820 return legitimate_reload_constant_p (hi)
2821 && legitimate_reload_constant_p (lo);
2822 }
2823
2824 /* Everything else cannot be handled without reload. */
2825 return false;
2826 }
2827
2828 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2829 return the class of reg to actually use. */
2830
2831 enum reg_class
2832 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2833 {
2834 switch (GET_CODE (op))
2835 {
2836 /* Constants we cannot reload must be forced into the
2837 literal pool. */
2838
2839 case CONST_DOUBLE:
2840 case CONST_INT:
2841 if (legitimate_reload_constant_p (op))
2842 return rclass;
2843 else
2844 return NO_REGS;
2845
2846 /* If a symbolic constant or a PLUS is reloaded,
2847 it is most likely being used as an address, so
2848 prefer ADDR_REGS. If 'class' is not a superset
2849 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2850 case PLUS:
2851 case LABEL_REF:
2852 case SYMBOL_REF:
2853 case CONST:
2854 if (reg_class_subset_p (ADDR_REGS, rclass))
2855 return ADDR_REGS;
2856 else
2857 return NO_REGS;
2858
2859 default:
2860 break;
2861 }
2862
2863 return rclass;
2864 }
2865
2866 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2867 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2868 aligned. */
2869
2870 bool
2871 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2872 {
2873 HOST_WIDE_INT addend;
2874 rtx symref;
2875
2876 if (!s390_symref_operand_p (addr, &symref, &addend))
2877 return false;
2878
2879 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2880 && !(addend & (alignment - 1)));
2881 }
2882
2883 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2884 operand SCRATCH is used to reload the even part of the address and
2885 adding one. */
2886
2887 void
2888 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2889 {
2890 HOST_WIDE_INT addend;
2891 rtx symref;
2892
2893 if (!s390_symref_operand_p (addr, &symref, &addend))
2894 gcc_unreachable ();
2895
2896 if (!(addend & 1))
2897 /* Easy case. The addend is even so larl will do fine. */
2898 emit_move_insn (reg, addr);
2899 else
2900 {
2901 /* We can leave the scratch register untouched if the target
2902 register is a valid base register. */
2903 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2904 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2905 scratch = reg;
2906
2907 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2908 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2909
2910 if (addend != 1)
2911 emit_move_insn (scratch,
2912 gen_rtx_CONST (Pmode,
2913 gen_rtx_PLUS (Pmode, symref,
2914 GEN_INT (addend - 1))));
2915 else
2916 emit_move_insn (scratch, symref);
2917
2918 /* Increment the address using la in order to avoid clobbering cc. */
2919 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2920 }
2921 }
2922
2923 /* Generate what is necessary to move between REG and MEM using
2924 SCRATCH. The direction is given by TOMEM. */
2925
2926 void
2927 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2928 {
2929 /* Reload might have pulled a constant out of the literal pool.
2930 Force it back in. */
2931 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2932 || GET_CODE (mem) == CONST)
2933 mem = force_const_mem (GET_MODE (reg), mem);
2934
2935 gcc_assert (MEM_P (mem));
2936
2937 /* For a load from memory we can leave the scratch register
2938 untouched if the target register is a valid base register. */
2939 if (!tomem
2940 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2941 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2942 && GET_MODE (reg) == GET_MODE (scratch))
2943 scratch = reg;
2944
2945 /* Load address into scratch register. Since we can't have a
2946 secondary reload for a secondary reload we have to cover the case
2947 where larl would need a secondary reload here as well. */
2948 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2949
2950 /* Now we can use a standard load/store to do the move. */
2951 if (tomem)
2952 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2953 else
2954 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2955 }
2956
2957 /* Inform reload about cases where moving X with a mode MODE to a register in
2958 RCLASS requires an extra scratch or immediate register. Return the class
2959 needed for the immediate register. */
2960
2961 static reg_class_t
2962 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
2963 enum machine_mode mode, secondary_reload_info *sri)
2964 {
2965 enum reg_class rclass = (enum reg_class) rclass_i;
2966
2967 /* Intermediate register needed. */
2968 if (reg_classes_intersect_p (CC_REGS, rclass))
2969 return GENERAL_REGS;
2970
2971 if (TARGET_Z10)
2972 {
2973 /* On z10 several optimizer steps may generate larl operands with
2974 an odd addend. */
2975 if (in_p
2976 && s390_symref_operand_p (x, NULL, NULL)
2977 && mode == Pmode
2978 && !s390_check_symref_alignment (x, 2))
2979 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2980 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2981
2982 /* On z10 we need a scratch register when moving QI, TI or floating
2983 point mode values from or to a memory location with a SYMBOL_REF
2984 or if the symref addend of a SI or DI move is not aligned to the
2985 width of the access. */
2986 if (MEM_P (x)
2987 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2988 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2989 || (!TARGET_ZARCH && mode == DImode)
2990 || ((mode == HImode || mode == SImode || mode == DImode)
2991 && (!s390_check_symref_alignment (XEXP (x, 0),
2992 GET_MODE_SIZE (mode))))))
2993 {
2994 #define __SECONDARY_RELOAD_CASE(M,m) \
2995 case M##mode: \
2996 if (TARGET_64BIT) \
2997 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2998 CODE_FOR_reload##m##di_tomem_z10; \
2999 else \
3000 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3001 CODE_FOR_reload##m##si_tomem_z10; \
3002 break;
3003
3004 switch (GET_MODE (x))
3005 {
3006 __SECONDARY_RELOAD_CASE (QI, qi);
3007 __SECONDARY_RELOAD_CASE (HI, hi);
3008 __SECONDARY_RELOAD_CASE (SI, si);
3009 __SECONDARY_RELOAD_CASE (DI, di);
3010 __SECONDARY_RELOAD_CASE (TI, ti);
3011 __SECONDARY_RELOAD_CASE (SF, sf);
3012 __SECONDARY_RELOAD_CASE (DF, df);
3013 __SECONDARY_RELOAD_CASE (TF, tf);
3014 __SECONDARY_RELOAD_CASE (SD, sd);
3015 __SECONDARY_RELOAD_CASE (DD, dd);
3016 __SECONDARY_RELOAD_CASE (TD, td);
3017
3018 default:
3019 gcc_unreachable ();
3020 }
3021 #undef __SECONDARY_RELOAD_CASE
3022 }
3023 }
3024
3025 /* We need a scratch register when loading a PLUS expression which
3026 is not a legitimate operand of the LOAD ADDRESS instruction. */
3027 if (in_p && s390_plus_operand (x, mode))
3028 sri->icode = (TARGET_64BIT ?
3029 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3030
3031 /* Performing a multiword move from or to memory we have to make sure the
3032 second chunk in memory is addressable without causing a displacement
3033 overflow. If that would be the case we calculate the address in
3034 a scratch register. */
3035 if (MEM_P (x)
3036 && GET_CODE (XEXP (x, 0)) == PLUS
3037 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3038 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3039 + GET_MODE_SIZE (mode) - 1))
3040 {
3041 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3042 in a s_operand address since we may fallback to lm/stm. So we only
3043 have to care about overflows in the b+i+d case. */
3044 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3045 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3046 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3047 /* For FP_REGS no lm/stm is available so this check is triggered
3048 for displacement overflows in b+i+d and b+d like addresses. */
3049 || (reg_classes_intersect_p (FP_REGS, rclass)
3050 && s390_class_max_nregs (FP_REGS, mode) > 1))
3051 {
3052 if (in_p)
3053 sri->icode = (TARGET_64BIT ?
3054 CODE_FOR_reloaddi_nonoffmem_in :
3055 CODE_FOR_reloadsi_nonoffmem_in);
3056 else
3057 sri->icode = (TARGET_64BIT ?
3058 CODE_FOR_reloaddi_nonoffmem_out :
3059 CODE_FOR_reloadsi_nonoffmem_out);
3060 }
3061 }
3062
3063 /* A scratch address register is needed when a symbolic constant is
3064 copied to r0 compiling with -fPIC. In other cases the target
3065 register might be used as temporary (see legitimize_pic_address). */
3066 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3067 sri->icode = (TARGET_64BIT ?
3068 CODE_FOR_reloaddi_PIC_addr :
3069 CODE_FOR_reloadsi_PIC_addr);
3070
3071 /* Either scratch or no register needed. */
3072 return NO_REGS;
3073 }
3074
3075 /* Generate code to load SRC, which is PLUS that is not a
3076 legitimate operand for the LA instruction, into TARGET.
3077 SCRATCH may be used as scratch register. */
3078
3079 void
3080 s390_expand_plus_operand (rtx target, rtx src,
3081 rtx scratch)
3082 {
3083 rtx sum1, sum2;
3084 struct s390_address ad;
3085
3086 /* src must be a PLUS; get its two operands. */
3087 gcc_assert (GET_CODE (src) == PLUS);
3088 gcc_assert (GET_MODE (src) == Pmode);
3089
3090 /* Check if any of the two operands is already scheduled
3091 for replacement by reload. This can happen e.g. when
3092 float registers occur in an address. */
3093 sum1 = find_replacement (&XEXP (src, 0));
3094 sum2 = find_replacement (&XEXP (src, 1));
3095 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3096
3097 /* If the address is already strictly valid, there's nothing to do. */
3098 if (!s390_decompose_address (src, &ad)
3099 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3100 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3101 {
3102 /* Otherwise, one of the operands cannot be an address register;
3103 we reload its value into the scratch register. */
3104 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3105 {
3106 emit_move_insn (scratch, sum1);
3107 sum1 = scratch;
3108 }
3109 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3110 {
3111 emit_move_insn (scratch, sum2);
3112 sum2 = scratch;
3113 }
3114
3115 /* According to the way these invalid addresses are generated
3116 in reload.c, it should never happen (at least on s390) that
3117 *neither* of the PLUS components, after find_replacements
3118 was applied, is an address register. */
3119 if (sum1 == scratch && sum2 == scratch)
3120 {
3121 debug_rtx (src);
3122 gcc_unreachable ();
3123 }
3124
3125 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3126 }
3127
3128 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3129 is only ever performed on addresses, so we can mark the
3130 sum as legitimate for LA in any case. */
3131 s390_load_address (target, src);
3132 }
3133
3134
3135 /* Return true if ADDR is a valid memory address.
3136 STRICT specifies whether strict register checking applies. */
3137
3138 static bool
3139 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3140 {
3141 struct s390_address ad;
3142
3143 if (TARGET_Z10
3144 && larl_operand (addr, VOIDmode)
3145 && (mode == VOIDmode
3146 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3147 return true;
3148
3149 if (!s390_decompose_address (addr, &ad))
3150 return false;
3151
3152 if (strict)
3153 {
3154 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3155 return false;
3156
3157 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3158 return false;
3159 }
3160 else
3161 {
3162 if (ad.base
3163 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3164 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3165 return false;
3166
3167 if (ad.indx
3168 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3169 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3170 return false;
3171 }
3172 return true;
3173 }
3174
3175 /* Return true if OP is a valid operand for the LA instruction.
3176 In 31-bit, we need to prove that the result is used as an
3177 address, as LA performs only a 31-bit addition. */
3178
3179 bool
3180 legitimate_la_operand_p (rtx op)
3181 {
3182 struct s390_address addr;
3183 if (!s390_decompose_address (op, &addr))
3184 return false;
3185
3186 return (TARGET_64BIT || addr.pointer);
3187 }
3188
3189 /* Return true if it is valid *and* preferable to use LA to
3190 compute the sum of OP1 and OP2. */
3191
3192 bool
3193 preferred_la_operand_p (rtx op1, rtx op2)
3194 {
3195 struct s390_address addr;
3196
3197 if (op2 != const0_rtx)
3198 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3199
3200 if (!s390_decompose_address (op1, &addr))
3201 return false;
3202 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3203 return false;
3204 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3205 return false;
3206
3207 if (!TARGET_64BIT && !addr.pointer)
3208 return false;
3209
3210 if (addr.pointer)
3211 return true;
3212
3213 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3214 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3215 return true;
3216
3217 return false;
3218 }
3219
3220 /* Emit a forced load-address operation to load SRC into DST.
3221 This will use the LOAD ADDRESS instruction even in situations
3222 where legitimate_la_operand_p (SRC) returns false. */
3223
3224 void
3225 s390_load_address (rtx dst, rtx src)
3226 {
3227 if (TARGET_64BIT)
3228 emit_move_insn (dst, src);
3229 else
3230 emit_insn (gen_force_la_31 (dst, src));
3231 }
3232
3233 /* Return a legitimate reference for ORIG (an address) using the
3234 register REG. If REG is 0, a new pseudo is generated.
3235
3236 There are two types of references that must be handled:
3237
3238 1. Global data references must load the address from the GOT, via
3239 the PIC reg. An insn is emitted to do this load, and the reg is
3240 returned.
3241
3242 2. Static data references, constant pool addresses, and code labels
3243 compute the address as an offset from the GOT, whose base is in
3244 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3245 differentiate them from global data objects. The returned
3246 address is the PIC reg + an unspec constant.
3247
3248 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3249 reg also appears in the address. */
3250
3251 rtx
3252 legitimize_pic_address (rtx orig, rtx reg)
3253 {
3254 rtx addr = orig;
3255 rtx new_rtx = orig;
3256 rtx base;
3257
3258 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3259
3260 if (GET_CODE (addr) == LABEL_REF
3261 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3262 {
3263 /* This is a local symbol. */
3264 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3265 {
3266 /* Access local symbols PC-relative via LARL.
3267 This is the same as in the non-PIC case, so it is
3268 handled automatically ... */
3269 }
3270 else
3271 {
3272 /* Access local symbols relative to the GOT. */
3273
3274 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3275
3276 if (reload_in_progress || reload_completed)
3277 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3278
3279 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3280 addr = gen_rtx_CONST (Pmode, addr);
3281 addr = force_const_mem (Pmode, addr);
3282 emit_move_insn (temp, addr);
3283
3284 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3285 if (reg != 0)
3286 {
3287 s390_load_address (reg, new_rtx);
3288 new_rtx = reg;
3289 }
3290 }
3291 }
3292 else if (GET_CODE (addr) == SYMBOL_REF)
3293 {
3294 if (reg == 0)
3295 reg = gen_reg_rtx (Pmode);
3296
3297 if (flag_pic == 1)
3298 {
3299 /* Assume GOT offset < 4k. This is handled the same way
3300 in both 31- and 64-bit code (@GOT). */
3301
3302 if (reload_in_progress || reload_completed)
3303 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3304
3305 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3306 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3307 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3308 new_rtx = gen_const_mem (Pmode, new_rtx);
3309 emit_move_insn (reg, new_rtx);
3310 new_rtx = reg;
3311 }
3312 else if (TARGET_CPU_ZARCH)
3313 {
3314 /* If the GOT offset might be >= 4k, we determine the position
3315 of the GOT entry via a PC-relative LARL (@GOTENT). */
3316
3317 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3318
3319 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3320 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3321
3322 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3323 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3324 emit_move_insn (temp, new_rtx);
3325
3326 new_rtx = gen_const_mem (Pmode, temp);
3327 emit_move_insn (reg, new_rtx);
3328 new_rtx = reg;
3329 }
3330 else
3331 {
3332 /* If the GOT offset might be >= 4k, we have to load it
3333 from the literal pool (@GOT). */
3334
3335 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3336
3337 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3338 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3339
3340 if (reload_in_progress || reload_completed)
3341 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3342
3343 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3344 addr = gen_rtx_CONST (Pmode, addr);
3345 addr = force_const_mem (Pmode, addr);
3346 emit_move_insn (temp, addr);
3347
3348 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3349 new_rtx = gen_const_mem (Pmode, new_rtx);
3350 emit_move_insn (reg, new_rtx);
3351 new_rtx = reg;
3352 }
3353 }
3354 else
3355 {
3356 if (GET_CODE (addr) == CONST)
3357 {
3358 addr = XEXP (addr, 0);
3359 if (GET_CODE (addr) == UNSPEC)
3360 {
3361 gcc_assert (XVECLEN (addr, 0) == 1);
3362 switch (XINT (addr, 1))
3363 {
3364 /* If someone moved a GOT-relative UNSPEC
3365 out of the literal pool, force them back in. */
3366 case UNSPEC_GOTOFF:
3367 case UNSPEC_PLTOFF:
3368 new_rtx = force_const_mem (Pmode, orig);
3369 break;
3370
3371 /* @GOT is OK as is if small. */
3372 case UNSPEC_GOT:
3373 if (flag_pic == 2)
3374 new_rtx = force_const_mem (Pmode, orig);
3375 break;
3376
3377 /* @GOTENT is OK as is. */
3378 case UNSPEC_GOTENT:
3379 break;
3380
3381 /* @PLT is OK as is on 64-bit, must be converted to
3382 GOT-relative @PLTOFF on 31-bit. */
3383 case UNSPEC_PLT:
3384 if (!TARGET_CPU_ZARCH)
3385 {
3386 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3387
3388 if (reload_in_progress || reload_completed)
3389 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3390
3391 addr = XVECEXP (addr, 0, 0);
3392 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3393 UNSPEC_PLTOFF);
3394 addr = gen_rtx_CONST (Pmode, addr);
3395 addr = force_const_mem (Pmode, addr);
3396 emit_move_insn (temp, addr);
3397
3398 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3399 if (reg != 0)
3400 {
3401 s390_load_address (reg, new_rtx);
3402 new_rtx = reg;
3403 }
3404 }
3405 break;
3406
3407 /* Everything else cannot happen. */
3408 default:
3409 gcc_unreachable ();
3410 }
3411 }
3412 else
3413 gcc_assert (GET_CODE (addr) == PLUS);
3414 }
3415 if (GET_CODE (addr) == PLUS)
3416 {
3417 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3418
3419 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3420 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3421
3422 /* Check first to see if this is a constant offset
3423 from a local symbol reference. */
3424 if ((GET_CODE (op0) == LABEL_REF
3425 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3426 && GET_CODE (op1) == CONST_INT)
3427 {
3428 if (TARGET_CPU_ZARCH
3429 && larl_operand (op0, VOIDmode)
3430 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3431 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3432 {
3433 if (INTVAL (op1) & 1)
3434 {
3435 /* LARL can't handle odd offsets, so emit a
3436 pair of LARL and LA. */
3437 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3438
3439 if (!DISP_IN_RANGE (INTVAL (op1)))
3440 {
3441 HOST_WIDE_INT even = INTVAL (op1) - 1;
3442 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3443 op0 = gen_rtx_CONST (Pmode, op0);
3444 op1 = const1_rtx;
3445 }
3446
3447 emit_move_insn (temp, op0);
3448 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3449
3450 if (reg != 0)
3451 {
3452 s390_load_address (reg, new_rtx);
3453 new_rtx = reg;
3454 }
3455 }
3456 else
3457 {
3458 /* If the offset is even, we can just use LARL.
3459 This will happen automatically. */
3460 }
3461 }
3462 else
3463 {
3464 /* Access local symbols relative to the GOT. */
3465
3466 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3467
3468 if (reload_in_progress || reload_completed)
3469 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3470
3471 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3472 UNSPEC_GOTOFF);
3473 addr = gen_rtx_PLUS (Pmode, addr, op1);
3474 addr = gen_rtx_CONST (Pmode, addr);
3475 addr = force_const_mem (Pmode, addr);
3476 emit_move_insn (temp, addr);
3477
3478 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3479 if (reg != 0)
3480 {
3481 s390_load_address (reg, new_rtx);
3482 new_rtx = reg;
3483 }
3484 }
3485 }
3486
3487 /* Now, check whether it is a GOT relative symbol plus offset
3488 that was pulled out of the literal pool. Force it back in. */
3489
3490 else if (GET_CODE (op0) == UNSPEC
3491 && GET_CODE (op1) == CONST_INT
3492 && XINT (op0, 1) == UNSPEC_GOTOFF)
3493 {
3494 gcc_assert (XVECLEN (op0, 0) == 1);
3495
3496 new_rtx = force_const_mem (Pmode, orig);
3497 }
3498
3499 /* Otherwise, compute the sum. */
3500 else
3501 {
3502 base = legitimize_pic_address (XEXP (addr, 0), reg);
3503 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3504 base == reg ? NULL_RTX : reg);
3505 if (GET_CODE (new_rtx) == CONST_INT)
3506 new_rtx = plus_constant (base, INTVAL (new_rtx));
3507 else
3508 {
3509 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3510 {
3511 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3512 new_rtx = XEXP (new_rtx, 1);
3513 }
3514 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3515 }
3516
3517 if (GET_CODE (new_rtx) == CONST)
3518 new_rtx = XEXP (new_rtx, 0);
3519 new_rtx = force_operand (new_rtx, 0);
3520 }
3521 }
3522 }
3523 return new_rtx;
3524 }
3525
3526 /* Load the thread pointer into a register. */
3527
3528 rtx
3529 s390_get_thread_pointer (void)
3530 {
3531 rtx tp = gen_reg_rtx (Pmode);
3532
3533 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3534 mark_reg_pointer (tp, BITS_PER_WORD);
3535
3536 return tp;
3537 }
3538
3539 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3540 in s390_tls_symbol which always refers to __tls_get_offset.
3541 The returned offset is written to RESULT_REG and an USE rtx is
3542 generated for TLS_CALL. */
3543
3544 static GTY(()) rtx s390_tls_symbol;
3545
3546 static void
3547 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3548 {
3549 rtx insn;
3550
3551 gcc_assert (flag_pic);
3552
3553 if (!s390_tls_symbol)
3554 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3555
3556 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3557 gen_rtx_REG (Pmode, RETURN_REGNUM));
3558
3559 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3560 RTL_CONST_CALL_P (insn) = 1;
3561 }
3562
3563 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3564 this (thread-local) address. REG may be used as temporary. */
3565
3566 static rtx
3567 legitimize_tls_address (rtx addr, rtx reg)
3568 {
3569 rtx new_rtx, tls_call, temp, base, r2, insn;
3570
3571 if (GET_CODE (addr) == SYMBOL_REF)
3572 switch (tls_symbolic_operand (addr))
3573 {
3574 case TLS_MODEL_GLOBAL_DYNAMIC:
3575 start_sequence ();
3576 r2 = gen_rtx_REG (Pmode, 2);
3577 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3578 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3579 new_rtx = force_const_mem (Pmode, new_rtx);
3580 emit_move_insn (r2, new_rtx);
3581 s390_emit_tls_call_insn (r2, tls_call);
3582 insn = get_insns ();
3583 end_sequence ();
3584
3585 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3586 temp = gen_reg_rtx (Pmode);
3587 emit_libcall_block (insn, temp, r2, new_rtx);
3588
3589 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3590 if (reg != 0)
3591 {
3592 s390_load_address (reg, new_rtx);
3593 new_rtx = reg;
3594 }
3595 break;
3596
3597 case TLS_MODEL_LOCAL_DYNAMIC:
3598 start_sequence ();
3599 r2 = gen_rtx_REG (Pmode, 2);
3600 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3601 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3602 new_rtx = force_const_mem (Pmode, new_rtx);
3603 emit_move_insn (r2, new_rtx);
3604 s390_emit_tls_call_insn (r2, tls_call);
3605 insn = get_insns ();
3606 end_sequence ();
3607
3608 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3609 temp = gen_reg_rtx (Pmode);
3610 emit_libcall_block (insn, temp, r2, new_rtx);
3611
3612 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3613 base = gen_reg_rtx (Pmode);
3614 s390_load_address (base, new_rtx);
3615
3616 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3617 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3618 new_rtx = force_const_mem (Pmode, new_rtx);
3619 temp = gen_reg_rtx (Pmode);
3620 emit_move_insn (temp, new_rtx);
3621
3622 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3623 if (reg != 0)
3624 {
3625 s390_load_address (reg, new_rtx);
3626 new_rtx = reg;
3627 }
3628 break;
3629
3630 case TLS_MODEL_INITIAL_EXEC:
3631 if (flag_pic == 1)
3632 {
3633 /* Assume GOT offset < 4k. This is handled the same way
3634 in both 31- and 64-bit code. */
3635
3636 if (reload_in_progress || reload_completed)
3637 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3638
3639 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3640 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3641 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3642 new_rtx = gen_const_mem (Pmode, new_rtx);
3643 temp = gen_reg_rtx (Pmode);
3644 emit_move_insn (temp, new_rtx);
3645 }
3646 else if (TARGET_CPU_ZARCH)
3647 {
3648 /* If the GOT offset might be >= 4k, we determine the position
3649 of the GOT entry via a PC-relative LARL. */
3650
3651 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3652 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3653 temp = gen_reg_rtx (Pmode);
3654 emit_move_insn (temp, new_rtx);
3655
3656 new_rtx = gen_const_mem (Pmode, temp);
3657 temp = gen_reg_rtx (Pmode);
3658 emit_move_insn (temp, new_rtx);
3659 }
3660 else if (flag_pic)
3661 {
3662 /* If the GOT offset might be >= 4k, we have to load it
3663 from the literal pool. */
3664
3665 if (reload_in_progress || reload_completed)
3666 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3667
3668 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3669 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3670 new_rtx = force_const_mem (Pmode, new_rtx);
3671 temp = gen_reg_rtx (Pmode);
3672 emit_move_insn (temp, new_rtx);
3673
3674 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3675 new_rtx = gen_const_mem (Pmode, new_rtx);
3676
3677 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3678 temp = gen_reg_rtx (Pmode);
3679 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3680 }
3681 else
3682 {
3683 /* In position-dependent code, load the absolute address of
3684 the GOT entry from the literal pool. */
3685
3686 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3687 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3688 new_rtx = force_const_mem (Pmode, new_rtx);
3689 temp = gen_reg_rtx (Pmode);
3690 emit_move_insn (temp, new_rtx);
3691
3692 new_rtx = temp;
3693 new_rtx = gen_const_mem (Pmode, new_rtx);
3694 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3695 temp = gen_reg_rtx (Pmode);
3696 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3697 }
3698
3699 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3700 if (reg != 0)
3701 {
3702 s390_load_address (reg, new_rtx);
3703 new_rtx = reg;
3704 }
3705 break;
3706
3707 case TLS_MODEL_LOCAL_EXEC:
3708 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3709 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3710 new_rtx = force_const_mem (Pmode, new_rtx);
3711 temp = gen_reg_rtx (Pmode);
3712 emit_move_insn (temp, new_rtx);
3713
3714 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3715 if (reg != 0)
3716 {
3717 s390_load_address (reg, new_rtx);
3718 new_rtx = reg;
3719 }
3720 break;
3721
3722 default:
3723 gcc_unreachable ();
3724 }
3725
3726 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3727 {
3728 switch (XINT (XEXP (addr, 0), 1))
3729 {
3730 case UNSPEC_INDNTPOFF:
3731 gcc_assert (TARGET_CPU_ZARCH);
3732 new_rtx = addr;
3733 break;
3734
3735 default:
3736 gcc_unreachable ();
3737 }
3738 }
3739
3740 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3741 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3742 {
3743 new_rtx = XEXP (XEXP (addr, 0), 0);
3744 if (GET_CODE (new_rtx) != SYMBOL_REF)
3745 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3746
3747 new_rtx = legitimize_tls_address (new_rtx, reg);
3748 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3749 new_rtx = force_operand (new_rtx, 0);
3750 }
3751
3752 else
3753 gcc_unreachable (); /* for now ... */
3754
3755 return new_rtx;
3756 }
3757
3758 /* Emit insns making the address in operands[1] valid for a standard
3759 move to operands[0]. operands[1] is replaced by an address which
3760 should be used instead of the former RTX to emit the move
3761 pattern. */
3762
3763 void
3764 emit_symbolic_move (rtx *operands)
3765 {
3766 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3767
3768 if (GET_CODE (operands[0]) == MEM)
3769 operands[1] = force_reg (Pmode, operands[1]);
3770 else if (TLS_SYMBOLIC_CONST (operands[1]))
3771 operands[1] = legitimize_tls_address (operands[1], temp);
3772 else if (flag_pic)
3773 operands[1] = legitimize_pic_address (operands[1], temp);
3774 }
3775
3776 /* Try machine-dependent ways of modifying an illegitimate address X
3777 to be legitimate. If we find one, return the new, valid address.
3778
3779 OLDX is the address as it was before break_out_memory_refs was called.
3780 In some cases it is useful to look at this to decide what needs to be done.
3781
3782 MODE is the mode of the operand pointed to by X.
3783
3784 When -fpic is used, special handling is needed for symbolic references.
3785 See comments by legitimize_pic_address for details. */
3786
3787 static rtx
3788 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3789 enum machine_mode mode ATTRIBUTE_UNUSED)
3790 {
3791 rtx constant_term = const0_rtx;
3792
3793 if (TLS_SYMBOLIC_CONST (x))
3794 {
3795 x = legitimize_tls_address (x, 0);
3796
3797 if (s390_legitimate_address_p (mode, x, FALSE))
3798 return x;
3799 }
3800 else if (GET_CODE (x) == PLUS
3801 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3802 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3803 {
3804 return x;
3805 }
3806 else if (flag_pic)
3807 {
3808 if (SYMBOLIC_CONST (x)
3809 || (GET_CODE (x) == PLUS
3810 && (SYMBOLIC_CONST (XEXP (x, 0))
3811 || SYMBOLIC_CONST (XEXP (x, 1)))))
3812 x = legitimize_pic_address (x, 0);
3813
3814 if (s390_legitimate_address_p (mode, x, FALSE))
3815 return x;
3816 }
3817
3818 x = eliminate_constant_term (x, &constant_term);
3819
3820 /* Optimize loading of large displacements by splitting them
3821 into the multiple of 4K and the rest; this allows the
3822 former to be CSE'd if possible.
3823
3824 Don't do this if the displacement is added to a register
3825 pointing into the stack frame, as the offsets will
3826 change later anyway. */
3827
3828 if (GET_CODE (constant_term) == CONST_INT
3829 && !TARGET_LONG_DISPLACEMENT
3830 && !DISP_IN_RANGE (INTVAL (constant_term))
3831 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3832 {
3833 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3834 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3835
3836 rtx temp = gen_reg_rtx (Pmode);
3837 rtx val = force_operand (GEN_INT (upper), temp);
3838 if (val != temp)
3839 emit_move_insn (temp, val);
3840
3841 x = gen_rtx_PLUS (Pmode, x, temp);
3842 constant_term = GEN_INT (lower);
3843 }
3844
3845 if (GET_CODE (x) == PLUS)
3846 {
3847 if (GET_CODE (XEXP (x, 0)) == REG)
3848 {
3849 rtx temp = gen_reg_rtx (Pmode);
3850 rtx val = force_operand (XEXP (x, 1), temp);
3851 if (val != temp)
3852 emit_move_insn (temp, val);
3853
3854 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3855 }
3856
3857 else if (GET_CODE (XEXP (x, 1)) == REG)
3858 {
3859 rtx temp = gen_reg_rtx (Pmode);
3860 rtx val = force_operand (XEXP (x, 0), temp);
3861 if (val != temp)
3862 emit_move_insn (temp, val);
3863
3864 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3865 }
3866 }
3867
3868 if (constant_term != const0_rtx)
3869 x = gen_rtx_PLUS (Pmode, x, constant_term);
3870
3871 return x;
3872 }
3873
3874 /* Try a machine-dependent way of reloading an illegitimate address AD
3875 operand. If we find one, push the reload and and return the new address.
3876
3877 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3878 and TYPE is the reload type of the current reload. */
3879
3880 rtx
3881 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3882 int opnum, int type)
3883 {
3884 if (!optimize || TARGET_LONG_DISPLACEMENT)
3885 return NULL_RTX;
3886
3887 if (GET_CODE (ad) == PLUS)
3888 {
3889 rtx tem = simplify_binary_operation (PLUS, Pmode,
3890 XEXP (ad, 0), XEXP (ad, 1));
3891 if (tem)
3892 ad = tem;
3893 }
3894
3895 if (GET_CODE (ad) == PLUS
3896 && GET_CODE (XEXP (ad, 0)) == REG
3897 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3898 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3899 {
3900 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3901 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3902 rtx cst, tem, new_rtx;
3903
3904 cst = GEN_INT (upper);
3905 if (!legitimate_reload_constant_p (cst))
3906 cst = force_const_mem (Pmode, cst);
3907
3908 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3909 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3910
3911 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3912 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3913 opnum, (enum reload_type) type);
3914 return new_rtx;
3915 }
3916
3917 return NULL_RTX;
3918 }
3919
3920 /* Emit code to move LEN bytes from DST to SRC. */
3921
3922 void
3923 s390_expand_movmem (rtx dst, rtx src, rtx len)
3924 {
3925 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3926 {
3927 if (INTVAL (len) > 0)
3928 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3929 }
3930
3931 else if (TARGET_MVCLE)
3932 {
3933 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3934 }
3935
3936 else
3937 {
3938 rtx dst_addr, src_addr, count, blocks, temp;
3939 rtx loop_start_label = gen_label_rtx ();
3940 rtx loop_end_label = gen_label_rtx ();
3941 rtx end_label = gen_label_rtx ();
3942 enum machine_mode mode;
3943
3944 mode = GET_MODE (len);
3945 if (mode == VOIDmode)
3946 mode = Pmode;
3947
3948 dst_addr = gen_reg_rtx (Pmode);
3949 src_addr = gen_reg_rtx (Pmode);
3950 count = gen_reg_rtx (mode);
3951 blocks = gen_reg_rtx (mode);
3952
3953 convert_move (count, len, 1);
3954 emit_cmp_and_jump_insns (count, const0_rtx,
3955 EQ, NULL_RTX, mode, 1, end_label);
3956
3957 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3958 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3959 dst = change_address (dst, VOIDmode, dst_addr);
3960 src = change_address (src, VOIDmode, src_addr);
3961
3962 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3963 OPTAB_DIRECT);
3964 if (temp != count)
3965 emit_move_insn (count, temp);
3966
3967 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3968 OPTAB_DIRECT);
3969 if (temp != blocks)
3970 emit_move_insn (blocks, temp);
3971
3972 emit_cmp_and_jump_insns (blocks, const0_rtx,
3973 EQ, NULL_RTX, mode, 1, loop_end_label);
3974
3975 emit_label (loop_start_label);
3976
3977 if (TARGET_Z10
3978 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
3979 {
3980 rtx prefetch;
3981
3982 /* Issue a read prefetch for the +3 cache line. */
3983 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
3984 const0_rtx, const0_rtx);
3985 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
3986 emit_insn (prefetch);
3987
3988 /* Issue a write prefetch for the +3 cache line. */
3989 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
3990 const1_rtx, const0_rtx);
3991 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
3992 emit_insn (prefetch);
3993 }
3994
3995 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3996 s390_load_address (dst_addr,
3997 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3998 s390_load_address (src_addr,
3999 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4000
4001 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4002 OPTAB_DIRECT);
4003 if (temp != blocks)
4004 emit_move_insn (blocks, temp);
4005
4006 emit_cmp_and_jump_insns (blocks, const0_rtx,
4007 EQ, NULL_RTX, mode, 1, loop_end_label);
4008
4009 emit_jump (loop_start_label);
4010 emit_label (loop_end_label);
4011
4012 emit_insn (gen_movmem_short (dst, src,
4013 convert_to_mode (Pmode, count, 1)));
4014 emit_label (end_label);
4015 }
4016 }
4017
4018 /* Emit code to set LEN bytes at DST to VAL.
4019 Make use of clrmem if VAL is zero. */
4020
4021 void
4022 s390_expand_setmem (rtx dst, rtx len, rtx val)
4023 {
4024 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4025 return;
4026
4027 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4028
4029 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4030 {
4031 if (val == const0_rtx && INTVAL (len) <= 256)
4032 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4033 else
4034 {
4035 /* Initialize memory by storing the first byte. */
4036 emit_move_insn (adjust_address (dst, QImode, 0), val);
4037
4038 if (INTVAL (len) > 1)
4039 {
4040 /* Initiate 1 byte overlap move.
4041 The first byte of DST is propagated through DSTP1.
4042 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4043 DST is set to size 1 so the rest of the memory location
4044 does not count as source operand. */
4045 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4046 set_mem_size (dst, const1_rtx);
4047
4048 emit_insn (gen_movmem_short (dstp1, dst,
4049 GEN_INT (INTVAL (len) - 2)));
4050 }
4051 }
4052 }
4053
4054 else if (TARGET_MVCLE)
4055 {
4056 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4057 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4058 }
4059
4060 else
4061 {
4062 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4063 rtx loop_start_label = gen_label_rtx ();
4064 rtx loop_end_label = gen_label_rtx ();
4065 rtx end_label = gen_label_rtx ();
4066 enum machine_mode mode;
4067
4068 mode = GET_MODE (len);
4069 if (mode == VOIDmode)
4070 mode = Pmode;
4071
4072 dst_addr = gen_reg_rtx (Pmode);
4073 count = gen_reg_rtx (mode);
4074 blocks = gen_reg_rtx (mode);
4075
4076 convert_move (count, len, 1);
4077 emit_cmp_and_jump_insns (count, const0_rtx,
4078 EQ, NULL_RTX, mode, 1, end_label);
4079
4080 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4081 dst = change_address (dst, VOIDmode, dst_addr);
4082
4083 if (val == const0_rtx)
4084 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4085 OPTAB_DIRECT);
4086 else
4087 {
4088 dstp1 = adjust_address (dst, VOIDmode, 1);
4089 set_mem_size (dst, const1_rtx);
4090
4091 /* Initialize memory by storing the first byte. */
4092 emit_move_insn (adjust_address (dst, QImode, 0), val);
4093
4094 /* If count is 1 we are done. */
4095 emit_cmp_and_jump_insns (count, const1_rtx,
4096 EQ, NULL_RTX, mode, 1, end_label);
4097
4098 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4099 OPTAB_DIRECT);
4100 }
4101 if (temp != count)
4102 emit_move_insn (count, temp);
4103
4104 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4105 OPTAB_DIRECT);
4106 if (temp != blocks)
4107 emit_move_insn (blocks, temp);
4108
4109 emit_cmp_and_jump_insns (blocks, const0_rtx,
4110 EQ, NULL_RTX, mode, 1, loop_end_label);
4111
4112 emit_label (loop_start_label);
4113
4114 if (TARGET_Z10
4115 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4116 {
4117 /* Issue a write prefetch for the +4 cache line. */
4118 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4119 GEN_INT (1024)),
4120 const1_rtx, const0_rtx);
4121 emit_insn (prefetch);
4122 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4123 }
4124
4125 if (val == const0_rtx)
4126 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4127 else
4128 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4129 s390_load_address (dst_addr,
4130 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4131
4132 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4133 OPTAB_DIRECT);
4134 if (temp != blocks)
4135 emit_move_insn (blocks, temp);
4136
4137 emit_cmp_and_jump_insns (blocks, const0_rtx,
4138 EQ, NULL_RTX, mode, 1, loop_end_label);
4139
4140 emit_jump (loop_start_label);
4141 emit_label (loop_end_label);
4142
4143 if (val == const0_rtx)
4144 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4145 else
4146 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4147 emit_label (end_label);
4148 }
4149 }
4150
4151 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4152 and return the result in TARGET. */
4153
4154 void
4155 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4156 {
4157 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4158 rtx tmp;
4159
4160 /* As the result of CMPINT is inverted compared to what we need,
4161 we have to swap the operands. */
4162 tmp = op0; op0 = op1; op1 = tmp;
4163
4164 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4165 {
4166 if (INTVAL (len) > 0)
4167 {
4168 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4169 emit_insn (gen_cmpint (target, ccreg));
4170 }
4171 else
4172 emit_move_insn (target, const0_rtx);
4173 }
4174 else if (TARGET_MVCLE)
4175 {
4176 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4177 emit_insn (gen_cmpint (target, ccreg));
4178 }
4179 else
4180 {
4181 rtx addr0, addr1, count, blocks, temp;
4182 rtx loop_start_label = gen_label_rtx ();
4183 rtx loop_end_label = gen_label_rtx ();
4184 rtx end_label = gen_label_rtx ();
4185 enum machine_mode mode;
4186
4187 mode = GET_MODE (len);
4188 if (mode == VOIDmode)
4189 mode = Pmode;
4190
4191 addr0 = gen_reg_rtx (Pmode);
4192 addr1 = gen_reg_rtx (Pmode);
4193 count = gen_reg_rtx (mode);
4194 blocks = gen_reg_rtx (mode);
4195
4196 convert_move (count, len, 1);
4197 emit_cmp_and_jump_insns (count, const0_rtx,
4198 EQ, NULL_RTX, mode, 1, end_label);
4199
4200 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4201 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4202 op0 = change_address (op0, VOIDmode, addr0);
4203 op1 = change_address (op1, VOIDmode, addr1);
4204
4205 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4206 OPTAB_DIRECT);
4207 if (temp != count)
4208 emit_move_insn (count, temp);
4209
4210 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4211 OPTAB_DIRECT);
4212 if (temp != blocks)
4213 emit_move_insn (blocks, temp);
4214
4215 emit_cmp_and_jump_insns (blocks, const0_rtx,
4216 EQ, NULL_RTX, mode, 1, loop_end_label);
4217
4218 emit_label (loop_start_label);
4219
4220 if (TARGET_Z10
4221 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4222 {
4223 rtx prefetch;
4224
4225 /* Issue a read prefetch for the +2 cache line of operand 1. */
4226 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4227 const0_rtx, const0_rtx);
4228 emit_insn (prefetch);
4229 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4230
4231 /* Issue a read prefetch for the +2 cache line of operand 2. */
4232 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4233 const0_rtx, const0_rtx);
4234 emit_insn (prefetch);
4235 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4236 }
4237
4238 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4239 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4240 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4241 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4242 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4243 emit_jump_insn (temp);
4244
4245 s390_load_address (addr0,
4246 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4247 s390_load_address (addr1,
4248 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4249
4250 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4251 OPTAB_DIRECT);
4252 if (temp != blocks)
4253 emit_move_insn (blocks, temp);
4254
4255 emit_cmp_and_jump_insns (blocks, const0_rtx,
4256 EQ, NULL_RTX, mode, 1, loop_end_label);
4257
4258 emit_jump (loop_start_label);
4259 emit_label (loop_end_label);
4260
4261 emit_insn (gen_cmpmem_short (op0, op1,
4262 convert_to_mode (Pmode, count, 1)));
4263 emit_label (end_label);
4264
4265 emit_insn (gen_cmpint (target, ccreg));
4266 }
4267 }
4268
4269
4270 /* Expand conditional increment or decrement using alc/slb instructions.
4271 Should generate code setting DST to either SRC or SRC + INCREMENT,
4272 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4273 Returns true if successful, false otherwise.
4274
4275 That makes it possible to implement some if-constructs without jumps e.g.:
4276 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4277 unsigned int a, b, c;
4278 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4279 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4280 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4281 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4282
4283 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4284 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4285 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4286 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4287 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4288
4289 bool
4290 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4291 rtx dst, rtx src, rtx increment)
4292 {
4293 enum machine_mode cmp_mode;
4294 enum machine_mode cc_mode;
4295 rtx op_res;
4296 rtx insn;
4297 rtvec p;
4298 int ret;
4299
4300 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4301 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4302 cmp_mode = SImode;
4303 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4304 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4305 cmp_mode = DImode;
4306 else
4307 return false;
4308
4309 /* Try ADD LOGICAL WITH CARRY. */
4310 if (increment == const1_rtx)
4311 {
4312 /* Determine CC mode to use. */
4313 if (cmp_code == EQ || cmp_code == NE)
4314 {
4315 if (cmp_op1 != const0_rtx)
4316 {
4317 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4318 NULL_RTX, 0, OPTAB_WIDEN);
4319 cmp_op1 = const0_rtx;
4320 }
4321
4322 cmp_code = cmp_code == EQ ? LEU : GTU;
4323 }
4324
4325 if (cmp_code == LTU || cmp_code == LEU)
4326 {
4327 rtx tem = cmp_op0;
4328 cmp_op0 = cmp_op1;
4329 cmp_op1 = tem;
4330 cmp_code = swap_condition (cmp_code);
4331 }
4332
4333 switch (cmp_code)
4334 {
4335 case GTU:
4336 cc_mode = CCUmode;
4337 break;
4338
4339 case GEU:
4340 cc_mode = CCL3mode;
4341 break;
4342
4343 default:
4344 return false;
4345 }
4346
4347 /* Emit comparison instruction pattern. */
4348 if (!register_operand (cmp_op0, cmp_mode))
4349 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4350
4351 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4352 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4353 /* We use insn_invalid_p here to add clobbers if required. */
4354 ret = insn_invalid_p (emit_insn (insn));
4355 gcc_assert (!ret);
4356
4357 /* Emit ALC instruction pattern. */
4358 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4359 gen_rtx_REG (cc_mode, CC_REGNUM),
4360 const0_rtx);
4361
4362 if (src != const0_rtx)
4363 {
4364 if (!register_operand (src, GET_MODE (dst)))
4365 src = force_reg (GET_MODE (dst), src);
4366
4367 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4368 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4369 }
4370
4371 p = rtvec_alloc (2);
4372 RTVEC_ELT (p, 0) =
4373 gen_rtx_SET (VOIDmode, dst, op_res);
4374 RTVEC_ELT (p, 1) =
4375 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4376 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4377
4378 return true;
4379 }
4380
4381 /* Try SUBTRACT LOGICAL WITH BORROW. */
4382 if (increment == constm1_rtx)
4383 {
4384 /* Determine CC mode to use. */
4385 if (cmp_code == EQ || cmp_code == NE)
4386 {
4387 if (cmp_op1 != const0_rtx)
4388 {
4389 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4390 NULL_RTX, 0, OPTAB_WIDEN);
4391 cmp_op1 = const0_rtx;
4392 }
4393
4394 cmp_code = cmp_code == EQ ? LEU : GTU;
4395 }
4396
4397 if (cmp_code == GTU || cmp_code == GEU)
4398 {
4399 rtx tem = cmp_op0;
4400 cmp_op0 = cmp_op1;
4401 cmp_op1 = tem;
4402 cmp_code = swap_condition (cmp_code);
4403 }
4404
4405 switch (cmp_code)
4406 {
4407 case LEU:
4408 cc_mode = CCUmode;
4409 break;
4410
4411 case LTU:
4412 cc_mode = CCL3mode;
4413 break;
4414
4415 default:
4416 return false;
4417 }
4418
4419 /* Emit comparison instruction pattern. */
4420 if (!register_operand (cmp_op0, cmp_mode))
4421 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4422
4423 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4424 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4425 /* We use insn_invalid_p here to add clobbers if required. */
4426 ret = insn_invalid_p (emit_insn (insn));
4427 gcc_assert (!ret);
4428
4429 /* Emit SLB instruction pattern. */
4430 if (!register_operand (src, GET_MODE (dst)))
4431 src = force_reg (GET_MODE (dst), src);
4432
4433 op_res = gen_rtx_MINUS (GET_MODE (dst),
4434 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4435 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4436 gen_rtx_REG (cc_mode, CC_REGNUM),
4437 const0_rtx));
4438 p = rtvec_alloc (2);
4439 RTVEC_ELT (p, 0) =
4440 gen_rtx_SET (VOIDmode, dst, op_res);
4441 RTVEC_ELT (p, 1) =
4442 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4443 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4444
4445 return true;
4446 }
4447
4448 return false;
4449 }
4450
4451 /* Expand code for the insv template. Return true if successful. */
4452
4453 bool
4454 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4455 {
4456 int bitsize = INTVAL (op1);
4457 int bitpos = INTVAL (op2);
4458
4459 /* On z10 we can use the risbg instruction to implement insv. */
4460 if (TARGET_Z10
4461 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4462 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4463 {
4464 rtx op;
4465 rtx clobber;
4466
4467 op = gen_rtx_SET (GET_MODE(src),
4468 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4469 src);
4470 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4471 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4472
4473 return true;
4474 }
4475
4476 /* We need byte alignment. */
4477 if (bitsize % BITS_PER_UNIT)
4478 return false;
4479
4480 if (bitpos == 0
4481 && memory_operand (dest, VOIDmode)
4482 && (register_operand (src, word_mode)
4483 || const_int_operand (src, VOIDmode)))
4484 {
4485 /* Emit standard pattern if possible. */
4486 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4487 if (GET_MODE_BITSIZE (mode) == bitsize)
4488 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4489
4490 /* (set (ze (mem)) (const_int)). */
4491 else if (const_int_operand (src, VOIDmode))
4492 {
4493 int size = bitsize / BITS_PER_UNIT;
4494 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4495 GET_MODE_SIZE (word_mode) - size);
4496
4497 dest = adjust_address (dest, BLKmode, 0);
4498 set_mem_size (dest, GEN_INT (size));
4499 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4500 }
4501
4502 /* (set (ze (mem)) (reg)). */
4503 else if (register_operand (src, word_mode))
4504 {
4505 if (bitsize <= GET_MODE_BITSIZE (SImode))
4506 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4507 const0_rtx), src);
4508 else
4509 {
4510 /* Emit st,stcmh sequence. */
4511 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4512 int size = stcmh_width / BITS_PER_UNIT;
4513
4514 emit_move_insn (adjust_address (dest, SImode, size),
4515 gen_lowpart (SImode, src));
4516 set_mem_size (dest, GEN_INT (size));
4517 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4518 (stcmh_width), const0_rtx),
4519 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4520 (GET_MODE_BITSIZE (SImode))));
4521 }
4522 }
4523 else
4524 return false;
4525
4526 return true;
4527 }
4528
4529 /* (set (ze (reg)) (const_int)). */
4530 if (TARGET_ZARCH
4531 && register_operand (dest, word_mode)
4532 && (bitpos % 16) == 0
4533 && (bitsize % 16) == 0
4534 && const_int_operand (src, VOIDmode))
4535 {
4536 HOST_WIDE_INT val = INTVAL (src);
4537 int regpos = bitpos + bitsize;
4538
4539 while (regpos > bitpos)
4540 {
4541 enum machine_mode putmode;
4542 int putsize;
4543
4544 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4545 putmode = SImode;
4546 else
4547 putmode = HImode;
4548
4549 putsize = GET_MODE_BITSIZE (putmode);
4550 regpos -= putsize;
4551 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4552 GEN_INT (putsize),
4553 GEN_INT (regpos)),
4554 gen_int_mode (val, putmode));
4555 val >>= putsize;
4556 }
4557 gcc_assert (regpos == bitpos);
4558 return true;
4559 }
4560
4561 return false;
4562 }
4563
4564 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4565 register that holds VAL of mode MODE shifted by COUNT bits. */
4566
4567 static inline rtx
4568 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4569 {
4570 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4571 NULL_RTX, 1, OPTAB_DIRECT);
4572 return expand_simple_binop (SImode, ASHIFT, val, count,
4573 NULL_RTX, 1, OPTAB_DIRECT);
4574 }
4575
4576 /* Structure to hold the initial parameters for a compare_and_swap operation
4577 in HImode and QImode. */
4578
4579 struct alignment_context
4580 {
4581 rtx memsi; /* SI aligned memory location. */
4582 rtx shift; /* Bit offset with regard to lsb. */
4583 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4584 rtx modemaski; /* ~modemask */
4585 bool aligned; /* True if memory is aligned, false else. */
4586 };
4587
4588 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4589 structure AC for transparent simplifying, if the memory alignment is known
4590 to be at least 32bit. MEM is the memory location for the actual operation
4591 and MODE its mode. */
4592
4593 static void
4594 init_alignment_context (struct alignment_context *ac, rtx mem,
4595 enum machine_mode mode)
4596 {
4597 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4598 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4599
4600 if (ac->aligned)
4601 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4602 else
4603 {
4604 /* Alignment is unknown. */
4605 rtx byteoffset, addr, align;
4606
4607 /* Force the address into a register. */
4608 addr = force_reg (Pmode, XEXP (mem, 0));
4609
4610 /* Align it to SImode. */
4611 align = expand_simple_binop (Pmode, AND, addr,
4612 GEN_INT (-GET_MODE_SIZE (SImode)),
4613 NULL_RTX, 1, OPTAB_DIRECT);
4614 /* Generate MEM. */
4615 ac->memsi = gen_rtx_MEM (SImode, align);
4616 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4617 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4618 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4619
4620 /* Calculate shiftcount. */
4621 byteoffset = expand_simple_binop (Pmode, AND, addr,
4622 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4623 NULL_RTX, 1, OPTAB_DIRECT);
4624 /* As we already have some offset, evaluate the remaining distance. */
4625 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4626 NULL_RTX, 1, OPTAB_DIRECT);
4627
4628 }
4629 /* Shift is the byte count, but we need the bitcount. */
4630 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4631 NULL_RTX, 1, OPTAB_DIRECT);
4632 /* Calculate masks. */
4633 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4634 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4635 NULL_RTX, 1, OPTAB_DIRECT);
4636 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4637 }
4638
4639 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4640 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4641 to set if CMP == MEM.
4642 CMP is never in memory for compare_and_swap_cc because
4643 expand_bool_compare_and_swap puts it into a register for later compare. */
4644
4645 void
4646 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4647 {
4648 struct alignment_context ac;
4649 rtx cmpv, newv, val, resv, cc;
4650 rtx res = gen_reg_rtx (SImode);
4651 rtx csloop = gen_label_rtx ();
4652 rtx csend = gen_label_rtx ();
4653
4654 gcc_assert (register_operand (target, VOIDmode));
4655 gcc_assert (MEM_P (mem));
4656
4657 init_alignment_context (&ac, mem, mode);
4658
4659 /* Shift the values to the correct bit positions. */
4660 if (!(ac.aligned && MEM_P (cmp)))
4661 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4662 if (!(ac.aligned && MEM_P (new_rtx)))
4663 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4664
4665 /* Load full word. Subsequent loads are performed by CS. */
4666 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4667 NULL_RTX, 1, OPTAB_DIRECT);
4668
4669 /* Start CS loop. */
4670 emit_label (csloop);
4671 /* val = "<mem>00..0<mem>"
4672 * cmp = "00..0<cmp>00..0"
4673 * new = "00..0<new>00..0"
4674 */
4675
4676 /* Patch cmp and new with val at correct position. */
4677 if (ac.aligned && MEM_P (cmp))
4678 {
4679 cmpv = force_reg (SImode, val);
4680 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4681 }
4682 else
4683 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4684 NULL_RTX, 1, OPTAB_DIRECT));
4685 if (ac.aligned && MEM_P (new_rtx))
4686 {
4687 newv = force_reg (SImode, val);
4688 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4689 }
4690 else
4691 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4692 NULL_RTX, 1, OPTAB_DIRECT));
4693
4694 /* Jump to end if we're done (likely?). */
4695 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4696 cmpv, newv));
4697
4698 /* Check for changes outside mode. */
4699 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4700 NULL_RTX, 1, OPTAB_DIRECT);
4701 cc = s390_emit_compare (NE, resv, val);
4702 emit_move_insn (val, resv);
4703 /* Loop internal if so. */
4704 s390_emit_jump (csloop, cc);
4705
4706 emit_label (csend);
4707
4708 /* Return the correct part of the bitfield. */
4709 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4710 NULL_RTX, 1, OPTAB_DIRECT), 1);
4711 }
4712
4713 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4714 and VAL the value to play with. If AFTER is true then store the value
4715 MEM holds after the operation, if AFTER is false then store the value MEM
4716 holds before the operation. If TARGET is zero then discard that value, else
4717 store it to TARGET. */
4718
4719 void
4720 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4721 rtx target, rtx mem, rtx val, bool after)
4722 {
4723 struct alignment_context ac;
4724 rtx cmp;
4725 rtx new_rtx = gen_reg_rtx (SImode);
4726 rtx orig = gen_reg_rtx (SImode);
4727 rtx csloop = gen_label_rtx ();
4728
4729 gcc_assert (!target || register_operand (target, VOIDmode));
4730 gcc_assert (MEM_P (mem));
4731
4732 init_alignment_context (&ac, mem, mode);
4733
4734 /* Shift val to the correct bit positions.
4735 Preserve "icm", but prevent "ex icm". */
4736 if (!(ac.aligned && code == SET && MEM_P (val)))
4737 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4738
4739 /* Further preparation insns. */
4740 if (code == PLUS || code == MINUS)
4741 emit_move_insn (orig, val);
4742 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4743 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4744 NULL_RTX, 1, OPTAB_DIRECT);
4745
4746 /* Load full word. Subsequent loads are performed by CS. */
4747 cmp = force_reg (SImode, ac.memsi);
4748
4749 /* Start CS loop. */
4750 emit_label (csloop);
4751 emit_move_insn (new_rtx, cmp);
4752
4753 /* Patch new with val at correct position. */
4754 switch (code)
4755 {
4756 case PLUS:
4757 case MINUS:
4758 val = expand_simple_binop (SImode, code, new_rtx, orig,
4759 NULL_RTX, 1, OPTAB_DIRECT);
4760 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4761 NULL_RTX, 1, OPTAB_DIRECT);
4762 /* FALLTHRU */
4763 case SET:
4764 if (ac.aligned && MEM_P (val))
4765 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4766 else
4767 {
4768 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4769 NULL_RTX, 1, OPTAB_DIRECT);
4770 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4771 NULL_RTX, 1, OPTAB_DIRECT);
4772 }
4773 break;
4774 case AND:
4775 case IOR:
4776 case XOR:
4777 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4778 NULL_RTX, 1, OPTAB_DIRECT);
4779 break;
4780 case MULT: /* NAND */
4781 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4782 NULL_RTX, 1, OPTAB_DIRECT);
4783 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4784 NULL_RTX, 1, OPTAB_DIRECT);
4785 break;
4786 default:
4787 gcc_unreachable ();
4788 }
4789
4790 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4791 ac.memsi, cmp, new_rtx));
4792
4793 /* Return the correct part of the bitfield. */
4794 if (target)
4795 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4796 after ? new_rtx : cmp, ac.shift,
4797 NULL_RTX, 1, OPTAB_DIRECT), 1);
4798 }
4799
4800 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4801 We need to emit DTP-relative relocations. */
4802
4803 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4804
4805 static void
4806 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4807 {
4808 switch (size)
4809 {
4810 case 4:
4811 fputs ("\t.long\t", file);
4812 break;
4813 case 8:
4814 fputs ("\t.quad\t", file);
4815 break;
4816 default:
4817 gcc_unreachable ();
4818 }
4819 output_addr_const (file, x);
4820 fputs ("@DTPOFF", file);
4821 }
4822
4823 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4824 /* Implement TARGET_MANGLE_TYPE. */
4825
4826 static const char *
4827 s390_mangle_type (const_tree type)
4828 {
4829 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4830 && TARGET_LONG_DOUBLE_128)
4831 return "g";
4832
4833 /* For all other types, use normal C++ mangling. */
4834 return NULL;
4835 }
4836 #endif
4837
4838 /* In the name of slightly smaller debug output, and to cater to
4839 general assembler lossage, recognize various UNSPEC sequences
4840 and turn them back into a direct symbol reference. */
4841
4842 static rtx
4843 s390_delegitimize_address (rtx orig_x)
4844 {
4845 rtx x, y;
4846
4847 orig_x = delegitimize_mem_from_attrs (orig_x);
4848 x = orig_x;
4849 if (GET_CODE (x) != MEM)
4850 return orig_x;
4851
4852 x = XEXP (x, 0);
4853 if (GET_CODE (x) == PLUS
4854 && GET_CODE (XEXP (x, 1)) == CONST
4855 && GET_CODE (XEXP (x, 0)) == REG
4856 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4857 {
4858 y = XEXP (XEXP (x, 1), 0);
4859 if (GET_CODE (y) == UNSPEC
4860 && XINT (y, 1) == UNSPEC_GOT)
4861 return XVECEXP (y, 0, 0);
4862 return orig_x;
4863 }
4864
4865 if (GET_CODE (x) == CONST)
4866 {
4867 y = XEXP (x, 0);
4868 if (GET_CODE (y) == UNSPEC
4869 && XINT (y, 1) == UNSPEC_GOTENT)
4870 return XVECEXP (y, 0, 0);
4871 return orig_x;
4872 }
4873
4874 return orig_x;
4875 }
4876
4877 /* Output operand OP to stdio stream FILE.
4878 OP is an address (register + offset) which is not used to address data;
4879 instead the rightmost bits are interpreted as the value. */
4880
4881 static void
4882 print_shift_count_operand (FILE *file, rtx op)
4883 {
4884 HOST_WIDE_INT offset;
4885 rtx base;
4886
4887 /* Extract base register and offset. */
4888 if (!s390_decompose_shift_count (op, &base, &offset))
4889 gcc_unreachable ();
4890
4891 /* Sanity check. */
4892 if (base)
4893 {
4894 gcc_assert (GET_CODE (base) == REG);
4895 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4896 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4897 }
4898
4899 /* Offsets are constricted to twelve bits. */
4900 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4901 if (base)
4902 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4903 }
4904
4905 /* See 'get_some_local_dynamic_name'. */
4906
4907 static int
4908 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4909 {
4910 rtx x = *px;
4911
4912 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4913 {
4914 x = get_pool_constant (x);
4915 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4916 }
4917
4918 if (GET_CODE (x) == SYMBOL_REF
4919 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4920 {
4921 cfun->machine->some_ld_name = XSTR (x, 0);
4922 return 1;
4923 }
4924
4925 return 0;
4926 }
4927
4928 /* Locate some local-dynamic symbol still in use by this function
4929 so that we can print its name in local-dynamic base patterns. */
4930
4931 static const char *
4932 get_some_local_dynamic_name (void)
4933 {
4934 rtx insn;
4935
4936 if (cfun->machine->some_ld_name)
4937 return cfun->machine->some_ld_name;
4938
4939 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4940 if (INSN_P (insn)
4941 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4942 return cfun->machine->some_ld_name;
4943
4944 gcc_unreachable ();
4945 }
4946
4947 /* Output machine-dependent UNSPECs occurring in address constant X
4948 in assembler syntax to stdio stream FILE. Returns true if the
4949 constant X could be recognized, false otherwise. */
4950
4951 bool
4952 s390_output_addr_const_extra (FILE *file, rtx x)
4953 {
4954 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4955 switch (XINT (x, 1))
4956 {
4957 case UNSPEC_GOTENT:
4958 output_addr_const (file, XVECEXP (x, 0, 0));
4959 fprintf (file, "@GOTENT");
4960 return true;
4961 case UNSPEC_GOT:
4962 output_addr_const (file, XVECEXP (x, 0, 0));
4963 fprintf (file, "@GOT");
4964 return true;
4965 case UNSPEC_GOTOFF:
4966 output_addr_const (file, XVECEXP (x, 0, 0));
4967 fprintf (file, "@GOTOFF");
4968 return true;
4969 case UNSPEC_PLT:
4970 output_addr_const (file, XVECEXP (x, 0, 0));
4971 fprintf (file, "@PLT");
4972 return true;
4973 case UNSPEC_PLTOFF:
4974 output_addr_const (file, XVECEXP (x, 0, 0));
4975 fprintf (file, "@PLTOFF");
4976 return true;
4977 case UNSPEC_TLSGD:
4978 output_addr_const (file, XVECEXP (x, 0, 0));
4979 fprintf (file, "@TLSGD");
4980 return true;
4981 case UNSPEC_TLSLDM:
4982 assemble_name (file, get_some_local_dynamic_name ());
4983 fprintf (file, "@TLSLDM");
4984 return true;
4985 case UNSPEC_DTPOFF:
4986 output_addr_const (file, XVECEXP (x, 0, 0));
4987 fprintf (file, "@DTPOFF");
4988 return true;
4989 case UNSPEC_NTPOFF:
4990 output_addr_const (file, XVECEXP (x, 0, 0));
4991 fprintf (file, "@NTPOFF");
4992 return true;
4993 case UNSPEC_GOTNTPOFF:
4994 output_addr_const (file, XVECEXP (x, 0, 0));
4995 fprintf (file, "@GOTNTPOFF");
4996 return true;
4997 case UNSPEC_INDNTPOFF:
4998 output_addr_const (file, XVECEXP (x, 0, 0));
4999 fprintf (file, "@INDNTPOFF");
5000 return true;
5001 }
5002
5003 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5004 switch (XINT (x, 1))
5005 {
5006 case UNSPEC_POOL_OFFSET:
5007 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5008 output_addr_const (file, x);
5009 return true;
5010 }
5011 return false;
5012 }
5013
5014 /* Output address operand ADDR in assembler syntax to
5015 stdio stream FILE. */
5016
5017 void
5018 print_operand_address (FILE *file, rtx addr)
5019 {
5020 struct s390_address ad;
5021
5022 if (s390_symref_operand_p (addr, NULL, NULL))
5023 {
5024 gcc_assert (TARGET_Z10);
5025 output_addr_const (file, addr);
5026 return;
5027 }
5028
5029 if (!s390_decompose_address (addr, &ad)
5030 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5031 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5032 output_operand_lossage ("cannot decompose address");
5033
5034 if (ad.disp)
5035 output_addr_const (file, ad.disp);
5036 else
5037 fprintf (file, "0");
5038
5039 if (ad.base && ad.indx)
5040 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5041 reg_names[REGNO (ad.base)]);
5042 else if (ad.base)
5043 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5044 }
5045
5046 /* Output operand X in assembler syntax to stdio stream FILE.
5047 CODE specified the format flag. The following format flags
5048 are recognized:
5049
5050 'C': print opcode suffix for branch condition.
5051 'D': print opcode suffix for inverse branch condition.
5052 'E': print opcode suffix for branch on index instruction.
5053 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5054 'G': print the size of the operand in bytes.
5055 'O': print only the displacement of a memory reference.
5056 'R': print only the base register of a memory reference.
5057 'S': print S-type memory reference (base+displacement).
5058 'N': print the second word of a DImode operand.
5059 'M': print the second word of a TImode operand.
5060 'Y': print shift count operand.
5061
5062 'b': print integer X as if it's an unsigned byte.
5063 'c': print integer X as if it's an signed byte.
5064 'x': print integer X as if it's an unsigned halfword.
5065 'h': print integer X as if it's a signed halfword.
5066 'i': print the first nonzero HImode part of X.
5067 'j': print the first HImode part unequal to -1 of X.
5068 'k': print the first nonzero SImode part of X.
5069 'm': print the first SImode part unequal to -1 of X.
5070 'o': print integer X as if it's an unsigned 32bit word. */
5071
5072 void
5073 print_operand (FILE *file, rtx x, int code)
5074 {
5075 switch (code)
5076 {
5077 case 'C':
5078 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5079 return;
5080
5081 case 'D':
5082 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5083 return;
5084
5085 case 'E':
5086 if (GET_CODE (x) == LE)
5087 fprintf (file, "l");
5088 else if (GET_CODE (x) == GT)
5089 fprintf (file, "h");
5090 else
5091 gcc_unreachable ();
5092 return;
5093
5094 case 'J':
5095 if (GET_CODE (x) == SYMBOL_REF)
5096 {
5097 fprintf (file, "%s", ":tls_load:");
5098 output_addr_const (file, x);
5099 }
5100 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5101 {
5102 fprintf (file, "%s", ":tls_gdcall:");
5103 output_addr_const (file, XVECEXP (x, 0, 0));
5104 }
5105 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5106 {
5107 fprintf (file, "%s", ":tls_ldcall:");
5108 assemble_name (file, get_some_local_dynamic_name ());
5109 }
5110 else
5111 gcc_unreachable ();
5112 return;
5113
5114 case 'G':
5115 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5116 return;
5117
5118 case 'O':
5119 {
5120 struct s390_address ad;
5121 int ret;
5122
5123 gcc_assert (GET_CODE (x) == MEM);
5124 ret = s390_decompose_address (XEXP (x, 0), &ad);
5125 gcc_assert (ret);
5126 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5127 gcc_assert (!ad.indx);
5128
5129 if (ad.disp)
5130 output_addr_const (file, ad.disp);
5131 else
5132 fprintf (file, "0");
5133 }
5134 return;
5135
5136 case 'R':
5137 {
5138 struct s390_address ad;
5139 int ret;
5140
5141 gcc_assert (GET_CODE (x) == MEM);
5142 ret = s390_decompose_address (XEXP (x, 0), &ad);
5143 gcc_assert (ret);
5144 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5145 gcc_assert (!ad.indx);
5146
5147 if (ad.base)
5148 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5149 else
5150 fprintf (file, "0");
5151 }
5152 return;
5153
5154 case 'S':
5155 {
5156 struct s390_address ad;
5157 int ret;
5158
5159 gcc_assert (GET_CODE (x) == MEM);
5160 ret = s390_decompose_address (XEXP (x, 0), &ad);
5161 gcc_assert (ret);
5162 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5163 gcc_assert (!ad.indx);
5164
5165 if (ad.disp)
5166 output_addr_const (file, ad.disp);
5167 else
5168 fprintf (file, "0");
5169
5170 if (ad.base)
5171 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5172 }
5173 return;
5174
5175 case 'N':
5176 if (GET_CODE (x) == REG)
5177 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5178 else if (GET_CODE (x) == MEM)
5179 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5180 else
5181 gcc_unreachable ();
5182 break;
5183
5184 case 'M':
5185 if (GET_CODE (x) == REG)
5186 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5187 else if (GET_CODE (x) == MEM)
5188 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5189 else
5190 gcc_unreachable ();
5191 break;
5192
5193 case 'Y':
5194 print_shift_count_operand (file, x);
5195 return;
5196 }
5197
5198 switch (GET_CODE (x))
5199 {
5200 case REG:
5201 fprintf (file, "%s", reg_names[REGNO (x)]);
5202 break;
5203
5204 case MEM:
5205 output_address (XEXP (x, 0));
5206 break;
5207
5208 case CONST:
5209 case CODE_LABEL:
5210 case LABEL_REF:
5211 case SYMBOL_REF:
5212 output_addr_const (file, x);
5213 break;
5214
5215 case CONST_INT:
5216 if (code == 'b')
5217 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5218 else if (code == 'c')
5219 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5220 else if (code == 'x')
5221 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5222 else if (code == 'h')
5223 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5224 else if (code == 'i')
5225 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5226 s390_extract_part (x, HImode, 0));
5227 else if (code == 'j')
5228 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5229 s390_extract_part (x, HImode, -1));
5230 else if (code == 'k')
5231 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5232 s390_extract_part (x, SImode, 0));
5233 else if (code == 'm')
5234 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5235 s390_extract_part (x, SImode, -1));
5236 else if (code == 'o')
5237 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5238 else
5239 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5240 break;
5241
5242 case CONST_DOUBLE:
5243 gcc_assert (GET_MODE (x) == VOIDmode);
5244 if (code == 'b')
5245 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5246 else if (code == 'x')
5247 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5248 else if (code == 'h')
5249 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5250 else
5251 gcc_unreachable ();
5252 break;
5253
5254 default:
5255 fatal_insn ("UNKNOWN in print_operand !?", x);
5256 break;
5257 }
5258 }
5259
5260 /* Target hook for assembling integer objects. We need to define it
5261 here to work a round a bug in some versions of GAS, which couldn't
5262 handle values smaller than INT_MIN when printed in decimal. */
5263
5264 static bool
5265 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5266 {
5267 if (size == 8 && aligned_p
5268 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5269 {
5270 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5271 INTVAL (x));
5272 return true;
5273 }
5274 return default_assemble_integer (x, size, aligned_p);
5275 }
5276
5277 /* Returns true if register REGNO is used for forming
5278 a memory address in expression X. */
5279
5280 static bool
5281 reg_used_in_mem_p (int regno, rtx x)
5282 {
5283 enum rtx_code code = GET_CODE (x);
5284 int i, j;
5285 const char *fmt;
5286
5287 if (code == MEM)
5288 {
5289 if (refers_to_regno_p (regno, regno+1,
5290 XEXP (x, 0), 0))
5291 return true;
5292 }
5293 else if (code == SET
5294 && GET_CODE (SET_DEST (x)) == PC)
5295 {
5296 if (refers_to_regno_p (regno, regno+1,
5297 SET_SRC (x), 0))
5298 return true;
5299 }
5300
5301 fmt = GET_RTX_FORMAT (code);
5302 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5303 {
5304 if (fmt[i] == 'e'
5305 && reg_used_in_mem_p (regno, XEXP (x, i)))
5306 return true;
5307
5308 else if (fmt[i] == 'E')
5309 for (j = 0; j < XVECLEN (x, i); j++)
5310 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5311 return true;
5312 }
5313 return false;
5314 }
5315
5316 /* Returns true if expression DEP_RTX sets an address register
5317 used by instruction INSN to address memory. */
5318
5319 static bool
5320 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5321 {
5322 rtx target, pat;
5323
5324 if (GET_CODE (dep_rtx) == INSN)
5325 dep_rtx = PATTERN (dep_rtx);
5326
5327 if (GET_CODE (dep_rtx) == SET)
5328 {
5329 target = SET_DEST (dep_rtx);
5330 if (GET_CODE (target) == STRICT_LOW_PART)
5331 target = XEXP (target, 0);
5332 while (GET_CODE (target) == SUBREG)
5333 target = SUBREG_REG (target);
5334
5335 if (GET_CODE (target) == REG)
5336 {
5337 int regno = REGNO (target);
5338
5339 if (s390_safe_attr_type (insn) == TYPE_LA)
5340 {
5341 pat = PATTERN (insn);
5342 if (GET_CODE (pat) == PARALLEL)
5343 {
5344 gcc_assert (XVECLEN (pat, 0) == 2);
5345 pat = XVECEXP (pat, 0, 0);
5346 }
5347 gcc_assert (GET_CODE (pat) == SET);
5348 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5349 }
5350 else if (get_attr_atype (insn) == ATYPE_AGEN)
5351 return reg_used_in_mem_p (regno, PATTERN (insn));
5352 }
5353 }
5354 return false;
5355 }
5356
5357 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5358
5359 int
5360 s390_agen_dep_p (rtx dep_insn, rtx insn)
5361 {
5362 rtx dep_rtx = PATTERN (dep_insn);
5363 int i;
5364
5365 if (GET_CODE (dep_rtx) == SET
5366 && addr_generation_dependency_p (dep_rtx, insn))
5367 return 1;
5368 else if (GET_CODE (dep_rtx) == PARALLEL)
5369 {
5370 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5371 {
5372 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5373 return 1;
5374 }
5375 }
5376 return 0;
5377 }
5378
5379
5380 /* A C statement (sans semicolon) to update the integer scheduling priority
5381 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5382 reduce the priority to execute INSN later. Do not define this macro if
5383 you do not need to adjust the scheduling priorities of insns.
5384
5385 A STD instruction should be scheduled earlier,
5386 in order to use the bypass. */
5387
5388
5389 static int
5390 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5391 {
5392 if (! INSN_P (insn))
5393 return priority;
5394
5395 if (s390_tune != PROCESSOR_2084_Z990
5396 && s390_tune != PROCESSOR_2094_Z9_109
5397 && s390_tune != PROCESSOR_2097_Z10)
5398 return priority;
5399
5400 switch (s390_safe_attr_type (insn))
5401 {
5402 case TYPE_FSTOREDF:
5403 case TYPE_FSTORESF:
5404 priority = priority << 3;
5405 break;
5406 case TYPE_STORE:
5407 case TYPE_STM:
5408 priority = priority << 1;
5409 break;
5410 default:
5411 break;
5412 }
5413 return priority;
5414 }
5415
5416
5417 /* The number of instructions that can be issued per cycle. */
5418
5419 static int
5420 s390_issue_rate (void)
5421 {
5422 switch (s390_tune)
5423 {
5424 case PROCESSOR_2084_Z990:
5425 case PROCESSOR_2094_Z9_109:
5426 return 3;
5427 case PROCESSOR_2097_Z10:
5428 return 2;
5429 default:
5430 return 1;
5431 }
5432 }
5433
5434 static int
5435 s390_first_cycle_multipass_dfa_lookahead (void)
5436 {
5437 return 4;
5438 }
5439
5440 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5441 Fix up MEMs as required. */
5442
5443 static void
5444 annotate_constant_pool_refs (rtx *x)
5445 {
5446 int i, j;
5447 const char *fmt;
5448
5449 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5450 || !CONSTANT_POOL_ADDRESS_P (*x));
5451
5452 /* Literal pool references can only occur inside a MEM ... */
5453 if (GET_CODE (*x) == MEM)
5454 {
5455 rtx memref = XEXP (*x, 0);
5456
5457 if (GET_CODE (memref) == SYMBOL_REF
5458 && CONSTANT_POOL_ADDRESS_P (memref))
5459 {
5460 rtx base = cfun->machine->base_reg;
5461 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5462 UNSPEC_LTREF);
5463
5464 *x = replace_equiv_address (*x, addr);
5465 return;
5466 }
5467
5468 if (GET_CODE (memref) == CONST
5469 && GET_CODE (XEXP (memref, 0)) == PLUS
5470 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5471 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5472 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5473 {
5474 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5475 rtx sym = XEXP (XEXP (memref, 0), 0);
5476 rtx base = cfun->machine->base_reg;
5477 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5478 UNSPEC_LTREF);
5479
5480 *x = replace_equiv_address (*x, plus_constant (addr, off));
5481 return;
5482 }
5483 }
5484
5485 /* ... or a load-address type pattern. */
5486 if (GET_CODE (*x) == SET)
5487 {
5488 rtx addrref = SET_SRC (*x);
5489
5490 if (GET_CODE (addrref) == SYMBOL_REF
5491 && CONSTANT_POOL_ADDRESS_P (addrref))
5492 {
5493 rtx base = cfun->machine->base_reg;
5494 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5495 UNSPEC_LTREF);
5496
5497 SET_SRC (*x) = addr;
5498 return;
5499 }
5500
5501 if (GET_CODE (addrref) == CONST
5502 && GET_CODE (XEXP (addrref, 0)) == PLUS
5503 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5504 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5505 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5506 {
5507 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5508 rtx sym = XEXP (XEXP (addrref, 0), 0);
5509 rtx base = cfun->machine->base_reg;
5510 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5511 UNSPEC_LTREF);
5512
5513 SET_SRC (*x) = plus_constant (addr, off);
5514 return;
5515 }
5516 }
5517
5518 /* Annotate LTREL_BASE as well. */
5519 if (GET_CODE (*x) == UNSPEC
5520 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5521 {
5522 rtx base = cfun->machine->base_reg;
5523 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5524 UNSPEC_LTREL_BASE);
5525 return;
5526 }
5527
5528 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5529 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5530 {
5531 if (fmt[i] == 'e')
5532 {
5533 annotate_constant_pool_refs (&XEXP (*x, i));
5534 }
5535 else if (fmt[i] == 'E')
5536 {
5537 for (j = 0; j < XVECLEN (*x, i); j++)
5538 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5539 }
5540 }
5541 }
5542
5543 /* Split all branches that exceed the maximum distance.
5544 Returns true if this created a new literal pool entry. */
5545
5546 static int
5547 s390_split_branches (void)
5548 {
5549 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5550 int new_literal = 0, ret;
5551 rtx insn, pat, tmp, target;
5552 rtx *label;
5553
5554 /* We need correct insn addresses. */
5555
5556 shorten_branches (get_insns ());
5557
5558 /* Find all branches that exceed 64KB, and split them. */
5559
5560 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5561 {
5562 if (GET_CODE (insn) != JUMP_INSN)
5563 continue;
5564
5565 pat = PATTERN (insn);
5566 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5567 pat = XVECEXP (pat, 0, 0);
5568 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5569 continue;
5570
5571 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5572 {
5573 label = &SET_SRC (pat);
5574 }
5575 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5576 {
5577 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5578 label = &XEXP (SET_SRC (pat), 1);
5579 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5580 label = &XEXP (SET_SRC (pat), 2);
5581 else
5582 continue;
5583 }
5584 else
5585 continue;
5586
5587 if (get_attr_length (insn) <= 4)
5588 continue;
5589
5590 /* We are going to use the return register as scratch register,
5591 make sure it will be saved/restored by the prologue/epilogue. */
5592 cfun_frame_layout.save_return_addr_p = 1;
5593
5594 if (!flag_pic)
5595 {
5596 new_literal = 1;
5597 tmp = force_const_mem (Pmode, *label);
5598 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5599 INSN_ADDRESSES_NEW (tmp, -1);
5600 annotate_constant_pool_refs (&PATTERN (tmp));
5601
5602 target = temp_reg;
5603 }
5604 else
5605 {
5606 new_literal = 1;
5607 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5608 UNSPEC_LTREL_OFFSET);
5609 target = gen_rtx_CONST (Pmode, target);
5610 target = force_const_mem (Pmode, target);
5611 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5612 INSN_ADDRESSES_NEW (tmp, -1);
5613 annotate_constant_pool_refs (&PATTERN (tmp));
5614
5615 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5616 cfun->machine->base_reg),
5617 UNSPEC_LTREL_BASE);
5618 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5619 }
5620
5621 ret = validate_change (insn, label, target, 0);
5622 gcc_assert (ret);
5623 }
5624
5625 return new_literal;
5626 }
5627
5628
5629 /* Find an annotated literal pool symbol referenced in RTX X,
5630 and store it at REF. Will abort if X contains references to
5631 more than one such pool symbol; multiple references to the same
5632 symbol are allowed, however.
5633
5634 The rtx pointed to by REF must be initialized to NULL_RTX
5635 by the caller before calling this routine. */
5636
5637 static void
5638 find_constant_pool_ref (rtx x, rtx *ref)
5639 {
5640 int i, j;
5641 const char *fmt;
5642
5643 /* Ignore LTREL_BASE references. */
5644 if (GET_CODE (x) == UNSPEC
5645 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5646 return;
5647 /* Likewise POOL_ENTRY insns. */
5648 if (GET_CODE (x) == UNSPEC_VOLATILE
5649 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5650 return;
5651
5652 gcc_assert (GET_CODE (x) != SYMBOL_REF
5653 || !CONSTANT_POOL_ADDRESS_P (x));
5654
5655 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5656 {
5657 rtx sym = XVECEXP (x, 0, 0);
5658 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5659 && CONSTANT_POOL_ADDRESS_P (sym));
5660
5661 if (*ref == NULL_RTX)
5662 *ref = sym;
5663 else
5664 gcc_assert (*ref == sym);
5665
5666 return;
5667 }
5668
5669 fmt = GET_RTX_FORMAT (GET_CODE (x));
5670 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5671 {
5672 if (fmt[i] == 'e')
5673 {
5674 find_constant_pool_ref (XEXP (x, i), ref);
5675 }
5676 else if (fmt[i] == 'E')
5677 {
5678 for (j = 0; j < XVECLEN (x, i); j++)
5679 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5680 }
5681 }
5682 }
5683
5684 /* Replace every reference to the annotated literal pool
5685 symbol REF in X by its base plus OFFSET. */
5686
5687 static void
5688 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5689 {
5690 int i, j;
5691 const char *fmt;
5692
5693 gcc_assert (*x != ref);
5694
5695 if (GET_CODE (*x) == UNSPEC
5696 && XINT (*x, 1) == UNSPEC_LTREF
5697 && XVECEXP (*x, 0, 0) == ref)
5698 {
5699 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5700 return;
5701 }
5702
5703 if (GET_CODE (*x) == PLUS
5704 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5705 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5706 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5707 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5708 {
5709 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5710 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5711 return;
5712 }
5713
5714 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5715 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5716 {
5717 if (fmt[i] == 'e')
5718 {
5719 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5720 }
5721 else if (fmt[i] == 'E')
5722 {
5723 for (j = 0; j < XVECLEN (*x, i); j++)
5724 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5725 }
5726 }
5727 }
5728
5729 /* Check whether X contains an UNSPEC_LTREL_BASE.
5730 Return its constant pool symbol if found, NULL_RTX otherwise. */
5731
5732 static rtx
5733 find_ltrel_base (rtx x)
5734 {
5735 int i, j;
5736 const char *fmt;
5737
5738 if (GET_CODE (x) == UNSPEC
5739 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5740 return XVECEXP (x, 0, 0);
5741
5742 fmt = GET_RTX_FORMAT (GET_CODE (x));
5743 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5744 {
5745 if (fmt[i] == 'e')
5746 {
5747 rtx fnd = find_ltrel_base (XEXP (x, i));
5748 if (fnd)
5749 return fnd;
5750 }
5751 else if (fmt[i] == 'E')
5752 {
5753 for (j = 0; j < XVECLEN (x, i); j++)
5754 {
5755 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5756 if (fnd)
5757 return fnd;
5758 }
5759 }
5760 }
5761
5762 return NULL_RTX;
5763 }
5764
5765 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5766
5767 static void
5768 replace_ltrel_base (rtx *x)
5769 {
5770 int i, j;
5771 const char *fmt;
5772
5773 if (GET_CODE (*x) == UNSPEC
5774 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5775 {
5776 *x = XVECEXP (*x, 0, 1);
5777 return;
5778 }
5779
5780 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5781 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5782 {
5783 if (fmt[i] == 'e')
5784 {
5785 replace_ltrel_base (&XEXP (*x, i));
5786 }
5787 else if (fmt[i] == 'E')
5788 {
5789 for (j = 0; j < XVECLEN (*x, i); j++)
5790 replace_ltrel_base (&XVECEXP (*x, i, j));
5791 }
5792 }
5793 }
5794
5795
5796 /* We keep a list of constants which we have to add to internal
5797 constant tables in the middle of large functions. */
5798
5799 #define NR_C_MODES 11
5800 enum machine_mode constant_modes[NR_C_MODES] =
5801 {
5802 TFmode, TImode, TDmode,
5803 DFmode, DImode, DDmode,
5804 SFmode, SImode, SDmode,
5805 HImode,
5806 QImode
5807 };
5808
5809 struct constant
5810 {
5811 struct constant *next;
5812 rtx value;
5813 rtx label;
5814 };
5815
5816 struct constant_pool
5817 {
5818 struct constant_pool *next;
5819 rtx first_insn;
5820 rtx pool_insn;
5821 bitmap insns;
5822 rtx emit_pool_after;
5823
5824 struct constant *constants[NR_C_MODES];
5825 struct constant *execute;
5826 rtx label;
5827 int size;
5828 };
5829
5830 /* Allocate new constant_pool structure. */
5831
5832 static struct constant_pool *
5833 s390_alloc_pool (void)
5834 {
5835 struct constant_pool *pool;
5836 int i;
5837
5838 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5839 pool->next = NULL;
5840 for (i = 0; i < NR_C_MODES; i++)
5841 pool->constants[i] = NULL;
5842
5843 pool->execute = NULL;
5844 pool->label = gen_label_rtx ();
5845 pool->first_insn = NULL_RTX;
5846 pool->pool_insn = NULL_RTX;
5847 pool->insns = BITMAP_ALLOC (NULL);
5848 pool->size = 0;
5849 pool->emit_pool_after = NULL_RTX;
5850
5851 return pool;
5852 }
5853
5854 /* Create new constant pool covering instructions starting at INSN
5855 and chain it to the end of POOL_LIST. */
5856
5857 static struct constant_pool *
5858 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5859 {
5860 struct constant_pool *pool, **prev;
5861
5862 pool = s390_alloc_pool ();
5863 pool->first_insn = insn;
5864
5865 for (prev = pool_list; *prev; prev = &(*prev)->next)
5866 ;
5867 *prev = pool;
5868
5869 return pool;
5870 }
5871
5872 /* End range of instructions covered by POOL at INSN and emit
5873 placeholder insn representing the pool. */
5874
5875 static void
5876 s390_end_pool (struct constant_pool *pool, rtx insn)
5877 {
5878 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5879
5880 if (!insn)
5881 insn = get_last_insn ();
5882
5883 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5884 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5885 }
5886
5887 /* Add INSN to the list of insns covered by POOL. */
5888
5889 static void
5890 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5891 {
5892 bitmap_set_bit (pool->insns, INSN_UID (insn));
5893 }
5894
5895 /* Return pool out of POOL_LIST that covers INSN. */
5896
5897 static struct constant_pool *
5898 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5899 {
5900 struct constant_pool *pool;
5901
5902 for (pool = pool_list; pool; pool = pool->next)
5903 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5904 break;
5905
5906 return pool;
5907 }
5908
5909 /* Add constant VAL of mode MODE to the constant pool POOL. */
5910
5911 static void
5912 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5913 {
5914 struct constant *c;
5915 int i;
5916
5917 for (i = 0; i < NR_C_MODES; i++)
5918 if (constant_modes[i] == mode)
5919 break;
5920 gcc_assert (i != NR_C_MODES);
5921
5922 for (c = pool->constants[i]; c != NULL; c = c->next)
5923 if (rtx_equal_p (val, c->value))
5924 break;
5925
5926 if (c == NULL)
5927 {
5928 c = (struct constant *) xmalloc (sizeof *c);
5929 c->value = val;
5930 c->label = gen_label_rtx ();
5931 c->next = pool->constants[i];
5932 pool->constants[i] = c;
5933 pool->size += GET_MODE_SIZE (mode);
5934 }
5935 }
5936
5937 /* Return an rtx that represents the offset of X from the start of
5938 pool POOL. */
5939
5940 static rtx
5941 s390_pool_offset (struct constant_pool *pool, rtx x)
5942 {
5943 rtx label;
5944
5945 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5946 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5947 UNSPEC_POOL_OFFSET);
5948 return gen_rtx_CONST (GET_MODE (x), x);
5949 }
5950
5951 /* Find constant VAL of mode MODE in the constant pool POOL.
5952 Return an RTX describing the distance from the start of
5953 the pool to the location of the new constant. */
5954
5955 static rtx
5956 s390_find_constant (struct constant_pool *pool, rtx val,
5957 enum machine_mode mode)
5958 {
5959 struct constant *c;
5960 int i;
5961
5962 for (i = 0; i < NR_C_MODES; i++)
5963 if (constant_modes[i] == mode)
5964 break;
5965 gcc_assert (i != NR_C_MODES);
5966
5967 for (c = pool->constants[i]; c != NULL; c = c->next)
5968 if (rtx_equal_p (val, c->value))
5969 break;
5970
5971 gcc_assert (c);
5972
5973 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5974 }
5975
5976 /* Check whether INSN is an execute. Return the label_ref to its
5977 execute target template if so, NULL_RTX otherwise. */
5978
5979 static rtx
5980 s390_execute_label (rtx insn)
5981 {
5982 if (GET_CODE (insn) == INSN
5983 && GET_CODE (PATTERN (insn)) == PARALLEL
5984 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5985 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5986 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5987
5988 return NULL_RTX;
5989 }
5990
5991 /* Add execute target for INSN to the constant pool POOL. */
5992
5993 static void
5994 s390_add_execute (struct constant_pool *pool, rtx insn)
5995 {
5996 struct constant *c;
5997
5998 for (c = pool->execute; c != NULL; c = c->next)
5999 if (INSN_UID (insn) == INSN_UID (c->value))
6000 break;
6001
6002 if (c == NULL)
6003 {
6004 c = (struct constant *) xmalloc (sizeof *c);
6005 c->value = insn;
6006 c->label = gen_label_rtx ();
6007 c->next = pool->execute;
6008 pool->execute = c;
6009 pool->size += 6;
6010 }
6011 }
6012
6013 /* Find execute target for INSN in the constant pool POOL.
6014 Return an RTX describing the distance from the start of
6015 the pool to the location of the execute target. */
6016
6017 static rtx
6018 s390_find_execute (struct constant_pool *pool, rtx insn)
6019 {
6020 struct constant *c;
6021
6022 for (c = pool->execute; c != NULL; c = c->next)
6023 if (INSN_UID (insn) == INSN_UID (c->value))
6024 break;
6025
6026 gcc_assert (c);
6027
6028 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6029 }
6030
6031 /* For an execute INSN, extract the execute target template. */
6032
6033 static rtx
6034 s390_execute_target (rtx insn)
6035 {
6036 rtx pattern = PATTERN (insn);
6037 gcc_assert (s390_execute_label (insn));
6038
6039 if (XVECLEN (pattern, 0) == 2)
6040 {
6041 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6042 }
6043 else
6044 {
6045 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6046 int i;
6047
6048 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6049 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6050
6051 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6052 }
6053
6054 return pattern;
6055 }
6056
6057 /* Indicate that INSN cannot be duplicated. This is the case for
6058 execute insns that carry a unique label. */
6059
6060 static bool
6061 s390_cannot_copy_insn_p (rtx insn)
6062 {
6063 rtx label = s390_execute_label (insn);
6064 return label && label != const0_rtx;
6065 }
6066
6067 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6068 do not emit the pool base label. */
6069
6070 static void
6071 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6072 {
6073 struct constant *c;
6074 rtx insn = pool->pool_insn;
6075 int i;
6076
6077 /* Switch to rodata section. */
6078 if (TARGET_CPU_ZARCH)
6079 {
6080 insn = emit_insn_after (gen_pool_section_start (), insn);
6081 INSN_ADDRESSES_NEW (insn, -1);
6082 }
6083
6084 /* Ensure minimum pool alignment. */
6085 if (TARGET_CPU_ZARCH)
6086 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6087 else
6088 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6089 INSN_ADDRESSES_NEW (insn, -1);
6090
6091 /* Emit pool base label. */
6092 if (!remote_label)
6093 {
6094 insn = emit_label_after (pool->label, insn);
6095 INSN_ADDRESSES_NEW (insn, -1);
6096 }
6097
6098 /* Dump constants in descending alignment requirement order,
6099 ensuring proper alignment for every constant. */
6100 for (i = 0; i < NR_C_MODES; i++)
6101 for (c = pool->constants[i]; c; c = c->next)
6102 {
6103 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6104 rtx value = copy_rtx (c->value);
6105 if (GET_CODE (value) == CONST
6106 && GET_CODE (XEXP (value, 0)) == UNSPEC
6107 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6108 && XVECLEN (XEXP (value, 0), 0) == 1)
6109 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6110
6111 insn = emit_label_after (c->label, insn);
6112 INSN_ADDRESSES_NEW (insn, -1);
6113
6114 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6115 gen_rtvec (1, value),
6116 UNSPECV_POOL_ENTRY);
6117 insn = emit_insn_after (value, insn);
6118 INSN_ADDRESSES_NEW (insn, -1);
6119 }
6120
6121 /* Ensure minimum alignment for instructions. */
6122 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6123 INSN_ADDRESSES_NEW (insn, -1);
6124
6125 /* Output in-pool execute template insns. */
6126 for (c = pool->execute; c; c = c->next)
6127 {
6128 insn = emit_label_after (c->label, insn);
6129 INSN_ADDRESSES_NEW (insn, -1);
6130
6131 insn = emit_insn_after (s390_execute_target (c->value), insn);
6132 INSN_ADDRESSES_NEW (insn, -1);
6133 }
6134
6135 /* Switch back to previous section. */
6136 if (TARGET_CPU_ZARCH)
6137 {
6138 insn = emit_insn_after (gen_pool_section_end (), insn);
6139 INSN_ADDRESSES_NEW (insn, -1);
6140 }
6141
6142 insn = emit_barrier_after (insn);
6143 INSN_ADDRESSES_NEW (insn, -1);
6144
6145 /* Remove placeholder insn. */
6146 remove_insn (pool->pool_insn);
6147 }
6148
6149 /* Free all memory used by POOL. */
6150
6151 static void
6152 s390_free_pool (struct constant_pool *pool)
6153 {
6154 struct constant *c, *next;
6155 int i;
6156
6157 for (i = 0; i < NR_C_MODES; i++)
6158 for (c = pool->constants[i]; c; c = next)
6159 {
6160 next = c->next;
6161 free (c);
6162 }
6163
6164 for (c = pool->execute; c; c = next)
6165 {
6166 next = c->next;
6167 free (c);
6168 }
6169
6170 BITMAP_FREE (pool->insns);
6171 free (pool);
6172 }
6173
6174
6175 /* Collect main literal pool. Return NULL on overflow. */
6176
6177 static struct constant_pool *
6178 s390_mainpool_start (void)
6179 {
6180 struct constant_pool *pool;
6181 rtx insn;
6182
6183 pool = s390_alloc_pool ();
6184
6185 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6186 {
6187 if (GET_CODE (insn) == INSN
6188 && GET_CODE (PATTERN (insn)) == SET
6189 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6190 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6191 {
6192 gcc_assert (!pool->pool_insn);
6193 pool->pool_insn = insn;
6194 }
6195
6196 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6197 {
6198 s390_add_execute (pool, insn);
6199 }
6200 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6201 {
6202 rtx pool_ref = NULL_RTX;
6203 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6204 if (pool_ref)
6205 {
6206 rtx constant = get_pool_constant (pool_ref);
6207 enum machine_mode mode = get_pool_mode (pool_ref);
6208 s390_add_constant (pool, constant, mode);
6209 }
6210 }
6211
6212 /* If hot/cold partitioning is enabled we have to make sure that
6213 the literal pool is emitted in the same section where the
6214 initialization of the literal pool base pointer takes place.
6215 emit_pool_after is only used in the non-overflow case on non
6216 Z cpus where we can emit the literal pool at the end of the
6217 function body within the text section. */
6218 if (NOTE_P (insn)
6219 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6220 && !pool->emit_pool_after)
6221 pool->emit_pool_after = PREV_INSN (insn);
6222 }
6223
6224 gcc_assert (pool->pool_insn || pool->size == 0);
6225
6226 if (pool->size >= 4096)
6227 {
6228 /* We're going to chunkify the pool, so remove the main
6229 pool placeholder insn. */
6230 remove_insn (pool->pool_insn);
6231
6232 s390_free_pool (pool);
6233 pool = NULL;
6234 }
6235
6236 /* If the functions ends with the section where the literal pool
6237 should be emitted set the marker to its end. */
6238 if (pool && !pool->emit_pool_after)
6239 pool->emit_pool_after = get_last_insn ();
6240
6241 return pool;
6242 }
6243
6244 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6245 Modify the current function to output the pool constants as well as
6246 the pool register setup instruction. */
6247
6248 static void
6249 s390_mainpool_finish (struct constant_pool *pool)
6250 {
6251 rtx base_reg = cfun->machine->base_reg;
6252 rtx insn;
6253
6254 /* If the pool is empty, we're done. */
6255 if (pool->size == 0)
6256 {
6257 /* We don't actually need a base register after all. */
6258 cfun->machine->base_reg = NULL_RTX;
6259
6260 if (pool->pool_insn)
6261 remove_insn (pool->pool_insn);
6262 s390_free_pool (pool);
6263 return;
6264 }
6265
6266 /* We need correct insn addresses. */
6267 shorten_branches (get_insns ());
6268
6269 /* On zSeries, we use a LARL to load the pool register. The pool is
6270 located in the .rodata section, so we emit it after the function. */
6271 if (TARGET_CPU_ZARCH)
6272 {
6273 insn = gen_main_base_64 (base_reg, pool->label);
6274 insn = emit_insn_after (insn, pool->pool_insn);
6275 INSN_ADDRESSES_NEW (insn, -1);
6276 remove_insn (pool->pool_insn);
6277
6278 insn = get_last_insn ();
6279 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6280 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6281
6282 s390_dump_pool (pool, 0);
6283 }
6284
6285 /* On S/390, if the total size of the function's code plus literal pool
6286 does not exceed 4096 bytes, we use BASR to set up a function base
6287 pointer, and emit the literal pool at the end of the function. */
6288 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6289 + pool->size + 8 /* alignment slop */ < 4096)
6290 {
6291 insn = gen_main_base_31_small (base_reg, pool->label);
6292 insn = emit_insn_after (insn, pool->pool_insn);
6293 INSN_ADDRESSES_NEW (insn, -1);
6294 remove_insn (pool->pool_insn);
6295
6296 insn = emit_label_after (pool->label, insn);
6297 INSN_ADDRESSES_NEW (insn, -1);
6298
6299 /* emit_pool_after will be set by s390_mainpool_start to the
6300 last insn of the section where the literal pool should be
6301 emitted. */
6302 insn = pool->emit_pool_after;
6303
6304 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6305 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6306
6307 s390_dump_pool (pool, 1);
6308 }
6309
6310 /* Otherwise, we emit an inline literal pool and use BASR to branch
6311 over it, setting up the pool register at the same time. */
6312 else
6313 {
6314 rtx pool_end = gen_label_rtx ();
6315
6316 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6317 insn = emit_insn_after (insn, pool->pool_insn);
6318 INSN_ADDRESSES_NEW (insn, -1);
6319 remove_insn (pool->pool_insn);
6320
6321 insn = emit_label_after (pool->label, insn);
6322 INSN_ADDRESSES_NEW (insn, -1);
6323
6324 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6325 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6326
6327 insn = emit_label_after (pool_end, pool->pool_insn);
6328 INSN_ADDRESSES_NEW (insn, -1);
6329
6330 s390_dump_pool (pool, 1);
6331 }
6332
6333
6334 /* Replace all literal pool references. */
6335
6336 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6337 {
6338 if (INSN_P (insn))
6339 replace_ltrel_base (&PATTERN (insn));
6340
6341 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6342 {
6343 rtx addr, pool_ref = NULL_RTX;
6344 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6345 if (pool_ref)
6346 {
6347 if (s390_execute_label (insn))
6348 addr = s390_find_execute (pool, insn);
6349 else
6350 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6351 get_pool_mode (pool_ref));
6352
6353 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6354 INSN_CODE (insn) = -1;
6355 }
6356 }
6357 }
6358
6359
6360 /* Free the pool. */
6361 s390_free_pool (pool);
6362 }
6363
6364 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6365 We have decided we cannot use this pool, so revert all changes
6366 to the current function that were done by s390_mainpool_start. */
6367 static void
6368 s390_mainpool_cancel (struct constant_pool *pool)
6369 {
6370 /* We didn't actually change the instruction stream, so simply
6371 free the pool memory. */
6372 s390_free_pool (pool);
6373 }
6374
6375
6376 /* Chunkify the literal pool. */
6377
6378 #define S390_POOL_CHUNK_MIN 0xc00
6379 #define S390_POOL_CHUNK_MAX 0xe00
6380
6381 static struct constant_pool *
6382 s390_chunkify_start (void)
6383 {
6384 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6385 int extra_size = 0;
6386 bitmap far_labels;
6387 rtx pending_ltrel = NULL_RTX;
6388 rtx insn;
6389
6390 rtx (*gen_reload_base) (rtx, rtx) =
6391 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6392
6393
6394 /* We need correct insn addresses. */
6395
6396 shorten_branches (get_insns ());
6397
6398 /* Scan all insns and move literals to pool chunks. */
6399
6400 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6401 {
6402 bool section_switch_p = false;
6403
6404 /* Check for pending LTREL_BASE. */
6405 if (INSN_P (insn))
6406 {
6407 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6408 if (ltrel_base)
6409 {
6410 gcc_assert (ltrel_base == pending_ltrel);
6411 pending_ltrel = NULL_RTX;
6412 }
6413 }
6414
6415 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6416 {
6417 if (!curr_pool)
6418 curr_pool = s390_start_pool (&pool_list, insn);
6419
6420 s390_add_execute (curr_pool, insn);
6421 s390_add_pool_insn (curr_pool, insn);
6422 }
6423 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6424 {
6425 rtx pool_ref = NULL_RTX;
6426 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6427 if (pool_ref)
6428 {
6429 rtx constant = get_pool_constant (pool_ref);
6430 enum machine_mode mode = get_pool_mode (pool_ref);
6431
6432 if (!curr_pool)
6433 curr_pool = s390_start_pool (&pool_list, insn);
6434
6435 s390_add_constant (curr_pool, constant, mode);
6436 s390_add_pool_insn (curr_pool, insn);
6437
6438 /* Don't split the pool chunk between a LTREL_OFFSET load
6439 and the corresponding LTREL_BASE. */
6440 if (GET_CODE (constant) == CONST
6441 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6442 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6443 {
6444 gcc_assert (!pending_ltrel);
6445 pending_ltrel = pool_ref;
6446 }
6447 }
6448 }
6449
6450 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6451 {
6452 if (curr_pool)
6453 s390_add_pool_insn (curr_pool, insn);
6454 /* An LTREL_BASE must follow within the same basic block. */
6455 gcc_assert (!pending_ltrel);
6456 }
6457
6458 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6459 section_switch_p = true;
6460
6461 if (!curr_pool
6462 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6463 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6464 continue;
6465
6466 if (TARGET_CPU_ZARCH)
6467 {
6468 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6469 continue;
6470
6471 s390_end_pool (curr_pool, NULL_RTX);
6472 curr_pool = NULL;
6473 }
6474 else
6475 {
6476 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6477 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6478 + extra_size;
6479
6480 /* We will later have to insert base register reload insns.
6481 Those will have an effect on code size, which we need to
6482 consider here. This calculation makes rather pessimistic
6483 worst-case assumptions. */
6484 if (GET_CODE (insn) == CODE_LABEL)
6485 extra_size += 6;
6486
6487 if (chunk_size < S390_POOL_CHUNK_MIN
6488 && curr_pool->size < S390_POOL_CHUNK_MIN
6489 && !section_switch_p)
6490 continue;
6491
6492 /* Pool chunks can only be inserted after BARRIERs ... */
6493 if (GET_CODE (insn) == BARRIER)
6494 {
6495 s390_end_pool (curr_pool, insn);
6496 curr_pool = NULL;
6497 extra_size = 0;
6498 }
6499
6500 /* ... so if we don't find one in time, create one. */
6501 else if (chunk_size > S390_POOL_CHUNK_MAX
6502 || curr_pool->size > S390_POOL_CHUNK_MAX
6503 || section_switch_p)
6504 {
6505 rtx label, jump, barrier;
6506
6507 if (!section_switch_p)
6508 {
6509 /* We can insert the barrier only after a 'real' insn. */
6510 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6511 continue;
6512 if (get_attr_length (insn) == 0)
6513 continue;
6514 /* Don't separate LTREL_BASE from the corresponding
6515 LTREL_OFFSET load. */
6516 if (pending_ltrel)
6517 continue;
6518 }
6519 else
6520 {
6521 gcc_assert (!pending_ltrel);
6522
6523 /* The old pool has to end before the section switch
6524 note in order to make it part of the current
6525 section. */
6526 insn = PREV_INSN (insn);
6527 }
6528
6529 label = gen_label_rtx ();
6530 jump = emit_jump_insn_after (gen_jump (label), insn);
6531 barrier = emit_barrier_after (jump);
6532 insn = emit_label_after (label, barrier);
6533 JUMP_LABEL (jump) = label;
6534 LABEL_NUSES (label) = 1;
6535
6536 INSN_ADDRESSES_NEW (jump, -1);
6537 INSN_ADDRESSES_NEW (barrier, -1);
6538 INSN_ADDRESSES_NEW (insn, -1);
6539
6540 s390_end_pool (curr_pool, barrier);
6541 curr_pool = NULL;
6542 extra_size = 0;
6543 }
6544 }
6545 }
6546
6547 if (curr_pool)
6548 s390_end_pool (curr_pool, NULL_RTX);
6549 gcc_assert (!pending_ltrel);
6550
6551 /* Find all labels that are branched into
6552 from an insn belonging to a different chunk. */
6553
6554 far_labels = BITMAP_ALLOC (NULL);
6555
6556 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6557 {
6558 /* Labels marked with LABEL_PRESERVE_P can be target
6559 of non-local jumps, so we have to mark them.
6560 The same holds for named labels.
6561
6562 Don't do that, however, if it is the label before
6563 a jump table. */
6564
6565 if (GET_CODE (insn) == CODE_LABEL
6566 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6567 {
6568 rtx vec_insn = next_real_insn (insn);
6569 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6570 PATTERN (vec_insn) : NULL_RTX;
6571 if (!vec_pat
6572 || !(GET_CODE (vec_pat) == ADDR_VEC
6573 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6574 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6575 }
6576
6577 /* If we have a direct jump (conditional or unconditional)
6578 or a casesi jump, check all potential targets. */
6579 else if (GET_CODE (insn) == JUMP_INSN)
6580 {
6581 rtx pat = PATTERN (insn);
6582 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6583 pat = XVECEXP (pat, 0, 0);
6584
6585 if (GET_CODE (pat) == SET)
6586 {
6587 rtx label = JUMP_LABEL (insn);
6588 if (label)
6589 {
6590 if (s390_find_pool (pool_list, label)
6591 != s390_find_pool (pool_list, insn))
6592 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6593 }
6594 }
6595 else if (GET_CODE (pat) == PARALLEL
6596 && XVECLEN (pat, 0) == 2
6597 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6598 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6599 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6600 {
6601 /* Find the jump table used by this casesi jump. */
6602 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6603 rtx vec_insn = next_real_insn (vec_label);
6604 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6605 PATTERN (vec_insn) : NULL_RTX;
6606 if (vec_pat
6607 && (GET_CODE (vec_pat) == ADDR_VEC
6608 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6609 {
6610 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6611
6612 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6613 {
6614 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6615
6616 if (s390_find_pool (pool_list, label)
6617 != s390_find_pool (pool_list, insn))
6618 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6619 }
6620 }
6621 }
6622 }
6623 }
6624
6625 /* Insert base register reload insns before every pool. */
6626
6627 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6628 {
6629 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6630 curr_pool->label);
6631 rtx insn = curr_pool->first_insn;
6632 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6633 }
6634
6635 /* Insert base register reload insns at every far label. */
6636
6637 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6638 if (GET_CODE (insn) == CODE_LABEL
6639 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6640 {
6641 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6642 if (pool)
6643 {
6644 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6645 pool->label);
6646 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6647 }
6648 }
6649
6650
6651 BITMAP_FREE (far_labels);
6652
6653
6654 /* Recompute insn addresses. */
6655
6656 init_insn_lengths ();
6657 shorten_branches (get_insns ());
6658
6659 return pool_list;
6660 }
6661
6662 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6663 After we have decided to use this list, finish implementing
6664 all changes to the current function as required. */
6665
6666 static void
6667 s390_chunkify_finish (struct constant_pool *pool_list)
6668 {
6669 struct constant_pool *curr_pool = NULL;
6670 rtx insn;
6671
6672
6673 /* Replace all literal pool references. */
6674
6675 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6676 {
6677 if (INSN_P (insn))
6678 replace_ltrel_base (&PATTERN (insn));
6679
6680 curr_pool = s390_find_pool (pool_list, insn);
6681 if (!curr_pool)
6682 continue;
6683
6684 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6685 {
6686 rtx addr, pool_ref = NULL_RTX;
6687 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6688 if (pool_ref)
6689 {
6690 if (s390_execute_label (insn))
6691 addr = s390_find_execute (curr_pool, insn);
6692 else
6693 addr = s390_find_constant (curr_pool,
6694 get_pool_constant (pool_ref),
6695 get_pool_mode (pool_ref));
6696
6697 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6698 INSN_CODE (insn) = -1;
6699 }
6700 }
6701 }
6702
6703 /* Dump out all literal pools. */
6704
6705 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6706 s390_dump_pool (curr_pool, 0);
6707
6708 /* Free pool list. */
6709
6710 while (pool_list)
6711 {
6712 struct constant_pool *next = pool_list->next;
6713 s390_free_pool (pool_list);
6714 pool_list = next;
6715 }
6716 }
6717
6718 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6719 We have decided we cannot use this list, so revert all changes
6720 to the current function that were done by s390_chunkify_start. */
6721
6722 static void
6723 s390_chunkify_cancel (struct constant_pool *pool_list)
6724 {
6725 struct constant_pool *curr_pool = NULL;
6726 rtx insn;
6727
6728 /* Remove all pool placeholder insns. */
6729
6730 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6731 {
6732 /* Did we insert an extra barrier? Remove it. */
6733 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6734 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6735 rtx label = NEXT_INSN (curr_pool->pool_insn);
6736
6737 if (jump && GET_CODE (jump) == JUMP_INSN
6738 && barrier && GET_CODE (barrier) == BARRIER
6739 && label && GET_CODE (label) == CODE_LABEL
6740 && GET_CODE (PATTERN (jump)) == SET
6741 && SET_DEST (PATTERN (jump)) == pc_rtx
6742 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6743 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6744 {
6745 remove_insn (jump);
6746 remove_insn (barrier);
6747 remove_insn (label);
6748 }
6749
6750 remove_insn (curr_pool->pool_insn);
6751 }
6752
6753 /* Remove all base register reload insns. */
6754
6755 for (insn = get_insns (); insn; )
6756 {
6757 rtx next_insn = NEXT_INSN (insn);
6758
6759 if (GET_CODE (insn) == INSN
6760 && GET_CODE (PATTERN (insn)) == SET
6761 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6762 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6763 remove_insn (insn);
6764
6765 insn = next_insn;
6766 }
6767
6768 /* Free pool list. */
6769
6770 while (pool_list)
6771 {
6772 struct constant_pool *next = pool_list->next;
6773 s390_free_pool (pool_list);
6774 pool_list = next;
6775 }
6776 }
6777
6778 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6779
6780 void
6781 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6782 {
6783 REAL_VALUE_TYPE r;
6784
6785 switch (GET_MODE_CLASS (mode))
6786 {
6787 case MODE_FLOAT:
6788 case MODE_DECIMAL_FLOAT:
6789 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6790
6791 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6792 assemble_real (r, mode, align);
6793 break;
6794
6795 case MODE_INT:
6796 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6797 mark_symbol_refs_as_used (exp);
6798 break;
6799
6800 default:
6801 gcc_unreachable ();
6802 }
6803 }
6804
6805
6806 /* Return an RTL expression representing the value of the return address
6807 for the frame COUNT steps up from the current frame. FRAME is the
6808 frame pointer of that frame. */
6809
6810 rtx
6811 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6812 {
6813 int offset;
6814 rtx addr;
6815
6816 /* Without backchain, we fail for all but the current frame. */
6817
6818 if (!TARGET_BACKCHAIN && count > 0)
6819 return NULL_RTX;
6820
6821 /* For the current frame, we need to make sure the initial
6822 value of RETURN_REGNUM is actually saved. */
6823
6824 if (count == 0)
6825 {
6826 /* On non-z architectures branch splitting could overwrite r14. */
6827 if (TARGET_CPU_ZARCH)
6828 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6829 else
6830 {
6831 cfun_frame_layout.save_return_addr_p = true;
6832 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6833 }
6834 }
6835
6836 if (TARGET_PACKED_STACK)
6837 offset = -2 * UNITS_PER_LONG;
6838 else
6839 offset = RETURN_REGNUM * UNITS_PER_LONG;
6840
6841 addr = plus_constant (frame, offset);
6842 addr = memory_address (Pmode, addr);
6843 return gen_rtx_MEM (Pmode, addr);
6844 }
6845
6846 /* Return an RTL expression representing the back chain stored in
6847 the current stack frame. */
6848
6849 rtx
6850 s390_back_chain_rtx (void)
6851 {
6852 rtx chain;
6853
6854 gcc_assert (TARGET_BACKCHAIN);
6855
6856 if (TARGET_PACKED_STACK)
6857 chain = plus_constant (stack_pointer_rtx,
6858 STACK_POINTER_OFFSET - UNITS_PER_LONG);
6859 else
6860 chain = stack_pointer_rtx;
6861
6862 chain = gen_rtx_MEM (Pmode, chain);
6863 return chain;
6864 }
6865
6866 /* Find first call clobbered register unused in a function.
6867 This could be used as base register in a leaf function
6868 or for holding the return address before epilogue. */
6869
6870 static int
6871 find_unused_clobbered_reg (void)
6872 {
6873 int i;
6874 for (i = 0; i < 6; i++)
6875 if (!df_regs_ever_live_p (i))
6876 return i;
6877 return 0;
6878 }
6879
6880
6881 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6882 clobbered hard regs in SETREG. */
6883
6884 static void
6885 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6886 {
6887 int *regs_ever_clobbered = (int *)data;
6888 unsigned int i, regno;
6889 enum machine_mode mode = GET_MODE (setreg);
6890
6891 if (GET_CODE (setreg) == SUBREG)
6892 {
6893 rtx inner = SUBREG_REG (setreg);
6894 if (!GENERAL_REG_P (inner))
6895 return;
6896 regno = subreg_regno (setreg);
6897 }
6898 else if (GENERAL_REG_P (setreg))
6899 regno = REGNO (setreg);
6900 else
6901 return;
6902
6903 for (i = regno;
6904 i < regno + HARD_REGNO_NREGS (regno, mode);
6905 i++)
6906 regs_ever_clobbered[i] = 1;
6907 }
6908
6909 /* Walks through all basic blocks of the current function looking
6910 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6911 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6912 each of those regs. */
6913
6914 static void
6915 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6916 {
6917 basic_block cur_bb;
6918 rtx cur_insn;
6919 unsigned int i;
6920
6921 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6922
6923 /* For non-leaf functions we have to consider all call clobbered regs to be
6924 clobbered. */
6925 if (!current_function_is_leaf)
6926 {
6927 for (i = 0; i < 16; i++)
6928 regs_ever_clobbered[i] = call_really_used_regs[i];
6929 }
6930
6931 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6932 this work is done by liveness analysis (mark_regs_live_at_end).
6933 Special care is needed for functions containing landing pads. Landing pads
6934 may use the eh registers, but the code which sets these registers is not
6935 contained in that function. Hence s390_regs_ever_clobbered is not able to
6936 deal with this automatically. */
6937 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6938 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6939 if (crtl->calls_eh_return
6940 || (cfun->machine->has_landing_pad_p
6941 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6942 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6943
6944 /* For nonlocal gotos all call-saved registers have to be saved.
6945 This flag is also set for the unwinding code in libgcc.
6946 See expand_builtin_unwind_init. For regs_ever_live this is done by
6947 reload. */
6948 if (cfun->has_nonlocal_label)
6949 for (i = 0; i < 16; i++)
6950 if (!call_really_used_regs[i])
6951 regs_ever_clobbered[i] = 1;
6952
6953 FOR_EACH_BB (cur_bb)
6954 {
6955 FOR_BB_INSNS (cur_bb, cur_insn)
6956 {
6957 if (INSN_P (cur_insn))
6958 note_stores (PATTERN (cur_insn),
6959 s390_reg_clobbered_rtx,
6960 regs_ever_clobbered);
6961 }
6962 }
6963 }
6964
6965 /* Determine the frame area which actually has to be accessed
6966 in the function epilogue. The values are stored at the
6967 given pointers AREA_BOTTOM (address of the lowest used stack
6968 address) and AREA_TOP (address of the first item which does
6969 not belong to the stack frame). */
6970
6971 static void
6972 s390_frame_area (int *area_bottom, int *area_top)
6973 {
6974 int b, t;
6975 int i;
6976
6977 b = INT_MAX;
6978 t = INT_MIN;
6979
6980 if (cfun_frame_layout.first_restore_gpr != -1)
6981 {
6982 b = (cfun_frame_layout.gprs_offset
6983 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
6984 t = b + (cfun_frame_layout.last_restore_gpr
6985 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
6986 }
6987
6988 if (TARGET_64BIT && cfun_save_high_fprs_p)
6989 {
6990 b = MIN (b, cfun_frame_layout.f8_offset);
6991 t = MAX (t, (cfun_frame_layout.f8_offset
6992 + cfun_frame_layout.high_fprs * 8));
6993 }
6994
6995 if (!TARGET_64BIT)
6996 for (i = 2; i < 4; i++)
6997 if (cfun_fpr_bit_p (i))
6998 {
6999 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7000 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7001 }
7002
7003 *area_bottom = b;
7004 *area_top = t;
7005 }
7006
7007 /* Fill cfun->machine with info about register usage of current function.
7008 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7009
7010 static void
7011 s390_register_info (int clobbered_regs[])
7012 {
7013 int i, j;
7014
7015 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7016 cfun_frame_layout.fpr_bitmap = 0;
7017 cfun_frame_layout.high_fprs = 0;
7018 if (TARGET_64BIT)
7019 for (i = 24; i < 32; i++)
7020 if (df_regs_ever_live_p (i) && !global_regs[i])
7021 {
7022 cfun_set_fpr_bit (i - 16);
7023 cfun_frame_layout.high_fprs++;
7024 }
7025
7026 /* Find first and last gpr to be saved. We trust regs_ever_live
7027 data, except that we don't save and restore global registers.
7028
7029 Also, all registers with special meaning to the compiler need
7030 to be handled extra. */
7031
7032 s390_regs_ever_clobbered (clobbered_regs);
7033
7034 for (i = 0; i < 16; i++)
7035 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7036
7037 if (frame_pointer_needed)
7038 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7039
7040 if (flag_pic)
7041 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7042 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7043
7044 clobbered_regs[BASE_REGNUM]
7045 |= (cfun->machine->base_reg
7046 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7047
7048 clobbered_regs[RETURN_REGNUM]
7049 |= (!current_function_is_leaf
7050 || TARGET_TPF_PROFILING
7051 || cfun->machine->split_branches_pending_p
7052 || cfun_frame_layout.save_return_addr_p
7053 || crtl->calls_eh_return
7054 || cfun->stdarg);
7055
7056 clobbered_regs[STACK_POINTER_REGNUM]
7057 |= (!current_function_is_leaf
7058 || TARGET_TPF_PROFILING
7059 || cfun_save_high_fprs_p
7060 || get_frame_size () > 0
7061 || cfun->calls_alloca
7062 || cfun->stdarg);
7063
7064 for (i = 6; i < 16; i++)
7065 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7066 break;
7067 for (j = 15; j > i; j--)
7068 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7069 break;
7070
7071 if (i == 16)
7072 {
7073 /* Nothing to save/restore. */
7074 cfun_frame_layout.first_save_gpr_slot = -1;
7075 cfun_frame_layout.last_save_gpr_slot = -1;
7076 cfun_frame_layout.first_save_gpr = -1;
7077 cfun_frame_layout.first_restore_gpr = -1;
7078 cfun_frame_layout.last_save_gpr = -1;
7079 cfun_frame_layout.last_restore_gpr = -1;
7080 }
7081 else
7082 {
7083 /* Save slots for gprs from i to j. */
7084 cfun_frame_layout.first_save_gpr_slot = i;
7085 cfun_frame_layout.last_save_gpr_slot = j;
7086
7087 for (i = cfun_frame_layout.first_save_gpr_slot;
7088 i < cfun_frame_layout.last_save_gpr_slot + 1;
7089 i++)
7090 if (clobbered_regs[i])
7091 break;
7092
7093 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7094 if (clobbered_regs[j])
7095 break;
7096
7097 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7098 {
7099 /* Nothing to save/restore. */
7100 cfun_frame_layout.first_save_gpr = -1;
7101 cfun_frame_layout.first_restore_gpr = -1;
7102 cfun_frame_layout.last_save_gpr = -1;
7103 cfun_frame_layout.last_restore_gpr = -1;
7104 }
7105 else
7106 {
7107 /* Save / Restore from gpr i to j. */
7108 cfun_frame_layout.first_save_gpr = i;
7109 cfun_frame_layout.first_restore_gpr = i;
7110 cfun_frame_layout.last_save_gpr = j;
7111 cfun_frame_layout.last_restore_gpr = j;
7112 }
7113 }
7114
7115 if (cfun->stdarg)
7116 {
7117 /* Varargs functions need to save gprs 2 to 6. */
7118 if (cfun->va_list_gpr_size
7119 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7120 {
7121 int min_gpr = crtl->args.info.gprs;
7122 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7123 if (max_gpr > GP_ARG_NUM_REG)
7124 max_gpr = GP_ARG_NUM_REG;
7125
7126 if (cfun_frame_layout.first_save_gpr == -1
7127 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7128 {
7129 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7130 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7131 }
7132
7133 if (cfun_frame_layout.last_save_gpr == -1
7134 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7135 {
7136 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7137 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7138 }
7139 }
7140
7141 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7142 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7143 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7144 {
7145 int min_fpr = crtl->args.info.fprs;
7146 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7147 if (max_fpr > FP_ARG_NUM_REG)
7148 max_fpr = FP_ARG_NUM_REG;
7149
7150 /* ??? This is currently required to ensure proper location
7151 of the fpr save slots within the va_list save area. */
7152 if (TARGET_PACKED_STACK)
7153 min_fpr = 0;
7154
7155 for (i = min_fpr; i < max_fpr; i++)
7156 cfun_set_fpr_bit (i);
7157 }
7158 }
7159
7160 if (!TARGET_64BIT)
7161 for (i = 2; i < 4; i++)
7162 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7163 cfun_set_fpr_bit (i);
7164 }
7165
7166 /* Fill cfun->machine with info about frame of current function. */
7167
7168 static void
7169 s390_frame_info (void)
7170 {
7171 int i;
7172
7173 cfun_frame_layout.frame_size = get_frame_size ();
7174 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7175 fatal_error ("total size of local variables exceeds architecture limit");
7176
7177 if (!TARGET_PACKED_STACK)
7178 {
7179 cfun_frame_layout.backchain_offset = 0;
7180 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7181 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7182 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7183 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7184 * UNITS_PER_LONG);
7185 }
7186 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7187 {
7188 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7189 - UNITS_PER_LONG);
7190 cfun_frame_layout.gprs_offset
7191 = (cfun_frame_layout.backchain_offset
7192 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7193 * UNITS_PER_LONG);
7194
7195 if (TARGET_64BIT)
7196 {
7197 cfun_frame_layout.f4_offset
7198 = (cfun_frame_layout.gprs_offset
7199 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7200
7201 cfun_frame_layout.f0_offset
7202 = (cfun_frame_layout.f4_offset
7203 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7204 }
7205 else
7206 {
7207 /* On 31 bit we have to care about alignment of the
7208 floating point regs to provide fastest access. */
7209 cfun_frame_layout.f0_offset
7210 = ((cfun_frame_layout.gprs_offset
7211 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7212 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7213
7214 cfun_frame_layout.f4_offset
7215 = (cfun_frame_layout.f0_offset
7216 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7217 }
7218 }
7219 else /* no backchain */
7220 {
7221 cfun_frame_layout.f4_offset
7222 = (STACK_POINTER_OFFSET
7223 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7224
7225 cfun_frame_layout.f0_offset
7226 = (cfun_frame_layout.f4_offset
7227 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7228
7229 cfun_frame_layout.gprs_offset
7230 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7231 }
7232
7233 if (current_function_is_leaf
7234 && !TARGET_TPF_PROFILING
7235 && cfun_frame_layout.frame_size == 0
7236 && !cfun_save_high_fprs_p
7237 && !cfun->calls_alloca
7238 && !cfun->stdarg)
7239 return;
7240
7241 if (!TARGET_PACKED_STACK)
7242 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7243 + crtl->outgoing_args_size
7244 + cfun_frame_layout.high_fprs * 8);
7245 else
7246 {
7247 if (TARGET_BACKCHAIN)
7248 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7249
7250 /* No alignment trouble here because f8-f15 are only saved under
7251 64 bit. */
7252 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7253 cfun_frame_layout.f4_offset),
7254 cfun_frame_layout.gprs_offset)
7255 - cfun_frame_layout.high_fprs * 8);
7256
7257 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7258
7259 for (i = 0; i < 8; i++)
7260 if (cfun_fpr_bit_p (i))
7261 cfun_frame_layout.frame_size += 8;
7262
7263 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7264
7265 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7266 the frame size to sustain 8 byte alignment of stack frames. */
7267 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7268 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7269 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7270
7271 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7272 }
7273 }
7274
7275 /* Generate frame layout. Fills in register and frame data for the current
7276 function in cfun->machine. This routine can be called multiple times;
7277 it will re-do the complete frame layout every time. */
7278
7279 static void
7280 s390_init_frame_layout (void)
7281 {
7282 HOST_WIDE_INT frame_size;
7283 int base_used;
7284 int clobbered_regs[16];
7285
7286 /* On S/390 machines, we may need to perform branch splitting, which
7287 will require both base and return address register. We have no
7288 choice but to assume we're going to need them until right at the
7289 end of the machine dependent reorg phase. */
7290 if (!TARGET_CPU_ZARCH)
7291 cfun->machine->split_branches_pending_p = true;
7292
7293 do
7294 {
7295 frame_size = cfun_frame_layout.frame_size;
7296
7297 /* Try to predict whether we'll need the base register. */
7298 base_used = cfun->machine->split_branches_pending_p
7299 || crtl->uses_const_pool
7300 || (!DISP_IN_RANGE (frame_size)
7301 && !CONST_OK_FOR_K (frame_size));
7302
7303 /* Decide which register to use as literal pool base. In small
7304 leaf functions, try to use an unused call-clobbered register
7305 as base register to avoid save/restore overhead. */
7306 if (!base_used)
7307 cfun->machine->base_reg = NULL_RTX;
7308 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7309 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7310 else
7311 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7312
7313 s390_register_info (clobbered_regs);
7314 s390_frame_info ();
7315 }
7316 while (frame_size != cfun_frame_layout.frame_size);
7317 }
7318
7319 /* Update frame layout. Recompute actual register save data based on
7320 current info and update regs_ever_live for the special registers.
7321 May be called multiple times, but may never cause *more* registers
7322 to be saved than s390_init_frame_layout allocated room for. */
7323
7324 static void
7325 s390_update_frame_layout (void)
7326 {
7327 int clobbered_regs[16];
7328
7329 s390_register_info (clobbered_regs);
7330
7331 df_set_regs_ever_live (BASE_REGNUM,
7332 clobbered_regs[BASE_REGNUM] ? true : false);
7333 df_set_regs_ever_live (RETURN_REGNUM,
7334 clobbered_regs[RETURN_REGNUM] ? true : false);
7335 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7336 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7337
7338 if (cfun->machine->base_reg)
7339 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7340 }
7341
7342 /* Return true if it is legal to put a value with MODE into REGNO. */
7343
7344 bool
7345 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7346 {
7347 switch (REGNO_REG_CLASS (regno))
7348 {
7349 case FP_REGS:
7350 if (REGNO_PAIR_OK (regno, mode))
7351 {
7352 if (mode == SImode || mode == DImode)
7353 return true;
7354
7355 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7356 return true;
7357 }
7358 break;
7359 case ADDR_REGS:
7360 if (FRAME_REGNO_P (regno) && mode == Pmode)
7361 return true;
7362
7363 /* fallthrough */
7364 case GENERAL_REGS:
7365 if (REGNO_PAIR_OK (regno, mode))
7366 {
7367 if (TARGET_ZARCH
7368 || (mode != TFmode && mode != TCmode && mode != TDmode))
7369 return true;
7370 }
7371 break;
7372 case CC_REGS:
7373 if (GET_MODE_CLASS (mode) == MODE_CC)
7374 return true;
7375 break;
7376 case ACCESS_REGS:
7377 if (REGNO_PAIR_OK (regno, mode))
7378 {
7379 if (mode == SImode || mode == Pmode)
7380 return true;
7381 }
7382 break;
7383 default:
7384 return false;
7385 }
7386
7387 return false;
7388 }
7389
7390 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7391
7392 bool
7393 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7394 {
7395 /* Once we've decided upon a register to use as base register, it must
7396 no longer be used for any other purpose. */
7397 if (cfun->machine->base_reg)
7398 if (REGNO (cfun->machine->base_reg) == old_reg
7399 || REGNO (cfun->machine->base_reg) == new_reg)
7400 return false;
7401
7402 return true;
7403 }
7404
7405 /* Maximum number of registers to represent a value of mode MODE
7406 in a register of class RCLASS. */
7407
7408 bool
7409 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7410 {
7411 switch (rclass)
7412 {
7413 case FP_REGS:
7414 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7415 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7416 else
7417 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7418 case ACCESS_REGS:
7419 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7420 default:
7421 break;
7422 }
7423 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7424 }
7425
7426 /* Return true if register FROM can be eliminated via register TO. */
7427
7428 static bool
7429 s390_can_eliminate (const int from, const int to)
7430 {
7431 /* On zSeries machines, we have not marked the base register as fixed.
7432 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7433 If a function requires the base register, we say here that this
7434 elimination cannot be performed. This will cause reload to free
7435 up the base register (as if it were fixed). On the other hand,
7436 if the current function does *not* require the base register, we
7437 say here the elimination succeeds, which in turn allows reload
7438 to allocate the base register for any other purpose. */
7439 if (from == BASE_REGNUM && to == BASE_REGNUM)
7440 {
7441 if (TARGET_CPU_ZARCH)
7442 {
7443 s390_init_frame_layout ();
7444 return cfun->machine->base_reg == NULL_RTX;
7445 }
7446
7447 return false;
7448 }
7449
7450 /* Everything else must point into the stack frame. */
7451 gcc_assert (to == STACK_POINTER_REGNUM
7452 || to == HARD_FRAME_POINTER_REGNUM);
7453
7454 gcc_assert (from == FRAME_POINTER_REGNUM
7455 || from == ARG_POINTER_REGNUM
7456 || from == RETURN_ADDRESS_POINTER_REGNUM);
7457
7458 /* Make sure we actually saved the return address. */
7459 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7460 if (!crtl->calls_eh_return
7461 && !cfun->stdarg
7462 && !cfun_frame_layout.save_return_addr_p)
7463 return false;
7464
7465 return true;
7466 }
7467
7468 /* Return offset between register FROM and TO initially after prolog. */
7469
7470 HOST_WIDE_INT
7471 s390_initial_elimination_offset (int from, int to)
7472 {
7473 HOST_WIDE_INT offset;
7474 int index;
7475
7476 /* ??? Why are we called for non-eliminable pairs? */
7477 if (!s390_can_eliminate (from, to))
7478 return 0;
7479
7480 switch (from)
7481 {
7482 case FRAME_POINTER_REGNUM:
7483 offset = (get_frame_size()
7484 + STACK_POINTER_OFFSET
7485 + crtl->outgoing_args_size);
7486 break;
7487
7488 case ARG_POINTER_REGNUM:
7489 s390_init_frame_layout ();
7490 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7491 break;
7492
7493 case RETURN_ADDRESS_POINTER_REGNUM:
7494 s390_init_frame_layout ();
7495 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7496 gcc_assert (index >= 0);
7497 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7498 offset += index * UNITS_PER_LONG;
7499 break;
7500
7501 case BASE_REGNUM:
7502 offset = 0;
7503 break;
7504
7505 default:
7506 gcc_unreachable ();
7507 }
7508
7509 return offset;
7510 }
7511
7512 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7513 to register BASE. Return generated insn. */
7514
7515 static rtx
7516 save_fpr (rtx base, int offset, int regnum)
7517 {
7518 rtx addr;
7519 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7520
7521 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7522 set_mem_alias_set (addr, get_varargs_alias_set ());
7523 else
7524 set_mem_alias_set (addr, get_frame_alias_set ());
7525
7526 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7527 }
7528
7529 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7530 to register BASE. Return generated insn. */
7531
7532 static rtx
7533 restore_fpr (rtx base, int offset, int regnum)
7534 {
7535 rtx addr;
7536 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7537 set_mem_alias_set (addr, get_frame_alias_set ());
7538
7539 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7540 }
7541
7542 /* Return true if REGNO is a global register, but not one
7543 of the special ones that need to be saved/restored in anyway. */
7544
7545 static inline bool
7546 global_not_special_regno_p (int regno)
7547 {
7548 return (global_regs[regno]
7549 /* These registers are special and need to be
7550 restored in any case. */
7551 && !(regno == STACK_POINTER_REGNUM
7552 || regno == RETURN_REGNUM
7553 || regno == BASE_REGNUM
7554 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7555 }
7556
7557 /* Generate insn to save registers FIRST to LAST into
7558 the register save area located at offset OFFSET
7559 relative to register BASE. */
7560
7561 static rtx
7562 save_gprs (rtx base, int offset, int first, int last)
7563 {
7564 rtx addr, insn, note;
7565 int i;
7566
7567 addr = plus_constant (base, offset);
7568 addr = gen_rtx_MEM (Pmode, addr);
7569
7570 set_mem_alias_set (addr, get_frame_alias_set ());
7571
7572 /* Special-case single register. */
7573 if (first == last)
7574 {
7575 if (TARGET_64BIT)
7576 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7577 else
7578 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7579
7580 if (!global_not_special_regno_p (first))
7581 RTX_FRAME_RELATED_P (insn) = 1;
7582 return insn;
7583 }
7584
7585
7586 insn = gen_store_multiple (addr,
7587 gen_rtx_REG (Pmode, first),
7588 GEN_INT (last - first + 1));
7589
7590 if (first <= 6 && cfun->stdarg)
7591 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7592 {
7593 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7594
7595 if (first + i <= 6)
7596 set_mem_alias_set (mem, get_varargs_alias_set ());
7597 }
7598
7599 /* We need to set the FRAME_RELATED flag on all SETs
7600 inside the store-multiple pattern.
7601
7602 However, we must not emit DWARF records for registers 2..5
7603 if they are stored for use by variable arguments ...
7604
7605 ??? Unfortunately, it is not enough to simply not the
7606 FRAME_RELATED flags for those SETs, because the first SET
7607 of the PARALLEL is always treated as if it had the flag
7608 set, even if it does not. Therefore we emit a new pattern
7609 without those registers as REG_FRAME_RELATED_EXPR note. */
7610
7611 if (first >= 6 && !global_not_special_regno_p (first))
7612 {
7613 rtx pat = PATTERN (insn);
7614
7615 for (i = 0; i < XVECLEN (pat, 0); i++)
7616 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7617 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7618 0, i)))))
7619 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7620
7621 RTX_FRAME_RELATED_P (insn) = 1;
7622 }
7623 else if (last >= 6)
7624 {
7625 int start;
7626
7627 for (start = first >= 6 ? first : 6; start <= last; start++)
7628 if (!global_not_special_regno_p (start))
7629 break;
7630
7631 if (start > last)
7632 return insn;
7633
7634 addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7635 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7636 gen_rtx_REG (Pmode, start),
7637 GEN_INT (last - start + 1));
7638 note = PATTERN (note);
7639
7640 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7641
7642 for (i = 0; i < XVECLEN (note, 0); i++)
7643 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7644 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7645 0, i)))))
7646 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7647
7648 RTX_FRAME_RELATED_P (insn) = 1;
7649 }
7650
7651 return insn;
7652 }
7653
7654 /* Generate insn to restore registers FIRST to LAST from
7655 the register save area located at offset OFFSET
7656 relative to register BASE. */
7657
7658 static rtx
7659 restore_gprs (rtx base, int offset, int first, int last)
7660 {
7661 rtx addr, insn;
7662
7663 addr = plus_constant (base, offset);
7664 addr = gen_rtx_MEM (Pmode, addr);
7665 set_mem_alias_set (addr, get_frame_alias_set ());
7666
7667 /* Special-case single register. */
7668 if (first == last)
7669 {
7670 if (TARGET_64BIT)
7671 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7672 else
7673 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7674
7675 return insn;
7676 }
7677
7678 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7679 addr,
7680 GEN_INT (last - first + 1));
7681 return insn;
7682 }
7683
7684 /* Return insn sequence to load the GOT register. */
7685
7686 static GTY(()) rtx got_symbol;
7687 rtx
7688 s390_load_got (void)
7689 {
7690 rtx insns;
7691
7692 if (!got_symbol)
7693 {
7694 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7695 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7696 }
7697
7698 start_sequence ();
7699
7700 if (TARGET_CPU_ZARCH)
7701 {
7702 emit_move_insn (pic_offset_table_rtx, got_symbol);
7703 }
7704 else
7705 {
7706 rtx offset;
7707
7708 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7709 UNSPEC_LTREL_OFFSET);
7710 offset = gen_rtx_CONST (Pmode, offset);
7711 offset = force_const_mem (Pmode, offset);
7712
7713 emit_move_insn (pic_offset_table_rtx, offset);
7714
7715 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7716 UNSPEC_LTREL_BASE);
7717 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7718
7719 emit_move_insn (pic_offset_table_rtx, offset);
7720 }
7721
7722 insns = get_insns ();
7723 end_sequence ();
7724 return insns;
7725 }
7726
7727 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7728 and the change to the stack pointer. */
7729
7730 static void
7731 s390_emit_stack_tie (void)
7732 {
7733 rtx mem = gen_frame_mem (BLKmode,
7734 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7735
7736 emit_insn (gen_stack_tie (mem));
7737 }
7738
7739 /* Expand the prologue into a bunch of separate insns. */
7740
7741 void
7742 s390_emit_prologue (void)
7743 {
7744 rtx insn, addr;
7745 rtx temp_reg;
7746 int i;
7747 int offset;
7748 int next_fpr = 0;
7749
7750 /* Complete frame layout. */
7751
7752 s390_update_frame_layout ();
7753
7754 /* Annotate all constant pool references to let the scheduler know
7755 they implicitly use the base register. */
7756
7757 push_topmost_sequence ();
7758
7759 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7760 if (INSN_P (insn))
7761 {
7762 annotate_constant_pool_refs (&PATTERN (insn));
7763 df_insn_rescan (insn);
7764 }
7765
7766 pop_topmost_sequence ();
7767
7768 /* Choose best register to use for temp use within prologue.
7769 See below for why TPF must use the register 1. */
7770
7771 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7772 && !current_function_is_leaf
7773 && !TARGET_TPF_PROFILING)
7774 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7775 else
7776 temp_reg = gen_rtx_REG (Pmode, 1);
7777
7778 /* Save call saved gprs. */
7779 if (cfun_frame_layout.first_save_gpr != -1)
7780 {
7781 insn = save_gprs (stack_pointer_rtx,
7782 cfun_frame_layout.gprs_offset +
7783 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7784 - cfun_frame_layout.first_save_gpr_slot),
7785 cfun_frame_layout.first_save_gpr,
7786 cfun_frame_layout.last_save_gpr);
7787 emit_insn (insn);
7788 }
7789
7790 /* Dummy insn to mark literal pool slot. */
7791
7792 if (cfun->machine->base_reg)
7793 emit_insn (gen_main_pool (cfun->machine->base_reg));
7794
7795 offset = cfun_frame_layout.f0_offset;
7796
7797 /* Save f0 and f2. */
7798 for (i = 0; i < 2; i++)
7799 {
7800 if (cfun_fpr_bit_p (i))
7801 {
7802 save_fpr (stack_pointer_rtx, offset, i + 16);
7803 offset += 8;
7804 }
7805 else if (!TARGET_PACKED_STACK)
7806 offset += 8;
7807 }
7808
7809 /* Save f4 and f6. */
7810 offset = cfun_frame_layout.f4_offset;
7811 for (i = 2; i < 4; i++)
7812 {
7813 if (cfun_fpr_bit_p (i))
7814 {
7815 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7816 offset += 8;
7817
7818 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7819 therefore are not frame related. */
7820 if (!call_really_used_regs[i + 16])
7821 RTX_FRAME_RELATED_P (insn) = 1;
7822 }
7823 else if (!TARGET_PACKED_STACK)
7824 offset += 8;
7825 }
7826
7827 if (TARGET_PACKED_STACK
7828 && cfun_save_high_fprs_p
7829 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7830 {
7831 offset = (cfun_frame_layout.f8_offset
7832 + (cfun_frame_layout.high_fprs - 1) * 8);
7833
7834 for (i = 15; i > 7 && offset >= 0; i--)
7835 if (cfun_fpr_bit_p (i))
7836 {
7837 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7838
7839 RTX_FRAME_RELATED_P (insn) = 1;
7840 offset -= 8;
7841 }
7842 if (offset >= cfun_frame_layout.f8_offset)
7843 next_fpr = i + 16;
7844 }
7845
7846 if (!TARGET_PACKED_STACK)
7847 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7848
7849 /* Decrement stack pointer. */
7850
7851 if (cfun_frame_layout.frame_size > 0)
7852 {
7853 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7854 rtx real_frame_off;
7855
7856 if (s390_stack_size)
7857 {
7858 HOST_WIDE_INT stack_guard;
7859
7860 if (s390_stack_guard)
7861 stack_guard = s390_stack_guard;
7862 else
7863 {
7864 /* If no value for stack guard is provided the smallest power of 2
7865 larger than the current frame size is chosen. */
7866 stack_guard = 1;
7867 while (stack_guard < cfun_frame_layout.frame_size)
7868 stack_guard <<= 1;
7869 }
7870
7871 if (cfun_frame_layout.frame_size >= s390_stack_size)
7872 {
7873 warning (0, "frame size of function %qs is "
7874 HOST_WIDE_INT_PRINT_DEC
7875 " bytes exceeding user provided stack limit of "
7876 HOST_WIDE_INT_PRINT_DEC " bytes. "
7877 "An unconditional trap is added.",
7878 current_function_name(), cfun_frame_layout.frame_size,
7879 s390_stack_size);
7880 emit_insn (gen_trap ());
7881 }
7882 else
7883 {
7884 /* stack_guard has to be smaller than s390_stack_size.
7885 Otherwise we would emit an AND with zero which would
7886 not match the test under mask pattern. */
7887 if (stack_guard >= s390_stack_size)
7888 {
7889 warning (0, "frame size of function %qs is "
7890 HOST_WIDE_INT_PRINT_DEC
7891 " bytes which is more than half the stack size. "
7892 "The dynamic check would not be reliable. "
7893 "No check emitted for this function.",
7894 current_function_name(),
7895 cfun_frame_layout.frame_size);
7896 }
7897 else
7898 {
7899 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7900 & ~(stack_guard - 1));
7901
7902 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7903 GEN_INT (stack_check_mask));
7904 if (TARGET_64BIT)
7905 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
7906 t, const0_rtx),
7907 t, const0_rtx, const0_rtx));
7908 else
7909 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
7910 t, const0_rtx),
7911 t, const0_rtx, const0_rtx));
7912 }
7913 }
7914 }
7915
7916 if (s390_warn_framesize > 0
7917 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7918 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7919 current_function_name (), cfun_frame_layout.frame_size);
7920
7921 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7922 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7923
7924 /* Save incoming stack pointer into temp reg. */
7925 if (TARGET_BACKCHAIN || next_fpr)
7926 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7927
7928 /* Subtract frame size from stack pointer. */
7929
7930 if (DISP_IN_RANGE (INTVAL (frame_off)))
7931 {
7932 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7933 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7934 frame_off));
7935 insn = emit_insn (insn);
7936 }
7937 else
7938 {
7939 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7940 frame_off = force_const_mem (Pmode, frame_off);
7941
7942 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7943 annotate_constant_pool_refs (&PATTERN (insn));
7944 }
7945
7946 RTX_FRAME_RELATED_P (insn) = 1;
7947 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7948 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7949 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7950 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7951 real_frame_off)));
7952
7953 /* Set backchain. */
7954
7955 if (TARGET_BACKCHAIN)
7956 {
7957 if (cfun_frame_layout.backchain_offset)
7958 addr = gen_rtx_MEM (Pmode,
7959 plus_constant (stack_pointer_rtx,
7960 cfun_frame_layout.backchain_offset));
7961 else
7962 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7963 set_mem_alias_set (addr, get_frame_alias_set ());
7964 insn = emit_insn (gen_move_insn (addr, temp_reg));
7965 }
7966
7967 /* If we support non-call exceptions (e.g. for Java),
7968 we need to make sure the backchain pointer is set up
7969 before any possibly trapping memory access. */
7970 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
7971 {
7972 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7973 emit_clobber (addr);
7974 }
7975 }
7976
7977 /* Save fprs 8 - 15 (64 bit ABI). */
7978
7979 if (cfun_save_high_fprs_p && next_fpr)
7980 {
7981 /* If the stack might be accessed through a different register
7982 we have to make sure that the stack pointer decrement is not
7983 moved below the use of the stack slots. */
7984 s390_emit_stack_tie ();
7985
7986 insn = emit_insn (gen_add2_insn (temp_reg,
7987 GEN_INT (cfun_frame_layout.f8_offset)));
7988
7989 offset = 0;
7990
7991 for (i = 24; i <= next_fpr; i++)
7992 if (cfun_fpr_bit_p (i - 16))
7993 {
7994 rtx addr = plus_constant (stack_pointer_rtx,
7995 cfun_frame_layout.frame_size
7996 + cfun_frame_layout.f8_offset
7997 + offset);
7998
7999 insn = save_fpr (temp_reg, offset, i);
8000 offset += 8;
8001 RTX_FRAME_RELATED_P (insn) = 1;
8002 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8003 gen_rtx_SET (VOIDmode,
8004 gen_rtx_MEM (DFmode, addr),
8005 gen_rtx_REG (DFmode, i)));
8006 }
8007 }
8008
8009 /* Set frame pointer, if needed. */
8010
8011 if (frame_pointer_needed)
8012 {
8013 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8014 RTX_FRAME_RELATED_P (insn) = 1;
8015 }
8016
8017 /* Set up got pointer, if needed. */
8018
8019 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8020 {
8021 rtx insns = s390_load_got ();
8022
8023 for (insn = insns; insn; insn = NEXT_INSN (insn))
8024 annotate_constant_pool_refs (&PATTERN (insn));
8025
8026 emit_insn (insns);
8027 }
8028
8029 if (TARGET_TPF_PROFILING)
8030 {
8031 /* Generate a BAS instruction to serve as a function
8032 entry intercept to facilitate the use of tracing
8033 algorithms located at the branch target. */
8034 emit_insn (gen_prologue_tpf ());
8035
8036 /* Emit a blockage here so that all code
8037 lies between the profiling mechanisms. */
8038 emit_insn (gen_blockage ());
8039 }
8040 }
8041
8042 /* Expand the epilogue into a bunch of separate insns. */
8043
8044 void
8045 s390_emit_epilogue (bool sibcall)
8046 {
8047 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8048 int area_bottom, area_top, offset = 0;
8049 int next_offset;
8050 rtvec p;
8051 int i;
8052
8053 if (TARGET_TPF_PROFILING)
8054 {
8055
8056 /* Generate a BAS instruction to serve as a function
8057 entry intercept to facilitate the use of tracing
8058 algorithms located at the branch target. */
8059
8060 /* Emit a blockage here so that all code
8061 lies between the profiling mechanisms. */
8062 emit_insn (gen_blockage ());
8063
8064 emit_insn (gen_epilogue_tpf ());
8065 }
8066
8067 /* Check whether to use frame or stack pointer for restore. */
8068
8069 frame_pointer = (frame_pointer_needed
8070 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8071
8072 s390_frame_area (&area_bottom, &area_top);
8073
8074 /* Check whether we can access the register save area.
8075 If not, increment the frame pointer as required. */
8076
8077 if (area_top <= area_bottom)
8078 {
8079 /* Nothing to restore. */
8080 }
8081 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8082 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8083 {
8084 /* Area is in range. */
8085 offset = cfun_frame_layout.frame_size;
8086 }
8087 else
8088 {
8089 rtx insn, frame_off, cfa;
8090
8091 offset = area_bottom < 0 ? -area_bottom : 0;
8092 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8093
8094 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8095 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8096 if (DISP_IN_RANGE (INTVAL (frame_off)))
8097 {
8098 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8099 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8100 insn = emit_insn (insn);
8101 }
8102 else
8103 {
8104 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8105 frame_off = force_const_mem (Pmode, frame_off);
8106
8107 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8108 annotate_constant_pool_refs (&PATTERN (insn));
8109 }
8110 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8111 RTX_FRAME_RELATED_P (insn) = 1;
8112 }
8113
8114 /* Restore call saved fprs. */
8115
8116 if (TARGET_64BIT)
8117 {
8118 if (cfun_save_high_fprs_p)
8119 {
8120 next_offset = cfun_frame_layout.f8_offset;
8121 for (i = 24; i < 32; i++)
8122 {
8123 if (cfun_fpr_bit_p (i - 16))
8124 {
8125 restore_fpr (frame_pointer,
8126 offset + next_offset, i);
8127 cfa_restores
8128 = alloc_reg_note (REG_CFA_RESTORE,
8129 gen_rtx_REG (DFmode, i), cfa_restores);
8130 next_offset += 8;
8131 }
8132 }
8133 }
8134
8135 }
8136 else
8137 {
8138 next_offset = cfun_frame_layout.f4_offset;
8139 for (i = 18; i < 20; i++)
8140 {
8141 if (cfun_fpr_bit_p (i - 16))
8142 {
8143 restore_fpr (frame_pointer,
8144 offset + next_offset, i);
8145 cfa_restores
8146 = alloc_reg_note (REG_CFA_RESTORE,
8147 gen_rtx_REG (DFmode, i), cfa_restores);
8148 next_offset += 8;
8149 }
8150 else if (!TARGET_PACKED_STACK)
8151 next_offset += 8;
8152 }
8153
8154 }
8155
8156 /* Return register. */
8157
8158 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8159
8160 /* Restore call saved gprs. */
8161
8162 if (cfun_frame_layout.first_restore_gpr != -1)
8163 {
8164 rtx insn, addr;
8165 int i;
8166
8167 /* Check for global register and save them
8168 to stack location from where they get restored. */
8169
8170 for (i = cfun_frame_layout.first_restore_gpr;
8171 i <= cfun_frame_layout.last_restore_gpr;
8172 i++)
8173 {
8174 if (global_not_special_regno_p (i))
8175 {
8176 addr = plus_constant (frame_pointer,
8177 offset + cfun_frame_layout.gprs_offset
8178 + (i - cfun_frame_layout.first_save_gpr_slot)
8179 * UNITS_PER_LONG);
8180 addr = gen_rtx_MEM (Pmode, addr);
8181 set_mem_alias_set (addr, get_frame_alias_set ());
8182 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8183 }
8184 else
8185 cfa_restores
8186 = alloc_reg_note (REG_CFA_RESTORE,
8187 gen_rtx_REG (Pmode, i), cfa_restores);
8188 }
8189
8190 if (! sibcall)
8191 {
8192 /* Fetch return address from stack before load multiple,
8193 this will do good for scheduling. */
8194
8195 if (cfun_frame_layout.save_return_addr_p
8196 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8197 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8198 {
8199 int return_regnum = find_unused_clobbered_reg();
8200 if (!return_regnum)
8201 return_regnum = 4;
8202 return_reg = gen_rtx_REG (Pmode, return_regnum);
8203
8204 addr = plus_constant (frame_pointer,
8205 offset + cfun_frame_layout.gprs_offset
8206 + (RETURN_REGNUM
8207 - cfun_frame_layout.first_save_gpr_slot)
8208 * UNITS_PER_LONG);
8209 addr = gen_rtx_MEM (Pmode, addr);
8210 set_mem_alias_set (addr, get_frame_alias_set ());
8211 emit_move_insn (return_reg, addr);
8212 }
8213 }
8214
8215 insn = restore_gprs (frame_pointer,
8216 offset + cfun_frame_layout.gprs_offset
8217 + (cfun_frame_layout.first_restore_gpr
8218 - cfun_frame_layout.first_save_gpr_slot)
8219 * UNITS_PER_LONG,
8220 cfun_frame_layout.first_restore_gpr,
8221 cfun_frame_layout.last_restore_gpr);
8222 insn = emit_insn (insn);
8223 REG_NOTES (insn) = cfa_restores;
8224 add_reg_note (insn, REG_CFA_DEF_CFA,
8225 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8226 RTX_FRAME_RELATED_P (insn) = 1;
8227 }
8228
8229 if (! sibcall)
8230 {
8231
8232 /* Return to caller. */
8233
8234 p = rtvec_alloc (2);
8235
8236 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8237 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8238 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8239 }
8240 }
8241
8242
8243 /* Return the size in bytes of a function argument of
8244 type TYPE and/or mode MODE. At least one of TYPE or
8245 MODE must be specified. */
8246
8247 static int
8248 s390_function_arg_size (enum machine_mode mode, const_tree type)
8249 {
8250 if (type)
8251 return int_size_in_bytes (type);
8252
8253 /* No type info available for some library calls ... */
8254 if (mode != BLKmode)
8255 return GET_MODE_SIZE (mode);
8256
8257 /* If we have neither type nor mode, abort */
8258 gcc_unreachable ();
8259 }
8260
8261 /* Return true if a function argument of type TYPE and mode MODE
8262 is to be passed in a floating-point register, if available. */
8263
8264 static bool
8265 s390_function_arg_float (enum machine_mode mode, tree type)
8266 {
8267 int size = s390_function_arg_size (mode, type);
8268 if (size > 8)
8269 return false;
8270
8271 /* Soft-float changes the ABI: no floating-point registers are used. */
8272 if (TARGET_SOFT_FLOAT)
8273 return false;
8274
8275 /* No type info available for some library calls ... */
8276 if (!type)
8277 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8278
8279 /* The ABI says that record types with a single member are treated
8280 just like that member would be. */
8281 while (TREE_CODE (type) == RECORD_TYPE)
8282 {
8283 tree field, single = NULL_TREE;
8284
8285 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8286 {
8287 if (TREE_CODE (field) != FIELD_DECL)
8288 continue;
8289
8290 if (single == NULL_TREE)
8291 single = TREE_TYPE (field);
8292 else
8293 return false;
8294 }
8295
8296 if (single == NULL_TREE)
8297 return false;
8298 else
8299 type = single;
8300 }
8301
8302 return TREE_CODE (type) == REAL_TYPE;
8303 }
8304
8305 /* Return true if a function argument of type TYPE and mode MODE
8306 is to be passed in an integer register, or a pair of integer
8307 registers, if available. */
8308
8309 static bool
8310 s390_function_arg_integer (enum machine_mode mode, tree type)
8311 {
8312 int size = s390_function_arg_size (mode, type);
8313 if (size > 8)
8314 return false;
8315
8316 /* No type info available for some library calls ... */
8317 if (!type)
8318 return GET_MODE_CLASS (mode) == MODE_INT
8319 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8320
8321 /* We accept small integral (and similar) types. */
8322 if (INTEGRAL_TYPE_P (type)
8323 || POINTER_TYPE_P (type)
8324 || TREE_CODE (type) == OFFSET_TYPE
8325 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8326 return true;
8327
8328 /* We also accept structs of size 1, 2, 4, 8 that are not
8329 passed in floating-point registers. */
8330 if (AGGREGATE_TYPE_P (type)
8331 && exact_log2 (size) >= 0
8332 && !s390_function_arg_float (mode, type))
8333 return true;
8334
8335 return false;
8336 }
8337
8338 /* Return 1 if a function argument of type TYPE and mode MODE
8339 is to be passed by reference. The ABI specifies that only
8340 structures of size 1, 2, 4, or 8 bytes are passed by value,
8341 all other structures (and complex numbers) are passed by
8342 reference. */
8343
8344 static bool
8345 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8346 enum machine_mode mode, const_tree type,
8347 bool named ATTRIBUTE_UNUSED)
8348 {
8349 int size = s390_function_arg_size (mode, type);
8350 if (size > 8)
8351 return true;
8352
8353 if (type)
8354 {
8355 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8356 return 1;
8357
8358 if (TREE_CODE (type) == COMPLEX_TYPE
8359 || TREE_CODE (type) == VECTOR_TYPE)
8360 return 1;
8361 }
8362
8363 return 0;
8364 }
8365
8366 /* Update the data in CUM to advance over an argument of mode MODE and
8367 data type TYPE. (TYPE is null for libcalls where that information
8368 may not be available.). The boolean NAMED specifies whether the
8369 argument is a named argument (as opposed to an unnamed argument
8370 matching an ellipsis). */
8371
8372 void
8373 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8374 tree type, int named ATTRIBUTE_UNUSED)
8375 {
8376 if (s390_function_arg_float (mode, type))
8377 {
8378 cum->fprs += 1;
8379 }
8380 else if (s390_function_arg_integer (mode, type))
8381 {
8382 int size = s390_function_arg_size (mode, type);
8383 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8384 }
8385 else
8386 gcc_unreachable ();
8387 }
8388
8389 /* Define where to put the arguments to a function.
8390 Value is zero to push the argument on the stack,
8391 or a hard register in which to store the argument.
8392
8393 MODE is the argument's machine mode.
8394 TYPE is the data type of the argument (as a tree).
8395 This is null for libcalls where that information may
8396 not be available.
8397 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8398 the preceding args and about the function being called.
8399 NAMED is nonzero if this argument is a named parameter
8400 (otherwise it is an extra parameter matching an ellipsis).
8401
8402 On S/390, we use general purpose registers 2 through 6 to
8403 pass integer, pointer, and certain structure arguments, and
8404 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8405 to pass floating point arguments. All remaining arguments
8406 are pushed to the stack. */
8407
8408 rtx
8409 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8410 int named ATTRIBUTE_UNUSED)
8411 {
8412 if (s390_function_arg_float (mode, type))
8413 {
8414 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8415 return 0;
8416 else
8417 return gen_rtx_REG (mode, cum->fprs + 16);
8418 }
8419 else if (s390_function_arg_integer (mode, type))
8420 {
8421 int size = s390_function_arg_size (mode, type);
8422 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8423
8424 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8425 return 0;
8426 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8427 return gen_rtx_REG (mode, cum->gprs + 2);
8428 else if (n_gprs == 2)
8429 {
8430 rtvec p = rtvec_alloc (2);
8431
8432 RTVEC_ELT (p, 0)
8433 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8434 const0_rtx);
8435 RTVEC_ELT (p, 1)
8436 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8437 GEN_INT (4));
8438
8439 return gen_rtx_PARALLEL (mode, p);
8440 }
8441 }
8442
8443 /* After the real arguments, expand_call calls us once again
8444 with a void_type_node type. Whatever we return here is
8445 passed as operand 2 to the call expanders.
8446
8447 We don't need this feature ... */
8448 else if (type == void_type_node)
8449 return const0_rtx;
8450
8451 gcc_unreachable ();
8452 }
8453
8454 /* Return true if return values of type TYPE should be returned
8455 in a memory buffer whose address is passed by the caller as
8456 hidden first argument. */
8457
8458 static bool
8459 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8460 {
8461 /* We accept small integral (and similar) types. */
8462 if (INTEGRAL_TYPE_P (type)
8463 || POINTER_TYPE_P (type)
8464 || TREE_CODE (type) == OFFSET_TYPE
8465 || TREE_CODE (type) == REAL_TYPE)
8466 return int_size_in_bytes (type) > 8;
8467
8468 /* Aggregates and similar constructs are always returned
8469 in memory. */
8470 if (AGGREGATE_TYPE_P (type)
8471 || TREE_CODE (type) == COMPLEX_TYPE
8472 || TREE_CODE (type) == VECTOR_TYPE)
8473 return true;
8474
8475 /* ??? We get called on all sorts of random stuff from
8476 aggregate_value_p. We can't abort, but it's not clear
8477 what's safe to return. Pretend it's a struct I guess. */
8478 return true;
8479 }
8480
8481 /* Function arguments and return values are promoted to word size. */
8482
8483 static enum machine_mode
8484 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8485 int *punsignedp,
8486 const_tree fntype ATTRIBUTE_UNUSED,
8487 int for_return ATTRIBUTE_UNUSED)
8488 {
8489 if (INTEGRAL_MODE_P (mode)
8490 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8491 {
8492 if (POINTER_TYPE_P (type))
8493 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8494 return Pmode;
8495 }
8496
8497 return mode;
8498 }
8499
8500 /* Define where to return a (scalar) value of type TYPE.
8501 If TYPE is null, define where to return a (scalar)
8502 value of mode MODE from a libcall. */
8503
8504 rtx
8505 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8506 {
8507 if (type)
8508 {
8509 int unsignedp = TYPE_UNSIGNED (type);
8510 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8511 }
8512
8513 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8514 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8515
8516 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8517 return gen_rtx_REG (mode, 16);
8518 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8519 || UNITS_PER_LONG == UNITS_PER_WORD)
8520 return gen_rtx_REG (mode, 2);
8521 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8522 {
8523 rtvec p = rtvec_alloc (2);
8524
8525 RTVEC_ELT (p, 0)
8526 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8527 RTVEC_ELT (p, 1)
8528 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8529
8530 return gen_rtx_PARALLEL (mode, p);
8531 }
8532
8533 gcc_unreachable ();
8534 }
8535
8536
8537 /* Create and return the va_list datatype.
8538
8539 On S/390, va_list is an array type equivalent to
8540
8541 typedef struct __va_list_tag
8542 {
8543 long __gpr;
8544 long __fpr;
8545 void *__overflow_arg_area;
8546 void *__reg_save_area;
8547 } va_list[1];
8548
8549 where __gpr and __fpr hold the number of general purpose
8550 or floating point arguments used up to now, respectively,
8551 __overflow_arg_area points to the stack location of the
8552 next argument passed on the stack, and __reg_save_area
8553 always points to the start of the register area in the
8554 call frame of the current function. The function prologue
8555 saves all registers used for argument passing into this
8556 area if the function uses variable arguments. */
8557
8558 static tree
8559 s390_build_builtin_va_list (void)
8560 {
8561 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8562
8563 record = lang_hooks.types.make_type (RECORD_TYPE);
8564
8565 type_decl =
8566 build_decl (BUILTINS_LOCATION,
8567 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8568
8569 f_gpr = build_decl (BUILTINS_LOCATION,
8570 FIELD_DECL, get_identifier ("__gpr"),
8571 long_integer_type_node);
8572 f_fpr = build_decl (BUILTINS_LOCATION,
8573 FIELD_DECL, get_identifier ("__fpr"),
8574 long_integer_type_node);
8575 f_ovf = build_decl (BUILTINS_LOCATION,
8576 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8577 ptr_type_node);
8578 f_sav = build_decl (BUILTINS_LOCATION,
8579 FIELD_DECL, get_identifier ("__reg_save_area"),
8580 ptr_type_node);
8581
8582 va_list_gpr_counter_field = f_gpr;
8583 va_list_fpr_counter_field = f_fpr;
8584
8585 DECL_FIELD_CONTEXT (f_gpr) = record;
8586 DECL_FIELD_CONTEXT (f_fpr) = record;
8587 DECL_FIELD_CONTEXT (f_ovf) = record;
8588 DECL_FIELD_CONTEXT (f_sav) = record;
8589
8590 TREE_CHAIN (record) = type_decl;
8591 TYPE_NAME (record) = type_decl;
8592 TYPE_FIELDS (record) = f_gpr;
8593 TREE_CHAIN (f_gpr) = f_fpr;
8594 TREE_CHAIN (f_fpr) = f_ovf;
8595 TREE_CHAIN (f_ovf) = f_sav;
8596
8597 layout_type (record);
8598
8599 /* The correct type is an array type of one element. */
8600 return build_array_type (record, build_index_type (size_zero_node));
8601 }
8602
8603 /* Implement va_start by filling the va_list structure VALIST.
8604 STDARG_P is always true, and ignored.
8605 NEXTARG points to the first anonymous stack argument.
8606
8607 The following global variables are used to initialize
8608 the va_list structure:
8609
8610 crtl->args.info:
8611 holds number of gprs and fprs used for named arguments.
8612 crtl->args.arg_offset_rtx:
8613 holds the offset of the first anonymous stack argument
8614 (relative to the virtual arg pointer). */
8615
8616 static void
8617 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8618 {
8619 HOST_WIDE_INT n_gpr, n_fpr;
8620 int off;
8621 tree f_gpr, f_fpr, f_ovf, f_sav;
8622 tree gpr, fpr, ovf, sav, t;
8623
8624 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8625 f_fpr = TREE_CHAIN (f_gpr);
8626 f_ovf = TREE_CHAIN (f_fpr);
8627 f_sav = TREE_CHAIN (f_ovf);
8628
8629 valist = build_va_arg_indirect_ref (valist);
8630 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8631 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8632 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8633 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8634
8635 /* Count number of gp and fp argument registers used. */
8636
8637 n_gpr = crtl->args.info.gprs;
8638 n_fpr = crtl->args.info.fprs;
8639
8640 if (cfun->va_list_gpr_size)
8641 {
8642 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8643 build_int_cst (NULL_TREE, n_gpr));
8644 TREE_SIDE_EFFECTS (t) = 1;
8645 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8646 }
8647
8648 if (cfun->va_list_fpr_size)
8649 {
8650 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8651 build_int_cst (NULL_TREE, n_fpr));
8652 TREE_SIDE_EFFECTS (t) = 1;
8653 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8654 }
8655
8656 /* Find the overflow area. */
8657 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8658 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8659 {
8660 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8661
8662 off = INTVAL (crtl->args.arg_offset_rtx);
8663 off = off < 0 ? 0 : off;
8664 if (TARGET_DEBUG_ARG)
8665 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8666 (int)n_gpr, (int)n_fpr, off);
8667
8668 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8669
8670 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8671 TREE_SIDE_EFFECTS (t) = 1;
8672 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8673 }
8674
8675 /* Find the register save area. */
8676 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8677 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8678 {
8679 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8680 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8681 size_int (-RETURN_REGNUM * UNITS_PER_LONG));
8682
8683 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8684 TREE_SIDE_EFFECTS (t) = 1;
8685 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8686 }
8687 }
8688
8689 /* Implement va_arg by updating the va_list structure
8690 VALIST as required to retrieve an argument of type
8691 TYPE, and returning that argument.
8692
8693 Generates code equivalent to:
8694
8695 if (integral value) {
8696 if (size <= 4 && args.gpr < 5 ||
8697 size > 4 && args.gpr < 4 )
8698 ret = args.reg_save_area[args.gpr+8]
8699 else
8700 ret = *args.overflow_arg_area++;
8701 } else if (float value) {
8702 if (args.fgpr < 2)
8703 ret = args.reg_save_area[args.fpr+64]
8704 else
8705 ret = *args.overflow_arg_area++;
8706 } else if (aggregate value) {
8707 if (args.gpr < 5)
8708 ret = *args.reg_save_area[args.gpr]
8709 else
8710 ret = **args.overflow_arg_area++;
8711 } */
8712
8713 static tree
8714 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8715 gimple_seq *post_p ATTRIBUTE_UNUSED)
8716 {
8717 tree f_gpr, f_fpr, f_ovf, f_sav;
8718 tree gpr, fpr, ovf, sav, reg, t, u;
8719 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8720 tree lab_false, lab_over, addr;
8721
8722 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8723 f_fpr = TREE_CHAIN (f_gpr);
8724 f_ovf = TREE_CHAIN (f_fpr);
8725 f_sav = TREE_CHAIN (f_ovf);
8726
8727 valist = build_va_arg_indirect_ref (valist);
8728 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8729 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8730 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8731
8732 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8733 both appear on a lhs. */
8734 valist = unshare_expr (valist);
8735 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8736
8737 size = int_size_in_bytes (type);
8738
8739 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8740 {
8741 if (TARGET_DEBUG_ARG)
8742 {
8743 fprintf (stderr, "va_arg: aggregate type");
8744 debug_tree (type);
8745 }
8746
8747 /* Aggregates are passed by reference. */
8748 indirect_p = 1;
8749 reg = gpr;
8750 n_reg = 1;
8751
8752 /* kernel stack layout on 31 bit: It is assumed here that no padding
8753 will be added by s390_frame_info because for va_args always an even
8754 number of gprs has to be saved r15-r2 = 14 regs. */
8755 sav_ofs = 2 * UNITS_PER_LONG;
8756 sav_scale = UNITS_PER_LONG;
8757 size = UNITS_PER_LONG;
8758 max_reg = GP_ARG_NUM_REG - n_reg;
8759 }
8760 else if (s390_function_arg_float (TYPE_MODE (type), type))
8761 {
8762 if (TARGET_DEBUG_ARG)
8763 {
8764 fprintf (stderr, "va_arg: float type");
8765 debug_tree (type);
8766 }
8767
8768 /* FP args go in FP registers, if present. */
8769 indirect_p = 0;
8770 reg = fpr;
8771 n_reg = 1;
8772 sav_ofs = 16 * UNITS_PER_LONG;
8773 sav_scale = 8;
8774 max_reg = FP_ARG_NUM_REG - n_reg;
8775 }
8776 else
8777 {
8778 if (TARGET_DEBUG_ARG)
8779 {
8780 fprintf (stderr, "va_arg: other type");
8781 debug_tree (type);
8782 }
8783
8784 /* Otherwise into GP registers. */
8785 indirect_p = 0;
8786 reg = gpr;
8787 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8788
8789 /* kernel stack layout on 31 bit: It is assumed here that no padding
8790 will be added by s390_frame_info because for va_args always an even
8791 number of gprs has to be saved r15-r2 = 14 regs. */
8792 sav_ofs = 2 * UNITS_PER_LONG;
8793
8794 if (size < UNITS_PER_LONG)
8795 sav_ofs += UNITS_PER_LONG - size;
8796
8797 sav_scale = UNITS_PER_LONG;
8798 max_reg = GP_ARG_NUM_REG - n_reg;
8799 }
8800
8801 /* Pull the value out of the saved registers ... */
8802
8803 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8804 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8805 addr = create_tmp_var (ptr_type_node, "addr");
8806
8807 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8808 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8809 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8810 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8811 gimplify_and_add (t, pre_p);
8812
8813 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8814 size_int (sav_ofs));
8815 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8816 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8817 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8818
8819 gimplify_assign (addr, t, pre_p);
8820
8821 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8822
8823 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8824
8825
8826 /* ... Otherwise out of the overflow area. */
8827
8828 t = ovf;
8829 if (size < UNITS_PER_LONG)
8830 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8831 size_int (UNITS_PER_LONG - size));
8832
8833 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8834
8835 gimplify_assign (addr, t, pre_p);
8836
8837 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8838 size_int (size));
8839 gimplify_assign (ovf, t, pre_p);
8840
8841 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8842
8843
8844 /* Increment register save count. */
8845
8846 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8847 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8848 gimplify_and_add (u, pre_p);
8849
8850 if (indirect_p)
8851 {
8852 t = build_pointer_type_for_mode (build_pointer_type (type),
8853 ptr_mode, true);
8854 addr = fold_convert (t, addr);
8855 addr = build_va_arg_indirect_ref (addr);
8856 }
8857 else
8858 {
8859 t = build_pointer_type_for_mode (type, ptr_mode, true);
8860 addr = fold_convert (t, addr);
8861 }
8862
8863 return build_va_arg_indirect_ref (addr);
8864 }
8865
8866
8867 /* Builtins. */
8868
8869 enum s390_builtin
8870 {
8871 S390_BUILTIN_THREAD_POINTER,
8872 S390_BUILTIN_SET_THREAD_POINTER,
8873
8874 S390_BUILTIN_max
8875 };
8876
8877 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8878 CODE_FOR_get_tp_64,
8879 CODE_FOR_set_tp_64
8880 };
8881
8882 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8883 CODE_FOR_get_tp_31,
8884 CODE_FOR_set_tp_31
8885 };
8886
8887 static void
8888 s390_init_builtins (void)
8889 {
8890 tree ftype;
8891
8892 ftype = build_function_type (ptr_type_node, void_list_node);
8893 add_builtin_function ("__builtin_thread_pointer", ftype,
8894 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8895 NULL, NULL_TREE);
8896
8897 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8898 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8899 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8900 NULL, NULL_TREE);
8901 }
8902
8903 /* Expand an expression EXP that calls a built-in function,
8904 with result going to TARGET if that's convenient
8905 (and in mode MODE if that's convenient).
8906 SUBTARGET may be used as the target for computing one of EXP's operands.
8907 IGNORE is nonzero if the value is to be ignored. */
8908
8909 static rtx
8910 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8911 enum machine_mode mode ATTRIBUTE_UNUSED,
8912 int ignore ATTRIBUTE_UNUSED)
8913 {
8914 #define MAX_ARGS 2
8915
8916 enum insn_code const *code_for_builtin =
8917 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8918
8919 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8920 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8921 enum insn_code icode;
8922 rtx op[MAX_ARGS], pat;
8923 int arity;
8924 bool nonvoid;
8925 tree arg;
8926 call_expr_arg_iterator iter;
8927
8928 if (fcode >= S390_BUILTIN_max)
8929 internal_error ("bad builtin fcode");
8930 icode = code_for_builtin[fcode];
8931 if (icode == 0)
8932 internal_error ("bad builtin fcode");
8933
8934 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8935
8936 arity = 0;
8937 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8938 {
8939 const struct insn_operand_data *insn_op;
8940
8941 if (arg == error_mark_node)
8942 return NULL_RTX;
8943 if (arity > MAX_ARGS)
8944 return NULL_RTX;
8945
8946 insn_op = &insn_data[icode].operand[arity + nonvoid];
8947
8948 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8949
8950 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8951 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8952 arity++;
8953 }
8954
8955 if (nonvoid)
8956 {
8957 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8958 if (!target
8959 || GET_MODE (target) != tmode
8960 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8961 target = gen_reg_rtx (tmode);
8962 }
8963
8964 switch (arity)
8965 {
8966 case 0:
8967 pat = GEN_FCN (icode) (target);
8968 break;
8969 case 1:
8970 if (nonvoid)
8971 pat = GEN_FCN (icode) (target, op[0]);
8972 else
8973 pat = GEN_FCN (icode) (op[0]);
8974 break;
8975 case 2:
8976 pat = GEN_FCN (icode) (target, op[0], op[1]);
8977 break;
8978 default:
8979 gcc_unreachable ();
8980 }
8981 if (!pat)
8982 return NULL_RTX;
8983 emit_insn (pat);
8984
8985 if (nonvoid)
8986 return target;
8987 else
8988 return const0_rtx;
8989 }
8990
8991
8992 /* Output assembly code for the trampoline template to
8993 stdio stream FILE.
8994
8995 On S/390, we use gpr 1 internally in the trampoline code;
8996 gpr 0 is used to hold the static chain. */
8997
8998 static void
8999 s390_asm_trampoline_template (FILE *file)
9000 {
9001 rtx op[2];
9002 op[0] = gen_rtx_REG (Pmode, 0);
9003 op[1] = gen_rtx_REG (Pmode, 1);
9004
9005 if (TARGET_64BIT)
9006 {
9007 output_asm_insn ("basr\t%1,0", op);
9008 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
9009 output_asm_insn ("br\t%1", op);
9010 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9011 }
9012 else
9013 {
9014 output_asm_insn ("basr\t%1,0", op);
9015 output_asm_insn ("lm\t%0,%1,6(%1)", op);
9016 output_asm_insn ("br\t%1", op);
9017 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9018 }
9019 }
9020
9021 /* Emit RTL insns to initialize the variable parts of a trampoline.
9022 FNADDR is an RTX for the address of the function's pure code.
9023 CXT is an RTX for the static chain value for the function. */
9024
9025 static void
9026 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9027 {
9028 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9029 rtx mem;
9030
9031 emit_block_move (m_tramp, assemble_trampoline_template (),
9032 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
9033
9034 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
9035 emit_move_insn (mem, cxt);
9036 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
9037 emit_move_insn (mem, fnaddr);
9038 }
9039
9040 /* Output assembler code to FILE to increment profiler label # LABELNO
9041 for profiling a function entry. */
9042
9043 void
9044 s390_function_profiler (FILE *file, int labelno)
9045 {
9046 rtx op[7];
9047
9048 char label[128];
9049 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9050
9051 fprintf (file, "# function profiler \n");
9052
9053 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9054 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9055 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9056
9057 op[2] = gen_rtx_REG (Pmode, 1);
9058 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9059 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9060
9061 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9062 if (flag_pic)
9063 {
9064 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9065 op[4] = gen_rtx_CONST (Pmode, op[4]);
9066 }
9067
9068 if (TARGET_64BIT)
9069 {
9070 output_asm_insn ("stg\t%0,%1", op);
9071 output_asm_insn ("larl\t%2,%3", op);
9072 output_asm_insn ("brasl\t%0,%4", op);
9073 output_asm_insn ("lg\t%0,%1", op);
9074 }
9075 else if (!flag_pic)
9076 {
9077 op[6] = gen_label_rtx ();
9078
9079 output_asm_insn ("st\t%0,%1", op);
9080 output_asm_insn ("bras\t%2,%l6", op);
9081 output_asm_insn (".long\t%4", op);
9082 output_asm_insn (".long\t%3", op);
9083 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9084 output_asm_insn ("l\t%0,0(%2)", op);
9085 output_asm_insn ("l\t%2,4(%2)", op);
9086 output_asm_insn ("basr\t%0,%0", op);
9087 output_asm_insn ("l\t%0,%1", op);
9088 }
9089 else
9090 {
9091 op[5] = gen_label_rtx ();
9092 op[6] = gen_label_rtx ();
9093
9094 output_asm_insn ("st\t%0,%1", op);
9095 output_asm_insn ("bras\t%2,%l6", op);
9096 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9097 output_asm_insn (".long\t%4-%l5", op);
9098 output_asm_insn (".long\t%3-%l5", op);
9099 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9100 output_asm_insn ("lr\t%0,%2", op);
9101 output_asm_insn ("a\t%0,0(%2)", op);
9102 output_asm_insn ("a\t%2,4(%2)", op);
9103 output_asm_insn ("basr\t%0,%0", op);
9104 output_asm_insn ("l\t%0,%1", op);
9105 }
9106 }
9107
9108 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9109 into its SYMBOL_REF_FLAGS. */
9110
9111 static void
9112 s390_encode_section_info (tree decl, rtx rtl, int first)
9113 {
9114 default_encode_section_info (decl, rtl, first);
9115
9116 if (TREE_CODE (decl) == VAR_DECL)
9117 {
9118 /* If a variable has a forced alignment to < 2 bytes, mark it
9119 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9120 operand. */
9121 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9122 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9123 if (!DECL_SIZE (decl)
9124 || !DECL_ALIGN (decl)
9125 || !host_integerp (DECL_SIZE (decl), 0)
9126 || (DECL_ALIGN (decl) <= 64
9127 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9128 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9129 }
9130
9131 /* Literal pool references don't have a decl so they are handled
9132 differently here. We rely on the information in the MEM_ALIGN
9133 entry to decide upon natural alignment. */
9134 if (MEM_P (rtl)
9135 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9136 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9137 && (MEM_ALIGN (rtl) == 0
9138 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9139 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9140 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9141 }
9142
9143 /* Output thunk to FILE that implements a C++ virtual function call (with
9144 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9145 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9146 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9147 relative to the resulting this pointer. */
9148
9149 static void
9150 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9151 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9152 tree function)
9153 {
9154 rtx op[10];
9155 int nonlocal = 0;
9156
9157 /* Make sure unwind info is emitted for the thunk if needed. */
9158 final_start_function (emit_barrier (), file, 1);
9159
9160 /* Operand 0 is the target function. */
9161 op[0] = XEXP (DECL_RTL (function), 0);
9162 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9163 {
9164 nonlocal = 1;
9165 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9166 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9167 op[0] = gen_rtx_CONST (Pmode, op[0]);
9168 }
9169
9170 /* Operand 1 is the 'this' pointer. */
9171 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9172 op[1] = gen_rtx_REG (Pmode, 3);
9173 else
9174 op[1] = gen_rtx_REG (Pmode, 2);
9175
9176 /* Operand 2 is the delta. */
9177 op[2] = GEN_INT (delta);
9178
9179 /* Operand 3 is the vcall_offset. */
9180 op[3] = GEN_INT (vcall_offset);
9181
9182 /* Operand 4 is the temporary register. */
9183 op[4] = gen_rtx_REG (Pmode, 1);
9184
9185 /* Operands 5 to 8 can be used as labels. */
9186 op[5] = NULL_RTX;
9187 op[6] = NULL_RTX;
9188 op[7] = NULL_RTX;
9189 op[8] = NULL_RTX;
9190
9191 /* Operand 9 can be used for temporary register. */
9192 op[9] = NULL_RTX;
9193
9194 /* Generate code. */
9195 if (TARGET_64BIT)
9196 {
9197 /* Setup literal pool pointer if required. */
9198 if ((!DISP_IN_RANGE (delta)
9199 && !CONST_OK_FOR_K (delta)
9200 && !CONST_OK_FOR_Os (delta))
9201 || (!DISP_IN_RANGE (vcall_offset)
9202 && !CONST_OK_FOR_K (vcall_offset)
9203 && !CONST_OK_FOR_Os (vcall_offset)))
9204 {
9205 op[5] = gen_label_rtx ();
9206 output_asm_insn ("larl\t%4,%5", op);
9207 }
9208
9209 /* Add DELTA to this pointer. */
9210 if (delta)
9211 {
9212 if (CONST_OK_FOR_J (delta))
9213 output_asm_insn ("la\t%1,%2(%1)", op);
9214 else if (DISP_IN_RANGE (delta))
9215 output_asm_insn ("lay\t%1,%2(%1)", op);
9216 else if (CONST_OK_FOR_K (delta))
9217 output_asm_insn ("aghi\t%1,%2", op);
9218 else if (CONST_OK_FOR_Os (delta))
9219 output_asm_insn ("agfi\t%1,%2", op);
9220 else
9221 {
9222 op[6] = gen_label_rtx ();
9223 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9224 }
9225 }
9226
9227 /* Perform vcall adjustment. */
9228 if (vcall_offset)
9229 {
9230 if (DISP_IN_RANGE (vcall_offset))
9231 {
9232 output_asm_insn ("lg\t%4,0(%1)", op);
9233 output_asm_insn ("ag\t%1,%3(%4)", op);
9234 }
9235 else if (CONST_OK_FOR_K (vcall_offset))
9236 {
9237 output_asm_insn ("lghi\t%4,%3", op);
9238 output_asm_insn ("ag\t%4,0(%1)", op);
9239 output_asm_insn ("ag\t%1,0(%4)", op);
9240 }
9241 else if (CONST_OK_FOR_Os (vcall_offset))
9242 {
9243 output_asm_insn ("lgfi\t%4,%3", op);
9244 output_asm_insn ("ag\t%4,0(%1)", op);
9245 output_asm_insn ("ag\t%1,0(%4)", op);
9246 }
9247 else
9248 {
9249 op[7] = gen_label_rtx ();
9250 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9251 output_asm_insn ("ag\t%4,0(%1)", op);
9252 output_asm_insn ("ag\t%1,0(%4)", op);
9253 }
9254 }
9255
9256 /* Jump to target. */
9257 output_asm_insn ("jg\t%0", op);
9258
9259 /* Output literal pool if required. */
9260 if (op[5])
9261 {
9262 output_asm_insn (".align\t4", op);
9263 targetm.asm_out.internal_label (file, "L",
9264 CODE_LABEL_NUMBER (op[5]));
9265 }
9266 if (op[6])
9267 {
9268 targetm.asm_out.internal_label (file, "L",
9269 CODE_LABEL_NUMBER (op[6]));
9270 output_asm_insn (".long\t%2", op);
9271 }
9272 if (op[7])
9273 {
9274 targetm.asm_out.internal_label (file, "L",
9275 CODE_LABEL_NUMBER (op[7]));
9276 output_asm_insn (".long\t%3", op);
9277 }
9278 }
9279 else
9280 {
9281 /* Setup base pointer if required. */
9282 if (!vcall_offset
9283 || (!DISP_IN_RANGE (delta)
9284 && !CONST_OK_FOR_K (delta)
9285 && !CONST_OK_FOR_Os (delta))
9286 || (!DISP_IN_RANGE (delta)
9287 && !CONST_OK_FOR_K (vcall_offset)
9288 && !CONST_OK_FOR_Os (vcall_offset)))
9289 {
9290 op[5] = gen_label_rtx ();
9291 output_asm_insn ("basr\t%4,0", op);
9292 targetm.asm_out.internal_label (file, "L",
9293 CODE_LABEL_NUMBER (op[5]));
9294 }
9295
9296 /* Add DELTA to this pointer. */
9297 if (delta)
9298 {
9299 if (CONST_OK_FOR_J (delta))
9300 output_asm_insn ("la\t%1,%2(%1)", op);
9301 else if (DISP_IN_RANGE (delta))
9302 output_asm_insn ("lay\t%1,%2(%1)", op);
9303 else if (CONST_OK_FOR_K (delta))
9304 output_asm_insn ("ahi\t%1,%2", op);
9305 else if (CONST_OK_FOR_Os (delta))
9306 output_asm_insn ("afi\t%1,%2", op);
9307 else
9308 {
9309 op[6] = gen_label_rtx ();
9310 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9311 }
9312 }
9313
9314 /* Perform vcall adjustment. */
9315 if (vcall_offset)
9316 {
9317 if (CONST_OK_FOR_J (vcall_offset))
9318 {
9319 output_asm_insn ("l\t%4,0(%1)", op);
9320 output_asm_insn ("a\t%1,%3(%4)", op);
9321 }
9322 else if (DISP_IN_RANGE (vcall_offset))
9323 {
9324 output_asm_insn ("l\t%4,0(%1)", op);
9325 output_asm_insn ("ay\t%1,%3(%4)", op);
9326 }
9327 else if (CONST_OK_FOR_K (vcall_offset))
9328 {
9329 output_asm_insn ("lhi\t%4,%3", op);
9330 output_asm_insn ("a\t%4,0(%1)", op);
9331 output_asm_insn ("a\t%1,0(%4)", op);
9332 }
9333 else if (CONST_OK_FOR_Os (vcall_offset))
9334 {
9335 output_asm_insn ("iilf\t%4,%3", op);
9336 output_asm_insn ("a\t%4,0(%1)", op);
9337 output_asm_insn ("a\t%1,0(%4)", op);
9338 }
9339 else
9340 {
9341 op[7] = gen_label_rtx ();
9342 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9343 output_asm_insn ("a\t%4,0(%1)", op);
9344 output_asm_insn ("a\t%1,0(%4)", op);
9345 }
9346
9347 /* We had to clobber the base pointer register.
9348 Re-setup the base pointer (with a different base). */
9349 op[5] = gen_label_rtx ();
9350 output_asm_insn ("basr\t%4,0", op);
9351 targetm.asm_out.internal_label (file, "L",
9352 CODE_LABEL_NUMBER (op[5]));
9353 }
9354
9355 /* Jump to target. */
9356 op[8] = gen_label_rtx ();
9357
9358 if (!flag_pic)
9359 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9360 else if (!nonlocal)
9361 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9362 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9363 else if (flag_pic == 1)
9364 {
9365 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9366 output_asm_insn ("l\t%4,%0(%4)", op);
9367 }
9368 else if (flag_pic == 2)
9369 {
9370 op[9] = gen_rtx_REG (Pmode, 0);
9371 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9372 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9373 output_asm_insn ("ar\t%4,%9", op);
9374 output_asm_insn ("l\t%4,0(%4)", op);
9375 }
9376
9377 output_asm_insn ("br\t%4", op);
9378
9379 /* Output literal pool. */
9380 output_asm_insn (".align\t4", op);
9381
9382 if (nonlocal && flag_pic == 2)
9383 output_asm_insn (".long\t%0", op);
9384 if (nonlocal)
9385 {
9386 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9387 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9388 }
9389
9390 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9391 if (!flag_pic)
9392 output_asm_insn (".long\t%0", op);
9393 else
9394 output_asm_insn (".long\t%0-%5", op);
9395
9396 if (op[6])
9397 {
9398 targetm.asm_out.internal_label (file, "L",
9399 CODE_LABEL_NUMBER (op[6]));
9400 output_asm_insn (".long\t%2", op);
9401 }
9402 if (op[7])
9403 {
9404 targetm.asm_out.internal_label (file, "L",
9405 CODE_LABEL_NUMBER (op[7]));
9406 output_asm_insn (".long\t%3", op);
9407 }
9408 }
9409 final_end_function ();
9410 }
9411
9412 static bool
9413 s390_valid_pointer_mode (enum machine_mode mode)
9414 {
9415 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9416 }
9417
9418 /* Checks whether the given CALL_EXPR would use a caller
9419 saved register. This is used to decide whether sibling call
9420 optimization could be performed on the respective function
9421 call. */
9422
9423 static bool
9424 s390_call_saved_register_used (tree call_expr)
9425 {
9426 CUMULATIVE_ARGS cum;
9427 tree parameter;
9428 enum machine_mode mode;
9429 tree type;
9430 rtx parm_rtx;
9431 int reg, i;
9432
9433 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9434
9435 for (i = 0; i < call_expr_nargs (call_expr); i++)
9436 {
9437 parameter = CALL_EXPR_ARG (call_expr, i);
9438 gcc_assert (parameter);
9439
9440 /* For an undeclared variable passed as parameter we will get
9441 an ERROR_MARK node here. */
9442 if (TREE_CODE (parameter) == ERROR_MARK)
9443 return true;
9444
9445 type = TREE_TYPE (parameter);
9446 gcc_assert (type);
9447
9448 mode = TYPE_MODE (type);
9449 gcc_assert (mode);
9450
9451 if (pass_by_reference (&cum, mode, type, true))
9452 {
9453 mode = Pmode;
9454 type = build_pointer_type (type);
9455 }
9456
9457 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9458
9459 s390_function_arg_advance (&cum, mode, type, 0);
9460
9461 if (!parm_rtx)
9462 continue;
9463
9464 if (REG_P (parm_rtx))
9465 {
9466 for (reg = 0;
9467 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9468 reg++)
9469 if (!call_used_regs[reg + REGNO (parm_rtx)])
9470 return true;
9471 }
9472
9473 if (GET_CODE (parm_rtx) == PARALLEL)
9474 {
9475 int i;
9476
9477 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9478 {
9479 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9480
9481 gcc_assert (REG_P (r));
9482
9483 for (reg = 0;
9484 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9485 reg++)
9486 if (!call_used_regs[reg + REGNO (r)])
9487 return true;
9488 }
9489 }
9490
9491 }
9492 return false;
9493 }
9494
9495 /* Return true if the given call expression can be
9496 turned into a sibling call.
9497 DECL holds the declaration of the function to be called whereas
9498 EXP is the call expression itself. */
9499
9500 static bool
9501 s390_function_ok_for_sibcall (tree decl, tree exp)
9502 {
9503 /* The TPF epilogue uses register 1. */
9504 if (TARGET_TPF_PROFILING)
9505 return false;
9506
9507 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9508 which would have to be restored before the sibcall. */
9509 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9510 return false;
9511
9512 /* Register 6 on s390 is available as an argument register but unfortunately
9513 "caller saved". This makes functions needing this register for arguments
9514 not suitable for sibcalls. */
9515 return !s390_call_saved_register_used (exp);
9516 }
9517
9518 /* Return the fixed registers used for condition codes. */
9519
9520 static bool
9521 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9522 {
9523 *p1 = CC_REGNUM;
9524 *p2 = INVALID_REGNUM;
9525
9526 return true;
9527 }
9528
9529 /* This function is used by the call expanders of the machine description.
9530 It emits the call insn itself together with the necessary operations
9531 to adjust the target address and returns the emitted insn.
9532 ADDR_LOCATION is the target address rtx
9533 TLS_CALL the location of the thread-local symbol
9534 RESULT_REG the register where the result of the call should be stored
9535 RETADDR_REG the register where the return address should be stored
9536 If this parameter is NULL_RTX the call is considered
9537 to be a sibling call. */
9538
9539 rtx
9540 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9541 rtx retaddr_reg)
9542 {
9543 bool plt_call = false;
9544 rtx insn;
9545 rtx call;
9546 rtx clobber;
9547 rtvec vec;
9548
9549 /* Direct function calls need special treatment. */
9550 if (GET_CODE (addr_location) == SYMBOL_REF)
9551 {
9552 /* When calling a global routine in PIC mode, we must
9553 replace the symbol itself with the PLT stub. */
9554 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9555 {
9556 if (retaddr_reg != NULL_RTX)
9557 {
9558 addr_location = gen_rtx_UNSPEC (Pmode,
9559 gen_rtvec (1, addr_location),
9560 UNSPEC_PLT);
9561 addr_location = gen_rtx_CONST (Pmode, addr_location);
9562 plt_call = true;
9563 }
9564 else
9565 /* For -fpic code the PLT entries might use r12 which is
9566 call-saved. Therefore we cannot do a sibcall when
9567 calling directly using a symbol ref. When reaching
9568 this point we decided (in s390_function_ok_for_sibcall)
9569 to do a sibcall for a function pointer but one of the
9570 optimizers was able to get rid of the function pointer
9571 by propagating the symbol ref into the call. This
9572 optimization is illegal for S/390 so we turn the direct
9573 call into a indirect call again. */
9574 addr_location = force_reg (Pmode, addr_location);
9575 }
9576
9577 /* Unless we can use the bras(l) insn, force the
9578 routine address into a register. */
9579 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9580 {
9581 if (flag_pic)
9582 addr_location = legitimize_pic_address (addr_location, 0);
9583 else
9584 addr_location = force_reg (Pmode, addr_location);
9585 }
9586 }
9587
9588 /* If it is already an indirect call or the code above moved the
9589 SYMBOL_REF to somewhere else make sure the address can be found in
9590 register 1. */
9591 if (retaddr_reg == NULL_RTX
9592 && GET_CODE (addr_location) != SYMBOL_REF
9593 && !plt_call)
9594 {
9595 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9596 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9597 }
9598
9599 addr_location = gen_rtx_MEM (QImode, addr_location);
9600 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9601
9602 if (result_reg != NULL_RTX)
9603 call = gen_rtx_SET (VOIDmode, result_reg, call);
9604
9605 if (retaddr_reg != NULL_RTX)
9606 {
9607 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9608
9609 if (tls_call != NULL_RTX)
9610 vec = gen_rtvec (3, call, clobber,
9611 gen_rtx_USE (VOIDmode, tls_call));
9612 else
9613 vec = gen_rtvec (2, call, clobber);
9614
9615 call = gen_rtx_PARALLEL (VOIDmode, vec);
9616 }
9617
9618 insn = emit_call_insn (call);
9619
9620 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9621 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9622 {
9623 /* s390_function_ok_for_sibcall should
9624 have denied sibcalls in this case. */
9625 gcc_assert (retaddr_reg != NULL_RTX);
9626
9627 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9628 }
9629 return insn;
9630 }
9631
9632 /* Implement CONDITIONAL_REGISTER_USAGE. */
9633
9634 void
9635 s390_conditional_register_usage (void)
9636 {
9637 int i;
9638
9639 if (flag_pic)
9640 {
9641 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9642 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9643 }
9644 if (TARGET_CPU_ZARCH)
9645 {
9646 fixed_regs[BASE_REGNUM] = 0;
9647 call_used_regs[BASE_REGNUM] = 0;
9648 fixed_regs[RETURN_REGNUM] = 0;
9649 call_used_regs[RETURN_REGNUM] = 0;
9650 }
9651 if (TARGET_64BIT)
9652 {
9653 for (i = 24; i < 32; i++)
9654 call_used_regs[i] = call_really_used_regs[i] = 0;
9655 }
9656 else
9657 {
9658 for (i = 18; i < 20; i++)
9659 call_used_regs[i] = call_really_used_regs[i] = 0;
9660 }
9661
9662 if (TARGET_SOFT_FLOAT)
9663 {
9664 for (i = 16; i < 32; i++)
9665 call_used_regs[i] = fixed_regs[i] = 1;
9666 }
9667 }
9668
9669 /* Corresponding function to eh_return expander. */
9670
9671 static GTY(()) rtx s390_tpf_eh_return_symbol;
9672 void
9673 s390_emit_tpf_eh_return (rtx target)
9674 {
9675 rtx insn, reg;
9676
9677 if (!s390_tpf_eh_return_symbol)
9678 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9679
9680 reg = gen_rtx_REG (Pmode, 2);
9681
9682 emit_move_insn (reg, target);
9683 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9684 gen_rtx_REG (Pmode, RETURN_REGNUM));
9685 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9686
9687 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9688 }
9689
9690 /* Rework the prologue/epilogue to avoid saving/restoring
9691 registers unnecessarily. */
9692
9693 static void
9694 s390_optimize_prologue (void)
9695 {
9696 rtx insn, new_insn, next_insn;
9697
9698 /* Do a final recompute of the frame-related data. */
9699
9700 s390_update_frame_layout ();
9701
9702 /* If all special registers are in fact used, there's nothing we
9703 can do, so no point in walking the insn list. */
9704
9705 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9706 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9707 && (TARGET_CPU_ZARCH
9708 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9709 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9710 return;
9711
9712 /* Search for prologue/epilogue insns and replace them. */
9713
9714 for (insn = get_insns (); insn; insn = next_insn)
9715 {
9716 int first, last, off;
9717 rtx set, base, offset;
9718
9719 next_insn = NEXT_INSN (insn);
9720
9721 if (GET_CODE (insn) != INSN)
9722 continue;
9723
9724 if (GET_CODE (PATTERN (insn)) == PARALLEL
9725 && store_multiple_operation (PATTERN (insn), VOIDmode))
9726 {
9727 set = XVECEXP (PATTERN (insn), 0, 0);
9728 first = REGNO (SET_SRC (set));
9729 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9730 offset = const0_rtx;
9731 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9732 off = INTVAL (offset);
9733
9734 if (GET_CODE (base) != REG || off < 0)
9735 continue;
9736 if (cfun_frame_layout.first_save_gpr != -1
9737 && (cfun_frame_layout.first_save_gpr < first
9738 || cfun_frame_layout.last_save_gpr > last))
9739 continue;
9740 if (REGNO (base) != STACK_POINTER_REGNUM
9741 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9742 continue;
9743 if (first > BASE_REGNUM || last < BASE_REGNUM)
9744 continue;
9745
9746 if (cfun_frame_layout.first_save_gpr != -1)
9747 {
9748 new_insn = save_gprs (base,
9749 off + (cfun_frame_layout.first_save_gpr
9750 - first) * UNITS_PER_LONG,
9751 cfun_frame_layout.first_save_gpr,
9752 cfun_frame_layout.last_save_gpr);
9753 new_insn = emit_insn_before (new_insn, insn);
9754 INSN_ADDRESSES_NEW (new_insn, -1);
9755 }
9756
9757 remove_insn (insn);
9758 continue;
9759 }
9760
9761 if (cfun_frame_layout.first_save_gpr == -1
9762 && GET_CODE (PATTERN (insn)) == SET
9763 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9764 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9765 || (!TARGET_CPU_ZARCH
9766 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9767 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9768 {
9769 set = PATTERN (insn);
9770 first = REGNO (SET_SRC (set));
9771 offset = const0_rtx;
9772 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9773 off = INTVAL (offset);
9774
9775 if (GET_CODE (base) != REG || off < 0)
9776 continue;
9777 if (REGNO (base) != STACK_POINTER_REGNUM
9778 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9779 continue;
9780
9781 remove_insn (insn);
9782 continue;
9783 }
9784
9785 if (GET_CODE (PATTERN (insn)) == PARALLEL
9786 && load_multiple_operation (PATTERN (insn), VOIDmode))
9787 {
9788 set = XVECEXP (PATTERN (insn), 0, 0);
9789 first = REGNO (SET_DEST (set));
9790 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9791 offset = const0_rtx;
9792 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9793 off = INTVAL (offset);
9794
9795 if (GET_CODE (base) != REG || off < 0)
9796 continue;
9797 if (cfun_frame_layout.first_restore_gpr != -1
9798 && (cfun_frame_layout.first_restore_gpr < first
9799 || cfun_frame_layout.last_restore_gpr > last))
9800 continue;
9801 if (REGNO (base) != STACK_POINTER_REGNUM
9802 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9803 continue;
9804 if (first > BASE_REGNUM || last < BASE_REGNUM)
9805 continue;
9806
9807 if (cfun_frame_layout.first_restore_gpr != -1)
9808 {
9809 new_insn = restore_gprs (base,
9810 off + (cfun_frame_layout.first_restore_gpr
9811 - first) * UNITS_PER_LONG,
9812 cfun_frame_layout.first_restore_gpr,
9813 cfun_frame_layout.last_restore_gpr);
9814 new_insn = emit_insn_before (new_insn, insn);
9815 INSN_ADDRESSES_NEW (new_insn, -1);
9816 }
9817
9818 remove_insn (insn);
9819 continue;
9820 }
9821
9822 if (cfun_frame_layout.first_restore_gpr == -1
9823 && GET_CODE (PATTERN (insn)) == SET
9824 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9825 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9826 || (!TARGET_CPU_ZARCH
9827 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9828 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9829 {
9830 set = PATTERN (insn);
9831 first = REGNO (SET_DEST (set));
9832 offset = const0_rtx;
9833 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9834 off = INTVAL (offset);
9835
9836 if (GET_CODE (base) != REG || off < 0)
9837 continue;
9838 if (REGNO (base) != STACK_POINTER_REGNUM
9839 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9840 continue;
9841
9842 remove_insn (insn);
9843 continue;
9844 }
9845 }
9846 }
9847
9848 /* On z10 the dynamic branch prediction must see the backward jump in
9849 a window of 384 bytes. If not it falls back to the static
9850 prediction. This function rearranges the loop backward branch in a
9851 way which makes the static prediction always correct. The function
9852 returns true if it added an instruction. */
9853 static bool
9854 s390_z10_fix_long_loop_prediction (rtx insn)
9855 {
9856 rtx set = single_set (insn);
9857 rtx code_label, label_ref, new_label;
9858 rtx uncond_jump;
9859 rtx cur_insn;
9860 rtx tmp;
9861 int distance;
9862
9863 /* This will exclude branch on count and branch on index patterns
9864 since these are correctly statically predicted. */
9865 if (!set
9866 || SET_DEST (set) != pc_rtx
9867 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
9868 return false;
9869
9870 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
9871 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
9872
9873 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
9874
9875 code_label = XEXP (label_ref, 0);
9876
9877 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
9878 || INSN_ADDRESSES (INSN_UID (insn)) == -1
9879 || (INSN_ADDRESSES (INSN_UID (insn))
9880 - INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE))
9881 return false;
9882
9883 for (distance = 0, cur_insn = PREV_INSN (insn);
9884 distance < Z10_PREDICT_DISTANCE - 6;
9885 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
9886 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
9887 return false;
9888
9889 new_label = gen_label_rtx ();
9890 uncond_jump = emit_jump_insn_after (
9891 gen_rtx_SET (VOIDmode, pc_rtx,
9892 gen_rtx_LABEL_REF (VOIDmode, code_label)),
9893 insn);
9894 emit_label_after (new_label, uncond_jump);
9895
9896 tmp = XEXP (SET_SRC (set), 1);
9897 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
9898 XEXP (SET_SRC (set), 2) = tmp;
9899 INSN_CODE (insn) = -1;
9900
9901 XEXP (label_ref, 0) = new_label;
9902 JUMP_LABEL (insn) = new_label;
9903 JUMP_LABEL (uncond_jump) = code_label;
9904
9905 return true;
9906 }
9907
9908 /* Returns 1 if INSN reads the value of REG for purposes not related
9909 to addressing of memory, and 0 otherwise. */
9910 static int
9911 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9912 {
9913 return reg_referenced_p (reg, PATTERN (insn))
9914 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9915 }
9916
9917 /* Starting from INSN find_cond_jump looks downwards in the insn
9918 stream for a single jump insn which is the last user of the
9919 condition code set in INSN. */
9920 static rtx
9921 find_cond_jump (rtx insn)
9922 {
9923 for (; insn; insn = NEXT_INSN (insn))
9924 {
9925 rtx ite, cc;
9926
9927 if (LABEL_P (insn))
9928 break;
9929
9930 if (!JUMP_P (insn))
9931 {
9932 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9933 break;
9934 continue;
9935 }
9936
9937 /* This will be triggered by a return. */
9938 if (GET_CODE (PATTERN (insn)) != SET)
9939 break;
9940
9941 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9942 ite = SET_SRC (PATTERN (insn));
9943
9944 if (GET_CODE (ite) != IF_THEN_ELSE)
9945 break;
9946
9947 cc = XEXP (XEXP (ite, 0), 0);
9948 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9949 break;
9950
9951 if (find_reg_note (insn, REG_DEAD, cc))
9952 return insn;
9953 break;
9954 }
9955
9956 return NULL_RTX;
9957 }
9958
9959 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9960 the semantics does not change. If NULL_RTX is passed as COND the
9961 function tries to find the conditional jump starting with INSN. */
9962 static void
9963 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9964 {
9965 rtx tmp = *op0;
9966
9967 if (cond == NULL_RTX)
9968 {
9969 rtx jump = find_cond_jump (NEXT_INSN (insn));
9970 jump = jump ? single_set (jump) : NULL_RTX;
9971
9972 if (jump == NULL_RTX)
9973 return;
9974
9975 cond = XEXP (XEXP (jump, 1), 0);
9976 }
9977
9978 *op0 = *op1;
9979 *op1 = tmp;
9980 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9981 }
9982
9983 /* On z10, instructions of the compare-and-branch family have the
9984 property to access the register occurring as second operand with
9985 its bits complemented. If such a compare is grouped with a second
9986 instruction that accesses the same register non-complemented, and
9987 if that register's value is delivered via a bypass, then the
9988 pipeline recycles, thereby causing significant performance decline.
9989 This function locates such situations and exchanges the two
9990 operands of the compare. The function return true whenever it
9991 added an insn. */
9992 static bool
9993 s390_z10_optimize_cmp (rtx insn)
9994 {
9995 rtx prev_insn, next_insn;
9996 bool insn_added_p = false;
9997 rtx cond, *op0, *op1;
9998
9999 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10000 {
10001 /* Handle compare and branch and branch on count
10002 instructions. */
10003 rtx pattern = single_set (insn);
10004
10005 if (!pattern
10006 || SET_DEST (pattern) != pc_rtx
10007 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10008 return false;
10009
10010 cond = XEXP (SET_SRC (pattern), 0);
10011 op0 = &XEXP (cond, 0);
10012 op1 = &XEXP (cond, 1);
10013 }
10014 else if (GET_CODE (PATTERN (insn)) == SET)
10015 {
10016 rtx src, dest;
10017
10018 /* Handle normal compare instructions. */
10019 src = SET_SRC (PATTERN (insn));
10020 dest = SET_DEST (PATTERN (insn));
10021
10022 if (!REG_P (dest)
10023 || !CC_REGNO_P (REGNO (dest))
10024 || GET_CODE (src) != COMPARE)
10025 return false;
10026
10027 /* s390_swap_cmp will try to find the conditional
10028 jump when passing NULL_RTX as condition. */
10029 cond = NULL_RTX;
10030 op0 = &XEXP (src, 0);
10031 op1 = &XEXP (src, 1);
10032 }
10033 else
10034 return false;
10035
10036 if (!REG_P (*op0) || !REG_P (*op1))
10037 return false;
10038
10039 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10040 return false;
10041
10042 /* Swap the COMPARE arguments and its mask if there is a
10043 conflicting access in the previous insn. */
10044 prev_insn = prev_active_insn (insn);
10045 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10046 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10047 s390_swap_cmp (cond, op0, op1, insn);
10048
10049 /* Check if there is a conflict with the next insn. If there
10050 was no conflict with the previous insn, then swap the
10051 COMPARE arguments and its mask. If we already swapped
10052 the operands, or if swapping them would cause a conflict
10053 with the previous insn, issue a NOP after the COMPARE in
10054 order to separate the two instuctions. */
10055 next_insn = next_active_insn (insn);
10056 if (next_insn != NULL_RTX && INSN_P (next_insn)
10057 && s390_non_addr_reg_read_p (*op1, next_insn))
10058 {
10059 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10060 && s390_non_addr_reg_read_p (*op0, prev_insn))
10061 {
10062 if (REGNO (*op1) == 0)
10063 emit_insn_after (gen_nop1 (), insn);
10064 else
10065 emit_insn_after (gen_nop (), insn);
10066 insn_added_p = true;
10067 }
10068 else
10069 s390_swap_cmp (cond, op0, op1, insn);
10070 }
10071 return insn_added_p;
10072 }
10073
10074 /* Perform machine-dependent processing. */
10075
10076 static void
10077 s390_reorg (void)
10078 {
10079 bool pool_overflow = false;
10080
10081 /* Make sure all splits have been performed; splits after
10082 machine_dependent_reorg might confuse insn length counts. */
10083 split_all_insns_noflow ();
10084
10085 /* Install the main literal pool and the associated base
10086 register load insns.
10087
10088 In addition, there are two problematic situations we need
10089 to correct:
10090
10091 - the literal pool might be > 4096 bytes in size, so that
10092 some of its elements cannot be directly accessed
10093
10094 - a branch target might be > 64K away from the branch, so that
10095 it is not possible to use a PC-relative instruction.
10096
10097 To fix those, we split the single literal pool into multiple
10098 pool chunks, reloading the pool base register at various
10099 points throughout the function to ensure it always points to
10100 the pool chunk the following code expects, and / or replace
10101 PC-relative branches by absolute branches.
10102
10103 However, the two problems are interdependent: splitting the
10104 literal pool can move a branch further away from its target,
10105 causing the 64K limit to overflow, and on the other hand,
10106 replacing a PC-relative branch by an absolute branch means
10107 we need to put the branch target address into the literal
10108 pool, possibly causing it to overflow.
10109
10110 So, we loop trying to fix up both problems until we manage
10111 to satisfy both conditions at the same time. Note that the
10112 loop is guaranteed to terminate as every pass of the loop
10113 strictly decreases the total number of PC-relative branches
10114 in the function. (This is not completely true as there
10115 might be branch-over-pool insns introduced by chunkify_start.
10116 Those never need to be split however.) */
10117
10118 for (;;)
10119 {
10120 struct constant_pool *pool = NULL;
10121
10122 /* Collect the literal pool. */
10123 if (!pool_overflow)
10124 {
10125 pool = s390_mainpool_start ();
10126 if (!pool)
10127 pool_overflow = true;
10128 }
10129
10130 /* If literal pool overflowed, start to chunkify it. */
10131 if (pool_overflow)
10132 pool = s390_chunkify_start ();
10133
10134 /* Split out-of-range branches. If this has created new
10135 literal pool entries, cancel current chunk list and
10136 recompute it. zSeries machines have large branch
10137 instructions, so we never need to split a branch. */
10138 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10139 {
10140 if (pool_overflow)
10141 s390_chunkify_cancel (pool);
10142 else
10143 s390_mainpool_cancel (pool);
10144
10145 continue;
10146 }
10147
10148 /* If we made it up to here, both conditions are satisfied.
10149 Finish up literal pool related changes. */
10150 if (pool_overflow)
10151 s390_chunkify_finish (pool);
10152 else
10153 s390_mainpool_finish (pool);
10154
10155 /* We're done splitting branches. */
10156 cfun->machine->split_branches_pending_p = false;
10157 break;
10158 }
10159
10160 /* Generate out-of-pool execute target insns. */
10161 if (TARGET_CPU_ZARCH)
10162 {
10163 rtx insn, label, target;
10164
10165 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10166 {
10167 label = s390_execute_label (insn);
10168 if (!label)
10169 continue;
10170
10171 gcc_assert (label != const0_rtx);
10172
10173 target = emit_label (XEXP (label, 0));
10174 INSN_ADDRESSES_NEW (target, -1);
10175
10176 target = emit_insn (s390_execute_target (insn));
10177 INSN_ADDRESSES_NEW (target, -1);
10178 }
10179 }
10180
10181 /* Try to optimize prologue and epilogue further. */
10182 s390_optimize_prologue ();
10183
10184 /* Walk over the insns and do some z10 specific changes. */
10185 if (s390_tune == PROCESSOR_2097_Z10)
10186 {
10187 rtx insn;
10188 bool insn_added_p = false;
10189
10190 /* The insn lengths and addresses have to be up to date for the
10191 following manipulations. */
10192 shorten_branches (get_insns ());
10193
10194 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10195 {
10196 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10197 continue;
10198
10199 if (JUMP_P (insn))
10200 insn_added_p |= s390_z10_fix_long_loop_prediction (insn);
10201
10202 if (GET_CODE (PATTERN (insn)) == PARALLEL
10203 || GET_CODE (PATTERN (insn)) == SET)
10204 insn_added_p |= s390_z10_optimize_cmp (insn);
10205 }
10206
10207 /* Adjust branches if we added new instructions. */
10208 if (insn_added_p)
10209 shorten_branches (get_insns ());
10210 }
10211 }
10212
10213 /* Return true if INSN is a fp load insn writing register REGNO. */
10214 static inline bool
10215 s390_fpload_toreg (rtx insn, unsigned int regno)
10216 {
10217 rtx set;
10218 enum attr_type flag = s390_safe_attr_type (insn);
10219
10220 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10221 return false;
10222
10223 set = single_set (insn);
10224
10225 if (set == NULL_RTX)
10226 return false;
10227
10228 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10229 return false;
10230
10231 if (REGNO (SET_DEST (set)) != regno)
10232 return false;
10233
10234 return true;
10235 }
10236
10237 /* This value describes the distance to be avoided between an
10238 aritmetic fp instruction and an fp load writing the same register.
10239 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10240 fine but the exact value has to be avoided. Otherwise the FP
10241 pipeline will throw an exception causing a major penalty. */
10242 #define Z10_EARLYLOAD_DISTANCE 7
10243
10244 /* Rearrange the ready list in order to avoid the situation described
10245 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10246 moved to the very end of the ready list. */
10247 static void
10248 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10249 {
10250 unsigned int regno;
10251 int nready = *nready_p;
10252 rtx tmp;
10253 int i;
10254 rtx insn;
10255 rtx set;
10256 enum attr_type flag;
10257 int distance;
10258
10259 /* Skip DISTANCE - 1 active insns. */
10260 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10261 distance > 0 && insn != NULL_RTX;
10262 distance--, insn = prev_active_insn (insn))
10263 if (CALL_P (insn) || JUMP_P (insn))
10264 return;
10265
10266 if (insn == NULL_RTX)
10267 return;
10268
10269 set = single_set (insn);
10270
10271 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10272 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10273 return;
10274
10275 flag = s390_safe_attr_type (insn);
10276
10277 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10278 return;
10279
10280 regno = REGNO (SET_DEST (set));
10281 i = nready - 1;
10282
10283 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10284 i--;
10285
10286 if (!i)
10287 return;
10288
10289 tmp = ready[i];
10290 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10291 ready[0] = tmp;
10292 }
10293
10294 /* This function is called via hook TARGET_SCHED_REORDER before
10295 issueing one insn from list READY which contains *NREADYP entries.
10296 For target z10 it reorders load instructions to avoid early load
10297 conflicts in the floating point pipeline */
10298 static int
10299 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10300 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10301 {
10302 if (s390_tune == PROCESSOR_2097_Z10)
10303 if (reload_completed && *nreadyp > 1)
10304 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10305
10306 return s390_issue_rate ();
10307 }
10308
10309 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10310 the scheduler has issued INSN. It stores the last issued insn into
10311 last_scheduled_insn in order to make it available for
10312 s390_sched_reorder. */
10313 static int
10314 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10315 int verbose ATTRIBUTE_UNUSED,
10316 rtx insn, int more)
10317 {
10318 last_scheduled_insn = insn;
10319
10320 if (GET_CODE (PATTERN (insn)) != USE
10321 && GET_CODE (PATTERN (insn)) != CLOBBER)
10322 return more - 1;
10323 else
10324 return more;
10325 }
10326
10327 static void
10328 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10329 int verbose ATTRIBUTE_UNUSED,
10330 int max_ready ATTRIBUTE_UNUSED)
10331 {
10332 last_scheduled_insn = NULL_RTX;
10333 }
10334
10335 /* This function checks the whole of insn X for memory references. The
10336 function always returns zero because the framework it is called
10337 from would stop recursively analyzing the insn upon a return value
10338 other than zero. The real result of this function is updating
10339 counter variable MEM_COUNT. */
10340 static int
10341 check_dpu (rtx *x, unsigned *mem_count)
10342 {
10343 if (*x != NULL_RTX && MEM_P (*x))
10344 (*mem_count)++;
10345 return 0;
10346 }
10347
10348 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10349 a new number struct loop *loop should be unrolled if tuned for the z10
10350 cpu. The loop is analyzed for memory accesses by calling check_dpu for
10351 each rtx of the loop. Depending on the loop_depth and the amount of
10352 memory accesses a new number <=nunroll is returned to improve the
10353 behaviour of the hardware prefetch unit. */
10354 static unsigned
10355 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10356 {
10357 basic_block *bbs;
10358 rtx insn;
10359 unsigned i;
10360 unsigned mem_count = 0;
10361
10362 /* Only z10 needs special handling. */
10363 if (s390_tune != PROCESSOR_2097_Z10)
10364 return nunroll;
10365
10366 /* Count the number of memory references within the loop body. */
10367 bbs = get_loop_body (loop);
10368 for (i = 0; i < loop->num_nodes; i++)
10369 {
10370 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10371 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10372 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10373 }
10374 free (bbs);
10375
10376 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10377 if (mem_count == 0)
10378 return nunroll;
10379
10380 switch (loop_depth(loop))
10381 {
10382 case 1:
10383 return MIN (nunroll, 28 / mem_count);
10384 case 2:
10385 return MIN (nunroll, 22 / mem_count);
10386 default:
10387 return MIN (nunroll, 16 / mem_count);
10388 }
10389 }
10390
10391 /* Initialize GCC target structure. */
10392
10393 #undef TARGET_ASM_ALIGNED_HI_OP
10394 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10395 #undef TARGET_ASM_ALIGNED_DI_OP
10396 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10397 #undef TARGET_ASM_INTEGER
10398 #define TARGET_ASM_INTEGER s390_assemble_integer
10399
10400 #undef TARGET_ASM_OPEN_PAREN
10401 #define TARGET_ASM_OPEN_PAREN ""
10402
10403 #undef TARGET_ASM_CLOSE_PAREN
10404 #define TARGET_ASM_CLOSE_PAREN ""
10405
10406 #undef TARGET_DEFAULT_TARGET_FLAGS
10407 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10408
10409 #undef TARGET_HANDLE_OPTION
10410 #define TARGET_HANDLE_OPTION s390_handle_option
10411
10412 #undef TARGET_ENCODE_SECTION_INFO
10413 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10414
10415 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10416 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10417
10418 #ifdef HAVE_AS_TLS
10419 #undef TARGET_HAVE_TLS
10420 #define TARGET_HAVE_TLS true
10421 #endif
10422 #undef TARGET_CANNOT_FORCE_CONST_MEM
10423 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10424
10425 #undef TARGET_DELEGITIMIZE_ADDRESS
10426 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10427
10428 #undef TARGET_LEGITIMIZE_ADDRESS
10429 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10430
10431 #undef TARGET_RETURN_IN_MEMORY
10432 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10433
10434 #undef TARGET_INIT_BUILTINS
10435 #define TARGET_INIT_BUILTINS s390_init_builtins
10436 #undef TARGET_EXPAND_BUILTIN
10437 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10438
10439 #undef TARGET_ASM_OUTPUT_MI_THUNK
10440 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10441 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10442 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10443
10444 #undef TARGET_SCHED_ADJUST_PRIORITY
10445 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10446 #undef TARGET_SCHED_ISSUE_RATE
10447 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10448 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10449 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10450
10451 #undef TARGET_SCHED_VARIABLE_ISSUE
10452 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10453 #undef TARGET_SCHED_REORDER
10454 #define TARGET_SCHED_REORDER s390_sched_reorder
10455 #undef TARGET_SCHED_INIT
10456 #define TARGET_SCHED_INIT s390_sched_init
10457
10458 #undef TARGET_CANNOT_COPY_INSN_P
10459 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10460 #undef TARGET_RTX_COSTS
10461 #define TARGET_RTX_COSTS s390_rtx_costs
10462 #undef TARGET_ADDRESS_COST
10463 #define TARGET_ADDRESS_COST s390_address_cost
10464
10465 #undef TARGET_MACHINE_DEPENDENT_REORG
10466 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10467
10468 #undef TARGET_VALID_POINTER_MODE
10469 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10470
10471 #undef TARGET_BUILD_BUILTIN_VA_LIST
10472 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10473 #undef TARGET_EXPAND_BUILTIN_VA_START
10474 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10475 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10476 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10477
10478 #undef TARGET_PROMOTE_FUNCTION_MODE
10479 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10480 #undef TARGET_PASS_BY_REFERENCE
10481 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10482
10483 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10484 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10485
10486 #undef TARGET_FIXED_CONDITION_CODE_REGS
10487 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10488
10489 #undef TARGET_CC_MODES_COMPATIBLE
10490 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10491
10492 #undef TARGET_INVALID_WITHIN_DOLOOP
10493 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10494
10495 #ifdef HAVE_AS_TLS
10496 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10497 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10498 #endif
10499
10500 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10501 #undef TARGET_MANGLE_TYPE
10502 #define TARGET_MANGLE_TYPE s390_mangle_type
10503 #endif
10504
10505 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10506 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10507
10508 #undef TARGET_SECONDARY_RELOAD
10509 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10510
10511 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10512 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10513
10514 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10515 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10516
10517 #undef TARGET_LEGITIMATE_ADDRESS_P
10518 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10519
10520 #undef TARGET_CAN_ELIMINATE
10521 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10522
10523 #undef TARGET_LOOP_UNROLL_ADJUST
10524 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10525
10526 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10527 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10528 #undef TARGET_TRAMPOLINE_INIT
10529 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10530
10531 #undef TARGET_UNWIND_WORD_MODE
10532 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10533
10534 struct gcc_target targetm = TARGET_INITIALIZER;
10535
10536 #include "gt-s390.h"