1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
59 /* Define the specific costs for a given cpu. */
61 struct processor_costs
64 const int m
; /* cost of an M instruction. */
65 const int mghi
; /* cost of an MGHI instruction. */
66 const int mh
; /* cost of an MH instruction. */
67 const int mhi
; /* cost of an MHI instruction. */
68 const int ml
; /* cost of an ML instruction. */
69 const int mr
; /* cost of an MR instruction. */
70 const int ms
; /* cost of an MS instruction. */
71 const int msg
; /* cost of an MSG instruction. */
72 const int msgf
; /* cost of an MSGF instruction. */
73 const int msgfr
; /* cost of an MSGFR instruction. */
74 const int msgr
; /* cost of an MSGR instruction. */
75 const int msr
; /* cost of an MSR instruction. */
76 const int mult_df
; /* cost of multiplication in DFmode. */
79 const int sqxbr
; /* cost of square root in TFmode. */
80 const int sqdbr
; /* cost of square root in DFmode. */
81 const int sqebr
; /* cost of square root in SFmode. */
82 /* multiply and add */
83 const int madbr
; /* cost of multiply and add in DFmode. */
84 const int maebr
; /* cost of multiply and add in SFmode. */
96 const struct processor_costs
*s390_cost
;
99 struct processor_costs z900_cost
=
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (30), /* DDBR */
122 COSTS_N_INSNS (27), /* DEBR */
123 COSTS_N_INSNS (220), /* DLGR */
124 COSTS_N_INSNS (34), /* DLR */
125 COSTS_N_INSNS (34), /* DR */
126 COSTS_N_INSNS (32), /* DSGFR */
127 COSTS_N_INSNS (32), /* DSGR */
131 struct processor_costs z990_cost
=
133 COSTS_N_INSNS (4), /* M */
134 COSTS_N_INSNS (2), /* MGHI */
135 COSTS_N_INSNS (2), /* MH */
136 COSTS_N_INSNS (2), /* MHI */
137 COSTS_N_INSNS (4), /* ML */
138 COSTS_N_INSNS (4), /* MR */
139 COSTS_N_INSNS (5), /* MS */
140 COSTS_N_INSNS (6), /* MSG */
141 COSTS_N_INSNS (4), /* MSGF */
142 COSTS_N_INSNS (4), /* MSGFR */
143 COSTS_N_INSNS (4), /* MSGR */
144 COSTS_N_INSNS (4), /* MSR */
145 COSTS_N_INSNS (1), /* multiplication in DFmode */
146 COSTS_N_INSNS (28), /* MXBR */
147 COSTS_N_INSNS (130), /* SQXBR */
148 COSTS_N_INSNS (66), /* SQDBR */
149 COSTS_N_INSNS (38), /* SQEBR */
150 COSTS_N_INSNS (1), /* MADBR */
151 COSTS_N_INSNS (1), /* MAEBR */
152 COSTS_N_INSNS (60), /* DXBR */
153 COSTS_N_INSNS (40), /* DDBR */
154 COSTS_N_INSNS (26), /* DEBR */
155 COSTS_N_INSNS (176), /* DLGR */
156 COSTS_N_INSNS (31), /* DLR */
157 COSTS_N_INSNS (31), /* DR */
158 COSTS_N_INSNS (31), /* DSGFR */
159 COSTS_N_INSNS (31), /* DSGR */
163 struct processor_costs z9_109_cost
=
165 COSTS_N_INSNS (4), /* M */
166 COSTS_N_INSNS (2), /* MGHI */
167 COSTS_N_INSNS (2), /* MH */
168 COSTS_N_INSNS (2), /* MHI */
169 COSTS_N_INSNS (4), /* ML */
170 COSTS_N_INSNS (4), /* MR */
171 COSTS_N_INSNS (5), /* MS */
172 COSTS_N_INSNS (6), /* MSG */
173 COSTS_N_INSNS (4), /* MSGF */
174 COSTS_N_INSNS (4), /* MSGFR */
175 COSTS_N_INSNS (4), /* MSGR */
176 COSTS_N_INSNS (4), /* MSR */
177 COSTS_N_INSNS (1), /* multiplication in DFmode */
178 COSTS_N_INSNS (28), /* MXBR */
179 COSTS_N_INSNS (130), /* SQXBR */
180 COSTS_N_INSNS (66), /* SQDBR */
181 COSTS_N_INSNS (38), /* SQEBR */
182 COSTS_N_INSNS (1), /* MADBR */
183 COSTS_N_INSNS (1), /* MAEBR */
184 COSTS_N_INSNS (60), /* DXBR */
185 COSTS_N_INSNS (40), /* DDBR */
186 COSTS_N_INSNS (26), /* DEBR */
187 COSTS_N_INSNS (30), /* DLGR */
188 COSTS_N_INSNS (23), /* DLR */
189 COSTS_N_INSNS (23), /* DR */
190 COSTS_N_INSNS (24), /* DSGFR */
191 COSTS_N_INSNS (24), /* DSGR */
195 struct processor_costs z10_cost
=
197 COSTS_N_INSNS (10), /* M */
198 COSTS_N_INSNS (10), /* MGHI */
199 COSTS_N_INSNS (10), /* MH */
200 COSTS_N_INSNS (10), /* MHI */
201 COSTS_N_INSNS (10), /* ML */
202 COSTS_N_INSNS (10), /* MR */
203 COSTS_N_INSNS (10), /* MS */
204 COSTS_N_INSNS (10), /* MSG */
205 COSTS_N_INSNS (10), /* MSGF */
206 COSTS_N_INSNS (10), /* MSGFR */
207 COSTS_N_INSNS (10), /* MSGR */
208 COSTS_N_INSNS (10), /* MSR */
209 COSTS_N_INSNS (1) , /* multiplication in DFmode */
210 COSTS_N_INSNS (50), /* MXBR */
211 COSTS_N_INSNS (120), /* SQXBR */
212 COSTS_N_INSNS (52), /* SQDBR */
213 COSTS_N_INSNS (38), /* SQEBR */
214 COSTS_N_INSNS (1), /* MADBR */
215 COSTS_N_INSNS (1), /* MAEBR */
216 COSTS_N_INSNS (111), /* DXBR */
217 COSTS_N_INSNS (39), /* DDBR */
218 COSTS_N_INSNS (32), /* DEBR */
219 COSTS_N_INSNS (160), /* DLGR */
220 COSTS_N_INSNS (71), /* DLR */
221 COSTS_N_INSNS (71), /* DR */
222 COSTS_N_INSNS (71), /* DSGFR */
223 COSTS_N_INSNS (71), /* DSGR */
226 extern int reload_completed
;
228 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
229 static rtx last_scheduled_insn
;
231 /* Structure used to hold the components of a S/390 memory
232 address. A legitimate address on S/390 is of the general
234 base + index + displacement
235 where any of the components is optional.
237 base and index are registers of the class ADDR_REGS,
238 displacement is an unsigned 12-bit immediate constant. */
249 /* Which cpu are we tuning for. */
250 enum processor_type s390_tune
= PROCESSOR_max
;
252 /* Which instruction set architecture to use. */
253 enum processor_type s390_arch
;
256 HOST_WIDE_INT s390_warn_framesize
= 0;
257 HOST_WIDE_INT s390_stack_size
= 0;
258 HOST_WIDE_INT s390_stack_guard
= 0;
260 /* The following structure is embedded in the machine
261 specific part of struct function. */
263 struct GTY (()) s390_frame_layout
265 /* Offset within stack frame. */
266 HOST_WIDE_INT gprs_offset
;
267 HOST_WIDE_INT f0_offset
;
268 HOST_WIDE_INT f4_offset
;
269 HOST_WIDE_INT f8_offset
;
270 HOST_WIDE_INT backchain_offset
;
272 /* Number of first and last gpr where slots in the register
273 save area are reserved for. */
274 int first_save_gpr_slot
;
275 int last_save_gpr_slot
;
277 /* Number of first and last gpr to be saved, restored. */
279 int first_restore_gpr
;
281 int last_restore_gpr
;
283 /* Bits standing for floating point registers. Set, if the
284 respective register has to be saved. Starting with reg 16 (f0)
285 at the rightmost bit.
286 Bit 15 - 8 7 6 5 4 3 2 1 0
287 fpr 15 - 8 7 5 3 1 6 4 2 0
288 reg 31 - 24 23 22 21 20 19 18 17 16 */
289 unsigned int fpr_bitmap
;
291 /* Number of floating point registers f8-f15 which must be saved. */
294 /* Set if return address needs to be saved.
295 This flag is set by s390_return_addr_rtx if it could not use
296 the initial value of r14 and therefore depends on r14 saved
298 bool save_return_addr_p
;
300 /* Size of stack frame. */
301 HOST_WIDE_INT frame_size
;
304 /* Define the structure for the machine field in struct function. */
306 struct GTY(()) machine_function
308 struct s390_frame_layout frame_layout
;
310 /* Literal pool base register. */
313 /* True if we may need to perform branch splitting. */
314 bool split_branches_pending_p
;
316 /* Some local-dynamic TLS symbol name. */
317 const char *some_ld_name
;
319 bool has_landing_pad_p
;
322 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
324 #define cfun_frame_layout (cfun->machine->frame_layout)
325 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
326 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
327 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
328 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
330 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
333 /* Number of GPRs and FPRs used for argument passing. */
334 #define GP_ARG_NUM_REG 5
335 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
337 /* A couple of shortcuts. */
338 #define CONST_OK_FOR_J(x) \
339 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
340 #define CONST_OK_FOR_K(x) \
341 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
342 #define CONST_OK_FOR_Os(x) \
343 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
344 #define CONST_OK_FOR_Op(x) \
345 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
346 #define CONST_OK_FOR_On(x) \
347 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
349 #define REGNO_PAIR_OK(REGNO, MODE) \
350 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
352 /* That's the read ahead of the dynamic branch prediction unit in
353 bytes on a z10 CPU. */
354 #define Z10_PREDICT_DISTANCE 384
356 static enum machine_mode
357 s390_libgcc_cmp_return_mode (void)
359 return TARGET_64BIT
? DImode
: SImode
;
362 static enum machine_mode
363 s390_libgcc_shift_count_mode (void)
365 return TARGET_64BIT
? DImode
: SImode
;
368 static enum machine_mode
369 s390_unwind_word_mode (void)
371 return TARGET_64BIT
? DImode
: SImode
;
374 /* Return true if the back end supports mode MODE. */
376 s390_scalar_mode_supported_p (enum machine_mode mode
)
378 /* In contrast to the default implementation reject TImode constants on 31bit
379 TARGET_ZARCH for ABI compliance. */
380 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
383 if (DECIMAL_FLOAT_MODE_P (mode
))
384 return default_decimal_float_supported_p ();
386 return default_scalar_mode_supported_p (mode
);
389 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
392 s390_set_has_landing_pad_p (bool value
)
394 cfun
->machine
->has_landing_pad_p
= value
;
397 /* If two condition code modes are compatible, return a condition code
398 mode which is compatible with both. Otherwise, return
401 static enum machine_mode
402 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
410 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
411 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
432 /* Return true if SET either doesn't set the CC register, or else
433 the source and destination have matching CC modes and that
434 CC mode is at least as constrained as REQ_MODE. */
437 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
439 enum machine_mode set_mode
;
441 gcc_assert (GET_CODE (set
) == SET
);
443 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
446 set_mode
= GET_MODE (SET_DEST (set
));
460 if (req_mode
!= set_mode
)
465 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
466 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
472 if (req_mode
!= CCAmode
)
480 return (GET_MODE (SET_SRC (set
)) == set_mode
);
483 /* Return true if every SET in INSN that sets the CC register
484 has source and destination with matching CC modes and that
485 CC mode is at least as constrained as REQ_MODE.
486 If REQ_MODE is VOIDmode, always return false. */
489 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
493 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
494 if (req_mode
== VOIDmode
)
497 if (GET_CODE (PATTERN (insn
)) == SET
)
498 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
500 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
501 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
503 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
504 if (GET_CODE (set
) == SET
)
505 if (!s390_match_ccmode_set (set
, req_mode
))
512 /* If a test-under-mask instruction can be used to implement
513 (compare (and ... OP1) OP2), return the CC mode required
514 to do that. Otherwise, return VOIDmode.
515 MIXED is true if the instruction can distinguish between
516 CC1 and CC2 for mixed selected bits (TMxx), it is false
517 if the instruction cannot (TM). */
520 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
524 /* ??? Fixme: should work on CONST_DOUBLE as well. */
525 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
528 /* Selected bits all zero: CC0.
529 e.g.: int a; if ((a & (16 + 128)) == 0) */
530 if (INTVAL (op2
) == 0)
533 /* Selected bits all one: CC3.
534 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
535 if (INTVAL (op2
) == INTVAL (op1
))
538 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
540 if ((a & (16 + 128)) == 16) -> CCT1
541 if ((a & (16 + 128)) == 128) -> CCT2 */
544 bit1
= exact_log2 (INTVAL (op2
));
545 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
546 if (bit0
!= -1 && bit1
!= -1)
547 return bit0
> bit1
? CCT1mode
: CCT2mode
;
553 /* Given a comparison code OP (EQ, NE, etc.) and the operands
554 OP0 and OP1 of a COMPARE, return the mode to be used for the
558 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
564 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
565 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
567 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
568 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
570 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
571 || GET_CODE (op1
) == NEG
)
572 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
575 if (GET_CODE (op0
) == AND
)
577 /* Check whether we can potentially do it via TM. */
578 enum machine_mode ccmode
;
579 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
580 if (ccmode
!= VOIDmode
)
582 /* Relax CCTmode to CCZmode to allow fall-back to AND
583 if that turns out to be beneficial. */
584 return ccmode
== CCTmode
? CCZmode
: ccmode
;
588 if (register_operand (op0
, HImode
)
589 && GET_CODE (op1
) == CONST_INT
590 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
592 if (register_operand (op0
, QImode
)
593 && GET_CODE (op1
) == CONST_INT
594 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
603 /* The only overflow condition of NEG and ABS happens when
604 -INT_MAX is used as parameter, which stays negative. So
605 we have an overflow from a positive value to a negative.
606 Using CCAP mode the resulting cc can be used for comparisons. */
607 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
608 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
611 /* If constants are involved in an add instruction it is possible to use
612 the resulting cc for comparisons with zero. Knowing the sign of the
613 constant the overflow behavior gets predictable. e.g.:
614 int a, b; if ((b = a + c) > 0)
615 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
616 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
617 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
619 if (INTVAL (XEXP((op0
), 1)) < 0)
633 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
634 && GET_CODE (op1
) != CONST_INT
)
640 if (GET_CODE (op0
) == PLUS
641 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
644 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
645 && GET_CODE (op1
) != CONST_INT
)
651 if (GET_CODE (op0
) == MINUS
652 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
655 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
656 && GET_CODE (op1
) != CONST_INT
)
665 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
666 that we can implement more efficiently. */
669 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
671 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
672 if ((*code
== EQ
|| *code
== NE
)
673 && *op1
== const0_rtx
674 && GET_CODE (*op0
) == ZERO_EXTRACT
675 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
676 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
677 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
679 rtx inner
= XEXP (*op0
, 0);
680 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
681 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
682 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
684 if (len
> 0 && len
< modesize
685 && pos
>= 0 && pos
+ len
<= modesize
686 && modesize
<= HOST_BITS_PER_WIDE_INT
)
688 unsigned HOST_WIDE_INT block
;
689 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
690 block
<<= modesize
- pos
- len
;
692 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
693 gen_int_mode (block
, GET_MODE (inner
)));
697 /* Narrow AND of memory against immediate to enable TM. */
698 if ((*code
== EQ
|| *code
== NE
)
699 && *op1
== const0_rtx
700 && GET_CODE (*op0
) == AND
701 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
702 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
704 rtx inner
= XEXP (*op0
, 0);
705 rtx mask
= XEXP (*op0
, 1);
707 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
708 if (GET_CODE (inner
) == SUBREG
709 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
710 && (GET_MODE_SIZE (GET_MODE (inner
))
711 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
713 & GET_MODE_MASK (GET_MODE (inner
))
714 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
716 inner
= SUBREG_REG (inner
);
718 /* Do not change volatile MEMs. */
719 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
721 int part
= s390_single_part (XEXP (*op0
, 1),
722 GET_MODE (inner
), QImode
, 0);
725 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
726 inner
= adjust_address_nv (inner
, QImode
, part
);
727 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
732 /* Narrow comparisons against 0xffff to HImode if possible. */
733 if ((*code
== EQ
|| *code
== NE
)
734 && GET_CODE (*op1
) == CONST_INT
735 && INTVAL (*op1
) == 0xffff
736 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
737 && (nonzero_bits (*op0
, GET_MODE (*op0
))
738 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
740 *op0
= gen_lowpart (HImode
, *op0
);
744 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
745 if (GET_CODE (*op0
) == UNSPEC
746 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
747 && XVECLEN (*op0
, 0) == 1
748 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
749 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
750 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
751 && *op1
== const0_rtx
)
753 enum rtx_code new_code
= UNKNOWN
;
756 case EQ
: new_code
= EQ
; break;
757 case NE
: new_code
= NE
; break;
758 case LT
: new_code
= GTU
; break;
759 case GT
: new_code
= LTU
; break;
760 case LE
: new_code
= GEU
; break;
761 case GE
: new_code
= LEU
; break;
765 if (new_code
!= UNKNOWN
)
767 *op0
= XVECEXP (*op0
, 0, 0);
772 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
773 if (GET_CODE (*op0
) == UNSPEC
774 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
775 && XVECLEN (*op0
, 0) == 1
776 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
777 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
778 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
779 && *op1
== const0_rtx
)
781 enum rtx_code new_code
= UNKNOWN
;
784 case EQ
: new_code
= EQ
; break;
785 case NE
: new_code
= NE
; break;
789 if (new_code
!= UNKNOWN
)
791 *op0
= XVECEXP (*op0
, 0, 0);
796 /* Simplify cascaded EQ, NE with const0_rtx. */
797 if ((*code
== NE
|| *code
== EQ
)
798 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
799 && GET_MODE (*op0
) == SImode
800 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
801 && REG_P (XEXP (*op0
, 0))
802 && XEXP (*op0
, 1) == const0_rtx
803 && *op1
== const0_rtx
)
805 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
806 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
810 *op0
= XEXP (*op0
, 0);
813 /* Prefer register over memory as first operand. */
814 if (MEM_P (*op0
) && REG_P (*op1
))
816 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
817 *code
= swap_condition (*code
);
821 /* Emit a compare instruction suitable to implement the comparison
822 OP0 CODE OP1. Return the correct condition RTL to be placed in
823 the IF_THEN_ELSE of the conditional branch testing the result. */
826 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
828 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
831 /* Do not output a redundant compare instruction if a compare_and_swap
832 pattern already computed the result and the machine modes are compatible. */
833 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
835 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
841 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
842 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
845 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
848 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
850 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
851 conditional branch testing the result. */
854 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
856 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
857 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
860 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
861 unconditional jump, else a conditional jump under condition COND. */
864 s390_emit_jump (rtx target
, rtx cond
)
868 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
870 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
872 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
873 emit_jump_insn (insn
);
876 /* Return branch condition mask to implement a branch
877 specified by CODE. Return -1 for invalid comparisons. */
880 s390_branch_condition_mask (rtx code
)
882 const int CC0
= 1 << 3;
883 const int CC1
= 1 << 2;
884 const int CC2
= 1 << 1;
885 const int CC3
= 1 << 0;
887 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
888 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
889 gcc_assert (XEXP (code
, 1) == const0_rtx
);
891 switch (GET_MODE (XEXP (code
, 0)))
895 switch (GET_CODE (code
))
898 case NE
: return CC1
| CC2
| CC3
;
904 switch (GET_CODE (code
))
907 case NE
: return CC0
| CC2
| CC3
;
913 switch (GET_CODE (code
))
916 case NE
: return CC0
| CC1
| CC3
;
922 switch (GET_CODE (code
))
925 case NE
: return CC0
| CC1
| CC2
;
931 switch (GET_CODE (code
))
933 case EQ
: return CC0
| CC2
;
934 case NE
: return CC1
| CC3
;
940 switch (GET_CODE (code
))
942 case LTU
: return CC2
| CC3
; /* carry */
943 case GEU
: return CC0
| CC1
; /* no carry */
949 switch (GET_CODE (code
))
951 case GTU
: return CC0
| CC1
; /* borrow */
952 case LEU
: return CC2
| CC3
; /* no borrow */
958 switch (GET_CODE (code
))
960 case EQ
: return CC0
| CC2
;
961 case NE
: return CC1
| CC3
;
962 case LTU
: return CC1
;
963 case GTU
: return CC3
;
964 case LEU
: return CC1
| CC2
;
965 case GEU
: return CC2
| CC3
;
970 switch (GET_CODE (code
))
973 case NE
: return CC1
| CC2
| CC3
;
974 case LTU
: return CC1
;
975 case GTU
: return CC2
;
976 case LEU
: return CC0
| CC1
;
977 case GEU
: return CC0
| CC2
;
983 switch (GET_CODE (code
))
986 case NE
: return CC2
| CC1
| CC3
;
987 case LTU
: return CC2
;
988 case GTU
: return CC1
;
989 case LEU
: return CC0
| CC2
;
990 case GEU
: return CC0
| CC1
;
996 switch (GET_CODE (code
))
999 case NE
: return CC1
| CC2
| CC3
;
1000 case LT
: return CC1
| CC3
;
1001 case GT
: return CC2
;
1002 case LE
: return CC0
| CC1
| CC3
;
1003 case GE
: return CC0
| CC2
;
1009 switch (GET_CODE (code
))
1011 case EQ
: return CC0
;
1012 case NE
: return CC1
| CC2
| CC3
;
1013 case LT
: return CC1
;
1014 case GT
: return CC2
| CC3
;
1015 case LE
: return CC0
| CC1
;
1016 case GE
: return CC0
| CC2
| CC3
;
1022 switch (GET_CODE (code
))
1024 case EQ
: return CC0
;
1025 case NE
: return CC1
| CC2
| CC3
;
1026 case LT
: return CC1
;
1027 case GT
: return CC2
;
1028 case LE
: return CC0
| CC1
;
1029 case GE
: return CC0
| CC2
;
1030 case UNORDERED
: return CC3
;
1031 case ORDERED
: return CC0
| CC1
| CC2
;
1032 case UNEQ
: return CC0
| CC3
;
1033 case UNLT
: return CC1
| CC3
;
1034 case UNGT
: return CC2
| CC3
;
1035 case UNLE
: return CC0
| CC1
| CC3
;
1036 case UNGE
: return CC0
| CC2
| CC3
;
1037 case LTGT
: return CC1
| CC2
;
1043 switch (GET_CODE (code
))
1045 case EQ
: return CC0
;
1046 case NE
: return CC2
| CC1
| CC3
;
1047 case LT
: return CC2
;
1048 case GT
: return CC1
;
1049 case LE
: return CC0
| CC2
;
1050 case GE
: return CC0
| CC1
;
1051 case UNORDERED
: return CC3
;
1052 case ORDERED
: return CC0
| CC2
| CC1
;
1053 case UNEQ
: return CC0
| CC3
;
1054 case UNLT
: return CC2
| CC3
;
1055 case UNGT
: return CC1
| CC3
;
1056 case UNLE
: return CC0
| CC2
| CC3
;
1057 case UNGE
: return CC0
| CC1
| CC3
;
1058 case LTGT
: return CC2
| CC1
;
1069 /* Return branch condition mask to implement a compare and branch
1070 specified by CODE. Return -1 for invalid comparisons. */
1073 s390_compare_and_branch_condition_mask (rtx code
)
1075 const int CC0
= 1 << 3;
1076 const int CC1
= 1 << 2;
1077 const int CC2
= 1 << 1;
1079 switch (GET_CODE (code
))
1103 /* If INV is false, return assembler mnemonic string to implement
1104 a branch specified by CODE. If INV is true, return mnemonic
1105 for the corresponding inverted branch. */
1108 s390_branch_condition_mnemonic (rtx code
, int inv
)
1112 static const char *const mnemonic
[16] =
1114 NULL
, "o", "h", "nle",
1115 "l", "nhe", "lh", "ne",
1116 "e", "nlh", "he", "nl",
1117 "le", "nh", "no", NULL
1120 if (GET_CODE (XEXP (code
, 0)) == REG
1121 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1122 && XEXP (code
, 1) == const0_rtx
)
1123 mask
= s390_branch_condition_mask (code
);
1125 mask
= s390_compare_and_branch_condition_mask (code
);
1127 gcc_assert (mask
>= 0);
1132 gcc_assert (mask
>= 1 && mask
<= 14);
1134 return mnemonic
[mask
];
1137 /* Return the part of op which has a value different from def.
1138 The size of the part is determined by mode.
1139 Use this function only if you already know that op really
1140 contains such a part. */
1142 unsigned HOST_WIDE_INT
1143 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1145 unsigned HOST_WIDE_INT value
= 0;
1146 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1147 int part_bits
= GET_MODE_BITSIZE (mode
);
1148 unsigned HOST_WIDE_INT part_mask
1149 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1152 for (i
= 0; i
< max_parts
; i
++)
1155 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1157 value
>>= part_bits
;
1159 if ((value
& part_mask
) != (def
& part_mask
))
1160 return value
& part_mask
;
1166 /* If OP is an integer constant of mode MODE with exactly one
1167 part of mode PART_MODE unequal to DEF, return the number of that
1168 part. Otherwise, return -1. */
1171 s390_single_part (rtx op
,
1172 enum machine_mode mode
,
1173 enum machine_mode part_mode
,
1176 unsigned HOST_WIDE_INT value
= 0;
1177 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1178 unsigned HOST_WIDE_INT part_mask
1179 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1182 if (GET_CODE (op
) != CONST_INT
)
1185 for (i
= 0; i
< n_parts
; i
++)
1188 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1190 value
>>= GET_MODE_BITSIZE (part_mode
);
1192 if ((value
& part_mask
) != (def
& part_mask
))
1200 return part
== -1 ? -1 : n_parts
- 1 - part
;
1203 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1204 bits and no other bits are set in IN. POS and LENGTH can be used
1205 to obtain the start position and the length of the bitfield.
1207 POS gives the position of the first bit of the bitfield counting
1208 from the lowest order bit starting with zero. In order to use this
1209 value for S/390 instructions this has to be converted to "bits big
1213 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1214 int *pos
, int *length
)
1219 unsigned HOST_WIDE_INT mask
= 1ULL;
1220 bool contiguous
= false;
1222 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1246 /* Calculate a mask for all bits beyond the contiguous bits. */
1247 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1252 if (tmp_length
+ tmp_pos
- 1 > size
)
1256 *length
= tmp_length
;
1264 /* Check whether we can (and want to) split a double-word
1265 move in mode MODE from SRC to DST into two single-word
1266 moves, moving the subword FIRST_SUBWORD first. */
1269 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1271 /* Floating point registers cannot be split. */
1272 if (FP_REG_P (src
) || FP_REG_P (dst
))
1275 /* We don't need to split if operands are directly accessible. */
1276 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1279 /* Non-offsettable memory references cannot be split. */
1280 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1281 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1284 /* Moving the first subword must not clobber a register
1285 needed to move the second subword. */
1286 if (register_operand (dst
, mode
))
1288 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1289 if (reg_overlap_mentioned_p (subreg
, src
))
1296 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1297 and [MEM2, MEM2 + SIZE] do overlap and false
1301 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1303 rtx addr1
, addr2
, addr_delta
;
1304 HOST_WIDE_INT delta
;
1306 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1312 addr1
= XEXP (mem1
, 0);
1313 addr2
= XEXP (mem2
, 0);
1315 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1317 /* This overlapping check is used by peepholes merging memory block operations.
1318 Overlapping operations would otherwise be recognized by the S/390 hardware
1319 and would fall back to a slower implementation. Allowing overlapping
1320 operations would lead to slow code but not to wrong code. Therefore we are
1321 somewhat optimistic if we cannot prove that the memory blocks are
1323 That's why we return false here although this may accept operations on
1324 overlapping memory areas. */
1325 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1328 delta
= INTVAL (addr_delta
);
1331 || (delta
> 0 && delta
< size
)
1332 || (delta
< 0 && -delta
< size
))
1338 /* Check whether the address of memory reference MEM2 equals exactly
1339 the address of memory reference MEM1 plus DELTA. Return true if
1340 we can prove this to be the case, false otherwise. */
1343 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1345 rtx addr1
, addr2
, addr_delta
;
1347 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1350 addr1
= XEXP (mem1
, 0);
1351 addr2
= XEXP (mem2
, 0);
1353 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1354 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1360 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1363 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1366 enum machine_mode wmode
= mode
;
1367 rtx dst
= operands
[0];
1368 rtx src1
= operands
[1];
1369 rtx src2
= operands
[2];
1372 /* If we cannot handle the operation directly, use a temp register. */
1373 if (!s390_logical_operator_ok_p (operands
))
1374 dst
= gen_reg_rtx (mode
);
1376 /* QImode and HImode patterns make sense only if we have a destination
1377 in memory. Otherwise perform the operation in SImode. */
1378 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1381 /* Widen operands if required. */
1384 if (GET_CODE (dst
) == SUBREG
1385 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1387 else if (REG_P (dst
))
1388 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1390 dst
= gen_reg_rtx (wmode
);
1392 if (GET_CODE (src1
) == SUBREG
1393 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1395 else if (GET_MODE (src1
) != VOIDmode
)
1396 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1398 if (GET_CODE (src2
) == SUBREG
1399 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1401 else if (GET_MODE (src2
) != VOIDmode
)
1402 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1405 /* Emit the instruction. */
1406 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1407 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1408 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1410 /* Fix up the destination if needed. */
1411 if (dst
!= operands
[0])
1412 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1415 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1418 s390_logical_operator_ok_p (rtx
*operands
)
1420 /* If the destination operand is in memory, it needs to coincide
1421 with one of the source operands. After reload, it has to be
1422 the first source operand. */
1423 if (GET_CODE (operands
[0]) == MEM
)
1424 return rtx_equal_p (operands
[0], operands
[1])
1425 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1430 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1431 operand IMMOP to switch from SS to SI type instructions. */
1434 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1436 int def
= code
== AND
? -1 : 0;
1440 gcc_assert (GET_CODE (*memop
) == MEM
);
1441 gcc_assert (!MEM_VOLATILE_P (*memop
));
1443 mask
= s390_extract_part (*immop
, QImode
, def
);
1444 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1445 gcc_assert (part
>= 0);
1447 *memop
= adjust_address (*memop
, QImode
, part
);
1448 *immop
= gen_int_mode (mask
, QImode
);
1452 /* How to allocate a 'struct machine_function'. */
1454 static struct machine_function
*
1455 s390_init_machine_status (void)
1457 return ggc_alloc_cleared_machine_function ();
1460 /* Change optimizations to be performed, depending on the
1463 LEVEL is the optimization level specified; 2 if `-O2' is
1464 specified, 1 if `-O' is specified, and 0 if neither is specified.
1466 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1469 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1471 /* ??? There are apparently still problems with -fcaller-saves. */
1472 flag_caller_saves
= 0;
1474 /* By default, always emit DWARF-2 unwind info. This allows debugging
1475 without maintaining a stack frame back-chain. */
1476 flag_asynchronous_unwind_tables
= 1;
1478 /* Use MVCLE instructions to decrease code size if requested. */
1480 target_flags
|= MASK_MVCLE
;
1483 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1484 to the associated processor_type and processor_flags if so. */
1487 s390_handle_arch_option (const char *arg
,
1488 enum processor_type
*type
,
1493 const char *const name
; /* processor name or nickname. */
1494 const enum processor_type processor
;
1495 const int flags
; /* From enum processor_flags. */
1497 const processor_alias_table
[] =
1499 {"g5", PROCESSOR_9672_G5
, PF_IEEE_FLOAT
},
1500 {"g6", PROCESSOR_9672_G6
, PF_IEEE_FLOAT
},
1501 {"z900", PROCESSOR_2064_Z900
, PF_IEEE_FLOAT
| PF_ZARCH
},
1502 {"z990", PROCESSOR_2084_Z990
, PF_IEEE_FLOAT
| PF_ZARCH
1503 | PF_LONG_DISPLACEMENT
},
1504 {"z9-109", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1505 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
},
1506 {"z9-ec", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1507 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
},
1508 {"z10", PROCESSOR_2097_Z10
, PF_IEEE_FLOAT
| PF_ZARCH
1509 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
},
1513 for (i
= 0; i
< ARRAY_SIZE (processor_alias_table
); i
++)
1514 if (strcmp (arg
, processor_alias_table
[i
].name
) == 0)
1516 *type
= processor_alias_table
[i
].processor
;
1517 *flags
= processor_alias_table
[i
].flags
;
1523 /* Implement TARGET_HANDLE_OPTION. */
1526 s390_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
1531 return s390_handle_arch_option (arg
, &s390_arch
, &s390_arch_flags
);
1533 case OPT_mstack_guard_
:
1534 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_guard
) != 1)
1536 if (exact_log2 (s390_stack_guard
) == -1)
1537 error ("stack guard value must be an exact power of 2");
1540 case OPT_mstack_size_
:
1541 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_size
) != 1)
1543 if (exact_log2 (s390_stack_size
) == -1)
1544 error ("stack size must be an exact power of 2");
1548 return s390_handle_arch_option (arg
, &s390_tune
, &s390_tune_flags
);
1550 case OPT_mwarn_framesize_
:
1551 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_warn_framesize
) == 1;
1559 s390_option_override (void)
1561 /* Set up function hooks. */
1562 init_machine_status
= s390_init_machine_status
;
1564 /* Architecture mode defaults according to ABI. */
1565 if (!(target_flags_explicit
& MASK_ZARCH
))
1568 target_flags
|= MASK_ZARCH
;
1570 target_flags
&= ~MASK_ZARCH
;
1573 /* Determine processor architectural level. */
1574 if (!s390_arch_string
)
1576 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1577 s390_handle_arch_option (s390_arch_string
, &s390_arch
, &s390_arch_flags
);
1580 /* Determine processor to tune for. */
1581 if (s390_tune
== PROCESSOR_max
)
1583 s390_tune
= s390_arch
;
1584 s390_tune_flags
= s390_arch_flags
;
1587 /* Sanity checks. */
1588 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1589 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1590 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1591 error ("64-bit ABI not supported in ESA/390 mode");
1593 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1595 if (target_flags_explicit
& MASK_HARD_DFP
)
1597 if (!TARGET_CPU_DFP
)
1598 error ("Hardware decimal floating point instructions"
1599 " not available on %s", s390_arch_string
);
1601 error ("Hardware decimal floating point instructions"
1602 " not available in ESA/390 mode");
1605 target_flags
&= ~MASK_HARD_DFP
;
1608 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1610 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1611 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1613 target_flags
&= ~MASK_HARD_DFP
;
1616 /* Set processor cost function. */
1619 case PROCESSOR_2084_Z990
:
1620 s390_cost
= &z990_cost
;
1622 case PROCESSOR_2094_Z9_109
:
1623 s390_cost
= &z9_109_cost
;
1625 case PROCESSOR_2097_Z10
:
1626 s390_cost
= &z10_cost
;
1629 s390_cost
= &z900_cost
;
1632 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1633 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1636 if (s390_stack_size
)
1638 if (s390_stack_guard
>= s390_stack_size
)
1639 error ("stack size must be greater than the stack guard value");
1640 else if (s390_stack_size
> 1 << 16)
1641 error ("stack size must not be greater than 64k");
1643 else if (s390_stack_guard
)
1644 error ("-mstack-guard implies use of -mstack-size");
1646 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1647 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1648 target_flags
|= MASK_LONG_DOUBLE_128
;
1651 if (s390_tune
== PROCESSOR_2097_Z10
)
1653 if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS
))
1654 set_param_value ("max-unrolled-insns", 100);
1655 if (!PARAM_SET_P (PARAM_MAX_UNROLL_TIMES
))
1656 set_param_value ("max-unroll-times", 32);
1657 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEELED_INSNS
))
1658 set_param_value ("max-completely-peeled-insns", 2000);
1659 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEEL_TIMES
))
1660 set_param_value ("max-completely-peel-times", 64);
1663 set_param_value ("max-pending-list-length", 256);
1664 /* values for loop prefetching */
1665 set_param_value ("l1-cache-line-size", 256);
1666 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE
))
1667 set_param_value ("l1-cache-size", 128);
1668 /* s390 has more than 2 levels and the size is much larger. Since
1669 we are always running virtualized assume that we only get a small
1670 part of the caches above l1. */
1671 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE
))
1672 set_param_value ("l2-cache-size", 1500);
1673 if (!PARAM_SET_P (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
))
1674 set_param_value ("prefetch-min-insn-to-mem-ratio", 2);
1675 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES
))
1676 set_param_value ("simultaneous-prefetches", 6);
1678 /* This cannot reside in optimization_options since HAVE_prefetch
1679 requires the arch flags to be evaluated already. Since prefetching
1680 is beneficial on s390, we enable it if available. */
1681 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1682 flag_prefetch_loop_arrays
= 1;
1685 /* Map for smallest class containing reg regno. */
1687 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1688 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1689 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1690 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1691 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1692 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1693 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1694 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1695 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1696 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1697 ACCESS_REGS
, ACCESS_REGS
1700 /* Return attribute type of insn. */
1702 static enum attr_type
1703 s390_safe_attr_type (rtx insn
)
1705 if (recog_memoized (insn
) >= 0)
1706 return get_attr_type (insn
);
1711 /* Return true if DISP is a valid short displacement. */
1714 s390_short_displacement (rtx disp
)
1716 /* No displacement is OK. */
1720 /* Without the long displacement facility we don't need to
1721 distingiush between long and short displacement. */
1722 if (!TARGET_LONG_DISPLACEMENT
)
1725 /* Integer displacement in range. */
1726 if (GET_CODE (disp
) == CONST_INT
)
1727 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1729 /* GOT offset is not OK, the GOT can be large. */
1730 if (GET_CODE (disp
) == CONST
1731 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1732 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1733 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1736 /* All other symbolic constants are literal pool references,
1737 which are OK as the literal pool must be small. */
1738 if (GET_CODE (disp
) == CONST
)
1744 /* Decompose a RTL expression ADDR for a memory address into
1745 its components, returned in OUT.
1747 Returns false if ADDR is not a valid memory address, true
1748 otherwise. If OUT is NULL, don't return the components,
1749 but check for validity only.
1751 Note: Only addresses in canonical form are recognized.
1752 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1753 canonical form so that they will be recognized. */
1756 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1758 HOST_WIDE_INT offset
= 0;
1759 rtx base
= NULL_RTX
;
1760 rtx indx
= NULL_RTX
;
1761 rtx disp
= NULL_RTX
;
1763 bool pointer
= false;
1764 bool base_ptr
= false;
1765 bool indx_ptr
= false;
1766 bool literal_pool
= false;
1768 /* We may need to substitute the literal pool base register into the address
1769 below. However, at this point we do not know which register is going to
1770 be used as base, so we substitute the arg pointer register. This is going
1771 to be treated as holding a pointer below -- it shouldn't be used for any
1773 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1775 /* Decompose address into base + index + displacement. */
1777 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1780 else if (GET_CODE (addr
) == PLUS
)
1782 rtx op0
= XEXP (addr
, 0);
1783 rtx op1
= XEXP (addr
, 1);
1784 enum rtx_code code0
= GET_CODE (op0
);
1785 enum rtx_code code1
= GET_CODE (op1
);
1787 if (code0
== REG
|| code0
== UNSPEC
)
1789 if (code1
== REG
|| code1
== UNSPEC
)
1791 indx
= op0
; /* index + base */
1797 base
= op0
; /* base + displacement */
1802 else if (code0
== PLUS
)
1804 indx
= XEXP (op0
, 0); /* index + base + disp */
1805 base
= XEXP (op0
, 1);
1816 disp
= addr
; /* displacement */
1818 /* Extract integer part of displacement. */
1822 if (GET_CODE (disp
) == CONST_INT
)
1824 offset
= INTVAL (disp
);
1827 else if (GET_CODE (disp
) == CONST
1828 && GET_CODE (XEXP (disp
, 0)) == PLUS
1829 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1831 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1832 disp
= XEXP (XEXP (disp
, 0), 0);
1836 /* Strip off CONST here to avoid special case tests later. */
1837 if (disp
&& GET_CODE (disp
) == CONST
)
1838 disp
= XEXP (disp
, 0);
1840 /* We can convert literal pool addresses to
1841 displacements by basing them off the base register. */
1842 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1844 /* Either base or index must be free to hold the base register. */
1846 base
= fake_pool_base
, literal_pool
= true;
1848 indx
= fake_pool_base
, literal_pool
= true;
1852 /* Mark up the displacement. */
1853 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1854 UNSPEC_LTREL_OFFSET
);
1857 /* Validate base register. */
1860 if (GET_CODE (base
) == UNSPEC
)
1861 switch (XINT (base
, 1))
1865 disp
= gen_rtx_UNSPEC (Pmode
,
1866 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1867 UNSPEC_LTREL_OFFSET
);
1871 base
= XVECEXP (base
, 0, 1);
1874 case UNSPEC_LTREL_BASE
:
1875 if (XVECLEN (base
, 0) == 1)
1876 base
= fake_pool_base
, literal_pool
= true;
1878 base
= XVECEXP (base
, 0, 1);
1886 || (GET_MODE (base
) != SImode
1887 && GET_MODE (base
) != Pmode
))
1890 if (REGNO (base
) == STACK_POINTER_REGNUM
1891 || REGNO (base
) == FRAME_POINTER_REGNUM
1892 || ((reload_completed
|| reload_in_progress
)
1893 && frame_pointer_needed
1894 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1895 || REGNO (base
) == ARG_POINTER_REGNUM
1897 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1898 pointer
= base_ptr
= true;
1900 if ((reload_completed
|| reload_in_progress
)
1901 && base
== cfun
->machine
->base_reg
)
1902 pointer
= base_ptr
= literal_pool
= true;
1905 /* Validate index register. */
1908 if (GET_CODE (indx
) == UNSPEC
)
1909 switch (XINT (indx
, 1))
1913 disp
= gen_rtx_UNSPEC (Pmode
,
1914 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1915 UNSPEC_LTREL_OFFSET
);
1919 indx
= XVECEXP (indx
, 0, 1);
1922 case UNSPEC_LTREL_BASE
:
1923 if (XVECLEN (indx
, 0) == 1)
1924 indx
= fake_pool_base
, literal_pool
= true;
1926 indx
= XVECEXP (indx
, 0, 1);
1934 || (GET_MODE (indx
) != SImode
1935 && GET_MODE (indx
) != Pmode
))
1938 if (REGNO (indx
) == STACK_POINTER_REGNUM
1939 || REGNO (indx
) == FRAME_POINTER_REGNUM
1940 || ((reload_completed
|| reload_in_progress
)
1941 && frame_pointer_needed
1942 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1943 || REGNO (indx
) == ARG_POINTER_REGNUM
1945 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1946 pointer
= indx_ptr
= true;
1948 if ((reload_completed
|| reload_in_progress
)
1949 && indx
== cfun
->machine
->base_reg
)
1950 pointer
= indx_ptr
= literal_pool
= true;
1953 /* Prefer to use pointer as base, not index. */
1954 if (base
&& indx
&& !base_ptr
1955 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1962 /* Validate displacement. */
1965 /* If virtual registers are involved, the displacement will change later
1966 anyway as the virtual registers get eliminated. This could make a
1967 valid displacement invalid, but it is more likely to make an invalid
1968 displacement valid, because we sometimes access the register save area
1969 via negative offsets to one of those registers.
1970 Thus we don't check the displacement for validity here. If after
1971 elimination the displacement turns out to be invalid after all,
1972 this is fixed up by reload in any case. */
1973 if (base
!= arg_pointer_rtx
1974 && indx
!= arg_pointer_rtx
1975 && base
!= return_address_pointer_rtx
1976 && indx
!= return_address_pointer_rtx
1977 && base
!= frame_pointer_rtx
1978 && indx
!= frame_pointer_rtx
1979 && base
!= virtual_stack_vars_rtx
1980 && indx
!= virtual_stack_vars_rtx
)
1981 if (!DISP_IN_RANGE (offset
))
1986 /* All the special cases are pointers. */
1989 /* In the small-PIC case, the linker converts @GOT
1990 and @GOTNTPOFF offsets to possible displacements. */
1991 if (GET_CODE (disp
) == UNSPEC
1992 && (XINT (disp
, 1) == UNSPEC_GOT
1993 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
1999 /* Accept pool label offsets. */
2000 else if (GET_CODE (disp
) == UNSPEC
2001 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2004 /* Accept literal pool references. */
2005 else if (GET_CODE (disp
) == UNSPEC
2006 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2008 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2011 /* If we have an offset, make sure it does not
2012 exceed the size of the constant pool entry. */
2013 rtx sym
= XVECEXP (disp
, 0, 0);
2014 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2017 orig_disp
= plus_constant (orig_disp
, offset
);
2032 out
->disp
= orig_disp
;
2033 out
->pointer
= pointer
;
2034 out
->literal_pool
= literal_pool
;
2040 /* Decompose a RTL expression OP for a shift count into its components,
2041 and return the base register in BASE and the offset in OFFSET.
2043 Return true if OP is a valid shift count, false if not. */
2046 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2048 HOST_WIDE_INT off
= 0;
2050 /* We can have an integer constant, an address register,
2051 or a sum of the two. */
2052 if (GET_CODE (op
) == CONST_INT
)
2057 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2059 off
= INTVAL (XEXP (op
, 1));
2062 while (op
&& GET_CODE (op
) == SUBREG
)
2063 op
= SUBREG_REG (op
);
2065 if (op
&& GET_CODE (op
) != REG
)
2077 /* Return true if CODE is a valid address without index. */
2080 s390_legitimate_address_without_index_p (rtx op
)
2082 struct s390_address addr
;
2084 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2093 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2094 and return these parts in SYMREF and ADDEND. You can pass NULL in
2095 SYMREF and/or ADDEND if you are not interested in these values.
2096 Literal pool references are *not* considered symbol references. */
2099 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2101 HOST_WIDE_INT tmpaddend
= 0;
2103 if (GET_CODE (addr
) == CONST
)
2104 addr
= XEXP (addr
, 0);
2106 if (GET_CODE (addr
) == PLUS
)
2108 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2109 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2110 && CONST_INT_P (XEXP (addr
, 1)))
2112 tmpaddend
= INTVAL (XEXP (addr
, 1));
2113 addr
= XEXP (addr
, 0);
2119 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2125 *addend
= tmpaddend
;
2131 /* Return true if the address in OP is valid for constraint letter C
2132 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2133 pool MEMs should be accepted. Only the Q, R, S, T constraint
2134 letters are allowed for C. */
2137 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2139 struct s390_address addr
;
2140 bool decomposed
= false;
2142 /* This check makes sure that no symbolic address (except literal
2143 pool references) are accepted by the R or T constraints. */
2144 if (s390_symref_operand_p (op
, NULL
, NULL
))
2147 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2150 if (!s390_decompose_address (op
, &addr
))
2152 if (addr
.literal_pool
)
2159 case 'Q': /* no index short displacement */
2160 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2164 if (!s390_short_displacement (addr
.disp
))
2168 case 'R': /* with index short displacement */
2169 if (TARGET_LONG_DISPLACEMENT
)
2171 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2173 if (!s390_short_displacement (addr
.disp
))
2176 /* Any invalid address here will be fixed up by reload,
2177 so accept it for the most generic constraint. */
2180 case 'S': /* no index long displacement */
2181 if (!TARGET_LONG_DISPLACEMENT
)
2183 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2187 if (s390_short_displacement (addr
.disp
))
2191 case 'T': /* with index long displacement */
2192 if (!TARGET_LONG_DISPLACEMENT
)
2194 /* Any invalid address here will be fixed up by reload,
2195 so accept it for the most generic constraint. */
2196 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2197 && s390_short_displacement (addr
.disp
))
2207 /* Evaluates constraint strings described by the regular expression
2208 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2209 the constraint given in STR, or 0 else. */
2212 s390_mem_constraint (const char *str
, rtx op
)
2219 /* Check for offsettable variants of memory constraints. */
2220 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2222 if ((reload_completed
|| reload_in_progress
)
2223 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2225 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2227 /* Check for non-literal-pool variants of memory constraints. */
2230 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2235 if (GET_CODE (op
) != MEM
)
2237 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2239 return (s390_check_qrst_address ('Q', op
, true)
2240 || s390_check_qrst_address ('R', op
, true));
2242 return (s390_check_qrst_address ('S', op
, true)
2243 || s390_check_qrst_address ('T', op
, true));
2245 /* Simply check for the basic form of a shift count. Reload will
2246 take care of making sure we have a proper base register. */
2247 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2251 return s390_check_qrst_address (str
[1], op
, true);
2259 /* Evaluates constraint strings starting with letter O. Input
2260 parameter C is the second letter following the "O" in the constraint
2261 string. Returns 1 if VALUE meets the respective constraint and 0
2265 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2273 return trunc_int_for_mode (value
, SImode
) == value
;
2277 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2280 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2288 /* Evaluates constraint strings starting with letter N. Parameter STR
2289 contains the letters following letter "N" in the constraint string.
2290 Returns true if VALUE matches the constraint. */
2293 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2295 enum machine_mode mode
, part_mode
;
2297 int part
, part_goal
;
2303 part_goal
= str
[0] - '0';
2347 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2350 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2353 if (part_goal
!= -1 && part_goal
!= part
)
2360 /* Returns true if the input parameter VALUE is a float zero. */
2363 s390_float_const_zero_p (rtx value
)
2365 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2366 && value
== CONST0_RTX (GET_MODE (value
)));
2370 /* Compute a (partial) cost for rtx X. Return true if the complete
2371 cost has been computed, and false if subexpressions should be
2372 scanned. In either case, *TOTAL contains the cost result.
2373 CODE contains GET_CODE (x), OUTER_CODE contains the code
2374 of the superexpression of x. */
2377 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2378 bool speed ATTRIBUTE_UNUSED
)
2401 *total
= COSTS_N_INSNS (1);
2406 /* Check for multiply and add. */
2407 if ((GET_MODE (x
) == DFmode
|| GET_MODE (x
) == SFmode
)
2408 && GET_CODE (XEXP (x
, 0)) == MULT
2409 && TARGET_HARD_FLOAT
&& TARGET_FUSED_MADD
)
2411 /* This is the multiply and add case. */
2412 if (GET_MODE (x
) == DFmode
)
2413 *total
= s390_cost
->madbr
;
2415 *total
= s390_cost
->maebr
;
2416 *total
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), MULT
, speed
)
2417 + rtx_cost (XEXP (XEXP (x
, 0), 1), MULT
, speed
)
2418 + rtx_cost (XEXP (x
, 1), (enum rtx_code
) code
, speed
));
2419 return true; /* Do not do an additional recursive descent. */
2421 *total
= COSTS_N_INSNS (1);
2425 switch (GET_MODE (x
))
2429 rtx left
= XEXP (x
, 0);
2430 rtx right
= XEXP (x
, 1);
2431 if (GET_CODE (right
) == CONST_INT
2432 && CONST_OK_FOR_K (INTVAL (right
)))
2433 *total
= s390_cost
->mhi
;
2434 else if (GET_CODE (left
) == SIGN_EXTEND
)
2435 *total
= s390_cost
->mh
;
2437 *total
= s390_cost
->ms
; /* msr, ms, msy */
2442 rtx left
= XEXP (x
, 0);
2443 rtx right
= XEXP (x
, 1);
2446 if (GET_CODE (right
) == CONST_INT
2447 && CONST_OK_FOR_K (INTVAL (right
)))
2448 *total
= s390_cost
->mghi
;
2449 else if (GET_CODE (left
) == SIGN_EXTEND
)
2450 *total
= s390_cost
->msgf
;
2452 *total
= s390_cost
->msg
; /* msgr, msg */
2454 else /* TARGET_31BIT */
2456 if (GET_CODE (left
) == SIGN_EXTEND
2457 && GET_CODE (right
) == SIGN_EXTEND
)
2458 /* mulsidi case: mr, m */
2459 *total
= s390_cost
->m
;
2460 else if (GET_CODE (left
) == ZERO_EXTEND
2461 && GET_CODE (right
) == ZERO_EXTEND
2462 && TARGET_CPU_ZARCH
)
2463 /* umulsidi case: ml, mlr */
2464 *total
= s390_cost
->ml
;
2466 /* Complex calculation is required. */
2467 *total
= COSTS_N_INSNS (40);
2473 *total
= s390_cost
->mult_df
;
2476 *total
= s390_cost
->mxbr
;
2485 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2486 *total
= s390_cost
->dlgr
;
2487 else if (GET_MODE (x
) == DImode
)
2489 rtx right
= XEXP (x
, 1);
2490 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2491 *total
= s390_cost
->dlr
;
2492 else /* 64 by 64 bit division */
2493 *total
= s390_cost
->dlgr
;
2495 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2496 *total
= s390_cost
->dlr
;
2501 if (GET_MODE (x
) == DImode
)
2503 rtx right
= XEXP (x
, 1);
2504 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2506 *total
= s390_cost
->dsgfr
;
2508 *total
= s390_cost
->dr
;
2509 else /* 64 by 64 bit division */
2510 *total
= s390_cost
->dsgr
;
2512 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2513 *total
= s390_cost
->dlr
;
2514 else if (GET_MODE (x
) == SFmode
)
2516 *total
= s390_cost
->debr
;
2518 else if (GET_MODE (x
) == DFmode
)
2520 *total
= s390_cost
->ddbr
;
2522 else if (GET_MODE (x
) == TFmode
)
2524 *total
= s390_cost
->dxbr
;
2529 if (GET_MODE (x
) == SFmode
)
2530 *total
= s390_cost
->sqebr
;
2531 else if (GET_MODE (x
) == DFmode
)
2532 *total
= s390_cost
->sqdbr
;
2534 *total
= s390_cost
->sqxbr
;
2539 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2540 || outer_code
== PLUS
|| outer_code
== MINUS
2541 || outer_code
== COMPARE
)
2546 *total
= COSTS_N_INSNS (1);
2547 if (GET_CODE (XEXP (x
, 0)) == AND
2548 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2549 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2551 rtx op0
= XEXP (XEXP (x
, 0), 0);
2552 rtx op1
= XEXP (XEXP (x
, 0), 1);
2553 rtx op2
= XEXP (x
, 1);
2555 if (memory_operand (op0
, GET_MODE (op0
))
2556 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2558 if (register_operand (op0
, GET_MODE (op0
))
2559 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2569 /* Return the cost of an address rtx ADDR. */
2572 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2574 struct s390_address ad
;
2575 if (!s390_decompose_address (addr
, &ad
))
2578 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2581 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2582 otherwise return 0. */
2585 tls_symbolic_operand (rtx op
)
2587 if (GET_CODE (op
) != SYMBOL_REF
)
2589 return SYMBOL_REF_TLS_MODEL (op
);
2592 /* Split DImode access register reference REG (on 64-bit) into its constituent
2593 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2594 gen_highpart cannot be used as they assume all registers are word-sized,
2595 while our access registers have only half that size. */
2598 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2600 gcc_assert (TARGET_64BIT
);
2601 gcc_assert (ACCESS_REG_P (reg
));
2602 gcc_assert (GET_MODE (reg
) == DImode
);
2603 gcc_assert (!(REGNO (reg
) & 1));
2605 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2606 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2609 /* Return true if OP contains a symbol reference */
2612 symbolic_reference_mentioned_p (rtx op
)
2617 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2620 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2621 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2627 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2628 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2632 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2639 /* Return true if OP contains a reference to a thread-local symbol. */
2642 tls_symbolic_reference_mentioned_p (rtx op
)
2647 if (GET_CODE (op
) == SYMBOL_REF
)
2648 return tls_symbolic_operand (op
);
2650 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2651 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2657 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2658 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2662 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2670 /* Return true if OP is a legitimate general operand when
2671 generating PIC code. It is given that flag_pic is on
2672 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2675 legitimate_pic_operand_p (rtx op
)
2677 /* Accept all non-symbolic constants. */
2678 if (!SYMBOLIC_CONST (op
))
2681 /* Reject everything else; must be handled
2682 via emit_symbolic_move. */
2686 /* Returns true if the constant value OP is a legitimate general operand.
2687 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2690 legitimate_constant_p (rtx op
)
2692 /* Accept all non-symbolic constants. */
2693 if (!SYMBOLIC_CONST (op
))
2696 /* Accept immediate LARL operands. */
2697 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2700 /* Thread-local symbols are never legal constants. This is
2701 so that emit_call knows that computing such addresses
2702 might require a function call. */
2703 if (TLS_SYMBOLIC_CONST (op
))
2706 /* In the PIC case, symbolic constants must *not* be
2707 forced into the literal pool. We accept them here,
2708 so that they will be handled by emit_symbolic_move. */
2712 /* All remaining non-PIC symbolic constants are
2713 forced into the literal pool. */
2717 /* Determine if it's legal to put X into the constant pool. This
2718 is not possible if X contains the address of a symbol that is
2719 not constant (TLS) or not known at final link time (PIC). */
2722 s390_cannot_force_const_mem (rtx x
)
2724 switch (GET_CODE (x
))
2728 /* Accept all non-symbolic constants. */
2732 /* Labels are OK iff we are non-PIC. */
2733 return flag_pic
!= 0;
2736 /* 'Naked' TLS symbol references are never OK,
2737 non-TLS symbols are OK iff we are non-PIC. */
2738 if (tls_symbolic_operand (x
))
2741 return flag_pic
!= 0;
2744 return s390_cannot_force_const_mem (XEXP (x
, 0));
2747 return s390_cannot_force_const_mem (XEXP (x
, 0))
2748 || s390_cannot_force_const_mem (XEXP (x
, 1));
2751 switch (XINT (x
, 1))
2753 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2754 case UNSPEC_LTREL_OFFSET
:
2762 case UNSPEC_GOTNTPOFF
:
2763 case UNSPEC_INDNTPOFF
:
2766 /* If the literal pool shares the code section, be put
2767 execute template placeholders into the pool as well. */
2769 return TARGET_CPU_ZARCH
;
2781 /* Returns true if the constant value OP is a legitimate general
2782 operand during and after reload. The difference to
2783 legitimate_constant_p is that this function will not accept
2784 a constant that would need to be forced to the literal pool
2785 before it can be used as operand. */
2788 legitimate_reload_constant_p (rtx op
)
2790 /* Accept la(y) operands. */
2791 if (GET_CODE (op
) == CONST_INT
2792 && DISP_IN_RANGE (INTVAL (op
)))
2795 /* Accept l(g)hi/l(g)fi operands. */
2796 if (GET_CODE (op
) == CONST_INT
2797 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2800 /* Accept lliXX operands. */
2802 && GET_CODE (op
) == CONST_INT
2803 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2804 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2808 && GET_CODE (op
) == CONST_INT
2809 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2810 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2813 /* Accept larl operands. */
2814 if (TARGET_CPU_ZARCH
2815 && larl_operand (op
, VOIDmode
))
2818 /* Accept floating-point zero operands that fit into a single GPR. */
2819 if (GET_CODE (op
) == CONST_DOUBLE
2820 && s390_float_const_zero_p (op
)
2821 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2824 /* Accept double-word operands that can be split. */
2825 if (GET_CODE (op
) == CONST_INT
2826 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2828 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2829 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2830 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2831 return legitimate_reload_constant_p (hi
)
2832 && legitimate_reload_constant_p (lo
);
2835 /* Everything else cannot be handled without reload. */
2839 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2840 return the class of reg to actually use. */
2843 s390_preferred_reload_class (rtx op
, enum reg_class rclass
)
2845 switch (GET_CODE (op
))
2847 /* Constants we cannot reload into general registers
2848 must be forced into the literal pool. */
2851 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2852 && legitimate_reload_constant_p (op
))
2853 return GENERAL_REGS
;
2854 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2855 && legitimate_reload_constant_p (op
))
2860 /* If a symbolic constant or a PLUS is reloaded,
2861 it is most likely being used as an address, so
2862 prefer ADDR_REGS. If 'class' is not a superset
2863 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2868 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2880 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2881 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2885 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2887 HOST_WIDE_INT addend
;
2890 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2893 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
2894 && !(addend
& (alignment
- 1)));
2897 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2898 operand SCRATCH is used to reload the even part of the address and
2902 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
2904 HOST_WIDE_INT addend
;
2907 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2911 /* Easy case. The addend is even so larl will do fine. */
2912 emit_move_insn (reg
, addr
);
2915 /* We can leave the scratch register untouched if the target
2916 register is a valid base register. */
2917 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
2918 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
2921 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
2922 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
2925 emit_move_insn (scratch
,
2926 gen_rtx_CONST (Pmode
,
2927 gen_rtx_PLUS (Pmode
, symref
,
2928 GEN_INT (addend
- 1))));
2930 emit_move_insn (scratch
, symref
);
2932 /* Increment the address using la in order to avoid clobbering cc. */
2933 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
2937 /* Generate what is necessary to move between REG and MEM using
2938 SCRATCH. The direction is given by TOMEM. */
2941 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
2943 /* Reload might have pulled a constant out of the literal pool.
2944 Force it back in. */
2945 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
2946 || GET_CODE (mem
) == CONST
)
2947 mem
= force_const_mem (GET_MODE (reg
), mem
);
2949 gcc_assert (MEM_P (mem
));
2951 /* For a load from memory we can leave the scratch register
2952 untouched if the target register is a valid base register. */
2954 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
2955 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
2956 && GET_MODE (reg
) == GET_MODE (scratch
))
2959 /* Load address into scratch register. Since we can't have a
2960 secondary reload for a secondary reload we have to cover the case
2961 where larl would need a secondary reload here as well. */
2962 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
2964 /* Now we can use a standard load/store to do the move. */
2966 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
2968 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
2971 /* Inform reload about cases where moving X with a mode MODE to a register in
2972 RCLASS requires an extra scratch or immediate register. Return the class
2973 needed for the immediate register. */
2976 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
2977 enum machine_mode mode
, secondary_reload_info
*sri
)
2979 enum reg_class rclass
= (enum reg_class
) rclass_i
;
2981 /* Intermediate register needed. */
2982 if (reg_classes_intersect_p (CC_REGS
, rclass
))
2983 return GENERAL_REGS
;
2987 /* On z10 several optimizer steps may generate larl operands with
2990 && s390_symref_operand_p (x
, NULL
, NULL
)
2992 && !s390_check_symref_alignment (x
, 2))
2993 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2994 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
2996 /* On z10 we need a scratch register when moving QI, TI or floating
2997 point mode values from or to a memory location with a SYMBOL_REF
2998 or if the symref addend of a SI or DI move is not aligned to the
2999 width of the access. */
3001 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3002 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3003 || (!TARGET_ZARCH
&& mode
== DImode
)
3004 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3005 && (!s390_check_symref_alignment (XEXP (x
, 0),
3006 GET_MODE_SIZE (mode
))))))
3008 #define __SECONDARY_RELOAD_CASE(M,m) \
3011 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3012 CODE_FOR_reload##m##di_tomem_z10; \
3014 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3015 CODE_FOR_reload##m##si_tomem_z10; \
3018 switch (GET_MODE (x
))
3020 __SECONDARY_RELOAD_CASE (QI
, qi
);
3021 __SECONDARY_RELOAD_CASE (HI
, hi
);
3022 __SECONDARY_RELOAD_CASE (SI
, si
);
3023 __SECONDARY_RELOAD_CASE (DI
, di
);
3024 __SECONDARY_RELOAD_CASE (TI
, ti
);
3025 __SECONDARY_RELOAD_CASE (SF
, sf
);
3026 __SECONDARY_RELOAD_CASE (DF
, df
);
3027 __SECONDARY_RELOAD_CASE (TF
, tf
);
3028 __SECONDARY_RELOAD_CASE (SD
, sd
);
3029 __SECONDARY_RELOAD_CASE (DD
, dd
);
3030 __SECONDARY_RELOAD_CASE (TD
, td
);
3035 #undef __SECONDARY_RELOAD_CASE
3039 /* We need a scratch register when loading a PLUS expression which
3040 is not a legitimate operand of the LOAD ADDRESS instruction. */
3041 if (in_p
&& s390_plus_operand (x
, mode
))
3042 sri
->icode
= (TARGET_64BIT
?
3043 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3045 /* Performing a multiword move from or to memory we have to make sure the
3046 second chunk in memory is addressable without causing a displacement
3047 overflow. If that would be the case we calculate the address in
3048 a scratch register. */
3050 && GET_CODE (XEXP (x
, 0)) == PLUS
3051 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3052 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3053 + GET_MODE_SIZE (mode
) - 1))
3055 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3056 in a s_operand address since we may fallback to lm/stm. So we only
3057 have to care about overflows in the b+i+d case. */
3058 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3059 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3060 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3061 /* For FP_REGS no lm/stm is available so this check is triggered
3062 for displacement overflows in b+i+d and b+d like addresses. */
3063 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3064 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3067 sri
->icode
= (TARGET_64BIT
?
3068 CODE_FOR_reloaddi_nonoffmem_in
:
3069 CODE_FOR_reloadsi_nonoffmem_in
);
3071 sri
->icode
= (TARGET_64BIT
?
3072 CODE_FOR_reloaddi_nonoffmem_out
:
3073 CODE_FOR_reloadsi_nonoffmem_out
);
3077 /* A scratch address register is needed when a symbolic constant is
3078 copied to r0 compiling with -fPIC. In other cases the target
3079 register might be used as temporary (see legitimize_pic_address). */
3080 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3081 sri
->icode
= (TARGET_64BIT
?
3082 CODE_FOR_reloaddi_PIC_addr
:
3083 CODE_FOR_reloadsi_PIC_addr
);
3085 /* Either scratch or no register needed. */
3089 /* Generate code to load SRC, which is PLUS that is not a
3090 legitimate operand for the LA instruction, into TARGET.
3091 SCRATCH may be used as scratch register. */
3094 s390_expand_plus_operand (rtx target
, rtx src
,
3098 struct s390_address ad
;
3100 /* src must be a PLUS; get its two operands. */
3101 gcc_assert (GET_CODE (src
) == PLUS
);
3102 gcc_assert (GET_MODE (src
) == Pmode
);
3104 /* Check if any of the two operands is already scheduled
3105 for replacement by reload. This can happen e.g. when
3106 float registers occur in an address. */
3107 sum1
= find_replacement (&XEXP (src
, 0));
3108 sum2
= find_replacement (&XEXP (src
, 1));
3109 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3111 /* If the address is already strictly valid, there's nothing to do. */
3112 if (!s390_decompose_address (src
, &ad
)
3113 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3114 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3116 /* Otherwise, one of the operands cannot be an address register;
3117 we reload its value into the scratch register. */
3118 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3120 emit_move_insn (scratch
, sum1
);
3123 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3125 emit_move_insn (scratch
, sum2
);
3129 /* According to the way these invalid addresses are generated
3130 in reload.c, it should never happen (at least on s390) that
3131 *neither* of the PLUS components, after find_replacements
3132 was applied, is an address register. */
3133 if (sum1
== scratch
&& sum2
== scratch
)
3139 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3142 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3143 is only ever performed on addresses, so we can mark the
3144 sum as legitimate for LA in any case. */
3145 s390_load_address (target
, src
);
3149 /* Return true if ADDR is a valid memory address.
3150 STRICT specifies whether strict register checking applies. */
3153 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3155 struct s390_address ad
;
3158 && larl_operand (addr
, VOIDmode
)
3159 && (mode
== VOIDmode
3160 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3163 if (!s390_decompose_address (addr
, &ad
))
3168 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3171 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3177 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3178 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3182 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3183 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3189 /* Return true if OP is a valid operand for the LA instruction.
3190 In 31-bit, we need to prove that the result is used as an
3191 address, as LA performs only a 31-bit addition. */
3194 legitimate_la_operand_p (rtx op
)
3196 struct s390_address addr
;
3197 if (!s390_decompose_address (op
, &addr
))
3200 return (TARGET_64BIT
|| addr
.pointer
);
3203 /* Return true if it is valid *and* preferable to use LA to
3204 compute the sum of OP1 and OP2. */
3207 preferred_la_operand_p (rtx op1
, rtx op2
)
3209 struct s390_address addr
;
3211 if (op2
!= const0_rtx
)
3212 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3214 if (!s390_decompose_address (op1
, &addr
))
3216 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3218 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3221 if (!TARGET_64BIT
&& !addr
.pointer
)
3227 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3228 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3234 /* Emit a forced load-address operation to load SRC into DST.
3235 This will use the LOAD ADDRESS instruction even in situations
3236 where legitimate_la_operand_p (SRC) returns false. */
3239 s390_load_address (rtx dst
, rtx src
)
3242 emit_move_insn (dst
, src
);
3244 emit_insn (gen_force_la_31 (dst
, src
));
3247 /* Return a legitimate reference for ORIG (an address) using the
3248 register REG. If REG is 0, a new pseudo is generated.
3250 There are two types of references that must be handled:
3252 1. Global data references must load the address from the GOT, via
3253 the PIC reg. An insn is emitted to do this load, and the reg is
3256 2. Static data references, constant pool addresses, and code labels
3257 compute the address as an offset from the GOT, whose base is in
3258 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3259 differentiate them from global data objects. The returned
3260 address is the PIC reg + an unspec constant.
3262 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3263 reg also appears in the address. */
3266 legitimize_pic_address (rtx orig
, rtx reg
)
3272 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3274 if (GET_CODE (addr
) == LABEL_REF
3275 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3277 /* This is a local symbol. */
3278 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3280 /* Access local symbols PC-relative via LARL.
3281 This is the same as in the non-PIC case, so it is
3282 handled automatically ... */
3286 /* Access local symbols relative to the GOT. */
3288 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3290 if (reload_in_progress
|| reload_completed
)
3291 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3293 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3294 addr
= gen_rtx_CONST (Pmode
, addr
);
3295 addr
= force_const_mem (Pmode
, addr
);
3296 emit_move_insn (temp
, addr
);
3298 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3301 s390_load_address (reg
, new_rtx
);
3306 else if (GET_CODE (addr
) == SYMBOL_REF
)
3309 reg
= gen_reg_rtx (Pmode
);
3313 /* Assume GOT offset < 4k. This is handled the same way
3314 in both 31- and 64-bit code (@GOT). */
3316 if (reload_in_progress
|| reload_completed
)
3317 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3319 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3320 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3321 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3322 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3323 emit_move_insn (reg
, new_rtx
);
3326 else if (TARGET_CPU_ZARCH
)
3328 /* If the GOT offset might be >= 4k, we determine the position
3329 of the GOT entry via a PC-relative LARL (@GOTENT). */
3331 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3333 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3334 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3336 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3337 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3338 emit_move_insn (temp
, new_rtx
);
3340 new_rtx
= gen_const_mem (Pmode
, temp
);
3341 emit_move_insn (reg
, new_rtx
);
3346 /* If the GOT offset might be >= 4k, we have to load it
3347 from the literal pool (@GOT). */
3349 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3351 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3352 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3354 if (reload_in_progress
|| reload_completed
)
3355 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3357 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3358 addr
= gen_rtx_CONST (Pmode
, addr
);
3359 addr
= force_const_mem (Pmode
, addr
);
3360 emit_move_insn (temp
, addr
);
3362 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3363 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3364 emit_move_insn (reg
, new_rtx
);
3370 if (GET_CODE (addr
) == CONST
)
3372 addr
= XEXP (addr
, 0);
3373 if (GET_CODE (addr
) == UNSPEC
)
3375 gcc_assert (XVECLEN (addr
, 0) == 1);
3376 switch (XINT (addr
, 1))
3378 /* If someone moved a GOT-relative UNSPEC
3379 out of the literal pool, force them back in. */
3382 new_rtx
= force_const_mem (Pmode
, orig
);
3385 /* @GOT is OK as is if small. */
3388 new_rtx
= force_const_mem (Pmode
, orig
);
3391 /* @GOTENT is OK as is. */
3395 /* @PLT is OK as is on 64-bit, must be converted to
3396 GOT-relative @PLTOFF on 31-bit. */
3398 if (!TARGET_CPU_ZARCH
)
3400 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3402 if (reload_in_progress
|| reload_completed
)
3403 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3405 addr
= XVECEXP (addr
, 0, 0);
3406 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3408 addr
= gen_rtx_CONST (Pmode
, addr
);
3409 addr
= force_const_mem (Pmode
, addr
);
3410 emit_move_insn (temp
, addr
);
3412 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3415 s390_load_address (reg
, new_rtx
);
3421 /* Everything else cannot happen. */
3427 gcc_assert (GET_CODE (addr
) == PLUS
);
3429 if (GET_CODE (addr
) == PLUS
)
3431 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3433 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3434 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3436 /* Check first to see if this is a constant offset
3437 from a local symbol reference. */
3438 if ((GET_CODE (op0
) == LABEL_REF
3439 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3440 && GET_CODE (op1
) == CONST_INT
)
3442 if (TARGET_CPU_ZARCH
3443 && larl_operand (op0
, VOIDmode
)
3444 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3445 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3447 if (INTVAL (op1
) & 1)
3449 /* LARL can't handle odd offsets, so emit a
3450 pair of LARL and LA. */
3451 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3453 if (!DISP_IN_RANGE (INTVAL (op1
)))
3455 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3456 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3457 op0
= gen_rtx_CONST (Pmode
, op0
);
3461 emit_move_insn (temp
, op0
);
3462 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3466 s390_load_address (reg
, new_rtx
);
3472 /* If the offset is even, we can just use LARL.
3473 This will happen automatically. */
3478 /* Access local symbols relative to the GOT. */
3480 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3482 if (reload_in_progress
|| reload_completed
)
3483 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3485 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3487 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3488 addr
= gen_rtx_CONST (Pmode
, addr
);
3489 addr
= force_const_mem (Pmode
, addr
);
3490 emit_move_insn (temp
, addr
);
3492 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3495 s390_load_address (reg
, new_rtx
);
3501 /* Now, check whether it is a GOT relative symbol plus offset
3502 that was pulled out of the literal pool. Force it back in. */
3504 else if (GET_CODE (op0
) == UNSPEC
3505 && GET_CODE (op1
) == CONST_INT
3506 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3508 gcc_assert (XVECLEN (op0
, 0) == 1);
3510 new_rtx
= force_const_mem (Pmode
, orig
);
3513 /* Otherwise, compute the sum. */
3516 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3517 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3518 base
== reg
? NULL_RTX
: reg
);
3519 if (GET_CODE (new_rtx
) == CONST_INT
)
3520 new_rtx
= plus_constant (base
, INTVAL (new_rtx
));
3523 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3525 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3526 new_rtx
= XEXP (new_rtx
, 1);
3528 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3531 if (GET_CODE (new_rtx
) == CONST
)
3532 new_rtx
= XEXP (new_rtx
, 0);
3533 new_rtx
= force_operand (new_rtx
, 0);
3540 /* Load the thread pointer into a register. */
3543 s390_get_thread_pointer (void)
3545 rtx tp
= gen_reg_rtx (Pmode
);
3547 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3548 mark_reg_pointer (tp
, BITS_PER_WORD
);
3553 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3554 in s390_tls_symbol which always refers to __tls_get_offset.
3555 The returned offset is written to RESULT_REG and an USE rtx is
3556 generated for TLS_CALL. */
3558 static GTY(()) rtx s390_tls_symbol
;
3561 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3565 gcc_assert (flag_pic
);
3567 if (!s390_tls_symbol
)
3568 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3570 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3571 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3573 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3574 RTL_CONST_CALL_P (insn
) = 1;
3577 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3578 this (thread-local) address. REG may be used as temporary. */
3581 legitimize_tls_address (rtx addr
, rtx reg
)
3583 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3585 if (GET_CODE (addr
) == SYMBOL_REF
)
3586 switch (tls_symbolic_operand (addr
))
3588 case TLS_MODEL_GLOBAL_DYNAMIC
:
3590 r2
= gen_rtx_REG (Pmode
, 2);
3591 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3592 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3593 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3594 emit_move_insn (r2
, new_rtx
);
3595 s390_emit_tls_call_insn (r2
, tls_call
);
3596 insn
= get_insns ();
3599 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3600 temp
= gen_reg_rtx (Pmode
);
3601 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3603 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3606 s390_load_address (reg
, new_rtx
);
3611 case TLS_MODEL_LOCAL_DYNAMIC
:
3613 r2
= gen_rtx_REG (Pmode
, 2);
3614 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3615 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3616 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3617 emit_move_insn (r2
, new_rtx
);
3618 s390_emit_tls_call_insn (r2
, tls_call
);
3619 insn
= get_insns ();
3622 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3623 temp
= gen_reg_rtx (Pmode
);
3624 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3626 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3627 base
= gen_reg_rtx (Pmode
);
3628 s390_load_address (base
, new_rtx
);
3630 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3631 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3632 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3633 temp
= gen_reg_rtx (Pmode
);
3634 emit_move_insn (temp
, new_rtx
);
3636 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3639 s390_load_address (reg
, new_rtx
);
3644 case TLS_MODEL_INITIAL_EXEC
:
3647 /* Assume GOT offset < 4k. This is handled the same way
3648 in both 31- and 64-bit code. */
3650 if (reload_in_progress
|| reload_completed
)
3651 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3653 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3654 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3655 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3656 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3657 temp
= gen_reg_rtx (Pmode
);
3658 emit_move_insn (temp
, new_rtx
);
3660 else if (TARGET_CPU_ZARCH
)
3662 /* If the GOT offset might be >= 4k, we determine the position
3663 of the GOT entry via a PC-relative LARL. */
3665 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3666 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3667 temp
= gen_reg_rtx (Pmode
);
3668 emit_move_insn (temp
, new_rtx
);
3670 new_rtx
= gen_const_mem (Pmode
, temp
);
3671 temp
= gen_reg_rtx (Pmode
);
3672 emit_move_insn (temp
, new_rtx
);
3676 /* If the GOT offset might be >= 4k, we have to load it
3677 from the literal pool. */
3679 if (reload_in_progress
|| reload_completed
)
3680 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3682 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3683 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3684 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3685 temp
= gen_reg_rtx (Pmode
);
3686 emit_move_insn (temp
, new_rtx
);
3688 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3689 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3691 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3692 temp
= gen_reg_rtx (Pmode
);
3693 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3697 /* In position-dependent code, load the absolute address of
3698 the GOT entry from the literal pool. */
3700 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3701 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3702 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3703 temp
= gen_reg_rtx (Pmode
);
3704 emit_move_insn (temp
, new_rtx
);
3707 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3708 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3709 temp
= gen_reg_rtx (Pmode
);
3710 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3713 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3716 s390_load_address (reg
, new_rtx
);
3721 case TLS_MODEL_LOCAL_EXEC
:
3722 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3723 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3724 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3725 temp
= gen_reg_rtx (Pmode
);
3726 emit_move_insn (temp
, new_rtx
);
3728 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3731 s390_load_address (reg
, new_rtx
);
3740 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3742 switch (XINT (XEXP (addr
, 0), 1))
3744 case UNSPEC_INDNTPOFF
:
3745 gcc_assert (TARGET_CPU_ZARCH
);
3754 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3755 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3757 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3758 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3759 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3761 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3762 new_rtx
= plus_constant (new_rtx
, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3763 new_rtx
= force_operand (new_rtx
, 0);
3767 gcc_unreachable (); /* for now ... */
3772 /* Emit insns making the address in operands[1] valid for a standard
3773 move to operands[0]. operands[1] is replaced by an address which
3774 should be used instead of the former RTX to emit the move
3778 emit_symbolic_move (rtx
*operands
)
3780 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3782 if (GET_CODE (operands
[0]) == MEM
)
3783 operands
[1] = force_reg (Pmode
, operands
[1]);
3784 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3785 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3787 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3790 /* Try machine-dependent ways of modifying an illegitimate address X
3791 to be legitimate. If we find one, return the new, valid address.
3793 OLDX is the address as it was before break_out_memory_refs was called.
3794 In some cases it is useful to look at this to decide what needs to be done.
3796 MODE is the mode of the operand pointed to by X.
3798 When -fpic is used, special handling is needed for symbolic references.
3799 See comments by legitimize_pic_address for details. */
3802 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3803 enum machine_mode mode ATTRIBUTE_UNUSED
)
3805 rtx constant_term
= const0_rtx
;
3807 if (TLS_SYMBOLIC_CONST (x
))
3809 x
= legitimize_tls_address (x
, 0);
3811 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3814 else if (GET_CODE (x
) == PLUS
3815 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3816 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3822 if (SYMBOLIC_CONST (x
)
3823 || (GET_CODE (x
) == PLUS
3824 && (SYMBOLIC_CONST (XEXP (x
, 0))
3825 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3826 x
= legitimize_pic_address (x
, 0);
3828 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3832 x
= eliminate_constant_term (x
, &constant_term
);
3834 /* Optimize loading of large displacements by splitting them
3835 into the multiple of 4K and the rest; this allows the
3836 former to be CSE'd if possible.
3838 Don't do this if the displacement is added to a register
3839 pointing into the stack frame, as the offsets will
3840 change later anyway. */
3842 if (GET_CODE (constant_term
) == CONST_INT
3843 && !TARGET_LONG_DISPLACEMENT
3844 && !DISP_IN_RANGE (INTVAL (constant_term
))
3845 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3847 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3848 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3850 rtx temp
= gen_reg_rtx (Pmode
);
3851 rtx val
= force_operand (GEN_INT (upper
), temp
);
3853 emit_move_insn (temp
, val
);
3855 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3856 constant_term
= GEN_INT (lower
);
3859 if (GET_CODE (x
) == PLUS
)
3861 if (GET_CODE (XEXP (x
, 0)) == REG
)
3863 rtx temp
= gen_reg_rtx (Pmode
);
3864 rtx val
= force_operand (XEXP (x
, 1), temp
);
3866 emit_move_insn (temp
, val
);
3868 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3871 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3873 rtx temp
= gen_reg_rtx (Pmode
);
3874 rtx val
= force_operand (XEXP (x
, 0), temp
);
3876 emit_move_insn (temp
, val
);
3878 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3882 if (constant_term
!= const0_rtx
)
3883 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3888 /* Try a machine-dependent way of reloading an illegitimate address AD
3889 operand. If we find one, push the reload and and return the new address.
3891 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3892 and TYPE is the reload type of the current reload. */
3895 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3896 int opnum
, int type
)
3898 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3901 if (GET_CODE (ad
) == PLUS
)
3903 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3904 XEXP (ad
, 0), XEXP (ad
, 1));
3909 if (GET_CODE (ad
) == PLUS
3910 && GET_CODE (XEXP (ad
, 0)) == REG
3911 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
3912 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
3914 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
3915 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
3916 rtx cst
, tem
, new_rtx
;
3918 cst
= GEN_INT (upper
);
3919 if (!legitimate_reload_constant_p (cst
))
3920 cst
= force_const_mem (Pmode
, cst
);
3922 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
3923 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
3925 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
3926 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3927 opnum
, (enum reload_type
) type
);
3934 /* Emit code to move LEN bytes from DST to SRC. */
3937 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
3939 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3941 if (INTVAL (len
) > 0)
3942 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
3945 else if (TARGET_MVCLE
)
3947 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
3952 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
3953 rtx loop_start_label
= gen_label_rtx ();
3954 rtx loop_end_label
= gen_label_rtx ();
3955 rtx end_label
= gen_label_rtx ();
3956 enum machine_mode mode
;
3958 mode
= GET_MODE (len
);
3959 if (mode
== VOIDmode
)
3962 dst_addr
= gen_reg_rtx (Pmode
);
3963 src_addr
= gen_reg_rtx (Pmode
);
3964 count
= gen_reg_rtx (mode
);
3965 blocks
= gen_reg_rtx (mode
);
3967 convert_move (count
, len
, 1);
3968 emit_cmp_and_jump_insns (count
, const0_rtx
,
3969 EQ
, NULL_RTX
, mode
, 1, end_label
);
3971 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
3972 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
3973 dst
= change_address (dst
, VOIDmode
, dst_addr
);
3974 src
= change_address (src
, VOIDmode
, src_addr
);
3976 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
3979 emit_move_insn (count
, temp
);
3981 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
3984 emit_move_insn (blocks
, temp
);
3986 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3987 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3989 emit_label (loop_start_label
);
3992 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
3996 /* Issue a read prefetch for the +3 cache line. */
3997 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
3998 const0_rtx
, const0_rtx
);
3999 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4000 emit_insn (prefetch
);
4002 /* Issue a write prefetch for the +3 cache line. */
4003 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4004 const1_rtx
, const0_rtx
);
4005 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4006 emit_insn (prefetch
);
4009 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4010 s390_load_address (dst_addr
,
4011 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4012 s390_load_address (src_addr
,
4013 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4015 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4018 emit_move_insn (blocks
, temp
);
4020 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4021 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4023 emit_jump (loop_start_label
);
4024 emit_label (loop_end_label
);
4026 emit_insn (gen_movmem_short (dst
, src
,
4027 convert_to_mode (Pmode
, count
, 1)));
4028 emit_label (end_label
);
4032 /* Emit code to set LEN bytes at DST to VAL.
4033 Make use of clrmem if VAL is zero. */
4036 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4038 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4041 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4043 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4045 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4046 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4049 /* Initialize memory by storing the first byte. */
4050 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4052 if (INTVAL (len
) > 1)
4054 /* Initiate 1 byte overlap move.
4055 The first byte of DST is propagated through DSTP1.
4056 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4057 DST is set to size 1 so the rest of the memory location
4058 does not count as source operand. */
4059 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4060 set_mem_size (dst
, const1_rtx
);
4062 emit_insn (gen_movmem_short (dstp1
, dst
,
4063 GEN_INT (INTVAL (len
) - 2)));
4068 else if (TARGET_MVCLE
)
4070 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4071 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4076 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4077 rtx loop_start_label
= gen_label_rtx ();
4078 rtx loop_end_label
= gen_label_rtx ();
4079 rtx end_label
= gen_label_rtx ();
4080 enum machine_mode mode
;
4082 mode
= GET_MODE (len
);
4083 if (mode
== VOIDmode
)
4086 dst_addr
= gen_reg_rtx (Pmode
);
4087 count
= gen_reg_rtx (mode
);
4088 blocks
= gen_reg_rtx (mode
);
4090 convert_move (count
, len
, 1);
4091 emit_cmp_and_jump_insns (count
, const0_rtx
,
4092 EQ
, NULL_RTX
, mode
, 1, end_label
);
4094 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4095 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4097 if (val
== const0_rtx
)
4098 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4102 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4103 set_mem_size (dst
, const1_rtx
);
4105 /* Initialize memory by storing the first byte. */
4106 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4108 /* If count is 1 we are done. */
4109 emit_cmp_and_jump_insns (count
, const1_rtx
,
4110 EQ
, NULL_RTX
, mode
, 1, end_label
);
4112 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4116 emit_move_insn (count
, temp
);
4118 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4121 emit_move_insn (blocks
, temp
);
4123 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4124 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4126 emit_label (loop_start_label
);
4129 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4131 /* Issue a write prefetch for the +4 cache line. */
4132 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4134 const1_rtx
, const0_rtx
);
4135 emit_insn (prefetch
);
4136 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4139 if (val
== const0_rtx
)
4140 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4142 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4143 s390_load_address (dst_addr
,
4144 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4146 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4149 emit_move_insn (blocks
, temp
);
4151 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4152 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4154 emit_jump (loop_start_label
);
4155 emit_label (loop_end_label
);
4157 if (val
== const0_rtx
)
4158 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4160 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4161 emit_label (end_label
);
4165 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4166 and return the result in TARGET. */
4169 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4171 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4174 /* As the result of CMPINT is inverted compared to what we need,
4175 we have to swap the operands. */
4176 tmp
= op0
; op0
= op1
; op1
= tmp
;
4178 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4180 if (INTVAL (len
) > 0)
4182 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4183 emit_insn (gen_cmpint (target
, ccreg
));
4186 emit_move_insn (target
, const0_rtx
);
4188 else if (TARGET_MVCLE
)
4190 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4191 emit_insn (gen_cmpint (target
, ccreg
));
4195 rtx addr0
, addr1
, count
, blocks
, temp
;
4196 rtx loop_start_label
= gen_label_rtx ();
4197 rtx loop_end_label
= gen_label_rtx ();
4198 rtx end_label
= gen_label_rtx ();
4199 enum machine_mode mode
;
4201 mode
= GET_MODE (len
);
4202 if (mode
== VOIDmode
)
4205 addr0
= gen_reg_rtx (Pmode
);
4206 addr1
= gen_reg_rtx (Pmode
);
4207 count
= gen_reg_rtx (mode
);
4208 blocks
= gen_reg_rtx (mode
);
4210 convert_move (count
, len
, 1);
4211 emit_cmp_and_jump_insns (count
, const0_rtx
,
4212 EQ
, NULL_RTX
, mode
, 1, end_label
);
4214 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4215 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4216 op0
= change_address (op0
, VOIDmode
, addr0
);
4217 op1
= change_address (op1
, VOIDmode
, addr1
);
4219 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4222 emit_move_insn (count
, temp
);
4224 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4227 emit_move_insn (blocks
, temp
);
4229 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4230 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4232 emit_label (loop_start_label
);
4235 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4239 /* Issue a read prefetch for the +2 cache line of operand 1. */
4240 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4241 const0_rtx
, const0_rtx
);
4242 emit_insn (prefetch
);
4243 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4245 /* Issue a read prefetch for the +2 cache line of operand 2. */
4246 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4247 const0_rtx
, const0_rtx
);
4248 emit_insn (prefetch
);
4249 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4252 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4253 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4254 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4255 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4256 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4257 emit_jump_insn (temp
);
4259 s390_load_address (addr0
,
4260 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4261 s390_load_address (addr1
,
4262 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4264 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4267 emit_move_insn (blocks
, temp
);
4269 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4270 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4272 emit_jump (loop_start_label
);
4273 emit_label (loop_end_label
);
4275 emit_insn (gen_cmpmem_short (op0
, op1
,
4276 convert_to_mode (Pmode
, count
, 1)));
4277 emit_label (end_label
);
4279 emit_insn (gen_cmpint (target
, ccreg
));
4284 /* Expand conditional increment or decrement using alc/slb instructions.
4285 Should generate code setting DST to either SRC or SRC + INCREMENT,
4286 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4287 Returns true if successful, false otherwise.
4289 That makes it possible to implement some if-constructs without jumps e.g.:
4290 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4291 unsigned int a, b, c;
4292 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4293 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4294 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4295 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4297 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4298 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4299 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4300 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4301 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4304 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4305 rtx dst
, rtx src
, rtx increment
)
4307 enum machine_mode cmp_mode
;
4308 enum machine_mode cc_mode
;
4314 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4315 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4317 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4318 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4323 /* Try ADD LOGICAL WITH CARRY. */
4324 if (increment
== const1_rtx
)
4326 /* Determine CC mode to use. */
4327 if (cmp_code
== EQ
|| cmp_code
== NE
)
4329 if (cmp_op1
!= const0_rtx
)
4331 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4332 NULL_RTX
, 0, OPTAB_WIDEN
);
4333 cmp_op1
= const0_rtx
;
4336 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4339 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4344 cmp_code
= swap_condition (cmp_code
);
4361 /* Emit comparison instruction pattern. */
4362 if (!register_operand (cmp_op0
, cmp_mode
))
4363 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4365 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4366 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4367 /* We use insn_invalid_p here to add clobbers if required. */
4368 ret
= insn_invalid_p (emit_insn (insn
));
4371 /* Emit ALC instruction pattern. */
4372 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4373 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4376 if (src
!= const0_rtx
)
4378 if (!register_operand (src
, GET_MODE (dst
)))
4379 src
= force_reg (GET_MODE (dst
), src
);
4381 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4382 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4385 p
= rtvec_alloc (2);
4387 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4389 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4390 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4395 /* Try SUBTRACT LOGICAL WITH BORROW. */
4396 if (increment
== constm1_rtx
)
4398 /* Determine CC mode to use. */
4399 if (cmp_code
== EQ
|| cmp_code
== NE
)
4401 if (cmp_op1
!= const0_rtx
)
4403 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4404 NULL_RTX
, 0, OPTAB_WIDEN
);
4405 cmp_op1
= const0_rtx
;
4408 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4411 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4416 cmp_code
= swap_condition (cmp_code
);
4433 /* Emit comparison instruction pattern. */
4434 if (!register_operand (cmp_op0
, cmp_mode
))
4435 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4437 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4438 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4439 /* We use insn_invalid_p here to add clobbers if required. */
4440 ret
= insn_invalid_p (emit_insn (insn
));
4443 /* Emit SLB instruction pattern. */
4444 if (!register_operand (src
, GET_MODE (dst
)))
4445 src
= force_reg (GET_MODE (dst
), src
);
4447 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4448 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4449 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4450 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4452 p
= rtvec_alloc (2);
4454 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4456 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4457 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4465 /* Expand code for the insv template. Return true if successful. */
4468 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4470 int bitsize
= INTVAL (op1
);
4471 int bitpos
= INTVAL (op2
);
4473 /* On z10 we can use the risbg instruction to implement insv. */
4475 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4476 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4481 op
= gen_rtx_SET (GET_MODE(src
),
4482 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4484 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4485 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4490 /* We need byte alignment. */
4491 if (bitsize
% BITS_PER_UNIT
)
4495 && memory_operand (dest
, VOIDmode
)
4496 && (register_operand (src
, word_mode
)
4497 || const_int_operand (src
, VOIDmode
)))
4499 /* Emit standard pattern if possible. */
4500 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4501 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4502 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4504 /* (set (ze (mem)) (const_int)). */
4505 else if (const_int_operand (src
, VOIDmode
))
4507 int size
= bitsize
/ BITS_PER_UNIT
;
4508 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4509 GET_MODE_SIZE (word_mode
) - size
);
4511 dest
= adjust_address (dest
, BLKmode
, 0);
4512 set_mem_size (dest
, GEN_INT (size
));
4513 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4516 /* (set (ze (mem)) (reg)). */
4517 else if (register_operand (src
, word_mode
))
4519 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4520 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4524 /* Emit st,stcmh sequence. */
4525 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4526 int size
= stcmh_width
/ BITS_PER_UNIT
;
4528 emit_move_insn (adjust_address (dest
, SImode
, size
),
4529 gen_lowpart (SImode
, src
));
4530 set_mem_size (dest
, GEN_INT (size
));
4531 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4532 (stcmh_width
), const0_rtx
),
4533 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4534 (GET_MODE_BITSIZE (SImode
))));
4543 /* (set (ze (reg)) (const_int)). */
4545 && register_operand (dest
, word_mode
)
4546 && (bitpos
% 16) == 0
4547 && (bitsize
% 16) == 0
4548 && const_int_operand (src
, VOIDmode
))
4550 HOST_WIDE_INT val
= INTVAL (src
);
4551 int regpos
= bitpos
+ bitsize
;
4553 while (regpos
> bitpos
)
4555 enum machine_mode putmode
;
4558 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4563 putsize
= GET_MODE_BITSIZE (putmode
);
4565 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4568 gen_int_mode (val
, putmode
));
4571 gcc_assert (regpos
== bitpos
);
4578 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4579 register that holds VAL of mode MODE shifted by COUNT bits. */
4582 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4584 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4585 NULL_RTX
, 1, OPTAB_DIRECT
);
4586 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4587 NULL_RTX
, 1, OPTAB_DIRECT
);
4590 /* Structure to hold the initial parameters for a compare_and_swap operation
4591 in HImode and QImode. */
4593 struct alignment_context
4595 rtx memsi
; /* SI aligned memory location. */
4596 rtx shift
; /* Bit offset with regard to lsb. */
4597 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4598 rtx modemaski
; /* ~modemask */
4599 bool aligned
; /* True if memory is aligned, false else. */
4602 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4603 structure AC for transparent simplifying, if the memory alignment is known
4604 to be at least 32bit. MEM is the memory location for the actual operation
4605 and MODE its mode. */
4608 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4609 enum machine_mode mode
)
4611 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4612 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4615 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4618 /* Alignment is unknown. */
4619 rtx byteoffset
, addr
, align
;
4621 /* Force the address into a register. */
4622 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4624 /* Align it to SImode. */
4625 align
= expand_simple_binop (Pmode
, AND
, addr
,
4626 GEN_INT (-GET_MODE_SIZE (SImode
)),
4627 NULL_RTX
, 1, OPTAB_DIRECT
);
4629 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4630 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4631 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4632 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4634 /* Calculate shiftcount. */
4635 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4636 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4637 NULL_RTX
, 1, OPTAB_DIRECT
);
4638 /* As we already have some offset, evaluate the remaining distance. */
4639 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4640 NULL_RTX
, 1, OPTAB_DIRECT
);
4643 /* Shift is the byte count, but we need the bitcount. */
4644 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4645 NULL_RTX
, 1, OPTAB_DIRECT
);
4646 /* Calculate masks. */
4647 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4648 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4649 NULL_RTX
, 1, OPTAB_DIRECT
);
4650 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4653 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4654 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4655 to set if CMP == MEM.
4656 CMP is never in memory for compare_and_swap_cc because
4657 expand_bool_compare_and_swap puts it into a register for later compare. */
4660 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4662 struct alignment_context ac
;
4663 rtx cmpv
, newv
, val
, resv
, cc
;
4664 rtx res
= gen_reg_rtx (SImode
);
4665 rtx csloop
= gen_label_rtx ();
4666 rtx csend
= gen_label_rtx ();
4668 gcc_assert (register_operand (target
, VOIDmode
));
4669 gcc_assert (MEM_P (mem
));
4671 init_alignment_context (&ac
, mem
, mode
);
4673 /* Shift the values to the correct bit positions. */
4674 if (!(ac
.aligned
&& MEM_P (cmp
)))
4675 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4676 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4677 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4679 /* Load full word. Subsequent loads are performed by CS. */
4680 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4681 NULL_RTX
, 1, OPTAB_DIRECT
);
4683 /* Start CS loop. */
4684 emit_label (csloop
);
4685 /* val = "<mem>00..0<mem>"
4686 * cmp = "00..0<cmp>00..0"
4687 * new = "00..0<new>00..0"
4690 /* Patch cmp and new with val at correct position. */
4691 if (ac
.aligned
&& MEM_P (cmp
))
4693 cmpv
= force_reg (SImode
, val
);
4694 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4697 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4698 NULL_RTX
, 1, OPTAB_DIRECT
));
4699 if (ac
.aligned
&& MEM_P (new_rtx
))
4701 newv
= force_reg (SImode
, val
);
4702 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new_rtx
);
4705 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4706 NULL_RTX
, 1, OPTAB_DIRECT
));
4708 /* Jump to end if we're done (likely?). */
4709 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4712 /* Check for changes outside mode. */
4713 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4714 NULL_RTX
, 1, OPTAB_DIRECT
);
4715 cc
= s390_emit_compare (NE
, resv
, val
);
4716 emit_move_insn (val
, resv
);
4717 /* Loop internal if so. */
4718 s390_emit_jump (csloop
, cc
);
4722 /* Return the correct part of the bitfield. */
4723 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4724 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4727 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4728 and VAL the value to play with. If AFTER is true then store the value
4729 MEM holds after the operation, if AFTER is false then store the value MEM
4730 holds before the operation. If TARGET is zero then discard that value, else
4731 store it to TARGET. */
4734 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4735 rtx target
, rtx mem
, rtx val
, bool after
)
4737 struct alignment_context ac
;
4739 rtx new_rtx
= gen_reg_rtx (SImode
);
4740 rtx orig
= gen_reg_rtx (SImode
);
4741 rtx csloop
= gen_label_rtx ();
4743 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4744 gcc_assert (MEM_P (mem
));
4746 init_alignment_context (&ac
, mem
, mode
);
4748 /* Shift val to the correct bit positions.
4749 Preserve "icm", but prevent "ex icm". */
4750 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4751 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4753 /* Further preparation insns. */
4754 if (code
== PLUS
|| code
== MINUS
)
4755 emit_move_insn (orig
, val
);
4756 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4757 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4758 NULL_RTX
, 1, OPTAB_DIRECT
);
4760 /* Load full word. Subsequent loads are performed by CS. */
4761 cmp
= force_reg (SImode
, ac
.memsi
);
4763 /* Start CS loop. */
4764 emit_label (csloop
);
4765 emit_move_insn (new_rtx
, cmp
);
4767 /* Patch new with val at correct position. */
4772 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4773 NULL_RTX
, 1, OPTAB_DIRECT
);
4774 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4775 NULL_RTX
, 1, OPTAB_DIRECT
);
4778 if (ac
.aligned
&& MEM_P (val
))
4779 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4782 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4783 NULL_RTX
, 1, OPTAB_DIRECT
);
4784 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4785 NULL_RTX
, 1, OPTAB_DIRECT
);
4791 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4792 NULL_RTX
, 1, OPTAB_DIRECT
);
4794 case MULT
: /* NAND */
4795 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4796 NULL_RTX
, 1, OPTAB_DIRECT
);
4797 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4798 NULL_RTX
, 1, OPTAB_DIRECT
);
4804 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4805 ac
.memsi
, cmp
, new_rtx
));
4807 /* Return the correct part of the bitfield. */
4809 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4810 after
? new_rtx
: cmp
, ac
.shift
,
4811 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4814 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4815 We need to emit DTP-relative relocations. */
4817 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4820 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4825 fputs ("\t.long\t", file
);
4828 fputs ("\t.quad\t", file
);
4833 output_addr_const (file
, x
);
4834 fputs ("@DTPOFF", file
);
4837 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4838 /* Implement TARGET_MANGLE_TYPE. */
4841 s390_mangle_type (const_tree type
)
4843 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4844 && TARGET_LONG_DOUBLE_128
)
4847 /* For all other types, use normal C++ mangling. */
4852 /* In the name of slightly smaller debug output, and to cater to
4853 general assembler lossage, recognize various UNSPEC sequences
4854 and turn them back into a direct symbol reference. */
4857 s390_delegitimize_address (rtx orig_x
)
4861 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4863 if (GET_CODE (x
) != MEM
)
4867 if (GET_CODE (x
) == PLUS
4868 && GET_CODE (XEXP (x
, 1)) == CONST
4869 && GET_CODE (XEXP (x
, 0)) == REG
4870 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4872 y
= XEXP (XEXP (x
, 1), 0);
4873 if (GET_CODE (y
) == UNSPEC
4874 && XINT (y
, 1) == UNSPEC_GOT
)
4875 return XVECEXP (y
, 0, 0);
4879 if (GET_CODE (x
) == CONST
)
4882 if (GET_CODE (y
) == UNSPEC
4883 && XINT (y
, 1) == UNSPEC_GOTENT
)
4884 return XVECEXP (y
, 0, 0);
4891 /* Output operand OP to stdio stream FILE.
4892 OP is an address (register + offset) which is not used to address data;
4893 instead the rightmost bits are interpreted as the value. */
4896 print_shift_count_operand (FILE *file
, rtx op
)
4898 HOST_WIDE_INT offset
;
4901 /* Extract base register and offset. */
4902 if (!s390_decompose_shift_count (op
, &base
, &offset
))
4908 gcc_assert (GET_CODE (base
) == REG
);
4909 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
4910 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
4913 /* Offsets are constricted to twelve bits. */
4914 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
4916 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
4919 /* See 'get_some_local_dynamic_name'. */
4922 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4926 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4928 x
= get_pool_constant (x
);
4929 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
4932 if (GET_CODE (x
) == SYMBOL_REF
4933 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4935 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4942 /* Locate some local-dynamic symbol still in use by this function
4943 so that we can print its name in local-dynamic base patterns. */
4946 get_some_local_dynamic_name (void)
4950 if (cfun
->machine
->some_ld_name
)
4951 return cfun
->machine
->some_ld_name
;
4953 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4955 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4956 return cfun
->machine
->some_ld_name
;
4961 /* Output machine-dependent UNSPECs occurring in address constant X
4962 in assembler syntax to stdio stream FILE. Returns true if the
4963 constant X could be recognized, false otherwise. */
4966 s390_output_addr_const_extra (FILE *file
, rtx x
)
4968 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
4969 switch (XINT (x
, 1))
4972 output_addr_const (file
, XVECEXP (x
, 0, 0));
4973 fprintf (file
, "@GOTENT");
4976 output_addr_const (file
, XVECEXP (x
, 0, 0));
4977 fprintf (file
, "@GOT");
4980 output_addr_const (file
, XVECEXP (x
, 0, 0));
4981 fprintf (file
, "@GOTOFF");
4984 output_addr_const (file
, XVECEXP (x
, 0, 0));
4985 fprintf (file
, "@PLT");
4988 output_addr_const (file
, XVECEXP (x
, 0, 0));
4989 fprintf (file
, "@PLTOFF");
4992 output_addr_const (file
, XVECEXP (x
, 0, 0));
4993 fprintf (file
, "@TLSGD");
4996 assemble_name (file
, get_some_local_dynamic_name ());
4997 fprintf (file
, "@TLSLDM");
5000 output_addr_const (file
, XVECEXP (x
, 0, 0));
5001 fprintf (file
, "@DTPOFF");
5004 output_addr_const (file
, XVECEXP (x
, 0, 0));
5005 fprintf (file
, "@NTPOFF");
5007 case UNSPEC_GOTNTPOFF
:
5008 output_addr_const (file
, XVECEXP (x
, 0, 0));
5009 fprintf (file
, "@GOTNTPOFF");
5011 case UNSPEC_INDNTPOFF
:
5012 output_addr_const (file
, XVECEXP (x
, 0, 0));
5013 fprintf (file
, "@INDNTPOFF");
5017 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5018 switch (XINT (x
, 1))
5020 case UNSPEC_POOL_OFFSET
:
5021 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5022 output_addr_const (file
, x
);
5028 /* Output address operand ADDR in assembler syntax to
5029 stdio stream FILE. */
5032 print_operand_address (FILE *file
, rtx addr
)
5034 struct s390_address ad
;
5036 if (s390_symref_operand_p (addr
, NULL
, NULL
))
5038 gcc_assert (TARGET_Z10
);
5039 output_addr_const (file
, addr
);
5043 if (!s390_decompose_address (addr
, &ad
)
5044 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5045 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5046 output_operand_lossage ("cannot decompose address");
5049 output_addr_const (file
, ad
.disp
);
5051 fprintf (file
, "0");
5053 if (ad
.base
&& ad
.indx
)
5054 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5055 reg_names
[REGNO (ad
.base
)]);
5057 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5060 /* Output operand X in assembler syntax to stdio stream FILE.
5061 CODE specified the format flag. The following format flags
5064 'C': print opcode suffix for branch condition.
5065 'D': print opcode suffix for inverse branch condition.
5066 'E': print opcode suffix for branch on index instruction.
5067 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5068 'G': print the size of the operand in bytes.
5069 'O': print only the displacement of a memory reference.
5070 'R': print only the base register of a memory reference.
5071 'S': print S-type memory reference (base+displacement).
5072 'N': print the second word of a DImode operand.
5073 'M': print the second word of a TImode operand.
5074 'Y': print shift count operand.
5076 'b': print integer X as if it's an unsigned byte.
5077 'c': print integer X as if it's an signed byte.
5078 'x': print integer X as if it's an unsigned halfword.
5079 'h': print integer X as if it's a signed halfword.
5080 'i': print the first nonzero HImode part of X.
5081 'j': print the first HImode part unequal to -1 of X.
5082 'k': print the first nonzero SImode part of X.
5083 'm': print the first SImode part unequal to -1 of X.
5084 'o': print integer X as if it's an unsigned 32bit word. */
5087 print_operand (FILE *file
, rtx x
, int code
)
5092 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5096 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5100 if (GET_CODE (x
) == LE
)
5101 fprintf (file
, "l");
5102 else if (GET_CODE (x
) == GT
)
5103 fprintf (file
, "h");
5109 if (GET_CODE (x
) == SYMBOL_REF
)
5111 fprintf (file
, "%s", ":tls_load:");
5112 output_addr_const (file
, x
);
5114 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5116 fprintf (file
, "%s", ":tls_gdcall:");
5117 output_addr_const (file
, XVECEXP (x
, 0, 0));
5119 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5121 fprintf (file
, "%s", ":tls_ldcall:");
5122 assemble_name (file
, get_some_local_dynamic_name ());
5129 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5134 struct s390_address ad
;
5137 gcc_assert (GET_CODE (x
) == MEM
);
5138 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5140 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5141 gcc_assert (!ad
.indx
);
5144 output_addr_const (file
, ad
.disp
);
5146 fprintf (file
, "0");
5152 struct s390_address ad
;
5155 gcc_assert (GET_CODE (x
) == MEM
);
5156 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5158 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5159 gcc_assert (!ad
.indx
);
5162 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5164 fprintf (file
, "0");
5170 struct s390_address ad
;
5173 gcc_assert (GET_CODE (x
) == MEM
);
5174 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5176 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5177 gcc_assert (!ad
.indx
);
5180 output_addr_const (file
, ad
.disp
);
5182 fprintf (file
, "0");
5185 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5190 if (GET_CODE (x
) == REG
)
5191 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5192 else if (GET_CODE (x
) == MEM
)
5193 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
5199 if (GET_CODE (x
) == REG
)
5200 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5201 else if (GET_CODE (x
) == MEM
)
5202 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
5208 print_shift_count_operand (file
, x
);
5212 switch (GET_CODE (x
))
5215 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5219 output_address (XEXP (x
, 0));
5226 output_addr_const (file
, x
);
5231 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5232 else if (code
== 'c')
5233 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5234 else if (code
== 'x')
5235 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5236 else if (code
== 'h')
5237 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5238 else if (code
== 'i')
5239 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5240 s390_extract_part (x
, HImode
, 0));
5241 else if (code
== 'j')
5242 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5243 s390_extract_part (x
, HImode
, -1));
5244 else if (code
== 'k')
5245 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5246 s390_extract_part (x
, SImode
, 0));
5247 else if (code
== 'm')
5248 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5249 s390_extract_part (x
, SImode
, -1));
5250 else if (code
== 'o')
5251 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5253 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5257 gcc_assert (GET_MODE (x
) == VOIDmode
);
5259 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5260 else if (code
== 'x')
5261 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5262 else if (code
== 'h')
5263 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5269 fatal_insn ("UNKNOWN in print_operand !?", x
);
5274 /* Target hook for assembling integer objects. We need to define it
5275 here to work a round a bug in some versions of GAS, which couldn't
5276 handle values smaller than INT_MIN when printed in decimal. */
5279 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5281 if (size
== 8 && aligned_p
5282 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5284 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5288 return default_assemble_integer (x
, size
, aligned_p
);
5291 /* Returns true if register REGNO is used for forming
5292 a memory address in expression X. */
5295 reg_used_in_mem_p (int regno
, rtx x
)
5297 enum rtx_code code
= GET_CODE (x
);
5303 if (refers_to_regno_p (regno
, regno
+1,
5307 else if (code
== SET
5308 && GET_CODE (SET_DEST (x
)) == PC
)
5310 if (refers_to_regno_p (regno
, regno
+1,
5315 fmt
= GET_RTX_FORMAT (code
);
5316 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5319 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5322 else if (fmt
[i
] == 'E')
5323 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5324 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5330 /* Returns true if expression DEP_RTX sets an address register
5331 used by instruction INSN to address memory. */
5334 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5338 if (GET_CODE (dep_rtx
) == INSN
)
5339 dep_rtx
= PATTERN (dep_rtx
);
5341 if (GET_CODE (dep_rtx
) == SET
)
5343 target
= SET_DEST (dep_rtx
);
5344 if (GET_CODE (target
) == STRICT_LOW_PART
)
5345 target
= XEXP (target
, 0);
5346 while (GET_CODE (target
) == SUBREG
)
5347 target
= SUBREG_REG (target
);
5349 if (GET_CODE (target
) == REG
)
5351 int regno
= REGNO (target
);
5353 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5355 pat
= PATTERN (insn
);
5356 if (GET_CODE (pat
) == PARALLEL
)
5358 gcc_assert (XVECLEN (pat
, 0) == 2);
5359 pat
= XVECEXP (pat
, 0, 0);
5361 gcc_assert (GET_CODE (pat
) == SET
);
5362 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5364 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5365 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5371 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5374 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5376 rtx dep_rtx
= PATTERN (dep_insn
);
5379 if (GET_CODE (dep_rtx
) == SET
5380 && addr_generation_dependency_p (dep_rtx
, insn
))
5382 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5384 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5386 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5394 /* A C statement (sans semicolon) to update the integer scheduling priority
5395 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5396 reduce the priority to execute INSN later. Do not define this macro if
5397 you do not need to adjust the scheduling priorities of insns.
5399 A STD instruction should be scheduled earlier,
5400 in order to use the bypass. */
5404 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5406 if (! INSN_P (insn
))
5409 if (s390_tune
!= PROCESSOR_2084_Z990
5410 && s390_tune
!= PROCESSOR_2094_Z9_109
5411 && s390_tune
!= PROCESSOR_2097_Z10
)
5414 switch (s390_safe_attr_type (insn
))
5418 priority
= priority
<< 3;
5422 priority
= priority
<< 1;
5431 /* The number of instructions that can be issued per cycle. */
5434 s390_issue_rate (void)
5438 case PROCESSOR_2084_Z990
:
5439 case PROCESSOR_2094_Z9_109
:
5441 case PROCESSOR_2097_Z10
:
5449 s390_first_cycle_multipass_dfa_lookahead (void)
5454 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5455 Fix up MEMs as required. */
5458 annotate_constant_pool_refs (rtx
*x
)
5463 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5464 || !CONSTANT_POOL_ADDRESS_P (*x
));
5466 /* Literal pool references can only occur inside a MEM ... */
5467 if (GET_CODE (*x
) == MEM
)
5469 rtx memref
= XEXP (*x
, 0);
5471 if (GET_CODE (memref
) == SYMBOL_REF
5472 && CONSTANT_POOL_ADDRESS_P (memref
))
5474 rtx base
= cfun
->machine
->base_reg
;
5475 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5478 *x
= replace_equiv_address (*x
, addr
);
5482 if (GET_CODE (memref
) == CONST
5483 && GET_CODE (XEXP (memref
, 0)) == PLUS
5484 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5485 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5486 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5488 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5489 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5490 rtx base
= cfun
->machine
->base_reg
;
5491 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5494 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
5499 /* ... or a load-address type pattern. */
5500 if (GET_CODE (*x
) == SET
)
5502 rtx addrref
= SET_SRC (*x
);
5504 if (GET_CODE (addrref
) == SYMBOL_REF
5505 && CONSTANT_POOL_ADDRESS_P (addrref
))
5507 rtx base
= cfun
->machine
->base_reg
;
5508 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5511 SET_SRC (*x
) = addr
;
5515 if (GET_CODE (addrref
) == CONST
5516 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5517 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5518 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5519 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5521 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5522 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5523 rtx base
= cfun
->machine
->base_reg
;
5524 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5527 SET_SRC (*x
) = plus_constant (addr
, off
);
5532 /* Annotate LTREL_BASE as well. */
5533 if (GET_CODE (*x
) == UNSPEC
5534 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5536 rtx base
= cfun
->machine
->base_reg
;
5537 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5542 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5543 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5547 annotate_constant_pool_refs (&XEXP (*x
, i
));
5549 else if (fmt
[i
] == 'E')
5551 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5552 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5557 /* Split all branches that exceed the maximum distance.
5558 Returns true if this created a new literal pool entry. */
5561 s390_split_branches (void)
5563 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5564 int new_literal
= 0, ret
;
5565 rtx insn
, pat
, tmp
, target
;
5568 /* We need correct insn addresses. */
5570 shorten_branches (get_insns ());
5572 /* Find all branches that exceed 64KB, and split them. */
5574 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5576 if (GET_CODE (insn
) != JUMP_INSN
)
5579 pat
= PATTERN (insn
);
5580 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5581 pat
= XVECEXP (pat
, 0, 0);
5582 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5585 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5587 label
= &SET_SRC (pat
);
5589 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5591 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5592 label
= &XEXP (SET_SRC (pat
), 1);
5593 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5594 label
= &XEXP (SET_SRC (pat
), 2);
5601 if (get_attr_length (insn
) <= 4)
5604 /* We are going to use the return register as scratch register,
5605 make sure it will be saved/restored by the prologue/epilogue. */
5606 cfun_frame_layout
.save_return_addr_p
= 1;
5611 tmp
= force_const_mem (Pmode
, *label
);
5612 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5613 INSN_ADDRESSES_NEW (tmp
, -1);
5614 annotate_constant_pool_refs (&PATTERN (tmp
));
5621 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5622 UNSPEC_LTREL_OFFSET
);
5623 target
= gen_rtx_CONST (Pmode
, target
);
5624 target
= force_const_mem (Pmode
, target
);
5625 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5626 INSN_ADDRESSES_NEW (tmp
, -1);
5627 annotate_constant_pool_refs (&PATTERN (tmp
));
5629 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5630 cfun
->machine
->base_reg
),
5632 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5635 ret
= validate_change (insn
, label
, target
, 0);
5643 /* Find an annotated literal pool symbol referenced in RTX X,
5644 and store it at REF. Will abort if X contains references to
5645 more than one such pool symbol; multiple references to the same
5646 symbol are allowed, however.
5648 The rtx pointed to by REF must be initialized to NULL_RTX
5649 by the caller before calling this routine. */
5652 find_constant_pool_ref (rtx x
, rtx
*ref
)
5657 /* Ignore LTREL_BASE references. */
5658 if (GET_CODE (x
) == UNSPEC
5659 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5661 /* Likewise POOL_ENTRY insns. */
5662 if (GET_CODE (x
) == UNSPEC_VOLATILE
5663 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5666 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5667 || !CONSTANT_POOL_ADDRESS_P (x
));
5669 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5671 rtx sym
= XVECEXP (x
, 0, 0);
5672 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5673 && CONSTANT_POOL_ADDRESS_P (sym
));
5675 if (*ref
== NULL_RTX
)
5678 gcc_assert (*ref
== sym
);
5683 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5684 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5688 find_constant_pool_ref (XEXP (x
, i
), ref
);
5690 else if (fmt
[i
] == 'E')
5692 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5693 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5698 /* Replace every reference to the annotated literal pool
5699 symbol REF in X by its base plus OFFSET. */
5702 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5707 gcc_assert (*x
!= ref
);
5709 if (GET_CODE (*x
) == UNSPEC
5710 && XINT (*x
, 1) == UNSPEC_LTREF
5711 && XVECEXP (*x
, 0, 0) == ref
)
5713 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5717 if (GET_CODE (*x
) == PLUS
5718 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5719 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5720 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5721 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5723 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5724 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5728 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5729 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5733 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5735 else if (fmt
[i
] == 'E')
5737 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5738 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5743 /* Check whether X contains an UNSPEC_LTREL_BASE.
5744 Return its constant pool symbol if found, NULL_RTX otherwise. */
5747 find_ltrel_base (rtx x
)
5752 if (GET_CODE (x
) == UNSPEC
5753 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5754 return XVECEXP (x
, 0, 0);
5756 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5757 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5761 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5765 else if (fmt
[i
] == 'E')
5767 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5769 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5779 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5782 replace_ltrel_base (rtx
*x
)
5787 if (GET_CODE (*x
) == UNSPEC
5788 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5790 *x
= XVECEXP (*x
, 0, 1);
5794 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5795 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5799 replace_ltrel_base (&XEXP (*x
, i
));
5801 else if (fmt
[i
] == 'E')
5803 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5804 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5810 /* We keep a list of constants which we have to add to internal
5811 constant tables in the middle of large functions. */
5813 #define NR_C_MODES 11
5814 enum machine_mode constant_modes
[NR_C_MODES
] =
5816 TFmode
, TImode
, TDmode
,
5817 DFmode
, DImode
, DDmode
,
5818 SFmode
, SImode
, SDmode
,
5825 struct constant
*next
;
5830 struct constant_pool
5832 struct constant_pool
*next
;
5836 rtx emit_pool_after
;
5838 struct constant
*constants
[NR_C_MODES
];
5839 struct constant
*execute
;
5844 /* Allocate new constant_pool structure. */
5846 static struct constant_pool
*
5847 s390_alloc_pool (void)
5849 struct constant_pool
*pool
;
5852 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
5854 for (i
= 0; i
< NR_C_MODES
; i
++)
5855 pool
->constants
[i
] = NULL
;
5857 pool
->execute
= NULL
;
5858 pool
->label
= gen_label_rtx ();
5859 pool
->first_insn
= NULL_RTX
;
5860 pool
->pool_insn
= NULL_RTX
;
5861 pool
->insns
= BITMAP_ALLOC (NULL
);
5863 pool
->emit_pool_after
= NULL_RTX
;
5868 /* Create new constant pool covering instructions starting at INSN
5869 and chain it to the end of POOL_LIST. */
5871 static struct constant_pool
*
5872 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
5874 struct constant_pool
*pool
, **prev
;
5876 pool
= s390_alloc_pool ();
5877 pool
->first_insn
= insn
;
5879 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
5886 /* End range of instructions covered by POOL at INSN and emit
5887 placeholder insn representing the pool. */
5890 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
5892 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
5895 insn
= get_last_insn ();
5897 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
5898 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5901 /* Add INSN to the list of insns covered by POOL. */
5904 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
5906 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
5909 /* Return pool out of POOL_LIST that covers INSN. */
5911 static struct constant_pool
*
5912 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
5914 struct constant_pool
*pool
;
5916 for (pool
= pool_list
; pool
; pool
= pool
->next
)
5917 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
5923 /* Add constant VAL of mode MODE to the constant pool POOL. */
5926 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
5931 for (i
= 0; i
< NR_C_MODES
; i
++)
5932 if (constant_modes
[i
] == mode
)
5934 gcc_assert (i
!= NR_C_MODES
);
5936 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5937 if (rtx_equal_p (val
, c
->value
))
5942 c
= (struct constant
*) xmalloc (sizeof *c
);
5944 c
->label
= gen_label_rtx ();
5945 c
->next
= pool
->constants
[i
];
5946 pool
->constants
[i
] = c
;
5947 pool
->size
+= GET_MODE_SIZE (mode
);
5951 /* Return an rtx that represents the offset of X from the start of
5955 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
5959 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
5960 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
5961 UNSPEC_POOL_OFFSET
);
5962 return gen_rtx_CONST (GET_MODE (x
), x
);
5965 /* Find constant VAL of mode MODE in the constant pool POOL.
5966 Return an RTX describing the distance from the start of
5967 the pool to the location of the new constant. */
5970 s390_find_constant (struct constant_pool
*pool
, rtx val
,
5971 enum machine_mode mode
)
5976 for (i
= 0; i
< NR_C_MODES
; i
++)
5977 if (constant_modes
[i
] == mode
)
5979 gcc_assert (i
!= NR_C_MODES
);
5981 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5982 if (rtx_equal_p (val
, c
->value
))
5987 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
5990 /* Check whether INSN is an execute. Return the label_ref to its
5991 execute target template if so, NULL_RTX otherwise. */
5994 s390_execute_label (rtx insn
)
5996 if (GET_CODE (insn
) == INSN
5997 && GET_CODE (PATTERN (insn
)) == PARALLEL
5998 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
5999 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6000 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6005 /* Add execute target for INSN to the constant pool POOL. */
6008 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6012 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6013 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6018 c
= (struct constant
*) xmalloc (sizeof *c
);
6020 c
->label
= gen_label_rtx ();
6021 c
->next
= pool
->execute
;
6027 /* Find execute target for INSN in the constant pool POOL.
6028 Return an RTX describing the distance from the start of
6029 the pool to the location of the execute target. */
6032 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6036 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6037 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6042 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6045 /* For an execute INSN, extract the execute target template. */
6048 s390_execute_target (rtx insn
)
6050 rtx pattern
= PATTERN (insn
);
6051 gcc_assert (s390_execute_label (insn
));
6053 if (XVECLEN (pattern
, 0) == 2)
6055 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6059 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6062 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6063 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6065 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6071 /* Indicate that INSN cannot be duplicated. This is the case for
6072 execute insns that carry a unique label. */
6075 s390_cannot_copy_insn_p (rtx insn
)
6077 rtx label
= s390_execute_label (insn
);
6078 return label
&& label
!= const0_rtx
;
6081 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6082 do not emit the pool base label. */
6085 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6088 rtx insn
= pool
->pool_insn
;
6091 /* Switch to rodata section. */
6092 if (TARGET_CPU_ZARCH
)
6094 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6095 INSN_ADDRESSES_NEW (insn
, -1);
6098 /* Ensure minimum pool alignment. */
6099 if (TARGET_CPU_ZARCH
)
6100 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6102 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6103 INSN_ADDRESSES_NEW (insn
, -1);
6105 /* Emit pool base label. */
6108 insn
= emit_label_after (pool
->label
, insn
);
6109 INSN_ADDRESSES_NEW (insn
, -1);
6112 /* Dump constants in descending alignment requirement order,
6113 ensuring proper alignment for every constant. */
6114 for (i
= 0; i
< NR_C_MODES
; i
++)
6115 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6117 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6118 rtx value
= copy_rtx (c
->value
);
6119 if (GET_CODE (value
) == CONST
6120 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6121 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6122 && XVECLEN (XEXP (value
, 0), 0) == 1)
6123 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6125 insn
= emit_label_after (c
->label
, insn
);
6126 INSN_ADDRESSES_NEW (insn
, -1);
6128 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6129 gen_rtvec (1, value
),
6130 UNSPECV_POOL_ENTRY
);
6131 insn
= emit_insn_after (value
, insn
);
6132 INSN_ADDRESSES_NEW (insn
, -1);
6135 /* Ensure minimum alignment for instructions. */
6136 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6137 INSN_ADDRESSES_NEW (insn
, -1);
6139 /* Output in-pool execute template insns. */
6140 for (c
= pool
->execute
; c
; c
= c
->next
)
6142 insn
= emit_label_after (c
->label
, insn
);
6143 INSN_ADDRESSES_NEW (insn
, -1);
6145 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6146 INSN_ADDRESSES_NEW (insn
, -1);
6149 /* Switch back to previous section. */
6150 if (TARGET_CPU_ZARCH
)
6152 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6153 INSN_ADDRESSES_NEW (insn
, -1);
6156 insn
= emit_barrier_after (insn
);
6157 INSN_ADDRESSES_NEW (insn
, -1);
6159 /* Remove placeholder insn. */
6160 remove_insn (pool
->pool_insn
);
6163 /* Free all memory used by POOL. */
6166 s390_free_pool (struct constant_pool
*pool
)
6168 struct constant
*c
, *next
;
6171 for (i
= 0; i
< NR_C_MODES
; i
++)
6172 for (c
= pool
->constants
[i
]; c
; c
= next
)
6178 for (c
= pool
->execute
; c
; c
= next
)
6184 BITMAP_FREE (pool
->insns
);
6189 /* Collect main literal pool. Return NULL on overflow. */
6191 static struct constant_pool
*
6192 s390_mainpool_start (void)
6194 struct constant_pool
*pool
;
6197 pool
= s390_alloc_pool ();
6199 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6201 if (GET_CODE (insn
) == INSN
6202 && GET_CODE (PATTERN (insn
)) == SET
6203 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6204 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6206 gcc_assert (!pool
->pool_insn
);
6207 pool
->pool_insn
= insn
;
6210 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6212 s390_add_execute (pool
, insn
);
6214 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6216 rtx pool_ref
= NULL_RTX
;
6217 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6220 rtx constant
= get_pool_constant (pool_ref
);
6221 enum machine_mode mode
= get_pool_mode (pool_ref
);
6222 s390_add_constant (pool
, constant
, mode
);
6226 /* If hot/cold partitioning is enabled we have to make sure that
6227 the literal pool is emitted in the same section where the
6228 initialization of the literal pool base pointer takes place.
6229 emit_pool_after is only used in the non-overflow case on non
6230 Z cpus where we can emit the literal pool at the end of the
6231 function body within the text section. */
6233 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6234 && !pool
->emit_pool_after
)
6235 pool
->emit_pool_after
= PREV_INSN (insn
);
6238 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6240 if (pool
->size
>= 4096)
6242 /* We're going to chunkify the pool, so remove the main
6243 pool placeholder insn. */
6244 remove_insn (pool
->pool_insn
);
6246 s390_free_pool (pool
);
6250 /* If the functions ends with the section where the literal pool
6251 should be emitted set the marker to its end. */
6252 if (pool
&& !pool
->emit_pool_after
)
6253 pool
->emit_pool_after
= get_last_insn ();
6258 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6259 Modify the current function to output the pool constants as well as
6260 the pool register setup instruction. */
6263 s390_mainpool_finish (struct constant_pool
*pool
)
6265 rtx base_reg
= cfun
->machine
->base_reg
;
6268 /* If the pool is empty, we're done. */
6269 if (pool
->size
== 0)
6271 /* We don't actually need a base register after all. */
6272 cfun
->machine
->base_reg
= NULL_RTX
;
6274 if (pool
->pool_insn
)
6275 remove_insn (pool
->pool_insn
);
6276 s390_free_pool (pool
);
6280 /* We need correct insn addresses. */
6281 shorten_branches (get_insns ());
6283 /* On zSeries, we use a LARL to load the pool register. The pool is
6284 located in the .rodata section, so we emit it after the function. */
6285 if (TARGET_CPU_ZARCH
)
6287 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6288 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6289 INSN_ADDRESSES_NEW (insn
, -1);
6290 remove_insn (pool
->pool_insn
);
6292 insn
= get_last_insn ();
6293 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6294 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6296 s390_dump_pool (pool
, 0);
6299 /* On S/390, if the total size of the function's code plus literal pool
6300 does not exceed 4096 bytes, we use BASR to set up a function base
6301 pointer, and emit the literal pool at the end of the function. */
6302 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6303 + pool
->size
+ 8 /* alignment slop */ < 4096)
6305 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6306 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6307 INSN_ADDRESSES_NEW (insn
, -1);
6308 remove_insn (pool
->pool_insn
);
6310 insn
= emit_label_after (pool
->label
, insn
);
6311 INSN_ADDRESSES_NEW (insn
, -1);
6313 /* emit_pool_after will be set by s390_mainpool_start to the
6314 last insn of the section where the literal pool should be
6316 insn
= pool
->emit_pool_after
;
6318 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6319 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6321 s390_dump_pool (pool
, 1);
6324 /* Otherwise, we emit an inline literal pool and use BASR to branch
6325 over it, setting up the pool register at the same time. */
6328 rtx pool_end
= gen_label_rtx ();
6330 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6331 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6332 INSN_ADDRESSES_NEW (insn
, -1);
6333 remove_insn (pool
->pool_insn
);
6335 insn
= emit_label_after (pool
->label
, insn
);
6336 INSN_ADDRESSES_NEW (insn
, -1);
6338 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6339 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6341 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6342 INSN_ADDRESSES_NEW (insn
, -1);
6344 s390_dump_pool (pool
, 1);
6348 /* Replace all literal pool references. */
6350 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6353 replace_ltrel_base (&PATTERN (insn
));
6355 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6357 rtx addr
, pool_ref
= NULL_RTX
;
6358 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6361 if (s390_execute_label (insn
))
6362 addr
= s390_find_execute (pool
, insn
);
6364 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6365 get_pool_mode (pool_ref
));
6367 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6368 INSN_CODE (insn
) = -1;
6374 /* Free the pool. */
6375 s390_free_pool (pool
);
6378 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6379 We have decided we cannot use this pool, so revert all changes
6380 to the current function that were done by s390_mainpool_start. */
6382 s390_mainpool_cancel (struct constant_pool
*pool
)
6384 /* We didn't actually change the instruction stream, so simply
6385 free the pool memory. */
6386 s390_free_pool (pool
);
6390 /* Chunkify the literal pool. */
6392 #define S390_POOL_CHUNK_MIN 0xc00
6393 #define S390_POOL_CHUNK_MAX 0xe00
6395 static struct constant_pool
*
6396 s390_chunkify_start (void)
6398 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6401 rtx pending_ltrel
= NULL_RTX
;
6404 rtx (*gen_reload_base
) (rtx
, rtx
) =
6405 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6408 /* We need correct insn addresses. */
6410 shorten_branches (get_insns ());
6412 /* Scan all insns and move literals to pool chunks. */
6414 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6416 bool section_switch_p
= false;
6418 /* Check for pending LTREL_BASE. */
6421 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6424 gcc_assert (ltrel_base
== pending_ltrel
);
6425 pending_ltrel
= NULL_RTX
;
6429 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6432 curr_pool
= s390_start_pool (&pool_list
, insn
);
6434 s390_add_execute (curr_pool
, insn
);
6435 s390_add_pool_insn (curr_pool
, insn
);
6437 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6439 rtx pool_ref
= NULL_RTX
;
6440 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6443 rtx constant
= get_pool_constant (pool_ref
);
6444 enum machine_mode mode
= get_pool_mode (pool_ref
);
6447 curr_pool
= s390_start_pool (&pool_list
, insn
);
6449 s390_add_constant (curr_pool
, constant
, mode
);
6450 s390_add_pool_insn (curr_pool
, insn
);
6452 /* Don't split the pool chunk between a LTREL_OFFSET load
6453 and the corresponding LTREL_BASE. */
6454 if (GET_CODE (constant
) == CONST
6455 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6456 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6458 gcc_assert (!pending_ltrel
);
6459 pending_ltrel
= pool_ref
;
6464 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6467 s390_add_pool_insn (curr_pool
, insn
);
6468 /* An LTREL_BASE must follow within the same basic block. */
6469 gcc_assert (!pending_ltrel
);
6472 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
6473 section_switch_p
= true;
6476 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6477 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6480 if (TARGET_CPU_ZARCH
)
6482 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6485 s390_end_pool (curr_pool
, NULL_RTX
);
6490 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6491 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6494 /* We will later have to insert base register reload insns.
6495 Those will have an effect on code size, which we need to
6496 consider here. This calculation makes rather pessimistic
6497 worst-case assumptions. */
6498 if (GET_CODE (insn
) == CODE_LABEL
)
6501 if (chunk_size
< S390_POOL_CHUNK_MIN
6502 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6503 && !section_switch_p
)
6506 /* Pool chunks can only be inserted after BARRIERs ... */
6507 if (GET_CODE (insn
) == BARRIER
)
6509 s390_end_pool (curr_pool
, insn
);
6514 /* ... so if we don't find one in time, create one. */
6515 else if (chunk_size
> S390_POOL_CHUNK_MAX
6516 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6517 || section_switch_p
)
6519 rtx label
, jump
, barrier
;
6521 if (!section_switch_p
)
6523 /* We can insert the barrier only after a 'real' insn. */
6524 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6526 if (get_attr_length (insn
) == 0)
6528 /* Don't separate LTREL_BASE from the corresponding
6529 LTREL_OFFSET load. */
6535 gcc_assert (!pending_ltrel
);
6537 /* The old pool has to end before the section switch
6538 note in order to make it part of the current
6540 insn
= PREV_INSN (insn
);
6543 label
= gen_label_rtx ();
6544 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
6545 barrier
= emit_barrier_after (jump
);
6546 insn
= emit_label_after (label
, barrier
);
6547 JUMP_LABEL (jump
) = label
;
6548 LABEL_NUSES (label
) = 1;
6550 INSN_ADDRESSES_NEW (jump
, -1);
6551 INSN_ADDRESSES_NEW (barrier
, -1);
6552 INSN_ADDRESSES_NEW (insn
, -1);
6554 s390_end_pool (curr_pool
, barrier
);
6562 s390_end_pool (curr_pool
, NULL_RTX
);
6563 gcc_assert (!pending_ltrel
);
6565 /* Find all labels that are branched into
6566 from an insn belonging to a different chunk. */
6568 far_labels
= BITMAP_ALLOC (NULL
);
6570 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6572 /* Labels marked with LABEL_PRESERVE_P can be target
6573 of non-local jumps, so we have to mark them.
6574 The same holds for named labels.
6576 Don't do that, however, if it is the label before
6579 if (GET_CODE (insn
) == CODE_LABEL
6580 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6582 rtx vec_insn
= next_real_insn (insn
);
6583 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6584 PATTERN (vec_insn
) : NULL_RTX
;
6586 || !(GET_CODE (vec_pat
) == ADDR_VEC
6587 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6588 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6591 /* If we have a direct jump (conditional or unconditional)
6592 or a casesi jump, check all potential targets. */
6593 else if (GET_CODE (insn
) == JUMP_INSN
)
6595 rtx pat
= PATTERN (insn
);
6596 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6597 pat
= XVECEXP (pat
, 0, 0);
6599 if (GET_CODE (pat
) == SET
)
6601 rtx label
= JUMP_LABEL (insn
);
6604 if (s390_find_pool (pool_list
, label
)
6605 != s390_find_pool (pool_list
, insn
))
6606 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6609 else if (GET_CODE (pat
) == PARALLEL
6610 && XVECLEN (pat
, 0) == 2
6611 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6612 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6613 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6615 /* Find the jump table used by this casesi jump. */
6616 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6617 rtx vec_insn
= next_real_insn (vec_label
);
6618 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6619 PATTERN (vec_insn
) : NULL_RTX
;
6621 && (GET_CODE (vec_pat
) == ADDR_VEC
6622 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6624 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6626 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6628 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6630 if (s390_find_pool (pool_list
, label
)
6631 != s390_find_pool (pool_list
, insn
))
6632 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6639 /* Insert base register reload insns before every pool. */
6641 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6643 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6645 rtx insn
= curr_pool
->first_insn
;
6646 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6649 /* Insert base register reload insns at every far label. */
6651 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6652 if (GET_CODE (insn
) == CODE_LABEL
6653 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6655 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6658 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6660 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6665 BITMAP_FREE (far_labels
);
6668 /* Recompute insn addresses. */
6670 init_insn_lengths ();
6671 shorten_branches (get_insns ());
6676 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6677 After we have decided to use this list, finish implementing
6678 all changes to the current function as required. */
6681 s390_chunkify_finish (struct constant_pool
*pool_list
)
6683 struct constant_pool
*curr_pool
= NULL
;
6687 /* Replace all literal pool references. */
6689 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6692 replace_ltrel_base (&PATTERN (insn
));
6694 curr_pool
= s390_find_pool (pool_list
, insn
);
6698 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6700 rtx addr
, pool_ref
= NULL_RTX
;
6701 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6704 if (s390_execute_label (insn
))
6705 addr
= s390_find_execute (curr_pool
, insn
);
6707 addr
= s390_find_constant (curr_pool
,
6708 get_pool_constant (pool_ref
),
6709 get_pool_mode (pool_ref
));
6711 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6712 INSN_CODE (insn
) = -1;
6717 /* Dump out all literal pools. */
6719 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6720 s390_dump_pool (curr_pool
, 0);
6722 /* Free pool list. */
6726 struct constant_pool
*next
= pool_list
->next
;
6727 s390_free_pool (pool_list
);
6732 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6733 We have decided we cannot use this list, so revert all changes
6734 to the current function that were done by s390_chunkify_start. */
6737 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6739 struct constant_pool
*curr_pool
= NULL
;
6742 /* Remove all pool placeholder insns. */
6744 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6746 /* Did we insert an extra barrier? Remove it. */
6747 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6748 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6749 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6751 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6752 && barrier
&& GET_CODE (barrier
) == BARRIER
6753 && label
&& GET_CODE (label
) == CODE_LABEL
6754 && GET_CODE (PATTERN (jump
)) == SET
6755 && SET_DEST (PATTERN (jump
)) == pc_rtx
6756 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6757 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6760 remove_insn (barrier
);
6761 remove_insn (label
);
6764 remove_insn (curr_pool
->pool_insn
);
6767 /* Remove all base register reload insns. */
6769 for (insn
= get_insns (); insn
; )
6771 rtx next_insn
= NEXT_INSN (insn
);
6773 if (GET_CODE (insn
) == INSN
6774 && GET_CODE (PATTERN (insn
)) == SET
6775 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6776 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6782 /* Free pool list. */
6786 struct constant_pool
*next
= pool_list
->next
;
6787 s390_free_pool (pool_list
);
6792 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6795 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6799 switch (GET_MODE_CLASS (mode
))
6802 case MODE_DECIMAL_FLOAT
:
6803 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6805 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6806 assemble_real (r
, mode
, align
);
6810 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6811 mark_symbol_refs_as_used (exp
);
6820 /* Return an RTL expression representing the value of the return address
6821 for the frame COUNT steps up from the current frame. FRAME is the
6822 frame pointer of that frame. */
6825 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
6830 /* Without backchain, we fail for all but the current frame. */
6832 if (!TARGET_BACKCHAIN
&& count
> 0)
6835 /* For the current frame, we need to make sure the initial
6836 value of RETURN_REGNUM is actually saved. */
6840 /* On non-z architectures branch splitting could overwrite r14. */
6841 if (TARGET_CPU_ZARCH
)
6842 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
6845 cfun_frame_layout
.save_return_addr_p
= true;
6846 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
6850 if (TARGET_PACKED_STACK
)
6851 offset
= -2 * UNITS_PER_LONG
;
6853 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
6855 addr
= plus_constant (frame
, offset
);
6856 addr
= memory_address (Pmode
, addr
);
6857 return gen_rtx_MEM (Pmode
, addr
);
6860 /* Return an RTL expression representing the back chain stored in
6861 the current stack frame. */
6864 s390_back_chain_rtx (void)
6868 gcc_assert (TARGET_BACKCHAIN
);
6870 if (TARGET_PACKED_STACK
)
6871 chain
= plus_constant (stack_pointer_rtx
,
6872 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
6874 chain
= stack_pointer_rtx
;
6876 chain
= gen_rtx_MEM (Pmode
, chain
);
6880 /* Find first call clobbered register unused in a function.
6881 This could be used as base register in a leaf function
6882 or for holding the return address before epilogue. */
6885 find_unused_clobbered_reg (void)
6888 for (i
= 0; i
< 6; i
++)
6889 if (!df_regs_ever_live_p (i
))
6895 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6896 clobbered hard regs in SETREG. */
6899 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
6901 int *regs_ever_clobbered
= (int *)data
;
6902 unsigned int i
, regno
;
6903 enum machine_mode mode
= GET_MODE (setreg
);
6905 if (GET_CODE (setreg
) == SUBREG
)
6907 rtx inner
= SUBREG_REG (setreg
);
6908 if (!GENERAL_REG_P (inner
))
6910 regno
= subreg_regno (setreg
);
6912 else if (GENERAL_REG_P (setreg
))
6913 regno
= REGNO (setreg
);
6918 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
6920 regs_ever_clobbered
[i
] = 1;
6923 /* Walks through all basic blocks of the current function looking
6924 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6925 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6926 each of those regs. */
6929 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
6935 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
6937 /* For non-leaf functions we have to consider all call clobbered regs to be
6939 if (!current_function_is_leaf
)
6941 for (i
= 0; i
< 16; i
++)
6942 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
6945 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6946 this work is done by liveness analysis (mark_regs_live_at_end).
6947 Special care is needed for functions containing landing pads. Landing pads
6948 may use the eh registers, but the code which sets these registers is not
6949 contained in that function. Hence s390_regs_ever_clobbered is not able to
6950 deal with this automatically. */
6951 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
6952 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
6953 if (crtl
->calls_eh_return
6954 || (cfun
->machine
->has_landing_pad_p
6955 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
6956 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
6958 /* For nonlocal gotos all call-saved registers have to be saved.
6959 This flag is also set for the unwinding code in libgcc.
6960 See expand_builtin_unwind_init. For regs_ever_live this is done by
6962 if (cfun
->has_nonlocal_label
)
6963 for (i
= 0; i
< 16; i
++)
6964 if (!call_really_used_regs
[i
])
6965 regs_ever_clobbered
[i
] = 1;
6967 FOR_EACH_BB (cur_bb
)
6969 FOR_BB_INSNS (cur_bb
, cur_insn
)
6971 if (INSN_P (cur_insn
))
6972 note_stores (PATTERN (cur_insn
),
6973 s390_reg_clobbered_rtx
,
6974 regs_ever_clobbered
);
6979 /* Determine the frame area which actually has to be accessed
6980 in the function epilogue. The values are stored at the
6981 given pointers AREA_BOTTOM (address of the lowest used stack
6982 address) and AREA_TOP (address of the first item which does
6983 not belong to the stack frame). */
6986 s390_frame_area (int *area_bottom
, int *area_top
)
6994 if (cfun_frame_layout
.first_restore_gpr
!= -1)
6996 b
= (cfun_frame_layout
.gprs_offset
6997 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
6998 t
= b
+ (cfun_frame_layout
.last_restore_gpr
6999 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7002 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7004 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7005 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7006 + cfun_frame_layout
.high_fprs
* 8));
7010 for (i
= 2; i
< 4; i
++)
7011 if (cfun_fpr_bit_p (i
))
7013 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7014 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7021 /* Fill cfun->machine with info about register usage of current function.
7022 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7025 s390_register_info (int clobbered_regs
[])
7029 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7030 cfun_frame_layout
.fpr_bitmap
= 0;
7031 cfun_frame_layout
.high_fprs
= 0;
7033 for (i
= 24; i
< 32; i
++)
7034 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7036 cfun_set_fpr_bit (i
- 16);
7037 cfun_frame_layout
.high_fprs
++;
7040 /* Find first and last gpr to be saved. We trust regs_ever_live
7041 data, except that we don't save and restore global registers.
7043 Also, all registers with special meaning to the compiler need
7044 to be handled extra. */
7046 s390_regs_ever_clobbered (clobbered_regs
);
7048 for (i
= 0; i
< 16; i
++)
7049 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7051 if (frame_pointer_needed
)
7052 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7055 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7056 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7058 clobbered_regs
[BASE_REGNUM
]
7059 |= (cfun
->machine
->base_reg
7060 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7062 clobbered_regs
[RETURN_REGNUM
]
7063 |= (!current_function_is_leaf
7064 || TARGET_TPF_PROFILING
7065 || cfun
->machine
->split_branches_pending_p
7066 || cfun_frame_layout
.save_return_addr_p
7067 || crtl
->calls_eh_return
7070 clobbered_regs
[STACK_POINTER_REGNUM
]
7071 |= (!current_function_is_leaf
7072 || TARGET_TPF_PROFILING
7073 || cfun_save_high_fprs_p
7074 || get_frame_size () > 0
7075 || cfun
->calls_alloca
7078 for (i
= 6; i
< 16; i
++)
7079 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7081 for (j
= 15; j
> i
; j
--)
7082 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7087 /* Nothing to save/restore. */
7088 cfun_frame_layout
.first_save_gpr_slot
= -1;
7089 cfun_frame_layout
.last_save_gpr_slot
= -1;
7090 cfun_frame_layout
.first_save_gpr
= -1;
7091 cfun_frame_layout
.first_restore_gpr
= -1;
7092 cfun_frame_layout
.last_save_gpr
= -1;
7093 cfun_frame_layout
.last_restore_gpr
= -1;
7097 /* Save slots for gprs from i to j. */
7098 cfun_frame_layout
.first_save_gpr_slot
= i
;
7099 cfun_frame_layout
.last_save_gpr_slot
= j
;
7101 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7102 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7104 if (clobbered_regs
[i
])
7107 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7108 if (clobbered_regs
[j
])
7111 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7113 /* Nothing to save/restore. */
7114 cfun_frame_layout
.first_save_gpr
= -1;
7115 cfun_frame_layout
.first_restore_gpr
= -1;
7116 cfun_frame_layout
.last_save_gpr
= -1;
7117 cfun_frame_layout
.last_restore_gpr
= -1;
7121 /* Save / Restore from gpr i to j. */
7122 cfun_frame_layout
.first_save_gpr
= i
;
7123 cfun_frame_layout
.first_restore_gpr
= i
;
7124 cfun_frame_layout
.last_save_gpr
= j
;
7125 cfun_frame_layout
.last_restore_gpr
= j
;
7131 /* Varargs functions need to save gprs 2 to 6. */
7132 if (cfun
->va_list_gpr_size
7133 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7135 int min_gpr
= crtl
->args
.info
.gprs
;
7136 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7137 if (max_gpr
> GP_ARG_NUM_REG
)
7138 max_gpr
= GP_ARG_NUM_REG
;
7140 if (cfun_frame_layout
.first_save_gpr
== -1
7141 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7143 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7144 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7147 if (cfun_frame_layout
.last_save_gpr
== -1
7148 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7150 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7151 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7155 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7156 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7157 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7159 int min_fpr
= crtl
->args
.info
.fprs
;
7160 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7161 if (max_fpr
> FP_ARG_NUM_REG
)
7162 max_fpr
= FP_ARG_NUM_REG
;
7164 /* ??? This is currently required to ensure proper location
7165 of the fpr save slots within the va_list save area. */
7166 if (TARGET_PACKED_STACK
)
7169 for (i
= min_fpr
; i
< max_fpr
; i
++)
7170 cfun_set_fpr_bit (i
);
7175 for (i
= 2; i
< 4; i
++)
7176 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7177 cfun_set_fpr_bit (i
);
7180 /* Fill cfun->machine with info about frame of current function. */
7183 s390_frame_info (void)
7187 cfun_frame_layout
.frame_size
= get_frame_size ();
7188 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7189 fatal_error ("total size of local variables exceeds architecture limit");
7191 if (!TARGET_PACKED_STACK
)
7193 cfun_frame_layout
.backchain_offset
= 0;
7194 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7195 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7196 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7197 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7200 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7202 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7204 cfun_frame_layout
.gprs_offset
7205 = (cfun_frame_layout
.backchain_offset
7206 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7211 cfun_frame_layout
.f4_offset
7212 = (cfun_frame_layout
.gprs_offset
7213 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7215 cfun_frame_layout
.f0_offset
7216 = (cfun_frame_layout
.f4_offset
7217 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7221 /* On 31 bit we have to care about alignment of the
7222 floating point regs to provide fastest access. */
7223 cfun_frame_layout
.f0_offset
7224 = ((cfun_frame_layout
.gprs_offset
7225 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7226 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7228 cfun_frame_layout
.f4_offset
7229 = (cfun_frame_layout
.f0_offset
7230 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7233 else /* no backchain */
7235 cfun_frame_layout
.f4_offset
7236 = (STACK_POINTER_OFFSET
7237 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7239 cfun_frame_layout
.f0_offset
7240 = (cfun_frame_layout
.f4_offset
7241 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7243 cfun_frame_layout
.gprs_offset
7244 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7247 if (current_function_is_leaf
7248 && !TARGET_TPF_PROFILING
7249 && cfun_frame_layout
.frame_size
== 0
7250 && !cfun_save_high_fprs_p
7251 && !cfun
->calls_alloca
7255 if (!TARGET_PACKED_STACK
)
7256 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7257 + crtl
->outgoing_args_size
7258 + cfun_frame_layout
.high_fprs
* 8);
7261 if (TARGET_BACKCHAIN
)
7262 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7264 /* No alignment trouble here because f8-f15 are only saved under
7266 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7267 cfun_frame_layout
.f4_offset
),
7268 cfun_frame_layout
.gprs_offset
)
7269 - cfun_frame_layout
.high_fprs
* 8);
7271 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7273 for (i
= 0; i
< 8; i
++)
7274 if (cfun_fpr_bit_p (i
))
7275 cfun_frame_layout
.frame_size
+= 8;
7277 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7279 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7280 the frame size to sustain 8 byte alignment of stack frames. */
7281 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7282 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7283 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7285 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7289 /* Generate frame layout. Fills in register and frame data for the current
7290 function in cfun->machine. This routine can be called multiple times;
7291 it will re-do the complete frame layout every time. */
7294 s390_init_frame_layout (void)
7296 HOST_WIDE_INT frame_size
;
7298 int clobbered_regs
[16];
7300 /* On S/390 machines, we may need to perform branch splitting, which
7301 will require both base and return address register. We have no
7302 choice but to assume we're going to need them until right at the
7303 end of the machine dependent reorg phase. */
7304 if (!TARGET_CPU_ZARCH
)
7305 cfun
->machine
->split_branches_pending_p
= true;
7309 frame_size
= cfun_frame_layout
.frame_size
;
7311 /* Try to predict whether we'll need the base register. */
7312 base_used
= cfun
->machine
->split_branches_pending_p
7313 || crtl
->uses_const_pool
7314 || (!DISP_IN_RANGE (frame_size
)
7315 && !CONST_OK_FOR_K (frame_size
));
7317 /* Decide which register to use as literal pool base. In small
7318 leaf functions, try to use an unused call-clobbered register
7319 as base register to avoid save/restore overhead. */
7321 cfun
->machine
->base_reg
= NULL_RTX
;
7322 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7323 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7325 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7327 s390_register_info (clobbered_regs
);
7330 while (frame_size
!= cfun_frame_layout
.frame_size
);
7333 /* Update frame layout. Recompute actual register save data based on
7334 current info and update regs_ever_live for the special registers.
7335 May be called multiple times, but may never cause *more* registers
7336 to be saved than s390_init_frame_layout allocated room for. */
7339 s390_update_frame_layout (void)
7341 int clobbered_regs
[16];
7343 s390_register_info (clobbered_regs
);
7345 df_set_regs_ever_live (BASE_REGNUM
,
7346 clobbered_regs
[BASE_REGNUM
] ? true : false);
7347 df_set_regs_ever_live (RETURN_REGNUM
,
7348 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7349 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7350 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7352 if (cfun
->machine
->base_reg
)
7353 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7356 /* Return true if it is legal to put a value with MODE into REGNO. */
7359 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7361 switch (REGNO_REG_CLASS (regno
))
7364 if (REGNO_PAIR_OK (regno
, mode
))
7366 if (mode
== SImode
|| mode
== DImode
)
7369 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7374 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7379 if (REGNO_PAIR_OK (regno
, mode
))
7382 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7387 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7391 if (REGNO_PAIR_OK (regno
, mode
))
7393 if (mode
== SImode
|| mode
== Pmode
)
7404 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7407 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7409 /* Once we've decided upon a register to use as base register, it must
7410 no longer be used for any other purpose. */
7411 if (cfun
->machine
->base_reg
)
7412 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7413 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7419 /* Maximum number of registers to represent a value of mode MODE
7420 in a register of class RCLASS. */
7423 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7428 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7429 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7431 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7433 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7437 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7440 /* Return true if register FROM can be eliminated via register TO. */
7443 s390_can_eliminate (const int from
, const int to
)
7445 /* On zSeries machines, we have not marked the base register as fixed.
7446 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7447 If a function requires the base register, we say here that this
7448 elimination cannot be performed. This will cause reload to free
7449 up the base register (as if it were fixed). On the other hand,
7450 if the current function does *not* require the base register, we
7451 say here the elimination succeeds, which in turn allows reload
7452 to allocate the base register for any other purpose. */
7453 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7455 if (TARGET_CPU_ZARCH
)
7457 s390_init_frame_layout ();
7458 return cfun
->machine
->base_reg
== NULL_RTX
;
7464 /* Everything else must point into the stack frame. */
7465 gcc_assert (to
== STACK_POINTER_REGNUM
7466 || to
== HARD_FRAME_POINTER_REGNUM
);
7468 gcc_assert (from
== FRAME_POINTER_REGNUM
7469 || from
== ARG_POINTER_REGNUM
7470 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7472 /* Make sure we actually saved the return address. */
7473 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7474 if (!crtl
->calls_eh_return
7476 && !cfun_frame_layout
.save_return_addr_p
)
7482 /* Return offset between register FROM and TO initially after prolog. */
7485 s390_initial_elimination_offset (int from
, int to
)
7487 HOST_WIDE_INT offset
;
7490 /* ??? Why are we called for non-eliminable pairs? */
7491 if (!s390_can_eliminate (from
, to
))
7496 case FRAME_POINTER_REGNUM
:
7497 offset
= (get_frame_size()
7498 + STACK_POINTER_OFFSET
7499 + crtl
->outgoing_args_size
);
7502 case ARG_POINTER_REGNUM
:
7503 s390_init_frame_layout ();
7504 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7507 case RETURN_ADDRESS_POINTER_REGNUM
:
7508 s390_init_frame_layout ();
7509 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7510 gcc_assert (index
>= 0);
7511 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7512 offset
+= index
* UNITS_PER_LONG
;
7526 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7527 to register BASE. Return generated insn. */
7530 save_fpr (rtx base
, int offset
, int regnum
)
7533 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7535 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7536 set_mem_alias_set (addr
, get_varargs_alias_set ());
7538 set_mem_alias_set (addr
, get_frame_alias_set ());
7540 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7543 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7544 to register BASE. Return generated insn. */
7547 restore_fpr (rtx base
, int offset
, int regnum
)
7550 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7551 set_mem_alias_set (addr
, get_frame_alias_set ());
7553 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7556 /* Return true if REGNO is a global register, but not one
7557 of the special ones that need to be saved/restored in anyway. */
7560 global_not_special_regno_p (int regno
)
7562 return (global_regs
[regno
]
7563 /* These registers are special and need to be
7564 restored in any case. */
7565 && !(regno
== STACK_POINTER_REGNUM
7566 || regno
== RETURN_REGNUM
7567 || regno
== BASE_REGNUM
7568 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7571 /* Generate insn to save registers FIRST to LAST into
7572 the register save area located at offset OFFSET
7573 relative to register BASE. */
7576 save_gprs (rtx base
, int offset
, int first
, int last
)
7578 rtx addr
, insn
, note
;
7581 addr
= plus_constant (base
, offset
);
7582 addr
= gen_rtx_MEM (Pmode
, addr
);
7584 set_mem_alias_set (addr
, get_frame_alias_set ());
7586 /* Special-case single register. */
7590 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7592 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7594 if (!global_not_special_regno_p (first
))
7595 RTX_FRAME_RELATED_P (insn
) = 1;
7600 insn
= gen_store_multiple (addr
,
7601 gen_rtx_REG (Pmode
, first
),
7602 GEN_INT (last
- first
+ 1));
7604 if (first
<= 6 && cfun
->stdarg
)
7605 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7607 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7610 set_mem_alias_set (mem
, get_varargs_alias_set ());
7613 /* We need to set the FRAME_RELATED flag on all SETs
7614 inside the store-multiple pattern.
7616 However, we must not emit DWARF records for registers 2..5
7617 if they are stored for use by variable arguments ...
7619 ??? Unfortunately, it is not enough to simply not the
7620 FRAME_RELATED flags for those SETs, because the first SET
7621 of the PARALLEL is always treated as if it had the flag
7622 set, even if it does not. Therefore we emit a new pattern
7623 without those registers as REG_FRAME_RELATED_EXPR note. */
7625 if (first
>= 6 && !global_not_special_regno_p (first
))
7627 rtx pat
= PATTERN (insn
);
7629 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7630 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
7631 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
7633 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7635 RTX_FRAME_RELATED_P (insn
) = 1;
7641 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
7642 if (!global_not_special_regno_p (start
))
7648 addr
= plus_constant (base
, offset
+ (start
- first
) * UNITS_PER_LONG
);
7649 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7650 gen_rtx_REG (Pmode
, start
),
7651 GEN_INT (last
- start
+ 1));
7652 note
= PATTERN (note
);
7654 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7656 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7657 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
7658 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
7660 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7662 RTX_FRAME_RELATED_P (insn
) = 1;
7668 /* Generate insn to restore registers FIRST to LAST from
7669 the register save area located at offset OFFSET
7670 relative to register BASE. */
7673 restore_gprs (rtx base
, int offset
, int first
, int last
)
7677 addr
= plus_constant (base
, offset
);
7678 addr
= gen_rtx_MEM (Pmode
, addr
);
7679 set_mem_alias_set (addr
, get_frame_alias_set ());
7681 /* Special-case single register. */
7685 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7687 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7692 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7694 GEN_INT (last
- first
+ 1));
7698 /* Return insn sequence to load the GOT register. */
7700 static GTY(()) rtx got_symbol
;
7702 s390_load_got (void)
7708 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7709 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7714 if (TARGET_CPU_ZARCH
)
7716 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7722 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7723 UNSPEC_LTREL_OFFSET
);
7724 offset
= gen_rtx_CONST (Pmode
, offset
);
7725 offset
= force_const_mem (Pmode
, offset
);
7727 emit_move_insn (pic_offset_table_rtx
, offset
);
7729 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7731 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7733 emit_move_insn (pic_offset_table_rtx
, offset
);
7736 insns
= get_insns ();
7741 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7742 and the change to the stack pointer. */
7745 s390_emit_stack_tie (void)
7747 rtx mem
= gen_frame_mem (BLKmode
,
7748 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
7750 emit_insn (gen_stack_tie (mem
));
7753 /* Expand the prologue into a bunch of separate insns. */
7756 s390_emit_prologue (void)
7764 /* Complete frame layout. */
7766 s390_update_frame_layout ();
7768 /* Annotate all constant pool references to let the scheduler know
7769 they implicitly use the base register. */
7771 push_topmost_sequence ();
7773 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7776 annotate_constant_pool_refs (&PATTERN (insn
));
7777 df_insn_rescan (insn
);
7780 pop_topmost_sequence ();
7782 /* Choose best register to use for temp use within prologue.
7783 See below for why TPF must use the register 1. */
7785 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7786 && !current_function_is_leaf
7787 && !TARGET_TPF_PROFILING
)
7788 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7790 temp_reg
= gen_rtx_REG (Pmode
, 1);
7792 /* Save call saved gprs. */
7793 if (cfun_frame_layout
.first_save_gpr
!= -1)
7795 insn
= save_gprs (stack_pointer_rtx
,
7796 cfun_frame_layout
.gprs_offset
+
7797 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
7798 - cfun_frame_layout
.first_save_gpr_slot
),
7799 cfun_frame_layout
.first_save_gpr
,
7800 cfun_frame_layout
.last_save_gpr
);
7804 /* Dummy insn to mark literal pool slot. */
7806 if (cfun
->machine
->base_reg
)
7807 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
7809 offset
= cfun_frame_layout
.f0_offset
;
7811 /* Save f0 and f2. */
7812 for (i
= 0; i
< 2; i
++)
7814 if (cfun_fpr_bit_p (i
))
7816 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7819 else if (!TARGET_PACKED_STACK
)
7823 /* Save f4 and f6. */
7824 offset
= cfun_frame_layout
.f4_offset
;
7825 for (i
= 2; i
< 4; i
++)
7827 if (cfun_fpr_bit_p (i
))
7829 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7832 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7833 therefore are not frame related. */
7834 if (!call_really_used_regs
[i
+ 16])
7835 RTX_FRAME_RELATED_P (insn
) = 1;
7837 else if (!TARGET_PACKED_STACK
)
7841 if (TARGET_PACKED_STACK
7842 && cfun_save_high_fprs_p
7843 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
7845 offset
= (cfun_frame_layout
.f8_offset
7846 + (cfun_frame_layout
.high_fprs
- 1) * 8);
7848 for (i
= 15; i
> 7 && offset
>= 0; i
--)
7849 if (cfun_fpr_bit_p (i
))
7851 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7853 RTX_FRAME_RELATED_P (insn
) = 1;
7856 if (offset
>= cfun_frame_layout
.f8_offset
)
7860 if (!TARGET_PACKED_STACK
)
7861 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
7863 /* Decrement stack pointer. */
7865 if (cfun_frame_layout
.frame_size
> 0)
7867 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7870 if (s390_stack_size
)
7872 HOST_WIDE_INT stack_guard
;
7874 if (s390_stack_guard
)
7875 stack_guard
= s390_stack_guard
;
7878 /* If no value for stack guard is provided the smallest power of 2
7879 larger than the current frame size is chosen. */
7881 while (stack_guard
< cfun_frame_layout
.frame_size
)
7885 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
7887 warning (0, "frame size of function %qs is "
7888 HOST_WIDE_INT_PRINT_DEC
7889 " bytes exceeding user provided stack limit of "
7890 HOST_WIDE_INT_PRINT_DEC
" bytes. "
7891 "An unconditional trap is added.",
7892 current_function_name(), cfun_frame_layout
.frame_size
,
7894 emit_insn (gen_trap ());
7898 /* stack_guard has to be smaller than s390_stack_size.
7899 Otherwise we would emit an AND with zero which would
7900 not match the test under mask pattern. */
7901 if (stack_guard
>= s390_stack_size
)
7903 warning (0, "frame size of function %qs is "
7904 HOST_WIDE_INT_PRINT_DEC
7905 " bytes which is more than half the stack size. "
7906 "The dynamic check would not be reliable. "
7907 "No check emitted for this function.",
7908 current_function_name(),
7909 cfun_frame_layout
.frame_size
);
7913 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
7914 & ~(stack_guard
- 1));
7916 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
7917 GEN_INT (stack_check_mask
));
7919 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
7921 t
, const0_rtx
, const0_rtx
));
7923 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
7925 t
, const0_rtx
, const0_rtx
));
7930 if (s390_warn_framesize
> 0
7931 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
7932 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC
" bytes",
7933 current_function_name (), cfun_frame_layout
.frame_size
);
7935 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
7936 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7938 /* Save incoming stack pointer into temp reg. */
7939 if (TARGET_BACKCHAIN
|| next_fpr
)
7940 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
7942 /* Subtract frame size from stack pointer. */
7944 if (DISP_IN_RANGE (INTVAL (frame_off
)))
7946 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7947 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7949 insn
= emit_insn (insn
);
7953 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
7954 frame_off
= force_const_mem (Pmode
, frame_off
);
7956 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
7957 annotate_constant_pool_refs (&PATTERN (insn
));
7960 RTX_FRAME_RELATED_P (insn
) = 1;
7961 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7962 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
7963 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7964 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7967 /* Set backchain. */
7969 if (TARGET_BACKCHAIN
)
7971 if (cfun_frame_layout
.backchain_offset
)
7972 addr
= gen_rtx_MEM (Pmode
,
7973 plus_constant (stack_pointer_rtx
,
7974 cfun_frame_layout
.backchain_offset
));
7976 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
7977 set_mem_alias_set (addr
, get_frame_alias_set ());
7978 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
7981 /* If we support non-call exceptions (e.g. for Java),
7982 we need to make sure the backchain pointer is set up
7983 before any possibly trapping memory access. */
7984 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
7986 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
7987 emit_clobber (addr
);
7991 /* Save fprs 8 - 15 (64 bit ABI). */
7993 if (cfun_save_high_fprs_p
&& next_fpr
)
7995 /* If the stack might be accessed through a different register
7996 we have to make sure that the stack pointer decrement is not
7997 moved below the use of the stack slots. */
7998 s390_emit_stack_tie ();
8000 insn
= emit_insn (gen_add2_insn (temp_reg
,
8001 GEN_INT (cfun_frame_layout
.f8_offset
)));
8005 for (i
= 24; i
<= next_fpr
; i
++)
8006 if (cfun_fpr_bit_p (i
- 16))
8008 rtx addr
= plus_constant (stack_pointer_rtx
,
8009 cfun_frame_layout
.frame_size
8010 + cfun_frame_layout
.f8_offset
8013 insn
= save_fpr (temp_reg
, offset
, i
);
8015 RTX_FRAME_RELATED_P (insn
) = 1;
8016 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8017 gen_rtx_SET (VOIDmode
,
8018 gen_rtx_MEM (DFmode
, addr
),
8019 gen_rtx_REG (DFmode
, i
)));
8023 /* Set frame pointer, if needed. */
8025 if (frame_pointer_needed
)
8027 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8028 RTX_FRAME_RELATED_P (insn
) = 1;
8031 /* Set up got pointer, if needed. */
8033 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8035 rtx insns
= s390_load_got ();
8037 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8038 annotate_constant_pool_refs (&PATTERN (insn
));
8043 if (TARGET_TPF_PROFILING
)
8045 /* Generate a BAS instruction to serve as a function
8046 entry intercept to facilitate the use of tracing
8047 algorithms located at the branch target. */
8048 emit_insn (gen_prologue_tpf ());
8050 /* Emit a blockage here so that all code
8051 lies between the profiling mechanisms. */
8052 emit_insn (gen_blockage ());
8056 /* Expand the epilogue into a bunch of separate insns. */
8059 s390_emit_epilogue (bool sibcall
)
8061 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8062 int area_bottom
, area_top
, offset
= 0;
8067 if (TARGET_TPF_PROFILING
)
8070 /* Generate a BAS instruction to serve as a function
8071 entry intercept to facilitate the use of tracing
8072 algorithms located at the branch target. */
8074 /* Emit a blockage here so that all code
8075 lies between the profiling mechanisms. */
8076 emit_insn (gen_blockage ());
8078 emit_insn (gen_epilogue_tpf ());
8081 /* Check whether to use frame or stack pointer for restore. */
8083 frame_pointer
= (frame_pointer_needed
8084 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8086 s390_frame_area (&area_bottom
, &area_top
);
8088 /* Check whether we can access the register save area.
8089 If not, increment the frame pointer as required. */
8091 if (area_top
<= area_bottom
)
8093 /* Nothing to restore. */
8095 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8096 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8098 /* Area is in range. */
8099 offset
= cfun_frame_layout
.frame_size
;
8103 rtx insn
, frame_off
, cfa
;
8105 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8106 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8108 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8109 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8110 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8112 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8113 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8114 insn
= emit_insn (insn
);
8118 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8119 frame_off
= force_const_mem (Pmode
, frame_off
);
8121 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8122 annotate_constant_pool_refs (&PATTERN (insn
));
8124 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8125 RTX_FRAME_RELATED_P (insn
) = 1;
8128 /* Restore call saved fprs. */
8132 if (cfun_save_high_fprs_p
)
8134 next_offset
= cfun_frame_layout
.f8_offset
;
8135 for (i
= 24; i
< 32; i
++)
8137 if (cfun_fpr_bit_p (i
- 16))
8139 restore_fpr (frame_pointer
,
8140 offset
+ next_offset
, i
);
8142 = alloc_reg_note (REG_CFA_RESTORE
,
8143 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8152 next_offset
= cfun_frame_layout
.f4_offset
;
8153 for (i
= 18; i
< 20; i
++)
8155 if (cfun_fpr_bit_p (i
- 16))
8157 restore_fpr (frame_pointer
,
8158 offset
+ next_offset
, i
);
8160 = alloc_reg_note (REG_CFA_RESTORE
,
8161 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8164 else if (!TARGET_PACKED_STACK
)
8170 /* Return register. */
8172 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8174 /* Restore call saved gprs. */
8176 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8181 /* Check for global register and save them
8182 to stack location from where they get restored. */
8184 for (i
= cfun_frame_layout
.first_restore_gpr
;
8185 i
<= cfun_frame_layout
.last_restore_gpr
;
8188 if (global_not_special_regno_p (i
))
8190 addr
= plus_constant (frame_pointer
,
8191 offset
+ cfun_frame_layout
.gprs_offset
8192 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8194 addr
= gen_rtx_MEM (Pmode
, addr
);
8195 set_mem_alias_set (addr
, get_frame_alias_set ());
8196 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8200 = alloc_reg_note (REG_CFA_RESTORE
,
8201 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8206 /* Fetch return address from stack before load multiple,
8207 this will do good for scheduling. */
8209 if (cfun_frame_layout
.save_return_addr_p
8210 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8211 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8213 int return_regnum
= find_unused_clobbered_reg();
8216 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8218 addr
= plus_constant (frame_pointer
,
8219 offset
+ cfun_frame_layout
.gprs_offset
8221 - cfun_frame_layout
.first_save_gpr_slot
)
8223 addr
= gen_rtx_MEM (Pmode
, addr
);
8224 set_mem_alias_set (addr
, get_frame_alias_set ());
8225 emit_move_insn (return_reg
, addr
);
8229 insn
= restore_gprs (frame_pointer
,
8230 offset
+ cfun_frame_layout
.gprs_offset
8231 + (cfun_frame_layout
.first_restore_gpr
8232 - cfun_frame_layout
.first_save_gpr_slot
)
8234 cfun_frame_layout
.first_restore_gpr
,
8235 cfun_frame_layout
.last_restore_gpr
);
8236 insn
= emit_insn (insn
);
8237 REG_NOTES (insn
) = cfa_restores
;
8238 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8239 plus_constant (stack_pointer_rtx
, STACK_POINTER_OFFSET
));
8240 RTX_FRAME_RELATED_P (insn
) = 1;
8246 /* Return to caller. */
8248 p
= rtvec_alloc (2);
8250 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
8251 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8252 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8257 /* Return the size in bytes of a function argument of
8258 type TYPE and/or mode MODE. At least one of TYPE or
8259 MODE must be specified. */
8262 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8265 return int_size_in_bytes (type
);
8267 /* No type info available for some library calls ... */
8268 if (mode
!= BLKmode
)
8269 return GET_MODE_SIZE (mode
);
8271 /* If we have neither type nor mode, abort */
8275 /* Return true if a function argument of type TYPE and mode MODE
8276 is to be passed in a floating-point register, if available. */
8279 s390_function_arg_float (enum machine_mode mode
, tree type
)
8281 int size
= s390_function_arg_size (mode
, type
);
8285 /* Soft-float changes the ABI: no floating-point registers are used. */
8286 if (TARGET_SOFT_FLOAT
)
8289 /* No type info available for some library calls ... */
8291 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8293 /* The ABI says that record types with a single member are treated
8294 just like that member would be. */
8295 while (TREE_CODE (type
) == RECORD_TYPE
)
8297 tree field
, single
= NULL_TREE
;
8299 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8301 if (TREE_CODE (field
) != FIELD_DECL
)
8304 if (single
== NULL_TREE
)
8305 single
= TREE_TYPE (field
);
8310 if (single
== NULL_TREE
)
8316 return TREE_CODE (type
) == REAL_TYPE
;
8319 /* Return true if a function argument of type TYPE and mode MODE
8320 is to be passed in an integer register, or a pair of integer
8321 registers, if available. */
8324 s390_function_arg_integer (enum machine_mode mode
, tree type
)
8326 int size
= s390_function_arg_size (mode
, type
);
8330 /* No type info available for some library calls ... */
8332 return GET_MODE_CLASS (mode
) == MODE_INT
8333 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8335 /* We accept small integral (and similar) types. */
8336 if (INTEGRAL_TYPE_P (type
)
8337 || POINTER_TYPE_P (type
)
8338 || TREE_CODE (type
) == OFFSET_TYPE
8339 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8342 /* We also accept structs of size 1, 2, 4, 8 that are not
8343 passed in floating-point registers. */
8344 if (AGGREGATE_TYPE_P (type
)
8345 && exact_log2 (size
) >= 0
8346 && !s390_function_arg_float (mode
, type
))
8352 /* Return 1 if a function argument of type TYPE and mode MODE
8353 is to be passed by reference. The ABI specifies that only
8354 structures of size 1, 2, 4, or 8 bytes are passed by value,
8355 all other structures (and complex numbers) are passed by
8359 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
8360 enum machine_mode mode
, const_tree type
,
8361 bool named ATTRIBUTE_UNUSED
)
8363 int size
= s390_function_arg_size (mode
, type
);
8369 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8372 if (TREE_CODE (type
) == COMPLEX_TYPE
8373 || TREE_CODE (type
) == VECTOR_TYPE
)
8380 /* Update the data in CUM to advance over an argument of mode MODE and
8381 data type TYPE. (TYPE is null for libcalls where that information
8382 may not be available.). The boolean NAMED specifies whether the
8383 argument is a named argument (as opposed to an unnamed argument
8384 matching an ellipsis). */
8387 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8388 tree type
, int named ATTRIBUTE_UNUSED
)
8390 if (s390_function_arg_float (mode
, type
))
8394 else if (s390_function_arg_integer (mode
, type
))
8396 int size
= s390_function_arg_size (mode
, type
);
8397 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8403 /* Define where to put the arguments to a function.
8404 Value is zero to push the argument on the stack,
8405 or a hard register in which to store the argument.
8407 MODE is the argument's machine mode.
8408 TYPE is the data type of the argument (as a tree).
8409 This is null for libcalls where that information may
8411 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8412 the preceding args and about the function being called.
8413 NAMED is nonzero if this argument is a named parameter
8414 (otherwise it is an extra parameter matching an ellipsis).
8416 On S/390, we use general purpose registers 2 through 6 to
8417 pass integer, pointer, and certain structure arguments, and
8418 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8419 to pass floating point arguments. All remaining arguments
8420 are pushed to the stack. */
8423 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
8424 int named ATTRIBUTE_UNUSED
)
8426 if (s390_function_arg_float (mode
, type
))
8428 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8431 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8433 else if (s390_function_arg_integer (mode
, type
))
8435 int size
= s390_function_arg_size (mode
, type
);
8436 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8438 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8440 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8441 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8442 else if (n_gprs
== 2)
8444 rtvec p
= rtvec_alloc (2);
8447 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8450 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8453 return gen_rtx_PARALLEL (mode
, p
);
8457 /* After the real arguments, expand_call calls us once again
8458 with a void_type_node type. Whatever we return here is
8459 passed as operand 2 to the call expanders.
8461 We don't need this feature ... */
8462 else if (type
== void_type_node
)
8468 /* Return true if return values of type TYPE should be returned
8469 in a memory buffer whose address is passed by the caller as
8470 hidden first argument. */
8473 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8475 /* We accept small integral (and similar) types. */
8476 if (INTEGRAL_TYPE_P (type
)
8477 || POINTER_TYPE_P (type
)
8478 || TREE_CODE (type
) == OFFSET_TYPE
8479 || TREE_CODE (type
) == REAL_TYPE
)
8480 return int_size_in_bytes (type
) > 8;
8482 /* Aggregates and similar constructs are always returned
8484 if (AGGREGATE_TYPE_P (type
)
8485 || TREE_CODE (type
) == COMPLEX_TYPE
8486 || TREE_CODE (type
) == VECTOR_TYPE
)
8489 /* ??? We get called on all sorts of random stuff from
8490 aggregate_value_p. We can't abort, but it's not clear
8491 what's safe to return. Pretend it's a struct I guess. */
8495 /* Function arguments and return values are promoted to word size. */
8497 static enum machine_mode
8498 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8500 const_tree fntype ATTRIBUTE_UNUSED
,
8501 int for_return ATTRIBUTE_UNUSED
)
8503 if (INTEGRAL_MODE_P (mode
)
8504 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8506 if (POINTER_TYPE_P (type
))
8507 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8514 /* Define where to return a (scalar) value of type TYPE.
8515 If TYPE is null, define where to return a (scalar)
8516 value of mode MODE from a libcall. */
8519 s390_function_value (const_tree type
, const_tree fn
, enum machine_mode mode
)
8523 int unsignedp
= TYPE_UNSIGNED (type
);
8524 mode
= promote_function_mode (type
, TYPE_MODE (type
), &unsignedp
, fn
, 1);
8527 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8528 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8530 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8531 return gen_rtx_REG (mode
, 16);
8532 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8533 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8534 return gen_rtx_REG (mode
, 2);
8535 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8537 rtvec p
= rtvec_alloc (2);
8540 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8542 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8544 return gen_rtx_PARALLEL (mode
, p
);
8551 /* Create and return the va_list datatype.
8553 On S/390, va_list is an array type equivalent to
8555 typedef struct __va_list_tag
8559 void *__overflow_arg_area;
8560 void *__reg_save_area;
8563 where __gpr and __fpr hold the number of general purpose
8564 or floating point arguments used up to now, respectively,
8565 __overflow_arg_area points to the stack location of the
8566 next argument passed on the stack, and __reg_save_area
8567 always points to the start of the register area in the
8568 call frame of the current function. The function prologue
8569 saves all registers used for argument passing into this
8570 area if the function uses variable arguments. */
8573 s390_build_builtin_va_list (void)
8575 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8577 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8580 build_decl (BUILTINS_LOCATION
,
8581 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8583 f_gpr
= build_decl (BUILTINS_LOCATION
,
8584 FIELD_DECL
, get_identifier ("__gpr"),
8585 long_integer_type_node
);
8586 f_fpr
= build_decl (BUILTINS_LOCATION
,
8587 FIELD_DECL
, get_identifier ("__fpr"),
8588 long_integer_type_node
);
8589 f_ovf
= build_decl (BUILTINS_LOCATION
,
8590 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8592 f_sav
= build_decl (BUILTINS_LOCATION
,
8593 FIELD_DECL
, get_identifier ("__reg_save_area"),
8596 va_list_gpr_counter_field
= f_gpr
;
8597 va_list_fpr_counter_field
= f_fpr
;
8599 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8600 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8601 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8602 DECL_FIELD_CONTEXT (f_sav
) = record
;
8604 TREE_CHAIN (record
) = type_decl
;
8605 TYPE_NAME (record
) = type_decl
;
8606 TYPE_FIELDS (record
) = f_gpr
;
8607 DECL_CHAIN (f_gpr
) = f_fpr
;
8608 DECL_CHAIN (f_fpr
) = f_ovf
;
8609 DECL_CHAIN (f_ovf
) = f_sav
;
8611 layout_type (record
);
8613 /* The correct type is an array type of one element. */
8614 return build_array_type (record
, build_index_type (size_zero_node
));
8617 /* Implement va_start by filling the va_list structure VALIST.
8618 STDARG_P is always true, and ignored.
8619 NEXTARG points to the first anonymous stack argument.
8621 The following global variables are used to initialize
8622 the va_list structure:
8625 holds number of gprs and fprs used for named arguments.
8626 crtl->args.arg_offset_rtx:
8627 holds the offset of the first anonymous stack argument
8628 (relative to the virtual arg pointer). */
8631 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8633 HOST_WIDE_INT n_gpr
, n_fpr
;
8635 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8636 tree gpr
, fpr
, ovf
, sav
, t
;
8638 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8639 f_fpr
= DECL_CHAIN (f_gpr
);
8640 f_ovf
= DECL_CHAIN (f_fpr
);
8641 f_sav
= DECL_CHAIN (f_ovf
);
8643 valist
= build_va_arg_indirect_ref (valist
);
8644 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8645 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8646 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8647 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8649 /* Count number of gp and fp argument registers used. */
8651 n_gpr
= crtl
->args
.info
.gprs
;
8652 n_fpr
= crtl
->args
.info
.fprs
;
8654 if (cfun
->va_list_gpr_size
)
8656 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8657 build_int_cst (NULL_TREE
, n_gpr
));
8658 TREE_SIDE_EFFECTS (t
) = 1;
8659 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8662 if (cfun
->va_list_fpr_size
)
8664 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8665 build_int_cst (NULL_TREE
, n_fpr
));
8666 TREE_SIDE_EFFECTS (t
) = 1;
8667 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8670 /* Find the overflow area. */
8671 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8672 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8674 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8676 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8677 off
= off
< 0 ? 0 : off
;
8678 if (TARGET_DEBUG_ARG
)
8679 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8680 (int)n_gpr
, (int)n_fpr
, off
);
8682 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
, size_int (off
));
8684 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8685 TREE_SIDE_EFFECTS (t
) = 1;
8686 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8689 /* Find the register save area. */
8690 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8691 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8693 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8694 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
8695 size_int (-RETURN_REGNUM
* UNITS_PER_LONG
));
8697 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
8698 TREE_SIDE_EFFECTS (t
) = 1;
8699 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8703 /* Implement va_arg by updating the va_list structure
8704 VALIST as required to retrieve an argument of type
8705 TYPE, and returning that argument.
8707 Generates code equivalent to:
8709 if (integral value) {
8710 if (size <= 4 && args.gpr < 5 ||
8711 size > 4 && args.gpr < 4 )
8712 ret = args.reg_save_area[args.gpr+8]
8714 ret = *args.overflow_arg_area++;
8715 } else if (float value) {
8717 ret = args.reg_save_area[args.fpr+64]
8719 ret = *args.overflow_arg_area++;
8720 } else if (aggregate value) {
8722 ret = *args.reg_save_area[args.gpr]
8724 ret = **args.overflow_arg_area++;
8728 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
8729 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8731 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8732 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8733 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8734 tree lab_false
, lab_over
, addr
;
8736 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8737 f_fpr
= DECL_CHAIN (f_gpr
);
8738 f_ovf
= DECL_CHAIN (f_fpr
);
8739 f_sav
= DECL_CHAIN (f_ovf
);
8741 valist
= build_va_arg_indirect_ref (valist
);
8742 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8743 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8744 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8746 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8747 both appear on a lhs. */
8748 valist
= unshare_expr (valist
);
8749 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8751 size
= int_size_in_bytes (type
);
8753 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8755 if (TARGET_DEBUG_ARG
)
8757 fprintf (stderr
, "va_arg: aggregate type");
8761 /* Aggregates are passed by reference. */
8766 /* kernel stack layout on 31 bit: It is assumed here that no padding
8767 will be added by s390_frame_info because for va_args always an even
8768 number of gprs has to be saved r15-r2 = 14 regs. */
8769 sav_ofs
= 2 * UNITS_PER_LONG
;
8770 sav_scale
= UNITS_PER_LONG
;
8771 size
= UNITS_PER_LONG
;
8772 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8774 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
8776 if (TARGET_DEBUG_ARG
)
8778 fprintf (stderr
, "va_arg: float type");
8782 /* FP args go in FP registers, if present. */
8786 sav_ofs
= 16 * UNITS_PER_LONG
;
8788 max_reg
= FP_ARG_NUM_REG
- n_reg
;
8792 if (TARGET_DEBUG_ARG
)
8794 fprintf (stderr
, "va_arg: other type");
8798 /* Otherwise into GP registers. */
8801 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8803 /* kernel stack layout on 31 bit: It is assumed here that no padding
8804 will be added by s390_frame_info because for va_args always an even
8805 number of gprs has to be saved r15-r2 = 14 regs. */
8806 sav_ofs
= 2 * UNITS_PER_LONG
;
8808 if (size
< UNITS_PER_LONG
)
8809 sav_ofs
+= UNITS_PER_LONG
- size
;
8811 sav_scale
= UNITS_PER_LONG
;
8812 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8815 /* Pull the value out of the saved registers ... */
8817 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
8818 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
8819 addr
= create_tmp_var (ptr_type_node
, "addr");
8821 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
8822 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
8823 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
8824 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
8825 gimplify_and_add (t
, pre_p
);
8827 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
,
8828 size_int (sav_ofs
));
8829 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
8830 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
8831 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, fold_convert (sizetype
, u
));
8833 gimplify_assign (addr
, t
, pre_p
);
8835 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
8837 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
8840 /* ... Otherwise out of the overflow area. */
8843 if (size
< UNITS_PER_LONG
)
8844 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8845 size_int (UNITS_PER_LONG
- size
));
8847 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
8849 gimplify_assign (addr
, t
, pre_p
);
8851 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8853 gimplify_assign (ovf
, t
, pre_p
);
8855 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
8858 /* Increment register save count. */
8860 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
8861 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
8862 gimplify_and_add (u
, pre_p
);
8866 t
= build_pointer_type_for_mode (build_pointer_type (type
),
8868 addr
= fold_convert (t
, addr
);
8869 addr
= build_va_arg_indirect_ref (addr
);
8873 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
8874 addr
= fold_convert (t
, addr
);
8877 return build_va_arg_indirect_ref (addr
);
8885 S390_BUILTIN_THREAD_POINTER
,
8886 S390_BUILTIN_SET_THREAD_POINTER
,
8891 static enum insn_code
const code_for_builtin_64
[S390_BUILTIN_max
] = {
8896 static enum insn_code
const code_for_builtin_31
[S390_BUILTIN_max
] = {
8902 s390_init_builtins (void)
8906 ftype
= build_function_type (ptr_type_node
, void_list_node
);
8907 add_builtin_function ("__builtin_thread_pointer", ftype
,
8908 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
8911 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
8912 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
8913 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
8917 /* Expand an expression EXP that calls a built-in function,
8918 with result going to TARGET if that's convenient
8919 (and in mode MODE if that's convenient).
8920 SUBTARGET may be used as the target for computing one of EXP's operands.
8921 IGNORE is nonzero if the value is to be ignored. */
8924 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8925 enum machine_mode mode ATTRIBUTE_UNUSED
,
8926 int ignore ATTRIBUTE_UNUSED
)
8930 enum insn_code
const *code_for_builtin
=
8931 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
8933 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8934 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8935 enum insn_code icode
;
8936 rtx op
[MAX_ARGS
], pat
;
8940 call_expr_arg_iterator iter
;
8942 if (fcode
>= S390_BUILTIN_max
)
8943 internal_error ("bad builtin fcode");
8944 icode
= code_for_builtin
[fcode
];
8946 internal_error ("bad builtin fcode");
8948 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
8951 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
8953 const struct insn_operand_data
*insn_op
;
8955 if (arg
== error_mark_node
)
8957 if (arity
> MAX_ARGS
)
8960 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
8962 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
8964 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
8965 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
8971 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8973 || GET_MODE (target
) != tmode
8974 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8975 target
= gen_reg_rtx (tmode
);
8981 pat
= GEN_FCN (icode
) (target
);
8985 pat
= GEN_FCN (icode
) (target
, op
[0]);
8987 pat
= GEN_FCN (icode
) (op
[0]);
8990 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
9006 /* Output assembly code for the trampoline template to
9009 On S/390, we use gpr 1 internally in the trampoline code;
9010 gpr 0 is used to hold the static chain. */
9013 s390_asm_trampoline_template (FILE *file
)
9016 op
[0] = gen_rtx_REG (Pmode
, 0);
9017 op
[1] = gen_rtx_REG (Pmode
, 1);
9021 output_asm_insn ("basr\t%1,0", op
);
9022 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
9023 output_asm_insn ("br\t%1", op
);
9024 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9028 output_asm_insn ("basr\t%1,0", op
);
9029 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
9030 output_asm_insn ("br\t%1", op
);
9031 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9035 /* Emit RTL insns to initialize the variable parts of a trampoline.
9036 FNADDR is an RTX for the address of the function's pure code.
9037 CXT is an RTX for the static chain value for the function. */
9040 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9042 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9045 emit_block_move (m_tramp
, assemble_trampoline_template (),
9046 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
9048 mem
= adjust_address (m_tramp
, Pmode
, 2*UNITS_PER_WORD
);
9049 emit_move_insn (mem
, cxt
);
9050 mem
= adjust_address (m_tramp
, Pmode
, 3*UNITS_PER_WORD
);
9051 emit_move_insn (mem
, fnaddr
);
9054 /* Output assembler code to FILE to increment profiler label # LABELNO
9055 for profiling a function entry. */
9058 s390_function_profiler (FILE *file
, int labelno
)
9063 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9065 fprintf (file
, "# function profiler \n");
9067 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9068 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9069 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_LONG
));
9071 op
[2] = gen_rtx_REG (Pmode
, 1);
9072 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9073 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9075 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9078 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9079 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9084 output_asm_insn ("stg\t%0,%1", op
);
9085 output_asm_insn ("larl\t%2,%3", op
);
9086 output_asm_insn ("brasl\t%0,%4", op
);
9087 output_asm_insn ("lg\t%0,%1", op
);
9091 op
[6] = gen_label_rtx ();
9093 output_asm_insn ("st\t%0,%1", op
);
9094 output_asm_insn ("bras\t%2,%l6", op
);
9095 output_asm_insn (".long\t%4", op
);
9096 output_asm_insn (".long\t%3", op
);
9097 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9098 output_asm_insn ("l\t%0,0(%2)", op
);
9099 output_asm_insn ("l\t%2,4(%2)", op
);
9100 output_asm_insn ("basr\t%0,%0", op
);
9101 output_asm_insn ("l\t%0,%1", op
);
9105 op
[5] = gen_label_rtx ();
9106 op
[6] = gen_label_rtx ();
9108 output_asm_insn ("st\t%0,%1", op
);
9109 output_asm_insn ("bras\t%2,%l6", op
);
9110 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9111 output_asm_insn (".long\t%4-%l5", op
);
9112 output_asm_insn (".long\t%3-%l5", op
);
9113 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9114 output_asm_insn ("lr\t%0,%2", op
);
9115 output_asm_insn ("a\t%0,0(%2)", op
);
9116 output_asm_insn ("a\t%2,4(%2)", op
);
9117 output_asm_insn ("basr\t%0,%0", op
);
9118 output_asm_insn ("l\t%0,%1", op
);
9122 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9123 into its SYMBOL_REF_FLAGS. */
9126 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9128 default_encode_section_info (decl
, rtl
, first
);
9130 if (TREE_CODE (decl
) == VAR_DECL
)
9132 /* If a variable has a forced alignment to < 2 bytes, mark it
9133 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9135 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9136 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9137 if (!DECL_SIZE (decl
)
9138 || !DECL_ALIGN (decl
)
9139 || !host_integerp (DECL_SIZE (decl
), 0)
9140 || (DECL_ALIGN (decl
) <= 64
9141 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9142 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9145 /* Literal pool references don't have a decl so they are handled
9146 differently here. We rely on the information in the MEM_ALIGN
9147 entry to decide upon natural alignment. */
9149 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9150 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9151 && (MEM_ALIGN (rtl
) == 0
9152 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9153 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9154 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9157 /* Output thunk to FILE that implements a C++ virtual function call (with
9158 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9159 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9160 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9161 relative to the resulting this pointer. */
9164 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9165 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9171 /* Make sure unwind info is emitted for the thunk if needed. */
9172 final_start_function (emit_barrier (), file
, 1);
9174 /* Operand 0 is the target function. */
9175 op
[0] = XEXP (DECL_RTL (function
), 0);
9176 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9179 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9180 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9181 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9184 /* Operand 1 is the 'this' pointer. */
9185 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9186 op
[1] = gen_rtx_REG (Pmode
, 3);
9188 op
[1] = gen_rtx_REG (Pmode
, 2);
9190 /* Operand 2 is the delta. */
9191 op
[2] = GEN_INT (delta
);
9193 /* Operand 3 is the vcall_offset. */
9194 op
[3] = GEN_INT (vcall_offset
);
9196 /* Operand 4 is the temporary register. */
9197 op
[4] = gen_rtx_REG (Pmode
, 1);
9199 /* Operands 5 to 8 can be used as labels. */
9205 /* Operand 9 can be used for temporary register. */
9208 /* Generate code. */
9211 /* Setup literal pool pointer if required. */
9212 if ((!DISP_IN_RANGE (delta
)
9213 && !CONST_OK_FOR_K (delta
)
9214 && !CONST_OK_FOR_Os (delta
))
9215 || (!DISP_IN_RANGE (vcall_offset
)
9216 && !CONST_OK_FOR_K (vcall_offset
)
9217 && !CONST_OK_FOR_Os (vcall_offset
)))
9219 op
[5] = gen_label_rtx ();
9220 output_asm_insn ("larl\t%4,%5", op
);
9223 /* Add DELTA to this pointer. */
9226 if (CONST_OK_FOR_J (delta
))
9227 output_asm_insn ("la\t%1,%2(%1)", op
);
9228 else if (DISP_IN_RANGE (delta
))
9229 output_asm_insn ("lay\t%1,%2(%1)", op
);
9230 else if (CONST_OK_FOR_K (delta
))
9231 output_asm_insn ("aghi\t%1,%2", op
);
9232 else if (CONST_OK_FOR_Os (delta
))
9233 output_asm_insn ("agfi\t%1,%2", op
);
9236 op
[6] = gen_label_rtx ();
9237 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9241 /* Perform vcall adjustment. */
9244 if (DISP_IN_RANGE (vcall_offset
))
9246 output_asm_insn ("lg\t%4,0(%1)", op
);
9247 output_asm_insn ("ag\t%1,%3(%4)", op
);
9249 else if (CONST_OK_FOR_K (vcall_offset
))
9251 output_asm_insn ("lghi\t%4,%3", op
);
9252 output_asm_insn ("ag\t%4,0(%1)", op
);
9253 output_asm_insn ("ag\t%1,0(%4)", op
);
9255 else if (CONST_OK_FOR_Os (vcall_offset
))
9257 output_asm_insn ("lgfi\t%4,%3", op
);
9258 output_asm_insn ("ag\t%4,0(%1)", op
);
9259 output_asm_insn ("ag\t%1,0(%4)", op
);
9263 op
[7] = gen_label_rtx ();
9264 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9265 output_asm_insn ("ag\t%4,0(%1)", op
);
9266 output_asm_insn ("ag\t%1,0(%4)", op
);
9270 /* Jump to target. */
9271 output_asm_insn ("jg\t%0", op
);
9273 /* Output literal pool if required. */
9276 output_asm_insn (".align\t4", op
);
9277 targetm
.asm_out
.internal_label (file
, "L",
9278 CODE_LABEL_NUMBER (op
[5]));
9282 targetm
.asm_out
.internal_label (file
, "L",
9283 CODE_LABEL_NUMBER (op
[6]));
9284 output_asm_insn (".long\t%2", op
);
9288 targetm
.asm_out
.internal_label (file
, "L",
9289 CODE_LABEL_NUMBER (op
[7]));
9290 output_asm_insn (".long\t%3", op
);
9295 /* Setup base pointer if required. */
9297 || (!DISP_IN_RANGE (delta
)
9298 && !CONST_OK_FOR_K (delta
)
9299 && !CONST_OK_FOR_Os (delta
))
9300 || (!DISP_IN_RANGE (delta
)
9301 && !CONST_OK_FOR_K (vcall_offset
)
9302 && !CONST_OK_FOR_Os (vcall_offset
)))
9304 op
[5] = gen_label_rtx ();
9305 output_asm_insn ("basr\t%4,0", op
);
9306 targetm
.asm_out
.internal_label (file
, "L",
9307 CODE_LABEL_NUMBER (op
[5]));
9310 /* Add DELTA to this pointer. */
9313 if (CONST_OK_FOR_J (delta
))
9314 output_asm_insn ("la\t%1,%2(%1)", op
);
9315 else if (DISP_IN_RANGE (delta
))
9316 output_asm_insn ("lay\t%1,%2(%1)", op
);
9317 else if (CONST_OK_FOR_K (delta
))
9318 output_asm_insn ("ahi\t%1,%2", op
);
9319 else if (CONST_OK_FOR_Os (delta
))
9320 output_asm_insn ("afi\t%1,%2", op
);
9323 op
[6] = gen_label_rtx ();
9324 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9328 /* Perform vcall adjustment. */
9331 if (CONST_OK_FOR_J (vcall_offset
))
9333 output_asm_insn ("l\t%4,0(%1)", op
);
9334 output_asm_insn ("a\t%1,%3(%4)", op
);
9336 else if (DISP_IN_RANGE (vcall_offset
))
9338 output_asm_insn ("l\t%4,0(%1)", op
);
9339 output_asm_insn ("ay\t%1,%3(%4)", op
);
9341 else if (CONST_OK_FOR_K (vcall_offset
))
9343 output_asm_insn ("lhi\t%4,%3", op
);
9344 output_asm_insn ("a\t%4,0(%1)", op
);
9345 output_asm_insn ("a\t%1,0(%4)", op
);
9347 else if (CONST_OK_FOR_Os (vcall_offset
))
9349 output_asm_insn ("iilf\t%4,%3", op
);
9350 output_asm_insn ("a\t%4,0(%1)", op
);
9351 output_asm_insn ("a\t%1,0(%4)", op
);
9355 op
[7] = gen_label_rtx ();
9356 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9357 output_asm_insn ("a\t%4,0(%1)", op
);
9358 output_asm_insn ("a\t%1,0(%4)", op
);
9361 /* We had to clobber the base pointer register.
9362 Re-setup the base pointer (with a different base). */
9363 op
[5] = gen_label_rtx ();
9364 output_asm_insn ("basr\t%4,0", op
);
9365 targetm
.asm_out
.internal_label (file
, "L",
9366 CODE_LABEL_NUMBER (op
[5]));
9369 /* Jump to target. */
9370 op
[8] = gen_label_rtx ();
9373 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9375 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9376 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9377 else if (flag_pic
== 1)
9379 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9380 output_asm_insn ("l\t%4,%0(%4)", op
);
9382 else if (flag_pic
== 2)
9384 op
[9] = gen_rtx_REG (Pmode
, 0);
9385 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9386 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9387 output_asm_insn ("ar\t%4,%9", op
);
9388 output_asm_insn ("l\t%4,0(%4)", op
);
9391 output_asm_insn ("br\t%4", op
);
9393 /* Output literal pool. */
9394 output_asm_insn (".align\t4", op
);
9396 if (nonlocal
&& flag_pic
== 2)
9397 output_asm_insn (".long\t%0", op
);
9400 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9401 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9404 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9406 output_asm_insn (".long\t%0", op
);
9408 output_asm_insn (".long\t%0-%5", op
);
9412 targetm
.asm_out
.internal_label (file
, "L",
9413 CODE_LABEL_NUMBER (op
[6]));
9414 output_asm_insn (".long\t%2", op
);
9418 targetm
.asm_out
.internal_label (file
, "L",
9419 CODE_LABEL_NUMBER (op
[7]));
9420 output_asm_insn (".long\t%3", op
);
9423 final_end_function ();
9427 s390_valid_pointer_mode (enum machine_mode mode
)
9429 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9432 /* Checks whether the given CALL_EXPR would use a caller
9433 saved register. This is used to decide whether sibling call
9434 optimization could be performed on the respective function
9438 s390_call_saved_register_used (tree call_expr
)
9440 CUMULATIVE_ARGS cum
;
9442 enum machine_mode mode
;
9447 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
9449 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9451 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9452 gcc_assert (parameter
);
9454 /* For an undeclared variable passed as parameter we will get
9455 an ERROR_MARK node here. */
9456 if (TREE_CODE (parameter
) == ERROR_MARK
)
9459 type
= TREE_TYPE (parameter
);
9462 mode
= TYPE_MODE (type
);
9465 if (pass_by_reference (&cum
, mode
, type
, true))
9468 type
= build_pointer_type (type
);
9471 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
9473 s390_function_arg_advance (&cum
, mode
, type
, 0);
9478 if (REG_P (parm_rtx
))
9481 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9483 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9487 if (GET_CODE (parm_rtx
) == PARALLEL
)
9491 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9493 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9495 gcc_assert (REG_P (r
));
9498 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9500 if (!call_used_regs
[reg
+ REGNO (r
)])
9509 /* Return true if the given call expression can be
9510 turned into a sibling call.
9511 DECL holds the declaration of the function to be called whereas
9512 EXP is the call expression itself. */
9515 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9517 /* The TPF epilogue uses register 1. */
9518 if (TARGET_TPF_PROFILING
)
9521 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9522 which would have to be restored before the sibcall. */
9523 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9526 /* Register 6 on s390 is available as an argument register but unfortunately
9527 "caller saved". This makes functions needing this register for arguments
9528 not suitable for sibcalls. */
9529 return !s390_call_saved_register_used (exp
);
9532 /* Return the fixed registers used for condition codes. */
9535 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9538 *p2
= INVALID_REGNUM
;
9543 /* This function is used by the call expanders of the machine description.
9544 It emits the call insn itself together with the necessary operations
9545 to adjust the target address and returns the emitted insn.
9546 ADDR_LOCATION is the target address rtx
9547 TLS_CALL the location of the thread-local symbol
9548 RESULT_REG the register where the result of the call should be stored
9549 RETADDR_REG the register where the return address should be stored
9550 If this parameter is NULL_RTX the call is considered
9551 to be a sibling call. */
9554 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9557 bool plt_call
= false;
9563 /* Direct function calls need special treatment. */
9564 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9566 /* When calling a global routine in PIC mode, we must
9567 replace the symbol itself with the PLT stub. */
9568 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9570 if (retaddr_reg
!= NULL_RTX
)
9572 addr_location
= gen_rtx_UNSPEC (Pmode
,
9573 gen_rtvec (1, addr_location
),
9575 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9579 /* For -fpic code the PLT entries might use r12 which is
9580 call-saved. Therefore we cannot do a sibcall when
9581 calling directly using a symbol ref. When reaching
9582 this point we decided (in s390_function_ok_for_sibcall)
9583 to do a sibcall for a function pointer but one of the
9584 optimizers was able to get rid of the function pointer
9585 by propagating the symbol ref into the call. This
9586 optimization is illegal for S/390 so we turn the direct
9587 call into a indirect call again. */
9588 addr_location
= force_reg (Pmode
, addr_location
);
9591 /* Unless we can use the bras(l) insn, force the
9592 routine address into a register. */
9593 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9596 addr_location
= legitimize_pic_address (addr_location
, 0);
9598 addr_location
= force_reg (Pmode
, addr_location
);
9602 /* If it is already an indirect call or the code above moved the
9603 SYMBOL_REF to somewhere else make sure the address can be found in
9605 if (retaddr_reg
== NULL_RTX
9606 && GET_CODE (addr_location
) != SYMBOL_REF
9609 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9610 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9613 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9614 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9616 if (result_reg
!= NULL_RTX
)
9617 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9619 if (retaddr_reg
!= NULL_RTX
)
9621 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9623 if (tls_call
!= NULL_RTX
)
9624 vec
= gen_rtvec (3, call
, clobber
,
9625 gen_rtx_USE (VOIDmode
, tls_call
));
9627 vec
= gen_rtvec (2, call
, clobber
);
9629 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9632 insn
= emit_call_insn (call
);
9634 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9635 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9637 /* s390_function_ok_for_sibcall should
9638 have denied sibcalls in this case. */
9639 gcc_assert (retaddr_reg
!= NULL_RTX
);
9641 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
9646 /* Implement CONDITIONAL_REGISTER_USAGE. */
9649 s390_conditional_register_usage (void)
9655 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9656 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9658 if (TARGET_CPU_ZARCH
)
9660 fixed_regs
[BASE_REGNUM
] = 0;
9661 call_used_regs
[BASE_REGNUM
] = 0;
9662 fixed_regs
[RETURN_REGNUM
] = 0;
9663 call_used_regs
[RETURN_REGNUM
] = 0;
9667 for (i
= 24; i
< 32; i
++)
9668 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9672 for (i
= 18; i
< 20; i
++)
9673 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9676 if (TARGET_SOFT_FLOAT
)
9678 for (i
= 16; i
< 32; i
++)
9679 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9683 /* Corresponding function to eh_return expander. */
9685 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9687 s390_emit_tpf_eh_return (rtx target
)
9691 if (!s390_tpf_eh_return_symbol
)
9692 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9694 reg
= gen_rtx_REG (Pmode
, 2);
9696 emit_move_insn (reg
, target
);
9697 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9698 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9699 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9701 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9704 /* Rework the prologue/epilogue to avoid saving/restoring
9705 registers unnecessarily. */
9708 s390_optimize_prologue (void)
9710 rtx insn
, new_insn
, next_insn
;
9712 /* Do a final recompute of the frame-related data. */
9714 s390_update_frame_layout ();
9716 /* If all special registers are in fact used, there's nothing we
9717 can do, so no point in walking the insn list. */
9719 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
9720 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
9721 && (TARGET_CPU_ZARCH
9722 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
9723 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
9726 /* Search for prologue/epilogue insns and replace them. */
9728 for (insn
= get_insns (); insn
; insn
= next_insn
)
9730 int first
, last
, off
;
9731 rtx set
, base
, offset
;
9733 next_insn
= NEXT_INSN (insn
);
9735 if (GET_CODE (insn
) != INSN
)
9738 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9739 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9741 set
= XVECEXP (PATTERN (insn
), 0, 0);
9742 first
= REGNO (SET_SRC (set
));
9743 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9744 offset
= const0_rtx
;
9745 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9746 off
= INTVAL (offset
);
9748 if (GET_CODE (base
) != REG
|| off
< 0)
9750 if (cfun_frame_layout
.first_save_gpr
!= -1
9751 && (cfun_frame_layout
.first_save_gpr
< first
9752 || cfun_frame_layout
.last_save_gpr
> last
))
9754 if (REGNO (base
) != STACK_POINTER_REGNUM
9755 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9757 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9760 if (cfun_frame_layout
.first_save_gpr
!= -1)
9762 new_insn
= save_gprs (base
,
9763 off
+ (cfun_frame_layout
.first_save_gpr
9764 - first
) * UNITS_PER_LONG
,
9765 cfun_frame_layout
.first_save_gpr
,
9766 cfun_frame_layout
.last_save_gpr
);
9767 new_insn
= emit_insn_before (new_insn
, insn
);
9768 INSN_ADDRESSES_NEW (new_insn
, -1);
9775 if (cfun_frame_layout
.first_save_gpr
== -1
9776 && GET_CODE (PATTERN (insn
)) == SET
9777 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
9778 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
9779 || (!TARGET_CPU_ZARCH
9780 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
9781 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
9783 set
= PATTERN (insn
);
9784 first
= REGNO (SET_SRC (set
));
9785 offset
= const0_rtx
;
9786 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9787 off
= INTVAL (offset
);
9789 if (GET_CODE (base
) != REG
|| off
< 0)
9791 if (REGNO (base
) != STACK_POINTER_REGNUM
9792 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9799 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9800 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
9802 set
= XVECEXP (PATTERN (insn
), 0, 0);
9803 first
= REGNO (SET_DEST (set
));
9804 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9805 offset
= const0_rtx
;
9806 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9807 off
= INTVAL (offset
);
9809 if (GET_CODE (base
) != REG
|| off
< 0)
9811 if (cfun_frame_layout
.first_restore_gpr
!= -1
9812 && (cfun_frame_layout
.first_restore_gpr
< first
9813 || cfun_frame_layout
.last_restore_gpr
> last
))
9815 if (REGNO (base
) != STACK_POINTER_REGNUM
9816 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9818 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9821 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9823 new_insn
= restore_gprs (base
,
9824 off
+ (cfun_frame_layout
.first_restore_gpr
9825 - first
) * UNITS_PER_LONG
,
9826 cfun_frame_layout
.first_restore_gpr
,
9827 cfun_frame_layout
.last_restore_gpr
);
9828 new_insn
= emit_insn_before (new_insn
, insn
);
9829 INSN_ADDRESSES_NEW (new_insn
, -1);
9836 if (cfun_frame_layout
.first_restore_gpr
== -1
9837 && GET_CODE (PATTERN (insn
)) == SET
9838 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
9839 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
9840 || (!TARGET_CPU_ZARCH
9841 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
9842 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
9844 set
= PATTERN (insn
);
9845 first
= REGNO (SET_DEST (set
));
9846 offset
= const0_rtx
;
9847 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9848 off
= INTVAL (offset
);
9850 if (GET_CODE (base
) != REG
|| off
< 0)
9852 if (REGNO (base
) != STACK_POINTER_REGNUM
9853 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9862 /* On z10 the dynamic branch prediction must see the backward jump in
9863 a window of 384 bytes. If not it falls back to the static
9864 prediction. This function rearranges the loop backward branch in a
9865 way which makes the static prediction always correct. The function
9866 returns true if it added an instruction. */
9868 s390_z10_fix_long_loop_prediction (rtx insn
)
9870 rtx set
= single_set (insn
);
9871 rtx code_label
, label_ref
, new_label
;
9877 /* This will exclude branch on count and branch on index patterns
9878 since these are correctly statically predicted. */
9880 || SET_DEST (set
) != pc_rtx
9881 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
9884 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
9885 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
9887 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
9889 code_label
= XEXP (label_ref
, 0);
9891 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
9892 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
9893 || (INSN_ADDRESSES (INSN_UID (insn
))
9894 - INSN_ADDRESSES (INSN_UID (code_label
)) < Z10_PREDICT_DISTANCE
))
9897 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
9898 distance
< Z10_PREDICT_DISTANCE
- 6;
9899 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
9900 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
9903 new_label
= gen_label_rtx ();
9904 uncond_jump
= emit_jump_insn_after (
9905 gen_rtx_SET (VOIDmode
, pc_rtx
,
9906 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
9908 emit_label_after (new_label
, uncond_jump
);
9910 tmp
= XEXP (SET_SRC (set
), 1);
9911 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
9912 XEXP (SET_SRC (set
), 2) = tmp
;
9913 INSN_CODE (insn
) = -1;
9915 XEXP (label_ref
, 0) = new_label
;
9916 JUMP_LABEL (insn
) = new_label
;
9917 JUMP_LABEL (uncond_jump
) = code_label
;
9922 /* Returns 1 if INSN reads the value of REG for purposes not related
9923 to addressing of memory, and 0 otherwise. */
9925 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
9927 return reg_referenced_p (reg
, PATTERN (insn
))
9928 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
9931 /* Starting from INSN find_cond_jump looks downwards in the insn
9932 stream for a single jump insn which is the last user of the
9933 condition code set in INSN. */
9935 find_cond_jump (rtx insn
)
9937 for (; insn
; insn
= NEXT_INSN (insn
))
9946 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
9951 /* This will be triggered by a return. */
9952 if (GET_CODE (PATTERN (insn
)) != SET
)
9955 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
9956 ite
= SET_SRC (PATTERN (insn
));
9958 if (GET_CODE (ite
) != IF_THEN_ELSE
)
9961 cc
= XEXP (XEXP (ite
, 0), 0);
9962 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
9965 if (find_reg_note (insn
, REG_DEAD
, cc
))
9973 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9974 the semantics does not change. If NULL_RTX is passed as COND the
9975 function tries to find the conditional jump starting with INSN. */
9977 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
9981 if (cond
== NULL_RTX
)
9983 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
9984 jump
= jump
? single_set (jump
) : NULL_RTX
;
9986 if (jump
== NULL_RTX
)
9989 cond
= XEXP (XEXP (jump
, 1), 0);
9994 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
9997 /* On z10, instructions of the compare-and-branch family have the
9998 property to access the register occurring as second operand with
9999 its bits complemented. If such a compare is grouped with a second
10000 instruction that accesses the same register non-complemented, and
10001 if that register's value is delivered via a bypass, then the
10002 pipeline recycles, thereby causing significant performance decline.
10003 This function locates such situations and exchanges the two
10004 operands of the compare. The function return true whenever it
10007 s390_z10_optimize_cmp (rtx insn
)
10009 rtx prev_insn
, next_insn
;
10010 bool insn_added_p
= false;
10011 rtx cond
, *op0
, *op1
;
10013 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10015 /* Handle compare and branch and branch on count
10017 rtx pattern
= single_set (insn
);
10020 || SET_DEST (pattern
) != pc_rtx
10021 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10024 cond
= XEXP (SET_SRC (pattern
), 0);
10025 op0
= &XEXP (cond
, 0);
10026 op1
= &XEXP (cond
, 1);
10028 else if (GET_CODE (PATTERN (insn
)) == SET
)
10032 /* Handle normal compare instructions. */
10033 src
= SET_SRC (PATTERN (insn
));
10034 dest
= SET_DEST (PATTERN (insn
));
10037 || !CC_REGNO_P (REGNO (dest
))
10038 || GET_CODE (src
) != COMPARE
)
10041 /* s390_swap_cmp will try to find the conditional
10042 jump when passing NULL_RTX as condition. */
10044 op0
= &XEXP (src
, 0);
10045 op1
= &XEXP (src
, 1);
10050 if (!REG_P (*op0
) || !REG_P (*op1
))
10053 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10056 /* Swap the COMPARE arguments and its mask if there is a
10057 conflicting access in the previous insn. */
10058 prev_insn
= prev_active_insn (insn
);
10059 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10060 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10061 s390_swap_cmp (cond
, op0
, op1
, insn
);
10063 /* Check if there is a conflict with the next insn. If there
10064 was no conflict with the previous insn, then swap the
10065 COMPARE arguments and its mask. If we already swapped
10066 the operands, or if swapping them would cause a conflict
10067 with the previous insn, issue a NOP after the COMPARE in
10068 order to separate the two instuctions. */
10069 next_insn
= next_active_insn (insn
);
10070 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10071 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10073 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10074 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10076 if (REGNO (*op1
) == 0)
10077 emit_insn_after (gen_nop1 (), insn
);
10079 emit_insn_after (gen_nop (), insn
);
10080 insn_added_p
= true;
10083 s390_swap_cmp (cond
, op0
, op1
, insn
);
10085 return insn_added_p
;
10088 /* Perform machine-dependent processing. */
10093 bool pool_overflow
= false;
10095 /* Make sure all splits have been performed; splits after
10096 machine_dependent_reorg might confuse insn length counts. */
10097 split_all_insns_noflow ();
10099 /* Install the main literal pool and the associated base
10100 register load insns.
10102 In addition, there are two problematic situations we need
10105 - the literal pool might be > 4096 bytes in size, so that
10106 some of its elements cannot be directly accessed
10108 - a branch target might be > 64K away from the branch, so that
10109 it is not possible to use a PC-relative instruction.
10111 To fix those, we split the single literal pool into multiple
10112 pool chunks, reloading the pool base register at various
10113 points throughout the function to ensure it always points to
10114 the pool chunk the following code expects, and / or replace
10115 PC-relative branches by absolute branches.
10117 However, the two problems are interdependent: splitting the
10118 literal pool can move a branch further away from its target,
10119 causing the 64K limit to overflow, and on the other hand,
10120 replacing a PC-relative branch by an absolute branch means
10121 we need to put the branch target address into the literal
10122 pool, possibly causing it to overflow.
10124 So, we loop trying to fix up both problems until we manage
10125 to satisfy both conditions at the same time. Note that the
10126 loop is guaranteed to terminate as every pass of the loop
10127 strictly decreases the total number of PC-relative branches
10128 in the function. (This is not completely true as there
10129 might be branch-over-pool insns introduced by chunkify_start.
10130 Those never need to be split however.) */
10134 struct constant_pool
*pool
= NULL
;
10136 /* Collect the literal pool. */
10137 if (!pool_overflow
)
10139 pool
= s390_mainpool_start ();
10141 pool_overflow
= true;
10144 /* If literal pool overflowed, start to chunkify it. */
10146 pool
= s390_chunkify_start ();
10148 /* Split out-of-range branches. If this has created new
10149 literal pool entries, cancel current chunk list and
10150 recompute it. zSeries machines have large branch
10151 instructions, so we never need to split a branch. */
10152 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10155 s390_chunkify_cancel (pool
);
10157 s390_mainpool_cancel (pool
);
10162 /* If we made it up to here, both conditions are satisfied.
10163 Finish up literal pool related changes. */
10165 s390_chunkify_finish (pool
);
10167 s390_mainpool_finish (pool
);
10169 /* We're done splitting branches. */
10170 cfun
->machine
->split_branches_pending_p
= false;
10174 /* Generate out-of-pool execute target insns. */
10175 if (TARGET_CPU_ZARCH
)
10177 rtx insn
, label
, target
;
10179 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10181 label
= s390_execute_label (insn
);
10185 gcc_assert (label
!= const0_rtx
);
10187 target
= emit_label (XEXP (label
, 0));
10188 INSN_ADDRESSES_NEW (target
, -1);
10190 target
= emit_insn (s390_execute_target (insn
));
10191 INSN_ADDRESSES_NEW (target
, -1);
10195 /* Try to optimize prologue and epilogue further. */
10196 s390_optimize_prologue ();
10198 /* Walk over the insns and do some z10 specific changes. */
10199 if (s390_tune
== PROCESSOR_2097_Z10
)
10202 bool insn_added_p
= false;
10204 /* The insn lengths and addresses have to be up to date for the
10205 following manipulations. */
10206 shorten_branches (get_insns ());
10208 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10210 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10214 insn_added_p
|= s390_z10_fix_long_loop_prediction (insn
);
10216 if (GET_CODE (PATTERN (insn
)) == PARALLEL
10217 || GET_CODE (PATTERN (insn
)) == SET
)
10218 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10221 /* Adjust branches if we added new instructions. */
10223 shorten_branches (get_insns ());
10227 /* Return true if INSN is a fp load insn writing register REGNO. */
10229 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10232 enum attr_type flag
= s390_safe_attr_type (insn
);
10234 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10237 set
= single_set (insn
);
10239 if (set
== NULL_RTX
)
10242 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10245 if (REGNO (SET_DEST (set
)) != regno
)
10251 /* This value describes the distance to be avoided between an
10252 aritmetic fp instruction and an fp load writing the same register.
10253 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10254 fine but the exact value has to be avoided. Otherwise the FP
10255 pipeline will throw an exception causing a major penalty. */
10256 #define Z10_EARLYLOAD_DISTANCE 7
10258 /* Rearrange the ready list in order to avoid the situation described
10259 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10260 moved to the very end of the ready list. */
10262 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10264 unsigned int regno
;
10265 int nready
= *nready_p
;
10270 enum attr_type flag
;
10273 /* Skip DISTANCE - 1 active insns. */
10274 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10275 distance
> 0 && insn
!= NULL_RTX
;
10276 distance
--, insn
= prev_active_insn (insn
))
10277 if (CALL_P (insn
) || JUMP_P (insn
))
10280 if (insn
== NULL_RTX
)
10283 set
= single_set (insn
);
10285 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10286 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10289 flag
= s390_safe_attr_type (insn
);
10291 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10294 regno
= REGNO (SET_DEST (set
));
10297 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10304 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10308 /* This function is called via hook TARGET_SCHED_REORDER before
10309 issueing one insn from list READY which contains *NREADYP entries.
10310 For target z10 it reorders load instructions to avoid early load
10311 conflicts in the floating point pipeline */
10313 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10314 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10316 if (s390_tune
== PROCESSOR_2097_Z10
)
10317 if (reload_completed
&& *nreadyp
> 1)
10318 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10320 return s390_issue_rate ();
10323 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10324 the scheduler has issued INSN. It stores the last issued insn into
10325 last_scheduled_insn in order to make it available for
10326 s390_sched_reorder. */
10328 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED
,
10329 int verbose ATTRIBUTE_UNUSED
,
10330 rtx insn
, int more
)
10332 last_scheduled_insn
= insn
;
10334 if (GET_CODE (PATTERN (insn
)) != USE
10335 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10342 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10343 int verbose ATTRIBUTE_UNUSED
,
10344 int max_ready ATTRIBUTE_UNUSED
)
10346 last_scheduled_insn
= NULL_RTX
;
10349 /* This function checks the whole of insn X for memory references. The
10350 function always returns zero because the framework it is called
10351 from would stop recursively analyzing the insn upon a return value
10352 other than zero. The real result of this function is updating
10353 counter variable MEM_COUNT. */
10355 check_dpu (rtx
*x
, unsigned *mem_count
)
10357 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10362 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10363 a new number struct loop *loop should be unrolled if tuned for the z10
10364 cpu. The loop is analyzed for memory accesses by calling check_dpu for
10365 each rtx of the loop. Depending on the loop_depth and the amount of
10366 memory accesses a new number <=nunroll is returned to improve the
10367 behaviour of the hardware prefetch unit. */
10369 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10374 unsigned mem_count
= 0;
10376 /* Only z10 needs special handling. */
10377 if (s390_tune
!= PROCESSOR_2097_Z10
)
10380 /* Count the number of memory references within the loop body. */
10381 bbs
= get_loop_body (loop
);
10382 for (i
= 0; i
< loop
->num_nodes
; i
++)
10384 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10385 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10386 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10390 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10391 if (mem_count
== 0)
10394 switch (loop_depth(loop
))
10397 return MIN (nunroll
, 28 / mem_count
);
10399 return MIN (nunroll
, 22 / mem_count
);
10401 return MIN (nunroll
, 16 / mem_count
);
10405 /* Initialize GCC target structure. */
10407 #undef TARGET_ASM_ALIGNED_HI_OP
10408 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10409 #undef TARGET_ASM_ALIGNED_DI_OP
10410 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10411 #undef TARGET_ASM_INTEGER
10412 #define TARGET_ASM_INTEGER s390_assemble_integer
10414 #undef TARGET_ASM_OPEN_PAREN
10415 #define TARGET_ASM_OPEN_PAREN ""
10417 #undef TARGET_ASM_CLOSE_PAREN
10418 #define TARGET_ASM_CLOSE_PAREN ""
10420 #undef TARGET_DEFAULT_TARGET_FLAGS
10421 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10423 #undef TARGET_HANDLE_OPTION
10424 #define TARGET_HANDLE_OPTION s390_handle_option
10426 #undef TARGET_OPTION_OVERRIDE
10427 #define TARGET_OPTION_OVERRIDE s390_option_override
10429 #undef TARGET_ENCODE_SECTION_INFO
10430 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10432 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10433 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10436 #undef TARGET_HAVE_TLS
10437 #define TARGET_HAVE_TLS true
10439 #undef TARGET_CANNOT_FORCE_CONST_MEM
10440 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10442 #undef TARGET_DELEGITIMIZE_ADDRESS
10443 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10445 #undef TARGET_LEGITIMIZE_ADDRESS
10446 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10448 #undef TARGET_RETURN_IN_MEMORY
10449 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10451 #undef TARGET_INIT_BUILTINS
10452 #define TARGET_INIT_BUILTINS s390_init_builtins
10453 #undef TARGET_EXPAND_BUILTIN
10454 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10456 #undef TARGET_ASM_OUTPUT_MI_THUNK
10457 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10458 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10459 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10461 #undef TARGET_SCHED_ADJUST_PRIORITY
10462 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10463 #undef TARGET_SCHED_ISSUE_RATE
10464 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10465 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10466 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10468 #undef TARGET_SCHED_VARIABLE_ISSUE
10469 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10470 #undef TARGET_SCHED_REORDER
10471 #define TARGET_SCHED_REORDER s390_sched_reorder
10472 #undef TARGET_SCHED_INIT
10473 #define TARGET_SCHED_INIT s390_sched_init
10475 #undef TARGET_CANNOT_COPY_INSN_P
10476 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10477 #undef TARGET_RTX_COSTS
10478 #define TARGET_RTX_COSTS s390_rtx_costs
10479 #undef TARGET_ADDRESS_COST
10480 #define TARGET_ADDRESS_COST s390_address_cost
10482 #undef TARGET_MACHINE_DEPENDENT_REORG
10483 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10485 #undef TARGET_VALID_POINTER_MODE
10486 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10488 #undef TARGET_BUILD_BUILTIN_VA_LIST
10489 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10490 #undef TARGET_EXPAND_BUILTIN_VA_START
10491 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10492 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10493 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10495 #undef TARGET_PROMOTE_FUNCTION_MODE
10496 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10497 #undef TARGET_PASS_BY_REFERENCE
10498 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10500 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10501 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10503 #undef TARGET_FIXED_CONDITION_CODE_REGS
10504 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10506 #undef TARGET_CC_MODES_COMPATIBLE
10507 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10509 #undef TARGET_INVALID_WITHIN_DOLOOP
10510 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10513 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10514 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10517 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10518 #undef TARGET_MANGLE_TYPE
10519 #define TARGET_MANGLE_TYPE s390_mangle_type
10522 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10523 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10525 #undef TARGET_SECONDARY_RELOAD
10526 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10528 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10529 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10531 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10532 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10534 #undef TARGET_LEGITIMATE_ADDRESS_P
10535 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10537 #undef TARGET_CAN_ELIMINATE
10538 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10540 #undef TARGET_LOOP_UNROLL_ADJUST
10541 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10543 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10544 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10545 #undef TARGET_TRAMPOLINE_INIT
10546 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10548 #undef TARGET_UNWIND_WORD_MODE
10549 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10551 struct gcc_target targetm
= TARGET_INITIALIZER
;
10553 #include "gt-s390.h"