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s390.c (s390_swap_cmp): New function.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (10), /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (10), /* MADBR */
213 COSTS_N_INSNS (10), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 extern int reload_completed;
225
226 /* Save information from a "cmpxx" operation until the branch or scc is
227 emitted. */
228 rtx s390_compare_op0, s390_compare_op1;
229
230 /* Save the result of a compare_and_swap until the branch or scc is
231 emitted. */
232 rtx s390_compare_emitted = NULL_RTX;
233
234 /* Structure used to hold the components of a S/390 memory
235 address. A legitimate address on S/390 is of the general
236 form
237 base + index + displacement
238 where any of the components is optional.
239
240 base and index are registers of the class ADDR_REGS,
241 displacement is an unsigned 12-bit immediate constant. */
242
243 struct s390_address
244 {
245 rtx base;
246 rtx indx;
247 rtx disp;
248 bool pointer;
249 bool literal_pool;
250 };
251
252 /* Which cpu are we tuning for. */
253 enum processor_type s390_tune = PROCESSOR_max;
254 enum processor_flags s390_tune_flags;
255 /* Which instruction set architecture to use. */
256 enum processor_type s390_arch;
257 enum processor_flags s390_arch_flags;
258
259 HOST_WIDE_INT s390_warn_framesize = 0;
260 HOST_WIDE_INT s390_stack_size = 0;
261 HOST_WIDE_INT s390_stack_guard = 0;
262
263 /* The following structure is embedded in the machine
264 specific part of struct function. */
265
266 struct s390_frame_layout GTY (())
267 {
268 /* Offset within stack frame. */
269 HOST_WIDE_INT gprs_offset;
270 HOST_WIDE_INT f0_offset;
271 HOST_WIDE_INT f4_offset;
272 HOST_WIDE_INT f8_offset;
273 HOST_WIDE_INT backchain_offset;
274
275 /* Number of first and last gpr where slots in the register
276 save area are reserved for. */
277 int first_save_gpr_slot;
278 int last_save_gpr_slot;
279
280 /* Number of first and last gpr to be saved, restored. */
281 int first_save_gpr;
282 int first_restore_gpr;
283 int last_save_gpr;
284 int last_restore_gpr;
285
286 /* Bits standing for floating point registers. Set, if the
287 respective register has to be saved. Starting with reg 16 (f0)
288 at the rightmost bit.
289 Bit 15 - 8 7 6 5 4 3 2 1 0
290 fpr 15 - 8 7 5 3 1 6 4 2 0
291 reg 31 - 24 23 22 21 20 19 18 17 16 */
292 unsigned int fpr_bitmap;
293
294 /* Number of floating point registers f8-f15 which must be saved. */
295 int high_fprs;
296
297 /* Set if return address needs to be saved.
298 This flag is set by s390_return_addr_rtx if it could not use
299 the initial value of r14 and therefore depends on r14 saved
300 to the stack. */
301 bool save_return_addr_p;
302
303 /* Size of stack frame. */
304 HOST_WIDE_INT frame_size;
305 };
306
307 /* Define the structure for the machine field in struct function. */
308
309 struct machine_function GTY(())
310 {
311 struct s390_frame_layout frame_layout;
312
313 /* Literal pool base register. */
314 rtx base_reg;
315
316 /* True if we may need to perform branch splitting. */
317 bool split_branches_pending_p;
318
319 /* Some local-dynamic TLS symbol name. */
320 const char *some_ld_name;
321
322 bool has_landing_pad_p;
323 };
324
325 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
326
327 #define cfun_frame_layout (cfun->machine->frame_layout)
328 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
329 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
330 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
331 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
332 (1 << (BITNUM)))
333 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
334 (1 << (BITNUM))))
335
336 /* Number of GPRs and FPRs used for argument passing. */
337 #define GP_ARG_NUM_REG 5
338 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
339
340 /* A couple of shortcuts. */
341 #define CONST_OK_FOR_J(x) \
342 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
343 #define CONST_OK_FOR_K(x) \
344 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
345 #define CONST_OK_FOR_Os(x) \
346 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
347 #define CONST_OK_FOR_Op(x) \
348 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
349 #define CONST_OK_FOR_On(x) \
350 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
351
352 #define REGNO_PAIR_OK(REGNO, MODE) \
353 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
354
355 static enum machine_mode
356 s390_libgcc_cmp_return_mode (void)
357 {
358 return TARGET_64BIT ? DImode : SImode;
359 }
360
361 static enum machine_mode
362 s390_libgcc_shift_count_mode (void)
363 {
364 return TARGET_64BIT ? DImode : SImode;
365 }
366
367 /* Return true if the back end supports mode MODE. */
368 static bool
369 s390_scalar_mode_supported_p (enum machine_mode mode)
370 {
371 if (DECIMAL_FLOAT_MODE_P (mode))
372 return true;
373 else
374 return default_scalar_mode_supported_p (mode);
375 }
376
377 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
378
379 void
380 s390_set_has_landing_pad_p (bool value)
381 {
382 cfun->machine->has_landing_pad_p = value;
383 }
384
385 /* If two condition code modes are compatible, return a condition code
386 mode which is compatible with both. Otherwise, return
387 VOIDmode. */
388
389 static enum machine_mode
390 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
391 {
392 if (m1 == m2)
393 return m1;
394
395 switch (m1)
396 {
397 case CCZmode:
398 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
399 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
400 return m2;
401 return VOIDmode;
402
403 case CCSmode:
404 case CCUmode:
405 case CCTmode:
406 case CCSRmode:
407 case CCURmode:
408 case CCZ1mode:
409 if (m2 == CCZmode)
410 return m1;
411
412 return VOIDmode;
413
414 default:
415 return VOIDmode;
416 }
417 return VOIDmode;
418 }
419
420 /* Return true if SET either doesn't set the CC register, or else
421 the source and destination have matching CC modes and that
422 CC mode is at least as constrained as REQ_MODE. */
423
424 static bool
425 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
426 {
427 enum machine_mode set_mode;
428
429 gcc_assert (GET_CODE (set) == SET);
430
431 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
432 return 1;
433
434 set_mode = GET_MODE (SET_DEST (set));
435 switch (set_mode)
436 {
437 case CCSmode:
438 case CCSRmode:
439 case CCUmode:
440 case CCURmode:
441 case CCLmode:
442 case CCL1mode:
443 case CCL2mode:
444 case CCL3mode:
445 case CCT1mode:
446 case CCT2mode:
447 case CCT3mode:
448 if (req_mode != set_mode)
449 return 0;
450 break;
451
452 case CCZmode:
453 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
454 && req_mode != CCSRmode && req_mode != CCURmode)
455 return 0;
456 break;
457
458 case CCAPmode:
459 case CCANmode:
460 if (req_mode != CCAmode)
461 return 0;
462 break;
463
464 default:
465 gcc_unreachable ();
466 }
467
468 return (GET_MODE (SET_SRC (set)) == set_mode);
469 }
470
471 /* Return true if every SET in INSN that sets the CC register
472 has source and destination with matching CC modes and that
473 CC mode is at least as constrained as REQ_MODE.
474 If REQ_MODE is VOIDmode, always return false. */
475
476 bool
477 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
478 {
479 int i;
480
481 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
482 if (req_mode == VOIDmode)
483 return false;
484
485 if (GET_CODE (PATTERN (insn)) == SET)
486 return s390_match_ccmode_set (PATTERN (insn), req_mode);
487
488 if (GET_CODE (PATTERN (insn)) == PARALLEL)
489 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
490 {
491 rtx set = XVECEXP (PATTERN (insn), 0, i);
492 if (GET_CODE (set) == SET)
493 if (!s390_match_ccmode_set (set, req_mode))
494 return false;
495 }
496
497 return true;
498 }
499
500 /* If a test-under-mask instruction can be used to implement
501 (compare (and ... OP1) OP2), return the CC mode required
502 to do that. Otherwise, return VOIDmode.
503 MIXED is true if the instruction can distinguish between
504 CC1 and CC2 for mixed selected bits (TMxx), it is false
505 if the instruction cannot (TM). */
506
507 enum machine_mode
508 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
509 {
510 int bit0, bit1;
511
512 /* ??? Fixme: should work on CONST_DOUBLE as well. */
513 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
514 return VOIDmode;
515
516 /* Selected bits all zero: CC0.
517 e.g.: int a; if ((a & (16 + 128)) == 0) */
518 if (INTVAL (op2) == 0)
519 return CCTmode;
520
521 /* Selected bits all one: CC3.
522 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
523 if (INTVAL (op2) == INTVAL (op1))
524 return CCT3mode;
525
526 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
527 int a;
528 if ((a & (16 + 128)) == 16) -> CCT1
529 if ((a & (16 + 128)) == 128) -> CCT2 */
530 if (mixed)
531 {
532 bit1 = exact_log2 (INTVAL (op2));
533 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
534 if (bit0 != -1 && bit1 != -1)
535 return bit0 > bit1 ? CCT1mode : CCT2mode;
536 }
537
538 return VOIDmode;
539 }
540
541 /* Given a comparison code OP (EQ, NE, etc.) and the operands
542 OP0 and OP1 of a COMPARE, return the mode to be used for the
543 comparison. */
544
545 enum machine_mode
546 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
547 {
548 switch (code)
549 {
550 case EQ:
551 case NE:
552 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
553 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
554 return CCAPmode;
555 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
556 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
557 return CCAPmode;
558 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
559 || GET_CODE (op1) == NEG)
560 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
561 return CCLmode;
562
563 if (GET_CODE (op0) == AND)
564 {
565 /* Check whether we can potentially do it via TM. */
566 enum machine_mode ccmode;
567 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
568 if (ccmode != VOIDmode)
569 {
570 /* Relax CCTmode to CCZmode to allow fall-back to AND
571 if that turns out to be beneficial. */
572 return ccmode == CCTmode ? CCZmode : ccmode;
573 }
574 }
575
576 if (register_operand (op0, HImode)
577 && GET_CODE (op1) == CONST_INT
578 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
579 return CCT3mode;
580 if (register_operand (op0, QImode)
581 && GET_CODE (op1) == CONST_INT
582 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
583 return CCT3mode;
584
585 return CCZmode;
586
587 case LE:
588 case LT:
589 case GE:
590 case GT:
591 /* The only overflow condition of NEG and ABS happens when
592 -INT_MAX is used as parameter, which stays negative. So
593 we have an overflow from a positive value to a negative.
594 Using CCAP mode the resulting cc can be used for comparisons. */
595 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
596 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
597 return CCAPmode;
598
599 /* If constants are involved in an add instruction it is possible to use
600 the resulting cc for comparisons with zero. Knowing the sign of the
601 constant the overflow behavior gets predictable. e.g.:
602 int a, b; if ((b = a + c) > 0)
603 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
604 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
605 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
606 {
607 if (INTVAL (XEXP((op0), 1)) < 0)
608 return CCANmode;
609 else
610 return CCAPmode;
611 }
612 /* Fall through. */
613 case UNORDERED:
614 case ORDERED:
615 case UNEQ:
616 case UNLE:
617 case UNLT:
618 case UNGE:
619 case UNGT:
620 case LTGT:
621 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
622 && GET_CODE (op1) != CONST_INT)
623 return CCSRmode;
624 return CCSmode;
625
626 case LTU:
627 case GEU:
628 if (GET_CODE (op0) == PLUS
629 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
630 return CCL1mode;
631
632 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
633 && GET_CODE (op1) != CONST_INT)
634 return CCURmode;
635 return CCUmode;
636
637 case LEU:
638 case GTU:
639 if (GET_CODE (op0) == MINUS
640 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
641 return CCL2mode;
642
643 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
644 && GET_CODE (op1) != CONST_INT)
645 return CCURmode;
646 return CCUmode;
647
648 default:
649 gcc_unreachable ();
650 }
651 }
652
653 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
654 that we can implement more efficiently. */
655
656 void
657 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
658 {
659 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
660 if ((*code == EQ || *code == NE)
661 && *op1 == const0_rtx
662 && GET_CODE (*op0) == ZERO_EXTRACT
663 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
664 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
665 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
666 {
667 rtx inner = XEXP (*op0, 0);
668 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
669 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
670 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
671
672 if (len > 0 && len < modesize
673 && pos >= 0 && pos + len <= modesize
674 && modesize <= HOST_BITS_PER_WIDE_INT)
675 {
676 unsigned HOST_WIDE_INT block;
677 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
678 block <<= modesize - pos - len;
679
680 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
681 gen_int_mode (block, GET_MODE (inner)));
682 }
683 }
684
685 /* Narrow AND of memory against immediate to enable TM. */
686 if ((*code == EQ || *code == NE)
687 && *op1 == const0_rtx
688 && GET_CODE (*op0) == AND
689 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
690 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
691 {
692 rtx inner = XEXP (*op0, 0);
693 rtx mask = XEXP (*op0, 1);
694
695 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
696 if (GET_CODE (inner) == SUBREG
697 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
698 && (GET_MODE_SIZE (GET_MODE (inner))
699 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
700 && ((INTVAL (mask)
701 & GET_MODE_MASK (GET_MODE (inner))
702 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
703 == 0))
704 inner = SUBREG_REG (inner);
705
706 /* Do not change volatile MEMs. */
707 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
708 {
709 int part = s390_single_part (XEXP (*op0, 1),
710 GET_MODE (inner), QImode, 0);
711 if (part >= 0)
712 {
713 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
714 inner = adjust_address_nv (inner, QImode, part);
715 *op0 = gen_rtx_AND (QImode, inner, mask);
716 }
717 }
718 }
719
720 /* Narrow comparisons against 0xffff to HImode if possible. */
721 if ((*code == EQ || *code == NE)
722 && GET_CODE (*op1) == CONST_INT
723 && INTVAL (*op1) == 0xffff
724 && SCALAR_INT_MODE_P (GET_MODE (*op0))
725 && (nonzero_bits (*op0, GET_MODE (*op0))
726 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
727 {
728 *op0 = gen_lowpart (HImode, *op0);
729 *op1 = constm1_rtx;
730 }
731
732 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
733 if (GET_CODE (*op0) == UNSPEC
734 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
735 && XVECLEN (*op0, 0) == 1
736 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
737 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
738 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
739 && *op1 == const0_rtx)
740 {
741 enum rtx_code new_code = UNKNOWN;
742 switch (*code)
743 {
744 case EQ: new_code = EQ; break;
745 case NE: new_code = NE; break;
746 case LT: new_code = GTU; break;
747 case GT: new_code = LTU; break;
748 case LE: new_code = GEU; break;
749 case GE: new_code = LEU; break;
750 default: break;
751 }
752
753 if (new_code != UNKNOWN)
754 {
755 *op0 = XVECEXP (*op0, 0, 0);
756 *code = new_code;
757 }
758 }
759
760 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
761 if (GET_CODE (*op0) == UNSPEC
762 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
763 && XVECLEN (*op0, 0) == 1
764 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
765 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
766 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
767 && *op1 == const0_rtx)
768 {
769 enum rtx_code new_code = UNKNOWN;
770 switch (*code)
771 {
772 case EQ: new_code = EQ; break;
773 case NE: new_code = NE; break;
774 default: break;
775 }
776
777 if (new_code != UNKNOWN)
778 {
779 *op0 = XVECEXP (*op0, 0, 0);
780 *code = new_code;
781 }
782 }
783
784 /* Simplify cascaded EQ, NE with const0_rtx. */
785 if ((*code == NE || *code == EQ)
786 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
787 && GET_MODE (*op0) == SImode
788 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
789 && REG_P (XEXP (*op0, 0))
790 && XEXP (*op0, 1) == const0_rtx
791 && *op1 == const0_rtx)
792 {
793 if ((*code == EQ && GET_CODE (*op0) == NE)
794 || (*code == NE && GET_CODE (*op0) == EQ))
795 *code = EQ;
796 else
797 *code = NE;
798 *op0 = XEXP (*op0, 0);
799 }
800
801 /* Prefer register over memory as first operand. */
802 if (MEM_P (*op0) && REG_P (*op1))
803 {
804 rtx tem = *op0; *op0 = *op1; *op1 = tem;
805 *code = swap_condition (*code);
806 }
807 }
808
809 /* Emit a compare instruction suitable to implement the comparison
810 OP0 CODE OP1. Return the correct condition RTL to be placed in
811 the IF_THEN_ELSE of the conditional branch testing the result. */
812
813 rtx
814 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
815 {
816 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
817 rtx ret = NULL_RTX;
818
819 /* Do not output a redundant compare instruction if a compare_and_swap
820 pattern already computed the result and the machine modes are compatible. */
821 if (s390_compare_emitted
822 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
823 == GET_MODE (s390_compare_emitted)))
824 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
825 else
826 {
827 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
828
829 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
830 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
831 }
832 s390_compare_emitted = NULL_RTX;
833 return ret;
834 }
835
836 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
837 matches CMP.
838 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
839 conditional branch testing the result. */
840
841 static rtx
842 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
843 {
844 rtx ret;
845
846 emit_insn (gen_sync_compare_and_swap_ccsi (old, mem, cmp, new_rtx));
847 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
848
849 s390_compare_emitted = NULL_RTX;
850
851 return ret;
852 }
853
854 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
855 unconditional jump, else a conditional jump under condition COND. */
856
857 void
858 s390_emit_jump (rtx target, rtx cond)
859 {
860 rtx insn;
861
862 target = gen_rtx_LABEL_REF (VOIDmode, target);
863 if (cond)
864 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
865
866 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
867 emit_jump_insn (insn);
868 }
869
870 /* Return branch condition mask to implement a branch
871 specified by CODE. Return -1 for invalid comparisons. */
872
873 int
874 s390_branch_condition_mask (rtx code)
875 {
876 const int CC0 = 1 << 3;
877 const int CC1 = 1 << 2;
878 const int CC2 = 1 << 1;
879 const int CC3 = 1 << 0;
880
881 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
882 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
883 gcc_assert (XEXP (code, 1) == const0_rtx);
884
885 switch (GET_MODE (XEXP (code, 0)))
886 {
887 case CCZmode:
888 case CCZ1mode:
889 switch (GET_CODE (code))
890 {
891 case EQ: return CC0;
892 case NE: return CC1 | CC2 | CC3;
893 default: return -1;
894 }
895 break;
896
897 case CCT1mode:
898 switch (GET_CODE (code))
899 {
900 case EQ: return CC1;
901 case NE: return CC0 | CC2 | CC3;
902 default: return -1;
903 }
904 break;
905
906 case CCT2mode:
907 switch (GET_CODE (code))
908 {
909 case EQ: return CC2;
910 case NE: return CC0 | CC1 | CC3;
911 default: return -1;
912 }
913 break;
914
915 case CCT3mode:
916 switch (GET_CODE (code))
917 {
918 case EQ: return CC3;
919 case NE: return CC0 | CC1 | CC2;
920 default: return -1;
921 }
922 break;
923
924 case CCLmode:
925 switch (GET_CODE (code))
926 {
927 case EQ: return CC0 | CC2;
928 case NE: return CC1 | CC3;
929 default: return -1;
930 }
931 break;
932
933 case CCL1mode:
934 switch (GET_CODE (code))
935 {
936 case LTU: return CC2 | CC3; /* carry */
937 case GEU: return CC0 | CC1; /* no carry */
938 default: return -1;
939 }
940 break;
941
942 case CCL2mode:
943 switch (GET_CODE (code))
944 {
945 case GTU: return CC0 | CC1; /* borrow */
946 case LEU: return CC2 | CC3; /* no borrow */
947 default: return -1;
948 }
949 break;
950
951 case CCL3mode:
952 switch (GET_CODE (code))
953 {
954 case EQ: return CC0 | CC2;
955 case NE: return CC1 | CC3;
956 case LTU: return CC1;
957 case GTU: return CC3;
958 case LEU: return CC1 | CC2;
959 case GEU: return CC2 | CC3;
960 default: return -1;
961 }
962
963 case CCUmode:
964 switch (GET_CODE (code))
965 {
966 case EQ: return CC0;
967 case NE: return CC1 | CC2 | CC3;
968 case LTU: return CC1;
969 case GTU: return CC2;
970 case LEU: return CC0 | CC1;
971 case GEU: return CC0 | CC2;
972 default: return -1;
973 }
974 break;
975
976 case CCURmode:
977 switch (GET_CODE (code))
978 {
979 case EQ: return CC0;
980 case NE: return CC2 | CC1 | CC3;
981 case LTU: return CC2;
982 case GTU: return CC1;
983 case LEU: return CC0 | CC2;
984 case GEU: return CC0 | CC1;
985 default: return -1;
986 }
987 break;
988
989 case CCAPmode:
990 switch (GET_CODE (code))
991 {
992 case EQ: return CC0;
993 case NE: return CC1 | CC2 | CC3;
994 case LT: return CC1 | CC3;
995 case GT: return CC2;
996 case LE: return CC0 | CC1 | CC3;
997 case GE: return CC0 | CC2;
998 default: return -1;
999 }
1000 break;
1001
1002 case CCANmode:
1003 switch (GET_CODE (code))
1004 {
1005 case EQ: return CC0;
1006 case NE: return CC1 | CC2 | CC3;
1007 case LT: return CC1;
1008 case GT: return CC2 | CC3;
1009 case LE: return CC0 | CC1;
1010 case GE: return CC0 | CC2 | CC3;
1011 default: return -1;
1012 }
1013 break;
1014
1015 case CCSmode:
1016 switch (GET_CODE (code))
1017 {
1018 case EQ: return CC0;
1019 case NE: return CC1 | CC2 | CC3;
1020 case LT: return CC1;
1021 case GT: return CC2;
1022 case LE: return CC0 | CC1;
1023 case GE: return CC0 | CC2;
1024 case UNORDERED: return CC3;
1025 case ORDERED: return CC0 | CC1 | CC2;
1026 case UNEQ: return CC0 | CC3;
1027 case UNLT: return CC1 | CC3;
1028 case UNGT: return CC2 | CC3;
1029 case UNLE: return CC0 | CC1 | CC3;
1030 case UNGE: return CC0 | CC2 | CC3;
1031 case LTGT: return CC1 | CC2;
1032 default: return -1;
1033 }
1034 break;
1035
1036 case CCSRmode:
1037 switch (GET_CODE (code))
1038 {
1039 case EQ: return CC0;
1040 case NE: return CC2 | CC1 | CC3;
1041 case LT: return CC2;
1042 case GT: return CC1;
1043 case LE: return CC0 | CC2;
1044 case GE: return CC0 | CC1;
1045 case UNORDERED: return CC3;
1046 case ORDERED: return CC0 | CC2 | CC1;
1047 case UNEQ: return CC0 | CC3;
1048 case UNLT: return CC2 | CC3;
1049 case UNGT: return CC1 | CC3;
1050 case UNLE: return CC0 | CC2 | CC3;
1051 case UNGE: return CC0 | CC1 | CC3;
1052 case LTGT: return CC2 | CC1;
1053 default: return -1;
1054 }
1055 break;
1056
1057 default:
1058 return -1;
1059 }
1060 }
1061
1062
1063 /* Return branch condition mask to implement a compare and branch
1064 specified by CODE. Return -1 for invalid comparisons. */
1065
1066 int
1067 s390_compare_and_branch_condition_mask (rtx code)
1068 {
1069 const int CC0 = 1 << 3;
1070 const int CC1 = 1 << 2;
1071 const int CC2 = 1 << 1;
1072
1073 switch (GET_CODE (code))
1074 {
1075 case EQ:
1076 return CC0;
1077 case NE:
1078 return CC1 | CC2;
1079 case LT:
1080 case LTU:
1081 return CC1;
1082 case GT:
1083 case GTU:
1084 return CC2;
1085 case LE:
1086 case LEU:
1087 return CC0 | CC1;
1088 case GE:
1089 case GEU:
1090 return CC0 | CC2;
1091 default:
1092 gcc_unreachable ();
1093 }
1094 return -1;
1095 }
1096
1097 /* If INV is false, return assembler mnemonic string to implement
1098 a branch specified by CODE. If INV is true, return mnemonic
1099 for the corresponding inverted branch. */
1100
1101 static const char *
1102 s390_branch_condition_mnemonic (rtx code, int inv)
1103 {
1104 int mask;
1105
1106 static const char *const mnemonic[16] =
1107 {
1108 NULL, "o", "h", "nle",
1109 "l", "nhe", "lh", "ne",
1110 "e", "nlh", "he", "nl",
1111 "le", "nh", "no", NULL
1112 };
1113
1114 if (GET_CODE (XEXP (code, 0)) == REG
1115 && REGNO (XEXP (code, 0)) == CC_REGNUM
1116 && XEXP (code, 1) == const0_rtx)
1117 mask = s390_branch_condition_mask (code);
1118 else
1119 mask = s390_compare_and_branch_condition_mask (code);
1120
1121 gcc_assert (mask >= 0);
1122
1123 if (inv)
1124 mask ^= 15;
1125
1126 gcc_assert (mask >= 1 && mask <= 14);
1127
1128 return mnemonic[mask];
1129 }
1130
1131 /* Return the part of op which has a value different from def.
1132 The size of the part is determined by mode.
1133 Use this function only if you already know that op really
1134 contains such a part. */
1135
1136 unsigned HOST_WIDE_INT
1137 s390_extract_part (rtx op, enum machine_mode mode, int def)
1138 {
1139 unsigned HOST_WIDE_INT value = 0;
1140 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1141 int part_bits = GET_MODE_BITSIZE (mode);
1142 unsigned HOST_WIDE_INT part_mask
1143 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1144 int i;
1145
1146 for (i = 0; i < max_parts; i++)
1147 {
1148 if (i == 0)
1149 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1150 else
1151 value >>= part_bits;
1152
1153 if ((value & part_mask) != (def & part_mask))
1154 return value & part_mask;
1155 }
1156
1157 gcc_unreachable ();
1158 }
1159
1160 /* If OP is an integer constant of mode MODE with exactly one
1161 part of mode PART_MODE unequal to DEF, return the number of that
1162 part. Otherwise, return -1. */
1163
1164 int
1165 s390_single_part (rtx op,
1166 enum machine_mode mode,
1167 enum machine_mode part_mode,
1168 int def)
1169 {
1170 unsigned HOST_WIDE_INT value = 0;
1171 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1172 unsigned HOST_WIDE_INT part_mask
1173 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1174 int i, part = -1;
1175
1176 if (GET_CODE (op) != CONST_INT)
1177 return -1;
1178
1179 for (i = 0; i < n_parts; i++)
1180 {
1181 if (i == 0)
1182 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1183 else
1184 value >>= GET_MODE_BITSIZE (part_mode);
1185
1186 if ((value & part_mask) != (def & part_mask))
1187 {
1188 if (part != -1)
1189 return -1;
1190 else
1191 part = i;
1192 }
1193 }
1194 return part == -1 ? -1 : n_parts - 1 - part;
1195 }
1196
1197 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1198 bits and no other bits are set in IN. POS and LENGTH can be used
1199 to obtain the start position and the length of the bitfield.
1200
1201 POS gives the position of the first bit of the bitfield counting
1202 from the lowest order bit starting with zero. In order to use this
1203 value for S/390 instructions this has to be converted to "bits big
1204 endian" style. */
1205
1206 bool
1207 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1208 int *pos, int *length)
1209 {
1210 int tmp_pos = 0;
1211 int tmp_length = 0;
1212 int i;
1213 unsigned HOST_WIDE_INT mask = 1ULL;
1214 bool contiguous = false;
1215
1216 for (i = 0; i < size; mask <<= 1, i++)
1217 {
1218 if (contiguous)
1219 {
1220 if (mask & in)
1221 tmp_length++;
1222 else
1223 break;
1224 }
1225 else
1226 {
1227 if (mask & in)
1228 {
1229 contiguous = true;
1230 tmp_length++;
1231 }
1232 else
1233 tmp_pos++;
1234 }
1235 }
1236
1237 if (!tmp_length)
1238 return false;
1239
1240 /* Calculate a mask for all bits beyond the contiguous bits. */
1241 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1242
1243 if (mask & in)
1244 return false;
1245
1246 if (tmp_length + tmp_pos - 1 > size)
1247 return false;
1248
1249 if (length)
1250 *length = tmp_length;
1251
1252 if (pos)
1253 *pos = tmp_pos;
1254
1255 return true;
1256 }
1257
1258 /* Check whether we can (and want to) split a double-word
1259 move in mode MODE from SRC to DST into two single-word
1260 moves, moving the subword FIRST_SUBWORD first. */
1261
1262 bool
1263 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1264 {
1265 /* Floating point registers cannot be split. */
1266 if (FP_REG_P (src) || FP_REG_P (dst))
1267 return false;
1268
1269 /* We don't need to split if operands are directly accessible. */
1270 if (s_operand (src, mode) || s_operand (dst, mode))
1271 return false;
1272
1273 /* Non-offsettable memory references cannot be split. */
1274 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1275 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1276 return false;
1277
1278 /* Moving the first subword must not clobber a register
1279 needed to move the second subword. */
1280 if (register_operand (dst, mode))
1281 {
1282 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1283 if (reg_overlap_mentioned_p (subreg, src))
1284 return false;
1285 }
1286
1287 return true;
1288 }
1289
1290 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1291 and [MEM2, MEM2 + SIZE] do overlap and false
1292 otherwise. */
1293
1294 bool
1295 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1296 {
1297 rtx addr1, addr2, addr_delta;
1298 HOST_WIDE_INT delta;
1299
1300 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1301 return true;
1302
1303 if (size == 0)
1304 return false;
1305
1306 addr1 = XEXP (mem1, 0);
1307 addr2 = XEXP (mem2, 0);
1308
1309 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1310
1311 /* This overlapping check is used by peepholes merging memory block operations.
1312 Overlapping operations would otherwise be recognized by the S/390 hardware
1313 and would fall back to a slower implementation. Allowing overlapping
1314 operations would lead to slow code but not to wrong code. Therefore we are
1315 somewhat optimistic if we cannot prove that the memory blocks are
1316 overlapping.
1317 That's why we return false here although this may accept operations on
1318 overlapping memory areas. */
1319 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1320 return false;
1321
1322 delta = INTVAL (addr_delta);
1323
1324 if (delta == 0
1325 || (delta > 0 && delta < size)
1326 || (delta < 0 && -delta < size))
1327 return true;
1328
1329 return false;
1330 }
1331
1332 /* Check whether the address of memory reference MEM2 equals exactly
1333 the address of memory reference MEM1 plus DELTA. Return true if
1334 we can prove this to be the case, false otherwise. */
1335
1336 bool
1337 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1338 {
1339 rtx addr1, addr2, addr_delta;
1340
1341 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1342 return false;
1343
1344 addr1 = XEXP (mem1, 0);
1345 addr2 = XEXP (mem2, 0);
1346
1347 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1348 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1349 return false;
1350
1351 return true;
1352 }
1353
1354 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1355
1356 void
1357 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1358 rtx *operands)
1359 {
1360 enum machine_mode wmode = mode;
1361 rtx dst = operands[0];
1362 rtx src1 = operands[1];
1363 rtx src2 = operands[2];
1364 rtx op, clob, tem;
1365
1366 /* If we cannot handle the operation directly, use a temp register. */
1367 if (!s390_logical_operator_ok_p (operands))
1368 dst = gen_reg_rtx (mode);
1369
1370 /* QImode and HImode patterns make sense only if we have a destination
1371 in memory. Otherwise perform the operation in SImode. */
1372 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1373 wmode = SImode;
1374
1375 /* Widen operands if required. */
1376 if (mode != wmode)
1377 {
1378 if (GET_CODE (dst) == SUBREG
1379 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1380 dst = tem;
1381 else if (REG_P (dst))
1382 dst = gen_rtx_SUBREG (wmode, dst, 0);
1383 else
1384 dst = gen_reg_rtx (wmode);
1385
1386 if (GET_CODE (src1) == SUBREG
1387 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1388 src1 = tem;
1389 else if (GET_MODE (src1) != VOIDmode)
1390 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1391
1392 if (GET_CODE (src2) == SUBREG
1393 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1394 src2 = tem;
1395 else if (GET_MODE (src2) != VOIDmode)
1396 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1397 }
1398
1399 /* Emit the instruction. */
1400 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1401 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1402 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1403
1404 /* Fix up the destination if needed. */
1405 if (dst != operands[0])
1406 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1407 }
1408
1409 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1410
1411 bool
1412 s390_logical_operator_ok_p (rtx *operands)
1413 {
1414 /* If the destination operand is in memory, it needs to coincide
1415 with one of the source operands. After reload, it has to be
1416 the first source operand. */
1417 if (GET_CODE (operands[0]) == MEM)
1418 return rtx_equal_p (operands[0], operands[1])
1419 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1420
1421 return true;
1422 }
1423
1424 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1425 operand IMMOP to switch from SS to SI type instructions. */
1426
1427 void
1428 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1429 {
1430 int def = code == AND ? -1 : 0;
1431 HOST_WIDE_INT mask;
1432 int part;
1433
1434 gcc_assert (GET_CODE (*memop) == MEM);
1435 gcc_assert (!MEM_VOLATILE_P (*memop));
1436
1437 mask = s390_extract_part (*immop, QImode, def);
1438 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1439 gcc_assert (part >= 0);
1440
1441 *memop = adjust_address (*memop, QImode, part);
1442 *immop = gen_int_mode (mask, QImode);
1443 }
1444
1445
1446 /* How to allocate a 'struct machine_function'. */
1447
1448 static struct machine_function *
1449 s390_init_machine_status (void)
1450 {
1451 return GGC_CNEW (struct machine_function);
1452 }
1453
1454 /* Change optimizations to be performed, depending on the
1455 optimization level.
1456
1457 LEVEL is the optimization level specified; 2 if `-O2' is
1458 specified, 1 if `-O' is specified, and 0 if neither is specified.
1459
1460 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1461
1462 void
1463 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1464 {
1465 /* ??? There are apparently still problems with -fcaller-saves. */
1466 flag_caller_saves = 0;
1467
1468 /* By default, always emit DWARF-2 unwind info. This allows debugging
1469 without maintaining a stack frame back-chain. */
1470 flag_asynchronous_unwind_tables = 1;
1471
1472 /* Use MVCLE instructions to decrease code size if requested. */
1473 if (size != 0)
1474 target_flags |= MASK_MVCLE;
1475 }
1476
1477 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1478 to the associated processor_type and processor_flags if so. */
1479
1480 static bool
1481 s390_handle_arch_option (const char *arg,
1482 enum processor_type *type,
1483 enum processor_flags *flags)
1484 {
1485 static struct pta
1486 {
1487 const char *const name; /* processor name or nickname. */
1488 const enum processor_type processor;
1489 const enum processor_flags flags;
1490 }
1491 const processor_alias_table[] =
1492 {
1493 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1494 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1495 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1496 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1497 | PF_LONG_DISPLACEMENT},
1498 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1499 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1500 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1501 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1502 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1503 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1504 };
1505 size_t i;
1506
1507 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1508 if (strcmp (arg, processor_alias_table[i].name) == 0)
1509 {
1510 *type = processor_alias_table[i].processor;
1511 *flags = processor_alias_table[i].flags;
1512 return true;
1513 }
1514 return false;
1515 }
1516
1517 /* Implement TARGET_HANDLE_OPTION. */
1518
1519 static bool
1520 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1521 {
1522 switch (code)
1523 {
1524 case OPT_march_:
1525 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1526
1527 case OPT_mstack_guard_:
1528 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1529 return false;
1530 if (exact_log2 (s390_stack_guard) == -1)
1531 error ("stack guard value must be an exact power of 2");
1532 return true;
1533
1534 case OPT_mstack_size_:
1535 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1536 return false;
1537 if (exact_log2 (s390_stack_size) == -1)
1538 error ("stack size must be an exact power of 2");
1539 return true;
1540
1541 case OPT_mtune_:
1542 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1543
1544 case OPT_mwarn_framesize_:
1545 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1546
1547 default:
1548 return true;
1549 }
1550 }
1551
1552 void
1553 override_options (void)
1554 {
1555 /* Set up function hooks. */
1556 init_machine_status = s390_init_machine_status;
1557
1558 /* Architecture mode defaults according to ABI. */
1559 if (!(target_flags_explicit & MASK_ZARCH))
1560 {
1561 if (TARGET_64BIT)
1562 target_flags |= MASK_ZARCH;
1563 else
1564 target_flags &= ~MASK_ZARCH;
1565 }
1566
1567 /* Determine processor architectural level. */
1568 if (!s390_arch_string)
1569 {
1570 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1571 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1572 }
1573
1574 /* Determine processor to tune for. */
1575 if (s390_tune == PROCESSOR_max)
1576 {
1577 s390_tune = s390_arch;
1578 s390_tune_flags = s390_arch_flags;
1579 }
1580
1581 /* Sanity checks. */
1582 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1583 error ("z/Architecture mode not supported on %s", s390_arch_string);
1584 if (TARGET_64BIT && !TARGET_ZARCH)
1585 error ("64-bit ABI not supported in ESA/390 mode");
1586
1587 if (TARGET_HARD_DFP && !TARGET_DFP)
1588 {
1589 if (target_flags_explicit & MASK_HARD_DFP)
1590 {
1591 if (!TARGET_CPU_DFP)
1592 error ("Hardware decimal floating point instructions"
1593 " not available on %s", s390_arch_string);
1594 if (!TARGET_ZARCH)
1595 error ("Hardware decimal floating point instructions"
1596 " not available in ESA/390 mode");
1597 }
1598 else
1599 target_flags &= ~MASK_HARD_DFP;
1600 }
1601
1602 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1603 {
1604 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1605 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1606
1607 target_flags &= ~MASK_HARD_DFP;
1608 }
1609
1610 /* Set processor cost function. */
1611 switch (s390_tune)
1612 {
1613 case PROCESSOR_2084_Z990:
1614 s390_cost = &z990_cost;
1615 break;
1616 case PROCESSOR_2094_Z9_109:
1617 s390_cost = &z9_109_cost;
1618 break;
1619 case PROCESSOR_2097_Z10:
1620 s390_cost = &z10_cost;
1621 break;
1622 default:
1623 s390_cost = &z900_cost;
1624 }
1625
1626 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1627 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1628 "in combination");
1629
1630 if (s390_stack_size)
1631 {
1632 if (s390_stack_guard >= s390_stack_size)
1633 error ("stack size must be greater than the stack guard value");
1634 else if (s390_stack_size > 1 << 16)
1635 error ("stack size must not be greater than 64k");
1636 }
1637 else if (s390_stack_guard)
1638 error ("-mstack-guard implies use of -mstack-size");
1639
1640 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1641 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1642 target_flags |= MASK_LONG_DOUBLE_128;
1643 #endif
1644 }
1645
1646 /* Map for smallest class containing reg regno. */
1647
1648 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1649 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1650 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1651 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1652 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1657 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1658 ACCESS_REGS, ACCESS_REGS
1659 };
1660
1661 /* Return attribute type of insn. */
1662
1663 static enum attr_type
1664 s390_safe_attr_type (rtx insn)
1665 {
1666 if (recog_memoized (insn) >= 0)
1667 return get_attr_type (insn);
1668 else
1669 return TYPE_NONE;
1670 }
1671
1672 /* Return true if DISP is a valid short displacement. */
1673
1674 static bool
1675 s390_short_displacement (rtx disp)
1676 {
1677 /* No displacement is OK. */
1678 if (!disp)
1679 return true;
1680
1681 /* Integer displacement in range. */
1682 if (GET_CODE (disp) == CONST_INT)
1683 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1684
1685 /* GOT offset is not OK, the GOT can be large. */
1686 if (GET_CODE (disp) == CONST
1687 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1688 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1689 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1690 return false;
1691
1692 /* All other symbolic constants are literal pool references,
1693 which are OK as the literal pool must be small. */
1694 if (GET_CODE (disp) == CONST)
1695 return true;
1696
1697 return false;
1698 }
1699
1700 /* Decompose a RTL expression ADDR for a memory address into
1701 its components, returned in OUT.
1702
1703 Returns false if ADDR is not a valid memory address, true
1704 otherwise. If OUT is NULL, don't return the components,
1705 but check for validity only.
1706
1707 Note: Only addresses in canonical form are recognized.
1708 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1709 canonical form so that they will be recognized. */
1710
1711 static int
1712 s390_decompose_address (rtx addr, struct s390_address *out)
1713 {
1714 HOST_WIDE_INT offset = 0;
1715 rtx base = NULL_RTX;
1716 rtx indx = NULL_RTX;
1717 rtx disp = NULL_RTX;
1718 rtx orig_disp;
1719 bool pointer = false;
1720 bool base_ptr = false;
1721 bool indx_ptr = false;
1722 bool literal_pool = false;
1723
1724 /* We may need to substitute the literal pool base register into the address
1725 below. However, at this point we do not know which register is going to
1726 be used as base, so we substitute the arg pointer register. This is going
1727 to be treated as holding a pointer below -- it shouldn't be used for any
1728 other purpose. */
1729 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1730
1731 /* Decompose address into base + index + displacement. */
1732
1733 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1734 base = addr;
1735
1736 else if (GET_CODE (addr) == PLUS)
1737 {
1738 rtx op0 = XEXP (addr, 0);
1739 rtx op1 = XEXP (addr, 1);
1740 enum rtx_code code0 = GET_CODE (op0);
1741 enum rtx_code code1 = GET_CODE (op1);
1742
1743 if (code0 == REG || code0 == UNSPEC)
1744 {
1745 if (code1 == REG || code1 == UNSPEC)
1746 {
1747 indx = op0; /* index + base */
1748 base = op1;
1749 }
1750
1751 else
1752 {
1753 base = op0; /* base + displacement */
1754 disp = op1;
1755 }
1756 }
1757
1758 else if (code0 == PLUS)
1759 {
1760 indx = XEXP (op0, 0); /* index + base + disp */
1761 base = XEXP (op0, 1);
1762 disp = op1;
1763 }
1764
1765 else
1766 {
1767 return false;
1768 }
1769 }
1770
1771 else
1772 disp = addr; /* displacement */
1773
1774 /* Extract integer part of displacement. */
1775 orig_disp = disp;
1776 if (disp)
1777 {
1778 if (GET_CODE (disp) == CONST_INT)
1779 {
1780 offset = INTVAL (disp);
1781 disp = NULL_RTX;
1782 }
1783 else if (GET_CODE (disp) == CONST
1784 && GET_CODE (XEXP (disp, 0)) == PLUS
1785 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1786 {
1787 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1788 disp = XEXP (XEXP (disp, 0), 0);
1789 }
1790 }
1791
1792 /* Strip off CONST here to avoid special case tests later. */
1793 if (disp && GET_CODE (disp) == CONST)
1794 disp = XEXP (disp, 0);
1795
1796 /* We can convert literal pool addresses to
1797 displacements by basing them off the base register. */
1798 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1799 {
1800 /* Either base or index must be free to hold the base register. */
1801 if (!base)
1802 base = fake_pool_base, literal_pool = true;
1803 else if (!indx)
1804 indx = fake_pool_base, literal_pool = true;
1805 else
1806 return false;
1807
1808 /* Mark up the displacement. */
1809 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1810 UNSPEC_LTREL_OFFSET);
1811 }
1812
1813 /* Validate base register. */
1814 if (base)
1815 {
1816 if (GET_CODE (base) == UNSPEC)
1817 switch (XINT (base, 1))
1818 {
1819 case UNSPEC_LTREF:
1820 if (!disp)
1821 disp = gen_rtx_UNSPEC (Pmode,
1822 gen_rtvec (1, XVECEXP (base, 0, 0)),
1823 UNSPEC_LTREL_OFFSET);
1824 else
1825 return false;
1826
1827 base = XVECEXP (base, 0, 1);
1828 break;
1829
1830 case UNSPEC_LTREL_BASE:
1831 if (XVECLEN (base, 0) == 1)
1832 base = fake_pool_base, literal_pool = true;
1833 else
1834 base = XVECEXP (base, 0, 1);
1835 break;
1836
1837 default:
1838 return false;
1839 }
1840
1841 if (!REG_P (base)
1842 || (GET_MODE (base) != SImode
1843 && GET_MODE (base) != Pmode))
1844 return false;
1845
1846 if (REGNO (base) == STACK_POINTER_REGNUM
1847 || REGNO (base) == FRAME_POINTER_REGNUM
1848 || ((reload_completed || reload_in_progress)
1849 && frame_pointer_needed
1850 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1851 || REGNO (base) == ARG_POINTER_REGNUM
1852 || (flag_pic
1853 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1854 pointer = base_ptr = true;
1855
1856 if ((reload_completed || reload_in_progress)
1857 && base == cfun->machine->base_reg)
1858 pointer = base_ptr = literal_pool = true;
1859 }
1860
1861 /* Validate index register. */
1862 if (indx)
1863 {
1864 if (GET_CODE (indx) == UNSPEC)
1865 switch (XINT (indx, 1))
1866 {
1867 case UNSPEC_LTREF:
1868 if (!disp)
1869 disp = gen_rtx_UNSPEC (Pmode,
1870 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1871 UNSPEC_LTREL_OFFSET);
1872 else
1873 return false;
1874
1875 indx = XVECEXP (indx, 0, 1);
1876 break;
1877
1878 case UNSPEC_LTREL_BASE:
1879 if (XVECLEN (indx, 0) == 1)
1880 indx = fake_pool_base, literal_pool = true;
1881 else
1882 indx = XVECEXP (indx, 0, 1);
1883 break;
1884
1885 default:
1886 return false;
1887 }
1888
1889 if (!REG_P (indx)
1890 || (GET_MODE (indx) != SImode
1891 && GET_MODE (indx) != Pmode))
1892 return false;
1893
1894 if (REGNO (indx) == STACK_POINTER_REGNUM
1895 || REGNO (indx) == FRAME_POINTER_REGNUM
1896 || ((reload_completed || reload_in_progress)
1897 && frame_pointer_needed
1898 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1899 || REGNO (indx) == ARG_POINTER_REGNUM
1900 || (flag_pic
1901 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1902 pointer = indx_ptr = true;
1903
1904 if ((reload_completed || reload_in_progress)
1905 && indx == cfun->machine->base_reg)
1906 pointer = indx_ptr = literal_pool = true;
1907 }
1908
1909 /* Prefer to use pointer as base, not index. */
1910 if (base && indx && !base_ptr
1911 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1912 {
1913 rtx tmp = base;
1914 base = indx;
1915 indx = tmp;
1916 }
1917
1918 /* Validate displacement. */
1919 if (!disp)
1920 {
1921 /* If virtual registers are involved, the displacement will change later
1922 anyway as the virtual registers get eliminated. This could make a
1923 valid displacement invalid, but it is more likely to make an invalid
1924 displacement valid, because we sometimes access the register save area
1925 via negative offsets to one of those registers.
1926 Thus we don't check the displacement for validity here. If after
1927 elimination the displacement turns out to be invalid after all,
1928 this is fixed up by reload in any case. */
1929 if (base != arg_pointer_rtx
1930 && indx != arg_pointer_rtx
1931 && base != return_address_pointer_rtx
1932 && indx != return_address_pointer_rtx
1933 && base != frame_pointer_rtx
1934 && indx != frame_pointer_rtx
1935 && base != virtual_stack_vars_rtx
1936 && indx != virtual_stack_vars_rtx)
1937 if (!DISP_IN_RANGE (offset))
1938 return false;
1939 }
1940 else
1941 {
1942 /* All the special cases are pointers. */
1943 pointer = true;
1944
1945 /* In the small-PIC case, the linker converts @GOT
1946 and @GOTNTPOFF offsets to possible displacements. */
1947 if (GET_CODE (disp) == UNSPEC
1948 && (XINT (disp, 1) == UNSPEC_GOT
1949 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1950 && flag_pic == 1)
1951 {
1952 ;
1953 }
1954
1955 /* Accept pool label offsets. */
1956 else if (GET_CODE (disp) == UNSPEC
1957 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1958 ;
1959
1960 /* Accept literal pool references. */
1961 else if (GET_CODE (disp) == UNSPEC
1962 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1963 {
1964 orig_disp = gen_rtx_CONST (Pmode, disp);
1965 if (offset)
1966 {
1967 /* If we have an offset, make sure it does not
1968 exceed the size of the constant pool entry. */
1969 rtx sym = XVECEXP (disp, 0, 0);
1970 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1971 return false;
1972
1973 orig_disp = plus_constant (orig_disp, offset);
1974 }
1975 }
1976
1977 else
1978 return false;
1979 }
1980
1981 if (!base && !indx)
1982 pointer = true;
1983
1984 if (out)
1985 {
1986 out->base = base;
1987 out->indx = indx;
1988 out->disp = orig_disp;
1989 out->pointer = pointer;
1990 out->literal_pool = literal_pool;
1991 }
1992
1993 return true;
1994 }
1995
1996 /* Decompose a RTL expression OP for a shift count into its components,
1997 and return the base register in BASE and the offset in OFFSET.
1998
1999 Return true if OP is a valid shift count, false if not. */
2000
2001 bool
2002 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2003 {
2004 HOST_WIDE_INT off = 0;
2005
2006 /* We can have an integer constant, an address register,
2007 or a sum of the two. */
2008 if (GET_CODE (op) == CONST_INT)
2009 {
2010 off = INTVAL (op);
2011 op = NULL_RTX;
2012 }
2013 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2014 {
2015 off = INTVAL (XEXP (op, 1));
2016 op = XEXP (op, 0);
2017 }
2018 while (op && GET_CODE (op) == SUBREG)
2019 op = SUBREG_REG (op);
2020
2021 if (op && GET_CODE (op) != REG)
2022 return false;
2023
2024 if (offset)
2025 *offset = off;
2026 if (base)
2027 *base = op;
2028
2029 return true;
2030 }
2031
2032
2033 /* Return true if CODE is a valid address without index. */
2034
2035 bool
2036 s390_legitimate_address_without_index_p (rtx op)
2037 {
2038 struct s390_address addr;
2039
2040 if (!s390_decompose_address (XEXP (op, 0), &addr))
2041 return false;
2042 if (addr.indx)
2043 return false;
2044
2045 return true;
2046 }
2047
2048
2049 /* Evaluates constraint strings described by the regular expression
2050 ([A|B](Q|R|S|T))|U|W and returns 1 if OP is a valid operand for the
2051 constraint given in STR, or 0 else. */
2052
2053 int
2054 s390_mem_constraint (const char *str, rtx op)
2055 {
2056 struct s390_address addr;
2057 char c = str[0];
2058
2059 /* Check for offsettable variants of memory constraints. */
2060 if (c == 'A')
2061 {
2062 /* Only accept non-volatile MEMs. */
2063 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2064 return 0;
2065
2066 if ((reload_completed || reload_in_progress)
2067 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2068 return 0;
2069
2070 c = str[1];
2071 }
2072
2073 /* Check for non-literal-pool variants of memory constraints. */
2074 else if (c == 'B')
2075 {
2076 if (GET_CODE (op) != MEM)
2077 return 0;
2078 if (!s390_decompose_address (XEXP (op, 0), &addr))
2079 return 0;
2080 if (addr.literal_pool)
2081 return 0;
2082
2083 c = str[1];
2084 }
2085
2086 switch (c)
2087 {
2088 case 'Q':
2089 if (GET_CODE (op) != MEM)
2090 return 0;
2091 if (!s390_decompose_address (XEXP (op, 0), &addr))
2092 return 0;
2093 if (addr.indx)
2094 return 0;
2095
2096 if (TARGET_LONG_DISPLACEMENT)
2097 {
2098 if (!s390_short_displacement (addr.disp))
2099 return 0;
2100 }
2101 break;
2102
2103 case 'R':
2104 if (GET_CODE (op) != MEM)
2105 return 0;
2106
2107 if (TARGET_LONG_DISPLACEMENT)
2108 {
2109 if (!s390_decompose_address (XEXP (op, 0), &addr))
2110 return 0;
2111 if (!s390_short_displacement (addr.disp))
2112 return 0;
2113 }
2114 break;
2115
2116 case 'S':
2117 if (!TARGET_LONG_DISPLACEMENT)
2118 return 0;
2119 if (GET_CODE (op) != MEM)
2120 return 0;
2121 if (!s390_decompose_address (XEXP (op, 0), &addr))
2122 return 0;
2123 if (addr.indx)
2124 return 0;
2125 if (s390_short_displacement (addr.disp))
2126 return 0;
2127 break;
2128
2129 case 'T':
2130 if (!TARGET_LONG_DISPLACEMENT)
2131 return 0;
2132 if (GET_CODE (op) != MEM)
2133 return 0;
2134 if (!s390_decompose_address (XEXP (op, 0), &addr))
2135 return 0;
2136 if (s390_short_displacement (addr.disp))
2137 return 0;
2138 break;
2139
2140 case 'U':
2141 if (TARGET_LONG_DISPLACEMENT)
2142 {
2143 if (!s390_decompose_address (op, &addr))
2144 return 0;
2145 if (!s390_short_displacement (addr.disp))
2146 return 0;
2147 }
2148 break;
2149
2150 case 'W':
2151 if (!TARGET_LONG_DISPLACEMENT)
2152 return 0;
2153 if (!s390_decompose_address (op, &addr))
2154 return 0;
2155 if (s390_short_displacement (addr.disp))
2156 return 0;
2157 break;
2158
2159 case 'Y':
2160 /* Simply check for the basic form of a shift count. Reload will
2161 take care of making sure we have a proper base register. */
2162 if (!s390_decompose_shift_count (op, NULL, NULL))
2163 return 0;
2164 break;
2165
2166 default:
2167 return 0;
2168 }
2169
2170 return 1;
2171 }
2172
2173
2174
2175 /* Evaluates constraint strings starting with letter O. Input
2176 parameter C is the second letter following the "O" in the constraint
2177 string. Returns 1 if VALUE meets the respective constraint and 0
2178 otherwise. */
2179
2180 int
2181 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2182 {
2183 if (!TARGET_EXTIMM)
2184 return 0;
2185
2186 switch (c)
2187 {
2188 case 's':
2189 return trunc_int_for_mode (value, SImode) == value;
2190
2191 case 'p':
2192 return value == 0
2193 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2194
2195 case 'n':
2196 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2197
2198 default:
2199 gcc_unreachable ();
2200 }
2201 }
2202
2203
2204 /* Evaluates constraint strings starting with letter N. Parameter STR
2205 contains the letters following letter "N" in the constraint string.
2206 Returns true if VALUE matches the constraint. */
2207
2208 int
2209 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2210 {
2211 enum machine_mode mode, part_mode;
2212 int def;
2213 int part, part_goal;
2214
2215
2216 if (str[0] == 'x')
2217 part_goal = -1;
2218 else
2219 part_goal = str[0] - '0';
2220
2221 switch (str[1])
2222 {
2223 case 'Q':
2224 part_mode = QImode;
2225 break;
2226 case 'H':
2227 part_mode = HImode;
2228 break;
2229 case 'S':
2230 part_mode = SImode;
2231 break;
2232 default:
2233 return 0;
2234 }
2235
2236 switch (str[2])
2237 {
2238 case 'H':
2239 mode = HImode;
2240 break;
2241 case 'S':
2242 mode = SImode;
2243 break;
2244 case 'D':
2245 mode = DImode;
2246 break;
2247 default:
2248 return 0;
2249 }
2250
2251 switch (str[3])
2252 {
2253 case '0':
2254 def = 0;
2255 break;
2256 case 'F':
2257 def = -1;
2258 break;
2259 default:
2260 return 0;
2261 }
2262
2263 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2264 return 0;
2265
2266 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2267 if (part < 0)
2268 return 0;
2269 if (part_goal != -1 && part_goal != part)
2270 return 0;
2271
2272 return 1;
2273 }
2274
2275
2276 /* Returns true if the input parameter VALUE is a float zero. */
2277
2278 int
2279 s390_float_const_zero_p (rtx value)
2280 {
2281 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2282 && value == CONST0_RTX (GET_MODE (value)));
2283 }
2284
2285
2286 /* Compute a (partial) cost for rtx X. Return true if the complete
2287 cost has been computed, and false if subexpressions should be
2288 scanned. In either case, *TOTAL contains the cost result.
2289 CODE contains GET_CODE (x), OUTER_CODE contains the code
2290 of the superexpression of x. */
2291
2292 static bool
2293 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2294 bool speed ATTRIBUTE_UNUSED)
2295 {
2296 switch (code)
2297 {
2298 case CONST:
2299 case CONST_INT:
2300 case LABEL_REF:
2301 case SYMBOL_REF:
2302 case CONST_DOUBLE:
2303 case MEM:
2304 *total = 0;
2305 return true;
2306
2307 case ASHIFT:
2308 case ASHIFTRT:
2309 case LSHIFTRT:
2310 case ROTATE:
2311 case ROTATERT:
2312 case AND:
2313 case IOR:
2314 case XOR:
2315 case NEG:
2316 case NOT:
2317 *total = COSTS_N_INSNS (1);
2318 return false;
2319
2320 case PLUS:
2321 case MINUS:
2322 /* Check for multiply and add. */
2323 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2324 && GET_CODE (XEXP (x, 0)) == MULT
2325 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2326 {
2327 /* This is the multiply and add case. */
2328 if (GET_MODE (x) == DFmode)
2329 *total = s390_cost->madbr;
2330 else
2331 *total = s390_cost->maebr;
2332 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2333 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2334 + rtx_cost (XEXP (x, 1), code, speed);
2335 return true; /* Do not do an additional recursive descent. */
2336 }
2337 *total = COSTS_N_INSNS (1);
2338 return false;
2339
2340 case MULT:
2341 switch (GET_MODE (x))
2342 {
2343 case SImode:
2344 {
2345 rtx left = XEXP (x, 0);
2346 rtx right = XEXP (x, 1);
2347 if (GET_CODE (right) == CONST_INT
2348 && CONST_OK_FOR_K (INTVAL (right)))
2349 *total = s390_cost->mhi;
2350 else if (GET_CODE (left) == SIGN_EXTEND)
2351 *total = s390_cost->mh;
2352 else
2353 *total = s390_cost->ms; /* msr, ms, msy */
2354 break;
2355 }
2356 case DImode:
2357 {
2358 rtx left = XEXP (x, 0);
2359 rtx right = XEXP (x, 1);
2360 if (TARGET_64BIT)
2361 {
2362 if (GET_CODE (right) == CONST_INT
2363 && CONST_OK_FOR_K (INTVAL (right)))
2364 *total = s390_cost->mghi;
2365 else if (GET_CODE (left) == SIGN_EXTEND)
2366 *total = s390_cost->msgf;
2367 else
2368 *total = s390_cost->msg; /* msgr, msg */
2369 }
2370 else /* TARGET_31BIT */
2371 {
2372 if (GET_CODE (left) == SIGN_EXTEND
2373 && GET_CODE (right) == SIGN_EXTEND)
2374 /* mulsidi case: mr, m */
2375 *total = s390_cost->m;
2376 else if (GET_CODE (left) == ZERO_EXTEND
2377 && GET_CODE (right) == ZERO_EXTEND
2378 && TARGET_CPU_ZARCH)
2379 /* umulsidi case: ml, mlr */
2380 *total = s390_cost->ml;
2381 else
2382 /* Complex calculation is required. */
2383 *total = COSTS_N_INSNS (40);
2384 }
2385 break;
2386 }
2387 case SFmode:
2388 case DFmode:
2389 *total = s390_cost->mult_df;
2390 break;
2391 case TFmode:
2392 *total = s390_cost->mxbr;
2393 break;
2394 default:
2395 return false;
2396 }
2397 return false;
2398
2399 case UDIV:
2400 case UMOD:
2401 if (GET_MODE (x) == TImode) /* 128 bit division */
2402 *total = s390_cost->dlgr;
2403 else if (GET_MODE (x) == DImode)
2404 {
2405 rtx right = XEXP (x, 1);
2406 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2407 *total = s390_cost->dlr;
2408 else /* 64 by 64 bit division */
2409 *total = s390_cost->dlgr;
2410 }
2411 else if (GET_MODE (x) == SImode) /* 32 bit division */
2412 *total = s390_cost->dlr;
2413 return false;
2414
2415 case DIV:
2416 case MOD:
2417 if (GET_MODE (x) == DImode)
2418 {
2419 rtx right = XEXP (x, 1);
2420 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2421 if (TARGET_64BIT)
2422 *total = s390_cost->dsgfr;
2423 else
2424 *total = s390_cost->dr;
2425 else /* 64 by 64 bit division */
2426 *total = s390_cost->dsgr;
2427 }
2428 else if (GET_MODE (x) == SImode) /* 32 bit division */
2429 *total = s390_cost->dlr;
2430 else if (GET_MODE (x) == SFmode)
2431 {
2432 *total = s390_cost->debr;
2433 }
2434 else if (GET_MODE (x) == DFmode)
2435 {
2436 *total = s390_cost->ddbr;
2437 }
2438 else if (GET_MODE (x) == TFmode)
2439 {
2440 *total = s390_cost->dxbr;
2441 }
2442 return false;
2443
2444 case SQRT:
2445 if (GET_MODE (x) == SFmode)
2446 *total = s390_cost->sqebr;
2447 else if (GET_MODE (x) == DFmode)
2448 *total = s390_cost->sqdbr;
2449 else /* TFmode */
2450 *total = s390_cost->sqxbr;
2451 return false;
2452
2453 case SIGN_EXTEND:
2454 case ZERO_EXTEND:
2455 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2456 || outer_code == PLUS || outer_code == MINUS
2457 || outer_code == COMPARE)
2458 *total = 0;
2459 return false;
2460
2461 case COMPARE:
2462 *total = COSTS_N_INSNS (1);
2463 if (GET_CODE (XEXP (x, 0)) == AND
2464 && GET_CODE (XEXP (x, 1)) == CONST_INT
2465 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2466 {
2467 rtx op0 = XEXP (XEXP (x, 0), 0);
2468 rtx op1 = XEXP (XEXP (x, 0), 1);
2469 rtx op2 = XEXP (x, 1);
2470
2471 if (memory_operand (op0, GET_MODE (op0))
2472 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2473 return true;
2474 if (register_operand (op0, GET_MODE (op0))
2475 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2476 return true;
2477 }
2478 return false;
2479
2480 default:
2481 return false;
2482 }
2483 }
2484
2485 /* Return the cost of an address rtx ADDR. */
2486
2487 static int
2488 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2489 {
2490 struct s390_address ad;
2491 if (!s390_decompose_address (addr, &ad))
2492 return 1000;
2493
2494 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2495 }
2496
2497 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2498 otherwise return 0. */
2499
2500 int
2501 tls_symbolic_operand (rtx op)
2502 {
2503 if (GET_CODE (op) != SYMBOL_REF)
2504 return 0;
2505 return SYMBOL_REF_TLS_MODEL (op);
2506 }
2507 \f
2508 /* Split DImode access register reference REG (on 64-bit) into its constituent
2509 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2510 gen_highpart cannot be used as they assume all registers are word-sized,
2511 while our access registers have only half that size. */
2512
2513 void
2514 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2515 {
2516 gcc_assert (TARGET_64BIT);
2517 gcc_assert (ACCESS_REG_P (reg));
2518 gcc_assert (GET_MODE (reg) == DImode);
2519 gcc_assert (!(REGNO (reg) & 1));
2520
2521 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2522 *hi = gen_rtx_REG (SImode, REGNO (reg));
2523 }
2524
2525 /* Return true if OP contains a symbol reference */
2526
2527 bool
2528 symbolic_reference_mentioned_p (rtx op)
2529 {
2530 const char *fmt;
2531 int i;
2532
2533 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2534 return 1;
2535
2536 fmt = GET_RTX_FORMAT (GET_CODE (op));
2537 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2538 {
2539 if (fmt[i] == 'E')
2540 {
2541 int j;
2542
2543 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2544 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2545 return 1;
2546 }
2547
2548 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2549 return 1;
2550 }
2551
2552 return 0;
2553 }
2554
2555 /* Return true if OP contains a reference to a thread-local symbol. */
2556
2557 bool
2558 tls_symbolic_reference_mentioned_p (rtx op)
2559 {
2560 const char *fmt;
2561 int i;
2562
2563 if (GET_CODE (op) == SYMBOL_REF)
2564 return tls_symbolic_operand (op);
2565
2566 fmt = GET_RTX_FORMAT (GET_CODE (op));
2567 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2568 {
2569 if (fmt[i] == 'E')
2570 {
2571 int j;
2572
2573 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2574 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2575 return true;
2576 }
2577
2578 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2579 return true;
2580 }
2581
2582 return false;
2583 }
2584
2585
2586 /* Return true if OP is a legitimate general operand when
2587 generating PIC code. It is given that flag_pic is on
2588 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2589
2590 int
2591 legitimate_pic_operand_p (rtx op)
2592 {
2593 /* Accept all non-symbolic constants. */
2594 if (!SYMBOLIC_CONST (op))
2595 return 1;
2596
2597 /* Reject everything else; must be handled
2598 via emit_symbolic_move. */
2599 return 0;
2600 }
2601
2602 /* Returns true if the constant value OP is a legitimate general operand.
2603 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2604
2605 int
2606 legitimate_constant_p (rtx op)
2607 {
2608 /* Accept all non-symbolic constants. */
2609 if (!SYMBOLIC_CONST (op))
2610 return 1;
2611
2612 /* Accept immediate LARL operands. */
2613 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2614 return 1;
2615
2616 /* Thread-local symbols are never legal constants. This is
2617 so that emit_call knows that computing such addresses
2618 might require a function call. */
2619 if (TLS_SYMBOLIC_CONST (op))
2620 return 0;
2621
2622 /* In the PIC case, symbolic constants must *not* be
2623 forced into the literal pool. We accept them here,
2624 so that they will be handled by emit_symbolic_move. */
2625 if (flag_pic)
2626 return 1;
2627
2628 /* All remaining non-PIC symbolic constants are
2629 forced into the literal pool. */
2630 return 0;
2631 }
2632
2633 /* Determine if it's legal to put X into the constant pool. This
2634 is not possible if X contains the address of a symbol that is
2635 not constant (TLS) or not known at final link time (PIC). */
2636
2637 static bool
2638 s390_cannot_force_const_mem (rtx x)
2639 {
2640 switch (GET_CODE (x))
2641 {
2642 case CONST_INT:
2643 case CONST_DOUBLE:
2644 /* Accept all non-symbolic constants. */
2645 return false;
2646
2647 case LABEL_REF:
2648 /* Labels are OK iff we are non-PIC. */
2649 return flag_pic != 0;
2650
2651 case SYMBOL_REF:
2652 /* 'Naked' TLS symbol references are never OK,
2653 non-TLS symbols are OK iff we are non-PIC. */
2654 if (tls_symbolic_operand (x))
2655 return true;
2656 else
2657 return flag_pic != 0;
2658
2659 case CONST:
2660 return s390_cannot_force_const_mem (XEXP (x, 0));
2661 case PLUS:
2662 case MINUS:
2663 return s390_cannot_force_const_mem (XEXP (x, 0))
2664 || s390_cannot_force_const_mem (XEXP (x, 1));
2665
2666 case UNSPEC:
2667 switch (XINT (x, 1))
2668 {
2669 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2670 case UNSPEC_LTREL_OFFSET:
2671 case UNSPEC_GOT:
2672 case UNSPEC_GOTOFF:
2673 case UNSPEC_PLTOFF:
2674 case UNSPEC_TLSGD:
2675 case UNSPEC_TLSLDM:
2676 case UNSPEC_NTPOFF:
2677 case UNSPEC_DTPOFF:
2678 case UNSPEC_GOTNTPOFF:
2679 case UNSPEC_INDNTPOFF:
2680 return false;
2681
2682 /* If the literal pool shares the code section, be put
2683 execute template placeholders into the pool as well. */
2684 case UNSPEC_INSN:
2685 return TARGET_CPU_ZARCH;
2686
2687 default:
2688 return true;
2689 }
2690 break;
2691
2692 default:
2693 gcc_unreachable ();
2694 }
2695 }
2696
2697 /* Returns true if the constant value OP is a legitimate general
2698 operand during and after reload. The difference to
2699 legitimate_constant_p is that this function will not accept
2700 a constant that would need to be forced to the literal pool
2701 before it can be used as operand. */
2702
2703 bool
2704 legitimate_reload_constant_p (rtx op)
2705 {
2706 /* Accept la(y) operands. */
2707 if (GET_CODE (op) == CONST_INT
2708 && DISP_IN_RANGE (INTVAL (op)))
2709 return true;
2710
2711 /* Accept l(g)hi/l(g)fi operands. */
2712 if (GET_CODE (op) == CONST_INT
2713 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2714 return true;
2715
2716 /* Accept lliXX operands. */
2717 if (TARGET_ZARCH
2718 && GET_CODE (op) == CONST_INT
2719 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2720 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2721 return true;
2722
2723 if (TARGET_EXTIMM
2724 && GET_CODE (op) == CONST_INT
2725 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2726 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2727 return true;
2728
2729 /* Accept larl operands. */
2730 if (TARGET_CPU_ZARCH
2731 && larl_operand (op, VOIDmode))
2732 return true;
2733
2734 /* Accept lzXX operands. */
2735 if (GET_CODE (op) == CONST_DOUBLE
2736 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2737 return true;
2738
2739 /* Accept double-word operands that can be split. */
2740 if (GET_CODE (op) == CONST_INT
2741 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2742 {
2743 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2744 rtx hi = operand_subword (op, 0, 0, dword_mode);
2745 rtx lo = operand_subword (op, 1, 0, dword_mode);
2746 return legitimate_reload_constant_p (hi)
2747 && legitimate_reload_constant_p (lo);
2748 }
2749
2750 /* Everything else cannot be handled without reload. */
2751 return false;
2752 }
2753
2754 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2755 return the class of reg to actually use. */
2756
2757 enum reg_class
2758 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2759 {
2760 switch (GET_CODE (op))
2761 {
2762 /* Constants we cannot reload must be forced into the
2763 literal pool. */
2764
2765 case CONST_DOUBLE:
2766 case CONST_INT:
2767 if (legitimate_reload_constant_p (op))
2768 return rclass;
2769 else
2770 return NO_REGS;
2771
2772 /* If a symbolic constant or a PLUS is reloaded,
2773 it is most likely being used as an address, so
2774 prefer ADDR_REGS. If 'class' is not a superset
2775 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2776 case PLUS:
2777 case LABEL_REF:
2778 case SYMBOL_REF:
2779 case CONST:
2780 if (reg_class_subset_p (ADDR_REGS, rclass))
2781 return ADDR_REGS;
2782 else
2783 return NO_REGS;
2784
2785 default:
2786 break;
2787 }
2788
2789 return rclass;
2790 }
2791
2792 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2793 and return these parts in SYMREF and ADDEND. You can pass NULL in
2794 SYMREF and/or ADDEND if you are not interested in these values. */
2795
2796 static bool
2797 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2798 {
2799 HOST_WIDE_INT tmpaddend = 0;
2800
2801 if (GET_CODE (addr) == CONST)
2802 addr = XEXP (addr, 0);
2803
2804 if (GET_CODE (addr) == PLUS)
2805 {
2806 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2807 && CONST_INT_P (XEXP (addr, 1)))
2808 {
2809 tmpaddend = INTVAL (XEXP (addr, 1));
2810 addr = XEXP (addr, 0);
2811 }
2812 else
2813 return false;
2814 }
2815 else
2816 if (GET_CODE (addr) != SYMBOL_REF)
2817 return false;
2818
2819 if (symref)
2820 *symref = addr;
2821 if (addend)
2822 *addend = tmpaddend;
2823
2824 return true;
2825 }
2826
2827 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2828 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2829 aligned. */
2830
2831 bool
2832 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2833 {
2834 HOST_WIDE_INT addend;
2835 rtx symref;
2836
2837 if (!s390_symref_operand_p (addr, &symref, &addend))
2838 return false;
2839
2840 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2841 && !(addend & (alignment - 1)));
2842 }
2843
2844 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2845 operand SCRATCH is used to reload the even part of the address and
2846 adding one. */
2847
2848 void
2849 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2850 {
2851 HOST_WIDE_INT addend;
2852 rtx symref;
2853
2854 if (!s390_symref_operand_p (addr, &symref, &addend))
2855 gcc_unreachable ();
2856
2857 if (!(addend & 1))
2858 /* Easy case. The addend is even so larl will do fine. */
2859 emit_move_insn (reg, addr);
2860 else
2861 {
2862 /* We can leave the scratch register untouched if the target
2863 register is a valid base register. */
2864 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2865 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2866 scratch = reg;
2867
2868 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2869 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2870
2871 if (addend != 1)
2872 emit_move_insn (scratch,
2873 gen_rtx_CONST (Pmode,
2874 gen_rtx_PLUS (Pmode, symref,
2875 GEN_INT (addend - 1))));
2876 else
2877 emit_move_insn (scratch, symref);
2878
2879 /* Increment the address using la in order to avoid clobbering cc. */
2880 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2881 }
2882 }
2883
2884 /* Generate what is necessary to move between REG and MEM using
2885 SCRATCH. The direction is given by TOMEM. */
2886
2887 void
2888 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2889 {
2890 /* Reload might have pulled a constant out of the literal pool.
2891 Force it back in. */
2892 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2893 || GET_CODE (mem) == CONST)
2894 mem = force_const_mem (GET_MODE (reg), mem);
2895
2896 gcc_assert (MEM_P (mem));
2897
2898 /* For a load from memory we can leave the scratch register
2899 untouched if the target register is a valid base register. */
2900 if (!tomem
2901 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2902 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2903 && GET_MODE (reg) == GET_MODE (scratch))
2904 scratch = reg;
2905
2906 /* Load address into scratch register. Since we can't have a
2907 secondary reload for a secondary reload we have to cover the case
2908 where larl would need a secondary reload here as well. */
2909 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2910
2911 /* Now we can use a standard load/store to do the move. */
2912 if (tomem)
2913 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2914 else
2915 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2916 }
2917
2918 /* Inform reload about cases where moving X with a mode MODE to a register in
2919 RCLASS requires an extra scratch or immediate register. Return the class
2920 needed for the immediate register. */
2921
2922 static enum reg_class
2923 s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2924 enum machine_mode mode, secondary_reload_info *sri)
2925 {
2926 /* Intermediate register needed. */
2927 if (reg_classes_intersect_p (CC_REGS, rclass))
2928 return GENERAL_REGS;
2929
2930 if (TARGET_Z10)
2931 {
2932 /* On z10 several optimizer steps may generate larl operands with
2933 an odd addend. */
2934 if (in_p
2935 && s390_symref_operand_p (x, NULL, NULL)
2936 && mode == Pmode
2937 && !s390_check_symref_alignment (x, 2))
2938 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2939 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2940
2941 /* On z10 we need a scratch register when moving QI, TI or floating
2942 point mode values from or to a memory location with a SYMBOL_REF
2943 or if the symref addend of a SI or DI move is not aligned to the
2944 width of the access. */
2945 if (MEM_P (x)
2946 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2947 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2948 || (!TARGET_64BIT && mode == DImode)
2949 || ((mode == HImode || mode == SImode || mode == DImode)
2950 && (!s390_check_symref_alignment (XEXP (x, 0),
2951 GET_MODE_SIZE (mode))))))
2952 {
2953 #define __SECONDARY_RELOAD_CASE(M,m) \
2954 case M##mode: \
2955 if (TARGET_64BIT) \
2956 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2957 CODE_FOR_reload##m##di_tomem_z10; \
2958 else \
2959 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
2960 CODE_FOR_reload##m##si_tomem_z10; \
2961 break;
2962
2963 switch (GET_MODE (x))
2964 {
2965 __SECONDARY_RELOAD_CASE (QI, qi);
2966 __SECONDARY_RELOAD_CASE (HI, hi);
2967 __SECONDARY_RELOAD_CASE (SI, si);
2968 __SECONDARY_RELOAD_CASE (DI, di);
2969 __SECONDARY_RELOAD_CASE (TI, ti);
2970 __SECONDARY_RELOAD_CASE (SF, sf);
2971 __SECONDARY_RELOAD_CASE (DF, df);
2972 __SECONDARY_RELOAD_CASE (TF, tf);
2973 __SECONDARY_RELOAD_CASE (SD, sd);
2974 __SECONDARY_RELOAD_CASE (DD, dd);
2975 __SECONDARY_RELOAD_CASE (TD, td);
2976
2977 default:
2978 gcc_unreachable ();
2979 }
2980 #undef __SECONDARY_RELOAD_CASE
2981 }
2982 }
2983
2984 /* We need a scratch register when loading a PLUS expression which
2985 is not a legitimate operand of the LOAD ADDRESS instruction. */
2986 if (in_p && s390_plus_operand (x, mode))
2987 sri->icode = (TARGET_64BIT ?
2988 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
2989
2990 /* Performing a multiword move from or to memory we have to make sure the
2991 second chunk in memory is addressable without causing a displacement
2992 overflow. If that would be the case we calculate the address in
2993 a scratch register. */
2994 if (MEM_P (x)
2995 && GET_CODE (XEXP (x, 0)) == PLUS
2996 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2997 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
2998 + GET_MODE_SIZE (mode) - 1))
2999 {
3000 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3001 in a s_operand address since we may fallback to lm/stm. So we only
3002 have to care about overflows in the b+i+d case. */
3003 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3004 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3005 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3006 /* For FP_REGS no lm/stm is available so this check is triggered
3007 for displacement overflows in b+i+d and b+d like addresses. */
3008 || (reg_classes_intersect_p (FP_REGS, rclass)
3009 && s390_class_max_nregs (FP_REGS, mode) > 1))
3010 {
3011 if (in_p)
3012 sri->icode = (TARGET_64BIT ?
3013 CODE_FOR_reloaddi_nonoffmem_in :
3014 CODE_FOR_reloadsi_nonoffmem_in);
3015 else
3016 sri->icode = (TARGET_64BIT ?
3017 CODE_FOR_reloaddi_nonoffmem_out :
3018 CODE_FOR_reloadsi_nonoffmem_out);
3019 }
3020 }
3021
3022 /* A scratch address register is needed when a symbolic constant is
3023 copied to r0 compiling with -fPIC. In other cases the target
3024 register might be used as temporary (see legitimize_pic_address). */
3025 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3026 sri->icode = (TARGET_64BIT ?
3027 CODE_FOR_reloaddi_PIC_addr :
3028 CODE_FOR_reloadsi_PIC_addr);
3029
3030 /* Either scratch or no register needed. */
3031 return NO_REGS;
3032 }
3033
3034 /* Generate code to load SRC, which is PLUS that is not a
3035 legitimate operand for the LA instruction, into TARGET.
3036 SCRATCH may be used as scratch register. */
3037
3038 void
3039 s390_expand_plus_operand (rtx target, rtx src,
3040 rtx scratch)
3041 {
3042 rtx sum1, sum2;
3043 struct s390_address ad;
3044
3045 /* src must be a PLUS; get its two operands. */
3046 gcc_assert (GET_CODE (src) == PLUS);
3047 gcc_assert (GET_MODE (src) == Pmode);
3048
3049 /* Check if any of the two operands is already scheduled
3050 for replacement by reload. This can happen e.g. when
3051 float registers occur in an address. */
3052 sum1 = find_replacement (&XEXP (src, 0));
3053 sum2 = find_replacement (&XEXP (src, 1));
3054 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3055
3056 /* If the address is already strictly valid, there's nothing to do. */
3057 if (!s390_decompose_address (src, &ad)
3058 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3059 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3060 {
3061 /* Otherwise, one of the operands cannot be an address register;
3062 we reload its value into the scratch register. */
3063 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3064 {
3065 emit_move_insn (scratch, sum1);
3066 sum1 = scratch;
3067 }
3068 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3069 {
3070 emit_move_insn (scratch, sum2);
3071 sum2 = scratch;
3072 }
3073
3074 /* According to the way these invalid addresses are generated
3075 in reload.c, it should never happen (at least on s390) that
3076 *neither* of the PLUS components, after find_replacements
3077 was applied, is an address register. */
3078 if (sum1 == scratch && sum2 == scratch)
3079 {
3080 debug_rtx (src);
3081 gcc_unreachable ();
3082 }
3083
3084 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3085 }
3086
3087 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3088 is only ever performed on addresses, so we can mark the
3089 sum as legitimate for LA in any case. */
3090 s390_load_address (target, src);
3091 }
3092
3093
3094 /* Return true if ADDR is a valid memory address.
3095 STRICT specifies whether strict register checking applies. */
3096
3097 bool
3098 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3099 {
3100 struct s390_address ad;
3101
3102 if (TARGET_Z10
3103 && larl_operand (addr, VOIDmode)
3104 && (mode == VOIDmode
3105 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3106 return true;
3107
3108 if (!s390_decompose_address (addr, &ad))
3109 return false;
3110
3111 if (strict)
3112 {
3113 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3114 return false;
3115
3116 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3117 return false;
3118 }
3119 else
3120 {
3121 if (ad.base
3122 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3123 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3124 return false;
3125
3126 if (ad.indx
3127 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3128 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3129 return false;
3130 }
3131 return true;
3132 }
3133
3134 /* Return true if OP is a valid operand for the LA instruction.
3135 In 31-bit, we need to prove that the result is used as an
3136 address, as LA performs only a 31-bit addition. */
3137
3138 bool
3139 legitimate_la_operand_p (rtx op)
3140 {
3141 struct s390_address addr;
3142 if (!s390_decompose_address (op, &addr))
3143 return false;
3144
3145 return (TARGET_64BIT || addr.pointer);
3146 }
3147
3148 /* Return true if it is valid *and* preferable to use LA to
3149 compute the sum of OP1 and OP2. */
3150
3151 bool
3152 preferred_la_operand_p (rtx op1, rtx op2)
3153 {
3154 struct s390_address addr;
3155
3156 if (op2 != const0_rtx)
3157 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3158
3159 if (!s390_decompose_address (op1, &addr))
3160 return false;
3161 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3162 return false;
3163 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3164 return false;
3165
3166 if (!TARGET_64BIT && !addr.pointer)
3167 return false;
3168
3169 if (addr.pointer)
3170 return true;
3171
3172 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3173 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3174 return true;
3175
3176 return false;
3177 }
3178
3179 /* Emit a forced load-address operation to load SRC into DST.
3180 This will use the LOAD ADDRESS instruction even in situations
3181 where legitimate_la_operand_p (SRC) returns false. */
3182
3183 void
3184 s390_load_address (rtx dst, rtx src)
3185 {
3186 if (TARGET_64BIT)
3187 emit_move_insn (dst, src);
3188 else
3189 emit_insn (gen_force_la_31 (dst, src));
3190 }
3191
3192 /* Return a legitimate reference for ORIG (an address) using the
3193 register REG. If REG is 0, a new pseudo is generated.
3194
3195 There are two types of references that must be handled:
3196
3197 1. Global data references must load the address from the GOT, via
3198 the PIC reg. An insn is emitted to do this load, and the reg is
3199 returned.
3200
3201 2. Static data references, constant pool addresses, and code labels
3202 compute the address as an offset from the GOT, whose base is in
3203 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3204 differentiate them from global data objects. The returned
3205 address is the PIC reg + an unspec constant.
3206
3207 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
3208 reg also appears in the address. */
3209
3210 rtx
3211 legitimize_pic_address (rtx orig, rtx reg)
3212 {
3213 rtx addr = orig;
3214 rtx new_rtx = orig;
3215 rtx base;
3216
3217 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3218
3219 if (GET_CODE (addr) == LABEL_REF
3220 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3221 {
3222 /* This is a local symbol. */
3223 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3224 {
3225 /* Access local symbols PC-relative via LARL.
3226 This is the same as in the non-PIC case, so it is
3227 handled automatically ... */
3228 }
3229 else
3230 {
3231 /* Access local symbols relative to the GOT. */
3232
3233 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3234
3235 if (reload_in_progress || reload_completed)
3236 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3237
3238 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3239 addr = gen_rtx_CONST (Pmode, addr);
3240 addr = force_const_mem (Pmode, addr);
3241 emit_move_insn (temp, addr);
3242
3243 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3244 if (reg != 0)
3245 {
3246 s390_load_address (reg, new_rtx);
3247 new_rtx = reg;
3248 }
3249 }
3250 }
3251 else if (GET_CODE (addr) == SYMBOL_REF)
3252 {
3253 if (reg == 0)
3254 reg = gen_reg_rtx (Pmode);
3255
3256 if (flag_pic == 1)
3257 {
3258 /* Assume GOT offset < 4k. This is handled the same way
3259 in both 31- and 64-bit code (@GOT). */
3260
3261 if (reload_in_progress || reload_completed)
3262 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3263
3264 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3265 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3266 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3267 new_rtx = gen_const_mem (Pmode, new_rtx);
3268 emit_move_insn (reg, new_rtx);
3269 new_rtx = reg;
3270 }
3271 else if (TARGET_CPU_ZARCH)
3272 {
3273 /* If the GOT offset might be >= 4k, we determine the position
3274 of the GOT entry via a PC-relative LARL (@GOTENT). */
3275
3276 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3277
3278 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3279 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3280
3281 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3282 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3283 emit_move_insn (temp, new_rtx);
3284
3285 new_rtx = gen_const_mem (Pmode, temp);
3286 emit_move_insn (reg, new_rtx);
3287 new_rtx = reg;
3288 }
3289 else
3290 {
3291 /* If the GOT offset might be >= 4k, we have to load it
3292 from the literal pool (@GOT). */
3293
3294 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3295
3296 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3297 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3298
3299 if (reload_in_progress || reload_completed)
3300 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3301
3302 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3303 addr = gen_rtx_CONST (Pmode, addr);
3304 addr = force_const_mem (Pmode, addr);
3305 emit_move_insn (temp, addr);
3306
3307 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3308 new_rtx = gen_const_mem (Pmode, new_rtx);
3309 emit_move_insn (reg, new_rtx);
3310 new_rtx = reg;
3311 }
3312 }
3313 else
3314 {
3315 if (GET_CODE (addr) == CONST)
3316 {
3317 addr = XEXP (addr, 0);
3318 if (GET_CODE (addr) == UNSPEC)
3319 {
3320 gcc_assert (XVECLEN (addr, 0) == 1);
3321 switch (XINT (addr, 1))
3322 {
3323 /* If someone moved a GOT-relative UNSPEC
3324 out of the literal pool, force them back in. */
3325 case UNSPEC_GOTOFF:
3326 case UNSPEC_PLTOFF:
3327 new_rtx = force_const_mem (Pmode, orig);
3328 break;
3329
3330 /* @GOT is OK as is if small. */
3331 case UNSPEC_GOT:
3332 if (flag_pic == 2)
3333 new_rtx = force_const_mem (Pmode, orig);
3334 break;
3335
3336 /* @GOTENT is OK as is. */
3337 case UNSPEC_GOTENT:
3338 break;
3339
3340 /* @PLT is OK as is on 64-bit, must be converted to
3341 GOT-relative @PLTOFF on 31-bit. */
3342 case UNSPEC_PLT:
3343 if (!TARGET_CPU_ZARCH)
3344 {
3345 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3346
3347 if (reload_in_progress || reload_completed)
3348 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3349
3350 addr = XVECEXP (addr, 0, 0);
3351 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3352 UNSPEC_PLTOFF);
3353 addr = gen_rtx_CONST (Pmode, addr);
3354 addr = force_const_mem (Pmode, addr);
3355 emit_move_insn (temp, addr);
3356
3357 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3358 if (reg != 0)
3359 {
3360 s390_load_address (reg, new_rtx);
3361 new_rtx = reg;
3362 }
3363 }
3364 break;
3365
3366 /* Everything else cannot happen. */
3367 default:
3368 gcc_unreachable ();
3369 }
3370 }
3371 else
3372 gcc_assert (GET_CODE (addr) == PLUS);
3373 }
3374 if (GET_CODE (addr) == PLUS)
3375 {
3376 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3377
3378 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3379 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3380
3381 /* Check first to see if this is a constant offset
3382 from a local symbol reference. */
3383 if ((GET_CODE (op0) == LABEL_REF
3384 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3385 && GET_CODE (op1) == CONST_INT)
3386 {
3387 if (TARGET_CPU_ZARCH
3388 && larl_operand (op0, VOIDmode)
3389 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3390 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3391 {
3392 if (INTVAL (op1) & 1)
3393 {
3394 /* LARL can't handle odd offsets, so emit a
3395 pair of LARL and LA. */
3396 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3397
3398 if (!DISP_IN_RANGE (INTVAL (op1)))
3399 {
3400 HOST_WIDE_INT even = INTVAL (op1) - 1;
3401 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3402 op0 = gen_rtx_CONST (Pmode, op0);
3403 op1 = const1_rtx;
3404 }
3405
3406 emit_move_insn (temp, op0);
3407 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3408
3409 if (reg != 0)
3410 {
3411 s390_load_address (reg, new_rtx);
3412 new_rtx = reg;
3413 }
3414 }
3415 else
3416 {
3417 /* If the offset is even, we can just use LARL.
3418 This will happen automatically. */
3419 }
3420 }
3421 else
3422 {
3423 /* Access local symbols relative to the GOT. */
3424
3425 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3426
3427 if (reload_in_progress || reload_completed)
3428 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3429
3430 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3431 UNSPEC_GOTOFF);
3432 addr = gen_rtx_PLUS (Pmode, addr, op1);
3433 addr = gen_rtx_CONST (Pmode, addr);
3434 addr = force_const_mem (Pmode, addr);
3435 emit_move_insn (temp, addr);
3436
3437 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3438 if (reg != 0)
3439 {
3440 s390_load_address (reg, new_rtx);
3441 new_rtx = reg;
3442 }
3443 }
3444 }
3445
3446 /* Now, check whether it is a GOT relative symbol plus offset
3447 that was pulled out of the literal pool. Force it back in. */
3448
3449 else if (GET_CODE (op0) == UNSPEC
3450 && GET_CODE (op1) == CONST_INT
3451 && XINT (op0, 1) == UNSPEC_GOTOFF)
3452 {
3453 gcc_assert (XVECLEN (op0, 0) == 1);
3454
3455 new_rtx = force_const_mem (Pmode, orig);
3456 }
3457
3458 /* Otherwise, compute the sum. */
3459 else
3460 {
3461 base = legitimize_pic_address (XEXP (addr, 0), reg);
3462 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3463 base == reg ? NULL_RTX : reg);
3464 if (GET_CODE (new_rtx) == CONST_INT)
3465 new_rtx = plus_constant (base, INTVAL (new_rtx));
3466 else
3467 {
3468 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3469 {
3470 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3471 new_rtx = XEXP (new_rtx, 1);
3472 }
3473 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3474 }
3475
3476 if (GET_CODE (new_rtx) == CONST)
3477 new_rtx = XEXP (new_rtx, 0);
3478 new_rtx = force_operand (new_rtx, 0);
3479 }
3480 }
3481 }
3482 return new_rtx;
3483 }
3484
3485 /* Load the thread pointer into a register. */
3486
3487 rtx
3488 s390_get_thread_pointer (void)
3489 {
3490 rtx tp = gen_reg_rtx (Pmode);
3491
3492 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3493 mark_reg_pointer (tp, BITS_PER_WORD);
3494
3495 return tp;
3496 }
3497
3498 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3499 in s390_tls_symbol which always refers to __tls_get_offset.
3500 The returned offset is written to RESULT_REG and an USE rtx is
3501 generated for TLS_CALL. */
3502
3503 static GTY(()) rtx s390_tls_symbol;
3504
3505 static void
3506 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3507 {
3508 rtx insn;
3509
3510 gcc_assert (flag_pic);
3511
3512 if (!s390_tls_symbol)
3513 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3514
3515 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3516 gen_rtx_REG (Pmode, RETURN_REGNUM));
3517
3518 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3519 RTL_CONST_CALL_P (insn) = 1;
3520 }
3521
3522 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3523 this (thread-local) address. REG may be used as temporary. */
3524
3525 static rtx
3526 legitimize_tls_address (rtx addr, rtx reg)
3527 {
3528 rtx new_rtx, tls_call, temp, base, r2, insn;
3529
3530 if (GET_CODE (addr) == SYMBOL_REF)
3531 switch (tls_symbolic_operand (addr))
3532 {
3533 case TLS_MODEL_GLOBAL_DYNAMIC:
3534 start_sequence ();
3535 r2 = gen_rtx_REG (Pmode, 2);
3536 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3537 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3538 new_rtx = force_const_mem (Pmode, new_rtx);
3539 emit_move_insn (r2, new_rtx);
3540 s390_emit_tls_call_insn (r2, tls_call);
3541 insn = get_insns ();
3542 end_sequence ();
3543
3544 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3545 temp = gen_reg_rtx (Pmode);
3546 emit_libcall_block (insn, temp, r2, new_rtx);
3547
3548 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3549 if (reg != 0)
3550 {
3551 s390_load_address (reg, new_rtx);
3552 new_rtx = reg;
3553 }
3554 break;
3555
3556 case TLS_MODEL_LOCAL_DYNAMIC:
3557 start_sequence ();
3558 r2 = gen_rtx_REG (Pmode, 2);
3559 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3560 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3561 new_rtx = force_const_mem (Pmode, new_rtx);
3562 emit_move_insn (r2, new_rtx);
3563 s390_emit_tls_call_insn (r2, tls_call);
3564 insn = get_insns ();
3565 end_sequence ();
3566
3567 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3568 temp = gen_reg_rtx (Pmode);
3569 emit_libcall_block (insn, temp, r2, new_rtx);
3570
3571 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3572 base = gen_reg_rtx (Pmode);
3573 s390_load_address (base, new_rtx);
3574
3575 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3576 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3577 new_rtx = force_const_mem (Pmode, new_rtx);
3578 temp = gen_reg_rtx (Pmode);
3579 emit_move_insn (temp, new_rtx);
3580
3581 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3582 if (reg != 0)
3583 {
3584 s390_load_address (reg, new_rtx);
3585 new_rtx = reg;
3586 }
3587 break;
3588
3589 case TLS_MODEL_INITIAL_EXEC:
3590 if (flag_pic == 1)
3591 {
3592 /* Assume GOT offset < 4k. This is handled the same way
3593 in both 31- and 64-bit code. */
3594
3595 if (reload_in_progress || reload_completed)
3596 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3597
3598 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3599 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3600 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3601 new_rtx = gen_const_mem (Pmode, new_rtx);
3602 temp = gen_reg_rtx (Pmode);
3603 emit_move_insn (temp, new_rtx);
3604 }
3605 else if (TARGET_CPU_ZARCH)
3606 {
3607 /* If the GOT offset might be >= 4k, we determine the position
3608 of the GOT entry via a PC-relative LARL. */
3609
3610 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3611 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3612 temp = gen_reg_rtx (Pmode);
3613 emit_move_insn (temp, new_rtx);
3614
3615 new_rtx = gen_const_mem (Pmode, temp);
3616 temp = gen_reg_rtx (Pmode);
3617 emit_move_insn (temp, new_rtx);
3618 }
3619 else if (flag_pic)
3620 {
3621 /* If the GOT offset might be >= 4k, we have to load it
3622 from the literal pool. */
3623
3624 if (reload_in_progress || reload_completed)
3625 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3626
3627 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3628 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3629 new_rtx = force_const_mem (Pmode, new_rtx);
3630 temp = gen_reg_rtx (Pmode);
3631 emit_move_insn (temp, new_rtx);
3632
3633 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3634 new_rtx = gen_const_mem (Pmode, new_rtx);
3635
3636 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3637 temp = gen_reg_rtx (Pmode);
3638 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3639 }
3640 else
3641 {
3642 /* In position-dependent code, load the absolute address of
3643 the GOT entry from the literal pool. */
3644
3645 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3646 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3647 new_rtx = force_const_mem (Pmode, new_rtx);
3648 temp = gen_reg_rtx (Pmode);
3649 emit_move_insn (temp, new_rtx);
3650
3651 new_rtx = temp;
3652 new_rtx = gen_const_mem (Pmode, new_rtx);
3653 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3654 temp = gen_reg_rtx (Pmode);
3655 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3656 }
3657
3658 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3659 if (reg != 0)
3660 {
3661 s390_load_address (reg, new_rtx);
3662 new_rtx = reg;
3663 }
3664 break;
3665
3666 case TLS_MODEL_LOCAL_EXEC:
3667 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3668 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3669 new_rtx = force_const_mem (Pmode, new_rtx);
3670 temp = gen_reg_rtx (Pmode);
3671 emit_move_insn (temp, new_rtx);
3672
3673 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3674 if (reg != 0)
3675 {
3676 s390_load_address (reg, new_rtx);
3677 new_rtx = reg;
3678 }
3679 break;
3680
3681 default:
3682 gcc_unreachable ();
3683 }
3684
3685 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3686 {
3687 switch (XINT (XEXP (addr, 0), 1))
3688 {
3689 case UNSPEC_INDNTPOFF:
3690 gcc_assert (TARGET_CPU_ZARCH);
3691 new_rtx = addr;
3692 break;
3693
3694 default:
3695 gcc_unreachable ();
3696 }
3697 }
3698
3699 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3700 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3701 {
3702 new_rtx = XEXP (XEXP (addr, 0), 0);
3703 if (GET_CODE (new_rtx) != SYMBOL_REF)
3704 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3705
3706 new_rtx = legitimize_tls_address (new_rtx, reg);
3707 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3708 new_rtx = force_operand (new_rtx, 0);
3709 }
3710
3711 else
3712 gcc_unreachable (); /* for now ... */
3713
3714 return new_rtx;
3715 }
3716
3717 /* Emit insns making the address in operands[1] valid for a standard
3718 move to operands[0]. operands[1] is replaced by an address which
3719 should be used instead of the former RTX to emit the move
3720 pattern. */
3721
3722 void
3723 emit_symbolic_move (rtx *operands)
3724 {
3725 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3726
3727 if (GET_CODE (operands[0]) == MEM)
3728 operands[1] = force_reg (Pmode, operands[1]);
3729 else if (TLS_SYMBOLIC_CONST (operands[1]))
3730 operands[1] = legitimize_tls_address (operands[1], temp);
3731 else if (flag_pic)
3732 operands[1] = legitimize_pic_address (operands[1], temp);
3733 }
3734
3735 /* Try machine-dependent ways of modifying an illegitimate address X
3736 to be legitimate. If we find one, return the new, valid address.
3737
3738 OLDX is the address as it was before break_out_memory_refs was called.
3739 In some cases it is useful to look at this to decide what needs to be done.
3740
3741 MODE is the mode of the operand pointed to by X.
3742
3743 When -fpic is used, special handling is needed for symbolic references.
3744 See comments by legitimize_pic_address for details. */
3745
3746 rtx
3747 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3748 enum machine_mode mode ATTRIBUTE_UNUSED)
3749 {
3750 rtx constant_term = const0_rtx;
3751
3752 if (TLS_SYMBOLIC_CONST (x))
3753 {
3754 x = legitimize_tls_address (x, 0);
3755
3756 if (legitimate_address_p (mode, x, FALSE))
3757 return x;
3758 }
3759 else if (GET_CODE (x) == PLUS
3760 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3761 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3762 {
3763 return x;
3764 }
3765 else if (flag_pic)
3766 {
3767 if (SYMBOLIC_CONST (x)
3768 || (GET_CODE (x) == PLUS
3769 && (SYMBOLIC_CONST (XEXP (x, 0))
3770 || SYMBOLIC_CONST (XEXP (x, 1)))))
3771 x = legitimize_pic_address (x, 0);
3772
3773 if (legitimate_address_p (mode, x, FALSE))
3774 return x;
3775 }
3776
3777 x = eliminate_constant_term (x, &constant_term);
3778
3779 /* Optimize loading of large displacements by splitting them
3780 into the multiple of 4K and the rest; this allows the
3781 former to be CSE'd if possible.
3782
3783 Don't do this if the displacement is added to a register
3784 pointing into the stack frame, as the offsets will
3785 change later anyway. */
3786
3787 if (GET_CODE (constant_term) == CONST_INT
3788 && !TARGET_LONG_DISPLACEMENT
3789 && !DISP_IN_RANGE (INTVAL (constant_term))
3790 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3791 {
3792 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3793 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3794
3795 rtx temp = gen_reg_rtx (Pmode);
3796 rtx val = force_operand (GEN_INT (upper), temp);
3797 if (val != temp)
3798 emit_move_insn (temp, val);
3799
3800 x = gen_rtx_PLUS (Pmode, x, temp);
3801 constant_term = GEN_INT (lower);
3802 }
3803
3804 if (GET_CODE (x) == PLUS)
3805 {
3806 if (GET_CODE (XEXP (x, 0)) == REG)
3807 {
3808 rtx temp = gen_reg_rtx (Pmode);
3809 rtx val = force_operand (XEXP (x, 1), temp);
3810 if (val != temp)
3811 emit_move_insn (temp, val);
3812
3813 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3814 }
3815
3816 else if (GET_CODE (XEXP (x, 1)) == REG)
3817 {
3818 rtx temp = gen_reg_rtx (Pmode);
3819 rtx val = force_operand (XEXP (x, 0), temp);
3820 if (val != temp)
3821 emit_move_insn (temp, val);
3822
3823 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3824 }
3825 }
3826
3827 if (constant_term != const0_rtx)
3828 x = gen_rtx_PLUS (Pmode, x, constant_term);
3829
3830 return x;
3831 }
3832
3833 /* Try a machine-dependent way of reloading an illegitimate address AD
3834 operand. If we find one, push the reload and and return the new address.
3835
3836 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3837 and TYPE is the reload type of the current reload. */
3838
3839 rtx
3840 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3841 int opnum, int type)
3842 {
3843 if (!optimize || TARGET_LONG_DISPLACEMENT)
3844 return NULL_RTX;
3845
3846 if (GET_CODE (ad) == PLUS)
3847 {
3848 rtx tem = simplify_binary_operation (PLUS, Pmode,
3849 XEXP (ad, 0), XEXP (ad, 1));
3850 if (tem)
3851 ad = tem;
3852 }
3853
3854 if (GET_CODE (ad) == PLUS
3855 && GET_CODE (XEXP (ad, 0)) == REG
3856 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3857 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3858 {
3859 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3860 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3861 rtx cst, tem, new_rtx;
3862
3863 cst = GEN_INT (upper);
3864 if (!legitimate_reload_constant_p (cst))
3865 cst = force_const_mem (Pmode, cst);
3866
3867 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3868 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3869
3870 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3871 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3872 opnum, (enum reload_type) type);
3873 return new_rtx;
3874 }
3875
3876 return NULL_RTX;
3877 }
3878
3879 /* Emit code to move LEN bytes from DST to SRC. */
3880
3881 void
3882 s390_expand_movmem (rtx dst, rtx src, rtx len)
3883 {
3884 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3885 {
3886 if (INTVAL (len) > 0)
3887 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3888 }
3889
3890 else if (TARGET_MVCLE)
3891 {
3892 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3893 }
3894
3895 else
3896 {
3897 rtx dst_addr, src_addr, count, blocks, temp;
3898 rtx loop_start_label = gen_label_rtx ();
3899 rtx loop_end_label = gen_label_rtx ();
3900 rtx end_label = gen_label_rtx ();
3901 enum machine_mode mode;
3902
3903 mode = GET_MODE (len);
3904 if (mode == VOIDmode)
3905 mode = Pmode;
3906
3907 dst_addr = gen_reg_rtx (Pmode);
3908 src_addr = gen_reg_rtx (Pmode);
3909 count = gen_reg_rtx (mode);
3910 blocks = gen_reg_rtx (mode);
3911
3912 convert_move (count, len, 1);
3913 emit_cmp_and_jump_insns (count, const0_rtx,
3914 EQ, NULL_RTX, mode, 1, end_label);
3915
3916 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3917 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3918 dst = change_address (dst, VOIDmode, dst_addr);
3919 src = change_address (src, VOIDmode, src_addr);
3920
3921 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3922 if (temp != count)
3923 emit_move_insn (count, temp);
3924
3925 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0);
3926 if (temp != blocks)
3927 emit_move_insn (blocks, temp);
3928
3929 emit_cmp_and_jump_insns (blocks, const0_rtx,
3930 EQ, NULL_RTX, mode, 1, loop_end_label);
3931
3932 emit_label (loop_start_label);
3933
3934 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3935 s390_load_address (dst_addr,
3936 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3937 s390_load_address (src_addr,
3938 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3939
3940 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3941 if (temp != blocks)
3942 emit_move_insn (blocks, temp);
3943
3944 emit_cmp_and_jump_insns (blocks, const0_rtx,
3945 EQ, NULL_RTX, mode, 1, loop_end_label);
3946
3947 emit_jump (loop_start_label);
3948 emit_label (loop_end_label);
3949
3950 emit_insn (gen_movmem_short (dst, src,
3951 convert_to_mode (Pmode, count, 1)));
3952 emit_label (end_label);
3953 }
3954 }
3955
3956 /* Emit code to set LEN bytes at DST to VAL.
3957 Make use of clrmem if VAL is zero. */
3958
3959 void
3960 s390_expand_setmem (rtx dst, rtx len, rtx val)
3961 {
3962 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
3963 return;
3964
3965 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3966
3967 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
3968 {
3969 if (val == const0_rtx && INTVAL (len) <= 256)
3970 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3971 else
3972 {
3973 /* Initialize memory by storing the first byte. */
3974 emit_move_insn (adjust_address (dst, QImode, 0), val);
3975
3976 if (INTVAL (len) > 1)
3977 {
3978 /* Initiate 1 byte overlap move.
3979 The first byte of DST is propagated through DSTP1.
3980 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3981 DST is set to size 1 so the rest of the memory location
3982 does not count as source operand. */
3983 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3984 set_mem_size (dst, const1_rtx);
3985
3986 emit_insn (gen_movmem_short (dstp1, dst,
3987 GEN_INT (INTVAL (len) - 2)));
3988 }
3989 }
3990 }
3991
3992 else if (TARGET_MVCLE)
3993 {
3994 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3995 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3996 }
3997
3998 else
3999 {
4000 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
4001 rtx loop_start_label = gen_label_rtx ();
4002 rtx loop_end_label = gen_label_rtx ();
4003 rtx end_label = gen_label_rtx ();
4004 enum machine_mode mode;
4005
4006 mode = GET_MODE (len);
4007 if (mode == VOIDmode)
4008 mode = Pmode;
4009
4010 dst_addr = gen_reg_rtx (Pmode);
4011 src_addr = gen_reg_rtx (Pmode);
4012 count = gen_reg_rtx (mode);
4013 blocks = gen_reg_rtx (mode);
4014
4015 convert_move (count, len, 1);
4016 emit_cmp_and_jump_insns (count, const0_rtx,
4017 EQ, NULL_RTX, mode, 1, end_label);
4018
4019 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4020 dst = change_address (dst, VOIDmode, dst_addr);
4021
4022 if (val == const0_rtx)
4023 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
4024 else
4025 {
4026 dstp1 = adjust_address (dst, VOIDmode, 1);
4027 set_mem_size (dst, const1_rtx);
4028
4029 /* Initialize memory by storing the first byte. */
4030 emit_move_insn (adjust_address (dst, QImode, 0), val);
4031
4032 /* If count is 1 we are done. */
4033 emit_cmp_and_jump_insns (count, const1_rtx,
4034 EQ, NULL_RTX, mode, 1, end_label);
4035
4036 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
4037 }
4038 if (temp != count)
4039 emit_move_insn (count, temp);
4040
4041 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0);
4042 if (temp != blocks)
4043 emit_move_insn (blocks, temp);
4044
4045 emit_cmp_and_jump_insns (blocks, const0_rtx,
4046 EQ, NULL_RTX, mode, 1, loop_end_label);
4047
4048 emit_label (loop_start_label);
4049
4050 if (val == const0_rtx)
4051 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4052 else
4053 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4054 s390_load_address (dst_addr,
4055 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4056
4057 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
4058 if (temp != blocks)
4059 emit_move_insn (blocks, temp);
4060
4061 emit_cmp_and_jump_insns (blocks, const0_rtx,
4062 EQ, NULL_RTX, mode, 1, loop_end_label);
4063
4064 emit_jump (loop_start_label);
4065 emit_label (loop_end_label);
4066
4067 if (val == const0_rtx)
4068 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4069 else
4070 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4071 emit_label (end_label);
4072 }
4073 }
4074
4075 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4076 and return the result in TARGET. */
4077
4078 void
4079 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4080 {
4081 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4082 rtx tmp;
4083
4084 /* As the result of CMPINT is inverted compared to what we need,
4085 we have to swap the operands. */
4086 tmp = op0; op0 = op1; op1 = tmp;
4087
4088 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4089 {
4090 if (INTVAL (len) > 0)
4091 {
4092 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4093 emit_insn (gen_cmpint (target, ccreg));
4094 }
4095 else
4096 emit_move_insn (target, const0_rtx);
4097 }
4098 else if (TARGET_MVCLE)
4099 {
4100 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4101 emit_insn (gen_cmpint (target, ccreg));
4102 }
4103 else
4104 {
4105 rtx addr0, addr1, count, blocks, temp;
4106 rtx loop_start_label = gen_label_rtx ();
4107 rtx loop_end_label = gen_label_rtx ();
4108 rtx end_label = gen_label_rtx ();
4109 enum machine_mode mode;
4110
4111 mode = GET_MODE (len);
4112 if (mode == VOIDmode)
4113 mode = Pmode;
4114
4115 addr0 = gen_reg_rtx (Pmode);
4116 addr1 = gen_reg_rtx (Pmode);
4117 count = gen_reg_rtx (mode);
4118 blocks = gen_reg_rtx (mode);
4119
4120 convert_move (count, len, 1);
4121 emit_cmp_and_jump_insns (count, const0_rtx,
4122 EQ, NULL_RTX, mode, 1, end_label);
4123
4124 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4125 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4126 op0 = change_address (op0, VOIDmode, addr0);
4127 op1 = change_address (op1, VOIDmode, addr1);
4128
4129 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
4130 if (temp != count)
4131 emit_move_insn (count, temp);
4132
4133 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0);
4134 if (temp != blocks)
4135 emit_move_insn (blocks, temp);
4136
4137 emit_cmp_and_jump_insns (blocks, const0_rtx,
4138 EQ, NULL_RTX, mode, 1, loop_end_label);
4139
4140 emit_label (loop_start_label);
4141
4142 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4143 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4144 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4145 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4146 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4147 emit_jump_insn (temp);
4148
4149 s390_load_address (addr0,
4150 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4151 s390_load_address (addr1,
4152 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4153
4154 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
4155 if (temp != blocks)
4156 emit_move_insn (blocks, temp);
4157
4158 emit_cmp_and_jump_insns (blocks, const0_rtx,
4159 EQ, NULL_RTX, mode, 1, loop_end_label);
4160
4161 emit_jump (loop_start_label);
4162 emit_label (loop_end_label);
4163
4164 emit_insn (gen_cmpmem_short (op0, op1,
4165 convert_to_mode (Pmode, count, 1)));
4166 emit_label (end_label);
4167
4168 emit_insn (gen_cmpint (target, ccreg));
4169 }
4170 }
4171
4172
4173 /* Expand conditional increment or decrement using alc/slb instructions.
4174 Should generate code setting DST to either SRC or SRC + INCREMENT,
4175 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4176 Returns true if successful, false otherwise.
4177
4178 That makes it possible to implement some if-constructs without jumps e.g.:
4179 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4180 unsigned int a, b, c;
4181 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4182 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4183 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4184 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4185
4186 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4187 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4188 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4189 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4190 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4191
4192 bool
4193 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4194 rtx dst, rtx src, rtx increment)
4195 {
4196 enum machine_mode cmp_mode;
4197 enum machine_mode cc_mode;
4198 rtx op_res;
4199 rtx insn;
4200 rtvec p;
4201 int ret;
4202
4203 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4204 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4205 cmp_mode = SImode;
4206 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4207 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4208 cmp_mode = DImode;
4209 else
4210 return false;
4211
4212 /* Try ADD LOGICAL WITH CARRY. */
4213 if (increment == const1_rtx)
4214 {
4215 /* Determine CC mode to use. */
4216 if (cmp_code == EQ || cmp_code == NE)
4217 {
4218 if (cmp_op1 != const0_rtx)
4219 {
4220 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4221 NULL_RTX, 0, OPTAB_WIDEN);
4222 cmp_op1 = const0_rtx;
4223 }
4224
4225 cmp_code = cmp_code == EQ ? LEU : GTU;
4226 }
4227
4228 if (cmp_code == LTU || cmp_code == LEU)
4229 {
4230 rtx tem = cmp_op0;
4231 cmp_op0 = cmp_op1;
4232 cmp_op1 = tem;
4233 cmp_code = swap_condition (cmp_code);
4234 }
4235
4236 switch (cmp_code)
4237 {
4238 case GTU:
4239 cc_mode = CCUmode;
4240 break;
4241
4242 case GEU:
4243 cc_mode = CCL3mode;
4244 break;
4245
4246 default:
4247 return false;
4248 }
4249
4250 /* Emit comparison instruction pattern. */
4251 if (!register_operand (cmp_op0, cmp_mode))
4252 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4253
4254 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4255 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4256 /* We use insn_invalid_p here to add clobbers if required. */
4257 ret = insn_invalid_p (emit_insn (insn));
4258 gcc_assert (!ret);
4259
4260 /* Emit ALC instruction pattern. */
4261 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4262 gen_rtx_REG (cc_mode, CC_REGNUM),
4263 const0_rtx);
4264
4265 if (src != const0_rtx)
4266 {
4267 if (!register_operand (src, GET_MODE (dst)))
4268 src = force_reg (GET_MODE (dst), src);
4269
4270 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4271 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4272 }
4273
4274 p = rtvec_alloc (2);
4275 RTVEC_ELT (p, 0) =
4276 gen_rtx_SET (VOIDmode, dst, op_res);
4277 RTVEC_ELT (p, 1) =
4278 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4279 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4280
4281 return true;
4282 }
4283
4284 /* Try SUBTRACT LOGICAL WITH BORROW. */
4285 if (increment == constm1_rtx)
4286 {
4287 /* Determine CC mode to use. */
4288 if (cmp_code == EQ || cmp_code == NE)
4289 {
4290 if (cmp_op1 != const0_rtx)
4291 {
4292 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4293 NULL_RTX, 0, OPTAB_WIDEN);
4294 cmp_op1 = const0_rtx;
4295 }
4296
4297 cmp_code = cmp_code == EQ ? LEU : GTU;
4298 }
4299
4300 if (cmp_code == GTU || cmp_code == GEU)
4301 {
4302 rtx tem = cmp_op0;
4303 cmp_op0 = cmp_op1;
4304 cmp_op1 = tem;
4305 cmp_code = swap_condition (cmp_code);
4306 }
4307
4308 switch (cmp_code)
4309 {
4310 case LEU:
4311 cc_mode = CCUmode;
4312 break;
4313
4314 case LTU:
4315 cc_mode = CCL3mode;
4316 break;
4317
4318 default:
4319 return false;
4320 }
4321
4322 /* Emit comparison instruction pattern. */
4323 if (!register_operand (cmp_op0, cmp_mode))
4324 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4325
4326 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4327 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4328 /* We use insn_invalid_p here to add clobbers if required. */
4329 ret = insn_invalid_p (emit_insn (insn));
4330 gcc_assert (!ret);
4331
4332 /* Emit SLB instruction pattern. */
4333 if (!register_operand (src, GET_MODE (dst)))
4334 src = force_reg (GET_MODE (dst), src);
4335
4336 op_res = gen_rtx_MINUS (GET_MODE (dst),
4337 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4338 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4339 gen_rtx_REG (cc_mode, CC_REGNUM),
4340 const0_rtx));
4341 p = rtvec_alloc (2);
4342 RTVEC_ELT (p, 0) =
4343 gen_rtx_SET (VOIDmode, dst, op_res);
4344 RTVEC_ELT (p, 1) =
4345 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4346 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4347
4348 return true;
4349 }
4350
4351 return false;
4352 }
4353
4354 /* Expand code for the insv template. Return true if successful. */
4355
4356 bool
4357 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4358 {
4359 int bitsize = INTVAL (op1);
4360 int bitpos = INTVAL (op2);
4361
4362 /* On z10 we can use the risbg instruction to implement insv. */
4363 if (TARGET_Z10
4364 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4365 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4366 {
4367 rtx op;
4368 rtx clobber;
4369
4370 op = gen_rtx_SET (GET_MODE(src),
4371 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4372 src);
4373 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4374 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4375
4376 return true;
4377 }
4378
4379 /* We need byte alignment. */
4380 if (bitsize % BITS_PER_UNIT)
4381 return false;
4382
4383 if (bitpos == 0
4384 && memory_operand (dest, VOIDmode)
4385 && (register_operand (src, word_mode)
4386 || const_int_operand (src, VOIDmode)))
4387 {
4388 /* Emit standard pattern if possible. */
4389 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4390 if (GET_MODE_BITSIZE (mode) == bitsize)
4391 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4392
4393 /* (set (ze (mem)) (const_int)). */
4394 else if (const_int_operand (src, VOIDmode))
4395 {
4396 int size = bitsize / BITS_PER_UNIT;
4397 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4398 GET_MODE_SIZE (word_mode) - size);
4399
4400 dest = adjust_address (dest, BLKmode, 0);
4401 set_mem_size (dest, GEN_INT (size));
4402 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4403 }
4404
4405 /* (set (ze (mem)) (reg)). */
4406 else if (register_operand (src, word_mode))
4407 {
4408 if (bitsize <= GET_MODE_BITSIZE (SImode))
4409 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4410 const0_rtx), src);
4411 else
4412 {
4413 /* Emit st,stcmh sequence. */
4414 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4415 int size = stcmh_width / BITS_PER_UNIT;
4416
4417 emit_move_insn (adjust_address (dest, SImode, size),
4418 gen_lowpart (SImode, src));
4419 set_mem_size (dest, GEN_INT (size));
4420 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4421 (stcmh_width), const0_rtx),
4422 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4423 (GET_MODE_BITSIZE (SImode))));
4424 }
4425 }
4426 else
4427 return false;
4428
4429 return true;
4430 }
4431
4432 /* (set (ze (reg)) (const_int)). */
4433 if (TARGET_ZARCH
4434 && register_operand (dest, word_mode)
4435 && (bitpos % 16) == 0
4436 && (bitsize % 16) == 0
4437 && const_int_operand (src, VOIDmode))
4438 {
4439 HOST_WIDE_INT val = INTVAL (src);
4440 int regpos = bitpos + bitsize;
4441
4442 while (regpos > bitpos)
4443 {
4444 enum machine_mode putmode;
4445 int putsize;
4446
4447 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4448 putmode = SImode;
4449 else
4450 putmode = HImode;
4451
4452 putsize = GET_MODE_BITSIZE (putmode);
4453 regpos -= putsize;
4454 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4455 GEN_INT (putsize),
4456 GEN_INT (regpos)),
4457 gen_int_mode (val, putmode));
4458 val >>= putsize;
4459 }
4460 gcc_assert (regpos == bitpos);
4461 return true;
4462 }
4463
4464 return false;
4465 }
4466
4467 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4468 register that holds VAL of mode MODE shifted by COUNT bits. */
4469
4470 static inline rtx
4471 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4472 {
4473 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4474 NULL_RTX, 1, OPTAB_DIRECT);
4475 return expand_simple_binop (SImode, ASHIFT, val, count,
4476 NULL_RTX, 1, OPTAB_DIRECT);
4477 }
4478
4479 /* Structure to hold the initial parameters for a compare_and_swap operation
4480 in HImode and QImode. */
4481
4482 struct alignment_context
4483 {
4484 rtx memsi; /* SI aligned memory location. */
4485 rtx shift; /* Bit offset with regard to lsb. */
4486 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4487 rtx modemaski; /* ~modemask */
4488 bool aligned; /* True if memory is aligned, false else. */
4489 };
4490
4491 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4492 structure AC for transparent simplifying, if the memory alignment is known
4493 to be at least 32bit. MEM is the memory location for the actual operation
4494 and MODE its mode. */
4495
4496 static void
4497 init_alignment_context (struct alignment_context *ac, rtx mem,
4498 enum machine_mode mode)
4499 {
4500 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4501 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4502
4503 if (ac->aligned)
4504 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4505 else
4506 {
4507 /* Alignment is unknown. */
4508 rtx byteoffset, addr, align;
4509
4510 /* Force the address into a register. */
4511 addr = force_reg (Pmode, XEXP (mem, 0));
4512
4513 /* Align it to SImode. */
4514 align = expand_simple_binop (Pmode, AND, addr,
4515 GEN_INT (-GET_MODE_SIZE (SImode)),
4516 NULL_RTX, 1, OPTAB_DIRECT);
4517 /* Generate MEM. */
4518 ac->memsi = gen_rtx_MEM (SImode, align);
4519 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4520 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4521 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4522
4523 /* Calculate shiftcount. */
4524 byteoffset = expand_simple_binop (Pmode, AND, addr,
4525 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4526 NULL_RTX, 1, OPTAB_DIRECT);
4527 /* As we already have some offset, evaluate the remaining distance. */
4528 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4529 NULL_RTX, 1, OPTAB_DIRECT);
4530
4531 }
4532 /* Shift is the byte count, but we need the bitcount. */
4533 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4534 NULL_RTX, 1, OPTAB_DIRECT);
4535 /* Calculate masks. */
4536 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4537 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4538 NULL_RTX, 1, OPTAB_DIRECT);
4539 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4540 }
4541
4542 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4543 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4544 to set if CMP == MEM.
4545 CMP is never in memory for compare_and_swap_cc because
4546 expand_bool_compare_and_swap puts it into a register for later compare. */
4547
4548 void
4549 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4550 {
4551 struct alignment_context ac;
4552 rtx cmpv, newv, val, resv, cc;
4553 rtx res = gen_reg_rtx (SImode);
4554 rtx csloop = gen_label_rtx ();
4555 rtx csend = gen_label_rtx ();
4556
4557 gcc_assert (register_operand (target, VOIDmode));
4558 gcc_assert (MEM_P (mem));
4559
4560 init_alignment_context (&ac, mem, mode);
4561
4562 /* Shift the values to the correct bit positions. */
4563 if (!(ac.aligned && MEM_P (cmp)))
4564 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4565 if (!(ac.aligned && MEM_P (new_rtx)))
4566 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4567
4568 /* Load full word. Subsequent loads are performed by CS. */
4569 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4570 NULL_RTX, 1, OPTAB_DIRECT);
4571
4572 /* Start CS loop. */
4573 emit_label (csloop);
4574 /* val = "<mem>00..0<mem>"
4575 * cmp = "00..0<cmp>00..0"
4576 * new = "00..0<new>00..0"
4577 */
4578
4579 /* Patch cmp and new with val at correct position. */
4580 if (ac.aligned && MEM_P (cmp))
4581 {
4582 cmpv = force_reg (SImode, val);
4583 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4584 }
4585 else
4586 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4587 NULL_RTX, 1, OPTAB_DIRECT));
4588 if (ac.aligned && MEM_P (new_rtx))
4589 {
4590 newv = force_reg (SImode, val);
4591 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4592 }
4593 else
4594 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4595 NULL_RTX, 1, OPTAB_DIRECT));
4596
4597 /* Jump to end if we're done (likely?). */
4598 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4599 cmpv, newv));
4600
4601 /* Check for changes outside mode. */
4602 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4603 NULL_RTX, 1, OPTAB_DIRECT);
4604 cc = s390_emit_compare (NE, resv, val);
4605 emit_move_insn (val, resv);
4606 /* Loop internal if so. */
4607 s390_emit_jump (csloop, cc);
4608
4609 emit_label (csend);
4610
4611 /* Return the correct part of the bitfield. */
4612 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4613 NULL_RTX, 1, OPTAB_DIRECT), 1);
4614 }
4615
4616 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4617 and VAL the value to play with. If AFTER is true then store the value
4618 MEM holds after the operation, if AFTER is false then store the value MEM
4619 holds before the operation. If TARGET is zero then discard that value, else
4620 store it to TARGET. */
4621
4622 void
4623 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4624 rtx target, rtx mem, rtx val, bool after)
4625 {
4626 struct alignment_context ac;
4627 rtx cmp;
4628 rtx new_rtx = gen_reg_rtx (SImode);
4629 rtx orig = gen_reg_rtx (SImode);
4630 rtx csloop = gen_label_rtx ();
4631
4632 gcc_assert (!target || register_operand (target, VOIDmode));
4633 gcc_assert (MEM_P (mem));
4634
4635 init_alignment_context (&ac, mem, mode);
4636
4637 /* Shift val to the correct bit positions.
4638 Preserve "icm", but prevent "ex icm". */
4639 if (!(ac.aligned && code == SET && MEM_P (val)))
4640 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4641
4642 /* Further preparation insns. */
4643 if (code == PLUS || code == MINUS)
4644 emit_move_insn (orig, val);
4645 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4646 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4647 NULL_RTX, 1, OPTAB_DIRECT);
4648
4649 /* Load full word. Subsequent loads are performed by CS. */
4650 cmp = force_reg (SImode, ac.memsi);
4651
4652 /* Start CS loop. */
4653 emit_label (csloop);
4654 emit_move_insn (new_rtx, cmp);
4655
4656 /* Patch new with val at correct position. */
4657 switch (code)
4658 {
4659 case PLUS:
4660 case MINUS:
4661 val = expand_simple_binop (SImode, code, new_rtx, orig,
4662 NULL_RTX, 1, OPTAB_DIRECT);
4663 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4664 NULL_RTX, 1, OPTAB_DIRECT);
4665 /* FALLTHRU */
4666 case SET:
4667 if (ac.aligned && MEM_P (val))
4668 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4669 else
4670 {
4671 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4672 NULL_RTX, 1, OPTAB_DIRECT);
4673 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4674 NULL_RTX, 1, OPTAB_DIRECT);
4675 }
4676 break;
4677 case AND:
4678 case IOR:
4679 case XOR:
4680 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4681 NULL_RTX, 1, OPTAB_DIRECT);
4682 break;
4683 case MULT: /* NAND */
4684 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4685 NULL_RTX, 1, OPTAB_DIRECT);
4686 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4687 NULL_RTX, 1, OPTAB_DIRECT);
4688 break;
4689 default:
4690 gcc_unreachable ();
4691 }
4692
4693 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4694 ac.memsi, cmp, new_rtx));
4695
4696 /* Return the correct part of the bitfield. */
4697 if (target)
4698 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4699 after ? new_rtx : cmp, ac.shift,
4700 NULL_RTX, 1, OPTAB_DIRECT), 1);
4701 }
4702
4703 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4704 We need to emit DTP-relative relocations. */
4705
4706 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4707
4708 static void
4709 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4710 {
4711 switch (size)
4712 {
4713 case 4:
4714 fputs ("\t.long\t", file);
4715 break;
4716 case 8:
4717 fputs ("\t.quad\t", file);
4718 break;
4719 default:
4720 gcc_unreachable ();
4721 }
4722 output_addr_const (file, x);
4723 fputs ("@DTPOFF", file);
4724 }
4725
4726 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4727 /* Implement TARGET_MANGLE_TYPE. */
4728
4729 static const char *
4730 s390_mangle_type (const_tree type)
4731 {
4732 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4733 && TARGET_LONG_DOUBLE_128)
4734 return "g";
4735
4736 /* For all other types, use normal C++ mangling. */
4737 return NULL;
4738 }
4739 #endif
4740
4741 /* In the name of slightly smaller debug output, and to cater to
4742 general assembler lossage, recognize various UNSPEC sequences
4743 and turn them back into a direct symbol reference. */
4744
4745 static rtx
4746 s390_delegitimize_address (rtx orig_x)
4747 {
4748 rtx x = orig_x, y;
4749
4750 if (GET_CODE (x) != MEM)
4751 return orig_x;
4752
4753 x = XEXP (x, 0);
4754 if (GET_CODE (x) == PLUS
4755 && GET_CODE (XEXP (x, 1)) == CONST
4756 && GET_CODE (XEXP (x, 0)) == REG
4757 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4758 {
4759 y = XEXP (XEXP (x, 1), 0);
4760 if (GET_CODE (y) == UNSPEC
4761 && XINT (y, 1) == UNSPEC_GOT)
4762 return XVECEXP (y, 0, 0);
4763 return orig_x;
4764 }
4765
4766 if (GET_CODE (x) == CONST)
4767 {
4768 y = XEXP (x, 0);
4769 if (GET_CODE (y) == UNSPEC
4770 && XINT (y, 1) == UNSPEC_GOTENT)
4771 return XVECEXP (y, 0, 0);
4772 return orig_x;
4773 }
4774
4775 return orig_x;
4776 }
4777
4778 /* Output operand OP to stdio stream FILE.
4779 OP is an address (register + offset) which is not used to address data;
4780 instead the rightmost bits are interpreted as the value. */
4781
4782 static void
4783 print_shift_count_operand (FILE *file, rtx op)
4784 {
4785 HOST_WIDE_INT offset;
4786 rtx base;
4787
4788 /* Extract base register and offset. */
4789 if (!s390_decompose_shift_count (op, &base, &offset))
4790 gcc_unreachable ();
4791
4792 /* Sanity check. */
4793 if (base)
4794 {
4795 gcc_assert (GET_CODE (base) == REG);
4796 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4797 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4798 }
4799
4800 /* Offsets are constricted to twelve bits. */
4801 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4802 if (base)
4803 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4804 }
4805
4806 /* See 'get_some_local_dynamic_name'. */
4807
4808 static int
4809 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4810 {
4811 rtx x = *px;
4812
4813 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4814 {
4815 x = get_pool_constant (x);
4816 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4817 }
4818
4819 if (GET_CODE (x) == SYMBOL_REF
4820 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4821 {
4822 cfun->machine->some_ld_name = XSTR (x, 0);
4823 return 1;
4824 }
4825
4826 return 0;
4827 }
4828
4829 /* Locate some local-dynamic symbol still in use by this function
4830 so that we can print its name in local-dynamic base patterns. */
4831
4832 static const char *
4833 get_some_local_dynamic_name (void)
4834 {
4835 rtx insn;
4836
4837 if (cfun->machine->some_ld_name)
4838 return cfun->machine->some_ld_name;
4839
4840 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4841 if (INSN_P (insn)
4842 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4843 return cfun->machine->some_ld_name;
4844
4845 gcc_unreachable ();
4846 }
4847
4848 /* Output machine-dependent UNSPECs occurring in address constant X
4849 in assembler syntax to stdio stream FILE. Returns true if the
4850 constant X could be recognized, false otherwise. */
4851
4852 bool
4853 s390_output_addr_const_extra (FILE *file, rtx x)
4854 {
4855 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4856 switch (XINT (x, 1))
4857 {
4858 case UNSPEC_GOTENT:
4859 output_addr_const (file, XVECEXP (x, 0, 0));
4860 fprintf (file, "@GOTENT");
4861 return true;
4862 case UNSPEC_GOT:
4863 output_addr_const (file, XVECEXP (x, 0, 0));
4864 fprintf (file, "@GOT");
4865 return true;
4866 case UNSPEC_GOTOFF:
4867 output_addr_const (file, XVECEXP (x, 0, 0));
4868 fprintf (file, "@GOTOFF");
4869 return true;
4870 case UNSPEC_PLT:
4871 output_addr_const (file, XVECEXP (x, 0, 0));
4872 fprintf (file, "@PLT");
4873 return true;
4874 case UNSPEC_PLTOFF:
4875 output_addr_const (file, XVECEXP (x, 0, 0));
4876 fprintf (file, "@PLTOFF");
4877 return true;
4878 case UNSPEC_TLSGD:
4879 output_addr_const (file, XVECEXP (x, 0, 0));
4880 fprintf (file, "@TLSGD");
4881 return true;
4882 case UNSPEC_TLSLDM:
4883 assemble_name (file, get_some_local_dynamic_name ());
4884 fprintf (file, "@TLSLDM");
4885 return true;
4886 case UNSPEC_DTPOFF:
4887 output_addr_const (file, XVECEXP (x, 0, 0));
4888 fprintf (file, "@DTPOFF");
4889 return true;
4890 case UNSPEC_NTPOFF:
4891 output_addr_const (file, XVECEXP (x, 0, 0));
4892 fprintf (file, "@NTPOFF");
4893 return true;
4894 case UNSPEC_GOTNTPOFF:
4895 output_addr_const (file, XVECEXP (x, 0, 0));
4896 fprintf (file, "@GOTNTPOFF");
4897 return true;
4898 case UNSPEC_INDNTPOFF:
4899 output_addr_const (file, XVECEXP (x, 0, 0));
4900 fprintf (file, "@INDNTPOFF");
4901 return true;
4902 }
4903
4904 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
4905 switch (XINT (x, 1))
4906 {
4907 case UNSPEC_POOL_OFFSET:
4908 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
4909 output_addr_const (file, x);
4910 return true;
4911 }
4912 return false;
4913 }
4914
4915 /* Output address operand ADDR in assembler syntax to
4916 stdio stream FILE. */
4917
4918 void
4919 print_operand_address (FILE *file, rtx addr)
4920 {
4921 struct s390_address ad;
4922
4923 if (s390_symref_operand_p (addr, NULL, NULL))
4924 {
4925 gcc_assert (TARGET_Z10);
4926 output_addr_const (file, addr);
4927 return;
4928 }
4929
4930 if (!s390_decompose_address (addr, &ad)
4931 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4932 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4933 output_operand_lossage ("cannot decompose address");
4934
4935 if (ad.disp)
4936 output_addr_const (file, ad.disp);
4937 else
4938 fprintf (file, "0");
4939
4940 if (ad.base && ad.indx)
4941 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4942 reg_names[REGNO (ad.base)]);
4943 else if (ad.base)
4944 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4945 }
4946
4947 /* Output operand X in assembler syntax to stdio stream FILE.
4948 CODE specified the format flag. The following format flags
4949 are recognized:
4950
4951 'C': print opcode suffix for branch condition.
4952 'D': print opcode suffix for inverse branch condition.
4953 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4954 'G': print the size of the operand in bytes.
4955 'O': print only the displacement of a memory reference.
4956 'R': print only the base register of a memory reference.
4957 'S': print S-type memory reference (base+displacement).
4958 'N': print the second word of a DImode operand.
4959 'M': print the second word of a TImode operand.
4960 'Y': print shift count operand.
4961
4962 'b': print integer X as if it's an unsigned byte.
4963 'c': print integer X as if it's an signed byte.
4964 'x': print integer X as if it's an unsigned halfword.
4965 'h': print integer X as if it's a signed halfword.
4966 'i': print the first nonzero HImode part of X.
4967 'j': print the first HImode part unequal to -1 of X.
4968 'k': print the first nonzero SImode part of X.
4969 'm': print the first SImode part unequal to -1 of X.
4970 'o': print integer X as if it's an unsigned 32bit word. */
4971
4972 void
4973 print_operand (FILE *file, rtx x, int code)
4974 {
4975 switch (code)
4976 {
4977 case 'C':
4978 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4979 return;
4980
4981 case 'D':
4982 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4983 return;
4984
4985 case 'J':
4986 if (GET_CODE (x) == SYMBOL_REF)
4987 {
4988 fprintf (file, "%s", ":tls_load:");
4989 output_addr_const (file, x);
4990 }
4991 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4992 {
4993 fprintf (file, "%s", ":tls_gdcall:");
4994 output_addr_const (file, XVECEXP (x, 0, 0));
4995 }
4996 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4997 {
4998 fprintf (file, "%s", ":tls_ldcall:");
4999 assemble_name (file, get_some_local_dynamic_name ());
5000 }
5001 else
5002 gcc_unreachable ();
5003 return;
5004
5005 case 'G':
5006 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5007 return;
5008
5009 case 'O':
5010 {
5011 struct s390_address ad;
5012 int ret;
5013
5014 gcc_assert (GET_CODE (x) == MEM);
5015 ret = s390_decompose_address (XEXP (x, 0), &ad);
5016 gcc_assert (ret);
5017 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5018 gcc_assert (!ad.indx);
5019
5020 if (ad.disp)
5021 output_addr_const (file, ad.disp);
5022 else
5023 fprintf (file, "0");
5024 }
5025 return;
5026
5027 case 'R':
5028 {
5029 struct s390_address ad;
5030 int ret;
5031
5032 gcc_assert (GET_CODE (x) == MEM);
5033 ret = s390_decompose_address (XEXP (x, 0), &ad);
5034 gcc_assert (ret);
5035 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5036 gcc_assert (!ad.indx);
5037
5038 if (ad.base)
5039 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5040 else
5041 fprintf (file, "0");
5042 }
5043 return;
5044
5045 case 'S':
5046 {
5047 struct s390_address ad;
5048 int ret;
5049
5050 gcc_assert (GET_CODE (x) == MEM);
5051 ret = s390_decompose_address (XEXP (x, 0), &ad);
5052 gcc_assert (ret);
5053 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5054 gcc_assert (!ad.indx);
5055
5056 if (ad.disp)
5057 output_addr_const (file, ad.disp);
5058 else
5059 fprintf (file, "0");
5060
5061 if (ad.base)
5062 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5063 }
5064 return;
5065
5066 case 'N':
5067 if (GET_CODE (x) == REG)
5068 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5069 else if (GET_CODE (x) == MEM)
5070 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5071 else
5072 gcc_unreachable ();
5073 break;
5074
5075 case 'M':
5076 if (GET_CODE (x) == REG)
5077 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5078 else if (GET_CODE (x) == MEM)
5079 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5080 else
5081 gcc_unreachable ();
5082 break;
5083
5084 case 'Y':
5085 print_shift_count_operand (file, x);
5086 return;
5087 }
5088
5089 switch (GET_CODE (x))
5090 {
5091 case REG:
5092 fprintf (file, "%s", reg_names[REGNO (x)]);
5093 break;
5094
5095 case MEM:
5096 output_address (XEXP (x, 0));
5097 break;
5098
5099 case CONST:
5100 case CODE_LABEL:
5101 case LABEL_REF:
5102 case SYMBOL_REF:
5103 output_addr_const (file, x);
5104 break;
5105
5106 case CONST_INT:
5107 if (code == 'b')
5108 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5109 else if (code == 'c')
5110 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5111 else if (code == 'x')
5112 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5113 else if (code == 'h')
5114 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5115 else if (code == 'i')
5116 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5117 s390_extract_part (x, HImode, 0));
5118 else if (code == 'j')
5119 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5120 s390_extract_part (x, HImode, -1));
5121 else if (code == 'k')
5122 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5123 s390_extract_part (x, SImode, 0));
5124 else if (code == 'm')
5125 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5126 s390_extract_part (x, SImode, -1));
5127 else if (code == 'o')
5128 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5129 else
5130 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5131 break;
5132
5133 case CONST_DOUBLE:
5134 gcc_assert (GET_MODE (x) == VOIDmode);
5135 if (code == 'b')
5136 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5137 else if (code == 'x')
5138 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5139 else if (code == 'h')
5140 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5141 else
5142 gcc_unreachable ();
5143 break;
5144
5145 default:
5146 fatal_insn ("UNKNOWN in print_operand !?", x);
5147 break;
5148 }
5149 }
5150
5151 /* Target hook for assembling integer objects. We need to define it
5152 here to work a round a bug in some versions of GAS, which couldn't
5153 handle values smaller than INT_MIN when printed in decimal. */
5154
5155 static bool
5156 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5157 {
5158 if (size == 8 && aligned_p
5159 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5160 {
5161 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5162 INTVAL (x));
5163 return true;
5164 }
5165 return default_assemble_integer (x, size, aligned_p);
5166 }
5167
5168 /* Returns true if register REGNO is used for forming
5169 a memory address in expression X. */
5170
5171 static bool
5172 reg_used_in_mem_p (int regno, rtx x)
5173 {
5174 enum rtx_code code = GET_CODE (x);
5175 int i, j;
5176 const char *fmt;
5177
5178 if (code == MEM)
5179 {
5180 if (refers_to_regno_p (regno, regno+1,
5181 XEXP (x, 0), 0))
5182 return true;
5183 }
5184 else if (code == SET
5185 && GET_CODE (SET_DEST (x)) == PC)
5186 {
5187 if (refers_to_regno_p (regno, regno+1,
5188 SET_SRC (x), 0))
5189 return true;
5190 }
5191
5192 fmt = GET_RTX_FORMAT (code);
5193 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5194 {
5195 if (fmt[i] == 'e'
5196 && reg_used_in_mem_p (regno, XEXP (x, i)))
5197 return true;
5198
5199 else if (fmt[i] == 'E')
5200 for (j = 0; j < XVECLEN (x, i); j++)
5201 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5202 return true;
5203 }
5204 return false;
5205 }
5206
5207 /* Returns true if expression DEP_RTX sets an address register
5208 used by instruction INSN to address memory. */
5209
5210 static bool
5211 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5212 {
5213 rtx target, pat;
5214
5215 if (GET_CODE (dep_rtx) == INSN)
5216 dep_rtx = PATTERN (dep_rtx);
5217
5218 if (GET_CODE (dep_rtx) == SET)
5219 {
5220 target = SET_DEST (dep_rtx);
5221 if (GET_CODE (target) == STRICT_LOW_PART)
5222 target = XEXP (target, 0);
5223 while (GET_CODE (target) == SUBREG)
5224 target = SUBREG_REG (target);
5225
5226 if (GET_CODE (target) == REG)
5227 {
5228 int regno = REGNO (target);
5229
5230 if (s390_safe_attr_type (insn) == TYPE_LA)
5231 {
5232 pat = PATTERN (insn);
5233 if (GET_CODE (pat) == PARALLEL)
5234 {
5235 gcc_assert (XVECLEN (pat, 0) == 2);
5236 pat = XVECEXP (pat, 0, 0);
5237 }
5238 gcc_assert (GET_CODE (pat) == SET);
5239 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5240 }
5241 else if (get_attr_atype (insn) == ATYPE_AGEN)
5242 return reg_used_in_mem_p (regno, PATTERN (insn));
5243 }
5244 }
5245 return false;
5246 }
5247
5248 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5249
5250 int
5251 s390_agen_dep_p (rtx dep_insn, rtx insn)
5252 {
5253 rtx dep_rtx = PATTERN (dep_insn);
5254 int i;
5255
5256 if (GET_CODE (dep_rtx) == SET
5257 && addr_generation_dependency_p (dep_rtx, insn))
5258 return 1;
5259 else if (GET_CODE (dep_rtx) == PARALLEL)
5260 {
5261 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5262 {
5263 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5264 return 1;
5265 }
5266 }
5267 return 0;
5268 }
5269
5270
5271 /* A C statement (sans semicolon) to update the integer scheduling priority
5272 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5273 reduce the priority to execute INSN later. Do not define this macro if
5274 you do not need to adjust the scheduling priorities of insns.
5275
5276 A STD instruction should be scheduled earlier,
5277 in order to use the bypass. */
5278
5279 static int
5280 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5281 {
5282 if (! INSN_P (insn))
5283 return priority;
5284
5285 if (s390_tune != PROCESSOR_2084_Z990
5286 && s390_tune != PROCESSOR_2094_Z9_109)
5287 return priority;
5288
5289 switch (s390_safe_attr_type (insn))
5290 {
5291 case TYPE_FSTOREDF:
5292 case TYPE_FSTORESF:
5293 priority = priority << 3;
5294 break;
5295 case TYPE_STORE:
5296 case TYPE_STM:
5297 priority = priority << 1;
5298 break;
5299 default:
5300 break;
5301 }
5302 return priority;
5303 }
5304
5305 /* The number of instructions that can be issued per cycle. */
5306
5307 static int
5308 s390_issue_rate (void)
5309 {
5310 switch (s390_tune)
5311 {
5312 case PROCESSOR_2084_Z990:
5313 case PROCESSOR_2094_Z9_109:
5314 return 3;
5315 case PROCESSOR_2097_Z10:
5316 return 2;
5317 default:
5318 return 1;
5319 }
5320 }
5321
5322 static int
5323 s390_first_cycle_multipass_dfa_lookahead (void)
5324 {
5325 return 4;
5326 }
5327
5328
5329 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5330 Fix up MEMs as required. */
5331
5332 static void
5333 annotate_constant_pool_refs (rtx *x)
5334 {
5335 int i, j;
5336 const char *fmt;
5337
5338 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5339 || !CONSTANT_POOL_ADDRESS_P (*x));
5340
5341 /* Literal pool references can only occur inside a MEM ... */
5342 if (GET_CODE (*x) == MEM)
5343 {
5344 rtx memref = XEXP (*x, 0);
5345
5346 if (GET_CODE (memref) == SYMBOL_REF
5347 && CONSTANT_POOL_ADDRESS_P (memref))
5348 {
5349 rtx base = cfun->machine->base_reg;
5350 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5351 UNSPEC_LTREF);
5352
5353 *x = replace_equiv_address (*x, addr);
5354 return;
5355 }
5356
5357 if (GET_CODE (memref) == CONST
5358 && GET_CODE (XEXP (memref, 0)) == PLUS
5359 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5360 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5361 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5362 {
5363 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5364 rtx sym = XEXP (XEXP (memref, 0), 0);
5365 rtx base = cfun->machine->base_reg;
5366 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5367 UNSPEC_LTREF);
5368
5369 *x = replace_equiv_address (*x, plus_constant (addr, off));
5370 return;
5371 }
5372 }
5373
5374 /* ... or a load-address type pattern. */
5375 if (GET_CODE (*x) == SET)
5376 {
5377 rtx addrref = SET_SRC (*x);
5378
5379 if (GET_CODE (addrref) == SYMBOL_REF
5380 && CONSTANT_POOL_ADDRESS_P (addrref))
5381 {
5382 rtx base = cfun->machine->base_reg;
5383 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5384 UNSPEC_LTREF);
5385
5386 SET_SRC (*x) = addr;
5387 return;
5388 }
5389
5390 if (GET_CODE (addrref) == CONST
5391 && GET_CODE (XEXP (addrref, 0)) == PLUS
5392 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5393 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5394 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5395 {
5396 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5397 rtx sym = XEXP (XEXP (addrref, 0), 0);
5398 rtx base = cfun->machine->base_reg;
5399 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5400 UNSPEC_LTREF);
5401
5402 SET_SRC (*x) = plus_constant (addr, off);
5403 return;
5404 }
5405 }
5406
5407 /* Annotate LTREL_BASE as well. */
5408 if (GET_CODE (*x) == UNSPEC
5409 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5410 {
5411 rtx base = cfun->machine->base_reg;
5412 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5413 UNSPEC_LTREL_BASE);
5414 return;
5415 }
5416
5417 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5418 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5419 {
5420 if (fmt[i] == 'e')
5421 {
5422 annotate_constant_pool_refs (&XEXP (*x, i));
5423 }
5424 else if (fmt[i] == 'E')
5425 {
5426 for (j = 0; j < XVECLEN (*x, i); j++)
5427 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5428 }
5429 }
5430 }
5431
5432 /* Split all branches that exceed the maximum distance.
5433 Returns true if this created a new literal pool entry. */
5434
5435 static int
5436 s390_split_branches (void)
5437 {
5438 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5439 int new_literal = 0, ret;
5440 rtx insn, pat, tmp, target;
5441 rtx *label;
5442
5443 /* We need correct insn addresses. */
5444
5445 shorten_branches (get_insns ());
5446
5447 /* Find all branches that exceed 64KB, and split them. */
5448
5449 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5450 {
5451 if (GET_CODE (insn) != JUMP_INSN)
5452 continue;
5453
5454 pat = PATTERN (insn);
5455 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5456 pat = XVECEXP (pat, 0, 0);
5457 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5458 continue;
5459
5460 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5461 {
5462 label = &SET_SRC (pat);
5463 }
5464 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5465 {
5466 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5467 label = &XEXP (SET_SRC (pat), 1);
5468 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5469 label = &XEXP (SET_SRC (pat), 2);
5470 else
5471 continue;
5472 }
5473 else
5474 continue;
5475
5476 if (get_attr_length (insn) <= 4)
5477 continue;
5478
5479 /* We are going to use the return register as scratch register,
5480 make sure it will be saved/restored by the prologue/epilogue. */
5481 cfun_frame_layout.save_return_addr_p = 1;
5482
5483 if (!flag_pic)
5484 {
5485 new_literal = 1;
5486 tmp = force_const_mem (Pmode, *label);
5487 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5488 INSN_ADDRESSES_NEW (tmp, -1);
5489 annotate_constant_pool_refs (&PATTERN (tmp));
5490
5491 target = temp_reg;
5492 }
5493 else
5494 {
5495 new_literal = 1;
5496 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5497 UNSPEC_LTREL_OFFSET);
5498 target = gen_rtx_CONST (Pmode, target);
5499 target = force_const_mem (Pmode, target);
5500 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5501 INSN_ADDRESSES_NEW (tmp, -1);
5502 annotate_constant_pool_refs (&PATTERN (tmp));
5503
5504 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5505 cfun->machine->base_reg),
5506 UNSPEC_LTREL_BASE);
5507 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5508 }
5509
5510 ret = validate_change (insn, label, target, 0);
5511 gcc_assert (ret);
5512 }
5513
5514 return new_literal;
5515 }
5516
5517
5518 /* Find an annotated literal pool symbol referenced in RTX X,
5519 and store it at REF. Will abort if X contains references to
5520 more than one such pool symbol; multiple references to the same
5521 symbol are allowed, however.
5522
5523 The rtx pointed to by REF must be initialized to NULL_RTX
5524 by the caller before calling this routine. */
5525
5526 static void
5527 find_constant_pool_ref (rtx x, rtx *ref)
5528 {
5529 int i, j;
5530 const char *fmt;
5531
5532 /* Ignore LTREL_BASE references. */
5533 if (GET_CODE (x) == UNSPEC
5534 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5535 return;
5536 /* Likewise POOL_ENTRY insns. */
5537 if (GET_CODE (x) == UNSPEC_VOLATILE
5538 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5539 return;
5540
5541 gcc_assert (GET_CODE (x) != SYMBOL_REF
5542 || !CONSTANT_POOL_ADDRESS_P (x));
5543
5544 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5545 {
5546 rtx sym = XVECEXP (x, 0, 0);
5547 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5548 && CONSTANT_POOL_ADDRESS_P (sym));
5549
5550 if (*ref == NULL_RTX)
5551 *ref = sym;
5552 else
5553 gcc_assert (*ref == sym);
5554
5555 return;
5556 }
5557
5558 fmt = GET_RTX_FORMAT (GET_CODE (x));
5559 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5560 {
5561 if (fmt[i] == 'e')
5562 {
5563 find_constant_pool_ref (XEXP (x, i), ref);
5564 }
5565 else if (fmt[i] == 'E')
5566 {
5567 for (j = 0; j < XVECLEN (x, i); j++)
5568 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5569 }
5570 }
5571 }
5572
5573 /* Replace every reference to the annotated literal pool
5574 symbol REF in X by its base plus OFFSET. */
5575
5576 static void
5577 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5578 {
5579 int i, j;
5580 const char *fmt;
5581
5582 gcc_assert (*x != ref);
5583
5584 if (GET_CODE (*x) == UNSPEC
5585 && XINT (*x, 1) == UNSPEC_LTREF
5586 && XVECEXP (*x, 0, 0) == ref)
5587 {
5588 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5589 return;
5590 }
5591
5592 if (GET_CODE (*x) == PLUS
5593 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5594 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5595 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5596 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5597 {
5598 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5599 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5600 return;
5601 }
5602
5603 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5604 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5605 {
5606 if (fmt[i] == 'e')
5607 {
5608 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5609 }
5610 else if (fmt[i] == 'E')
5611 {
5612 for (j = 0; j < XVECLEN (*x, i); j++)
5613 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5614 }
5615 }
5616 }
5617
5618 /* Check whether X contains an UNSPEC_LTREL_BASE.
5619 Return its constant pool symbol if found, NULL_RTX otherwise. */
5620
5621 static rtx
5622 find_ltrel_base (rtx x)
5623 {
5624 int i, j;
5625 const char *fmt;
5626
5627 if (GET_CODE (x) == UNSPEC
5628 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5629 return XVECEXP (x, 0, 0);
5630
5631 fmt = GET_RTX_FORMAT (GET_CODE (x));
5632 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5633 {
5634 if (fmt[i] == 'e')
5635 {
5636 rtx fnd = find_ltrel_base (XEXP (x, i));
5637 if (fnd)
5638 return fnd;
5639 }
5640 else if (fmt[i] == 'E')
5641 {
5642 for (j = 0; j < XVECLEN (x, i); j++)
5643 {
5644 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5645 if (fnd)
5646 return fnd;
5647 }
5648 }
5649 }
5650
5651 return NULL_RTX;
5652 }
5653
5654 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5655
5656 static void
5657 replace_ltrel_base (rtx *x)
5658 {
5659 int i, j;
5660 const char *fmt;
5661
5662 if (GET_CODE (*x) == UNSPEC
5663 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5664 {
5665 *x = XVECEXP (*x, 0, 1);
5666 return;
5667 }
5668
5669 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5670 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5671 {
5672 if (fmt[i] == 'e')
5673 {
5674 replace_ltrel_base (&XEXP (*x, i));
5675 }
5676 else if (fmt[i] == 'E')
5677 {
5678 for (j = 0; j < XVECLEN (*x, i); j++)
5679 replace_ltrel_base (&XVECEXP (*x, i, j));
5680 }
5681 }
5682 }
5683
5684
5685 /* We keep a list of constants which we have to add to internal
5686 constant tables in the middle of large functions. */
5687
5688 #define NR_C_MODES 11
5689 enum machine_mode constant_modes[NR_C_MODES] =
5690 {
5691 TFmode, TImode, TDmode,
5692 DFmode, DImode, DDmode,
5693 SFmode, SImode, SDmode,
5694 HImode,
5695 QImode
5696 };
5697
5698 struct constant
5699 {
5700 struct constant *next;
5701 rtx value;
5702 rtx label;
5703 };
5704
5705 struct constant_pool
5706 {
5707 struct constant_pool *next;
5708 rtx first_insn;
5709 rtx pool_insn;
5710 bitmap insns;
5711 rtx emit_pool_after;
5712
5713 struct constant *constants[NR_C_MODES];
5714 struct constant *execute;
5715 rtx label;
5716 int size;
5717 };
5718
5719 /* Allocate new constant_pool structure. */
5720
5721 static struct constant_pool *
5722 s390_alloc_pool (void)
5723 {
5724 struct constant_pool *pool;
5725 int i;
5726
5727 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5728 pool->next = NULL;
5729 for (i = 0; i < NR_C_MODES; i++)
5730 pool->constants[i] = NULL;
5731
5732 pool->execute = NULL;
5733 pool->label = gen_label_rtx ();
5734 pool->first_insn = NULL_RTX;
5735 pool->pool_insn = NULL_RTX;
5736 pool->insns = BITMAP_ALLOC (NULL);
5737 pool->size = 0;
5738 pool->emit_pool_after = NULL_RTX;
5739
5740 return pool;
5741 }
5742
5743 /* Create new constant pool covering instructions starting at INSN
5744 and chain it to the end of POOL_LIST. */
5745
5746 static struct constant_pool *
5747 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5748 {
5749 struct constant_pool *pool, **prev;
5750
5751 pool = s390_alloc_pool ();
5752 pool->first_insn = insn;
5753
5754 for (prev = pool_list; *prev; prev = &(*prev)->next)
5755 ;
5756 *prev = pool;
5757
5758 return pool;
5759 }
5760
5761 /* End range of instructions covered by POOL at INSN and emit
5762 placeholder insn representing the pool. */
5763
5764 static void
5765 s390_end_pool (struct constant_pool *pool, rtx insn)
5766 {
5767 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5768
5769 if (!insn)
5770 insn = get_last_insn ();
5771
5772 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5773 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5774 }
5775
5776 /* Add INSN to the list of insns covered by POOL. */
5777
5778 static void
5779 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5780 {
5781 bitmap_set_bit (pool->insns, INSN_UID (insn));
5782 }
5783
5784 /* Return pool out of POOL_LIST that covers INSN. */
5785
5786 static struct constant_pool *
5787 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5788 {
5789 struct constant_pool *pool;
5790
5791 for (pool = pool_list; pool; pool = pool->next)
5792 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5793 break;
5794
5795 return pool;
5796 }
5797
5798 /* Add constant VAL of mode MODE to the constant pool POOL. */
5799
5800 static void
5801 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5802 {
5803 struct constant *c;
5804 int i;
5805
5806 for (i = 0; i < NR_C_MODES; i++)
5807 if (constant_modes[i] == mode)
5808 break;
5809 gcc_assert (i != NR_C_MODES);
5810
5811 for (c = pool->constants[i]; c != NULL; c = c->next)
5812 if (rtx_equal_p (val, c->value))
5813 break;
5814
5815 if (c == NULL)
5816 {
5817 c = (struct constant *) xmalloc (sizeof *c);
5818 c->value = val;
5819 c->label = gen_label_rtx ();
5820 c->next = pool->constants[i];
5821 pool->constants[i] = c;
5822 pool->size += GET_MODE_SIZE (mode);
5823 }
5824 }
5825
5826 /* Return an rtx that represents the offset of X from the start of
5827 pool POOL. */
5828
5829 static rtx
5830 s390_pool_offset (struct constant_pool *pool, rtx x)
5831 {
5832 rtx label;
5833
5834 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5835 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5836 UNSPEC_POOL_OFFSET);
5837 return gen_rtx_CONST (GET_MODE (x), x);
5838 }
5839
5840 /* Find constant VAL of mode MODE in the constant pool POOL.
5841 Return an RTX describing the distance from the start of
5842 the pool to the location of the new constant. */
5843
5844 static rtx
5845 s390_find_constant (struct constant_pool *pool, rtx val,
5846 enum machine_mode mode)
5847 {
5848 struct constant *c;
5849 int i;
5850
5851 for (i = 0; i < NR_C_MODES; i++)
5852 if (constant_modes[i] == mode)
5853 break;
5854 gcc_assert (i != NR_C_MODES);
5855
5856 for (c = pool->constants[i]; c != NULL; c = c->next)
5857 if (rtx_equal_p (val, c->value))
5858 break;
5859
5860 gcc_assert (c);
5861
5862 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5863 }
5864
5865 /* Check whether INSN is an execute. Return the label_ref to its
5866 execute target template if so, NULL_RTX otherwise. */
5867
5868 static rtx
5869 s390_execute_label (rtx insn)
5870 {
5871 if (GET_CODE (insn) == INSN
5872 && GET_CODE (PATTERN (insn)) == PARALLEL
5873 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5874 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5875 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5876
5877 return NULL_RTX;
5878 }
5879
5880 /* Add execute target for INSN to the constant pool POOL. */
5881
5882 static void
5883 s390_add_execute (struct constant_pool *pool, rtx insn)
5884 {
5885 struct constant *c;
5886
5887 for (c = pool->execute; c != NULL; c = c->next)
5888 if (INSN_UID (insn) == INSN_UID (c->value))
5889 break;
5890
5891 if (c == NULL)
5892 {
5893 c = (struct constant *) xmalloc (sizeof *c);
5894 c->value = insn;
5895 c->label = gen_label_rtx ();
5896 c->next = pool->execute;
5897 pool->execute = c;
5898 pool->size += 6;
5899 }
5900 }
5901
5902 /* Find execute target for INSN in the constant pool POOL.
5903 Return an RTX describing the distance from the start of
5904 the pool to the location of the execute target. */
5905
5906 static rtx
5907 s390_find_execute (struct constant_pool *pool, rtx insn)
5908 {
5909 struct constant *c;
5910
5911 for (c = pool->execute; c != NULL; c = c->next)
5912 if (INSN_UID (insn) == INSN_UID (c->value))
5913 break;
5914
5915 gcc_assert (c);
5916
5917 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5918 }
5919
5920 /* For an execute INSN, extract the execute target template. */
5921
5922 static rtx
5923 s390_execute_target (rtx insn)
5924 {
5925 rtx pattern = PATTERN (insn);
5926 gcc_assert (s390_execute_label (insn));
5927
5928 if (XVECLEN (pattern, 0) == 2)
5929 {
5930 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5931 }
5932 else
5933 {
5934 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5935 int i;
5936
5937 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5938 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5939
5940 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5941 }
5942
5943 return pattern;
5944 }
5945
5946 /* Indicate that INSN cannot be duplicated. This is the case for
5947 execute insns that carry a unique label. */
5948
5949 static bool
5950 s390_cannot_copy_insn_p (rtx insn)
5951 {
5952 rtx label = s390_execute_label (insn);
5953 return label && label != const0_rtx;
5954 }
5955
5956 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5957 do not emit the pool base label. */
5958
5959 static void
5960 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5961 {
5962 struct constant *c;
5963 rtx insn = pool->pool_insn;
5964 int i;
5965
5966 /* Switch to rodata section. */
5967 if (TARGET_CPU_ZARCH)
5968 {
5969 insn = emit_insn_after (gen_pool_section_start (), insn);
5970 INSN_ADDRESSES_NEW (insn, -1);
5971 }
5972
5973 /* Ensure minimum pool alignment. */
5974 if (TARGET_CPU_ZARCH)
5975 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5976 else
5977 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5978 INSN_ADDRESSES_NEW (insn, -1);
5979
5980 /* Emit pool base label. */
5981 if (!remote_label)
5982 {
5983 insn = emit_label_after (pool->label, insn);
5984 INSN_ADDRESSES_NEW (insn, -1);
5985 }
5986
5987 /* Dump constants in descending alignment requirement order,
5988 ensuring proper alignment for every constant. */
5989 for (i = 0; i < NR_C_MODES; i++)
5990 for (c = pool->constants[i]; c; c = c->next)
5991 {
5992 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5993 rtx value = copy_rtx (c->value);
5994 if (GET_CODE (value) == CONST
5995 && GET_CODE (XEXP (value, 0)) == UNSPEC
5996 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5997 && XVECLEN (XEXP (value, 0), 0) == 1)
5998 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
5999
6000 insn = emit_label_after (c->label, insn);
6001 INSN_ADDRESSES_NEW (insn, -1);
6002
6003 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6004 gen_rtvec (1, value),
6005 UNSPECV_POOL_ENTRY);
6006 insn = emit_insn_after (value, insn);
6007 INSN_ADDRESSES_NEW (insn, -1);
6008 }
6009
6010 /* Ensure minimum alignment for instructions. */
6011 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6012 INSN_ADDRESSES_NEW (insn, -1);
6013
6014 /* Output in-pool execute template insns. */
6015 for (c = pool->execute; c; c = c->next)
6016 {
6017 insn = emit_label_after (c->label, insn);
6018 INSN_ADDRESSES_NEW (insn, -1);
6019
6020 insn = emit_insn_after (s390_execute_target (c->value), insn);
6021 INSN_ADDRESSES_NEW (insn, -1);
6022 }
6023
6024 /* Switch back to previous section. */
6025 if (TARGET_CPU_ZARCH)
6026 {
6027 insn = emit_insn_after (gen_pool_section_end (), insn);
6028 INSN_ADDRESSES_NEW (insn, -1);
6029 }
6030
6031 insn = emit_barrier_after (insn);
6032 INSN_ADDRESSES_NEW (insn, -1);
6033
6034 /* Remove placeholder insn. */
6035 remove_insn (pool->pool_insn);
6036 }
6037
6038 /* Free all memory used by POOL. */
6039
6040 static void
6041 s390_free_pool (struct constant_pool *pool)
6042 {
6043 struct constant *c, *next;
6044 int i;
6045
6046 for (i = 0; i < NR_C_MODES; i++)
6047 for (c = pool->constants[i]; c; c = next)
6048 {
6049 next = c->next;
6050 free (c);
6051 }
6052
6053 for (c = pool->execute; c; c = next)
6054 {
6055 next = c->next;
6056 free (c);
6057 }
6058
6059 BITMAP_FREE (pool->insns);
6060 free (pool);
6061 }
6062
6063
6064 /* Collect main literal pool. Return NULL on overflow. */
6065
6066 static struct constant_pool *
6067 s390_mainpool_start (void)
6068 {
6069 struct constant_pool *pool;
6070 rtx insn;
6071
6072 pool = s390_alloc_pool ();
6073
6074 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6075 {
6076 if (GET_CODE (insn) == INSN
6077 && GET_CODE (PATTERN (insn)) == SET
6078 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6079 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6080 {
6081 gcc_assert (!pool->pool_insn);
6082 pool->pool_insn = insn;
6083 }
6084
6085 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6086 {
6087 s390_add_execute (pool, insn);
6088 }
6089 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6090 {
6091 rtx pool_ref = NULL_RTX;
6092 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6093 if (pool_ref)
6094 {
6095 rtx constant = get_pool_constant (pool_ref);
6096 enum machine_mode mode = get_pool_mode (pool_ref);
6097 s390_add_constant (pool, constant, mode);
6098 }
6099 }
6100
6101 /* If hot/cold partitioning is enabled we have to make sure that
6102 the literal pool is emitted in the same section where the
6103 initialization of the literal pool base pointer takes place.
6104 emit_pool_after is only used in the non-overflow case on non
6105 Z cpus where we can emit the literal pool at the end of the
6106 function body within the text section. */
6107 if (NOTE_P (insn)
6108 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6109 && !pool->emit_pool_after)
6110 pool->emit_pool_after = PREV_INSN (insn);
6111 }
6112
6113 gcc_assert (pool->pool_insn || pool->size == 0);
6114
6115 if (pool->size >= 4096)
6116 {
6117 /* We're going to chunkify the pool, so remove the main
6118 pool placeholder insn. */
6119 remove_insn (pool->pool_insn);
6120
6121 s390_free_pool (pool);
6122 pool = NULL;
6123 }
6124
6125 /* If the functions ends with the section where the literal pool
6126 should be emitted set the marker to its end. */
6127 if (pool && !pool->emit_pool_after)
6128 pool->emit_pool_after = get_last_insn ();
6129
6130 return pool;
6131 }
6132
6133 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6134 Modify the current function to output the pool constants as well as
6135 the pool register setup instruction. */
6136
6137 static void
6138 s390_mainpool_finish (struct constant_pool *pool)
6139 {
6140 rtx base_reg = cfun->machine->base_reg;
6141 rtx insn;
6142
6143 /* If the pool is empty, we're done. */
6144 if (pool->size == 0)
6145 {
6146 /* We don't actually need a base register after all. */
6147 cfun->machine->base_reg = NULL_RTX;
6148
6149 if (pool->pool_insn)
6150 remove_insn (pool->pool_insn);
6151 s390_free_pool (pool);
6152 return;
6153 }
6154
6155 /* We need correct insn addresses. */
6156 shorten_branches (get_insns ());
6157
6158 /* On zSeries, we use a LARL to load the pool register. The pool is
6159 located in the .rodata section, so we emit it after the function. */
6160 if (TARGET_CPU_ZARCH)
6161 {
6162 insn = gen_main_base_64 (base_reg, pool->label);
6163 insn = emit_insn_after (insn, pool->pool_insn);
6164 INSN_ADDRESSES_NEW (insn, -1);
6165 remove_insn (pool->pool_insn);
6166
6167 insn = get_last_insn ();
6168 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6169 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6170
6171 s390_dump_pool (pool, 0);
6172 }
6173
6174 /* On S/390, if the total size of the function's code plus literal pool
6175 does not exceed 4096 bytes, we use BASR to set up a function base
6176 pointer, and emit the literal pool at the end of the function. */
6177 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6178 + pool->size + 8 /* alignment slop */ < 4096)
6179 {
6180 insn = gen_main_base_31_small (base_reg, pool->label);
6181 insn = emit_insn_after (insn, pool->pool_insn);
6182 INSN_ADDRESSES_NEW (insn, -1);
6183 remove_insn (pool->pool_insn);
6184
6185 insn = emit_label_after (pool->label, insn);
6186 INSN_ADDRESSES_NEW (insn, -1);
6187
6188 /* emit_pool_after will be set by s390_mainpool_start to the
6189 last insn of the section where the literal pool should be
6190 emitted. */
6191 insn = pool->emit_pool_after;
6192
6193 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6194 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6195
6196 s390_dump_pool (pool, 1);
6197 }
6198
6199 /* Otherwise, we emit an inline literal pool and use BASR to branch
6200 over it, setting up the pool register at the same time. */
6201 else
6202 {
6203 rtx pool_end = gen_label_rtx ();
6204
6205 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6206 insn = emit_insn_after (insn, pool->pool_insn);
6207 INSN_ADDRESSES_NEW (insn, -1);
6208 remove_insn (pool->pool_insn);
6209
6210 insn = emit_label_after (pool->label, insn);
6211 INSN_ADDRESSES_NEW (insn, -1);
6212
6213 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6214 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6215
6216 insn = emit_label_after (pool_end, pool->pool_insn);
6217 INSN_ADDRESSES_NEW (insn, -1);
6218
6219 s390_dump_pool (pool, 1);
6220 }
6221
6222
6223 /* Replace all literal pool references. */
6224
6225 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6226 {
6227 if (INSN_P (insn))
6228 replace_ltrel_base (&PATTERN (insn));
6229
6230 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6231 {
6232 rtx addr, pool_ref = NULL_RTX;
6233 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6234 if (pool_ref)
6235 {
6236 if (s390_execute_label (insn))
6237 addr = s390_find_execute (pool, insn);
6238 else
6239 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6240 get_pool_mode (pool_ref));
6241
6242 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6243 INSN_CODE (insn) = -1;
6244 }
6245 }
6246 }
6247
6248
6249 /* Free the pool. */
6250 s390_free_pool (pool);
6251 }
6252
6253 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6254 We have decided we cannot use this pool, so revert all changes
6255 to the current function that were done by s390_mainpool_start. */
6256 static void
6257 s390_mainpool_cancel (struct constant_pool *pool)
6258 {
6259 /* We didn't actually change the instruction stream, so simply
6260 free the pool memory. */
6261 s390_free_pool (pool);
6262 }
6263
6264
6265 /* Chunkify the literal pool. */
6266
6267 #define S390_POOL_CHUNK_MIN 0xc00
6268 #define S390_POOL_CHUNK_MAX 0xe00
6269
6270 static struct constant_pool *
6271 s390_chunkify_start (void)
6272 {
6273 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6274 int extra_size = 0;
6275 bitmap far_labels;
6276 rtx pending_ltrel = NULL_RTX;
6277 rtx insn;
6278
6279 rtx (*gen_reload_base) (rtx, rtx) =
6280 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6281
6282
6283 /* We need correct insn addresses. */
6284
6285 shorten_branches (get_insns ());
6286
6287 /* Scan all insns and move literals to pool chunks. */
6288
6289 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6290 {
6291 bool section_switch_p = false;
6292
6293 /* Check for pending LTREL_BASE. */
6294 if (INSN_P (insn))
6295 {
6296 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6297 if (ltrel_base)
6298 {
6299 gcc_assert (ltrel_base == pending_ltrel);
6300 pending_ltrel = NULL_RTX;
6301 }
6302 }
6303
6304 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6305 {
6306 if (!curr_pool)
6307 curr_pool = s390_start_pool (&pool_list, insn);
6308
6309 s390_add_execute (curr_pool, insn);
6310 s390_add_pool_insn (curr_pool, insn);
6311 }
6312 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6313 {
6314 rtx pool_ref = NULL_RTX;
6315 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6316 if (pool_ref)
6317 {
6318 rtx constant = get_pool_constant (pool_ref);
6319 enum machine_mode mode = get_pool_mode (pool_ref);
6320
6321 if (!curr_pool)
6322 curr_pool = s390_start_pool (&pool_list, insn);
6323
6324 s390_add_constant (curr_pool, constant, mode);
6325 s390_add_pool_insn (curr_pool, insn);
6326
6327 /* Don't split the pool chunk between a LTREL_OFFSET load
6328 and the corresponding LTREL_BASE. */
6329 if (GET_CODE (constant) == CONST
6330 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6331 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6332 {
6333 gcc_assert (!pending_ltrel);
6334 pending_ltrel = pool_ref;
6335 }
6336 }
6337 }
6338
6339 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6340 {
6341 if (curr_pool)
6342 s390_add_pool_insn (curr_pool, insn);
6343 /* An LTREL_BASE must follow within the same basic block. */
6344 gcc_assert (!pending_ltrel);
6345 }
6346
6347 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6348 section_switch_p = true;
6349
6350 if (!curr_pool
6351 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6352 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6353 continue;
6354
6355 if (TARGET_CPU_ZARCH)
6356 {
6357 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6358 continue;
6359
6360 s390_end_pool (curr_pool, NULL_RTX);
6361 curr_pool = NULL;
6362 }
6363 else
6364 {
6365 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6366 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6367 + extra_size;
6368
6369 /* We will later have to insert base register reload insns.
6370 Those will have an effect on code size, which we need to
6371 consider here. This calculation makes rather pessimistic
6372 worst-case assumptions. */
6373 if (GET_CODE (insn) == CODE_LABEL)
6374 extra_size += 6;
6375
6376 if (chunk_size < S390_POOL_CHUNK_MIN
6377 && curr_pool->size < S390_POOL_CHUNK_MIN
6378 && !section_switch_p)
6379 continue;
6380
6381 /* Pool chunks can only be inserted after BARRIERs ... */
6382 if (GET_CODE (insn) == BARRIER)
6383 {
6384 s390_end_pool (curr_pool, insn);
6385 curr_pool = NULL;
6386 extra_size = 0;
6387 }
6388
6389 /* ... so if we don't find one in time, create one. */
6390 else if (chunk_size > S390_POOL_CHUNK_MAX
6391 || curr_pool->size > S390_POOL_CHUNK_MAX
6392 || section_switch_p)
6393 {
6394 rtx label, jump, barrier;
6395
6396 if (!section_switch_p)
6397 {
6398 /* We can insert the barrier only after a 'real' insn. */
6399 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6400 continue;
6401 if (get_attr_length (insn) == 0)
6402 continue;
6403 /* Don't separate LTREL_BASE from the corresponding
6404 LTREL_OFFSET load. */
6405 if (pending_ltrel)
6406 continue;
6407 }
6408 else
6409 {
6410 gcc_assert (!pending_ltrel);
6411
6412 /* The old pool has to end before the section switch
6413 note in order to make it part of the current
6414 section. */
6415 insn = PREV_INSN (insn);
6416 }
6417
6418 label = gen_label_rtx ();
6419 jump = emit_jump_insn_after (gen_jump (label), insn);
6420 barrier = emit_barrier_after (jump);
6421 insn = emit_label_after (label, barrier);
6422 JUMP_LABEL (jump) = label;
6423 LABEL_NUSES (label) = 1;
6424
6425 INSN_ADDRESSES_NEW (jump, -1);
6426 INSN_ADDRESSES_NEW (barrier, -1);
6427 INSN_ADDRESSES_NEW (insn, -1);
6428
6429 s390_end_pool (curr_pool, barrier);
6430 curr_pool = NULL;
6431 extra_size = 0;
6432 }
6433 }
6434 }
6435
6436 if (curr_pool)
6437 s390_end_pool (curr_pool, NULL_RTX);
6438 gcc_assert (!pending_ltrel);
6439
6440 /* Find all labels that are branched into
6441 from an insn belonging to a different chunk. */
6442
6443 far_labels = BITMAP_ALLOC (NULL);
6444
6445 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6446 {
6447 /* Labels marked with LABEL_PRESERVE_P can be target
6448 of non-local jumps, so we have to mark them.
6449 The same holds for named labels.
6450
6451 Don't do that, however, if it is the label before
6452 a jump table. */
6453
6454 if (GET_CODE (insn) == CODE_LABEL
6455 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6456 {
6457 rtx vec_insn = next_real_insn (insn);
6458 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6459 PATTERN (vec_insn) : NULL_RTX;
6460 if (!vec_pat
6461 || !(GET_CODE (vec_pat) == ADDR_VEC
6462 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6463 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6464 }
6465
6466 /* If we have a direct jump (conditional or unconditional)
6467 or a casesi jump, check all potential targets. */
6468 else if (GET_CODE (insn) == JUMP_INSN)
6469 {
6470 rtx pat = PATTERN (insn);
6471 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6472 pat = XVECEXP (pat, 0, 0);
6473
6474 if (GET_CODE (pat) == SET)
6475 {
6476 rtx label = JUMP_LABEL (insn);
6477 if (label)
6478 {
6479 if (s390_find_pool (pool_list, label)
6480 != s390_find_pool (pool_list, insn))
6481 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6482 }
6483 }
6484 else if (GET_CODE (pat) == PARALLEL
6485 && XVECLEN (pat, 0) == 2
6486 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6487 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6488 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6489 {
6490 /* Find the jump table used by this casesi jump. */
6491 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6492 rtx vec_insn = next_real_insn (vec_label);
6493 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6494 PATTERN (vec_insn) : NULL_RTX;
6495 if (vec_pat
6496 && (GET_CODE (vec_pat) == ADDR_VEC
6497 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6498 {
6499 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6500
6501 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6502 {
6503 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6504
6505 if (s390_find_pool (pool_list, label)
6506 != s390_find_pool (pool_list, insn))
6507 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6508 }
6509 }
6510 }
6511 }
6512 }
6513
6514 /* Insert base register reload insns before every pool. */
6515
6516 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6517 {
6518 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6519 curr_pool->label);
6520 rtx insn = curr_pool->first_insn;
6521 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6522 }
6523
6524 /* Insert base register reload insns at every far label. */
6525
6526 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6527 if (GET_CODE (insn) == CODE_LABEL
6528 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6529 {
6530 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6531 if (pool)
6532 {
6533 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6534 pool->label);
6535 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6536 }
6537 }
6538
6539
6540 BITMAP_FREE (far_labels);
6541
6542
6543 /* Recompute insn addresses. */
6544
6545 init_insn_lengths ();
6546 shorten_branches (get_insns ());
6547
6548 return pool_list;
6549 }
6550
6551 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6552 After we have decided to use this list, finish implementing
6553 all changes to the current function as required. */
6554
6555 static void
6556 s390_chunkify_finish (struct constant_pool *pool_list)
6557 {
6558 struct constant_pool *curr_pool = NULL;
6559 rtx insn;
6560
6561
6562 /* Replace all literal pool references. */
6563
6564 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6565 {
6566 if (INSN_P (insn))
6567 replace_ltrel_base (&PATTERN (insn));
6568
6569 curr_pool = s390_find_pool (pool_list, insn);
6570 if (!curr_pool)
6571 continue;
6572
6573 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6574 {
6575 rtx addr, pool_ref = NULL_RTX;
6576 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6577 if (pool_ref)
6578 {
6579 if (s390_execute_label (insn))
6580 addr = s390_find_execute (curr_pool, insn);
6581 else
6582 addr = s390_find_constant (curr_pool,
6583 get_pool_constant (pool_ref),
6584 get_pool_mode (pool_ref));
6585
6586 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6587 INSN_CODE (insn) = -1;
6588 }
6589 }
6590 }
6591
6592 /* Dump out all literal pools. */
6593
6594 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6595 s390_dump_pool (curr_pool, 0);
6596
6597 /* Free pool list. */
6598
6599 while (pool_list)
6600 {
6601 struct constant_pool *next = pool_list->next;
6602 s390_free_pool (pool_list);
6603 pool_list = next;
6604 }
6605 }
6606
6607 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6608 We have decided we cannot use this list, so revert all changes
6609 to the current function that were done by s390_chunkify_start. */
6610
6611 static void
6612 s390_chunkify_cancel (struct constant_pool *pool_list)
6613 {
6614 struct constant_pool *curr_pool = NULL;
6615 rtx insn;
6616
6617 /* Remove all pool placeholder insns. */
6618
6619 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6620 {
6621 /* Did we insert an extra barrier? Remove it. */
6622 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6623 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6624 rtx label = NEXT_INSN (curr_pool->pool_insn);
6625
6626 if (jump && GET_CODE (jump) == JUMP_INSN
6627 && barrier && GET_CODE (barrier) == BARRIER
6628 && label && GET_CODE (label) == CODE_LABEL
6629 && GET_CODE (PATTERN (jump)) == SET
6630 && SET_DEST (PATTERN (jump)) == pc_rtx
6631 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6632 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6633 {
6634 remove_insn (jump);
6635 remove_insn (barrier);
6636 remove_insn (label);
6637 }
6638
6639 remove_insn (curr_pool->pool_insn);
6640 }
6641
6642 /* Remove all base register reload insns. */
6643
6644 for (insn = get_insns (); insn; )
6645 {
6646 rtx next_insn = NEXT_INSN (insn);
6647
6648 if (GET_CODE (insn) == INSN
6649 && GET_CODE (PATTERN (insn)) == SET
6650 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6651 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6652 remove_insn (insn);
6653
6654 insn = next_insn;
6655 }
6656
6657 /* Free pool list. */
6658
6659 while (pool_list)
6660 {
6661 struct constant_pool *next = pool_list->next;
6662 s390_free_pool (pool_list);
6663 pool_list = next;
6664 }
6665 }
6666
6667 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6668
6669 void
6670 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6671 {
6672 REAL_VALUE_TYPE r;
6673
6674 switch (GET_MODE_CLASS (mode))
6675 {
6676 case MODE_FLOAT:
6677 case MODE_DECIMAL_FLOAT:
6678 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6679
6680 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6681 assemble_real (r, mode, align);
6682 break;
6683
6684 case MODE_INT:
6685 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6686 mark_symbol_refs_as_used (exp);
6687 break;
6688
6689 default:
6690 gcc_unreachable ();
6691 }
6692 }
6693
6694
6695 /* Return an RTL expression representing the value of the return address
6696 for the frame COUNT steps up from the current frame. FRAME is the
6697 frame pointer of that frame. */
6698
6699 rtx
6700 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6701 {
6702 int offset;
6703 rtx addr;
6704
6705 /* Without backchain, we fail for all but the current frame. */
6706
6707 if (!TARGET_BACKCHAIN && count > 0)
6708 return NULL_RTX;
6709
6710 /* For the current frame, we need to make sure the initial
6711 value of RETURN_REGNUM is actually saved. */
6712
6713 if (count == 0)
6714 {
6715 /* On non-z architectures branch splitting could overwrite r14. */
6716 if (TARGET_CPU_ZARCH)
6717 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6718 else
6719 {
6720 cfun_frame_layout.save_return_addr_p = true;
6721 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6722 }
6723 }
6724
6725 if (TARGET_PACKED_STACK)
6726 offset = -2 * UNITS_PER_WORD;
6727 else
6728 offset = RETURN_REGNUM * UNITS_PER_WORD;
6729
6730 addr = plus_constant (frame, offset);
6731 addr = memory_address (Pmode, addr);
6732 return gen_rtx_MEM (Pmode, addr);
6733 }
6734
6735 /* Return an RTL expression representing the back chain stored in
6736 the current stack frame. */
6737
6738 rtx
6739 s390_back_chain_rtx (void)
6740 {
6741 rtx chain;
6742
6743 gcc_assert (TARGET_BACKCHAIN);
6744
6745 if (TARGET_PACKED_STACK)
6746 chain = plus_constant (stack_pointer_rtx,
6747 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6748 else
6749 chain = stack_pointer_rtx;
6750
6751 chain = gen_rtx_MEM (Pmode, chain);
6752 return chain;
6753 }
6754
6755 /* Find first call clobbered register unused in a function.
6756 This could be used as base register in a leaf function
6757 or for holding the return address before epilogue. */
6758
6759 static int
6760 find_unused_clobbered_reg (void)
6761 {
6762 int i;
6763 for (i = 0; i < 6; i++)
6764 if (!df_regs_ever_live_p (i))
6765 return i;
6766 return 0;
6767 }
6768
6769
6770 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6771 clobbered hard regs in SETREG. */
6772
6773 static void
6774 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6775 {
6776 int *regs_ever_clobbered = (int *)data;
6777 unsigned int i, regno;
6778 enum machine_mode mode = GET_MODE (setreg);
6779
6780 if (GET_CODE (setreg) == SUBREG)
6781 {
6782 rtx inner = SUBREG_REG (setreg);
6783 if (!GENERAL_REG_P (inner))
6784 return;
6785 regno = subreg_regno (setreg);
6786 }
6787 else if (GENERAL_REG_P (setreg))
6788 regno = REGNO (setreg);
6789 else
6790 return;
6791
6792 for (i = regno;
6793 i < regno + HARD_REGNO_NREGS (regno, mode);
6794 i++)
6795 regs_ever_clobbered[i] = 1;
6796 }
6797
6798 /* Walks through all basic blocks of the current function looking
6799 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6800 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6801 each of those regs. */
6802
6803 static void
6804 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6805 {
6806 basic_block cur_bb;
6807 rtx cur_insn;
6808 unsigned int i;
6809
6810 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6811
6812 /* For non-leaf functions we have to consider all call clobbered regs to be
6813 clobbered. */
6814 if (!current_function_is_leaf)
6815 {
6816 for (i = 0; i < 16; i++)
6817 regs_ever_clobbered[i] = call_really_used_regs[i];
6818 }
6819
6820 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6821 this work is done by liveness analysis (mark_regs_live_at_end).
6822 Special care is needed for functions containing landing pads. Landing pads
6823 may use the eh registers, but the code which sets these registers is not
6824 contained in that function. Hence s390_regs_ever_clobbered is not able to
6825 deal with this automatically. */
6826 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6827 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6828 if (crtl->calls_eh_return
6829 || (cfun->machine->has_landing_pad_p
6830 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6831 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6832
6833 /* For nonlocal gotos all call-saved registers have to be saved.
6834 This flag is also set for the unwinding code in libgcc.
6835 See expand_builtin_unwind_init. For regs_ever_live this is done by
6836 reload. */
6837 if (cfun->has_nonlocal_label)
6838 for (i = 0; i < 16; i++)
6839 if (!call_really_used_regs[i])
6840 regs_ever_clobbered[i] = 1;
6841
6842 FOR_EACH_BB (cur_bb)
6843 {
6844 FOR_BB_INSNS (cur_bb, cur_insn)
6845 {
6846 if (INSN_P (cur_insn))
6847 note_stores (PATTERN (cur_insn),
6848 s390_reg_clobbered_rtx,
6849 regs_ever_clobbered);
6850 }
6851 }
6852 }
6853
6854 /* Determine the frame area which actually has to be accessed
6855 in the function epilogue. The values are stored at the
6856 given pointers AREA_BOTTOM (address of the lowest used stack
6857 address) and AREA_TOP (address of the first item which does
6858 not belong to the stack frame). */
6859
6860 static void
6861 s390_frame_area (int *area_bottom, int *area_top)
6862 {
6863 int b, t;
6864 int i;
6865
6866 b = INT_MAX;
6867 t = INT_MIN;
6868
6869 if (cfun_frame_layout.first_restore_gpr != -1)
6870 {
6871 b = (cfun_frame_layout.gprs_offset
6872 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6873 t = b + (cfun_frame_layout.last_restore_gpr
6874 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6875 }
6876
6877 if (TARGET_64BIT && cfun_save_high_fprs_p)
6878 {
6879 b = MIN (b, cfun_frame_layout.f8_offset);
6880 t = MAX (t, (cfun_frame_layout.f8_offset
6881 + cfun_frame_layout.high_fprs * 8));
6882 }
6883
6884 if (!TARGET_64BIT)
6885 for (i = 2; i < 4; i++)
6886 if (cfun_fpr_bit_p (i))
6887 {
6888 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6889 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6890 }
6891
6892 *area_bottom = b;
6893 *area_top = t;
6894 }
6895
6896 /* Fill cfun->machine with info about register usage of current function.
6897 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6898
6899 static void
6900 s390_register_info (int clobbered_regs[])
6901 {
6902 int i, j;
6903
6904 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6905 cfun_frame_layout.fpr_bitmap = 0;
6906 cfun_frame_layout.high_fprs = 0;
6907 if (TARGET_64BIT)
6908 for (i = 24; i < 32; i++)
6909 if (df_regs_ever_live_p (i) && !global_regs[i])
6910 {
6911 cfun_set_fpr_bit (i - 16);
6912 cfun_frame_layout.high_fprs++;
6913 }
6914
6915 /* Find first and last gpr to be saved. We trust regs_ever_live
6916 data, except that we don't save and restore global registers.
6917
6918 Also, all registers with special meaning to the compiler need
6919 to be handled extra. */
6920
6921 s390_regs_ever_clobbered (clobbered_regs);
6922
6923 for (i = 0; i < 16; i++)
6924 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6925
6926 if (frame_pointer_needed)
6927 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6928
6929 if (flag_pic)
6930 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6931 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6932
6933 clobbered_regs[BASE_REGNUM]
6934 |= (cfun->machine->base_reg
6935 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6936
6937 clobbered_regs[RETURN_REGNUM]
6938 |= (!current_function_is_leaf
6939 || TARGET_TPF_PROFILING
6940 || cfun->machine->split_branches_pending_p
6941 || cfun_frame_layout.save_return_addr_p
6942 || crtl->calls_eh_return
6943 || cfun->stdarg);
6944
6945 clobbered_regs[STACK_POINTER_REGNUM]
6946 |= (!current_function_is_leaf
6947 || TARGET_TPF_PROFILING
6948 || cfun_save_high_fprs_p
6949 || get_frame_size () > 0
6950 || cfun->calls_alloca
6951 || cfun->stdarg);
6952
6953 for (i = 6; i < 16; i++)
6954 if (df_regs_ever_live_p (i) || clobbered_regs[i])
6955 break;
6956 for (j = 15; j > i; j--)
6957 if (df_regs_ever_live_p (j) || clobbered_regs[j])
6958 break;
6959
6960 if (i == 16)
6961 {
6962 /* Nothing to save/restore. */
6963 cfun_frame_layout.first_save_gpr_slot = -1;
6964 cfun_frame_layout.last_save_gpr_slot = -1;
6965 cfun_frame_layout.first_save_gpr = -1;
6966 cfun_frame_layout.first_restore_gpr = -1;
6967 cfun_frame_layout.last_save_gpr = -1;
6968 cfun_frame_layout.last_restore_gpr = -1;
6969 }
6970 else
6971 {
6972 /* Save slots for gprs from i to j. */
6973 cfun_frame_layout.first_save_gpr_slot = i;
6974 cfun_frame_layout.last_save_gpr_slot = j;
6975
6976 for (i = cfun_frame_layout.first_save_gpr_slot;
6977 i < cfun_frame_layout.last_save_gpr_slot + 1;
6978 i++)
6979 if (clobbered_regs[i])
6980 break;
6981
6982 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6983 if (clobbered_regs[j])
6984 break;
6985
6986 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6987 {
6988 /* Nothing to save/restore. */
6989 cfun_frame_layout.first_save_gpr = -1;
6990 cfun_frame_layout.first_restore_gpr = -1;
6991 cfun_frame_layout.last_save_gpr = -1;
6992 cfun_frame_layout.last_restore_gpr = -1;
6993 }
6994 else
6995 {
6996 /* Save / Restore from gpr i to j. */
6997 cfun_frame_layout.first_save_gpr = i;
6998 cfun_frame_layout.first_restore_gpr = i;
6999 cfun_frame_layout.last_save_gpr = j;
7000 cfun_frame_layout.last_restore_gpr = j;
7001 }
7002 }
7003
7004 if (cfun->stdarg)
7005 {
7006 /* Varargs functions need to save gprs 2 to 6. */
7007 if (cfun->va_list_gpr_size
7008 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7009 {
7010 int min_gpr = crtl->args.info.gprs;
7011 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7012 if (max_gpr > GP_ARG_NUM_REG)
7013 max_gpr = GP_ARG_NUM_REG;
7014
7015 if (cfun_frame_layout.first_save_gpr == -1
7016 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7017 {
7018 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7019 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7020 }
7021
7022 if (cfun_frame_layout.last_save_gpr == -1
7023 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7024 {
7025 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7026 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7027 }
7028 }
7029
7030 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7031 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7032 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7033 {
7034 int min_fpr = crtl->args.info.fprs;
7035 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7036 if (max_fpr > FP_ARG_NUM_REG)
7037 max_fpr = FP_ARG_NUM_REG;
7038
7039 /* ??? This is currently required to ensure proper location
7040 of the fpr save slots within the va_list save area. */
7041 if (TARGET_PACKED_STACK)
7042 min_fpr = 0;
7043
7044 for (i = min_fpr; i < max_fpr; i++)
7045 cfun_set_fpr_bit (i);
7046 }
7047 }
7048
7049 if (!TARGET_64BIT)
7050 for (i = 2; i < 4; i++)
7051 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7052 cfun_set_fpr_bit (i);
7053 }
7054
7055 /* Fill cfun->machine with info about frame of current function. */
7056
7057 static void
7058 s390_frame_info (void)
7059 {
7060 int i;
7061
7062 cfun_frame_layout.frame_size = get_frame_size ();
7063 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7064 fatal_error ("total size of local variables exceeds architecture limit");
7065
7066 if (!TARGET_PACKED_STACK)
7067 {
7068 cfun_frame_layout.backchain_offset = 0;
7069 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
7070 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7071 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7072 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7073 * UNITS_PER_WORD);
7074 }
7075 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7076 {
7077 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7078 - UNITS_PER_WORD);
7079 cfun_frame_layout.gprs_offset
7080 = (cfun_frame_layout.backchain_offset
7081 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7082 * UNITS_PER_WORD);
7083
7084 if (TARGET_64BIT)
7085 {
7086 cfun_frame_layout.f4_offset
7087 = (cfun_frame_layout.gprs_offset
7088 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7089
7090 cfun_frame_layout.f0_offset
7091 = (cfun_frame_layout.f4_offset
7092 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7093 }
7094 else
7095 {
7096 /* On 31 bit we have to care about alignment of the
7097 floating point regs to provide fastest access. */
7098 cfun_frame_layout.f0_offset
7099 = ((cfun_frame_layout.gprs_offset
7100 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7101 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7102
7103 cfun_frame_layout.f4_offset
7104 = (cfun_frame_layout.f0_offset
7105 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7106 }
7107 }
7108 else /* no backchain */
7109 {
7110 cfun_frame_layout.f4_offset
7111 = (STACK_POINTER_OFFSET
7112 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7113
7114 cfun_frame_layout.f0_offset
7115 = (cfun_frame_layout.f4_offset
7116 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7117
7118 cfun_frame_layout.gprs_offset
7119 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7120 }
7121
7122 if (current_function_is_leaf
7123 && !TARGET_TPF_PROFILING
7124 && cfun_frame_layout.frame_size == 0
7125 && !cfun_save_high_fprs_p
7126 && !cfun->calls_alloca
7127 && !cfun->stdarg)
7128 return;
7129
7130 if (!TARGET_PACKED_STACK)
7131 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7132 + crtl->outgoing_args_size
7133 + cfun_frame_layout.high_fprs * 8);
7134 else
7135 {
7136 if (TARGET_BACKCHAIN)
7137 cfun_frame_layout.frame_size += UNITS_PER_WORD;
7138
7139 /* No alignment trouble here because f8-f15 are only saved under
7140 64 bit. */
7141 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7142 cfun_frame_layout.f4_offset),
7143 cfun_frame_layout.gprs_offset)
7144 - cfun_frame_layout.high_fprs * 8);
7145
7146 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7147
7148 for (i = 0; i < 8; i++)
7149 if (cfun_fpr_bit_p (i))
7150 cfun_frame_layout.frame_size += 8;
7151
7152 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7153
7154 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7155 the frame size to sustain 8 byte alignment of stack frames. */
7156 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7157 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7158 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7159
7160 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7161 }
7162 }
7163
7164 /* Generate frame layout. Fills in register and frame data for the current
7165 function in cfun->machine. This routine can be called multiple times;
7166 it will re-do the complete frame layout every time. */
7167
7168 static void
7169 s390_init_frame_layout (void)
7170 {
7171 HOST_WIDE_INT frame_size;
7172 int base_used;
7173 int clobbered_regs[16];
7174
7175 /* On S/390 machines, we may need to perform branch splitting, which
7176 will require both base and return address register. We have no
7177 choice but to assume we're going to need them until right at the
7178 end of the machine dependent reorg phase. */
7179 if (!TARGET_CPU_ZARCH)
7180 cfun->machine->split_branches_pending_p = true;
7181
7182 do
7183 {
7184 frame_size = cfun_frame_layout.frame_size;
7185
7186 /* Try to predict whether we'll need the base register. */
7187 base_used = cfun->machine->split_branches_pending_p
7188 || crtl->uses_const_pool
7189 || (!DISP_IN_RANGE (frame_size)
7190 && !CONST_OK_FOR_K (frame_size));
7191
7192 /* Decide which register to use as literal pool base. In small
7193 leaf functions, try to use an unused call-clobbered register
7194 as base register to avoid save/restore overhead. */
7195 if (!base_used)
7196 cfun->machine->base_reg = NULL_RTX;
7197 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7198 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7199 else
7200 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7201
7202 s390_register_info (clobbered_regs);
7203 s390_frame_info ();
7204 }
7205 while (frame_size != cfun_frame_layout.frame_size);
7206 }
7207
7208 /* Update frame layout. Recompute actual register save data based on
7209 current info and update regs_ever_live for the special registers.
7210 May be called multiple times, but may never cause *more* registers
7211 to be saved than s390_init_frame_layout allocated room for. */
7212
7213 static void
7214 s390_update_frame_layout (void)
7215 {
7216 int clobbered_regs[16];
7217
7218 s390_register_info (clobbered_regs);
7219
7220 df_set_regs_ever_live (BASE_REGNUM,
7221 clobbered_regs[BASE_REGNUM] ? true : false);
7222 df_set_regs_ever_live (RETURN_REGNUM,
7223 clobbered_regs[RETURN_REGNUM] ? true : false);
7224 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7225 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7226
7227 if (cfun->machine->base_reg)
7228 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7229 }
7230
7231 /* Return true if it is legal to put a value with MODE into REGNO. */
7232
7233 bool
7234 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7235 {
7236 switch (REGNO_REG_CLASS (regno))
7237 {
7238 case FP_REGS:
7239 if (REGNO_PAIR_OK (regno, mode))
7240 {
7241 if (mode == SImode || mode == DImode)
7242 return true;
7243
7244 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7245 return true;
7246 }
7247 break;
7248 case ADDR_REGS:
7249 if (FRAME_REGNO_P (regno) && mode == Pmode)
7250 return true;
7251
7252 /* fallthrough */
7253 case GENERAL_REGS:
7254 if (REGNO_PAIR_OK (regno, mode))
7255 {
7256 if (TARGET_64BIT
7257 || (mode != TFmode && mode != TCmode && mode != TDmode))
7258 return true;
7259 }
7260 break;
7261 case CC_REGS:
7262 if (GET_MODE_CLASS (mode) == MODE_CC)
7263 return true;
7264 break;
7265 case ACCESS_REGS:
7266 if (REGNO_PAIR_OK (regno, mode))
7267 {
7268 if (mode == SImode || mode == Pmode)
7269 return true;
7270 }
7271 break;
7272 default:
7273 return false;
7274 }
7275
7276 return false;
7277 }
7278
7279 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7280
7281 bool
7282 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7283 {
7284 /* Once we've decided upon a register to use as base register, it must
7285 no longer be used for any other purpose. */
7286 if (cfun->machine->base_reg)
7287 if (REGNO (cfun->machine->base_reg) == old_reg
7288 || REGNO (cfun->machine->base_reg) == new_reg)
7289 return false;
7290
7291 return true;
7292 }
7293
7294 /* Maximum number of registers to represent a value of mode MODE
7295 in a register of class RCLASS. */
7296
7297 bool
7298 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7299 {
7300 switch (rclass)
7301 {
7302 case FP_REGS:
7303 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7304 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7305 else
7306 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7307 case ACCESS_REGS:
7308 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7309 default:
7310 break;
7311 }
7312 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7313 }
7314
7315 /* Return true if register FROM can be eliminated via register TO. */
7316
7317 bool
7318 s390_can_eliminate (int from, int to)
7319 {
7320 /* On zSeries machines, we have not marked the base register as fixed.
7321 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7322 If a function requires the base register, we say here that this
7323 elimination cannot be performed. This will cause reload to free
7324 up the base register (as if it were fixed). On the other hand,
7325 if the current function does *not* require the base register, we
7326 say here the elimination succeeds, which in turn allows reload
7327 to allocate the base register for any other purpose. */
7328 if (from == BASE_REGNUM && to == BASE_REGNUM)
7329 {
7330 if (TARGET_CPU_ZARCH)
7331 {
7332 s390_init_frame_layout ();
7333 return cfun->machine->base_reg == NULL_RTX;
7334 }
7335
7336 return false;
7337 }
7338
7339 /* Everything else must point into the stack frame. */
7340 gcc_assert (to == STACK_POINTER_REGNUM
7341 || to == HARD_FRAME_POINTER_REGNUM);
7342
7343 gcc_assert (from == FRAME_POINTER_REGNUM
7344 || from == ARG_POINTER_REGNUM
7345 || from == RETURN_ADDRESS_POINTER_REGNUM);
7346
7347 /* Make sure we actually saved the return address. */
7348 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7349 if (!crtl->calls_eh_return
7350 && !cfun->stdarg
7351 && !cfun_frame_layout.save_return_addr_p)
7352 return false;
7353
7354 return true;
7355 }
7356
7357 /* Return offset between register FROM and TO initially after prolog. */
7358
7359 HOST_WIDE_INT
7360 s390_initial_elimination_offset (int from, int to)
7361 {
7362 HOST_WIDE_INT offset;
7363 int index;
7364
7365 /* ??? Why are we called for non-eliminable pairs? */
7366 if (!s390_can_eliminate (from, to))
7367 return 0;
7368
7369 switch (from)
7370 {
7371 case FRAME_POINTER_REGNUM:
7372 offset = (get_frame_size()
7373 + STACK_POINTER_OFFSET
7374 + crtl->outgoing_args_size);
7375 break;
7376
7377 case ARG_POINTER_REGNUM:
7378 s390_init_frame_layout ();
7379 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7380 break;
7381
7382 case RETURN_ADDRESS_POINTER_REGNUM:
7383 s390_init_frame_layout ();
7384 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7385 gcc_assert (index >= 0);
7386 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7387 offset += index * UNITS_PER_WORD;
7388 break;
7389
7390 case BASE_REGNUM:
7391 offset = 0;
7392 break;
7393
7394 default:
7395 gcc_unreachable ();
7396 }
7397
7398 return offset;
7399 }
7400
7401 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7402 to register BASE. Return generated insn. */
7403
7404 static rtx
7405 save_fpr (rtx base, int offset, int regnum)
7406 {
7407 rtx addr;
7408 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7409
7410 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7411 set_mem_alias_set (addr, get_varargs_alias_set ());
7412 else
7413 set_mem_alias_set (addr, get_frame_alias_set ());
7414
7415 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7416 }
7417
7418 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7419 to register BASE. Return generated insn. */
7420
7421 static rtx
7422 restore_fpr (rtx base, int offset, int regnum)
7423 {
7424 rtx addr;
7425 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7426 set_mem_alias_set (addr, get_frame_alias_set ());
7427
7428 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7429 }
7430
7431 /* Generate insn to save registers FIRST to LAST into
7432 the register save area located at offset OFFSET
7433 relative to register BASE. */
7434
7435 static rtx
7436 save_gprs (rtx base, int offset, int first, int last)
7437 {
7438 rtx addr, insn, note;
7439 int i;
7440
7441 addr = plus_constant (base, offset);
7442 addr = gen_rtx_MEM (Pmode, addr);
7443
7444 set_mem_alias_set (addr, get_frame_alias_set ());
7445
7446 /* Special-case single register. */
7447 if (first == last)
7448 {
7449 if (TARGET_64BIT)
7450 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7451 else
7452 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7453
7454 RTX_FRAME_RELATED_P (insn) = 1;
7455 return insn;
7456 }
7457
7458
7459 insn = gen_store_multiple (addr,
7460 gen_rtx_REG (Pmode, first),
7461 GEN_INT (last - first + 1));
7462
7463 if (first <= 6 && cfun->stdarg)
7464 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7465 {
7466 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7467
7468 if (first + i <= 6)
7469 set_mem_alias_set (mem, get_varargs_alias_set ());
7470 }
7471
7472 /* We need to set the FRAME_RELATED flag on all SETs
7473 inside the store-multiple pattern.
7474
7475 However, we must not emit DWARF records for registers 2..5
7476 if they are stored for use by variable arguments ...
7477
7478 ??? Unfortunately, it is not enough to simply not the
7479 FRAME_RELATED flags for those SETs, because the first SET
7480 of the PARALLEL is always treated as if it had the flag
7481 set, even if it does not. Therefore we emit a new pattern
7482 without those registers as REG_FRAME_RELATED_EXPR note. */
7483
7484 if (first >= 6)
7485 {
7486 rtx pat = PATTERN (insn);
7487
7488 for (i = 0; i < XVECLEN (pat, 0); i++)
7489 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
7490 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7491
7492 RTX_FRAME_RELATED_P (insn) = 1;
7493 }
7494 else if (last >= 6)
7495 {
7496 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
7497 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7498 gen_rtx_REG (Pmode, 6),
7499 GEN_INT (last - 6 + 1));
7500 note = PATTERN (note);
7501
7502 REG_NOTES (insn) =
7503 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7504 note, REG_NOTES (insn));
7505
7506 for (i = 0; i < XVECLEN (note, 0); i++)
7507 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
7508 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7509
7510 RTX_FRAME_RELATED_P (insn) = 1;
7511 }
7512
7513 return insn;
7514 }
7515
7516 /* Generate insn to restore registers FIRST to LAST from
7517 the register save area located at offset OFFSET
7518 relative to register BASE. */
7519
7520 static rtx
7521 restore_gprs (rtx base, int offset, int first, int last)
7522 {
7523 rtx addr, insn;
7524
7525 addr = plus_constant (base, offset);
7526 addr = gen_rtx_MEM (Pmode, addr);
7527 set_mem_alias_set (addr, get_frame_alias_set ());
7528
7529 /* Special-case single register. */
7530 if (first == last)
7531 {
7532 if (TARGET_64BIT)
7533 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7534 else
7535 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7536
7537 return insn;
7538 }
7539
7540 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7541 addr,
7542 GEN_INT (last - first + 1));
7543 return insn;
7544 }
7545
7546 /* Return insn sequence to load the GOT register. */
7547
7548 static GTY(()) rtx got_symbol;
7549 rtx
7550 s390_load_got (void)
7551 {
7552 rtx insns;
7553
7554 if (!got_symbol)
7555 {
7556 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7557 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7558 }
7559
7560 start_sequence ();
7561
7562 if (TARGET_CPU_ZARCH)
7563 {
7564 emit_move_insn (pic_offset_table_rtx, got_symbol);
7565 }
7566 else
7567 {
7568 rtx offset;
7569
7570 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7571 UNSPEC_LTREL_OFFSET);
7572 offset = gen_rtx_CONST (Pmode, offset);
7573 offset = force_const_mem (Pmode, offset);
7574
7575 emit_move_insn (pic_offset_table_rtx, offset);
7576
7577 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7578 UNSPEC_LTREL_BASE);
7579 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7580
7581 emit_move_insn (pic_offset_table_rtx, offset);
7582 }
7583
7584 insns = get_insns ();
7585 end_sequence ();
7586 return insns;
7587 }
7588
7589 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7590 and the change to the stack pointer. */
7591
7592 static void
7593 s390_emit_stack_tie (void)
7594 {
7595 rtx mem = gen_frame_mem (BLKmode,
7596 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7597
7598 emit_insn (gen_stack_tie (mem));
7599 }
7600
7601 /* Expand the prologue into a bunch of separate insns. */
7602
7603 void
7604 s390_emit_prologue (void)
7605 {
7606 rtx insn, addr;
7607 rtx temp_reg;
7608 int i;
7609 int offset;
7610 int next_fpr = 0;
7611
7612 /* Complete frame layout. */
7613
7614 s390_update_frame_layout ();
7615
7616 /* Annotate all constant pool references to let the scheduler know
7617 they implicitly use the base register. */
7618
7619 push_topmost_sequence ();
7620
7621 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7622 if (INSN_P (insn))
7623 {
7624 annotate_constant_pool_refs (&PATTERN (insn));
7625 df_insn_rescan (insn);
7626 }
7627
7628 pop_topmost_sequence ();
7629
7630 /* Choose best register to use for temp use within prologue.
7631 See below for why TPF must use the register 1. */
7632
7633 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7634 && !current_function_is_leaf
7635 && !TARGET_TPF_PROFILING)
7636 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7637 else
7638 temp_reg = gen_rtx_REG (Pmode, 1);
7639
7640 /* Save call saved gprs. */
7641 if (cfun_frame_layout.first_save_gpr != -1)
7642 {
7643 insn = save_gprs (stack_pointer_rtx,
7644 cfun_frame_layout.gprs_offset +
7645 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7646 - cfun_frame_layout.first_save_gpr_slot),
7647 cfun_frame_layout.first_save_gpr,
7648 cfun_frame_layout.last_save_gpr);
7649 emit_insn (insn);
7650 }
7651
7652 /* Dummy insn to mark literal pool slot. */
7653
7654 if (cfun->machine->base_reg)
7655 emit_insn (gen_main_pool (cfun->machine->base_reg));
7656
7657 offset = cfun_frame_layout.f0_offset;
7658
7659 /* Save f0 and f2. */
7660 for (i = 0; i < 2; i++)
7661 {
7662 if (cfun_fpr_bit_p (i))
7663 {
7664 save_fpr (stack_pointer_rtx, offset, i + 16);
7665 offset += 8;
7666 }
7667 else if (!TARGET_PACKED_STACK)
7668 offset += 8;
7669 }
7670
7671 /* Save f4 and f6. */
7672 offset = cfun_frame_layout.f4_offset;
7673 for (i = 2; i < 4; i++)
7674 {
7675 if (cfun_fpr_bit_p (i))
7676 {
7677 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7678 offset += 8;
7679
7680 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7681 therefore are not frame related. */
7682 if (!call_really_used_regs[i + 16])
7683 RTX_FRAME_RELATED_P (insn) = 1;
7684 }
7685 else if (!TARGET_PACKED_STACK)
7686 offset += 8;
7687 }
7688
7689 if (TARGET_PACKED_STACK
7690 && cfun_save_high_fprs_p
7691 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7692 {
7693 offset = (cfun_frame_layout.f8_offset
7694 + (cfun_frame_layout.high_fprs - 1) * 8);
7695
7696 for (i = 15; i > 7 && offset >= 0; i--)
7697 if (cfun_fpr_bit_p (i))
7698 {
7699 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7700
7701 RTX_FRAME_RELATED_P (insn) = 1;
7702 offset -= 8;
7703 }
7704 if (offset >= cfun_frame_layout.f8_offset)
7705 next_fpr = i + 16;
7706 }
7707
7708 if (!TARGET_PACKED_STACK)
7709 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7710
7711 /* Decrement stack pointer. */
7712
7713 if (cfun_frame_layout.frame_size > 0)
7714 {
7715 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7716
7717 if (s390_stack_size)
7718 {
7719 HOST_WIDE_INT stack_guard;
7720
7721 if (s390_stack_guard)
7722 stack_guard = s390_stack_guard;
7723 else
7724 {
7725 /* If no value for stack guard is provided the smallest power of 2
7726 larger than the current frame size is chosen. */
7727 stack_guard = 1;
7728 while (stack_guard < cfun_frame_layout.frame_size)
7729 stack_guard <<= 1;
7730 }
7731
7732 if (cfun_frame_layout.frame_size >= s390_stack_size)
7733 {
7734 warning (0, "frame size of function %qs is "
7735 HOST_WIDE_INT_PRINT_DEC
7736 " bytes exceeding user provided stack limit of "
7737 HOST_WIDE_INT_PRINT_DEC " bytes. "
7738 "An unconditional trap is added.",
7739 current_function_name(), cfun_frame_layout.frame_size,
7740 s390_stack_size);
7741 emit_insn (gen_trap ());
7742 }
7743 else
7744 {
7745 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7746 & ~(stack_guard - 1));
7747 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7748 GEN_INT (stack_check_mask));
7749 if (TARGET_64BIT)
7750 gen_cmpdi (t, const0_rtx);
7751 else
7752 gen_cmpsi (t, const0_rtx);
7753
7754 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7755 gen_rtx_REG (CCmode,
7756 CC_REGNUM),
7757 const0_rtx),
7758 const0_rtx));
7759 }
7760 }
7761
7762 if (s390_warn_framesize > 0
7763 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7764 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7765 current_function_name (), cfun_frame_layout.frame_size);
7766
7767 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7768 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7769
7770 /* Save incoming stack pointer into temp reg. */
7771 if (TARGET_BACKCHAIN || next_fpr)
7772 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7773
7774 /* Subtract frame size from stack pointer. */
7775
7776 if (DISP_IN_RANGE (INTVAL (frame_off)))
7777 {
7778 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7779 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7780 frame_off));
7781 insn = emit_insn (insn);
7782 }
7783 else
7784 {
7785 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7786 frame_off = force_const_mem (Pmode, frame_off);
7787
7788 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7789 annotate_constant_pool_refs (&PATTERN (insn));
7790 }
7791
7792 RTX_FRAME_RELATED_P (insn) = 1;
7793 REG_NOTES (insn) =
7794 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7795 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7796 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7797 GEN_INT (-cfun_frame_layout.frame_size))),
7798 REG_NOTES (insn));
7799
7800 /* Set backchain. */
7801
7802 if (TARGET_BACKCHAIN)
7803 {
7804 if (cfun_frame_layout.backchain_offset)
7805 addr = gen_rtx_MEM (Pmode,
7806 plus_constant (stack_pointer_rtx,
7807 cfun_frame_layout.backchain_offset));
7808 else
7809 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7810 set_mem_alias_set (addr, get_frame_alias_set ());
7811 insn = emit_insn (gen_move_insn (addr, temp_reg));
7812 }
7813
7814 /* If we support asynchronous exceptions (e.g. for Java),
7815 we need to make sure the backchain pointer is set up
7816 before any possibly trapping memory access. */
7817
7818 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7819 {
7820 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7821 emit_clobber (addr);
7822 }
7823 }
7824
7825 /* Save fprs 8 - 15 (64 bit ABI). */
7826
7827 if (cfun_save_high_fprs_p && next_fpr)
7828 {
7829 /* If the stack might be accessed through a different register
7830 we have to make sure that the stack pointer decrement is not
7831 moved below the use of the stack slots. */
7832 s390_emit_stack_tie ();
7833
7834 insn = emit_insn (gen_add2_insn (temp_reg,
7835 GEN_INT (cfun_frame_layout.f8_offset)));
7836
7837 offset = 0;
7838
7839 for (i = 24; i <= next_fpr; i++)
7840 if (cfun_fpr_bit_p (i - 16))
7841 {
7842 rtx addr = plus_constant (stack_pointer_rtx,
7843 cfun_frame_layout.frame_size
7844 + cfun_frame_layout.f8_offset
7845 + offset);
7846
7847 insn = save_fpr (temp_reg, offset, i);
7848 offset += 8;
7849 RTX_FRAME_RELATED_P (insn) = 1;
7850 REG_NOTES (insn) =
7851 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7852 gen_rtx_SET (VOIDmode,
7853 gen_rtx_MEM (DFmode, addr),
7854 gen_rtx_REG (DFmode, i)),
7855 REG_NOTES (insn));
7856 }
7857 }
7858
7859 /* Set frame pointer, if needed. */
7860
7861 if (frame_pointer_needed)
7862 {
7863 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7864 RTX_FRAME_RELATED_P (insn) = 1;
7865 }
7866
7867 /* Set up got pointer, if needed. */
7868
7869 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7870 {
7871 rtx insns = s390_load_got ();
7872
7873 for (insn = insns; insn; insn = NEXT_INSN (insn))
7874 annotate_constant_pool_refs (&PATTERN (insn));
7875
7876 emit_insn (insns);
7877 }
7878
7879 if (TARGET_TPF_PROFILING)
7880 {
7881 /* Generate a BAS instruction to serve as a function
7882 entry intercept to facilitate the use of tracing
7883 algorithms located at the branch target. */
7884 emit_insn (gen_prologue_tpf ());
7885
7886 /* Emit a blockage here so that all code
7887 lies between the profiling mechanisms. */
7888 emit_insn (gen_blockage ());
7889 }
7890 }
7891
7892 /* Expand the epilogue into a bunch of separate insns. */
7893
7894 void
7895 s390_emit_epilogue (bool sibcall)
7896 {
7897 rtx frame_pointer, return_reg;
7898 int area_bottom, area_top, offset = 0;
7899 int next_offset;
7900 rtvec p;
7901 int i;
7902
7903 if (TARGET_TPF_PROFILING)
7904 {
7905
7906 /* Generate a BAS instruction to serve as a function
7907 entry intercept to facilitate the use of tracing
7908 algorithms located at the branch target. */
7909
7910 /* Emit a blockage here so that all code
7911 lies between the profiling mechanisms. */
7912 emit_insn (gen_blockage ());
7913
7914 emit_insn (gen_epilogue_tpf ());
7915 }
7916
7917 /* Check whether to use frame or stack pointer for restore. */
7918
7919 frame_pointer = (frame_pointer_needed
7920 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7921
7922 s390_frame_area (&area_bottom, &area_top);
7923
7924 /* Check whether we can access the register save area.
7925 If not, increment the frame pointer as required. */
7926
7927 if (area_top <= area_bottom)
7928 {
7929 /* Nothing to restore. */
7930 }
7931 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7932 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7933 {
7934 /* Area is in range. */
7935 offset = cfun_frame_layout.frame_size;
7936 }
7937 else
7938 {
7939 rtx insn, frame_off;
7940
7941 offset = area_bottom < 0 ? -area_bottom : 0;
7942 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7943
7944 if (DISP_IN_RANGE (INTVAL (frame_off)))
7945 {
7946 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7947 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7948 insn = emit_insn (insn);
7949 }
7950 else
7951 {
7952 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7953 frame_off = force_const_mem (Pmode, frame_off);
7954
7955 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7956 annotate_constant_pool_refs (&PATTERN (insn));
7957 }
7958 }
7959
7960 /* Restore call saved fprs. */
7961
7962 if (TARGET_64BIT)
7963 {
7964 if (cfun_save_high_fprs_p)
7965 {
7966 next_offset = cfun_frame_layout.f8_offset;
7967 for (i = 24; i < 32; i++)
7968 {
7969 if (cfun_fpr_bit_p (i - 16))
7970 {
7971 restore_fpr (frame_pointer,
7972 offset + next_offset, i);
7973 next_offset += 8;
7974 }
7975 }
7976 }
7977
7978 }
7979 else
7980 {
7981 next_offset = cfun_frame_layout.f4_offset;
7982 for (i = 18; i < 20; i++)
7983 {
7984 if (cfun_fpr_bit_p (i - 16))
7985 {
7986 restore_fpr (frame_pointer,
7987 offset + next_offset, i);
7988 next_offset += 8;
7989 }
7990 else if (!TARGET_PACKED_STACK)
7991 next_offset += 8;
7992 }
7993
7994 }
7995
7996 /* Return register. */
7997
7998 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7999
8000 /* Restore call saved gprs. */
8001
8002 if (cfun_frame_layout.first_restore_gpr != -1)
8003 {
8004 rtx insn, addr;
8005 int i;
8006
8007 /* Check for global register and save them
8008 to stack location from where they get restored. */
8009
8010 for (i = cfun_frame_layout.first_restore_gpr;
8011 i <= cfun_frame_layout.last_restore_gpr;
8012 i++)
8013 {
8014 /* These registers are special and need to be
8015 restored in any case. */
8016 if (i == STACK_POINTER_REGNUM
8017 || i == RETURN_REGNUM
8018 || i == BASE_REGNUM
8019 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
8020 continue;
8021
8022 if (global_regs[i])
8023 {
8024 addr = plus_constant (frame_pointer,
8025 offset + cfun_frame_layout.gprs_offset
8026 + (i - cfun_frame_layout.first_save_gpr_slot)
8027 * UNITS_PER_WORD);
8028 addr = gen_rtx_MEM (Pmode, addr);
8029 set_mem_alias_set (addr, get_frame_alias_set ());
8030 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8031 }
8032 }
8033
8034 if (! sibcall)
8035 {
8036 /* Fetch return address from stack before load multiple,
8037 this will do good for scheduling. */
8038
8039 if (cfun_frame_layout.save_return_addr_p
8040 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8041 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8042 {
8043 int return_regnum = find_unused_clobbered_reg();
8044 if (!return_regnum)
8045 return_regnum = 4;
8046 return_reg = gen_rtx_REG (Pmode, return_regnum);
8047
8048 addr = plus_constant (frame_pointer,
8049 offset + cfun_frame_layout.gprs_offset
8050 + (RETURN_REGNUM
8051 - cfun_frame_layout.first_save_gpr_slot)
8052 * UNITS_PER_WORD);
8053 addr = gen_rtx_MEM (Pmode, addr);
8054 set_mem_alias_set (addr, get_frame_alias_set ());
8055 emit_move_insn (return_reg, addr);
8056 }
8057 }
8058
8059 insn = restore_gprs (frame_pointer,
8060 offset + cfun_frame_layout.gprs_offset
8061 + (cfun_frame_layout.first_restore_gpr
8062 - cfun_frame_layout.first_save_gpr_slot)
8063 * UNITS_PER_WORD,
8064 cfun_frame_layout.first_restore_gpr,
8065 cfun_frame_layout.last_restore_gpr);
8066 emit_insn (insn);
8067 }
8068
8069 if (! sibcall)
8070 {
8071
8072 /* Return to caller. */
8073
8074 p = rtvec_alloc (2);
8075
8076 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8077 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8078 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8079 }
8080 }
8081
8082
8083 /* Return the size in bytes of a function argument of
8084 type TYPE and/or mode MODE. At least one of TYPE or
8085 MODE must be specified. */
8086
8087 static int
8088 s390_function_arg_size (enum machine_mode mode, const_tree type)
8089 {
8090 if (type)
8091 return int_size_in_bytes (type);
8092
8093 /* No type info available for some library calls ... */
8094 if (mode != BLKmode)
8095 return GET_MODE_SIZE (mode);
8096
8097 /* If we have neither type nor mode, abort */
8098 gcc_unreachable ();
8099 }
8100
8101 /* Return true if a function argument of type TYPE and mode MODE
8102 is to be passed in a floating-point register, if available. */
8103
8104 static bool
8105 s390_function_arg_float (enum machine_mode mode, tree type)
8106 {
8107 int size = s390_function_arg_size (mode, type);
8108 if (size > 8)
8109 return false;
8110
8111 /* Soft-float changes the ABI: no floating-point registers are used. */
8112 if (TARGET_SOFT_FLOAT)
8113 return false;
8114
8115 /* No type info available for some library calls ... */
8116 if (!type)
8117 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8118
8119 /* The ABI says that record types with a single member are treated
8120 just like that member would be. */
8121 while (TREE_CODE (type) == RECORD_TYPE)
8122 {
8123 tree field, single = NULL_TREE;
8124
8125 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8126 {
8127 if (TREE_CODE (field) != FIELD_DECL)
8128 continue;
8129
8130 if (single == NULL_TREE)
8131 single = TREE_TYPE (field);
8132 else
8133 return false;
8134 }
8135
8136 if (single == NULL_TREE)
8137 return false;
8138 else
8139 type = single;
8140 }
8141
8142 return TREE_CODE (type) == REAL_TYPE;
8143 }
8144
8145 /* Return true if a function argument of type TYPE and mode MODE
8146 is to be passed in an integer register, or a pair of integer
8147 registers, if available. */
8148
8149 static bool
8150 s390_function_arg_integer (enum machine_mode mode, tree type)
8151 {
8152 int size = s390_function_arg_size (mode, type);
8153 if (size > 8)
8154 return false;
8155
8156 /* No type info available for some library calls ... */
8157 if (!type)
8158 return GET_MODE_CLASS (mode) == MODE_INT
8159 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8160
8161 /* We accept small integral (and similar) types. */
8162 if (INTEGRAL_TYPE_P (type)
8163 || POINTER_TYPE_P (type)
8164 || TREE_CODE (type) == OFFSET_TYPE
8165 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8166 return true;
8167
8168 /* We also accept structs of size 1, 2, 4, 8 that are not
8169 passed in floating-point registers. */
8170 if (AGGREGATE_TYPE_P (type)
8171 && exact_log2 (size) >= 0
8172 && !s390_function_arg_float (mode, type))
8173 return true;
8174
8175 return false;
8176 }
8177
8178 /* Return 1 if a function argument of type TYPE and mode MODE
8179 is to be passed by reference. The ABI specifies that only
8180 structures of size 1, 2, 4, or 8 bytes are passed by value,
8181 all other structures (and complex numbers) are passed by
8182 reference. */
8183
8184 static bool
8185 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8186 enum machine_mode mode, const_tree type,
8187 bool named ATTRIBUTE_UNUSED)
8188 {
8189 int size = s390_function_arg_size (mode, type);
8190 if (size > 8)
8191 return true;
8192
8193 if (type)
8194 {
8195 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8196 return 1;
8197
8198 if (TREE_CODE (type) == COMPLEX_TYPE
8199 || TREE_CODE (type) == VECTOR_TYPE)
8200 return 1;
8201 }
8202
8203 return 0;
8204 }
8205
8206 /* Update the data in CUM to advance over an argument of mode MODE and
8207 data type TYPE. (TYPE is null for libcalls where that information
8208 may not be available.). The boolean NAMED specifies whether the
8209 argument is a named argument (as opposed to an unnamed argument
8210 matching an ellipsis). */
8211
8212 void
8213 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8214 tree type, int named ATTRIBUTE_UNUSED)
8215 {
8216 if (s390_function_arg_float (mode, type))
8217 {
8218 cum->fprs += 1;
8219 }
8220 else if (s390_function_arg_integer (mode, type))
8221 {
8222 int size = s390_function_arg_size (mode, type);
8223 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
8224 }
8225 else
8226 gcc_unreachable ();
8227 }
8228
8229 /* Define where to put the arguments to a function.
8230 Value is zero to push the argument on the stack,
8231 or a hard register in which to store the argument.
8232
8233 MODE is the argument's machine mode.
8234 TYPE is the data type of the argument (as a tree).
8235 This is null for libcalls where that information may
8236 not be available.
8237 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8238 the preceding args and about the function being called.
8239 NAMED is nonzero if this argument is a named parameter
8240 (otherwise it is an extra parameter matching an ellipsis).
8241
8242 On S/390, we use general purpose registers 2 through 6 to
8243 pass integer, pointer, and certain structure arguments, and
8244 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8245 to pass floating point arguments. All remaining arguments
8246 are pushed to the stack. */
8247
8248 rtx
8249 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8250 int named ATTRIBUTE_UNUSED)
8251 {
8252 if (s390_function_arg_float (mode, type))
8253 {
8254 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8255 return 0;
8256 else
8257 return gen_rtx_REG (mode, cum->fprs + 16);
8258 }
8259 else if (s390_function_arg_integer (mode, type))
8260 {
8261 int size = s390_function_arg_size (mode, type);
8262 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
8263
8264 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8265 return 0;
8266 else
8267 return gen_rtx_REG (mode, cum->gprs + 2);
8268 }
8269
8270 /* After the real arguments, expand_call calls us once again
8271 with a void_type_node type. Whatever we return here is
8272 passed as operand 2 to the call expanders.
8273
8274 We don't need this feature ... */
8275 else if (type == void_type_node)
8276 return const0_rtx;
8277
8278 gcc_unreachable ();
8279 }
8280
8281 /* Return true if return values of type TYPE should be returned
8282 in a memory buffer whose address is passed by the caller as
8283 hidden first argument. */
8284
8285 static bool
8286 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8287 {
8288 /* We accept small integral (and similar) types. */
8289 if (INTEGRAL_TYPE_P (type)
8290 || POINTER_TYPE_P (type)
8291 || TREE_CODE (type) == OFFSET_TYPE
8292 || TREE_CODE (type) == REAL_TYPE)
8293 return int_size_in_bytes (type) > 8;
8294
8295 /* Aggregates and similar constructs are always returned
8296 in memory. */
8297 if (AGGREGATE_TYPE_P (type)
8298 || TREE_CODE (type) == COMPLEX_TYPE
8299 || TREE_CODE (type) == VECTOR_TYPE)
8300 return true;
8301
8302 /* ??? We get called on all sorts of random stuff from
8303 aggregate_value_p. We can't abort, but it's not clear
8304 what's safe to return. Pretend it's a struct I guess. */
8305 return true;
8306 }
8307
8308 /* Define where to return a (scalar) value of type TYPE.
8309 If TYPE is null, define where to return a (scalar)
8310 value of mode MODE from a libcall. */
8311
8312 rtx
8313 s390_function_value (const_tree type, enum machine_mode mode)
8314 {
8315 if (type)
8316 {
8317 int unsignedp = TYPE_UNSIGNED (type);
8318 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
8319 }
8320
8321 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8322 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8323
8324 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8325 return gen_rtx_REG (mode, 16);
8326 else
8327 return gen_rtx_REG (mode, 2);
8328 }
8329
8330
8331 /* Create and return the va_list datatype.
8332
8333 On S/390, va_list is an array type equivalent to
8334
8335 typedef struct __va_list_tag
8336 {
8337 long __gpr;
8338 long __fpr;
8339 void *__overflow_arg_area;
8340 void *__reg_save_area;
8341 } va_list[1];
8342
8343 where __gpr and __fpr hold the number of general purpose
8344 or floating point arguments used up to now, respectively,
8345 __overflow_arg_area points to the stack location of the
8346 next argument passed on the stack, and __reg_save_area
8347 always points to the start of the register area in the
8348 call frame of the current function. The function prologue
8349 saves all registers used for argument passing into this
8350 area if the function uses variable arguments. */
8351
8352 static tree
8353 s390_build_builtin_va_list (void)
8354 {
8355 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8356
8357 record = lang_hooks.types.make_type (RECORD_TYPE);
8358
8359 type_decl =
8360 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
8361
8362 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
8363 long_integer_type_node);
8364 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
8365 long_integer_type_node);
8366 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
8367 ptr_type_node);
8368 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
8369 ptr_type_node);
8370
8371 va_list_gpr_counter_field = f_gpr;
8372 va_list_fpr_counter_field = f_fpr;
8373
8374 DECL_FIELD_CONTEXT (f_gpr) = record;
8375 DECL_FIELD_CONTEXT (f_fpr) = record;
8376 DECL_FIELD_CONTEXT (f_ovf) = record;
8377 DECL_FIELD_CONTEXT (f_sav) = record;
8378
8379 TREE_CHAIN (record) = type_decl;
8380 TYPE_NAME (record) = type_decl;
8381 TYPE_FIELDS (record) = f_gpr;
8382 TREE_CHAIN (f_gpr) = f_fpr;
8383 TREE_CHAIN (f_fpr) = f_ovf;
8384 TREE_CHAIN (f_ovf) = f_sav;
8385
8386 layout_type (record);
8387
8388 /* The correct type is an array type of one element. */
8389 return build_array_type (record, build_index_type (size_zero_node));
8390 }
8391
8392 /* Implement va_start by filling the va_list structure VALIST.
8393 STDARG_P is always true, and ignored.
8394 NEXTARG points to the first anonymous stack argument.
8395
8396 The following global variables are used to initialize
8397 the va_list structure:
8398
8399 crtl->args.info:
8400 holds number of gprs and fprs used for named arguments.
8401 crtl->args.arg_offset_rtx:
8402 holds the offset of the first anonymous stack argument
8403 (relative to the virtual arg pointer). */
8404
8405 static void
8406 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8407 {
8408 HOST_WIDE_INT n_gpr, n_fpr;
8409 int off;
8410 tree f_gpr, f_fpr, f_ovf, f_sav;
8411 tree gpr, fpr, ovf, sav, t;
8412
8413 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8414 f_fpr = TREE_CHAIN (f_gpr);
8415 f_ovf = TREE_CHAIN (f_fpr);
8416 f_sav = TREE_CHAIN (f_ovf);
8417
8418 valist = build_va_arg_indirect_ref (valist);
8419 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8420 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8421 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8422 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8423
8424 /* Count number of gp and fp argument registers used. */
8425
8426 n_gpr = crtl->args.info.gprs;
8427 n_fpr = crtl->args.info.fprs;
8428
8429 if (cfun->va_list_gpr_size)
8430 {
8431 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8432 build_int_cst (NULL_TREE, n_gpr));
8433 TREE_SIDE_EFFECTS (t) = 1;
8434 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8435 }
8436
8437 if (cfun->va_list_fpr_size)
8438 {
8439 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8440 build_int_cst (NULL_TREE, n_fpr));
8441 TREE_SIDE_EFFECTS (t) = 1;
8442 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8443 }
8444
8445 /* Find the overflow area. */
8446 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8447 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8448 {
8449 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8450
8451 off = INTVAL (crtl->args.arg_offset_rtx);
8452 off = off < 0 ? 0 : off;
8453 if (TARGET_DEBUG_ARG)
8454 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8455 (int)n_gpr, (int)n_fpr, off);
8456
8457 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8458
8459 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8460 TREE_SIDE_EFFECTS (t) = 1;
8461 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8462 }
8463
8464 /* Find the register save area. */
8465 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8466 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8467 {
8468 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8469 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8470 size_int (-RETURN_REGNUM * UNITS_PER_WORD));
8471
8472 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8473 TREE_SIDE_EFFECTS (t) = 1;
8474 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8475 }
8476 }
8477
8478 /* Implement va_arg by updating the va_list structure
8479 VALIST as required to retrieve an argument of type
8480 TYPE, and returning that argument.
8481
8482 Generates code equivalent to:
8483
8484 if (integral value) {
8485 if (size <= 4 && args.gpr < 5 ||
8486 size > 4 && args.gpr < 4 )
8487 ret = args.reg_save_area[args.gpr+8]
8488 else
8489 ret = *args.overflow_arg_area++;
8490 } else if (float value) {
8491 if (args.fgpr < 2)
8492 ret = args.reg_save_area[args.fpr+64]
8493 else
8494 ret = *args.overflow_arg_area++;
8495 } else if (aggregate value) {
8496 if (args.gpr < 5)
8497 ret = *args.reg_save_area[args.gpr]
8498 else
8499 ret = **args.overflow_arg_area++;
8500 } */
8501
8502 static tree
8503 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8504 gimple_seq *post_p ATTRIBUTE_UNUSED)
8505 {
8506 tree f_gpr, f_fpr, f_ovf, f_sav;
8507 tree gpr, fpr, ovf, sav, reg, t, u;
8508 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8509 tree lab_false, lab_over, addr;
8510
8511 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8512 f_fpr = TREE_CHAIN (f_gpr);
8513 f_ovf = TREE_CHAIN (f_fpr);
8514 f_sav = TREE_CHAIN (f_ovf);
8515
8516 valist = build_va_arg_indirect_ref (valist);
8517 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8518 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8519 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8520
8521 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8522 both appear on a lhs. */
8523 valist = unshare_expr (valist);
8524 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8525
8526 size = int_size_in_bytes (type);
8527
8528 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8529 {
8530 if (TARGET_DEBUG_ARG)
8531 {
8532 fprintf (stderr, "va_arg: aggregate type");
8533 debug_tree (type);
8534 }
8535
8536 /* Aggregates are passed by reference. */
8537 indirect_p = 1;
8538 reg = gpr;
8539 n_reg = 1;
8540
8541 /* kernel stack layout on 31 bit: It is assumed here that no padding
8542 will be added by s390_frame_info because for va_args always an even
8543 number of gprs has to be saved r15-r2 = 14 regs. */
8544 sav_ofs = 2 * UNITS_PER_WORD;
8545 sav_scale = UNITS_PER_WORD;
8546 size = UNITS_PER_WORD;
8547 max_reg = GP_ARG_NUM_REG - n_reg;
8548 }
8549 else if (s390_function_arg_float (TYPE_MODE (type), type))
8550 {
8551 if (TARGET_DEBUG_ARG)
8552 {
8553 fprintf (stderr, "va_arg: float type");
8554 debug_tree (type);
8555 }
8556
8557 /* FP args go in FP registers, if present. */
8558 indirect_p = 0;
8559 reg = fpr;
8560 n_reg = 1;
8561 sav_ofs = 16 * UNITS_PER_WORD;
8562 sav_scale = 8;
8563 max_reg = FP_ARG_NUM_REG - n_reg;
8564 }
8565 else
8566 {
8567 if (TARGET_DEBUG_ARG)
8568 {
8569 fprintf (stderr, "va_arg: other type");
8570 debug_tree (type);
8571 }
8572
8573 /* Otherwise into GP registers. */
8574 indirect_p = 0;
8575 reg = gpr;
8576 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8577
8578 /* kernel stack layout on 31 bit: It is assumed here that no padding
8579 will be added by s390_frame_info because for va_args always an even
8580 number of gprs has to be saved r15-r2 = 14 regs. */
8581 sav_ofs = 2 * UNITS_PER_WORD;
8582
8583 if (size < UNITS_PER_WORD)
8584 sav_ofs += UNITS_PER_WORD - size;
8585
8586 sav_scale = UNITS_PER_WORD;
8587 max_reg = GP_ARG_NUM_REG - n_reg;
8588 }
8589
8590 /* Pull the value out of the saved registers ... */
8591
8592 lab_false = create_artificial_label ();
8593 lab_over = create_artificial_label ();
8594 addr = create_tmp_var (ptr_type_node, "addr");
8595 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
8596
8597 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8598 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8599 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8600 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8601 gimplify_and_add (t, pre_p);
8602
8603 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8604 size_int (sav_ofs));
8605 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8606 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8607 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8608
8609 gimplify_assign (addr, t, pre_p);
8610
8611 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8612
8613 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8614
8615
8616 /* ... Otherwise out of the overflow area. */
8617
8618 t = ovf;
8619 if (size < UNITS_PER_WORD)
8620 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8621 size_int (UNITS_PER_WORD - size));
8622
8623 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8624
8625 gimplify_assign (addr, t, pre_p);
8626
8627 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8628 size_int (size));
8629 gimplify_assign (ovf, t, pre_p);
8630
8631 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8632
8633
8634 /* Increment register save count. */
8635
8636 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8637 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8638 gimplify_and_add (u, pre_p);
8639
8640 if (indirect_p)
8641 {
8642 t = build_pointer_type (build_pointer_type (type));
8643 addr = fold_convert (t, addr);
8644 addr = build_va_arg_indirect_ref (addr);
8645 }
8646 else
8647 {
8648 t = build_pointer_type (type);
8649 addr = fold_convert (t, addr);
8650 }
8651
8652 return build_va_arg_indirect_ref (addr);
8653 }
8654
8655
8656 /* Builtins. */
8657
8658 enum s390_builtin
8659 {
8660 S390_BUILTIN_THREAD_POINTER,
8661 S390_BUILTIN_SET_THREAD_POINTER,
8662
8663 S390_BUILTIN_max
8664 };
8665
8666 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8667 CODE_FOR_get_tp_64,
8668 CODE_FOR_set_tp_64
8669 };
8670
8671 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8672 CODE_FOR_get_tp_31,
8673 CODE_FOR_set_tp_31
8674 };
8675
8676 static void
8677 s390_init_builtins (void)
8678 {
8679 tree ftype;
8680
8681 ftype = build_function_type (ptr_type_node, void_list_node);
8682 add_builtin_function ("__builtin_thread_pointer", ftype,
8683 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8684 NULL, NULL_TREE);
8685
8686 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8687 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8688 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8689 NULL, NULL_TREE);
8690 }
8691
8692 /* Expand an expression EXP that calls a built-in function,
8693 with result going to TARGET if that's convenient
8694 (and in mode MODE if that's convenient).
8695 SUBTARGET may be used as the target for computing one of EXP's operands.
8696 IGNORE is nonzero if the value is to be ignored. */
8697
8698 static rtx
8699 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8700 enum machine_mode mode ATTRIBUTE_UNUSED,
8701 int ignore ATTRIBUTE_UNUSED)
8702 {
8703 #define MAX_ARGS 2
8704
8705 unsigned int const *code_for_builtin =
8706 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8707
8708 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8709 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8710 enum insn_code icode;
8711 rtx op[MAX_ARGS], pat;
8712 int arity;
8713 bool nonvoid;
8714 tree arg;
8715 call_expr_arg_iterator iter;
8716
8717 if (fcode >= S390_BUILTIN_max)
8718 internal_error ("bad builtin fcode");
8719 icode = code_for_builtin[fcode];
8720 if (icode == 0)
8721 internal_error ("bad builtin fcode");
8722
8723 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8724
8725 arity = 0;
8726 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8727 {
8728 const struct insn_operand_data *insn_op;
8729
8730 if (arg == error_mark_node)
8731 return NULL_RTX;
8732 if (arity > MAX_ARGS)
8733 return NULL_RTX;
8734
8735 insn_op = &insn_data[icode].operand[arity + nonvoid];
8736
8737 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8738
8739 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8740 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8741 arity++;
8742 }
8743
8744 if (nonvoid)
8745 {
8746 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8747 if (!target
8748 || GET_MODE (target) != tmode
8749 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8750 target = gen_reg_rtx (tmode);
8751 }
8752
8753 switch (arity)
8754 {
8755 case 0:
8756 pat = GEN_FCN (icode) (target);
8757 break;
8758 case 1:
8759 if (nonvoid)
8760 pat = GEN_FCN (icode) (target, op[0]);
8761 else
8762 pat = GEN_FCN (icode) (op[0]);
8763 break;
8764 case 2:
8765 pat = GEN_FCN (icode) (target, op[0], op[1]);
8766 break;
8767 default:
8768 gcc_unreachable ();
8769 }
8770 if (!pat)
8771 return NULL_RTX;
8772 emit_insn (pat);
8773
8774 if (nonvoid)
8775 return target;
8776 else
8777 return const0_rtx;
8778 }
8779
8780
8781 /* Output assembly code for the trampoline template to
8782 stdio stream FILE.
8783
8784 On S/390, we use gpr 1 internally in the trampoline code;
8785 gpr 0 is used to hold the static chain. */
8786
8787 void
8788 s390_trampoline_template (FILE *file)
8789 {
8790 rtx op[2];
8791 op[0] = gen_rtx_REG (Pmode, 0);
8792 op[1] = gen_rtx_REG (Pmode, 1);
8793
8794 if (TARGET_64BIT)
8795 {
8796 output_asm_insn ("basr\t%1,0", op);
8797 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8798 output_asm_insn ("br\t%1", op);
8799 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8800 }
8801 else
8802 {
8803 output_asm_insn ("basr\t%1,0", op);
8804 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8805 output_asm_insn ("br\t%1", op);
8806 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8807 }
8808 }
8809
8810 /* Emit RTL insns to initialize the variable parts of a trampoline.
8811 FNADDR is an RTX for the address of the function's pure code.
8812 CXT is an RTX for the static chain value for the function. */
8813
8814 void
8815 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8816 {
8817 emit_move_insn (gen_rtx_MEM (Pmode,
8818 memory_address (Pmode,
8819 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8820 emit_move_insn (gen_rtx_MEM (Pmode,
8821 memory_address (Pmode,
8822 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8823 }
8824
8825 /* Output assembler code to FILE to increment profiler label # LABELNO
8826 for profiling a function entry. */
8827
8828 void
8829 s390_function_profiler (FILE *file, int labelno)
8830 {
8831 rtx op[7];
8832
8833 char label[128];
8834 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8835
8836 fprintf (file, "# function profiler \n");
8837
8838 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8839 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8840 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8841
8842 op[2] = gen_rtx_REG (Pmode, 1);
8843 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8844 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8845
8846 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8847 if (flag_pic)
8848 {
8849 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8850 op[4] = gen_rtx_CONST (Pmode, op[4]);
8851 }
8852
8853 if (TARGET_64BIT)
8854 {
8855 output_asm_insn ("stg\t%0,%1", op);
8856 output_asm_insn ("larl\t%2,%3", op);
8857 output_asm_insn ("brasl\t%0,%4", op);
8858 output_asm_insn ("lg\t%0,%1", op);
8859 }
8860 else if (!flag_pic)
8861 {
8862 op[6] = gen_label_rtx ();
8863
8864 output_asm_insn ("st\t%0,%1", op);
8865 output_asm_insn ("bras\t%2,%l6", op);
8866 output_asm_insn (".long\t%4", op);
8867 output_asm_insn (".long\t%3", op);
8868 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8869 output_asm_insn ("l\t%0,0(%2)", op);
8870 output_asm_insn ("l\t%2,4(%2)", op);
8871 output_asm_insn ("basr\t%0,%0", op);
8872 output_asm_insn ("l\t%0,%1", op);
8873 }
8874 else
8875 {
8876 op[5] = gen_label_rtx ();
8877 op[6] = gen_label_rtx ();
8878
8879 output_asm_insn ("st\t%0,%1", op);
8880 output_asm_insn ("bras\t%2,%l6", op);
8881 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8882 output_asm_insn (".long\t%4-%l5", op);
8883 output_asm_insn (".long\t%3-%l5", op);
8884 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8885 output_asm_insn ("lr\t%0,%2", op);
8886 output_asm_insn ("a\t%0,0(%2)", op);
8887 output_asm_insn ("a\t%2,4(%2)", op);
8888 output_asm_insn ("basr\t%0,%0", op);
8889 output_asm_insn ("l\t%0,%1", op);
8890 }
8891 }
8892
8893 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8894 into its SYMBOL_REF_FLAGS. */
8895
8896 static void
8897 s390_encode_section_info (tree decl, rtx rtl, int first)
8898 {
8899 default_encode_section_info (decl, rtl, first);
8900
8901 if (TREE_CODE (decl) == VAR_DECL)
8902 {
8903 /* If a variable has a forced alignment to < 2 bytes, mark it
8904 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
8905 operand. */
8906 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8907 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8908 if (!DECL_SIZE (decl)
8909 || !DECL_ALIGN (decl)
8910 || !host_integerp (DECL_SIZE (decl), 0)
8911 || (DECL_ALIGN (decl) <= 64
8912 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
8913 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8914 }
8915
8916 /* Literal pool references don't have a decl so they are handled
8917 differently here. We rely on the information in the MEM_ALIGN
8918 entry to decide upon natural alignment. */
8919 if (MEM_P (rtl)
8920 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
8921 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
8922 && (MEM_ALIGN (rtl) == 0
8923 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
8924 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8925 }
8926
8927 /* Output thunk to FILE that implements a C++ virtual function call (with
8928 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8929 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8930 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8931 relative to the resulting this pointer. */
8932
8933 static void
8934 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8935 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8936 tree function)
8937 {
8938 rtx op[10];
8939 int nonlocal = 0;
8940
8941 /* Operand 0 is the target function. */
8942 op[0] = XEXP (DECL_RTL (function), 0);
8943 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8944 {
8945 nonlocal = 1;
8946 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8947 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8948 op[0] = gen_rtx_CONST (Pmode, op[0]);
8949 }
8950
8951 /* Operand 1 is the 'this' pointer. */
8952 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8953 op[1] = gen_rtx_REG (Pmode, 3);
8954 else
8955 op[1] = gen_rtx_REG (Pmode, 2);
8956
8957 /* Operand 2 is the delta. */
8958 op[2] = GEN_INT (delta);
8959
8960 /* Operand 3 is the vcall_offset. */
8961 op[3] = GEN_INT (vcall_offset);
8962
8963 /* Operand 4 is the temporary register. */
8964 op[4] = gen_rtx_REG (Pmode, 1);
8965
8966 /* Operands 5 to 8 can be used as labels. */
8967 op[5] = NULL_RTX;
8968 op[6] = NULL_RTX;
8969 op[7] = NULL_RTX;
8970 op[8] = NULL_RTX;
8971
8972 /* Operand 9 can be used for temporary register. */
8973 op[9] = NULL_RTX;
8974
8975 /* Generate code. */
8976 if (TARGET_64BIT)
8977 {
8978 /* Setup literal pool pointer if required. */
8979 if ((!DISP_IN_RANGE (delta)
8980 && !CONST_OK_FOR_K (delta)
8981 && !CONST_OK_FOR_Os (delta))
8982 || (!DISP_IN_RANGE (vcall_offset)
8983 && !CONST_OK_FOR_K (vcall_offset)
8984 && !CONST_OK_FOR_Os (vcall_offset)))
8985 {
8986 op[5] = gen_label_rtx ();
8987 output_asm_insn ("larl\t%4,%5", op);
8988 }
8989
8990 /* Add DELTA to this pointer. */
8991 if (delta)
8992 {
8993 if (CONST_OK_FOR_J (delta))
8994 output_asm_insn ("la\t%1,%2(%1)", op);
8995 else if (DISP_IN_RANGE (delta))
8996 output_asm_insn ("lay\t%1,%2(%1)", op);
8997 else if (CONST_OK_FOR_K (delta))
8998 output_asm_insn ("aghi\t%1,%2", op);
8999 else if (CONST_OK_FOR_Os (delta))
9000 output_asm_insn ("agfi\t%1,%2", op);
9001 else
9002 {
9003 op[6] = gen_label_rtx ();
9004 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9005 }
9006 }
9007
9008 /* Perform vcall adjustment. */
9009 if (vcall_offset)
9010 {
9011 if (DISP_IN_RANGE (vcall_offset))
9012 {
9013 output_asm_insn ("lg\t%4,0(%1)", op);
9014 output_asm_insn ("ag\t%1,%3(%4)", op);
9015 }
9016 else if (CONST_OK_FOR_K (vcall_offset))
9017 {
9018 output_asm_insn ("lghi\t%4,%3", op);
9019 output_asm_insn ("ag\t%4,0(%1)", op);
9020 output_asm_insn ("ag\t%1,0(%4)", op);
9021 }
9022 else if (CONST_OK_FOR_Os (vcall_offset))
9023 {
9024 output_asm_insn ("lgfi\t%4,%3", op);
9025 output_asm_insn ("ag\t%4,0(%1)", op);
9026 output_asm_insn ("ag\t%1,0(%4)", op);
9027 }
9028 else
9029 {
9030 op[7] = gen_label_rtx ();
9031 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9032 output_asm_insn ("ag\t%4,0(%1)", op);
9033 output_asm_insn ("ag\t%1,0(%4)", op);
9034 }
9035 }
9036
9037 /* Jump to target. */
9038 output_asm_insn ("jg\t%0", op);
9039
9040 /* Output literal pool if required. */
9041 if (op[5])
9042 {
9043 output_asm_insn (".align\t4", op);
9044 targetm.asm_out.internal_label (file, "L",
9045 CODE_LABEL_NUMBER (op[5]));
9046 }
9047 if (op[6])
9048 {
9049 targetm.asm_out.internal_label (file, "L",
9050 CODE_LABEL_NUMBER (op[6]));
9051 output_asm_insn (".long\t%2", op);
9052 }
9053 if (op[7])
9054 {
9055 targetm.asm_out.internal_label (file, "L",
9056 CODE_LABEL_NUMBER (op[7]));
9057 output_asm_insn (".long\t%3", op);
9058 }
9059 }
9060 else
9061 {
9062 /* Setup base pointer if required. */
9063 if (!vcall_offset
9064 || (!DISP_IN_RANGE (delta)
9065 && !CONST_OK_FOR_K (delta)
9066 && !CONST_OK_FOR_Os (delta))
9067 || (!DISP_IN_RANGE (delta)
9068 && !CONST_OK_FOR_K (vcall_offset)
9069 && !CONST_OK_FOR_Os (vcall_offset)))
9070 {
9071 op[5] = gen_label_rtx ();
9072 output_asm_insn ("basr\t%4,0", op);
9073 targetm.asm_out.internal_label (file, "L",
9074 CODE_LABEL_NUMBER (op[5]));
9075 }
9076
9077 /* Add DELTA to this pointer. */
9078 if (delta)
9079 {
9080 if (CONST_OK_FOR_J (delta))
9081 output_asm_insn ("la\t%1,%2(%1)", op);
9082 else if (DISP_IN_RANGE (delta))
9083 output_asm_insn ("lay\t%1,%2(%1)", op);
9084 else if (CONST_OK_FOR_K (delta))
9085 output_asm_insn ("ahi\t%1,%2", op);
9086 else if (CONST_OK_FOR_Os (delta))
9087 output_asm_insn ("afi\t%1,%2", op);
9088 else
9089 {
9090 op[6] = gen_label_rtx ();
9091 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9092 }
9093 }
9094
9095 /* Perform vcall adjustment. */
9096 if (vcall_offset)
9097 {
9098 if (CONST_OK_FOR_J (vcall_offset))
9099 {
9100 output_asm_insn ("l\t%4,0(%1)", op);
9101 output_asm_insn ("a\t%1,%3(%4)", op);
9102 }
9103 else if (DISP_IN_RANGE (vcall_offset))
9104 {
9105 output_asm_insn ("l\t%4,0(%1)", op);
9106 output_asm_insn ("ay\t%1,%3(%4)", op);
9107 }
9108 else if (CONST_OK_FOR_K (vcall_offset))
9109 {
9110 output_asm_insn ("lhi\t%4,%3", op);
9111 output_asm_insn ("a\t%4,0(%1)", op);
9112 output_asm_insn ("a\t%1,0(%4)", op);
9113 }
9114 else if (CONST_OK_FOR_Os (vcall_offset))
9115 {
9116 output_asm_insn ("iilf\t%4,%3", op);
9117 output_asm_insn ("a\t%4,0(%1)", op);
9118 output_asm_insn ("a\t%1,0(%4)", op);
9119 }
9120 else
9121 {
9122 op[7] = gen_label_rtx ();
9123 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9124 output_asm_insn ("a\t%4,0(%1)", op);
9125 output_asm_insn ("a\t%1,0(%4)", op);
9126 }
9127
9128 /* We had to clobber the base pointer register.
9129 Re-setup the base pointer (with a different base). */
9130 op[5] = gen_label_rtx ();
9131 output_asm_insn ("basr\t%4,0", op);
9132 targetm.asm_out.internal_label (file, "L",
9133 CODE_LABEL_NUMBER (op[5]));
9134 }
9135
9136 /* Jump to target. */
9137 op[8] = gen_label_rtx ();
9138
9139 if (!flag_pic)
9140 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9141 else if (!nonlocal)
9142 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9143 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9144 else if (flag_pic == 1)
9145 {
9146 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9147 output_asm_insn ("l\t%4,%0(%4)", op);
9148 }
9149 else if (flag_pic == 2)
9150 {
9151 op[9] = gen_rtx_REG (Pmode, 0);
9152 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9153 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9154 output_asm_insn ("ar\t%4,%9", op);
9155 output_asm_insn ("l\t%4,0(%4)", op);
9156 }
9157
9158 output_asm_insn ("br\t%4", op);
9159
9160 /* Output literal pool. */
9161 output_asm_insn (".align\t4", op);
9162
9163 if (nonlocal && flag_pic == 2)
9164 output_asm_insn (".long\t%0", op);
9165 if (nonlocal)
9166 {
9167 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9168 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9169 }
9170
9171 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9172 if (!flag_pic)
9173 output_asm_insn (".long\t%0", op);
9174 else
9175 output_asm_insn (".long\t%0-%5", op);
9176
9177 if (op[6])
9178 {
9179 targetm.asm_out.internal_label (file, "L",
9180 CODE_LABEL_NUMBER (op[6]));
9181 output_asm_insn (".long\t%2", op);
9182 }
9183 if (op[7])
9184 {
9185 targetm.asm_out.internal_label (file, "L",
9186 CODE_LABEL_NUMBER (op[7]));
9187 output_asm_insn (".long\t%3", op);
9188 }
9189 }
9190 }
9191
9192 static bool
9193 s390_valid_pointer_mode (enum machine_mode mode)
9194 {
9195 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9196 }
9197
9198 /* Checks whether the given CALL_EXPR would use a caller
9199 saved register. This is used to decide whether sibling call
9200 optimization could be performed on the respective function
9201 call. */
9202
9203 static bool
9204 s390_call_saved_register_used (tree call_expr)
9205 {
9206 CUMULATIVE_ARGS cum;
9207 tree parameter;
9208 enum machine_mode mode;
9209 tree type;
9210 rtx parm_rtx;
9211 int reg, i;
9212
9213 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9214
9215 for (i = 0; i < call_expr_nargs (call_expr); i++)
9216 {
9217 parameter = CALL_EXPR_ARG (call_expr, i);
9218 gcc_assert (parameter);
9219
9220 /* For an undeclared variable passed as parameter we will get
9221 an ERROR_MARK node here. */
9222 if (TREE_CODE (parameter) == ERROR_MARK)
9223 return true;
9224
9225 type = TREE_TYPE (parameter);
9226 gcc_assert (type);
9227
9228 mode = TYPE_MODE (type);
9229 gcc_assert (mode);
9230
9231 if (pass_by_reference (&cum, mode, type, true))
9232 {
9233 mode = Pmode;
9234 type = build_pointer_type (type);
9235 }
9236
9237 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9238
9239 s390_function_arg_advance (&cum, mode, type, 0);
9240
9241 if (parm_rtx && REG_P (parm_rtx))
9242 {
9243 for (reg = 0;
9244 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9245 reg++)
9246 if (! call_used_regs[reg + REGNO (parm_rtx)])
9247 return true;
9248 }
9249 }
9250 return false;
9251 }
9252
9253 /* Return true if the given call expression can be
9254 turned into a sibling call.
9255 DECL holds the declaration of the function to be called whereas
9256 EXP is the call expression itself. */
9257
9258 static bool
9259 s390_function_ok_for_sibcall (tree decl, tree exp)
9260 {
9261 /* The TPF epilogue uses register 1. */
9262 if (TARGET_TPF_PROFILING)
9263 return false;
9264
9265 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9266 which would have to be restored before the sibcall. */
9267 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9268 return false;
9269
9270 /* Register 6 on s390 is available as an argument register but unfortunately
9271 "caller saved". This makes functions needing this register for arguments
9272 not suitable for sibcalls. */
9273 return !s390_call_saved_register_used (exp);
9274 }
9275
9276 /* Return the fixed registers used for condition codes. */
9277
9278 static bool
9279 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9280 {
9281 *p1 = CC_REGNUM;
9282 *p2 = INVALID_REGNUM;
9283
9284 return true;
9285 }
9286
9287 /* This function is used by the call expanders of the machine description.
9288 It emits the call insn itself together with the necessary operations
9289 to adjust the target address and returns the emitted insn.
9290 ADDR_LOCATION is the target address rtx
9291 TLS_CALL the location of the thread-local symbol
9292 RESULT_REG the register where the result of the call should be stored
9293 RETADDR_REG the register where the return address should be stored
9294 If this parameter is NULL_RTX the call is considered
9295 to be a sibling call. */
9296
9297 rtx
9298 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9299 rtx retaddr_reg)
9300 {
9301 bool plt_call = false;
9302 rtx insn;
9303 rtx call;
9304 rtx clobber;
9305 rtvec vec;
9306
9307 /* Direct function calls need special treatment. */
9308 if (GET_CODE (addr_location) == SYMBOL_REF)
9309 {
9310 /* When calling a global routine in PIC mode, we must
9311 replace the symbol itself with the PLT stub. */
9312 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9313 {
9314 addr_location = gen_rtx_UNSPEC (Pmode,
9315 gen_rtvec (1, addr_location),
9316 UNSPEC_PLT);
9317 addr_location = gen_rtx_CONST (Pmode, addr_location);
9318 plt_call = true;
9319 }
9320
9321 /* Unless we can use the bras(l) insn, force the
9322 routine address into a register. */
9323 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9324 {
9325 if (flag_pic)
9326 addr_location = legitimize_pic_address (addr_location, 0);
9327 else
9328 addr_location = force_reg (Pmode, addr_location);
9329 }
9330 }
9331
9332 /* If it is already an indirect call or the code above moved the
9333 SYMBOL_REF to somewhere else make sure the address can be found in
9334 register 1. */
9335 if (retaddr_reg == NULL_RTX
9336 && GET_CODE (addr_location) != SYMBOL_REF
9337 && !plt_call)
9338 {
9339 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9340 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9341 }
9342
9343 addr_location = gen_rtx_MEM (QImode, addr_location);
9344 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9345
9346 if (result_reg != NULL_RTX)
9347 call = gen_rtx_SET (VOIDmode, result_reg, call);
9348
9349 if (retaddr_reg != NULL_RTX)
9350 {
9351 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9352
9353 if (tls_call != NULL_RTX)
9354 vec = gen_rtvec (3, call, clobber,
9355 gen_rtx_USE (VOIDmode, tls_call));
9356 else
9357 vec = gen_rtvec (2, call, clobber);
9358
9359 call = gen_rtx_PARALLEL (VOIDmode, vec);
9360 }
9361
9362 insn = emit_call_insn (call);
9363
9364 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9365 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9366 {
9367 /* s390_function_ok_for_sibcall should
9368 have denied sibcalls in this case. */
9369 gcc_assert (retaddr_reg != NULL_RTX);
9370
9371 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9372 }
9373 return insn;
9374 }
9375
9376 /* Implement CONDITIONAL_REGISTER_USAGE. */
9377
9378 void
9379 s390_conditional_register_usage (void)
9380 {
9381 int i;
9382
9383 if (flag_pic)
9384 {
9385 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9386 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9387 }
9388 if (TARGET_CPU_ZARCH)
9389 {
9390 fixed_regs[BASE_REGNUM] = 0;
9391 call_used_regs[BASE_REGNUM] = 0;
9392 fixed_regs[RETURN_REGNUM] = 0;
9393 call_used_regs[RETURN_REGNUM] = 0;
9394 }
9395 if (TARGET_64BIT)
9396 {
9397 for (i = 24; i < 32; i++)
9398 call_used_regs[i] = call_really_used_regs[i] = 0;
9399 }
9400 else
9401 {
9402 for (i = 18; i < 20; i++)
9403 call_used_regs[i] = call_really_used_regs[i] = 0;
9404 }
9405
9406 if (TARGET_SOFT_FLOAT)
9407 {
9408 for (i = 16; i < 32; i++)
9409 call_used_regs[i] = fixed_regs[i] = 1;
9410 }
9411 }
9412
9413 /* Corresponding function to eh_return expander. */
9414
9415 static GTY(()) rtx s390_tpf_eh_return_symbol;
9416 void
9417 s390_emit_tpf_eh_return (rtx target)
9418 {
9419 rtx insn, reg;
9420
9421 if (!s390_tpf_eh_return_symbol)
9422 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9423
9424 reg = gen_rtx_REG (Pmode, 2);
9425
9426 emit_move_insn (reg, target);
9427 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9428 gen_rtx_REG (Pmode, RETURN_REGNUM));
9429 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9430
9431 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9432 }
9433
9434 /* Rework the prologue/epilogue to avoid saving/restoring
9435 registers unnecessarily. */
9436
9437 static void
9438 s390_optimize_prologue (void)
9439 {
9440 rtx insn, new_insn, next_insn;
9441
9442 /* Do a final recompute of the frame-related data. */
9443
9444 s390_update_frame_layout ();
9445
9446 /* If all special registers are in fact used, there's nothing we
9447 can do, so no point in walking the insn list. */
9448
9449 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9450 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9451 && (TARGET_CPU_ZARCH
9452 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9453 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9454 return;
9455
9456 /* Search for prologue/epilogue insns and replace them. */
9457
9458 for (insn = get_insns (); insn; insn = next_insn)
9459 {
9460 int first, last, off;
9461 rtx set, base, offset;
9462
9463 next_insn = NEXT_INSN (insn);
9464
9465 if (GET_CODE (insn) != INSN)
9466 continue;
9467
9468 if (GET_CODE (PATTERN (insn)) == PARALLEL
9469 && store_multiple_operation (PATTERN (insn), VOIDmode))
9470 {
9471 set = XVECEXP (PATTERN (insn), 0, 0);
9472 first = REGNO (SET_SRC (set));
9473 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9474 offset = const0_rtx;
9475 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9476 off = INTVAL (offset);
9477
9478 if (GET_CODE (base) != REG || off < 0)
9479 continue;
9480 if (cfun_frame_layout.first_save_gpr != -1
9481 && (cfun_frame_layout.first_save_gpr < first
9482 || cfun_frame_layout.last_save_gpr > last))
9483 continue;
9484 if (REGNO (base) != STACK_POINTER_REGNUM
9485 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9486 continue;
9487 if (first > BASE_REGNUM || last < BASE_REGNUM)
9488 continue;
9489
9490 if (cfun_frame_layout.first_save_gpr != -1)
9491 {
9492 new_insn = save_gprs (base,
9493 off + (cfun_frame_layout.first_save_gpr
9494 - first) * UNITS_PER_WORD,
9495 cfun_frame_layout.first_save_gpr,
9496 cfun_frame_layout.last_save_gpr);
9497 new_insn = emit_insn_before (new_insn, insn);
9498 INSN_ADDRESSES_NEW (new_insn, -1);
9499 }
9500
9501 remove_insn (insn);
9502 continue;
9503 }
9504
9505 if (cfun_frame_layout.first_save_gpr == -1
9506 && GET_CODE (PATTERN (insn)) == SET
9507 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9508 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9509 || (!TARGET_CPU_ZARCH
9510 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9511 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9512 {
9513 set = PATTERN (insn);
9514 first = REGNO (SET_SRC (set));
9515 offset = const0_rtx;
9516 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9517 off = INTVAL (offset);
9518
9519 if (GET_CODE (base) != REG || off < 0)
9520 continue;
9521 if (REGNO (base) != STACK_POINTER_REGNUM
9522 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9523 continue;
9524
9525 remove_insn (insn);
9526 continue;
9527 }
9528
9529 if (GET_CODE (PATTERN (insn)) == PARALLEL
9530 && load_multiple_operation (PATTERN (insn), VOIDmode))
9531 {
9532 set = XVECEXP (PATTERN (insn), 0, 0);
9533 first = REGNO (SET_DEST (set));
9534 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9535 offset = const0_rtx;
9536 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9537 off = INTVAL (offset);
9538
9539 if (GET_CODE (base) != REG || off < 0)
9540 continue;
9541 if (cfun_frame_layout.first_restore_gpr != -1
9542 && (cfun_frame_layout.first_restore_gpr < first
9543 || cfun_frame_layout.last_restore_gpr > last))
9544 continue;
9545 if (REGNO (base) != STACK_POINTER_REGNUM
9546 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9547 continue;
9548 if (first > BASE_REGNUM || last < BASE_REGNUM)
9549 continue;
9550
9551 if (cfun_frame_layout.first_restore_gpr != -1)
9552 {
9553 new_insn = restore_gprs (base,
9554 off + (cfun_frame_layout.first_restore_gpr
9555 - first) * UNITS_PER_WORD,
9556 cfun_frame_layout.first_restore_gpr,
9557 cfun_frame_layout.last_restore_gpr);
9558 new_insn = emit_insn_before (new_insn, insn);
9559 INSN_ADDRESSES_NEW (new_insn, -1);
9560 }
9561
9562 remove_insn (insn);
9563 continue;
9564 }
9565
9566 if (cfun_frame_layout.first_restore_gpr == -1
9567 && GET_CODE (PATTERN (insn)) == SET
9568 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9569 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9570 || (!TARGET_CPU_ZARCH
9571 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9572 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9573 {
9574 set = PATTERN (insn);
9575 first = REGNO (SET_DEST (set));
9576 offset = const0_rtx;
9577 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9578 off = INTVAL (offset);
9579
9580 if (GET_CODE (base) != REG || off < 0)
9581 continue;
9582 if (REGNO (base) != STACK_POINTER_REGNUM
9583 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9584 continue;
9585
9586 remove_insn (insn);
9587 continue;
9588 }
9589 }
9590 }
9591
9592
9593 /* Exchange the two operands of COND, and swap its mask so that the
9594 semantics does not change. */
9595 static void
9596 s390_swap_cmp (rtx cond)
9597 {
9598 enum rtx_code code = swap_condition (GET_CODE (cond));
9599 rtx tmp = XEXP (cond, 0);
9600
9601 XEXP (cond, 0) = XEXP (cond, 1);
9602 XEXP (cond, 1) = tmp;
9603 PUT_CODE (cond, code);
9604 }
9605
9606
9607 /* Returns 1 if INSN reads the value of REG for purposes not related
9608 to addressing of memory, and 0 otherwise. */
9609 static int
9610 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9611 {
9612 return reg_referenced_p (reg, PATTERN (insn))
9613 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9614 }
9615
9616
9617 /* On z10, instructions of the compare-and-branch family have the
9618 property to access the register occurring as second operand with
9619 its bits complemented. If such a compare is grouped with a second
9620 instruction that accesses the same register non-complemented, and
9621 if that register's value is delivered via a bypass, then the
9622 pipeline recycles, thereby causing significant performance decline.
9623 This function locates such situations and exchanges the two
9624 operands of the compare. */
9625 static void
9626 s390_z10_optimize_cmp (void)
9627 {
9628 rtx insn, prev_insn, next_insn;
9629 int added_NOPs = 0;
9630
9631 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9632 {
9633 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
9634 continue;
9635
9636 if (get_attr_z10prop (insn) == Z10PROP_Z10_COBRA)
9637 {
9638 rtx op0, op1, pattern, jump_expr, cond;
9639
9640 /* Extract the comparison´s condition and its operands. */
9641 pattern = single_set (insn);
9642 gcc_assert (GET_CODE (pattern) == SET);
9643 jump_expr = XEXP (pattern, 1);
9644 gcc_assert (GET_CODE (jump_expr) == IF_THEN_ELSE);
9645 cond = XEXP (jump_expr, 0);
9646 op0 = XEXP (cond, 0);
9647 op1 = XEXP (cond, 1);
9648
9649 /* Swap the COMPARE´s arguments and its mask if there is a
9650 conflicting access in the previous insn. */
9651 prev_insn = PREV_INSN (insn);
9652 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9653 && reg_referenced_p (op1, PATTERN (prev_insn)))
9654 {
9655 s390_swap_cmp (cond);
9656 op0 = XEXP (cond, 0);
9657 op1 = XEXP (cond, 1);
9658 }
9659
9660 /* Check if there is a conflict with the next insn. If there
9661 was no conflict with the previous insn, then swap the
9662 COMPARE´s arguments and its mask. If we already swapped
9663 the operands, or if swapping them would cause a conflict
9664 with the previous insn, issue a NOP after the COMPARE in
9665 order to separate the two instuctions. */
9666 next_insn = NEXT_INSN (insn);
9667 if (next_insn != NULL_RTX && INSN_P (next_insn)
9668 && s390_non_addr_reg_read_p (op1, next_insn))
9669 {
9670 if (s390_non_addr_reg_read_p (op0, prev_insn))
9671 {
9672 if (REGNO(op1) == 0)
9673 emit_insn_after (gen_nop1 (), insn);
9674 else
9675 emit_insn_after (gen_nop (), insn);
9676 added_NOPs = 1;
9677 }
9678 else
9679 s390_swap_cmp (cond);
9680 }
9681 }
9682 }
9683
9684 /* Adjust branches if we added new instructions. */
9685 if (added_NOPs)
9686 shorten_branches (get_insns ());
9687 }
9688
9689
9690 /* Perform machine-dependent processing. */
9691
9692 static void
9693 s390_reorg (void)
9694 {
9695 bool pool_overflow = false;
9696
9697 /* Make sure all splits have been performed; splits after
9698 machine_dependent_reorg might confuse insn length counts. */
9699 split_all_insns_noflow ();
9700
9701 /* Install the main literal pool and the associated base
9702 register load insns.
9703
9704 In addition, there are two problematic situations we need
9705 to correct:
9706
9707 - the literal pool might be > 4096 bytes in size, so that
9708 some of its elements cannot be directly accessed
9709
9710 - a branch target might be > 64K away from the branch, so that
9711 it is not possible to use a PC-relative instruction.
9712
9713 To fix those, we split the single literal pool into multiple
9714 pool chunks, reloading the pool base register at various
9715 points throughout the function to ensure it always points to
9716 the pool chunk the following code expects, and / or replace
9717 PC-relative branches by absolute branches.
9718
9719 However, the two problems are interdependent: splitting the
9720 literal pool can move a branch further away from its target,
9721 causing the 64K limit to overflow, and on the other hand,
9722 replacing a PC-relative branch by an absolute branch means
9723 we need to put the branch target address into the literal
9724 pool, possibly causing it to overflow.
9725
9726 So, we loop trying to fix up both problems until we manage
9727 to satisfy both conditions at the same time. Note that the
9728 loop is guaranteed to terminate as every pass of the loop
9729 strictly decreases the total number of PC-relative branches
9730 in the function. (This is not completely true as there
9731 might be branch-over-pool insns introduced by chunkify_start.
9732 Those never need to be split however.) */
9733
9734 for (;;)
9735 {
9736 struct constant_pool *pool = NULL;
9737
9738 /* Collect the literal pool. */
9739 if (!pool_overflow)
9740 {
9741 pool = s390_mainpool_start ();
9742 if (!pool)
9743 pool_overflow = true;
9744 }
9745
9746 /* If literal pool overflowed, start to chunkify it. */
9747 if (pool_overflow)
9748 pool = s390_chunkify_start ();
9749
9750 /* Split out-of-range branches. If this has created new
9751 literal pool entries, cancel current chunk list and
9752 recompute it. zSeries machines have large branch
9753 instructions, so we never need to split a branch. */
9754 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9755 {
9756 if (pool_overflow)
9757 s390_chunkify_cancel (pool);
9758 else
9759 s390_mainpool_cancel (pool);
9760
9761 continue;
9762 }
9763
9764 /* If we made it up to here, both conditions are satisfied.
9765 Finish up literal pool related changes. */
9766 if (pool_overflow)
9767 s390_chunkify_finish (pool);
9768 else
9769 s390_mainpool_finish (pool);
9770
9771 /* We're done splitting branches. */
9772 cfun->machine->split_branches_pending_p = false;
9773 break;
9774 }
9775
9776 /* Generate out-of-pool execute target insns. */
9777 if (TARGET_CPU_ZARCH)
9778 {
9779 rtx insn, label, target;
9780
9781 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9782 {
9783 label = s390_execute_label (insn);
9784 if (!label)
9785 continue;
9786
9787 gcc_assert (label != const0_rtx);
9788
9789 target = emit_label (XEXP (label, 0));
9790 INSN_ADDRESSES_NEW (target, -1);
9791
9792 target = emit_insn (s390_execute_target (insn));
9793 INSN_ADDRESSES_NEW (target, -1);
9794 }
9795 }
9796
9797 /* Try to optimize prologue and epilogue further. */
9798 s390_optimize_prologue ();
9799
9800 /* Eliminate z10-specific pipeline recycles related to some compare
9801 instructions. */
9802 if (TARGET_Z10)
9803 s390_z10_optimize_cmp ();
9804 }
9805
9806
9807 /* Initialize GCC target structure. */
9808
9809 #undef TARGET_ASM_ALIGNED_HI_OP
9810 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9811 #undef TARGET_ASM_ALIGNED_DI_OP
9812 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9813 #undef TARGET_ASM_INTEGER
9814 #define TARGET_ASM_INTEGER s390_assemble_integer
9815
9816 #undef TARGET_ASM_OPEN_PAREN
9817 #define TARGET_ASM_OPEN_PAREN ""
9818
9819 #undef TARGET_ASM_CLOSE_PAREN
9820 #define TARGET_ASM_CLOSE_PAREN ""
9821
9822 #undef TARGET_DEFAULT_TARGET_FLAGS
9823 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9824 #undef TARGET_HANDLE_OPTION
9825 #define TARGET_HANDLE_OPTION s390_handle_option
9826
9827 #undef TARGET_ENCODE_SECTION_INFO
9828 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9829
9830 #ifdef HAVE_AS_TLS
9831 #undef TARGET_HAVE_TLS
9832 #define TARGET_HAVE_TLS true
9833 #endif
9834 #undef TARGET_CANNOT_FORCE_CONST_MEM
9835 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9836
9837 #undef TARGET_DELEGITIMIZE_ADDRESS
9838 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9839
9840 #undef TARGET_RETURN_IN_MEMORY
9841 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9842
9843 #undef TARGET_INIT_BUILTINS
9844 #define TARGET_INIT_BUILTINS s390_init_builtins
9845 #undef TARGET_EXPAND_BUILTIN
9846 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9847
9848 #undef TARGET_ASM_OUTPUT_MI_THUNK
9849 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9850 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9851 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
9852
9853 #undef TARGET_SCHED_ADJUST_PRIORITY
9854 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9855 #undef TARGET_SCHED_ISSUE_RATE
9856 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9857 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9858 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9859
9860 #undef TARGET_CANNOT_COPY_INSN_P
9861 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9862 #undef TARGET_RTX_COSTS
9863 #define TARGET_RTX_COSTS s390_rtx_costs
9864 #undef TARGET_ADDRESS_COST
9865 #define TARGET_ADDRESS_COST s390_address_cost
9866
9867 #undef TARGET_MACHINE_DEPENDENT_REORG
9868 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9869
9870 #undef TARGET_VALID_POINTER_MODE
9871 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9872
9873 #undef TARGET_BUILD_BUILTIN_VA_LIST
9874 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9875 #undef TARGET_EXPAND_BUILTIN_VA_START
9876 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
9877 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9878 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9879
9880 #undef TARGET_PROMOTE_FUNCTION_ARGS
9881 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
9882 #undef TARGET_PROMOTE_FUNCTION_RETURN
9883 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
9884 #undef TARGET_PASS_BY_REFERENCE
9885 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9886
9887 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9888 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9889
9890 #undef TARGET_FIXED_CONDITION_CODE_REGS
9891 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9892
9893 #undef TARGET_CC_MODES_COMPATIBLE
9894 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9895
9896 #undef TARGET_INVALID_WITHIN_DOLOOP
9897 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
9898
9899 #ifdef HAVE_AS_TLS
9900 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9901 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9902 #endif
9903
9904 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9905 #undef TARGET_MANGLE_TYPE
9906 #define TARGET_MANGLE_TYPE s390_mangle_type
9907 #endif
9908
9909 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9910 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9911
9912 #undef TARGET_SECONDARY_RELOAD
9913 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
9914
9915 #undef TARGET_LIBGCC_CMP_RETURN_MODE
9916 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
9917
9918 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
9919 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
9920
9921 struct gcc_target targetm = TARGET_INITIALIZER;
9922
9923 #include "gt-s390.h"