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[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55 #include "params.h"
56
57
58 /* Define the specific costs for a given cpu. */
59
60 struct processor_costs
61 {
62 /* multiplication */
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
76 const int mxbr;
77 /* square root */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
84 /* division */
85 const int dxbr;
86 const int ddbr;
87 const int debr;
88 const int dlgr;
89 const int dlr;
90 const int dr;
91 const int dsgfr;
92 const int dsgr;
93 };
94
95 const struct processor_costs *s390_cost;
96
97 static const
98 struct processor_costs z900_cost =
99 {
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
127 };
128
129 static const
130 struct processor_costs z990_cost =
131 {
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
159 };
160
161 static const
162 struct processor_costs z9_109_cost =
163 {
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
191 };
192
193 static const
194 struct processor_costs z10_cost =
195 {
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (10), /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (10), /* MADBR */
214 COSTS_N_INSNS (10), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
223 };
224
225 extern int reload_completed;
226
227 /* Structure used to hold the components of a S/390 memory
228 address. A legitimate address on S/390 is of the general
229 form
230 base + index + displacement
231 where any of the components is optional.
232
233 base and index are registers of the class ADDR_REGS,
234 displacement is an unsigned 12-bit immediate constant. */
235
236 struct s390_address
237 {
238 rtx base;
239 rtx indx;
240 rtx disp;
241 bool pointer;
242 bool literal_pool;
243 };
244
245 /* Which cpu are we tuning for. */
246 enum processor_type s390_tune = PROCESSOR_max;
247 int s390_tune_flags;
248 /* Which instruction set architecture to use. */
249 enum processor_type s390_arch;
250 int s390_arch_flags;
251
252 HOST_WIDE_INT s390_warn_framesize = 0;
253 HOST_WIDE_INT s390_stack_size = 0;
254 HOST_WIDE_INT s390_stack_guard = 0;
255
256 /* The following structure is embedded in the machine
257 specific part of struct function. */
258
259 struct GTY (()) s390_frame_layout
260 {
261 /* Offset within stack frame. */
262 HOST_WIDE_INT gprs_offset;
263 HOST_WIDE_INT f0_offset;
264 HOST_WIDE_INT f4_offset;
265 HOST_WIDE_INT f8_offset;
266 HOST_WIDE_INT backchain_offset;
267
268 /* Number of first and last gpr where slots in the register
269 save area are reserved for. */
270 int first_save_gpr_slot;
271 int last_save_gpr_slot;
272
273 /* Number of first and last gpr to be saved, restored. */
274 int first_save_gpr;
275 int first_restore_gpr;
276 int last_save_gpr;
277 int last_restore_gpr;
278
279 /* Bits standing for floating point registers. Set, if the
280 respective register has to be saved. Starting with reg 16 (f0)
281 at the rightmost bit.
282 Bit 15 - 8 7 6 5 4 3 2 1 0
283 fpr 15 - 8 7 5 3 1 6 4 2 0
284 reg 31 - 24 23 22 21 20 19 18 17 16 */
285 unsigned int fpr_bitmap;
286
287 /* Number of floating point registers f8-f15 which must be saved. */
288 int high_fprs;
289
290 /* Set if return address needs to be saved.
291 This flag is set by s390_return_addr_rtx if it could not use
292 the initial value of r14 and therefore depends on r14 saved
293 to the stack. */
294 bool save_return_addr_p;
295
296 /* Size of stack frame. */
297 HOST_WIDE_INT frame_size;
298 };
299
300 /* Define the structure for the machine field in struct function. */
301
302 struct GTY(()) machine_function
303 {
304 struct s390_frame_layout frame_layout;
305
306 /* Literal pool base register. */
307 rtx base_reg;
308
309 /* True if we may need to perform branch splitting. */
310 bool split_branches_pending_p;
311
312 /* Some local-dynamic TLS symbol name. */
313 const char *some_ld_name;
314
315 bool has_landing_pad_p;
316 };
317
318 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
319
320 #define cfun_frame_layout (cfun->machine->frame_layout)
321 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
322 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
323 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
324 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
325 (1 << (BITNUM)))
326 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
327 (1 << (BITNUM))))
328
329 /* Number of GPRs and FPRs used for argument passing. */
330 #define GP_ARG_NUM_REG 5
331 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
332
333 /* A couple of shortcuts. */
334 #define CONST_OK_FOR_J(x) \
335 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
336 #define CONST_OK_FOR_K(x) \
337 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
338 #define CONST_OK_FOR_Os(x) \
339 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
340 #define CONST_OK_FOR_Op(x) \
341 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
342 #define CONST_OK_FOR_On(x) \
343 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
344
345 #define REGNO_PAIR_OK(REGNO, MODE) \
346 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
347
348 static enum machine_mode
349 s390_libgcc_cmp_return_mode (void)
350 {
351 return TARGET_64BIT ? DImode : SImode;
352 }
353
354 static enum machine_mode
355 s390_libgcc_shift_count_mode (void)
356 {
357 return TARGET_64BIT ? DImode : SImode;
358 }
359
360 /* Return true if the back end supports mode MODE. */
361 static bool
362 s390_scalar_mode_supported_p (enum machine_mode mode)
363 {
364 if (DECIMAL_FLOAT_MODE_P (mode))
365 return true;
366 else
367 return default_scalar_mode_supported_p (mode);
368 }
369
370 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
371
372 void
373 s390_set_has_landing_pad_p (bool value)
374 {
375 cfun->machine->has_landing_pad_p = value;
376 }
377
378 /* If two condition code modes are compatible, return a condition code
379 mode which is compatible with both. Otherwise, return
380 VOIDmode. */
381
382 static enum machine_mode
383 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
384 {
385 if (m1 == m2)
386 return m1;
387
388 switch (m1)
389 {
390 case CCZmode:
391 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
392 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
393 return m2;
394 return VOIDmode;
395
396 case CCSmode:
397 case CCUmode:
398 case CCTmode:
399 case CCSRmode:
400 case CCURmode:
401 case CCZ1mode:
402 if (m2 == CCZmode)
403 return m1;
404
405 return VOIDmode;
406
407 default:
408 return VOIDmode;
409 }
410 return VOIDmode;
411 }
412
413 /* Return true if SET either doesn't set the CC register, or else
414 the source and destination have matching CC modes and that
415 CC mode is at least as constrained as REQ_MODE. */
416
417 static bool
418 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
419 {
420 enum machine_mode set_mode;
421
422 gcc_assert (GET_CODE (set) == SET);
423
424 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
425 return 1;
426
427 set_mode = GET_MODE (SET_DEST (set));
428 switch (set_mode)
429 {
430 case CCSmode:
431 case CCSRmode:
432 case CCUmode:
433 case CCURmode:
434 case CCLmode:
435 case CCL1mode:
436 case CCL2mode:
437 case CCL3mode:
438 case CCT1mode:
439 case CCT2mode:
440 case CCT3mode:
441 if (req_mode != set_mode)
442 return 0;
443 break;
444
445 case CCZmode:
446 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
447 && req_mode != CCSRmode && req_mode != CCURmode)
448 return 0;
449 break;
450
451 case CCAPmode:
452 case CCANmode:
453 if (req_mode != CCAmode)
454 return 0;
455 break;
456
457 default:
458 gcc_unreachable ();
459 }
460
461 return (GET_MODE (SET_SRC (set)) == set_mode);
462 }
463
464 /* Return true if every SET in INSN that sets the CC register
465 has source and destination with matching CC modes and that
466 CC mode is at least as constrained as REQ_MODE.
467 If REQ_MODE is VOIDmode, always return false. */
468
469 bool
470 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
471 {
472 int i;
473
474 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
475 if (req_mode == VOIDmode)
476 return false;
477
478 if (GET_CODE (PATTERN (insn)) == SET)
479 return s390_match_ccmode_set (PATTERN (insn), req_mode);
480
481 if (GET_CODE (PATTERN (insn)) == PARALLEL)
482 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
483 {
484 rtx set = XVECEXP (PATTERN (insn), 0, i);
485 if (GET_CODE (set) == SET)
486 if (!s390_match_ccmode_set (set, req_mode))
487 return false;
488 }
489
490 return true;
491 }
492
493 /* If a test-under-mask instruction can be used to implement
494 (compare (and ... OP1) OP2), return the CC mode required
495 to do that. Otherwise, return VOIDmode.
496 MIXED is true if the instruction can distinguish between
497 CC1 and CC2 for mixed selected bits (TMxx), it is false
498 if the instruction cannot (TM). */
499
500 enum machine_mode
501 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
502 {
503 int bit0, bit1;
504
505 /* ??? Fixme: should work on CONST_DOUBLE as well. */
506 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
507 return VOIDmode;
508
509 /* Selected bits all zero: CC0.
510 e.g.: int a; if ((a & (16 + 128)) == 0) */
511 if (INTVAL (op2) == 0)
512 return CCTmode;
513
514 /* Selected bits all one: CC3.
515 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
516 if (INTVAL (op2) == INTVAL (op1))
517 return CCT3mode;
518
519 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
520 int a;
521 if ((a & (16 + 128)) == 16) -> CCT1
522 if ((a & (16 + 128)) == 128) -> CCT2 */
523 if (mixed)
524 {
525 bit1 = exact_log2 (INTVAL (op2));
526 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
527 if (bit0 != -1 && bit1 != -1)
528 return bit0 > bit1 ? CCT1mode : CCT2mode;
529 }
530
531 return VOIDmode;
532 }
533
534 /* Given a comparison code OP (EQ, NE, etc.) and the operands
535 OP0 and OP1 of a COMPARE, return the mode to be used for the
536 comparison. */
537
538 enum machine_mode
539 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
540 {
541 switch (code)
542 {
543 case EQ:
544 case NE:
545 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
546 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
547 return CCAPmode;
548 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
549 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
550 return CCAPmode;
551 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
552 || GET_CODE (op1) == NEG)
553 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
554 return CCLmode;
555
556 if (GET_CODE (op0) == AND)
557 {
558 /* Check whether we can potentially do it via TM. */
559 enum machine_mode ccmode;
560 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
561 if (ccmode != VOIDmode)
562 {
563 /* Relax CCTmode to CCZmode to allow fall-back to AND
564 if that turns out to be beneficial. */
565 return ccmode == CCTmode ? CCZmode : ccmode;
566 }
567 }
568
569 if (register_operand (op0, HImode)
570 && GET_CODE (op1) == CONST_INT
571 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
572 return CCT3mode;
573 if (register_operand (op0, QImode)
574 && GET_CODE (op1) == CONST_INT
575 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
576 return CCT3mode;
577
578 return CCZmode;
579
580 case LE:
581 case LT:
582 case GE:
583 case GT:
584 /* The only overflow condition of NEG and ABS happens when
585 -INT_MAX is used as parameter, which stays negative. So
586 we have an overflow from a positive value to a negative.
587 Using CCAP mode the resulting cc can be used for comparisons. */
588 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
589 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
590 return CCAPmode;
591
592 /* If constants are involved in an add instruction it is possible to use
593 the resulting cc for comparisons with zero. Knowing the sign of the
594 constant the overflow behavior gets predictable. e.g.:
595 int a, b; if ((b = a + c) > 0)
596 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
597 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
598 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
599 {
600 if (INTVAL (XEXP((op0), 1)) < 0)
601 return CCANmode;
602 else
603 return CCAPmode;
604 }
605 /* Fall through. */
606 case UNORDERED:
607 case ORDERED:
608 case UNEQ:
609 case UNLE:
610 case UNLT:
611 case UNGE:
612 case UNGT:
613 case LTGT:
614 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
615 && GET_CODE (op1) != CONST_INT)
616 return CCSRmode;
617 return CCSmode;
618
619 case LTU:
620 case GEU:
621 if (GET_CODE (op0) == PLUS
622 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
623 return CCL1mode;
624
625 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
626 && GET_CODE (op1) != CONST_INT)
627 return CCURmode;
628 return CCUmode;
629
630 case LEU:
631 case GTU:
632 if (GET_CODE (op0) == MINUS
633 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
634 return CCL2mode;
635
636 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
637 && GET_CODE (op1) != CONST_INT)
638 return CCURmode;
639 return CCUmode;
640
641 default:
642 gcc_unreachable ();
643 }
644 }
645
646 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
647 that we can implement more efficiently. */
648
649 void
650 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
651 {
652 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
653 if ((*code == EQ || *code == NE)
654 && *op1 == const0_rtx
655 && GET_CODE (*op0) == ZERO_EXTRACT
656 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
657 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
658 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
659 {
660 rtx inner = XEXP (*op0, 0);
661 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
662 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
663 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
664
665 if (len > 0 && len < modesize
666 && pos >= 0 && pos + len <= modesize
667 && modesize <= HOST_BITS_PER_WIDE_INT)
668 {
669 unsigned HOST_WIDE_INT block;
670 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
671 block <<= modesize - pos - len;
672
673 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
674 gen_int_mode (block, GET_MODE (inner)));
675 }
676 }
677
678 /* Narrow AND of memory against immediate to enable TM. */
679 if ((*code == EQ || *code == NE)
680 && *op1 == const0_rtx
681 && GET_CODE (*op0) == AND
682 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
683 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
684 {
685 rtx inner = XEXP (*op0, 0);
686 rtx mask = XEXP (*op0, 1);
687
688 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
689 if (GET_CODE (inner) == SUBREG
690 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
691 && (GET_MODE_SIZE (GET_MODE (inner))
692 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
693 && ((INTVAL (mask)
694 & GET_MODE_MASK (GET_MODE (inner))
695 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
696 == 0))
697 inner = SUBREG_REG (inner);
698
699 /* Do not change volatile MEMs. */
700 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
701 {
702 int part = s390_single_part (XEXP (*op0, 1),
703 GET_MODE (inner), QImode, 0);
704 if (part >= 0)
705 {
706 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
707 inner = adjust_address_nv (inner, QImode, part);
708 *op0 = gen_rtx_AND (QImode, inner, mask);
709 }
710 }
711 }
712
713 /* Narrow comparisons against 0xffff to HImode if possible. */
714 if ((*code == EQ || *code == NE)
715 && GET_CODE (*op1) == CONST_INT
716 && INTVAL (*op1) == 0xffff
717 && SCALAR_INT_MODE_P (GET_MODE (*op0))
718 && (nonzero_bits (*op0, GET_MODE (*op0))
719 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
720 {
721 *op0 = gen_lowpart (HImode, *op0);
722 *op1 = constm1_rtx;
723 }
724
725 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
726 if (GET_CODE (*op0) == UNSPEC
727 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
728 && XVECLEN (*op0, 0) == 1
729 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
730 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
731 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
732 && *op1 == const0_rtx)
733 {
734 enum rtx_code new_code = UNKNOWN;
735 switch (*code)
736 {
737 case EQ: new_code = EQ; break;
738 case NE: new_code = NE; break;
739 case LT: new_code = GTU; break;
740 case GT: new_code = LTU; break;
741 case LE: new_code = GEU; break;
742 case GE: new_code = LEU; break;
743 default: break;
744 }
745
746 if (new_code != UNKNOWN)
747 {
748 *op0 = XVECEXP (*op0, 0, 0);
749 *code = new_code;
750 }
751 }
752
753 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
754 if (GET_CODE (*op0) == UNSPEC
755 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
756 && XVECLEN (*op0, 0) == 1
757 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
758 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
759 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
760 && *op1 == const0_rtx)
761 {
762 enum rtx_code new_code = UNKNOWN;
763 switch (*code)
764 {
765 case EQ: new_code = EQ; break;
766 case NE: new_code = NE; break;
767 default: break;
768 }
769
770 if (new_code != UNKNOWN)
771 {
772 *op0 = XVECEXP (*op0, 0, 0);
773 *code = new_code;
774 }
775 }
776
777 /* Simplify cascaded EQ, NE with const0_rtx. */
778 if ((*code == NE || *code == EQ)
779 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
780 && GET_MODE (*op0) == SImode
781 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
782 && REG_P (XEXP (*op0, 0))
783 && XEXP (*op0, 1) == const0_rtx
784 && *op1 == const0_rtx)
785 {
786 if ((*code == EQ && GET_CODE (*op0) == NE)
787 || (*code == NE && GET_CODE (*op0) == EQ))
788 *code = EQ;
789 else
790 *code = NE;
791 *op0 = XEXP (*op0, 0);
792 }
793
794 /* Prefer register over memory as first operand. */
795 if (MEM_P (*op0) && REG_P (*op1))
796 {
797 rtx tem = *op0; *op0 = *op1; *op1 = tem;
798 *code = swap_condition (*code);
799 }
800 }
801
802 /* Emit a compare instruction suitable to implement the comparison
803 OP0 CODE OP1. Return the correct condition RTL to be placed in
804 the IF_THEN_ELSE of the conditional branch testing the result. */
805
806 rtx
807 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
808 {
809 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
810 rtx cc;
811
812 /* Do not output a redundant compare instruction if a compare_and_swap
813 pattern already computed the result and the machine modes are compatible. */
814 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
815 {
816 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
817 == GET_MODE (op0));
818 cc = op0;
819 }
820 else
821 {
822 cc = gen_rtx_REG (mode, CC_REGNUM);
823 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
824 }
825
826 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
827 }
828
829 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
830 matches CMP.
831 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
832 conditional branch testing the result. */
833
834 static rtx
835 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
836 {
837 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
838 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
839 }
840
841 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
842 unconditional jump, else a conditional jump under condition COND. */
843
844 void
845 s390_emit_jump (rtx target, rtx cond)
846 {
847 rtx insn;
848
849 target = gen_rtx_LABEL_REF (VOIDmode, target);
850 if (cond)
851 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
852
853 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
854 emit_jump_insn (insn);
855 }
856
857 /* Return branch condition mask to implement a branch
858 specified by CODE. Return -1 for invalid comparisons. */
859
860 int
861 s390_branch_condition_mask (rtx code)
862 {
863 const int CC0 = 1 << 3;
864 const int CC1 = 1 << 2;
865 const int CC2 = 1 << 1;
866 const int CC3 = 1 << 0;
867
868 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
869 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
870 gcc_assert (XEXP (code, 1) == const0_rtx);
871
872 switch (GET_MODE (XEXP (code, 0)))
873 {
874 case CCZmode:
875 case CCZ1mode:
876 switch (GET_CODE (code))
877 {
878 case EQ: return CC0;
879 case NE: return CC1 | CC2 | CC3;
880 default: return -1;
881 }
882 break;
883
884 case CCT1mode:
885 switch (GET_CODE (code))
886 {
887 case EQ: return CC1;
888 case NE: return CC0 | CC2 | CC3;
889 default: return -1;
890 }
891 break;
892
893 case CCT2mode:
894 switch (GET_CODE (code))
895 {
896 case EQ: return CC2;
897 case NE: return CC0 | CC1 | CC3;
898 default: return -1;
899 }
900 break;
901
902 case CCT3mode:
903 switch (GET_CODE (code))
904 {
905 case EQ: return CC3;
906 case NE: return CC0 | CC1 | CC2;
907 default: return -1;
908 }
909 break;
910
911 case CCLmode:
912 switch (GET_CODE (code))
913 {
914 case EQ: return CC0 | CC2;
915 case NE: return CC1 | CC3;
916 default: return -1;
917 }
918 break;
919
920 case CCL1mode:
921 switch (GET_CODE (code))
922 {
923 case LTU: return CC2 | CC3; /* carry */
924 case GEU: return CC0 | CC1; /* no carry */
925 default: return -1;
926 }
927 break;
928
929 case CCL2mode:
930 switch (GET_CODE (code))
931 {
932 case GTU: return CC0 | CC1; /* borrow */
933 case LEU: return CC2 | CC3; /* no borrow */
934 default: return -1;
935 }
936 break;
937
938 case CCL3mode:
939 switch (GET_CODE (code))
940 {
941 case EQ: return CC0 | CC2;
942 case NE: return CC1 | CC3;
943 case LTU: return CC1;
944 case GTU: return CC3;
945 case LEU: return CC1 | CC2;
946 case GEU: return CC2 | CC3;
947 default: return -1;
948 }
949
950 case CCUmode:
951 switch (GET_CODE (code))
952 {
953 case EQ: return CC0;
954 case NE: return CC1 | CC2 | CC3;
955 case LTU: return CC1;
956 case GTU: return CC2;
957 case LEU: return CC0 | CC1;
958 case GEU: return CC0 | CC2;
959 default: return -1;
960 }
961 break;
962
963 case CCURmode:
964 switch (GET_CODE (code))
965 {
966 case EQ: return CC0;
967 case NE: return CC2 | CC1 | CC3;
968 case LTU: return CC2;
969 case GTU: return CC1;
970 case LEU: return CC0 | CC2;
971 case GEU: return CC0 | CC1;
972 default: return -1;
973 }
974 break;
975
976 case CCAPmode:
977 switch (GET_CODE (code))
978 {
979 case EQ: return CC0;
980 case NE: return CC1 | CC2 | CC3;
981 case LT: return CC1 | CC3;
982 case GT: return CC2;
983 case LE: return CC0 | CC1 | CC3;
984 case GE: return CC0 | CC2;
985 default: return -1;
986 }
987 break;
988
989 case CCANmode:
990 switch (GET_CODE (code))
991 {
992 case EQ: return CC0;
993 case NE: return CC1 | CC2 | CC3;
994 case LT: return CC1;
995 case GT: return CC2 | CC3;
996 case LE: return CC0 | CC1;
997 case GE: return CC0 | CC2 | CC3;
998 default: return -1;
999 }
1000 break;
1001
1002 case CCSmode:
1003 switch (GET_CODE (code))
1004 {
1005 case EQ: return CC0;
1006 case NE: return CC1 | CC2 | CC3;
1007 case LT: return CC1;
1008 case GT: return CC2;
1009 case LE: return CC0 | CC1;
1010 case GE: return CC0 | CC2;
1011 case UNORDERED: return CC3;
1012 case ORDERED: return CC0 | CC1 | CC2;
1013 case UNEQ: return CC0 | CC3;
1014 case UNLT: return CC1 | CC3;
1015 case UNGT: return CC2 | CC3;
1016 case UNLE: return CC0 | CC1 | CC3;
1017 case UNGE: return CC0 | CC2 | CC3;
1018 case LTGT: return CC1 | CC2;
1019 default: return -1;
1020 }
1021 break;
1022
1023 case CCSRmode:
1024 switch (GET_CODE (code))
1025 {
1026 case EQ: return CC0;
1027 case NE: return CC2 | CC1 | CC3;
1028 case LT: return CC2;
1029 case GT: return CC1;
1030 case LE: return CC0 | CC2;
1031 case GE: return CC0 | CC1;
1032 case UNORDERED: return CC3;
1033 case ORDERED: return CC0 | CC2 | CC1;
1034 case UNEQ: return CC0 | CC3;
1035 case UNLT: return CC2 | CC3;
1036 case UNGT: return CC1 | CC3;
1037 case UNLE: return CC0 | CC2 | CC3;
1038 case UNGE: return CC0 | CC1 | CC3;
1039 case LTGT: return CC2 | CC1;
1040 default: return -1;
1041 }
1042 break;
1043
1044 default:
1045 return -1;
1046 }
1047 }
1048
1049
1050 /* Return branch condition mask to implement a compare and branch
1051 specified by CODE. Return -1 for invalid comparisons. */
1052
1053 int
1054 s390_compare_and_branch_condition_mask (rtx code)
1055 {
1056 const int CC0 = 1 << 3;
1057 const int CC1 = 1 << 2;
1058 const int CC2 = 1 << 1;
1059
1060 switch (GET_CODE (code))
1061 {
1062 case EQ:
1063 return CC0;
1064 case NE:
1065 return CC1 | CC2;
1066 case LT:
1067 case LTU:
1068 return CC1;
1069 case GT:
1070 case GTU:
1071 return CC2;
1072 case LE:
1073 case LEU:
1074 return CC0 | CC1;
1075 case GE:
1076 case GEU:
1077 return CC0 | CC2;
1078 default:
1079 gcc_unreachable ();
1080 }
1081 return -1;
1082 }
1083
1084 /* If INV is false, return assembler mnemonic string to implement
1085 a branch specified by CODE. If INV is true, return mnemonic
1086 for the corresponding inverted branch. */
1087
1088 static const char *
1089 s390_branch_condition_mnemonic (rtx code, int inv)
1090 {
1091 int mask;
1092
1093 static const char *const mnemonic[16] =
1094 {
1095 NULL, "o", "h", "nle",
1096 "l", "nhe", "lh", "ne",
1097 "e", "nlh", "he", "nl",
1098 "le", "nh", "no", NULL
1099 };
1100
1101 if (GET_CODE (XEXP (code, 0)) == REG
1102 && REGNO (XEXP (code, 0)) == CC_REGNUM
1103 && XEXP (code, 1) == const0_rtx)
1104 mask = s390_branch_condition_mask (code);
1105 else
1106 mask = s390_compare_and_branch_condition_mask (code);
1107
1108 gcc_assert (mask >= 0);
1109
1110 if (inv)
1111 mask ^= 15;
1112
1113 gcc_assert (mask >= 1 && mask <= 14);
1114
1115 return mnemonic[mask];
1116 }
1117
1118 /* Return the part of op which has a value different from def.
1119 The size of the part is determined by mode.
1120 Use this function only if you already know that op really
1121 contains such a part. */
1122
1123 unsigned HOST_WIDE_INT
1124 s390_extract_part (rtx op, enum machine_mode mode, int def)
1125 {
1126 unsigned HOST_WIDE_INT value = 0;
1127 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1128 int part_bits = GET_MODE_BITSIZE (mode);
1129 unsigned HOST_WIDE_INT part_mask
1130 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1131 int i;
1132
1133 for (i = 0; i < max_parts; i++)
1134 {
1135 if (i == 0)
1136 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1137 else
1138 value >>= part_bits;
1139
1140 if ((value & part_mask) != (def & part_mask))
1141 return value & part_mask;
1142 }
1143
1144 gcc_unreachable ();
1145 }
1146
1147 /* If OP is an integer constant of mode MODE with exactly one
1148 part of mode PART_MODE unequal to DEF, return the number of that
1149 part. Otherwise, return -1. */
1150
1151 int
1152 s390_single_part (rtx op,
1153 enum machine_mode mode,
1154 enum machine_mode part_mode,
1155 int def)
1156 {
1157 unsigned HOST_WIDE_INT value = 0;
1158 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1159 unsigned HOST_WIDE_INT part_mask
1160 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1161 int i, part = -1;
1162
1163 if (GET_CODE (op) != CONST_INT)
1164 return -1;
1165
1166 for (i = 0; i < n_parts; i++)
1167 {
1168 if (i == 0)
1169 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1170 else
1171 value >>= GET_MODE_BITSIZE (part_mode);
1172
1173 if ((value & part_mask) != (def & part_mask))
1174 {
1175 if (part != -1)
1176 return -1;
1177 else
1178 part = i;
1179 }
1180 }
1181 return part == -1 ? -1 : n_parts - 1 - part;
1182 }
1183
1184 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1185 bits and no other bits are set in IN. POS and LENGTH can be used
1186 to obtain the start position and the length of the bitfield.
1187
1188 POS gives the position of the first bit of the bitfield counting
1189 from the lowest order bit starting with zero. In order to use this
1190 value for S/390 instructions this has to be converted to "bits big
1191 endian" style. */
1192
1193 bool
1194 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1195 int *pos, int *length)
1196 {
1197 int tmp_pos = 0;
1198 int tmp_length = 0;
1199 int i;
1200 unsigned HOST_WIDE_INT mask = 1ULL;
1201 bool contiguous = false;
1202
1203 for (i = 0; i < size; mask <<= 1, i++)
1204 {
1205 if (contiguous)
1206 {
1207 if (mask & in)
1208 tmp_length++;
1209 else
1210 break;
1211 }
1212 else
1213 {
1214 if (mask & in)
1215 {
1216 contiguous = true;
1217 tmp_length++;
1218 }
1219 else
1220 tmp_pos++;
1221 }
1222 }
1223
1224 if (!tmp_length)
1225 return false;
1226
1227 /* Calculate a mask for all bits beyond the contiguous bits. */
1228 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1229
1230 if (mask & in)
1231 return false;
1232
1233 if (tmp_length + tmp_pos - 1 > size)
1234 return false;
1235
1236 if (length)
1237 *length = tmp_length;
1238
1239 if (pos)
1240 *pos = tmp_pos;
1241
1242 return true;
1243 }
1244
1245 /* Check whether we can (and want to) split a double-word
1246 move in mode MODE from SRC to DST into two single-word
1247 moves, moving the subword FIRST_SUBWORD first. */
1248
1249 bool
1250 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1251 {
1252 /* Floating point registers cannot be split. */
1253 if (FP_REG_P (src) || FP_REG_P (dst))
1254 return false;
1255
1256 /* We don't need to split if operands are directly accessible. */
1257 if (s_operand (src, mode) || s_operand (dst, mode))
1258 return false;
1259
1260 /* Non-offsettable memory references cannot be split. */
1261 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1262 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1263 return false;
1264
1265 /* Moving the first subword must not clobber a register
1266 needed to move the second subword. */
1267 if (register_operand (dst, mode))
1268 {
1269 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1270 if (reg_overlap_mentioned_p (subreg, src))
1271 return false;
1272 }
1273
1274 return true;
1275 }
1276
1277 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1278 and [MEM2, MEM2 + SIZE] do overlap and false
1279 otherwise. */
1280
1281 bool
1282 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1283 {
1284 rtx addr1, addr2, addr_delta;
1285 HOST_WIDE_INT delta;
1286
1287 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1288 return true;
1289
1290 if (size == 0)
1291 return false;
1292
1293 addr1 = XEXP (mem1, 0);
1294 addr2 = XEXP (mem2, 0);
1295
1296 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1297
1298 /* This overlapping check is used by peepholes merging memory block operations.
1299 Overlapping operations would otherwise be recognized by the S/390 hardware
1300 and would fall back to a slower implementation. Allowing overlapping
1301 operations would lead to slow code but not to wrong code. Therefore we are
1302 somewhat optimistic if we cannot prove that the memory blocks are
1303 overlapping.
1304 That's why we return false here although this may accept operations on
1305 overlapping memory areas. */
1306 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1307 return false;
1308
1309 delta = INTVAL (addr_delta);
1310
1311 if (delta == 0
1312 || (delta > 0 && delta < size)
1313 || (delta < 0 && -delta < size))
1314 return true;
1315
1316 return false;
1317 }
1318
1319 /* Check whether the address of memory reference MEM2 equals exactly
1320 the address of memory reference MEM1 plus DELTA. Return true if
1321 we can prove this to be the case, false otherwise. */
1322
1323 bool
1324 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1325 {
1326 rtx addr1, addr2, addr_delta;
1327
1328 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1329 return false;
1330
1331 addr1 = XEXP (mem1, 0);
1332 addr2 = XEXP (mem2, 0);
1333
1334 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1335 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1336 return false;
1337
1338 return true;
1339 }
1340
1341 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1342
1343 void
1344 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1345 rtx *operands)
1346 {
1347 enum machine_mode wmode = mode;
1348 rtx dst = operands[0];
1349 rtx src1 = operands[1];
1350 rtx src2 = operands[2];
1351 rtx op, clob, tem;
1352
1353 /* If we cannot handle the operation directly, use a temp register. */
1354 if (!s390_logical_operator_ok_p (operands))
1355 dst = gen_reg_rtx (mode);
1356
1357 /* QImode and HImode patterns make sense only if we have a destination
1358 in memory. Otherwise perform the operation in SImode. */
1359 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1360 wmode = SImode;
1361
1362 /* Widen operands if required. */
1363 if (mode != wmode)
1364 {
1365 if (GET_CODE (dst) == SUBREG
1366 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1367 dst = tem;
1368 else if (REG_P (dst))
1369 dst = gen_rtx_SUBREG (wmode, dst, 0);
1370 else
1371 dst = gen_reg_rtx (wmode);
1372
1373 if (GET_CODE (src1) == SUBREG
1374 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1375 src1 = tem;
1376 else if (GET_MODE (src1) != VOIDmode)
1377 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1378
1379 if (GET_CODE (src2) == SUBREG
1380 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1381 src2 = tem;
1382 else if (GET_MODE (src2) != VOIDmode)
1383 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1384 }
1385
1386 /* Emit the instruction. */
1387 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1388 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1389 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1390
1391 /* Fix up the destination if needed. */
1392 if (dst != operands[0])
1393 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1394 }
1395
1396 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1397
1398 bool
1399 s390_logical_operator_ok_p (rtx *operands)
1400 {
1401 /* If the destination operand is in memory, it needs to coincide
1402 with one of the source operands. After reload, it has to be
1403 the first source operand. */
1404 if (GET_CODE (operands[0]) == MEM)
1405 return rtx_equal_p (operands[0], operands[1])
1406 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1407
1408 return true;
1409 }
1410
1411 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1412 operand IMMOP to switch from SS to SI type instructions. */
1413
1414 void
1415 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1416 {
1417 int def = code == AND ? -1 : 0;
1418 HOST_WIDE_INT mask;
1419 int part;
1420
1421 gcc_assert (GET_CODE (*memop) == MEM);
1422 gcc_assert (!MEM_VOLATILE_P (*memop));
1423
1424 mask = s390_extract_part (*immop, QImode, def);
1425 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1426 gcc_assert (part >= 0);
1427
1428 *memop = adjust_address (*memop, QImode, part);
1429 *immop = gen_int_mode (mask, QImode);
1430 }
1431
1432
1433 /* How to allocate a 'struct machine_function'. */
1434
1435 static struct machine_function *
1436 s390_init_machine_status (void)
1437 {
1438 return GGC_CNEW (struct machine_function);
1439 }
1440
1441 /* Change optimizations to be performed, depending on the
1442 optimization level.
1443
1444 LEVEL is the optimization level specified; 2 if `-O2' is
1445 specified, 1 if `-O' is specified, and 0 if neither is specified.
1446
1447 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1448
1449 void
1450 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1451 {
1452 /* ??? There are apparently still problems with -fcaller-saves. */
1453 flag_caller_saves = 0;
1454
1455 /* By default, always emit DWARF-2 unwind info. This allows debugging
1456 without maintaining a stack frame back-chain. */
1457 flag_asynchronous_unwind_tables = 1;
1458
1459 /* Use MVCLE instructions to decrease code size if requested. */
1460 if (size != 0)
1461 target_flags |= MASK_MVCLE;
1462 }
1463
1464 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1465 to the associated processor_type and processor_flags if so. */
1466
1467 static bool
1468 s390_handle_arch_option (const char *arg,
1469 enum processor_type *type,
1470 int *flags)
1471 {
1472 static struct pta
1473 {
1474 const char *const name; /* processor name or nickname. */
1475 const enum processor_type processor;
1476 const int flags; /* From enum processor_flags. */
1477 }
1478 const processor_alias_table[] =
1479 {
1480 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1481 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1482 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1483 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1484 | PF_LONG_DISPLACEMENT},
1485 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1486 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1487 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1488 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1489 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1490 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1491 };
1492 size_t i;
1493
1494 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1495 if (strcmp (arg, processor_alias_table[i].name) == 0)
1496 {
1497 *type = processor_alias_table[i].processor;
1498 *flags = processor_alias_table[i].flags;
1499 return true;
1500 }
1501 return false;
1502 }
1503
1504 /* Implement TARGET_HANDLE_OPTION. */
1505
1506 static bool
1507 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1508 {
1509 switch (code)
1510 {
1511 case OPT_march_:
1512 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1513
1514 case OPT_mstack_guard_:
1515 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1516 return false;
1517 if (exact_log2 (s390_stack_guard) == -1)
1518 error ("stack guard value must be an exact power of 2");
1519 return true;
1520
1521 case OPT_mstack_size_:
1522 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1523 return false;
1524 if (exact_log2 (s390_stack_size) == -1)
1525 error ("stack size must be an exact power of 2");
1526 return true;
1527
1528 case OPT_mtune_:
1529 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1530
1531 case OPT_mwarn_framesize_:
1532 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1533
1534 default:
1535 return true;
1536 }
1537 }
1538
1539 void
1540 override_options (void)
1541 {
1542 /* Set up function hooks. */
1543 init_machine_status = s390_init_machine_status;
1544
1545 /* Architecture mode defaults according to ABI. */
1546 if (!(target_flags_explicit & MASK_ZARCH))
1547 {
1548 if (TARGET_64BIT)
1549 target_flags |= MASK_ZARCH;
1550 else
1551 target_flags &= ~MASK_ZARCH;
1552 }
1553
1554 /* Determine processor architectural level. */
1555 if (!s390_arch_string)
1556 {
1557 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1558 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1559 }
1560
1561 /* Determine processor to tune for. */
1562 if (s390_tune == PROCESSOR_max)
1563 {
1564 s390_tune = s390_arch;
1565 s390_tune_flags = s390_arch_flags;
1566 }
1567
1568 /* Sanity checks. */
1569 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1570 error ("z/Architecture mode not supported on %s", s390_arch_string);
1571 if (TARGET_64BIT && !TARGET_ZARCH)
1572 error ("64-bit ABI not supported in ESA/390 mode");
1573
1574 if (TARGET_HARD_DFP && !TARGET_DFP)
1575 {
1576 if (target_flags_explicit & MASK_HARD_DFP)
1577 {
1578 if (!TARGET_CPU_DFP)
1579 error ("Hardware decimal floating point instructions"
1580 " not available on %s", s390_arch_string);
1581 if (!TARGET_ZARCH)
1582 error ("Hardware decimal floating point instructions"
1583 " not available in ESA/390 mode");
1584 }
1585 else
1586 target_flags &= ~MASK_HARD_DFP;
1587 }
1588
1589 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1590 {
1591 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1592 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1593
1594 target_flags &= ~MASK_HARD_DFP;
1595 }
1596
1597 /* Set processor cost function. */
1598 switch (s390_tune)
1599 {
1600 case PROCESSOR_2084_Z990:
1601 s390_cost = &z990_cost;
1602 break;
1603 case PROCESSOR_2094_Z9_109:
1604 s390_cost = &z9_109_cost;
1605 break;
1606 case PROCESSOR_2097_Z10:
1607 s390_cost = &z10_cost;
1608 break;
1609 default:
1610 s390_cost = &z900_cost;
1611 }
1612
1613 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1614 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1615 "in combination");
1616
1617 if (s390_stack_size)
1618 {
1619 if (s390_stack_guard >= s390_stack_size)
1620 error ("stack size must be greater than the stack guard value");
1621 else if (s390_stack_size > 1 << 16)
1622 error ("stack size must not be greater than 64k");
1623 }
1624 else if (s390_stack_guard)
1625 error ("-mstack-guard implies use of -mstack-size");
1626
1627 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1628 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1629 target_flags |= MASK_LONG_DOUBLE_128;
1630 #endif
1631
1632 if (s390_tune == PROCESSOR_2097_Z10
1633 && !PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
1634 set_param_value ("max-unrolled-insns", 100);
1635 }
1636
1637 /* Map for smallest class containing reg regno. */
1638
1639 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1640 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1641 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1642 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1643 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1644 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1645 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1646 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1647 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1648 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1649 ACCESS_REGS, ACCESS_REGS
1650 };
1651
1652 /* Return attribute type of insn. */
1653
1654 static enum attr_type
1655 s390_safe_attr_type (rtx insn)
1656 {
1657 if (recog_memoized (insn) >= 0)
1658 return get_attr_type (insn);
1659 else
1660 return TYPE_NONE;
1661 }
1662
1663 /* Return true if DISP is a valid short displacement. */
1664
1665 static bool
1666 s390_short_displacement (rtx disp)
1667 {
1668 /* No displacement is OK. */
1669 if (!disp)
1670 return true;
1671
1672 /* Without the long displacement facility we don't need to
1673 distingiush between long and short displacement. */
1674 if (!TARGET_LONG_DISPLACEMENT)
1675 return true;
1676
1677 /* Integer displacement in range. */
1678 if (GET_CODE (disp) == CONST_INT)
1679 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1680
1681 /* GOT offset is not OK, the GOT can be large. */
1682 if (GET_CODE (disp) == CONST
1683 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1684 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1685 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1686 return false;
1687
1688 /* All other symbolic constants are literal pool references,
1689 which are OK as the literal pool must be small. */
1690 if (GET_CODE (disp) == CONST)
1691 return true;
1692
1693 return false;
1694 }
1695
1696 /* Decompose a RTL expression ADDR for a memory address into
1697 its components, returned in OUT.
1698
1699 Returns false if ADDR is not a valid memory address, true
1700 otherwise. If OUT is NULL, don't return the components,
1701 but check for validity only.
1702
1703 Note: Only addresses in canonical form are recognized.
1704 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1705 canonical form so that they will be recognized. */
1706
1707 static int
1708 s390_decompose_address (rtx addr, struct s390_address *out)
1709 {
1710 HOST_WIDE_INT offset = 0;
1711 rtx base = NULL_RTX;
1712 rtx indx = NULL_RTX;
1713 rtx disp = NULL_RTX;
1714 rtx orig_disp;
1715 bool pointer = false;
1716 bool base_ptr = false;
1717 bool indx_ptr = false;
1718 bool literal_pool = false;
1719
1720 /* We may need to substitute the literal pool base register into the address
1721 below. However, at this point we do not know which register is going to
1722 be used as base, so we substitute the arg pointer register. This is going
1723 to be treated as holding a pointer below -- it shouldn't be used for any
1724 other purpose. */
1725 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1726
1727 /* Decompose address into base + index + displacement. */
1728
1729 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1730 base = addr;
1731
1732 else if (GET_CODE (addr) == PLUS)
1733 {
1734 rtx op0 = XEXP (addr, 0);
1735 rtx op1 = XEXP (addr, 1);
1736 enum rtx_code code0 = GET_CODE (op0);
1737 enum rtx_code code1 = GET_CODE (op1);
1738
1739 if (code0 == REG || code0 == UNSPEC)
1740 {
1741 if (code1 == REG || code1 == UNSPEC)
1742 {
1743 indx = op0; /* index + base */
1744 base = op1;
1745 }
1746
1747 else
1748 {
1749 base = op0; /* base + displacement */
1750 disp = op1;
1751 }
1752 }
1753
1754 else if (code0 == PLUS)
1755 {
1756 indx = XEXP (op0, 0); /* index + base + disp */
1757 base = XEXP (op0, 1);
1758 disp = op1;
1759 }
1760
1761 else
1762 {
1763 return false;
1764 }
1765 }
1766
1767 else
1768 disp = addr; /* displacement */
1769
1770 /* Extract integer part of displacement. */
1771 orig_disp = disp;
1772 if (disp)
1773 {
1774 if (GET_CODE (disp) == CONST_INT)
1775 {
1776 offset = INTVAL (disp);
1777 disp = NULL_RTX;
1778 }
1779 else if (GET_CODE (disp) == CONST
1780 && GET_CODE (XEXP (disp, 0)) == PLUS
1781 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1782 {
1783 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1784 disp = XEXP (XEXP (disp, 0), 0);
1785 }
1786 }
1787
1788 /* Strip off CONST here to avoid special case tests later. */
1789 if (disp && GET_CODE (disp) == CONST)
1790 disp = XEXP (disp, 0);
1791
1792 /* We can convert literal pool addresses to
1793 displacements by basing them off the base register. */
1794 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1795 {
1796 /* Either base or index must be free to hold the base register. */
1797 if (!base)
1798 base = fake_pool_base, literal_pool = true;
1799 else if (!indx)
1800 indx = fake_pool_base, literal_pool = true;
1801 else
1802 return false;
1803
1804 /* Mark up the displacement. */
1805 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1806 UNSPEC_LTREL_OFFSET);
1807 }
1808
1809 /* Validate base register. */
1810 if (base)
1811 {
1812 if (GET_CODE (base) == UNSPEC)
1813 switch (XINT (base, 1))
1814 {
1815 case UNSPEC_LTREF:
1816 if (!disp)
1817 disp = gen_rtx_UNSPEC (Pmode,
1818 gen_rtvec (1, XVECEXP (base, 0, 0)),
1819 UNSPEC_LTREL_OFFSET);
1820 else
1821 return false;
1822
1823 base = XVECEXP (base, 0, 1);
1824 break;
1825
1826 case UNSPEC_LTREL_BASE:
1827 if (XVECLEN (base, 0) == 1)
1828 base = fake_pool_base, literal_pool = true;
1829 else
1830 base = XVECEXP (base, 0, 1);
1831 break;
1832
1833 default:
1834 return false;
1835 }
1836
1837 if (!REG_P (base)
1838 || (GET_MODE (base) != SImode
1839 && GET_MODE (base) != Pmode))
1840 return false;
1841
1842 if (REGNO (base) == STACK_POINTER_REGNUM
1843 || REGNO (base) == FRAME_POINTER_REGNUM
1844 || ((reload_completed || reload_in_progress)
1845 && frame_pointer_needed
1846 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1847 || REGNO (base) == ARG_POINTER_REGNUM
1848 || (flag_pic
1849 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1850 pointer = base_ptr = true;
1851
1852 if ((reload_completed || reload_in_progress)
1853 && base == cfun->machine->base_reg)
1854 pointer = base_ptr = literal_pool = true;
1855 }
1856
1857 /* Validate index register. */
1858 if (indx)
1859 {
1860 if (GET_CODE (indx) == UNSPEC)
1861 switch (XINT (indx, 1))
1862 {
1863 case UNSPEC_LTREF:
1864 if (!disp)
1865 disp = gen_rtx_UNSPEC (Pmode,
1866 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1867 UNSPEC_LTREL_OFFSET);
1868 else
1869 return false;
1870
1871 indx = XVECEXP (indx, 0, 1);
1872 break;
1873
1874 case UNSPEC_LTREL_BASE:
1875 if (XVECLEN (indx, 0) == 1)
1876 indx = fake_pool_base, literal_pool = true;
1877 else
1878 indx = XVECEXP (indx, 0, 1);
1879 break;
1880
1881 default:
1882 return false;
1883 }
1884
1885 if (!REG_P (indx)
1886 || (GET_MODE (indx) != SImode
1887 && GET_MODE (indx) != Pmode))
1888 return false;
1889
1890 if (REGNO (indx) == STACK_POINTER_REGNUM
1891 || REGNO (indx) == FRAME_POINTER_REGNUM
1892 || ((reload_completed || reload_in_progress)
1893 && frame_pointer_needed
1894 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1895 || REGNO (indx) == ARG_POINTER_REGNUM
1896 || (flag_pic
1897 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1898 pointer = indx_ptr = true;
1899
1900 if ((reload_completed || reload_in_progress)
1901 && indx == cfun->machine->base_reg)
1902 pointer = indx_ptr = literal_pool = true;
1903 }
1904
1905 /* Prefer to use pointer as base, not index. */
1906 if (base && indx && !base_ptr
1907 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1908 {
1909 rtx tmp = base;
1910 base = indx;
1911 indx = tmp;
1912 }
1913
1914 /* Validate displacement. */
1915 if (!disp)
1916 {
1917 /* If virtual registers are involved, the displacement will change later
1918 anyway as the virtual registers get eliminated. This could make a
1919 valid displacement invalid, but it is more likely to make an invalid
1920 displacement valid, because we sometimes access the register save area
1921 via negative offsets to one of those registers.
1922 Thus we don't check the displacement for validity here. If after
1923 elimination the displacement turns out to be invalid after all,
1924 this is fixed up by reload in any case. */
1925 if (base != arg_pointer_rtx
1926 && indx != arg_pointer_rtx
1927 && base != return_address_pointer_rtx
1928 && indx != return_address_pointer_rtx
1929 && base != frame_pointer_rtx
1930 && indx != frame_pointer_rtx
1931 && base != virtual_stack_vars_rtx
1932 && indx != virtual_stack_vars_rtx)
1933 if (!DISP_IN_RANGE (offset))
1934 return false;
1935 }
1936 else
1937 {
1938 /* All the special cases are pointers. */
1939 pointer = true;
1940
1941 /* In the small-PIC case, the linker converts @GOT
1942 and @GOTNTPOFF offsets to possible displacements. */
1943 if (GET_CODE (disp) == UNSPEC
1944 && (XINT (disp, 1) == UNSPEC_GOT
1945 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1946 && flag_pic == 1)
1947 {
1948 ;
1949 }
1950
1951 /* Accept pool label offsets. */
1952 else if (GET_CODE (disp) == UNSPEC
1953 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1954 ;
1955
1956 /* Accept literal pool references. */
1957 else if (GET_CODE (disp) == UNSPEC
1958 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1959 {
1960 orig_disp = gen_rtx_CONST (Pmode, disp);
1961 if (offset)
1962 {
1963 /* If we have an offset, make sure it does not
1964 exceed the size of the constant pool entry. */
1965 rtx sym = XVECEXP (disp, 0, 0);
1966 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1967 return false;
1968
1969 orig_disp = plus_constant (orig_disp, offset);
1970 }
1971 }
1972
1973 else
1974 return false;
1975 }
1976
1977 if (!base && !indx)
1978 pointer = true;
1979
1980 if (out)
1981 {
1982 out->base = base;
1983 out->indx = indx;
1984 out->disp = orig_disp;
1985 out->pointer = pointer;
1986 out->literal_pool = literal_pool;
1987 }
1988
1989 return true;
1990 }
1991
1992 /* Decompose a RTL expression OP for a shift count into its components,
1993 and return the base register in BASE and the offset in OFFSET.
1994
1995 Return true if OP is a valid shift count, false if not. */
1996
1997 bool
1998 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1999 {
2000 HOST_WIDE_INT off = 0;
2001
2002 /* We can have an integer constant, an address register,
2003 or a sum of the two. */
2004 if (GET_CODE (op) == CONST_INT)
2005 {
2006 off = INTVAL (op);
2007 op = NULL_RTX;
2008 }
2009 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2010 {
2011 off = INTVAL (XEXP (op, 1));
2012 op = XEXP (op, 0);
2013 }
2014 while (op && GET_CODE (op) == SUBREG)
2015 op = SUBREG_REG (op);
2016
2017 if (op && GET_CODE (op) != REG)
2018 return false;
2019
2020 if (offset)
2021 *offset = off;
2022 if (base)
2023 *base = op;
2024
2025 return true;
2026 }
2027
2028
2029 /* Return true if CODE is a valid address without index. */
2030
2031 bool
2032 s390_legitimate_address_without_index_p (rtx op)
2033 {
2034 struct s390_address addr;
2035
2036 if (!s390_decompose_address (XEXP (op, 0), &addr))
2037 return false;
2038 if (addr.indx)
2039 return false;
2040
2041 return true;
2042 }
2043
2044
2045 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2046 and return these parts in SYMREF and ADDEND. You can pass NULL in
2047 SYMREF and/or ADDEND if you are not interested in these values. */
2048
2049 static bool
2050 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2051 {
2052 HOST_WIDE_INT tmpaddend = 0;
2053
2054 if (GET_CODE (addr) == CONST)
2055 addr = XEXP (addr, 0);
2056
2057 if (GET_CODE (addr) == PLUS)
2058 {
2059 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2060 && CONST_INT_P (XEXP (addr, 1)))
2061 {
2062 tmpaddend = INTVAL (XEXP (addr, 1));
2063 addr = XEXP (addr, 0);
2064 }
2065 else
2066 return false;
2067 }
2068 else
2069 if (GET_CODE (addr) != SYMBOL_REF)
2070 return false;
2071
2072 if (symref)
2073 *symref = addr;
2074 if (addend)
2075 *addend = tmpaddend;
2076
2077 return true;
2078 }
2079
2080
2081 /* Return true if the address in OP is valid for constraint letter C
2082 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2083 pool MEMs should be accepted. Only the Q, R, S, T constraint
2084 letters are allowed for C. */
2085
2086 static int
2087 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2088 {
2089 struct s390_address addr;
2090 bool decomposed = false;
2091
2092 /* This check makes sure that no symbolic address (except literal
2093 pool references) are accepted by the R or T constraints. */
2094 if (s390_symref_operand_p (op, NULL, NULL))
2095 {
2096 if (!lit_pool_ok)
2097 return 0;
2098 if (!s390_decompose_address (op, &addr))
2099 return 0;
2100 if (!addr.literal_pool)
2101 return 0;
2102 decomposed = true;
2103 }
2104
2105 switch (c)
2106 {
2107 case 'Q': /* no index short displacement */
2108 if (!decomposed && !s390_decompose_address (op, &addr))
2109 return 0;
2110 if (addr.indx)
2111 return 0;
2112 if (!s390_short_displacement (addr.disp))
2113 return 0;
2114 break;
2115
2116 case 'R': /* with index short displacement */
2117 if (TARGET_LONG_DISPLACEMENT)
2118 {
2119 if (!decomposed && !s390_decompose_address (op, &addr))
2120 return 0;
2121 if (!s390_short_displacement (addr.disp))
2122 return 0;
2123 }
2124 /* Any invalid address here will be fixed up by reload,
2125 so accept it for the most generic constraint. */
2126 break;
2127
2128 case 'S': /* no index long displacement */
2129 if (!TARGET_LONG_DISPLACEMENT)
2130 return 0;
2131 if (!decomposed && !s390_decompose_address (op, &addr))
2132 return 0;
2133 if (addr.indx)
2134 return 0;
2135 if (s390_short_displacement (addr.disp))
2136 return 0;
2137 break;
2138
2139 case 'T': /* with index long displacement */
2140 if (!TARGET_LONG_DISPLACEMENT)
2141 return 0;
2142 /* Any invalid address here will be fixed up by reload,
2143 so accept it for the most generic constraint. */
2144 if ((decomposed || s390_decompose_address (op, &addr))
2145 && s390_short_displacement (addr.disp))
2146 return 0;
2147 break;
2148 default:
2149 return 0;
2150 }
2151 return 1;
2152 }
2153
2154
2155 /* Evaluates constraint strings described by the regular expression
2156 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2157 the constraint given in STR, or 0 else. */
2158
2159 int
2160 s390_mem_constraint (const char *str, rtx op)
2161 {
2162 char c = str[0];
2163
2164 switch (c)
2165 {
2166 case 'A':
2167 /* Check for offsettable variants of memory constraints. */
2168 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2169 return 0;
2170 if ((reload_completed || reload_in_progress)
2171 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2172 return 0;
2173 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2174 case 'B':
2175 /* Check for non-literal-pool variants of memory constraints. */
2176 if (!MEM_P (op))
2177 return 0;
2178 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2179 case 'Q':
2180 case 'R':
2181 case 'S':
2182 case 'T':
2183 if (GET_CODE (op) != MEM)
2184 return 0;
2185 return s390_check_qrst_address (c, XEXP (op, 0), true);
2186 case 'U':
2187 return (s390_check_qrst_address ('Q', op, true)
2188 || s390_check_qrst_address ('R', op, true));
2189 case 'W':
2190 return (s390_check_qrst_address ('S', op, true)
2191 || s390_check_qrst_address ('T', op, true));
2192 case 'Y':
2193 /* Simply check for the basic form of a shift count. Reload will
2194 take care of making sure we have a proper base register. */
2195 if (!s390_decompose_shift_count (op, NULL, NULL))
2196 return 0;
2197 break;
2198 case 'Z':
2199 return s390_check_qrst_address (str[1], op, true);
2200 default:
2201 return 0;
2202 }
2203 return 1;
2204 }
2205
2206
2207 /* Evaluates constraint strings starting with letter O. Input
2208 parameter C is the second letter following the "O" in the constraint
2209 string. Returns 1 if VALUE meets the respective constraint and 0
2210 otherwise. */
2211
2212 int
2213 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2214 {
2215 if (!TARGET_EXTIMM)
2216 return 0;
2217
2218 switch (c)
2219 {
2220 case 's':
2221 return trunc_int_for_mode (value, SImode) == value;
2222
2223 case 'p':
2224 return value == 0
2225 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2226
2227 case 'n':
2228 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2229
2230 default:
2231 gcc_unreachable ();
2232 }
2233 }
2234
2235
2236 /* Evaluates constraint strings starting with letter N. Parameter STR
2237 contains the letters following letter "N" in the constraint string.
2238 Returns true if VALUE matches the constraint. */
2239
2240 int
2241 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2242 {
2243 enum machine_mode mode, part_mode;
2244 int def;
2245 int part, part_goal;
2246
2247
2248 if (str[0] == 'x')
2249 part_goal = -1;
2250 else
2251 part_goal = str[0] - '0';
2252
2253 switch (str[1])
2254 {
2255 case 'Q':
2256 part_mode = QImode;
2257 break;
2258 case 'H':
2259 part_mode = HImode;
2260 break;
2261 case 'S':
2262 part_mode = SImode;
2263 break;
2264 default:
2265 return 0;
2266 }
2267
2268 switch (str[2])
2269 {
2270 case 'H':
2271 mode = HImode;
2272 break;
2273 case 'S':
2274 mode = SImode;
2275 break;
2276 case 'D':
2277 mode = DImode;
2278 break;
2279 default:
2280 return 0;
2281 }
2282
2283 switch (str[3])
2284 {
2285 case '0':
2286 def = 0;
2287 break;
2288 case 'F':
2289 def = -1;
2290 break;
2291 default:
2292 return 0;
2293 }
2294
2295 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2296 return 0;
2297
2298 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2299 if (part < 0)
2300 return 0;
2301 if (part_goal != -1 && part_goal != part)
2302 return 0;
2303
2304 return 1;
2305 }
2306
2307
2308 /* Returns true if the input parameter VALUE is a float zero. */
2309
2310 int
2311 s390_float_const_zero_p (rtx value)
2312 {
2313 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2314 && value == CONST0_RTX (GET_MODE (value)));
2315 }
2316
2317
2318 /* Compute a (partial) cost for rtx X. Return true if the complete
2319 cost has been computed, and false if subexpressions should be
2320 scanned. In either case, *TOTAL contains the cost result.
2321 CODE contains GET_CODE (x), OUTER_CODE contains the code
2322 of the superexpression of x. */
2323
2324 static bool
2325 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2326 bool speed ATTRIBUTE_UNUSED)
2327 {
2328 switch (code)
2329 {
2330 case CONST:
2331 case CONST_INT:
2332 case LABEL_REF:
2333 case SYMBOL_REF:
2334 case CONST_DOUBLE:
2335 case MEM:
2336 *total = 0;
2337 return true;
2338
2339 case ASHIFT:
2340 case ASHIFTRT:
2341 case LSHIFTRT:
2342 case ROTATE:
2343 case ROTATERT:
2344 case AND:
2345 case IOR:
2346 case XOR:
2347 case NEG:
2348 case NOT:
2349 *total = COSTS_N_INSNS (1);
2350 return false;
2351
2352 case PLUS:
2353 case MINUS:
2354 /* Check for multiply and add. */
2355 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2356 && GET_CODE (XEXP (x, 0)) == MULT
2357 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2358 {
2359 /* This is the multiply and add case. */
2360 if (GET_MODE (x) == DFmode)
2361 *total = s390_cost->madbr;
2362 else
2363 *total = s390_cost->maebr;
2364 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2365 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2366 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2367 return true; /* Do not do an additional recursive descent. */
2368 }
2369 *total = COSTS_N_INSNS (1);
2370 return false;
2371
2372 case MULT:
2373 switch (GET_MODE (x))
2374 {
2375 case SImode:
2376 {
2377 rtx left = XEXP (x, 0);
2378 rtx right = XEXP (x, 1);
2379 if (GET_CODE (right) == CONST_INT
2380 && CONST_OK_FOR_K (INTVAL (right)))
2381 *total = s390_cost->mhi;
2382 else if (GET_CODE (left) == SIGN_EXTEND)
2383 *total = s390_cost->mh;
2384 else
2385 *total = s390_cost->ms; /* msr, ms, msy */
2386 break;
2387 }
2388 case DImode:
2389 {
2390 rtx left = XEXP (x, 0);
2391 rtx right = XEXP (x, 1);
2392 if (TARGET_64BIT)
2393 {
2394 if (GET_CODE (right) == CONST_INT
2395 && CONST_OK_FOR_K (INTVAL (right)))
2396 *total = s390_cost->mghi;
2397 else if (GET_CODE (left) == SIGN_EXTEND)
2398 *total = s390_cost->msgf;
2399 else
2400 *total = s390_cost->msg; /* msgr, msg */
2401 }
2402 else /* TARGET_31BIT */
2403 {
2404 if (GET_CODE (left) == SIGN_EXTEND
2405 && GET_CODE (right) == SIGN_EXTEND)
2406 /* mulsidi case: mr, m */
2407 *total = s390_cost->m;
2408 else if (GET_CODE (left) == ZERO_EXTEND
2409 && GET_CODE (right) == ZERO_EXTEND
2410 && TARGET_CPU_ZARCH)
2411 /* umulsidi case: ml, mlr */
2412 *total = s390_cost->ml;
2413 else
2414 /* Complex calculation is required. */
2415 *total = COSTS_N_INSNS (40);
2416 }
2417 break;
2418 }
2419 case SFmode:
2420 case DFmode:
2421 *total = s390_cost->mult_df;
2422 break;
2423 case TFmode:
2424 *total = s390_cost->mxbr;
2425 break;
2426 default:
2427 return false;
2428 }
2429 return false;
2430
2431 case UDIV:
2432 case UMOD:
2433 if (GET_MODE (x) == TImode) /* 128 bit division */
2434 *total = s390_cost->dlgr;
2435 else if (GET_MODE (x) == DImode)
2436 {
2437 rtx right = XEXP (x, 1);
2438 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2439 *total = s390_cost->dlr;
2440 else /* 64 by 64 bit division */
2441 *total = s390_cost->dlgr;
2442 }
2443 else if (GET_MODE (x) == SImode) /* 32 bit division */
2444 *total = s390_cost->dlr;
2445 return false;
2446
2447 case DIV:
2448 case MOD:
2449 if (GET_MODE (x) == DImode)
2450 {
2451 rtx right = XEXP (x, 1);
2452 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2453 if (TARGET_64BIT)
2454 *total = s390_cost->dsgfr;
2455 else
2456 *total = s390_cost->dr;
2457 else /* 64 by 64 bit division */
2458 *total = s390_cost->dsgr;
2459 }
2460 else if (GET_MODE (x) == SImode) /* 32 bit division */
2461 *total = s390_cost->dlr;
2462 else if (GET_MODE (x) == SFmode)
2463 {
2464 *total = s390_cost->debr;
2465 }
2466 else if (GET_MODE (x) == DFmode)
2467 {
2468 *total = s390_cost->ddbr;
2469 }
2470 else if (GET_MODE (x) == TFmode)
2471 {
2472 *total = s390_cost->dxbr;
2473 }
2474 return false;
2475
2476 case SQRT:
2477 if (GET_MODE (x) == SFmode)
2478 *total = s390_cost->sqebr;
2479 else if (GET_MODE (x) == DFmode)
2480 *total = s390_cost->sqdbr;
2481 else /* TFmode */
2482 *total = s390_cost->sqxbr;
2483 return false;
2484
2485 case SIGN_EXTEND:
2486 case ZERO_EXTEND:
2487 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2488 || outer_code == PLUS || outer_code == MINUS
2489 || outer_code == COMPARE)
2490 *total = 0;
2491 return false;
2492
2493 case COMPARE:
2494 *total = COSTS_N_INSNS (1);
2495 if (GET_CODE (XEXP (x, 0)) == AND
2496 && GET_CODE (XEXP (x, 1)) == CONST_INT
2497 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2498 {
2499 rtx op0 = XEXP (XEXP (x, 0), 0);
2500 rtx op1 = XEXP (XEXP (x, 0), 1);
2501 rtx op2 = XEXP (x, 1);
2502
2503 if (memory_operand (op0, GET_MODE (op0))
2504 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2505 return true;
2506 if (register_operand (op0, GET_MODE (op0))
2507 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2508 return true;
2509 }
2510 return false;
2511
2512 default:
2513 return false;
2514 }
2515 }
2516
2517 /* Return the cost of an address rtx ADDR. */
2518
2519 static int
2520 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2521 {
2522 struct s390_address ad;
2523 if (!s390_decompose_address (addr, &ad))
2524 return 1000;
2525
2526 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2527 }
2528
2529 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2530 otherwise return 0. */
2531
2532 int
2533 tls_symbolic_operand (rtx op)
2534 {
2535 if (GET_CODE (op) != SYMBOL_REF)
2536 return 0;
2537 return SYMBOL_REF_TLS_MODEL (op);
2538 }
2539 \f
2540 /* Split DImode access register reference REG (on 64-bit) into its constituent
2541 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2542 gen_highpart cannot be used as they assume all registers are word-sized,
2543 while our access registers have only half that size. */
2544
2545 void
2546 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2547 {
2548 gcc_assert (TARGET_64BIT);
2549 gcc_assert (ACCESS_REG_P (reg));
2550 gcc_assert (GET_MODE (reg) == DImode);
2551 gcc_assert (!(REGNO (reg) & 1));
2552
2553 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2554 *hi = gen_rtx_REG (SImode, REGNO (reg));
2555 }
2556
2557 /* Return true if OP contains a symbol reference */
2558
2559 bool
2560 symbolic_reference_mentioned_p (rtx op)
2561 {
2562 const char *fmt;
2563 int i;
2564
2565 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2566 return 1;
2567
2568 fmt = GET_RTX_FORMAT (GET_CODE (op));
2569 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2570 {
2571 if (fmt[i] == 'E')
2572 {
2573 int j;
2574
2575 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2576 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2577 return 1;
2578 }
2579
2580 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2581 return 1;
2582 }
2583
2584 return 0;
2585 }
2586
2587 /* Return true if OP contains a reference to a thread-local symbol. */
2588
2589 bool
2590 tls_symbolic_reference_mentioned_p (rtx op)
2591 {
2592 const char *fmt;
2593 int i;
2594
2595 if (GET_CODE (op) == SYMBOL_REF)
2596 return tls_symbolic_operand (op);
2597
2598 fmt = GET_RTX_FORMAT (GET_CODE (op));
2599 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2600 {
2601 if (fmt[i] == 'E')
2602 {
2603 int j;
2604
2605 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2606 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2607 return true;
2608 }
2609
2610 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2611 return true;
2612 }
2613
2614 return false;
2615 }
2616
2617
2618 /* Return true if OP is a legitimate general operand when
2619 generating PIC code. It is given that flag_pic is on
2620 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2621
2622 int
2623 legitimate_pic_operand_p (rtx op)
2624 {
2625 /* Accept all non-symbolic constants. */
2626 if (!SYMBOLIC_CONST (op))
2627 return 1;
2628
2629 /* Reject everything else; must be handled
2630 via emit_symbolic_move. */
2631 return 0;
2632 }
2633
2634 /* Returns true if the constant value OP is a legitimate general operand.
2635 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2636
2637 int
2638 legitimate_constant_p (rtx op)
2639 {
2640 /* Accept all non-symbolic constants. */
2641 if (!SYMBOLIC_CONST (op))
2642 return 1;
2643
2644 /* Accept immediate LARL operands. */
2645 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2646 return 1;
2647
2648 /* Thread-local symbols are never legal constants. This is
2649 so that emit_call knows that computing such addresses
2650 might require a function call. */
2651 if (TLS_SYMBOLIC_CONST (op))
2652 return 0;
2653
2654 /* In the PIC case, symbolic constants must *not* be
2655 forced into the literal pool. We accept them here,
2656 so that they will be handled by emit_symbolic_move. */
2657 if (flag_pic)
2658 return 1;
2659
2660 /* All remaining non-PIC symbolic constants are
2661 forced into the literal pool. */
2662 return 0;
2663 }
2664
2665 /* Determine if it's legal to put X into the constant pool. This
2666 is not possible if X contains the address of a symbol that is
2667 not constant (TLS) or not known at final link time (PIC). */
2668
2669 static bool
2670 s390_cannot_force_const_mem (rtx x)
2671 {
2672 switch (GET_CODE (x))
2673 {
2674 case CONST_INT:
2675 case CONST_DOUBLE:
2676 /* Accept all non-symbolic constants. */
2677 return false;
2678
2679 case LABEL_REF:
2680 /* Labels are OK iff we are non-PIC. */
2681 return flag_pic != 0;
2682
2683 case SYMBOL_REF:
2684 /* 'Naked' TLS symbol references are never OK,
2685 non-TLS symbols are OK iff we are non-PIC. */
2686 if (tls_symbolic_operand (x))
2687 return true;
2688 else
2689 return flag_pic != 0;
2690
2691 case CONST:
2692 return s390_cannot_force_const_mem (XEXP (x, 0));
2693 case PLUS:
2694 case MINUS:
2695 return s390_cannot_force_const_mem (XEXP (x, 0))
2696 || s390_cannot_force_const_mem (XEXP (x, 1));
2697
2698 case UNSPEC:
2699 switch (XINT (x, 1))
2700 {
2701 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2702 case UNSPEC_LTREL_OFFSET:
2703 case UNSPEC_GOT:
2704 case UNSPEC_GOTOFF:
2705 case UNSPEC_PLTOFF:
2706 case UNSPEC_TLSGD:
2707 case UNSPEC_TLSLDM:
2708 case UNSPEC_NTPOFF:
2709 case UNSPEC_DTPOFF:
2710 case UNSPEC_GOTNTPOFF:
2711 case UNSPEC_INDNTPOFF:
2712 return false;
2713
2714 /* If the literal pool shares the code section, be put
2715 execute template placeholders into the pool as well. */
2716 case UNSPEC_INSN:
2717 return TARGET_CPU_ZARCH;
2718
2719 default:
2720 return true;
2721 }
2722 break;
2723
2724 default:
2725 gcc_unreachable ();
2726 }
2727 }
2728
2729 /* Returns true if the constant value OP is a legitimate general
2730 operand during and after reload. The difference to
2731 legitimate_constant_p is that this function will not accept
2732 a constant that would need to be forced to the literal pool
2733 before it can be used as operand. */
2734
2735 bool
2736 legitimate_reload_constant_p (rtx op)
2737 {
2738 /* Accept la(y) operands. */
2739 if (GET_CODE (op) == CONST_INT
2740 && DISP_IN_RANGE (INTVAL (op)))
2741 return true;
2742
2743 /* Accept l(g)hi/l(g)fi operands. */
2744 if (GET_CODE (op) == CONST_INT
2745 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2746 return true;
2747
2748 /* Accept lliXX operands. */
2749 if (TARGET_ZARCH
2750 && GET_CODE (op) == CONST_INT
2751 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2752 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2753 return true;
2754
2755 if (TARGET_EXTIMM
2756 && GET_CODE (op) == CONST_INT
2757 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2758 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2759 return true;
2760
2761 /* Accept larl operands. */
2762 if (TARGET_CPU_ZARCH
2763 && larl_operand (op, VOIDmode))
2764 return true;
2765
2766 /* Accept lzXX operands. */
2767 if (GET_CODE (op) == CONST_DOUBLE
2768 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2769 return true;
2770
2771 /* Accept double-word operands that can be split. */
2772 if (GET_CODE (op) == CONST_INT
2773 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2774 {
2775 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2776 rtx hi = operand_subword (op, 0, 0, dword_mode);
2777 rtx lo = operand_subword (op, 1, 0, dword_mode);
2778 return legitimate_reload_constant_p (hi)
2779 && legitimate_reload_constant_p (lo);
2780 }
2781
2782 /* Everything else cannot be handled without reload. */
2783 return false;
2784 }
2785
2786 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2787 return the class of reg to actually use. */
2788
2789 enum reg_class
2790 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2791 {
2792 switch (GET_CODE (op))
2793 {
2794 /* Constants we cannot reload must be forced into the
2795 literal pool. */
2796
2797 case CONST_DOUBLE:
2798 case CONST_INT:
2799 if (legitimate_reload_constant_p (op))
2800 return rclass;
2801 else
2802 return NO_REGS;
2803
2804 /* If a symbolic constant or a PLUS is reloaded,
2805 it is most likely being used as an address, so
2806 prefer ADDR_REGS. If 'class' is not a superset
2807 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2808 case PLUS:
2809 case LABEL_REF:
2810 case SYMBOL_REF:
2811 case CONST:
2812 if (reg_class_subset_p (ADDR_REGS, rclass))
2813 return ADDR_REGS;
2814 else
2815 return NO_REGS;
2816
2817 default:
2818 break;
2819 }
2820
2821 return rclass;
2822 }
2823
2824 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2825 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2826 aligned. */
2827
2828 bool
2829 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2830 {
2831 HOST_WIDE_INT addend;
2832 rtx symref;
2833
2834 if (!s390_symref_operand_p (addr, &symref, &addend))
2835 return false;
2836
2837 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2838 && !(addend & (alignment - 1)));
2839 }
2840
2841 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2842 operand SCRATCH is used to reload the even part of the address and
2843 adding one. */
2844
2845 void
2846 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2847 {
2848 HOST_WIDE_INT addend;
2849 rtx symref;
2850
2851 if (!s390_symref_operand_p (addr, &symref, &addend))
2852 gcc_unreachable ();
2853
2854 if (!(addend & 1))
2855 /* Easy case. The addend is even so larl will do fine. */
2856 emit_move_insn (reg, addr);
2857 else
2858 {
2859 /* We can leave the scratch register untouched if the target
2860 register is a valid base register. */
2861 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2862 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2863 scratch = reg;
2864
2865 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2866 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2867
2868 if (addend != 1)
2869 emit_move_insn (scratch,
2870 gen_rtx_CONST (Pmode,
2871 gen_rtx_PLUS (Pmode, symref,
2872 GEN_INT (addend - 1))));
2873 else
2874 emit_move_insn (scratch, symref);
2875
2876 /* Increment the address using la in order to avoid clobbering cc. */
2877 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2878 }
2879 }
2880
2881 /* Generate what is necessary to move between REG and MEM using
2882 SCRATCH. The direction is given by TOMEM. */
2883
2884 void
2885 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2886 {
2887 /* Reload might have pulled a constant out of the literal pool.
2888 Force it back in. */
2889 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2890 || GET_CODE (mem) == CONST)
2891 mem = force_const_mem (GET_MODE (reg), mem);
2892
2893 gcc_assert (MEM_P (mem));
2894
2895 /* For a load from memory we can leave the scratch register
2896 untouched if the target register is a valid base register. */
2897 if (!tomem
2898 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2899 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2900 && GET_MODE (reg) == GET_MODE (scratch))
2901 scratch = reg;
2902
2903 /* Load address into scratch register. Since we can't have a
2904 secondary reload for a secondary reload we have to cover the case
2905 where larl would need a secondary reload here as well. */
2906 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2907
2908 /* Now we can use a standard load/store to do the move. */
2909 if (tomem)
2910 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2911 else
2912 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2913 }
2914
2915 /* Inform reload about cases where moving X with a mode MODE to a register in
2916 RCLASS requires an extra scratch or immediate register. Return the class
2917 needed for the immediate register. */
2918
2919 static enum reg_class
2920 s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2921 enum machine_mode mode, secondary_reload_info *sri)
2922 {
2923 /* Intermediate register needed. */
2924 if (reg_classes_intersect_p (CC_REGS, rclass))
2925 return GENERAL_REGS;
2926
2927 if (TARGET_Z10)
2928 {
2929 /* On z10 several optimizer steps may generate larl operands with
2930 an odd addend. */
2931 if (in_p
2932 && s390_symref_operand_p (x, NULL, NULL)
2933 && mode == Pmode
2934 && !s390_check_symref_alignment (x, 2))
2935 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2936 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2937
2938 /* On z10 we need a scratch register when moving QI, TI or floating
2939 point mode values from or to a memory location with a SYMBOL_REF
2940 or if the symref addend of a SI or DI move is not aligned to the
2941 width of the access. */
2942 if (MEM_P (x)
2943 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2944 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2945 || (!TARGET_64BIT && mode == DImode)
2946 || ((mode == HImode || mode == SImode || mode == DImode)
2947 && (!s390_check_symref_alignment (XEXP (x, 0),
2948 GET_MODE_SIZE (mode))))))
2949 {
2950 #define __SECONDARY_RELOAD_CASE(M,m) \
2951 case M##mode: \
2952 if (TARGET_64BIT) \
2953 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2954 CODE_FOR_reload##m##di_tomem_z10; \
2955 else \
2956 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
2957 CODE_FOR_reload##m##si_tomem_z10; \
2958 break;
2959
2960 switch (GET_MODE (x))
2961 {
2962 __SECONDARY_RELOAD_CASE (QI, qi);
2963 __SECONDARY_RELOAD_CASE (HI, hi);
2964 __SECONDARY_RELOAD_CASE (SI, si);
2965 __SECONDARY_RELOAD_CASE (DI, di);
2966 __SECONDARY_RELOAD_CASE (TI, ti);
2967 __SECONDARY_RELOAD_CASE (SF, sf);
2968 __SECONDARY_RELOAD_CASE (DF, df);
2969 __SECONDARY_RELOAD_CASE (TF, tf);
2970 __SECONDARY_RELOAD_CASE (SD, sd);
2971 __SECONDARY_RELOAD_CASE (DD, dd);
2972 __SECONDARY_RELOAD_CASE (TD, td);
2973
2974 default:
2975 gcc_unreachable ();
2976 }
2977 #undef __SECONDARY_RELOAD_CASE
2978 }
2979 }
2980
2981 /* We need a scratch register when loading a PLUS expression which
2982 is not a legitimate operand of the LOAD ADDRESS instruction. */
2983 if (in_p && s390_plus_operand (x, mode))
2984 sri->icode = (TARGET_64BIT ?
2985 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
2986
2987 /* Performing a multiword move from or to memory we have to make sure the
2988 second chunk in memory is addressable without causing a displacement
2989 overflow. If that would be the case we calculate the address in
2990 a scratch register. */
2991 if (MEM_P (x)
2992 && GET_CODE (XEXP (x, 0)) == PLUS
2993 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2994 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
2995 + GET_MODE_SIZE (mode) - 1))
2996 {
2997 /* For GENERAL_REGS a displacement overflow is no problem if occurring
2998 in a s_operand address since we may fallback to lm/stm. So we only
2999 have to care about overflows in the b+i+d case. */
3000 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3001 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3002 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3003 /* For FP_REGS no lm/stm is available so this check is triggered
3004 for displacement overflows in b+i+d and b+d like addresses. */
3005 || (reg_classes_intersect_p (FP_REGS, rclass)
3006 && s390_class_max_nregs (FP_REGS, mode) > 1))
3007 {
3008 if (in_p)
3009 sri->icode = (TARGET_64BIT ?
3010 CODE_FOR_reloaddi_nonoffmem_in :
3011 CODE_FOR_reloadsi_nonoffmem_in);
3012 else
3013 sri->icode = (TARGET_64BIT ?
3014 CODE_FOR_reloaddi_nonoffmem_out :
3015 CODE_FOR_reloadsi_nonoffmem_out);
3016 }
3017 }
3018
3019 /* A scratch address register is needed when a symbolic constant is
3020 copied to r0 compiling with -fPIC. In other cases the target
3021 register might be used as temporary (see legitimize_pic_address). */
3022 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3023 sri->icode = (TARGET_64BIT ?
3024 CODE_FOR_reloaddi_PIC_addr :
3025 CODE_FOR_reloadsi_PIC_addr);
3026
3027 /* Either scratch or no register needed. */
3028 return NO_REGS;
3029 }
3030
3031 /* Generate code to load SRC, which is PLUS that is not a
3032 legitimate operand for the LA instruction, into TARGET.
3033 SCRATCH may be used as scratch register. */
3034
3035 void
3036 s390_expand_plus_operand (rtx target, rtx src,
3037 rtx scratch)
3038 {
3039 rtx sum1, sum2;
3040 struct s390_address ad;
3041
3042 /* src must be a PLUS; get its two operands. */
3043 gcc_assert (GET_CODE (src) == PLUS);
3044 gcc_assert (GET_MODE (src) == Pmode);
3045
3046 /* Check if any of the two operands is already scheduled
3047 for replacement by reload. This can happen e.g. when
3048 float registers occur in an address. */
3049 sum1 = find_replacement (&XEXP (src, 0));
3050 sum2 = find_replacement (&XEXP (src, 1));
3051 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3052
3053 /* If the address is already strictly valid, there's nothing to do. */
3054 if (!s390_decompose_address (src, &ad)
3055 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3056 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3057 {
3058 /* Otherwise, one of the operands cannot be an address register;
3059 we reload its value into the scratch register. */
3060 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3061 {
3062 emit_move_insn (scratch, sum1);
3063 sum1 = scratch;
3064 }
3065 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3066 {
3067 emit_move_insn (scratch, sum2);
3068 sum2 = scratch;
3069 }
3070
3071 /* According to the way these invalid addresses are generated
3072 in reload.c, it should never happen (at least on s390) that
3073 *neither* of the PLUS components, after find_replacements
3074 was applied, is an address register. */
3075 if (sum1 == scratch && sum2 == scratch)
3076 {
3077 debug_rtx (src);
3078 gcc_unreachable ();
3079 }
3080
3081 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3082 }
3083
3084 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3085 is only ever performed on addresses, so we can mark the
3086 sum as legitimate for LA in any case. */
3087 s390_load_address (target, src);
3088 }
3089
3090
3091 /* Return true if ADDR is a valid memory address.
3092 STRICT specifies whether strict register checking applies. */
3093
3094 static bool
3095 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3096 {
3097 struct s390_address ad;
3098
3099 if (TARGET_Z10
3100 && larl_operand (addr, VOIDmode)
3101 && (mode == VOIDmode
3102 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3103 return true;
3104
3105 if (!s390_decompose_address (addr, &ad))
3106 return false;
3107
3108 if (strict)
3109 {
3110 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3111 return false;
3112
3113 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3114 return false;
3115 }
3116 else
3117 {
3118 if (ad.base
3119 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3120 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3121 return false;
3122
3123 if (ad.indx
3124 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3125 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3126 return false;
3127 }
3128 return true;
3129 }
3130
3131 /* Return true if OP is a valid operand for the LA instruction.
3132 In 31-bit, we need to prove that the result is used as an
3133 address, as LA performs only a 31-bit addition. */
3134
3135 bool
3136 legitimate_la_operand_p (rtx op)
3137 {
3138 struct s390_address addr;
3139 if (!s390_decompose_address (op, &addr))
3140 return false;
3141
3142 return (TARGET_64BIT || addr.pointer);
3143 }
3144
3145 /* Return true if it is valid *and* preferable to use LA to
3146 compute the sum of OP1 and OP2. */
3147
3148 bool
3149 preferred_la_operand_p (rtx op1, rtx op2)
3150 {
3151 struct s390_address addr;
3152
3153 if (op2 != const0_rtx)
3154 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3155
3156 if (!s390_decompose_address (op1, &addr))
3157 return false;
3158 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3159 return false;
3160 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3161 return false;
3162
3163 if (!TARGET_64BIT && !addr.pointer)
3164 return false;
3165
3166 if (addr.pointer)
3167 return true;
3168
3169 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3170 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3171 return true;
3172
3173 return false;
3174 }
3175
3176 /* Emit a forced load-address operation to load SRC into DST.
3177 This will use the LOAD ADDRESS instruction even in situations
3178 where legitimate_la_operand_p (SRC) returns false. */
3179
3180 void
3181 s390_load_address (rtx dst, rtx src)
3182 {
3183 if (TARGET_64BIT)
3184 emit_move_insn (dst, src);
3185 else
3186 emit_insn (gen_force_la_31 (dst, src));
3187 }
3188
3189 /* Return a legitimate reference for ORIG (an address) using the
3190 register REG. If REG is 0, a new pseudo is generated.
3191
3192 There are two types of references that must be handled:
3193
3194 1. Global data references must load the address from the GOT, via
3195 the PIC reg. An insn is emitted to do this load, and the reg is
3196 returned.
3197
3198 2. Static data references, constant pool addresses, and code labels
3199 compute the address as an offset from the GOT, whose base is in
3200 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3201 differentiate them from global data objects. The returned
3202 address is the PIC reg + an unspec constant.
3203
3204 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3205 reg also appears in the address. */
3206
3207 rtx
3208 legitimize_pic_address (rtx orig, rtx reg)
3209 {
3210 rtx addr = orig;
3211 rtx new_rtx = orig;
3212 rtx base;
3213
3214 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3215
3216 if (GET_CODE (addr) == LABEL_REF
3217 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3218 {
3219 /* This is a local symbol. */
3220 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3221 {
3222 /* Access local symbols PC-relative via LARL.
3223 This is the same as in the non-PIC case, so it is
3224 handled automatically ... */
3225 }
3226 else
3227 {
3228 /* Access local symbols relative to the GOT. */
3229
3230 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3231
3232 if (reload_in_progress || reload_completed)
3233 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3234
3235 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3236 addr = gen_rtx_CONST (Pmode, addr);
3237 addr = force_const_mem (Pmode, addr);
3238 emit_move_insn (temp, addr);
3239
3240 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3241 if (reg != 0)
3242 {
3243 s390_load_address (reg, new_rtx);
3244 new_rtx = reg;
3245 }
3246 }
3247 }
3248 else if (GET_CODE (addr) == SYMBOL_REF)
3249 {
3250 if (reg == 0)
3251 reg = gen_reg_rtx (Pmode);
3252
3253 if (flag_pic == 1)
3254 {
3255 /* Assume GOT offset < 4k. This is handled the same way
3256 in both 31- and 64-bit code (@GOT). */
3257
3258 if (reload_in_progress || reload_completed)
3259 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3260
3261 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3262 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3263 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3264 new_rtx = gen_const_mem (Pmode, new_rtx);
3265 emit_move_insn (reg, new_rtx);
3266 new_rtx = reg;
3267 }
3268 else if (TARGET_CPU_ZARCH)
3269 {
3270 /* If the GOT offset might be >= 4k, we determine the position
3271 of the GOT entry via a PC-relative LARL (@GOTENT). */
3272
3273 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3274
3275 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3276 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3277
3278 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3279 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3280 emit_move_insn (temp, new_rtx);
3281
3282 new_rtx = gen_const_mem (Pmode, temp);
3283 emit_move_insn (reg, new_rtx);
3284 new_rtx = reg;
3285 }
3286 else
3287 {
3288 /* If the GOT offset might be >= 4k, we have to load it
3289 from the literal pool (@GOT). */
3290
3291 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3292
3293 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3294 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3295
3296 if (reload_in_progress || reload_completed)
3297 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3298
3299 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3300 addr = gen_rtx_CONST (Pmode, addr);
3301 addr = force_const_mem (Pmode, addr);
3302 emit_move_insn (temp, addr);
3303
3304 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3305 new_rtx = gen_const_mem (Pmode, new_rtx);
3306 emit_move_insn (reg, new_rtx);
3307 new_rtx = reg;
3308 }
3309 }
3310 else
3311 {
3312 if (GET_CODE (addr) == CONST)
3313 {
3314 addr = XEXP (addr, 0);
3315 if (GET_CODE (addr) == UNSPEC)
3316 {
3317 gcc_assert (XVECLEN (addr, 0) == 1);
3318 switch (XINT (addr, 1))
3319 {
3320 /* If someone moved a GOT-relative UNSPEC
3321 out of the literal pool, force them back in. */
3322 case UNSPEC_GOTOFF:
3323 case UNSPEC_PLTOFF:
3324 new_rtx = force_const_mem (Pmode, orig);
3325 break;
3326
3327 /* @GOT is OK as is if small. */
3328 case UNSPEC_GOT:
3329 if (flag_pic == 2)
3330 new_rtx = force_const_mem (Pmode, orig);
3331 break;
3332
3333 /* @GOTENT is OK as is. */
3334 case UNSPEC_GOTENT:
3335 break;
3336
3337 /* @PLT is OK as is on 64-bit, must be converted to
3338 GOT-relative @PLTOFF on 31-bit. */
3339 case UNSPEC_PLT:
3340 if (!TARGET_CPU_ZARCH)
3341 {
3342 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3343
3344 if (reload_in_progress || reload_completed)
3345 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3346
3347 addr = XVECEXP (addr, 0, 0);
3348 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3349 UNSPEC_PLTOFF);
3350 addr = gen_rtx_CONST (Pmode, addr);
3351 addr = force_const_mem (Pmode, addr);
3352 emit_move_insn (temp, addr);
3353
3354 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3355 if (reg != 0)
3356 {
3357 s390_load_address (reg, new_rtx);
3358 new_rtx = reg;
3359 }
3360 }
3361 break;
3362
3363 /* Everything else cannot happen. */
3364 default:
3365 gcc_unreachable ();
3366 }
3367 }
3368 else
3369 gcc_assert (GET_CODE (addr) == PLUS);
3370 }
3371 if (GET_CODE (addr) == PLUS)
3372 {
3373 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3374
3375 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3376 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3377
3378 /* Check first to see if this is a constant offset
3379 from a local symbol reference. */
3380 if ((GET_CODE (op0) == LABEL_REF
3381 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3382 && GET_CODE (op1) == CONST_INT)
3383 {
3384 if (TARGET_CPU_ZARCH
3385 && larl_operand (op0, VOIDmode)
3386 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3387 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3388 {
3389 if (INTVAL (op1) & 1)
3390 {
3391 /* LARL can't handle odd offsets, so emit a
3392 pair of LARL and LA. */
3393 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3394
3395 if (!DISP_IN_RANGE (INTVAL (op1)))
3396 {
3397 HOST_WIDE_INT even = INTVAL (op1) - 1;
3398 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3399 op0 = gen_rtx_CONST (Pmode, op0);
3400 op1 = const1_rtx;
3401 }
3402
3403 emit_move_insn (temp, op0);
3404 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3405
3406 if (reg != 0)
3407 {
3408 s390_load_address (reg, new_rtx);
3409 new_rtx = reg;
3410 }
3411 }
3412 else
3413 {
3414 /* If the offset is even, we can just use LARL.
3415 This will happen automatically. */
3416 }
3417 }
3418 else
3419 {
3420 /* Access local symbols relative to the GOT. */
3421
3422 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3423
3424 if (reload_in_progress || reload_completed)
3425 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3426
3427 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3428 UNSPEC_GOTOFF);
3429 addr = gen_rtx_PLUS (Pmode, addr, op1);
3430 addr = gen_rtx_CONST (Pmode, addr);
3431 addr = force_const_mem (Pmode, addr);
3432 emit_move_insn (temp, addr);
3433
3434 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3435 if (reg != 0)
3436 {
3437 s390_load_address (reg, new_rtx);
3438 new_rtx = reg;
3439 }
3440 }
3441 }
3442
3443 /* Now, check whether it is a GOT relative symbol plus offset
3444 that was pulled out of the literal pool. Force it back in. */
3445
3446 else if (GET_CODE (op0) == UNSPEC
3447 && GET_CODE (op1) == CONST_INT
3448 && XINT (op0, 1) == UNSPEC_GOTOFF)
3449 {
3450 gcc_assert (XVECLEN (op0, 0) == 1);
3451
3452 new_rtx = force_const_mem (Pmode, orig);
3453 }
3454
3455 /* Otherwise, compute the sum. */
3456 else
3457 {
3458 base = legitimize_pic_address (XEXP (addr, 0), reg);
3459 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3460 base == reg ? NULL_RTX : reg);
3461 if (GET_CODE (new_rtx) == CONST_INT)
3462 new_rtx = plus_constant (base, INTVAL (new_rtx));
3463 else
3464 {
3465 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3466 {
3467 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3468 new_rtx = XEXP (new_rtx, 1);
3469 }
3470 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3471 }
3472
3473 if (GET_CODE (new_rtx) == CONST)
3474 new_rtx = XEXP (new_rtx, 0);
3475 new_rtx = force_operand (new_rtx, 0);
3476 }
3477 }
3478 }
3479 return new_rtx;
3480 }
3481
3482 /* Load the thread pointer into a register. */
3483
3484 rtx
3485 s390_get_thread_pointer (void)
3486 {
3487 rtx tp = gen_reg_rtx (Pmode);
3488
3489 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3490 mark_reg_pointer (tp, BITS_PER_WORD);
3491
3492 return tp;
3493 }
3494
3495 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3496 in s390_tls_symbol which always refers to __tls_get_offset.
3497 The returned offset is written to RESULT_REG and an USE rtx is
3498 generated for TLS_CALL. */
3499
3500 static GTY(()) rtx s390_tls_symbol;
3501
3502 static void
3503 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3504 {
3505 rtx insn;
3506
3507 gcc_assert (flag_pic);
3508
3509 if (!s390_tls_symbol)
3510 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3511
3512 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3513 gen_rtx_REG (Pmode, RETURN_REGNUM));
3514
3515 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3516 RTL_CONST_CALL_P (insn) = 1;
3517 }
3518
3519 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3520 this (thread-local) address. REG may be used as temporary. */
3521
3522 static rtx
3523 legitimize_tls_address (rtx addr, rtx reg)
3524 {
3525 rtx new_rtx, tls_call, temp, base, r2, insn;
3526
3527 if (GET_CODE (addr) == SYMBOL_REF)
3528 switch (tls_symbolic_operand (addr))
3529 {
3530 case TLS_MODEL_GLOBAL_DYNAMIC:
3531 start_sequence ();
3532 r2 = gen_rtx_REG (Pmode, 2);
3533 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3534 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3535 new_rtx = force_const_mem (Pmode, new_rtx);
3536 emit_move_insn (r2, new_rtx);
3537 s390_emit_tls_call_insn (r2, tls_call);
3538 insn = get_insns ();
3539 end_sequence ();
3540
3541 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3542 temp = gen_reg_rtx (Pmode);
3543 emit_libcall_block (insn, temp, r2, new_rtx);
3544
3545 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3546 if (reg != 0)
3547 {
3548 s390_load_address (reg, new_rtx);
3549 new_rtx = reg;
3550 }
3551 break;
3552
3553 case TLS_MODEL_LOCAL_DYNAMIC:
3554 start_sequence ();
3555 r2 = gen_rtx_REG (Pmode, 2);
3556 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3557 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3558 new_rtx = force_const_mem (Pmode, new_rtx);
3559 emit_move_insn (r2, new_rtx);
3560 s390_emit_tls_call_insn (r2, tls_call);
3561 insn = get_insns ();
3562 end_sequence ();
3563
3564 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3565 temp = gen_reg_rtx (Pmode);
3566 emit_libcall_block (insn, temp, r2, new_rtx);
3567
3568 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3569 base = gen_reg_rtx (Pmode);
3570 s390_load_address (base, new_rtx);
3571
3572 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3573 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3574 new_rtx = force_const_mem (Pmode, new_rtx);
3575 temp = gen_reg_rtx (Pmode);
3576 emit_move_insn (temp, new_rtx);
3577
3578 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3579 if (reg != 0)
3580 {
3581 s390_load_address (reg, new_rtx);
3582 new_rtx = reg;
3583 }
3584 break;
3585
3586 case TLS_MODEL_INITIAL_EXEC:
3587 if (flag_pic == 1)
3588 {
3589 /* Assume GOT offset < 4k. This is handled the same way
3590 in both 31- and 64-bit code. */
3591
3592 if (reload_in_progress || reload_completed)
3593 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3594
3595 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3596 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3597 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3598 new_rtx = gen_const_mem (Pmode, new_rtx);
3599 temp = gen_reg_rtx (Pmode);
3600 emit_move_insn (temp, new_rtx);
3601 }
3602 else if (TARGET_CPU_ZARCH)
3603 {
3604 /* If the GOT offset might be >= 4k, we determine the position
3605 of the GOT entry via a PC-relative LARL. */
3606
3607 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3608 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3609 temp = gen_reg_rtx (Pmode);
3610 emit_move_insn (temp, new_rtx);
3611
3612 new_rtx = gen_const_mem (Pmode, temp);
3613 temp = gen_reg_rtx (Pmode);
3614 emit_move_insn (temp, new_rtx);
3615 }
3616 else if (flag_pic)
3617 {
3618 /* If the GOT offset might be >= 4k, we have to load it
3619 from the literal pool. */
3620
3621 if (reload_in_progress || reload_completed)
3622 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3623
3624 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3625 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3626 new_rtx = force_const_mem (Pmode, new_rtx);
3627 temp = gen_reg_rtx (Pmode);
3628 emit_move_insn (temp, new_rtx);
3629
3630 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3631 new_rtx = gen_const_mem (Pmode, new_rtx);
3632
3633 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3634 temp = gen_reg_rtx (Pmode);
3635 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3636 }
3637 else
3638 {
3639 /* In position-dependent code, load the absolute address of
3640 the GOT entry from the literal pool. */
3641
3642 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3643 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3644 new_rtx = force_const_mem (Pmode, new_rtx);
3645 temp = gen_reg_rtx (Pmode);
3646 emit_move_insn (temp, new_rtx);
3647
3648 new_rtx = temp;
3649 new_rtx = gen_const_mem (Pmode, new_rtx);
3650 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3651 temp = gen_reg_rtx (Pmode);
3652 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3653 }
3654
3655 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3656 if (reg != 0)
3657 {
3658 s390_load_address (reg, new_rtx);
3659 new_rtx = reg;
3660 }
3661 break;
3662
3663 case TLS_MODEL_LOCAL_EXEC:
3664 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3665 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3666 new_rtx = force_const_mem (Pmode, new_rtx);
3667 temp = gen_reg_rtx (Pmode);
3668 emit_move_insn (temp, new_rtx);
3669
3670 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3671 if (reg != 0)
3672 {
3673 s390_load_address (reg, new_rtx);
3674 new_rtx = reg;
3675 }
3676 break;
3677
3678 default:
3679 gcc_unreachable ();
3680 }
3681
3682 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3683 {
3684 switch (XINT (XEXP (addr, 0), 1))
3685 {
3686 case UNSPEC_INDNTPOFF:
3687 gcc_assert (TARGET_CPU_ZARCH);
3688 new_rtx = addr;
3689 break;
3690
3691 default:
3692 gcc_unreachable ();
3693 }
3694 }
3695
3696 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3697 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3698 {
3699 new_rtx = XEXP (XEXP (addr, 0), 0);
3700 if (GET_CODE (new_rtx) != SYMBOL_REF)
3701 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3702
3703 new_rtx = legitimize_tls_address (new_rtx, reg);
3704 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3705 new_rtx = force_operand (new_rtx, 0);
3706 }
3707
3708 else
3709 gcc_unreachable (); /* for now ... */
3710
3711 return new_rtx;
3712 }
3713
3714 /* Emit insns making the address in operands[1] valid for a standard
3715 move to operands[0]. operands[1] is replaced by an address which
3716 should be used instead of the former RTX to emit the move
3717 pattern. */
3718
3719 void
3720 emit_symbolic_move (rtx *operands)
3721 {
3722 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3723
3724 if (GET_CODE (operands[0]) == MEM)
3725 operands[1] = force_reg (Pmode, operands[1]);
3726 else if (TLS_SYMBOLIC_CONST (operands[1]))
3727 operands[1] = legitimize_tls_address (operands[1], temp);
3728 else if (flag_pic)
3729 operands[1] = legitimize_pic_address (operands[1], temp);
3730 }
3731
3732 /* Try machine-dependent ways of modifying an illegitimate address X
3733 to be legitimate. If we find one, return the new, valid address.
3734
3735 OLDX is the address as it was before break_out_memory_refs was called.
3736 In some cases it is useful to look at this to decide what needs to be done.
3737
3738 MODE is the mode of the operand pointed to by X.
3739
3740 When -fpic is used, special handling is needed for symbolic references.
3741 See comments by legitimize_pic_address for details. */
3742
3743 static rtx
3744 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3745 enum machine_mode mode ATTRIBUTE_UNUSED)
3746 {
3747 rtx constant_term = const0_rtx;
3748
3749 if (TLS_SYMBOLIC_CONST (x))
3750 {
3751 x = legitimize_tls_address (x, 0);
3752
3753 if (s390_legitimate_address_p (mode, x, FALSE))
3754 return x;
3755 }
3756 else if (GET_CODE (x) == PLUS
3757 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3758 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3759 {
3760 return x;
3761 }
3762 else if (flag_pic)
3763 {
3764 if (SYMBOLIC_CONST (x)
3765 || (GET_CODE (x) == PLUS
3766 && (SYMBOLIC_CONST (XEXP (x, 0))
3767 || SYMBOLIC_CONST (XEXP (x, 1)))))
3768 x = legitimize_pic_address (x, 0);
3769
3770 if (s390_legitimate_address_p (mode, x, FALSE))
3771 return x;
3772 }
3773
3774 x = eliminate_constant_term (x, &constant_term);
3775
3776 /* Optimize loading of large displacements by splitting them
3777 into the multiple of 4K and the rest; this allows the
3778 former to be CSE'd if possible.
3779
3780 Don't do this if the displacement is added to a register
3781 pointing into the stack frame, as the offsets will
3782 change later anyway. */
3783
3784 if (GET_CODE (constant_term) == CONST_INT
3785 && !TARGET_LONG_DISPLACEMENT
3786 && !DISP_IN_RANGE (INTVAL (constant_term))
3787 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3788 {
3789 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3790 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3791
3792 rtx temp = gen_reg_rtx (Pmode);
3793 rtx val = force_operand (GEN_INT (upper), temp);
3794 if (val != temp)
3795 emit_move_insn (temp, val);
3796
3797 x = gen_rtx_PLUS (Pmode, x, temp);
3798 constant_term = GEN_INT (lower);
3799 }
3800
3801 if (GET_CODE (x) == PLUS)
3802 {
3803 if (GET_CODE (XEXP (x, 0)) == REG)
3804 {
3805 rtx temp = gen_reg_rtx (Pmode);
3806 rtx val = force_operand (XEXP (x, 1), temp);
3807 if (val != temp)
3808 emit_move_insn (temp, val);
3809
3810 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3811 }
3812
3813 else if (GET_CODE (XEXP (x, 1)) == REG)
3814 {
3815 rtx temp = gen_reg_rtx (Pmode);
3816 rtx val = force_operand (XEXP (x, 0), temp);
3817 if (val != temp)
3818 emit_move_insn (temp, val);
3819
3820 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3821 }
3822 }
3823
3824 if (constant_term != const0_rtx)
3825 x = gen_rtx_PLUS (Pmode, x, constant_term);
3826
3827 return x;
3828 }
3829
3830 /* Try a machine-dependent way of reloading an illegitimate address AD
3831 operand. If we find one, push the reload and and return the new address.
3832
3833 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3834 and TYPE is the reload type of the current reload. */
3835
3836 rtx
3837 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3838 int opnum, int type)
3839 {
3840 if (!optimize || TARGET_LONG_DISPLACEMENT)
3841 return NULL_RTX;
3842
3843 if (GET_CODE (ad) == PLUS)
3844 {
3845 rtx tem = simplify_binary_operation (PLUS, Pmode,
3846 XEXP (ad, 0), XEXP (ad, 1));
3847 if (tem)
3848 ad = tem;
3849 }
3850
3851 if (GET_CODE (ad) == PLUS
3852 && GET_CODE (XEXP (ad, 0)) == REG
3853 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3854 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3855 {
3856 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3857 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3858 rtx cst, tem, new_rtx;
3859
3860 cst = GEN_INT (upper);
3861 if (!legitimate_reload_constant_p (cst))
3862 cst = force_const_mem (Pmode, cst);
3863
3864 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3865 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3866
3867 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3868 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3869 opnum, (enum reload_type) type);
3870 return new_rtx;
3871 }
3872
3873 return NULL_RTX;
3874 }
3875
3876 /* Emit code to move LEN bytes from DST to SRC. */
3877
3878 void
3879 s390_expand_movmem (rtx dst, rtx src, rtx len)
3880 {
3881 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3882 {
3883 if (INTVAL (len) > 0)
3884 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3885 }
3886
3887 else if (TARGET_MVCLE)
3888 {
3889 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3890 }
3891
3892 else
3893 {
3894 rtx dst_addr, src_addr, count, blocks, temp;
3895 rtx loop_start_label = gen_label_rtx ();
3896 rtx loop_end_label = gen_label_rtx ();
3897 rtx end_label = gen_label_rtx ();
3898 enum machine_mode mode;
3899
3900 mode = GET_MODE (len);
3901 if (mode == VOIDmode)
3902 mode = Pmode;
3903
3904 dst_addr = gen_reg_rtx (Pmode);
3905 src_addr = gen_reg_rtx (Pmode);
3906 count = gen_reg_rtx (mode);
3907 blocks = gen_reg_rtx (mode);
3908
3909 convert_move (count, len, 1);
3910 emit_cmp_and_jump_insns (count, const0_rtx,
3911 EQ, NULL_RTX, mode, 1, end_label);
3912
3913 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3914 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3915 dst = change_address (dst, VOIDmode, dst_addr);
3916 src = change_address (src, VOIDmode, src_addr);
3917
3918 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3919 OPTAB_DIRECT);
3920 if (temp != count)
3921 emit_move_insn (count, temp);
3922
3923 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3924 OPTAB_DIRECT);
3925 if (temp != blocks)
3926 emit_move_insn (blocks, temp);
3927
3928 emit_cmp_and_jump_insns (blocks, const0_rtx,
3929 EQ, NULL_RTX, mode, 1, loop_end_label);
3930
3931 emit_label (loop_start_label);
3932
3933 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3934 s390_load_address (dst_addr,
3935 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3936 s390_load_address (src_addr,
3937 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3938
3939 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
3940 OPTAB_DIRECT);
3941 if (temp != blocks)
3942 emit_move_insn (blocks, temp);
3943
3944 emit_cmp_and_jump_insns (blocks, const0_rtx,
3945 EQ, NULL_RTX, mode, 1, loop_end_label);
3946
3947 emit_jump (loop_start_label);
3948 emit_label (loop_end_label);
3949
3950 emit_insn (gen_movmem_short (dst, src,
3951 convert_to_mode (Pmode, count, 1)));
3952 emit_label (end_label);
3953 }
3954 }
3955
3956 /* Emit code to set LEN bytes at DST to VAL.
3957 Make use of clrmem if VAL is zero. */
3958
3959 void
3960 s390_expand_setmem (rtx dst, rtx len, rtx val)
3961 {
3962 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
3963 return;
3964
3965 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3966
3967 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
3968 {
3969 if (val == const0_rtx && INTVAL (len) <= 256)
3970 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3971 else
3972 {
3973 /* Initialize memory by storing the first byte. */
3974 emit_move_insn (adjust_address (dst, QImode, 0), val);
3975
3976 if (INTVAL (len) > 1)
3977 {
3978 /* Initiate 1 byte overlap move.
3979 The first byte of DST is propagated through DSTP1.
3980 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3981 DST is set to size 1 so the rest of the memory location
3982 does not count as source operand. */
3983 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3984 set_mem_size (dst, const1_rtx);
3985
3986 emit_insn (gen_movmem_short (dstp1, dst,
3987 GEN_INT (INTVAL (len) - 2)));
3988 }
3989 }
3990 }
3991
3992 else if (TARGET_MVCLE)
3993 {
3994 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3995 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3996 }
3997
3998 else
3999 {
4000 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
4001 rtx loop_start_label = gen_label_rtx ();
4002 rtx loop_end_label = gen_label_rtx ();
4003 rtx end_label = gen_label_rtx ();
4004 enum machine_mode mode;
4005
4006 mode = GET_MODE (len);
4007 if (mode == VOIDmode)
4008 mode = Pmode;
4009
4010 dst_addr = gen_reg_rtx (Pmode);
4011 src_addr = gen_reg_rtx (Pmode);
4012 count = gen_reg_rtx (mode);
4013 blocks = gen_reg_rtx (mode);
4014
4015 convert_move (count, len, 1);
4016 emit_cmp_and_jump_insns (count, const0_rtx,
4017 EQ, NULL_RTX, mode, 1, end_label);
4018
4019 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4020 dst = change_address (dst, VOIDmode, dst_addr);
4021
4022 if (val == const0_rtx)
4023 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4024 OPTAB_DIRECT);
4025 else
4026 {
4027 dstp1 = adjust_address (dst, VOIDmode, 1);
4028 set_mem_size (dst, const1_rtx);
4029
4030 /* Initialize memory by storing the first byte. */
4031 emit_move_insn (adjust_address (dst, QImode, 0), val);
4032
4033 /* If count is 1 we are done. */
4034 emit_cmp_and_jump_insns (count, const1_rtx,
4035 EQ, NULL_RTX, mode, 1, end_label);
4036
4037 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4038 OPTAB_DIRECT);
4039 }
4040 if (temp != count)
4041 emit_move_insn (count, temp);
4042
4043 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4044 OPTAB_DIRECT);
4045 if (temp != blocks)
4046 emit_move_insn (blocks, temp);
4047
4048 emit_cmp_and_jump_insns (blocks, const0_rtx,
4049 EQ, NULL_RTX, mode, 1, loop_end_label);
4050
4051 emit_label (loop_start_label);
4052
4053 if (val == const0_rtx)
4054 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4055 else
4056 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4057 s390_load_address (dst_addr,
4058 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4059
4060 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4061 OPTAB_DIRECT);
4062 if (temp != blocks)
4063 emit_move_insn (blocks, temp);
4064
4065 emit_cmp_and_jump_insns (blocks, const0_rtx,
4066 EQ, NULL_RTX, mode, 1, loop_end_label);
4067
4068 emit_jump (loop_start_label);
4069 emit_label (loop_end_label);
4070
4071 if (val == const0_rtx)
4072 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4073 else
4074 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4075 emit_label (end_label);
4076 }
4077 }
4078
4079 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4080 and return the result in TARGET. */
4081
4082 void
4083 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4084 {
4085 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4086 rtx tmp;
4087
4088 /* As the result of CMPINT is inverted compared to what we need,
4089 we have to swap the operands. */
4090 tmp = op0; op0 = op1; op1 = tmp;
4091
4092 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4093 {
4094 if (INTVAL (len) > 0)
4095 {
4096 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4097 emit_insn (gen_cmpint (target, ccreg));
4098 }
4099 else
4100 emit_move_insn (target, const0_rtx);
4101 }
4102 else if (TARGET_MVCLE)
4103 {
4104 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4105 emit_insn (gen_cmpint (target, ccreg));
4106 }
4107 else
4108 {
4109 rtx addr0, addr1, count, blocks, temp;
4110 rtx loop_start_label = gen_label_rtx ();
4111 rtx loop_end_label = gen_label_rtx ();
4112 rtx end_label = gen_label_rtx ();
4113 enum machine_mode mode;
4114
4115 mode = GET_MODE (len);
4116 if (mode == VOIDmode)
4117 mode = Pmode;
4118
4119 addr0 = gen_reg_rtx (Pmode);
4120 addr1 = gen_reg_rtx (Pmode);
4121 count = gen_reg_rtx (mode);
4122 blocks = gen_reg_rtx (mode);
4123
4124 convert_move (count, len, 1);
4125 emit_cmp_and_jump_insns (count, const0_rtx,
4126 EQ, NULL_RTX, mode, 1, end_label);
4127
4128 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4129 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4130 op0 = change_address (op0, VOIDmode, addr0);
4131 op1 = change_address (op1, VOIDmode, addr1);
4132
4133 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4134 OPTAB_DIRECT);
4135 if (temp != count)
4136 emit_move_insn (count, temp);
4137
4138 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4139 OPTAB_DIRECT);
4140 if (temp != blocks)
4141 emit_move_insn (blocks, temp);
4142
4143 emit_cmp_and_jump_insns (blocks, const0_rtx,
4144 EQ, NULL_RTX, mode, 1, loop_end_label);
4145
4146 emit_label (loop_start_label);
4147
4148 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4149 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4150 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4151 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4152 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4153 emit_jump_insn (temp);
4154
4155 s390_load_address (addr0,
4156 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4157 s390_load_address (addr1,
4158 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4159
4160 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4161 OPTAB_DIRECT);
4162 if (temp != blocks)
4163 emit_move_insn (blocks, temp);
4164
4165 emit_cmp_and_jump_insns (blocks, const0_rtx,
4166 EQ, NULL_RTX, mode, 1, loop_end_label);
4167
4168 emit_jump (loop_start_label);
4169 emit_label (loop_end_label);
4170
4171 emit_insn (gen_cmpmem_short (op0, op1,
4172 convert_to_mode (Pmode, count, 1)));
4173 emit_label (end_label);
4174
4175 emit_insn (gen_cmpint (target, ccreg));
4176 }
4177 }
4178
4179
4180 /* Expand conditional increment or decrement using alc/slb instructions.
4181 Should generate code setting DST to either SRC or SRC + INCREMENT,
4182 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4183 Returns true if successful, false otherwise.
4184
4185 That makes it possible to implement some if-constructs without jumps e.g.:
4186 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4187 unsigned int a, b, c;
4188 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4189 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4190 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4191 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4192
4193 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4194 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4195 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4196 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4197 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4198
4199 bool
4200 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4201 rtx dst, rtx src, rtx increment)
4202 {
4203 enum machine_mode cmp_mode;
4204 enum machine_mode cc_mode;
4205 rtx op_res;
4206 rtx insn;
4207 rtvec p;
4208 int ret;
4209
4210 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4211 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4212 cmp_mode = SImode;
4213 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4214 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4215 cmp_mode = DImode;
4216 else
4217 return false;
4218
4219 /* Try ADD LOGICAL WITH CARRY. */
4220 if (increment == const1_rtx)
4221 {
4222 /* Determine CC mode to use. */
4223 if (cmp_code == EQ || cmp_code == NE)
4224 {
4225 if (cmp_op1 != const0_rtx)
4226 {
4227 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4228 NULL_RTX, 0, OPTAB_WIDEN);
4229 cmp_op1 = const0_rtx;
4230 }
4231
4232 cmp_code = cmp_code == EQ ? LEU : GTU;
4233 }
4234
4235 if (cmp_code == LTU || cmp_code == LEU)
4236 {
4237 rtx tem = cmp_op0;
4238 cmp_op0 = cmp_op1;
4239 cmp_op1 = tem;
4240 cmp_code = swap_condition (cmp_code);
4241 }
4242
4243 switch (cmp_code)
4244 {
4245 case GTU:
4246 cc_mode = CCUmode;
4247 break;
4248
4249 case GEU:
4250 cc_mode = CCL3mode;
4251 break;
4252
4253 default:
4254 return false;
4255 }
4256
4257 /* Emit comparison instruction pattern. */
4258 if (!register_operand (cmp_op0, cmp_mode))
4259 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4260
4261 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4262 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4263 /* We use insn_invalid_p here to add clobbers if required. */
4264 ret = insn_invalid_p (emit_insn (insn));
4265 gcc_assert (!ret);
4266
4267 /* Emit ALC instruction pattern. */
4268 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4269 gen_rtx_REG (cc_mode, CC_REGNUM),
4270 const0_rtx);
4271
4272 if (src != const0_rtx)
4273 {
4274 if (!register_operand (src, GET_MODE (dst)))
4275 src = force_reg (GET_MODE (dst), src);
4276
4277 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4278 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4279 }
4280
4281 p = rtvec_alloc (2);
4282 RTVEC_ELT (p, 0) =
4283 gen_rtx_SET (VOIDmode, dst, op_res);
4284 RTVEC_ELT (p, 1) =
4285 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4286 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4287
4288 return true;
4289 }
4290
4291 /* Try SUBTRACT LOGICAL WITH BORROW. */
4292 if (increment == constm1_rtx)
4293 {
4294 /* Determine CC mode to use. */
4295 if (cmp_code == EQ || cmp_code == NE)
4296 {
4297 if (cmp_op1 != const0_rtx)
4298 {
4299 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4300 NULL_RTX, 0, OPTAB_WIDEN);
4301 cmp_op1 = const0_rtx;
4302 }
4303
4304 cmp_code = cmp_code == EQ ? LEU : GTU;
4305 }
4306
4307 if (cmp_code == GTU || cmp_code == GEU)
4308 {
4309 rtx tem = cmp_op0;
4310 cmp_op0 = cmp_op1;
4311 cmp_op1 = tem;
4312 cmp_code = swap_condition (cmp_code);
4313 }
4314
4315 switch (cmp_code)
4316 {
4317 case LEU:
4318 cc_mode = CCUmode;
4319 break;
4320
4321 case LTU:
4322 cc_mode = CCL3mode;
4323 break;
4324
4325 default:
4326 return false;
4327 }
4328
4329 /* Emit comparison instruction pattern. */
4330 if (!register_operand (cmp_op0, cmp_mode))
4331 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4332
4333 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4334 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4335 /* We use insn_invalid_p here to add clobbers if required. */
4336 ret = insn_invalid_p (emit_insn (insn));
4337 gcc_assert (!ret);
4338
4339 /* Emit SLB instruction pattern. */
4340 if (!register_operand (src, GET_MODE (dst)))
4341 src = force_reg (GET_MODE (dst), src);
4342
4343 op_res = gen_rtx_MINUS (GET_MODE (dst),
4344 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4345 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4346 gen_rtx_REG (cc_mode, CC_REGNUM),
4347 const0_rtx));
4348 p = rtvec_alloc (2);
4349 RTVEC_ELT (p, 0) =
4350 gen_rtx_SET (VOIDmode, dst, op_res);
4351 RTVEC_ELT (p, 1) =
4352 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4353 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4354
4355 return true;
4356 }
4357
4358 return false;
4359 }
4360
4361 /* Expand code for the insv template. Return true if successful. */
4362
4363 bool
4364 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4365 {
4366 int bitsize = INTVAL (op1);
4367 int bitpos = INTVAL (op2);
4368
4369 /* On z10 we can use the risbg instruction to implement insv. */
4370 if (TARGET_Z10
4371 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4372 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4373 {
4374 rtx op;
4375 rtx clobber;
4376
4377 op = gen_rtx_SET (GET_MODE(src),
4378 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4379 src);
4380 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4381 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4382
4383 return true;
4384 }
4385
4386 /* We need byte alignment. */
4387 if (bitsize % BITS_PER_UNIT)
4388 return false;
4389
4390 if (bitpos == 0
4391 && memory_operand (dest, VOIDmode)
4392 && (register_operand (src, word_mode)
4393 || const_int_operand (src, VOIDmode)))
4394 {
4395 /* Emit standard pattern if possible. */
4396 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4397 if (GET_MODE_BITSIZE (mode) == bitsize)
4398 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4399
4400 /* (set (ze (mem)) (const_int)). */
4401 else if (const_int_operand (src, VOIDmode))
4402 {
4403 int size = bitsize / BITS_PER_UNIT;
4404 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4405 GET_MODE_SIZE (word_mode) - size);
4406
4407 dest = adjust_address (dest, BLKmode, 0);
4408 set_mem_size (dest, GEN_INT (size));
4409 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4410 }
4411
4412 /* (set (ze (mem)) (reg)). */
4413 else if (register_operand (src, word_mode))
4414 {
4415 if (bitsize <= GET_MODE_BITSIZE (SImode))
4416 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4417 const0_rtx), src);
4418 else
4419 {
4420 /* Emit st,stcmh sequence. */
4421 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4422 int size = stcmh_width / BITS_PER_UNIT;
4423
4424 emit_move_insn (adjust_address (dest, SImode, size),
4425 gen_lowpart (SImode, src));
4426 set_mem_size (dest, GEN_INT (size));
4427 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4428 (stcmh_width), const0_rtx),
4429 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4430 (GET_MODE_BITSIZE (SImode))));
4431 }
4432 }
4433 else
4434 return false;
4435
4436 return true;
4437 }
4438
4439 /* (set (ze (reg)) (const_int)). */
4440 if (TARGET_ZARCH
4441 && register_operand (dest, word_mode)
4442 && (bitpos % 16) == 0
4443 && (bitsize % 16) == 0
4444 && const_int_operand (src, VOIDmode))
4445 {
4446 HOST_WIDE_INT val = INTVAL (src);
4447 int regpos = bitpos + bitsize;
4448
4449 while (regpos > bitpos)
4450 {
4451 enum machine_mode putmode;
4452 int putsize;
4453
4454 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4455 putmode = SImode;
4456 else
4457 putmode = HImode;
4458
4459 putsize = GET_MODE_BITSIZE (putmode);
4460 regpos -= putsize;
4461 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4462 GEN_INT (putsize),
4463 GEN_INT (regpos)),
4464 gen_int_mode (val, putmode));
4465 val >>= putsize;
4466 }
4467 gcc_assert (regpos == bitpos);
4468 return true;
4469 }
4470
4471 return false;
4472 }
4473
4474 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4475 register that holds VAL of mode MODE shifted by COUNT bits. */
4476
4477 static inline rtx
4478 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4479 {
4480 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4481 NULL_RTX, 1, OPTAB_DIRECT);
4482 return expand_simple_binop (SImode, ASHIFT, val, count,
4483 NULL_RTX, 1, OPTAB_DIRECT);
4484 }
4485
4486 /* Structure to hold the initial parameters for a compare_and_swap operation
4487 in HImode and QImode. */
4488
4489 struct alignment_context
4490 {
4491 rtx memsi; /* SI aligned memory location. */
4492 rtx shift; /* Bit offset with regard to lsb. */
4493 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4494 rtx modemaski; /* ~modemask */
4495 bool aligned; /* True if memory is aligned, false else. */
4496 };
4497
4498 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4499 structure AC for transparent simplifying, if the memory alignment is known
4500 to be at least 32bit. MEM is the memory location for the actual operation
4501 and MODE its mode. */
4502
4503 static void
4504 init_alignment_context (struct alignment_context *ac, rtx mem,
4505 enum machine_mode mode)
4506 {
4507 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4508 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4509
4510 if (ac->aligned)
4511 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4512 else
4513 {
4514 /* Alignment is unknown. */
4515 rtx byteoffset, addr, align;
4516
4517 /* Force the address into a register. */
4518 addr = force_reg (Pmode, XEXP (mem, 0));
4519
4520 /* Align it to SImode. */
4521 align = expand_simple_binop (Pmode, AND, addr,
4522 GEN_INT (-GET_MODE_SIZE (SImode)),
4523 NULL_RTX, 1, OPTAB_DIRECT);
4524 /* Generate MEM. */
4525 ac->memsi = gen_rtx_MEM (SImode, align);
4526 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4527 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4528 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4529
4530 /* Calculate shiftcount. */
4531 byteoffset = expand_simple_binop (Pmode, AND, addr,
4532 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4533 NULL_RTX, 1, OPTAB_DIRECT);
4534 /* As we already have some offset, evaluate the remaining distance. */
4535 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4536 NULL_RTX, 1, OPTAB_DIRECT);
4537
4538 }
4539 /* Shift is the byte count, but we need the bitcount. */
4540 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4541 NULL_RTX, 1, OPTAB_DIRECT);
4542 /* Calculate masks. */
4543 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4544 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4545 NULL_RTX, 1, OPTAB_DIRECT);
4546 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4547 }
4548
4549 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4550 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4551 to set if CMP == MEM.
4552 CMP is never in memory for compare_and_swap_cc because
4553 expand_bool_compare_and_swap puts it into a register for later compare. */
4554
4555 void
4556 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4557 {
4558 struct alignment_context ac;
4559 rtx cmpv, newv, val, resv, cc;
4560 rtx res = gen_reg_rtx (SImode);
4561 rtx csloop = gen_label_rtx ();
4562 rtx csend = gen_label_rtx ();
4563
4564 gcc_assert (register_operand (target, VOIDmode));
4565 gcc_assert (MEM_P (mem));
4566
4567 init_alignment_context (&ac, mem, mode);
4568
4569 /* Shift the values to the correct bit positions. */
4570 if (!(ac.aligned && MEM_P (cmp)))
4571 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4572 if (!(ac.aligned && MEM_P (new_rtx)))
4573 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4574
4575 /* Load full word. Subsequent loads are performed by CS. */
4576 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4577 NULL_RTX, 1, OPTAB_DIRECT);
4578
4579 /* Start CS loop. */
4580 emit_label (csloop);
4581 /* val = "<mem>00..0<mem>"
4582 * cmp = "00..0<cmp>00..0"
4583 * new = "00..0<new>00..0"
4584 */
4585
4586 /* Patch cmp and new with val at correct position. */
4587 if (ac.aligned && MEM_P (cmp))
4588 {
4589 cmpv = force_reg (SImode, val);
4590 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4591 }
4592 else
4593 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4594 NULL_RTX, 1, OPTAB_DIRECT));
4595 if (ac.aligned && MEM_P (new_rtx))
4596 {
4597 newv = force_reg (SImode, val);
4598 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4599 }
4600 else
4601 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4602 NULL_RTX, 1, OPTAB_DIRECT));
4603
4604 /* Jump to end if we're done (likely?). */
4605 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4606 cmpv, newv));
4607
4608 /* Check for changes outside mode. */
4609 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4610 NULL_RTX, 1, OPTAB_DIRECT);
4611 cc = s390_emit_compare (NE, resv, val);
4612 emit_move_insn (val, resv);
4613 /* Loop internal if so. */
4614 s390_emit_jump (csloop, cc);
4615
4616 emit_label (csend);
4617
4618 /* Return the correct part of the bitfield. */
4619 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4620 NULL_RTX, 1, OPTAB_DIRECT), 1);
4621 }
4622
4623 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4624 and VAL the value to play with. If AFTER is true then store the value
4625 MEM holds after the operation, if AFTER is false then store the value MEM
4626 holds before the operation. If TARGET is zero then discard that value, else
4627 store it to TARGET. */
4628
4629 void
4630 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4631 rtx target, rtx mem, rtx val, bool after)
4632 {
4633 struct alignment_context ac;
4634 rtx cmp;
4635 rtx new_rtx = gen_reg_rtx (SImode);
4636 rtx orig = gen_reg_rtx (SImode);
4637 rtx csloop = gen_label_rtx ();
4638
4639 gcc_assert (!target || register_operand (target, VOIDmode));
4640 gcc_assert (MEM_P (mem));
4641
4642 init_alignment_context (&ac, mem, mode);
4643
4644 /* Shift val to the correct bit positions.
4645 Preserve "icm", but prevent "ex icm". */
4646 if (!(ac.aligned && code == SET && MEM_P (val)))
4647 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4648
4649 /* Further preparation insns. */
4650 if (code == PLUS || code == MINUS)
4651 emit_move_insn (orig, val);
4652 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4653 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4654 NULL_RTX, 1, OPTAB_DIRECT);
4655
4656 /* Load full word. Subsequent loads are performed by CS. */
4657 cmp = force_reg (SImode, ac.memsi);
4658
4659 /* Start CS loop. */
4660 emit_label (csloop);
4661 emit_move_insn (new_rtx, cmp);
4662
4663 /* Patch new with val at correct position. */
4664 switch (code)
4665 {
4666 case PLUS:
4667 case MINUS:
4668 val = expand_simple_binop (SImode, code, new_rtx, orig,
4669 NULL_RTX, 1, OPTAB_DIRECT);
4670 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4671 NULL_RTX, 1, OPTAB_DIRECT);
4672 /* FALLTHRU */
4673 case SET:
4674 if (ac.aligned && MEM_P (val))
4675 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4676 else
4677 {
4678 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4679 NULL_RTX, 1, OPTAB_DIRECT);
4680 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4681 NULL_RTX, 1, OPTAB_DIRECT);
4682 }
4683 break;
4684 case AND:
4685 case IOR:
4686 case XOR:
4687 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4688 NULL_RTX, 1, OPTAB_DIRECT);
4689 break;
4690 case MULT: /* NAND */
4691 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4692 NULL_RTX, 1, OPTAB_DIRECT);
4693 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4694 NULL_RTX, 1, OPTAB_DIRECT);
4695 break;
4696 default:
4697 gcc_unreachable ();
4698 }
4699
4700 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4701 ac.memsi, cmp, new_rtx));
4702
4703 /* Return the correct part of the bitfield. */
4704 if (target)
4705 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4706 after ? new_rtx : cmp, ac.shift,
4707 NULL_RTX, 1, OPTAB_DIRECT), 1);
4708 }
4709
4710 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4711 We need to emit DTP-relative relocations. */
4712
4713 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4714
4715 static void
4716 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4717 {
4718 switch (size)
4719 {
4720 case 4:
4721 fputs ("\t.long\t", file);
4722 break;
4723 case 8:
4724 fputs ("\t.quad\t", file);
4725 break;
4726 default:
4727 gcc_unreachable ();
4728 }
4729 output_addr_const (file, x);
4730 fputs ("@DTPOFF", file);
4731 }
4732
4733 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4734 /* Implement TARGET_MANGLE_TYPE. */
4735
4736 static const char *
4737 s390_mangle_type (const_tree type)
4738 {
4739 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4740 && TARGET_LONG_DOUBLE_128)
4741 return "g";
4742
4743 /* For all other types, use normal C++ mangling. */
4744 return NULL;
4745 }
4746 #endif
4747
4748 /* In the name of slightly smaller debug output, and to cater to
4749 general assembler lossage, recognize various UNSPEC sequences
4750 and turn them back into a direct symbol reference. */
4751
4752 static rtx
4753 s390_delegitimize_address (rtx orig_x)
4754 {
4755 rtx x = orig_x, y;
4756
4757 if (GET_CODE (x) != MEM)
4758 return orig_x;
4759
4760 x = XEXP (x, 0);
4761 if (GET_CODE (x) == PLUS
4762 && GET_CODE (XEXP (x, 1)) == CONST
4763 && GET_CODE (XEXP (x, 0)) == REG
4764 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4765 {
4766 y = XEXP (XEXP (x, 1), 0);
4767 if (GET_CODE (y) == UNSPEC
4768 && XINT (y, 1) == UNSPEC_GOT)
4769 return XVECEXP (y, 0, 0);
4770 return orig_x;
4771 }
4772
4773 if (GET_CODE (x) == CONST)
4774 {
4775 y = XEXP (x, 0);
4776 if (GET_CODE (y) == UNSPEC
4777 && XINT (y, 1) == UNSPEC_GOTENT)
4778 return XVECEXP (y, 0, 0);
4779 return orig_x;
4780 }
4781
4782 return orig_x;
4783 }
4784
4785 /* Output operand OP to stdio stream FILE.
4786 OP is an address (register + offset) which is not used to address data;
4787 instead the rightmost bits are interpreted as the value. */
4788
4789 static void
4790 print_shift_count_operand (FILE *file, rtx op)
4791 {
4792 HOST_WIDE_INT offset;
4793 rtx base;
4794
4795 /* Extract base register and offset. */
4796 if (!s390_decompose_shift_count (op, &base, &offset))
4797 gcc_unreachable ();
4798
4799 /* Sanity check. */
4800 if (base)
4801 {
4802 gcc_assert (GET_CODE (base) == REG);
4803 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4804 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4805 }
4806
4807 /* Offsets are constricted to twelve bits. */
4808 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4809 if (base)
4810 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4811 }
4812
4813 /* See 'get_some_local_dynamic_name'. */
4814
4815 static int
4816 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4817 {
4818 rtx x = *px;
4819
4820 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4821 {
4822 x = get_pool_constant (x);
4823 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4824 }
4825
4826 if (GET_CODE (x) == SYMBOL_REF
4827 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4828 {
4829 cfun->machine->some_ld_name = XSTR (x, 0);
4830 return 1;
4831 }
4832
4833 return 0;
4834 }
4835
4836 /* Locate some local-dynamic symbol still in use by this function
4837 so that we can print its name in local-dynamic base patterns. */
4838
4839 static const char *
4840 get_some_local_dynamic_name (void)
4841 {
4842 rtx insn;
4843
4844 if (cfun->machine->some_ld_name)
4845 return cfun->machine->some_ld_name;
4846
4847 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4848 if (INSN_P (insn)
4849 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4850 return cfun->machine->some_ld_name;
4851
4852 gcc_unreachable ();
4853 }
4854
4855 /* Output machine-dependent UNSPECs occurring in address constant X
4856 in assembler syntax to stdio stream FILE. Returns true if the
4857 constant X could be recognized, false otherwise. */
4858
4859 bool
4860 s390_output_addr_const_extra (FILE *file, rtx x)
4861 {
4862 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4863 switch (XINT (x, 1))
4864 {
4865 case UNSPEC_GOTENT:
4866 output_addr_const (file, XVECEXP (x, 0, 0));
4867 fprintf (file, "@GOTENT");
4868 return true;
4869 case UNSPEC_GOT:
4870 output_addr_const (file, XVECEXP (x, 0, 0));
4871 fprintf (file, "@GOT");
4872 return true;
4873 case UNSPEC_GOTOFF:
4874 output_addr_const (file, XVECEXP (x, 0, 0));
4875 fprintf (file, "@GOTOFF");
4876 return true;
4877 case UNSPEC_PLT:
4878 output_addr_const (file, XVECEXP (x, 0, 0));
4879 fprintf (file, "@PLT");
4880 return true;
4881 case UNSPEC_PLTOFF:
4882 output_addr_const (file, XVECEXP (x, 0, 0));
4883 fprintf (file, "@PLTOFF");
4884 return true;
4885 case UNSPEC_TLSGD:
4886 output_addr_const (file, XVECEXP (x, 0, 0));
4887 fprintf (file, "@TLSGD");
4888 return true;
4889 case UNSPEC_TLSLDM:
4890 assemble_name (file, get_some_local_dynamic_name ());
4891 fprintf (file, "@TLSLDM");
4892 return true;
4893 case UNSPEC_DTPOFF:
4894 output_addr_const (file, XVECEXP (x, 0, 0));
4895 fprintf (file, "@DTPOFF");
4896 return true;
4897 case UNSPEC_NTPOFF:
4898 output_addr_const (file, XVECEXP (x, 0, 0));
4899 fprintf (file, "@NTPOFF");
4900 return true;
4901 case UNSPEC_GOTNTPOFF:
4902 output_addr_const (file, XVECEXP (x, 0, 0));
4903 fprintf (file, "@GOTNTPOFF");
4904 return true;
4905 case UNSPEC_INDNTPOFF:
4906 output_addr_const (file, XVECEXP (x, 0, 0));
4907 fprintf (file, "@INDNTPOFF");
4908 return true;
4909 }
4910
4911 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
4912 switch (XINT (x, 1))
4913 {
4914 case UNSPEC_POOL_OFFSET:
4915 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
4916 output_addr_const (file, x);
4917 return true;
4918 }
4919 return false;
4920 }
4921
4922 /* Output address operand ADDR in assembler syntax to
4923 stdio stream FILE. */
4924
4925 void
4926 print_operand_address (FILE *file, rtx addr)
4927 {
4928 struct s390_address ad;
4929
4930 if (s390_symref_operand_p (addr, NULL, NULL))
4931 {
4932 gcc_assert (TARGET_Z10);
4933 output_addr_const (file, addr);
4934 return;
4935 }
4936
4937 if (!s390_decompose_address (addr, &ad)
4938 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4939 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4940 output_operand_lossage ("cannot decompose address");
4941
4942 if (ad.disp)
4943 output_addr_const (file, ad.disp);
4944 else
4945 fprintf (file, "0");
4946
4947 if (ad.base && ad.indx)
4948 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4949 reg_names[REGNO (ad.base)]);
4950 else if (ad.base)
4951 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4952 }
4953
4954 /* Output operand X in assembler syntax to stdio stream FILE.
4955 CODE specified the format flag. The following format flags
4956 are recognized:
4957
4958 'C': print opcode suffix for branch condition.
4959 'D': print opcode suffix for inverse branch condition.
4960 'E': print opcode suffix for branch on index instruction.
4961 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4962 'G': print the size of the operand in bytes.
4963 'O': print only the displacement of a memory reference.
4964 'R': print only the base register of a memory reference.
4965 'S': print S-type memory reference (base+displacement).
4966 'N': print the second word of a DImode operand.
4967 'M': print the second word of a TImode operand.
4968 'Y': print shift count operand.
4969
4970 'b': print integer X as if it's an unsigned byte.
4971 'c': print integer X as if it's an signed byte.
4972 'x': print integer X as if it's an unsigned halfword.
4973 'h': print integer X as if it's a signed halfword.
4974 'i': print the first nonzero HImode part of X.
4975 'j': print the first HImode part unequal to -1 of X.
4976 'k': print the first nonzero SImode part of X.
4977 'm': print the first SImode part unequal to -1 of X.
4978 'o': print integer X as if it's an unsigned 32bit word. */
4979
4980 void
4981 print_operand (FILE *file, rtx x, int code)
4982 {
4983 switch (code)
4984 {
4985 case 'C':
4986 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4987 return;
4988
4989 case 'D':
4990 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4991 return;
4992
4993 case 'E':
4994 if (GET_CODE (x) == LE)
4995 fprintf (file, "l");
4996 else if (GET_CODE (x) == GT)
4997 fprintf (file, "h");
4998 else
4999 gcc_unreachable ();
5000 return;
5001
5002 case 'J':
5003 if (GET_CODE (x) == SYMBOL_REF)
5004 {
5005 fprintf (file, "%s", ":tls_load:");
5006 output_addr_const (file, x);
5007 }
5008 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5009 {
5010 fprintf (file, "%s", ":tls_gdcall:");
5011 output_addr_const (file, XVECEXP (x, 0, 0));
5012 }
5013 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5014 {
5015 fprintf (file, "%s", ":tls_ldcall:");
5016 assemble_name (file, get_some_local_dynamic_name ());
5017 }
5018 else
5019 gcc_unreachable ();
5020 return;
5021
5022 case 'G':
5023 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5024 return;
5025
5026 case 'O':
5027 {
5028 struct s390_address ad;
5029 int ret;
5030
5031 gcc_assert (GET_CODE (x) == MEM);
5032 ret = s390_decompose_address (XEXP (x, 0), &ad);
5033 gcc_assert (ret);
5034 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5035 gcc_assert (!ad.indx);
5036
5037 if (ad.disp)
5038 output_addr_const (file, ad.disp);
5039 else
5040 fprintf (file, "0");
5041 }
5042 return;
5043
5044 case 'R':
5045 {
5046 struct s390_address ad;
5047 int ret;
5048
5049 gcc_assert (GET_CODE (x) == MEM);
5050 ret = s390_decompose_address (XEXP (x, 0), &ad);
5051 gcc_assert (ret);
5052 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5053 gcc_assert (!ad.indx);
5054
5055 if (ad.base)
5056 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5057 else
5058 fprintf (file, "0");
5059 }
5060 return;
5061
5062 case 'S':
5063 {
5064 struct s390_address ad;
5065 int ret;
5066
5067 gcc_assert (GET_CODE (x) == MEM);
5068 ret = s390_decompose_address (XEXP (x, 0), &ad);
5069 gcc_assert (ret);
5070 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5071 gcc_assert (!ad.indx);
5072
5073 if (ad.disp)
5074 output_addr_const (file, ad.disp);
5075 else
5076 fprintf (file, "0");
5077
5078 if (ad.base)
5079 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5080 }
5081 return;
5082
5083 case 'N':
5084 if (GET_CODE (x) == REG)
5085 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5086 else if (GET_CODE (x) == MEM)
5087 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5088 else
5089 gcc_unreachable ();
5090 break;
5091
5092 case 'M':
5093 if (GET_CODE (x) == REG)
5094 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5095 else if (GET_CODE (x) == MEM)
5096 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5097 else
5098 gcc_unreachable ();
5099 break;
5100
5101 case 'Y':
5102 print_shift_count_operand (file, x);
5103 return;
5104 }
5105
5106 switch (GET_CODE (x))
5107 {
5108 case REG:
5109 fprintf (file, "%s", reg_names[REGNO (x)]);
5110 break;
5111
5112 case MEM:
5113 output_address (XEXP (x, 0));
5114 break;
5115
5116 case CONST:
5117 case CODE_LABEL:
5118 case LABEL_REF:
5119 case SYMBOL_REF:
5120 output_addr_const (file, x);
5121 break;
5122
5123 case CONST_INT:
5124 if (code == 'b')
5125 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5126 else if (code == 'c')
5127 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5128 else if (code == 'x')
5129 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5130 else if (code == 'h')
5131 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5132 else if (code == 'i')
5133 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5134 s390_extract_part (x, HImode, 0));
5135 else if (code == 'j')
5136 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5137 s390_extract_part (x, HImode, -1));
5138 else if (code == 'k')
5139 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5140 s390_extract_part (x, SImode, 0));
5141 else if (code == 'm')
5142 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5143 s390_extract_part (x, SImode, -1));
5144 else if (code == 'o')
5145 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5146 else
5147 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5148 break;
5149
5150 case CONST_DOUBLE:
5151 gcc_assert (GET_MODE (x) == VOIDmode);
5152 if (code == 'b')
5153 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5154 else if (code == 'x')
5155 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5156 else if (code == 'h')
5157 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5158 else
5159 gcc_unreachable ();
5160 break;
5161
5162 default:
5163 fatal_insn ("UNKNOWN in print_operand !?", x);
5164 break;
5165 }
5166 }
5167
5168 /* Target hook for assembling integer objects. We need to define it
5169 here to work a round a bug in some versions of GAS, which couldn't
5170 handle values smaller than INT_MIN when printed in decimal. */
5171
5172 static bool
5173 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5174 {
5175 if (size == 8 && aligned_p
5176 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5177 {
5178 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5179 INTVAL (x));
5180 return true;
5181 }
5182 return default_assemble_integer (x, size, aligned_p);
5183 }
5184
5185 /* Returns true if register REGNO is used for forming
5186 a memory address in expression X. */
5187
5188 static bool
5189 reg_used_in_mem_p (int regno, rtx x)
5190 {
5191 enum rtx_code code = GET_CODE (x);
5192 int i, j;
5193 const char *fmt;
5194
5195 if (code == MEM)
5196 {
5197 if (refers_to_regno_p (regno, regno+1,
5198 XEXP (x, 0), 0))
5199 return true;
5200 }
5201 else if (code == SET
5202 && GET_CODE (SET_DEST (x)) == PC)
5203 {
5204 if (refers_to_regno_p (regno, regno+1,
5205 SET_SRC (x), 0))
5206 return true;
5207 }
5208
5209 fmt = GET_RTX_FORMAT (code);
5210 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5211 {
5212 if (fmt[i] == 'e'
5213 && reg_used_in_mem_p (regno, XEXP (x, i)))
5214 return true;
5215
5216 else if (fmt[i] == 'E')
5217 for (j = 0; j < XVECLEN (x, i); j++)
5218 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5219 return true;
5220 }
5221 return false;
5222 }
5223
5224 /* Returns true if expression DEP_RTX sets an address register
5225 used by instruction INSN to address memory. */
5226
5227 static bool
5228 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5229 {
5230 rtx target, pat;
5231
5232 if (GET_CODE (dep_rtx) == INSN)
5233 dep_rtx = PATTERN (dep_rtx);
5234
5235 if (GET_CODE (dep_rtx) == SET)
5236 {
5237 target = SET_DEST (dep_rtx);
5238 if (GET_CODE (target) == STRICT_LOW_PART)
5239 target = XEXP (target, 0);
5240 while (GET_CODE (target) == SUBREG)
5241 target = SUBREG_REG (target);
5242
5243 if (GET_CODE (target) == REG)
5244 {
5245 int regno = REGNO (target);
5246
5247 if (s390_safe_attr_type (insn) == TYPE_LA)
5248 {
5249 pat = PATTERN (insn);
5250 if (GET_CODE (pat) == PARALLEL)
5251 {
5252 gcc_assert (XVECLEN (pat, 0) == 2);
5253 pat = XVECEXP (pat, 0, 0);
5254 }
5255 gcc_assert (GET_CODE (pat) == SET);
5256 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5257 }
5258 else if (get_attr_atype (insn) == ATYPE_AGEN)
5259 return reg_used_in_mem_p (regno, PATTERN (insn));
5260 }
5261 }
5262 return false;
5263 }
5264
5265 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5266
5267 int
5268 s390_agen_dep_p (rtx dep_insn, rtx insn)
5269 {
5270 rtx dep_rtx = PATTERN (dep_insn);
5271 int i;
5272
5273 if (GET_CODE (dep_rtx) == SET
5274 && addr_generation_dependency_p (dep_rtx, insn))
5275 return 1;
5276 else if (GET_CODE (dep_rtx) == PARALLEL)
5277 {
5278 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5279 {
5280 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5281 return 1;
5282 }
5283 }
5284 return 0;
5285 }
5286
5287
5288 /* A C statement (sans semicolon) to update the integer scheduling priority
5289 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5290 reduce the priority to execute INSN later. Do not define this macro if
5291 you do not need to adjust the scheduling priorities of insns.
5292
5293 A STD instruction should be scheduled earlier,
5294 in order to use the bypass. */
5295
5296 static int
5297 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5298 {
5299 if (! INSN_P (insn))
5300 return priority;
5301
5302 if (s390_tune != PROCESSOR_2084_Z990
5303 && s390_tune != PROCESSOR_2094_Z9_109)
5304 return priority;
5305
5306 switch (s390_safe_attr_type (insn))
5307 {
5308 case TYPE_FSTOREDF:
5309 case TYPE_FSTORESF:
5310 priority = priority << 3;
5311 break;
5312 case TYPE_STORE:
5313 case TYPE_STM:
5314 priority = priority << 1;
5315 break;
5316 default:
5317 break;
5318 }
5319 return priority;
5320 }
5321
5322 /* The number of instructions that can be issued per cycle. */
5323
5324 static int
5325 s390_issue_rate (void)
5326 {
5327 switch (s390_tune)
5328 {
5329 case PROCESSOR_2084_Z990:
5330 case PROCESSOR_2094_Z9_109:
5331 return 3;
5332 case PROCESSOR_2097_Z10:
5333 return 2;
5334 default:
5335 return 1;
5336 }
5337 }
5338
5339 static int
5340 s390_first_cycle_multipass_dfa_lookahead (void)
5341 {
5342 return 4;
5343 }
5344
5345
5346 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5347 Fix up MEMs as required. */
5348
5349 static void
5350 annotate_constant_pool_refs (rtx *x)
5351 {
5352 int i, j;
5353 const char *fmt;
5354
5355 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5356 || !CONSTANT_POOL_ADDRESS_P (*x));
5357
5358 /* Literal pool references can only occur inside a MEM ... */
5359 if (GET_CODE (*x) == MEM)
5360 {
5361 rtx memref = XEXP (*x, 0);
5362
5363 if (GET_CODE (memref) == SYMBOL_REF
5364 && CONSTANT_POOL_ADDRESS_P (memref))
5365 {
5366 rtx base = cfun->machine->base_reg;
5367 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5368 UNSPEC_LTREF);
5369
5370 *x = replace_equiv_address (*x, addr);
5371 return;
5372 }
5373
5374 if (GET_CODE (memref) == CONST
5375 && GET_CODE (XEXP (memref, 0)) == PLUS
5376 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5377 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5378 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5379 {
5380 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5381 rtx sym = XEXP (XEXP (memref, 0), 0);
5382 rtx base = cfun->machine->base_reg;
5383 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5384 UNSPEC_LTREF);
5385
5386 *x = replace_equiv_address (*x, plus_constant (addr, off));
5387 return;
5388 }
5389 }
5390
5391 /* ... or a load-address type pattern. */
5392 if (GET_CODE (*x) == SET)
5393 {
5394 rtx addrref = SET_SRC (*x);
5395
5396 if (GET_CODE (addrref) == SYMBOL_REF
5397 && CONSTANT_POOL_ADDRESS_P (addrref))
5398 {
5399 rtx base = cfun->machine->base_reg;
5400 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5401 UNSPEC_LTREF);
5402
5403 SET_SRC (*x) = addr;
5404 return;
5405 }
5406
5407 if (GET_CODE (addrref) == CONST
5408 && GET_CODE (XEXP (addrref, 0)) == PLUS
5409 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5410 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5411 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5412 {
5413 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5414 rtx sym = XEXP (XEXP (addrref, 0), 0);
5415 rtx base = cfun->machine->base_reg;
5416 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5417 UNSPEC_LTREF);
5418
5419 SET_SRC (*x) = plus_constant (addr, off);
5420 return;
5421 }
5422 }
5423
5424 /* Annotate LTREL_BASE as well. */
5425 if (GET_CODE (*x) == UNSPEC
5426 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5427 {
5428 rtx base = cfun->machine->base_reg;
5429 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5430 UNSPEC_LTREL_BASE);
5431 return;
5432 }
5433
5434 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5435 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5436 {
5437 if (fmt[i] == 'e')
5438 {
5439 annotate_constant_pool_refs (&XEXP (*x, i));
5440 }
5441 else if (fmt[i] == 'E')
5442 {
5443 for (j = 0; j < XVECLEN (*x, i); j++)
5444 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5445 }
5446 }
5447 }
5448
5449 /* Split all branches that exceed the maximum distance.
5450 Returns true if this created a new literal pool entry. */
5451
5452 static int
5453 s390_split_branches (void)
5454 {
5455 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5456 int new_literal = 0, ret;
5457 rtx insn, pat, tmp, target;
5458 rtx *label;
5459
5460 /* We need correct insn addresses. */
5461
5462 shorten_branches (get_insns ());
5463
5464 /* Find all branches that exceed 64KB, and split them. */
5465
5466 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5467 {
5468 if (GET_CODE (insn) != JUMP_INSN)
5469 continue;
5470
5471 pat = PATTERN (insn);
5472 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5473 pat = XVECEXP (pat, 0, 0);
5474 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5475 continue;
5476
5477 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5478 {
5479 label = &SET_SRC (pat);
5480 }
5481 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5482 {
5483 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5484 label = &XEXP (SET_SRC (pat), 1);
5485 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5486 label = &XEXP (SET_SRC (pat), 2);
5487 else
5488 continue;
5489 }
5490 else
5491 continue;
5492
5493 if (get_attr_length (insn) <= 4)
5494 continue;
5495
5496 /* We are going to use the return register as scratch register,
5497 make sure it will be saved/restored by the prologue/epilogue. */
5498 cfun_frame_layout.save_return_addr_p = 1;
5499
5500 if (!flag_pic)
5501 {
5502 new_literal = 1;
5503 tmp = force_const_mem (Pmode, *label);
5504 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5505 INSN_ADDRESSES_NEW (tmp, -1);
5506 annotate_constant_pool_refs (&PATTERN (tmp));
5507
5508 target = temp_reg;
5509 }
5510 else
5511 {
5512 new_literal = 1;
5513 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5514 UNSPEC_LTREL_OFFSET);
5515 target = gen_rtx_CONST (Pmode, target);
5516 target = force_const_mem (Pmode, target);
5517 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5518 INSN_ADDRESSES_NEW (tmp, -1);
5519 annotate_constant_pool_refs (&PATTERN (tmp));
5520
5521 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5522 cfun->machine->base_reg),
5523 UNSPEC_LTREL_BASE);
5524 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5525 }
5526
5527 ret = validate_change (insn, label, target, 0);
5528 gcc_assert (ret);
5529 }
5530
5531 return new_literal;
5532 }
5533
5534
5535 /* Find an annotated literal pool symbol referenced in RTX X,
5536 and store it at REF. Will abort if X contains references to
5537 more than one such pool symbol; multiple references to the same
5538 symbol are allowed, however.
5539
5540 The rtx pointed to by REF must be initialized to NULL_RTX
5541 by the caller before calling this routine. */
5542
5543 static void
5544 find_constant_pool_ref (rtx x, rtx *ref)
5545 {
5546 int i, j;
5547 const char *fmt;
5548
5549 /* Ignore LTREL_BASE references. */
5550 if (GET_CODE (x) == UNSPEC
5551 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5552 return;
5553 /* Likewise POOL_ENTRY insns. */
5554 if (GET_CODE (x) == UNSPEC_VOLATILE
5555 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5556 return;
5557
5558 gcc_assert (GET_CODE (x) != SYMBOL_REF
5559 || !CONSTANT_POOL_ADDRESS_P (x));
5560
5561 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5562 {
5563 rtx sym = XVECEXP (x, 0, 0);
5564 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5565 && CONSTANT_POOL_ADDRESS_P (sym));
5566
5567 if (*ref == NULL_RTX)
5568 *ref = sym;
5569 else
5570 gcc_assert (*ref == sym);
5571
5572 return;
5573 }
5574
5575 fmt = GET_RTX_FORMAT (GET_CODE (x));
5576 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5577 {
5578 if (fmt[i] == 'e')
5579 {
5580 find_constant_pool_ref (XEXP (x, i), ref);
5581 }
5582 else if (fmt[i] == 'E')
5583 {
5584 for (j = 0; j < XVECLEN (x, i); j++)
5585 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5586 }
5587 }
5588 }
5589
5590 /* Replace every reference to the annotated literal pool
5591 symbol REF in X by its base plus OFFSET. */
5592
5593 static void
5594 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5595 {
5596 int i, j;
5597 const char *fmt;
5598
5599 gcc_assert (*x != ref);
5600
5601 if (GET_CODE (*x) == UNSPEC
5602 && XINT (*x, 1) == UNSPEC_LTREF
5603 && XVECEXP (*x, 0, 0) == ref)
5604 {
5605 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5606 return;
5607 }
5608
5609 if (GET_CODE (*x) == PLUS
5610 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5611 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5612 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5613 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5614 {
5615 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5616 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5617 return;
5618 }
5619
5620 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5621 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5622 {
5623 if (fmt[i] == 'e')
5624 {
5625 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5626 }
5627 else if (fmt[i] == 'E')
5628 {
5629 for (j = 0; j < XVECLEN (*x, i); j++)
5630 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5631 }
5632 }
5633 }
5634
5635 /* Check whether X contains an UNSPEC_LTREL_BASE.
5636 Return its constant pool symbol if found, NULL_RTX otherwise. */
5637
5638 static rtx
5639 find_ltrel_base (rtx x)
5640 {
5641 int i, j;
5642 const char *fmt;
5643
5644 if (GET_CODE (x) == UNSPEC
5645 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5646 return XVECEXP (x, 0, 0);
5647
5648 fmt = GET_RTX_FORMAT (GET_CODE (x));
5649 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5650 {
5651 if (fmt[i] == 'e')
5652 {
5653 rtx fnd = find_ltrel_base (XEXP (x, i));
5654 if (fnd)
5655 return fnd;
5656 }
5657 else if (fmt[i] == 'E')
5658 {
5659 for (j = 0; j < XVECLEN (x, i); j++)
5660 {
5661 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5662 if (fnd)
5663 return fnd;
5664 }
5665 }
5666 }
5667
5668 return NULL_RTX;
5669 }
5670
5671 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5672
5673 static void
5674 replace_ltrel_base (rtx *x)
5675 {
5676 int i, j;
5677 const char *fmt;
5678
5679 if (GET_CODE (*x) == UNSPEC
5680 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5681 {
5682 *x = XVECEXP (*x, 0, 1);
5683 return;
5684 }
5685
5686 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5687 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5688 {
5689 if (fmt[i] == 'e')
5690 {
5691 replace_ltrel_base (&XEXP (*x, i));
5692 }
5693 else if (fmt[i] == 'E')
5694 {
5695 for (j = 0; j < XVECLEN (*x, i); j++)
5696 replace_ltrel_base (&XVECEXP (*x, i, j));
5697 }
5698 }
5699 }
5700
5701
5702 /* We keep a list of constants which we have to add to internal
5703 constant tables in the middle of large functions. */
5704
5705 #define NR_C_MODES 11
5706 enum machine_mode constant_modes[NR_C_MODES] =
5707 {
5708 TFmode, TImode, TDmode,
5709 DFmode, DImode, DDmode,
5710 SFmode, SImode, SDmode,
5711 HImode,
5712 QImode
5713 };
5714
5715 struct constant
5716 {
5717 struct constant *next;
5718 rtx value;
5719 rtx label;
5720 };
5721
5722 struct constant_pool
5723 {
5724 struct constant_pool *next;
5725 rtx first_insn;
5726 rtx pool_insn;
5727 bitmap insns;
5728 rtx emit_pool_after;
5729
5730 struct constant *constants[NR_C_MODES];
5731 struct constant *execute;
5732 rtx label;
5733 int size;
5734 };
5735
5736 /* Allocate new constant_pool structure. */
5737
5738 static struct constant_pool *
5739 s390_alloc_pool (void)
5740 {
5741 struct constant_pool *pool;
5742 int i;
5743
5744 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5745 pool->next = NULL;
5746 for (i = 0; i < NR_C_MODES; i++)
5747 pool->constants[i] = NULL;
5748
5749 pool->execute = NULL;
5750 pool->label = gen_label_rtx ();
5751 pool->first_insn = NULL_RTX;
5752 pool->pool_insn = NULL_RTX;
5753 pool->insns = BITMAP_ALLOC (NULL);
5754 pool->size = 0;
5755 pool->emit_pool_after = NULL_RTX;
5756
5757 return pool;
5758 }
5759
5760 /* Create new constant pool covering instructions starting at INSN
5761 and chain it to the end of POOL_LIST. */
5762
5763 static struct constant_pool *
5764 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5765 {
5766 struct constant_pool *pool, **prev;
5767
5768 pool = s390_alloc_pool ();
5769 pool->first_insn = insn;
5770
5771 for (prev = pool_list; *prev; prev = &(*prev)->next)
5772 ;
5773 *prev = pool;
5774
5775 return pool;
5776 }
5777
5778 /* End range of instructions covered by POOL at INSN and emit
5779 placeholder insn representing the pool. */
5780
5781 static void
5782 s390_end_pool (struct constant_pool *pool, rtx insn)
5783 {
5784 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5785
5786 if (!insn)
5787 insn = get_last_insn ();
5788
5789 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5790 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5791 }
5792
5793 /* Add INSN to the list of insns covered by POOL. */
5794
5795 static void
5796 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5797 {
5798 bitmap_set_bit (pool->insns, INSN_UID (insn));
5799 }
5800
5801 /* Return pool out of POOL_LIST that covers INSN. */
5802
5803 static struct constant_pool *
5804 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5805 {
5806 struct constant_pool *pool;
5807
5808 for (pool = pool_list; pool; pool = pool->next)
5809 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5810 break;
5811
5812 return pool;
5813 }
5814
5815 /* Add constant VAL of mode MODE to the constant pool POOL. */
5816
5817 static void
5818 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5819 {
5820 struct constant *c;
5821 int i;
5822
5823 for (i = 0; i < NR_C_MODES; i++)
5824 if (constant_modes[i] == mode)
5825 break;
5826 gcc_assert (i != NR_C_MODES);
5827
5828 for (c = pool->constants[i]; c != NULL; c = c->next)
5829 if (rtx_equal_p (val, c->value))
5830 break;
5831
5832 if (c == NULL)
5833 {
5834 c = (struct constant *) xmalloc (sizeof *c);
5835 c->value = val;
5836 c->label = gen_label_rtx ();
5837 c->next = pool->constants[i];
5838 pool->constants[i] = c;
5839 pool->size += GET_MODE_SIZE (mode);
5840 }
5841 }
5842
5843 /* Return an rtx that represents the offset of X from the start of
5844 pool POOL. */
5845
5846 static rtx
5847 s390_pool_offset (struct constant_pool *pool, rtx x)
5848 {
5849 rtx label;
5850
5851 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5852 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5853 UNSPEC_POOL_OFFSET);
5854 return gen_rtx_CONST (GET_MODE (x), x);
5855 }
5856
5857 /* Find constant VAL of mode MODE in the constant pool POOL.
5858 Return an RTX describing the distance from the start of
5859 the pool to the location of the new constant. */
5860
5861 static rtx
5862 s390_find_constant (struct constant_pool *pool, rtx val,
5863 enum machine_mode mode)
5864 {
5865 struct constant *c;
5866 int i;
5867
5868 for (i = 0; i < NR_C_MODES; i++)
5869 if (constant_modes[i] == mode)
5870 break;
5871 gcc_assert (i != NR_C_MODES);
5872
5873 for (c = pool->constants[i]; c != NULL; c = c->next)
5874 if (rtx_equal_p (val, c->value))
5875 break;
5876
5877 gcc_assert (c);
5878
5879 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5880 }
5881
5882 /* Check whether INSN is an execute. Return the label_ref to its
5883 execute target template if so, NULL_RTX otherwise. */
5884
5885 static rtx
5886 s390_execute_label (rtx insn)
5887 {
5888 if (GET_CODE (insn) == INSN
5889 && GET_CODE (PATTERN (insn)) == PARALLEL
5890 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5891 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5892 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5893
5894 return NULL_RTX;
5895 }
5896
5897 /* Add execute target for INSN to the constant pool POOL. */
5898
5899 static void
5900 s390_add_execute (struct constant_pool *pool, rtx insn)
5901 {
5902 struct constant *c;
5903
5904 for (c = pool->execute; c != NULL; c = c->next)
5905 if (INSN_UID (insn) == INSN_UID (c->value))
5906 break;
5907
5908 if (c == NULL)
5909 {
5910 c = (struct constant *) xmalloc (sizeof *c);
5911 c->value = insn;
5912 c->label = gen_label_rtx ();
5913 c->next = pool->execute;
5914 pool->execute = c;
5915 pool->size += 6;
5916 }
5917 }
5918
5919 /* Find execute target for INSN in the constant pool POOL.
5920 Return an RTX describing the distance from the start of
5921 the pool to the location of the execute target. */
5922
5923 static rtx
5924 s390_find_execute (struct constant_pool *pool, rtx insn)
5925 {
5926 struct constant *c;
5927
5928 for (c = pool->execute; c != NULL; c = c->next)
5929 if (INSN_UID (insn) == INSN_UID (c->value))
5930 break;
5931
5932 gcc_assert (c);
5933
5934 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5935 }
5936
5937 /* For an execute INSN, extract the execute target template. */
5938
5939 static rtx
5940 s390_execute_target (rtx insn)
5941 {
5942 rtx pattern = PATTERN (insn);
5943 gcc_assert (s390_execute_label (insn));
5944
5945 if (XVECLEN (pattern, 0) == 2)
5946 {
5947 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5948 }
5949 else
5950 {
5951 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5952 int i;
5953
5954 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5955 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5956
5957 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5958 }
5959
5960 return pattern;
5961 }
5962
5963 /* Indicate that INSN cannot be duplicated. This is the case for
5964 execute insns that carry a unique label. */
5965
5966 static bool
5967 s390_cannot_copy_insn_p (rtx insn)
5968 {
5969 rtx label = s390_execute_label (insn);
5970 return label && label != const0_rtx;
5971 }
5972
5973 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5974 do not emit the pool base label. */
5975
5976 static void
5977 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5978 {
5979 struct constant *c;
5980 rtx insn = pool->pool_insn;
5981 int i;
5982
5983 /* Switch to rodata section. */
5984 if (TARGET_CPU_ZARCH)
5985 {
5986 insn = emit_insn_after (gen_pool_section_start (), insn);
5987 INSN_ADDRESSES_NEW (insn, -1);
5988 }
5989
5990 /* Ensure minimum pool alignment. */
5991 if (TARGET_CPU_ZARCH)
5992 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5993 else
5994 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5995 INSN_ADDRESSES_NEW (insn, -1);
5996
5997 /* Emit pool base label. */
5998 if (!remote_label)
5999 {
6000 insn = emit_label_after (pool->label, insn);
6001 INSN_ADDRESSES_NEW (insn, -1);
6002 }
6003
6004 /* Dump constants in descending alignment requirement order,
6005 ensuring proper alignment for every constant. */
6006 for (i = 0; i < NR_C_MODES; i++)
6007 for (c = pool->constants[i]; c; c = c->next)
6008 {
6009 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6010 rtx value = copy_rtx (c->value);
6011 if (GET_CODE (value) == CONST
6012 && GET_CODE (XEXP (value, 0)) == UNSPEC
6013 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6014 && XVECLEN (XEXP (value, 0), 0) == 1)
6015 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6016
6017 insn = emit_label_after (c->label, insn);
6018 INSN_ADDRESSES_NEW (insn, -1);
6019
6020 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6021 gen_rtvec (1, value),
6022 UNSPECV_POOL_ENTRY);
6023 insn = emit_insn_after (value, insn);
6024 INSN_ADDRESSES_NEW (insn, -1);
6025 }
6026
6027 /* Ensure minimum alignment for instructions. */
6028 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6029 INSN_ADDRESSES_NEW (insn, -1);
6030
6031 /* Output in-pool execute template insns. */
6032 for (c = pool->execute; c; c = c->next)
6033 {
6034 insn = emit_label_after (c->label, insn);
6035 INSN_ADDRESSES_NEW (insn, -1);
6036
6037 insn = emit_insn_after (s390_execute_target (c->value), insn);
6038 INSN_ADDRESSES_NEW (insn, -1);
6039 }
6040
6041 /* Switch back to previous section. */
6042 if (TARGET_CPU_ZARCH)
6043 {
6044 insn = emit_insn_after (gen_pool_section_end (), insn);
6045 INSN_ADDRESSES_NEW (insn, -1);
6046 }
6047
6048 insn = emit_barrier_after (insn);
6049 INSN_ADDRESSES_NEW (insn, -1);
6050
6051 /* Remove placeholder insn. */
6052 remove_insn (pool->pool_insn);
6053 }
6054
6055 /* Free all memory used by POOL. */
6056
6057 static void
6058 s390_free_pool (struct constant_pool *pool)
6059 {
6060 struct constant *c, *next;
6061 int i;
6062
6063 for (i = 0; i < NR_C_MODES; i++)
6064 for (c = pool->constants[i]; c; c = next)
6065 {
6066 next = c->next;
6067 free (c);
6068 }
6069
6070 for (c = pool->execute; c; c = next)
6071 {
6072 next = c->next;
6073 free (c);
6074 }
6075
6076 BITMAP_FREE (pool->insns);
6077 free (pool);
6078 }
6079
6080
6081 /* Collect main literal pool. Return NULL on overflow. */
6082
6083 static struct constant_pool *
6084 s390_mainpool_start (void)
6085 {
6086 struct constant_pool *pool;
6087 rtx insn;
6088
6089 pool = s390_alloc_pool ();
6090
6091 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6092 {
6093 if (GET_CODE (insn) == INSN
6094 && GET_CODE (PATTERN (insn)) == SET
6095 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6096 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6097 {
6098 gcc_assert (!pool->pool_insn);
6099 pool->pool_insn = insn;
6100 }
6101
6102 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6103 {
6104 s390_add_execute (pool, insn);
6105 }
6106 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6107 {
6108 rtx pool_ref = NULL_RTX;
6109 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6110 if (pool_ref)
6111 {
6112 rtx constant = get_pool_constant (pool_ref);
6113 enum machine_mode mode = get_pool_mode (pool_ref);
6114 s390_add_constant (pool, constant, mode);
6115 }
6116 }
6117
6118 /* If hot/cold partitioning is enabled we have to make sure that
6119 the literal pool is emitted in the same section where the
6120 initialization of the literal pool base pointer takes place.
6121 emit_pool_after is only used in the non-overflow case on non
6122 Z cpus where we can emit the literal pool at the end of the
6123 function body within the text section. */
6124 if (NOTE_P (insn)
6125 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6126 && !pool->emit_pool_after)
6127 pool->emit_pool_after = PREV_INSN (insn);
6128 }
6129
6130 gcc_assert (pool->pool_insn || pool->size == 0);
6131
6132 if (pool->size >= 4096)
6133 {
6134 /* We're going to chunkify the pool, so remove the main
6135 pool placeholder insn. */
6136 remove_insn (pool->pool_insn);
6137
6138 s390_free_pool (pool);
6139 pool = NULL;
6140 }
6141
6142 /* If the functions ends with the section where the literal pool
6143 should be emitted set the marker to its end. */
6144 if (pool && !pool->emit_pool_after)
6145 pool->emit_pool_after = get_last_insn ();
6146
6147 return pool;
6148 }
6149
6150 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6151 Modify the current function to output the pool constants as well as
6152 the pool register setup instruction. */
6153
6154 static void
6155 s390_mainpool_finish (struct constant_pool *pool)
6156 {
6157 rtx base_reg = cfun->machine->base_reg;
6158 rtx insn;
6159
6160 /* If the pool is empty, we're done. */
6161 if (pool->size == 0)
6162 {
6163 /* We don't actually need a base register after all. */
6164 cfun->machine->base_reg = NULL_RTX;
6165
6166 if (pool->pool_insn)
6167 remove_insn (pool->pool_insn);
6168 s390_free_pool (pool);
6169 return;
6170 }
6171
6172 /* We need correct insn addresses. */
6173 shorten_branches (get_insns ());
6174
6175 /* On zSeries, we use a LARL to load the pool register. The pool is
6176 located in the .rodata section, so we emit it after the function. */
6177 if (TARGET_CPU_ZARCH)
6178 {
6179 insn = gen_main_base_64 (base_reg, pool->label);
6180 insn = emit_insn_after (insn, pool->pool_insn);
6181 INSN_ADDRESSES_NEW (insn, -1);
6182 remove_insn (pool->pool_insn);
6183
6184 insn = get_last_insn ();
6185 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6186 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6187
6188 s390_dump_pool (pool, 0);
6189 }
6190
6191 /* On S/390, if the total size of the function's code plus literal pool
6192 does not exceed 4096 bytes, we use BASR to set up a function base
6193 pointer, and emit the literal pool at the end of the function. */
6194 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6195 + pool->size + 8 /* alignment slop */ < 4096)
6196 {
6197 insn = gen_main_base_31_small (base_reg, pool->label);
6198 insn = emit_insn_after (insn, pool->pool_insn);
6199 INSN_ADDRESSES_NEW (insn, -1);
6200 remove_insn (pool->pool_insn);
6201
6202 insn = emit_label_after (pool->label, insn);
6203 INSN_ADDRESSES_NEW (insn, -1);
6204
6205 /* emit_pool_after will be set by s390_mainpool_start to the
6206 last insn of the section where the literal pool should be
6207 emitted. */
6208 insn = pool->emit_pool_after;
6209
6210 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6211 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6212
6213 s390_dump_pool (pool, 1);
6214 }
6215
6216 /* Otherwise, we emit an inline literal pool and use BASR to branch
6217 over it, setting up the pool register at the same time. */
6218 else
6219 {
6220 rtx pool_end = gen_label_rtx ();
6221
6222 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6223 insn = emit_insn_after (insn, pool->pool_insn);
6224 INSN_ADDRESSES_NEW (insn, -1);
6225 remove_insn (pool->pool_insn);
6226
6227 insn = emit_label_after (pool->label, insn);
6228 INSN_ADDRESSES_NEW (insn, -1);
6229
6230 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6231 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6232
6233 insn = emit_label_after (pool_end, pool->pool_insn);
6234 INSN_ADDRESSES_NEW (insn, -1);
6235
6236 s390_dump_pool (pool, 1);
6237 }
6238
6239
6240 /* Replace all literal pool references. */
6241
6242 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6243 {
6244 if (INSN_P (insn))
6245 replace_ltrel_base (&PATTERN (insn));
6246
6247 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6248 {
6249 rtx addr, pool_ref = NULL_RTX;
6250 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6251 if (pool_ref)
6252 {
6253 if (s390_execute_label (insn))
6254 addr = s390_find_execute (pool, insn);
6255 else
6256 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6257 get_pool_mode (pool_ref));
6258
6259 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6260 INSN_CODE (insn) = -1;
6261 }
6262 }
6263 }
6264
6265
6266 /* Free the pool. */
6267 s390_free_pool (pool);
6268 }
6269
6270 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6271 We have decided we cannot use this pool, so revert all changes
6272 to the current function that were done by s390_mainpool_start. */
6273 static void
6274 s390_mainpool_cancel (struct constant_pool *pool)
6275 {
6276 /* We didn't actually change the instruction stream, so simply
6277 free the pool memory. */
6278 s390_free_pool (pool);
6279 }
6280
6281
6282 /* Chunkify the literal pool. */
6283
6284 #define S390_POOL_CHUNK_MIN 0xc00
6285 #define S390_POOL_CHUNK_MAX 0xe00
6286
6287 static struct constant_pool *
6288 s390_chunkify_start (void)
6289 {
6290 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6291 int extra_size = 0;
6292 bitmap far_labels;
6293 rtx pending_ltrel = NULL_RTX;
6294 rtx insn;
6295
6296 rtx (*gen_reload_base) (rtx, rtx) =
6297 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6298
6299
6300 /* We need correct insn addresses. */
6301
6302 shorten_branches (get_insns ());
6303
6304 /* Scan all insns and move literals to pool chunks. */
6305
6306 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6307 {
6308 bool section_switch_p = false;
6309
6310 /* Check for pending LTREL_BASE. */
6311 if (INSN_P (insn))
6312 {
6313 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6314 if (ltrel_base)
6315 {
6316 gcc_assert (ltrel_base == pending_ltrel);
6317 pending_ltrel = NULL_RTX;
6318 }
6319 }
6320
6321 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6322 {
6323 if (!curr_pool)
6324 curr_pool = s390_start_pool (&pool_list, insn);
6325
6326 s390_add_execute (curr_pool, insn);
6327 s390_add_pool_insn (curr_pool, insn);
6328 }
6329 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6330 {
6331 rtx pool_ref = NULL_RTX;
6332 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6333 if (pool_ref)
6334 {
6335 rtx constant = get_pool_constant (pool_ref);
6336 enum machine_mode mode = get_pool_mode (pool_ref);
6337
6338 if (!curr_pool)
6339 curr_pool = s390_start_pool (&pool_list, insn);
6340
6341 s390_add_constant (curr_pool, constant, mode);
6342 s390_add_pool_insn (curr_pool, insn);
6343
6344 /* Don't split the pool chunk between a LTREL_OFFSET load
6345 and the corresponding LTREL_BASE. */
6346 if (GET_CODE (constant) == CONST
6347 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6348 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6349 {
6350 gcc_assert (!pending_ltrel);
6351 pending_ltrel = pool_ref;
6352 }
6353 }
6354 }
6355
6356 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6357 {
6358 if (curr_pool)
6359 s390_add_pool_insn (curr_pool, insn);
6360 /* An LTREL_BASE must follow within the same basic block. */
6361 gcc_assert (!pending_ltrel);
6362 }
6363
6364 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6365 section_switch_p = true;
6366
6367 if (!curr_pool
6368 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6369 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6370 continue;
6371
6372 if (TARGET_CPU_ZARCH)
6373 {
6374 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6375 continue;
6376
6377 s390_end_pool (curr_pool, NULL_RTX);
6378 curr_pool = NULL;
6379 }
6380 else
6381 {
6382 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6383 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6384 + extra_size;
6385
6386 /* We will later have to insert base register reload insns.
6387 Those will have an effect on code size, which we need to
6388 consider here. This calculation makes rather pessimistic
6389 worst-case assumptions. */
6390 if (GET_CODE (insn) == CODE_LABEL)
6391 extra_size += 6;
6392
6393 if (chunk_size < S390_POOL_CHUNK_MIN
6394 && curr_pool->size < S390_POOL_CHUNK_MIN
6395 && !section_switch_p)
6396 continue;
6397
6398 /* Pool chunks can only be inserted after BARRIERs ... */
6399 if (GET_CODE (insn) == BARRIER)
6400 {
6401 s390_end_pool (curr_pool, insn);
6402 curr_pool = NULL;
6403 extra_size = 0;
6404 }
6405
6406 /* ... so if we don't find one in time, create one. */
6407 else if (chunk_size > S390_POOL_CHUNK_MAX
6408 || curr_pool->size > S390_POOL_CHUNK_MAX
6409 || section_switch_p)
6410 {
6411 rtx label, jump, barrier;
6412
6413 if (!section_switch_p)
6414 {
6415 /* We can insert the barrier only after a 'real' insn. */
6416 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6417 continue;
6418 if (get_attr_length (insn) == 0)
6419 continue;
6420 /* Don't separate LTREL_BASE from the corresponding
6421 LTREL_OFFSET load. */
6422 if (pending_ltrel)
6423 continue;
6424 }
6425 else
6426 {
6427 gcc_assert (!pending_ltrel);
6428
6429 /* The old pool has to end before the section switch
6430 note in order to make it part of the current
6431 section. */
6432 insn = PREV_INSN (insn);
6433 }
6434
6435 label = gen_label_rtx ();
6436 jump = emit_jump_insn_after (gen_jump (label), insn);
6437 barrier = emit_barrier_after (jump);
6438 insn = emit_label_after (label, barrier);
6439 JUMP_LABEL (jump) = label;
6440 LABEL_NUSES (label) = 1;
6441
6442 INSN_ADDRESSES_NEW (jump, -1);
6443 INSN_ADDRESSES_NEW (barrier, -1);
6444 INSN_ADDRESSES_NEW (insn, -1);
6445
6446 s390_end_pool (curr_pool, barrier);
6447 curr_pool = NULL;
6448 extra_size = 0;
6449 }
6450 }
6451 }
6452
6453 if (curr_pool)
6454 s390_end_pool (curr_pool, NULL_RTX);
6455 gcc_assert (!pending_ltrel);
6456
6457 /* Find all labels that are branched into
6458 from an insn belonging to a different chunk. */
6459
6460 far_labels = BITMAP_ALLOC (NULL);
6461
6462 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6463 {
6464 /* Labels marked with LABEL_PRESERVE_P can be target
6465 of non-local jumps, so we have to mark them.
6466 The same holds for named labels.
6467
6468 Don't do that, however, if it is the label before
6469 a jump table. */
6470
6471 if (GET_CODE (insn) == CODE_LABEL
6472 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6473 {
6474 rtx vec_insn = next_real_insn (insn);
6475 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6476 PATTERN (vec_insn) : NULL_RTX;
6477 if (!vec_pat
6478 || !(GET_CODE (vec_pat) == ADDR_VEC
6479 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6480 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6481 }
6482
6483 /* If we have a direct jump (conditional or unconditional)
6484 or a casesi jump, check all potential targets. */
6485 else if (GET_CODE (insn) == JUMP_INSN)
6486 {
6487 rtx pat = PATTERN (insn);
6488 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6489 pat = XVECEXP (pat, 0, 0);
6490
6491 if (GET_CODE (pat) == SET)
6492 {
6493 rtx label = JUMP_LABEL (insn);
6494 if (label)
6495 {
6496 if (s390_find_pool (pool_list, label)
6497 != s390_find_pool (pool_list, insn))
6498 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6499 }
6500 }
6501 else if (GET_CODE (pat) == PARALLEL
6502 && XVECLEN (pat, 0) == 2
6503 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6504 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6505 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6506 {
6507 /* Find the jump table used by this casesi jump. */
6508 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6509 rtx vec_insn = next_real_insn (vec_label);
6510 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6511 PATTERN (vec_insn) : NULL_RTX;
6512 if (vec_pat
6513 && (GET_CODE (vec_pat) == ADDR_VEC
6514 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6515 {
6516 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6517
6518 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6519 {
6520 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6521
6522 if (s390_find_pool (pool_list, label)
6523 != s390_find_pool (pool_list, insn))
6524 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6525 }
6526 }
6527 }
6528 }
6529 }
6530
6531 /* Insert base register reload insns before every pool. */
6532
6533 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6534 {
6535 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6536 curr_pool->label);
6537 rtx insn = curr_pool->first_insn;
6538 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6539 }
6540
6541 /* Insert base register reload insns at every far label. */
6542
6543 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6544 if (GET_CODE (insn) == CODE_LABEL
6545 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6546 {
6547 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6548 if (pool)
6549 {
6550 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6551 pool->label);
6552 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6553 }
6554 }
6555
6556
6557 BITMAP_FREE (far_labels);
6558
6559
6560 /* Recompute insn addresses. */
6561
6562 init_insn_lengths ();
6563 shorten_branches (get_insns ());
6564
6565 return pool_list;
6566 }
6567
6568 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6569 After we have decided to use this list, finish implementing
6570 all changes to the current function as required. */
6571
6572 static void
6573 s390_chunkify_finish (struct constant_pool *pool_list)
6574 {
6575 struct constant_pool *curr_pool = NULL;
6576 rtx insn;
6577
6578
6579 /* Replace all literal pool references. */
6580
6581 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6582 {
6583 if (INSN_P (insn))
6584 replace_ltrel_base (&PATTERN (insn));
6585
6586 curr_pool = s390_find_pool (pool_list, insn);
6587 if (!curr_pool)
6588 continue;
6589
6590 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6591 {
6592 rtx addr, pool_ref = NULL_RTX;
6593 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6594 if (pool_ref)
6595 {
6596 if (s390_execute_label (insn))
6597 addr = s390_find_execute (curr_pool, insn);
6598 else
6599 addr = s390_find_constant (curr_pool,
6600 get_pool_constant (pool_ref),
6601 get_pool_mode (pool_ref));
6602
6603 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6604 INSN_CODE (insn) = -1;
6605 }
6606 }
6607 }
6608
6609 /* Dump out all literal pools. */
6610
6611 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6612 s390_dump_pool (curr_pool, 0);
6613
6614 /* Free pool list. */
6615
6616 while (pool_list)
6617 {
6618 struct constant_pool *next = pool_list->next;
6619 s390_free_pool (pool_list);
6620 pool_list = next;
6621 }
6622 }
6623
6624 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6625 We have decided we cannot use this list, so revert all changes
6626 to the current function that were done by s390_chunkify_start. */
6627
6628 static void
6629 s390_chunkify_cancel (struct constant_pool *pool_list)
6630 {
6631 struct constant_pool *curr_pool = NULL;
6632 rtx insn;
6633
6634 /* Remove all pool placeholder insns. */
6635
6636 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6637 {
6638 /* Did we insert an extra barrier? Remove it. */
6639 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6640 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6641 rtx label = NEXT_INSN (curr_pool->pool_insn);
6642
6643 if (jump && GET_CODE (jump) == JUMP_INSN
6644 && barrier && GET_CODE (barrier) == BARRIER
6645 && label && GET_CODE (label) == CODE_LABEL
6646 && GET_CODE (PATTERN (jump)) == SET
6647 && SET_DEST (PATTERN (jump)) == pc_rtx
6648 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6649 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6650 {
6651 remove_insn (jump);
6652 remove_insn (barrier);
6653 remove_insn (label);
6654 }
6655
6656 remove_insn (curr_pool->pool_insn);
6657 }
6658
6659 /* Remove all base register reload insns. */
6660
6661 for (insn = get_insns (); insn; )
6662 {
6663 rtx next_insn = NEXT_INSN (insn);
6664
6665 if (GET_CODE (insn) == INSN
6666 && GET_CODE (PATTERN (insn)) == SET
6667 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6668 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6669 remove_insn (insn);
6670
6671 insn = next_insn;
6672 }
6673
6674 /* Free pool list. */
6675
6676 while (pool_list)
6677 {
6678 struct constant_pool *next = pool_list->next;
6679 s390_free_pool (pool_list);
6680 pool_list = next;
6681 }
6682 }
6683
6684 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6685
6686 void
6687 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6688 {
6689 REAL_VALUE_TYPE r;
6690
6691 switch (GET_MODE_CLASS (mode))
6692 {
6693 case MODE_FLOAT:
6694 case MODE_DECIMAL_FLOAT:
6695 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6696
6697 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6698 assemble_real (r, mode, align);
6699 break;
6700
6701 case MODE_INT:
6702 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6703 mark_symbol_refs_as_used (exp);
6704 break;
6705
6706 default:
6707 gcc_unreachable ();
6708 }
6709 }
6710
6711
6712 /* Return an RTL expression representing the value of the return address
6713 for the frame COUNT steps up from the current frame. FRAME is the
6714 frame pointer of that frame. */
6715
6716 rtx
6717 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6718 {
6719 int offset;
6720 rtx addr;
6721
6722 /* Without backchain, we fail for all but the current frame. */
6723
6724 if (!TARGET_BACKCHAIN && count > 0)
6725 return NULL_RTX;
6726
6727 /* For the current frame, we need to make sure the initial
6728 value of RETURN_REGNUM is actually saved. */
6729
6730 if (count == 0)
6731 {
6732 /* On non-z architectures branch splitting could overwrite r14. */
6733 if (TARGET_CPU_ZARCH)
6734 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6735 else
6736 {
6737 cfun_frame_layout.save_return_addr_p = true;
6738 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6739 }
6740 }
6741
6742 if (TARGET_PACKED_STACK)
6743 offset = -2 * UNITS_PER_WORD;
6744 else
6745 offset = RETURN_REGNUM * UNITS_PER_WORD;
6746
6747 addr = plus_constant (frame, offset);
6748 addr = memory_address (Pmode, addr);
6749 return gen_rtx_MEM (Pmode, addr);
6750 }
6751
6752 /* Return an RTL expression representing the back chain stored in
6753 the current stack frame. */
6754
6755 rtx
6756 s390_back_chain_rtx (void)
6757 {
6758 rtx chain;
6759
6760 gcc_assert (TARGET_BACKCHAIN);
6761
6762 if (TARGET_PACKED_STACK)
6763 chain = plus_constant (stack_pointer_rtx,
6764 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6765 else
6766 chain = stack_pointer_rtx;
6767
6768 chain = gen_rtx_MEM (Pmode, chain);
6769 return chain;
6770 }
6771
6772 /* Find first call clobbered register unused in a function.
6773 This could be used as base register in a leaf function
6774 or for holding the return address before epilogue. */
6775
6776 static int
6777 find_unused_clobbered_reg (void)
6778 {
6779 int i;
6780 for (i = 0; i < 6; i++)
6781 if (!df_regs_ever_live_p (i))
6782 return i;
6783 return 0;
6784 }
6785
6786
6787 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6788 clobbered hard regs in SETREG. */
6789
6790 static void
6791 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6792 {
6793 int *regs_ever_clobbered = (int *)data;
6794 unsigned int i, regno;
6795 enum machine_mode mode = GET_MODE (setreg);
6796
6797 if (GET_CODE (setreg) == SUBREG)
6798 {
6799 rtx inner = SUBREG_REG (setreg);
6800 if (!GENERAL_REG_P (inner))
6801 return;
6802 regno = subreg_regno (setreg);
6803 }
6804 else if (GENERAL_REG_P (setreg))
6805 regno = REGNO (setreg);
6806 else
6807 return;
6808
6809 for (i = regno;
6810 i < regno + HARD_REGNO_NREGS (regno, mode);
6811 i++)
6812 regs_ever_clobbered[i] = 1;
6813 }
6814
6815 /* Walks through all basic blocks of the current function looking
6816 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6817 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6818 each of those regs. */
6819
6820 static void
6821 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6822 {
6823 basic_block cur_bb;
6824 rtx cur_insn;
6825 unsigned int i;
6826
6827 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6828
6829 /* For non-leaf functions we have to consider all call clobbered regs to be
6830 clobbered. */
6831 if (!current_function_is_leaf)
6832 {
6833 for (i = 0; i < 16; i++)
6834 regs_ever_clobbered[i] = call_really_used_regs[i];
6835 }
6836
6837 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6838 this work is done by liveness analysis (mark_regs_live_at_end).
6839 Special care is needed for functions containing landing pads. Landing pads
6840 may use the eh registers, but the code which sets these registers is not
6841 contained in that function. Hence s390_regs_ever_clobbered is not able to
6842 deal with this automatically. */
6843 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6844 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6845 if (crtl->calls_eh_return
6846 || (cfun->machine->has_landing_pad_p
6847 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6848 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6849
6850 /* For nonlocal gotos all call-saved registers have to be saved.
6851 This flag is also set for the unwinding code in libgcc.
6852 See expand_builtin_unwind_init. For regs_ever_live this is done by
6853 reload. */
6854 if (cfun->has_nonlocal_label)
6855 for (i = 0; i < 16; i++)
6856 if (!call_really_used_regs[i])
6857 regs_ever_clobbered[i] = 1;
6858
6859 FOR_EACH_BB (cur_bb)
6860 {
6861 FOR_BB_INSNS (cur_bb, cur_insn)
6862 {
6863 if (INSN_P (cur_insn))
6864 note_stores (PATTERN (cur_insn),
6865 s390_reg_clobbered_rtx,
6866 regs_ever_clobbered);
6867 }
6868 }
6869 }
6870
6871 /* Determine the frame area which actually has to be accessed
6872 in the function epilogue. The values are stored at the
6873 given pointers AREA_BOTTOM (address of the lowest used stack
6874 address) and AREA_TOP (address of the first item which does
6875 not belong to the stack frame). */
6876
6877 static void
6878 s390_frame_area (int *area_bottom, int *area_top)
6879 {
6880 int b, t;
6881 int i;
6882
6883 b = INT_MAX;
6884 t = INT_MIN;
6885
6886 if (cfun_frame_layout.first_restore_gpr != -1)
6887 {
6888 b = (cfun_frame_layout.gprs_offset
6889 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6890 t = b + (cfun_frame_layout.last_restore_gpr
6891 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6892 }
6893
6894 if (TARGET_64BIT && cfun_save_high_fprs_p)
6895 {
6896 b = MIN (b, cfun_frame_layout.f8_offset);
6897 t = MAX (t, (cfun_frame_layout.f8_offset
6898 + cfun_frame_layout.high_fprs * 8));
6899 }
6900
6901 if (!TARGET_64BIT)
6902 for (i = 2; i < 4; i++)
6903 if (cfun_fpr_bit_p (i))
6904 {
6905 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6906 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6907 }
6908
6909 *area_bottom = b;
6910 *area_top = t;
6911 }
6912
6913 /* Fill cfun->machine with info about register usage of current function.
6914 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6915
6916 static void
6917 s390_register_info (int clobbered_regs[])
6918 {
6919 int i, j;
6920
6921 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6922 cfun_frame_layout.fpr_bitmap = 0;
6923 cfun_frame_layout.high_fprs = 0;
6924 if (TARGET_64BIT)
6925 for (i = 24; i < 32; i++)
6926 if (df_regs_ever_live_p (i) && !global_regs[i])
6927 {
6928 cfun_set_fpr_bit (i - 16);
6929 cfun_frame_layout.high_fprs++;
6930 }
6931
6932 /* Find first and last gpr to be saved. We trust regs_ever_live
6933 data, except that we don't save and restore global registers.
6934
6935 Also, all registers with special meaning to the compiler need
6936 to be handled extra. */
6937
6938 s390_regs_ever_clobbered (clobbered_regs);
6939
6940 for (i = 0; i < 16; i++)
6941 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6942
6943 if (frame_pointer_needed)
6944 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6945
6946 if (flag_pic)
6947 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6948 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6949
6950 clobbered_regs[BASE_REGNUM]
6951 |= (cfun->machine->base_reg
6952 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6953
6954 clobbered_regs[RETURN_REGNUM]
6955 |= (!current_function_is_leaf
6956 || TARGET_TPF_PROFILING
6957 || cfun->machine->split_branches_pending_p
6958 || cfun_frame_layout.save_return_addr_p
6959 || crtl->calls_eh_return
6960 || cfun->stdarg);
6961
6962 clobbered_regs[STACK_POINTER_REGNUM]
6963 |= (!current_function_is_leaf
6964 || TARGET_TPF_PROFILING
6965 || cfun_save_high_fprs_p
6966 || get_frame_size () > 0
6967 || cfun->calls_alloca
6968 || cfun->stdarg);
6969
6970 for (i = 6; i < 16; i++)
6971 if (df_regs_ever_live_p (i) || clobbered_regs[i])
6972 break;
6973 for (j = 15; j > i; j--)
6974 if (df_regs_ever_live_p (j) || clobbered_regs[j])
6975 break;
6976
6977 if (i == 16)
6978 {
6979 /* Nothing to save/restore. */
6980 cfun_frame_layout.first_save_gpr_slot = -1;
6981 cfun_frame_layout.last_save_gpr_slot = -1;
6982 cfun_frame_layout.first_save_gpr = -1;
6983 cfun_frame_layout.first_restore_gpr = -1;
6984 cfun_frame_layout.last_save_gpr = -1;
6985 cfun_frame_layout.last_restore_gpr = -1;
6986 }
6987 else
6988 {
6989 /* Save slots for gprs from i to j. */
6990 cfun_frame_layout.first_save_gpr_slot = i;
6991 cfun_frame_layout.last_save_gpr_slot = j;
6992
6993 for (i = cfun_frame_layout.first_save_gpr_slot;
6994 i < cfun_frame_layout.last_save_gpr_slot + 1;
6995 i++)
6996 if (clobbered_regs[i])
6997 break;
6998
6999 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7000 if (clobbered_regs[j])
7001 break;
7002
7003 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7004 {
7005 /* Nothing to save/restore. */
7006 cfun_frame_layout.first_save_gpr = -1;
7007 cfun_frame_layout.first_restore_gpr = -1;
7008 cfun_frame_layout.last_save_gpr = -1;
7009 cfun_frame_layout.last_restore_gpr = -1;
7010 }
7011 else
7012 {
7013 /* Save / Restore from gpr i to j. */
7014 cfun_frame_layout.first_save_gpr = i;
7015 cfun_frame_layout.first_restore_gpr = i;
7016 cfun_frame_layout.last_save_gpr = j;
7017 cfun_frame_layout.last_restore_gpr = j;
7018 }
7019 }
7020
7021 if (cfun->stdarg)
7022 {
7023 /* Varargs functions need to save gprs 2 to 6. */
7024 if (cfun->va_list_gpr_size
7025 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7026 {
7027 int min_gpr = crtl->args.info.gprs;
7028 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7029 if (max_gpr > GP_ARG_NUM_REG)
7030 max_gpr = GP_ARG_NUM_REG;
7031
7032 if (cfun_frame_layout.first_save_gpr == -1
7033 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7034 {
7035 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7036 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7037 }
7038
7039 if (cfun_frame_layout.last_save_gpr == -1
7040 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7041 {
7042 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7043 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7044 }
7045 }
7046
7047 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7048 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7049 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7050 {
7051 int min_fpr = crtl->args.info.fprs;
7052 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7053 if (max_fpr > FP_ARG_NUM_REG)
7054 max_fpr = FP_ARG_NUM_REG;
7055
7056 /* ??? This is currently required to ensure proper location
7057 of the fpr save slots within the va_list save area. */
7058 if (TARGET_PACKED_STACK)
7059 min_fpr = 0;
7060
7061 for (i = min_fpr; i < max_fpr; i++)
7062 cfun_set_fpr_bit (i);
7063 }
7064 }
7065
7066 if (!TARGET_64BIT)
7067 for (i = 2; i < 4; i++)
7068 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7069 cfun_set_fpr_bit (i);
7070 }
7071
7072 /* Fill cfun->machine with info about frame of current function. */
7073
7074 static void
7075 s390_frame_info (void)
7076 {
7077 int i;
7078
7079 cfun_frame_layout.frame_size = get_frame_size ();
7080 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7081 fatal_error ("total size of local variables exceeds architecture limit");
7082
7083 if (!TARGET_PACKED_STACK)
7084 {
7085 cfun_frame_layout.backchain_offset = 0;
7086 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
7087 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7088 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7089 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7090 * UNITS_PER_WORD);
7091 }
7092 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7093 {
7094 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7095 - UNITS_PER_WORD);
7096 cfun_frame_layout.gprs_offset
7097 = (cfun_frame_layout.backchain_offset
7098 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7099 * UNITS_PER_WORD);
7100
7101 if (TARGET_64BIT)
7102 {
7103 cfun_frame_layout.f4_offset
7104 = (cfun_frame_layout.gprs_offset
7105 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7106
7107 cfun_frame_layout.f0_offset
7108 = (cfun_frame_layout.f4_offset
7109 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7110 }
7111 else
7112 {
7113 /* On 31 bit we have to care about alignment of the
7114 floating point regs to provide fastest access. */
7115 cfun_frame_layout.f0_offset
7116 = ((cfun_frame_layout.gprs_offset
7117 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7118 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7119
7120 cfun_frame_layout.f4_offset
7121 = (cfun_frame_layout.f0_offset
7122 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7123 }
7124 }
7125 else /* no backchain */
7126 {
7127 cfun_frame_layout.f4_offset
7128 = (STACK_POINTER_OFFSET
7129 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7130
7131 cfun_frame_layout.f0_offset
7132 = (cfun_frame_layout.f4_offset
7133 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7134
7135 cfun_frame_layout.gprs_offset
7136 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7137 }
7138
7139 if (current_function_is_leaf
7140 && !TARGET_TPF_PROFILING
7141 && cfun_frame_layout.frame_size == 0
7142 && !cfun_save_high_fprs_p
7143 && !cfun->calls_alloca
7144 && !cfun->stdarg)
7145 return;
7146
7147 if (!TARGET_PACKED_STACK)
7148 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7149 + crtl->outgoing_args_size
7150 + cfun_frame_layout.high_fprs * 8);
7151 else
7152 {
7153 if (TARGET_BACKCHAIN)
7154 cfun_frame_layout.frame_size += UNITS_PER_WORD;
7155
7156 /* No alignment trouble here because f8-f15 are only saved under
7157 64 bit. */
7158 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7159 cfun_frame_layout.f4_offset),
7160 cfun_frame_layout.gprs_offset)
7161 - cfun_frame_layout.high_fprs * 8);
7162
7163 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7164
7165 for (i = 0; i < 8; i++)
7166 if (cfun_fpr_bit_p (i))
7167 cfun_frame_layout.frame_size += 8;
7168
7169 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7170
7171 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7172 the frame size to sustain 8 byte alignment of stack frames. */
7173 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7174 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7175 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7176
7177 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7178 }
7179 }
7180
7181 /* Generate frame layout. Fills in register and frame data for the current
7182 function in cfun->machine. This routine can be called multiple times;
7183 it will re-do the complete frame layout every time. */
7184
7185 static void
7186 s390_init_frame_layout (void)
7187 {
7188 HOST_WIDE_INT frame_size;
7189 int base_used;
7190 int clobbered_regs[16];
7191
7192 /* On S/390 machines, we may need to perform branch splitting, which
7193 will require both base and return address register. We have no
7194 choice but to assume we're going to need them until right at the
7195 end of the machine dependent reorg phase. */
7196 if (!TARGET_CPU_ZARCH)
7197 cfun->machine->split_branches_pending_p = true;
7198
7199 do
7200 {
7201 frame_size = cfun_frame_layout.frame_size;
7202
7203 /* Try to predict whether we'll need the base register. */
7204 base_used = cfun->machine->split_branches_pending_p
7205 || crtl->uses_const_pool
7206 || (!DISP_IN_RANGE (frame_size)
7207 && !CONST_OK_FOR_K (frame_size));
7208
7209 /* Decide which register to use as literal pool base. In small
7210 leaf functions, try to use an unused call-clobbered register
7211 as base register to avoid save/restore overhead. */
7212 if (!base_used)
7213 cfun->machine->base_reg = NULL_RTX;
7214 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7215 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7216 else
7217 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7218
7219 s390_register_info (clobbered_regs);
7220 s390_frame_info ();
7221 }
7222 while (frame_size != cfun_frame_layout.frame_size);
7223 }
7224
7225 /* Update frame layout. Recompute actual register save data based on
7226 current info and update regs_ever_live for the special registers.
7227 May be called multiple times, but may never cause *more* registers
7228 to be saved than s390_init_frame_layout allocated room for. */
7229
7230 static void
7231 s390_update_frame_layout (void)
7232 {
7233 int clobbered_regs[16];
7234
7235 s390_register_info (clobbered_regs);
7236
7237 df_set_regs_ever_live (BASE_REGNUM,
7238 clobbered_regs[BASE_REGNUM] ? true : false);
7239 df_set_regs_ever_live (RETURN_REGNUM,
7240 clobbered_regs[RETURN_REGNUM] ? true : false);
7241 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7242 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7243
7244 if (cfun->machine->base_reg)
7245 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7246 }
7247
7248 /* Return true if it is legal to put a value with MODE into REGNO. */
7249
7250 bool
7251 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7252 {
7253 switch (REGNO_REG_CLASS (regno))
7254 {
7255 case FP_REGS:
7256 if (REGNO_PAIR_OK (regno, mode))
7257 {
7258 if (mode == SImode || mode == DImode)
7259 return true;
7260
7261 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7262 return true;
7263 }
7264 break;
7265 case ADDR_REGS:
7266 if (FRAME_REGNO_P (regno) && mode == Pmode)
7267 return true;
7268
7269 /* fallthrough */
7270 case GENERAL_REGS:
7271 if (REGNO_PAIR_OK (regno, mode))
7272 {
7273 if (TARGET_64BIT
7274 || (mode != TFmode && mode != TCmode && mode != TDmode))
7275 return true;
7276 }
7277 break;
7278 case CC_REGS:
7279 if (GET_MODE_CLASS (mode) == MODE_CC)
7280 return true;
7281 break;
7282 case ACCESS_REGS:
7283 if (REGNO_PAIR_OK (regno, mode))
7284 {
7285 if (mode == SImode || mode == Pmode)
7286 return true;
7287 }
7288 break;
7289 default:
7290 return false;
7291 }
7292
7293 return false;
7294 }
7295
7296 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7297
7298 bool
7299 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7300 {
7301 /* Once we've decided upon a register to use as base register, it must
7302 no longer be used for any other purpose. */
7303 if (cfun->machine->base_reg)
7304 if (REGNO (cfun->machine->base_reg) == old_reg
7305 || REGNO (cfun->machine->base_reg) == new_reg)
7306 return false;
7307
7308 return true;
7309 }
7310
7311 /* Maximum number of registers to represent a value of mode MODE
7312 in a register of class RCLASS. */
7313
7314 bool
7315 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7316 {
7317 switch (rclass)
7318 {
7319 case FP_REGS:
7320 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7321 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7322 else
7323 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7324 case ACCESS_REGS:
7325 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7326 default:
7327 break;
7328 }
7329 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7330 }
7331
7332 /* Return true if register FROM can be eliminated via register TO. */
7333
7334 bool
7335 s390_can_eliminate (int from, int to)
7336 {
7337 /* On zSeries machines, we have not marked the base register as fixed.
7338 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7339 If a function requires the base register, we say here that this
7340 elimination cannot be performed. This will cause reload to free
7341 up the base register (as if it were fixed). On the other hand,
7342 if the current function does *not* require the base register, we
7343 say here the elimination succeeds, which in turn allows reload
7344 to allocate the base register for any other purpose. */
7345 if (from == BASE_REGNUM && to == BASE_REGNUM)
7346 {
7347 if (TARGET_CPU_ZARCH)
7348 {
7349 s390_init_frame_layout ();
7350 return cfun->machine->base_reg == NULL_RTX;
7351 }
7352
7353 return false;
7354 }
7355
7356 /* Everything else must point into the stack frame. */
7357 gcc_assert (to == STACK_POINTER_REGNUM
7358 || to == HARD_FRAME_POINTER_REGNUM);
7359
7360 gcc_assert (from == FRAME_POINTER_REGNUM
7361 || from == ARG_POINTER_REGNUM
7362 || from == RETURN_ADDRESS_POINTER_REGNUM);
7363
7364 /* Make sure we actually saved the return address. */
7365 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7366 if (!crtl->calls_eh_return
7367 && !cfun->stdarg
7368 && !cfun_frame_layout.save_return_addr_p)
7369 return false;
7370
7371 return true;
7372 }
7373
7374 /* Return offset between register FROM and TO initially after prolog. */
7375
7376 HOST_WIDE_INT
7377 s390_initial_elimination_offset (int from, int to)
7378 {
7379 HOST_WIDE_INT offset;
7380 int index;
7381
7382 /* ??? Why are we called for non-eliminable pairs? */
7383 if (!s390_can_eliminate (from, to))
7384 return 0;
7385
7386 switch (from)
7387 {
7388 case FRAME_POINTER_REGNUM:
7389 offset = (get_frame_size()
7390 + STACK_POINTER_OFFSET
7391 + crtl->outgoing_args_size);
7392 break;
7393
7394 case ARG_POINTER_REGNUM:
7395 s390_init_frame_layout ();
7396 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7397 break;
7398
7399 case RETURN_ADDRESS_POINTER_REGNUM:
7400 s390_init_frame_layout ();
7401 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7402 gcc_assert (index >= 0);
7403 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7404 offset += index * UNITS_PER_WORD;
7405 break;
7406
7407 case BASE_REGNUM:
7408 offset = 0;
7409 break;
7410
7411 default:
7412 gcc_unreachable ();
7413 }
7414
7415 return offset;
7416 }
7417
7418 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7419 to register BASE. Return generated insn. */
7420
7421 static rtx
7422 save_fpr (rtx base, int offset, int regnum)
7423 {
7424 rtx addr;
7425 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7426
7427 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7428 set_mem_alias_set (addr, get_varargs_alias_set ());
7429 else
7430 set_mem_alias_set (addr, get_frame_alias_set ());
7431
7432 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7433 }
7434
7435 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7436 to register BASE. Return generated insn. */
7437
7438 static rtx
7439 restore_fpr (rtx base, int offset, int regnum)
7440 {
7441 rtx addr;
7442 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7443 set_mem_alias_set (addr, get_frame_alias_set ());
7444
7445 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7446 }
7447
7448 /* Return true if REGNO is a global register, but not one
7449 of the special ones that need to be saved/restored in anyway. */
7450
7451 static inline bool
7452 global_not_special_regno_p (int regno)
7453 {
7454 return (global_regs[regno]
7455 /* These registers are special and need to be
7456 restored in any case. */
7457 && !(regno == STACK_POINTER_REGNUM
7458 || regno == RETURN_REGNUM
7459 || regno == BASE_REGNUM
7460 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7461 }
7462
7463 /* Generate insn to save registers FIRST to LAST into
7464 the register save area located at offset OFFSET
7465 relative to register BASE. */
7466
7467 static rtx
7468 save_gprs (rtx base, int offset, int first, int last)
7469 {
7470 rtx addr, insn, note;
7471 int i;
7472
7473 addr = plus_constant (base, offset);
7474 addr = gen_rtx_MEM (Pmode, addr);
7475
7476 set_mem_alias_set (addr, get_frame_alias_set ());
7477
7478 /* Special-case single register. */
7479 if (first == last)
7480 {
7481 if (TARGET_64BIT)
7482 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7483 else
7484 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7485
7486 if (!global_not_special_regno_p (first))
7487 RTX_FRAME_RELATED_P (insn) = 1;
7488 return insn;
7489 }
7490
7491
7492 insn = gen_store_multiple (addr,
7493 gen_rtx_REG (Pmode, first),
7494 GEN_INT (last - first + 1));
7495
7496 if (first <= 6 && cfun->stdarg)
7497 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7498 {
7499 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7500
7501 if (first + i <= 6)
7502 set_mem_alias_set (mem, get_varargs_alias_set ());
7503 }
7504
7505 /* We need to set the FRAME_RELATED flag on all SETs
7506 inside the store-multiple pattern.
7507
7508 However, we must not emit DWARF records for registers 2..5
7509 if they are stored for use by variable arguments ...
7510
7511 ??? Unfortunately, it is not enough to simply not the
7512 FRAME_RELATED flags for those SETs, because the first SET
7513 of the PARALLEL is always treated as if it had the flag
7514 set, even if it does not. Therefore we emit a new pattern
7515 without those registers as REG_FRAME_RELATED_EXPR note. */
7516
7517 if (first >= 6 && !global_not_special_regno_p (first))
7518 {
7519 rtx pat = PATTERN (insn);
7520
7521 for (i = 0; i < XVECLEN (pat, 0); i++)
7522 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7523 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7524 0, i)))))
7525 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7526
7527 RTX_FRAME_RELATED_P (insn) = 1;
7528 }
7529 else if (last >= 6)
7530 {
7531 int start;
7532
7533 for (start = first >= 6 ? first : 6; start <= last; start++)
7534 if (!global_not_special_regno_p (start))
7535 break;
7536
7537 if (start > last)
7538 return insn;
7539
7540 addr = plus_constant (base, offset + (start - first) * UNITS_PER_WORD);
7541 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7542 gen_rtx_REG (Pmode, start),
7543 GEN_INT (last - start + 1));
7544 note = PATTERN (note);
7545
7546 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7547
7548 for (i = 0; i < XVECLEN (note, 0); i++)
7549 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7550 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7551 0, i)))))
7552 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7553
7554 RTX_FRAME_RELATED_P (insn) = 1;
7555 }
7556
7557 return insn;
7558 }
7559
7560 /* Generate insn to restore registers FIRST to LAST from
7561 the register save area located at offset OFFSET
7562 relative to register BASE. */
7563
7564 static rtx
7565 restore_gprs (rtx base, int offset, int first, int last)
7566 {
7567 rtx addr, insn;
7568
7569 addr = plus_constant (base, offset);
7570 addr = gen_rtx_MEM (Pmode, addr);
7571 set_mem_alias_set (addr, get_frame_alias_set ());
7572
7573 /* Special-case single register. */
7574 if (first == last)
7575 {
7576 if (TARGET_64BIT)
7577 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7578 else
7579 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7580
7581 return insn;
7582 }
7583
7584 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7585 addr,
7586 GEN_INT (last - first + 1));
7587 return insn;
7588 }
7589
7590 /* Return insn sequence to load the GOT register. */
7591
7592 static GTY(()) rtx got_symbol;
7593 rtx
7594 s390_load_got (void)
7595 {
7596 rtx insns;
7597
7598 if (!got_symbol)
7599 {
7600 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7601 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7602 }
7603
7604 start_sequence ();
7605
7606 if (TARGET_CPU_ZARCH)
7607 {
7608 emit_move_insn (pic_offset_table_rtx, got_symbol);
7609 }
7610 else
7611 {
7612 rtx offset;
7613
7614 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7615 UNSPEC_LTREL_OFFSET);
7616 offset = gen_rtx_CONST (Pmode, offset);
7617 offset = force_const_mem (Pmode, offset);
7618
7619 emit_move_insn (pic_offset_table_rtx, offset);
7620
7621 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7622 UNSPEC_LTREL_BASE);
7623 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7624
7625 emit_move_insn (pic_offset_table_rtx, offset);
7626 }
7627
7628 insns = get_insns ();
7629 end_sequence ();
7630 return insns;
7631 }
7632
7633 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7634 and the change to the stack pointer. */
7635
7636 static void
7637 s390_emit_stack_tie (void)
7638 {
7639 rtx mem = gen_frame_mem (BLKmode,
7640 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7641
7642 emit_insn (gen_stack_tie (mem));
7643 }
7644
7645 /* Expand the prologue into a bunch of separate insns. */
7646
7647 void
7648 s390_emit_prologue (void)
7649 {
7650 rtx insn, addr;
7651 rtx temp_reg;
7652 int i;
7653 int offset;
7654 int next_fpr = 0;
7655
7656 /* Complete frame layout. */
7657
7658 s390_update_frame_layout ();
7659
7660 /* Annotate all constant pool references to let the scheduler know
7661 they implicitly use the base register. */
7662
7663 push_topmost_sequence ();
7664
7665 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7666 if (INSN_P (insn))
7667 {
7668 annotate_constant_pool_refs (&PATTERN (insn));
7669 df_insn_rescan (insn);
7670 }
7671
7672 pop_topmost_sequence ();
7673
7674 /* Choose best register to use for temp use within prologue.
7675 See below for why TPF must use the register 1. */
7676
7677 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7678 && !current_function_is_leaf
7679 && !TARGET_TPF_PROFILING)
7680 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7681 else
7682 temp_reg = gen_rtx_REG (Pmode, 1);
7683
7684 /* Save call saved gprs. */
7685 if (cfun_frame_layout.first_save_gpr != -1)
7686 {
7687 insn = save_gprs (stack_pointer_rtx,
7688 cfun_frame_layout.gprs_offset +
7689 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7690 - cfun_frame_layout.first_save_gpr_slot),
7691 cfun_frame_layout.first_save_gpr,
7692 cfun_frame_layout.last_save_gpr);
7693 emit_insn (insn);
7694 }
7695
7696 /* Dummy insn to mark literal pool slot. */
7697
7698 if (cfun->machine->base_reg)
7699 emit_insn (gen_main_pool (cfun->machine->base_reg));
7700
7701 offset = cfun_frame_layout.f0_offset;
7702
7703 /* Save f0 and f2. */
7704 for (i = 0; i < 2; i++)
7705 {
7706 if (cfun_fpr_bit_p (i))
7707 {
7708 save_fpr (stack_pointer_rtx, offset, i + 16);
7709 offset += 8;
7710 }
7711 else if (!TARGET_PACKED_STACK)
7712 offset += 8;
7713 }
7714
7715 /* Save f4 and f6. */
7716 offset = cfun_frame_layout.f4_offset;
7717 for (i = 2; i < 4; i++)
7718 {
7719 if (cfun_fpr_bit_p (i))
7720 {
7721 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7722 offset += 8;
7723
7724 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7725 therefore are not frame related. */
7726 if (!call_really_used_regs[i + 16])
7727 RTX_FRAME_RELATED_P (insn) = 1;
7728 }
7729 else if (!TARGET_PACKED_STACK)
7730 offset += 8;
7731 }
7732
7733 if (TARGET_PACKED_STACK
7734 && cfun_save_high_fprs_p
7735 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7736 {
7737 offset = (cfun_frame_layout.f8_offset
7738 + (cfun_frame_layout.high_fprs - 1) * 8);
7739
7740 for (i = 15; i > 7 && offset >= 0; i--)
7741 if (cfun_fpr_bit_p (i))
7742 {
7743 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7744
7745 RTX_FRAME_RELATED_P (insn) = 1;
7746 offset -= 8;
7747 }
7748 if (offset >= cfun_frame_layout.f8_offset)
7749 next_fpr = i + 16;
7750 }
7751
7752 if (!TARGET_PACKED_STACK)
7753 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7754
7755 /* Decrement stack pointer. */
7756
7757 if (cfun_frame_layout.frame_size > 0)
7758 {
7759 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7760 rtx real_frame_off;
7761
7762 if (s390_stack_size)
7763 {
7764 HOST_WIDE_INT stack_guard;
7765
7766 if (s390_stack_guard)
7767 stack_guard = s390_stack_guard;
7768 else
7769 {
7770 /* If no value for stack guard is provided the smallest power of 2
7771 larger than the current frame size is chosen. */
7772 stack_guard = 1;
7773 while (stack_guard < cfun_frame_layout.frame_size)
7774 stack_guard <<= 1;
7775 }
7776
7777 if (cfun_frame_layout.frame_size >= s390_stack_size)
7778 {
7779 warning (0, "frame size of function %qs is "
7780 HOST_WIDE_INT_PRINT_DEC
7781 " bytes exceeding user provided stack limit of "
7782 HOST_WIDE_INT_PRINT_DEC " bytes. "
7783 "An unconditional trap is added.",
7784 current_function_name(), cfun_frame_layout.frame_size,
7785 s390_stack_size);
7786 emit_insn (gen_trap ());
7787 }
7788 else
7789 {
7790 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7791 & ~(stack_guard - 1));
7792 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7793 GEN_INT (stack_check_mask));
7794 if (TARGET_64BIT)
7795 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7796 t, const0_rtx, const0_rtx));
7797 else
7798 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7799 t, const0_rtx, const0_rtx));
7800 }
7801 }
7802
7803 if (s390_warn_framesize > 0
7804 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7805 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7806 current_function_name (), cfun_frame_layout.frame_size);
7807
7808 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7809 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7810
7811 /* Save incoming stack pointer into temp reg. */
7812 if (TARGET_BACKCHAIN || next_fpr)
7813 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7814
7815 /* Subtract frame size from stack pointer. */
7816
7817 if (DISP_IN_RANGE (INTVAL (frame_off)))
7818 {
7819 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7820 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7821 frame_off));
7822 insn = emit_insn (insn);
7823 }
7824 else
7825 {
7826 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7827 frame_off = force_const_mem (Pmode, frame_off);
7828
7829 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7830 annotate_constant_pool_refs (&PATTERN (insn));
7831 }
7832
7833 RTX_FRAME_RELATED_P (insn) = 1;
7834 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7835 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7836 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7837 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7838 real_frame_off)));
7839
7840 /* Set backchain. */
7841
7842 if (TARGET_BACKCHAIN)
7843 {
7844 if (cfun_frame_layout.backchain_offset)
7845 addr = gen_rtx_MEM (Pmode,
7846 plus_constant (stack_pointer_rtx,
7847 cfun_frame_layout.backchain_offset));
7848 else
7849 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7850 set_mem_alias_set (addr, get_frame_alias_set ());
7851 insn = emit_insn (gen_move_insn (addr, temp_reg));
7852 }
7853
7854 /* If we support asynchronous exceptions (e.g. for Java),
7855 we need to make sure the backchain pointer is set up
7856 before any possibly trapping memory access. */
7857
7858 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7859 {
7860 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7861 emit_clobber (addr);
7862 }
7863 }
7864
7865 /* Save fprs 8 - 15 (64 bit ABI). */
7866
7867 if (cfun_save_high_fprs_p && next_fpr)
7868 {
7869 /* If the stack might be accessed through a different register
7870 we have to make sure that the stack pointer decrement is not
7871 moved below the use of the stack slots. */
7872 s390_emit_stack_tie ();
7873
7874 insn = emit_insn (gen_add2_insn (temp_reg,
7875 GEN_INT (cfun_frame_layout.f8_offset)));
7876
7877 offset = 0;
7878
7879 for (i = 24; i <= next_fpr; i++)
7880 if (cfun_fpr_bit_p (i - 16))
7881 {
7882 rtx addr = plus_constant (stack_pointer_rtx,
7883 cfun_frame_layout.frame_size
7884 + cfun_frame_layout.f8_offset
7885 + offset);
7886
7887 insn = save_fpr (temp_reg, offset, i);
7888 offset += 8;
7889 RTX_FRAME_RELATED_P (insn) = 1;
7890 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7891 gen_rtx_SET (VOIDmode,
7892 gen_rtx_MEM (DFmode, addr),
7893 gen_rtx_REG (DFmode, i)));
7894 }
7895 }
7896
7897 /* Set frame pointer, if needed. */
7898
7899 if (frame_pointer_needed)
7900 {
7901 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7902 RTX_FRAME_RELATED_P (insn) = 1;
7903 }
7904
7905 /* Set up got pointer, if needed. */
7906
7907 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7908 {
7909 rtx insns = s390_load_got ();
7910
7911 for (insn = insns; insn; insn = NEXT_INSN (insn))
7912 annotate_constant_pool_refs (&PATTERN (insn));
7913
7914 emit_insn (insns);
7915 }
7916
7917 if (TARGET_TPF_PROFILING)
7918 {
7919 /* Generate a BAS instruction to serve as a function
7920 entry intercept to facilitate the use of tracing
7921 algorithms located at the branch target. */
7922 emit_insn (gen_prologue_tpf ());
7923
7924 /* Emit a blockage here so that all code
7925 lies between the profiling mechanisms. */
7926 emit_insn (gen_blockage ());
7927 }
7928 }
7929
7930 /* Expand the epilogue into a bunch of separate insns. */
7931
7932 void
7933 s390_emit_epilogue (bool sibcall)
7934 {
7935 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
7936 int area_bottom, area_top, offset = 0;
7937 int next_offset;
7938 rtvec p;
7939 int i;
7940
7941 if (TARGET_TPF_PROFILING)
7942 {
7943
7944 /* Generate a BAS instruction to serve as a function
7945 entry intercept to facilitate the use of tracing
7946 algorithms located at the branch target. */
7947
7948 /* Emit a blockage here so that all code
7949 lies between the profiling mechanisms. */
7950 emit_insn (gen_blockage ());
7951
7952 emit_insn (gen_epilogue_tpf ());
7953 }
7954
7955 /* Check whether to use frame or stack pointer for restore. */
7956
7957 frame_pointer = (frame_pointer_needed
7958 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7959
7960 s390_frame_area (&area_bottom, &area_top);
7961
7962 /* Check whether we can access the register save area.
7963 If not, increment the frame pointer as required. */
7964
7965 if (area_top <= area_bottom)
7966 {
7967 /* Nothing to restore. */
7968 }
7969 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7970 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7971 {
7972 /* Area is in range. */
7973 offset = cfun_frame_layout.frame_size;
7974 }
7975 else
7976 {
7977 rtx insn, frame_off, cfa;
7978
7979 offset = area_bottom < 0 ? -area_bottom : 0;
7980 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7981
7982 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
7983 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7984 if (DISP_IN_RANGE (INTVAL (frame_off)))
7985 {
7986 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7987 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7988 insn = emit_insn (insn);
7989 }
7990 else
7991 {
7992 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7993 frame_off = force_const_mem (Pmode, frame_off);
7994
7995 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7996 annotate_constant_pool_refs (&PATTERN (insn));
7997 }
7998 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
7999 RTX_FRAME_RELATED_P (insn) = 1;
8000 }
8001
8002 /* Restore call saved fprs. */
8003
8004 if (TARGET_64BIT)
8005 {
8006 if (cfun_save_high_fprs_p)
8007 {
8008 next_offset = cfun_frame_layout.f8_offset;
8009 for (i = 24; i < 32; i++)
8010 {
8011 if (cfun_fpr_bit_p (i - 16))
8012 {
8013 restore_fpr (frame_pointer,
8014 offset + next_offset, i);
8015 cfa_restores
8016 = alloc_reg_note (REG_CFA_RESTORE,
8017 gen_rtx_REG (DFmode, i), cfa_restores);
8018 next_offset += 8;
8019 }
8020 }
8021 }
8022
8023 }
8024 else
8025 {
8026 next_offset = cfun_frame_layout.f4_offset;
8027 for (i = 18; i < 20; i++)
8028 {
8029 if (cfun_fpr_bit_p (i - 16))
8030 {
8031 restore_fpr (frame_pointer,
8032 offset + next_offset, i);
8033 cfa_restores
8034 = alloc_reg_note (REG_CFA_RESTORE,
8035 gen_rtx_REG (DFmode, i), cfa_restores);
8036 next_offset += 8;
8037 }
8038 else if (!TARGET_PACKED_STACK)
8039 next_offset += 8;
8040 }
8041
8042 }
8043
8044 /* Return register. */
8045
8046 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8047
8048 /* Restore call saved gprs. */
8049
8050 if (cfun_frame_layout.first_restore_gpr != -1)
8051 {
8052 rtx insn, addr;
8053 int i;
8054
8055 /* Check for global register and save them
8056 to stack location from where they get restored. */
8057
8058 for (i = cfun_frame_layout.first_restore_gpr;
8059 i <= cfun_frame_layout.last_restore_gpr;
8060 i++)
8061 {
8062 if (global_not_special_regno_p (i))
8063 {
8064 addr = plus_constant (frame_pointer,
8065 offset + cfun_frame_layout.gprs_offset
8066 + (i - cfun_frame_layout.first_save_gpr_slot)
8067 * UNITS_PER_WORD);
8068 addr = gen_rtx_MEM (Pmode, addr);
8069 set_mem_alias_set (addr, get_frame_alias_set ());
8070 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8071 }
8072 else
8073 cfa_restores
8074 = alloc_reg_note (REG_CFA_RESTORE,
8075 gen_rtx_REG (Pmode, i), cfa_restores);
8076 }
8077
8078 if (! sibcall)
8079 {
8080 /* Fetch return address from stack before load multiple,
8081 this will do good for scheduling. */
8082
8083 if (cfun_frame_layout.save_return_addr_p
8084 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8085 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8086 {
8087 int return_regnum = find_unused_clobbered_reg();
8088 if (!return_regnum)
8089 return_regnum = 4;
8090 return_reg = gen_rtx_REG (Pmode, return_regnum);
8091
8092 addr = plus_constant (frame_pointer,
8093 offset + cfun_frame_layout.gprs_offset
8094 + (RETURN_REGNUM
8095 - cfun_frame_layout.first_save_gpr_slot)
8096 * UNITS_PER_WORD);
8097 addr = gen_rtx_MEM (Pmode, addr);
8098 set_mem_alias_set (addr, get_frame_alias_set ());
8099 emit_move_insn (return_reg, addr);
8100 }
8101 }
8102
8103 insn = restore_gprs (frame_pointer,
8104 offset + cfun_frame_layout.gprs_offset
8105 + (cfun_frame_layout.first_restore_gpr
8106 - cfun_frame_layout.first_save_gpr_slot)
8107 * UNITS_PER_WORD,
8108 cfun_frame_layout.first_restore_gpr,
8109 cfun_frame_layout.last_restore_gpr);
8110 insn = emit_insn (insn);
8111 REG_NOTES (insn) = cfa_restores;
8112 add_reg_note (insn, REG_CFA_DEF_CFA,
8113 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8114 RTX_FRAME_RELATED_P (insn) = 1;
8115 }
8116
8117 if (! sibcall)
8118 {
8119
8120 /* Return to caller. */
8121
8122 p = rtvec_alloc (2);
8123
8124 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8125 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8126 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8127 }
8128 }
8129
8130
8131 /* Return the size in bytes of a function argument of
8132 type TYPE and/or mode MODE. At least one of TYPE or
8133 MODE must be specified. */
8134
8135 static int
8136 s390_function_arg_size (enum machine_mode mode, const_tree type)
8137 {
8138 if (type)
8139 return int_size_in_bytes (type);
8140
8141 /* No type info available for some library calls ... */
8142 if (mode != BLKmode)
8143 return GET_MODE_SIZE (mode);
8144
8145 /* If we have neither type nor mode, abort */
8146 gcc_unreachable ();
8147 }
8148
8149 /* Return true if a function argument of type TYPE and mode MODE
8150 is to be passed in a floating-point register, if available. */
8151
8152 static bool
8153 s390_function_arg_float (enum machine_mode mode, tree type)
8154 {
8155 int size = s390_function_arg_size (mode, type);
8156 if (size > 8)
8157 return false;
8158
8159 /* Soft-float changes the ABI: no floating-point registers are used. */
8160 if (TARGET_SOFT_FLOAT)
8161 return false;
8162
8163 /* No type info available for some library calls ... */
8164 if (!type)
8165 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8166
8167 /* The ABI says that record types with a single member are treated
8168 just like that member would be. */
8169 while (TREE_CODE (type) == RECORD_TYPE)
8170 {
8171 tree field, single = NULL_TREE;
8172
8173 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8174 {
8175 if (TREE_CODE (field) != FIELD_DECL)
8176 continue;
8177
8178 if (single == NULL_TREE)
8179 single = TREE_TYPE (field);
8180 else
8181 return false;
8182 }
8183
8184 if (single == NULL_TREE)
8185 return false;
8186 else
8187 type = single;
8188 }
8189
8190 return TREE_CODE (type) == REAL_TYPE;
8191 }
8192
8193 /* Return true if a function argument of type TYPE and mode MODE
8194 is to be passed in an integer register, or a pair of integer
8195 registers, if available. */
8196
8197 static bool
8198 s390_function_arg_integer (enum machine_mode mode, tree type)
8199 {
8200 int size = s390_function_arg_size (mode, type);
8201 if (size > 8)
8202 return false;
8203
8204 /* No type info available for some library calls ... */
8205 if (!type)
8206 return GET_MODE_CLASS (mode) == MODE_INT
8207 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8208
8209 /* We accept small integral (and similar) types. */
8210 if (INTEGRAL_TYPE_P (type)
8211 || POINTER_TYPE_P (type)
8212 || TREE_CODE (type) == OFFSET_TYPE
8213 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8214 return true;
8215
8216 /* We also accept structs of size 1, 2, 4, 8 that are not
8217 passed in floating-point registers. */
8218 if (AGGREGATE_TYPE_P (type)
8219 && exact_log2 (size) >= 0
8220 && !s390_function_arg_float (mode, type))
8221 return true;
8222
8223 return false;
8224 }
8225
8226 /* Return 1 if a function argument of type TYPE and mode MODE
8227 is to be passed by reference. The ABI specifies that only
8228 structures of size 1, 2, 4, or 8 bytes are passed by value,
8229 all other structures (and complex numbers) are passed by
8230 reference. */
8231
8232 static bool
8233 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8234 enum machine_mode mode, const_tree type,
8235 bool named ATTRIBUTE_UNUSED)
8236 {
8237 int size = s390_function_arg_size (mode, type);
8238 if (size > 8)
8239 return true;
8240
8241 if (type)
8242 {
8243 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8244 return 1;
8245
8246 if (TREE_CODE (type) == COMPLEX_TYPE
8247 || TREE_CODE (type) == VECTOR_TYPE)
8248 return 1;
8249 }
8250
8251 return 0;
8252 }
8253
8254 /* Update the data in CUM to advance over an argument of mode MODE and
8255 data type TYPE. (TYPE is null for libcalls where that information
8256 may not be available.). The boolean NAMED specifies whether the
8257 argument is a named argument (as opposed to an unnamed argument
8258 matching an ellipsis). */
8259
8260 void
8261 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8262 tree type, int named ATTRIBUTE_UNUSED)
8263 {
8264 if (s390_function_arg_float (mode, type))
8265 {
8266 cum->fprs += 1;
8267 }
8268 else if (s390_function_arg_integer (mode, type))
8269 {
8270 int size = s390_function_arg_size (mode, type);
8271 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
8272 }
8273 else
8274 gcc_unreachable ();
8275 }
8276
8277 /* Define where to put the arguments to a function.
8278 Value is zero to push the argument on the stack,
8279 or a hard register in which to store the argument.
8280
8281 MODE is the argument's machine mode.
8282 TYPE is the data type of the argument (as a tree).
8283 This is null for libcalls where that information may
8284 not be available.
8285 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8286 the preceding args and about the function being called.
8287 NAMED is nonzero if this argument is a named parameter
8288 (otherwise it is an extra parameter matching an ellipsis).
8289
8290 On S/390, we use general purpose registers 2 through 6 to
8291 pass integer, pointer, and certain structure arguments, and
8292 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8293 to pass floating point arguments. All remaining arguments
8294 are pushed to the stack. */
8295
8296 rtx
8297 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8298 int named ATTRIBUTE_UNUSED)
8299 {
8300 if (s390_function_arg_float (mode, type))
8301 {
8302 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8303 return 0;
8304 else
8305 return gen_rtx_REG (mode, cum->fprs + 16);
8306 }
8307 else if (s390_function_arg_integer (mode, type))
8308 {
8309 int size = s390_function_arg_size (mode, type);
8310 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
8311
8312 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8313 return 0;
8314 else
8315 return gen_rtx_REG (mode, cum->gprs + 2);
8316 }
8317
8318 /* After the real arguments, expand_call calls us once again
8319 with a void_type_node type. Whatever we return here is
8320 passed as operand 2 to the call expanders.
8321
8322 We don't need this feature ... */
8323 else if (type == void_type_node)
8324 return const0_rtx;
8325
8326 gcc_unreachable ();
8327 }
8328
8329 /* Return true if return values of type TYPE should be returned
8330 in a memory buffer whose address is passed by the caller as
8331 hidden first argument. */
8332
8333 static bool
8334 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8335 {
8336 /* We accept small integral (and similar) types. */
8337 if (INTEGRAL_TYPE_P (type)
8338 || POINTER_TYPE_P (type)
8339 || TREE_CODE (type) == OFFSET_TYPE
8340 || TREE_CODE (type) == REAL_TYPE)
8341 return int_size_in_bytes (type) > 8;
8342
8343 /* Aggregates and similar constructs are always returned
8344 in memory. */
8345 if (AGGREGATE_TYPE_P (type)
8346 || TREE_CODE (type) == COMPLEX_TYPE
8347 || TREE_CODE (type) == VECTOR_TYPE)
8348 return true;
8349
8350 /* ??? We get called on all sorts of random stuff from
8351 aggregate_value_p. We can't abort, but it's not clear
8352 what's safe to return. Pretend it's a struct I guess. */
8353 return true;
8354 }
8355
8356 /* Function arguments and return values are promoted to word size. */
8357
8358 static enum machine_mode
8359 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8360 int *punsignedp,
8361 const_tree fntype ATTRIBUTE_UNUSED,
8362 int for_return ATTRIBUTE_UNUSED)
8363 {
8364 if (INTEGRAL_MODE_P (mode)
8365 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
8366 {
8367 if (POINTER_TYPE_P (type))
8368 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8369 return Pmode;
8370 }
8371
8372 return mode;
8373 }
8374
8375 /* Define where to return a (scalar) value of type TYPE.
8376 If TYPE is null, define where to return a (scalar)
8377 value of mode MODE from a libcall. */
8378
8379 rtx
8380 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8381 {
8382 if (type)
8383 {
8384 int unsignedp = TYPE_UNSIGNED (type);
8385 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8386 }
8387
8388 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8389 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8390
8391 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8392 return gen_rtx_REG (mode, 16);
8393 else
8394 return gen_rtx_REG (mode, 2);
8395 }
8396
8397
8398 /* Create and return the va_list datatype.
8399
8400 On S/390, va_list is an array type equivalent to
8401
8402 typedef struct __va_list_tag
8403 {
8404 long __gpr;
8405 long __fpr;
8406 void *__overflow_arg_area;
8407 void *__reg_save_area;
8408 } va_list[1];
8409
8410 where __gpr and __fpr hold the number of general purpose
8411 or floating point arguments used up to now, respectively,
8412 __overflow_arg_area points to the stack location of the
8413 next argument passed on the stack, and __reg_save_area
8414 always points to the start of the register area in the
8415 call frame of the current function. The function prologue
8416 saves all registers used for argument passing into this
8417 area if the function uses variable arguments. */
8418
8419 static tree
8420 s390_build_builtin_va_list (void)
8421 {
8422 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8423
8424 record = lang_hooks.types.make_type (RECORD_TYPE);
8425
8426 type_decl =
8427 build_decl (BUILTINS_LOCATION,
8428 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8429
8430 f_gpr = build_decl (BUILTINS_LOCATION,
8431 FIELD_DECL, get_identifier ("__gpr"),
8432 long_integer_type_node);
8433 f_fpr = build_decl (BUILTINS_LOCATION,
8434 FIELD_DECL, get_identifier ("__fpr"),
8435 long_integer_type_node);
8436 f_ovf = build_decl (BUILTINS_LOCATION,
8437 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8438 ptr_type_node);
8439 f_sav = build_decl (BUILTINS_LOCATION,
8440 FIELD_DECL, get_identifier ("__reg_save_area"),
8441 ptr_type_node);
8442
8443 va_list_gpr_counter_field = f_gpr;
8444 va_list_fpr_counter_field = f_fpr;
8445
8446 DECL_FIELD_CONTEXT (f_gpr) = record;
8447 DECL_FIELD_CONTEXT (f_fpr) = record;
8448 DECL_FIELD_CONTEXT (f_ovf) = record;
8449 DECL_FIELD_CONTEXT (f_sav) = record;
8450
8451 TREE_CHAIN (record) = type_decl;
8452 TYPE_NAME (record) = type_decl;
8453 TYPE_FIELDS (record) = f_gpr;
8454 TREE_CHAIN (f_gpr) = f_fpr;
8455 TREE_CHAIN (f_fpr) = f_ovf;
8456 TREE_CHAIN (f_ovf) = f_sav;
8457
8458 layout_type (record);
8459
8460 /* The correct type is an array type of one element. */
8461 return build_array_type (record, build_index_type (size_zero_node));
8462 }
8463
8464 /* Implement va_start by filling the va_list structure VALIST.
8465 STDARG_P is always true, and ignored.
8466 NEXTARG points to the first anonymous stack argument.
8467
8468 The following global variables are used to initialize
8469 the va_list structure:
8470
8471 crtl->args.info:
8472 holds number of gprs and fprs used for named arguments.
8473 crtl->args.arg_offset_rtx:
8474 holds the offset of the first anonymous stack argument
8475 (relative to the virtual arg pointer). */
8476
8477 static void
8478 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8479 {
8480 HOST_WIDE_INT n_gpr, n_fpr;
8481 int off;
8482 tree f_gpr, f_fpr, f_ovf, f_sav;
8483 tree gpr, fpr, ovf, sav, t;
8484
8485 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8486 f_fpr = TREE_CHAIN (f_gpr);
8487 f_ovf = TREE_CHAIN (f_fpr);
8488 f_sav = TREE_CHAIN (f_ovf);
8489
8490 valist = build_va_arg_indirect_ref (valist);
8491 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8492 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8493 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8494 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8495
8496 /* Count number of gp and fp argument registers used. */
8497
8498 n_gpr = crtl->args.info.gprs;
8499 n_fpr = crtl->args.info.fprs;
8500
8501 if (cfun->va_list_gpr_size)
8502 {
8503 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8504 build_int_cst (NULL_TREE, n_gpr));
8505 TREE_SIDE_EFFECTS (t) = 1;
8506 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8507 }
8508
8509 if (cfun->va_list_fpr_size)
8510 {
8511 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8512 build_int_cst (NULL_TREE, n_fpr));
8513 TREE_SIDE_EFFECTS (t) = 1;
8514 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8515 }
8516
8517 /* Find the overflow area. */
8518 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8519 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8520 {
8521 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8522
8523 off = INTVAL (crtl->args.arg_offset_rtx);
8524 off = off < 0 ? 0 : off;
8525 if (TARGET_DEBUG_ARG)
8526 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8527 (int)n_gpr, (int)n_fpr, off);
8528
8529 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8530
8531 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8532 TREE_SIDE_EFFECTS (t) = 1;
8533 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8534 }
8535
8536 /* Find the register save area. */
8537 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8538 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8539 {
8540 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8541 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8542 size_int (-RETURN_REGNUM * UNITS_PER_WORD));
8543
8544 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8545 TREE_SIDE_EFFECTS (t) = 1;
8546 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8547 }
8548 }
8549
8550 /* Implement va_arg by updating the va_list structure
8551 VALIST as required to retrieve an argument of type
8552 TYPE, and returning that argument.
8553
8554 Generates code equivalent to:
8555
8556 if (integral value) {
8557 if (size <= 4 && args.gpr < 5 ||
8558 size > 4 && args.gpr < 4 )
8559 ret = args.reg_save_area[args.gpr+8]
8560 else
8561 ret = *args.overflow_arg_area++;
8562 } else if (float value) {
8563 if (args.fgpr < 2)
8564 ret = args.reg_save_area[args.fpr+64]
8565 else
8566 ret = *args.overflow_arg_area++;
8567 } else if (aggregate value) {
8568 if (args.gpr < 5)
8569 ret = *args.reg_save_area[args.gpr]
8570 else
8571 ret = **args.overflow_arg_area++;
8572 } */
8573
8574 static tree
8575 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8576 gimple_seq *post_p ATTRIBUTE_UNUSED)
8577 {
8578 tree f_gpr, f_fpr, f_ovf, f_sav;
8579 tree gpr, fpr, ovf, sav, reg, t, u;
8580 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8581 tree lab_false, lab_over, addr;
8582
8583 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8584 f_fpr = TREE_CHAIN (f_gpr);
8585 f_ovf = TREE_CHAIN (f_fpr);
8586 f_sav = TREE_CHAIN (f_ovf);
8587
8588 valist = build_va_arg_indirect_ref (valist);
8589 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8590 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8591 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8592
8593 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8594 both appear on a lhs. */
8595 valist = unshare_expr (valist);
8596 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8597
8598 size = int_size_in_bytes (type);
8599
8600 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8601 {
8602 if (TARGET_DEBUG_ARG)
8603 {
8604 fprintf (stderr, "va_arg: aggregate type");
8605 debug_tree (type);
8606 }
8607
8608 /* Aggregates are passed by reference. */
8609 indirect_p = 1;
8610 reg = gpr;
8611 n_reg = 1;
8612
8613 /* kernel stack layout on 31 bit: It is assumed here that no padding
8614 will be added by s390_frame_info because for va_args always an even
8615 number of gprs has to be saved r15-r2 = 14 regs. */
8616 sav_ofs = 2 * UNITS_PER_WORD;
8617 sav_scale = UNITS_PER_WORD;
8618 size = UNITS_PER_WORD;
8619 max_reg = GP_ARG_NUM_REG - n_reg;
8620 }
8621 else if (s390_function_arg_float (TYPE_MODE (type), type))
8622 {
8623 if (TARGET_DEBUG_ARG)
8624 {
8625 fprintf (stderr, "va_arg: float type");
8626 debug_tree (type);
8627 }
8628
8629 /* FP args go in FP registers, if present. */
8630 indirect_p = 0;
8631 reg = fpr;
8632 n_reg = 1;
8633 sav_ofs = 16 * UNITS_PER_WORD;
8634 sav_scale = 8;
8635 max_reg = FP_ARG_NUM_REG - n_reg;
8636 }
8637 else
8638 {
8639 if (TARGET_DEBUG_ARG)
8640 {
8641 fprintf (stderr, "va_arg: other type");
8642 debug_tree (type);
8643 }
8644
8645 /* Otherwise into GP registers. */
8646 indirect_p = 0;
8647 reg = gpr;
8648 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8649
8650 /* kernel stack layout on 31 bit: It is assumed here that no padding
8651 will be added by s390_frame_info because for va_args always an even
8652 number of gprs has to be saved r15-r2 = 14 regs. */
8653 sav_ofs = 2 * UNITS_PER_WORD;
8654
8655 if (size < UNITS_PER_WORD)
8656 sav_ofs += UNITS_PER_WORD - size;
8657
8658 sav_scale = UNITS_PER_WORD;
8659 max_reg = GP_ARG_NUM_REG - n_reg;
8660 }
8661
8662 /* Pull the value out of the saved registers ... */
8663
8664 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8665 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8666 addr = create_tmp_var (ptr_type_node, "addr");
8667
8668 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8669 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8670 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8671 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8672 gimplify_and_add (t, pre_p);
8673
8674 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8675 size_int (sav_ofs));
8676 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8677 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8678 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8679
8680 gimplify_assign (addr, t, pre_p);
8681
8682 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8683
8684 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8685
8686
8687 /* ... Otherwise out of the overflow area. */
8688
8689 t = ovf;
8690 if (size < UNITS_PER_WORD)
8691 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8692 size_int (UNITS_PER_WORD - size));
8693
8694 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8695
8696 gimplify_assign (addr, t, pre_p);
8697
8698 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8699 size_int (size));
8700 gimplify_assign (ovf, t, pre_p);
8701
8702 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8703
8704
8705 /* Increment register save count. */
8706
8707 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8708 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8709 gimplify_and_add (u, pre_p);
8710
8711 if (indirect_p)
8712 {
8713 t = build_pointer_type_for_mode (build_pointer_type (type),
8714 ptr_mode, true);
8715 addr = fold_convert (t, addr);
8716 addr = build_va_arg_indirect_ref (addr);
8717 }
8718 else
8719 {
8720 t = build_pointer_type_for_mode (type, ptr_mode, true);
8721 addr = fold_convert (t, addr);
8722 }
8723
8724 return build_va_arg_indirect_ref (addr);
8725 }
8726
8727
8728 /* Builtins. */
8729
8730 enum s390_builtin
8731 {
8732 S390_BUILTIN_THREAD_POINTER,
8733 S390_BUILTIN_SET_THREAD_POINTER,
8734
8735 S390_BUILTIN_max
8736 };
8737
8738 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8739 CODE_FOR_get_tp_64,
8740 CODE_FOR_set_tp_64
8741 };
8742
8743 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8744 CODE_FOR_get_tp_31,
8745 CODE_FOR_set_tp_31
8746 };
8747
8748 static void
8749 s390_init_builtins (void)
8750 {
8751 tree ftype;
8752
8753 ftype = build_function_type (ptr_type_node, void_list_node);
8754 add_builtin_function ("__builtin_thread_pointer", ftype,
8755 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8756 NULL, NULL_TREE);
8757
8758 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8759 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8760 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8761 NULL, NULL_TREE);
8762 }
8763
8764 /* Expand an expression EXP that calls a built-in function,
8765 with result going to TARGET if that's convenient
8766 (and in mode MODE if that's convenient).
8767 SUBTARGET may be used as the target for computing one of EXP's operands.
8768 IGNORE is nonzero if the value is to be ignored. */
8769
8770 static rtx
8771 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8772 enum machine_mode mode ATTRIBUTE_UNUSED,
8773 int ignore ATTRIBUTE_UNUSED)
8774 {
8775 #define MAX_ARGS 2
8776
8777 enum insn_code const *code_for_builtin =
8778 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8779
8780 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8781 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8782 enum insn_code icode;
8783 rtx op[MAX_ARGS], pat;
8784 int arity;
8785 bool nonvoid;
8786 tree arg;
8787 call_expr_arg_iterator iter;
8788
8789 if (fcode >= S390_BUILTIN_max)
8790 internal_error ("bad builtin fcode");
8791 icode = code_for_builtin[fcode];
8792 if (icode == 0)
8793 internal_error ("bad builtin fcode");
8794
8795 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8796
8797 arity = 0;
8798 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8799 {
8800 const struct insn_operand_data *insn_op;
8801
8802 if (arg == error_mark_node)
8803 return NULL_RTX;
8804 if (arity > MAX_ARGS)
8805 return NULL_RTX;
8806
8807 insn_op = &insn_data[icode].operand[arity + nonvoid];
8808
8809 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8810
8811 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8812 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8813 arity++;
8814 }
8815
8816 if (nonvoid)
8817 {
8818 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8819 if (!target
8820 || GET_MODE (target) != tmode
8821 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8822 target = gen_reg_rtx (tmode);
8823 }
8824
8825 switch (arity)
8826 {
8827 case 0:
8828 pat = GEN_FCN (icode) (target);
8829 break;
8830 case 1:
8831 if (nonvoid)
8832 pat = GEN_FCN (icode) (target, op[0]);
8833 else
8834 pat = GEN_FCN (icode) (op[0]);
8835 break;
8836 case 2:
8837 pat = GEN_FCN (icode) (target, op[0], op[1]);
8838 break;
8839 default:
8840 gcc_unreachable ();
8841 }
8842 if (!pat)
8843 return NULL_RTX;
8844 emit_insn (pat);
8845
8846 if (nonvoid)
8847 return target;
8848 else
8849 return const0_rtx;
8850 }
8851
8852
8853 /* Output assembly code for the trampoline template to
8854 stdio stream FILE.
8855
8856 On S/390, we use gpr 1 internally in the trampoline code;
8857 gpr 0 is used to hold the static chain. */
8858
8859 void
8860 s390_trampoline_template (FILE *file)
8861 {
8862 rtx op[2];
8863 op[0] = gen_rtx_REG (Pmode, 0);
8864 op[1] = gen_rtx_REG (Pmode, 1);
8865
8866 if (TARGET_64BIT)
8867 {
8868 output_asm_insn ("basr\t%1,0", op);
8869 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8870 output_asm_insn ("br\t%1", op);
8871 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8872 }
8873 else
8874 {
8875 output_asm_insn ("basr\t%1,0", op);
8876 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8877 output_asm_insn ("br\t%1", op);
8878 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8879 }
8880 }
8881
8882 /* Emit RTL insns to initialize the variable parts of a trampoline.
8883 FNADDR is an RTX for the address of the function's pure code.
8884 CXT is an RTX for the static chain value for the function. */
8885
8886 void
8887 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8888 {
8889 emit_move_insn (gen_rtx_MEM (Pmode,
8890 memory_address (Pmode,
8891 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8892 emit_move_insn (gen_rtx_MEM (Pmode,
8893 memory_address (Pmode,
8894 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8895 }
8896
8897 /* Output assembler code to FILE to increment profiler label # LABELNO
8898 for profiling a function entry. */
8899
8900 void
8901 s390_function_profiler (FILE *file, int labelno)
8902 {
8903 rtx op[7];
8904
8905 char label[128];
8906 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8907
8908 fprintf (file, "# function profiler \n");
8909
8910 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8911 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8912 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8913
8914 op[2] = gen_rtx_REG (Pmode, 1);
8915 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8916 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8917
8918 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8919 if (flag_pic)
8920 {
8921 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8922 op[4] = gen_rtx_CONST (Pmode, op[4]);
8923 }
8924
8925 if (TARGET_64BIT)
8926 {
8927 output_asm_insn ("stg\t%0,%1", op);
8928 output_asm_insn ("larl\t%2,%3", op);
8929 output_asm_insn ("brasl\t%0,%4", op);
8930 output_asm_insn ("lg\t%0,%1", op);
8931 }
8932 else if (!flag_pic)
8933 {
8934 op[6] = gen_label_rtx ();
8935
8936 output_asm_insn ("st\t%0,%1", op);
8937 output_asm_insn ("bras\t%2,%l6", op);
8938 output_asm_insn (".long\t%4", op);
8939 output_asm_insn (".long\t%3", op);
8940 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8941 output_asm_insn ("l\t%0,0(%2)", op);
8942 output_asm_insn ("l\t%2,4(%2)", op);
8943 output_asm_insn ("basr\t%0,%0", op);
8944 output_asm_insn ("l\t%0,%1", op);
8945 }
8946 else
8947 {
8948 op[5] = gen_label_rtx ();
8949 op[6] = gen_label_rtx ();
8950
8951 output_asm_insn ("st\t%0,%1", op);
8952 output_asm_insn ("bras\t%2,%l6", op);
8953 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8954 output_asm_insn (".long\t%4-%l5", op);
8955 output_asm_insn (".long\t%3-%l5", op);
8956 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8957 output_asm_insn ("lr\t%0,%2", op);
8958 output_asm_insn ("a\t%0,0(%2)", op);
8959 output_asm_insn ("a\t%2,4(%2)", op);
8960 output_asm_insn ("basr\t%0,%0", op);
8961 output_asm_insn ("l\t%0,%1", op);
8962 }
8963 }
8964
8965 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8966 into its SYMBOL_REF_FLAGS. */
8967
8968 static void
8969 s390_encode_section_info (tree decl, rtx rtl, int first)
8970 {
8971 default_encode_section_info (decl, rtl, first);
8972
8973 if (TREE_CODE (decl) == VAR_DECL)
8974 {
8975 /* If a variable has a forced alignment to < 2 bytes, mark it
8976 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
8977 operand. */
8978 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8979 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8980 if (!DECL_SIZE (decl)
8981 || !DECL_ALIGN (decl)
8982 || !host_integerp (DECL_SIZE (decl), 0)
8983 || (DECL_ALIGN (decl) <= 64
8984 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
8985 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8986 }
8987
8988 /* Literal pool references don't have a decl so they are handled
8989 differently here. We rely on the information in the MEM_ALIGN
8990 entry to decide upon natural alignment. */
8991 if (MEM_P (rtl)
8992 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
8993 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
8994 && (MEM_ALIGN (rtl) == 0
8995 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
8996 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8997 }
8998
8999 /* Output thunk to FILE that implements a C++ virtual function call (with
9000 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9001 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9002 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9003 relative to the resulting this pointer. */
9004
9005 static void
9006 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9007 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9008 tree function)
9009 {
9010 rtx op[10];
9011 int nonlocal = 0;
9012
9013 /* Operand 0 is the target function. */
9014 op[0] = XEXP (DECL_RTL (function), 0);
9015 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9016 {
9017 nonlocal = 1;
9018 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9019 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9020 op[0] = gen_rtx_CONST (Pmode, op[0]);
9021 }
9022
9023 /* Operand 1 is the 'this' pointer. */
9024 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9025 op[1] = gen_rtx_REG (Pmode, 3);
9026 else
9027 op[1] = gen_rtx_REG (Pmode, 2);
9028
9029 /* Operand 2 is the delta. */
9030 op[2] = GEN_INT (delta);
9031
9032 /* Operand 3 is the vcall_offset. */
9033 op[3] = GEN_INT (vcall_offset);
9034
9035 /* Operand 4 is the temporary register. */
9036 op[4] = gen_rtx_REG (Pmode, 1);
9037
9038 /* Operands 5 to 8 can be used as labels. */
9039 op[5] = NULL_RTX;
9040 op[6] = NULL_RTX;
9041 op[7] = NULL_RTX;
9042 op[8] = NULL_RTX;
9043
9044 /* Operand 9 can be used for temporary register. */
9045 op[9] = NULL_RTX;
9046
9047 /* Generate code. */
9048 if (TARGET_64BIT)
9049 {
9050 /* Setup literal pool pointer if required. */
9051 if ((!DISP_IN_RANGE (delta)
9052 && !CONST_OK_FOR_K (delta)
9053 && !CONST_OK_FOR_Os (delta))
9054 || (!DISP_IN_RANGE (vcall_offset)
9055 && !CONST_OK_FOR_K (vcall_offset)
9056 && !CONST_OK_FOR_Os (vcall_offset)))
9057 {
9058 op[5] = gen_label_rtx ();
9059 output_asm_insn ("larl\t%4,%5", op);
9060 }
9061
9062 /* Add DELTA to this pointer. */
9063 if (delta)
9064 {
9065 if (CONST_OK_FOR_J (delta))
9066 output_asm_insn ("la\t%1,%2(%1)", op);
9067 else if (DISP_IN_RANGE (delta))
9068 output_asm_insn ("lay\t%1,%2(%1)", op);
9069 else if (CONST_OK_FOR_K (delta))
9070 output_asm_insn ("aghi\t%1,%2", op);
9071 else if (CONST_OK_FOR_Os (delta))
9072 output_asm_insn ("agfi\t%1,%2", op);
9073 else
9074 {
9075 op[6] = gen_label_rtx ();
9076 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9077 }
9078 }
9079
9080 /* Perform vcall adjustment. */
9081 if (vcall_offset)
9082 {
9083 if (DISP_IN_RANGE (vcall_offset))
9084 {
9085 output_asm_insn ("lg\t%4,0(%1)", op);
9086 output_asm_insn ("ag\t%1,%3(%4)", op);
9087 }
9088 else if (CONST_OK_FOR_K (vcall_offset))
9089 {
9090 output_asm_insn ("lghi\t%4,%3", op);
9091 output_asm_insn ("ag\t%4,0(%1)", op);
9092 output_asm_insn ("ag\t%1,0(%4)", op);
9093 }
9094 else if (CONST_OK_FOR_Os (vcall_offset))
9095 {
9096 output_asm_insn ("lgfi\t%4,%3", op);
9097 output_asm_insn ("ag\t%4,0(%1)", op);
9098 output_asm_insn ("ag\t%1,0(%4)", op);
9099 }
9100 else
9101 {
9102 op[7] = gen_label_rtx ();
9103 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9104 output_asm_insn ("ag\t%4,0(%1)", op);
9105 output_asm_insn ("ag\t%1,0(%4)", op);
9106 }
9107 }
9108
9109 /* Jump to target. */
9110 output_asm_insn ("jg\t%0", op);
9111
9112 /* Output literal pool if required. */
9113 if (op[5])
9114 {
9115 output_asm_insn (".align\t4", op);
9116 targetm.asm_out.internal_label (file, "L",
9117 CODE_LABEL_NUMBER (op[5]));
9118 }
9119 if (op[6])
9120 {
9121 targetm.asm_out.internal_label (file, "L",
9122 CODE_LABEL_NUMBER (op[6]));
9123 output_asm_insn (".long\t%2", op);
9124 }
9125 if (op[7])
9126 {
9127 targetm.asm_out.internal_label (file, "L",
9128 CODE_LABEL_NUMBER (op[7]));
9129 output_asm_insn (".long\t%3", op);
9130 }
9131 }
9132 else
9133 {
9134 /* Setup base pointer if required. */
9135 if (!vcall_offset
9136 || (!DISP_IN_RANGE (delta)
9137 && !CONST_OK_FOR_K (delta)
9138 && !CONST_OK_FOR_Os (delta))
9139 || (!DISP_IN_RANGE (delta)
9140 && !CONST_OK_FOR_K (vcall_offset)
9141 && !CONST_OK_FOR_Os (vcall_offset)))
9142 {
9143 op[5] = gen_label_rtx ();
9144 output_asm_insn ("basr\t%4,0", op);
9145 targetm.asm_out.internal_label (file, "L",
9146 CODE_LABEL_NUMBER (op[5]));
9147 }
9148
9149 /* Add DELTA to this pointer. */
9150 if (delta)
9151 {
9152 if (CONST_OK_FOR_J (delta))
9153 output_asm_insn ("la\t%1,%2(%1)", op);
9154 else if (DISP_IN_RANGE (delta))
9155 output_asm_insn ("lay\t%1,%2(%1)", op);
9156 else if (CONST_OK_FOR_K (delta))
9157 output_asm_insn ("ahi\t%1,%2", op);
9158 else if (CONST_OK_FOR_Os (delta))
9159 output_asm_insn ("afi\t%1,%2", op);
9160 else
9161 {
9162 op[6] = gen_label_rtx ();
9163 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9164 }
9165 }
9166
9167 /* Perform vcall adjustment. */
9168 if (vcall_offset)
9169 {
9170 if (CONST_OK_FOR_J (vcall_offset))
9171 {
9172 output_asm_insn ("l\t%4,0(%1)", op);
9173 output_asm_insn ("a\t%1,%3(%4)", op);
9174 }
9175 else if (DISP_IN_RANGE (vcall_offset))
9176 {
9177 output_asm_insn ("l\t%4,0(%1)", op);
9178 output_asm_insn ("ay\t%1,%3(%4)", op);
9179 }
9180 else if (CONST_OK_FOR_K (vcall_offset))
9181 {
9182 output_asm_insn ("lhi\t%4,%3", op);
9183 output_asm_insn ("a\t%4,0(%1)", op);
9184 output_asm_insn ("a\t%1,0(%4)", op);
9185 }
9186 else if (CONST_OK_FOR_Os (vcall_offset))
9187 {
9188 output_asm_insn ("iilf\t%4,%3", op);
9189 output_asm_insn ("a\t%4,0(%1)", op);
9190 output_asm_insn ("a\t%1,0(%4)", op);
9191 }
9192 else
9193 {
9194 op[7] = gen_label_rtx ();
9195 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9196 output_asm_insn ("a\t%4,0(%1)", op);
9197 output_asm_insn ("a\t%1,0(%4)", op);
9198 }
9199
9200 /* We had to clobber the base pointer register.
9201 Re-setup the base pointer (with a different base). */
9202 op[5] = gen_label_rtx ();
9203 output_asm_insn ("basr\t%4,0", op);
9204 targetm.asm_out.internal_label (file, "L",
9205 CODE_LABEL_NUMBER (op[5]));
9206 }
9207
9208 /* Jump to target. */
9209 op[8] = gen_label_rtx ();
9210
9211 if (!flag_pic)
9212 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9213 else if (!nonlocal)
9214 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9215 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9216 else if (flag_pic == 1)
9217 {
9218 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9219 output_asm_insn ("l\t%4,%0(%4)", op);
9220 }
9221 else if (flag_pic == 2)
9222 {
9223 op[9] = gen_rtx_REG (Pmode, 0);
9224 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9225 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9226 output_asm_insn ("ar\t%4,%9", op);
9227 output_asm_insn ("l\t%4,0(%4)", op);
9228 }
9229
9230 output_asm_insn ("br\t%4", op);
9231
9232 /* Output literal pool. */
9233 output_asm_insn (".align\t4", op);
9234
9235 if (nonlocal && flag_pic == 2)
9236 output_asm_insn (".long\t%0", op);
9237 if (nonlocal)
9238 {
9239 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9240 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9241 }
9242
9243 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9244 if (!flag_pic)
9245 output_asm_insn (".long\t%0", op);
9246 else
9247 output_asm_insn (".long\t%0-%5", op);
9248
9249 if (op[6])
9250 {
9251 targetm.asm_out.internal_label (file, "L",
9252 CODE_LABEL_NUMBER (op[6]));
9253 output_asm_insn (".long\t%2", op);
9254 }
9255 if (op[7])
9256 {
9257 targetm.asm_out.internal_label (file, "L",
9258 CODE_LABEL_NUMBER (op[7]));
9259 output_asm_insn (".long\t%3", op);
9260 }
9261 }
9262 }
9263
9264 static bool
9265 s390_valid_pointer_mode (enum machine_mode mode)
9266 {
9267 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9268 }
9269
9270 /* Checks whether the given CALL_EXPR would use a caller
9271 saved register. This is used to decide whether sibling call
9272 optimization could be performed on the respective function
9273 call. */
9274
9275 static bool
9276 s390_call_saved_register_used (tree call_expr)
9277 {
9278 CUMULATIVE_ARGS cum;
9279 tree parameter;
9280 enum machine_mode mode;
9281 tree type;
9282 rtx parm_rtx;
9283 int reg, i;
9284
9285 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9286
9287 for (i = 0; i < call_expr_nargs (call_expr); i++)
9288 {
9289 parameter = CALL_EXPR_ARG (call_expr, i);
9290 gcc_assert (parameter);
9291
9292 /* For an undeclared variable passed as parameter we will get
9293 an ERROR_MARK node here. */
9294 if (TREE_CODE (parameter) == ERROR_MARK)
9295 return true;
9296
9297 type = TREE_TYPE (parameter);
9298 gcc_assert (type);
9299
9300 mode = TYPE_MODE (type);
9301 gcc_assert (mode);
9302
9303 if (pass_by_reference (&cum, mode, type, true))
9304 {
9305 mode = Pmode;
9306 type = build_pointer_type (type);
9307 }
9308
9309 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9310
9311 s390_function_arg_advance (&cum, mode, type, 0);
9312
9313 if (parm_rtx && REG_P (parm_rtx))
9314 {
9315 for (reg = 0;
9316 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9317 reg++)
9318 if (! call_used_regs[reg + REGNO (parm_rtx)])
9319 return true;
9320 }
9321 }
9322 return false;
9323 }
9324
9325 /* Return true if the given call expression can be
9326 turned into a sibling call.
9327 DECL holds the declaration of the function to be called whereas
9328 EXP is the call expression itself. */
9329
9330 static bool
9331 s390_function_ok_for_sibcall (tree decl, tree exp)
9332 {
9333 /* The TPF epilogue uses register 1. */
9334 if (TARGET_TPF_PROFILING)
9335 return false;
9336
9337 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9338 which would have to be restored before the sibcall. */
9339 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9340 return false;
9341
9342 /* Register 6 on s390 is available as an argument register but unfortunately
9343 "caller saved". This makes functions needing this register for arguments
9344 not suitable for sibcalls. */
9345 return !s390_call_saved_register_used (exp);
9346 }
9347
9348 /* Return the fixed registers used for condition codes. */
9349
9350 static bool
9351 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9352 {
9353 *p1 = CC_REGNUM;
9354 *p2 = INVALID_REGNUM;
9355
9356 return true;
9357 }
9358
9359 /* This function is used by the call expanders of the machine description.
9360 It emits the call insn itself together with the necessary operations
9361 to adjust the target address and returns the emitted insn.
9362 ADDR_LOCATION is the target address rtx
9363 TLS_CALL the location of the thread-local symbol
9364 RESULT_REG the register where the result of the call should be stored
9365 RETADDR_REG the register where the return address should be stored
9366 If this parameter is NULL_RTX the call is considered
9367 to be a sibling call. */
9368
9369 rtx
9370 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9371 rtx retaddr_reg)
9372 {
9373 bool plt_call = false;
9374 rtx insn;
9375 rtx call;
9376 rtx clobber;
9377 rtvec vec;
9378
9379 /* Direct function calls need special treatment. */
9380 if (GET_CODE (addr_location) == SYMBOL_REF)
9381 {
9382 /* When calling a global routine in PIC mode, we must
9383 replace the symbol itself with the PLT stub. */
9384 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9385 {
9386 addr_location = gen_rtx_UNSPEC (Pmode,
9387 gen_rtvec (1, addr_location),
9388 UNSPEC_PLT);
9389 addr_location = gen_rtx_CONST (Pmode, addr_location);
9390 plt_call = true;
9391 }
9392
9393 /* Unless we can use the bras(l) insn, force the
9394 routine address into a register. */
9395 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9396 {
9397 if (flag_pic)
9398 addr_location = legitimize_pic_address (addr_location, 0);
9399 else
9400 addr_location = force_reg (Pmode, addr_location);
9401 }
9402 }
9403
9404 /* If it is already an indirect call or the code above moved the
9405 SYMBOL_REF to somewhere else make sure the address can be found in
9406 register 1. */
9407 if (retaddr_reg == NULL_RTX
9408 && GET_CODE (addr_location) != SYMBOL_REF
9409 && !plt_call)
9410 {
9411 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9412 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9413 }
9414
9415 addr_location = gen_rtx_MEM (QImode, addr_location);
9416 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9417
9418 if (result_reg != NULL_RTX)
9419 call = gen_rtx_SET (VOIDmode, result_reg, call);
9420
9421 if (retaddr_reg != NULL_RTX)
9422 {
9423 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9424
9425 if (tls_call != NULL_RTX)
9426 vec = gen_rtvec (3, call, clobber,
9427 gen_rtx_USE (VOIDmode, tls_call));
9428 else
9429 vec = gen_rtvec (2, call, clobber);
9430
9431 call = gen_rtx_PARALLEL (VOIDmode, vec);
9432 }
9433
9434 insn = emit_call_insn (call);
9435
9436 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9437 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9438 {
9439 /* s390_function_ok_for_sibcall should
9440 have denied sibcalls in this case. */
9441 gcc_assert (retaddr_reg != NULL_RTX);
9442
9443 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9444 }
9445 return insn;
9446 }
9447
9448 /* Implement CONDITIONAL_REGISTER_USAGE. */
9449
9450 void
9451 s390_conditional_register_usage (void)
9452 {
9453 int i;
9454
9455 if (flag_pic)
9456 {
9457 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9458 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9459 }
9460 if (TARGET_CPU_ZARCH)
9461 {
9462 fixed_regs[BASE_REGNUM] = 0;
9463 call_used_regs[BASE_REGNUM] = 0;
9464 fixed_regs[RETURN_REGNUM] = 0;
9465 call_used_regs[RETURN_REGNUM] = 0;
9466 }
9467 if (TARGET_64BIT)
9468 {
9469 for (i = 24; i < 32; i++)
9470 call_used_regs[i] = call_really_used_regs[i] = 0;
9471 }
9472 else
9473 {
9474 for (i = 18; i < 20; i++)
9475 call_used_regs[i] = call_really_used_regs[i] = 0;
9476 }
9477
9478 if (TARGET_SOFT_FLOAT)
9479 {
9480 for (i = 16; i < 32; i++)
9481 call_used_regs[i] = fixed_regs[i] = 1;
9482 }
9483 }
9484
9485 /* Corresponding function to eh_return expander. */
9486
9487 static GTY(()) rtx s390_tpf_eh_return_symbol;
9488 void
9489 s390_emit_tpf_eh_return (rtx target)
9490 {
9491 rtx insn, reg;
9492
9493 if (!s390_tpf_eh_return_symbol)
9494 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9495
9496 reg = gen_rtx_REG (Pmode, 2);
9497
9498 emit_move_insn (reg, target);
9499 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9500 gen_rtx_REG (Pmode, RETURN_REGNUM));
9501 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9502
9503 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9504 }
9505
9506 /* Rework the prologue/epilogue to avoid saving/restoring
9507 registers unnecessarily. */
9508
9509 static void
9510 s390_optimize_prologue (void)
9511 {
9512 rtx insn, new_insn, next_insn;
9513
9514 /* Do a final recompute of the frame-related data. */
9515
9516 s390_update_frame_layout ();
9517
9518 /* If all special registers are in fact used, there's nothing we
9519 can do, so no point in walking the insn list. */
9520
9521 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9522 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9523 && (TARGET_CPU_ZARCH
9524 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9525 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9526 return;
9527
9528 /* Search for prologue/epilogue insns and replace them. */
9529
9530 for (insn = get_insns (); insn; insn = next_insn)
9531 {
9532 int first, last, off;
9533 rtx set, base, offset;
9534
9535 next_insn = NEXT_INSN (insn);
9536
9537 if (GET_CODE (insn) != INSN)
9538 continue;
9539
9540 if (GET_CODE (PATTERN (insn)) == PARALLEL
9541 && store_multiple_operation (PATTERN (insn), VOIDmode))
9542 {
9543 set = XVECEXP (PATTERN (insn), 0, 0);
9544 first = REGNO (SET_SRC (set));
9545 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9546 offset = const0_rtx;
9547 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9548 off = INTVAL (offset);
9549
9550 if (GET_CODE (base) != REG || off < 0)
9551 continue;
9552 if (cfun_frame_layout.first_save_gpr != -1
9553 && (cfun_frame_layout.first_save_gpr < first
9554 || cfun_frame_layout.last_save_gpr > last))
9555 continue;
9556 if (REGNO (base) != STACK_POINTER_REGNUM
9557 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9558 continue;
9559 if (first > BASE_REGNUM || last < BASE_REGNUM)
9560 continue;
9561
9562 if (cfun_frame_layout.first_save_gpr != -1)
9563 {
9564 new_insn = save_gprs (base,
9565 off + (cfun_frame_layout.first_save_gpr
9566 - first) * UNITS_PER_WORD,
9567 cfun_frame_layout.first_save_gpr,
9568 cfun_frame_layout.last_save_gpr);
9569 new_insn = emit_insn_before (new_insn, insn);
9570 INSN_ADDRESSES_NEW (new_insn, -1);
9571 }
9572
9573 remove_insn (insn);
9574 continue;
9575 }
9576
9577 if (cfun_frame_layout.first_save_gpr == -1
9578 && GET_CODE (PATTERN (insn)) == SET
9579 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9580 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9581 || (!TARGET_CPU_ZARCH
9582 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9583 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9584 {
9585 set = PATTERN (insn);
9586 first = REGNO (SET_SRC (set));
9587 offset = const0_rtx;
9588 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9589 off = INTVAL (offset);
9590
9591 if (GET_CODE (base) != REG || off < 0)
9592 continue;
9593 if (REGNO (base) != STACK_POINTER_REGNUM
9594 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9595 continue;
9596
9597 remove_insn (insn);
9598 continue;
9599 }
9600
9601 if (GET_CODE (PATTERN (insn)) == PARALLEL
9602 && load_multiple_operation (PATTERN (insn), VOIDmode))
9603 {
9604 set = XVECEXP (PATTERN (insn), 0, 0);
9605 first = REGNO (SET_DEST (set));
9606 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9607 offset = const0_rtx;
9608 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9609 off = INTVAL (offset);
9610
9611 if (GET_CODE (base) != REG || off < 0)
9612 continue;
9613 if (cfun_frame_layout.first_restore_gpr != -1
9614 && (cfun_frame_layout.first_restore_gpr < first
9615 || cfun_frame_layout.last_restore_gpr > last))
9616 continue;
9617 if (REGNO (base) != STACK_POINTER_REGNUM
9618 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9619 continue;
9620 if (first > BASE_REGNUM || last < BASE_REGNUM)
9621 continue;
9622
9623 if (cfun_frame_layout.first_restore_gpr != -1)
9624 {
9625 new_insn = restore_gprs (base,
9626 off + (cfun_frame_layout.first_restore_gpr
9627 - first) * UNITS_PER_WORD,
9628 cfun_frame_layout.first_restore_gpr,
9629 cfun_frame_layout.last_restore_gpr);
9630 new_insn = emit_insn_before (new_insn, insn);
9631 INSN_ADDRESSES_NEW (new_insn, -1);
9632 }
9633
9634 remove_insn (insn);
9635 continue;
9636 }
9637
9638 if (cfun_frame_layout.first_restore_gpr == -1
9639 && GET_CODE (PATTERN (insn)) == SET
9640 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9641 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9642 || (!TARGET_CPU_ZARCH
9643 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9644 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9645 {
9646 set = PATTERN (insn);
9647 first = REGNO (SET_DEST (set));
9648 offset = const0_rtx;
9649 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9650 off = INTVAL (offset);
9651
9652 if (GET_CODE (base) != REG || off < 0)
9653 continue;
9654 if (REGNO (base) != STACK_POINTER_REGNUM
9655 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9656 continue;
9657
9658 remove_insn (insn);
9659 continue;
9660 }
9661 }
9662 }
9663
9664 /* Returns 1 if INSN reads the value of REG for purposes not related
9665 to addressing of memory, and 0 otherwise. */
9666 static int
9667 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9668 {
9669 return reg_referenced_p (reg, PATTERN (insn))
9670 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9671 }
9672
9673 /* Starting from INSN find_cond_jump looks downwards in the insn
9674 stream for a single jump insn which is the last user of the
9675 condition code set in INSN. */
9676 static rtx
9677 find_cond_jump (rtx insn)
9678 {
9679 for (; insn; insn = NEXT_INSN (insn))
9680 {
9681 rtx ite, cc;
9682
9683 if (LABEL_P (insn))
9684 break;
9685
9686 if (!JUMP_P (insn))
9687 {
9688 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9689 break;
9690 continue;
9691 }
9692
9693 /* This will be triggered by a return. */
9694 if (GET_CODE (PATTERN (insn)) != SET)
9695 break;
9696
9697 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9698 ite = SET_SRC (PATTERN (insn));
9699
9700 if (GET_CODE (ite) != IF_THEN_ELSE)
9701 break;
9702
9703 cc = XEXP (XEXP (ite, 0), 0);
9704 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9705 break;
9706
9707 if (find_reg_note (insn, REG_DEAD, cc))
9708 return insn;
9709 break;
9710 }
9711
9712 return NULL_RTX;
9713 }
9714
9715 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9716 the semantics does not change. If NULL_RTX is passed as COND the
9717 function tries to find the conditional jump starting with INSN. */
9718 static void
9719 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9720 {
9721 rtx tmp = *op0;
9722
9723 if (cond == NULL_RTX)
9724 {
9725 rtx jump = find_cond_jump (NEXT_INSN (insn));
9726 jump = jump ? single_set (jump) : NULL_RTX;
9727
9728 if (jump == NULL_RTX)
9729 return;
9730
9731 cond = XEXP (XEXP (jump, 1), 0);
9732 }
9733
9734 *op0 = *op1;
9735 *op1 = tmp;
9736 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9737 }
9738
9739 /* On z10, instructions of the compare-and-branch family have the
9740 property to access the register occurring as second operand with
9741 its bits complemented. If such a compare is grouped with a second
9742 instruction that accesses the same register non-complemented, and
9743 if that register's value is delivered via a bypass, then the
9744 pipeline recycles, thereby causing significant performance decline.
9745 This function locates such situations and exchanges the two
9746 operands of the compare. */
9747 static void
9748 s390_z10_optimize_cmp (void)
9749 {
9750 rtx insn, prev_insn, next_insn;
9751 int added_NOPs = 0;
9752
9753 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9754 {
9755 rtx cond, *op0, *op1;
9756
9757 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
9758 continue;
9759
9760 if (GET_CODE (PATTERN (insn)) == PARALLEL)
9761 {
9762 /* Handle compare and branch and branch on count
9763 instructions. */
9764 rtx pattern = single_set (insn);
9765
9766 if (!pattern
9767 || SET_DEST (pattern) != pc_rtx
9768 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
9769 continue;
9770
9771 cond = XEXP (SET_SRC (pattern), 0);
9772 op0 = &XEXP (cond, 0);
9773 op1 = &XEXP (cond, 1);
9774 }
9775 else if (GET_CODE (PATTERN (insn)) == SET)
9776 {
9777 rtx src, dest;
9778
9779 /* Handle normal compare instructions. */
9780 src = SET_SRC (PATTERN (insn));
9781 dest = SET_DEST (PATTERN (insn));
9782
9783 if (!REG_P (dest)
9784 || !CC_REGNO_P (REGNO (dest))
9785 || GET_CODE (src) != COMPARE)
9786 continue;
9787
9788 /* s390_swap_cmp will try to find the conditional
9789 jump when passing NULL_RTX as condition. */
9790 cond = NULL_RTX;
9791 op0 = &XEXP (src, 0);
9792 op1 = &XEXP (src, 1);
9793 }
9794 else
9795 continue;
9796
9797 if (!REG_P (*op0) || !REG_P (*op1))
9798 continue;
9799
9800 /* Swap the COMPARE arguments and its mask if there is a
9801 conflicting access in the previous insn. */
9802 prev_insn = PREV_INSN (insn);
9803 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9804 && reg_referenced_p (*op1, PATTERN (prev_insn)))
9805 s390_swap_cmp (cond, op0, op1, insn);
9806
9807 /* Check if there is a conflict with the next insn. If there
9808 was no conflict with the previous insn, then swap the
9809 COMPARE arguments and its mask. If we already swapped
9810 the operands, or if swapping them would cause a conflict
9811 with the previous insn, issue a NOP after the COMPARE in
9812 order to separate the two instuctions. */
9813 next_insn = NEXT_INSN (insn);
9814 if (next_insn != NULL_RTX && INSN_P (next_insn)
9815 && s390_non_addr_reg_read_p (*op1, next_insn))
9816 {
9817 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9818 && s390_non_addr_reg_read_p (*op0, prev_insn))
9819 {
9820 if (REGNO (*op1) == 0)
9821 emit_insn_after (gen_nop1 (), insn);
9822 else
9823 emit_insn_after (gen_nop (), insn);
9824 added_NOPs = 1;
9825 }
9826 else
9827 s390_swap_cmp (cond, op0, op1, insn);
9828 }
9829 }
9830
9831 /* Adjust branches if we added new instructions. */
9832 if (added_NOPs)
9833 shorten_branches (get_insns ());
9834 }
9835
9836
9837 /* Perform machine-dependent processing. */
9838
9839 static void
9840 s390_reorg (void)
9841 {
9842 bool pool_overflow = false;
9843
9844 /* Make sure all splits have been performed; splits after
9845 machine_dependent_reorg might confuse insn length counts. */
9846 split_all_insns_noflow ();
9847
9848 /* Install the main literal pool and the associated base
9849 register load insns.
9850
9851 In addition, there are two problematic situations we need
9852 to correct:
9853
9854 - the literal pool might be > 4096 bytes in size, so that
9855 some of its elements cannot be directly accessed
9856
9857 - a branch target might be > 64K away from the branch, so that
9858 it is not possible to use a PC-relative instruction.
9859
9860 To fix those, we split the single literal pool into multiple
9861 pool chunks, reloading the pool base register at various
9862 points throughout the function to ensure it always points to
9863 the pool chunk the following code expects, and / or replace
9864 PC-relative branches by absolute branches.
9865
9866 However, the two problems are interdependent: splitting the
9867 literal pool can move a branch further away from its target,
9868 causing the 64K limit to overflow, and on the other hand,
9869 replacing a PC-relative branch by an absolute branch means
9870 we need to put the branch target address into the literal
9871 pool, possibly causing it to overflow.
9872
9873 So, we loop trying to fix up both problems until we manage
9874 to satisfy both conditions at the same time. Note that the
9875 loop is guaranteed to terminate as every pass of the loop
9876 strictly decreases the total number of PC-relative branches
9877 in the function. (This is not completely true as there
9878 might be branch-over-pool insns introduced by chunkify_start.
9879 Those never need to be split however.) */
9880
9881 for (;;)
9882 {
9883 struct constant_pool *pool = NULL;
9884
9885 /* Collect the literal pool. */
9886 if (!pool_overflow)
9887 {
9888 pool = s390_mainpool_start ();
9889 if (!pool)
9890 pool_overflow = true;
9891 }
9892
9893 /* If literal pool overflowed, start to chunkify it. */
9894 if (pool_overflow)
9895 pool = s390_chunkify_start ();
9896
9897 /* Split out-of-range branches. If this has created new
9898 literal pool entries, cancel current chunk list and
9899 recompute it. zSeries machines have large branch
9900 instructions, so we never need to split a branch. */
9901 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9902 {
9903 if (pool_overflow)
9904 s390_chunkify_cancel (pool);
9905 else
9906 s390_mainpool_cancel (pool);
9907
9908 continue;
9909 }
9910
9911 /* If we made it up to here, both conditions are satisfied.
9912 Finish up literal pool related changes. */
9913 if (pool_overflow)
9914 s390_chunkify_finish (pool);
9915 else
9916 s390_mainpool_finish (pool);
9917
9918 /* We're done splitting branches. */
9919 cfun->machine->split_branches_pending_p = false;
9920 break;
9921 }
9922
9923 /* Generate out-of-pool execute target insns. */
9924 if (TARGET_CPU_ZARCH)
9925 {
9926 rtx insn, label, target;
9927
9928 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9929 {
9930 label = s390_execute_label (insn);
9931 if (!label)
9932 continue;
9933
9934 gcc_assert (label != const0_rtx);
9935
9936 target = emit_label (XEXP (label, 0));
9937 INSN_ADDRESSES_NEW (target, -1);
9938
9939 target = emit_insn (s390_execute_target (insn));
9940 INSN_ADDRESSES_NEW (target, -1);
9941 }
9942 }
9943
9944 /* Try to optimize prologue and epilogue further. */
9945 s390_optimize_prologue ();
9946
9947 /* Eliminate z10-specific pipeline recycles related to some compare
9948 instructions. */
9949 if (s390_tune == PROCESSOR_2097_Z10)
9950 s390_z10_optimize_cmp ();
9951 }
9952
9953
9954 /* Initialize GCC target structure. */
9955
9956 #undef TARGET_ASM_ALIGNED_HI_OP
9957 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9958 #undef TARGET_ASM_ALIGNED_DI_OP
9959 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9960 #undef TARGET_ASM_INTEGER
9961 #define TARGET_ASM_INTEGER s390_assemble_integer
9962
9963 #undef TARGET_ASM_OPEN_PAREN
9964 #define TARGET_ASM_OPEN_PAREN ""
9965
9966 #undef TARGET_ASM_CLOSE_PAREN
9967 #define TARGET_ASM_CLOSE_PAREN ""
9968
9969 #undef TARGET_DEFAULT_TARGET_FLAGS
9970 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9971 #undef TARGET_HANDLE_OPTION
9972 #define TARGET_HANDLE_OPTION s390_handle_option
9973
9974 #undef TARGET_ENCODE_SECTION_INFO
9975 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9976
9977 #ifdef HAVE_AS_TLS
9978 #undef TARGET_HAVE_TLS
9979 #define TARGET_HAVE_TLS true
9980 #endif
9981 #undef TARGET_CANNOT_FORCE_CONST_MEM
9982 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9983
9984 #undef TARGET_DELEGITIMIZE_ADDRESS
9985 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9986
9987 #undef TARGET_LEGITIMIZE_ADDRESS
9988 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
9989
9990 #undef TARGET_RETURN_IN_MEMORY
9991 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9992
9993 #undef TARGET_INIT_BUILTINS
9994 #define TARGET_INIT_BUILTINS s390_init_builtins
9995 #undef TARGET_EXPAND_BUILTIN
9996 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9997
9998 #undef TARGET_ASM_OUTPUT_MI_THUNK
9999 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10000 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10001 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10002
10003 #undef TARGET_SCHED_ADJUST_PRIORITY
10004 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10005 #undef TARGET_SCHED_ISSUE_RATE
10006 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10007 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10008 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10009
10010 #undef TARGET_CANNOT_COPY_INSN_P
10011 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10012 #undef TARGET_RTX_COSTS
10013 #define TARGET_RTX_COSTS s390_rtx_costs
10014 #undef TARGET_ADDRESS_COST
10015 #define TARGET_ADDRESS_COST s390_address_cost
10016
10017 #undef TARGET_MACHINE_DEPENDENT_REORG
10018 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10019
10020 #undef TARGET_VALID_POINTER_MODE
10021 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10022
10023 #undef TARGET_BUILD_BUILTIN_VA_LIST
10024 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10025 #undef TARGET_EXPAND_BUILTIN_VA_START
10026 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10027 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10028 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10029
10030 #undef TARGET_PROMOTE_FUNCTION_MODE
10031 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10032 #undef TARGET_PASS_BY_REFERENCE
10033 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10034
10035 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10036 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10037
10038 #undef TARGET_FIXED_CONDITION_CODE_REGS
10039 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10040
10041 #undef TARGET_CC_MODES_COMPATIBLE
10042 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10043
10044 #undef TARGET_INVALID_WITHIN_DOLOOP
10045 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10046
10047 #ifdef HAVE_AS_TLS
10048 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10049 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10050 #endif
10051
10052 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10053 #undef TARGET_MANGLE_TYPE
10054 #define TARGET_MANGLE_TYPE s390_mangle_type
10055 #endif
10056
10057 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10058 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10059
10060 #undef TARGET_SECONDARY_RELOAD
10061 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10062
10063 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10064 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10065
10066 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10067 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10068
10069 #undef TARGET_LEGITIMATE_ADDRESS_P
10070 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10071
10072 struct gcc_target targetm = TARGET_INITIALIZER;
10073
10074 #include "gt-s390.h"