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2084.md: Enable all insn reservations also for z9_ec cpu attribute value.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "integrate.h"
46 #include "ggc.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "debug.h"
50 #include "langhooks.h"
51 #include "optabs.h"
52 #include "gimple.h"
53 #include "df.h"
54 #include "params.h"
55 #include "cfgloop.h"
56 #include "opts.h"
57
58 static const int processor_flags_table[] =
59 {
60 /* g5 */ PF_IEEE_FLOAT,
61 /* g6 */ PF_IEEE_FLOAT,
62 /* z900 */ PF_IEEE_FLOAT | PF_ZARCH,
63 /* z990 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT,
64 /* z9-109 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
65 | PF_EXTIMM,
66 /* z9-ec */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
67 | PF_EXTIMM | PF_DFP,
68 /* z10 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
69 | PF_EXTIMM | PF_DFP | PF_Z10,
70 /* z196 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
71 | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196
72 };
73
74 /* Define the specific costs for a given cpu. */
75
76 struct processor_costs
77 {
78 /* multiplication */
79 const int m; /* cost of an M instruction. */
80 const int mghi; /* cost of an MGHI instruction. */
81 const int mh; /* cost of an MH instruction. */
82 const int mhi; /* cost of an MHI instruction. */
83 const int ml; /* cost of an ML instruction. */
84 const int mr; /* cost of an MR instruction. */
85 const int ms; /* cost of an MS instruction. */
86 const int msg; /* cost of an MSG instruction. */
87 const int msgf; /* cost of an MSGF instruction. */
88 const int msgfr; /* cost of an MSGFR instruction. */
89 const int msgr; /* cost of an MSGR instruction. */
90 const int msr; /* cost of an MSR instruction. */
91 const int mult_df; /* cost of multiplication in DFmode. */
92 const int mxbr;
93 /* square root */
94 const int sqxbr; /* cost of square root in TFmode. */
95 const int sqdbr; /* cost of square root in DFmode. */
96 const int sqebr; /* cost of square root in SFmode. */
97 /* multiply and add */
98 const int madbr; /* cost of multiply and add in DFmode. */
99 const int maebr; /* cost of multiply and add in SFmode. */
100 /* division */
101 const int dxbr;
102 const int ddbr;
103 const int debr;
104 const int dlgr;
105 const int dlr;
106 const int dr;
107 const int dsgfr;
108 const int dsgr;
109 };
110
111 const struct processor_costs *s390_cost;
112
113 static const
114 struct processor_costs z900_cost =
115 {
116 COSTS_N_INSNS (5), /* M */
117 COSTS_N_INSNS (10), /* MGHI */
118 COSTS_N_INSNS (5), /* MH */
119 COSTS_N_INSNS (4), /* MHI */
120 COSTS_N_INSNS (5), /* ML */
121 COSTS_N_INSNS (5), /* MR */
122 COSTS_N_INSNS (4), /* MS */
123 COSTS_N_INSNS (15), /* MSG */
124 COSTS_N_INSNS (7), /* MSGF */
125 COSTS_N_INSNS (7), /* MSGFR */
126 COSTS_N_INSNS (10), /* MSGR */
127 COSTS_N_INSNS (4), /* MSR */
128 COSTS_N_INSNS (7), /* multiplication in DFmode */
129 COSTS_N_INSNS (13), /* MXBR */
130 COSTS_N_INSNS (136), /* SQXBR */
131 COSTS_N_INSNS (44), /* SQDBR */
132 COSTS_N_INSNS (35), /* SQEBR */
133 COSTS_N_INSNS (18), /* MADBR */
134 COSTS_N_INSNS (13), /* MAEBR */
135 COSTS_N_INSNS (134), /* DXBR */
136 COSTS_N_INSNS (30), /* DDBR */
137 COSTS_N_INSNS (27), /* DEBR */
138 COSTS_N_INSNS (220), /* DLGR */
139 COSTS_N_INSNS (34), /* DLR */
140 COSTS_N_INSNS (34), /* DR */
141 COSTS_N_INSNS (32), /* DSGFR */
142 COSTS_N_INSNS (32), /* DSGR */
143 };
144
145 static const
146 struct processor_costs z990_cost =
147 {
148 COSTS_N_INSNS (4), /* M */
149 COSTS_N_INSNS (2), /* MGHI */
150 COSTS_N_INSNS (2), /* MH */
151 COSTS_N_INSNS (2), /* MHI */
152 COSTS_N_INSNS (4), /* ML */
153 COSTS_N_INSNS (4), /* MR */
154 COSTS_N_INSNS (5), /* MS */
155 COSTS_N_INSNS (6), /* MSG */
156 COSTS_N_INSNS (4), /* MSGF */
157 COSTS_N_INSNS (4), /* MSGFR */
158 COSTS_N_INSNS (4), /* MSGR */
159 COSTS_N_INSNS (4), /* MSR */
160 COSTS_N_INSNS (1), /* multiplication in DFmode */
161 COSTS_N_INSNS (28), /* MXBR */
162 COSTS_N_INSNS (130), /* SQXBR */
163 COSTS_N_INSNS (66), /* SQDBR */
164 COSTS_N_INSNS (38), /* SQEBR */
165 COSTS_N_INSNS (1), /* MADBR */
166 COSTS_N_INSNS (1), /* MAEBR */
167 COSTS_N_INSNS (60), /* DXBR */
168 COSTS_N_INSNS (40), /* DDBR */
169 COSTS_N_INSNS (26), /* DEBR */
170 COSTS_N_INSNS (176), /* DLGR */
171 COSTS_N_INSNS (31), /* DLR */
172 COSTS_N_INSNS (31), /* DR */
173 COSTS_N_INSNS (31), /* DSGFR */
174 COSTS_N_INSNS (31), /* DSGR */
175 };
176
177 static const
178 struct processor_costs z9_109_cost =
179 {
180 COSTS_N_INSNS (4), /* M */
181 COSTS_N_INSNS (2), /* MGHI */
182 COSTS_N_INSNS (2), /* MH */
183 COSTS_N_INSNS (2), /* MHI */
184 COSTS_N_INSNS (4), /* ML */
185 COSTS_N_INSNS (4), /* MR */
186 COSTS_N_INSNS (5), /* MS */
187 COSTS_N_INSNS (6), /* MSG */
188 COSTS_N_INSNS (4), /* MSGF */
189 COSTS_N_INSNS (4), /* MSGFR */
190 COSTS_N_INSNS (4), /* MSGR */
191 COSTS_N_INSNS (4), /* MSR */
192 COSTS_N_INSNS (1), /* multiplication in DFmode */
193 COSTS_N_INSNS (28), /* MXBR */
194 COSTS_N_INSNS (130), /* SQXBR */
195 COSTS_N_INSNS (66), /* SQDBR */
196 COSTS_N_INSNS (38), /* SQEBR */
197 COSTS_N_INSNS (1), /* MADBR */
198 COSTS_N_INSNS (1), /* MAEBR */
199 COSTS_N_INSNS (60), /* DXBR */
200 COSTS_N_INSNS (40), /* DDBR */
201 COSTS_N_INSNS (26), /* DEBR */
202 COSTS_N_INSNS (30), /* DLGR */
203 COSTS_N_INSNS (23), /* DLR */
204 COSTS_N_INSNS (23), /* DR */
205 COSTS_N_INSNS (24), /* DSGFR */
206 COSTS_N_INSNS (24), /* DSGR */
207 };
208
209 static const
210 struct processor_costs z10_cost =
211 {
212 COSTS_N_INSNS (10), /* M */
213 COSTS_N_INSNS (10), /* MGHI */
214 COSTS_N_INSNS (10), /* MH */
215 COSTS_N_INSNS (10), /* MHI */
216 COSTS_N_INSNS (10), /* ML */
217 COSTS_N_INSNS (10), /* MR */
218 COSTS_N_INSNS (10), /* MS */
219 COSTS_N_INSNS (10), /* MSG */
220 COSTS_N_INSNS (10), /* MSGF */
221 COSTS_N_INSNS (10), /* MSGFR */
222 COSTS_N_INSNS (10), /* MSGR */
223 COSTS_N_INSNS (10), /* MSR */
224 COSTS_N_INSNS (1) , /* multiplication in DFmode */
225 COSTS_N_INSNS (50), /* MXBR */
226 COSTS_N_INSNS (120), /* SQXBR */
227 COSTS_N_INSNS (52), /* SQDBR */
228 COSTS_N_INSNS (38), /* SQEBR */
229 COSTS_N_INSNS (1), /* MADBR */
230 COSTS_N_INSNS (1), /* MAEBR */
231 COSTS_N_INSNS (111), /* DXBR */
232 COSTS_N_INSNS (39), /* DDBR */
233 COSTS_N_INSNS (32), /* DEBR */
234 COSTS_N_INSNS (160), /* DLGR */
235 COSTS_N_INSNS (71), /* DLR */
236 COSTS_N_INSNS (71), /* DR */
237 COSTS_N_INSNS (71), /* DSGFR */
238 COSTS_N_INSNS (71), /* DSGR */
239 };
240
241 static const
242 struct processor_costs z196_cost =
243 {
244 COSTS_N_INSNS (7), /* M */
245 COSTS_N_INSNS (5), /* MGHI */
246 COSTS_N_INSNS (5), /* MH */
247 COSTS_N_INSNS (5), /* MHI */
248 COSTS_N_INSNS (7), /* ML */
249 COSTS_N_INSNS (7), /* MR */
250 COSTS_N_INSNS (6), /* MS */
251 COSTS_N_INSNS (8), /* MSG */
252 COSTS_N_INSNS (6), /* MSGF */
253 COSTS_N_INSNS (6), /* MSGFR */
254 COSTS_N_INSNS (8), /* MSGR */
255 COSTS_N_INSNS (6), /* MSR */
256 COSTS_N_INSNS (1) , /* multiplication in DFmode */
257 COSTS_N_INSNS (40), /* MXBR B+40 */
258 COSTS_N_INSNS (100), /* SQXBR B+100 */
259 COSTS_N_INSNS (42), /* SQDBR B+42 */
260 COSTS_N_INSNS (28), /* SQEBR B+28 */
261 COSTS_N_INSNS (1), /* MADBR B */
262 COSTS_N_INSNS (1), /* MAEBR B */
263 COSTS_N_INSNS (101), /* DXBR B+101 */
264 COSTS_N_INSNS (29), /* DDBR */
265 COSTS_N_INSNS (22), /* DEBR */
266 COSTS_N_INSNS (160), /* DLGR cracked */
267 COSTS_N_INSNS (160), /* DLR cracked */
268 COSTS_N_INSNS (160), /* DR expanded */
269 COSTS_N_INSNS (160), /* DSGFR cracked */
270 COSTS_N_INSNS (160), /* DSGR cracked */
271 };
272
273 extern int reload_completed;
274
275 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
276 static rtx last_scheduled_insn;
277
278 /* Structure used to hold the components of a S/390 memory
279 address. A legitimate address on S/390 is of the general
280 form
281 base + index + displacement
282 where any of the components is optional.
283
284 base and index are registers of the class ADDR_REGS,
285 displacement is an unsigned 12-bit immediate constant. */
286
287 struct s390_address
288 {
289 rtx base;
290 rtx indx;
291 rtx disp;
292 bool pointer;
293 bool literal_pool;
294 };
295
296 /* The following structure is embedded in the machine
297 specific part of struct function. */
298
299 struct GTY (()) s390_frame_layout
300 {
301 /* Offset within stack frame. */
302 HOST_WIDE_INT gprs_offset;
303 HOST_WIDE_INT f0_offset;
304 HOST_WIDE_INT f4_offset;
305 HOST_WIDE_INT f8_offset;
306 HOST_WIDE_INT backchain_offset;
307
308 /* Number of first and last gpr where slots in the register
309 save area are reserved for. */
310 int first_save_gpr_slot;
311 int last_save_gpr_slot;
312
313 /* Number of first and last gpr to be saved, restored. */
314 int first_save_gpr;
315 int first_restore_gpr;
316 int last_save_gpr;
317 int last_restore_gpr;
318
319 /* Bits standing for floating point registers. Set, if the
320 respective register has to be saved. Starting with reg 16 (f0)
321 at the rightmost bit.
322 Bit 15 - 8 7 6 5 4 3 2 1 0
323 fpr 15 - 8 7 5 3 1 6 4 2 0
324 reg 31 - 24 23 22 21 20 19 18 17 16 */
325 unsigned int fpr_bitmap;
326
327 /* Number of floating point registers f8-f15 which must be saved. */
328 int high_fprs;
329
330 /* Set if return address needs to be saved.
331 This flag is set by s390_return_addr_rtx if it could not use
332 the initial value of r14 and therefore depends on r14 saved
333 to the stack. */
334 bool save_return_addr_p;
335
336 /* Size of stack frame. */
337 HOST_WIDE_INT frame_size;
338 };
339
340 /* Define the structure for the machine field in struct function. */
341
342 struct GTY(()) machine_function
343 {
344 struct s390_frame_layout frame_layout;
345
346 /* Literal pool base register. */
347 rtx base_reg;
348
349 /* True if we may need to perform branch splitting. */
350 bool split_branches_pending_p;
351
352 /* Some local-dynamic TLS symbol name. */
353 const char *some_ld_name;
354
355 bool has_landing_pad_p;
356 };
357
358 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
359
360 #define cfun_frame_layout (cfun->machine->frame_layout)
361 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
362 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
363 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
364 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
365 (1 << (BITNUM)))
366 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
367 (1 << (BITNUM))))
368
369 /* Number of GPRs and FPRs used for argument passing. */
370 #define GP_ARG_NUM_REG 5
371 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
372
373 /* A couple of shortcuts. */
374 #define CONST_OK_FOR_J(x) \
375 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
376 #define CONST_OK_FOR_K(x) \
377 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
378 #define CONST_OK_FOR_Os(x) \
379 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
380 #define CONST_OK_FOR_Op(x) \
381 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
382 #define CONST_OK_FOR_On(x) \
383 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
384
385 #define REGNO_PAIR_OK(REGNO, MODE) \
386 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
387
388 /* That's the read ahead of the dynamic branch prediction unit in
389 bytes on a z10 (or higher) CPU. */
390 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
391
392 /* Return the alignment for LABEL. We default to the -falign-labels
393 value except for the literal pool base label. */
394 int
395 s390_label_align (rtx label)
396 {
397 rtx prev_insn = prev_active_insn (label);
398
399 if (prev_insn == NULL_RTX)
400 goto old;
401
402 prev_insn = single_set (prev_insn);
403
404 if (prev_insn == NULL_RTX)
405 goto old;
406
407 prev_insn = SET_SRC (prev_insn);
408
409 /* Don't align literal pool base labels. */
410 if (GET_CODE (prev_insn) == UNSPEC
411 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
412 return 0;
413
414 old:
415 return align_labels_log;
416 }
417
418 static enum machine_mode
419 s390_libgcc_cmp_return_mode (void)
420 {
421 return TARGET_64BIT ? DImode : SImode;
422 }
423
424 static enum machine_mode
425 s390_libgcc_shift_count_mode (void)
426 {
427 return TARGET_64BIT ? DImode : SImode;
428 }
429
430 static enum machine_mode
431 s390_unwind_word_mode (void)
432 {
433 return TARGET_64BIT ? DImode : SImode;
434 }
435
436 /* Return true if the back end supports mode MODE. */
437 static bool
438 s390_scalar_mode_supported_p (enum machine_mode mode)
439 {
440 /* In contrast to the default implementation reject TImode constants on 31bit
441 TARGET_ZARCH for ABI compliance. */
442 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
443 return false;
444
445 if (DECIMAL_FLOAT_MODE_P (mode))
446 return default_decimal_float_supported_p ();
447
448 return default_scalar_mode_supported_p (mode);
449 }
450
451 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
452
453 void
454 s390_set_has_landing_pad_p (bool value)
455 {
456 cfun->machine->has_landing_pad_p = value;
457 }
458
459 /* If two condition code modes are compatible, return a condition code
460 mode which is compatible with both. Otherwise, return
461 VOIDmode. */
462
463 static enum machine_mode
464 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
465 {
466 if (m1 == m2)
467 return m1;
468
469 switch (m1)
470 {
471 case CCZmode:
472 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
473 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
474 return m2;
475 return VOIDmode;
476
477 case CCSmode:
478 case CCUmode:
479 case CCTmode:
480 case CCSRmode:
481 case CCURmode:
482 case CCZ1mode:
483 if (m2 == CCZmode)
484 return m1;
485
486 return VOIDmode;
487
488 default:
489 return VOIDmode;
490 }
491 return VOIDmode;
492 }
493
494 /* Return true if SET either doesn't set the CC register, or else
495 the source and destination have matching CC modes and that
496 CC mode is at least as constrained as REQ_MODE. */
497
498 static bool
499 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
500 {
501 enum machine_mode set_mode;
502
503 gcc_assert (GET_CODE (set) == SET);
504
505 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
506 return 1;
507
508 set_mode = GET_MODE (SET_DEST (set));
509 switch (set_mode)
510 {
511 case CCSmode:
512 case CCSRmode:
513 case CCUmode:
514 case CCURmode:
515 case CCLmode:
516 case CCL1mode:
517 case CCL2mode:
518 case CCL3mode:
519 case CCT1mode:
520 case CCT2mode:
521 case CCT3mode:
522 if (req_mode != set_mode)
523 return 0;
524 break;
525
526 case CCZmode:
527 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
528 && req_mode != CCSRmode && req_mode != CCURmode)
529 return 0;
530 break;
531
532 case CCAPmode:
533 case CCANmode:
534 if (req_mode != CCAmode)
535 return 0;
536 break;
537
538 default:
539 gcc_unreachable ();
540 }
541
542 return (GET_MODE (SET_SRC (set)) == set_mode);
543 }
544
545 /* Return true if every SET in INSN that sets the CC register
546 has source and destination with matching CC modes and that
547 CC mode is at least as constrained as REQ_MODE.
548 If REQ_MODE is VOIDmode, always return false. */
549
550 bool
551 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
552 {
553 int i;
554
555 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
556 if (req_mode == VOIDmode)
557 return false;
558
559 if (GET_CODE (PATTERN (insn)) == SET)
560 return s390_match_ccmode_set (PATTERN (insn), req_mode);
561
562 if (GET_CODE (PATTERN (insn)) == PARALLEL)
563 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
564 {
565 rtx set = XVECEXP (PATTERN (insn), 0, i);
566 if (GET_CODE (set) == SET)
567 if (!s390_match_ccmode_set (set, req_mode))
568 return false;
569 }
570
571 return true;
572 }
573
574 /* If a test-under-mask instruction can be used to implement
575 (compare (and ... OP1) OP2), return the CC mode required
576 to do that. Otherwise, return VOIDmode.
577 MIXED is true if the instruction can distinguish between
578 CC1 and CC2 for mixed selected bits (TMxx), it is false
579 if the instruction cannot (TM). */
580
581 enum machine_mode
582 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
583 {
584 int bit0, bit1;
585
586 /* ??? Fixme: should work on CONST_DOUBLE as well. */
587 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
588 return VOIDmode;
589
590 /* Selected bits all zero: CC0.
591 e.g.: int a; if ((a & (16 + 128)) == 0) */
592 if (INTVAL (op2) == 0)
593 return CCTmode;
594
595 /* Selected bits all one: CC3.
596 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
597 if (INTVAL (op2) == INTVAL (op1))
598 return CCT3mode;
599
600 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
601 int a;
602 if ((a & (16 + 128)) == 16) -> CCT1
603 if ((a & (16 + 128)) == 128) -> CCT2 */
604 if (mixed)
605 {
606 bit1 = exact_log2 (INTVAL (op2));
607 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
608 if (bit0 != -1 && bit1 != -1)
609 return bit0 > bit1 ? CCT1mode : CCT2mode;
610 }
611
612 return VOIDmode;
613 }
614
615 /* Given a comparison code OP (EQ, NE, etc.) and the operands
616 OP0 and OP1 of a COMPARE, return the mode to be used for the
617 comparison. */
618
619 enum machine_mode
620 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
621 {
622 switch (code)
623 {
624 case EQ:
625 case NE:
626 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
627 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
628 return CCAPmode;
629 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
630 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
631 return CCAPmode;
632 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
633 || GET_CODE (op1) == NEG)
634 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
635 return CCLmode;
636
637 if (GET_CODE (op0) == AND)
638 {
639 /* Check whether we can potentially do it via TM. */
640 enum machine_mode ccmode;
641 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
642 if (ccmode != VOIDmode)
643 {
644 /* Relax CCTmode to CCZmode to allow fall-back to AND
645 if that turns out to be beneficial. */
646 return ccmode == CCTmode ? CCZmode : ccmode;
647 }
648 }
649
650 if (register_operand (op0, HImode)
651 && GET_CODE (op1) == CONST_INT
652 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
653 return CCT3mode;
654 if (register_operand (op0, QImode)
655 && GET_CODE (op1) == CONST_INT
656 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
657 return CCT3mode;
658
659 return CCZmode;
660
661 case LE:
662 case LT:
663 case GE:
664 case GT:
665 /* The only overflow condition of NEG and ABS happens when
666 -INT_MAX is used as parameter, which stays negative. So
667 we have an overflow from a positive value to a negative.
668 Using CCAP mode the resulting cc can be used for comparisons. */
669 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
670 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
671 return CCAPmode;
672
673 /* If constants are involved in an add instruction it is possible to use
674 the resulting cc for comparisons with zero. Knowing the sign of the
675 constant the overflow behavior gets predictable. e.g.:
676 int a, b; if ((b = a + c) > 0)
677 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
678 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
679 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
680 {
681 if (INTVAL (XEXP((op0), 1)) < 0)
682 return CCANmode;
683 else
684 return CCAPmode;
685 }
686 /* Fall through. */
687 case UNORDERED:
688 case ORDERED:
689 case UNEQ:
690 case UNLE:
691 case UNLT:
692 case UNGE:
693 case UNGT:
694 case LTGT:
695 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
696 && GET_CODE (op1) != CONST_INT)
697 return CCSRmode;
698 return CCSmode;
699
700 case LTU:
701 case GEU:
702 if (GET_CODE (op0) == PLUS
703 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
704 return CCL1mode;
705
706 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
707 && GET_CODE (op1) != CONST_INT)
708 return CCURmode;
709 return CCUmode;
710
711 case LEU:
712 case GTU:
713 if (GET_CODE (op0) == MINUS
714 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
715 return CCL2mode;
716
717 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
718 && GET_CODE (op1) != CONST_INT)
719 return CCURmode;
720 return CCUmode;
721
722 default:
723 gcc_unreachable ();
724 }
725 }
726
727 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
728 that we can implement more efficiently. */
729
730 void
731 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
732 {
733 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
734 if ((*code == EQ || *code == NE)
735 && *op1 == const0_rtx
736 && GET_CODE (*op0) == ZERO_EXTRACT
737 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
738 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
739 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
740 {
741 rtx inner = XEXP (*op0, 0);
742 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
743 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
744 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
745
746 if (len > 0 && len < modesize
747 && pos >= 0 && pos + len <= modesize
748 && modesize <= HOST_BITS_PER_WIDE_INT)
749 {
750 unsigned HOST_WIDE_INT block;
751 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
752 block <<= modesize - pos - len;
753
754 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
755 gen_int_mode (block, GET_MODE (inner)));
756 }
757 }
758
759 /* Narrow AND of memory against immediate to enable TM. */
760 if ((*code == EQ || *code == NE)
761 && *op1 == const0_rtx
762 && GET_CODE (*op0) == AND
763 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
764 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
765 {
766 rtx inner = XEXP (*op0, 0);
767 rtx mask = XEXP (*op0, 1);
768
769 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
770 if (GET_CODE (inner) == SUBREG
771 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
772 && (GET_MODE_SIZE (GET_MODE (inner))
773 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
774 && ((INTVAL (mask)
775 & GET_MODE_MASK (GET_MODE (inner))
776 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
777 == 0))
778 inner = SUBREG_REG (inner);
779
780 /* Do not change volatile MEMs. */
781 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
782 {
783 int part = s390_single_part (XEXP (*op0, 1),
784 GET_MODE (inner), QImode, 0);
785 if (part >= 0)
786 {
787 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
788 inner = adjust_address_nv (inner, QImode, part);
789 *op0 = gen_rtx_AND (QImode, inner, mask);
790 }
791 }
792 }
793
794 /* Narrow comparisons against 0xffff to HImode if possible. */
795 if ((*code == EQ || *code == NE)
796 && GET_CODE (*op1) == CONST_INT
797 && INTVAL (*op1) == 0xffff
798 && SCALAR_INT_MODE_P (GET_MODE (*op0))
799 && (nonzero_bits (*op0, GET_MODE (*op0))
800 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
801 {
802 *op0 = gen_lowpart (HImode, *op0);
803 *op1 = constm1_rtx;
804 }
805
806 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
807 if (GET_CODE (*op0) == UNSPEC
808 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
809 && XVECLEN (*op0, 0) == 1
810 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
811 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
812 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
813 && *op1 == const0_rtx)
814 {
815 enum rtx_code new_code = UNKNOWN;
816 switch (*code)
817 {
818 case EQ: new_code = EQ; break;
819 case NE: new_code = NE; break;
820 case LT: new_code = GTU; break;
821 case GT: new_code = LTU; break;
822 case LE: new_code = GEU; break;
823 case GE: new_code = LEU; break;
824 default: break;
825 }
826
827 if (new_code != UNKNOWN)
828 {
829 *op0 = XVECEXP (*op0, 0, 0);
830 *code = new_code;
831 }
832 }
833
834 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
835 if (GET_CODE (*op0) == UNSPEC
836 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
837 && XVECLEN (*op0, 0) == 1
838 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
839 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
840 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
841 && *op1 == const0_rtx)
842 {
843 enum rtx_code new_code = UNKNOWN;
844 switch (*code)
845 {
846 case EQ: new_code = EQ; break;
847 case NE: new_code = NE; break;
848 default: break;
849 }
850
851 if (new_code != UNKNOWN)
852 {
853 *op0 = XVECEXP (*op0, 0, 0);
854 *code = new_code;
855 }
856 }
857
858 /* Simplify cascaded EQ, NE with const0_rtx. */
859 if ((*code == NE || *code == EQ)
860 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
861 && GET_MODE (*op0) == SImode
862 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
863 && REG_P (XEXP (*op0, 0))
864 && XEXP (*op0, 1) == const0_rtx
865 && *op1 == const0_rtx)
866 {
867 if ((*code == EQ && GET_CODE (*op0) == NE)
868 || (*code == NE && GET_CODE (*op0) == EQ))
869 *code = EQ;
870 else
871 *code = NE;
872 *op0 = XEXP (*op0, 0);
873 }
874
875 /* Prefer register over memory as first operand. */
876 if (MEM_P (*op0) && REG_P (*op1))
877 {
878 rtx tem = *op0; *op0 = *op1; *op1 = tem;
879 *code = swap_condition (*code);
880 }
881 }
882
883 /* Emit a compare instruction suitable to implement the comparison
884 OP0 CODE OP1. Return the correct condition RTL to be placed in
885 the IF_THEN_ELSE of the conditional branch testing the result. */
886
887 rtx
888 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
889 {
890 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
891 rtx cc;
892
893 /* Do not output a redundant compare instruction if a compare_and_swap
894 pattern already computed the result and the machine modes are compatible. */
895 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
896 {
897 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
898 == GET_MODE (op0));
899 cc = op0;
900 }
901 else
902 {
903 cc = gen_rtx_REG (mode, CC_REGNUM);
904 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
905 }
906
907 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
908 }
909
910 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
911 matches CMP.
912 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
913 conditional branch testing the result. */
914
915 static rtx
916 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
917 {
918 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
919 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
920 }
921
922 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
923 unconditional jump, else a conditional jump under condition COND. */
924
925 void
926 s390_emit_jump (rtx target, rtx cond)
927 {
928 rtx insn;
929
930 target = gen_rtx_LABEL_REF (VOIDmode, target);
931 if (cond)
932 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
933
934 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
935 emit_jump_insn (insn);
936 }
937
938 /* Return branch condition mask to implement a branch
939 specified by CODE. Return -1 for invalid comparisons. */
940
941 int
942 s390_branch_condition_mask (rtx code)
943 {
944 const int CC0 = 1 << 3;
945 const int CC1 = 1 << 2;
946 const int CC2 = 1 << 1;
947 const int CC3 = 1 << 0;
948
949 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
950 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
951 gcc_assert (XEXP (code, 1) == const0_rtx);
952
953 switch (GET_MODE (XEXP (code, 0)))
954 {
955 case CCZmode:
956 case CCZ1mode:
957 switch (GET_CODE (code))
958 {
959 case EQ: return CC0;
960 case NE: return CC1 | CC2 | CC3;
961 default: return -1;
962 }
963 break;
964
965 case CCT1mode:
966 switch (GET_CODE (code))
967 {
968 case EQ: return CC1;
969 case NE: return CC0 | CC2 | CC3;
970 default: return -1;
971 }
972 break;
973
974 case CCT2mode:
975 switch (GET_CODE (code))
976 {
977 case EQ: return CC2;
978 case NE: return CC0 | CC1 | CC3;
979 default: return -1;
980 }
981 break;
982
983 case CCT3mode:
984 switch (GET_CODE (code))
985 {
986 case EQ: return CC3;
987 case NE: return CC0 | CC1 | CC2;
988 default: return -1;
989 }
990 break;
991
992 case CCLmode:
993 switch (GET_CODE (code))
994 {
995 case EQ: return CC0 | CC2;
996 case NE: return CC1 | CC3;
997 default: return -1;
998 }
999 break;
1000
1001 case CCL1mode:
1002 switch (GET_CODE (code))
1003 {
1004 case LTU: return CC2 | CC3; /* carry */
1005 case GEU: return CC0 | CC1; /* no carry */
1006 default: return -1;
1007 }
1008 break;
1009
1010 case CCL2mode:
1011 switch (GET_CODE (code))
1012 {
1013 case GTU: return CC0 | CC1; /* borrow */
1014 case LEU: return CC2 | CC3; /* no borrow */
1015 default: return -1;
1016 }
1017 break;
1018
1019 case CCL3mode:
1020 switch (GET_CODE (code))
1021 {
1022 case EQ: return CC0 | CC2;
1023 case NE: return CC1 | CC3;
1024 case LTU: return CC1;
1025 case GTU: return CC3;
1026 case LEU: return CC1 | CC2;
1027 case GEU: return CC2 | CC3;
1028 default: return -1;
1029 }
1030
1031 case CCUmode:
1032 switch (GET_CODE (code))
1033 {
1034 case EQ: return CC0;
1035 case NE: return CC1 | CC2 | CC3;
1036 case LTU: return CC1;
1037 case GTU: return CC2;
1038 case LEU: return CC0 | CC1;
1039 case GEU: return CC0 | CC2;
1040 default: return -1;
1041 }
1042 break;
1043
1044 case CCURmode:
1045 switch (GET_CODE (code))
1046 {
1047 case EQ: return CC0;
1048 case NE: return CC2 | CC1 | CC3;
1049 case LTU: return CC2;
1050 case GTU: return CC1;
1051 case LEU: return CC0 | CC2;
1052 case GEU: return CC0 | CC1;
1053 default: return -1;
1054 }
1055 break;
1056
1057 case CCAPmode:
1058 switch (GET_CODE (code))
1059 {
1060 case EQ: return CC0;
1061 case NE: return CC1 | CC2 | CC3;
1062 case LT: return CC1 | CC3;
1063 case GT: return CC2;
1064 case LE: return CC0 | CC1 | CC3;
1065 case GE: return CC0 | CC2;
1066 default: return -1;
1067 }
1068 break;
1069
1070 case CCANmode:
1071 switch (GET_CODE (code))
1072 {
1073 case EQ: return CC0;
1074 case NE: return CC1 | CC2 | CC3;
1075 case LT: return CC1;
1076 case GT: return CC2 | CC3;
1077 case LE: return CC0 | CC1;
1078 case GE: return CC0 | CC2 | CC3;
1079 default: return -1;
1080 }
1081 break;
1082
1083 case CCSmode:
1084 switch (GET_CODE (code))
1085 {
1086 case EQ: return CC0;
1087 case NE: return CC1 | CC2 | CC3;
1088 case LT: return CC1;
1089 case GT: return CC2;
1090 case LE: return CC0 | CC1;
1091 case GE: return CC0 | CC2;
1092 case UNORDERED: return CC3;
1093 case ORDERED: return CC0 | CC1 | CC2;
1094 case UNEQ: return CC0 | CC3;
1095 case UNLT: return CC1 | CC3;
1096 case UNGT: return CC2 | CC3;
1097 case UNLE: return CC0 | CC1 | CC3;
1098 case UNGE: return CC0 | CC2 | CC3;
1099 case LTGT: return CC1 | CC2;
1100 default: return -1;
1101 }
1102 break;
1103
1104 case CCSRmode:
1105 switch (GET_CODE (code))
1106 {
1107 case EQ: return CC0;
1108 case NE: return CC2 | CC1 | CC3;
1109 case LT: return CC2;
1110 case GT: return CC1;
1111 case LE: return CC0 | CC2;
1112 case GE: return CC0 | CC1;
1113 case UNORDERED: return CC3;
1114 case ORDERED: return CC0 | CC2 | CC1;
1115 case UNEQ: return CC0 | CC3;
1116 case UNLT: return CC2 | CC3;
1117 case UNGT: return CC1 | CC3;
1118 case UNLE: return CC0 | CC2 | CC3;
1119 case UNGE: return CC0 | CC1 | CC3;
1120 case LTGT: return CC2 | CC1;
1121 default: return -1;
1122 }
1123 break;
1124
1125 default:
1126 return -1;
1127 }
1128 }
1129
1130
1131 /* Return branch condition mask to implement a compare and branch
1132 specified by CODE. Return -1 for invalid comparisons. */
1133
1134 int
1135 s390_compare_and_branch_condition_mask (rtx code)
1136 {
1137 const int CC0 = 1 << 3;
1138 const int CC1 = 1 << 2;
1139 const int CC2 = 1 << 1;
1140
1141 switch (GET_CODE (code))
1142 {
1143 case EQ:
1144 return CC0;
1145 case NE:
1146 return CC1 | CC2;
1147 case LT:
1148 case LTU:
1149 return CC1;
1150 case GT:
1151 case GTU:
1152 return CC2;
1153 case LE:
1154 case LEU:
1155 return CC0 | CC1;
1156 case GE:
1157 case GEU:
1158 return CC0 | CC2;
1159 default:
1160 gcc_unreachable ();
1161 }
1162 return -1;
1163 }
1164
1165 /* If INV is false, return assembler mnemonic string to implement
1166 a branch specified by CODE. If INV is true, return mnemonic
1167 for the corresponding inverted branch. */
1168
1169 static const char *
1170 s390_branch_condition_mnemonic (rtx code, int inv)
1171 {
1172 int mask;
1173
1174 static const char *const mnemonic[16] =
1175 {
1176 NULL, "o", "h", "nle",
1177 "l", "nhe", "lh", "ne",
1178 "e", "nlh", "he", "nl",
1179 "le", "nh", "no", NULL
1180 };
1181
1182 if (GET_CODE (XEXP (code, 0)) == REG
1183 && REGNO (XEXP (code, 0)) == CC_REGNUM
1184 && XEXP (code, 1) == const0_rtx)
1185 mask = s390_branch_condition_mask (code);
1186 else
1187 mask = s390_compare_and_branch_condition_mask (code);
1188
1189 gcc_assert (mask >= 0);
1190
1191 if (inv)
1192 mask ^= 15;
1193
1194 gcc_assert (mask >= 1 && mask <= 14);
1195
1196 return mnemonic[mask];
1197 }
1198
1199 /* Return the part of op which has a value different from def.
1200 The size of the part is determined by mode.
1201 Use this function only if you already know that op really
1202 contains such a part. */
1203
1204 unsigned HOST_WIDE_INT
1205 s390_extract_part (rtx op, enum machine_mode mode, int def)
1206 {
1207 unsigned HOST_WIDE_INT value = 0;
1208 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1209 int part_bits = GET_MODE_BITSIZE (mode);
1210 unsigned HOST_WIDE_INT part_mask
1211 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1212 int i;
1213
1214 for (i = 0; i < max_parts; i++)
1215 {
1216 if (i == 0)
1217 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1218 else
1219 value >>= part_bits;
1220
1221 if ((value & part_mask) != (def & part_mask))
1222 return value & part_mask;
1223 }
1224
1225 gcc_unreachable ();
1226 }
1227
1228 /* If OP is an integer constant of mode MODE with exactly one
1229 part of mode PART_MODE unequal to DEF, return the number of that
1230 part. Otherwise, return -1. */
1231
1232 int
1233 s390_single_part (rtx op,
1234 enum machine_mode mode,
1235 enum machine_mode part_mode,
1236 int def)
1237 {
1238 unsigned HOST_WIDE_INT value = 0;
1239 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1240 unsigned HOST_WIDE_INT part_mask
1241 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1242 int i, part = -1;
1243
1244 if (GET_CODE (op) != CONST_INT)
1245 return -1;
1246
1247 for (i = 0; i < n_parts; i++)
1248 {
1249 if (i == 0)
1250 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1251 else
1252 value >>= GET_MODE_BITSIZE (part_mode);
1253
1254 if ((value & part_mask) != (def & part_mask))
1255 {
1256 if (part != -1)
1257 return -1;
1258 else
1259 part = i;
1260 }
1261 }
1262 return part == -1 ? -1 : n_parts - 1 - part;
1263 }
1264
1265 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1266 bits and no other bits are set in IN. POS and LENGTH can be used
1267 to obtain the start position and the length of the bitfield.
1268
1269 POS gives the position of the first bit of the bitfield counting
1270 from the lowest order bit starting with zero. In order to use this
1271 value for S/390 instructions this has to be converted to "bits big
1272 endian" style. */
1273
1274 bool
1275 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1276 int *pos, int *length)
1277 {
1278 int tmp_pos = 0;
1279 int tmp_length = 0;
1280 int i;
1281 unsigned HOST_WIDE_INT mask = 1ULL;
1282 bool contiguous = false;
1283
1284 for (i = 0; i < size; mask <<= 1, i++)
1285 {
1286 if (contiguous)
1287 {
1288 if (mask & in)
1289 tmp_length++;
1290 else
1291 break;
1292 }
1293 else
1294 {
1295 if (mask & in)
1296 {
1297 contiguous = true;
1298 tmp_length++;
1299 }
1300 else
1301 tmp_pos++;
1302 }
1303 }
1304
1305 if (!tmp_length)
1306 return false;
1307
1308 /* Calculate a mask for all bits beyond the contiguous bits. */
1309 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1310
1311 if (mask & in)
1312 return false;
1313
1314 if (tmp_length + tmp_pos - 1 > size)
1315 return false;
1316
1317 if (length)
1318 *length = tmp_length;
1319
1320 if (pos)
1321 *pos = tmp_pos;
1322
1323 return true;
1324 }
1325
1326 /* Check whether we can (and want to) split a double-word
1327 move in mode MODE from SRC to DST into two single-word
1328 moves, moving the subword FIRST_SUBWORD first. */
1329
1330 bool
1331 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1332 {
1333 /* Floating point registers cannot be split. */
1334 if (FP_REG_P (src) || FP_REG_P (dst))
1335 return false;
1336
1337 /* We don't need to split if operands are directly accessible. */
1338 if (s_operand (src, mode) || s_operand (dst, mode))
1339 return false;
1340
1341 /* Non-offsettable memory references cannot be split. */
1342 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1343 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1344 return false;
1345
1346 /* Moving the first subword must not clobber a register
1347 needed to move the second subword. */
1348 if (register_operand (dst, mode))
1349 {
1350 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1351 if (reg_overlap_mentioned_p (subreg, src))
1352 return false;
1353 }
1354
1355 return true;
1356 }
1357
1358 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1359 and [MEM2, MEM2 + SIZE] do overlap and false
1360 otherwise. */
1361
1362 bool
1363 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1364 {
1365 rtx addr1, addr2, addr_delta;
1366 HOST_WIDE_INT delta;
1367
1368 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1369 return true;
1370
1371 if (size == 0)
1372 return false;
1373
1374 addr1 = XEXP (mem1, 0);
1375 addr2 = XEXP (mem2, 0);
1376
1377 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1378
1379 /* This overlapping check is used by peepholes merging memory block operations.
1380 Overlapping operations would otherwise be recognized by the S/390 hardware
1381 and would fall back to a slower implementation. Allowing overlapping
1382 operations would lead to slow code but not to wrong code. Therefore we are
1383 somewhat optimistic if we cannot prove that the memory blocks are
1384 overlapping.
1385 That's why we return false here although this may accept operations on
1386 overlapping memory areas. */
1387 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1388 return false;
1389
1390 delta = INTVAL (addr_delta);
1391
1392 if (delta == 0
1393 || (delta > 0 && delta < size)
1394 || (delta < 0 && -delta < size))
1395 return true;
1396
1397 return false;
1398 }
1399
1400 /* Check whether the address of memory reference MEM2 equals exactly
1401 the address of memory reference MEM1 plus DELTA. Return true if
1402 we can prove this to be the case, false otherwise. */
1403
1404 bool
1405 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1406 {
1407 rtx addr1, addr2, addr_delta;
1408
1409 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1410 return false;
1411
1412 addr1 = XEXP (mem1, 0);
1413 addr2 = XEXP (mem2, 0);
1414
1415 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1416 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1417 return false;
1418
1419 return true;
1420 }
1421
1422 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1423
1424 void
1425 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1426 rtx *operands)
1427 {
1428 enum machine_mode wmode = mode;
1429 rtx dst = operands[0];
1430 rtx src1 = operands[1];
1431 rtx src2 = operands[2];
1432 rtx op, clob, tem;
1433
1434 /* If we cannot handle the operation directly, use a temp register. */
1435 if (!s390_logical_operator_ok_p (operands))
1436 dst = gen_reg_rtx (mode);
1437
1438 /* QImode and HImode patterns make sense only if we have a destination
1439 in memory. Otherwise perform the operation in SImode. */
1440 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1441 wmode = SImode;
1442
1443 /* Widen operands if required. */
1444 if (mode != wmode)
1445 {
1446 if (GET_CODE (dst) == SUBREG
1447 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1448 dst = tem;
1449 else if (REG_P (dst))
1450 dst = gen_rtx_SUBREG (wmode, dst, 0);
1451 else
1452 dst = gen_reg_rtx (wmode);
1453
1454 if (GET_CODE (src1) == SUBREG
1455 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1456 src1 = tem;
1457 else if (GET_MODE (src1) != VOIDmode)
1458 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1459
1460 if (GET_CODE (src2) == SUBREG
1461 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1462 src2 = tem;
1463 else if (GET_MODE (src2) != VOIDmode)
1464 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1465 }
1466
1467 /* Emit the instruction. */
1468 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1469 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1470 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1471
1472 /* Fix up the destination if needed. */
1473 if (dst != operands[0])
1474 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1475 }
1476
1477 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1478
1479 bool
1480 s390_logical_operator_ok_p (rtx *operands)
1481 {
1482 /* If the destination operand is in memory, it needs to coincide
1483 with one of the source operands. After reload, it has to be
1484 the first source operand. */
1485 if (GET_CODE (operands[0]) == MEM)
1486 return rtx_equal_p (operands[0], operands[1])
1487 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1488
1489 return true;
1490 }
1491
1492 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1493 operand IMMOP to switch from SS to SI type instructions. */
1494
1495 void
1496 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1497 {
1498 int def = code == AND ? -1 : 0;
1499 HOST_WIDE_INT mask;
1500 int part;
1501
1502 gcc_assert (GET_CODE (*memop) == MEM);
1503 gcc_assert (!MEM_VOLATILE_P (*memop));
1504
1505 mask = s390_extract_part (*immop, QImode, def);
1506 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1507 gcc_assert (part >= 0);
1508
1509 *memop = adjust_address (*memop, QImode, part);
1510 *immop = gen_int_mode (mask, QImode);
1511 }
1512
1513
1514 /* How to allocate a 'struct machine_function'. */
1515
1516 static struct machine_function *
1517 s390_init_machine_status (void)
1518 {
1519 return ggc_alloc_cleared_machine_function ();
1520 }
1521
1522 /* Change optimizations to be performed, depending on the
1523 optimization level. */
1524
1525 static const struct default_options s390_option_optimization_table[] =
1526 {
1527 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
1528
1529 /* ??? There are apparently still problems with -fcaller-saves. */
1530 { OPT_LEVELS_ALL, OPT_fcaller_saves, NULL, 0 },
1531
1532 /* Use MVCLE instructions to decrease code size if requested. */
1533 { OPT_LEVELS_SIZE, OPT_mmvcle, NULL, 1 },
1534
1535 { OPT_LEVELS_NONE, 0, NULL, 0 }
1536 };
1537
1538 /* Implement TARGET_OPTION_INIT_STRUCT. */
1539
1540 static void
1541 s390_option_init_struct (struct gcc_options *opts)
1542 {
1543 /* By default, always emit DWARF-2 unwind info. This allows debugging
1544 without maintaining a stack frame back-chain. */
1545 opts->x_flag_asynchronous_unwind_tables = 1;
1546 }
1547
1548 /* Implement TARGET_HANDLE_OPTION. */
1549
1550 static bool
1551 s390_handle_option (struct gcc_options *opts,
1552 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
1553 const struct cl_decoded_option *decoded,
1554 location_t loc)
1555 {
1556 size_t code = decoded->opt_index;
1557 const char *arg = decoded->arg;
1558 int value = decoded->value;
1559
1560 switch (code)
1561 {
1562 case OPT_march_:
1563 opts->x_s390_arch_flags = processor_flags_table[value];
1564 opts->x_s390_arch_string = arg;
1565 return true;
1566
1567 case OPT_mstack_guard_:
1568 if (exact_log2 (value) == -1)
1569 error_at (loc, "stack guard value must be an exact power of 2");
1570 return true;
1571
1572 case OPT_mstack_size_:
1573 if (exact_log2 (value) == -1)
1574 error_at (loc, "stack size must be an exact power of 2");
1575 return true;
1576
1577 case OPT_mtune_:
1578 opts->x_s390_tune_flags = processor_flags_table[value];
1579 return true;
1580
1581 case OPT_mwarn_framesize_:
1582 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC,
1583 &opts->x_s390_warn_framesize) == 1;
1584
1585 default:
1586 return true;
1587 }
1588 }
1589
1590 static void
1591 s390_option_override (void)
1592 {
1593 /* Set up function hooks. */
1594 init_machine_status = s390_init_machine_status;
1595
1596 /* Architecture mode defaults according to ABI. */
1597 if (!(target_flags_explicit & MASK_ZARCH))
1598 {
1599 if (TARGET_64BIT)
1600 target_flags |= MASK_ZARCH;
1601 else
1602 target_flags &= ~MASK_ZARCH;
1603 }
1604
1605 /* Set the march default in case it hasn't been specified on
1606 cmdline. */
1607 if (s390_arch == PROCESSOR_max)
1608 {
1609 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1610 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1611 s390_arch_flags = processor_flags_table[(int)s390_arch];
1612 }
1613
1614 /* Determine processor to tune for. */
1615 if (s390_tune == PROCESSOR_max)
1616 {
1617 s390_tune = s390_arch;
1618 s390_tune_flags = s390_arch_flags;
1619 }
1620
1621 /* Sanity checks. */
1622 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1623 error ("z/Architecture mode not supported on %s", s390_arch_string);
1624 if (TARGET_64BIT && !TARGET_ZARCH)
1625 error ("64-bit ABI not supported in ESA/390 mode");
1626
1627 if (TARGET_HARD_DFP && !TARGET_DFP)
1628 {
1629 if (target_flags_explicit & MASK_HARD_DFP)
1630 {
1631 if (!TARGET_CPU_DFP)
1632 error ("hardware decimal floating point instructions"
1633 " not available on %s", s390_arch_string);
1634 if (!TARGET_ZARCH)
1635 error ("hardware decimal floating point instructions"
1636 " not available in ESA/390 mode");
1637 }
1638 else
1639 target_flags &= ~MASK_HARD_DFP;
1640 }
1641
1642 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1643 {
1644 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1645 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1646
1647 target_flags &= ~MASK_HARD_DFP;
1648 }
1649
1650 /* Set processor cost function. */
1651 switch (s390_tune)
1652 {
1653 case PROCESSOR_2084_Z990:
1654 s390_cost = &z990_cost;
1655 break;
1656 case PROCESSOR_2094_Z9_109:
1657 s390_cost = &z9_109_cost;
1658 break;
1659 case PROCESSOR_2097_Z10:
1660 s390_cost = &z10_cost;
1661 case PROCESSOR_2817_Z196:
1662 s390_cost = &z196_cost;
1663 break;
1664 default:
1665 s390_cost = &z900_cost;
1666 }
1667
1668 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1669 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1670 "in combination");
1671
1672 if (s390_stack_size)
1673 {
1674 if (s390_stack_guard >= s390_stack_size)
1675 error ("stack size must be greater than the stack guard value");
1676 else if (s390_stack_size > 1 << 16)
1677 error ("stack size must not be greater than 64k");
1678 }
1679 else if (s390_stack_guard)
1680 error ("-mstack-guard implies use of -mstack-size");
1681
1682 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1683 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1684 target_flags |= MASK_LONG_DOUBLE_128;
1685 #endif
1686
1687 if (s390_tune == PROCESSOR_2097_Z10
1688 || s390_tune == PROCESSOR_2817_Z196)
1689 {
1690 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1691 global_options.x_param_values,
1692 global_options_set.x_param_values);
1693 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1694 global_options.x_param_values,
1695 global_options_set.x_param_values);
1696 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1697 global_options.x_param_values,
1698 global_options_set.x_param_values);
1699 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1700 global_options.x_param_values,
1701 global_options_set.x_param_values);
1702 }
1703
1704 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1705 global_options.x_param_values,
1706 global_options_set.x_param_values);
1707 /* values for loop prefetching */
1708 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1709 global_options.x_param_values,
1710 global_options_set.x_param_values);
1711 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1712 global_options.x_param_values,
1713 global_options_set.x_param_values);
1714 /* s390 has more than 2 levels and the size is much larger. Since
1715 we are always running virtualized assume that we only get a small
1716 part of the caches above l1. */
1717 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1718 global_options.x_param_values,
1719 global_options_set.x_param_values);
1720 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1721 global_options.x_param_values,
1722 global_options_set.x_param_values);
1723 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1724 global_options.x_param_values,
1725 global_options_set.x_param_values);
1726
1727 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1728 requires the arch flags to be evaluated already. Since prefetching
1729 is beneficial on s390, we enable it if available. */
1730 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1731 flag_prefetch_loop_arrays = 1;
1732 }
1733
1734 /* Map for smallest class containing reg regno. */
1735
1736 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1737 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1738 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1739 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1740 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1741 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1742 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1743 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1744 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1745 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1746 ACCESS_REGS, ACCESS_REGS
1747 };
1748
1749 /* Return attribute type of insn. */
1750
1751 static enum attr_type
1752 s390_safe_attr_type (rtx insn)
1753 {
1754 if (recog_memoized (insn) >= 0)
1755 return get_attr_type (insn);
1756 else
1757 return TYPE_NONE;
1758 }
1759
1760 /* Return true if DISP is a valid short displacement. */
1761
1762 static bool
1763 s390_short_displacement (rtx disp)
1764 {
1765 /* No displacement is OK. */
1766 if (!disp)
1767 return true;
1768
1769 /* Without the long displacement facility we don't need to
1770 distingiush between long and short displacement. */
1771 if (!TARGET_LONG_DISPLACEMENT)
1772 return true;
1773
1774 /* Integer displacement in range. */
1775 if (GET_CODE (disp) == CONST_INT)
1776 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1777
1778 /* GOT offset is not OK, the GOT can be large. */
1779 if (GET_CODE (disp) == CONST
1780 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1781 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1782 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1783 return false;
1784
1785 /* All other symbolic constants are literal pool references,
1786 which are OK as the literal pool must be small. */
1787 if (GET_CODE (disp) == CONST)
1788 return true;
1789
1790 return false;
1791 }
1792
1793 /* Decompose a RTL expression ADDR for a memory address into
1794 its components, returned in OUT.
1795
1796 Returns false if ADDR is not a valid memory address, true
1797 otherwise. If OUT is NULL, don't return the components,
1798 but check for validity only.
1799
1800 Note: Only addresses in canonical form are recognized.
1801 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1802 canonical form so that they will be recognized. */
1803
1804 static int
1805 s390_decompose_address (rtx addr, struct s390_address *out)
1806 {
1807 HOST_WIDE_INT offset = 0;
1808 rtx base = NULL_RTX;
1809 rtx indx = NULL_RTX;
1810 rtx disp = NULL_RTX;
1811 rtx orig_disp;
1812 bool pointer = false;
1813 bool base_ptr = false;
1814 bool indx_ptr = false;
1815 bool literal_pool = false;
1816
1817 /* We may need to substitute the literal pool base register into the address
1818 below. However, at this point we do not know which register is going to
1819 be used as base, so we substitute the arg pointer register. This is going
1820 to be treated as holding a pointer below -- it shouldn't be used for any
1821 other purpose. */
1822 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1823
1824 /* Decompose address into base + index + displacement. */
1825
1826 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1827 base = addr;
1828
1829 else if (GET_CODE (addr) == PLUS)
1830 {
1831 rtx op0 = XEXP (addr, 0);
1832 rtx op1 = XEXP (addr, 1);
1833 enum rtx_code code0 = GET_CODE (op0);
1834 enum rtx_code code1 = GET_CODE (op1);
1835
1836 if (code0 == REG || code0 == UNSPEC)
1837 {
1838 if (code1 == REG || code1 == UNSPEC)
1839 {
1840 indx = op0; /* index + base */
1841 base = op1;
1842 }
1843
1844 else
1845 {
1846 base = op0; /* base + displacement */
1847 disp = op1;
1848 }
1849 }
1850
1851 else if (code0 == PLUS)
1852 {
1853 indx = XEXP (op0, 0); /* index + base + disp */
1854 base = XEXP (op0, 1);
1855 disp = op1;
1856 }
1857
1858 else
1859 {
1860 return false;
1861 }
1862 }
1863
1864 else
1865 disp = addr; /* displacement */
1866
1867 /* Extract integer part of displacement. */
1868 orig_disp = disp;
1869 if (disp)
1870 {
1871 if (GET_CODE (disp) == CONST_INT)
1872 {
1873 offset = INTVAL (disp);
1874 disp = NULL_RTX;
1875 }
1876 else if (GET_CODE (disp) == CONST
1877 && GET_CODE (XEXP (disp, 0)) == PLUS
1878 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1879 {
1880 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1881 disp = XEXP (XEXP (disp, 0), 0);
1882 }
1883 }
1884
1885 /* Strip off CONST here to avoid special case tests later. */
1886 if (disp && GET_CODE (disp) == CONST)
1887 disp = XEXP (disp, 0);
1888
1889 /* We can convert literal pool addresses to
1890 displacements by basing them off the base register. */
1891 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1892 {
1893 /* Either base or index must be free to hold the base register. */
1894 if (!base)
1895 base = fake_pool_base, literal_pool = true;
1896 else if (!indx)
1897 indx = fake_pool_base, literal_pool = true;
1898 else
1899 return false;
1900
1901 /* Mark up the displacement. */
1902 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1903 UNSPEC_LTREL_OFFSET);
1904 }
1905
1906 /* Validate base register. */
1907 if (base)
1908 {
1909 if (GET_CODE (base) == UNSPEC)
1910 switch (XINT (base, 1))
1911 {
1912 case UNSPEC_LTREF:
1913 if (!disp)
1914 disp = gen_rtx_UNSPEC (Pmode,
1915 gen_rtvec (1, XVECEXP (base, 0, 0)),
1916 UNSPEC_LTREL_OFFSET);
1917 else
1918 return false;
1919
1920 base = XVECEXP (base, 0, 1);
1921 break;
1922
1923 case UNSPEC_LTREL_BASE:
1924 if (XVECLEN (base, 0) == 1)
1925 base = fake_pool_base, literal_pool = true;
1926 else
1927 base = XVECEXP (base, 0, 1);
1928 break;
1929
1930 default:
1931 return false;
1932 }
1933
1934 if (!REG_P (base)
1935 || (GET_MODE (base) != SImode
1936 && GET_MODE (base) != Pmode))
1937 return false;
1938
1939 if (REGNO (base) == STACK_POINTER_REGNUM
1940 || REGNO (base) == FRAME_POINTER_REGNUM
1941 || ((reload_completed || reload_in_progress)
1942 && frame_pointer_needed
1943 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1944 || REGNO (base) == ARG_POINTER_REGNUM
1945 || (flag_pic
1946 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1947 pointer = base_ptr = true;
1948
1949 if ((reload_completed || reload_in_progress)
1950 && base == cfun->machine->base_reg)
1951 pointer = base_ptr = literal_pool = true;
1952 }
1953
1954 /* Validate index register. */
1955 if (indx)
1956 {
1957 if (GET_CODE (indx) == UNSPEC)
1958 switch (XINT (indx, 1))
1959 {
1960 case UNSPEC_LTREF:
1961 if (!disp)
1962 disp = gen_rtx_UNSPEC (Pmode,
1963 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1964 UNSPEC_LTREL_OFFSET);
1965 else
1966 return false;
1967
1968 indx = XVECEXP (indx, 0, 1);
1969 break;
1970
1971 case UNSPEC_LTREL_BASE:
1972 if (XVECLEN (indx, 0) == 1)
1973 indx = fake_pool_base, literal_pool = true;
1974 else
1975 indx = XVECEXP (indx, 0, 1);
1976 break;
1977
1978 default:
1979 return false;
1980 }
1981
1982 if (!REG_P (indx)
1983 || (GET_MODE (indx) != SImode
1984 && GET_MODE (indx) != Pmode))
1985 return false;
1986
1987 if (REGNO (indx) == STACK_POINTER_REGNUM
1988 || REGNO (indx) == FRAME_POINTER_REGNUM
1989 || ((reload_completed || reload_in_progress)
1990 && frame_pointer_needed
1991 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1992 || REGNO (indx) == ARG_POINTER_REGNUM
1993 || (flag_pic
1994 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1995 pointer = indx_ptr = true;
1996
1997 if ((reload_completed || reload_in_progress)
1998 && indx == cfun->machine->base_reg)
1999 pointer = indx_ptr = literal_pool = true;
2000 }
2001
2002 /* Prefer to use pointer as base, not index. */
2003 if (base && indx && !base_ptr
2004 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
2005 {
2006 rtx tmp = base;
2007 base = indx;
2008 indx = tmp;
2009 }
2010
2011 /* Validate displacement. */
2012 if (!disp)
2013 {
2014 /* If virtual registers are involved, the displacement will change later
2015 anyway as the virtual registers get eliminated. This could make a
2016 valid displacement invalid, but it is more likely to make an invalid
2017 displacement valid, because we sometimes access the register save area
2018 via negative offsets to one of those registers.
2019 Thus we don't check the displacement for validity here. If after
2020 elimination the displacement turns out to be invalid after all,
2021 this is fixed up by reload in any case. */
2022 if (base != arg_pointer_rtx
2023 && indx != arg_pointer_rtx
2024 && base != return_address_pointer_rtx
2025 && indx != return_address_pointer_rtx
2026 && base != frame_pointer_rtx
2027 && indx != frame_pointer_rtx
2028 && base != virtual_stack_vars_rtx
2029 && indx != virtual_stack_vars_rtx)
2030 if (!DISP_IN_RANGE (offset))
2031 return false;
2032 }
2033 else
2034 {
2035 /* All the special cases are pointers. */
2036 pointer = true;
2037
2038 /* In the small-PIC case, the linker converts @GOT
2039 and @GOTNTPOFF offsets to possible displacements. */
2040 if (GET_CODE (disp) == UNSPEC
2041 && (XINT (disp, 1) == UNSPEC_GOT
2042 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2043 && flag_pic == 1)
2044 {
2045 ;
2046 }
2047
2048 /* Accept pool label offsets. */
2049 else if (GET_CODE (disp) == UNSPEC
2050 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2051 ;
2052
2053 /* Accept literal pool references. */
2054 else if (GET_CODE (disp) == UNSPEC
2055 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2056 {
2057 /* In case CSE pulled a non literal pool reference out of
2058 the pool we have to reject the address. This is
2059 especially important when loading the GOT pointer on non
2060 zarch CPUs. In this case the literal pool contains an lt
2061 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2062 will most likely exceed the displacement. */
2063 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2064 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2065 return false;
2066
2067 orig_disp = gen_rtx_CONST (Pmode, disp);
2068 if (offset)
2069 {
2070 /* If we have an offset, make sure it does not
2071 exceed the size of the constant pool entry. */
2072 rtx sym = XVECEXP (disp, 0, 0);
2073 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2074 return false;
2075
2076 orig_disp = plus_constant (orig_disp, offset);
2077 }
2078 }
2079
2080 else
2081 return false;
2082 }
2083
2084 if (!base && !indx)
2085 pointer = true;
2086
2087 if (out)
2088 {
2089 out->base = base;
2090 out->indx = indx;
2091 out->disp = orig_disp;
2092 out->pointer = pointer;
2093 out->literal_pool = literal_pool;
2094 }
2095
2096 return true;
2097 }
2098
2099 /* Decompose a RTL expression OP for a shift count into its components,
2100 and return the base register in BASE and the offset in OFFSET.
2101
2102 Return true if OP is a valid shift count, false if not. */
2103
2104 bool
2105 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2106 {
2107 HOST_WIDE_INT off = 0;
2108
2109 /* We can have an integer constant, an address register,
2110 or a sum of the two. */
2111 if (GET_CODE (op) == CONST_INT)
2112 {
2113 off = INTVAL (op);
2114 op = NULL_RTX;
2115 }
2116 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2117 {
2118 off = INTVAL (XEXP (op, 1));
2119 op = XEXP (op, 0);
2120 }
2121 while (op && GET_CODE (op) == SUBREG)
2122 op = SUBREG_REG (op);
2123
2124 if (op && GET_CODE (op) != REG)
2125 return false;
2126
2127 if (offset)
2128 *offset = off;
2129 if (base)
2130 *base = op;
2131
2132 return true;
2133 }
2134
2135
2136 /* Return true if CODE is a valid address without index. */
2137
2138 bool
2139 s390_legitimate_address_without_index_p (rtx op)
2140 {
2141 struct s390_address addr;
2142
2143 if (!s390_decompose_address (XEXP (op, 0), &addr))
2144 return false;
2145 if (addr.indx)
2146 return false;
2147
2148 return true;
2149 }
2150
2151
2152 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2153 and return these parts in SYMREF and ADDEND. You can pass NULL in
2154 SYMREF and/or ADDEND if you are not interested in these values.
2155 Literal pool references are *not* considered symbol references. */
2156
2157 static bool
2158 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2159 {
2160 HOST_WIDE_INT tmpaddend = 0;
2161
2162 if (GET_CODE (addr) == CONST)
2163 addr = XEXP (addr, 0);
2164
2165 if (GET_CODE (addr) == PLUS)
2166 {
2167 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2168 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2169 && CONST_INT_P (XEXP (addr, 1)))
2170 {
2171 tmpaddend = INTVAL (XEXP (addr, 1));
2172 addr = XEXP (addr, 0);
2173 }
2174 else
2175 return false;
2176 }
2177 else
2178 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2179 return false;
2180
2181 if (symref)
2182 *symref = addr;
2183 if (addend)
2184 *addend = tmpaddend;
2185
2186 return true;
2187 }
2188
2189
2190 /* Return true if the address in OP is valid for constraint letter C
2191 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2192 pool MEMs should be accepted. Only the Q, R, S, T constraint
2193 letters are allowed for C. */
2194
2195 static int
2196 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2197 {
2198 struct s390_address addr;
2199 bool decomposed = false;
2200
2201 /* This check makes sure that no symbolic address (except literal
2202 pool references) are accepted by the R or T constraints. */
2203 if (s390_symref_operand_p (op, NULL, NULL))
2204 return 0;
2205
2206 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2207 if (!lit_pool_ok)
2208 {
2209 if (!s390_decompose_address (op, &addr))
2210 return 0;
2211 if (addr.literal_pool)
2212 return 0;
2213 decomposed = true;
2214 }
2215
2216 switch (c)
2217 {
2218 case 'Q': /* no index short displacement */
2219 if (!decomposed && !s390_decompose_address (op, &addr))
2220 return 0;
2221 if (addr.indx)
2222 return 0;
2223 if (!s390_short_displacement (addr.disp))
2224 return 0;
2225 break;
2226
2227 case 'R': /* with index short displacement */
2228 if (TARGET_LONG_DISPLACEMENT)
2229 {
2230 if (!decomposed && !s390_decompose_address (op, &addr))
2231 return 0;
2232 if (!s390_short_displacement (addr.disp))
2233 return 0;
2234 }
2235 /* Any invalid address here will be fixed up by reload,
2236 so accept it for the most generic constraint. */
2237 break;
2238
2239 case 'S': /* no index long displacement */
2240 if (!TARGET_LONG_DISPLACEMENT)
2241 return 0;
2242 if (!decomposed && !s390_decompose_address (op, &addr))
2243 return 0;
2244 if (addr.indx)
2245 return 0;
2246 if (s390_short_displacement (addr.disp))
2247 return 0;
2248 break;
2249
2250 case 'T': /* with index long displacement */
2251 if (!TARGET_LONG_DISPLACEMENT)
2252 return 0;
2253 /* Any invalid address here will be fixed up by reload,
2254 so accept it for the most generic constraint. */
2255 if ((decomposed || s390_decompose_address (op, &addr))
2256 && s390_short_displacement (addr.disp))
2257 return 0;
2258 break;
2259 default:
2260 return 0;
2261 }
2262 return 1;
2263 }
2264
2265
2266 /* Evaluates constraint strings described by the regular expression
2267 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2268 the constraint given in STR, or 0 else. */
2269
2270 int
2271 s390_mem_constraint (const char *str, rtx op)
2272 {
2273 char c = str[0];
2274
2275 switch (c)
2276 {
2277 case 'A':
2278 /* Check for offsettable variants of memory constraints. */
2279 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2280 return 0;
2281 if ((reload_completed || reload_in_progress)
2282 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2283 return 0;
2284 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2285 case 'B':
2286 /* Check for non-literal-pool variants of memory constraints. */
2287 if (!MEM_P (op))
2288 return 0;
2289 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2290 case 'Q':
2291 case 'R':
2292 case 'S':
2293 case 'T':
2294 if (GET_CODE (op) != MEM)
2295 return 0;
2296 return s390_check_qrst_address (c, XEXP (op, 0), true);
2297 case 'U':
2298 return (s390_check_qrst_address ('Q', op, true)
2299 || s390_check_qrst_address ('R', op, true));
2300 case 'W':
2301 return (s390_check_qrst_address ('S', op, true)
2302 || s390_check_qrst_address ('T', op, true));
2303 case 'Y':
2304 /* Simply check for the basic form of a shift count. Reload will
2305 take care of making sure we have a proper base register. */
2306 if (!s390_decompose_shift_count (op, NULL, NULL))
2307 return 0;
2308 break;
2309 case 'Z':
2310 return s390_check_qrst_address (str[1], op, true);
2311 default:
2312 return 0;
2313 }
2314 return 1;
2315 }
2316
2317
2318 /* Evaluates constraint strings starting with letter O. Input
2319 parameter C is the second letter following the "O" in the constraint
2320 string. Returns 1 if VALUE meets the respective constraint and 0
2321 otherwise. */
2322
2323 int
2324 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2325 {
2326 if (!TARGET_EXTIMM)
2327 return 0;
2328
2329 switch (c)
2330 {
2331 case 's':
2332 return trunc_int_for_mode (value, SImode) == value;
2333
2334 case 'p':
2335 return value == 0
2336 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2337
2338 case 'n':
2339 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2340
2341 default:
2342 gcc_unreachable ();
2343 }
2344 }
2345
2346
2347 /* Evaluates constraint strings starting with letter N. Parameter STR
2348 contains the letters following letter "N" in the constraint string.
2349 Returns true if VALUE matches the constraint. */
2350
2351 int
2352 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2353 {
2354 enum machine_mode mode, part_mode;
2355 int def;
2356 int part, part_goal;
2357
2358
2359 if (str[0] == 'x')
2360 part_goal = -1;
2361 else
2362 part_goal = str[0] - '0';
2363
2364 switch (str[1])
2365 {
2366 case 'Q':
2367 part_mode = QImode;
2368 break;
2369 case 'H':
2370 part_mode = HImode;
2371 break;
2372 case 'S':
2373 part_mode = SImode;
2374 break;
2375 default:
2376 return 0;
2377 }
2378
2379 switch (str[2])
2380 {
2381 case 'H':
2382 mode = HImode;
2383 break;
2384 case 'S':
2385 mode = SImode;
2386 break;
2387 case 'D':
2388 mode = DImode;
2389 break;
2390 default:
2391 return 0;
2392 }
2393
2394 switch (str[3])
2395 {
2396 case '0':
2397 def = 0;
2398 break;
2399 case 'F':
2400 def = -1;
2401 break;
2402 default:
2403 return 0;
2404 }
2405
2406 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2407 return 0;
2408
2409 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2410 if (part < 0)
2411 return 0;
2412 if (part_goal != -1 && part_goal != part)
2413 return 0;
2414
2415 return 1;
2416 }
2417
2418
2419 /* Returns true if the input parameter VALUE is a float zero. */
2420
2421 int
2422 s390_float_const_zero_p (rtx value)
2423 {
2424 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2425 && value == CONST0_RTX (GET_MODE (value)));
2426 }
2427
2428 /* Implement TARGET_REGISTER_MOVE_COST. */
2429
2430 static int
2431 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2432 reg_class_t from, reg_class_t to)
2433 {
2434 /* On s390, copy between fprs and gprs is expensive. */
2435 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2436 && reg_classes_intersect_p (to, FP_REGS))
2437 || (reg_classes_intersect_p (from, FP_REGS)
2438 && reg_classes_intersect_p (to, GENERAL_REGS)))
2439 return 10;
2440
2441 return 1;
2442 }
2443
2444 /* Implement TARGET_MEMORY_MOVE_COST. */
2445
2446 static int
2447 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2448 reg_class_t rclass ATTRIBUTE_UNUSED,
2449 bool in ATTRIBUTE_UNUSED)
2450 {
2451 return 1;
2452 }
2453
2454 /* Compute a (partial) cost for rtx X. Return true if the complete
2455 cost has been computed, and false if subexpressions should be
2456 scanned. In either case, *TOTAL contains the cost result.
2457 CODE contains GET_CODE (x), OUTER_CODE contains the code
2458 of the superexpression of x. */
2459
2460 static bool
2461 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2462 bool speed ATTRIBUTE_UNUSED)
2463 {
2464 switch (code)
2465 {
2466 case CONST:
2467 case CONST_INT:
2468 case LABEL_REF:
2469 case SYMBOL_REF:
2470 case CONST_DOUBLE:
2471 case MEM:
2472 *total = 0;
2473 return true;
2474
2475 case ASHIFT:
2476 case ASHIFTRT:
2477 case LSHIFTRT:
2478 case ROTATE:
2479 case ROTATERT:
2480 case AND:
2481 case IOR:
2482 case XOR:
2483 case NEG:
2484 case NOT:
2485 *total = COSTS_N_INSNS (1);
2486 return false;
2487
2488 case PLUS:
2489 case MINUS:
2490 *total = COSTS_N_INSNS (1);
2491 return false;
2492
2493 case MULT:
2494 switch (GET_MODE (x))
2495 {
2496 case SImode:
2497 {
2498 rtx left = XEXP (x, 0);
2499 rtx right = XEXP (x, 1);
2500 if (GET_CODE (right) == CONST_INT
2501 && CONST_OK_FOR_K (INTVAL (right)))
2502 *total = s390_cost->mhi;
2503 else if (GET_CODE (left) == SIGN_EXTEND)
2504 *total = s390_cost->mh;
2505 else
2506 *total = s390_cost->ms; /* msr, ms, msy */
2507 break;
2508 }
2509 case DImode:
2510 {
2511 rtx left = XEXP (x, 0);
2512 rtx right = XEXP (x, 1);
2513 if (TARGET_ZARCH)
2514 {
2515 if (GET_CODE (right) == CONST_INT
2516 && CONST_OK_FOR_K (INTVAL (right)))
2517 *total = s390_cost->mghi;
2518 else if (GET_CODE (left) == SIGN_EXTEND)
2519 *total = s390_cost->msgf;
2520 else
2521 *total = s390_cost->msg; /* msgr, msg */
2522 }
2523 else /* TARGET_31BIT */
2524 {
2525 if (GET_CODE (left) == SIGN_EXTEND
2526 && GET_CODE (right) == SIGN_EXTEND)
2527 /* mulsidi case: mr, m */
2528 *total = s390_cost->m;
2529 else if (GET_CODE (left) == ZERO_EXTEND
2530 && GET_CODE (right) == ZERO_EXTEND
2531 && TARGET_CPU_ZARCH)
2532 /* umulsidi case: ml, mlr */
2533 *total = s390_cost->ml;
2534 else
2535 /* Complex calculation is required. */
2536 *total = COSTS_N_INSNS (40);
2537 }
2538 break;
2539 }
2540 case SFmode:
2541 case DFmode:
2542 *total = s390_cost->mult_df;
2543 break;
2544 case TFmode:
2545 *total = s390_cost->mxbr;
2546 break;
2547 default:
2548 return false;
2549 }
2550 return false;
2551
2552 case FMA:
2553 switch (GET_MODE (x))
2554 {
2555 case DFmode:
2556 *total = s390_cost->madbr;
2557 break;
2558 case SFmode:
2559 *total = s390_cost->maebr;
2560 break;
2561 default:
2562 return false;
2563 }
2564 /* Negate in the third argument is free: FMSUB. */
2565 if (GET_CODE (XEXP (x, 2)) == NEG)
2566 {
2567 *total += (rtx_cost (XEXP (x, 0), FMA, speed)
2568 + rtx_cost (XEXP (x, 1), FMA, speed)
2569 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, speed));
2570 return true;
2571 }
2572 return false;
2573
2574 case UDIV:
2575 case UMOD:
2576 if (GET_MODE (x) == TImode) /* 128 bit division */
2577 *total = s390_cost->dlgr;
2578 else if (GET_MODE (x) == DImode)
2579 {
2580 rtx right = XEXP (x, 1);
2581 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2582 *total = s390_cost->dlr;
2583 else /* 64 by 64 bit division */
2584 *total = s390_cost->dlgr;
2585 }
2586 else if (GET_MODE (x) == SImode) /* 32 bit division */
2587 *total = s390_cost->dlr;
2588 return false;
2589
2590 case DIV:
2591 case MOD:
2592 if (GET_MODE (x) == DImode)
2593 {
2594 rtx right = XEXP (x, 1);
2595 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2596 if (TARGET_ZARCH)
2597 *total = s390_cost->dsgfr;
2598 else
2599 *total = s390_cost->dr;
2600 else /* 64 by 64 bit division */
2601 *total = s390_cost->dsgr;
2602 }
2603 else if (GET_MODE (x) == SImode) /* 32 bit division */
2604 *total = s390_cost->dlr;
2605 else if (GET_MODE (x) == SFmode)
2606 {
2607 *total = s390_cost->debr;
2608 }
2609 else if (GET_MODE (x) == DFmode)
2610 {
2611 *total = s390_cost->ddbr;
2612 }
2613 else if (GET_MODE (x) == TFmode)
2614 {
2615 *total = s390_cost->dxbr;
2616 }
2617 return false;
2618
2619 case SQRT:
2620 if (GET_MODE (x) == SFmode)
2621 *total = s390_cost->sqebr;
2622 else if (GET_MODE (x) == DFmode)
2623 *total = s390_cost->sqdbr;
2624 else /* TFmode */
2625 *total = s390_cost->sqxbr;
2626 return false;
2627
2628 case SIGN_EXTEND:
2629 case ZERO_EXTEND:
2630 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2631 || outer_code == PLUS || outer_code == MINUS
2632 || outer_code == COMPARE)
2633 *total = 0;
2634 return false;
2635
2636 case COMPARE:
2637 *total = COSTS_N_INSNS (1);
2638 if (GET_CODE (XEXP (x, 0)) == AND
2639 && GET_CODE (XEXP (x, 1)) == CONST_INT
2640 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2641 {
2642 rtx op0 = XEXP (XEXP (x, 0), 0);
2643 rtx op1 = XEXP (XEXP (x, 0), 1);
2644 rtx op2 = XEXP (x, 1);
2645
2646 if (memory_operand (op0, GET_MODE (op0))
2647 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2648 return true;
2649 if (register_operand (op0, GET_MODE (op0))
2650 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2651 return true;
2652 }
2653 return false;
2654
2655 default:
2656 return false;
2657 }
2658 }
2659
2660 /* Return the cost of an address rtx ADDR. */
2661
2662 static int
2663 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2664 {
2665 struct s390_address ad;
2666 if (!s390_decompose_address (addr, &ad))
2667 return 1000;
2668
2669 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2670 }
2671
2672 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2673 otherwise return 0. */
2674
2675 int
2676 tls_symbolic_operand (rtx op)
2677 {
2678 if (GET_CODE (op) != SYMBOL_REF)
2679 return 0;
2680 return SYMBOL_REF_TLS_MODEL (op);
2681 }
2682 \f
2683 /* Split DImode access register reference REG (on 64-bit) into its constituent
2684 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2685 gen_highpart cannot be used as they assume all registers are word-sized,
2686 while our access registers have only half that size. */
2687
2688 void
2689 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2690 {
2691 gcc_assert (TARGET_64BIT);
2692 gcc_assert (ACCESS_REG_P (reg));
2693 gcc_assert (GET_MODE (reg) == DImode);
2694 gcc_assert (!(REGNO (reg) & 1));
2695
2696 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2697 *hi = gen_rtx_REG (SImode, REGNO (reg));
2698 }
2699
2700 /* Return true if OP contains a symbol reference */
2701
2702 bool
2703 symbolic_reference_mentioned_p (rtx op)
2704 {
2705 const char *fmt;
2706 int i;
2707
2708 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2709 return 1;
2710
2711 fmt = GET_RTX_FORMAT (GET_CODE (op));
2712 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2713 {
2714 if (fmt[i] == 'E')
2715 {
2716 int j;
2717
2718 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2719 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2720 return 1;
2721 }
2722
2723 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2724 return 1;
2725 }
2726
2727 return 0;
2728 }
2729
2730 /* Return true if OP contains a reference to a thread-local symbol. */
2731
2732 bool
2733 tls_symbolic_reference_mentioned_p (rtx op)
2734 {
2735 const char *fmt;
2736 int i;
2737
2738 if (GET_CODE (op) == SYMBOL_REF)
2739 return tls_symbolic_operand (op);
2740
2741 fmt = GET_RTX_FORMAT (GET_CODE (op));
2742 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2743 {
2744 if (fmt[i] == 'E')
2745 {
2746 int j;
2747
2748 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2749 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2750 return true;
2751 }
2752
2753 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2754 return true;
2755 }
2756
2757 return false;
2758 }
2759
2760
2761 /* Return true if OP is a legitimate general operand when
2762 generating PIC code. It is given that flag_pic is on
2763 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2764
2765 int
2766 legitimate_pic_operand_p (rtx op)
2767 {
2768 /* Accept all non-symbolic constants. */
2769 if (!SYMBOLIC_CONST (op))
2770 return 1;
2771
2772 /* Reject everything else; must be handled
2773 via emit_symbolic_move. */
2774 return 0;
2775 }
2776
2777 /* Returns true if the constant value OP is a legitimate general operand.
2778 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2779
2780 int
2781 legitimate_constant_p (rtx op)
2782 {
2783 /* Accept all non-symbolic constants. */
2784 if (!SYMBOLIC_CONST (op))
2785 return 1;
2786
2787 /* Accept immediate LARL operands. */
2788 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2789 return 1;
2790
2791 /* Thread-local symbols are never legal constants. This is
2792 so that emit_call knows that computing such addresses
2793 might require a function call. */
2794 if (TLS_SYMBOLIC_CONST (op))
2795 return 0;
2796
2797 /* In the PIC case, symbolic constants must *not* be
2798 forced into the literal pool. We accept them here,
2799 so that they will be handled by emit_symbolic_move. */
2800 if (flag_pic)
2801 return 1;
2802
2803 /* All remaining non-PIC symbolic constants are
2804 forced into the literal pool. */
2805 return 0;
2806 }
2807
2808 /* Determine if it's legal to put X into the constant pool. This
2809 is not possible if X contains the address of a symbol that is
2810 not constant (TLS) or not known at final link time (PIC). */
2811
2812 static bool
2813 s390_cannot_force_const_mem (rtx x)
2814 {
2815 switch (GET_CODE (x))
2816 {
2817 case CONST_INT:
2818 case CONST_DOUBLE:
2819 /* Accept all non-symbolic constants. */
2820 return false;
2821
2822 case LABEL_REF:
2823 /* Labels are OK iff we are non-PIC. */
2824 return flag_pic != 0;
2825
2826 case SYMBOL_REF:
2827 /* 'Naked' TLS symbol references are never OK,
2828 non-TLS symbols are OK iff we are non-PIC. */
2829 if (tls_symbolic_operand (x))
2830 return true;
2831 else
2832 return flag_pic != 0;
2833
2834 case CONST:
2835 return s390_cannot_force_const_mem (XEXP (x, 0));
2836 case PLUS:
2837 case MINUS:
2838 return s390_cannot_force_const_mem (XEXP (x, 0))
2839 || s390_cannot_force_const_mem (XEXP (x, 1));
2840
2841 case UNSPEC:
2842 switch (XINT (x, 1))
2843 {
2844 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2845 case UNSPEC_LTREL_OFFSET:
2846 case UNSPEC_GOT:
2847 case UNSPEC_GOTOFF:
2848 case UNSPEC_PLTOFF:
2849 case UNSPEC_TLSGD:
2850 case UNSPEC_TLSLDM:
2851 case UNSPEC_NTPOFF:
2852 case UNSPEC_DTPOFF:
2853 case UNSPEC_GOTNTPOFF:
2854 case UNSPEC_INDNTPOFF:
2855 return false;
2856
2857 /* If the literal pool shares the code section, be put
2858 execute template placeholders into the pool as well. */
2859 case UNSPEC_INSN:
2860 return TARGET_CPU_ZARCH;
2861
2862 default:
2863 return true;
2864 }
2865 break;
2866
2867 default:
2868 gcc_unreachable ();
2869 }
2870 }
2871
2872 /* Returns true if the constant value OP is a legitimate general
2873 operand during and after reload. The difference to
2874 legitimate_constant_p is that this function will not accept
2875 a constant that would need to be forced to the literal pool
2876 before it can be used as operand.
2877 This function accepts all constants which can be loaded directly
2878 into a GPR. */
2879
2880 bool
2881 legitimate_reload_constant_p (rtx op)
2882 {
2883 /* Accept la(y) operands. */
2884 if (GET_CODE (op) == CONST_INT
2885 && DISP_IN_RANGE (INTVAL (op)))
2886 return true;
2887
2888 /* Accept l(g)hi/l(g)fi operands. */
2889 if (GET_CODE (op) == CONST_INT
2890 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2891 return true;
2892
2893 /* Accept lliXX operands. */
2894 if (TARGET_ZARCH
2895 && GET_CODE (op) == CONST_INT
2896 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2897 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2898 return true;
2899
2900 if (TARGET_EXTIMM
2901 && GET_CODE (op) == CONST_INT
2902 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2903 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2904 return true;
2905
2906 /* Accept larl operands. */
2907 if (TARGET_CPU_ZARCH
2908 && larl_operand (op, VOIDmode))
2909 return true;
2910
2911 /* Accept floating-point zero operands that fit into a single GPR. */
2912 if (GET_CODE (op) == CONST_DOUBLE
2913 && s390_float_const_zero_p (op)
2914 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2915 return true;
2916
2917 /* Accept double-word operands that can be split. */
2918 if (GET_CODE (op) == CONST_INT
2919 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2920 {
2921 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2922 rtx hi = operand_subword (op, 0, 0, dword_mode);
2923 rtx lo = operand_subword (op, 1, 0, dword_mode);
2924 return legitimate_reload_constant_p (hi)
2925 && legitimate_reload_constant_p (lo);
2926 }
2927
2928 /* Everything else cannot be handled without reload. */
2929 return false;
2930 }
2931
2932 /* Returns true if the constant value OP is a legitimate fp operand
2933 during and after reload.
2934 This function accepts all constants which can be loaded directly
2935 into an FPR. */
2936
2937 static bool
2938 legitimate_reload_fp_constant_p (rtx op)
2939 {
2940 /* Accept floating-point zero operands if the load zero instruction
2941 can be used. */
2942 if (TARGET_Z196
2943 && GET_CODE (op) == CONST_DOUBLE
2944 && s390_float_const_zero_p (op))
2945 return true;
2946
2947 return false;
2948 }
2949
2950 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2951 return the class of reg to actually use. */
2952
2953 static reg_class_t
2954 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2955 {
2956 switch (GET_CODE (op))
2957 {
2958 /* Constants we cannot reload into general registers
2959 must be forced into the literal pool. */
2960 case CONST_DOUBLE:
2961 case CONST_INT:
2962 if (reg_class_subset_p (GENERAL_REGS, rclass)
2963 && legitimate_reload_constant_p (op))
2964 return GENERAL_REGS;
2965 else if (reg_class_subset_p (ADDR_REGS, rclass)
2966 && legitimate_reload_constant_p (op))
2967 return ADDR_REGS;
2968 else if (reg_class_subset_p (FP_REGS, rclass)
2969 && legitimate_reload_fp_constant_p (op))
2970 return FP_REGS;
2971 return NO_REGS;
2972
2973 /* If a symbolic constant or a PLUS is reloaded,
2974 it is most likely being used as an address, so
2975 prefer ADDR_REGS. If 'class' is not a superset
2976 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2977 case PLUS:
2978 case LABEL_REF:
2979 case SYMBOL_REF:
2980 case CONST:
2981 if (reg_class_subset_p (ADDR_REGS, rclass))
2982 return ADDR_REGS;
2983 else
2984 return NO_REGS;
2985
2986 default:
2987 break;
2988 }
2989
2990 return rclass;
2991 }
2992
2993 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2994 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2995 aligned. */
2996
2997 bool
2998 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2999 {
3000 HOST_WIDE_INT addend;
3001 rtx symref;
3002
3003 if (!s390_symref_operand_p (addr, &symref, &addend))
3004 return false;
3005
3006 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
3007 && !(addend & (alignment - 1)));
3008 }
3009
3010 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3011 operand SCRATCH is used to reload the even part of the address and
3012 adding one. */
3013
3014 void
3015 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3016 {
3017 HOST_WIDE_INT addend;
3018 rtx symref;
3019
3020 if (!s390_symref_operand_p (addr, &symref, &addend))
3021 gcc_unreachable ();
3022
3023 if (!(addend & 1))
3024 /* Easy case. The addend is even so larl will do fine. */
3025 emit_move_insn (reg, addr);
3026 else
3027 {
3028 /* We can leave the scratch register untouched if the target
3029 register is a valid base register. */
3030 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3031 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3032 scratch = reg;
3033
3034 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3035 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3036
3037 if (addend != 1)
3038 emit_move_insn (scratch,
3039 gen_rtx_CONST (Pmode,
3040 gen_rtx_PLUS (Pmode, symref,
3041 GEN_INT (addend - 1))));
3042 else
3043 emit_move_insn (scratch, symref);
3044
3045 /* Increment the address using la in order to avoid clobbering cc. */
3046 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3047 }
3048 }
3049
3050 /* Generate what is necessary to move between REG and MEM using
3051 SCRATCH. The direction is given by TOMEM. */
3052
3053 void
3054 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3055 {
3056 /* Reload might have pulled a constant out of the literal pool.
3057 Force it back in. */
3058 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3059 || GET_CODE (mem) == CONST)
3060 mem = force_const_mem (GET_MODE (reg), mem);
3061
3062 gcc_assert (MEM_P (mem));
3063
3064 /* For a load from memory we can leave the scratch register
3065 untouched if the target register is a valid base register. */
3066 if (!tomem
3067 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3068 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3069 && GET_MODE (reg) == GET_MODE (scratch))
3070 scratch = reg;
3071
3072 /* Load address into scratch register. Since we can't have a
3073 secondary reload for a secondary reload we have to cover the case
3074 where larl would need a secondary reload here as well. */
3075 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3076
3077 /* Now we can use a standard load/store to do the move. */
3078 if (tomem)
3079 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3080 else
3081 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3082 }
3083
3084 /* Inform reload about cases where moving X with a mode MODE to a register in
3085 RCLASS requires an extra scratch or immediate register. Return the class
3086 needed for the immediate register. */
3087
3088 static reg_class_t
3089 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3090 enum machine_mode mode, secondary_reload_info *sri)
3091 {
3092 enum reg_class rclass = (enum reg_class) rclass_i;
3093
3094 /* Intermediate register needed. */
3095 if (reg_classes_intersect_p (CC_REGS, rclass))
3096 return GENERAL_REGS;
3097
3098 if (TARGET_Z10)
3099 {
3100 /* On z10 several optimizer steps may generate larl operands with
3101 an odd addend. */
3102 if (in_p
3103 && s390_symref_operand_p (x, NULL, NULL)
3104 && mode == Pmode
3105 && !s390_check_symref_alignment (x, 2))
3106 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3107 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3108
3109 /* On z10 we need a scratch register when moving QI, TI or floating
3110 point mode values from or to a memory location with a SYMBOL_REF
3111 or if the symref addend of a SI or DI move is not aligned to the
3112 width of the access. */
3113 if (MEM_P (x)
3114 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3115 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3116 || (!TARGET_ZARCH && mode == DImode)
3117 || ((mode == HImode || mode == SImode || mode == DImode)
3118 && (!s390_check_symref_alignment (XEXP (x, 0),
3119 GET_MODE_SIZE (mode))))))
3120 {
3121 #define __SECONDARY_RELOAD_CASE(M,m) \
3122 case M##mode: \
3123 if (TARGET_64BIT) \
3124 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3125 CODE_FOR_reload##m##di_tomem_z10; \
3126 else \
3127 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3128 CODE_FOR_reload##m##si_tomem_z10; \
3129 break;
3130
3131 switch (GET_MODE (x))
3132 {
3133 __SECONDARY_RELOAD_CASE (QI, qi);
3134 __SECONDARY_RELOAD_CASE (HI, hi);
3135 __SECONDARY_RELOAD_CASE (SI, si);
3136 __SECONDARY_RELOAD_CASE (DI, di);
3137 __SECONDARY_RELOAD_CASE (TI, ti);
3138 __SECONDARY_RELOAD_CASE (SF, sf);
3139 __SECONDARY_RELOAD_CASE (DF, df);
3140 __SECONDARY_RELOAD_CASE (TF, tf);
3141 __SECONDARY_RELOAD_CASE (SD, sd);
3142 __SECONDARY_RELOAD_CASE (DD, dd);
3143 __SECONDARY_RELOAD_CASE (TD, td);
3144
3145 default:
3146 gcc_unreachable ();
3147 }
3148 #undef __SECONDARY_RELOAD_CASE
3149 }
3150 }
3151
3152 /* We need a scratch register when loading a PLUS expression which
3153 is not a legitimate operand of the LOAD ADDRESS instruction. */
3154 if (in_p && s390_plus_operand (x, mode))
3155 sri->icode = (TARGET_64BIT ?
3156 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3157
3158 /* Performing a multiword move from or to memory we have to make sure the
3159 second chunk in memory is addressable without causing a displacement
3160 overflow. If that would be the case we calculate the address in
3161 a scratch register. */
3162 if (MEM_P (x)
3163 && GET_CODE (XEXP (x, 0)) == PLUS
3164 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3165 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3166 + GET_MODE_SIZE (mode) - 1))
3167 {
3168 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3169 in a s_operand address since we may fallback to lm/stm. So we only
3170 have to care about overflows in the b+i+d case. */
3171 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3172 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3173 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3174 /* For FP_REGS no lm/stm is available so this check is triggered
3175 for displacement overflows in b+i+d and b+d like addresses. */
3176 || (reg_classes_intersect_p (FP_REGS, rclass)
3177 && s390_class_max_nregs (FP_REGS, mode) > 1))
3178 {
3179 if (in_p)
3180 sri->icode = (TARGET_64BIT ?
3181 CODE_FOR_reloaddi_nonoffmem_in :
3182 CODE_FOR_reloadsi_nonoffmem_in);
3183 else
3184 sri->icode = (TARGET_64BIT ?
3185 CODE_FOR_reloaddi_nonoffmem_out :
3186 CODE_FOR_reloadsi_nonoffmem_out);
3187 }
3188 }
3189
3190 /* A scratch address register is needed when a symbolic constant is
3191 copied to r0 compiling with -fPIC. In other cases the target
3192 register might be used as temporary (see legitimize_pic_address). */
3193 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3194 sri->icode = (TARGET_64BIT ?
3195 CODE_FOR_reloaddi_PIC_addr :
3196 CODE_FOR_reloadsi_PIC_addr);
3197
3198 /* Either scratch or no register needed. */
3199 return NO_REGS;
3200 }
3201
3202 /* Generate code to load SRC, which is PLUS that is not a
3203 legitimate operand for the LA instruction, into TARGET.
3204 SCRATCH may be used as scratch register. */
3205
3206 void
3207 s390_expand_plus_operand (rtx target, rtx src,
3208 rtx scratch)
3209 {
3210 rtx sum1, sum2;
3211 struct s390_address ad;
3212
3213 /* src must be a PLUS; get its two operands. */
3214 gcc_assert (GET_CODE (src) == PLUS);
3215 gcc_assert (GET_MODE (src) == Pmode);
3216
3217 /* Check if any of the two operands is already scheduled
3218 for replacement by reload. This can happen e.g. when
3219 float registers occur in an address. */
3220 sum1 = find_replacement (&XEXP (src, 0));
3221 sum2 = find_replacement (&XEXP (src, 1));
3222 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3223
3224 /* If the address is already strictly valid, there's nothing to do. */
3225 if (!s390_decompose_address (src, &ad)
3226 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3227 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3228 {
3229 /* Otherwise, one of the operands cannot be an address register;
3230 we reload its value into the scratch register. */
3231 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3232 {
3233 emit_move_insn (scratch, sum1);
3234 sum1 = scratch;
3235 }
3236 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3237 {
3238 emit_move_insn (scratch, sum2);
3239 sum2 = scratch;
3240 }
3241
3242 /* According to the way these invalid addresses are generated
3243 in reload.c, it should never happen (at least on s390) that
3244 *neither* of the PLUS components, after find_replacements
3245 was applied, is an address register. */
3246 if (sum1 == scratch && sum2 == scratch)
3247 {
3248 debug_rtx (src);
3249 gcc_unreachable ();
3250 }
3251
3252 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3253 }
3254
3255 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3256 is only ever performed on addresses, so we can mark the
3257 sum as legitimate for LA in any case. */
3258 s390_load_address (target, src);
3259 }
3260
3261
3262 /* Return true if ADDR is a valid memory address.
3263 STRICT specifies whether strict register checking applies. */
3264
3265 static bool
3266 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3267 {
3268 struct s390_address ad;
3269
3270 if (TARGET_Z10
3271 && larl_operand (addr, VOIDmode)
3272 && (mode == VOIDmode
3273 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3274 return true;
3275
3276 if (!s390_decompose_address (addr, &ad))
3277 return false;
3278
3279 if (strict)
3280 {
3281 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3282 return false;
3283
3284 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3285 return false;
3286 }
3287 else
3288 {
3289 if (ad.base
3290 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3291 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3292 return false;
3293
3294 if (ad.indx
3295 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3296 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3297 return false;
3298 }
3299 return true;
3300 }
3301
3302 /* Return true if OP is a valid operand for the LA instruction.
3303 In 31-bit, we need to prove that the result is used as an
3304 address, as LA performs only a 31-bit addition. */
3305
3306 bool
3307 legitimate_la_operand_p (rtx op)
3308 {
3309 struct s390_address addr;
3310 if (!s390_decompose_address (op, &addr))
3311 return false;
3312
3313 return (TARGET_64BIT || addr.pointer);
3314 }
3315
3316 /* Return true if it is valid *and* preferable to use LA to
3317 compute the sum of OP1 and OP2. */
3318
3319 bool
3320 preferred_la_operand_p (rtx op1, rtx op2)
3321 {
3322 struct s390_address addr;
3323
3324 if (op2 != const0_rtx)
3325 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3326
3327 if (!s390_decompose_address (op1, &addr))
3328 return false;
3329 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3330 return false;
3331 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3332 return false;
3333
3334 /* Avoid LA instructions with index register on z196; it is
3335 preferable to use regular add instructions when possible. */
3336 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3337 return false;
3338
3339 if (!TARGET_64BIT && !addr.pointer)
3340 return false;
3341
3342 if (addr.pointer)
3343 return true;
3344
3345 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3346 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3347 return true;
3348
3349 return false;
3350 }
3351
3352 /* Emit a forced load-address operation to load SRC into DST.
3353 This will use the LOAD ADDRESS instruction even in situations
3354 where legitimate_la_operand_p (SRC) returns false. */
3355
3356 void
3357 s390_load_address (rtx dst, rtx src)
3358 {
3359 if (TARGET_64BIT)
3360 emit_move_insn (dst, src);
3361 else
3362 emit_insn (gen_force_la_31 (dst, src));
3363 }
3364
3365 /* Return a legitimate reference for ORIG (an address) using the
3366 register REG. If REG is 0, a new pseudo is generated.
3367
3368 There are two types of references that must be handled:
3369
3370 1. Global data references must load the address from the GOT, via
3371 the PIC reg. An insn is emitted to do this load, and the reg is
3372 returned.
3373
3374 2. Static data references, constant pool addresses, and code labels
3375 compute the address as an offset from the GOT, whose base is in
3376 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3377 differentiate them from global data objects. The returned
3378 address is the PIC reg + an unspec constant.
3379
3380 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3381 reg also appears in the address. */
3382
3383 rtx
3384 legitimize_pic_address (rtx orig, rtx reg)
3385 {
3386 rtx addr = orig;
3387 rtx new_rtx = orig;
3388 rtx base;
3389
3390 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3391
3392 if (GET_CODE (addr) == LABEL_REF
3393 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3394 {
3395 /* This is a local symbol. */
3396 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3397 {
3398 /* Access local symbols PC-relative via LARL.
3399 This is the same as in the non-PIC case, so it is
3400 handled automatically ... */
3401 }
3402 else
3403 {
3404 /* Access local symbols relative to the GOT. */
3405
3406 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3407
3408 if (reload_in_progress || reload_completed)
3409 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3410
3411 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3412 addr = gen_rtx_CONST (Pmode, addr);
3413 addr = force_const_mem (Pmode, addr);
3414 emit_move_insn (temp, addr);
3415
3416 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3417 if (reg != 0)
3418 {
3419 s390_load_address (reg, new_rtx);
3420 new_rtx = reg;
3421 }
3422 }
3423 }
3424 else if (GET_CODE (addr) == SYMBOL_REF)
3425 {
3426 if (reg == 0)
3427 reg = gen_reg_rtx (Pmode);
3428
3429 if (flag_pic == 1)
3430 {
3431 /* Assume GOT offset < 4k. This is handled the same way
3432 in both 31- and 64-bit code (@GOT). */
3433
3434 if (reload_in_progress || reload_completed)
3435 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3436
3437 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3438 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3439 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3440 new_rtx = gen_const_mem (Pmode, new_rtx);
3441 emit_move_insn (reg, new_rtx);
3442 new_rtx = reg;
3443 }
3444 else if (TARGET_CPU_ZARCH)
3445 {
3446 /* If the GOT offset might be >= 4k, we determine the position
3447 of the GOT entry via a PC-relative LARL (@GOTENT). */
3448
3449 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3450
3451 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3452 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3453
3454 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3455 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3456 emit_move_insn (temp, new_rtx);
3457
3458 new_rtx = gen_const_mem (Pmode, temp);
3459 emit_move_insn (reg, new_rtx);
3460 new_rtx = reg;
3461 }
3462 else
3463 {
3464 /* If the GOT offset might be >= 4k, we have to load it
3465 from the literal pool (@GOT). */
3466
3467 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3468
3469 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3470 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3471
3472 if (reload_in_progress || reload_completed)
3473 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3474
3475 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3476 addr = gen_rtx_CONST (Pmode, addr);
3477 addr = force_const_mem (Pmode, addr);
3478 emit_move_insn (temp, addr);
3479
3480 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3481 new_rtx = gen_const_mem (Pmode, new_rtx);
3482 emit_move_insn (reg, new_rtx);
3483 new_rtx = reg;
3484 }
3485 }
3486 else
3487 {
3488 if (GET_CODE (addr) == CONST)
3489 {
3490 addr = XEXP (addr, 0);
3491 if (GET_CODE (addr) == UNSPEC)
3492 {
3493 gcc_assert (XVECLEN (addr, 0) == 1);
3494 switch (XINT (addr, 1))
3495 {
3496 /* If someone moved a GOT-relative UNSPEC
3497 out of the literal pool, force them back in. */
3498 case UNSPEC_GOTOFF:
3499 case UNSPEC_PLTOFF:
3500 new_rtx = force_const_mem (Pmode, orig);
3501 break;
3502
3503 /* @GOT is OK as is if small. */
3504 case UNSPEC_GOT:
3505 if (flag_pic == 2)
3506 new_rtx = force_const_mem (Pmode, orig);
3507 break;
3508
3509 /* @GOTENT is OK as is. */
3510 case UNSPEC_GOTENT:
3511 break;
3512
3513 /* @PLT is OK as is on 64-bit, must be converted to
3514 GOT-relative @PLTOFF on 31-bit. */
3515 case UNSPEC_PLT:
3516 if (!TARGET_CPU_ZARCH)
3517 {
3518 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3519
3520 if (reload_in_progress || reload_completed)
3521 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3522
3523 addr = XVECEXP (addr, 0, 0);
3524 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3525 UNSPEC_PLTOFF);
3526 addr = gen_rtx_CONST (Pmode, addr);
3527 addr = force_const_mem (Pmode, addr);
3528 emit_move_insn (temp, addr);
3529
3530 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3531 if (reg != 0)
3532 {
3533 s390_load_address (reg, new_rtx);
3534 new_rtx = reg;
3535 }
3536 }
3537 break;
3538
3539 /* Everything else cannot happen. */
3540 default:
3541 gcc_unreachable ();
3542 }
3543 }
3544 else
3545 gcc_assert (GET_CODE (addr) == PLUS);
3546 }
3547 if (GET_CODE (addr) == PLUS)
3548 {
3549 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3550
3551 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3552 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3553
3554 /* Check first to see if this is a constant offset
3555 from a local symbol reference. */
3556 if ((GET_CODE (op0) == LABEL_REF
3557 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3558 && GET_CODE (op1) == CONST_INT)
3559 {
3560 if (TARGET_CPU_ZARCH
3561 && larl_operand (op0, VOIDmode)
3562 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3563 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3564 {
3565 if (INTVAL (op1) & 1)
3566 {
3567 /* LARL can't handle odd offsets, so emit a
3568 pair of LARL and LA. */
3569 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3570
3571 if (!DISP_IN_RANGE (INTVAL (op1)))
3572 {
3573 HOST_WIDE_INT even = INTVAL (op1) - 1;
3574 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3575 op0 = gen_rtx_CONST (Pmode, op0);
3576 op1 = const1_rtx;
3577 }
3578
3579 emit_move_insn (temp, op0);
3580 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3581
3582 if (reg != 0)
3583 {
3584 s390_load_address (reg, new_rtx);
3585 new_rtx = reg;
3586 }
3587 }
3588 else
3589 {
3590 /* If the offset is even, we can just use LARL.
3591 This will happen automatically. */
3592 }
3593 }
3594 else
3595 {
3596 /* Access local symbols relative to the GOT. */
3597
3598 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3599
3600 if (reload_in_progress || reload_completed)
3601 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3602
3603 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3604 UNSPEC_GOTOFF);
3605 addr = gen_rtx_PLUS (Pmode, addr, op1);
3606 addr = gen_rtx_CONST (Pmode, addr);
3607 addr = force_const_mem (Pmode, addr);
3608 emit_move_insn (temp, addr);
3609
3610 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3611 if (reg != 0)
3612 {
3613 s390_load_address (reg, new_rtx);
3614 new_rtx = reg;
3615 }
3616 }
3617 }
3618
3619 /* Now, check whether it is a GOT relative symbol plus offset
3620 that was pulled out of the literal pool. Force it back in. */
3621
3622 else if (GET_CODE (op0) == UNSPEC
3623 && GET_CODE (op1) == CONST_INT
3624 && XINT (op0, 1) == UNSPEC_GOTOFF)
3625 {
3626 gcc_assert (XVECLEN (op0, 0) == 1);
3627
3628 new_rtx = force_const_mem (Pmode, orig);
3629 }
3630
3631 /* Otherwise, compute the sum. */
3632 else
3633 {
3634 base = legitimize_pic_address (XEXP (addr, 0), reg);
3635 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3636 base == reg ? NULL_RTX : reg);
3637 if (GET_CODE (new_rtx) == CONST_INT)
3638 new_rtx = plus_constant (base, INTVAL (new_rtx));
3639 else
3640 {
3641 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3642 {
3643 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3644 new_rtx = XEXP (new_rtx, 1);
3645 }
3646 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3647 }
3648
3649 if (GET_CODE (new_rtx) == CONST)
3650 new_rtx = XEXP (new_rtx, 0);
3651 new_rtx = force_operand (new_rtx, 0);
3652 }
3653 }
3654 }
3655 return new_rtx;
3656 }
3657
3658 /* Load the thread pointer into a register. */
3659
3660 rtx
3661 s390_get_thread_pointer (void)
3662 {
3663 rtx tp = gen_reg_rtx (Pmode);
3664
3665 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3666 mark_reg_pointer (tp, BITS_PER_WORD);
3667
3668 return tp;
3669 }
3670
3671 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3672 in s390_tls_symbol which always refers to __tls_get_offset.
3673 The returned offset is written to RESULT_REG and an USE rtx is
3674 generated for TLS_CALL. */
3675
3676 static GTY(()) rtx s390_tls_symbol;
3677
3678 static void
3679 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3680 {
3681 rtx insn;
3682
3683 gcc_assert (flag_pic);
3684
3685 if (!s390_tls_symbol)
3686 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3687
3688 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3689 gen_rtx_REG (Pmode, RETURN_REGNUM));
3690
3691 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3692 RTL_CONST_CALL_P (insn) = 1;
3693 }
3694
3695 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3696 this (thread-local) address. REG may be used as temporary. */
3697
3698 static rtx
3699 legitimize_tls_address (rtx addr, rtx reg)
3700 {
3701 rtx new_rtx, tls_call, temp, base, r2, insn;
3702
3703 if (GET_CODE (addr) == SYMBOL_REF)
3704 switch (tls_symbolic_operand (addr))
3705 {
3706 case TLS_MODEL_GLOBAL_DYNAMIC:
3707 start_sequence ();
3708 r2 = gen_rtx_REG (Pmode, 2);
3709 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3710 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3711 new_rtx = force_const_mem (Pmode, new_rtx);
3712 emit_move_insn (r2, new_rtx);
3713 s390_emit_tls_call_insn (r2, tls_call);
3714 insn = get_insns ();
3715 end_sequence ();
3716
3717 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3718 temp = gen_reg_rtx (Pmode);
3719 emit_libcall_block (insn, temp, r2, new_rtx);
3720
3721 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3722 if (reg != 0)
3723 {
3724 s390_load_address (reg, new_rtx);
3725 new_rtx = reg;
3726 }
3727 break;
3728
3729 case TLS_MODEL_LOCAL_DYNAMIC:
3730 start_sequence ();
3731 r2 = gen_rtx_REG (Pmode, 2);
3732 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3733 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3734 new_rtx = force_const_mem (Pmode, new_rtx);
3735 emit_move_insn (r2, new_rtx);
3736 s390_emit_tls_call_insn (r2, tls_call);
3737 insn = get_insns ();
3738 end_sequence ();
3739
3740 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3741 temp = gen_reg_rtx (Pmode);
3742 emit_libcall_block (insn, temp, r2, new_rtx);
3743
3744 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3745 base = gen_reg_rtx (Pmode);
3746 s390_load_address (base, new_rtx);
3747
3748 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3749 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3750 new_rtx = force_const_mem (Pmode, new_rtx);
3751 temp = gen_reg_rtx (Pmode);
3752 emit_move_insn (temp, new_rtx);
3753
3754 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3755 if (reg != 0)
3756 {
3757 s390_load_address (reg, new_rtx);
3758 new_rtx = reg;
3759 }
3760 break;
3761
3762 case TLS_MODEL_INITIAL_EXEC:
3763 if (flag_pic == 1)
3764 {
3765 /* Assume GOT offset < 4k. This is handled the same way
3766 in both 31- and 64-bit code. */
3767
3768 if (reload_in_progress || reload_completed)
3769 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3770
3771 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3772 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3773 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3774 new_rtx = gen_const_mem (Pmode, new_rtx);
3775 temp = gen_reg_rtx (Pmode);
3776 emit_move_insn (temp, new_rtx);
3777 }
3778 else if (TARGET_CPU_ZARCH)
3779 {
3780 /* If the GOT offset might be >= 4k, we determine the position
3781 of the GOT entry via a PC-relative LARL. */
3782
3783 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3784 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3785 temp = gen_reg_rtx (Pmode);
3786 emit_move_insn (temp, new_rtx);
3787
3788 new_rtx = gen_const_mem (Pmode, temp);
3789 temp = gen_reg_rtx (Pmode);
3790 emit_move_insn (temp, new_rtx);
3791 }
3792 else if (flag_pic)
3793 {
3794 /* If the GOT offset might be >= 4k, we have to load it
3795 from the literal pool. */
3796
3797 if (reload_in_progress || reload_completed)
3798 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3799
3800 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3801 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3802 new_rtx = force_const_mem (Pmode, new_rtx);
3803 temp = gen_reg_rtx (Pmode);
3804 emit_move_insn (temp, new_rtx);
3805
3806 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3807 new_rtx = gen_const_mem (Pmode, new_rtx);
3808
3809 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3810 temp = gen_reg_rtx (Pmode);
3811 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3812 }
3813 else
3814 {
3815 /* In position-dependent code, load the absolute address of
3816 the GOT entry from the literal pool. */
3817
3818 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3819 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3820 new_rtx = force_const_mem (Pmode, new_rtx);
3821 temp = gen_reg_rtx (Pmode);
3822 emit_move_insn (temp, new_rtx);
3823
3824 new_rtx = temp;
3825 new_rtx = gen_const_mem (Pmode, new_rtx);
3826 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3827 temp = gen_reg_rtx (Pmode);
3828 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3829 }
3830
3831 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3832 if (reg != 0)
3833 {
3834 s390_load_address (reg, new_rtx);
3835 new_rtx = reg;
3836 }
3837 break;
3838
3839 case TLS_MODEL_LOCAL_EXEC:
3840 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3841 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3842 new_rtx = force_const_mem (Pmode, new_rtx);
3843 temp = gen_reg_rtx (Pmode);
3844 emit_move_insn (temp, new_rtx);
3845
3846 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3847 if (reg != 0)
3848 {
3849 s390_load_address (reg, new_rtx);
3850 new_rtx = reg;
3851 }
3852 break;
3853
3854 default:
3855 gcc_unreachable ();
3856 }
3857
3858 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3859 {
3860 switch (XINT (XEXP (addr, 0), 1))
3861 {
3862 case UNSPEC_INDNTPOFF:
3863 gcc_assert (TARGET_CPU_ZARCH);
3864 new_rtx = addr;
3865 break;
3866
3867 default:
3868 gcc_unreachable ();
3869 }
3870 }
3871
3872 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3873 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3874 {
3875 new_rtx = XEXP (XEXP (addr, 0), 0);
3876 if (GET_CODE (new_rtx) != SYMBOL_REF)
3877 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3878
3879 new_rtx = legitimize_tls_address (new_rtx, reg);
3880 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3881 new_rtx = force_operand (new_rtx, 0);
3882 }
3883
3884 else
3885 gcc_unreachable (); /* for now ... */
3886
3887 return new_rtx;
3888 }
3889
3890 /* Emit insns making the address in operands[1] valid for a standard
3891 move to operands[0]. operands[1] is replaced by an address which
3892 should be used instead of the former RTX to emit the move
3893 pattern. */
3894
3895 void
3896 emit_symbolic_move (rtx *operands)
3897 {
3898 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3899
3900 if (GET_CODE (operands[0]) == MEM)
3901 operands[1] = force_reg (Pmode, operands[1]);
3902 else if (TLS_SYMBOLIC_CONST (operands[1]))
3903 operands[1] = legitimize_tls_address (operands[1], temp);
3904 else if (flag_pic)
3905 operands[1] = legitimize_pic_address (operands[1], temp);
3906 }
3907
3908 /* Try machine-dependent ways of modifying an illegitimate address X
3909 to be legitimate. If we find one, return the new, valid address.
3910
3911 OLDX is the address as it was before break_out_memory_refs was called.
3912 In some cases it is useful to look at this to decide what needs to be done.
3913
3914 MODE is the mode of the operand pointed to by X.
3915
3916 When -fpic is used, special handling is needed for symbolic references.
3917 See comments by legitimize_pic_address for details. */
3918
3919 static rtx
3920 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3921 enum machine_mode mode ATTRIBUTE_UNUSED)
3922 {
3923 rtx constant_term = const0_rtx;
3924
3925 if (TLS_SYMBOLIC_CONST (x))
3926 {
3927 x = legitimize_tls_address (x, 0);
3928
3929 if (s390_legitimate_address_p (mode, x, FALSE))
3930 return x;
3931 }
3932 else if (GET_CODE (x) == PLUS
3933 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3934 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3935 {
3936 return x;
3937 }
3938 else if (flag_pic)
3939 {
3940 if (SYMBOLIC_CONST (x)
3941 || (GET_CODE (x) == PLUS
3942 && (SYMBOLIC_CONST (XEXP (x, 0))
3943 || SYMBOLIC_CONST (XEXP (x, 1)))))
3944 x = legitimize_pic_address (x, 0);
3945
3946 if (s390_legitimate_address_p (mode, x, FALSE))
3947 return x;
3948 }
3949
3950 x = eliminate_constant_term (x, &constant_term);
3951
3952 /* Optimize loading of large displacements by splitting them
3953 into the multiple of 4K and the rest; this allows the
3954 former to be CSE'd if possible.
3955
3956 Don't do this if the displacement is added to a register
3957 pointing into the stack frame, as the offsets will
3958 change later anyway. */
3959
3960 if (GET_CODE (constant_term) == CONST_INT
3961 && !TARGET_LONG_DISPLACEMENT
3962 && !DISP_IN_RANGE (INTVAL (constant_term))
3963 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3964 {
3965 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3966 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3967
3968 rtx temp = gen_reg_rtx (Pmode);
3969 rtx val = force_operand (GEN_INT (upper), temp);
3970 if (val != temp)
3971 emit_move_insn (temp, val);
3972
3973 x = gen_rtx_PLUS (Pmode, x, temp);
3974 constant_term = GEN_INT (lower);
3975 }
3976
3977 if (GET_CODE (x) == PLUS)
3978 {
3979 if (GET_CODE (XEXP (x, 0)) == REG)
3980 {
3981 rtx temp = gen_reg_rtx (Pmode);
3982 rtx val = force_operand (XEXP (x, 1), temp);
3983 if (val != temp)
3984 emit_move_insn (temp, val);
3985
3986 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3987 }
3988
3989 else if (GET_CODE (XEXP (x, 1)) == REG)
3990 {
3991 rtx temp = gen_reg_rtx (Pmode);
3992 rtx val = force_operand (XEXP (x, 0), temp);
3993 if (val != temp)
3994 emit_move_insn (temp, val);
3995
3996 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3997 }
3998 }
3999
4000 if (constant_term != const0_rtx)
4001 x = gen_rtx_PLUS (Pmode, x, constant_term);
4002
4003 return x;
4004 }
4005
4006 /* Try a machine-dependent way of reloading an illegitimate address AD
4007 operand. If we find one, push the reload and and return the new address.
4008
4009 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4010 and TYPE is the reload type of the current reload. */
4011
4012 rtx
4013 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
4014 int opnum, int type)
4015 {
4016 if (!optimize || TARGET_LONG_DISPLACEMENT)
4017 return NULL_RTX;
4018
4019 if (GET_CODE (ad) == PLUS)
4020 {
4021 rtx tem = simplify_binary_operation (PLUS, Pmode,
4022 XEXP (ad, 0), XEXP (ad, 1));
4023 if (tem)
4024 ad = tem;
4025 }
4026
4027 if (GET_CODE (ad) == PLUS
4028 && GET_CODE (XEXP (ad, 0)) == REG
4029 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4030 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4031 {
4032 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4033 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4034 rtx cst, tem, new_rtx;
4035
4036 cst = GEN_INT (upper);
4037 if (!legitimate_reload_constant_p (cst))
4038 cst = force_const_mem (Pmode, cst);
4039
4040 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4041 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4042
4043 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4044 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4045 opnum, (enum reload_type) type);
4046 return new_rtx;
4047 }
4048
4049 return NULL_RTX;
4050 }
4051
4052 /* Emit code to move LEN bytes from DST to SRC. */
4053
4054 void
4055 s390_expand_movmem (rtx dst, rtx src, rtx len)
4056 {
4057 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4058 {
4059 if (INTVAL (len) > 0)
4060 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4061 }
4062
4063 else if (TARGET_MVCLE)
4064 {
4065 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4066 }
4067
4068 else
4069 {
4070 rtx dst_addr, src_addr, count, blocks, temp;
4071 rtx loop_start_label = gen_label_rtx ();
4072 rtx loop_end_label = gen_label_rtx ();
4073 rtx end_label = gen_label_rtx ();
4074 enum machine_mode mode;
4075
4076 mode = GET_MODE (len);
4077 if (mode == VOIDmode)
4078 mode = Pmode;
4079
4080 dst_addr = gen_reg_rtx (Pmode);
4081 src_addr = gen_reg_rtx (Pmode);
4082 count = gen_reg_rtx (mode);
4083 blocks = gen_reg_rtx (mode);
4084
4085 convert_move (count, len, 1);
4086 emit_cmp_and_jump_insns (count, const0_rtx,
4087 EQ, NULL_RTX, mode, 1, end_label);
4088
4089 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4090 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4091 dst = change_address (dst, VOIDmode, dst_addr);
4092 src = change_address (src, VOIDmode, src_addr);
4093
4094 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4095 OPTAB_DIRECT);
4096 if (temp != count)
4097 emit_move_insn (count, temp);
4098
4099 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4100 OPTAB_DIRECT);
4101 if (temp != blocks)
4102 emit_move_insn (blocks, temp);
4103
4104 emit_cmp_and_jump_insns (blocks, const0_rtx,
4105 EQ, NULL_RTX, mode, 1, loop_end_label);
4106
4107 emit_label (loop_start_label);
4108
4109 if (TARGET_Z10
4110 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4111 {
4112 rtx prefetch;
4113
4114 /* Issue a read prefetch for the +3 cache line. */
4115 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4116 const0_rtx, const0_rtx);
4117 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4118 emit_insn (prefetch);
4119
4120 /* Issue a write prefetch for the +3 cache line. */
4121 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4122 const1_rtx, const0_rtx);
4123 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4124 emit_insn (prefetch);
4125 }
4126
4127 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4128 s390_load_address (dst_addr,
4129 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4130 s390_load_address (src_addr,
4131 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4132
4133 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4134 OPTAB_DIRECT);
4135 if (temp != blocks)
4136 emit_move_insn (blocks, temp);
4137
4138 emit_cmp_and_jump_insns (blocks, const0_rtx,
4139 EQ, NULL_RTX, mode, 1, loop_end_label);
4140
4141 emit_jump (loop_start_label);
4142 emit_label (loop_end_label);
4143
4144 emit_insn (gen_movmem_short (dst, src,
4145 convert_to_mode (Pmode, count, 1)));
4146 emit_label (end_label);
4147 }
4148 }
4149
4150 /* Emit code to set LEN bytes at DST to VAL.
4151 Make use of clrmem if VAL is zero. */
4152
4153 void
4154 s390_expand_setmem (rtx dst, rtx len, rtx val)
4155 {
4156 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4157 return;
4158
4159 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4160
4161 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4162 {
4163 if (val == const0_rtx && INTVAL (len) <= 256)
4164 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4165 else
4166 {
4167 /* Initialize memory by storing the first byte. */
4168 emit_move_insn (adjust_address (dst, QImode, 0), val);
4169
4170 if (INTVAL (len) > 1)
4171 {
4172 /* Initiate 1 byte overlap move.
4173 The first byte of DST is propagated through DSTP1.
4174 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4175 DST is set to size 1 so the rest of the memory location
4176 does not count as source operand. */
4177 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4178 set_mem_size (dst, const1_rtx);
4179
4180 emit_insn (gen_movmem_short (dstp1, dst,
4181 GEN_INT (INTVAL (len) - 2)));
4182 }
4183 }
4184 }
4185
4186 else if (TARGET_MVCLE)
4187 {
4188 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4189 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4190 }
4191
4192 else
4193 {
4194 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4195 rtx loop_start_label = gen_label_rtx ();
4196 rtx loop_end_label = gen_label_rtx ();
4197 rtx end_label = gen_label_rtx ();
4198 enum machine_mode mode;
4199
4200 mode = GET_MODE (len);
4201 if (mode == VOIDmode)
4202 mode = Pmode;
4203
4204 dst_addr = gen_reg_rtx (Pmode);
4205 count = gen_reg_rtx (mode);
4206 blocks = gen_reg_rtx (mode);
4207
4208 convert_move (count, len, 1);
4209 emit_cmp_and_jump_insns (count, const0_rtx,
4210 EQ, NULL_RTX, mode, 1, end_label);
4211
4212 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4213 dst = change_address (dst, VOIDmode, dst_addr);
4214
4215 if (val == const0_rtx)
4216 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4217 OPTAB_DIRECT);
4218 else
4219 {
4220 dstp1 = adjust_address (dst, VOIDmode, 1);
4221 set_mem_size (dst, const1_rtx);
4222
4223 /* Initialize memory by storing the first byte. */
4224 emit_move_insn (adjust_address (dst, QImode, 0), val);
4225
4226 /* If count is 1 we are done. */
4227 emit_cmp_and_jump_insns (count, const1_rtx,
4228 EQ, NULL_RTX, mode, 1, end_label);
4229
4230 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4231 OPTAB_DIRECT);
4232 }
4233 if (temp != count)
4234 emit_move_insn (count, temp);
4235
4236 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4237 OPTAB_DIRECT);
4238 if (temp != blocks)
4239 emit_move_insn (blocks, temp);
4240
4241 emit_cmp_and_jump_insns (blocks, const0_rtx,
4242 EQ, NULL_RTX, mode, 1, loop_end_label);
4243
4244 emit_label (loop_start_label);
4245
4246 if (TARGET_Z10
4247 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4248 {
4249 /* Issue a write prefetch for the +4 cache line. */
4250 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4251 GEN_INT (1024)),
4252 const1_rtx, const0_rtx);
4253 emit_insn (prefetch);
4254 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4255 }
4256
4257 if (val == const0_rtx)
4258 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4259 else
4260 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4261 s390_load_address (dst_addr,
4262 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4263
4264 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4265 OPTAB_DIRECT);
4266 if (temp != blocks)
4267 emit_move_insn (blocks, temp);
4268
4269 emit_cmp_and_jump_insns (blocks, const0_rtx,
4270 EQ, NULL_RTX, mode, 1, loop_end_label);
4271
4272 emit_jump (loop_start_label);
4273 emit_label (loop_end_label);
4274
4275 if (val == const0_rtx)
4276 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4277 else
4278 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4279 emit_label (end_label);
4280 }
4281 }
4282
4283 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4284 and return the result in TARGET. */
4285
4286 void
4287 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4288 {
4289 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4290 rtx tmp;
4291
4292 /* As the result of CMPINT is inverted compared to what we need,
4293 we have to swap the operands. */
4294 tmp = op0; op0 = op1; op1 = tmp;
4295
4296 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4297 {
4298 if (INTVAL (len) > 0)
4299 {
4300 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4301 emit_insn (gen_cmpint (target, ccreg));
4302 }
4303 else
4304 emit_move_insn (target, const0_rtx);
4305 }
4306 else if (TARGET_MVCLE)
4307 {
4308 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4309 emit_insn (gen_cmpint (target, ccreg));
4310 }
4311 else
4312 {
4313 rtx addr0, addr1, count, blocks, temp;
4314 rtx loop_start_label = gen_label_rtx ();
4315 rtx loop_end_label = gen_label_rtx ();
4316 rtx end_label = gen_label_rtx ();
4317 enum machine_mode mode;
4318
4319 mode = GET_MODE (len);
4320 if (mode == VOIDmode)
4321 mode = Pmode;
4322
4323 addr0 = gen_reg_rtx (Pmode);
4324 addr1 = gen_reg_rtx (Pmode);
4325 count = gen_reg_rtx (mode);
4326 blocks = gen_reg_rtx (mode);
4327
4328 convert_move (count, len, 1);
4329 emit_cmp_and_jump_insns (count, const0_rtx,
4330 EQ, NULL_RTX, mode, 1, end_label);
4331
4332 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4333 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4334 op0 = change_address (op0, VOIDmode, addr0);
4335 op1 = change_address (op1, VOIDmode, addr1);
4336
4337 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4338 OPTAB_DIRECT);
4339 if (temp != count)
4340 emit_move_insn (count, temp);
4341
4342 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4343 OPTAB_DIRECT);
4344 if (temp != blocks)
4345 emit_move_insn (blocks, temp);
4346
4347 emit_cmp_and_jump_insns (blocks, const0_rtx,
4348 EQ, NULL_RTX, mode, 1, loop_end_label);
4349
4350 emit_label (loop_start_label);
4351
4352 if (TARGET_Z10
4353 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4354 {
4355 rtx prefetch;
4356
4357 /* Issue a read prefetch for the +2 cache line of operand 1. */
4358 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4359 const0_rtx, const0_rtx);
4360 emit_insn (prefetch);
4361 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4362
4363 /* Issue a read prefetch for the +2 cache line of operand 2. */
4364 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4365 const0_rtx, const0_rtx);
4366 emit_insn (prefetch);
4367 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4368 }
4369
4370 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4371 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4372 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4373 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4374 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4375 emit_jump_insn (temp);
4376
4377 s390_load_address (addr0,
4378 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4379 s390_load_address (addr1,
4380 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4381
4382 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4383 OPTAB_DIRECT);
4384 if (temp != blocks)
4385 emit_move_insn (blocks, temp);
4386
4387 emit_cmp_and_jump_insns (blocks, const0_rtx,
4388 EQ, NULL_RTX, mode, 1, loop_end_label);
4389
4390 emit_jump (loop_start_label);
4391 emit_label (loop_end_label);
4392
4393 emit_insn (gen_cmpmem_short (op0, op1,
4394 convert_to_mode (Pmode, count, 1)));
4395 emit_label (end_label);
4396
4397 emit_insn (gen_cmpint (target, ccreg));
4398 }
4399 }
4400
4401
4402 /* Expand conditional increment or decrement using alc/slb instructions.
4403 Should generate code setting DST to either SRC or SRC + INCREMENT,
4404 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4405 Returns true if successful, false otherwise.
4406
4407 That makes it possible to implement some if-constructs without jumps e.g.:
4408 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4409 unsigned int a, b, c;
4410 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4411 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4412 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4413 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4414
4415 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4416 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4417 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4418 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4419 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4420
4421 bool
4422 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4423 rtx dst, rtx src, rtx increment)
4424 {
4425 enum machine_mode cmp_mode;
4426 enum machine_mode cc_mode;
4427 rtx op_res;
4428 rtx insn;
4429 rtvec p;
4430 int ret;
4431
4432 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4433 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4434 cmp_mode = SImode;
4435 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4436 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4437 cmp_mode = DImode;
4438 else
4439 return false;
4440
4441 /* Try ADD LOGICAL WITH CARRY. */
4442 if (increment == const1_rtx)
4443 {
4444 /* Determine CC mode to use. */
4445 if (cmp_code == EQ || cmp_code == NE)
4446 {
4447 if (cmp_op1 != const0_rtx)
4448 {
4449 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4450 NULL_RTX, 0, OPTAB_WIDEN);
4451 cmp_op1 = const0_rtx;
4452 }
4453
4454 cmp_code = cmp_code == EQ ? LEU : GTU;
4455 }
4456
4457 if (cmp_code == LTU || cmp_code == LEU)
4458 {
4459 rtx tem = cmp_op0;
4460 cmp_op0 = cmp_op1;
4461 cmp_op1 = tem;
4462 cmp_code = swap_condition (cmp_code);
4463 }
4464
4465 switch (cmp_code)
4466 {
4467 case GTU:
4468 cc_mode = CCUmode;
4469 break;
4470
4471 case GEU:
4472 cc_mode = CCL3mode;
4473 break;
4474
4475 default:
4476 return false;
4477 }
4478
4479 /* Emit comparison instruction pattern. */
4480 if (!register_operand (cmp_op0, cmp_mode))
4481 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4482
4483 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4484 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4485 /* We use insn_invalid_p here to add clobbers if required. */
4486 ret = insn_invalid_p (emit_insn (insn));
4487 gcc_assert (!ret);
4488
4489 /* Emit ALC instruction pattern. */
4490 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4491 gen_rtx_REG (cc_mode, CC_REGNUM),
4492 const0_rtx);
4493
4494 if (src != const0_rtx)
4495 {
4496 if (!register_operand (src, GET_MODE (dst)))
4497 src = force_reg (GET_MODE (dst), src);
4498
4499 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4500 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4501 }
4502
4503 p = rtvec_alloc (2);
4504 RTVEC_ELT (p, 0) =
4505 gen_rtx_SET (VOIDmode, dst, op_res);
4506 RTVEC_ELT (p, 1) =
4507 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4508 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4509
4510 return true;
4511 }
4512
4513 /* Try SUBTRACT LOGICAL WITH BORROW. */
4514 if (increment == constm1_rtx)
4515 {
4516 /* Determine CC mode to use. */
4517 if (cmp_code == EQ || cmp_code == NE)
4518 {
4519 if (cmp_op1 != const0_rtx)
4520 {
4521 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4522 NULL_RTX, 0, OPTAB_WIDEN);
4523 cmp_op1 = const0_rtx;
4524 }
4525
4526 cmp_code = cmp_code == EQ ? LEU : GTU;
4527 }
4528
4529 if (cmp_code == GTU || cmp_code == GEU)
4530 {
4531 rtx tem = cmp_op0;
4532 cmp_op0 = cmp_op1;
4533 cmp_op1 = tem;
4534 cmp_code = swap_condition (cmp_code);
4535 }
4536
4537 switch (cmp_code)
4538 {
4539 case LEU:
4540 cc_mode = CCUmode;
4541 break;
4542
4543 case LTU:
4544 cc_mode = CCL3mode;
4545 break;
4546
4547 default:
4548 return false;
4549 }
4550
4551 /* Emit comparison instruction pattern. */
4552 if (!register_operand (cmp_op0, cmp_mode))
4553 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4554
4555 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4556 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4557 /* We use insn_invalid_p here to add clobbers if required. */
4558 ret = insn_invalid_p (emit_insn (insn));
4559 gcc_assert (!ret);
4560
4561 /* Emit SLB instruction pattern. */
4562 if (!register_operand (src, GET_MODE (dst)))
4563 src = force_reg (GET_MODE (dst), src);
4564
4565 op_res = gen_rtx_MINUS (GET_MODE (dst),
4566 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4567 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4568 gen_rtx_REG (cc_mode, CC_REGNUM),
4569 const0_rtx));
4570 p = rtvec_alloc (2);
4571 RTVEC_ELT (p, 0) =
4572 gen_rtx_SET (VOIDmode, dst, op_res);
4573 RTVEC_ELT (p, 1) =
4574 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4575 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4576
4577 return true;
4578 }
4579
4580 return false;
4581 }
4582
4583 /* Expand code for the insv template. Return true if successful. */
4584
4585 bool
4586 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4587 {
4588 int bitsize = INTVAL (op1);
4589 int bitpos = INTVAL (op2);
4590
4591 /* On z10 we can use the risbg instruction to implement insv. */
4592 if (TARGET_Z10
4593 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4594 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4595 {
4596 rtx op;
4597 rtx clobber;
4598
4599 op = gen_rtx_SET (GET_MODE(src),
4600 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4601 src);
4602 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4603 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4604
4605 return true;
4606 }
4607
4608 /* We need byte alignment. */
4609 if (bitsize % BITS_PER_UNIT)
4610 return false;
4611
4612 if (bitpos == 0
4613 && memory_operand (dest, VOIDmode)
4614 && (register_operand (src, word_mode)
4615 || const_int_operand (src, VOIDmode)))
4616 {
4617 /* Emit standard pattern if possible. */
4618 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4619 if (GET_MODE_BITSIZE (mode) == bitsize)
4620 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4621
4622 /* (set (ze (mem)) (const_int)). */
4623 else if (const_int_operand (src, VOIDmode))
4624 {
4625 int size = bitsize / BITS_PER_UNIT;
4626 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4627 GET_MODE_SIZE (word_mode) - size);
4628
4629 dest = adjust_address (dest, BLKmode, 0);
4630 set_mem_size (dest, GEN_INT (size));
4631 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4632 }
4633
4634 /* (set (ze (mem)) (reg)). */
4635 else if (register_operand (src, word_mode))
4636 {
4637 if (bitsize <= GET_MODE_BITSIZE (SImode))
4638 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4639 const0_rtx), src);
4640 else
4641 {
4642 /* Emit st,stcmh sequence. */
4643 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4644 int size = stcmh_width / BITS_PER_UNIT;
4645
4646 emit_move_insn (adjust_address (dest, SImode, size),
4647 gen_lowpart (SImode, src));
4648 set_mem_size (dest, GEN_INT (size));
4649 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4650 (stcmh_width), const0_rtx),
4651 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4652 (GET_MODE_BITSIZE (SImode))));
4653 }
4654 }
4655 else
4656 return false;
4657
4658 return true;
4659 }
4660
4661 /* (set (ze (reg)) (const_int)). */
4662 if (TARGET_ZARCH
4663 && register_operand (dest, word_mode)
4664 && (bitpos % 16) == 0
4665 && (bitsize % 16) == 0
4666 && const_int_operand (src, VOIDmode))
4667 {
4668 HOST_WIDE_INT val = INTVAL (src);
4669 int regpos = bitpos + bitsize;
4670
4671 while (regpos > bitpos)
4672 {
4673 enum machine_mode putmode;
4674 int putsize;
4675
4676 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4677 putmode = SImode;
4678 else
4679 putmode = HImode;
4680
4681 putsize = GET_MODE_BITSIZE (putmode);
4682 regpos -= putsize;
4683 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4684 GEN_INT (putsize),
4685 GEN_INT (regpos)),
4686 gen_int_mode (val, putmode));
4687 val >>= putsize;
4688 }
4689 gcc_assert (regpos == bitpos);
4690 return true;
4691 }
4692
4693 return false;
4694 }
4695
4696 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4697 register that holds VAL of mode MODE shifted by COUNT bits. */
4698
4699 static inline rtx
4700 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4701 {
4702 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4703 NULL_RTX, 1, OPTAB_DIRECT);
4704 return expand_simple_binop (SImode, ASHIFT, val, count,
4705 NULL_RTX, 1, OPTAB_DIRECT);
4706 }
4707
4708 /* Structure to hold the initial parameters for a compare_and_swap operation
4709 in HImode and QImode. */
4710
4711 struct alignment_context
4712 {
4713 rtx memsi; /* SI aligned memory location. */
4714 rtx shift; /* Bit offset with regard to lsb. */
4715 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4716 rtx modemaski; /* ~modemask */
4717 bool aligned; /* True if memory is aligned, false else. */
4718 };
4719
4720 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4721 structure AC for transparent simplifying, if the memory alignment is known
4722 to be at least 32bit. MEM is the memory location for the actual operation
4723 and MODE its mode. */
4724
4725 static void
4726 init_alignment_context (struct alignment_context *ac, rtx mem,
4727 enum machine_mode mode)
4728 {
4729 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4730 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4731
4732 if (ac->aligned)
4733 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4734 else
4735 {
4736 /* Alignment is unknown. */
4737 rtx byteoffset, addr, align;
4738
4739 /* Force the address into a register. */
4740 addr = force_reg (Pmode, XEXP (mem, 0));
4741
4742 /* Align it to SImode. */
4743 align = expand_simple_binop (Pmode, AND, addr,
4744 GEN_INT (-GET_MODE_SIZE (SImode)),
4745 NULL_RTX, 1, OPTAB_DIRECT);
4746 /* Generate MEM. */
4747 ac->memsi = gen_rtx_MEM (SImode, align);
4748 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4749 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4750 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4751
4752 /* Calculate shiftcount. */
4753 byteoffset = expand_simple_binop (Pmode, AND, addr,
4754 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4755 NULL_RTX, 1, OPTAB_DIRECT);
4756 /* As we already have some offset, evaluate the remaining distance. */
4757 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4758 NULL_RTX, 1, OPTAB_DIRECT);
4759
4760 }
4761 /* Shift is the byte count, but we need the bitcount. */
4762 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4763 NULL_RTX, 1, OPTAB_DIRECT);
4764 /* Calculate masks. */
4765 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4766 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4767 NULL_RTX, 1, OPTAB_DIRECT);
4768 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4769 }
4770
4771 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4772 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4773 to set if CMP == MEM.
4774 CMP is never in memory for compare_and_swap_cc because
4775 expand_bool_compare_and_swap puts it into a register for later compare. */
4776
4777 void
4778 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4779 {
4780 struct alignment_context ac;
4781 rtx cmpv, newv, val, resv, cc;
4782 rtx res = gen_reg_rtx (SImode);
4783 rtx csloop = gen_label_rtx ();
4784 rtx csend = gen_label_rtx ();
4785
4786 gcc_assert (register_operand (target, VOIDmode));
4787 gcc_assert (MEM_P (mem));
4788
4789 init_alignment_context (&ac, mem, mode);
4790
4791 /* Shift the values to the correct bit positions. */
4792 if (!(ac.aligned && MEM_P (cmp)))
4793 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4794 if (!(ac.aligned && MEM_P (new_rtx)))
4795 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4796
4797 /* Load full word. Subsequent loads are performed by CS. */
4798 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4799 NULL_RTX, 1, OPTAB_DIRECT);
4800
4801 /* Start CS loop. */
4802 emit_label (csloop);
4803 /* val = "<mem>00..0<mem>"
4804 * cmp = "00..0<cmp>00..0"
4805 * new = "00..0<new>00..0"
4806 */
4807
4808 /* Patch cmp and new with val at correct position. */
4809 if (ac.aligned && MEM_P (cmp))
4810 {
4811 cmpv = force_reg (SImode, val);
4812 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4813 }
4814 else
4815 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4816 NULL_RTX, 1, OPTAB_DIRECT));
4817 if (ac.aligned && MEM_P (new_rtx))
4818 {
4819 newv = force_reg (SImode, val);
4820 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4821 }
4822 else
4823 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4824 NULL_RTX, 1, OPTAB_DIRECT));
4825
4826 /* Jump to end if we're done (likely?). */
4827 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4828 cmpv, newv));
4829
4830 /* Check for changes outside mode. */
4831 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4832 NULL_RTX, 1, OPTAB_DIRECT);
4833 cc = s390_emit_compare (NE, resv, val);
4834 emit_move_insn (val, resv);
4835 /* Loop internal if so. */
4836 s390_emit_jump (csloop, cc);
4837
4838 emit_label (csend);
4839
4840 /* Return the correct part of the bitfield. */
4841 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4842 NULL_RTX, 1, OPTAB_DIRECT), 1);
4843 }
4844
4845 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4846 and VAL the value to play with. If AFTER is true then store the value
4847 MEM holds after the operation, if AFTER is false then store the value MEM
4848 holds before the operation. If TARGET is zero then discard that value, else
4849 store it to TARGET. */
4850
4851 void
4852 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4853 rtx target, rtx mem, rtx val, bool after)
4854 {
4855 struct alignment_context ac;
4856 rtx cmp;
4857 rtx new_rtx = gen_reg_rtx (SImode);
4858 rtx orig = gen_reg_rtx (SImode);
4859 rtx csloop = gen_label_rtx ();
4860
4861 gcc_assert (!target || register_operand (target, VOIDmode));
4862 gcc_assert (MEM_P (mem));
4863
4864 init_alignment_context (&ac, mem, mode);
4865
4866 /* Shift val to the correct bit positions.
4867 Preserve "icm", but prevent "ex icm". */
4868 if (!(ac.aligned && code == SET && MEM_P (val)))
4869 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4870
4871 /* Further preparation insns. */
4872 if (code == PLUS || code == MINUS)
4873 emit_move_insn (orig, val);
4874 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4875 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4876 NULL_RTX, 1, OPTAB_DIRECT);
4877
4878 /* Load full word. Subsequent loads are performed by CS. */
4879 cmp = force_reg (SImode, ac.memsi);
4880
4881 /* Start CS loop. */
4882 emit_label (csloop);
4883 emit_move_insn (new_rtx, cmp);
4884
4885 /* Patch new with val at correct position. */
4886 switch (code)
4887 {
4888 case PLUS:
4889 case MINUS:
4890 val = expand_simple_binop (SImode, code, new_rtx, orig,
4891 NULL_RTX, 1, OPTAB_DIRECT);
4892 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4893 NULL_RTX, 1, OPTAB_DIRECT);
4894 /* FALLTHRU */
4895 case SET:
4896 if (ac.aligned && MEM_P (val))
4897 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4898 else
4899 {
4900 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4901 NULL_RTX, 1, OPTAB_DIRECT);
4902 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4903 NULL_RTX, 1, OPTAB_DIRECT);
4904 }
4905 break;
4906 case AND:
4907 case IOR:
4908 case XOR:
4909 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4910 NULL_RTX, 1, OPTAB_DIRECT);
4911 break;
4912 case MULT: /* NAND */
4913 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4914 NULL_RTX, 1, OPTAB_DIRECT);
4915 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4916 NULL_RTX, 1, OPTAB_DIRECT);
4917 break;
4918 default:
4919 gcc_unreachable ();
4920 }
4921
4922 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4923 ac.memsi, cmp, new_rtx));
4924
4925 /* Return the correct part of the bitfield. */
4926 if (target)
4927 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4928 after ? new_rtx : cmp, ac.shift,
4929 NULL_RTX, 1, OPTAB_DIRECT), 1);
4930 }
4931
4932 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4933 We need to emit DTP-relative relocations. */
4934
4935 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4936
4937 static void
4938 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4939 {
4940 switch (size)
4941 {
4942 case 4:
4943 fputs ("\t.long\t", file);
4944 break;
4945 case 8:
4946 fputs ("\t.quad\t", file);
4947 break;
4948 default:
4949 gcc_unreachable ();
4950 }
4951 output_addr_const (file, x);
4952 fputs ("@DTPOFF", file);
4953 }
4954
4955 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4956 /* Implement TARGET_MANGLE_TYPE. */
4957
4958 static const char *
4959 s390_mangle_type (const_tree type)
4960 {
4961 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4962 && TARGET_LONG_DOUBLE_128)
4963 return "g";
4964
4965 /* For all other types, use normal C++ mangling. */
4966 return NULL;
4967 }
4968 #endif
4969
4970 /* In the name of slightly smaller debug output, and to cater to
4971 general assembler lossage, recognize various UNSPEC sequences
4972 and turn them back into a direct symbol reference. */
4973
4974 static rtx
4975 s390_delegitimize_address (rtx orig_x)
4976 {
4977 rtx x, y;
4978
4979 orig_x = delegitimize_mem_from_attrs (orig_x);
4980 x = orig_x;
4981
4982 /* Extract the symbol ref from:
4983 (plus:SI (reg:SI 12 %r12)
4984 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4985 UNSPEC_GOTOFF/PLTOFF)))
4986 and
4987 (plus:SI (reg:SI 12 %r12)
4988 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4989 UNSPEC_GOTOFF/PLTOFF)
4990 (const_int 4 [0x4])))) */
4991 if (GET_CODE (x) == PLUS
4992 && REG_P (XEXP (x, 0))
4993 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
4994 && GET_CODE (XEXP (x, 1)) == CONST)
4995 {
4996 HOST_WIDE_INT offset = 0;
4997
4998 /* The const operand. */
4999 y = XEXP (XEXP (x, 1), 0);
5000
5001 if (GET_CODE (y) == PLUS
5002 && GET_CODE (XEXP (y, 1)) == CONST_INT)
5003 {
5004 offset = INTVAL (XEXP (y, 1));
5005 y = XEXP (y, 0);
5006 }
5007
5008 if (GET_CODE (y) == UNSPEC
5009 && (XINT (y, 1) == UNSPEC_GOTOFF
5010 || XINT (y, 1) == UNSPEC_PLTOFF))
5011 return plus_constant (XVECEXP (y, 0, 0), offset);
5012 }
5013
5014 if (GET_CODE (x) != MEM)
5015 return orig_x;
5016
5017 x = XEXP (x, 0);
5018 if (GET_CODE (x) == PLUS
5019 && GET_CODE (XEXP (x, 1)) == CONST
5020 && GET_CODE (XEXP (x, 0)) == REG
5021 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5022 {
5023 y = XEXP (XEXP (x, 1), 0);
5024 if (GET_CODE (y) == UNSPEC
5025 && XINT (y, 1) == UNSPEC_GOT)
5026 y = XVECEXP (y, 0, 0);
5027 else
5028 return orig_x;
5029 }
5030 else if (GET_CODE (x) == CONST)
5031 {
5032 /* Extract the symbol ref from:
5033 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5034 UNSPEC_PLT/GOTENT))) */
5035
5036 y = XEXP (x, 0);
5037 if (GET_CODE (y) == UNSPEC
5038 && (XINT (y, 1) == UNSPEC_GOTENT
5039 || XINT (y, 1) == UNSPEC_PLT))
5040 y = XVECEXP (y, 0, 0);
5041 else
5042 return orig_x;
5043 }
5044 else
5045 return orig_x;
5046
5047 if (GET_MODE (orig_x) != Pmode)
5048 {
5049 if (GET_MODE (orig_x) == BLKmode)
5050 return orig_x;
5051 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5052 if (y == NULL_RTX)
5053 return orig_x;
5054 }
5055 return y;
5056 }
5057
5058 /* Output operand OP to stdio stream FILE.
5059 OP is an address (register + offset) which is not used to address data;
5060 instead the rightmost bits are interpreted as the value. */
5061
5062 static void
5063 print_shift_count_operand (FILE *file, rtx op)
5064 {
5065 HOST_WIDE_INT offset;
5066 rtx base;
5067
5068 /* Extract base register and offset. */
5069 if (!s390_decompose_shift_count (op, &base, &offset))
5070 gcc_unreachable ();
5071
5072 /* Sanity check. */
5073 if (base)
5074 {
5075 gcc_assert (GET_CODE (base) == REG);
5076 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5077 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5078 }
5079
5080 /* Offsets are constricted to twelve bits. */
5081 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5082 if (base)
5083 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5084 }
5085
5086 /* See 'get_some_local_dynamic_name'. */
5087
5088 static int
5089 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5090 {
5091 rtx x = *px;
5092
5093 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5094 {
5095 x = get_pool_constant (x);
5096 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5097 }
5098
5099 if (GET_CODE (x) == SYMBOL_REF
5100 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5101 {
5102 cfun->machine->some_ld_name = XSTR (x, 0);
5103 return 1;
5104 }
5105
5106 return 0;
5107 }
5108
5109 /* Locate some local-dynamic symbol still in use by this function
5110 so that we can print its name in local-dynamic base patterns. */
5111
5112 static const char *
5113 get_some_local_dynamic_name (void)
5114 {
5115 rtx insn;
5116
5117 if (cfun->machine->some_ld_name)
5118 return cfun->machine->some_ld_name;
5119
5120 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5121 if (INSN_P (insn)
5122 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5123 return cfun->machine->some_ld_name;
5124
5125 gcc_unreachable ();
5126 }
5127
5128 /* Output machine-dependent UNSPECs occurring in address constant X
5129 in assembler syntax to stdio stream FILE. Returns true if the
5130 constant X could be recognized, false otherwise. */
5131
5132 static bool
5133 s390_output_addr_const_extra (FILE *file, rtx x)
5134 {
5135 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5136 switch (XINT (x, 1))
5137 {
5138 case UNSPEC_GOTENT:
5139 output_addr_const (file, XVECEXP (x, 0, 0));
5140 fprintf (file, "@GOTENT");
5141 return true;
5142 case UNSPEC_GOT:
5143 output_addr_const (file, XVECEXP (x, 0, 0));
5144 fprintf (file, "@GOT");
5145 return true;
5146 case UNSPEC_GOTOFF:
5147 output_addr_const (file, XVECEXP (x, 0, 0));
5148 fprintf (file, "@GOTOFF");
5149 return true;
5150 case UNSPEC_PLT:
5151 output_addr_const (file, XVECEXP (x, 0, 0));
5152 fprintf (file, "@PLT");
5153 return true;
5154 case UNSPEC_PLTOFF:
5155 output_addr_const (file, XVECEXP (x, 0, 0));
5156 fprintf (file, "@PLTOFF");
5157 return true;
5158 case UNSPEC_TLSGD:
5159 output_addr_const (file, XVECEXP (x, 0, 0));
5160 fprintf (file, "@TLSGD");
5161 return true;
5162 case UNSPEC_TLSLDM:
5163 assemble_name (file, get_some_local_dynamic_name ());
5164 fprintf (file, "@TLSLDM");
5165 return true;
5166 case UNSPEC_DTPOFF:
5167 output_addr_const (file, XVECEXP (x, 0, 0));
5168 fprintf (file, "@DTPOFF");
5169 return true;
5170 case UNSPEC_NTPOFF:
5171 output_addr_const (file, XVECEXP (x, 0, 0));
5172 fprintf (file, "@NTPOFF");
5173 return true;
5174 case UNSPEC_GOTNTPOFF:
5175 output_addr_const (file, XVECEXP (x, 0, 0));
5176 fprintf (file, "@GOTNTPOFF");
5177 return true;
5178 case UNSPEC_INDNTPOFF:
5179 output_addr_const (file, XVECEXP (x, 0, 0));
5180 fprintf (file, "@INDNTPOFF");
5181 return true;
5182 }
5183
5184 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5185 switch (XINT (x, 1))
5186 {
5187 case UNSPEC_POOL_OFFSET:
5188 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5189 output_addr_const (file, x);
5190 return true;
5191 }
5192 return false;
5193 }
5194
5195 /* Output address operand ADDR in assembler syntax to
5196 stdio stream FILE. */
5197
5198 void
5199 print_operand_address (FILE *file, rtx addr)
5200 {
5201 struct s390_address ad;
5202
5203 if (s390_symref_operand_p (addr, NULL, NULL))
5204 {
5205 if (!TARGET_Z10)
5206 {
5207 output_operand_lossage ("symbolic memory references are "
5208 "only supported on z10 or later");
5209 return;
5210 }
5211 output_addr_const (file, addr);
5212 return;
5213 }
5214
5215 if (!s390_decompose_address (addr, &ad)
5216 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5217 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5218 output_operand_lossage ("cannot decompose address");
5219
5220 if (ad.disp)
5221 output_addr_const (file, ad.disp);
5222 else
5223 fprintf (file, "0");
5224
5225 if (ad.base && ad.indx)
5226 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5227 reg_names[REGNO (ad.base)]);
5228 else if (ad.base)
5229 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5230 }
5231
5232 /* Output operand X in assembler syntax to stdio stream FILE.
5233 CODE specified the format flag. The following format flags
5234 are recognized:
5235
5236 'C': print opcode suffix for branch condition.
5237 'D': print opcode suffix for inverse branch condition.
5238 'E': print opcode suffix for branch on index instruction.
5239 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5240 'G': print the size of the operand in bytes.
5241 'O': print only the displacement of a memory reference.
5242 'R': print only the base register of a memory reference.
5243 'S': print S-type memory reference (base+displacement).
5244 'N': print the second word of a DImode operand.
5245 'M': print the second word of a TImode operand.
5246 'Y': print shift count operand.
5247
5248 'b': print integer X as if it's an unsigned byte.
5249 'c': print integer X as if it's an signed byte.
5250 'x': print integer X as if it's an unsigned halfword.
5251 'h': print integer X as if it's a signed halfword.
5252 'i': print the first nonzero HImode part of X.
5253 'j': print the first HImode part unequal to -1 of X.
5254 'k': print the first nonzero SImode part of X.
5255 'm': print the first SImode part unequal to -1 of X.
5256 'o': print integer X as if it's an unsigned 32bit word. */
5257
5258 void
5259 print_operand (FILE *file, rtx x, int code)
5260 {
5261 switch (code)
5262 {
5263 case 'C':
5264 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5265 return;
5266
5267 case 'D':
5268 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5269 return;
5270
5271 case 'E':
5272 if (GET_CODE (x) == LE)
5273 fprintf (file, "l");
5274 else if (GET_CODE (x) == GT)
5275 fprintf (file, "h");
5276 else
5277 output_operand_lossage ("invalid comparison operator "
5278 "for 'E' output modifier");
5279 return;
5280
5281 case 'J':
5282 if (GET_CODE (x) == SYMBOL_REF)
5283 {
5284 fprintf (file, "%s", ":tls_load:");
5285 output_addr_const (file, x);
5286 }
5287 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5288 {
5289 fprintf (file, "%s", ":tls_gdcall:");
5290 output_addr_const (file, XVECEXP (x, 0, 0));
5291 }
5292 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5293 {
5294 fprintf (file, "%s", ":tls_ldcall:");
5295 assemble_name (file, get_some_local_dynamic_name ());
5296 }
5297 else
5298 output_operand_lossage ("invalid reference for 'J' output modifier");
5299 return;
5300
5301 case 'G':
5302 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5303 return;
5304
5305 case 'O':
5306 {
5307 struct s390_address ad;
5308 int ret;
5309
5310 if (!MEM_P (x))
5311 {
5312 output_operand_lossage ("memory reference expected for "
5313 "'O' output modifier");
5314 return;
5315 }
5316
5317 ret = s390_decompose_address (XEXP (x, 0), &ad);
5318
5319 if (!ret
5320 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5321 || ad.indx)
5322 {
5323 output_operand_lossage ("invalid address for 'O' output modifier");
5324 return;
5325 }
5326
5327 if (ad.disp)
5328 output_addr_const (file, ad.disp);
5329 else
5330 fprintf (file, "0");
5331 }
5332 return;
5333
5334 case 'R':
5335 {
5336 struct s390_address ad;
5337 int ret;
5338
5339 if (!MEM_P (x))
5340 {
5341 output_operand_lossage ("memory reference expected for "
5342 "'R' output modifier");
5343 return;
5344 }
5345
5346 ret = s390_decompose_address (XEXP (x, 0), &ad);
5347
5348 if (!ret
5349 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5350 || ad.indx)
5351 {
5352 output_operand_lossage ("invalid address for 'R' output modifier");
5353 return;
5354 }
5355
5356 if (ad.base)
5357 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5358 else
5359 fprintf (file, "0");
5360 }
5361 return;
5362
5363 case 'S':
5364 {
5365 struct s390_address ad;
5366 int ret;
5367
5368 if (!MEM_P (x))
5369 {
5370 output_operand_lossage ("memory reference expected for "
5371 "'S' output modifier");
5372 return;
5373 }
5374 ret = s390_decompose_address (XEXP (x, 0), &ad);
5375
5376 if (!ret
5377 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5378 || ad.indx)
5379 {
5380 output_operand_lossage ("invalid address for 'S' output modifier");
5381 return;
5382 }
5383
5384 if (ad.disp)
5385 output_addr_const (file, ad.disp);
5386 else
5387 fprintf (file, "0");
5388
5389 if (ad.base)
5390 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5391 }
5392 return;
5393
5394 case 'N':
5395 if (GET_CODE (x) == REG)
5396 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5397 else if (GET_CODE (x) == MEM)
5398 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5399 else
5400 output_operand_lossage ("register or memory expression expected "
5401 "for 'N' output modifier");
5402 break;
5403
5404 case 'M':
5405 if (GET_CODE (x) == REG)
5406 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5407 else if (GET_CODE (x) == MEM)
5408 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5409 else
5410 output_operand_lossage ("register or memory expression expected "
5411 "for 'M' output modifier");
5412 break;
5413
5414 case 'Y':
5415 print_shift_count_operand (file, x);
5416 return;
5417 }
5418
5419 switch (GET_CODE (x))
5420 {
5421 case REG:
5422 fprintf (file, "%s", reg_names[REGNO (x)]);
5423 break;
5424
5425 case MEM:
5426 output_address (XEXP (x, 0));
5427 break;
5428
5429 case CONST:
5430 case CODE_LABEL:
5431 case LABEL_REF:
5432 case SYMBOL_REF:
5433 output_addr_const (file, x);
5434 break;
5435
5436 case CONST_INT:
5437 if (code == 'b')
5438 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5439 else if (code == 'c')
5440 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5441 else if (code == 'x')
5442 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5443 else if (code == 'h')
5444 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5445 else if (code == 'i')
5446 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5447 s390_extract_part (x, HImode, 0));
5448 else if (code == 'j')
5449 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5450 s390_extract_part (x, HImode, -1));
5451 else if (code == 'k')
5452 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5453 s390_extract_part (x, SImode, 0));
5454 else if (code == 'm')
5455 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5456 s390_extract_part (x, SImode, -1));
5457 else if (code == 'o')
5458 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5459 else
5460 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5461 break;
5462
5463 case CONST_DOUBLE:
5464 gcc_assert (GET_MODE (x) == VOIDmode);
5465 if (code == 'b')
5466 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5467 else if (code == 'x')
5468 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5469 else if (code == 'h')
5470 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5471 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5472 else
5473 {
5474 if (code == 0)
5475 output_operand_lossage ("invalid constant - try using "
5476 "an output modifier");
5477 else
5478 output_operand_lossage ("invalid constant for output modifier '%c'",
5479 code);
5480 }
5481 break;
5482
5483 default:
5484 if (code == 0)
5485 output_operand_lossage ("invalid expression - try using "
5486 "an output modifier");
5487 else
5488 output_operand_lossage ("invalid expression for output "
5489 "modifier '%c'", code);
5490 break;
5491 }
5492 }
5493
5494 /* Target hook for assembling integer objects. We need to define it
5495 here to work a round a bug in some versions of GAS, which couldn't
5496 handle values smaller than INT_MIN when printed in decimal. */
5497
5498 static bool
5499 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5500 {
5501 if (size == 8 && aligned_p
5502 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5503 {
5504 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5505 INTVAL (x));
5506 return true;
5507 }
5508 return default_assemble_integer (x, size, aligned_p);
5509 }
5510
5511 /* Returns true if register REGNO is used for forming
5512 a memory address in expression X. */
5513
5514 static bool
5515 reg_used_in_mem_p (int regno, rtx x)
5516 {
5517 enum rtx_code code = GET_CODE (x);
5518 int i, j;
5519 const char *fmt;
5520
5521 if (code == MEM)
5522 {
5523 if (refers_to_regno_p (regno, regno+1,
5524 XEXP (x, 0), 0))
5525 return true;
5526 }
5527 else if (code == SET
5528 && GET_CODE (SET_DEST (x)) == PC)
5529 {
5530 if (refers_to_regno_p (regno, regno+1,
5531 SET_SRC (x), 0))
5532 return true;
5533 }
5534
5535 fmt = GET_RTX_FORMAT (code);
5536 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5537 {
5538 if (fmt[i] == 'e'
5539 && reg_used_in_mem_p (regno, XEXP (x, i)))
5540 return true;
5541
5542 else if (fmt[i] == 'E')
5543 for (j = 0; j < XVECLEN (x, i); j++)
5544 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5545 return true;
5546 }
5547 return false;
5548 }
5549
5550 /* Returns true if expression DEP_RTX sets an address register
5551 used by instruction INSN to address memory. */
5552
5553 static bool
5554 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5555 {
5556 rtx target, pat;
5557
5558 if (GET_CODE (dep_rtx) == INSN)
5559 dep_rtx = PATTERN (dep_rtx);
5560
5561 if (GET_CODE (dep_rtx) == SET)
5562 {
5563 target = SET_DEST (dep_rtx);
5564 if (GET_CODE (target) == STRICT_LOW_PART)
5565 target = XEXP (target, 0);
5566 while (GET_CODE (target) == SUBREG)
5567 target = SUBREG_REG (target);
5568
5569 if (GET_CODE (target) == REG)
5570 {
5571 int regno = REGNO (target);
5572
5573 if (s390_safe_attr_type (insn) == TYPE_LA)
5574 {
5575 pat = PATTERN (insn);
5576 if (GET_CODE (pat) == PARALLEL)
5577 {
5578 gcc_assert (XVECLEN (pat, 0) == 2);
5579 pat = XVECEXP (pat, 0, 0);
5580 }
5581 gcc_assert (GET_CODE (pat) == SET);
5582 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5583 }
5584 else if (get_attr_atype (insn) == ATYPE_AGEN)
5585 return reg_used_in_mem_p (regno, PATTERN (insn));
5586 }
5587 }
5588 return false;
5589 }
5590
5591 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5592
5593 int
5594 s390_agen_dep_p (rtx dep_insn, rtx insn)
5595 {
5596 rtx dep_rtx = PATTERN (dep_insn);
5597 int i;
5598
5599 if (GET_CODE (dep_rtx) == SET
5600 && addr_generation_dependency_p (dep_rtx, insn))
5601 return 1;
5602 else if (GET_CODE (dep_rtx) == PARALLEL)
5603 {
5604 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5605 {
5606 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5607 return 1;
5608 }
5609 }
5610 return 0;
5611 }
5612
5613
5614 /* A C statement (sans semicolon) to update the integer scheduling priority
5615 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5616 reduce the priority to execute INSN later. Do not define this macro if
5617 you do not need to adjust the scheduling priorities of insns.
5618
5619 A STD instruction should be scheduled earlier,
5620 in order to use the bypass. */
5621 static int
5622 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5623 {
5624 if (! INSN_P (insn))
5625 return priority;
5626
5627 if (s390_tune != PROCESSOR_2084_Z990
5628 && s390_tune != PROCESSOR_2094_Z9_109
5629 && s390_tune != PROCESSOR_2097_Z10
5630 && s390_tune != PROCESSOR_2817_Z196)
5631 return priority;
5632
5633 switch (s390_safe_attr_type (insn))
5634 {
5635 case TYPE_FSTOREDF:
5636 case TYPE_FSTORESF:
5637 priority = priority << 3;
5638 break;
5639 case TYPE_STORE:
5640 case TYPE_STM:
5641 priority = priority << 1;
5642 break;
5643 default:
5644 break;
5645 }
5646 return priority;
5647 }
5648
5649
5650 /* The number of instructions that can be issued per cycle. */
5651
5652 static int
5653 s390_issue_rate (void)
5654 {
5655 switch (s390_tune)
5656 {
5657 case PROCESSOR_2084_Z990:
5658 case PROCESSOR_2094_Z9_109:
5659 case PROCESSOR_2817_Z196:
5660 return 3;
5661 case PROCESSOR_2097_Z10:
5662 return 2;
5663 default:
5664 return 1;
5665 }
5666 }
5667
5668 static int
5669 s390_first_cycle_multipass_dfa_lookahead (void)
5670 {
5671 return 4;
5672 }
5673
5674 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5675 Fix up MEMs as required. */
5676
5677 static void
5678 annotate_constant_pool_refs (rtx *x)
5679 {
5680 int i, j;
5681 const char *fmt;
5682
5683 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5684 || !CONSTANT_POOL_ADDRESS_P (*x));
5685
5686 /* Literal pool references can only occur inside a MEM ... */
5687 if (GET_CODE (*x) == MEM)
5688 {
5689 rtx memref = XEXP (*x, 0);
5690
5691 if (GET_CODE (memref) == SYMBOL_REF
5692 && CONSTANT_POOL_ADDRESS_P (memref))
5693 {
5694 rtx base = cfun->machine->base_reg;
5695 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5696 UNSPEC_LTREF);
5697
5698 *x = replace_equiv_address (*x, addr);
5699 return;
5700 }
5701
5702 if (GET_CODE (memref) == CONST
5703 && GET_CODE (XEXP (memref, 0)) == PLUS
5704 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5705 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5706 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5707 {
5708 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5709 rtx sym = XEXP (XEXP (memref, 0), 0);
5710 rtx base = cfun->machine->base_reg;
5711 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5712 UNSPEC_LTREF);
5713
5714 *x = replace_equiv_address (*x, plus_constant (addr, off));
5715 return;
5716 }
5717 }
5718
5719 /* ... or a load-address type pattern. */
5720 if (GET_CODE (*x) == SET)
5721 {
5722 rtx addrref = SET_SRC (*x);
5723
5724 if (GET_CODE (addrref) == SYMBOL_REF
5725 && CONSTANT_POOL_ADDRESS_P (addrref))
5726 {
5727 rtx base = cfun->machine->base_reg;
5728 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5729 UNSPEC_LTREF);
5730
5731 SET_SRC (*x) = addr;
5732 return;
5733 }
5734
5735 if (GET_CODE (addrref) == CONST
5736 && GET_CODE (XEXP (addrref, 0)) == PLUS
5737 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5738 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5739 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5740 {
5741 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5742 rtx sym = XEXP (XEXP (addrref, 0), 0);
5743 rtx base = cfun->machine->base_reg;
5744 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5745 UNSPEC_LTREF);
5746
5747 SET_SRC (*x) = plus_constant (addr, off);
5748 return;
5749 }
5750 }
5751
5752 /* Annotate LTREL_BASE as well. */
5753 if (GET_CODE (*x) == UNSPEC
5754 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5755 {
5756 rtx base = cfun->machine->base_reg;
5757 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5758 UNSPEC_LTREL_BASE);
5759 return;
5760 }
5761
5762 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5763 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5764 {
5765 if (fmt[i] == 'e')
5766 {
5767 annotate_constant_pool_refs (&XEXP (*x, i));
5768 }
5769 else if (fmt[i] == 'E')
5770 {
5771 for (j = 0; j < XVECLEN (*x, i); j++)
5772 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5773 }
5774 }
5775 }
5776
5777 /* Split all branches that exceed the maximum distance.
5778 Returns true if this created a new literal pool entry. */
5779
5780 static int
5781 s390_split_branches (void)
5782 {
5783 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5784 int new_literal = 0, ret;
5785 rtx insn, pat, tmp, target;
5786 rtx *label;
5787
5788 /* We need correct insn addresses. */
5789
5790 shorten_branches (get_insns ());
5791
5792 /* Find all branches that exceed 64KB, and split them. */
5793
5794 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5795 {
5796 if (GET_CODE (insn) != JUMP_INSN)
5797 continue;
5798
5799 pat = PATTERN (insn);
5800 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5801 pat = XVECEXP (pat, 0, 0);
5802 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5803 continue;
5804
5805 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5806 {
5807 label = &SET_SRC (pat);
5808 }
5809 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5810 {
5811 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5812 label = &XEXP (SET_SRC (pat), 1);
5813 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5814 label = &XEXP (SET_SRC (pat), 2);
5815 else
5816 continue;
5817 }
5818 else
5819 continue;
5820
5821 if (get_attr_length (insn) <= 4)
5822 continue;
5823
5824 /* We are going to use the return register as scratch register,
5825 make sure it will be saved/restored by the prologue/epilogue. */
5826 cfun_frame_layout.save_return_addr_p = 1;
5827
5828 if (!flag_pic)
5829 {
5830 new_literal = 1;
5831 tmp = force_const_mem (Pmode, *label);
5832 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5833 INSN_ADDRESSES_NEW (tmp, -1);
5834 annotate_constant_pool_refs (&PATTERN (tmp));
5835
5836 target = temp_reg;
5837 }
5838 else
5839 {
5840 new_literal = 1;
5841 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5842 UNSPEC_LTREL_OFFSET);
5843 target = gen_rtx_CONST (Pmode, target);
5844 target = force_const_mem (Pmode, target);
5845 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5846 INSN_ADDRESSES_NEW (tmp, -1);
5847 annotate_constant_pool_refs (&PATTERN (tmp));
5848
5849 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5850 cfun->machine->base_reg),
5851 UNSPEC_LTREL_BASE);
5852 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5853 }
5854
5855 ret = validate_change (insn, label, target, 0);
5856 gcc_assert (ret);
5857 }
5858
5859 return new_literal;
5860 }
5861
5862
5863 /* Find an annotated literal pool symbol referenced in RTX X,
5864 and store it at REF. Will abort if X contains references to
5865 more than one such pool symbol; multiple references to the same
5866 symbol are allowed, however.
5867
5868 The rtx pointed to by REF must be initialized to NULL_RTX
5869 by the caller before calling this routine. */
5870
5871 static void
5872 find_constant_pool_ref (rtx x, rtx *ref)
5873 {
5874 int i, j;
5875 const char *fmt;
5876
5877 /* Ignore LTREL_BASE references. */
5878 if (GET_CODE (x) == UNSPEC
5879 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5880 return;
5881 /* Likewise POOL_ENTRY insns. */
5882 if (GET_CODE (x) == UNSPEC_VOLATILE
5883 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5884 return;
5885
5886 gcc_assert (GET_CODE (x) != SYMBOL_REF
5887 || !CONSTANT_POOL_ADDRESS_P (x));
5888
5889 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5890 {
5891 rtx sym = XVECEXP (x, 0, 0);
5892 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5893 && CONSTANT_POOL_ADDRESS_P (sym));
5894
5895 if (*ref == NULL_RTX)
5896 *ref = sym;
5897 else
5898 gcc_assert (*ref == sym);
5899
5900 return;
5901 }
5902
5903 fmt = GET_RTX_FORMAT (GET_CODE (x));
5904 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5905 {
5906 if (fmt[i] == 'e')
5907 {
5908 find_constant_pool_ref (XEXP (x, i), ref);
5909 }
5910 else if (fmt[i] == 'E')
5911 {
5912 for (j = 0; j < XVECLEN (x, i); j++)
5913 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5914 }
5915 }
5916 }
5917
5918 /* Replace every reference to the annotated literal pool
5919 symbol REF in X by its base plus OFFSET. */
5920
5921 static void
5922 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5923 {
5924 int i, j;
5925 const char *fmt;
5926
5927 gcc_assert (*x != ref);
5928
5929 if (GET_CODE (*x) == UNSPEC
5930 && XINT (*x, 1) == UNSPEC_LTREF
5931 && XVECEXP (*x, 0, 0) == ref)
5932 {
5933 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5934 return;
5935 }
5936
5937 if (GET_CODE (*x) == PLUS
5938 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5939 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5940 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5941 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5942 {
5943 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5944 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5945 return;
5946 }
5947
5948 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5949 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5950 {
5951 if (fmt[i] == 'e')
5952 {
5953 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5954 }
5955 else if (fmt[i] == 'E')
5956 {
5957 for (j = 0; j < XVECLEN (*x, i); j++)
5958 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5959 }
5960 }
5961 }
5962
5963 /* Check whether X contains an UNSPEC_LTREL_BASE.
5964 Return its constant pool symbol if found, NULL_RTX otherwise. */
5965
5966 static rtx
5967 find_ltrel_base (rtx x)
5968 {
5969 int i, j;
5970 const char *fmt;
5971
5972 if (GET_CODE (x) == UNSPEC
5973 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5974 return XVECEXP (x, 0, 0);
5975
5976 fmt = GET_RTX_FORMAT (GET_CODE (x));
5977 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5978 {
5979 if (fmt[i] == 'e')
5980 {
5981 rtx fnd = find_ltrel_base (XEXP (x, i));
5982 if (fnd)
5983 return fnd;
5984 }
5985 else if (fmt[i] == 'E')
5986 {
5987 for (j = 0; j < XVECLEN (x, i); j++)
5988 {
5989 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5990 if (fnd)
5991 return fnd;
5992 }
5993 }
5994 }
5995
5996 return NULL_RTX;
5997 }
5998
5999 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6000
6001 static void
6002 replace_ltrel_base (rtx *x)
6003 {
6004 int i, j;
6005 const char *fmt;
6006
6007 if (GET_CODE (*x) == UNSPEC
6008 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6009 {
6010 *x = XVECEXP (*x, 0, 1);
6011 return;
6012 }
6013
6014 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6015 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6016 {
6017 if (fmt[i] == 'e')
6018 {
6019 replace_ltrel_base (&XEXP (*x, i));
6020 }
6021 else if (fmt[i] == 'E')
6022 {
6023 for (j = 0; j < XVECLEN (*x, i); j++)
6024 replace_ltrel_base (&XVECEXP (*x, i, j));
6025 }
6026 }
6027 }
6028
6029
6030 /* We keep a list of constants which we have to add to internal
6031 constant tables in the middle of large functions. */
6032
6033 #define NR_C_MODES 11
6034 enum machine_mode constant_modes[NR_C_MODES] =
6035 {
6036 TFmode, TImode, TDmode,
6037 DFmode, DImode, DDmode,
6038 SFmode, SImode, SDmode,
6039 HImode,
6040 QImode
6041 };
6042
6043 struct constant
6044 {
6045 struct constant *next;
6046 rtx value;
6047 rtx label;
6048 };
6049
6050 struct constant_pool
6051 {
6052 struct constant_pool *next;
6053 rtx first_insn;
6054 rtx pool_insn;
6055 bitmap insns;
6056 rtx emit_pool_after;
6057
6058 struct constant *constants[NR_C_MODES];
6059 struct constant *execute;
6060 rtx label;
6061 int size;
6062 };
6063
6064 /* Allocate new constant_pool structure. */
6065
6066 static struct constant_pool *
6067 s390_alloc_pool (void)
6068 {
6069 struct constant_pool *pool;
6070 int i;
6071
6072 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6073 pool->next = NULL;
6074 for (i = 0; i < NR_C_MODES; i++)
6075 pool->constants[i] = NULL;
6076
6077 pool->execute = NULL;
6078 pool->label = gen_label_rtx ();
6079 pool->first_insn = NULL_RTX;
6080 pool->pool_insn = NULL_RTX;
6081 pool->insns = BITMAP_ALLOC (NULL);
6082 pool->size = 0;
6083 pool->emit_pool_after = NULL_RTX;
6084
6085 return pool;
6086 }
6087
6088 /* Create new constant pool covering instructions starting at INSN
6089 and chain it to the end of POOL_LIST. */
6090
6091 static struct constant_pool *
6092 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6093 {
6094 struct constant_pool *pool, **prev;
6095
6096 pool = s390_alloc_pool ();
6097 pool->first_insn = insn;
6098
6099 for (prev = pool_list; *prev; prev = &(*prev)->next)
6100 ;
6101 *prev = pool;
6102
6103 return pool;
6104 }
6105
6106 /* End range of instructions covered by POOL at INSN and emit
6107 placeholder insn representing the pool. */
6108
6109 static void
6110 s390_end_pool (struct constant_pool *pool, rtx insn)
6111 {
6112 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6113
6114 if (!insn)
6115 insn = get_last_insn ();
6116
6117 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6118 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6119 }
6120
6121 /* Add INSN to the list of insns covered by POOL. */
6122
6123 static void
6124 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6125 {
6126 bitmap_set_bit (pool->insns, INSN_UID (insn));
6127 }
6128
6129 /* Return pool out of POOL_LIST that covers INSN. */
6130
6131 static struct constant_pool *
6132 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6133 {
6134 struct constant_pool *pool;
6135
6136 for (pool = pool_list; pool; pool = pool->next)
6137 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6138 break;
6139
6140 return pool;
6141 }
6142
6143 /* Add constant VAL of mode MODE to the constant pool POOL. */
6144
6145 static void
6146 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6147 {
6148 struct constant *c;
6149 int i;
6150
6151 for (i = 0; i < NR_C_MODES; i++)
6152 if (constant_modes[i] == mode)
6153 break;
6154 gcc_assert (i != NR_C_MODES);
6155
6156 for (c = pool->constants[i]; c != NULL; c = c->next)
6157 if (rtx_equal_p (val, c->value))
6158 break;
6159
6160 if (c == NULL)
6161 {
6162 c = (struct constant *) xmalloc (sizeof *c);
6163 c->value = val;
6164 c->label = gen_label_rtx ();
6165 c->next = pool->constants[i];
6166 pool->constants[i] = c;
6167 pool->size += GET_MODE_SIZE (mode);
6168 }
6169 }
6170
6171 /* Return an rtx that represents the offset of X from the start of
6172 pool POOL. */
6173
6174 static rtx
6175 s390_pool_offset (struct constant_pool *pool, rtx x)
6176 {
6177 rtx label;
6178
6179 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6180 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6181 UNSPEC_POOL_OFFSET);
6182 return gen_rtx_CONST (GET_MODE (x), x);
6183 }
6184
6185 /* Find constant VAL of mode MODE in the constant pool POOL.
6186 Return an RTX describing the distance from the start of
6187 the pool to the location of the new constant. */
6188
6189 static rtx
6190 s390_find_constant (struct constant_pool *pool, rtx val,
6191 enum machine_mode mode)
6192 {
6193 struct constant *c;
6194 int i;
6195
6196 for (i = 0; i < NR_C_MODES; i++)
6197 if (constant_modes[i] == mode)
6198 break;
6199 gcc_assert (i != NR_C_MODES);
6200
6201 for (c = pool->constants[i]; c != NULL; c = c->next)
6202 if (rtx_equal_p (val, c->value))
6203 break;
6204
6205 gcc_assert (c);
6206
6207 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6208 }
6209
6210 /* Check whether INSN is an execute. Return the label_ref to its
6211 execute target template if so, NULL_RTX otherwise. */
6212
6213 static rtx
6214 s390_execute_label (rtx insn)
6215 {
6216 if (GET_CODE (insn) == INSN
6217 && GET_CODE (PATTERN (insn)) == PARALLEL
6218 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6219 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6220 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6221
6222 return NULL_RTX;
6223 }
6224
6225 /* Add execute target for INSN to the constant pool POOL. */
6226
6227 static void
6228 s390_add_execute (struct constant_pool *pool, rtx insn)
6229 {
6230 struct constant *c;
6231
6232 for (c = pool->execute; c != NULL; c = c->next)
6233 if (INSN_UID (insn) == INSN_UID (c->value))
6234 break;
6235
6236 if (c == NULL)
6237 {
6238 c = (struct constant *) xmalloc (sizeof *c);
6239 c->value = insn;
6240 c->label = gen_label_rtx ();
6241 c->next = pool->execute;
6242 pool->execute = c;
6243 pool->size += 6;
6244 }
6245 }
6246
6247 /* Find execute target for INSN in the constant pool POOL.
6248 Return an RTX describing the distance from the start of
6249 the pool to the location of the execute target. */
6250
6251 static rtx
6252 s390_find_execute (struct constant_pool *pool, rtx insn)
6253 {
6254 struct constant *c;
6255
6256 for (c = pool->execute; c != NULL; c = c->next)
6257 if (INSN_UID (insn) == INSN_UID (c->value))
6258 break;
6259
6260 gcc_assert (c);
6261
6262 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6263 }
6264
6265 /* For an execute INSN, extract the execute target template. */
6266
6267 static rtx
6268 s390_execute_target (rtx insn)
6269 {
6270 rtx pattern = PATTERN (insn);
6271 gcc_assert (s390_execute_label (insn));
6272
6273 if (XVECLEN (pattern, 0) == 2)
6274 {
6275 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6276 }
6277 else
6278 {
6279 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6280 int i;
6281
6282 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6283 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6284
6285 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6286 }
6287
6288 return pattern;
6289 }
6290
6291 /* Indicate that INSN cannot be duplicated. This is the case for
6292 execute insns that carry a unique label. */
6293
6294 static bool
6295 s390_cannot_copy_insn_p (rtx insn)
6296 {
6297 rtx label = s390_execute_label (insn);
6298 return label && label != const0_rtx;
6299 }
6300
6301 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6302 do not emit the pool base label. */
6303
6304 static void
6305 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6306 {
6307 struct constant *c;
6308 rtx insn = pool->pool_insn;
6309 int i;
6310
6311 /* Switch to rodata section. */
6312 if (TARGET_CPU_ZARCH)
6313 {
6314 insn = emit_insn_after (gen_pool_section_start (), insn);
6315 INSN_ADDRESSES_NEW (insn, -1);
6316 }
6317
6318 /* Ensure minimum pool alignment. */
6319 if (TARGET_CPU_ZARCH)
6320 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6321 else
6322 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6323 INSN_ADDRESSES_NEW (insn, -1);
6324
6325 /* Emit pool base label. */
6326 if (!remote_label)
6327 {
6328 insn = emit_label_after (pool->label, insn);
6329 INSN_ADDRESSES_NEW (insn, -1);
6330 }
6331
6332 /* Dump constants in descending alignment requirement order,
6333 ensuring proper alignment for every constant. */
6334 for (i = 0; i < NR_C_MODES; i++)
6335 for (c = pool->constants[i]; c; c = c->next)
6336 {
6337 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6338 rtx value = copy_rtx (c->value);
6339 if (GET_CODE (value) == CONST
6340 && GET_CODE (XEXP (value, 0)) == UNSPEC
6341 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6342 && XVECLEN (XEXP (value, 0), 0) == 1)
6343 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6344
6345 insn = emit_label_after (c->label, insn);
6346 INSN_ADDRESSES_NEW (insn, -1);
6347
6348 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6349 gen_rtvec (1, value),
6350 UNSPECV_POOL_ENTRY);
6351 insn = emit_insn_after (value, insn);
6352 INSN_ADDRESSES_NEW (insn, -1);
6353 }
6354
6355 /* Ensure minimum alignment for instructions. */
6356 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6357 INSN_ADDRESSES_NEW (insn, -1);
6358
6359 /* Output in-pool execute template insns. */
6360 for (c = pool->execute; c; c = c->next)
6361 {
6362 insn = emit_label_after (c->label, insn);
6363 INSN_ADDRESSES_NEW (insn, -1);
6364
6365 insn = emit_insn_after (s390_execute_target (c->value), insn);
6366 INSN_ADDRESSES_NEW (insn, -1);
6367 }
6368
6369 /* Switch back to previous section. */
6370 if (TARGET_CPU_ZARCH)
6371 {
6372 insn = emit_insn_after (gen_pool_section_end (), insn);
6373 INSN_ADDRESSES_NEW (insn, -1);
6374 }
6375
6376 insn = emit_barrier_after (insn);
6377 INSN_ADDRESSES_NEW (insn, -1);
6378
6379 /* Remove placeholder insn. */
6380 remove_insn (pool->pool_insn);
6381 }
6382
6383 /* Free all memory used by POOL. */
6384
6385 static void
6386 s390_free_pool (struct constant_pool *pool)
6387 {
6388 struct constant *c, *next;
6389 int i;
6390
6391 for (i = 0; i < NR_C_MODES; i++)
6392 for (c = pool->constants[i]; c; c = next)
6393 {
6394 next = c->next;
6395 free (c);
6396 }
6397
6398 for (c = pool->execute; c; c = next)
6399 {
6400 next = c->next;
6401 free (c);
6402 }
6403
6404 BITMAP_FREE (pool->insns);
6405 free (pool);
6406 }
6407
6408
6409 /* Collect main literal pool. Return NULL on overflow. */
6410
6411 static struct constant_pool *
6412 s390_mainpool_start (void)
6413 {
6414 struct constant_pool *pool;
6415 rtx insn;
6416
6417 pool = s390_alloc_pool ();
6418
6419 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6420 {
6421 if (GET_CODE (insn) == INSN
6422 && GET_CODE (PATTERN (insn)) == SET
6423 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6424 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6425 {
6426 gcc_assert (!pool->pool_insn);
6427 pool->pool_insn = insn;
6428 }
6429
6430 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6431 {
6432 s390_add_execute (pool, insn);
6433 }
6434 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6435 {
6436 rtx pool_ref = NULL_RTX;
6437 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6438 if (pool_ref)
6439 {
6440 rtx constant = get_pool_constant (pool_ref);
6441 enum machine_mode mode = get_pool_mode (pool_ref);
6442 s390_add_constant (pool, constant, mode);
6443 }
6444 }
6445
6446 /* If hot/cold partitioning is enabled we have to make sure that
6447 the literal pool is emitted in the same section where the
6448 initialization of the literal pool base pointer takes place.
6449 emit_pool_after is only used in the non-overflow case on non
6450 Z cpus where we can emit the literal pool at the end of the
6451 function body within the text section. */
6452 if (NOTE_P (insn)
6453 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6454 && !pool->emit_pool_after)
6455 pool->emit_pool_after = PREV_INSN (insn);
6456 }
6457
6458 gcc_assert (pool->pool_insn || pool->size == 0);
6459
6460 if (pool->size >= 4096)
6461 {
6462 /* We're going to chunkify the pool, so remove the main
6463 pool placeholder insn. */
6464 remove_insn (pool->pool_insn);
6465
6466 s390_free_pool (pool);
6467 pool = NULL;
6468 }
6469
6470 /* If the functions ends with the section where the literal pool
6471 should be emitted set the marker to its end. */
6472 if (pool && !pool->emit_pool_after)
6473 pool->emit_pool_after = get_last_insn ();
6474
6475 return pool;
6476 }
6477
6478 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6479 Modify the current function to output the pool constants as well as
6480 the pool register setup instruction. */
6481
6482 static void
6483 s390_mainpool_finish (struct constant_pool *pool)
6484 {
6485 rtx base_reg = cfun->machine->base_reg;
6486 rtx insn;
6487
6488 /* If the pool is empty, we're done. */
6489 if (pool->size == 0)
6490 {
6491 /* We don't actually need a base register after all. */
6492 cfun->machine->base_reg = NULL_RTX;
6493
6494 if (pool->pool_insn)
6495 remove_insn (pool->pool_insn);
6496 s390_free_pool (pool);
6497 return;
6498 }
6499
6500 /* We need correct insn addresses. */
6501 shorten_branches (get_insns ());
6502
6503 /* On zSeries, we use a LARL to load the pool register. The pool is
6504 located in the .rodata section, so we emit it after the function. */
6505 if (TARGET_CPU_ZARCH)
6506 {
6507 insn = gen_main_base_64 (base_reg, pool->label);
6508 insn = emit_insn_after (insn, pool->pool_insn);
6509 INSN_ADDRESSES_NEW (insn, -1);
6510 remove_insn (pool->pool_insn);
6511
6512 insn = get_last_insn ();
6513 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6514 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6515
6516 s390_dump_pool (pool, 0);
6517 }
6518
6519 /* On S/390, if the total size of the function's code plus literal pool
6520 does not exceed 4096 bytes, we use BASR to set up a function base
6521 pointer, and emit the literal pool at the end of the function. */
6522 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6523 + pool->size + 8 /* alignment slop */ < 4096)
6524 {
6525 insn = gen_main_base_31_small (base_reg, pool->label);
6526 insn = emit_insn_after (insn, pool->pool_insn);
6527 INSN_ADDRESSES_NEW (insn, -1);
6528 remove_insn (pool->pool_insn);
6529
6530 insn = emit_label_after (pool->label, insn);
6531 INSN_ADDRESSES_NEW (insn, -1);
6532
6533 /* emit_pool_after will be set by s390_mainpool_start to the
6534 last insn of the section where the literal pool should be
6535 emitted. */
6536 insn = pool->emit_pool_after;
6537
6538 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6539 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6540
6541 s390_dump_pool (pool, 1);
6542 }
6543
6544 /* Otherwise, we emit an inline literal pool and use BASR to branch
6545 over it, setting up the pool register at the same time. */
6546 else
6547 {
6548 rtx pool_end = gen_label_rtx ();
6549
6550 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6551 insn = emit_insn_after (insn, pool->pool_insn);
6552 INSN_ADDRESSES_NEW (insn, -1);
6553 remove_insn (pool->pool_insn);
6554
6555 insn = emit_label_after (pool->label, insn);
6556 INSN_ADDRESSES_NEW (insn, -1);
6557
6558 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6559 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6560
6561 insn = emit_label_after (pool_end, pool->pool_insn);
6562 INSN_ADDRESSES_NEW (insn, -1);
6563
6564 s390_dump_pool (pool, 1);
6565 }
6566
6567
6568 /* Replace all literal pool references. */
6569
6570 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6571 {
6572 if (INSN_P (insn))
6573 replace_ltrel_base (&PATTERN (insn));
6574
6575 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6576 {
6577 rtx addr, pool_ref = NULL_RTX;
6578 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6579 if (pool_ref)
6580 {
6581 if (s390_execute_label (insn))
6582 addr = s390_find_execute (pool, insn);
6583 else
6584 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6585 get_pool_mode (pool_ref));
6586
6587 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6588 INSN_CODE (insn) = -1;
6589 }
6590 }
6591 }
6592
6593
6594 /* Free the pool. */
6595 s390_free_pool (pool);
6596 }
6597
6598 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6599 We have decided we cannot use this pool, so revert all changes
6600 to the current function that were done by s390_mainpool_start. */
6601 static void
6602 s390_mainpool_cancel (struct constant_pool *pool)
6603 {
6604 /* We didn't actually change the instruction stream, so simply
6605 free the pool memory. */
6606 s390_free_pool (pool);
6607 }
6608
6609
6610 /* Chunkify the literal pool. */
6611
6612 #define S390_POOL_CHUNK_MIN 0xc00
6613 #define S390_POOL_CHUNK_MAX 0xe00
6614
6615 static struct constant_pool *
6616 s390_chunkify_start (void)
6617 {
6618 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6619 int extra_size = 0;
6620 bitmap far_labels;
6621 rtx pending_ltrel = NULL_RTX;
6622 rtx insn;
6623
6624 rtx (*gen_reload_base) (rtx, rtx) =
6625 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6626
6627
6628 /* We need correct insn addresses. */
6629
6630 shorten_branches (get_insns ());
6631
6632 /* Scan all insns and move literals to pool chunks. */
6633
6634 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6635 {
6636 bool section_switch_p = false;
6637
6638 /* Check for pending LTREL_BASE. */
6639 if (INSN_P (insn))
6640 {
6641 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6642 if (ltrel_base)
6643 {
6644 gcc_assert (ltrel_base == pending_ltrel);
6645 pending_ltrel = NULL_RTX;
6646 }
6647 }
6648
6649 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6650 {
6651 if (!curr_pool)
6652 curr_pool = s390_start_pool (&pool_list, insn);
6653
6654 s390_add_execute (curr_pool, insn);
6655 s390_add_pool_insn (curr_pool, insn);
6656 }
6657 else if (GET_CODE (insn) == INSN || CALL_P (insn))
6658 {
6659 rtx pool_ref = NULL_RTX;
6660 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6661 if (pool_ref)
6662 {
6663 rtx constant = get_pool_constant (pool_ref);
6664 enum machine_mode mode = get_pool_mode (pool_ref);
6665
6666 if (!curr_pool)
6667 curr_pool = s390_start_pool (&pool_list, insn);
6668
6669 s390_add_constant (curr_pool, constant, mode);
6670 s390_add_pool_insn (curr_pool, insn);
6671
6672 /* Don't split the pool chunk between a LTREL_OFFSET load
6673 and the corresponding LTREL_BASE. */
6674 if (GET_CODE (constant) == CONST
6675 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6676 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6677 {
6678 gcc_assert (!pending_ltrel);
6679 pending_ltrel = pool_ref;
6680 }
6681 }
6682 /* Make sure we do not split between a call and its
6683 corresponding CALL_ARG_LOCATION note. */
6684 if (CALL_P (insn))
6685 {
6686 rtx next = NEXT_INSN (insn);
6687 if (next && NOTE_P (next)
6688 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
6689 continue;
6690 }
6691 }
6692
6693 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6694 {
6695 if (curr_pool)
6696 s390_add_pool_insn (curr_pool, insn);
6697 /* An LTREL_BASE must follow within the same basic block. */
6698 gcc_assert (!pending_ltrel);
6699 }
6700
6701 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6702 section_switch_p = true;
6703
6704 if (!curr_pool
6705 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6706 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6707 continue;
6708
6709 if (TARGET_CPU_ZARCH)
6710 {
6711 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6712 continue;
6713
6714 s390_end_pool (curr_pool, NULL_RTX);
6715 curr_pool = NULL;
6716 }
6717 else
6718 {
6719 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6720 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6721 + extra_size;
6722
6723 /* We will later have to insert base register reload insns.
6724 Those will have an effect on code size, which we need to
6725 consider here. This calculation makes rather pessimistic
6726 worst-case assumptions. */
6727 if (GET_CODE (insn) == CODE_LABEL)
6728 extra_size += 6;
6729
6730 if (chunk_size < S390_POOL_CHUNK_MIN
6731 && curr_pool->size < S390_POOL_CHUNK_MIN
6732 && !section_switch_p)
6733 continue;
6734
6735 /* Pool chunks can only be inserted after BARRIERs ... */
6736 if (GET_CODE (insn) == BARRIER)
6737 {
6738 s390_end_pool (curr_pool, insn);
6739 curr_pool = NULL;
6740 extra_size = 0;
6741 }
6742
6743 /* ... so if we don't find one in time, create one. */
6744 else if (chunk_size > S390_POOL_CHUNK_MAX
6745 || curr_pool->size > S390_POOL_CHUNK_MAX
6746 || section_switch_p)
6747 {
6748 rtx label, jump, barrier;
6749
6750 if (!section_switch_p)
6751 {
6752 /* We can insert the barrier only after a 'real' insn. */
6753 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6754 continue;
6755 if (get_attr_length (insn) == 0)
6756 continue;
6757 /* Don't separate LTREL_BASE from the corresponding
6758 LTREL_OFFSET load. */
6759 if (pending_ltrel)
6760 continue;
6761 }
6762 else
6763 {
6764 gcc_assert (!pending_ltrel);
6765
6766 /* The old pool has to end before the section switch
6767 note in order to make it part of the current
6768 section. */
6769 insn = PREV_INSN (insn);
6770 }
6771
6772 label = gen_label_rtx ();
6773 jump = emit_jump_insn_after (gen_jump (label), insn);
6774 barrier = emit_barrier_after (jump);
6775 insn = emit_label_after (label, barrier);
6776 JUMP_LABEL (jump) = label;
6777 LABEL_NUSES (label) = 1;
6778
6779 INSN_ADDRESSES_NEW (jump, -1);
6780 INSN_ADDRESSES_NEW (barrier, -1);
6781 INSN_ADDRESSES_NEW (insn, -1);
6782
6783 s390_end_pool (curr_pool, barrier);
6784 curr_pool = NULL;
6785 extra_size = 0;
6786 }
6787 }
6788 }
6789
6790 if (curr_pool)
6791 s390_end_pool (curr_pool, NULL_RTX);
6792 gcc_assert (!pending_ltrel);
6793
6794 /* Find all labels that are branched into
6795 from an insn belonging to a different chunk. */
6796
6797 far_labels = BITMAP_ALLOC (NULL);
6798
6799 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6800 {
6801 /* Labels marked with LABEL_PRESERVE_P can be target
6802 of non-local jumps, so we have to mark them.
6803 The same holds for named labels.
6804
6805 Don't do that, however, if it is the label before
6806 a jump table. */
6807
6808 if (GET_CODE (insn) == CODE_LABEL
6809 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6810 {
6811 rtx vec_insn = next_real_insn (insn);
6812 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6813 PATTERN (vec_insn) : NULL_RTX;
6814 if (!vec_pat
6815 || !(GET_CODE (vec_pat) == ADDR_VEC
6816 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6817 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6818 }
6819
6820 /* If we have a direct jump (conditional or unconditional)
6821 or a casesi jump, check all potential targets. */
6822 else if (GET_CODE (insn) == JUMP_INSN)
6823 {
6824 rtx pat = PATTERN (insn);
6825 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6826 pat = XVECEXP (pat, 0, 0);
6827
6828 if (GET_CODE (pat) == SET)
6829 {
6830 rtx label = JUMP_LABEL (insn);
6831 if (label)
6832 {
6833 if (s390_find_pool (pool_list, label)
6834 != s390_find_pool (pool_list, insn))
6835 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6836 }
6837 }
6838 else if (GET_CODE (pat) == PARALLEL
6839 && XVECLEN (pat, 0) == 2
6840 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6841 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6842 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6843 {
6844 /* Find the jump table used by this casesi jump. */
6845 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6846 rtx vec_insn = next_real_insn (vec_label);
6847 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6848 PATTERN (vec_insn) : NULL_RTX;
6849 if (vec_pat
6850 && (GET_CODE (vec_pat) == ADDR_VEC
6851 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6852 {
6853 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6854
6855 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6856 {
6857 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6858
6859 if (s390_find_pool (pool_list, label)
6860 != s390_find_pool (pool_list, insn))
6861 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6862 }
6863 }
6864 }
6865 }
6866 }
6867
6868 /* Insert base register reload insns before every pool. */
6869
6870 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6871 {
6872 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6873 curr_pool->label);
6874 rtx insn = curr_pool->first_insn;
6875 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6876 }
6877
6878 /* Insert base register reload insns at every far label. */
6879
6880 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6881 if (GET_CODE (insn) == CODE_LABEL
6882 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6883 {
6884 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6885 if (pool)
6886 {
6887 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6888 pool->label);
6889 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6890 }
6891 }
6892
6893
6894 BITMAP_FREE (far_labels);
6895
6896
6897 /* Recompute insn addresses. */
6898
6899 init_insn_lengths ();
6900 shorten_branches (get_insns ());
6901
6902 return pool_list;
6903 }
6904
6905 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6906 After we have decided to use this list, finish implementing
6907 all changes to the current function as required. */
6908
6909 static void
6910 s390_chunkify_finish (struct constant_pool *pool_list)
6911 {
6912 struct constant_pool *curr_pool = NULL;
6913 rtx insn;
6914
6915
6916 /* Replace all literal pool references. */
6917
6918 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6919 {
6920 if (INSN_P (insn))
6921 replace_ltrel_base (&PATTERN (insn));
6922
6923 curr_pool = s390_find_pool (pool_list, insn);
6924 if (!curr_pool)
6925 continue;
6926
6927 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6928 {
6929 rtx addr, pool_ref = NULL_RTX;
6930 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6931 if (pool_ref)
6932 {
6933 if (s390_execute_label (insn))
6934 addr = s390_find_execute (curr_pool, insn);
6935 else
6936 addr = s390_find_constant (curr_pool,
6937 get_pool_constant (pool_ref),
6938 get_pool_mode (pool_ref));
6939
6940 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6941 INSN_CODE (insn) = -1;
6942 }
6943 }
6944 }
6945
6946 /* Dump out all literal pools. */
6947
6948 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6949 s390_dump_pool (curr_pool, 0);
6950
6951 /* Free pool list. */
6952
6953 while (pool_list)
6954 {
6955 struct constant_pool *next = pool_list->next;
6956 s390_free_pool (pool_list);
6957 pool_list = next;
6958 }
6959 }
6960
6961 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6962 We have decided we cannot use this list, so revert all changes
6963 to the current function that were done by s390_chunkify_start. */
6964
6965 static void
6966 s390_chunkify_cancel (struct constant_pool *pool_list)
6967 {
6968 struct constant_pool *curr_pool = NULL;
6969 rtx insn;
6970
6971 /* Remove all pool placeholder insns. */
6972
6973 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6974 {
6975 /* Did we insert an extra barrier? Remove it. */
6976 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6977 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6978 rtx label = NEXT_INSN (curr_pool->pool_insn);
6979
6980 if (jump && GET_CODE (jump) == JUMP_INSN
6981 && barrier && GET_CODE (barrier) == BARRIER
6982 && label && GET_CODE (label) == CODE_LABEL
6983 && GET_CODE (PATTERN (jump)) == SET
6984 && SET_DEST (PATTERN (jump)) == pc_rtx
6985 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6986 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6987 {
6988 remove_insn (jump);
6989 remove_insn (barrier);
6990 remove_insn (label);
6991 }
6992
6993 remove_insn (curr_pool->pool_insn);
6994 }
6995
6996 /* Remove all base register reload insns. */
6997
6998 for (insn = get_insns (); insn; )
6999 {
7000 rtx next_insn = NEXT_INSN (insn);
7001
7002 if (GET_CODE (insn) == INSN
7003 && GET_CODE (PATTERN (insn)) == SET
7004 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
7005 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
7006 remove_insn (insn);
7007
7008 insn = next_insn;
7009 }
7010
7011 /* Free pool list. */
7012
7013 while (pool_list)
7014 {
7015 struct constant_pool *next = pool_list->next;
7016 s390_free_pool (pool_list);
7017 pool_list = next;
7018 }
7019 }
7020
7021 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7022
7023 void
7024 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
7025 {
7026 REAL_VALUE_TYPE r;
7027
7028 switch (GET_MODE_CLASS (mode))
7029 {
7030 case MODE_FLOAT:
7031 case MODE_DECIMAL_FLOAT:
7032 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7033
7034 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7035 assemble_real (r, mode, align);
7036 break;
7037
7038 case MODE_INT:
7039 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7040 mark_symbol_refs_as_used (exp);
7041 break;
7042
7043 default:
7044 gcc_unreachable ();
7045 }
7046 }
7047
7048
7049 /* Return an RTL expression representing the value of the return address
7050 for the frame COUNT steps up from the current frame. FRAME is the
7051 frame pointer of that frame. */
7052
7053 rtx
7054 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7055 {
7056 int offset;
7057 rtx addr;
7058
7059 /* Without backchain, we fail for all but the current frame. */
7060
7061 if (!TARGET_BACKCHAIN && count > 0)
7062 return NULL_RTX;
7063
7064 /* For the current frame, we need to make sure the initial
7065 value of RETURN_REGNUM is actually saved. */
7066
7067 if (count == 0)
7068 {
7069 /* On non-z architectures branch splitting could overwrite r14. */
7070 if (TARGET_CPU_ZARCH)
7071 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7072 else
7073 {
7074 cfun_frame_layout.save_return_addr_p = true;
7075 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7076 }
7077 }
7078
7079 if (TARGET_PACKED_STACK)
7080 offset = -2 * UNITS_PER_LONG;
7081 else
7082 offset = RETURN_REGNUM * UNITS_PER_LONG;
7083
7084 addr = plus_constant (frame, offset);
7085 addr = memory_address (Pmode, addr);
7086 return gen_rtx_MEM (Pmode, addr);
7087 }
7088
7089 /* Return an RTL expression representing the back chain stored in
7090 the current stack frame. */
7091
7092 rtx
7093 s390_back_chain_rtx (void)
7094 {
7095 rtx chain;
7096
7097 gcc_assert (TARGET_BACKCHAIN);
7098
7099 if (TARGET_PACKED_STACK)
7100 chain = plus_constant (stack_pointer_rtx,
7101 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7102 else
7103 chain = stack_pointer_rtx;
7104
7105 chain = gen_rtx_MEM (Pmode, chain);
7106 return chain;
7107 }
7108
7109 /* Find first call clobbered register unused in a function.
7110 This could be used as base register in a leaf function
7111 or for holding the return address before epilogue. */
7112
7113 static int
7114 find_unused_clobbered_reg (void)
7115 {
7116 int i;
7117 for (i = 0; i < 6; i++)
7118 if (!df_regs_ever_live_p (i))
7119 return i;
7120 return 0;
7121 }
7122
7123
7124 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7125 clobbered hard regs in SETREG. */
7126
7127 static void
7128 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7129 {
7130 int *regs_ever_clobbered = (int *)data;
7131 unsigned int i, regno;
7132 enum machine_mode mode = GET_MODE (setreg);
7133
7134 if (GET_CODE (setreg) == SUBREG)
7135 {
7136 rtx inner = SUBREG_REG (setreg);
7137 if (!GENERAL_REG_P (inner))
7138 return;
7139 regno = subreg_regno (setreg);
7140 }
7141 else if (GENERAL_REG_P (setreg))
7142 regno = REGNO (setreg);
7143 else
7144 return;
7145
7146 for (i = regno;
7147 i < regno + HARD_REGNO_NREGS (regno, mode);
7148 i++)
7149 regs_ever_clobbered[i] = 1;
7150 }
7151
7152 /* Walks through all basic blocks of the current function looking
7153 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7154 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7155 each of those regs. */
7156
7157 static void
7158 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7159 {
7160 basic_block cur_bb;
7161 rtx cur_insn;
7162 unsigned int i;
7163
7164 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7165
7166 /* For non-leaf functions we have to consider all call clobbered regs to be
7167 clobbered. */
7168 if (!current_function_is_leaf)
7169 {
7170 for (i = 0; i < 16; i++)
7171 regs_ever_clobbered[i] = call_really_used_regs[i];
7172 }
7173
7174 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7175 this work is done by liveness analysis (mark_regs_live_at_end).
7176 Special care is needed for functions containing landing pads. Landing pads
7177 may use the eh registers, but the code which sets these registers is not
7178 contained in that function. Hence s390_regs_ever_clobbered is not able to
7179 deal with this automatically. */
7180 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7181 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7182 if (crtl->calls_eh_return
7183 || (cfun->machine->has_landing_pad_p
7184 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7185 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7186
7187 /* For nonlocal gotos all call-saved registers have to be saved.
7188 This flag is also set for the unwinding code in libgcc.
7189 See expand_builtin_unwind_init. For regs_ever_live this is done by
7190 reload. */
7191 if (cfun->has_nonlocal_label)
7192 for (i = 0; i < 16; i++)
7193 if (!call_really_used_regs[i])
7194 regs_ever_clobbered[i] = 1;
7195
7196 FOR_EACH_BB (cur_bb)
7197 {
7198 FOR_BB_INSNS (cur_bb, cur_insn)
7199 {
7200 if (INSN_P (cur_insn))
7201 note_stores (PATTERN (cur_insn),
7202 s390_reg_clobbered_rtx,
7203 regs_ever_clobbered);
7204 }
7205 }
7206 }
7207
7208 /* Determine the frame area which actually has to be accessed
7209 in the function epilogue. The values are stored at the
7210 given pointers AREA_BOTTOM (address of the lowest used stack
7211 address) and AREA_TOP (address of the first item which does
7212 not belong to the stack frame). */
7213
7214 static void
7215 s390_frame_area (int *area_bottom, int *area_top)
7216 {
7217 int b, t;
7218 int i;
7219
7220 b = INT_MAX;
7221 t = INT_MIN;
7222
7223 if (cfun_frame_layout.first_restore_gpr != -1)
7224 {
7225 b = (cfun_frame_layout.gprs_offset
7226 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7227 t = b + (cfun_frame_layout.last_restore_gpr
7228 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7229 }
7230
7231 if (TARGET_64BIT && cfun_save_high_fprs_p)
7232 {
7233 b = MIN (b, cfun_frame_layout.f8_offset);
7234 t = MAX (t, (cfun_frame_layout.f8_offset
7235 + cfun_frame_layout.high_fprs * 8));
7236 }
7237
7238 if (!TARGET_64BIT)
7239 for (i = 2; i < 4; i++)
7240 if (cfun_fpr_bit_p (i))
7241 {
7242 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7243 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7244 }
7245
7246 *area_bottom = b;
7247 *area_top = t;
7248 }
7249
7250 /* Fill cfun->machine with info about register usage of current function.
7251 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7252
7253 static void
7254 s390_register_info (int clobbered_regs[])
7255 {
7256 int i, j;
7257
7258 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7259 cfun_frame_layout.fpr_bitmap = 0;
7260 cfun_frame_layout.high_fprs = 0;
7261 if (TARGET_64BIT)
7262 for (i = 24; i < 32; i++)
7263 if (df_regs_ever_live_p (i) && !global_regs[i])
7264 {
7265 cfun_set_fpr_bit (i - 16);
7266 cfun_frame_layout.high_fprs++;
7267 }
7268
7269 /* Find first and last gpr to be saved. We trust regs_ever_live
7270 data, except that we don't save and restore global registers.
7271
7272 Also, all registers with special meaning to the compiler need
7273 to be handled extra. */
7274
7275 s390_regs_ever_clobbered (clobbered_regs);
7276
7277 for (i = 0; i < 16; i++)
7278 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7279
7280 if (frame_pointer_needed)
7281 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7282
7283 if (flag_pic)
7284 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7285 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7286
7287 clobbered_regs[BASE_REGNUM]
7288 |= (cfun->machine->base_reg
7289 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7290
7291 clobbered_regs[RETURN_REGNUM]
7292 |= (!current_function_is_leaf
7293 || TARGET_TPF_PROFILING
7294 || cfun->machine->split_branches_pending_p
7295 || cfun_frame_layout.save_return_addr_p
7296 || crtl->calls_eh_return
7297 || cfun->stdarg);
7298
7299 clobbered_regs[STACK_POINTER_REGNUM]
7300 |= (!current_function_is_leaf
7301 || TARGET_TPF_PROFILING
7302 || cfun_save_high_fprs_p
7303 || get_frame_size () > 0
7304 || cfun->calls_alloca
7305 || cfun->stdarg);
7306
7307 for (i = 6; i < 16; i++)
7308 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7309 break;
7310 for (j = 15; j > i; j--)
7311 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7312 break;
7313
7314 if (i == 16)
7315 {
7316 /* Nothing to save/restore. */
7317 cfun_frame_layout.first_save_gpr_slot = -1;
7318 cfun_frame_layout.last_save_gpr_slot = -1;
7319 cfun_frame_layout.first_save_gpr = -1;
7320 cfun_frame_layout.first_restore_gpr = -1;
7321 cfun_frame_layout.last_save_gpr = -1;
7322 cfun_frame_layout.last_restore_gpr = -1;
7323 }
7324 else
7325 {
7326 /* Save slots for gprs from i to j. */
7327 cfun_frame_layout.first_save_gpr_slot = i;
7328 cfun_frame_layout.last_save_gpr_slot = j;
7329
7330 for (i = cfun_frame_layout.first_save_gpr_slot;
7331 i < cfun_frame_layout.last_save_gpr_slot + 1;
7332 i++)
7333 if (clobbered_regs[i])
7334 break;
7335
7336 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7337 if (clobbered_regs[j])
7338 break;
7339
7340 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7341 {
7342 /* Nothing to save/restore. */
7343 cfun_frame_layout.first_save_gpr = -1;
7344 cfun_frame_layout.first_restore_gpr = -1;
7345 cfun_frame_layout.last_save_gpr = -1;
7346 cfun_frame_layout.last_restore_gpr = -1;
7347 }
7348 else
7349 {
7350 /* Save / Restore from gpr i to j. */
7351 cfun_frame_layout.first_save_gpr = i;
7352 cfun_frame_layout.first_restore_gpr = i;
7353 cfun_frame_layout.last_save_gpr = j;
7354 cfun_frame_layout.last_restore_gpr = j;
7355 }
7356 }
7357
7358 if (cfun->stdarg)
7359 {
7360 /* Varargs functions need to save gprs 2 to 6. */
7361 if (cfun->va_list_gpr_size
7362 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7363 {
7364 int min_gpr = crtl->args.info.gprs;
7365 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7366 if (max_gpr > GP_ARG_NUM_REG)
7367 max_gpr = GP_ARG_NUM_REG;
7368
7369 if (cfun_frame_layout.first_save_gpr == -1
7370 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7371 {
7372 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7373 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7374 }
7375
7376 if (cfun_frame_layout.last_save_gpr == -1
7377 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7378 {
7379 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7380 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7381 }
7382 }
7383
7384 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7385 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7386 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7387 {
7388 int min_fpr = crtl->args.info.fprs;
7389 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7390 if (max_fpr > FP_ARG_NUM_REG)
7391 max_fpr = FP_ARG_NUM_REG;
7392
7393 /* ??? This is currently required to ensure proper location
7394 of the fpr save slots within the va_list save area. */
7395 if (TARGET_PACKED_STACK)
7396 min_fpr = 0;
7397
7398 for (i = min_fpr; i < max_fpr; i++)
7399 cfun_set_fpr_bit (i);
7400 }
7401 }
7402
7403 if (!TARGET_64BIT)
7404 for (i = 2; i < 4; i++)
7405 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7406 cfun_set_fpr_bit (i);
7407 }
7408
7409 /* Fill cfun->machine with info about frame of current function. */
7410
7411 static void
7412 s390_frame_info (void)
7413 {
7414 int i;
7415
7416 cfun_frame_layout.frame_size = get_frame_size ();
7417 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7418 fatal_error ("total size of local variables exceeds architecture limit");
7419
7420 if (!TARGET_PACKED_STACK)
7421 {
7422 cfun_frame_layout.backchain_offset = 0;
7423 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7424 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7425 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7426 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7427 * UNITS_PER_LONG);
7428 }
7429 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7430 {
7431 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7432 - UNITS_PER_LONG);
7433 cfun_frame_layout.gprs_offset
7434 = (cfun_frame_layout.backchain_offset
7435 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7436 * UNITS_PER_LONG);
7437
7438 if (TARGET_64BIT)
7439 {
7440 cfun_frame_layout.f4_offset
7441 = (cfun_frame_layout.gprs_offset
7442 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7443
7444 cfun_frame_layout.f0_offset
7445 = (cfun_frame_layout.f4_offset
7446 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7447 }
7448 else
7449 {
7450 /* On 31 bit we have to care about alignment of the
7451 floating point regs to provide fastest access. */
7452 cfun_frame_layout.f0_offset
7453 = ((cfun_frame_layout.gprs_offset
7454 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7455 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7456
7457 cfun_frame_layout.f4_offset
7458 = (cfun_frame_layout.f0_offset
7459 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7460 }
7461 }
7462 else /* no backchain */
7463 {
7464 cfun_frame_layout.f4_offset
7465 = (STACK_POINTER_OFFSET
7466 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7467
7468 cfun_frame_layout.f0_offset
7469 = (cfun_frame_layout.f4_offset
7470 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7471
7472 cfun_frame_layout.gprs_offset
7473 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7474 }
7475
7476 if (current_function_is_leaf
7477 && !TARGET_TPF_PROFILING
7478 && cfun_frame_layout.frame_size == 0
7479 && !cfun_save_high_fprs_p
7480 && !cfun->calls_alloca
7481 && !cfun->stdarg)
7482 return;
7483
7484 if (!TARGET_PACKED_STACK)
7485 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7486 + crtl->outgoing_args_size
7487 + cfun_frame_layout.high_fprs * 8);
7488 else
7489 {
7490 if (TARGET_BACKCHAIN)
7491 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7492
7493 /* No alignment trouble here because f8-f15 are only saved under
7494 64 bit. */
7495 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7496 cfun_frame_layout.f4_offset),
7497 cfun_frame_layout.gprs_offset)
7498 - cfun_frame_layout.high_fprs * 8);
7499
7500 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7501
7502 for (i = 0; i < 8; i++)
7503 if (cfun_fpr_bit_p (i))
7504 cfun_frame_layout.frame_size += 8;
7505
7506 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7507
7508 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7509 the frame size to sustain 8 byte alignment of stack frames. */
7510 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7511 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7512 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7513
7514 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7515 }
7516 }
7517
7518 /* Generate frame layout. Fills in register and frame data for the current
7519 function in cfun->machine. This routine can be called multiple times;
7520 it will re-do the complete frame layout every time. */
7521
7522 static void
7523 s390_init_frame_layout (void)
7524 {
7525 HOST_WIDE_INT frame_size;
7526 int base_used;
7527 int clobbered_regs[16];
7528
7529 /* On S/390 machines, we may need to perform branch splitting, which
7530 will require both base and return address register. We have no
7531 choice but to assume we're going to need them until right at the
7532 end of the machine dependent reorg phase. */
7533 if (!TARGET_CPU_ZARCH)
7534 cfun->machine->split_branches_pending_p = true;
7535
7536 do
7537 {
7538 frame_size = cfun_frame_layout.frame_size;
7539
7540 /* Try to predict whether we'll need the base register. */
7541 base_used = cfun->machine->split_branches_pending_p
7542 || crtl->uses_const_pool
7543 || (!DISP_IN_RANGE (frame_size)
7544 && !CONST_OK_FOR_K (frame_size));
7545
7546 /* Decide which register to use as literal pool base. In small
7547 leaf functions, try to use an unused call-clobbered register
7548 as base register to avoid save/restore overhead. */
7549 if (!base_used)
7550 cfun->machine->base_reg = NULL_RTX;
7551 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7552 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7553 else
7554 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7555
7556 s390_register_info (clobbered_regs);
7557 s390_frame_info ();
7558 }
7559 while (frame_size != cfun_frame_layout.frame_size);
7560 }
7561
7562 /* Update frame layout. Recompute actual register save data based on
7563 current info and update regs_ever_live for the special registers.
7564 May be called multiple times, but may never cause *more* registers
7565 to be saved than s390_init_frame_layout allocated room for. */
7566
7567 static void
7568 s390_update_frame_layout (void)
7569 {
7570 int clobbered_regs[16];
7571
7572 s390_register_info (clobbered_regs);
7573
7574 df_set_regs_ever_live (BASE_REGNUM,
7575 clobbered_regs[BASE_REGNUM] ? true : false);
7576 df_set_regs_ever_live (RETURN_REGNUM,
7577 clobbered_regs[RETURN_REGNUM] ? true : false);
7578 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7579 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7580
7581 if (cfun->machine->base_reg)
7582 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7583 }
7584
7585 /* Return true if it is legal to put a value with MODE into REGNO. */
7586
7587 bool
7588 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7589 {
7590 switch (REGNO_REG_CLASS (regno))
7591 {
7592 case FP_REGS:
7593 if (REGNO_PAIR_OK (regno, mode))
7594 {
7595 if (mode == SImode || mode == DImode)
7596 return true;
7597
7598 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7599 return true;
7600 }
7601 break;
7602 case ADDR_REGS:
7603 if (FRAME_REGNO_P (regno) && mode == Pmode)
7604 return true;
7605
7606 /* fallthrough */
7607 case GENERAL_REGS:
7608 if (REGNO_PAIR_OK (regno, mode))
7609 {
7610 if (TARGET_ZARCH
7611 || (mode != TFmode && mode != TCmode && mode != TDmode))
7612 return true;
7613 }
7614 break;
7615 case CC_REGS:
7616 if (GET_MODE_CLASS (mode) == MODE_CC)
7617 return true;
7618 break;
7619 case ACCESS_REGS:
7620 if (REGNO_PAIR_OK (regno, mode))
7621 {
7622 if (mode == SImode || mode == Pmode)
7623 return true;
7624 }
7625 break;
7626 default:
7627 return false;
7628 }
7629
7630 return false;
7631 }
7632
7633 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7634
7635 bool
7636 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7637 {
7638 /* Once we've decided upon a register to use as base register, it must
7639 no longer be used for any other purpose. */
7640 if (cfun->machine->base_reg)
7641 if (REGNO (cfun->machine->base_reg) == old_reg
7642 || REGNO (cfun->machine->base_reg) == new_reg)
7643 return false;
7644
7645 return true;
7646 }
7647
7648 /* Maximum number of registers to represent a value of mode MODE
7649 in a register of class RCLASS. */
7650
7651 bool
7652 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7653 {
7654 switch (rclass)
7655 {
7656 case FP_REGS:
7657 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7658 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7659 else
7660 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7661 case ACCESS_REGS:
7662 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7663 default:
7664 break;
7665 }
7666 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7667 }
7668
7669 /* Return true if register FROM can be eliminated via register TO. */
7670
7671 static bool
7672 s390_can_eliminate (const int from, const int to)
7673 {
7674 /* On zSeries machines, we have not marked the base register as fixed.
7675 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7676 If a function requires the base register, we say here that this
7677 elimination cannot be performed. This will cause reload to free
7678 up the base register (as if it were fixed). On the other hand,
7679 if the current function does *not* require the base register, we
7680 say here the elimination succeeds, which in turn allows reload
7681 to allocate the base register for any other purpose. */
7682 if (from == BASE_REGNUM && to == BASE_REGNUM)
7683 {
7684 if (TARGET_CPU_ZARCH)
7685 {
7686 s390_init_frame_layout ();
7687 return cfun->machine->base_reg == NULL_RTX;
7688 }
7689
7690 return false;
7691 }
7692
7693 /* Everything else must point into the stack frame. */
7694 gcc_assert (to == STACK_POINTER_REGNUM
7695 || to == HARD_FRAME_POINTER_REGNUM);
7696
7697 gcc_assert (from == FRAME_POINTER_REGNUM
7698 || from == ARG_POINTER_REGNUM
7699 || from == RETURN_ADDRESS_POINTER_REGNUM);
7700
7701 /* Make sure we actually saved the return address. */
7702 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7703 if (!crtl->calls_eh_return
7704 && !cfun->stdarg
7705 && !cfun_frame_layout.save_return_addr_p)
7706 return false;
7707
7708 return true;
7709 }
7710
7711 /* Return offset between register FROM and TO initially after prolog. */
7712
7713 HOST_WIDE_INT
7714 s390_initial_elimination_offset (int from, int to)
7715 {
7716 HOST_WIDE_INT offset;
7717 int index;
7718
7719 /* ??? Why are we called for non-eliminable pairs? */
7720 if (!s390_can_eliminate (from, to))
7721 return 0;
7722
7723 switch (from)
7724 {
7725 case FRAME_POINTER_REGNUM:
7726 offset = (get_frame_size()
7727 + STACK_POINTER_OFFSET
7728 + crtl->outgoing_args_size);
7729 break;
7730
7731 case ARG_POINTER_REGNUM:
7732 s390_init_frame_layout ();
7733 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7734 break;
7735
7736 case RETURN_ADDRESS_POINTER_REGNUM:
7737 s390_init_frame_layout ();
7738 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7739 gcc_assert (index >= 0);
7740 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7741 offset += index * UNITS_PER_LONG;
7742 break;
7743
7744 case BASE_REGNUM:
7745 offset = 0;
7746 break;
7747
7748 default:
7749 gcc_unreachable ();
7750 }
7751
7752 return offset;
7753 }
7754
7755 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7756 to register BASE. Return generated insn. */
7757
7758 static rtx
7759 save_fpr (rtx base, int offset, int regnum)
7760 {
7761 rtx addr;
7762 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7763
7764 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7765 set_mem_alias_set (addr, get_varargs_alias_set ());
7766 else
7767 set_mem_alias_set (addr, get_frame_alias_set ());
7768
7769 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7770 }
7771
7772 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7773 to register BASE. Return generated insn. */
7774
7775 static rtx
7776 restore_fpr (rtx base, int offset, int regnum)
7777 {
7778 rtx addr;
7779 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7780 set_mem_alias_set (addr, get_frame_alias_set ());
7781
7782 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7783 }
7784
7785 /* Return true if REGNO is a global register, but not one
7786 of the special ones that need to be saved/restored in anyway. */
7787
7788 static inline bool
7789 global_not_special_regno_p (int regno)
7790 {
7791 return (global_regs[regno]
7792 /* These registers are special and need to be
7793 restored in any case. */
7794 && !(regno == STACK_POINTER_REGNUM
7795 || regno == RETURN_REGNUM
7796 || regno == BASE_REGNUM
7797 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7798 }
7799
7800 /* Generate insn to save registers FIRST to LAST into
7801 the register save area located at offset OFFSET
7802 relative to register BASE. */
7803
7804 static rtx
7805 save_gprs (rtx base, int offset, int first, int last)
7806 {
7807 rtx addr, insn, note;
7808 int i;
7809
7810 addr = plus_constant (base, offset);
7811 addr = gen_rtx_MEM (Pmode, addr);
7812
7813 set_mem_alias_set (addr, get_frame_alias_set ());
7814
7815 /* Special-case single register. */
7816 if (first == last)
7817 {
7818 if (TARGET_64BIT)
7819 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7820 else
7821 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7822
7823 if (!global_not_special_regno_p (first))
7824 RTX_FRAME_RELATED_P (insn) = 1;
7825 return insn;
7826 }
7827
7828
7829 insn = gen_store_multiple (addr,
7830 gen_rtx_REG (Pmode, first),
7831 GEN_INT (last - first + 1));
7832
7833 if (first <= 6 && cfun->stdarg)
7834 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7835 {
7836 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7837
7838 if (first + i <= 6)
7839 set_mem_alias_set (mem, get_varargs_alias_set ());
7840 }
7841
7842 /* We need to set the FRAME_RELATED flag on all SETs
7843 inside the store-multiple pattern.
7844
7845 However, we must not emit DWARF records for registers 2..5
7846 if they are stored for use by variable arguments ...
7847
7848 ??? Unfortunately, it is not enough to simply not the
7849 FRAME_RELATED flags for those SETs, because the first SET
7850 of the PARALLEL is always treated as if it had the flag
7851 set, even if it does not. Therefore we emit a new pattern
7852 without those registers as REG_FRAME_RELATED_EXPR note. */
7853
7854 if (first >= 6 && !global_not_special_regno_p (first))
7855 {
7856 rtx pat = PATTERN (insn);
7857
7858 for (i = 0; i < XVECLEN (pat, 0); i++)
7859 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7860 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7861 0, i)))))
7862 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7863
7864 RTX_FRAME_RELATED_P (insn) = 1;
7865 }
7866 else if (last >= 6)
7867 {
7868 int start;
7869
7870 for (start = first >= 6 ? first : 6; start <= last; start++)
7871 if (!global_not_special_regno_p (start))
7872 break;
7873
7874 if (start > last)
7875 return insn;
7876
7877 addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7878 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7879 gen_rtx_REG (Pmode, start),
7880 GEN_INT (last - start + 1));
7881 note = PATTERN (note);
7882
7883 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7884
7885 for (i = 0; i < XVECLEN (note, 0); i++)
7886 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7887 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7888 0, i)))))
7889 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7890
7891 RTX_FRAME_RELATED_P (insn) = 1;
7892 }
7893
7894 return insn;
7895 }
7896
7897 /* Generate insn to restore registers FIRST to LAST from
7898 the register save area located at offset OFFSET
7899 relative to register BASE. */
7900
7901 static rtx
7902 restore_gprs (rtx base, int offset, int first, int last)
7903 {
7904 rtx addr, insn;
7905
7906 addr = plus_constant (base, offset);
7907 addr = gen_rtx_MEM (Pmode, addr);
7908 set_mem_alias_set (addr, get_frame_alias_set ());
7909
7910 /* Special-case single register. */
7911 if (first == last)
7912 {
7913 if (TARGET_64BIT)
7914 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7915 else
7916 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7917
7918 return insn;
7919 }
7920
7921 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7922 addr,
7923 GEN_INT (last - first + 1));
7924 return insn;
7925 }
7926
7927 /* Return insn sequence to load the GOT register. */
7928
7929 static GTY(()) rtx got_symbol;
7930 rtx
7931 s390_load_got (void)
7932 {
7933 rtx insns;
7934
7935 if (!got_symbol)
7936 {
7937 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7938 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7939 }
7940
7941 start_sequence ();
7942
7943 if (TARGET_CPU_ZARCH)
7944 {
7945 emit_move_insn (pic_offset_table_rtx, got_symbol);
7946 }
7947 else
7948 {
7949 rtx offset;
7950
7951 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7952 UNSPEC_LTREL_OFFSET);
7953 offset = gen_rtx_CONST (Pmode, offset);
7954 offset = force_const_mem (Pmode, offset);
7955
7956 emit_move_insn (pic_offset_table_rtx, offset);
7957
7958 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7959 UNSPEC_LTREL_BASE);
7960 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7961
7962 emit_move_insn (pic_offset_table_rtx, offset);
7963 }
7964
7965 insns = get_insns ();
7966 end_sequence ();
7967 return insns;
7968 }
7969
7970 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7971 and the change to the stack pointer. */
7972
7973 static void
7974 s390_emit_stack_tie (void)
7975 {
7976 rtx mem = gen_frame_mem (BLKmode,
7977 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7978
7979 emit_insn (gen_stack_tie (mem));
7980 }
7981
7982 /* Expand the prologue into a bunch of separate insns. */
7983
7984 void
7985 s390_emit_prologue (void)
7986 {
7987 rtx insn, addr;
7988 rtx temp_reg;
7989 int i;
7990 int offset;
7991 int next_fpr = 0;
7992
7993 /* Complete frame layout. */
7994
7995 s390_update_frame_layout ();
7996
7997 /* Annotate all constant pool references to let the scheduler know
7998 they implicitly use the base register. */
7999
8000 push_topmost_sequence ();
8001
8002 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8003 if (INSN_P (insn))
8004 {
8005 annotate_constant_pool_refs (&PATTERN (insn));
8006 df_insn_rescan (insn);
8007 }
8008
8009 pop_topmost_sequence ();
8010
8011 /* Choose best register to use for temp use within prologue.
8012 See below for why TPF must use the register 1. */
8013
8014 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8015 && !current_function_is_leaf
8016 && !TARGET_TPF_PROFILING)
8017 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8018 else
8019 temp_reg = gen_rtx_REG (Pmode, 1);
8020
8021 /* Save call saved gprs. */
8022 if (cfun_frame_layout.first_save_gpr != -1)
8023 {
8024 insn = save_gprs (stack_pointer_rtx,
8025 cfun_frame_layout.gprs_offset +
8026 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8027 - cfun_frame_layout.first_save_gpr_slot),
8028 cfun_frame_layout.first_save_gpr,
8029 cfun_frame_layout.last_save_gpr);
8030 emit_insn (insn);
8031 }
8032
8033 /* Dummy insn to mark literal pool slot. */
8034
8035 if (cfun->machine->base_reg)
8036 emit_insn (gen_main_pool (cfun->machine->base_reg));
8037
8038 offset = cfun_frame_layout.f0_offset;
8039
8040 /* Save f0 and f2. */
8041 for (i = 0; i < 2; i++)
8042 {
8043 if (cfun_fpr_bit_p (i))
8044 {
8045 save_fpr (stack_pointer_rtx, offset, i + 16);
8046 offset += 8;
8047 }
8048 else if (!TARGET_PACKED_STACK)
8049 offset += 8;
8050 }
8051
8052 /* Save f4 and f6. */
8053 offset = cfun_frame_layout.f4_offset;
8054 for (i = 2; i < 4; i++)
8055 {
8056 if (cfun_fpr_bit_p (i))
8057 {
8058 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8059 offset += 8;
8060
8061 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8062 therefore are not frame related. */
8063 if (!call_really_used_regs[i + 16])
8064 RTX_FRAME_RELATED_P (insn) = 1;
8065 }
8066 else if (!TARGET_PACKED_STACK)
8067 offset += 8;
8068 }
8069
8070 if (TARGET_PACKED_STACK
8071 && cfun_save_high_fprs_p
8072 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8073 {
8074 offset = (cfun_frame_layout.f8_offset
8075 + (cfun_frame_layout.high_fprs - 1) * 8);
8076
8077 for (i = 15; i > 7 && offset >= 0; i--)
8078 if (cfun_fpr_bit_p (i))
8079 {
8080 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8081
8082 RTX_FRAME_RELATED_P (insn) = 1;
8083 offset -= 8;
8084 }
8085 if (offset >= cfun_frame_layout.f8_offset)
8086 next_fpr = i + 16;
8087 }
8088
8089 if (!TARGET_PACKED_STACK)
8090 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8091
8092 if (flag_stack_usage)
8093 current_function_static_stack_size = cfun_frame_layout.frame_size;
8094
8095 /* Decrement stack pointer. */
8096
8097 if (cfun_frame_layout.frame_size > 0)
8098 {
8099 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8100 rtx real_frame_off;
8101
8102 if (s390_stack_size)
8103 {
8104 HOST_WIDE_INT stack_guard;
8105
8106 if (s390_stack_guard)
8107 stack_guard = s390_stack_guard;
8108 else
8109 {
8110 /* If no value for stack guard is provided the smallest power of 2
8111 larger than the current frame size is chosen. */
8112 stack_guard = 1;
8113 while (stack_guard < cfun_frame_layout.frame_size)
8114 stack_guard <<= 1;
8115 }
8116
8117 if (cfun_frame_layout.frame_size >= s390_stack_size)
8118 {
8119 warning (0, "frame size of function %qs is %wd"
8120 " bytes exceeding user provided stack limit of "
8121 "%d bytes. "
8122 "An unconditional trap is added.",
8123 current_function_name(), cfun_frame_layout.frame_size,
8124 s390_stack_size);
8125 emit_insn (gen_trap ());
8126 }
8127 else
8128 {
8129 /* stack_guard has to be smaller than s390_stack_size.
8130 Otherwise we would emit an AND with zero which would
8131 not match the test under mask pattern. */
8132 if (stack_guard >= s390_stack_size)
8133 {
8134 warning (0, "frame size of function %qs is %wd"
8135 " bytes which is more than half the stack size. "
8136 "The dynamic check would not be reliable. "
8137 "No check emitted for this function.",
8138 current_function_name(),
8139 cfun_frame_layout.frame_size);
8140 }
8141 else
8142 {
8143 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8144 & ~(stack_guard - 1));
8145
8146 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8147 GEN_INT (stack_check_mask));
8148 if (TARGET_64BIT)
8149 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8150 t, const0_rtx),
8151 t, const0_rtx, const0_rtx));
8152 else
8153 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8154 t, const0_rtx),
8155 t, const0_rtx, const0_rtx));
8156 }
8157 }
8158 }
8159
8160 if (s390_warn_framesize > 0
8161 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8162 warning (0, "frame size of %qs is %wd bytes",
8163 current_function_name (), cfun_frame_layout.frame_size);
8164
8165 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8166 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8167
8168 /* Save incoming stack pointer into temp reg. */
8169 if (TARGET_BACKCHAIN || next_fpr)
8170 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8171
8172 /* Subtract frame size from stack pointer. */
8173
8174 if (DISP_IN_RANGE (INTVAL (frame_off)))
8175 {
8176 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8177 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8178 frame_off));
8179 insn = emit_insn (insn);
8180 }
8181 else
8182 {
8183 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8184 frame_off = force_const_mem (Pmode, frame_off);
8185
8186 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8187 annotate_constant_pool_refs (&PATTERN (insn));
8188 }
8189
8190 RTX_FRAME_RELATED_P (insn) = 1;
8191 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8192 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8193 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8194 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8195 real_frame_off)));
8196
8197 /* Set backchain. */
8198
8199 if (TARGET_BACKCHAIN)
8200 {
8201 if (cfun_frame_layout.backchain_offset)
8202 addr = gen_rtx_MEM (Pmode,
8203 plus_constant (stack_pointer_rtx,
8204 cfun_frame_layout.backchain_offset));
8205 else
8206 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8207 set_mem_alias_set (addr, get_frame_alias_set ());
8208 insn = emit_insn (gen_move_insn (addr, temp_reg));
8209 }
8210
8211 /* If we support non-call exceptions (e.g. for Java),
8212 we need to make sure the backchain pointer is set up
8213 before any possibly trapping memory access. */
8214 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8215 {
8216 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8217 emit_clobber (addr);
8218 }
8219 }
8220
8221 /* Save fprs 8 - 15 (64 bit ABI). */
8222
8223 if (cfun_save_high_fprs_p && next_fpr)
8224 {
8225 /* If the stack might be accessed through a different register
8226 we have to make sure that the stack pointer decrement is not
8227 moved below the use of the stack slots. */
8228 s390_emit_stack_tie ();
8229
8230 insn = emit_insn (gen_add2_insn (temp_reg,
8231 GEN_INT (cfun_frame_layout.f8_offset)));
8232
8233 offset = 0;
8234
8235 for (i = 24; i <= next_fpr; i++)
8236 if (cfun_fpr_bit_p (i - 16))
8237 {
8238 rtx addr = plus_constant (stack_pointer_rtx,
8239 cfun_frame_layout.frame_size
8240 + cfun_frame_layout.f8_offset
8241 + offset);
8242
8243 insn = save_fpr (temp_reg, offset, i);
8244 offset += 8;
8245 RTX_FRAME_RELATED_P (insn) = 1;
8246 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8247 gen_rtx_SET (VOIDmode,
8248 gen_rtx_MEM (DFmode, addr),
8249 gen_rtx_REG (DFmode, i)));
8250 }
8251 }
8252
8253 /* Set frame pointer, if needed. */
8254
8255 if (frame_pointer_needed)
8256 {
8257 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8258 RTX_FRAME_RELATED_P (insn) = 1;
8259 }
8260
8261 /* Set up got pointer, if needed. */
8262
8263 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8264 {
8265 rtx insns = s390_load_got ();
8266
8267 for (insn = insns; insn; insn = NEXT_INSN (insn))
8268 annotate_constant_pool_refs (&PATTERN (insn));
8269
8270 emit_insn (insns);
8271 }
8272
8273 if (TARGET_TPF_PROFILING)
8274 {
8275 /* Generate a BAS instruction to serve as a function
8276 entry intercept to facilitate the use of tracing
8277 algorithms located at the branch target. */
8278 emit_insn (gen_prologue_tpf ());
8279
8280 /* Emit a blockage here so that all code
8281 lies between the profiling mechanisms. */
8282 emit_insn (gen_blockage ());
8283 }
8284 }
8285
8286 /* Expand the epilogue into a bunch of separate insns. */
8287
8288 void
8289 s390_emit_epilogue (bool sibcall)
8290 {
8291 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8292 int area_bottom, area_top, offset = 0;
8293 int next_offset;
8294 rtvec p;
8295 int i;
8296
8297 if (TARGET_TPF_PROFILING)
8298 {
8299
8300 /* Generate a BAS instruction to serve as a function
8301 entry intercept to facilitate the use of tracing
8302 algorithms located at the branch target. */
8303
8304 /* Emit a blockage here so that all code
8305 lies between the profiling mechanisms. */
8306 emit_insn (gen_blockage ());
8307
8308 emit_insn (gen_epilogue_tpf ());
8309 }
8310
8311 /* Check whether to use frame or stack pointer for restore. */
8312
8313 frame_pointer = (frame_pointer_needed
8314 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8315
8316 s390_frame_area (&area_bottom, &area_top);
8317
8318 /* Check whether we can access the register save area.
8319 If not, increment the frame pointer as required. */
8320
8321 if (area_top <= area_bottom)
8322 {
8323 /* Nothing to restore. */
8324 }
8325 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8326 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8327 {
8328 /* Area is in range. */
8329 offset = cfun_frame_layout.frame_size;
8330 }
8331 else
8332 {
8333 rtx insn, frame_off, cfa;
8334
8335 offset = area_bottom < 0 ? -area_bottom : 0;
8336 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8337
8338 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8339 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8340 if (DISP_IN_RANGE (INTVAL (frame_off)))
8341 {
8342 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8343 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8344 insn = emit_insn (insn);
8345 }
8346 else
8347 {
8348 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8349 frame_off = force_const_mem (Pmode, frame_off);
8350
8351 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8352 annotate_constant_pool_refs (&PATTERN (insn));
8353 }
8354 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8355 RTX_FRAME_RELATED_P (insn) = 1;
8356 }
8357
8358 /* Restore call saved fprs. */
8359
8360 if (TARGET_64BIT)
8361 {
8362 if (cfun_save_high_fprs_p)
8363 {
8364 next_offset = cfun_frame_layout.f8_offset;
8365 for (i = 24; i < 32; i++)
8366 {
8367 if (cfun_fpr_bit_p (i - 16))
8368 {
8369 restore_fpr (frame_pointer,
8370 offset + next_offset, i);
8371 cfa_restores
8372 = alloc_reg_note (REG_CFA_RESTORE,
8373 gen_rtx_REG (DFmode, i), cfa_restores);
8374 next_offset += 8;
8375 }
8376 }
8377 }
8378
8379 }
8380 else
8381 {
8382 next_offset = cfun_frame_layout.f4_offset;
8383 for (i = 18; i < 20; i++)
8384 {
8385 if (cfun_fpr_bit_p (i - 16))
8386 {
8387 restore_fpr (frame_pointer,
8388 offset + next_offset, i);
8389 cfa_restores
8390 = alloc_reg_note (REG_CFA_RESTORE,
8391 gen_rtx_REG (DFmode, i), cfa_restores);
8392 next_offset += 8;
8393 }
8394 else if (!TARGET_PACKED_STACK)
8395 next_offset += 8;
8396 }
8397
8398 }
8399
8400 /* Return register. */
8401
8402 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8403
8404 /* Restore call saved gprs. */
8405
8406 if (cfun_frame_layout.first_restore_gpr != -1)
8407 {
8408 rtx insn, addr;
8409 int i;
8410
8411 /* Check for global register and save them
8412 to stack location from where they get restored. */
8413
8414 for (i = cfun_frame_layout.first_restore_gpr;
8415 i <= cfun_frame_layout.last_restore_gpr;
8416 i++)
8417 {
8418 if (global_not_special_regno_p (i))
8419 {
8420 addr = plus_constant (frame_pointer,
8421 offset + cfun_frame_layout.gprs_offset
8422 + (i - cfun_frame_layout.first_save_gpr_slot)
8423 * UNITS_PER_LONG);
8424 addr = gen_rtx_MEM (Pmode, addr);
8425 set_mem_alias_set (addr, get_frame_alias_set ());
8426 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8427 }
8428 else
8429 cfa_restores
8430 = alloc_reg_note (REG_CFA_RESTORE,
8431 gen_rtx_REG (Pmode, i), cfa_restores);
8432 }
8433
8434 if (! sibcall)
8435 {
8436 /* Fetch return address from stack before load multiple,
8437 this will do good for scheduling. */
8438
8439 if (cfun_frame_layout.save_return_addr_p
8440 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8441 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8442 {
8443 int return_regnum = find_unused_clobbered_reg();
8444 if (!return_regnum)
8445 return_regnum = 4;
8446 return_reg = gen_rtx_REG (Pmode, return_regnum);
8447
8448 addr = plus_constant (frame_pointer,
8449 offset + cfun_frame_layout.gprs_offset
8450 + (RETURN_REGNUM
8451 - cfun_frame_layout.first_save_gpr_slot)
8452 * UNITS_PER_LONG);
8453 addr = gen_rtx_MEM (Pmode, addr);
8454 set_mem_alias_set (addr, get_frame_alias_set ());
8455 emit_move_insn (return_reg, addr);
8456 }
8457 }
8458
8459 insn = restore_gprs (frame_pointer,
8460 offset + cfun_frame_layout.gprs_offset
8461 + (cfun_frame_layout.first_restore_gpr
8462 - cfun_frame_layout.first_save_gpr_slot)
8463 * UNITS_PER_LONG,
8464 cfun_frame_layout.first_restore_gpr,
8465 cfun_frame_layout.last_restore_gpr);
8466 insn = emit_insn (insn);
8467 REG_NOTES (insn) = cfa_restores;
8468 add_reg_note (insn, REG_CFA_DEF_CFA,
8469 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8470 RTX_FRAME_RELATED_P (insn) = 1;
8471 }
8472
8473 if (! sibcall)
8474 {
8475
8476 /* Return to caller. */
8477
8478 p = rtvec_alloc (2);
8479
8480 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8481 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8482 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8483 }
8484 }
8485
8486
8487 /* Return the size in bytes of a function argument of
8488 type TYPE and/or mode MODE. At least one of TYPE or
8489 MODE must be specified. */
8490
8491 static int
8492 s390_function_arg_size (enum machine_mode mode, const_tree type)
8493 {
8494 if (type)
8495 return int_size_in_bytes (type);
8496
8497 /* No type info available for some library calls ... */
8498 if (mode != BLKmode)
8499 return GET_MODE_SIZE (mode);
8500
8501 /* If we have neither type nor mode, abort */
8502 gcc_unreachable ();
8503 }
8504
8505 /* Return true if a function argument of type TYPE and mode MODE
8506 is to be passed in a floating-point register, if available. */
8507
8508 static bool
8509 s390_function_arg_float (enum machine_mode mode, const_tree type)
8510 {
8511 int size = s390_function_arg_size (mode, type);
8512 if (size > 8)
8513 return false;
8514
8515 /* Soft-float changes the ABI: no floating-point registers are used. */
8516 if (TARGET_SOFT_FLOAT)
8517 return false;
8518
8519 /* No type info available for some library calls ... */
8520 if (!type)
8521 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8522
8523 /* The ABI says that record types with a single member are treated
8524 just like that member would be. */
8525 while (TREE_CODE (type) == RECORD_TYPE)
8526 {
8527 tree field, single = NULL_TREE;
8528
8529 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8530 {
8531 if (TREE_CODE (field) != FIELD_DECL)
8532 continue;
8533
8534 if (single == NULL_TREE)
8535 single = TREE_TYPE (field);
8536 else
8537 return false;
8538 }
8539
8540 if (single == NULL_TREE)
8541 return false;
8542 else
8543 type = single;
8544 }
8545
8546 return TREE_CODE (type) == REAL_TYPE;
8547 }
8548
8549 /* Return true if a function argument of type TYPE and mode MODE
8550 is to be passed in an integer register, or a pair of integer
8551 registers, if available. */
8552
8553 static bool
8554 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8555 {
8556 int size = s390_function_arg_size (mode, type);
8557 if (size > 8)
8558 return false;
8559
8560 /* No type info available for some library calls ... */
8561 if (!type)
8562 return GET_MODE_CLASS (mode) == MODE_INT
8563 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8564
8565 /* We accept small integral (and similar) types. */
8566 if (INTEGRAL_TYPE_P (type)
8567 || POINTER_TYPE_P (type)
8568 || TREE_CODE (type) == NULLPTR_TYPE
8569 || TREE_CODE (type) == OFFSET_TYPE
8570 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8571 return true;
8572
8573 /* We also accept structs of size 1, 2, 4, 8 that are not
8574 passed in floating-point registers. */
8575 if (AGGREGATE_TYPE_P (type)
8576 && exact_log2 (size) >= 0
8577 && !s390_function_arg_float (mode, type))
8578 return true;
8579
8580 return false;
8581 }
8582
8583 /* Return 1 if a function argument of type TYPE and mode MODE
8584 is to be passed by reference. The ABI specifies that only
8585 structures of size 1, 2, 4, or 8 bytes are passed by value,
8586 all other structures (and complex numbers) are passed by
8587 reference. */
8588
8589 static bool
8590 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8591 enum machine_mode mode, const_tree type,
8592 bool named ATTRIBUTE_UNUSED)
8593 {
8594 int size = s390_function_arg_size (mode, type);
8595 if (size > 8)
8596 return true;
8597
8598 if (type)
8599 {
8600 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8601 return 1;
8602
8603 if (TREE_CODE (type) == COMPLEX_TYPE
8604 || TREE_CODE (type) == VECTOR_TYPE)
8605 return 1;
8606 }
8607
8608 return 0;
8609 }
8610
8611 /* Update the data in CUM to advance over an argument of mode MODE and
8612 data type TYPE. (TYPE is null for libcalls where that information
8613 may not be available.). The boolean NAMED specifies whether the
8614 argument is a named argument (as opposed to an unnamed argument
8615 matching an ellipsis). */
8616
8617 static void
8618 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8619 const_tree type, bool named ATTRIBUTE_UNUSED)
8620 {
8621 if (s390_function_arg_float (mode, type))
8622 {
8623 cum->fprs += 1;
8624 }
8625 else if (s390_function_arg_integer (mode, type))
8626 {
8627 int size = s390_function_arg_size (mode, type);
8628 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8629 }
8630 else
8631 gcc_unreachable ();
8632 }
8633
8634 /* Define where to put the arguments to a function.
8635 Value is zero to push the argument on the stack,
8636 or a hard register in which to store the argument.
8637
8638 MODE is the argument's machine mode.
8639 TYPE is the data type of the argument (as a tree).
8640 This is null for libcalls where that information may
8641 not be available.
8642 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8643 the preceding args and about the function being called.
8644 NAMED is nonzero if this argument is a named parameter
8645 (otherwise it is an extra parameter matching an ellipsis).
8646
8647 On S/390, we use general purpose registers 2 through 6 to
8648 pass integer, pointer, and certain structure arguments, and
8649 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8650 to pass floating point arguments. All remaining arguments
8651 are pushed to the stack. */
8652
8653 static rtx
8654 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8655 const_tree type, bool named ATTRIBUTE_UNUSED)
8656 {
8657 if (s390_function_arg_float (mode, type))
8658 {
8659 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8660 return 0;
8661 else
8662 return gen_rtx_REG (mode, cum->fprs + 16);
8663 }
8664 else if (s390_function_arg_integer (mode, type))
8665 {
8666 int size = s390_function_arg_size (mode, type);
8667 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8668
8669 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8670 return 0;
8671 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8672 return gen_rtx_REG (mode, cum->gprs + 2);
8673 else if (n_gprs == 2)
8674 {
8675 rtvec p = rtvec_alloc (2);
8676
8677 RTVEC_ELT (p, 0)
8678 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8679 const0_rtx);
8680 RTVEC_ELT (p, 1)
8681 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8682 GEN_INT (4));
8683
8684 return gen_rtx_PARALLEL (mode, p);
8685 }
8686 }
8687
8688 /* After the real arguments, expand_call calls us once again
8689 with a void_type_node type. Whatever we return here is
8690 passed as operand 2 to the call expanders.
8691
8692 We don't need this feature ... */
8693 else if (type == void_type_node)
8694 return const0_rtx;
8695
8696 gcc_unreachable ();
8697 }
8698
8699 /* Return true if return values of type TYPE should be returned
8700 in a memory buffer whose address is passed by the caller as
8701 hidden first argument. */
8702
8703 static bool
8704 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8705 {
8706 /* We accept small integral (and similar) types. */
8707 if (INTEGRAL_TYPE_P (type)
8708 || POINTER_TYPE_P (type)
8709 || TREE_CODE (type) == OFFSET_TYPE
8710 || TREE_CODE (type) == REAL_TYPE)
8711 return int_size_in_bytes (type) > 8;
8712
8713 /* Aggregates and similar constructs are always returned
8714 in memory. */
8715 if (AGGREGATE_TYPE_P (type)
8716 || TREE_CODE (type) == COMPLEX_TYPE
8717 || TREE_CODE (type) == VECTOR_TYPE)
8718 return true;
8719
8720 /* ??? We get called on all sorts of random stuff from
8721 aggregate_value_p. We can't abort, but it's not clear
8722 what's safe to return. Pretend it's a struct I guess. */
8723 return true;
8724 }
8725
8726 /* Function arguments and return values are promoted to word size. */
8727
8728 static enum machine_mode
8729 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8730 int *punsignedp,
8731 const_tree fntype ATTRIBUTE_UNUSED,
8732 int for_return ATTRIBUTE_UNUSED)
8733 {
8734 if (INTEGRAL_MODE_P (mode)
8735 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8736 {
8737 if (POINTER_TYPE_P (type))
8738 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8739 return Pmode;
8740 }
8741
8742 return mode;
8743 }
8744
8745 /* Define where to return a (scalar) value of type RET_TYPE.
8746 If RET_TYPE is null, define where to return a (scalar)
8747 value of mode MODE from a libcall. */
8748
8749 static rtx
8750 s390_function_and_libcall_value (enum machine_mode mode,
8751 const_tree ret_type,
8752 const_tree fntype_or_decl,
8753 bool outgoing ATTRIBUTE_UNUSED)
8754 {
8755 /* For normal functions perform the promotion as
8756 promote_function_mode would do. */
8757 if (ret_type)
8758 {
8759 int unsignedp = TYPE_UNSIGNED (ret_type);
8760 mode = promote_function_mode (ret_type, mode, &unsignedp,
8761 fntype_or_decl, 1);
8762 }
8763
8764 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8765 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8766
8767 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8768 return gen_rtx_REG (mode, 16);
8769 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8770 || UNITS_PER_LONG == UNITS_PER_WORD)
8771 return gen_rtx_REG (mode, 2);
8772 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8773 {
8774 /* This case is triggered when returning a 64 bit value with
8775 -m31 -mzarch. Although the value would fit into a single
8776 register it has to be forced into a 32 bit register pair in
8777 order to match the ABI. */
8778 rtvec p = rtvec_alloc (2);
8779
8780 RTVEC_ELT (p, 0)
8781 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8782 RTVEC_ELT (p, 1)
8783 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8784
8785 return gen_rtx_PARALLEL (mode, p);
8786 }
8787
8788 gcc_unreachable ();
8789 }
8790
8791 /* Define where to return a scalar return value of type RET_TYPE. */
8792
8793 static rtx
8794 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8795 bool outgoing)
8796 {
8797 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8798 fn_decl_or_type, outgoing);
8799 }
8800
8801 /* Define where to return a scalar libcall return value of mode
8802 MODE. */
8803
8804 static rtx
8805 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8806 {
8807 return s390_function_and_libcall_value (mode, NULL_TREE,
8808 NULL_TREE, true);
8809 }
8810
8811
8812 /* Create and return the va_list datatype.
8813
8814 On S/390, va_list is an array type equivalent to
8815
8816 typedef struct __va_list_tag
8817 {
8818 long __gpr;
8819 long __fpr;
8820 void *__overflow_arg_area;
8821 void *__reg_save_area;
8822 } va_list[1];
8823
8824 where __gpr and __fpr hold the number of general purpose
8825 or floating point arguments used up to now, respectively,
8826 __overflow_arg_area points to the stack location of the
8827 next argument passed on the stack, and __reg_save_area
8828 always points to the start of the register area in the
8829 call frame of the current function. The function prologue
8830 saves all registers used for argument passing into this
8831 area if the function uses variable arguments. */
8832
8833 static tree
8834 s390_build_builtin_va_list (void)
8835 {
8836 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8837
8838 record = lang_hooks.types.make_type (RECORD_TYPE);
8839
8840 type_decl =
8841 build_decl (BUILTINS_LOCATION,
8842 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8843
8844 f_gpr = build_decl (BUILTINS_LOCATION,
8845 FIELD_DECL, get_identifier ("__gpr"),
8846 long_integer_type_node);
8847 f_fpr = build_decl (BUILTINS_LOCATION,
8848 FIELD_DECL, get_identifier ("__fpr"),
8849 long_integer_type_node);
8850 f_ovf = build_decl (BUILTINS_LOCATION,
8851 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8852 ptr_type_node);
8853 f_sav = build_decl (BUILTINS_LOCATION,
8854 FIELD_DECL, get_identifier ("__reg_save_area"),
8855 ptr_type_node);
8856
8857 va_list_gpr_counter_field = f_gpr;
8858 va_list_fpr_counter_field = f_fpr;
8859
8860 DECL_FIELD_CONTEXT (f_gpr) = record;
8861 DECL_FIELD_CONTEXT (f_fpr) = record;
8862 DECL_FIELD_CONTEXT (f_ovf) = record;
8863 DECL_FIELD_CONTEXT (f_sav) = record;
8864
8865 TYPE_STUB_DECL (record) = type_decl;
8866 TYPE_NAME (record) = type_decl;
8867 TYPE_FIELDS (record) = f_gpr;
8868 DECL_CHAIN (f_gpr) = f_fpr;
8869 DECL_CHAIN (f_fpr) = f_ovf;
8870 DECL_CHAIN (f_ovf) = f_sav;
8871
8872 layout_type (record);
8873
8874 /* The correct type is an array type of one element. */
8875 return build_array_type (record, build_index_type (size_zero_node));
8876 }
8877
8878 /* Implement va_start by filling the va_list structure VALIST.
8879 STDARG_P is always true, and ignored.
8880 NEXTARG points to the first anonymous stack argument.
8881
8882 The following global variables are used to initialize
8883 the va_list structure:
8884
8885 crtl->args.info:
8886 holds number of gprs and fprs used for named arguments.
8887 crtl->args.arg_offset_rtx:
8888 holds the offset of the first anonymous stack argument
8889 (relative to the virtual arg pointer). */
8890
8891 static void
8892 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8893 {
8894 HOST_WIDE_INT n_gpr, n_fpr;
8895 int off;
8896 tree f_gpr, f_fpr, f_ovf, f_sav;
8897 tree gpr, fpr, ovf, sav, t;
8898
8899 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8900 f_fpr = DECL_CHAIN (f_gpr);
8901 f_ovf = DECL_CHAIN (f_fpr);
8902 f_sav = DECL_CHAIN (f_ovf);
8903
8904 valist = build_simple_mem_ref (valist);
8905 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8906 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8907 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8908 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8909
8910 /* Count number of gp and fp argument registers used. */
8911
8912 n_gpr = crtl->args.info.gprs;
8913 n_fpr = crtl->args.info.fprs;
8914
8915 if (cfun->va_list_gpr_size)
8916 {
8917 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8918 build_int_cst (NULL_TREE, n_gpr));
8919 TREE_SIDE_EFFECTS (t) = 1;
8920 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8921 }
8922
8923 if (cfun->va_list_fpr_size)
8924 {
8925 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8926 build_int_cst (NULL_TREE, n_fpr));
8927 TREE_SIDE_EFFECTS (t) = 1;
8928 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8929 }
8930
8931 /* Find the overflow area. */
8932 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8933 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8934 {
8935 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8936
8937 off = INTVAL (crtl->args.arg_offset_rtx);
8938 off = off < 0 ? 0 : off;
8939 if (TARGET_DEBUG_ARG)
8940 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8941 (int)n_gpr, (int)n_fpr, off);
8942
8943 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8944
8945 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8946 TREE_SIDE_EFFECTS (t) = 1;
8947 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8948 }
8949
8950 /* Find the register save area. */
8951 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8952 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8953 {
8954 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8955 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8956 size_int (-RETURN_REGNUM * UNITS_PER_LONG));
8957
8958 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8959 TREE_SIDE_EFFECTS (t) = 1;
8960 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8961 }
8962 }
8963
8964 /* Implement va_arg by updating the va_list structure
8965 VALIST as required to retrieve an argument of type
8966 TYPE, and returning that argument.
8967
8968 Generates code equivalent to:
8969
8970 if (integral value) {
8971 if (size <= 4 && args.gpr < 5 ||
8972 size > 4 && args.gpr < 4 )
8973 ret = args.reg_save_area[args.gpr+8]
8974 else
8975 ret = *args.overflow_arg_area++;
8976 } else if (float value) {
8977 if (args.fgpr < 2)
8978 ret = args.reg_save_area[args.fpr+64]
8979 else
8980 ret = *args.overflow_arg_area++;
8981 } else if (aggregate value) {
8982 if (args.gpr < 5)
8983 ret = *args.reg_save_area[args.gpr]
8984 else
8985 ret = **args.overflow_arg_area++;
8986 } */
8987
8988 static tree
8989 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8990 gimple_seq *post_p ATTRIBUTE_UNUSED)
8991 {
8992 tree f_gpr, f_fpr, f_ovf, f_sav;
8993 tree gpr, fpr, ovf, sav, reg, t, u;
8994 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8995 tree lab_false, lab_over, addr;
8996
8997 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8998 f_fpr = DECL_CHAIN (f_gpr);
8999 f_ovf = DECL_CHAIN (f_fpr);
9000 f_sav = DECL_CHAIN (f_ovf);
9001
9002 valist = build_va_arg_indirect_ref (valist);
9003 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9004 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9005 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9006
9007 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9008 both appear on a lhs. */
9009 valist = unshare_expr (valist);
9010 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9011
9012 size = int_size_in_bytes (type);
9013
9014 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9015 {
9016 if (TARGET_DEBUG_ARG)
9017 {
9018 fprintf (stderr, "va_arg: aggregate type");
9019 debug_tree (type);
9020 }
9021
9022 /* Aggregates are passed by reference. */
9023 indirect_p = 1;
9024 reg = gpr;
9025 n_reg = 1;
9026
9027 /* kernel stack layout on 31 bit: It is assumed here that no padding
9028 will be added by s390_frame_info because for va_args always an even
9029 number of gprs has to be saved r15-r2 = 14 regs. */
9030 sav_ofs = 2 * UNITS_PER_LONG;
9031 sav_scale = UNITS_PER_LONG;
9032 size = UNITS_PER_LONG;
9033 max_reg = GP_ARG_NUM_REG - n_reg;
9034 }
9035 else if (s390_function_arg_float (TYPE_MODE (type), type))
9036 {
9037 if (TARGET_DEBUG_ARG)
9038 {
9039 fprintf (stderr, "va_arg: float type");
9040 debug_tree (type);
9041 }
9042
9043 /* FP args go in FP registers, if present. */
9044 indirect_p = 0;
9045 reg = fpr;
9046 n_reg = 1;
9047 sav_ofs = 16 * UNITS_PER_LONG;
9048 sav_scale = 8;
9049 max_reg = FP_ARG_NUM_REG - n_reg;
9050 }
9051 else
9052 {
9053 if (TARGET_DEBUG_ARG)
9054 {
9055 fprintf (stderr, "va_arg: other type");
9056 debug_tree (type);
9057 }
9058
9059 /* Otherwise into GP registers. */
9060 indirect_p = 0;
9061 reg = gpr;
9062 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9063
9064 /* kernel stack layout on 31 bit: It is assumed here that no padding
9065 will be added by s390_frame_info because for va_args always an even
9066 number of gprs has to be saved r15-r2 = 14 regs. */
9067 sav_ofs = 2 * UNITS_PER_LONG;
9068
9069 if (size < UNITS_PER_LONG)
9070 sav_ofs += UNITS_PER_LONG - size;
9071
9072 sav_scale = UNITS_PER_LONG;
9073 max_reg = GP_ARG_NUM_REG - n_reg;
9074 }
9075
9076 /* Pull the value out of the saved registers ... */
9077
9078 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9079 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9080 addr = create_tmp_var (ptr_type_node, "addr");
9081
9082 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9083 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9084 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9085 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9086 gimplify_and_add (t, pre_p);
9087
9088 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
9089 size_int (sav_ofs));
9090 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9091 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9092 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
9093
9094 gimplify_assign (addr, t, pre_p);
9095
9096 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9097
9098 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9099
9100
9101 /* ... Otherwise out of the overflow area. */
9102
9103 t = ovf;
9104 if (size < UNITS_PER_LONG)
9105 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
9106 size_int (UNITS_PER_LONG - size));
9107
9108 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9109
9110 gimplify_assign (addr, t, pre_p);
9111
9112 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
9113 size_int (size));
9114 gimplify_assign (ovf, t, pre_p);
9115
9116 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9117
9118
9119 /* Increment register save count. */
9120
9121 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9122 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9123 gimplify_and_add (u, pre_p);
9124
9125 if (indirect_p)
9126 {
9127 t = build_pointer_type_for_mode (build_pointer_type (type),
9128 ptr_mode, true);
9129 addr = fold_convert (t, addr);
9130 addr = build_va_arg_indirect_ref (addr);
9131 }
9132 else
9133 {
9134 t = build_pointer_type_for_mode (type, ptr_mode, true);
9135 addr = fold_convert (t, addr);
9136 }
9137
9138 return build_va_arg_indirect_ref (addr);
9139 }
9140
9141
9142 /* Builtins. */
9143
9144 enum s390_builtin
9145 {
9146 S390_BUILTIN_THREAD_POINTER,
9147 S390_BUILTIN_SET_THREAD_POINTER,
9148
9149 S390_BUILTIN_max
9150 };
9151
9152 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9153 CODE_FOR_get_tp_64,
9154 CODE_FOR_set_tp_64
9155 };
9156
9157 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9158 CODE_FOR_get_tp_31,
9159 CODE_FOR_set_tp_31
9160 };
9161
9162 static void
9163 s390_init_builtins (void)
9164 {
9165 tree ftype;
9166
9167 ftype = build_function_type (ptr_type_node, void_list_node);
9168 add_builtin_function ("__builtin_thread_pointer", ftype,
9169 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9170 NULL, NULL_TREE);
9171
9172 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9173 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9174 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9175 NULL, NULL_TREE);
9176 }
9177
9178 /* Expand an expression EXP that calls a built-in function,
9179 with result going to TARGET if that's convenient
9180 (and in mode MODE if that's convenient).
9181 SUBTARGET may be used as the target for computing one of EXP's operands.
9182 IGNORE is nonzero if the value is to be ignored. */
9183
9184 static rtx
9185 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9186 enum machine_mode mode ATTRIBUTE_UNUSED,
9187 int ignore ATTRIBUTE_UNUSED)
9188 {
9189 #define MAX_ARGS 2
9190
9191 enum insn_code const *code_for_builtin =
9192 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9193
9194 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9195 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9196 enum insn_code icode;
9197 rtx op[MAX_ARGS], pat;
9198 int arity;
9199 bool nonvoid;
9200 tree arg;
9201 call_expr_arg_iterator iter;
9202
9203 if (fcode >= S390_BUILTIN_max)
9204 internal_error ("bad builtin fcode");
9205 icode = code_for_builtin[fcode];
9206 if (icode == 0)
9207 internal_error ("bad builtin fcode");
9208
9209 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9210
9211 arity = 0;
9212 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9213 {
9214 const struct insn_operand_data *insn_op;
9215
9216 if (arg == error_mark_node)
9217 return NULL_RTX;
9218 if (arity > MAX_ARGS)
9219 return NULL_RTX;
9220
9221 insn_op = &insn_data[icode].operand[arity + nonvoid];
9222
9223 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9224
9225 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9226 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9227 arity++;
9228 }
9229
9230 if (nonvoid)
9231 {
9232 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9233 if (!target
9234 || GET_MODE (target) != tmode
9235 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9236 target = gen_reg_rtx (tmode);
9237 }
9238
9239 switch (arity)
9240 {
9241 case 0:
9242 pat = GEN_FCN (icode) (target);
9243 break;
9244 case 1:
9245 if (nonvoid)
9246 pat = GEN_FCN (icode) (target, op[0]);
9247 else
9248 pat = GEN_FCN (icode) (op[0]);
9249 break;
9250 case 2:
9251 pat = GEN_FCN (icode) (target, op[0], op[1]);
9252 break;
9253 default:
9254 gcc_unreachable ();
9255 }
9256 if (!pat)
9257 return NULL_RTX;
9258 emit_insn (pat);
9259
9260 if (nonvoid)
9261 return target;
9262 else
9263 return const0_rtx;
9264 }
9265
9266
9267 /* Output assembly code for the trampoline template to
9268 stdio stream FILE.
9269
9270 On S/390, we use gpr 1 internally in the trampoline code;
9271 gpr 0 is used to hold the static chain. */
9272
9273 static void
9274 s390_asm_trampoline_template (FILE *file)
9275 {
9276 rtx op[2];
9277 op[0] = gen_rtx_REG (Pmode, 0);
9278 op[1] = gen_rtx_REG (Pmode, 1);
9279
9280 if (TARGET_64BIT)
9281 {
9282 output_asm_insn ("basr\t%1,0", op);
9283 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
9284 output_asm_insn ("br\t%1", op);
9285 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9286 }
9287 else
9288 {
9289 output_asm_insn ("basr\t%1,0", op);
9290 output_asm_insn ("lm\t%0,%1,6(%1)", op);
9291 output_asm_insn ("br\t%1", op);
9292 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9293 }
9294 }
9295
9296 /* Emit RTL insns to initialize the variable parts of a trampoline.
9297 FNADDR is an RTX for the address of the function's pure code.
9298 CXT is an RTX for the static chain value for the function. */
9299
9300 static void
9301 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9302 {
9303 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9304 rtx mem;
9305
9306 emit_block_move (m_tramp, assemble_trampoline_template (),
9307 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
9308
9309 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
9310 emit_move_insn (mem, cxt);
9311 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
9312 emit_move_insn (mem, fnaddr);
9313 }
9314
9315 /* Output assembler code to FILE to increment profiler label # LABELNO
9316 for profiling a function entry. */
9317
9318 void
9319 s390_function_profiler (FILE *file, int labelno)
9320 {
9321 rtx op[7];
9322
9323 char label[128];
9324 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9325
9326 fprintf (file, "# function profiler \n");
9327
9328 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9329 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9330 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9331
9332 op[2] = gen_rtx_REG (Pmode, 1);
9333 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9334 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9335
9336 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9337 if (flag_pic)
9338 {
9339 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9340 op[4] = gen_rtx_CONST (Pmode, op[4]);
9341 }
9342
9343 if (TARGET_64BIT)
9344 {
9345 output_asm_insn ("stg\t%0,%1", op);
9346 output_asm_insn ("larl\t%2,%3", op);
9347 output_asm_insn ("brasl\t%0,%4", op);
9348 output_asm_insn ("lg\t%0,%1", op);
9349 }
9350 else if (!flag_pic)
9351 {
9352 op[6] = gen_label_rtx ();
9353
9354 output_asm_insn ("st\t%0,%1", op);
9355 output_asm_insn ("bras\t%2,%l6", op);
9356 output_asm_insn (".long\t%4", op);
9357 output_asm_insn (".long\t%3", op);
9358 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9359 output_asm_insn ("l\t%0,0(%2)", op);
9360 output_asm_insn ("l\t%2,4(%2)", op);
9361 output_asm_insn ("basr\t%0,%0", op);
9362 output_asm_insn ("l\t%0,%1", op);
9363 }
9364 else
9365 {
9366 op[5] = gen_label_rtx ();
9367 op[6] = gen_label_rtx ();
9368
9369 output_asm_insn ("st\t%0,%1", op);
9370 output_asm_insn ("bras\t%2,%l6", op);
9371 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9372 output_asm_insn (".long\t%4-%l5", op);
9373 output_asm_insn (".long\t%3-%l5", op);
9374 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9375 output_asm_insn ("lr\t%0,%2", op);
9376 output_asm_insn ("a\t%0,0(%2)", op);
9377 output_asm_insn ("a\t%2,4(%2)", op);
9378 output_asm_insn ("basr\t%0,%0", op);
9379 output_asm_insn ("l\t%0,%1", op);
9380 }
9381 }
9382
9383 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9384 into its SYMBOL_REF_FLAGS. */
9385
9386 static void
9387 s390_encode_section_info (tree decl, rtx rtl, int first)
9388 {
9389 default_encode_section_info (decl, rtl, first);
9390
9391 if (TREE_CODE (decl) == VAR_DECL)
9392 {
9393 /* If a variable has a forced alignment to < 2 bytes, mark it
9394 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9395 operand. */
9396 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9397 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9398 if (!DECL_SIZE (decl)
9399 || !DECL_ALIGN (decl)
9400 || !host_integerp (DECL_SIZE (decl), 0)
9401 || (DECL_ALIGN (decl) <= 64
9402 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9403 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9404 }
9405
9406 /* Literal pool references don't have a decl so they are handled
9407 differently here. We rely on the information in the MEM_ALIGN
9408 entry to decide upon natural alignment. */
9409 if (MEM_P (rtl)
9410 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9411 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9412 && (MEM_ALIGN (rtl) == 0
9413 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9414 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9415 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9416 }
9417
9418 /* Output thunk to FILE that implements a C++ virtual function call (with
9419 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9420 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9421 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9422 relative to the resulting this pointer. */
9423
9424 static void
9425 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9426 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9427 tree function)
9428 {
9429 rtx op[10];
9430 int nonlocal = 0;
9431
9432 /* Make sure unwind info is emitted for the thunk if needed. */
9433 final_start_function (emit_barrier (), file, 1);
9434
9435 /* Operand 0 is the target function. */
9436 op[0] = XEXP (DECL_RTL (function), 0);
9437 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9438 {
9439 nonlocal = 1;
9440 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9441 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9442 op[0] = gen_rtx_CONST (Pmode, op[0]);
9443 }
9444
9445 /* Operand 1 is the 'this' pointer. */
9446 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9447 op[1] = gen_rtx_REG (Pmode, 3);
9448 else
9449 op[1] = gen_rtx_REG (Pmode, 2);
9450
9451 /* Operand 2 is the delta. */
9452 op[2] = GEN_INT (delta);
9453
9454 /* Operand 3 is the vcall_offset. */
9455 op[3] = GEN_INT (vcall_offset);
9456
9457 /* Operand 4 is the temporary register. */
9458 op[4] = gen_rtx_REG (Pmode, 1);
9459
9460 /* Operands 5 to 8 can be used as labels. */
9461 op[5] = NULL_RTX;
9462 op[6] = NULL_RTX;
9463 op[7] = NULL_RTX;
9464 op[8] = NULL_RTX;
9465
9466 /* Operand 9 can be used for temporary register. */
9467 op[9] = NULL_RTX;
9468
9469 /* Generate code. */
9470 if (TARGET_64BIT)
9471 {
9472 /* Setup literal pool pointer if required. */
9473 if ((!DISP_IN_RANGE (delta)
9474 && !CONST_OK_FOR_K (delta)
9475 && !CONST_OK_FOR_Os (delta))
9476 || (!DISP_IN_RANGE (vcall_offset)
9477 && !CONST_OK_FOR_K (vcall_offset)
9478 && !CONST_OK_FOR_Os (vcall_offset)))
9479 {
9480 op[5] = gen_label_rtx ();
9481 output_asm_insn ("larl\t%4,%5", op);
9482 }
9483
9484 /* Add DELTA to this pointer. */
9485 if (delta)
9486 {
9487 if (CONST_OK_FOR_J (delta))
9488 output_asm_insn ("la\t%1,%2(%1)", op);
9489 else if (DISP_IN_RANGE (delta))
9490 output_asm_insn ("lay\t%1,%2(%1)", op);
9491 else if (CONST_OK_FOR_K (delta))
9492 output_asm_insn ("aghi\t%1,%2", op);
9493 else if (CONST_OK_FOR_Os (delta))
9494 output_asm_insn ("agfi\t%1,%2", op);
9495 else
9496 {
9497 op[6] = gen_label_rtx ();
9498 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9499 }
9500 }
9501
9502 /* Perform vcall adjustment. */
9503 if (vcall_offset)
9504 {
9505 if (DISP_IN_RANGE (vcall_offset))
9506 {
9507 output_asm_insn ("lg\t%4,0(%1)", op);
9508 output_asm_insn ("ag\t%1,%3(%4)", op);
9509 }
9510 else if (CONST_OK_FOR_K (vcall_offset))
9511 {
9512 output_asm_insn ("lghi\t%4,%3", op);
9513 output_asm_insn ("ag\t%4,0(%1)", op);
9514 output_asm_insn ("ag\t%1,0(%4)", op);
9515 }
9516 else if (CONST_OK_FOR_Os (vcall_offset))
9517 {
9518 output_asm_insn ("lgfi\t%4,%3", op);
9519 output_asm_insn ("ag\t%4,0(%1)", op);
9520 output_asm_insn ("ag\t%1,0(%4)", op);
9521 }
9522 else
9523 {
9524 op[7] = gen_label_rtx ();
9525 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9526 output_asm_insn ("ag\t%4,0(%1)", op);
9527 output_asm_insn ("ag\t%1,0(%4)", op);
9528 }
9529 }
9530
9531 /* Jump to target. */
9532 output_asm_insn ("jg\t%0", op);
9533
9534 /* Output literal pool if required. */
9535 if (op[5])
9536 {
9537 output_asm_insn (".align\t4", op);
9538 targetm.asm_out.internal_label (file, "L",
9539 CODE_LABEL_NUMBER (op[5]));
9540 }
9541 if (op[6])
9542 {
9543 targetm.asm_out.internal_label (file, "L",
9544 CODE_LABEL_NUMBER (op[6]));
9545 output_asm_insn (".long\t%2", op);
9546 }
9547 if (op[7])
9548 {
9549 targetm.asm_out.internal_label (file, "L",
9550 CODE_LABEL_NUMBER (op[7]));
9551 output_asm_insn (".long\t%3", op);
9552 }
9553 }
9554 else
9555 {
9556 /* Setup base pointer if required. */
9557 if (!vcall_offset
9558 || (!DISP_IN_RANGE (delta)
9559 && !CONST_OK_FOR_K (delta)
9560 && !CONST_OK_FOR_Os (delta))
9561 || (!DISP_IN_RANGE (delta)
9562 && !CONST_OK_FOR_K (vcall_offset)
9563 && !CONST_OK_FOR_Os (vcall_offset)))
9564 {
9565 op[5] = gen_label_rtx ();
9566 output_asm_insn ("basr\t%4,0", op);
9567 targetm.asm_out.internal_label (file, "L",
9568 CODE_LABEL_NUMBER (op[5]));
9569 }
9570
9571 /* Add DELTA to this pointer. */
9572 if (delta)
9573 {
9574 if (CONST_OK_FOR_J (delta))
9575 output_asm_insn ("la\t%1,%2(%1)", op);
9576 else if (DISP_IN_RANGE (delta))
9577 output_asm_insn ("lay\t%1,%2(%1)", op);
9578 else if (CONST_OK_FOR_K (delta))
9579 output_asm_insn ("ahi\t%1,%2", op);
9580 else if (CONST_OK_FOR_Os (delta))
9581 output_asm_insn ("afi\t%1,%2", op);
9582 else
9583 {
9584 op[6] = gen_label_rtx ();
9585 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9586 }
9587 }
9588
9589 /* Perform vcall adjustment. */
9590 if (vcall_offset)
9591 {
9592 if (CONST_OK_FOR_J (vcall_offset))
9593 {
9594 output_asm_insn ("l\t%4,0(%1)", op);
9595 output_asm_insn ("a\t%1,%3(%4)", op);
9596 }
9597 else if (DISP_IN_RANGE (vcall_offset))
9598 {
9599 output_asm_insn ("l\t%4,0(%1)", op);
9600 output_asm_insn ("ay\t%1,%3(%4)", op);
9601 }
9602 else if (CONST_OK_FOR_K (vcall_offset))
9603 {
9604 output_asm_insn ("lhi\t%4,%3", op);
9605 output_asm_insn ("a\t%4,0(%1)", op);
9606 output_asm_insn ("a\t%1,0(%4)", op);
9607 }
9608 else if (CONST_OK_FOR_Os (vcall_offset))
9609 {
9610 output_asm_insn ("iilf\t%4,%3", op);
9611 output_asm_insn ("a\t%4,0(%1)", op);
9612 output_asm_insn ("a\t%1,0(%4)", op);
9613 }
9614 else
9615 {
9616 op[7] = gen_label_rtx ();
9617 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9618 output_asm_insn ("a\t%4,0(%1)", op);
9619 output_asm_insn ("a\t%1,0(%4)", op);
9620 }
9621
9622 /* We had to clobber the base pointer register.
9623 Re-setup the base pointer (with a different base). */
9624 op[5] = gen_label_rtx ();
9625 output_asm_insn ("basr\t%4,0", op);
9626 targetm.asm_out.internal_label (file, "L",
9627 CODE_LABEL_NUMBER (op[5]));
9628 }
9629
9630 /* Jump to target. */
9631 op[8] = gen_label_rtx ();
9632
9633 if (!flag_pic)
9634 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9635 else if (!nonlocal)
9636 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9637 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9638 else if (flag_pic == 1)
9639 {
9640 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9641 output_asm_insn ("l\t%4,%0(%4)", op);
9642 }
9643 else if (flag_pic == 2)
9644 {
9645 op[9] = gen_rtx_REG (Pmode, 0);
9646 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9647 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9648 output_asm_insn ("ar\t%4,%9", op);
9649 output_asm_insn ("l\t%4,0(%4)", op);
9650 }
9651
9652 output_asm_insn ("br\t%4", op);
9653
9654 /* Output literal pool. */
9655 output_asm_insn (".align\t4", op);
9656
9657 if (nonlocal && flag_pic == 2)
9658 output_asm_insn (".long\t%0", op);
9659 if (nonlocal)
9660 {
9661 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9662 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9663 }
9664
9665 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9666 if (!flag_pic)
9667 output_asm_insn (".long\t%0", op);
9668 else
9669 output_asm_insn (".long\t%0-%5", op);
9670
9671 if (op[6])
9672 {
9673 targetm.asm_out.internal_label (file, "L",
9674 CODE_LABEL_NUMBER (op[6]));
9675 output_asm_insn (".long\t%2", op);
9676 }
9677 if (op[7])
9678 {
9679 targetm.asm_out.internal_label (file, "L",
9680 CODE_LABEL_NUMBER (op[7]));
9681 output_asm_insn (".long\t%3", op);
9682 }
9683 }
9684 final_end_function ();
9685 }
9686
9687 static bool
9688 s390_valid_pointer_mode (enum machine_mode mode)
9689 {
9690 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9691 }
9692
9693 /* Checks whether the given CALL_EXPR would use a caller
9694 saved register. This is used to decide whether sibling call
9695 optimization could be performed on the respective function
9696 call. */
9697
9698 static bool
9699 s390_call_saved_register_used (tree call_expr)
9700 {
9701 CUMULATIVE_ARGS cum;
9702 tree parameter;
9703 enum machine_mode mode;
9704 tree type;
9705 rtx parm_rtx;
9706 int reg, i;
9707
9708 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9709
9710 for (i = 0; i < call_expr_nargs (call_expr); i++)
9711 {
9712 parameter = CALL_EXPR_ARG (call_expr, i);
9713 gcc_assert (parameter);
9714
9715 /* For an undeclared variable passed as parameter we will get
9716 an ERROR_MARK node here. */
9717 if (TREE_CODE (parameter) == ERROR_MARK)
9718 return true;
9719
9720 type = TREE_TYPE (parameter);
9721 gcc_assert (type);
9722
9723 mode = TYPE_MODE (type);
9724 gcc_assert (mode);
9725
9726 if (pass_by_reference (&cum, mode, type, true))
9727 {
9728 mode = Pmode;
9729 type = build_pointer_type (type);
9730 }
9731
9732 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9733
9734 s390_function_arg_advance (&cum, mode, type, 0);
9735
9736 if (!parm_rtx)
9737 continue;
9738
9739 if (REG_P (parm_rtx))
9740 {
9741 for (reg = 0;
9742 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9743 reg++)
9744 if (!call_used_regs[reg + REGNO (parm_rtx)])
9745 return true;
9746 }
9747
9748 if (GET_CODE (parm_rtx) == PARALLEL)
9749 {
9750 int i;
9751
9752 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9753 {
9754 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9755
9756 gcc_assert (REG_P (r));
9757
9758 for (reg = 0;
9759 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9760 reg++)
9761 if (!call_used_regs[reg + REGNO (r)])
9762 return true;
9763 }
9764 }
9765
9766 }
9767 return false;
9768 }
9769
9770 /* Return true if the given call expression can be
9771 turned into a sibling call.
9772 DECL holds the declaration of the function to be called whereas
9773 EXP is the call expression itself. */
9774
9775 static bool
9776 s390_function_ok_for_sibcall (tree decl, tree exp)
9777 {
9778 /* The TPF epilogue uses register 1. */
9779 if (TARGET_TPF_PROFILING)
9780 return false;
9781
9782 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9783 which would have to be restored before the sibcall. */
9784 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9785 return false;
9786
9787 /* Register 6 on s390 is available as an argument register but unfortunately
9788 "caller saved". This makes functions needing this register for arguments
9789 not suitable for sibcalls. */
9790 return !s390_call_saved_register_used (exp);
9791 }
9792
9793 /* Return the fixed registers used for condition codes. */
9794
9795 static bool
9796 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9797 {
9798 *p1 = CC_REGNUM;
9799 *p2 = INVALID_REGNUM;
9800
9801 return true;
9802 }
9803
9804 /* This function is used by the call expanders of the machine description.
9805 It emits the call insn itself together with the necessary operations
9806 to adjust the target address and returns the emitted insn.
9807 ADDR_LOCATION is the target address rtx
9808 TLS_CALL the location of the thread-local symbol
9809 RESULT_REG the register where the result of the call should be stored
9810 RETADDR_REG the register where the return address should be stored
9811 If this parameter is NULL_RTX the call is considered
9812 to be a sibling call. */
9813
9814 rtx
9815 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9816 rtx retaddr_reg)
9817 {
9818 bool plt_call = false;
9819 rtx insn;
9820 rtx call;
9821 rtx clobber;
9822 rtvec vec;
9823
9824 /* Direct function calls need special treatment. */
9825 if (GET_CODE (addr_location) == SYMBOL_REF)
9826 {
9827 /* When calling a global routine in PIC mode, we must
9828 replace the symbol itself with the PLT stub. */
9829 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9830 {
9831 if (retaddr_reg != NULL_RTX)
9832 {
9833 addr_location = gen_rtx_UNSPEC (Pmode,
9834 gen_rtvec (1, addr_location),
9835 UNSPEC_PLT);
9836 addr_location = gen_rtx_CONST (Pmode, addr_location);
9837 plt_call = true;
9838 }
9839 else
9840 /* For -fpic code the PLT entries might use r12 which is
9841 call-saved. Therefore we cannot do a sibcall when
9842 calling directly using a symbol ref. When reaching
9843 this point we decided (in s390_function_ok_for_sibcall)
9844 to do a sibcall for a function pointer but one of the
9845 optimizers was able to get rid of the function pointer
9846 by propagating the symbol ref into the call. This
9847 optimization is illegal for S/390 so we turn the direct
9848 call into a indirect call again. */
9849 addr_location = force_reg (Pmode, addr_location);
9850 }
9851
9852 /* Unless we can use the bras(l) insn, force the
9853 routine address into a register. */
9854 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9855 {
9856 if (flag_pic)
9857 addr_location = legitimize_pic_address (addr_location, 0);
9858 else
9859 addr_location = force_reg (Pmode, addr_location);
9860 }
9861 }
9862
9863 /* If it is already an indirect call or the code above moved the
9864 SYMBOL_REF to somewhere else make sure the address can be found in
9865 register 1. */
9866 if (retaddr_reg == NULL_RTX
9867 && GET_CODE (addr_location) != SYMBOL_REF
9868 && !plt_call)
9869 {
9870 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9871 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9872 }
9873
9874 addr_location = gen_rtx_MEM (QImode, addr_location);
9875 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9876
9877 if (result_reg != NULL_RTX)
9878 call = gen_rtx_SET (VOIDmode, result_reg, call);
9879
9880 if (retaddr_reg != NULL_RTX)
9881 {
9882 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9883
9884 if (tls_call != NULL_RTX)
9885 vec = gen_rtvec (3, call, clobber,
9886 gen_rtx_USE (VOIDmode, tls_call));
9887 else
9888 vec = gen_rtvec (2, call, clobber);
9889
9890 call = gen_rtx_PARALLEL (VOIDmode, vec);
9891 }
9892
9893 insn = emit_call_insn (call);
9894
9895 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9896 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9897 {
9898 /* s390_function_ok_for_sibcall should
9899 have denied sibcalls in this case. */
9900 gcc_assert (retaddr_reg != NULL_RTX);
9901
9902 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9903 }
9904 return insn;
9905 }
9906
9907 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9908
9909 static void
9910 s390_conditional_register_usage (void)
9911 {
9912 int i;
9913
9914 if (flag_pic)
9915 {
9916 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9917 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9918 }
9919 if (TARGET_CPU_ZARCH)
9920 {
9921 fixed_regs[BASE_REGNUM] = 0;
9922 call_used_regs[BASE_REGNUM] = 0;
9923 fixed_regs[RETURN_REGNUM] = 0;
9924 call_used_regs[RETURN_REGNUM] = 0;
9925 }
9926 if (TARGET_64BIT)
9927 {
9928 for (i = 24; i < 32; i++)
9929 call_used_regs[i] = call_really_used_regs[i] = 0;
9930 }
9931 else
9932 {
9933 for (i = 18; i < 20; i++)
9934 call_used_regs[i] = call_really_used_regs[i] = 0;
9935 }
9936
9937 if (TARGET_SOFT_FLOAT)
9938 {
9939 for (i = 16; i < 32; i++)
9940 call_used_regs[i] = fixed_regs[i] = 1;
9941 }
9942 }
9943
9944 /* Corresponding function to eh_return expander. */
9945
9946 static GTY(()) rtx s390_tpf_eh_return_symbol;
9947 void
9948 s390_emit_tpf_eh_return (rtx target)
9949 {
9950 rtx insn, reg;
9951
9952 if (!s390_tpf_eh_return_symbol)
9953 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9954
9955 reg = gen_rtx_REG (Pmode, 2);
9956
9957 emit_move_insn (reg, target);
9958 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9959 gen_rtx_REG (Pmode, RETURN_REGNUM));
9960 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9961
9962 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9963 }
9964
9965 /* Rework the prologue/epilogue to avoid saving/restoring
9966 registers unnecessarily. */
9967
9968 static void
9969 s390_optimize_prologue (void)
9970 {
9971 rtx insn, new_insn, next_insn;
9972
9973 /* Do a final recompute of the frame-related data. */
9974
9975 s390_update_frame_layout ();
9976
9977 /* If all special registers are in fact used, there's nothing we
9978 can do, so no point in walking the insn list. */
9979
9980 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9981 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9982 && (TARGET_CPU_ZARCH
9983 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9984 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9985 return;
9986
9987 /* Search for prologue/epilogue insns and replace them. */
9988
9989 for (insn = get_insns (); insn; insn = next_insn)
9990 {
9991 int first, last, off;
9992 rtx set, base, offset;
9993
9994 next_insn = NEXT_INSN (insn);
9995
9996 if (GET_CODE (insn) != INSN)
9997 continue;
9998
9999 if (GET_CODE (PATTERN (insn)) == PARALLEL
10000 && store_multiple_operation (PATTERN (insn), VOIDmode))
10001 {
10002 set = XVECEXP (PATTERN (insn), 0, 0);
10003 first = REGNO (SET_SRC (set));
10004 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10005 offset = const0_rtx;
10006 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10007 off = INTVAL (offset);
10008
10009 if (GET_CODE (base) != REG || off < 0)
10010 continue;
10011 if (cfun_frame_layout.first_save_gpr != -1
10012 && (cfun_frame_layout.first_save_gpr < first
10013 || cfun_frame_layout.last_save_gpr > last))
10014 continue;
10015 if (REGNO (base) != STACK_POINTER_REGNUM
10016 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10017 continue;
10018 if (first > BASE_REGNUM || last < BASE_REGNUM)
10019 continue;
10020
10021 if (cfun_frame_layout.first_save_gpr != -1)
10022 {
10023 new_insn = save_gprs (base,
10024 off + (cfun_frame_layout.first_save_gpr
10025 - first) * UNITS_PER_LONG,
10026 cfun_frame_layout.first_save_gpr,
10027 cfun_frame_layout.last_save_gpr);
10028 new_insn = emit_insn_before (new_insn, insn);
10029 INSN_ADDRESSES_NEW (new_insn, -1);
10030 }
10031
10032 remove_insn (insn);
10033 continue;
10034 }
10035
10036 if (cfun_frame_layout.first_save_gpr == -1
10037 && GET_CODE (PATTERN (insn)) == SET
10038 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10039 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10040 || (!TARGET_CPU_ZARCH
10041 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10042 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10043 {
10044 set = PATTERN (insn);
10045 first = REGNO (SET_SRC (set));
10046 offset = const0_rtx;
10047 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10048 off = INTVAL (offset);
10049
10050 if (GET_CODE (base) != REG || off < 0)
10051 continue;
10052 if (REGNO (base) != STACK_POINTER_REGNUM
10053 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10054 continue;
10055
10056 remove_insn (insn);
10057 continue;
10058 }
10059
10060 if (GET_CODE (PATTERN (insn)) == PARALLEL
10061 && load_multiple_operation (PATTERN (insn), VOIDmode))
10062 {
10063 set = XVECEXP (PATTERN (insn), 0, 0);
10064 first = REGNO (SET_DEST (set));
10065 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10066 offset = const0_rtx;
10067 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10068 off = INTVAL (offset);
10069
10070 if (GET_CODE (base) != REG || off < 0)
10071 continue;
10072 if (cfun_frame_layout.first_restore_gpr != -1
10073 && (cfun_frame_layout.first_restore_gpr < first
10074 || cfun_frame_layout.last_restore_gpr > last))
10075 continue;
10076 if (REGNO (base) != STACK_POINTER_REGNUM
10077 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10078 continue;
10079 if (first > BASE_REGNUM || last < BASE_REGNUM)
10080 continue;
10081
10082 if (cfun_frame_layout.first_restore_gpr != -1)
10083 {
10084 new_insn = restore_gprs (base,
10085 off + (cfun_frame_layout.first_restore_gpr
10086 - first) * UNITS_PER_LONG,
10087 cfun_frame_layout.first_restore_gpr,
10088 cfun_frame_layout.last_restore_gpr);
10089 new_insn = emit_insn_before (new_insn, insn);
10090 INSN_ADDRESSES_NEW (new_insn, -1);
10091 }
10092
10093 remove_insn (insn);
10094 continue;
10095 }
10096
10097 if (cfun_frame_layout.first_restore_gpr == -1
10098 && GET_CODE (PATTERN (insn)) == SET
10099 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10100 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10101 || (!TARGET_CPU_ZARCH
10102 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10103 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10104 {
10105 set = PATTERN (insn);
10106 first = REGNO (SET_DEST (set));
10107 offset = const0_rtx;
10108 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10109 off = INTVAL (offset);
10110
10111 if (GET_CODE (base) != REG || off < 0)
10112 continue;
10113 if (REGNO (base) != STACK_POINTER_REGNUM
10114 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10115 continue;
10116
10117 remove_insn (insn);
10118 continue;
10119 }
10120 }
10121 }
10122
10123 /* On z10 and later the dynamic branch prediction must see the
10124 backward jump within a certain windows. If not it falls back to
10125 the static prediction. This function rearranges the loop backward
10126 branch in a way which makes the static prediction always correct.
10127 The function returns true if it added an instruction. */
10128 static bool
10129 s390_fix_long_loop_prediction (rtx insn)
10130 {
10131 rtx set = single_set (insn);
10132 rtx code_label, label_ref, new_label;
10133 rtx uncond_jump;
10134 rtx cur_insn;
10135 rtx tmp;
10136 int distance;
10137
10138 /* This will exclude branch on count and branch on index patterns
10139 since these are correctly statically predicted. */
10140 if (!set
10141 || SET_DEST (set) != pc_rtx
10142 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10143 return false;
10144
10145 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10146 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10147
10148 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10149
10150 code_label = XEXP (label_ref, 0);
10151
10152 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10153 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10154 || (INSN_ADDRESSES (INSN_UID (insn))
10155 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10156 return false;
10157
10158 for (distance = 0, cur_insn = PREV_INSN (insn);
10159 distance < PREDICT_DISTANCE - 6;
10160 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10161 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10162 return false;
10163
10164 new_label = gen_label_rtx ();
10165 uncond_jump = emit_jump_insn_after (
10166 gen_rtx_SET (VOIDmode, pc_rtx,
10167 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10168 insn);
10169 emit_label_after (new_label, uncond_jump);
10170
10171 tmp = XEXP (SET_SRC (set), 1);
10172 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10173 XEXP (SET_SRC (set), 2) = tmp;
10174 INSN_CODE (insn) = -1;
10175
10176 XEXP (label_ref, 0) = new_label;
10177 JUMP_LABEL (insn) = new_label;
10178 JUMP_LABEL (uncond_jump) = code_label;
10179
10180 return true;
10181 }
10182
10183 /* Returns 1 if INSN reads the value of REG for purposes not related
10184 to addressing of memory, and 0 otherwise. */
10185 static int
10186 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10187 {
10188 return reg_referenced_p (reg, PATTERN (insn))
10189 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10190 }
10191
10192 /* Starting from INSN find_cond_jump looks downwards in the insn
10193 stream for a single jump insn which is the last user of the
10194 condition code set in INSN. */
10195 static rtx
10196 find_cond_jump (rtx insn)
10197 {
10198 for (; insn; insn = NEXT_INSN (insn))
10199 {
10200 rtx ite, cc;
10201
10202 if (LABEL_P (insn))
10203 break;
10204
10205 if (!JUMP_P (insn))
10206 {
10207 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10208 break;
10209 continue;
10210 }
10211
10212 /* This will be triggered by a return. */
10213 if (GET_CODE (PATTERN (insn)) != SET)
10214 break;
10215
10216 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10217 ite = SET_SRC (PATTERN (insn));
10218
10219 if (GET_CODE (ite) != IF_THEN_ELSE)
10220 break;
10221
10222 cc = XEXP (XEXP (ite, 0), 0);
10223 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10224 break;
10225
10226 if (find_reg_note (insn, REG_DEAD, cc))
10227 return insn;
10228 break;
10229 }
10230
10231 return NULL_RTX;
10232 }
10233
10234 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10235 the semantics does not change. If NULL_RTX is passed as COND the
10236 function tries to find the conditional jump starting with INSN. */
10237 static void
10238 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10239 {
10240 rtx tmp = *op0;
10241
10242 if (cond == NULL_RTX)
10243 {
10244 rtx jump = find_cond_jump (NEXT_INSN (insn));
10245 jump = jump ? single_set (jump) : NULL_RTX;
10246
10247 if (jump == NULL_RTX)
10248 return;
10249
10250 cond = XEXP (XEXP (jump, 1), 0);
10251 }
10252
10253 *op0 = *op1;
10254 *op1 = tmp;
10255 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10256 }
10257
10258 /* On z10, instructions of the compare-and-branch family have the
10259 property to access the register occurring as second operand with
10260 its bits complemented. If such a compare is grouped with a second
10261 instruction that accesses the same register non-complemented, and
10262 if that register's value is delivered via a bypass, then the
10263 pipeline recycles, thereby causing significant performance decline.
10264 This function locates such situations and exchanges the two
10265 operands of the compare. The function return true whenever it
10266 added an insn. */
10267 static bool
10268 s390_z10_optimize_cmp (rtx insn)
10269 {
10270 rtx prev_insn, next_insn;
10271 bool insn_added_p = false;
10272 rtx cond, *op0, *op1;
10273
10274 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10275 {
10276 /* Handle compare and branch and branch on count
10277 instructions. */
10278 rtx pattern = single_set (insn);
10279
10280 if (!pattern
10281 || SET_DEST (pattern) != pc_rtx
10282 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10283 return false;
10284
10285 cond = XEXP (SET_SRC (pattern), 0);
10286 op0 = &XEXP (cond, 0);
10287 op1 = &XEXP (cond, 1);
10288 }
10289 else if (GET_CODE (PATTERN (insn)) == SET)
10290 {
10291 rtx src, dest;
10292
10293 /* Handle normal compare instructions. */
10294 src = SET_SRC (PATTERN (insn));
10295 dest = SET_DEST (PATTERN (insn));
10296
10297 if (!REG_P (dest)
10298 || !CC_REGNO_P (REGNO (dest))
10299 || GET_CODE (src) != COMPARE)
10300 return false;
10301
10302 /* s390_swap_cmp will try to find the conditional
10303 jump when passing NULL_RTX as condition. */
10304 cond = NULL_RTX;
10305 op0 = &XEXP (src, 0);
10306 op1 = &XEXP (src, 1);
10307 }
10308 else
10309 return false;
10310
10311 if (!REG_P (*op0) || !REG_P (*op1))
10312 return false;
10313
10314 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10315 return false;
10316
10317 /* Swap the COMPARE arguments and its mask if there is a
10318 conflicting access in the previous insn. */
10319 prev_insn = prev_active_insn (insn);
10320 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10321 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10322 s390_swap_cmp (cond, op0, op1, insn);
10323
10324 /* Check if there is a conflict with the next insn. If there
10325 was no conflict with the previous insn, then swap the
10326 COMPARE arguments and its mask. If we already swapped
10327 the operands, or if swapping them would cause a conflict
10328 with the previous insn, issue a NOP after the COMPARE in
10329 order to separate the two instuctions. */
10330 next_insn = next_active_insn (insn);
10331 if (next_insn != NULL_RTX && INSN_P (next_insn)
10332 && s390_non_addr_reg_read_p (*op1, next_insn))
10333 {
10334 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10335 && s390_non_addr_reg_read_p (*op0, prev_insn))
10336 {
10337 if (REGNO (*op1) == 0)
10338 emit_insn_after (gen_nop1 (), insn);
10339 else
10340 emit_insn_after (gen_nop (), insn);
10341 insn_added_p = true;
10342 }
10343 else
10344 s390_swap_cmp (cond, op0, op1, insn);
10345 }
10346 return insn_added_p;
10347 }
10348
10349 /* Perform machine-dependent processing. */
10350
10351 static void
10352 s390_reorg (void)
10353 {
10354 bool pool_overflow = false;
10355
10356 /* Make sure all splits have been performed; splits after
10357 machine_dependent_reorg might confuse insn length counts. */
10358 split_all_insns_noflow ();
10359
10360 /* Install the main literal pool and the associated base
10361 register load insns.
10362
10363 In addition, there are two problematic situations we need
10364 to correct:
10365
10366 - the literal pool might be > 4096 bytes in size, so that
10367 some of its elements cannot be directly accessed
10368
10369 - a branch target might be > 64K away from the branch, so that
10370 it is not possible to use a PC-relative instruction.
10371
10372 To fix those, we split the single literal pool into multiple
10373 pool chunks, reloading the pool base register at various
10374 points throughout the function to ensure it always points to
10375 the pool chunk the following code expects, and / or replace
10376 PC-relative branches by absolute branches.
10377
10378 However, the two problems are interdependent: splitting the
10379 literal pool can move a branch further away from its target,
10380 causing the 64K limit to overflow, and on the other hand,
10381 replacing a PC-relative branch by an absolute branch means
10382 we need to put the branch target address into the literal
10383 pool, possibly causing it to overflow.
10384
10385 So, we loop trying to fix up both problems until we manage
10386 to satisfy both conditions at the same time. Note that the
10387 loop is guaranteed to terminate as every pass of the loop
10388 strictly decreases the total number of PC-relative branches
10389 in the function. (This is not completely true as there
10390 might be branch-over-pool insns introduced by chunkify_start.
10391 Those never need to be split however.) */
10392
10393 for (;;)
10394 {
10395 struct constant_pool *pool = NULL;
10396
10397 /* Collect the literal pool. */
10398 if (!pool_overflow)
10399 {
10400 pool = s390_mainpool_start ();
10401 if (!pool)
10402 pool_overflow = true;
10403 }
10404
10405 /* If literal pool overflowed, start to chunkify it. */
10406 if (pool_overflow)
10407 pool = s390_chunkify_start ();
10408
10409 /* Split out-of-range branches. If this has created new
10410 literal pool entries, cancel current chunk list and
10411 recompute it. zSeries machines have large branch
10412 instructions, so we never need to split a branch. */
10413 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10414 {
10415 if (pool_overflow)
10416 s390_chunkify_cancel (pool);
10417 else
10418 s390_mainpool_cancel (pool);
10419
10420 continue;
10421 }
10422
10423 /* If we made it up to here, both conditions are satisfied.
10424 Finish up literal pool related changes. */
10425 if (pool_overflow)
10426 s390_chunkify_finish (pool);
10427 else
10428 s390_mainpool_finish (pool);
10429
10430 /* We're done splitting branches. */
10431 cfun->machine->split_branches_pending_p = false;
10432 break;
10433 }
10434
10435 /* Generate out-of-pool execute target insns. */
10436 if (TARGET_CPU_ZARCH)
10437 {
10438 rtx insn, label, target;
10439
10440 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10441 {
10442 label = s390_execute_label (insn);
10443 if (!label)
10444 continue;
10445
10446 gcc_assert (label != const0_rtx);
10447
10448 target = emit_label (XEXP (label, 0));
10449 INSN_ADDRESSES_NEW (target, -1);
10450
10451 target = emit_insn (s390_execute_target (insn));
10452 INSN_ADDRESSES_NEW (target, -1);
10453 }
10454 }
10455
10456 /* Try to optimize prologue and epilogue further. */
10457 s390_optimize_prologue ();
10458
10459 /* Walk over the insns and do some >=z10 specific changes. */
10460 if (s390_tune == PROCESSOR_2097_Z10
10461 || s390_tune == PROCESSOR_2817_Z196)
10462 {
10463 rtx insn;
10464 bool insn_added_p = false;
10465
10466 /* The insn lengths and addresses have to be up to date for the
10467 following manipulations. */
10468 shorten_branches (get_insns ());
10469
10470 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10471 {
10472 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10473 continue;
10474
10475 if (JUMP_P (insn))
10476 insn_added_p |= s390_fix_long_loop_prediction (insn);
10477
10478 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10479 || GET_CODE (PATTERN (insn)) == SET)
10480 && s390_tune == PROCESSOR_2097_Z10)
10481 insn_added_p |= s390_z10_optimize_cmp (insn);
10482 }
10483
10484 /* Adjust branches if we added new instructions. */
10485 if (insn_added_p)
10486 shorten_branches (get_insns ());
10487 }
10488 }
10489
10490 /* Return true if INSN is a fp load insn writing register REGNO. */
10491 static inline bool
10492 s390_fpload_toreg (rtx insn, unsigned int regno)
10493 {
10494 rtx set;
10495 enum attr_type flag = s390_safe_attr_type (insn);
10496
10497 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10498 return false;
10499
10500 set = single_set (insn);
10501
10502 if (set == NULL_RTX)
10503 return false;
10504
10505 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10506 return false;
10507
10508 if (REGNO (SET_DEST (set)) != regno)
10509 return false;
10510
10511 return true;
10512 }
10513
10514 /* This value describes the distance to be avoided between an
10515 aritmetic fp instruction and an fp load writing the same register.
10516 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10517 fine but the exact value has to be avoided. Otherwise the FP
10518 pipeline will throw an exception causing a major penalty. */
10519 #define Z10_EARLYLOAD_DISTANCE 7
10520
10521 /* Rearrange the ready list in order to avoid the situation described
10522 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10523 moved to the very end of the ready list. */
10524 static void
10525 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10526 {
10527 unsigned int regno;
10528 int nready = *nready_p;
10529 rtx tmp;
10530 int i;
10531 rtx insn;
10532 rtx set;
10533 enum attr_type flag;
10534 int distance;
10535
10536 /* Skip DISTANCE - 1 active insns. */
10537 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10538 distance > 0 && insn != NULL_RTX;
10539 distance--, insn = prev_active_insn (insn))
10540 if (CALL_P (insn) || JUMP_P (insn))
10541 return;
10542
10543 if (insn == NULL_RTX)
10544 return;
10545
10546 set = single_set (insn);
10547
10548 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10549 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10550 return;
10551
10552 flag = s390_safe_attr_type (insn);
10553
10554 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10555 return;
10556
10557 regno = REGNO (SET_DEST (set));
10558 i = nready - 1;
10559
10560 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10561 i--;
10562
10563 if (!i)
10564 return;
10565
10566 tmp = ready[i];
10567 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10568 ready[0] = tmp;
10569 }
10570
10571 /* This function is called via hook TARGET_SCHED_REORDER before
10572 issueing one insn from list READY which contains *NREADYP entries.
10573 For target z10 it reorders load instructions to avoid early load
10574 conflicts in the floating point pipeline */
10575 static int
10576 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10577 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10578 {
10579 if (s390_tune == PROCESSOR_2097_Z10)
10580 if (reload_completed && *nreadyp > 1)
10581 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10582
10583 return s390_issue_rate ();
10584 }
10585
10586 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10587 the scheduler has issued INSN. It stores the last issued insn into
10588 last_scheduled_insn in order to make it available for
10589 s390_sched_reorder. */
10590 static int
10591 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10592 int verbose ATTRIBUTE_UNUSED,
10593 rtx insn, int more)
10594 {
10595 last_scheduled_insn = insn;
10596
10597 if (GET_CODE (PATTERN (insn)) != USE
10598 && GET_CODE (PATTERN (insn)) != CLOBBER)
10599 return more - 1;
10600 else
10601 return more;
10602 }
10603
10604 static void
10605 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10606 int verbose ATTRIBUTE_UNUSED,
10607 int max_ready ATTRIBUTE_UNUSED)
10608 {
10609 last_scheduled_insn = NULL_RTX;
10610 }
10611
10612 /* This function checks the whole of insn X for memory references. The
10613 function always returns zero because the framework it is called
10614 from would stop recursively analyzing the insn upon a return value
10615 other than zero. The real result of this function is updating
10616 counter variable MEM_COUNT. */
10617 static int
10618 check_dpu (rtx *x, unsigned *mem_count)
10619 {
10620 if (*x != NULL_RTX && MEM_P (*x))
10621 (*mem_count)++;
10622 return 0;
10623 }
10624
10625 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10626 a new number struct loop *loop should be unrolled if tuned for cpus with
10627 a built-in stride prefetcher.
10628 The loop is analyzed for memory accesses by calling check_dpu for
10629 each rtx of the loop. Depending on the loop_depth and the amount of
10630 memory accesses a new number <=nunroll is returned to improve the
10631 behaviour of the hardware prefetch unit. */
10632 static unsigned
10633 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10634 {
10635 basic_block *bbs;
10636 rtx insn;
10637 unsigned i;
10638 unsigned mem_count = 0;
10639
10640 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10641 return nunroll;
10642
10643 /* Count the number of memory references within the loop body. */
10644 bbs = get_loop_body (loop);
10645 for (i = 0; i < loop->num_nodes; i++)
10646 {
10647 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10648 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10649 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10650 }
10651 free (bbs);
10652
10653 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10654 if (mem_count == 0)
10655 return nunroll;
10656
10657 switch (loop_depth(loop))
10658 {
10659 case 1:
10660 return MIN (nunroll, 28 / mem_count);
10661 case 2:
10662 return MIN (nunroll, 22 / mem_count);
10663 default:
10664 return MIN (nunroll, 16 / mem_count);
10665 }
10666 }
10667
10668 /* Initialize GCC target structure. */
10669
10670 #undef TARGET_ASM_ALIGNED_HI_OP
10671 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10672 #undef TARGET_ASM_ALIGNED_DI_OP
10673 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10674 #undef TARGET_ASM_INTEGER
10675 #define TARGET_ASM_INTEGER s390_assemble_integer
10676
10677 #undef TARGET_ASM_OPEN_PAREN
10678 #define TARGET_ASM_OPEN_PAREN ""
10679
10680 #undef TARGET_ASM_CLOSE_PAREN
10681 #define TARGET_ASM_CLOSE_PAREN ""
10682
10683 #undef TARGET_DEFAULT_TARGET_FLAGS
10684 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
10685
10686 #undef TARGET_HANDLE_OPTION
10687 #define TARGET_HANDLE_OPTION s390_handle_option
10688
10689 #undef TARGET_OPTION_OVERRIDE
10690 #define TARGET_OPTION_OVERRIDE s390_option_override
10691
10692 #undef TARGET_OPTION_OPTIMIZATION_TABLE
10693 #define TARGET_OPTION_OPTIMIZATION_TABLE s390_option_optimization_table
10694
10695 #undef TARGET_OPTION_INIT_STRUCT
10696 #define TARGET_OPTION_INIT_STRUCT s390_option_init_struct
10697
10698 #undef TARGET_ENCODE_SECTION_INFO
10699 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10700
10701 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10702 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10703
10704 #ifdef HAVE_AS_TLS
10705 #undef TARGET_HAVE_TLS
10706 #define TARGET_HAVE_TLS true
10707 #endif
10708 #undef TARGET_CANNOT_FORCE_CONST_MEM
10709 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10710
10711 #undef TARGET_DELEGITIMIZE_ADDRESS
10712 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10713
10714 #undef TARGET_LEGITIMIZE_ADDRESS
10715 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10716
10717 #undef TARGET_RETURN_IN_MEMORY
10718 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10719
10720 #undef TARGET_INIT_BUILTINS
10721 #define TARGET_INIT_BUILTINS s390_init_builtins
10722 #undef TARGET_EXPAND_BUILTIN
10723 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10724
10725 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10726 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10727
10728 #undef TARGET_ASM_OUTPUT_MI_THUNK
10729 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10730 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10731 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10732
10733 #undef TARGET_SCHED_ADJUST_PRIORITY
10734 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10735 #undef TARGET_SCHED_ISSUE_RATE
10736 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10737 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10738 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10739
10740 #undef TARGET_SCHED_VARIABLE_ISSUE
10741 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10742 #undef TARGET_SCHED_REORDER
10743 #define TARGET_SCHED_REORDER s390_sched_reorder
10744 #undef TARGET_SCHED_INIT
10745 #define TARGET_SCHED_INIT s390_sched_init
10746
10747 #undef TARGET_CANNOT_COPY_INSN_P
10748 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10749 #undef TARGET_RTX_COSTS
10750 #define TARGET_RTX_COSTS s390_rtx_costs
10751 #undef TARGET_ADDRESS_COST
10752 #define TARGET_ADDRESS_COST s390_address_cost
10753 #undef TARGET_REGISTER_MOVE_COST
10754 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10755 #undef TARGET_MEMORY_MOVE_COST
10756 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10757
10758 #undef TARGET_MACHINE_DEPENDENT_REORG
10759 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10760
10761 #undef TARGET_VALID_POINTER_MODE
10762 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10763
10764 #undef TARGET_BUILD_BUILTIN_VA_LIST
10765 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10766 #undef TARGET_EXPAND_BUILTIN_VA_START
10767 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10768 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10769 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10770
10771 #undef TARGET_PROMOTE_FUNCTION_MODE
10772 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10773 #undef TARGET_PASS_BY_REFERENCE
10774 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10775
10776 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10777 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10778 #undef TARGET_FUNCTION_ARG
10779 #define TARGET_FUNCTION_ARG s390_function_arg
10780 #undef TARGET_FUNCTION_ARG_ADVANCE
10781 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10782 #undef TARGET_FUNCTION_VALUE
10783 #define TARGET_FUNCTION_VALUE s390_function_value
10784 #undef TARGET_LIBCALL_VALUE
10785 #define TARGET_LIBCALL_VALUE s390_libcall_value
10786
10787 #undef TARGET_FIXED_CONDITION_CODE_REGS
10788 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10789
10790 #undef TARGET_CC_MODES_COMPATIBLE
10791 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10792
10793 #undef TARGET_INVALID_WITHIN_DOLOOP
10794 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10795
10796 #ifdef HAVE_AS_TLS
10797 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10798 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10799 #endif
10800
10801 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10802 #undef TARGET_MANGLE_TYPE
10803 #define TARGET_MANGLE_TYPE s390_mangle_type
10804 #endif
10805
10806 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10807 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10808
10809 #undef TARGET_PREFERRED_RELOAD_CLASS
10810 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10811
10812 #undef TARGET_SECONDARY_RELOAD
10813 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10814
10815 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10816 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10817
10818 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10819 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10820
10821 #undef TARGET_LEGITIMATE_ADDRESS_P
10822 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10823
10824 #undef TARGET_CAN_ELIMINATE
10825 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10826
10827 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10828 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10829
10830 #undef TARGET_LOOP_UNROLL_ADJUST
10831 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10832
10833 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10834 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10835 #undef TARGET_TRAMPOLINE_INIT
10836 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10837
10838 #undef TARGET_UNWIND_WORD_MODE
10839 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10840
10841 struct gcc_target targetm = TARGET_INITIALIZER;
10842
10843 #include "gt-s390.h"