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fwprop.c (should_replace_address): Add speed attribute.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (10), /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (10), /* MADBR */
213 COSTS_N_INSNS (10), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 extern int reload_completed;
225
226 /* Save information from a "cmpxx" operation until the branch or scc is
227 emitted. */
228 rtx s390_compare_op0, s390_compare_op1;
229
230 /* Save the result of a compare_and_swap until the branch or scc is
231 emitted. */
232 rtx s390_compare_emitted = NULL_RTX;
233
234 /* Structure used to hold the components of a S/390 memory
235 address. A legitimate address on S/390 is of the general
236 form
237 base + index + displacement
238 where any of the components is optional.
239
240 base and index are registers of the class ADDR_REGS,
241 displacement is an unsigned 12-bit immediate constant. */
242
243 struct s390_address
244 {
245 rtx base;
246 rtx indx;
247 rtx disp;
248 bool pointer;
249 bool literal_pool;
250 };
251
252 /* Which cpu are we tuning for. */
253 enum processor_type s390_tune = PROCESSOR_max;
254 enum processor_flags s390_tune_flags;
255 /* Which instruction set architecture to use. */
256 enum processor_type s390_arch;
257 enum processor_flags s390_arch_flags;
258
259 HOST_WIDE_INT s390_warn_framesize = 0;
260 HOST_WIDE_INT s390_stack_size = 0;
261 HOST_WIDE_INT s390_stack_guard = 0;
262
263 /* The following structure is embedded in the machine
264 specific part of struct function. */
265
266 struct s390_frame_layout GTY (())
267 {
268 /* Offset within stack frame. */
269 HOST_WIDE_INT gprs_offset;
270 HOST_WIDE_INT f0_offset;
271 HOST_WIDE_INT f4_offset;
272 HOST_WIDE_INT f8_offset;
273 HOST_WIDE_INT backchain_offset;
274
275 /* Number of first and last gpr where slots in the register
276 save area are reserved for. */
277 int first_save_gpr_slot;
278 int last_save_gpr_slot;
279
280 /* Number of first and last gpr to be saved, restored. */
281 int first_save_gpr;
282 int first_restore_gpr;
283 int last_save_gpr;
284 int last_restore_gpr;
285
286 /* Bits standing for floating point registers. Set, if the
287 respective register has to be saved. Starting with reg 16 (f0)
288 at the rightmost bit.
289 Bit 15 - 8 7 6 5 4 3 2 1 0
290 fpr 15 - 8 7 5 3 1 6 4 2 0
291 reg 31 - 24 23 22 21 20 19 18 17 16 */
292 unsigned int fpr_bitmap;
293
294 /* Number of floating point registers f8-f15 which must be saved. */
295 int high_fprs;
296
297 /* Set if return address needs to be saved.
298 This flag is set by s390_return_addr_rtx if it could not use
299 the initial value of r14 and therefore depends on r14 saved
300 to the stack. */
301 bool save_return_addr_p;
302
303 /* Size of stack frame. */
304 HOST_WIDE_INT frame_size;
305 };
306
307 /* Define the structure for the machine field in struct function. */
308
309 struct machine_function GTY(())
310 {
311 struct s390_frame_layout frame_layout;
312
313 /* Literal pool base register. */
314 rtx base_reg;
315
316 /* True if we may need to perform branch splitting. */
317 bool split_branches_pending_p;
318
319 /* True during final stage of literal pool processing. */
320 bool decomposed_literal_pool_addresses_ok_p;
321
322 /* Some local-dynamic TLS symbol name. */
323 const char *some_ld_name;
324
325 bool has_landing_pad_p;
326 };
327
328 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
329
330 #define cfun_frame_layout (cfun->machine->frame_layout)
331 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
332 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
333 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
334 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
335 (1 << (BITNUM)))
336 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
337 (1 << (BITNUM))))
338
339 /* Number of GPRs and FPRs used for argument passing. */
340 #define GP_ARG_NUM_REG 5
341 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
342
343 /* A couple of shortcuts. */
344 #define CONST_OK_FOR_J(x) \
345 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
346 #define CONST_OK_FOR_K(x) \
347 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
348 #define CONST_OK_FOR_Os(x) \
349 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
350 #define CONST_OK_FOR_Op(x) \
351 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
352 #define CONST_OK_FOR_On(x) \
353 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
354
355 #define REGNO_PAIR_OK(REGNO, MODE) \
356 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
357
358 static enum machine_mode
359 s390_libgcc_cmp_return_mode (void)
360 {
361 return TARGET_64BIT ? DImode : SImode;
362 }
363
364 static enum machine_mode
365 s390_libgcc_shift_count_mode (void)
366 {
367 return TARGET_64BIT ? DImode : SImode;
368 }
369
370 /* Return true if the back end supports mode MODE. */
371 static bool
372 s390_scalar_mode_supported_p (enum machine_mode mode)
373 {
374 if (DECIMAL_FLOAT_MODE_P (mode))
375 return true;
376 else
377 return default_scalar_mode_supported_p (mode);
378 }
379
380 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
381
382 void
383 s390_set_has_landing_pad_p (bool value)
384 {
385 cfun->machine->has_landing_pad_p = value;
386 }
387
388 /* If two condition code modes are compatible, return a condition code
389 mode which is compatible with both. Otherwise, return
390 VOIDmode. */
391
392 static enum machine_mode
393 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
394 {
395 if (m1 == m2)
396 return m1;
397
398 switch (m1)
399 {
400 case CCZmode:
401 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
402 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
403 return m2;
404 return VOIDmode;
405
406 case CCSmode:
407 case CCUmode:
408 case CCTmode:
409 case CCSRmode:
410 case CCURmode:
411 case CCZ1mode:
412 if (m2 == CCZmode)
413 return m1;
414
415 return VOIDmode;
416
417 default:
418 return VOIDmode;
419 }
420 return VOIDmode;
421 }
422
423 /* Return true if SET either doesn't set the CC register, or else
424 the source and destination have matching CC modes and that
425 CC mode is at least as constrained as REQ_MODE. */
426
427 static bool
428 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
429 {
430 enum machine_mode set_mode;
431
432 gcc_assert (GET_CODE (set) == SET);
433
434 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
435 return 1;
436
437 set_mode = GET_MODE (SET_DEST (set));
438 switch (set_mode)
439 {
440 case CCSmode:
441 case CCSRmode:
442 case CCUmode:
443 case CCURmode:
444 case CCLmode:
445 case CCL1mode:
446 case CCL2mode:
447 case CCL3mode:
448 case CCT1mode:
449 case CCT2mode:
450 case CCT3mode:
451 if (req_mode != set_mode)
452 return 0;
453 break;
454
455 case CCZmode:
456 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
457 && req_mode != CCSRmode && req_mode != CCURmode)
458 return 0;
459 break;
460
461 case CCAPmode:
462 case CCANmode:
463 if (req_mode != CCAmode)
464 return 0;
465 break;
466
467 default:
468 gcc_unreachable ();
469 }
470
471 return (GET_MODE (SET_SRC (set)) == set_mode);
472 }
473
474 /* Return true if every SET in INSN that sets the CC register
475 has source and destination with matching CC modes and that
476 CC mode is at least as constrained as REQ_MODE.
477 If REQ_MODE is VOIDmode, always return false. */
478
479 bool
480 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
481 {
482 int i;
483
484 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
485 if (req_mode == VOIDmode)
486 return false;
487
488 if (GET_CODE (PATTERN (insn)) == SET)
489 return s390_match_ccmode_set (PATTERN (insn), req_mode);
490
491 if (GET_CODE (PATTERN (insn)) == PARALLEL)
492 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
493 {
494 rtx set = XVECEXP (PATTERN (insn), 0, i);
495 if (GET_CODE (set) == SET)
496 if (!s390_match_ccmode_set (set, req_mode))
497 return false;
498 }
499
500 return true;
501 }
502
503 /* If a test-under-mask instruction can be used to implement
504 (compare (and ... OP1) OP2), return the CC mode required
505 to do that. Otherwise, return VOIDmode.
506 MIXED is true if the instruction can distinguish between
507 CC1 and CC2 for mixed selected bits (TMxx), it is false
508 if the instruction cannot (TM). */
509
510 enum machine_mode
511 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
512 {
513 int bit0, bit1;
514
515 /* ??? Fixme: should work on CONST_DOUBLE as well. */
516 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
517 return VOIDmode;
518
519 /* Selected bits all zero: CC0.
520 e.g.: int a; if ((a & (16 + 128)) == 0) */
521 if (INTVAL (op2) == 0)
522 return CCTmode;
523
524 /* Selected bits all one: CC3.
525 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
526 if (INTVAL (op2) == INTVAL (op1))
527 return CCT3mode;
528
529 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
530 int a;
531 if ((a & (16 + 128)) == 16) -> CCT1
532 if ((a & (16 + 128)) == 128) -> CCT2 */
533 if (mixed)
534 {
535 bit1 = exact_log2 (INTVAL (op2));
536 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
537 if (bit0 != -1 && bit1 != -1)
538 return bit0 > bit1 ? CCT1mode : CCT2mode;
539 }
540
541 return VOIDmode;
542 }
543
544 /* Given a comparison code OP (EQ, NE, etc.) and the operands
545 OP0 and OP1 of a COMPARE, return the mode to be used for the
546 comparison. */
547
548 enum machine_mode
549 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
550 {
551 switch (code)
552 {
553 case EQ:
554 case NE:
555 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
556 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
557 return CCAPmode;
558 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
559 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
560 return CCAPmode;
561 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
562 || GET_CODE (op1) == NEG)
563 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
564 return CCLmode;
565
566 if (GET_CODE (op0) == AND)
567 {
568 /* Check whether we can potentially do it via TM. */
569 enum machine_mode ccmode;
570 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
571 if (ccmode != VOIDmode)
572 {
573 /* Relax CCTmode to CCZmode to allow fall-back to AND
574 if that turns out to be beneficial. */
575 return ccmode == CCTmode ? CCZmode : ccmode;
576 }
577 }
578
579 if (register_operand (op0, HImode)
580 && GET_CODE (op1) == CONST_INT
581 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
582 return CCT3mode;
583 if (register_operand (op0, QImode)
584 && GET_CODE (op1) == CONST_INT
585 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
586 return CCT3mode;
587
588 return CCZmode;
589
590 case LE:
591 case LT:
592 case GE:
593 case GT:
594 /* The only overflow condition of NEG and ABS happens when
595 -INT_MAX is used as parameter, which stays negative. So
596 we have an overflow from a positive value to a negative.
597 Using CCAP mode the resulting cc can be used for comparisons. */
598 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
599 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
600 return CCAPmode;
601
602 /* If constants are involved in an add instruction it is possible to use
603 the resulting cc for comparisons with zero. Knowing the sign of the
604 constant the overflow behavior gets predictable. e.g.:
605 int a, b; if ((b = a + c) > 0)
606 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
607 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
608 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
609 {
610 if (INTVAL (XEXP((op0), 1)) < 0)
611 return CCANmode;
612 else
613 return CCAPmode;
614 }
615 /* Fall through. */
616 case UNORDERED:
617 case ORDERED:
618 case UNEQ:
619 case UNLE:
620 case UNLT:
621 case UNGE:
622 case UNGT:
623 case LTGT:
624 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
625 && GET_CODE (op1) != CONST_INT)
626 return CCSRmode;
627 return CCSmode;
628
629 case LTU:
630 case GEU:
631 if (GET_CODE (op0) == PLUS
632 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
633 return CCL1mode;
634
635 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
636 && GET_CODE (op1) != CONST_INT)
637 return CCURmode;
638 return CCUmode;
639
640 case LEU:
641 case GTU:
642 if (GET_CODE (op0) == MINUS
643 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
644 return CCL2mode;
645
646 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
647 && GET_CODE (op1) != CONST_INT)
648 return CCURmode;
649 return CCUmode;
650
651 default:
652 gcc_unreachable ();
653 }
654 }
655
656 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
657 that we can implement more efficiently. */
658
659 void
660 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
661 {
662 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
663 if ((*code == EQ || *code == NE)
664 && *op1 == const0_rtx
665 && GET_CODE (*op0) == ZERO_EXTRACT
666 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
667 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
668 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
669 {
670 rtx inner = XEXP (*op0, 0);
671 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
672 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
673 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
674
675 if (len > 0 && len < modesize
676 && pos >= 0 && pos + len <= modesize
677 && modesize <= HOST_BITS_PER_WIDE_INT)
678 {
679 unsigned HOST_WIDE_INT block;
680 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
681 block <<= modesize - pos - len;
682
683 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
684 gen_int_mode (block, GET_MODE (inner)));
685 }
686 }
687
688 /* Narrow AND of memory against immediate to enable TM. */
689 if ((*code == EQ || *code == NE)
690 && *op1 == const0_rtx
691 && GET_CODE (*op0) == AND
692 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
693 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
694 {
695 rtx inner = XEXP (*op0, 0);
696 rtx mask = XEXP (*op0, 1);
697
698 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
699 if (GET_CODE (inner) == SUBREG
700 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
701 && (GET_MODE_SIZE (GET_MODE (inner))
702 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
703 && ((INTVAL (mask)
704 & GET_MODE_MASK (GET_MODE (inner))
705 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
706 == 0))
707 inner = SUBREG_REG (inner);
708
709 /* Do not change volatile MEMs. */
710 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
711 {
712 int part = s390_single_part (XEXP (*op0, 1),
713 GET_MODE (inner), QImode, 0);
714 if (part >= 0)
715 {
716 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
717 inner = adjust_address_nv (inner, QImode, part);
718 *op0 = gen_rtx_AND (QImode, inner, mask);
719 }
720 }
721 }
722
723 /* Narrow comparisons against 0xffff to HImode if possible. */
724 if ((*code == EQ || *code == NE)
725 && GET_CODE (*op1) == CONST_INT
726 && INTVAL (*op1) == 0xffff
727 && SCALAR_INT_MODE_P (GET_MODE (*op0))
728 && (nonzero_bits (*op0, GET_MODE (*op0))
729 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
730 {
731 *op0 = gen_lowpart (HImode, *op0);
732 *op1 = constm1_rtx;
733 }
734
735 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
736 if (GET_CODE (*op0) == UNSPEC
737 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
738 && XVECLEN (*op0, 0) == 1
739 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
740 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
741 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
742 && *op1 == const0_rtx)
743 {
744 enum rtx_code new_code = UNKNOWN;
745 switch (*code)
746 {
747 case EQ: new_code = EQ; break;
748 case NE: new_code = NE; break;
749 case LT: new_code = GTU; break;
750 case GT: new_code = LTU; break;
751 case LE: new_code = GEU; break;
752 case GE: new_code = LEU; break;
753 default: break;
754 }
755
756 if (new_code != UNKNOWN)
757 {
758 *op0 = XVECEXP (*op0, 0, 0);
759 *code = new_code;
760 }
761 }
762
763 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
764 if (GET_CODE (*op0) == UNSPEC
765 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
766 && XVECLEN (*op0, 0) == 1
767 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
768 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
769 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
770 && *op1 == const0_rtx)
771 {
772 enum rtx_code new_code = UNKNOWN;
773 switch (*code)
774 {
775 case EQ: new_code = EQ; break;
776 case NE: new_code = NE; break;
777 default: break;
778 }
779
780 if (new_code != UNKNOWN)
781 {
782 *op0 = XVECEXP (*op0, 0, 0);
783 *code = new_code;
784 }
785 }
786
787 /* Simplify cascaded EQ, NE with const0_rtx. */
788 if ((*code == NE || *code == EQ)
789 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
790 && GET_MODE (*op0) == SImode
791 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
792 && REG_P (XEXP (*op0, 0))
793 && XEXP (*op0, 1) == const0_rtx
794 && *op1 == const0_rtx)
795 {
796 if ((*code == EQ && GET_CODE (*op0) == NE)
797 || (*code == NE && GET_CODE (*op0) == EQ))
798 *code = EQ;
799 else
800 *code = NE;
801 *op0 = XEXP (*op0, 0);
802 }
803
804 /* Prefer register over memory as first operand. */
805 if (MEM_P (*op0) && REG_P (*op1))
806 {
807 rtx tem = *op0; *op0 = *op1; *op1 = tem;
808 *code = swap_condition (*code);
809 }
810 }
811
812 /* Emit a compare instruction suitable to implement the comparison
813 OP0 CODE OP1. Return the correct condition RTL to be placed in
814 the IF_THEN_ELSE of the conditional branch testing the result. */
815
816 rtx
817 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
818 {
819 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
820 rtx ret = NULL_RTX;
821
822 /* Do not output a redundant compare instruction if a compare_and_swap
823 pattern already computed the result and the machine modes are compatible. */
824 if (s390_compare_emitted
825 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
826 == GET_MODE (s390_compare_emitted)))
827 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
828 else
829 {
830 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
831
832 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
833 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
834 }
835 s390_compare_emitted = NULL_RTX;
836 return ret;
837 }
838
839 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
840 matches CMP.
841 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
842 conditional branch testing the result. */
843
844 static rtx
845 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
846 {
847 rtx ret;
848
849 emit_insn (gen_sync_compare_and_swap_ccsi (old, mem, cmp, new_rtx));
850 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
851
852 s390_compare_emitted = NULL_RTX;
853
854 return ret;
855 }
856
857 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
858 unconditional jump, else a conditional jump under condition COND. */
859
860 void
861 s390_emit_jump (rtx target, rtx cond)
862 {
863 rtx insn;
864
865 target = gen_rtx_LABEL_REF (VOIDmode, target);
866 if (cond)
867 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
868
869 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
870 emit_jump_insn (insn);
871 }
872
873 /* Return branch condition mask to implement a branch
874 specified by CODE. Return -1 for invalid comparisons. */
875
876 int
877 s390_branch_condition_mask (rtx code)
878 {
879 const int CC0 = 1 << 3;
880 const int CC1 = 1 << 2;
881 const int CC2 = 1 << 1;
882 const int CC3 = 1 << 0;
883
884 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
885 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
886 gcc_assert (XEXP (code, 1) == const0_rtx);
887
888 switch (GET_MODE (XEXP (code, 0)))
889 {
890 case CCZmode:
891 case CCZ1mode:
892 switch (GET_CODE (code))
893 {
894 case EQ: return CC0;
895 case NE: return CC1 | CC2 | CC3;
896 default: return -1;
897 }
898 break;
899
900 case CCT1mode:
901 switch (GET_CODE (code))
902 {
903 case EQ: return CC1;
904 case NE: return CC0 | CC2 | CC3;
905 default: return -1;
906 }
907 break;
908
909 case CCT2mode:
910 switch (GET_CODE (code))
911 {
912 case EQ: return CC2;
913 case NE: return CC0 | CC1 | CC3;
914 default: return -1;
915 }
916 break;
917
918 case CCT3mode:
919 switch (GET_CODE (code))
920 {
921 case EQ: return CC3;
922 case NE: return CC0 | CC1 | CC2;
923 default: return -1;
924 }
925 break;
926
927 case CCLmode:
928 switch (GET_CODE (code))
929 {
930 case EQ: return CC0 | CC2;
931 case NE: return CC1 | CC3;
932 default: return -1;
933 }
934 break;
935
936 case CCL1mode:
937 switch (GET_CODE (code))
938 {
939 case LTU: return CC2 | CC3; /* carry */
940 case GEU: return CC0 | CC1; /* no carry */
941 default: return -1;
942 }
943 break;
944
945 case CCL2mode:
946 switch (GET_CODE (code))
947 {
948 case GTU: return CC0 | CC1; /* borrow */
949 case LEU: return CC2 | CC3; /* no borrow */
950 default: return -1;
951 }
952 break;
953
954 case CCL3mode:
955 switch (GET_CODE (code))
956 {
957 case EQ: return CC0 | CC2;
958 case NE: return CC1 | CC3;
959 case LTU: return CC1;
960 case GTU: return CC3;
961 case LEU: return CC1 | CC2;
962 case GEU: return CC2 | CC3;
963 default: return -1;
964 }
965
966 case CCUmode:
967 switch (GET_CODE (code))
968 {
969 case EQ: return CC0;
970 case NE: return CC1 | CC2 | CC3;
971 case LTU: return CC1;
972 case GTU: return CC2;
973 case LEU: return CC0 | CC1;
974 case GEU: return CC0 | CC2;
975 default: return -1;
976 }
977 break;
978
979 case CCURmode:
980 switch (GET_CODE (code))
981 {
982 case EQ: return CC0;
983 case NE: return CC2 | CC1 | CC3;
984 case LTU: return CC2;
985 case GTU: return CC1;
986 case LEU: return CC0 | CC2;
987 case GEU: return CC0 | CC1;
988 default: return -1;
989 }
990 break;
991
992 case CCAPmode:
993 switch (GET_CODE (code))
994 {
995 case EQ: return CC0;
996 case NE: return CC1 | CC2 | CC3;
997 case LT: return CC1 | CC3;
998 case GT: return CC2;
999 case LE: return CC0 | CC1 | CC3;
1000 case GE: return CC0 | CC2;
1001 default: return -1;
1002 }
1003 break;
1004
1005 case CCANmode:
1006 switch (GET_CODE (code))
1007 {
1008 case EQ: return CC0;
1009 case NE: return CC1 | CC2 | CC3;
1010 case LT: return CC1;
1011 case GT: return CC2 | CC3;
1012 case LE: return CC0 | CC1;
1013 case GE: return CC0 | CC2 | CC3;
1014 default: return -1;
1015 }
1016 break;
1017
1018 case CCSmode:
1019 switch (GET_CODE (code))
1020 {
1021 case EQ: return CC0;
1022 case NE: return CC1 | CC2 | CC3;
1023 case LT: return CC1;
1024 case GT: return CC2;
1025 case LE: return CC0 | CC1;
1026 case GE: return CC0 | CC2;
1027 case UNORDERED: return CC3;
1028 case ORDERED: return CC0 | CC1 | CC2;
1029 case UNEQ: return CC0 | CC3;
1030 case UNLT: return CC1 | CC3;
1031 case UNGT: return CC2 | CC3;
1032 case UNLE: return CC0 | CC1 | CC3;
1033 case UNGE: return CC0 | CC2 | CC3;
1034 case LTGT: return CC1 | CC2;
1035 default: return -1;
1036 }
1037 break;
1038
1039 case CCSRmode:
1040 switch (GET_CODE (code))
1041 {
1042 case EQ: return CC0;
1043 case NE: return CC2 | CC1 | CC3;
1044 case LT: return CC2;
1045 case GT: return CC1;
1046 case LE: return CC0 | CC2;
1047 case GE: return CC0 | CC1;
1048 case UNORDERED: return CC3;
1049 case ORDERED: return CC0 | CC2 | CC1;
1050 case UNEQ: return CC0 | CC3;
1051 case UNLT: return CC2 | CC3;
1052 case UNGT: return CC1 | CC3;
1053 case UNLE: return CC0 | CC2 | CC3;
1054 case UNGE: return CC0 | CC1 | CC3;
1055 case LTGT: return CC2 | CC1;
1056 default: return -1;
1057 }
1058 break;
1059
1060 default:
1061 return -1;
1062 }
1063 }
1064
1065
1066 /* Return branch condition mask to implement a compare and branch
1067 specified by CODE. Return -1 for invalid comparisons. */
1068
1069 int
1070 s390_compare_and_branch_condition_mask (rtx code)
1071 {
1072 const int CC0 = 1 << 3;
1073 const int CC1 = 1 << 2;
1074 const int CC2 = 1 << 1;
1075
1076 switch (GET_CODE (code))
1077 {
1078 case EQ:
1079 return CC0;
1080 case NE:
1081 return CC1 | CC2;
1082 case LT:
1083 case LTU:
1084 return CC1;
1085 case GT:
1086 case GTU:
1087 return CC2;
1088 case LE:
1089 case LEU:
1090 return CC0 | CC1;
1091 case GE:
1092 case GEU:
1093 return CC0 | CC2;
1094 default:
1095 gcc_unreachable ();
1096 }
1097 return -1;
1098 }
1099
1100 /* If INV is false, return assembler mnemonic string to implement
1101 a branch specified by CODE. If INV is true, return mnemonic
1102 for the corresponding inverted branch. */
1103
1104 static const char *
1105 s390_branch_condition_mnemonic (rtx code, int inv)
1106 {
1107 int mask;
1108
1109 static const char *const mnemonic[16] =
1110 {
1111 NULL, "o", "h", "nle",
1112 "l", "nhe", "lh", "ne",
1113 "e", "nlh", "he", "nl",
1114 "le", "nh", "no", NULL
1115 };
1116
1117 if (GET_CODE (XEXP (code, 0)) == REG
1118 && REGNO (XEXP (code, 0)) == CC_REGNUM
1119 && XEXP (code, 1) == const0_rtx)
1120 mask = s390_branch_condition_mask (code);
1121 else
1122 mask = s390_compare_and_branch_condition_mask (code);
1123
1124 gcc_assert (mask >= 0);
1125
1126 if (inv)
1127 mask ^= 15;
1128
1129 gcc_assert (mask >= 1 && mask <= 14);
1130
1131 return mnemonic[mask];
1132 }
1133
1134 /* Return the part of op which has a value different from def.
1135 The size of the part is determined by mode.
1136 Use this function only if you already know that op really
1137 contains such a part. */
1138
1139 unsigned HOST_WIDE_INT
1140 s390_extract_part (rtx op, enum machine_mode mode, int def)
1141 {
1142 unsigned HOST_WIDE_INT value = 0;
1143 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1144 int part_bits = GET_MODE_BITSIZE (mode);
1145 unsigned HOST_WIDE_INT part_mask
1146 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1147 int i;
1148
1149 for (i = 0; i < max_parts; i++)
1150 {
1151 if (i == 0)
1152 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1153 else
1154 value >>= part_bits;
1155
1156 if ((value & part_mask) != (def & part_mask))
1157 return value & part_mask;
1158 }
1159
1160 gcc_unreachable ();
1161 }
1162
1163 /* If OP is an integer constant of mode MODE with exactly one
1164 part of mode PART_MODE unequal to DEF, return the number of that
1165 part. Otherwise, return -1. */
1166
1167 int
1168 s390_single_part (rtx op,
1169 enum machine_mode mode,
1170 enum machine_mode part_mode,
1171 int def)
1172 {
1173 unsigned HOST_WIDE_INT value = 0;
1174 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1175 unsigned HOST_WIDE_INT part_mask
1176 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1177 int i, part = -1;
1178
1179 if (GET_CODE (op) != CONST_INT)
1180 return -1;
1181
1182 for (i = 0; i < n_parts; i++)
1183 {
1184 if (i == 0)
1185 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1186 else
1187 value >>= GET_MODE_BITSIZE (part_mode);
1188
1189 if ((value & part_mask) != (def & part_mask))
1190 {
1191 if (part != -1)
1192 return -1;
1193 else
1194 part = i;
1195 }
1196 }
1197 return part == -1 ? -1 : n_parts - 1 - part;
1198 }
1199
1200 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1201 bits and no other bits are set in IN. POS and LENGTH can be used
1202 to obtain the start position and the length of the bitfield.
1203
1204 POS gives the position of the first bit of the bitfield counting
1205 from the lowest order bit starting with zero. In order to use this
1206 value for S/390 instructions this has to be converted to "bits big
1207 endian" style. */
1208
1209 bool
1210 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1211 int *pos, int *length)
1212 {
1213 int tmp_pos = 0;
1214 int tmp_length = 0;
1215 int i;
1216 unsigned HOST_WIDE_INT mask = 1ULL;
1217 bool contiguous = false;
1218
1219 for (i = 0; i < size; mask <<= 1, i++)
1220 {
1221 if (contiguous)
1222 {
1223 if (mask & in)
1224 tmp_length++;
1225 else
1226 break;
1227 }
1228 else
1229 {
1230 if (mask & in)
1231 {
1232 contiguous = true;
1233 tmp_length++;
1234 }
1235 else
1236 tmp_pos++;
1237 }
1238 }
1239
1240 if (!tmp_length)
1241 return false;
1242
1243 /* Calculate a mask for all bits beyond the contiguous bits. */
1244 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1245
1246 if (mask & in)
1247 return false;
1248
1249 if (tmp_length + tmp_pos - 1 > size)
1250 return false;
1251
1252 if (length)
1253 *length = tmp_length;
1254
1255 if (pos)
1256 *pos = tmp_pos;
1257
1258 return true;
1259 }
1260
1261 /* Check whether we can (and want to) split a double-word
1262 move in mode MODE from SRC to DST into two single-word
1263 moves, moving the subword FIRST_SUBWORD first. */
1264
1265 bool
1266 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1267 {
1268 /* Floating point registers cannot be split. */
1269 if (FP_REG_P (src) || FP_REG_P (dst))
1270 return false;
1271
1272 /* We don't need to split if operands are directly accessible. */
1273 if (s_operand (src, mode) || s_operand (dst, mode))
1274 return false;
1275
1276 /* Non-offsettable memory references cannot be split. */
1277 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1278 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1279 return false;
1280
1281 /* Moving the first subword must not clobber a register
1282 needed to move the second subword. */
1283 if (register_operand (dst, mode))
1284 {
1285 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1286 if (reg_overlap_mentioned_p (subreg, src))
1287 return false;
1288 }
1289
1290 return true;
1291 }
1292
1293 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1294 and [MEM2, MEM2 + SIZE] do overlap and false
1295 otherwise. */
1296
1297 bool
1298 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1299 {
1300 rtx addr1, addr2, addr_delta;
1301 HOST_WIDE_INT delta;
1302
1303 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1304 return true;
1305
1306 if (size == 0)
1307 return false;
1308
1309 addr1 = XEXP (mem1, 0);
1310 addr2 = XEXP (mem2, 0);
1311
1312 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1313
1314 /* This overlapping check is used by peepholes merging memory block operations.
1315 Overlapping operations would otherwise be recognized by the S/390 hardware
1316 and would fall back to a slower implementation. Allowing overlapping
1317 operations would lead to slow code but not to wrong code. Therefore we are
1318 somewhat optimistic if we cannot prove that the memory blocks are
1319 overlapping.
1320 That's why we return false here although this may accept operations on
1321 overlapping memory areas. */
1322 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1323 return false;
1324
1325 delta = INTVAL (addr_delta);
1326
1327 if (delta == 0
1328 || (delta > 0 && delta < size)
1329 || (delta < 0 && -delta < size))
1330 return true;
1331
1332 return false;
1333 }
1334
1335 /* Check whether the address of memory reference MEM2 equals exactly
1336 the address of memory reference MEM1 plus DELTA. Return true if
1337 we can prove this to be the case, false otherwise. */
1338
1339 bool
1340 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1341 {
1342 rtx addr1, addr2, addr_delta;
1343
1344 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1345 return false;
1346
1347 addr1 = XEXP (mem1, 0);
1348 addr2 = XEXP (mem2, 0);
1349
1350 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1351 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1352 return false;
1353
1354 return true;
1355 }
1356
1357 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1358
1359 void
1360 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1361 rtx *operands)
1362 {
1363 enum machine_mode wmode = mode;
1364 rtx dst = operands[0];
1365 rtx src1 = operands[1];
1366 rtx src2 = operands[2];
1367 rtx op, clob, tem;
1368
1369 /* If we cannot handle the operation directly, use a temp register. */
1370 if (!s390_logical_operator_ok_p (operands))
1371 dst = gen_reg_rtx (mode);
1372
1373 /* QImode and HImode patterns make sense only if we have a destination
1374 in memory. Otherwise perform the operation in SImode. */
1375 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1376 wmode = SImode;
1377
1378 /* Widen operands if required. */
1379 if (mode != wmode)
1380 {
1381 if (GET_CODE (dst) == SUBREG
1382 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1383 dst = tem;
1384 else if (REG_P (dst))
1385 dst = gen_rtx_SUBREG (wmode, dst, 0);
1386 else
1387 dst = gen_reg_rtx (wmode);
1388
1389 if (GET_CODE (src1) == SUBREG
1390 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1391 src1 = tem;
1392 else if (GET_MODE (src1) != VOIDmode)
1393 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1394
1395 if (GET_CODE (src2) == SUBREG
1396 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1397 src2 = tem;
1398 else if (GET_MODE (src2) != VOIDmode)
1399 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1400 }
1401
1402 /* Emit the instruction. */
1403 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1404 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1405 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1406
1407 /* Fix up the destination if needed. */
1408 if (dst != operands[0])
1409 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1410 }
1411
1412 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1413
1414 bool
1415 s390_logical_operator_ok_p (rtx *operands)
1416 {
1417 /* If the destination operand is in memory, it needs to coincide
1418 with one of the source operands. After reload, it has to be
1419 the first source operand. */
1420 if (GET_CODE (operands[0]) == MEM)
1421 return rtx_equal_p (operands[0], operands[1])
1422 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1423
1424 return true;
1425 }
1426
1427 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1428 operand IMMOP to switch from SS to SI type instructions. */
1429
1430 void
1431 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1432 {
1433 int def = code == AND ? -1 : 0;
1434 HOST_WIDE_INT mask;
1435 int part;
1436
1437 gcc_assert (GET_CODE (*memop) == MEM);
1438 gcc_assert (!MEM_VOLATILE_P (*memop));
1439
1440 mask = s390_extract_part (*immop, QImode, def);
1441 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1442 gcc_assert (part >= 0);
1443
1444 *memop = adjust_address (*memop, QImode, part);
1445 *immop = gen_int_mode (mask, QImode);
1446 }
1447
1448
1449 /* How to allocate a 'struct machine_function'. */
1450
1451 static struct machine_function *
1452 s390_init_machine_status (void)
1453 {
1454 return GGC_CNEW (struct machine_function);
1455 }
1456
1457 /* Change optimizations to be performed, depending on the
1458 optimization level.
1459
1460 LEVEL is the optimization level specified; 2 if `-O2' is
1461 specified, 1 if `-O' is specified, and 0 if neither is specified.
1462
1463 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1464
1465 void
1466 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1467 {
1468 /* ??? There are apparently still problems with -fcaller-saves. */
1469 flag_caller_saves = 0;
1470
1471 /* By default, always emit DWARF-2 unwind info. This allows debugging
1472 without maintaining a stack frame back-chain. */
1473 flag_asynchronous_unwind_tables = 1;
1474
1475 /* Use MVCLE instructions to decrease code size if requested. */
1476 if (size != 0)
1477 target_flags |= MASK_MVCLE;
1478 }
1479
1480 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1481 to the associated processor_type and processor_flags if so. */
1482
1483 static bool
1484 s390_handle_arch_option (const char *arg,
1485 enum processor_type *type,
1486 enum processor_flags *flags)
1487 {
1488 static struct pta
1489 {
1490 const char *const name; /* processor name or nickname. */
1491 const enum processor_type processor;
1492 const enum processor_flags flags;
1493 }
1494 const processor_alias_table[] =
1495 {
1496 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1497 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1498 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1499 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1500 | PF_LONG_DISPLACEMENT},
1501 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1502 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1503 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1504 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1505 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1506 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1507 };
1508 size_t i;
1509
1510 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1511 if (strcmp (arg, processor_alias_table[i].name) == 0)
1512 {
1513 *type = processor_alias_table[i].processor;
1514 *flags = processor_alias_table[i].flags;
1515 return true;
1516 }
1517 return false;
1518 }
1519
1520 /* Implement TARGET_HANDLE_OPTION. */
1521
1522 static bool
1523 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1524 {
1525 switch (code)
1526 {
1527 case OPT_march_:
1528 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1529
1530 case OPT_mstack_guard_:
1531 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1532 return false;
1533 if (exact_log2 (s390_stack_guard) == -1)
1534 error ("stack guard value must be an exact power of 2");
1535 return true;
1536
1537 case OPT_mstack_size_:
1538 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1539 return false;
1540 if (exact_log2 (s390_stack_size) == -1)
1541 error ("stack size must be an exact power of 2");
1542 return true;
1543
1544 case OPT_mtune_:
1545 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1546
1547 case OPT_mwarn_framesize_:
1548 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1549
1550 default:
1551 return true;
1552 }
1553 }
1554
1555 void
1556 override_options (void)
1557 {
1558 /* Set up function hooks. */
1559 init_machine_status = s390_init_machine_status;
1560
1561 /* Architecture mode defaults according to ABI. */
1562 if (!(target_flags_explicit & MASK_ZARCH))
1563 {
1564 if (TARGET_64BIT)
1565 target_flags |= MASK_ZARCH;
1566 else
1567 target_flags &= ~MASK_ZARCH;
1568 }
1569
1570 /* Determine processor architectural level. */
1571 if (!s390_arch_string)
1572 {
1573 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1574 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1575 }
1576
1577 /* Determine processor to tune for. */
1578 if (s390_tune == PROCESSOR_max)
1579 {
1580 s390_tune = s390_arch;
1581 s390_tune_flags = s390_arch_flags;
1582 }
1583
1584 /* Sanity checks. */
1585 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1586 error ("z/Architecture mode not supported on %s", s390_arch_string);
1587 if (TARGET_64BIT && !TARGET_ZARCH)
1588 error ("64-bit ABI not supported in ESA/390 mode");
1589
1590 if (TARGET_HARD_DFP && !TARGET_DFP)
1591 {
1592 if (target_flags_explicit & MASK_HARD_DFP)
1593 {
1594 if (!TARGET_CPU_DFP)
1595 error ("Hardware decimal floating point instructions"
1596 " not available on %s", s390_arch_string);
1597 if (!TARGET_ZARCH)
1598 error ("Hardware decimal floating point instructions"
1599 " not available in ESA/390 mode");
1600 }
1601 else
1602 target_flags &= ~MASK_HARD_DFP;
1603 }
1604
1605 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1606 {
1607 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1608 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1609
1610 target_flags &= ~MASK_HARD_DFP;
1611 }
1612
1613 /* Set processor cost function. */
1614 switch (s390_tune)
1615 {
1616 case PROCESSOR_2084_Z990:
1617 s390_cost = &z990_cost;
1618 break;
1619 case PROCESSOR_2094_Z9_109:
1620 s390_cost = &z9_109_cost;
1621 break;
1622 case PROCESSOR_2097_Z10:
1623 s390_cost = &z10_cost;
1624 break;
1625 default:
1626 s390_cost = &z900_cost;
1627 }
1628
1629 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1630 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1631 "in combination");
1632
1633 if (s390_stack_size)
1634 {
1635 if (s390_stack_guard >= s390_stack_size)
1636 error ("stack size must be greater than the stack guard value");
1637 else if (s390_stack_size > 1 << 16)
1638 error ("stack size must not be greater than 64k");
1639 }
1640 else if (s390_stack_guard)
1641 error ("-mstack-guard implies use of -mstack-size");
1642
1643 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1644 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1645 target_flags |= MASK_LONG_DOUBLE_128;
1646 #endif
1647 }
1648
1649 /* Map for smallest class containing reg regno. */
1650
1651 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1652 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1653 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1654 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1655 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1658 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1659 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1660 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1661 ACCESS_REGS, ACCESS_REGS
1662 };
1663
1664 /* Return attribute type of insn. */
1665
1666 static enum attr_type
1667 s390_safe_attr_type (rtx insn)
1668 {
1669 if (recog_memoized (insn) >= 0)
1670 return get_attr_type (insn);
1671 else
1672 return TYPE_NONE;
1673 }
1674
1675 /* Return true if DISP is a valid short displacement. */
1676
1677 static bool
1678 s390_short_displacement (rtx disp)
1679 {
1680 /* No displacement is OK. */
1681 if (!disp)
1682 return true;
1683
1684 /* Integer displacement in range. */
1685 if (GET_CODE (disp) == CONST_INT)
1686 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1687
1688 /* GOT offset is not OK, the GOT can be large. */
1689 if (GET_CODE (disp) == CONST
1690 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1691 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1692 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1693 return false;
1694
1695 /* All other symbolic constants are literal pool references,
1696 which are OK as the literal pool must be small. */
1697 if (GET_CODE (disp) == CONST)
1698 return true;
1699
1700 return false;
1701 }
1702
1703 /* Decompose a RTL expression ADDR for a memory address into
1704 its components, returned in OUT.
1705
1706 Returns false if ADDR is not a valid memory address, true
1707 otherwise. If OUT is NULL, don't return the components,
1708 but check for validity only.
1709
1710 Note: Only addresses in canonical form are recognized.
1711 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1712 canonical form so that they will be recognized. */
1713
1714 static int
1715 s390_decompose_address (rtx addr, struct s390_address *out)
1716 {
1717 HOST_WIDE_INT offset = 0;
1718 rtx base = NULL_RTX;
1719 rtx indx = NULL_RTX;
1720 rtx disp = NULL_RTX;
1721 rtx orig_disp;
1722 bool pointer = false;
1723 bool base_ptr = false;
1724 bool indx_ptr = false;
1725 bool literal_pool = false;
1726
1727 /* We may need to substitute the literal pool base register into the address
1728 below. However, at this point we do not know which register is going to
1729 be used as base, so we substitute the arg pointer register. This is going
1730 to be treated as holding a pointer below -- it shouldn't be used for any
1731 other purpose. */
1732 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1733
1734 /* Decompose address into base + index + displacement. */
1735
1736 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1737 base = addr;
1738
1739 else if (GET_CODE (addr) == PLUS)
1740 {
1741 rtx op0 = XEXP (addr, 0);
1742 rtx op1 = XEXP (addr, 1);
1743 enum rtx_code code0 = GET_CODE (op0);
1744 enum rtx_code code1 = GET_CODE (op1);
1745
1746 if (code0 == REG || code0 == UNSPEC)
1747 {
1748 if (code1 == REG || code1 == UNSPEC)
1749 {
1750 indx = op0; /* index + base */
1751 base = op1;
1752 }
1753
1754 else
1755 {
1756 base = op0; /* base + displacement */
1757 disp = op1;
1758 }
1759 }
1760
1761 else if (code0 == PLUS)
1762 {
1763 indx = XEXP (op0, 0); /* index + base + disp */
1764 base = XEXP (op0, 1);
1765 disp = op1;
1766 }
1767
1768 else
1769 {
1770 return false;
1771 }
1772 }
1773
1774 else
1775 disp = addr; /* displacement */
1776
1777 /* Extract integer part of displacement. */
1778 orig_disp = disp;
1779 if (disp)
1780 {
1781 if (GET_CODE (disp) == CONST_INT)
1782 {
1783 offset = INTVAL (disp);
1784 disp = NULL_RTX;
1785 }
1786 else if (GET_CODE (disp) == CONST
1787 && GET_CODE (XEXP (disp, 0)) == PLUS
1788 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1789 {
1790 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1791 disp = XEXP (XEXP (disp, 0), 0);
1792 }
1793 }
1794
1795 /* Strip off CONST here to avoid special case tests later. */
1796 if (disp && GET_CODE (disp) == CONST)
1797 disp = XEXP (disp, 0);
1798
1799 /* We can convert literal pool addresses to
1800 displacements by basing them off the base register. */
1801 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1802 {
1803 /* Either base or index must be free to hold the base register. */
1804 if (!base)
1805 base = fake_pool_base, literal_pool = true;
1806 else if (!indx)
1807 indx = fake_pool_base, literal_pool = true;
1808 else
1809 return false;
1810
1811 /* Mark up the displacement. */
1812 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1813 UNSPEC_LTREL_OFFSET);
1814 }
1815
1816 /* Validate base register. */
1817 if (base)
1818 {
1819 if (GET_CODE (base) == UNSPEC)
1820 switch (XINT (base, 1))
1821 {
1822 case UNSPEC_LTREF:
1823 if (!disp)
1824 disp = gen_rtx_UNSPEC (Pmode,
1825 gen_rtvec (1, XVECEXP (base, 0, 0)),
1826 UNSPEC_LTREL_OFFSET);
1827 else
1828 return false;
1829
1830 base = XVECEXP (base, 0, 1);
1831 break;
1832
1833 case UNSPEC_LTREL_BASE:
1834 if (XVECLEN (base, 0) == 1)
1835 base = fake_pool_base, literal_pool = true;
1836 else
1837 base = XVECEXP (base, 0, 1);
1838 break;
1839
1840 default:
1841 return false;
1842 }
1843
1844 if (!REG_P (base)
1845 || (GET_MODE (base) != SImode
1846 && GET_MODE (base) != Pmode))
1847 return false;
1848
1849 if (REGNO (base) == STACK_POINTER_REGNUM
1850 || REGNO (base) == FRAME_POINTER_REGNUM
1851 || ((reload_completed || reload_in_progress)
1852 && frame_pointer_needed
1853 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1854 || REGNO (base) == ARG_POINTER_REGNUM
1855 || (flag_pic
1856 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1857 pointer = base_ptr = true;
1858
1859 if ((reload_completed || reload_in_progress)
1860 && base == cfun->machine->base_reg)
1861 pointer = base_ptr = literal_pool = true;
1862 }
1863
1864 /* Validate index register. */
1865 if (indx)
1866 {
1867 if (GET_CODE (indx) == UNSPEC)
1868 switch (XINT (indx, 1))
1869 {
1870 case UNSPEC_LTREF:
1871 if (!disp)
1872 disp = gen_rtx_UNSPEC (Pmode,
1873 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1874 UNSPEC_LTREL_OFFSET);
1875 else
1876 return false;
1877
1878 indx = XVECEXP (indx, 0, 1);
1879 break;
1880
1881 case UNSPEC_LTREL_BASE:
1882 if (XVECLEN (indx, 0) == 1)
1883 indx = fake_pool_base, literal_pool = true;
1884 else
1885 indx = XVECEXP (indx, 0, 1);
1886 break;
1887
1888 default:
1889 return false;
1890 }
1891
1892 if (!REG_P (indx)
1893 || (GET_MODE (indx) != SImode
1894 && GET_MODE (indx) != Pmode))
1895 return false;
1896
1897 if (REGNO (indx) == STACK_POINTER_REGNUM
1898 || REGNO (indx) == FRAME_POINTER_REGNUM
1899 || ((reload_completed || reload_in_progress)
1900 && frame_pointer_needed
1901 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1902 || REGNO (indx) == ARG_POINTER_REGNUM
1903 || (flag_pic
1904 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1905 pointer = indx_ptr = true;
1906
1907 if ((reload_completed || reload_in_progress)
1908 && indx == cfun->machine->base_reg)
1909 pointer = indx_ptr = literal_pool = true;
1910 }
1911
1912 /* Prefer to use pointer as base, not index. */
1913 if (base && indx && !base_ptr
1914 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1915 {
1916 rtx tmp = base;
1917 base = indx;
1918 indx = tmp;
1919 }
1920
1921 /* Validate displacement. */
1922 if (!disp)
1923 {
1924 /* If virtual registers are involved, the displacement will change later
1925 anyway as the virtual registers get eliminated. This could make a
1926 valid displacement invalid, but it is more likely to make an invalid
1927 displacement valid, because we sometimes access the register save area
1928 via negative offsets to one of those registers.
1929 Thus we don't check the displacement for validity here. If after
1930 elimination the displacement turns out to be invalid after all,
1931 this is fixed up by reload in any case. */
1932 if (base != arg_pointer_rtx
1933 && indx != arg_pointer_rtx
1934 && base != return_address_pointer_rtx
1935 && indx != return_address_pointer_rtx
1936 && base != frame_pointer_rtx
1937 && indx != frame_pointer_rtx
1938 && base != virtual_stack_vars_rtx
1939 && indx != virtual_stack_vars_rtx)
1940 if (!DISP_IN_RANGE (offset))
1941 return false;
1942 }
1943 else
1944 {
1945 /* All the special cases are pointers. */
1946 pointer = true;
1947
1948 /* In the small-PIC case, the linker converts @GOT
1949 and @GOTNTPOFF offsets to possible displacements. */
1950 if (GET_CODE (disp) == UNSPEC
1951 && (XINT (disp, 1) == UNSPEC_GOT
1952 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1953 && flag_pic == 1)
1954 {
1955 ;
1956 }
1957
1958 /* Accept chunkified literal pool symbol references. */
1959 else if (cfun && cfun->machine
1960 && cfun->machine->decomposed_literal_pool_addresses_ok_p
1961 && GET_CODE (disp) == MINUS
1962 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1963 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1964 {
1965 ;
1966 }
1967
1968 /* Accept literal pool references. */
1969 else if (GET_CODE (disp) == UNSPEC
1970 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1971 {
1972 orig_disp = gen_rtx_CONST (Pmode, disp);
1973 if (offset)
1974 {
1975 /* If we have an offset, make sure it does not
1976 exceed the size of the constant pool entry. */
1977 rtx sym = XVECEXP (disp, 0, 0);
1978 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1979 return false;
1980
1981 orig_disp = plus_constant (orig_disp, offset);
1982 }
1983 }
1984
1985 else
1986 return false;
1987 }
1988
1989 if (!base && !indx)
1990 pointer = true;
1991
1992 if (out)
1993 {
1994 out->base = base;
1995 out->indx = indx;
1996 out->disp = orig_disp;
1997 out->pointer = pointer;
1998 out->literal_pool = literal_pool;
1999 }
2000
2001 return true;
2002 }
2003
2004 /* Decompose a RTL expression OP for a shift count into its components,
2005 and return the base register in BASE and the offset in OFFSET.
2006
2007 Return true if OP is a valid shift count, false if not. */
2008
2009 bool
2010 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2011 {
2012 HOST_WIDE_INT off = 0;
2013
2014 /* We can have an integer constant, an address register,
2015 or a sum of the two. */
2016 if (GET_CODE (op) == CONST_INT)
2017 {
2018 off = INTVAL (op);
2019 op = NULL_RTX;
2020 }
2021 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2022 {
2023 off = INTVAL (XEXP (op, 1));
2024 op = XEXP (op, 0);
2025 }
2026 while (op && GET_CODE (op) == SUBREG)
2027 op = SUBREG_REG (op);
2028
2029 if (op && GET_CODE (op) != REG)
2030 return false;
2031
2032 if (offset)
2033 *offset = off;
2034 if (base)
2035 *base = op;
2036
2037 return true;
2038 }
2039
2040
2041 /* Return true if CODE is a valid address without index. */
2042
2043 bool
2044 s390_legitimate_address_without_index_p (rtx op)
2045 {
2046 struct s390_address addr;
2047
2048 if (!s390_decompose_address (XEXP (op, 0), &addr))
2049 return false;
2050 if (addr.indx)
2051 return false;
2052
2053 return true;
2054 }
2055
2056
2057 /* Evaluates constraint strings described by the regular expression
2058 ([A|B](Q|R|S|T))|U|W and returns 1 if OP is a valid operand for the
2059 constraint given in STR, or 0 else. */
2060
2061 int
2062 s390_mem_constraint (const char *str, rtx op)
2063 {
2064 struct s390_address addr;
2065 char c = str[0];
2066
2067 /* Check for offsettable variants of memory constraints. */
2068 if (c == 'A')
2069 {
2070 /* Only accept non-volatile MEMs. */
2071 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2072 return 0;
2073
2074 if ((reload_completed || reload_in_progress)
2075 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2076 return 0;
2077
2078 c = str[1];
2079 }
2080
2081 /* Check for non-literal-pool variants of memory constraints. */
2082 else if (c == 'B')
2083 {
2084 if (GET_CODE (op) != MEM)
2085 return 0;
2086 if (!s390_decompose_address (XEXP (op, 0), &addr))
2087 return 0;
2088 if (addr.literal_pool)
2089 return 0;
2090
2091 c = str[1];
2092 }
2093
2094 switch (c)
2095 {
2096 case 'Q':
2097 if (GET_CODE (op) != MEM)
2098 return 0;
2099 if (!s390_decompose_address (XEXP (op, 0), &addr))
2100 return 0;
2101 if (addr.indx)
2102 return 0;
2103
2104 if (TARGET_LONG_DISPLACEMENT)
2105 {
2106 if (!s390_short_displacement (addr.disp))
2107 return 0;
2108 }
2109 break;
2110
2111 case 'R':
2112 if (GET_CODE (op) != MEM)
2113 return 0;
2114
2115 if (TARGET_LONG_DISPLACEMENT)
2116 {
2117 if (!s390_decompose_address (XEXP (op, 0), &addr))
2118 return 0;
2119 if (!s390_short_displacement (addr.disp))
2120 return 0;
2121 }
2122 break;
2123
2124 case 'S':
2125 if (!TARGET_LONG_DISPLACEMENT)
2126 return 0;
2127 if (GET_CODE (op) != MEM)
2128 return 0;
2129 if (!s390_decompose_address (XEXP (op, 0), &addr))
2130 return 0;
2131 if (addr.indx)
2132 return 0;
2133 if (s390_short_displacement (addr.disp))
2134 return 0;
2135 break;
2136
2137 case 'T':
2138 if (!TARGET_LONG_DISPLACEMENT)
2139 return 0;
2140 if (GET_CODE (op) != MEM)
2141 return 0;
2142 if (!s390_decompose_address (XEXP (op, 0), &addr))
2143 return 0;
2144 if (s390_short_displacement (addr.disp))
2145 return 0;
2146 break;
2147
2148 case 'U':
2149 if (TARGET_LONG_DISPLACEMENT)
2150 {
2151 if (!s390_decompose_address (op, &addr))
2152 return 0;
2153 if (!s390_short_displacement (addr.disp))
2154 return 0;
2155 }
2156 break;
2157
2158 case 'W':
2159 if (!TARGET_LONG_DISPLACEMENT)
2160 return 0;
2161 if (!s390_decompose_address (op, &addr))
2162 return 0;
2163 if (s390_short_displacement (addr.disp))
2164 return 0;
2165 break;
2166
2167 case 'Y':
2168 /* Simply check for the basic form of a shift count. Reload will
2169 take care of making sure we have a proper base register. */
2170 if (!s390_decompose_shift_count (op, NULL, NULL))
2171 return 0;
2172 break;
2173
2174 default:
2175 return 0;
2176 }
2177
2178 return 1;
2179 }
2180
2181
2182
2183 /* Evaluates constraint strings starting with letter O. Input
2184 parameter C is the second letter following the "O" in the constraint
2185 string. Returns 1 if VALUE meets the respective constraint and 0
2186 otherwise. */
2187
2188 int
2189 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2190 {
2191 if (!TARGET_EXTIMM)
2192 return 0;
2193
2194 switch (c)
2195 {
2196 case 's':
2197 return trunc_int_for_mode (value, SImode) == value;
2198
2199 case 'p':
2200 return value == 0
2201 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2202
2203 case 'n':
2204 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2205
2206 default:
2207 gcc_unreachable ();
2208 }
2209 }
2210
2211
2212 /* Evaluates constraint strings starting with letter N. Parameter STR
2213 contains the letters following letter "N" in the constraint string.
2214 Returns true if VALUE matches the constraint. */
2215
2216 int
2217 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2218 {
2219 enum machine_mode mode, part_mode;
2220 int def;
2221 int part, part_goal;
2222
2223
2224 if (str[0] == 'x')
2225 part_goal = -1;
2226 else
2227 part_goal = str[0] - '0';
2228
2229 switch (str[1])
2230 {
2231 case 'Q':
2232 part_mode = QImode;
2233 break;
2234 case 'H':
2235 part_mode = HImode;
2236 break;
2237 case 'S':
2238 part_mode = SImode;
2239 break;
2240 default:
2241 return 0;
2242 }
2243
2244 switch (str[2])
2245 {
2246 case 'H':
2247 mode = HImode;
2248 break;
2249 case 'S':
2250 mode = SImode;
2251 break;
2252 case 'D':
2253 mode = DImode;
2254 break;
2255 default:
2256 return 0;
2257 }
2258
2259 switch (str[3])
2260 {
2261 case '0':
2262 def = 0;
2263 break;
2264 case 'F':
2265 def = -1;
2266 break;
2267 default:
2268 return 0;
2269 }
2270
2271 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2272 return 0;
2273
2274 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2275 if (part < 0)
2276 return 0;
2277 if (part_goal != -1 && part_goal != part)
2278 return 0;
2279
2280 return 1;
2281 }
2282
2283
2284 /* Returns true if the input parameter VALUE is a float zero. */
2285
2286 int
2287 s390_float_const_zero_p (rtx value)
2288 {
2289 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2290 && value == CONST0_RTX (GET_MODE (value)));
2291 }
2292
2293
2294 /* Compute a (partial) cost for rtx X. Return true if the complete
2295 cost has been computed, and false if subexpressions should be
2296 scanned. In either case, *TOTAL contains the cost result.
2297 CODE contains GET_CODE (x), OUTER_CODE contains the code
2298 of the superexpression of x. */
2299
2300 static bool
2301 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2302 bool speed ATTRIBUTE_UNUSED)
2303 {
2304 switch (code)
2305 {
2306 case CONST:
2307 case CONST_INT:
2308 case LABEL_REF:
2309 case SYMBOL_REF:
2310 case CONST_DOUBLE:
2311 case MEM:
2312 *total = 0;
2313 return true;
2314
2315 case ASHIFT:
2316 case ASHIFTRT:
2317 case LSHIFTRT:
2318 case ROTATE:
2319 case ROTATERT:
2320 case AND:
2321 case IOR:
2322 case XOR:
2323 case NEG:
2324 case NOT:
2325 *total = COSTS_N_INSNS (1);
2326 return false;
2327
2328 case PLUS:
2329 case MINUS:
2330 /* Check for multiply and add. */
2331 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2332 && GET_CODE (XEXP (x, 0)) == MULT
2333 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2334 {
2335 /* This is the multiply and add case. */
2336 if (GET_MODE (x) == DFmode)
2337 *total = s390_cost->madbr;
2338 else
2339 *total = s390_cost->maebr;
2340 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2341 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2342 + rtx_cost (XEXP (x, 1), code, speed);
2343 return true; /* Do not do an additional recursive descent. */
2344 }
2345 *total = COSTS_N_INSNS (1);
2346 return false;
2347
2348 case MULT:
2349 switch (GET_MODE (x))
2350 {
2351 case SImode:
2352 {
2353 rtx left = XEXP (x, 0);
2354 rtx right = XEXP (x, 1);
2355 if (GET_CODE (right) == CONST_INT
2356 && CONST_OK_FOR_K (INTVAL (right)))
2357 *total = s390_cost->mhi;
2358 else if (GET_CODE (left) == SIGN_EXTEND)
2359 *total = s390_cost->mh;
2360 else
2361 *total = s390_cost->ms; /* msr, ms, msy */
2362 break;
2363 }
2364 case DImode:
2365 {
2366 rtx left = XEXP (x, 0);
2367 rtx right = XEXP (x, 1);
2368 if (TARGET_64BIT)
2369 {
2370 if (GET_CODE (right) == CONST_INT
2371 && CONST_OK_FOR_K (INTVAL (right)))
2372 *total = s390_cost->mghi;
2373 else if (GET_CODE (left) == SIGN_EXTEND)
2374 *total = s390_cost->msgf;
2375 else
2376 *total = s390_cost->msg; /* msgr, msg */
2377 }
2378 else /* TARGET_31BIT */
2379 {
2380 if (GET_CODE (left) == SIGN_EXTEND
2381 && GET_CODE (right) == SIGN_EXTEND)
2382 /* mulsidi case: mr, m */
2383 *total = s390_cost->m;
2384 else if (GET_CODE (left) == ZERO_EXTEND
2385 && GET_CODE (right) == ZERO_EXTEND
2386 && TARGET_CPU_ZARCH)
2387 /* umulsidi case: ml, mlr */
2388 *total = s390_cost->ml;
2389 else
2390 /* Complex calculation is required. */
2391 *total = COSTS_N_INSNS (40);
2392 }
2393 break;
2394 }
2395 case SFmode:
2396 case DFmode:
2397 *total = s390_cost->mult_df;
2398 break;
2399 case TFmode:
2400 *total = s390_cost->mxbr;
2401 break;
2402 default:
2403 return false;
2404 }
2405 return false;
2406
2407 case UDIV:
2408 case UMOD:
2409 if (GET_MODE (x) == TImode) /* 128 bit division */
2410 *total = s390_cost->dlgr;
2411 else if (GET_MODE (x) == DImode)
2412 {
2413 rtx right = XEXP (x, 1);
2414 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2415 *total = s390_cost->dlr;
2416 else /* 64 by 64 bit division */
2417 *total = s390_cost->dlgr;
2418 }
2419 else if (GET_MODE (x) == SImode) /* 32 bit division */
2420 *total = s390_cost->dlr;
2421 return false;
2422
2423 case DIV:
2424 case MOD:
2425 if (GET_MODE (x) == DImode)
2426 {
2427 rtx right = XEXP (x, 1);
2428 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2429 if (TARGET_64BIT)
2430 *total = s390_cost->dsgfr;
2431 else
2432 *total = s390_cost->dr;
2433 else /* 64 by 64 bit division */
2434 *total = s390_cost->dsgr;
2435 }
2436 else if (GET_MODE (x) == SImode) /* 32 bit division */
2437 *total = s390_cost->dlr;
2438 else if (GET_MODE (x) == SFmode)
2439 {
2440 *total = s390_cost->debr;
2441 }
2442 else if (GET_MODE (x) == DFmode)
2443 {
2444 *total = s390_cost->ddbr;
2445 }
2446 else if (GET_MODE (x) == TFmode)
2447 {
2448 *total = s390_cost->dxbr;
2449 }
2450 return false;
2451
2452 case SQRT:
2453 if (GET_MODE (x) == SFmode)
2454 *total = s390_cost->sqebr;
2455 else if (GET_MODE (x) == DFmode)
2456 *total = s390_cost->sqdbr;
2457 else /* TFmode */
2458 *total = s390_cost->sqxbr;
2459 return false;
2460
2461 case SIGN_EXTEND:
2462 case ZERO_EXTEND:
2463 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2464 || outer_code == PLUS || outer_code == MINUS
2465 || outer_code == COMPARE)
2466 *total = 0;
2467 return false;
2468
2469 case COMPARE:
2470 *total = COSTS_N_INSNS (1);
2471 if (GET_CODE (XEXP (x, 0)) == AND
2472 && GET_CODE (XEXP (x, 1)) == CONST_INT
2473 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2474 {
2475 rtx op0 = XEXP (XEXP (x, 0), 0);
2476 rtx op1 = XEXP (XEXP (x, 0), 1);
2477 rtx op2 = XEXP (x, 1);
2478
2479 if (memory_operand (op0, GET_MODE (op0))
2480 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2481 return true;
2482 if (register_operand (op0, GET_MODE (op0))
2483 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2484 return true;
2485 }
2486 return false;
2487
2488 default:
2489 return false;
2490 }
2491 }
2492
2493 /* Return the cost of an address rtx ADDR. */
2494
2495 static int
2496 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2497 {
2498 struct s390_address ad;
2499 if (!s390_decompose_address (addr, &ad))
2500 return 1000;
2501
2502 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2503 }
2504
2505 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2506 otherwise return 0. */
2507
2508 int
2509 tls_symbolic_operand (rtx op)
2510 {
2511 if (GET_CODE (op) != SYMBOL_REF)
2512 return 0;
2513 return SYMBOL_REF_TLS_MODEL (op);
2514 }
2515 \f
2516 /* Split DImode access register reference REG (on 64-bit) into its constituent
2517 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2518 gen_highpart cannot be used as they assume all registers are word-sized,
2519 while our access registers have only half that size. */
2520
2521 void
2522 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2523 {
2524 gcc_assert (TARGET_64BIT);
2525 gcc_assert (ACCESS_REG_P (reg));
2526 gcc_assert (GET_MODE (reg) == DImode);
2527 gcc_assert (!(REGNO (reg) & 1));
2528
2529 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2530 *hi = gen_rtx_REG (SImode, REGNO (reg));
2531 }
2532
2533 /* Return true if OP contains a symbol reference */
2534
2535 bool
2536 symbolic_reference_mentioned_p (rtx op)
2537 {
2538 const char *fmt;
2539 int i;
2540
2541 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2542 return 1;
2543
2544 fmt = GET_RTX_FORMAT (GET_CODE (op));
2545 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2546 {
2547 if (fmt[i] == 'E')
2548 {
2549 int j;
2550
2551 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2552 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2553 return 1;
2554 }
2555
2556 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2557 return 1;
2558 }
2559
2560 return 0;
2561 }
2562
2563 /* Return true if OP contains a reference to a thread-local symbol. */
2564
2565 bool
2566 tls_symbolic_reference_mentioned_p (rtx op)
2567 {
2568 const char *fmt;
2569 int i;
2570
2571 if (GET_CODE (op) == SYMBOL_REF)
2572 return tls_symbolic_operand (op);
2573
2574 fmt = GET_RTX_FORMAT (GET_CODE (op));
2575 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2576 {
2577 if (fmt[i] == 'E')
2578 {
2579 int j;
2580
2581 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2582 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2583 return true;
2584 }
2585
2586 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2587 return true;
2588 }
2589
2590 return false;
2591 }
2592
2593
2594 /* Return true if OP is a legitimate general operand when
2595 generating PIC code. It is given that flag_pic is on
2596 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2597
2598 int
2599 legitimate_pic_operand_p (rtx op)
2600 {
2601 /* Accept all non-symbolic constants. */
2602 if (!SYMBOLIC_CONST (op))
2603 return 1;
2604
2605 /* Reject everything else; must be handled
2606 via emit_symbolic_move. */
2607 return 0;
2608 }
2609
2610 /* Returns true if the constant value OP is a legitimate general operand.
2611 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2612
2613 int
2614 legitimate_constant_p (rtx op)
2615 {
2616 /* Accept all non-symbolic constants. */
2617 if (!SYMBOLIC_CONST (op))
2618 return 1;
2619
2620 /* Accept immediate LARL operands. */
2621 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2622 return 1;
2623
2624 /* Thread-local symbols are never legal constants. This is
2625 so that emit_call knows that computing such addresses
2626 might require a function call. */
2627 if (TLS_SYMBOLIC_CONST (op))
2628 return 0;
2629
2630 /* In the PIC case, symbolic constants must *not* be
2631 forced into the literal pool. We accept them here,
2632 so that they will be handled by emit_symbolic_move. */
2633 if (flag_pic)
2634 return 1;
2635
2636 /* All remaining non-PIC symbolic constants are
2637 forced into the literal pool. */
2638 return 0;
2639 }
2640
2641 /* Determine if it's legal to put X into the constant pool. This
2642 is not possible if X contains the address of a symbol that is
2643 not constant (TLS) or not known at final link time (PIC). */
2644
2645 static bool
2646 s390_cannot_force_const_mem (rtx x)
2647 {
2648 switch (GET_CODE (x))
2649 {
2650 case CONST_INT:
2651 case CONST_DOUBLE:
2652 /* Accept all non-symbolic constants. */
2653 return false;
2654
2655 case LABEL_REF:
2656 /* Labels are OK iff we are non-PIC. */
2657 return flag_pic != 0;
2658
2659 case SYMBOL_REF:
2660 /* 'Naked' TLS symbol references are never OK,
2661 non-TLS symbols are OK iff we are non-PIC. */
2662 if (tls_symbolic_operand (x))
2663 return true;
2664 else
2665 return flag_pic != 0;
2666
2667 case CONST:
2668 return s390_cannot_force_const_mem (XEXP (x, 0));
2669 case PLUS:
2670 case MINUS:
2671 return s390_cannot_force_const_mem (XEXP (x, 0))
2672 || s390_cannot_force_const_mem (XEXP (x, 1));
2673
2674 case UNSPEC:
2675 switch (XINT (x, 1))
2676 {
2677 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2678 case UNSPEC_LTREL_OFFSET:
2679 case UNSPEC_GOT:
2680 case UNSPEC_GOTOFF:
2681 case UNSPEC_PLTOFF:
2682 case UNSPEC_TLSGD:
2683 case UNSPEC_TLSLDM:
2684 case UNSPEC_NTPOFF:
2685 case UNSPEC_DTPOFF:
2686 case UNSPEC_GOTNTPOFF:
2687 case UNSPEC_INDNTPOFF:
2688 return false;
2689
2690 /* If the literal pool shares the code section, be put
2691 execute template placeholders into the pool as well. */
2692 case UNSPEC_INSN:
2693 return TARGET_CPU_ZARCH;
2694
2695 default:
2696 return true;
2697 }
2698 break;
2699
2700 default:
2701 gcc_unreachable ();
2702 }
2703 }
2704
2705 /* Returns true if the constant value OP is a legitimate general
2706 operand during and after reload. The difference to
2707 legitimate_constant_p is that this function will not accept
2708 a constant that would need to be forced to the literal pool
2709 before it can be used as operand. */
2710
2711 bool
2712 legitimate_reload_constant_p (rtx op)
2713 {
2714 /* Accept la(y) operands. */
2715 if (GET_CODE (op) == CONST_INT
2716 && DISP_IN_RANGE (INTVAL (op)))
2717 return true;
2718
2719 /* Accept l(g)hi/l(g)fi operands. */
2720 if (GET_CODE (op) == CONST_INT
2721 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2722 return true;
2723
2724 /* Accept lliXX operands. */
2725 if (TARGET_ZARCH
2726 && GET_CODE (op) == CONST_INT
2727 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2728 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2729 return true;
2730
2731 if (TARGET_EXTIMM
2732 && GET_CODE (op) == CONST_INT
2733 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2734 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2735 return true;
2736
2737 /* Accept larl operands. */
2738 if (TARGET_CPU_ZARCH
2739 && larl_operand (op, VOIDmode))
2740 return true;
2741
2742 /* Accept lzXX operands. */
2743 if (GET_CODE (op) == CONST_DOUBLE
2744 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2745 return true;
2746
2747 /* Accept double-word operands that can be split. */
2748 if (GET_CODE (op) == CONST_INT
2749 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2750 {
2751 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2752 rtx hi = operand_subword (op, 0, 0, dword_mode);
2753 rtx lo = operand_subword (op, 1, 0, dword_mode);
2754 return legitimate_reload_constant_p (hi)
2755 && legitimate_reload_constant_p (lo);
2756 }
2757
2758 /* Everything else cannot be handled without reload. */
2759 return false;
2760 }
2761
2762 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2763 return the class of reg to actually use. */
2764
2765 enum reg_class
2766 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2767 {
2768 switch (GET_CODE (op))
2769 {
2770 /* Constants we cannot reload must be forced into the
2771 literal pool. */
2772
2773 case CONST_DOUBLE:
2774 case CONST_INT:
2775 if (legitimate_reload_constant_p (op))
2776 return rclass;
2777 else
2778 return NO_REGS;
2779
2780 /* If a symbolic constant or a PLUS is reloaded,
2781 it is most likely being used as an address, so
2782 prefer ADDR_REGS. If 'class' is not a superset
2783 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2784 case PLUS:
2785 case LABEL_REF:
2786 case SYMBOL_REF:
2787 case CONST:
2788 if (reg_class_subset_p (ADDR_REGS, rclass))
2789 return ADDR_REGS;
2790 else
2791 return NO_REGS;
2792
2793 default:
2794 break;
2795 }
2796
2797 return rclass;
2798 }
2799
2800 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2801 and return these parts in SYMREF and ADDEND. You can pass NULL in
2802 SYMREF and/or ADDEND if you are not interested in these values. */
2803
2804 static bool
2805 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2806 {
2807 HOST_WIDE_INT tmpaddend = 0;
2808
2809 if (GET_CODE (addr) == CONST)
2810 addr = XEXP (addr, 0);
2811
2812 if (GET_CODE (addr) == PLUS)
2813 {
2814 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2815 && CONST_INT_P (XEXP (addr, 1)))
2816 {
2817 tmpaddend = INTVAL (XEXP (addr, 1));
2818 addr = XEXP (addr, 0);
2819 }
2820 else
2821 return false;
2822 }
2823 else
2824 if (GET_CODE (addr) != SYMBOL_REF)
2825 return false;
2826
2827 if (symref)
2828 *symref = addr;
2829 if (addend)
2830 *addend = tmpaddend;
2831
2832 return true;
2833 }
2834
2835 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2836 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2837 aligned. */
2838
2839 bool
2840 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2841 {
2842 HOST_WIDE_INT addend;
2843 rtx symref;
2844
2845 if (!s390_symref_operand_p (addr, &symref, &addend))
2846 return false;
2847
2848 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2849 && !(addend & (alignment - 1)));
2850 }
2851
2852 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2853 operand SCRATCH is used to reload the even part of the address and
2854 adding one. */
2855
2856 void
2857 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2858 {
2859 HOST_WIDE_INT addend;
2860 rtx symref;
2861
2862 if (!s390_symref_operand_p (addr, &symref, &addend))
2863 gcc_unreachable ();
2864
2865 if (!(addend & 1))
2866 /* Easy case. The addend is even so larl will do fine. */
2867 emit_move_insn (reg, addr);
2868 else
2869 {
2870 /* We can leave the scratch register untouched if the target
2871 register is a valid base register. */
2872 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2873 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2874 scratch = reg;
2875
2876 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2877 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2878
2879 if (addend != 1)
2880 emit_move_insn (scratch,
2881 gen_rtx_CONST (Pmode,
2882 gen_rtx_PLUS (Pmode, symref,
2883 GEN_INT (addend - 1))));
2884 else
2885 emit_move_insn (scratch, symref);
2886
2887 /* Increment the address using la in order to avoid clobbering cc. */
2888 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2889 }
2890 }
2891
2892 /* Generate what is necessary to move between REG and MEM using
2893 SCRATCH. The direction is given by TOMEM. */
2894
2895 void
2896 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2897 {
2898 /* Reload might have pulled a constant out of the literal pool.
2899 Force it back in. */
2900 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2901 || GET_CODE (mem) == CONST)
2902 mem = force_const_mem (GET_MODE (reg), mem);
2903
2904 gcc_assert (MEM_P (mem));
2905
2906 /* For a load from memory we can leave the scratch register
2907 untouched if the target register is a valid base register. */
2908 if (!tomem
2909 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2910 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2911 && GET_MODE (reg) == GET_MODE (scratch))
2912 scratch = reg;
2913
2914 /* Load address into scratch register. Since we can't have a
2915 secondary reload for a secondary reload we have to cover the case
2916 where larl would need a secondary reload here as well. */
2917 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2918
2919 /* Now we can use a standard load/store to do the move. */
2920 if (tomem)
2921 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2922 else
2923 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2924 }
2925
2926 /* Inform reload about cases where moving X with a mode MODE to a register in
2927 RCLASS requires an extra scratch or immediate register. Return the class
2928 needed for the immediate register. */
2929
2930 static enum reg_class
2931 s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2932 enum machine_mode mode, secondary_reload_info *sri)
2933 {
2934 /* Intermediate register needed. */
2935 if (reg_classes_intersect_p (CC_REGS, rclass))
2936 return GENERAL_REGS;
2937
2938 if (TARGET_Z10)
2939 {
2940 /* On z10 several optimizer steps may generate larl operands with
2941 an odd addend. */
2942 if (in_p
2943 && s390_symref_operand_p (x, NULL, NULL)
2944 && mode == Pmode
2945 && !s390_check_symref_alignment (x, 2))
2946 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2947 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2948
2949 /* On z10 we need a scratch register when moving QI, TI or floating
2950 point mode values from or to a memory location with a SYMBOL_REF
2951 or if the symref addend of a SI or DI move is not aligned to the
2952 width of the access. */
2953 if (MEM_P (x)
2954 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2955 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2956 || (!TARGET_64BIT && mode == DImode)
2957 || ((mode == HImode || mode == SImode || mode == DImode)
2958 && (!s390_check_symref_alignment (XEXP (x, 0),
2959 GET_MODE_SIZE (mode))))))
2960 {
2961 #define __SECONDARY_RELOAD_CASE(M,m) \
2962 case M##mode: \
2963 if (TARGET_64BIT) \
2964 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2965 CODE_FOR_reload##m##di_tomem_z10; \
2966 else \
2967 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
2968 CODE_FOR_reload##m##si_tomem_z10; \
2969 break;
2970
2971 switch (GET_MODE (x))
2972 {
2973 __SECONDARY_RELOAD_CASE (QI, qi);
2974 __SECONDARY_RELOAD_CASE (HI, hi);
2975 __SECONDARY_RELOAD_CASE (SI, si);
2976 __SECONDARY_RELOAD_CASE (DI, di);
2977 __SECONDARY_RELOAD_CASE (TI, ti);
2978 __SECONDARY_RELOAD_CASE (SF, sf);
2979 __SECONDARY_RELOAD_CASE (DF, df);
2980 __SECONDARY_RELOAD_CASE (TF, tf);
2981 __SECONDARY_RELOAD_CASE (SD, sd);
2982 __SECONDARY_RELOAD_CASE (DD, dd);
2983 __SECONDARY_RELOAD_CASE (TD, td);
2984
2985 default:
2986 gcc_unreachable ();
2987 }
2988 #undef __SECONDARY_RELOAD_CASE
2989 }
2990 }
2991
2992 /* We need a scratch register when loading a PLUS expression which
2993 is not a legitimate operand of the LOAD ADDRESS instruction. */
2994 if (in_p && s390_plus_operand (x, mode))
2995 sri->icode = (TARGET_64BIT ?
2996 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
2997
2998 /* Performing a multiword move from or to memory we have to make sure the
2999 second chunk in memory is addressable without causing a displacement
3000 overflow. If that would be the case we calculate the address in
3001 a scratch register. */
3002 if (MEM_P (x)
3003 && GET_CODE (XEXP (x, 0)) == PLUS
3004 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3005 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3006 + GET_MODE_SIZE (mode) - 1))
3007 {
3008 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3009 in a s_operand address since we may fallback to lm/stm. So we only
3010 have to care about overflows in the b+i+d case. */
3011 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3012 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3013 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3014 /* For FP_REGS no lm/stm is available so this check is triggered
3015 for displacement overflows in b+i+d and b+d like addresses. */
3016 || (reg_classes_intersect_p (FP_REGS, rclass)
3017 && s390_class_max_nregs (FP_REGS, mode) > 1))
3018 {
3019 if (in_p)
3020 sri->icode = (TARGET_64BIT ?
3021 CODE_FOR_reloaddi_nonoffmem_in :
3022 CODE_FOR_reloadsi_nonoffmem_in);
3023 else
3024 sri->icode = (TARGET_64BIT ?
3025 CODE_FOR_reloaddi_nonoffmem_out :
3026 CODE_FOR_reloadsi_nonoffmem_out);
3027 }
3028 }
3029
3030 /* A scratch address register is needed when a symbolic constant is
3031 copied to r0 compiling with -fPIC. In other cases the target
3032 register might be used as temporary (see legitimize_pic_address). */
3033 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3034 sri->icode = (TARGET_64BIT ?
3035 CODE_FOR_reloaddi_PIC_addr :
3036 CODE_FOR_reloadsi_PIC_addr);
3037
3038 /* Either scratch or no register needed. */
3039 return NO_REGS;
3040 }
3041
3042 /* Generate code to load SRC, which is PLUS that is not a
3043 legitimate operand for the LA instruction, into TARGET.
3044 SCRATCH may be used as scratch register. */
3045
3046 void
3047 s390_expand_plus_operand (rtx target, rtx src,
3048 rtx scratch)
3049 {
3050 rtx sum1, sum2;
3051 struct s390_address ad;
3052
3053 /* src must be a PLUS; get its two operands. */
3054 gcc_assert (GET_CODE (src) == PLUS);
3055 gcc_assert (GET_MODE (src) == Pmode);
3056
3057 /* Check if any of the two operands is already scheduled
3058 for replacement by reload. This can happen e.g. when
3059 float registers occur in an address. */
3060 sum1 = find_replacement (&XEXP (src, 0));
3061 sum2 = find_replacement (&XEXP (src, 1));
3062 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3063
3064 /* If the address is already strictly valid, there's nothing to do. */
3065 if (!s390_decompose_address (src, &ad)
3066 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3067 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3068 {
3069 /* Otherwise, one of the operands cannot be an address register;
3070 we reload its value into the scratch register. */
3071 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3072 {
3073 emit_move_insn (scratch, sum1);
3074 sum1 = scratch;
3075 }
3076 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3077 {
3078 emit_move_insn (scratch, sum2);
3079 sum2 = scratch;
3080 }
3081
3082 /* According to the way these invalid addresses are generated
3083 in reload.c, it should never happen (at least on s390) that
3084 *neither* of the PLUS components, after find_replacements
3085 was applied, is an address register. */
3086 if (sum1 == scratch && sum2 == scratch)
3087 {
3088 debug_rtx (src);
3089 gcc_unreachable ();
3090 }
3091
3092 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3093 }
3094
3095 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3096 is only ever performed on addresses, so we can mark the
3097 sum as legitimate for LA in any case. */
3098 s390_load_address (target, src);
3099 }
3100
3101
3102 /* Return true if ADDR is a valid memory address.
3103 STRICT specifies whether strict register checking applies. */
3104
3105 bool
3106 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3107 {
3108 struct s390_address ad;
3109
3110 if (TARGET_Z10
3111 && larl_operand (addr, VOIDmode)
3112 && (mode == VOIDmode
3113 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3114 return true;
3115
3116 if (!s390_decompose_address (addr, &ad))
3117 return false;
3118
3119 if (strict)
3120 {
3121 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3122 return false;
3123
3124 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3125 return false;
3126 }
3127 else
3128 {
3129 if (ad.base
3130 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3131 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3132 return false;
3133
3134 if (ad.indx
3135 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3136 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3137 return false;
3138 }
3139 return true;
3140 }
3141
3142 /* Return true if OP is a valid operand for the LA instruction.
3143 In 31-bit, we need to prove that the result is used as an
3144 address, as LA performs only a 31-bit addition. */
3145
3146 bool
3147 legitimate_la_operand_p (rtx op)
3148 {
3149 struct s390_address addr;
3150 if (!s390_decompose_address (op, &addr))
3151 return false;
3152
3153 return (TARGET_64BIT || addr.pointer);
3154 }
3155
3156 /* Return true if it is valid *and* preferable to use LA to
3157 compute the sum of OP1 and OP2. */
3158
3159 bool
3160 preferred_la_operand_p (rtx op1, rtx op2)
3161 {
3162 struct s390_address addr;
3163
3164 if (op2 != const0_rtx)
3165 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3166
3167 if (!s390_decompose_address (op1, &addr))
3168 return false;
3169 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3170 return false;
3171 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3172 return false;
3173
3174 if (!TARGET_64BIT && !addr.pointer)
3175 return false;
3176
3177 if (addr.pointer)
3178 return true;
3179
3180 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3181 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3182 return true;
3183
3184 return false;
3185 }
3186
3187 /* Emit a forced load-address operation to load SRC into DST.
3188 This will use the LOAD ADDRESS instruction even in situations
3189 where legitimate_la_operand_p (SRC) returns false. */
3190
3191 void
3192 s390_load_address (rtx dst, rtx src)
3193 {
3194 if (TARGET_64BIT)
3195 emit_move_insn (dst, src);
3196 else
3197 emit_insn (gen_force_la_31 (dst, src));
3198 }
3199
3200 /* Return a legitimate reference for ORIG (an address) using the
3201 register REG. If REG is 0, a new pseudo is generated.
3202
3203 There are two types of references that must be handled:
3204
3205 1. Global data references must load the address from the GOT, via
3206 the PIC reg. An insn is emitted to do this load, and the reg is
3207 returned.
3208
3209 2. Static data references, constant pool addresses, and code labels
3210 compute the address as an offset from the GOT, whose base is in
3211 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3212 differentiate them from global data objects. The returned
3213 address is the PIC reg + an unspec constant.
3214
3215 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
3216 reg also appears in the address. */
3217
3218 rtx
3219 legitimize_pic_address (rtx orig, rtx reg)
3220 {
3221 rtx addr = orig;
3222 rtx new_rtx = orig;
3223 rtx base;
3224
3225 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3226
3227 if (GET_CODE (addr) == LABEL_REF
3228 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3229 {
3230 /* This is a local symbol. */
3231 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3232 {
3233 /* Access local symbols PC-relative via LARL.
3234 This is the same as in the non-PIC case, so it is
3235 handled automatically ... */
3236 }
3237 else
3238 {
3239 /* Access local symbols relative to the GOT. */
3240
3241 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3242
3243 if (reload_in_progress || reload_completed)
3244 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3245
3246 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3247 addr = gen_rtx_CONST (Pmode, addr);
3248 addr = force_const_mem (Pmode, addr);
3249 emit_move_insn (temp, addr);
3250
3251 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3252 if (reg != 0)
3253 {
3254 s390_load_address (reg, new_rtx);
3255 new_rtx = reg;
3256 }
3257 }
3258 }
3259 else if (GET_CODE (addr) == SYMBOL_REF)
3260 {
3261 if (reg == 0)
3262 reg = gen_reg_rtx (Pmode);
3263
3264 if (flag_pic == 1)
3265 {
3266 /* Assume GOT offset < 4k. This is handled the same way
3267 in both 31- and 64-bit code (@GOT). */
3268
3269 if (reload_in_progress || reload_completed)
3270 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3271
3272 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3273 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3274 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3275 new_rtx = gen_const_mem (Pmode, new_rtx);
3276 emit_move_insn (reg, new_rtx);
3277 new_rtx = reg;
3278 }
3279 else if (TARGET_CPU_ZARCH)
3280 {
3281 /* If the GOT offset might be >= 4k, we determine the position
3282 of the GOT entry via a PC-relative LARL (@GOTENT). */
3283
3284 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3285
3286 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3287 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3288
3289 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3290 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3291 emit_move_insn (temp, new_rtx);
3292
3293 new_rtx = gen_const_mem (Pmode, temp);
3294 emit_move_insn (reg, new_rtx);
3295 new_rtx = reg;
3296 }
3297 else
3298 {
3299 /* If the GOT offset might be >= 4k, we have to load it
3300 from the literal pool (@GOT). */
3301
3302 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3303
3304 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3305 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3306
3307 if (reload_in_progress || reload_completed)
3308 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3309
3310 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3311 addr = gen_rtx_CONST (Pmode, addr);
3312 addr = force_const_mem (Pmode, addr);
3313 emit_move_insn (temp, addr);
3314
3315 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3316 new_rtx = gen_const_mem (Pmode, new_rtx);
3317 emit_move_insn (reg, new_rtx);
3318 new_rtx = reg;
3319 }
3320 }
3321 else
3322 {
3323 if (GET_CODE (addr) == CONST)
3324 {
3325 addr = XEXP (addr, 0);
3326 if (GET_CODE (addr) == UNSPEC)
3327 {
3328 gcc_assert (XVECLEN (addr, 0) == 1);
3329 switch (XINT (addr, 1))
3330 {
3331 /* If someone moved a GOT-relative UNSPEC
3332 out of the literal pool, force them back in. */
3333 case UNSPEC_GOTOFF:
3334 case UNSPEC_PLTOFF:
3335 new_rtx = force_const_mem (Pmode, orig);
3336 break;
3337
3338 /* @GOT is OK as is if small. */
3339 case UNSPEC_GOT:
3340 if (flag_pic == 2)
3341 new_rtx = force_const_mem (Pmode, orig);
3342 break;
3343
3344 /* @GOTENT is OK as is. */
3345 case UNSPEC_GOTENT:
3346 break;
3347
3348 /* @PLT is OK as is on 64-bit, must be converted to
3349 GOT-relative @PLTOFF on 31-bit. */
3350 case UNSPEC_PLT:
3351 if (!TARGET_CPU_ZARCH)
3352 {
3353 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3354
3355 if (reload_in_progress || reload_completed)
3356 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3357
3358 addr = XVECEXP (addr, 0, 0);
3359 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3360 UNSPEC_PLTOFF);
3361 addr = gen_rtx_CONST (Pmode, addr);
3362 addr = force_const_mem (Pmode, addr);
3363 emit_move_insn (temp, addr);
3364
3365 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3366 if (reg != 0)
3367 {
3368 s390_load_address (reg, new_rtx);
3369 new_rtx = reg;
3370 }
3371 }
3372 break;
3373
3374 /* Everything else cannot happen. */
3375 default:
3376 gcc_unreachable ();
3377 }
3378 }
3379 else
3380 gcc_assert (GET_CODE (addr) == PLUS);
3381 }
3382 if (GET_CODE (addr) == PLUS)
3383 {
3384 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3385
3386 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3387 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3388
3389 /* Check first to see if this is a constant offset
3390 from a local symbol reference. */
3391 if ((GET_CODE (op0) == LABEL_REF
3392 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3393 && GET_CODE (op1) == CONST_INT)
3394 {
3395 if (TARGET_CPU_ZARCH
3396 && larl_operand (op0, VOIDmode)
3397 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3398 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3399 {
3400 if (INTVAL (op1) & 1)
3401 {
3402 /* LARL can't handle odd offsets, so emit a
3403 pair of LARL and LA. */
3404 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3405
3406 if (!DISP_IN_RANGE (INTVAL (op1)))
3407 {
3408 HOST_WIDE_INT even = INTVAL (op1) - 1;
3409 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3410 op0 = gen_rtx_CONST (Pmode, op0);
3411 op1 = const1_rtx;
3412 }
3413
3414 emit_move_insn (temp, op0);
3415 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3416
3417 if (reg != 0)
3418 {
3419 s390_load_address (reg, new_rtx);
3420 new_rtx = reg;
3421 }
3422 }
3423 else
3424 {
3425 /* If the offset is even, we can just use LARL.
3426 This will happen automatically. */
3427 }
3428 }
3429 else
3430 {
3431 /* Access local symbols relative to the GOT. */
3432
3433 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3434
3435 if (reload_in_progress || reload_completed)
3436 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3437
3438 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3439 UNSPEC_GOTOFF);
3440 addr = gen_rtx_PLUS (Pmode, addr, op1);
3441 addr = gen_rtx_CONST (Pmode, addr);
3442 addr = force_const_mem (Pmode, addr);
3443 emit_move_insn (temp, addr);
3444
3445 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3446 if (reg != 0)
3447 {
3448 s390_load_address (reg, new_rtx);
3449 new_rtx = reg;
3450 }
3451 }
3452 }
3453
3454 /* Now, check whether it is a GOT relative symbol plus offset
3455 that was pulled out of the literal pool. Force it back in. */
3456
3457 else if (GET_CODE (op0) == UNSPEC
3458 && GET_CODE (op1) == CONST_INT
3459 && XINT (op0, 1) == UNSPEC_GOTOFF)
3460 {
3461 gcc_assert (XVECLEN (op0, 0) == 1);
3462
3463 new_rtx = force_const_mem (Pmode, orig);
3464 }
3465
3466 /* Otherwise, compute the sum. */
3467 else
3468 {
3469 base = legitimize_pic_address (XEXP (addr, 0), reg);
3470 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3471 base == reg ? NULL_RTX : reg);
3472 if (GET_CODE (new_rtx) == CONST_INT)
3473 new_rtx = plus_constant (base, INTVAL (new_rtx));
3474 else
3475 {
3476 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3477 {
3478 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3479 new_rtx = XEXP (new_rtx, 1);
3480 }
3481 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3482 }
3483
3484 if (GET_CODE (new_rtx) == CONST)
3485 new_rtx = XEXP (new_rtx, 0);
3486 new_rtx = force_operand (new_rtx, 0);
3487 }
3488 }
3489 }
3490 return new_rtx;
3491 }
3492
3493 /* Load the thread pointer into a register. */
3494
3495 rtx
3496 s390_get_thread_pointer (void)
3497 {
3498 rtx tp = gen_reg_rtx (Pmode);
3499
3500 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3501 mark_reg_pointer (tp, BITS_PER_WORD);
3502
3503 return tp;
3504 }
3505
3506 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3507 in s390_tls_symbol which always refers to __tls_get_offset.
3508 The returned offset is written to RESULT_REG and an USE rtx is
3509 generated for TLS_CALL. */
3510
3511 static GTY(()) rtx s390_tls_symbol;
3512
3513 static void
3514 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3515 {
3516 rtx insn;
3517
3518 gcc_assert (flag_pic);
3519
3520 if (!s390_tls_symbol)
3521 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3522
3523 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3524 gen_rtx_REG (Pmode, RETURN_REGNUM));
3525
3526 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3527 RTL_CONST_CALL_P (insn) = 1;
3528 }
3529
3530 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3531 this (thread-local) address. REG may be used as temporary. */
3532
3533 static rtx
3534 legitimize_tls_address (rtx addr, rtx reg)
3535 {
3536 rtx new_rtx, tls_call, temp, base, r2, insn;
3537
3538 if (GET_CODE (addr) == SYMBOL_REF)
3539 switch (tls_symbolic_operand (addr))
3540 {
3541 case TLS_MODEL_GLOBAL_DYNAMIC:
3542 start_sequence ();
3543 r2 = gen_rtx_REG (Pmode, 2);
3544 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3545 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3546 new_rtx = force_const_mem (Pmode, new_rtx);
3547 emit_move_insn (r2, new_rtx);
3548 s390_emit_tls_call_insn (r2, tls_call);
3549 insn = get_insns ();
3550 end_sequence ();
3551
3552 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3553 temp = gen_reg_rtx (Pmode);
3554 emit_libcall_block (insn, temp, r2, new_rtx);
3555
3556 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3557 if (reg != 0)
3558 {
3559 s390_load_address (reg, new_rtx);
3560 new_rtx = reg;
3561 }
3562 break;
3563
3564 case TLS_MODEL_LOCAL_DYNAMIC:
3565 start_sequence ();
3566 r2 = gen_rtx_REG (Pmode, 2);
3567 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3568 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3569 new_rtx = force_const_mem (Pmode, new_rtx);
3570 emit_move_insn (r2, new_rtx);
3571 s390_emit_tls_call_insn (r2, tls_call);
3572 insn = get_insns ();
3573 end_sequence ();
3574
3575 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3576 temp = gen_reg_rtx (Pmode);
3577 emit_libcall_block (insn, temp, r2, new_rtx);
3578
3579 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3580 base = gen_reg_rtx (Pmode);
3581 s390_load_address (base, new_rtx);
3582
3583 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3584 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3585 new_rtx = force_const_mem (Pmode, new_rtx);
3586 temp = gen_reg_rtx (Pmode);
3587 emit_move_insn (temp, new_rtx);
3588
3589 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3590 if (reg != 0)
3591 {
3592 s390_load_address (reg, new_rtx);
3593 new_rtx = reg;
3594 }
3595 break;
3596
3597 case TLS_MODEL_INITIAL_EXEC:
3598 if (flag_pic == 1)
3599 {
3600 /* Assume GOT offset < 4k. This is handled the same way
3601 in both 31- and 64-bit code. */
3602
3603 if (reload_in_progress || reload_completed)
3604 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3605
3606 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3607 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3608 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3609 new_rtx = gen_const_mem (Pmode, new_rtx);
3610 temp = gen_reg_rtx (Pmode);
3611 emit_move_insn (temp, new_rtx);
3612 }
3613 else if (TARGET_CPU_ZARCH)
3614 {
3615 /* If the GOT offset might be >= 4k, we determine the position
3616 of the GOT entry via a PC-relative LARL. */
3617
3618 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3619 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3620 temp = gen_reg_rtx (Pmode);
3621 emit_move_insn (temp, new_rtx);
3622
3623 new_rtx = gen_const_mem (Pmode, temp);
3624 temp = gen_reg_rtx (Pmode);
3625 emit_move_insn (temp, new_rtx);
3626 }
3627 else if (flag_pic)
3628 {
3629 /* If the GOT offset might be >= 4k, we have to load it
3630 from the literal pool. */
3631
3632 if (reload_in_progress || reload_completed)
3633 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3634
3635 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3636 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3637 new_rtx = force_const_mem (Pmode, new_rtx);
3638 temp = gen_reg_rtx (Pmode);
3639 emit_move_insn (temp, new_rtx);
3640
3641 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3642 new_rtx = gen_const_mem (Pmode, new_rtx);
3643
3644 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3645 temp = gen_reg_rtx (Pmode);
3646 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3647 }
3648 else
3649 {
3650 /* In position-dependent code, load the absolute address of
3651 the GOT entry from the literal pool. */
3652
3653 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3654 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3655 new_rtx = force_const_mem (Pmode, new_rtx);
3656 temp = gen_reg_rtx (Pmode);
3657 emit_move_insn (temp, new_rtx);
3658
3659 new_rtx = temp;
3660 new_rtx = gen_const_mem (Pmode, new_rtx);
3661 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3662 temp = gen_reg_rtx (Pmode);
3663 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3664 }
3665
3666 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3667 if (reg != 0)
3668 {
3669 s390_load_address (reg, new_rtx);
3670 new_rtx = reg;
3671 }
3672 break;
3673
3674 case TLS_MODEL_LOCAL_EXEC:
3675 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3676 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3677 new_rtx = force_const_mem (Pmode, new_rtx);
3678 temp = gen_reg_rtx (Pmode);
3679 emit_move_insn (temp, new_rtx);
3680
3681 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3682 if (reg != 0)
3683 {
3684 s390_load_address (reg, new_rtx);
3685 new_rtx = reg;
3686 }
3687 break;
3688
3689 default:
3690 gcc_unreachable ();
3691 }
3692
3693 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3694 {
3695 switch (XINT (XEXP (addr, 0), 1))
3696 {
3697 case UNSPEC_INDNTPOFF:
3698 gcc_assert (TARGET_CPU_ZARCH);
3699 new_rtx = addr;
3700 break;
3701
3702 default:
3703 gcc_unreachable ();
3704 }
3705 }
3706
3707 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3708 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3709 {
3710 new_rtx = XEXP (XEXP (addr, 0), 0);
3711 if (GET_CODE (new_rtx) != SYMBOL_REF)
3712 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3713
3714 new_rtx = legitimize_tls_address (new_rtx, reg);
3715 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3716 new_rtx = force_operand (new_rtx, 0);
3717 }
3718
3719 else
3720 gcc_unreachable (); /* for now ... */
3721
3722 return new_rtx;
3723 }
3724
3725 /* Emit insns making the address in operands[1] valid for a standard
3726 move to operands[0]. operands[1] is replaced by an address which
3727 should be used instead of the former RTX to emit the move
3728 pattern. */
3729
3730 void
3731 emit_symbolic_move (rtx *operands)
3732 {
3733 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3734
3735 if (GET_CODE (operands[0]) == MEM)
3736 operands[1] = force_reg (Pmode, operands[1]);
3737 else if (TLS_SYMBOLIC_CONST (operands[1]))
3738 operands[1] = legitimize_tls_address (operands[1], temp);
3739 else if (flag_pic)
3740 operands[1] = legitimize_pic_address (operands[1], temp);
3741 }
3742
3743 /* Try machine-dependent ways of modifying an illegitimate address X
3744 to be legitimate. If we find one, return the new, valid address.
3745
3746 OLDX is the address as it was before break_out_memory_refs was called.
3747 In some cases it is useful to look at this to decide what needs to be done.
3748
3749 MODE is the mode of the operand pointed to by X.
3750
3751 When -fpic is used, special handling is needed for symbolic references.
3752 See comments by legitimize_pic_address for details. */
3753
3754 rtx
3755 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3756 enum machine_mode mode ATTRIBUTE_UNUSED)
3757 {
3758 rtx constant_term = const0_rtx;
3759
3760 if (TLS_SYMBOLIC_CONST (x))
3761 {
3762 x = legitimize_tls_address (x, 0);
3763
3764 if (legitimate_address_p (mode, x, FALSE))
3765 return x;
3766 }
3767 else if (GET_CODE (x) == PLUS
3768 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3769 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3770 {
3771 return x;
3772 }
3773 else if (flag_pic)
3774 {
3775 if (SYMBOLIC_CONST (x)
3776 || (GET_CODE (x) == PLUS
3777 && (SYMBOLIC_CONST (XEXP (x, 0))
3778 || SYMBOLIC_CONST (XEXP (x, 1)))))
3779 x = legitimize_pic_address (x, 0);
3780
3781 if (legitimate_address_p (mode, x, FALSE))
3782 return x;
3783 }
3784
3785 x = eliminate_constant_term (x, &constant_term);
3786
3787 /* Optimize loading of large displacements by splitting them
3788 into the multiple of 4K and the rest; this allows the
3789 former to be CSE'd if possible.
3790
3791 Don't do this if the displacement is added to a register
3792 pointing into the stack frame, as the offsets will
3793 change later anyway. */
3794
3795 if (GET_CODE (constant_term) == CONST_INT
3796 && !TARGET_LONG_DISPLACEMENT
3797 && !DISP_IN_RANGE (INTVAL (constant_term))
3798 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3799 {
3800 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3801 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3802
3803 rtx temp = gen_reg_rtx (Pmode);
3804 rtx val = force_operand (GEN_INT (upper), temp);
3805 if (val != temp)
3806 emit_move_insn (temp, val);
3807
3808 x = gen_rtx_PLUS (Pmode, x, temp);
3809 constant_term = GEN_INT (lower);
3810 }
3811
3812 if (GET_CODE (x) == PLUS)
3813 {
3814 if (GET_CODE (XEXP (x, 0)) == REG)
3815 {
3816 rtx temp = gen_reg_rtx (Pmode);
3817 rtx val = force_operand (XEXP (x, 1), temp);
3818 if (val != temp)
3819 emit_move_insn (temp, val);
3820
3821 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3822 }
3823
3824 else if (GET_CODE (XEXP (x, 1)) == REG)
3825 {
3826 rtx temp = gen_reg_rtx (Pmode);
3827 rtx val = force_operand (XEXP (x, 0), temp);
3828 if (val != temp)
3829 emit_move_insn (temp, val);
3830
3831 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3832 }
3833 }
3834
3835 if (constant_term != const0_rtx)
3836 x = gen_rtx_PLUS (Pmode, x, constant_term);
3837
3838 return x;
3839 }
3840
3841 /* Try a machine-dependent way of reloading an illegitimate address AD
3842 operand. If we find one, push the reload and and return the new address.
3843
3844 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3845 and TYPE is the reload type of the current reload. */
3846
3847 rtx
3848 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3849 int opnum, int type)
3850 {
3851 if (!optimize || TARGET_LONG_DISPLACEMENT)
3852 return NULL_RTX;
3853
3854 if (GET_CODE (ad) == PLUS)
3855 {
3856 rtx tem = simplify_binary_operation (PLUS, Pmode,
3857 XEXP (ad, 0), XEXP (ad, 1));
3858 if (tem)
3859 ad = tem;
3860 }
3861
3862 if (GET_CODE (ad) == PLUS
3863 && GET_CODE (XEXP (ad, 0)) == REG
3864 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3865 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3866 {
3867 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3868 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3869 rtx cst, tem, new_rtx;
3870
3871 cst = GEN_INT (upper);
3872 if (!legitimate_reload_constant_p (cst))
3873 cst = force_const_mem (Pmode, cst);
3874
3875 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3876 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3877
3878 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3879 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3880 opnum, (enum reload_type) type);
3881 return new_rtx;
3882 }
3883
3884 return NULL_RTX;
3885 }
3886
3887 /* Emit code to move LEN bytes from DST to SRC. */
3888
3889 void
3890 s390_expand_movmem (rtx dst, rtx src, rtx len)
3891 {
3892 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3893 {
3894 if (INTVAL (len) > 0)
3895 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3896 }
3897
3898 else if (TARGET_MVCLE)
3899 {
3900 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3901 }
3902
3903 else
3904 {
3905 rtx dst_addr, src_addr, count, blocks, temp;
3906 rtx loop_start_label = gen_label_rtx ();
3907 rtx loop_end_label = gen_label_rtx ();
3908 rtx end_label = gen_label_rtx ();
3909 enum machine_mode mode;
3910
3911 mode = GET_MODE (len);
3912 if (mode == VOIDmode)
3913 mode = Pmode;
3914
3915 dst_addr = gen_reg_rtx (Pmode);
3916 src_addr = gen_reg_rtx (Pmode);
3917 count = gen_reg_rtx (mode);
3918 blocks = gen_reg_rtx (mode);
3919
3920 convert_move (count, len, 1);
3921 emit_cmp_and_jump_insns (count, const0_rtx,
3922 EQ, NULL_RTX, mode, 1, end_label);
3923
3924 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3925 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3926 dst = change_address (dst, VOIDmode, dst_addr);
3927 src = change_address (src, VOIDmode, src_addr);
3928
3929 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3930 if (temp != count)
3931 emit_move_insn (count, temp);
3932
3933 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0);
3934 if (temp != blocks)
3935 emit_move_insn (blocks, temp);
3936
3937 emit_cmp_and_jump_insns (blocks, const0_rtx,
3938 EQ, NULL_RTX, mode, 1, loop_end_label);
3939
3940 emit_label (loop_start_label);
3941
3942 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3943 s390_load_address (dst_addr,
3944 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3945 s390_load_address (src_addr,
3946 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3947
3948 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3949 if (temp != blocks)
3950 emit_move_insn (blocks, temp);
3951
3952 emit_cmp_and_jump_insns (blocks, const0_rtx,
3953 EQ, NULL_RTX, mode, 1, loop_end_label);
3954
3955 emit_jump (loop_start_label);
3956 emit_label (loop_end_label);
3957
3958 emit_insn (gen_movmem_short (dst, src,
3959 convert_to_mode (Pmode, count, 1)));
3960 emit_label (end_label);
3961 }
3962 }
3963
3964 /* Emit code to set LEN bytes at DST to VAL.
3965 Make use of clrmem if VAL is zero. */
3966
3967 void
3968 s390_expand_setmem (rtx dst, rtx len, rtx val)
3969 {
3970 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
3971 return;
3972
3973 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3974
3975 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
3976 {
3977 if (val == const0_rtx && INTVAL (len) <= 256)
3978 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3979 else
3980 {
3981 /* Initialize memory by storing the first byte. */
3982 emit_move_insn (adjust_address (dst, QImode, 0), val);
3983
3984 if (INTVAL (len) > 1)
3985 {
3986 /* Initiate 1 byte overlap move.
3987 The first byte of DST is propagated through DSTP1.
3988 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3989 DST is set to size 1 so the rest of the memory location
3990 does not count as source operand. */
3991 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3992 set_mem_size (dst, const1_rtx);
3993
3994 emit_insn (gen_movmem_short (dstp1, dst,
3995 GEN_INT (INTVAL (len) - 2)));
3996 }
3997 }
3998 }
3999
4000 else if (TARGET_MVCLE)
4001 {
4002 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4003 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4004 }
4005
4006 else
4007 {
4008 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
4009 rtx loop_start_label = gen_label_rtx ();
4010 rtx loop_end_label = gen_label_rtx ();
4011 rtx end_label = gen_label_rtx ();
4012 enum machine_mode mode;
4013
4014 mode = GET_MODE (len);
4015 if (mode == VOIDmode)
4016 mode = Pmode;
4017
4018 dst_addr = gen_reg_rtx (Pmode);
4019 src_addr = gen_reg_rtx (Pmode);
4020 count = gen_reg_rtx (mode);
4021 blocks = gen_reg_rtx (mode);
4022
4023 convert_move (count, len, 1);
4024 emit_cmp_and_jump_insns (count, const0_rtx,
4025 EQ, NULL_RTX, mode, 1, end_label);
4026
4027 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4028 dst = change_address (dst, VOIDmode, dst_addr);
4029
4030 if (val == const0_rtx)
4031 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
4032 else
4033 {
4034 dstp1 = adjust_address (dst, VOIDmode, 1);
4035 set_mem_size (dst, const1_rtx);
4036
4037 /* Initialize memory by storing the first byte. */
4038 emit_move_insn (adjust_address (dst, QImode, 0), val);
4039
4040 /* If count is 1 we are done. */
4041 emit_cmp_and_jump_insns (count, const1_rtx,
4042 EQ, NULL_RTX, mode, 1, end_label);
4043
4044 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
4045 }
4046 if (temp != count)
4047 emit_move_insn (count, temp);
4048
4049 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0);
4050 if (temp != blocks)
4051 emit_move_insn (blocks, temp);
4052
4053 emit_cmp_and_jump_insns (blocks, const0_rtx,
4054 EQ, NULL_RTX, mode, 1, loop_end_label);
4055
4056 emit_label (loop_start_label);
4057
4058 if (val == const0_rtx)
4059 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4060 else
4061 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4062 s390_load_address (dst_addr,
4063 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4064
4065 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
4066 if (temp != blocks)
4067 emit_move_insn (blocks, temp);
4068
4069 emit_cmp_and_jump_insns (blocks, const0_rtx,
4070 EQ, NULL_RTX, mode, 1, loop_end_label);
4071
4072 emit_jump (loop_start_label);
4073 emit_label (loop_end_label);
4074
4075 if (val == const0_rtx)
4076 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4077 else
4078 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4079 emit_label (end_label);
4080 }
4081 }
4082
4083 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4084 and return the result in TARGET. */
4085
4086 void
4087 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4088 {
4089 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4090 rtx tmp;
4091
4092 /* As the result of CMPINT is inverted compared to what we need,
4093 we have to swap the operands. */
4094 tmp = op0; op0 = op1; op1 = tmp;
4095
4096 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4097 {
4098 if (INTVAL (len) > 0)
4099 {
4100 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4101 emit_insn (gen_cmpint (target, ccreg));
4102 }
4103 else
4104 emit_move_insn (target, const0_rtx);
4105 }
4106 else if (TARGET_MVCLE)
4107 {
4108 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4109 emit_insn (gen_cmpint (target, ccreg));
4110 }
4111 else
4112 {
4113 rtx addr0, addr1, count, blocks, temp;
4114 rtx loop_start_label = gen_label_rtx ();
4115 rtx loop_end_label = gen_label_rtx ();
4116 rtx end_label = gen_label_rtx ();
4117 enum machine_mode mode;
4118
4119 mode = GET_MODE (len);
4120 if (mode == VOIDmode)
4121 mode = Pmode;
4122
4123 addr0 = gen_reg_rtx (Pmode);
4124 addr1 = gen_reg_rtx (Pmode);
4125 count = gen_reg_rtx (mode);
4126 blocks = gen_reg_rtx (mode);
4127
4128 convert_move (count, len, 1);
4129 emit_cmp_and_jump_insns (count, const0_rtx,
4130 EQ, NULL_RTX, mode, 1, end_label);
4131
4132 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4133 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4134 op0 = change_address (op0, VOIDmode, addr0);
4135 op1 = change_address (op1, VOIDmode, addr1);
4136
4137 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
4138 if (temp != count)
4139 emit_move_insn (count, temp);
4140
4141 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, 0);
4142 if (temp != blocks)
4143 emit_move_insn (blocks, temp);
4144
4145 emit_cmp_and_jump_insns (blocks, const0_rtx,
4146 EQ, NULL_RTX, mode, 1, loop_end_label);
4147
4148 emit_label (loop_start_label);
4149
4150 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4151 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4152 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4153 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4154 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4155 emit_jump_insn (temp);
4156
4157 s390_load_address (addr0,
4158 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4159 s390_load_address (addr1,
4160 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4161
4162 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
4163 if (temp != blocks)
4164 emit_move_insn (blocks, temp);
4165
4166 emit_cmp_and_jump_insns (blocks, const0_rtx,
4167 EQ, NULL_RTX, mode, 1, loop_end_label);
4168
4169 emit_jump (loop_start_label);
4170 emit_label (loop_end_label);
4171
4172 emit_insn (gen_cmpmem_short (op0, op1,
4173 convert_to_mode (Pmode, count, 1)));
4174 emit_label (end_label);
4175
4176 emit_insn (gen_cmpint (target, ccreg));
4177 }
4178 }
4179
4180
4181 /* Expand conditional increment or decrement using alc/slb instructions.
4182 Should generate code setting DST to either SRC or SRC + INCREMENT,
4183 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4184 Returns true if successful, false otherwise.
4185
4186 That makes it possible to implement some if-constructs without jumps e.g.:
4187 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4188 unsigned int a, b, c;
4189 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4190 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4191 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4192 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4193
4194 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4195 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4196 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4197 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4198 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4199
4200 bool
4201 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4202 rtx dst, rtx src, rtx increment)
4203 {
4204 enum machine_mode cmp_mode;
4205 enum machine_mode cc_mode;
4206 rtx op_res;
4207 rtx insn;
4208 rtvec p;
4209 int ret;
4210
4211 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4212 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4213 cmp_mode = SImode;
4214 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4215 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4216 cmp_mode = DImode;
4217 else
4218 return false;
4219
4220 /* Try ADD LOGICAL WITH CARRY. */
4221 if (increment == const1_rtx)
4222 {
4223 /* Determine CC mode to use. */
4224 if (cmp_code == EQ || cmp_code == NE)
4225 {
4226 if (cmp_op1 != const0_rtx)
4227 {
4228 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4229 NULL_RTX, 0, OPTAB_WIDEN);
4230 cmp_op1 = const0_rtx;
4231 }
4232
4233 cmp_code = cmp_code == EQ ? LEU : GTU;
4234 }
4235
4236 if (cmp_code == LTU || cmp_code == LEU)
4237 {
4238 rtx tem = cmp_op0;
4239 cmp_op0 = cmp_op1;
4240 cmp_op1 = tem;
4241 cmp_code = swap_condition (cmp_code);
4242 }
4243
4244 switch (cmp_code)
4245 {
4246 case GTU:
4247 cc_mode = CCUmode;
4248 break;
4249
4250 case GEU:
4251 cc_mode = CCL3mode;
4252 break;
4253
4254 default:
4255 return false;
4256 }
4257
4258 /* Emit comparison instruction pattern. */
4259 if (!register_operand (cmp_op0, cmp_mode))
4260 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4261
4262 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4263 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4264 /* We use insn_invalid_p here to add clobbers if required. */
4265 ret = insn_invalid_p (emit_insn (insn));
4266 gcc_assert (!ret);
4267
4268 /* Emit ALC instruction pattern. */
4269 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4270 gen_rtx_REG (cc_mode, CC_REGNUM),
4271 const0_rtx);
4272
4273 if (src != const0_rtx)
4274 {
4275 if (!register_operand (src, GET_MODE (dst)))
4276 src = force_reg (GET_MODE (dst), src);
4277
4278 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4279 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4280 }
4281
4282 p = rtvec_alloc (2);
4283 RTVEC_ELT (p, 0) =
4284 gen_rtx_SET (VOIDmode, dst, op_res);
4285 RTVEC_ELT (p, 1) =
4286 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4287 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4288
4289 return true;
4290 }
4291
4292 /* Try SUBTRACT LOGICAL WITH BORROW. */
4293 if (increment == constm1_rtx)
4294 {
4295 /* Determine CC mode to use. */
4296 if (cmp_code == EQ || cmp_code == NE)
4297 {
4298 if (cmp_op1 != const0_rtx)
4299 {
4300 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4301 NULL_RTX, 0, OPTAB_WIDEN);
4302 cmp_op1 = const0_rtx;
4303 }
4304
4305 cmp_code = cmp_code == EQ ? LEU : GTU;
4306 }
4307
4308 if (cmp_code == GTU || cmp_code == GEU)
4309 {
4310 rtx tem = cmp_op0;
4311 cmp_op0 = cmp_op1;
4312 cmp_op1 = tem;
4313 cmp_code = swap_condition (cmp_code);
4314 }
4315
4316 switch (cmp_code)
4317 {
4318 case LEU:
4319 cc_mode = CCUmode;
4320 break;
4321
4322 case LTU:
4323 cc_mode = CCL3mode;
4324 break;
4325
4326 default:
4327 return false;
4328 }
4329
4330 /* Emit comparison instruction pattern. */
4331 if (!register_operand (cmp_op0, cmp_mode))
4332 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4333
4334 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4335 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4336 /* We use insn_invalid_p here to add clobbers if required. */
4337 ret = insn_invalid_p (emit_insn (insn));
4338 gcc_assert (!ret);
4339
4340 /* Emit SLB instruction pattern. */
4341 if (!register_operand (src, GET_MODE (dst)))
4342 src = force_reg (GET_MODE (dst), src);
4343
4344 op_res = gen_rtx_MINUS (GET_MODE (dst),
4345 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4346 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4347 gen_rtx_REG (cc_mode, CC_REGNUM),
4348 const0_rtx));
4349 p = rtvec_alloc (2);
4350 RTVEC_ELT (p, 0) =
4351 gen_rtx_SET (VOIDmode, dst, op_res);
4352 RTVEC_ELT (p, 1) =
4353 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4354 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4355
4356 return true;
4357 }
4358
4359 return false;
4360 }
4361
4362 /* Expand code for the insv template. Return true if successful. */
4363
4364 bool
4365 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4366 {
4367 int bitsize = INTVAL (op1);
4368 int bitpos = INTVAL (op2);
4369
4370 /* On z10 we can use the risbg instruction to implement insv. */
4371 if (TARGET_Z10
4372 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4373 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4374 {
4375 rtx op;
4376 rtx clobber;
4377
4378 op = gen_rtx_SET (GET_MODE(src),
4379 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4380 src);
4381 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4382 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4383
4384 return true;
4385 }
4386
4387 /* We need byte alignment. */
4388 if (bitsize % BITS_PER_UNIT)
4389 return false;
4390
4391 if (bitpos == 0
4392 && memory_operand (dest, VOIDmode)
4393 && (register_operand (src, word_mode)
4394 || const_int_operand (src, VOIDmode)))
4395 {
4396 /* Emit standard pattern if possible. */
4397 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4398 if (GET_MODE_BITSIZE (mode) == bitsize)
4399 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4400
4401 /* (set (ze (mem)) (const_int)). */
4402 else if (const_int_operand (src, VOIDmode))
4403 {
4404 int size = bitsize / BITS_PER_UNIT;
4405 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4406 GET_MODE_SIZE (word_mode) - size);
4407
4408 dest = adjust_address (dest, BLKmode, 0);
4409 set_mem_size (dest, GEN_INT (size));
4410 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4411 }
4412
4413 /* (set (ze (mem)) (reg)). */
4414 else if (register_operand (src, word_mode))
4415 {
4416 if (bitsize <= GET_MODE_BITSIZE (SImode))
4417 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4418 const0_rtx), src);
4419 else
4420 {
4421 /* Emit st,stcmh sequence. */
4422 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4423 int size = stcmh_width / BITS_PER_UNIT;
4424
4425 emit_move_insn (adjust_address (dest, SImode, size),
4426 gen_lowpart (SImode, src));
4427 set_mem_size (dest, GEN_INT (size));
4428 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4429 (stcmh_width), const0_rtx),
4430 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4431 (GET_MODE_BITSIZE (SImode))));
4432 }
4433 }
4434 else
4435 return false;
4436
4437 return true;
4438 }
4439
4440 /* (set (ze (reg)) (const_int)). */
4441 if (TARGET_ZARCH
4442 && register_operand (dest, word_mode)
4443 && (bitpos % 16) == 0
4444 && (bitsize % 16) == 0
4445 && const_int_operand (src, VOIDmode))
4446 {
4447 HOST_WIDE_INT val = INTVAL (src);
4448 int regpos = bitpos + bitsize;
4449
4450 while (regpos > bitpos)
4451 {
4452 enum machine_mode putmode;
4453 int putsize;
4454
4455 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4456 putmode = SImode;
4457 else
4458 putmode = HImode;
4459
4460 putsize = GET_MODE_BITSIZE (putmode);
4461 regpos -= putsize;
4462 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4463 GEN_INT (putsize),
4464 GEN_INT (regpos)),
4465 gen_int_mode (val, putmode));
4466 val >>= putsize;
4467 }
4468 gcc_assert (regpos == bitpos);
4469 return true;
4470 }
4471
4472 return false;
4473 }
4474
4475 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4476 register that holds VAL of mode MODE shifted by COUNT bits. */
4477
4478 static inline rtx
4479 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4480 {
4481 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4482 NULL_RTX, 1, OPTAB_DIRECT);
4483 return expand_simple_binop (SImode, ASHIFT, val, count,
4484 NULL_RTX, 1, OPTAB_DIRECT);
4485 }
4486
4487 /* Structure to hold the initial parameters for a compare_and_swap operation
4488 in HImode and QImode. */
4489
4490 struct alignment_context
4491 {
4492 rtx memsi; /* SI aligned memory location. */
4493 rtx shift; /* Bit offset with regard to lsb. */
4494 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4495 rtx modemaski; /* ~modemask */
4496 bool aligned; /* True if memory is aligned, false else. */
4497 };
4498
4499 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4500 structure AC for transparent simplifying, if the memory alignment is known
4501 to be at least 32bit. MEM is the memory location for the actual operation
4502 and MODE its mode. */
4503
4504 static void
4505 init_alignment_context (struct alignment_context *ac, rtx mem,
4506 enum machine_mode mode)
4507 {
4508 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4509 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4510
4511 if (ac->aligned)
4512 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4513 else
4514 {
4515 /* Alignment is unknown. */
4516 rtx byteoffset, addr, align;
4517
4518 /* Force the address into a register. */
4519 addr = force_reg (Pmode, XEXP (mem, 0));
4520
4521 /* Align it to SImode. */
4522 align = expand_simple_binop (Pmode, AND, addr,
4523 GEN_INT (-GET_MODE_SIZE (SImode)),
4524 NULL_RTX, 1, OPTAB_DIRECT);
4525 /* Generate MEM. */
4526 ac->memsi = gen_rtx_MEM (SImode, align);
4527 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4528 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4529 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4530
4531 /* Calculate shiftcount. */
4532 byteoffset = expand_simple_binop (Pmode, AND, addr,
4533 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4534 NULL_RTX, 1, OPTAB_DIRECT);
4535 /* As we already have some offset, evaluate the remaining distance. */
4536 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4537 NULL_RTX, 1, OPTAB_DIRECT);
4538
4539 }
4540 /* Shift is the byte count, but we need the bitcount. */
4541 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4542 NULL_RTX, 1, OPTAB_DIRECT);
4543 /* Calculate masks. */
4544 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4545 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4546 NULL_RTX, 1, OPTAB_DIRECT);
4547 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4548 }
4549
4550 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4551 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4552 to set if CMP == MEM.
4553 CMP is never in memory for compare_and_swap_cc because
4554 expand_bool_compare_and_swap puts it into a register for later compare. */
4555
4556 void
4557 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4558 {
4559 struct alignment_context ac;
4560 rtx cmpv, newv, val, resv, cc;
4561 rtx res = gen_reg_rtx (SImode);
4562 rtx csloop = gen_label_rtx ();
4563 rtx csend = gen_label_rtx ();
4564
4565 gcc_assert (register_operand (target, VOIDmode));
4566 gcc_assert (MEM_P (mem));
4567
4568 init_alignment_context (&ac, mem, mode);
4569
4570 /* Shift the values to the correct bit positions. */
4571 if (!(ac.aligned && MEM_P (cmp)))
4572 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4573 if (!(ac.aligned && MEM_P (new_rtx)))
4574 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4575
4576 /* Load full word. Subsequent loads are performed by CS. */
4577 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4578 NULL_RTX, 1, OPTAB_DIRECT);
4579
4580 /* Start CS loop. */
4581 emit_label (csloop);
4582 /* val = "<mem>00..0<mem>"
4583 * cmp = "00..0<cmp>00..0"
4584 * new = "00..0<new>00..0"
4585 */
4586
4587 /* Patch cmp and new with val at correct position. */
4588 if (ac.aligned && MEM_P (cmp))
4589 {
4590 cmpv = force_reg (SImode, val);
4591 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4592 }
4593 else
4594 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4595 NULL_RTX, 1, OPTAB_DIRECT));
4596 if (ac.aligned && MEM_P (new_rtx))
4597 {
4598 newv = force_reg (SImode, val);
4599 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4600 }
4601 else
4602 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4603 NULL_RTX, 1, OPTAB_DIRECT));
4604
4605 /* Jump to end if we're done (likely?). */
4606 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4607 cmpv, newv));
4608
4609 /* Check for changes outside mode. */
4610 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4611 NULL_RTX, 1, OPTAB_DIRECT);
4612 cc = s390_emit_compare (NE, resv, val);
4613 emit_move_insn (val, resv);
4614 /* Loop internal if so. */
4615 s390_emit_jump (csloop, cc);
4616
4617 emit_label (csend);
4618
4619 /* Return the correct part of the bitfield. */
4620 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4621 NULL_RTX, 1, OPTAB_DIRECT), 1);
4622 }
4623
4624 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4625 and VAL the value to play with. If AFTER is true then store the value
4626 MEM holds after the operation, if AFTER is false then store the value MEM
4627 holds before the operation. If TARGET is zero then discard that value, else
4628 store it to TARGET. */
4629
4630 void
4631 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4632 rtx target, rtx mem, rtx val, bool after)
4633 {
4634 struct alignment_context ac;
4635 rtx cmp;
4636 rtx new_rtx = gen_reg_rtx (SImode);
4637 rtx orig = gen_reg_rtx (SImode);
4638 rtx csloop = gen_label_rtx ();
4639
4640 gcc_assert (!target || register_operand (target, VOIDmode));
4641 gcc_assert (MEM_P (mem));
4642
4643 init_alignment_context (&ac, mem, mode);
4644
4645 /* Shift val to the correct bit positions.
4646 Preserve "icm", but prevent "ex icm". */
4647 if (!(ac.aligned && code == SET && MEM_P (val)))
4648 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4649
4650 /* Further preparation insns. */
4651 if (code == PLUS || code == MINUS)
4652 emit_move_insn (orig, val);
4653 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4654 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4655 NULL_RTX, 1, OPTAB_DIRECT);
4656
4657 /* Load full word. Subsequent loads are performed by CS. */
4658 cmp = force_reg (SImode, ac.memsi);
4659
4660 /* Start CS loop. */
4661 emit_label (csloop);
4662 emit_move_insn (new_rtx, cmp);
4663
4664 /* Patch new with val at correct position. */
4665 switch (code)
4666 {
4667 case PLUS:
4668 case MINUS:
4669 val = expand_simple_binop (SImode, code, new_rtx, orig,
4670 NULL_RTX, 1, OPTAB_DIRECT);
4671 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4672 NULL_RTX, 1, OPTAB_DIRECT);
4673 /* FALLTHRU */
4674 case SET:
4675 if (ac.aligned && MEM_P (val))
4676 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4677 else
4678 {
4679 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4680 NULL_RTX, 1, OPTAB_DIRECT);
4681 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4682 NULL_RTX, 1, OPTAB_DIRECT);
4683 }
4684 break;
4685 case AND:
4686 case IOR:
4687 case XOR:
4688 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4689 NULL_RTX, 1, OPTAB_DIRECT);
4690 break;
4691 case MULT: /* NAND */
4692 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4693 NULL_RTX, 1, OPTAB_DIRECT);
4694 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4695 NULL_RTX, 1, OPTAB_DIRECT);
4696 break;
4697 default:
4698 gcc_unreachable ();
4699 }
4700
4701 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4702 ac.memsi, cmp, new_rtx));
4703
4704 /* Return the correct part of the bitfield. */
4705 if (target)
4706 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4707 after ? new_rtx : cmp, ac.shift,
4708 NULL_RTX, 1, OPTAB_DIRECT), 1);
4709 }
4710
4711 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4712 We need to emit DTP-relative relocations. */
4713
4714 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4715
4716 static void
4717 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4718 {
4719 switch (size)
4720 {
4721 case 4:
4722 fputs ("\t.long\t", file);
4723 break;
4724 case 8:
4725 fputs ("\t.quad\t", file);
4726 break;
4727 default:
4728 gcc_unreachable ();
4729 }
4730 output_addr_const (file, x);
4731 fputs ("@DTPOFF", file);
4732 }
4733
4734 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4735 /* Implement TARGET_MANGLE_TYPE. */
4736
4737 static const char *
4738 s390_mangle_type (const_tree type)
4739 {
4740 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4741 && TARGET_LONG_DOUBLE_128)
4742 return "g";
4743
4744 /* For all other types, use normal C++ mangling. */
4745 return NULL;
4746 }
4747 #endif
4748
4749 /* In the name of slightly smaller debug output, and to cater to
4750 general assembler lossage, recognize various UNSPEC sequences
4751 and turn them back into a direct symbol reference. */
4752
4753 static rtx
4754 s390_delegitimize_address (rtx orig_x)
4755 {
4756 rtx x = orig_x, y;
4757
4758 if (GET_CODE (x) != MEM)
4759 return orig_x;
4760
4761 x = XEXP (x, 0);
4762 if (GET_CODE (x) == PLUS
4763 && GET_CODE (XEXP (x, 1)) == CONST
4764 && GET_CODE (XEXP (x, 0)) == REG
4765 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4766 {
4767 y = XEXP (XEXP (x, 1), 0);
4768 if (GET_CODE (y) == UNSPEC
4769 && XINT (y, 1) == UNSPEC_GOT)
4770 return XVECEXP (y, 0, 0);
4771 return orig_x;
4772 }
4773
4774 if (GET_CODE (x) == CONST)
4775 {
4776 y = XEXP (x, 0);
4777 if (GET_CODE (y) == UNSPEC
4778 && XINT (y, 1) == UNSPEC_GOTENT)
4779 return XVECEXP (y, 0, 0);
4780 return orig_x;
4781 }
4782
4783 return orig_x;
4784 }
4785
4786 /* Output operand OP to stdio stream FILE.
4787 OP is an address (register + offset) which is not used to address data;
4788 instead the rightmost bits are interpreted as the value. */
4789
4790 static void
4791 print_shift_count_operand (FILE *file, rtx op)
4792 {
4793 HOST_WIDE_INT offset;
4794 rtx base;
4795
4796 /* Extract base register and offset. */
4797 if (!s390_decompose_shift_count (op, &base, &offset))
4798 gcc_unreachable ();
4799
4800 /* Sanity check. */
4801 if (base)
4802 {
4803 gcc_assert (GET_CODE (base) == REG);
4804 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4805 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4806 }
4807
4808 /* Offsets are constricted to twelve bits. */
4809 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4810 if (base)
4811 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4812 }
4813
4814 /* See 'get_some_local_dynamic_name'. */
4815
4816 static int
4817 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4818 {
4819 rtx x = *px;
4820
4821 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4822 {
4823 x = get_pool_constant (x);
4824 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4825 }
4826
4827 if (GET_CODE (x) == SYMBOL_REF
4828 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4829 {
4830 cfun->machine->some_ld_name = XSTR (x, 0);
4831 return 1;
4832 }
4833
4834 return 0;
4835 }
4836
4837 /* Locate some local-dynamic symbol still in use by this function
4838 so that we can print its name in local-dynamic base patterns. */
4839
4840 static const char *
4841 get_some_local_dynamic_name (void)
4842 {
4843 rtx insn;
4844
4845 if (cfun->machine->some_ld_name)
4846 return cfun->machine->some_ld_name;
4847
4848 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4849 if (INSN_P (insn)
4850 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4851 return cfun->machine->some_ld_name;
4852
4853 gcc_unreachable ();
4854 }
4855
4856 /* Output machine-dependent UNSPECs occurring in address constant X
4857 in assembler syntax to stdio stream FILE. Returns true if the
4858 constant X could be recognized, false otherwise. */
4859
4860 bool
4861 s390_output_addr_const_extra (FILE *file, rtx x)
4862 {
4863 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4864 switch (XINT (x, 1))
4865 {
4866 case UNSPEC_GOTENT:
4867 output_addr_const (file, XVECEXP (x, 0, 0));
4868 fprintf (file, "@GOTENT");
4869 return true;
4870 case UNSPEC_GOT:
4871 output_addr_const (file, XVECEXP (x, 0, 0));
4872 fprintf (file, "@GOT");
4873 return true;
4874 case UNSPEC_GOTOFF:
4875 output_addr_const (file, XVECEXP (x, 0, 0));
4876 fprintf (file, "@GOTOFF");
4877 return true;
4878 case UNSPEC_PLT:
4879 output_addr_const (file, XVECEXP (x, 0, 0));
4880 fprintf (file, "@PLT");
4881 return true;
4882 case UNSPEC_PLTOFF:
4883 output_addr_const (file, XVECEXP (x, 0, 0));
4884 fprintf (file, "@PLTOFF");
4885 return true;
4886 case UNSPEC_TLSGD:
4887 output_addr_const (file, XVECEXP (x, 0, 0));
4888 fprintf (file, "@TLSGD");
4889 return true;
4890 case UNSPEC_TLSLDM:
4891 assemble_name (file, get_some_local_dynamic_name ());
4892 fprintf (file, "@TLSLDM");
4893 return true;
4894 case UNSPEC_DTPOFF:
4895 output_addr_const (file, XVECEXP (x, 0, 0));
4896 fprintf (file, "@DTPOFF");
4897 return true;
4898 case UNSPEC_NTPOFF:
4899 output_addr_const (file, XVECEXP (x, 0, 0));
4900 fprintf (file, "@NTPOFF");
4901 return true;
4902 case UNSPEC_GOTNTPOFF:
4903 output_addr_const (file, XVECEXP (x, 0, 0));
4904 fprintf (file, "@GOTNTPOFF");
4905 return true;
4906 case UNSPEC_INDNTPOFF:
4907 output_addr_const (file, XVECEXP (x, 0, 0));
4908 fprintf (file, "@INDNTPOFF");
4909 return true;
4910 }
4911
4912 return false;
4913 }
4914
4915 /* Output address operand ADDR in assembler syntax to
4916 stdio stream FILE. */
4917
4918 void
4919 print_operand_address (FILE *file, rtx addr)
4920 {
4921 struct s390_address ad;
4922
4923 if (s390_symref_operand_p (addr, NULL, NULL))
4924 {
4925 gcc_assert (TARGET_Z10);
4926 output_addr_const (file, addr);
4927 return;
4928 }
4929
4930 if (!s390_decompose_address (addr, &ad)
4931 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4932 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4933 output_operand_lossage ("cannot decompose address");
4934
4935 if (ad.disp)
4936 output_addr_const (file, ad.disp);
4937 else
4938 fprintf (file, "0");
4939
4940 if (ad.base && ad.indx)
4941 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4942 reg_names[REGNO (ad.base)]);
4943 else if (ad.base)
4944 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4945 }
4946
4947 /* Output operand X in assembler syntax to stdio stream FILE.
4948 CODE specified the format flag. The following format flags
4949 are recognized:
4950
4951 'C': print opcode suffix for branch condition.
4952 'D': print opcode suffix for inverse branch condition.
4953 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4954 'G': print the size of the operand in bytes.
4955 'O': print only the displacement of a memory reference.
4956 'R': print only the base register of a memory reference.
4957 'S': print S-type memory reference (base+displacement).
4958 'N': print the second word of a DImode operand.
4959 'M': print the second word of a TImode operand.
4960 'Y': print shift count operand.
4961
4962 'b': print integer X as if it's an unsigned byte.
4963 'c': print integer X as if it's an signed byte.
4964 'x': print integer X as if it's an unsigned halfword.
4965 'h': print integer X as if it's a signed halfword.
4966 'i': print the first nonzero HImode part of X.
4967 'j': print the first HImode part unequal to -1 of X.
4968 'k': print the first nonzero SImode part of X.
4969 'm': print the first SImode part unequal to -1 of X.
4970 'o': print integer X as if it's an unsigned 32bit word. */
4971
4972 void
4973 print_operand (FILE *file, rtx x, int code)
4974 {
4975 switch (code)
4976 {
4977 case 'C':
4978 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4979 return;
4980
4981 case 'D':
4982 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4983 return;
4984
4985 case 'J':
4986 if (GET_CODE (x) == SYMBOL_REF)
4987 {
4988 fprintf (file, "%s", ":tls_load:");
4989 output_addr_const (file, x);
4990 }
4991 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4992 {
4993 fprintf (file, "%s", ":tls_gdcall:");
4994 output_addr_const (file, XVECEXP (x, 0, 0));
4995 }
4996 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4997 {
4998 fprintf (file, "%s", ":tls_ldcall:");
4999 assemble_name (file, get_some_local_dynamic_name ());
5000 }
5001 else
5002 gcc_unreachable ();
5003 return;
5004
5005 case 'G':
5006 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5007 return;
5008
5009 case 'O':
5010 {
5011 struct s390_address ad;
5012 int ret;
5013
5014 gcc_assert (GET_CODE (x) == MEM);
5015 ret = s390_decompose_address (XEXP (x, 0), &ad);
5016 gcc_assert (ret);
5017 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5018 gcc_assert (!ad.indx);
5019
5020 if (ad.disp)
5021 output_addr_const (file, ad.disp);
5022 else
5023 fprintf (file, "0");
5024 }
5025 return;
5026
5027 case 'R':
5028 {
5029 struct s390_address ad;
5030 int ret;
5031
5032 gcc_assert (GET_CODE (x) == MEM);
5033 ret = s390_decompose_address (XEXP (x, 0), &ad);
5034 gcc_assert (ret);
5035 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5036 gcc_assert (!ad.indx);
5037
5038 if (ad.base)
5039 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5040 else
5041 fprintf (file, "0");
5042 }
5043 return;
5044
5045 case 'S':
5046 {
5047 struct s390_address ad;
5048 int ret;
5049
5050 gcc_assert (GET_CODE (x) == MEM);
5051 ret = s390_decompose_address (XEXP (x, 0), &ad);
5052 gcc_assert (ret);
5053 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5054 gcc_assert (!ad.indx);
5055
5056 if (ad.disp)
5057 output_addr_const (file, ad.disp);
5058 else
5059 fprintf (file, "0");
5060
5061 if (ad.base)
5062 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5063 }
5064 return;
5065
5066 case 'N':
5067 if (GET_CODE (x) == REG)
5068 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5069 else if (GET_CODE (x) == MEM)
5070 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5071 else
5072 gcc_unreachable ();
5073 break;
5074
5075 case 'M':
5076 if (GET_CODE (x) == REG)
5077 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5078 else if (GET_CODE (x) == MEM)
5079 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5080 else
5081 gcc_unreachable ();
5082 break;
5083
5084 case 'Y':
5085 print_shift_count_operand (file, x);
5086 return;
5087 }
5088
5089 switch (GET_CODE (x))
5090 {
5091 case REG:
5092 fprintf (file, "%s", reg_names[REGNO (x)]);
5093 break;
5094
5095 case MEM:
5096 output_address (XEXP (x, 0));
5097 break;
5098
5099 case CONST:
5100 case CODE_LABEL:
5101 case LABEL_REF:
5102 case SYMBOL_REF:
5103 output_addr_const (file, x);
5104 break;
5105
5106 case CONST_INT:
5107 if (code == 'b')
5108 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5109 else if (code == 'c')
5110 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5111 else if (code == 'x')
5112 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5113 else if (code == 'h')
5114 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5115 else if (code == 'i')
5116 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5117 s390_extract_part (x, HImode, 0));
5118 else if (code == 'j')
5119 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5120 s390_extract_part (x, HImode, -1));
5121 else if (code == 'k')
5122 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5123 s390_extract_part (x, SImode, 0));
5124 else if (code == 'm')
5125 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5126 s390_extract_part (x, SImode, -1));
5127 else if (code == 'o')
5128 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5129 else
5130 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5131 break;
5132
5133 case CONST_DOUBLE:
5134 gcc_assert (GET_MODE (x) == VOIDmode);
5135 if (code == 'b')
5136 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5137 else if (code == 'x')
5138 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5139 else if (code == 'h')
5140 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5141 else
5142 gcc_unreachable ();
5143 break;
5144
5145 default:
5146 fatal_insn ("UNKNOWN in print_operand !?", x);
5147 break;
5148 }
5149 }
5150
5151 /* Target hook for assembling integer objects. We need to define it
5152 here to work a round a bug in some versions of GAS, which couldn't
5153 handle values smaller than INT_MIN when printed in decimal. */
5154
5155 static bool
5156 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5157 {
5158 if (size == 8 && aligned_p
5159 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5160 {
5161 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5162 INTVAL (x));
5163 return true;
5164 }
5165 return default_assemble_integer (x, size, aligned_p);
5166 }
5167
5168 /* Returns true if register REGNO is used for forming
5169 a memory address in expression X. */
5170
5171 static bool
5172 reg_used_in_mem_p (int regno, rtx x)
5173 {
5174 enum rtx_code code = GET_CODE (x);
5175 int i, j;
5176 const char *fmt;
5177
5178 if (code == MEM)
5179 {
5180 if (refers_to_regno_p (regno, regno+1,
5181 XEXP (x, 0), 0))
5182 return true;
5183 }
5184 else if (code == SET
5185 && GET_CODE (SET_DEST (x)) == PC)
5186 {
5187 if (refers_to_regno_p (regno, regno+1,
5188 SET_SRC (x), 0))
5189 return true;
5190 }
5191
5192 fmt = GET_RTX_FORMAT (code);
5193 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5194 {
5195 if (fmt[i] == 'e'
5196 && reg_used_in_mem_p (regno, XEXP (x, i)))
5197 return true;
5198
5199 else if (fmt[i] == 'E')
5200 for (j = 0; j < XVECLEN (x, i); j++)
5201 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5202 return true;
5203 }
5204 return false;
5205 }
5206
5207 /* Returns true if expression DEP_RTX sets an address register
5208 used by instruction INSN to address memory. */
5209
5210 static bool
5211 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5212 {
5213 rtx target, pat;
5214
5215 if (GET_CODE (dep_rtx) == INSN)
5216 dep_rtx = PATTERN (dep_rtx);
5217
5218 if (GET_CODE (dep_rtx) == SET)
5219 {
5220 target = SET_DEST (dep_rtx);
5221 if (GET_CODE (target) == STRICT_LOW_PART)
5222 target = XEXP (target, 0);
5223 while (GET_CODE (target) == SUBREG)
5224 target = SUBREG_REG (target);
5225
5226 if (GET_CODE (target) == REG)
5227 {
5228 int regno = REGNO (target);
5229
5230 if (s390_safe_attr_type (insn) == TYPE_LA)
5231 {
5232 pat = PATTERN (insn);
5233 if (GET_CODE (pat) == PARALLEL)
5234 {
5235 gcc_assert (XVECLEN (pat, 0) == 2);
5236 pat = XVECEXP (pat, 0, 0);
5237 }
5238 gcc_assert (GET_CODE (pat) == SET);
5239 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5240 }
5241 else if (get_attr_atype (insn) == ATYPE_AGEN)
5242 return reg_used_in_mem_p (regno, PATTERN (insn));
5243 }
5244 }
5245 return false;
5246 }
5247
5248 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5249
5250 int
5251 s390_agen_dep_p (rtx dep_insn, rtx insn)
5252 {
5253 rtx dep_rtx = PATTERN (dep_insn);
5254 int i;
5255
5256 if (GET_CODE (dep_rtx) == SET
5257 && addr_generation_dependency_p (dep_rtx, insn))
5258 return 1;
5259 else if (GET_CODE (dep_rtx) == PARALLEL)
5260 {
5261 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5262 {
5263 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5264 return 1;
5265 }
5266 }
5267 return 0;
5268 }
5269
5270
5271 /* A C statement (sans semicolon) to update the integer scheduling priority
5272 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5273 reduce the priority to execute INSN later. Do not define this macro if
5274 you do not need to adjust the scheduling priorities of insns.
5275
5276 A STD instruction should be scheduled earlier,
5277 in order to use the bypass. */
5278
5279 static int
5280 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5281 {
5282 if (! INSN_P (insn))
5283 return priority;
5284
5285 if (s390_tune != PROCESSOR_2084_Z990
5286 && s390_tune != PROCESSOR_2094_Z9_109)
5287 return priority;
5288
5289 switch (s390_safe_attr_type (insn))
5290 {
5291 case TYPE_FSTOREDF:
5292 case TYPE_FSTORESF:
5293 priority = priority << 3;
5294 break;
5295 case TYPE_STORE:
5296 case TYPE_STM:
5297 priority = priority << 1;
5298 break;
5299 default:
5300 break;
5301 }
5302 return priority;
5303 }
5304
5305 /* The number of instructions that can be issued per cycle. */
5306
5307 static int
5308 s390_issue_rate (void)
5309 {
5310 switch (s390_tune)
5311 {
5312 case PROCESSOR_2084_Z990:
5313 case PROCESSOR_2094_Z9_109:
5314 return 3;
5315 case PROCESSOR_2097_Z10:
5316 return 2;
5317 default:
5318 return 1;
5319 }
5320 }
5321
5322 static int
5323 s390_first_cycle_multipass_dfa_lookahead (void)
5324 {
5325 return 4;
5326 }
5327
5328
5329 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5330 Fix up MEMs as required. */
5331
5332 static void
5333 annotate_constant_pool_refs (rtx *x)
5334 {
5335 int i, j;
5336 const char *fmt;
5337
5338 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5339 || !CONSTANT_POOL_ADDRESS_P (*x));
5340
5341 /* Literal pool references can only occur inside a MEM ... */
5342 if (GET_CODE (*x) == MEM)
5343 {
5344 rtx memref = XEXP (*x, 0);
5345
5346 if (GET_CODE (memref) == SYMBOL_REF
5347 && CONSTANT_POOL_ADDRESS_P (memref))
5348 {
5349 rtx base = cfun->machine->base_reg;
5350 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5351 UNSPEC_LTREF);
5352
5353 *x = replace_equiv_address (*x, addr);
5354 return;
5355 }
5356
5357 if (GET_CODE (memref) == CONST
5358 && GET_CODE (XEXP (memref, 0)) == PLUS
5359 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5360 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5361 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5362 {
5363 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5364 rtx sym = XEXP (XEXP (memref, 0), 0);
5365 rtx base = cfun->machine->base_reg;
5366 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5367 UNSPEC_LTREF);
5368
5369 *x = replace_equiv_address (*x, plus_constant (addr, off));
5370 return;
5371 }
5372 }
5373
5374 /* ... or a load-address type pattern. */
5375 if (GET_CODE (*x) == SET)
5376 {
5377 rtx addrref = SET_SRC (*x);
5378
5379 if (GET_CODE (addrref) == SYMBOL_REF
5380 && CONSTANT_POOL_ADDRESS_P (addrref))
5381 {
5382 rtx base = cfun->machine->base_reg;
5383 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5384 UNSPEC_LTREF);
5385
5386 SET_SRC (*x) = addr;
5387 return;
5388 }
5389
5390 if (GET_CODE (addrref) == CONST
5391 && GET_CODE (XEXP (addrref, 0)) == PLUS
5392 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5393 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5394 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5395 {
5396 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5397 rtx sym = XEXP (XEXP (addrref, 0), 0);
5398 rtx base = cfun->machine->base_reg;
5399 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5400 UNSPEC_LTREF);
5401
5402 SET_SRC (*x) = plus_constant (addr, off);
5403 return;
5404 }
5405 }
5406
5407 /* Annotate LTREL_BASE as well. */
5408 if (GET_CODE (*x) == UNSPEC
5409 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5410 {
5411 rtx base = cfun->machine->base_reg;
5412 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5413 UNSPEC_LTREL_BASE);
5414 return;
5415 }
5416
5417 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5418 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5419 {
5420 if (fmt[i] == 'e')
5421 {
5422 annotate_constant_pool_refs (&XEXP (*x, i));
5423 }
5424 else if (fmt[i] == 'E')
5425 {
5426 for (j = 0; j < XVECLEN (*x, i); j++)
5427 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5428 }
5429 }
5430 }
5431
5432 /* Split all branches that exceed the maximum distance.
5433 Returns true if this created a new literal pool entry. */
5434
5435 static int
5436 s390_split_branches (void)
5437 {
5438 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5439 int new_literal = 0, ret;
5440 rtx insn, pat, tmp, target;
5441 rtx *label;
5442
5443 /* We need correct insn addresses. */
5444
5445 shorten_branches (get_insns ());
5446
5447 /* Find all branches that exceed 64KB, and split them. */
5448
5449 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5450 {
5451 if (GET_CODE (insn) != JUMP_INSN)
5452 continue;
5453
5454 pat = PATTERN (insn);
5455 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5456 pat = XVECEXP (pat, 0, 0);
5457 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5458 continue;
5459
5460 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5461 {
5462 label = &SET_SRC (pat);
5463 }
5464 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5465 {
5466 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5467 label = &XEXP (SET_SRC (pat), 1);
5468 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5469 label = &XEXP (SET_SRC (pat), 2);
5470 else
5471 continue;
5472 }
5473 else
5474 continue;
5475
5476 if (get_attr_length (insn) <= 4)
5477 continue;
5478
5479 /* We are going to use the return register as scratch register,
5480 make sure it will be saved/restored by the prologue/epilogue. */
5481 cfun_frame_layout.save_return_addr_p = 1;
5482
5483 if (!flag_pic)
5484 {
5485 new_literal = 1;
5486 tmp = force_const_mem (Pmode, *label);
5487 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5488 INSN_ADDRESSES_NEW (tmp, -1);
5489 annotate_constant_pool_refs (&PATTERN (tmp));
5490
5491 target = temp_reg;
5492 }
5493 else
5494 {
5495 new_literal = 1;
5496 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5497 UNSPEC_LTREL_OFFSET);
5498 target = gen_rtx_CONST (Pmode, target);
5499 target = force_const_mem (Pmode, target);
5500 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5501 INSN_ADDRESSES_NEW (tmp, -1);
5502 annotate_constant_pool_refs (&PATTERN (tmp));
5503
5504 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5505 cfun->machine->base_reg),
5506 UNSPEC_LTREL_BASE);
5507 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5508 }
5509
5510 ret = validate_change (insn, label, target, 0);
5511 gcc_assert (ret);
5512 }
5513
5514 return new_literal;
5515 }
5516
5517
5518 /* Find an annotated literal pool symbol referenced in RTX X,
5519 and store it at REF. Will abort if X contains references to
5520 more than one such pool symbol; multiple references to the same
5521 symbol are allowed, however.
5522
5523 The rtx pointed to by REF must be initialized to NULL_RTX
5524 by the caller before calling this routine. */
5525
5526 static void
5527 find_constant_pool_ref (rtx x, rtx *ref)
5528 {
5529 int i, j;
5530 const char *fmt;
5531
5532 /* Ignore LTREL_BASE references. */
5533 if (GET_CODE (x) == UNSPEC
5534 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5535 return;
5536 /* Likewise POOL_ENTRY insns. */
5537 if (GET_CODE (x) == UNSPEC_VOLATILE
5538 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5539 return;
5540
5541 gcc_assert (GET_CODE (x) != SYMBOL_REF
5542 || !CONSTANT_POOL_ADDRESS_P (x));
5543
5544 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5545 {
5546 rtx sym = XVECEXP (x, 0, 0);
5547 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5548 && CONSTANT_POOL_ADDRESS_P (sym));
5549
5550 if (*ref == NULL_RTX)
5551 *ref = sym;
5552 else
5553 gcc_assert (*ref == sym);
5554
5555 return;
5556 }
5557
5558 fmt = GET_RTX_FORMAT (GET_CODE (x));
5559 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5560 {
5561 if (fmt[i] == 'e')
5562 {
5563 find_constant_pool_ref (XEXP (x, i), ref);
5564 }
5565 else if (fmt[i] == 'E')
5566 {
5567 for (j = 0; j < XVECLEN (x, i); j++)
5568 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5569 }
5570 }
5571 }
5572
5573 /* Replace every reference to the annotated literal pool
5574 symbol REF in X by its base plus OFFSET. */
5575
5576 static void
5577 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5578 {
5579 int i, j;
5580 const char *fmt;
5581
5582 gcc_assert (*x != ref);
5583
5584 if (GET_CODE (*x) == UNSPEC
5585 && XINT (*x, 1) == UNSPEC_LTREF
5586 && XVECEXP (*x, 0, 0) == ref)
5587 {
5588 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5589 return;
5590 }
5591
5592 if (GET_CODE (*x) == PLUS
5593 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5594 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5595 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5596 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5597 {
5598 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5599 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5600 return;
5601 }
5602
5603 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5604 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5605 {
5606 if (fmt[i] == 'e')
5607 {
5608 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5609 }
5610 else if (fmt[i] == 'E')
5611 {
5612 for (j = 0; j < XVECLEN (*x, i); j++)
5613 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5614 }
5615 }
5616 }
5617
5618 /* Check whether X contains an UNSPEC_LTREL_BASE.
5619 Return its constant pool symbol if found, NULL_RTX otherwise. */
5620
5621 static rtx
5622 find_ltrel_base (rtx x)
5623 {
5624 int i, j;
5625 const char *fmt;
5626
5627 if (GET_CODE (x) == UNSPEC
5628 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5629 return XVECEXP (x, 0, 0);
5630
5631 fmt = GET_RTX_FORMAT (GET_CODE (x));
5632 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5633 {
5634 if (fmt[i] == 'e')
5635 {
5636 rtx fnd = find_ltrel_base (XEXP (x, i));
5637 if (fnd)
5638 return fnd;
5639 }
5640 else if (fmt[i] == 'E')
5641 {
5642 for (j = 0; j < XVECLEN (x, i); j++)
5643 {
5644 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5645 if (fnd)
5646 return fnd;
5647 }
5648 }
5649 }
5650
5651 return NULL_RTX;
5652 }
5653
5654 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5655
5656 static void
5657 replace_ltrel_base (rtx *x)
5658 {
5659 int i, j;
5660 const char *fmt;
5661
5662 if (GET_CODE (*x) == UNSPEC
5663 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5664 {
5665 *x = XVECEXP (*x, 0, 1);
5666 return;
5667 }
5668
5669 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5670 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5671 {
5672 if (fmt[i] == 'e')
5673 {
5674 replace_ltrel_base (&XEXP (*x, i));
5675 }
5676 else if (fmt[i] == 'E')
5677 {
5678 for (j = 0; j < XVECLEN (*x, i); j++)
5679 replace_ltrel_base (&XVECEXP (*x, i, j));
5680 }
5681 }
5682 }
5683
5684
5685 /* We keep a list of constants which we have to add to internal
5686 constant tables in the middle of large functions. */
5687
5688 #define NR_C_MODES 11
5689 enum machine_mode constant_modes[NR_C_MODES] =
5690 {
5691 TFmode, TImode, TDmode,
5692 DFmode, DImode, DDmode,
5693 SFmode, SImode, SDmode,
5694 HImode,
5695 QImode
5696 };
5697
5698 struct constant
5699 {
5700 struct constant *next;
5701 rtx value;
5702 rtx label;
5703 };
5704
5705 struct constant_pool
5706 {
5707 struct constant_pool *next;
5708 rtx first_insn;
5709 rtx pool_insn;
5710 bitmap insns;
5711 rtx emit_pool_after;
5712
5713 struct constant *constants[NR_C_MODES];
5714 struct constant *execute;
5715 rtx label;
5716 int size;
5717 };
5718
5719 /* Allocate new constant_pool structure. */
5720
5721 static struct constant_pool *
5722 s390_alloc_pool (void)
5723 {
5724 struct constant_pool *pool;
5725 int i;
5726
5727 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5728 pool->next = NULL;
5729 for (i = 0; i < NR_C_MODES; i++)
5730 pool->constants[i] = NULL;
5731
5732 pool->execute = NULL;
5733 pool->label = gen_label_rtx ();
5734 pool->first_insn = NULL_RTX;
5735 pool->pool_insn = NULL_RTX;
5736 pool->insns = BITMAP_ALLOC (NULL);
5737 pool->size = 0;
5738 pool->emit_pool_after = NULL_RTX;
5739
5740 return pool;
5741 }
5742
5743 /* Create new constant pool covering instructions starting at INSN
5744 and chain it to the end of POOL_LIST. */
5745
5746 static struct constant_pool *
5747 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5748 {
5749 struct constant_pool *pool, **prev;
5750
5751 pool = s390_alloc_pool ();
5752 pool->first_insn = insn;
5753
5754 for (prev = pool_list; *prev; prev = &(*prev)->next)
5755 ;
5756 *prev = pool;
5757
5758 return pool;
5759 }
5760
5761 /* End range of instructions covered by POOL at INSN and emit
5762 placeholder insn representing the pool. */
5763
5764 static void
5765 s390_end_pool (struct constant_pool *pool, rtx insn)
5766 {
5767 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5768
5769 if (!insn)
5770 insn = get_last_insn ();
5771
5772 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5773 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5774 }
5775
5776 /* Add INSN to the list of insns covered by POOL. */
5777
5778 static void
5779 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5780 {
5781 bitmap_set_bit (pool->insns, INSN_UID (insn));
5782 }
5783
5784 /* Return pool out of POOL_LIST that covers INSN. */
5785
5786 static struct constant_pool *
5787 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5788 {
5789 struct constant_pool *pool;
5790
5791 for (pool = pool_list; pool; pool = pool->next)
5792 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5793 break;
5794
5795 return pool;
5796 }
5797
5798 /* Add constant VAL of mode MODE to the constant pool POOL. */
5799
5800 static void
5801 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5802 {
5803 struct constant *c;
5804 int i;
5805
5806 for (i = 0; i < NR_C_MODES; i++)
5807 if (constant_modes[i] == mode)
5808 break;
5809 gcc_assert (i != NR_C_MODES);
5810
5811 for (c = pool->constants[i]; c != NULL; c = c->next)
5812 if (rtx_equal_p (val, c->value))
5813 break;
5814
5815 if (c == NULL)
5816 {
5817 c = (struct constant *) xmalloc (sizeof *c);
5818 c->value = val;
5819 c->label = gen_label_rtx ();
5820 c->next = pool->constants[i];
5821 pool->constants[i] = c;
5822 pool->size += GET_MODE_SIZE (mode);
5823 }
5824 }
5825
5826 /* Find constant VAL of mode MODE in the constant pool POOL.
5827 Return an RTX describing the distance from the start of
5828 the pool to the location of the new constant. */
5829
5830 static rtx
5831 s390_find_constant (struct constant_pool *pool, rtx val,
5832 enum machine_mode mode)
5833 {
5834 struct constant *c;
5835 rtx offset;
5836 int i;
5837
5838 for (i = 0; i < NR_C_MODES; i++)
5839 if (constant_modes[i] == mode)
5840 break;
5841 gcc_assert (i != NR_C_MODES);
5842
5843 for (c = pool->constants[i]; c != NULL; c = c->next)
5844 if (rtx_equal_p (val, c->value))
5845 break;
5846
5847 gcc_assert (c);
5848
5849 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5850 gen_rtx_LABEL_REF (Pmode, pool->label));
5851 offset = gen_rtx_CONST (Pmode, offset);
5852 return offset;
5853 }
5854
5855 /* Check whether INSN is an execute. Return the label_ref to its
5856 execute target template if so, NULL_RTX otherwise. */
5857
5858 static rtx
5859 s390_execute_label (rtx insn)
5860 {
5861 if (GET_CODE (insn) == INSN
5862 && GET_CODE (PATTERN (insn)) == PARALLEL
5863 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5864 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5865 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5866
5867 return NULL_RTX;
5868 }
5869
5870 /* Add execute target for INSN to the constant pool POOL. */
5871
5872 static void
5873 s390_add_execute (struct constant_pool *pool, rtx insn)
5874 {
5875 struct constant *c;
5876
5877 for (c = pool->execute; c != NULL; c = c->next)
5878 if (INSN_UID (insn) == INSN_UID (c->value))
5879 break;
5880
5881 if (c == NULL)
5882 {
5883 c = (struct constant *) xmalloc (sizeof *c);
5884 c->value = insn;
5885 c->label = gen_label_rtx ();
5886 c->next = pool->execute;
5887 pool->execute = c;
5888 pool->size += 6;
5889 }
5890 }
5891
5892 /* Find execute target for INSN in the constant pool POOL.
5893 Return an RTX describing the distance from the start of
5894 the pool to the location of the execute target. */
5895
5896 static rtx
5897 s390_find_execute (struct constant_pool *pool, rtx insn)
5898 {
5899 struct constant *c;
5900 rtx offset;
5901
5902 for (c = pool->execute; c != NULL; c = c->next)
5903 if (INSN_UID (insn) == INSN_UID (c->value))
5904 break;
5905
5906 gcc_assert (c);
5907
5908 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5909 gen_rtx_LABEL_REF (Pmode, pool->label));
5910 offset = gen_rtx_CONST (Pmode, offset);
5911 return offset;
5912 }
5913
5914 /* For an execute INSN, extract the execute target template. */
5915
5916 static rtx
5917 s390_execute_target (rtx insn)
5918 {
5919 rtx pattern = PATTERN (insn);
5920 gcc_assert (s390_execute_label (insn));
5921
5922 if (XVECLEN (pattern, 0) == 2)
5923 {
5924 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5925 }
5926 else
5927 {
5928 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5929 int i;
5930
5931 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5932 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5933
5934 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5935 }
5936
5937 return pattern;
5938 }
5939
5940 /* Indicate that INSN cannot be duplicated. This is the case for
5941 execute insns that carry a unique label. */
5942
5943 static bool
5944 s390_cannot_copy_insn_p (rtx insn)
5945 {
5946 rtx label = s390_execute_label (insn);
5947 return label && label != const0_rtx;
5948 }
5949
5950 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5951 do not emit the pool base label. */
5952
5953 static void
5954 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5955 {
5956 struct constant *c;
5957 rtx insn = pool->pool_insn;
5958 int i;
5959
5960 /* Switch to rodata section. */
5961 if (TARGET_CPU_ZARCH)
5962 {
5963 insn = emit_insn_after (gen_pool_section_start (), insn);
5964 INSN_ADDRESSES_NEW (insn, -1);
5965 }
5966
5967 /* Ensure minimum pool alignment. */
5968 if (TARGET_CPU_ZARCH)
5969 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5970 else
5971 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5972 INSN_ADDRESSES_NEW (insn, -1);
5973
5974 /* Emit pool base label. */
5975 if (!remote_label)
5976 {
5977 insn = emit_label_after (pool->label, insn);
5978 INSN_ADDRESSES_NEW (insn, -1);
5979 }
5980
5981 /* Dump constants in descending alignment requirement order,
5982 ensuring proper alignment for every constant. */
5983 for (i = 0; i < NR_C_MODES; i++)
5984 for (c = pool->constants[i]; c; c = c->next)
5985 {
5986 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5987 rtx value = copy_rtx (c->value);
5988 if (GET_CODE (value) == CONST
5989 && GET_CODE (XEXP (value, 0)) == UNSPEC
5990 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5991 && XVECLEN (XEXP (value, 0), 0) == 1)
5992 {
5993 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5994 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5995 value = gen_rtx_CONST (VOIDmode, value);
5996 }
5997
5998 insn = emit_label_after (c->label, insn);
5999 INSN_ADDRESSES_NEW (insn, -1);
6000
6001 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6002 gen_rtvec (1, value),
6003 UNSPECV_POOL_ENTRY);
6004 insn = emit_insn_after (value, insn);
6005 INSN_ADDRESSES_NEW (insn, -1);
6006 }
6007
6008 /* Ensure minimum alignment for instructions. */
6009 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6010 INSN_ADDRESSES_NEW (insn, -1);
6011
6012 /* Output in-pool execute template insns. */
6013 for (c = pool->execute; c; c = c->next)
6014 {
6015 insn = emit_label_after (c->label, insn);
6016 INSN_ADDRESSES_NEW (insn, -1);
6017
6018 insn = emit_insn_after (s390_execute_target (c->value), insn);
6019 INSN_ADDRESSES_NEW (insn, -1);
6020 }
6021
6022 /* Switch back to previous section. */
6023 if (TARGET_CPU_ZARCH)
6024 {
6025 insn = emit_insn_after (gen_pool_section_end (), insn);
6026 INSN_ADDRESSES_NEW (insn, -1);
6027 }
6028
6029 insn = emit_barrier_after (insn);
6030 INSN_ADDRESSES_NEW (insn, -1);
6031
6032 /* Remove placeholder insn. */
6033 remove_insn (pool->pool_insn);
6034 }
6035
6036 /* Free all memory used by POOL. */
6037
6038 static void
6039 s390_free_pool (struct constant_pool *pool)
6040 {
6041 struct constant *c, *next;
6042 int i;
6043
6044 for (i = 0; i < NR_C_MODES; i++)
6045 for (c = pool->constants[i]; c; c = next)
6046 {
6047 next = c->next;
6048 free (c);
6049 }
6050
6051 for (c = pool->execute; c; c = next)
6052 {
6053 next = c->next;
6054 free (c);
6055 }
6056
6057 BITMAP_FREE (pool->insns);
6058 free (pool);
6059 }
6060
6061
6062 /* Collect main literal pool. Return NULL on overflow. */
6063
6064 static struct constant_pool *
6065 s390_mainpool_start (void)
6066 {
6067 struct constant_pool *pool;
6068 rtx insn;
6069
6070 pool = s390_alloc_pool ();
6071
6072 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6073 {
6074 if (GET_CODE (insn) == INSN
6075 && GET_CODE (PATTERN (insn)) == SET
6076 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6077 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6078 {
6079 gcc_assert (!pool->pool_insn);
6080 pool->pool_insn = insn;
6081 }
6082
6083 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6084 {
6085 s390_add_execute (pool, insn);
6086 }
6087 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6088 {
6089 rtx pool_ref = NULL_RTX;
6090 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6091 if (pool_ref)
6092 {
6093 rtx constant = get_pool_constant (pool_ref);
6094 enum machine_mode mode = get_pool_mode (pool_ref);
6095 s390_add_constant (pool, constant, mode);
6096 }
6097 }
6098
6099 /* If hot/cold partitioning is enabled we have to make sure that
6100 the literal pool is emitted in the same section where the
6101 initialization of the literal pool base pointer takes place.
6102 emit_pool_after is only used in the non-overflow case on non
6103 Z cpus where we can emit the literal pool at the end of the
6104 function body within the text section. */
6105 if (NOTE_P (insn)
6106 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6107 && !pool->emit_pool_after)
6108 pool->emit_pool_after = PREV_INSN (insn);
6109 }
6110
6111 gcc_assert (pool->pool_insn || pool->size == 0);
6112
6113 if (pool->size >= 4096)
6114 {
6115 /* We're going to chunkify the pool, so remove the main
6116 pool placeholder insn. */
6117 remove_insn (pool->pool_insn);
6118
6119 s390_free_pool (pool);
6120 pool = NULL;
6121 }
6122
6123 /* If the functions ends with the section where the literal pool
6124 should be emitted set the marker to its end. */
6125 if (pool && !pool->emit_pool_after)
6126 pool->emit_pool_after = get_last_insn ();
6127
6128 return pool;
6129 }
6130
6131 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6132 Modify the current function to output the pool constants as well as
6133 the pool register setup instruction. */
6134
6135 static void
6136 s390_mainpool_finish (struct constant_pool *pool)
6137 {
6138 rtx base_reg = cfun->machine->base_reg;
6139 rtx insn;
6140
6141 /* If the pool is empty, we're done. */
6142 if (pool->size == 0)
6143 {
6144 /* We don't actually need a base register after all. */
6145 cfun->machine->base_reg = NULL_RTX;
6146
6147 if (pool->pool_insn)
6148 remove_insn (pool->pool_insn);
6149 s390_free_pool (pool);
6150 return;
6151 }
6152
6153 /* We need correct insn addresses. */
6154 shorten_branches (get_insns ());
6155
6156 /* On zSeries, we use a LARL to load the pool register. The pool is
6157 located in the .rodata section, so we emit it after the function. */
6158 if (TARGET_CPU_ZARCH)
6159 {
6160 insn = gen_main_base_64 (base_reg, pool->label);
6161 insn = emit_insn_after (insn, pool->pool_insn);
6162 INSN_ADDRESSES_NEW (insn, -1);
6163 remove_insn (pool->pool_insn);
6164
6165 insn = get_last_insn ();
6166 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6167 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6168
6169 s390_dump_pool (pool, 0);
6170 }
6171
6172 /* On S/390, if the total size of the function's code plus literal pool
6173 does not exceed 4096 bytes, we use BASR to set up a function base
6174 pointer, and emit the literal pool at the end of the function. */
6175 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6176 + pool->size + 8 /* alignment slop */ < 4096)
6177 {
6178 insn = gen_main_base_31_small (base_reg, pool->label);
6179 insn = emit_insn_after (insn, pool->pool_insn);
6180 INSN_ADDRESSES_NEW (insn, -1);
6181 remove_insn (pool->pool_insn);
6182
6183 insn = emit_label_after (pool->label, insn);
6184 INSN_ADDRESSES_NEW (insn, -1);
6185
6186 /* emit_pool_after will be set by s390_mainpool_start to the
6187 last insn of the section where the literal pool should be
6188 emitted. */
6189 insn = pool->emit_pool_after;
6190
6191 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6192 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6193
6194 s390_dump_pool (pool, 1);
6195 }
6196
6197 /* Otherwise, we emit an inline literal pool and use BASR to branch
6198 over it, setting up the pool register at the same time. */
6199 else
6200 {
6201 rtx pool_end = gen_label_rtx ();
6202
6203 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6204 insn = emit_insn_after (insn, pool->pool_insn);
6205 INSN_ADDRESSES_NEW (insn, -1);
6206 remove_insn (pool->pool_insn);
6207
6208 insn = emit_label_after (pool->label, insn);
6209 INSN_ADDRESSES_NEW (insn, -1);
6210
6211 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6212 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6213
6214 insn = emit_label_after (pool_end, pool->pool_insn);
6215 INSN_ADDRESSES_NEW (insn, -1);
6216
6217 s390_dump_pool (pool, 1);
6218 }
6219
6220
6221 /* Replace all literal pool references. */
6222
6223 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6224 {
6225 if (INSN_P (insn))
6226 replace_ltrel_base (&PATTERN (insn));
6227
6228 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6229 {
6230 rtx addr, pool_ref = NULL_RTX;
6231 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6232 if (pool_ref)
6233 {
6234 if (s390_execute_label (insn))
6235 addr = s390_find_execute (pool, insn);
6236 else
6237 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6238 get_pool_mode (pool_ref));
6239
6240 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6241 INSN_CODE (insn) = -1;
6242 }
6243 }
6244 }
6245
6246
6247 /* Free the pool. */
6248 s390_free_pool (pool);
6249 }
6250
6251 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6252 We have decided we cannot use this pool, so revert all changes
6253 to the current function that were done by s390_mainpool_start. */
6254 static void
6255 s390_mainpool_cancel (struct constant_pool *pool)
6256 {
6257 /* We didn't actually change the instruction stream, so simply
6258 free the pool memory. */
6259 s390_free_pool (pool);
6260 }
6261
6262
6263 /* Chunkify the literal pool. */
6264
6265 #define S390_POOL_CHUNK_MIN 0xc00
6266 #define S390_POOL_CHUNK_MAX 0xe00
6267
6268 static struct constant_pool *
6269 s390_chunkify_start (void)
6270 {
6271 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6272 int extra_size = 0;
6273 bitmap far_labels;
6274 rtx pending_ltrel = NULL_RTX;
6275 rtx insn;
6276
6277 rtx (*gen_reload_base) (rtx, rtx) =
6278 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6279
6280
6281 /* We need correct insn addresses. */
6282
6283 shorten_branches (get_insns ());
6284
6285 /* Scan all insns and move literals to pool chunks. */
6286
6287 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6288 {
6289 bool section_switch_p = false;
6290
6291 /* Check for pending LTREL_BASE. */
6292 if (INSN_P (insn))
6293 {
6294 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6295 if (ltrel_base)
6296 {
6297 gcc_assert (ltrel_base == pending_ltrel);
6298 pending_ltrel = NULL_RTX;
6299 }
6300 }
6301
6302 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6303 {
6304 if (!curr_pool)
6305 curr_pool = s390_start_pool (&pool_list, insn);
6306
6307 s390_add_execute (curr_pool, insn);
6308 s390_add_pool_insn (curr_pool, insn);
6309 }
6310 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6311 {
6312 rtx pool_ref = NULL_RTX;
6313 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6314 if (pool_ref)
6315 {
6316 rtx constant = get_pool_constant (pool_ref);
6317 enum machine_mode mode = get_pool_mode (pool_ref);
6318
6319 if (!curr_pool)
6320 curr_pool = s390_start_pool (&pool_list, insn);
6321
6322 s390_add_constant (curr_pool, constant, mode);
6323 s390_add_pool_insn (curr_pool, insn);
6324
6325 /* Don't split the pool chunk between a LTREL_OFFSET load
6326 and the corresponding LTREL_BASE. */
6327 if (GET_CODE (constant) == CONST
6328 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6329 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6330 {
6331 gcc_assert (!pending_ltrel);
6332 pending_ltrel = pool_ref;
6333 }
6334 }
6335 }
6336
6337 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6338 {
6339 if (curr_pool)
6340 s390_add_pool_insn (curr_pool, insn);
6341 /* An LTREL_BASE must follow within the same basic block. */
6342 gcc_assert (!pending_ltrel);
6343 }
6344
6345 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6346 section_switch_p = true;
6347
6348 if (!curr_pool
6349 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6350 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6351 continue;
6352
6353 if (TARGET_CPU_ZARCH)
6354 {
6355 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6356 continue;
6357
6358 s390_end_pool (curr_pool, NULL_RTX);
6359 curr_pool = NULL;
6360 }
6361 else
6362 {
6363 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6364 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6365 + extra_size;
6366
6367 /* We will later have to insert base register reload insns.
6368 Those will have an effect on code size, which we need to
6369 consider here. This calculation makes rather pessimistic
6370 worst-case assumptions. */
6371 if (GET_CODE (insn) == CODE_LABEL)
6372 extra_size += 6;
6373
6374 if (chunk_size < S390_POOL_CHUNK_MIN
6375 && curr_pool->size < S390_POOL_CHUNK_MIN
6376 && !section_switch_p)
6377 continue;
6378
6379 /* Pool chunks can only be inserted after BARRIERs ... */
6380 if (GET_CODE (insn) == BARRIER)
6381 {
6382 s390_end_pool (curr_pool, insn);
6383 curr_pool = NULL;
6384 extra_size = 0;
6385 }
6386
6387 /* ... so if we don't find one in time, create one. */
6388 else if (chunk_size > S390_POOL_CHUNK_MAX
6389 || curr_pool->size > S390_POOL_CHUNK_MAX
6390 || section_switch_p)
6391 {
6392 rtx label, jump, barrier;
6393
6394 if (!section_switch_p)
6395 {
6396 /* We can insert the barrier only after a 'real' insn. */
6397 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6398 continue;
6399 if (get_attr_length (insn) == 0)
6400 continue;
6401 /* Don't separate LTREL_BASE from the corresponding
6402 LTREL_OFFSET load. */
6403 if (pending_ltrel)
6404 continue;
6405 }
6406 else
6407 {
6408 gcc_assert (!pending_ltrel);
6409
6410 /* The old pool has to end before the section switch
6411 note in order to make it part of the current
6412 section. */
6413 insn = PREV_INSN (insn);
6414 }
6415
6416 label = gen_label_rtx ();
6417 jump = emit_jump_insn_after (gen_jump (label), insn);
6418 barrier = emit_barrier_after (jump);
6419 insn = emit_label_after (label, barrier);
6420 JUMP_LABEL (jump) = label;
6421 LABEL_NUSES (label) = 1;
6422
6423 INSN_ADDRESSES_NEW (jump, -1);
6424 INSN_ADDRESSES_NEW (barrier, -1);
6425 INSN_ADDRESSES_NEW (insn, -1);
6426
6427 s390_end_pool (curr_pool, barrier);
6428 curr_pool = NULL;
6429 extra_size = 0;
6430 }
6431 }
6432 }
6433
6434 if (curr_pool)
6435 s390_end_pool (curr_pool, NULL_RTX);
6436 gcc_assert (!pending_ltrel);
6437
6438 /* Find all labels that are branched into
6439 from an insn belonging to a different chunk. */
6440
6441 far_labels = BITMAP_ALLOC (NULL);
6442
6443 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6444 {
6445 /* Labels marked with LABEL_PRESERVE_P can be target
6446 of non-local jumps, so we have to mark them.
6447 The same holds for named labels.
6448
6449 Don't do that, however, if it is the label before
6450 a jump table. */
6451
6452 if (GET_CODE (insn) == CODE_LABEL
6453 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6454 {
6455 rtx vec_insn = next_real_insn (insn);
6456 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6457 PATTERN (vec_insn) : NULL_RTX;
6458 if (!vec_pat
6459 || !(GET_CODE (vec_pat) == ADDR_VEC
6460 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6461 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6462 }
6463
6464 /* If we have a direct jump (conditional or unconditional)
6465 or a casesi jump, check all potential targets. */
6466 else if (GET_CODE (insn) == JUMP_INSN)
6467 {
6468 rtx pat = PATTERN (insn);
6469 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6470 pat = XVECEXP (pat, 0, 0);
6471
6472 if (GET_CODE (pat) == SET)
6473 {
6474 rtx label = JUMP_LABEL (insn);
6475 if (label)
6476 {
6477 if (s390_find_pool (pool_list, label)
6478 != s390_find_pool (pool_list, insn))
6479 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6480 }
6481 }
6482 else if (GET_CODE (pat) == PARALLEL
6483 && XVECLEN (pat, 0) == 2
6484 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6485 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6486 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6487 {
6488 /* Find the jump table used by this casesi jump. */
6489 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6490 rtx vec_insn = next_real_insn (vec_label);
6491 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6492 PATTERN (vec_insn) : NULL_RTX;
6493 if (vec_pat
6494 && (GET_CODE (vec_pat) == ADDR_VEC
6495 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6496 {
6497 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6498
6499 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6500 {
6501 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6502
6503 if (s390_find_pool (pool_list, label)
6504 != s390_find_pool (pool_list, insn))
6505 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6506 }
6507 }
6508 }
6509 }
6510 }
6511
6512 /* Insert base register reload insns before every pool. */
6513
6514 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6515 {
6516 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6517 curr_pool->label);
6518 rtx insn = curr_pool->first_insn;
6519 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6520 }
6521
6522 /* Insert base register reload insns at every far label. */
6523
6524 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6525 if (GET_CODE (insn) == CODE_LABEL
6526 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6527 {
6528 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6529 if (pool)
6530 {
6531 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6532 pool->label);
6533 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6534 }
6535 }
6536
6537
6538 BITMAP_FREE (far_labels);
6539
6540
6541 /* Recompute insn addresses. */
6542
6543 init_insn_lengths ();
6544 shorten_branches (get_insns ());
6545
6546 return pool_list;
6547 }
6548
6549 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6550 After we have decided to use this list, finish implementing
6551 all changes to the current function as required. */
6552
6553 static void
6554 s390_chunkify_finish (struct constant_pool *pool_list)
6555 {
6556 struct constant_pool *curr_pool = NULL;
6557 rtx insn;
6558
6559
6560 /* Replace all literal pool references. */
6561
6562 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6563 {
6564 if (INSN_P (insn))
6565 replace_ltrel_base (&PATTERN (insn));
6566
6567 curr_pool = s390_find_pool (pool_list, insn);
6568 if (!curr_pool)
6569 continue;
6570
6571 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6572 {
6573 rtx addr, pool_ref = NULL_RTX;
6574 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6575 if (pool_ref)
6576 {
6577 if (s390_execute_label (insn))
6578 addr = s390_find_execute (curr_pool, insn);
6579 else
6580 addr = s390_find_constant (curr_pool,
6581 get_pool_constant (pool_ref),
6582 get_pool_mode (pool_ref));
6583
6584 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6585 INSN_CODE (insn) = -1;
6586 }
6587 }
6588 }
6589
6590 /* Dump out all literal pools. */
6591
6592 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6593 s390_dump_pool (curr_pool, 0);
6594
6595 /* Free pool list. */
6596
6597 while (pool_list)
6598 {
6599 struct constant_pool *next = pool_list->next;
6600 s390_free_pool (pool_list);
6601 pool_list = next;
6602 }
6603 }
6604
6605 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6606 We have decided we cannot use this list, so revert all changes
6607 to the current function that were done by s390_chunkify_start. */
6608
6609 static void
6610 s390_chunkify_cancel (struct constant_pool *pool_list)
6611 {
6612 struct constant_pool *curr_pool = NULL;
6613 rtx insn;
6614
6615 /* Remove all pool placeholder insns. */
6616
6617 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6618 {
6619 /* Did we insert an extra barrier? Remove it. */
6620 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6621 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6622 rtx label = NEXT_INSN (curr_pool->pool_insn);
6623
6624 if (jump && GET_CODE (jump) == JUMP_INSN
6625 && barrier && GET_CODE (barrier) == BARRIER
6626 && label && GET_CODE (label) == CODE_LABEL
6627 && GET_CODE (PATTERN (jump)) == SET
6628 && SET_DEST (PATTERN (jump)) == pc_rtx
6629 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6630 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6631 {
6632 remove_insn (jump);
6633 remove_insn (barrier);
6634 remove_insn (label);
6635 }
6636
6637 remove_insn (curr_pool->pool_insn);
6638 }
6639
6640 /* Remove all base register reload insns. */
6641
6642 for (insn = get_insns (); insn; )
6643 {
6644 rtx next_insn = NEXT_INSN (insn);
6645
6646 if (GET_CODE (insn) == INSN
6647 && GET_CODE (PATTERN (insn)) == SET
6648 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6649 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6650 remove_insn (insn);
6651
6652 insn = next_insn;
6653 }
6654
6655 /* Free pool list. */
6656
6657 while (pool_list)
6658 {
6659 struct constant_pool *next = pool_list->next;
6660 s390_free_pool (pool_list);
6661 pool_list = next;
6662 }
6663 }
6664
6665
6666 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6667
6668 void
6669 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6670 {
6671 REAL_VALUE_TYPE r;
6672
6673 switch (GET_MODE_CLASS (mode))
6674 {
6675 case MODE_FLOAT:
6676 case MODE_DECIMAL_FLOAT:
6677 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6678
6679 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6680 assemble_real (r, mode, align);
6681 break;
6682
6683 case MODE_INT:
6684 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6685 break;
6686
6687 default:
6688 gcc_unreachable ();
6689 }
6690 }
6691
6692
6693 /* Return an RTL expression representing the value of the return address
6694 for the frame COUNT steps up from the current frame. FRAME is the
6695 frame pointer of that frame. */
6696
6697 rtx
6698 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6699 {
6700 int offset;
6701 rtx addr;
6702
6703 /* Without backchain, we fail for all but the current frame. */
6704
6705 if (!TARGET_BACKCHAIN && count > 0)
6706 return NULL_RTX;
6707
6708 /* For the current frame, we need to make sure the initial
6709 value of RETURN_REGNUM is actually saved. */
6710
6711 if (count == 0)
6712 {
6713 /* On non-z architectures branch splitting could overwrite r14. */
6714 if (TARGET_CPU_ZARCH)
6715 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6716 else
6717 {
6718 cfun_frame_layout.save_return_addr_p = true;
6719 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6720 }
6721 }
6722
6723 if (TARGET_PACKED_STACK)
6724 offset = -2 * UNITS_PER_WORD;
6725 else
6726 offset = RETURN_REGNUM * UNITS_PER_WORD;
6727
6728 addr = plus_constant (frame, offset);
6729 addr = memory_address (Pmode, addr);
6730 return gen_rtx_MEM (Pmode, addr);
6731 }
6732
6733 /* Return an RTL expression representing the back chain stored in
6734 the current stack frame. */
6735
6736 rtx
6737 s390_back_chain_rtx (void)
6738 {
6739 rtx chain;
6740
6741 gcc_assert (TARGET_BACKCHAIN);
6742
6743 if (TARGET_PACKED_STACK)
6744 chain = plus_constant (stack_pointer_rtx,
6745 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6746 else
6747 chain = stack_pointer_rtx;
6748
6749 chain = gen_rtx_MEM (Pmode, chain);
6750 return chain;
6751 }
6752
6753 /* Find first call clobbered register unused in a function.
6754 This could be used as base register in a leaf function
6755 or for holding the return address before epilogue. */
6756
6757 static int
6758 find_unused_clobbered_reg (void)
6759 {
6760 int i;
6761 for (i = 0; i < 6; i++)
6762 if (!df_regs_ever_live_p (i))
6763 return i;
6764 return 0;
6765 }
6766
6767
6768 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6769 clobbered hard regs in SETREG. */
6770
6771 static void
6772 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6773 {
6774 int *regs_ever_clobbered = (int *)data;
6775 unsigned int i, regno;
6776 enum machine_mode mode = GET_MODE (setreg);
6777
6778 if (GET_CODE (setreg) == SUBREG)
6779 {
6780 rtx inner = SUBREG_REG (setreg);
6781 if (!GENERAL_REG_P (inner))
6782 return;
6783 regno = subreg_regno (setreg);
6784 }
6785 else if (GENERAL_REG_P (setreg))
6786 regno = REGNO (setreg);
6787 else
6788 return;
6789
6790 for (i = regno;
6791 i < regno + HARD_REGNO_NREGS (regno, mode);
6792 i++)
6793 regs_ever_clobbered[i] = 1;
6794 }
6795
6796 /* Walks through all basic blocks of the current function looking
6797 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6798 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6799 each of those regs. */
6800
6801 static void
6802 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6803 {
6804 basic_block cur_bb;
6805 rtx cur_insn;
6806 unsigned int i;
6807
6808 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6809
6810 /* For non-leaf functions we have to consider all call clobbered regs to be
6811 clobbered. */
6812 if (!current_function_is_leaf)
6813 {
6814 for (i = 0; i < 16; i++)
6815 regs_ever_clobbered[i] = call_really_used_regs[i];
6816 }
6817
6818 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6819 this work is done by liveness analysis (mark_regs_live_at_end).
6820 Special care is needed for functions containing landing pads. Landing pads
6821 may use the eh registers, but the code which sets these registers is not
6822 contained in that function. Hence s390_regs_ever_clobbered is not able to
6823 deal with this automatically. */
6824 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6825 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6826 if (crtl->calls_eh_return
6827 || (cfun->machine->has_landing_pad_p
6828 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6829 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6830
6831 /* For nonlocal gotos all call-saved registers have to be saved.
6832 This flag is also set for the unwinding code in libgcc.
6833 See expand_builtin_unwind_init. For regs_ever_live this is done by
6834 reload. */
6835 if (cfun->has_nonlocal_label)
6836 for (i = 0; i < 16; i++)
6837 if (!call_really_used_regs[i])
6838 regs_ever_clobbered[i] = 1;
6839
6840 FOR_EACH_BB (cur_bb)
6841 {
6842 FOR_BB_INSNS (cur_bb, cur_insn)
6843 {
6844 if (INSN_P (cur_insn))
6845 note_stores (PATTERN (cur_insn),
6846 s390_reg_clobbered_rtx,
6847 regs_ever_clobbered);
6848 }
6849 }
6850 }
6851
6852 /* Determine the frame area which actually has to be accessed
6853 in the function epilogue. The values are stored at the
6854 given pointers AREA_BOTTOM (address of the lowest used stack
6855 address) and AREA_TOP (address of the first item which does
6856 not belong to the stack frame). */
6857
6858 static void
6859 s390_frame_area (int *area_bottom, int *area_top)
6860 {
6861 int b, t;
6862 int i;
6863
6864 b = INT_MAX;
6865 t = INT_MIN;
6866
6867 if (cfun_frame_layout.first_restore_gpr != -1)
6868 {
6869 b = (cfun_frame_layout.gprs_offset
6870 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6871 t = b + (cfun_frame_layout.last_restore_gpr
6872 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6873 }
6874
6875 if (TARGET_64BIT && cfun_save_high_fprs_p)
6876 {
6877 b = MIN (b, cfun_frame_layout.f8_offset);
6878 t = MAX (t, (cfun_frame_layout.f8_offset
6879 + cfun_frame_layout.high_fprs * 8));
6880 }
6881
6882 if (!TARGET_64BIT)
6883 for (i = 2; i < 4; i++)
6884 if (cfun_fpr_bit_p (i))
6885 {
6886 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6887 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6888 }
6889
6890 *area_bottom = b;
6891 *area_top = t;
6892 }
6893
6894 /* Fill cfun->machine with info about register usage of current function.
6895 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6896
6897 static void
6898 s390_register_info (int clobbered_regs[])
6899 {
6900 int i, j;
6901
6902 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6903 cfun_frame_layout.fpr_bitmap = 0;
6904 cfun_frame_layout.high_fprs = 0;
6905 if (TARGET_64BIT)
6906 for (i = 24; i < 32; i++)
6907 if (df_regs_ever_live_p (i) && !global_regs[i])
6908 {
6909 cfun_set_fpr_bit (i - 16);
6910 cfun_frame_layout.high_fprs++;
6911 }
6912
6913 /* Find first and last gpr to be saved. We trust regs_ever_live
6914 data, except that we don't save and restore global registers.
6915
6916 Also, all registers with special meaning to the compiler need
6917 to be handled extra. */
6918
6919 s390_regs_ever_clobbered (clobbered_regs);
6920
6921 for (i = 0; i < 16; i++)
6922 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6923
6924 if (frame_pointer_needed)
6925 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6926
6927 if (flag_pic)
6928 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6929 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6930
6931 clobbered_regs[BASE_REGNUM]
6932 |= (cfun->machine->base_reg
6933 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6934
6935 clobbered_regs[RETURN_REGNUM]
6936 |= (!current_function_is_leaf
6937 || TARGET_TPF_PROFILING
6938 || cfun->machine->split_branches_pending_p
6939 || cfun_frame_layout.save_return_addr_p
6940 || crtl->calls_eh_return
6941 || cfun->stdarg);
6942
6943 clobbered_regs[STACK_POINTER_REGNUM]
6944 |= (!current_function_is_leaf
6945 || TARGET_TPF_PROFILING
6946 || cfun_save_high_fprs_p
6947 || get_frame_size () > 0
6948 || cfun->calls_alloca
6949 || cfun->stdarg);
6950
6951 for (i = 6; i < 16; i++)
6952 if (df_regs_ever_live_p (i) || clobbered_regs[i])
6953 break;
6954 for (j = 15; j > i; j--)
6955 if (df_regs_ever_live_p (j) || clobbered_regs[j])
6956 break;
6957
6958 if (i == 16)
6959 {
6960 /* Nothing to save/restore. */
6961 cfun_frame_layout.first_save_gpr_slot = -1;
6962 cfun_frame_layout.last_save_gpr_slot = -1;
6963 cfun_frame_layout.first_save_gpr = -1;
6964 cfun_frame_layout.first_restore_gpr = -1;
6965 cfun_frame_layout.last_save_gpr = -1;
6966 cfun_frame_layout.last_restore_gpr = -1;
6967 }
6968 else
6969 {
6970 /* Save slots for gprs from i to j. */
6971 cfun_frame_layout.first_save_gpr_slot = i;
6972 cfun_frame_layout.last_save_gpr_slot = j;
6973
6974 for (i = cfun_frame_layout.first_save_gpr_slot;
6975 i < cfun_frame_layout.last_save_gpr_slot + 1;
6976 i++)
6977 if (clobbered_regs[i])
6978 break;
6979
6980 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6981 if (clobbered_regs[j])
6982 break;
6983
6984 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6985 {
6986 /* Nothing to save/restore. */
6987 cfun_frame_layout.first_save_gpr = -1;
6988 cfun_frame_layout.first_restore_gpr = -1;
6989 cfun_frame_layout.last_save_gpr = -1;
6990 cfun_frame_layout.last_restore_gpr = -1;
6991 }
6992 else
6993 {
6994 /* Save / Restore from gpr i to j. */
6995 cfun_frame_layout.first_save_gpr = i;
6996 cfun_frame_layout.first_restore_gpr = i;
6997 cfun_frame_layout.last_save_gpr = j;
6998 cfun_frame_layout.last_restore_gpr = j;
6999 }
7000 }
7001
7002 if (cfun->stdarg)
7003 {
7004 /* Varargs functions need to save gprs 2 to 6. */
7005 if (cfun->va_list_gpr_size
7006 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7007 {
7008 int min_gpr = crtl->args.info.gprs;
7009 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7010 if (max_gpr > GP_ARG_NUM_REG)
7011 max_gpr = GP_ARG_NUM_REG;
7012
7013 if (cfun_frame_layout.first_save_gpr == -1
7014 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7015 {
7016 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7017 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7018 }
7019
7020 if (cfun_frame_layout.last_save_gpr == -1
7021 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7022 {
7023 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7024 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7025 }
7026 }
7027
7028 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7029 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7030 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7031 {
7032 int min_fpr = crtl->args.info.fprs;
7033 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7034 if (max_fpr > FP_ARG_NUM_REG)
7035 max_fpr = FP_ARG_NUM_REG;
7036
7037 /* ??? This is currently required to ensure proper location
7038 of the fpr save slots within the va_list save area. */
7039 if (TARGET_PACKED_STACK)
7040 min_fpr = 0;
7041
7042 for (i = min_fpr; i < max_fpr; i++)
7043 cfun_set_fpr_bit (i);
7044 }
7045 }
7046
7047 if (!TARGET_64BIT)
7048 for (i = 2; i < 4; i++)
7049 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7050 cfun_set_fpr_bit (i);
7051 }
7052
7053 /* Fill cfun->machine with info about frame of current function. */
7054
7055 static void
7056 s390_frame_info (void)
7057 {
7058 int i;
7059
7060 cfun_frame_layout.frame_size = get_frame_size ();
7061 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7062 fatal_error ("total size of local variables exceeds architecture limit");
7063
7064 if (!TARGET_PACKED_STACK)
7065 {
7066 cfun_frame_layout.backchain_offset = 0;
7067 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
7068 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7069 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7070 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7071 * UNITS_PER_WORD);
7072 }
7073 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7074 {
7075 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7076 - UNITS_PER_WORD);
7077 cfun_frame_layout.gprs_offset
7078 = (cfun_frame_layout.backchain_offset
7079 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7080 * UNITS_PER_WORD);
7081
7082 if (TARGET_64BIT)
7083 {
7084 cfun_frame_layout.f4_offset
7085 = (cfun_frame_layout.gprs_offset
7086 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7087
7088 cfun_frame_layout.f0_offset
7089 = (cfun_frame_layout.f4_offset
7090 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7091 }
7092 else
7093 {
7094 /* On 31 bit we have to care about alignment of the
7095 floating point regs to provide fastest access. */
7096 cfun_frame_layout.f0_offset
7097 = ((cfun_frame_layout.gprs_offset
7098 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7099 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7100
7101 cfun_frame_layout.f4_offset
7102 = (cfun_frame_layout.f0_offset
7103 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7104 }
7105 }
7106 else /* no backchain */
7107 {
7108 cfun_frame_layout.f4_offset
7109 = (STACK_POINTER_OFFSET
7110 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7111
7112 cfun_frame_layout.f0_offset
7113 = (cfun_frame_layout.f4_offset
7114 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7115
7116 cfun_frame_layout.gprs_offset
7117 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7118 }
7119
7120 if (current_function_is_leaf
7121 && !TARGET_TPF_PROFILING
7122 && cfun_frame_layout.frame_size == 0
7123 && !cfun_save_high_fprs_p
7124 && !cfun->calls_alloca
7125 && !cfun->stdarg)
7126 return;
7127
7128 if (!TARGET_PACKED_STACK)
7129 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7130 + crtl->outgoing_args_size
7131 + cfun_frame_layout.high_fprs * 8);
7132 else
7133 {
7134 if (TARGET_BACKCHAIN)
7135 cfun_frame_layout.frame_size += UNITS_PER_WORD;
7136
7137 /* No alignment trouble here because f8-f15 are only saved under
7138 64 bit. */
7139 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7140 cfun_frame_layout.f4_offset),
7141 cfun_frame_layout.gprs_offset)
7142 - cfun_frame_layout.high_fprs * 8);
7143
7144 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7145
7146 for (i = 0; i < 8; i++)
7147 if (cfun_fpr_bit_p (i))
7148 cfun_frame_layout.frame_size += 8;
7149
7150 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7151
7152 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7153 the frame size to sustain 8 byte alignment of stack frames. */
7154 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7155 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7156 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7157
7158 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7159 }
7160 }
7161
7162 /* Generate frame layout. Fills in register and frame data for the current
7163 function in cfun->machine. This routine can be called multiple times;
7164 it will re-do the complete frame layout every time. */
7165
7166 static void
7167 s390_init_frame_layout (void)
7168 {
7169 HOST_WIDE_INT frame_size;
7170 int base_used;
7171 int clobbered_regs[16];
7172
7173 /* On S/390 machines, we may need to perform branch splitting, which
7174 will require both base and return address register. We have no
7175 choice but to assume we're going to need them until right at the
7176 end of the machine dependent reorg phase. */
7177 if (!TARGET_CPU_ZARCH)
7178 cfun->machine->split_branches_pending_p = true;
7179
7180 do
7181 {
7182 frame_size = cfun_frame_layout.frame_size;
7183
7184 /* Try to predict whether we'll need the base register. */
7185 base_used = cfun->machine->split_branches_pending_p
7186 || crtl->uses_const_pool
7187 || (!DISP_IN_RANGE (frame_size)
7188 && !CONST_OK_FOR_K (frame_size));
7189
7190 /* Decide which register to use as literal pool base. In small
7191 leaf functions, try to use an unused call-clobbered register
7192 as base register to avoid save/restore overhead. */
7193 if (!base_used)
7194 cfun->machine->base_reg = NULL_RTX;
7195 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7196 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7197 else
7198 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7199
7200 s390_register_info (clobbered_regs);
7201 s390_frame_info ();
7202 }
7203 while (frame_size != cfun_frame_layout.frame_size);
7204 }
7205
7206 /* Update frame layout. Recompute actual register save data based on
7207 current info and update regs_ever_live for the special registers.
7208 May be called multiple times, but may never cause *more* registers
7209 to be saved than s390_init_frame_layout allocated room for. */
7210
7211 static void
7212 s390_update_frame_layout (void)
7213 {
7214 int clobbered_regs[16];
7215
7216 s390_register_info (clobbered_regs);
7217
7218 df_set_regs_ever_live (BASE_REGNUM,
7219 clobbered_regs[BASE_REGNUM] ? true : false);
7220 df_set_regs_ever_live (RETURN_REGNUM,
7221 clobbered_regs[RETURN_REGNUM] ? true : false);
7222 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7223 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7224
7225 if (cfun->machine->base_reg)
7226 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7227 }
7228
7229 /* Return true if it is legal to put a value with MODE into REGNO. */
7230
7231 bool
7232 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7233 {
7234 switch (REGNO_REG_CLASS (regno))
7235 {
7236 case FP_REGS:
7237 if (REGNO_PAIR_OK (regno, mode))
7238 {
7239 if (mode == SImode || mode == DImode)
7240 return true;
7241
7242 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7243 return true;
7244 }
7245 break;
7246 case ADDR_REGS:
7247 if (FRAME_REGNO_P (regno) && mode == Pmode)
7248 return true;
7249
7250 /* fallthrough */
7251 case GENERAL_REGS:
7252 if (REGNO_PAIR_OK (regno, mode))
7253 {
7254 if (TARGET_64BIT
7255 || (mode != TFmode && mode != TCmode && mode != TDmode))
7256 return true;
7257 }
7258 break;
7259 case CC_REGS:
7260 if (GET_MODE_CLASS (mode) == MODE_CC)
7261 return true;
7262 break;
7263 case ACCESS_REGS:
7264 if (REGNO_PAIR_OK (regno, mode))
7265 {
7266 if (mode == SImode || mode == Pmode)
7267 return true;
7268 }
7269 break;
7270 default:
7271 return false;
7272 }
7273
7274 return false;
7275 }
7276
7277 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7278
7279 bool
7280 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7281 {
7282 /* Once we've decided upon a register to use as base register, it must
7283 no longer be used for any other purpose. */
7284 if (cfun->machine->base_reg)
7285 if (REGNO (cfun->machine->base_reg) == old_reg
7286 || REGNO (cfun->machine->base_reg) == new_reg)
7287 return false;
7288
7289 return true;
7290 }
7291
7292 /* Maximum number of registers to represent a value of mode MODE
7293 in a register of class RCLASS. */
7294
7295 bool
7296 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7297 {
7298 switch (rclass)
7299 {
7300 case FP_REGS:
7301 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7302 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7303 else
7304 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7305 case ACCESS_REGS:
7306 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7307 default:
7308 break;
7309 }
7310 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7311 }
7312
7313 /* Return true if register FROM can be eliminated via register TO. */
7314
7315 bool
7316 s390_can_eliminate (int from, int to)
7317 {
7318 /* On zSeries machines, we have not marked the base register as fixed.
7319 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7320 If a function requires the base register, we say here that this
7321 elimination cannot be performed. This will cause reload to free
7322 up the base register (as if it were fixed). On the other hand,
7323 if the current function does *not* require the base register, we
7324 say here the elimination succeeds, which in turn allows reload
7325 to allocate the base register for any other purpose. */
7326 if (from == BASE_REGNUM && to == BASE_REGNUM)
7327 {
7328 if (TARGET_CPU_ZARCH)
7329 {
7330 s390_init_frame_layout ();
7331 return cfun->machine->base_reg == NULL_RTX;
7332 }
7333
7334 return false;
7335 }
7336
7337 /* Everything else must point into the stack frame. */
7338 gcc_assert (to == STACK_POINTER_REGNUM
7339 || to == HARD_FRAME_POINTER_REGNUM);
7340
7341 gcc_assert (from == FRAME_POINTER_REGNUM
7342 || from == ARG_POINTER_REGNUM
7343 || from == RETURN_ADDRESS_POINTER_REGNUM);
7344
7345 /* Make sure we actually saved the return address. */
7346 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7347 if (!crtl->calls_eh_return
7348 && !cfun->stdarg
7349 && !cfun_frame_layout.save_return_addr_p)
7350 return false;
7351
7352 return true;
7353 }
7354
7355 /* Return offset between register FROM and TO initially after prolog. */
7356
7357 HOST_WIDE_INT
7358 s390_initial_elimination_offset (int from, int to)
7359 {
7360 HOST_WIDE_INT offset;
7361 int index;
7362
7363 /* ??? Why are we called for non-eliminable pairs? */
7364 if (!s390_can_eliminate (from, to))
7365 return 0;
7366
7367 switch (from)
7368 {
7369 case FRAME_POINTER_REGNUM:
7370 offset = (get_frame_size()
7371 + STACK_POINTER_OFFSET
7372 + crtl->outgoing_args_size);
7373 break;
7374
7375 case ARG_POINTER_REGNUM:
7376 s390_init_frame_layout ();
7377 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7378 break;
7379
7380 case RETURN_ADDRESS_POINTER_REGNUM:
7381 s390_init_frame_layout ();
7382 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7383 gcc_assert (index >= 0);
7384 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7385 offset += index * UNITS_PER_WORD;
7386 break;
7387
7388 case BASE_REGNUM:
7389 offset = 0;
7390 break;
7391
7392 default:
7393 gcc_unreachable ();
7394 }
7395
7396 return offset;
7397 }
7398
7399 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7400 to register BASE. Return generated insn. */
7401
7402 static rtx
7403 save_fpr (rtx base, int offset, int regnum)
7404 {
7405 rtx addr;
7406 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7407
7408 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7409 set_mem_alias_set (addr, get_varargs_alias_set ());
7410 else
7411 set_mem_alias_set (addr, get_frame_alias_set ());
7412
7413 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7414 }
7415
7416 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7417 to register BASE. Return generated insn. */
7418
7419 static rtx
7420 restore_fpr (rtx base, int offset, int regnum)
7421 {
7422 rtx addr;
7423 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7424 set_mem_alias_set (addr, get_frame_alias_set ());
7425
7426 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7427 }
7428
7429 /* Generate insn to save registers FIRST to LAST into
7430 the register save area located at offset OFFSET
7431 relative to register BASE. */
7432
7433 static rtx
7434 save_gprs (rtx base, int offset, int first, int last)
7435 {
7436 rtx addr, insn, note;
7437 int i;
7438
7439 addr = plus_constant (base, offset);
7440 addr = gen_rtx_MEM (Pmode, addr);
7441
7442 set_mem_alias_set (addr, get_frame_alias_set ());
7443
7444 /* Special-case single register. */
7445 if (first == last)
7446 {
7447 if (TARGET_64BIT)
7448 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7449 else
7450 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7451
7452 RTX_FRAME_RELATED_P (insn) = 1;
7453 return insn;
7454 }
7455
7456
7457 insn = gen_store_multiple (addr,
7458 gen_rtx_REG (Pmode, first),
7459 GEN_INT (last - first + 1));
7460
7461 if (first <= 6 && cfun->stdarg)
7462 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7463 {
7464 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7465
7466 if (first + i <= 6)
7467 set_mem_alias_set (mem, get_varargs_alias_set ());
7468 }
7469
7470 /* We need to set the FRAME_RELATED flag on all SETs
7471 inside the store-multiple pattern.
7472
7473 However, we must not emit DWARF records for registers 2..5
7474 if they are stored for use by variable arguments ...
7475
7476 ??? Unfortunately, it is not enough to simply not the
7477 FRAME_RELATED flags for those SETs, because the first SET
7478 of the PARALLEL is always treated as if it had the flag
7479 set, even if it does not. Therefore we emit a new pattern
7480 without those registers as REG_FRAME_RELATED_EXPR note. */
7481
7482 if (first >= 6)
7483 {
7484 rtx pat = PATTERN (insn);
7485
7486 for (i = 0; i < XVECLEN (pat, 0); i++)
7487 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
7488 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7489
7490 RTX_FRAME_RELATED_P (insn) = 1;
7491 }
7492 else if (last >= 6)
7493 {
7494 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
7495 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7496 gen_rtx_REG (Pmode, 6),
7497 GEN_INT (last - 6 + 1));
7498 note = PATTERN (note);
7499
7500 REG_NOTES (insn) =
7501 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7502 note, REG_NOTES (insn));
7503
7504 for (i = 0; i < XVECLEN (note, 0); i++)
7505 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
7506 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7507
7508 RTX_FRAME_RELATED_P (insn) = 1;
7509 }
7510
7511 return insn;
7512 }
7513
7514 /* Generate insn to restore registers FIRST to LAST from
7515 the register save area located at offset OFFSET
7516 relative to register BASE. */
7517
7518 static rtx
7519 restore_gprs (rtx base, int offset, int first, int last)
7520 {
7521 rtx addr, insn;
7522
7523 addr = plus_constant (base, offset);
7524 addr = gen_rtx_MEM (Pmode, addr);
7525 set_mem_alias_set (addr, get_frame_alias_set ());
7526
7527 /* Special-case single register. */
7528 if (first == last)
7529 {
7530 if (TARGET_64BIT)
7531 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7532 else
7533 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7534
7535 return insn;
7536 }
7537
7538 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7539 addr,
7540 GEN_INT (last - first + 1));
7541 return insn;
7542 }
7543
7544 /* Return insn sequence to load the GOT register. */
7545
7546 static GTY(()) rtx got_symbol;
7547 rtx
7548 s390_load_got (void)
7549 {
7550 rtx insns;
7551
7552 if (!got_symbol)
7553 {
7554 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7555 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7556 }
7557
7558 start_sequence ();
7559
7560 if (TARGET_CPU_ZARCH)
7561 {
7562 emit_move_insn (pic_offset_table_rtx, got_symbol);
7563 }
7564 else
7565 {
7566 rtx offset;
7567
7568 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7569 UNSPEC_LTREL_OFFSET);
7570 offset = gen_rtx_CONST (Pmode, offset);
7571 offset = force_const_mem (Pmode, offset);
7572
7573 emit_move_insn (pic_offset_table_rtx, offset);
7574
7575 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7576 UNSPEC_LTREL_BASE);
7577 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7578
7579 emit_move_insn (pic_offset_table_rtx, offset);
7580 }
7581
7582 insns = get_insns ();
7583 end_sequence ();
7584 return insns;
7585 }
7586
7587 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7588 and the change to the stack pointer. */
7589
7590 static void
7591 s390_emit_stack_tie (void)
7592 {
7593 rtx mem = gen_frame_mem (BLKmode,
7594 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7595
7596 emit_insn (gen_stack_tie (mem));
7597 }
7598
7599 /* Expand the prologue into a bunch of separate insns. */
7600
7601 void
7602 s390_emit_prologue (void)
7603 {
7604 rtx insn, addr;
7605 rtx temp_reg;
7606 int i;
7607 int offset;
7608 int next_fpr = 0;
7609
7610 /* Complete frame layout. */
7611
7612 s390_update_frame_layout ();
7613
7614 /* Annotate all constant pool references to let the scheduler know
7615 they implicitly use the base register. */
7616
7617 push_topmost_sequence ();
7618
7619 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7620 if (INSN_P (insn))
7621 {
7622 annotate_constant_pool_refs (&PATTERN (insn));
7623 df_insn_rescan (insn);
7624 }
7625
7626 pop_topmost_sequence ();
7627
7628 /* Choose best register to use for temp use within prologue.
7629 See below for why TPF must use the register 1. */
7630
7631 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7632 && !current_function_is_leaf
7633 && !TARGET_TPF_PROFILING)
7634 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7635 else
7636 temp_reg = gen_rtx_REG (Pmode, 1);
7637
7638 /* Save call saved gprs. */
7639 if (cfun_frame_layout.first_save_gpr != -1)
7640 {
7641 insn = save_gprs (stack_pointer_rtx,
7642 cfun_frame_layout.gprs_offset +
7643 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7644 - cfun_frame_layout.first_save_gpr_slot),
7645 cfun_frame_layout.first_save_gpr,
7646 cfun_frame_layout.last_save_gpr);
7647 emit_insn (insn);
7648 }
7649
7650 /* Dummy insn to mark literal pool slot. */
7651
7652 if (cfun->machine->base_reg)
7653 emit_insn (gen_main_pool (cfun->machine->base_reg));
7654
7655 offset = cfun_frame_layout.f0_offset;
7656
7657 /* Save f0 and f2. */
7658 for (i = 0; i < 2; i++)
7659 {
7660 if (cfun_fpr_bit_p (i))
7661 {
7662 save_fpr (stack_pointer_rtx, offset, i + 16);
7663 offset += 8;
7664 }
7665 else if (!TARGET_PACKED_STACK)
7666 offset += 8;
7667 }
7668
7669 /* Save f4 and f6. */
7670 offset = cfun_frame_layout.f4_offset;
7671 for (i = 2; i < 4; i++)
7672 {
7673 if (cfun_fpr_bit_p (i))
7674 {
7675 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7676 offset += 8;
7677
7678 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7679 therefore are not frame related. */
7680 if (!call_really_used_regs[i + 16])
7681 RTX_FRAME_RELATED_P (insn) = 1;
7682 }
7683 else if (!TARGET_PACKED_STACK)
7684 offset += 8;
7685 }
7686
7687 if (TARGET_PACKED_STACK
7688 && cfun_save_high_fprs_p
7689 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7690 {
7691 offset = (cfun_frame_layout.f8_offset
7692 + (cfun_frame_layout.high_fprs - 1) * 8);
7693
7694 for (i = 15; i > 7 && offset >= 0; i--)
7695 if (cfun_fpr_bit_p (i))
7696 {
7697 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7698
7699 RTX_FRAME_RELATED_P (insn) = 1;
7700 offset -= 8;
7701 }
7702 if (offset >= cfun_frame_layout.f8_offset)
7703 next_fpr = i + 16;
7704 }
7705
7706 if (!TARGET_PACKED_STACK)
7707 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7708
7709 /* Decrement stack pointer. */
7710
7711 if (cfun_frame_layout.frame_size > 0)
7712 {
7713 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7714
7715 if (s390_stack_size)
7716 {
7717 HOST_WIDE_INT stack_guard;
7718
7719 if (s390_stack_guard)
7720 stack_guard = s390_stack_guard;
7721 else
7722 {
7723 /* If no value for stack guard is provided the smallest power of 2
7724 larger than the current frame size is chosen. */
7725 stack_guard = 1;
7726 while (stack_guard < cfun_frame_layout.frame_size)
7727 stack_guard <<= 1;
7728 }
7729
7730 if (cfun_frame_layout.frame_size >= s390_stack_size)
7731 {
7732 warning (0, "frame size of function %qs is "
7733 HOST_WIDE_INT_PRINT_DEC
7734 " bytes exceeding user provided stack limit of "
7735 HOST_WIDE_INT_PRINT_DEC " bytes. "
7736 "An unconditional trap is added.",
7737 current_function_name(), cfun_frame_layout.frame_size,
7738 s390_stack_size);
7739 emit_insn (gen_trap ());
7740 }
7741 else
7742 {
7743 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7744 & ~(stack_guard - 1));
7745 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7746 GEN_INT (stack_check_mask));
7747 if (TARGET_64BIT)
7748 gen_cmpdi (t, const0_rtx);
7749 else
7750 gen_cmpsi (t, const0_rtx);
7751
7752 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7753 gen_rtx_REG (CCmode,
7754 CC_REGNUM),
7755 const0_rtx),
7756 const0_rtx));
7757 }
7758 }
7759
7760 if (s390_warn_framesize > 0
7761 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7762 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7763 current_function_name (), cfun_frame_layout.frame_size);
7764
7765 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7766 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7767
7768 /* Save incoming stack pointer into temp reg. */
7769 if (TARGET_BACKCHAIN || next_fpr)
7770 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7771
7772 /* Subtract frame size from stack pointer. */
7773
7774 if (DISP_IN_RANGE (INTVAL (frame_off)))
7775 {
7776 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7777 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7778 frame_off));
7779 insn = emit_insn (insn);
7780 }
7781 else
7782 {
7783 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7784 frame_off = force_const_mem (Pmode, frame_off);
7785
7786 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7787 annotate_constant_pool_refs (&PATTERN (insn));
7788 }
7789
7790 RTX_FRAME_RELATED_P (insn) = 1;
7791 REG_NOTES (insn) =
7792 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7793 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7794 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7795 GEN_INT (-cfun_frame_layout.frame_size))),
7796 REG_NOTES (insn));
7797
7798 /* Set backchain. */
7799
7800 if (TARGET_BACKCHAIN)
7801 {
7802 if (cfun_frame_layout.backchain_offset)
7803 addr = gen_rtx_MEM (Pmode,
7804 plus_constant (stack_pointer_rtx,
7805 cfun_frame_layout.backchain_offset));
7806 else
7807 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7808 set_mem_alias_set (addr, get_frame_alias_set ());
7809 insn = emit_insn (gen_move_insn (addr, temp_reg));
7810 }
7811
7812 /* If we support asynchronous exceptions (e.g. for Java),
7813 we need to make sure the backchain pointer is set up
7814 before any possibly trapping memory access. */
7815
7816 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7817 {
7818 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7819 emit_clobber (addr);
7820 }
7821 }
7822
7823 /* Save fprs 8 - 15 (64 bit ABI). */
7824
7825 if (cfun_save_high_fprs_p && next_fpr)
7826 {
7827 /* If the stack might be accessed through a different register
7828 we have to make sure that the stack pointer decrement is not
7829 moved below the use of the stack slots. */
7830 s390_emit_stack_tie ();
7831
7832 insn = emit_insn (gen_add2_insn (temp_reg,
7833 GEN_INT (cfun_frame_layout.f8_offset)));
7834
7835 offset = 0;
7836
7837 for (i = 24; i <= next_fpr; i++)
7838 if (cfun_fpr_bit_p (i - 16))
7839 {
7840 rtx addr = plus_constant (stack_pointer_rtx,
7841 cfun_frame_layout.frame_size
7842 + cfun_frame_layout.f8_offset
7843 + offset);
7844
7845 insn = save_fpr (temp_reg, offset, i);
7846 offset += 8;
7847 RTX_FRAME_RELATED_P (insn) = 1;
7848 REG_NOTES (insn) =
7849 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7850 gen_rtx_SET (VOIDmode,
7851 gen_rtx_MEM (DFmode, addr),
7852 gen_rtx_REG (DFmode, i)),
7853 REG_NOTES (insn));
7854 }
7855 }
7856
7857 /* Set frame pointer, if needed. */
7858
7859 if (frame_pointer_needed)
7860 {
7861 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7862 RTX_FRAME_RELATED_P (insn) = 1;
7863 }
7864
7865 /* Set up got pointer, if needed. */
7866
7867 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7868 {
7869 rtx insns = s390_load_got ();
7870
7871 for (insn = insns; insn; insn = NEXT_INSN (insn))
7872 annotate_constant_pool_refs (&PATTERN (insn));
7873
7874 emit_insn (insns);
7875 }
7876
7877 if (TARGET_TPF_PROFILING)
7878 {
7879 /* Generate a BAS instruction to serve as a function
7880 entry intercept to facilitate the use of tracing
7881 algorithms located at the branch target. */
7882 emit_insn (gen_prologue_tpf ());
7883
7884 /* Emit a blockage here so that all code
7885 lies between the profiling mechanisms. */
7886 emit_insn (gen_blockage ());
7887 }
7888 }
7889
7890 /* Expand the epilogue into a bunch of separate insns. */
7891
7892 void
7893 s390_emit_epilogue (bool sibcall)
7894 {
7895 rtx frame_pointer, return_reg;
7896 int area_bottom, area_top, offset = 0;
7897 int next_offset;
7898 rtvec p;
7899 int i;
7900
7901 if (TARGET_TPF_PROFILING)
7902 {
7903
7904 /* Generate a BAS instruction to serve as a function
7905 entry intercept to facilitate the use of tracing
7906 algorithms located at the branch target. */
7907
7908 /* Emit a blockage here so that all code
7909 lies between the profiling mechanisms. */
7910 emit_insn (gen_blockage ());
7911
7912 emit_insn (gen_epilogue_tpf ());
7913 }
7914
7915 /* Check whether to use frame or stack pointer for restore. */
7916
7917 frame_pointer = (frame_pointer_needed
7918 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7919
7920 s390_frame_area (&area_bottom, &area_top);
7921
7922 /* Check whether we can access the register save area.
7923 If not, increment the frame pointer as required. */
7924
7925 if (area_top <= area_bottom)
7926 {
7927 /* Nothing to restore. */
7928 }
7929 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7930 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7931 {
7932 /* Area is in range. */
7933 offset = cfun_frame_layout.frame_size;
7934 }
7935 else
7936 {
7937 rtx insn, frame_off;
7938
7939 offset = area_bottom < 0 ? -area_bottom : 0;
7940 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7941
7942 if (DISP_IN_RANGE (INTVAL (frame_off)))
7943 {
7944 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7945 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7946 insn = emit_insn (insn);
7947 }
7948 else
7949 {
7950 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7951 frame_off = force_const_mem (Pmode, frame_off);
7952
7953 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7954 annotate_constant_pool_refs (&PATTERN (insn));
7955 }
7956 }
7957
7958 /* Restore call saved fprs. */
7959
7960 if (TARGET_64BIT)
7961 {
7962 if (cfun_save_high_fprs_p)
7963 {
7964 next_offset = cfun_frame_layout.f8_offset;
7965 for (i = 24; i < 32; i++)
7966 {
7967 if (cfun_fpr_bit_p (i - 16))
7968 {
7969 restore_fpr (frame_pointer,
7970 offset + next_offset, i);
7971 next_offset += 8;
7972 }
7973 }
7974 }
7975
7976 }
7977 else
7978 {
7979 next_offset = cfun_frame_layout.f4_offset;
7980 for (i = 18; i < 20; i++)
7981 {
7982 if (cfun_fpr_bit_p (i - 16))
7983 {
7984 restore_fpr (frame_pointer,
7985 offset + next_offset, i);
7986 next_offset += 8;
7987 }
7988 else if (!TARGET_PACKED_STACK)
7989 next_offset += 8;
7990 }
7991
7992 }
7993
7994 /* Return register. */
7995
7996 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7997
7998 /* Restore call saved gprs. */
7999
8000 if (cfun_frame_layout.first_restore_gpr != -1)
8001 {
8002 rtx insn, addr;
8003 int i;
8004
8005 /* Check for global register and save them
8006 to stack location from where they get restored. */
8007
8008 for (i = cfun_frame_layout.first_restore_gpr;
8009 i <= cfun_frame_layout.last_restore_gpr;
8010 i++)
8011 {
8012 /* These registers are special and need to be
8013 restored in any case. */
8014 if (i == STACK_POINTER_REGNUM
8015 || i == RETURN_REGNUM
8016 || i == BASE_REGNUM
8017 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
8018 continue;
8019
8020 if (global_regs[i])
8021 {
8022 addr = plus_constant (frame_pointer,
8023 offset + cfun_frame_layout.gprs_offset
8024 + (i - cfun_frame_layout.first_save_gpr_slot)
8025 * UNITS_PER_WORD);
8026 addr = gen_rtx_MEM (Pmode, addr);
8027 set_mem_alias_set (addr, get_frame_alias_set ());
8028 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8029 }
8030 }
8031
8032 if (! sibcall)
8033 {
8034 /* Fetch return address from stack before load multiple,
8035 this will do good for scheduling. */
8036
8037 if (cfun_frame_layout.save_return_addr_p
8038 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8039 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8040 {
8041 int return_regnum = find_unused_clobbered_reg();
8042 if (!return_regnum)
8043 return_regnum = 4;
8044 return_reg = gen_rtx_REG (Pmode, return_regnum);
8045
8046 addr = plus_constant (frame_pointer,
8047 offset + cfun_frame_layout.gprs_offset
8048 + (RETURN_REGNUM
8049 - cfun_frame_layout.first_save_gpr_slot)
8050 * UNITS_PER_WORD);
8051 addr = gen_rtx_MEM (Pmode, addr);
8052 set_mem_alias_set (addr, get_frame_alias_set ());
8053 emit_move_insn (return_reg, addr);
8054 }
8055 }
8056
8057 insn = restore_gprs (frame_pointer,
8058 offset + cfun_frame_layout.gprs_offset
8059 + (cfun_frame_layout.first_restore_gpr
8060 - cfun_frame_layout.first_save_gpr_slot)
8061 * UNITS_PER_WORD,
8062 cfun_frame_layout.first_restore_gpr,
8063 cfun_frame_layout.last_restore_gpr);
8064 emit_insn (insn);
8065 }
8066
8067 if (! sibcall)
8068 {
8069
8070 /* Return to caller. */
8071
8072 p = rtvec_alloc (2);
8073
8074 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8075 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8076 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8077 }
8078 }
8079
8080
8081 /* Return the size in bytes of a function argument of
8082 type TYPE and/or mode MODE. At least one of TYPE or
8083 MODE must be specified. */
8084
8085 static int
8086 s390_function_arg_size (enum machine_mode mode, const_tree type)
8087 {
8088 if (type)
8089 return int_size_in_bytes (type);
8090
8091 /* No type info available for some library calls ... */
8092 if (mode != BLKmode)
8093 return GET_MODE_SIZE (mode);
8094
8095 /* If we have neither type nor mode, abort */
8096 gcc_unreachable ();
8097 }
8098
8099 /* Return true if a function argument of type TYPE and mode MODE
8100 is to be passed in a floating-point register, if available. */
8101
8102 static bool
8103 s390_function_arg_float (enum machine_mode mode, tree type)
8104 {
8105 int size = s390_function_arg_size (mode, type);
8106 if (size > 8)
8107 return false;
8108
8109 /* Soft-float changes the ABI: no floating-point registers are used. */
8110 if (TARGET_SOFT_FLOAT)
8111 return false;
8112
8113 /* No type info available for some library calls ... */
8114 if (!type)
8115 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8116
8117 /* The ABI says that record types with a single member are treated
8118 just like that member would be. */
8119 while (TREE_CODE (type) == RECORD_TYPE)
8120 {
8121 tree field, single = NULL_TREE;
8122
8123 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8124 {
8125 if (TREE_CODE (field) != FIELD_DECL)
8126 continue;
8127
8128 if (single == NULL_TREE)
8129 single = TREE_TYPE (field);
8130 else
8131 return false;
8132 }
8133
8134 if (single == NULL_TREE)
8135 return false;
8136 else
8137 type = single;
8138 }
8139
8140 return TREE_CODE (type) == REAL_TYPE;
8141 }
8142
8143 /* Return true if a function argument of type TYPE and mode MODE
8144 is to be passed in an integer register, or a pair of integer
8145 registers, if available. */
8146
8147 static bool
8148 s390_function_arg_integer (enum machine_mode mode, tree type)
8149 {
8150 int size = s390_function_arg_size (mode, type);
8151 if (size > 8)
8152 return false;
8153
8154 /* No type info available for some library calls ... */
8155 if (!type)
8156 return GET_MODE_CLASS (mode) == MODE_INT
8157 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8158
8159 /* We accept small integral (and similar) types. */
8160 if (INTEGRAL_TYPE_P (type)
8161 || POINTER_TYPE_P (type)
8162 || TREE_CODE (type) == OFFSET_TYPE
8163 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8164 return true;
8165
8166 /* We also accept structs of size 1, 2, 4, 8 that are not
8167 passed in floating-point registers. */
8168 if (AGGREGATE_TYPE_P (type)
8169 && exact_log2 (size) >= 0
8170 && !s390_function_arg_float (mode, type))
8171 return true;
8172
8173 return false;
8174 }
8175
8176 /* Return 1 if a function argument of type TYPE and mode MODE
8177 is to be passed by reference. The ABI specifies that only
8178 structures of size 1, 2, 4, or 8 bytes are passed by value,
8179 all other structures (and complex numbers) are passed by
8180 reference. */
8181
8182 static bool
8183 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8184 enum machine_mode mode, const_tree type,
8185 bool named ATTRIBUTE_UNUSED)
8186 {
8187 int size = s390_function_arg_size (mode, type);
8188 if (size > 8)
8189 return true;
8190
8191 if (type)
8192 {
8193 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8194 return 1;
8195
8196 if (TREE_CODE (type) == COMPLEX_TYPE
8197 || TREE_CODE (type) == VECTOR_TYPE)
8198 return 1;
8199 }
8200
8201 return 0;
8202 }
8203
8204 /* Update the data in CUM to advance over an argument of mode MODE and
8205 data type TYPE. (TYPE is null for libcalls where that information
8206 may not be available.). The boolean NAMED specifies whether the
8207 argument is a named argument (as opposed to an unnamed argument
8208 matching an ellipsis). */
8209
8210 void
8211 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8212 tree type, int named ATTRIBUTE_UNUSED)
8213 {
8214 if (s390_function_arg_float (mode, type))
8215 {
8216 cum->fprs += 1;
8217 }
8218 else if (s390_function_arg_integer (mode, type))
8219 {
8220 int size = s390_function_arg_size (mode, type);
8221 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
8222 }
8223 else
8224 gcc_unreachable ();
8225 }
8226
8227 /* Define where to put the arguments to a function.
8228 Value is zero to push the argument on the stack,
8229 or a hard register in which to store the argument.
8230
8231 MODE is the argument's machine mode.
8232 TYPE is the data type of the argument (as a tree).
8233 This is null for libcalls where that information may
8234 not be available.
8235 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8236 the preceding args and about the function being called.
8237 NAMED is nonzero if this argument is a named parameter
8238 (otherwise it is an extra parameter matching an ellipsis).
8239
8240 On S/390, we use general purpose registers 2 through 6 to
8241 pass integer, pointer, and certain structure arguments, and
8242 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8243 to pass floating point arguments. All remaining arguments
8244 are pushed to the stack. */
8245
8246 rtx
8247 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8248 int named ATTRIBUTE_UNUSED)
8249 {
8250 if (s390_function_arg_float (mode, type))
8251 {
8252 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8253 return 0;
8254 else
8255 return gen_rtx_REG (mode, cum->fprs + 16);
8256 }
8257 else if (s390_function_arg_integer (mode, type))
8258 {
8259 int size = s390_function_arg_size (mode, type);
8260 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
8261
8262 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8263 return 0;
8264 else
8265 return gen_rtx_REG (mode, cum->gprs + 2);
8266 }
8267
8268 /* After the real arguments, expand_call calls us once again
8269 with a void_type_node type. Whatever we return here is
8270 passed as operand 2 to the call expanders.
8271
8272 We don't need this feature ... */
8273 else if (type == void_type_node)
8274 return const0_rtx;
8275
8276 gcc_unreachable ();
8277 }
8278
8279 /* Return true if return values of type TYPE should be returned
8280 in a memory buffer whose address is passed by the caller as
8281 hidden first argument. */
8282
8283 static bool
8284 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8285 {
8286 /* We accept small integral (and similar) types. */
8287 if (INTEGRAL_TYPE_P (type)
8288 || POINTER_TYPE_P (type)
8289 || TREE_CODE (type) == OFFSET_TYPE
8290 || TREE_CODE (type) == REAL_TYPE)
8291 return int_size_in_bytes (type) > 8;
8292
8293 /* Aggregates and similar constructs are always returned
8294 in memory. */
8295 if (AGGREGATE_TYPE_P (type)
8296 || TREE_CODE (type) == COMPLEX_TYPE
8297 || TREE_CODE (type) == VECTOR_TYPE)
8298 return true;
8299
8300 /* ??? We get called on all sorts of random stuff from
8301 aggregate_value_p. We can't abort, but it's not clear
8302 what's safe to return. Pretend it's a struct I guess. */
8303 return true;
8304 }
8305
8306 /* Define where to return a (scalar) value of type TYPE.
8307 If TYPE is null, define where to return a (scalar)
8308 value of mode MODE from a libcall. */
8309
8310 rtx
8311 s390_function_value (const_tree type, enum machine_mode mode)
8312 {
8313 if (type)
8314 {
8315 int unsignedp = TYPE_UNSIGNED (type);
8316 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
8317 }
8318
8319 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8320 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8321
8322 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8323 return gen_rtx_REG (mode, 16);
8324 else
8325 return gen_rtx_REG (mode, 2);
8326 }
8327
8328
8329 /* Create and return the va_list datatype.
8330
8331 On S/390, va_list is an array type equivalent to
8332
8333 typedef struct __va_list_tag
8334 {
8335 long __gpr;
8336 long __fpr;
8337 void *__overflow_arg_area;
8338 void *__reg_save_area;
8339 } va_list[1];
8340
8341 where __gpr and __fpr hold the number of general purpose
8342 or floating point arguments used up to now, respectively,
8343 __overflow_arg_area points to the stack location of the
8344 next argument passed on the stack, and __reg_save_area
8345 always points to the start of the register area in the
8346 call frame of the current function. The function prologue
8347 saves all registers used for argument passing into this
8348 area if the function uses variable arguments. */
8349
8350 static tree
8351 s390_build_builtin_va_list (void)
8352 {
8353 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8354
8355 record = lang_hooks.types.make_type (RECORD_TYPE);
8356
8357 type_decl =
8358 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
8359
8360 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
8361 long_integer_type_node);
8362 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
8363 long_integer_type_node);
8364 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
8365 ptr_type_node);
8366 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
8367 ptr_type_node);
8368
8369 va_list_gpr_counter_field = f_gpr;
8370 va_list_fpr_counter_field = f_fpr;
8371
8372 DECL_FIELD_CONTEXT (f_gpr) = record;
8373 DECL_FIELD_CONTEXT (f_fpr) = record;
8374 DECL_FIELD_CONTEXT (f_ovf) = record;
8375 DECL_FIELD_CONTEXT (f_sav) = record;
8376
8377 TREE_CHAIN (record) = type_decl;
8378 TYPE_NAME (record) = type_decl;
8379 TYPE_FIELDS (record) = f_gpr;
8380 TREE_CHAIN (f_gpr) = f_fpr;
8381 TREE_CHAIN (f_fpr) = f_ovf;
8382 TREE_CHAIN (f_ovf) = f_sav;
8383
8384 layout_type (record);
8385
8386 /* The correct type is an array type of one element. */
8387 return build_array_type (record, build_index_type (size_zero_node));
8388 }
8389
8390 /* Implement va_start by filling the va_list structure VALIST.
8391 STDARG_P is always true, and ignored.
8392 NEXTARG points to the first anonymous stack argument.
8393
8394 The following global variables are used to initialize
8395 the va_list structure:
8396
8397 crtl->args.info:
8398 holds number of gprs and fprs used for named arguments.
8399 crtl->args.arg_offset_rtx:
8400 holds the offset of the first anonymous stack argument
8401 (relative to the virtual arg pointer). */
8402
8403 static void
8404 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8405 {
8406 HOST_WIDE_INT n_gpr, n_fpr;
8407 int off;
8408 tree f_gpr, f_fpr, f_ovf, f_sav;
8409 tree gpr, fpr, ovf, sav, t;
8410
8411 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8412 f_fpr = TREE_CHAIN (f_gpr);
8413 f_ovf = TREE_CHAIN (f_fpr);
8414 f_sav = TREE_CHAIN (f_ovf);
8415
8416 valist = build_va_arg_indirect_ref (valist);
8417 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8418 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8419 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8420 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8421
8422 /* Count number of gp and fp argument registers used. */
8423
8424 n_gpr = crtl->args.info.gprs;
8425 n_fpr = crtl->args.info.fprs;
8426
8427 if (cfun->va_list_gpr_size)
8428 {
8429 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8430 build_int_cst (NULL_TREE, n_gpr));
8431 TREE_SIDE_EFFECTS (t) = 1;
8432 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8433 }
8434
8435 if (cfun->va_list_fpr_size)
8436 {
8437 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8438 build_int_cst (NULL_TREE, n_fpr));
8439 TREE_SIDE_EFFECTS (t) = 1;
8440 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8441 }
8442
8443 /* Find the overflow area. */
8444 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8445 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8446 {
8447 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8448
8449 off = INTVAL (crtl->args.arg_offset_rtx);
8450 off = off < 0 ? 0 : off;
8451 if (TARGET_DEBUG_ARG)
8452 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8453 (int)n_gpr, (int)n_fpr, off);
8454
8455 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8456
8457 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8458 TREE_SIDE_EFFECTS (t) = 1;
8459 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8460 }
8461
8462 /* Find the register save area. */
8463 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8464 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8465 {
8466 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8467 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8468 size_int (-RETURN_REGNUM * UNITS_PER_WORD));
8469
8470 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8471 TREE_SIDE_EFFECTS (t) = 1;
8472 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8473 }
8474 }
8475
8476 /* Implement va_arg by updating the va_list structure
8477 VALIST as required to retrieve an argument of type
8478 TYPE, and returning that argument.
8479
8480 Generates code equivalent to:
8481
8482 if (integral value) {
8483 if (size <= 4 && args.gpr < 5 ||
8484 size > 4 && args.gpr < 4 )
8485 ret = args.reg_save_area[args.gpr+8]
8486 else
8487 ret = *args.overflow_arg_area++;
8488 } else if (float value) {
8489 if (args.fgpr < 2)
8490 ret = args.reg_save_area[args.fpr+64]
8491 else
8492 ret = *args.overflow_arg_area++;
8493 } else if (aggregate value) {
8494 if (args.gpr < 5)
8495 ret = *args.reg_save_area[args.gpr]
8496 else
8497 ret = **args.overflow_arg_area++;
8498 } */
8499
8500 static tree
8501 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8502 gimple_seq *post_p ATTRIBUTE_UNUSED)
8503 {
8504 tree f_gpr, f_fpr, f_ovf, f_sav;
8505 tree gpr, fpr, ovf, sav, reg, t, u;
8506 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8507 tree lab_false, lab_over, addr;
8508
8509 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8510 f_fpr = TREE_CHAIN (f_gpr);
8511 f_ovf = TREE_CHAIN (f_fpr);
8512 f_sav = TREE_CHAIN (f_ovf);
8513
8514 valist = build_va_arg_indirect_ref (valist);
8515 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8516 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8517 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8518
8519 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8520 both appear on a lhs. */
8521 valist = unshare_expr (valist);
8522 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8523
8524 size = int_size_in_bytes (type);
8525
8526 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8527 {
8528 if (TARGET_DEBUG_ARG)
8529 {
8530 fprintf (stderr, "va_arg: aggregate type");
8531 debug_tree (type);
8532 }
8533
8534 /* Aggregates are passed by reference. */
8535 indirect_p = 1;
8536 reg = gpr;
8537 n_reg = 1;
8538
8539 /* kernel stack layout on 31 bit: It is assumed here that no padding
8540 will be added by s390_frame_info because for va_args always an even
8541 number of gprs has to be saved r15-r2 = 14 regs. */
8542 sav_ofs = 2 * UNITS_PER_WORD;
8543 sav_scale = UNITS_PER_WORD;
8544 size = UNITS_PER_WORD;
8545 max_reg = GP_ARG_NUM_REG - n_reg;
8546 }
8547 else if (s390_function_arg_float (TYPE_MODE (type), type))
8548 {
8549 if (TARGET_DEBUG_ARG)
8550 {
8551 fprintf (stderr, "va_arg: float type");
8552 debug_tree (type);
8553 }
8554
8555 /* FP args go in FP registers, if present. */
8556 indirect_p = 0;
8557 reg = fpr;
8558 n_reg = 1;
8559 sav_ofs = 16 * UNITS_PER_WORD;
8560 sav_scale = 8;
8561 max_reg = FP_ARG_NUM_REG - n_reg;
8562 }
8563 else
8564 {
8565 if (TARGET_DEBUG_ARG)
8566 {
8567 fprintf (stderr, "va_arg: other type");
8568 debug_tree (type);
8569 }
8570
8571 /* Otherwise into GP registers. */
8572 indirect_p = 0;
8573 reg = gpr;
8574 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8575
8576 /* kernel stack layout on 31 bit: It is assumed here that no padding
8577 will be added by s390_frame_info because for va_args always an even
8578 number of gprs has to be saved r15-r2 = 14 regs. */
8579 sav_ofs = 2 * UNITS_PER_WORD;
8580
8581 if (size < UNITS_PER_WORD)
8582 sav_ofs += UNITS_PER_WORD - size;
8583
8584 sav_scale = UNITS_PER_WORD;
8585 max_reg = GP_ARG_NUM_REG - n_reg;
8586 }
8587
8588 /* Pull the value out of the saved registers ... */
8589
8590 lab_false = create_artificial_label ();
8591 lab_over = create_artificial_label ();
8592 addr = create_tmp_var (ptr_type_node, "addr");
8593 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
8594
8595 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8596 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8597 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8598 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8599 gimplify_and_add (t, pre_p);
8600
8601 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8602 size_int (sav_ofs));
8603 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8604 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8605 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8606
8607 gimplify_assign (addr, t, pre_p);
8608
8609 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8610
8611 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8612
8613
8614 /* ... Otherwise out of the overflow area. */
8615
8616 t = ovf;
8617 if (size < UNITS_PER_WORD)
8618 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8619 size_int (UNITS_PER_WORD - size));
8620
8621 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8622
8623 gimplify_assign (addr, t, pre_p);
8624
8625 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8626 size_int (size));
8627 gimplify_assign (ovf, t, pre_p);
8628
8629 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8630
8631
8632 /* Increment register save count. */
8633
8634 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8635 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8636 gimplify_and_add (u, pre_p);
8637
8638 if (indirect_p)
8639 {
8640 t = build_pointer_type (build_pointer_type (type));
8641 addr = fold_convert (t, addr);
8642 addr = build_va_arg_indirect_ref (addr);
8643 }
8644 else
8645 {
8646 t = build_pointer_type (type);
8647 addr = fold_convert (t, addr);
8648 }
8649
8650 return build_va_arg_indirect_ref (addr);
8651 }
8652
8653
8654 /* Builtins. */
8655
8656 enum s390_builtin
8657 {
8658 S390_BUILTIN_THREAD_POINTER,
8659 S390_BUILTIN_SET_THREAD_POINTER,
8660
8661 S390_BUILTIN_max
8662 };
8663
8664 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8665 CODE_FOR_get_tp_64,
8666 CODE_FOR_set_tp_64
8667 };
8668
8669 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8670 CODE_FOR_get_tp_31,
8671 CODE_FOR_set_tp_31
8672 };
8673
8674 static void
8675 s390_init_builtins (void)
8676 {
8677 tree ftype;
8678
8679 ftype = build_function_type (ptr_type_node, void_list_node);
8680 add_builtin_function ("__builtin_thread_pointer", ftype,
8681 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8682 NULL, NULL_TREE);
8683
8684 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8685 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8686 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8687 NULL, NULL_TREE);
8688 }
8689
8690 /* Expand an expression EXP that calls a built-in function,
8691 with result going to TARGET if that's convenient
8692 (and in mode MODE if that's convenient).
8693 SUBTARGET may be used as the target for computing one of EXP's operands.
8694 IGNORE is nonzero if the value is to be ignored. */
8695
8696 static rtx
8697 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8698 enum machine_mode mode ATTRIBUTE_UNUSED,
8699 int ignore ATTRIBUTE_UNUSED)
8700 {
8701 #define MAX_ARGS 2
8702
8703 unsigned int const *code_for_builtin =
8704 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8705
8706 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8707 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8708 enum insn_code icode;
8709 rtx op[MAX_ARGS], pat;
8710 int arity;
8711 bool nonvoid;
8712 tree arg;
8713 call_expr_arg_iterator iter;
8714
8715 if (fcode >= S390_BUILTIN_max)
8716 internal_error ("bad builtin fcode");
8717 icode = code_for_builtin[fcode];
8718 if (icode == 0)
8719 internal_error ("bad builtin fcode");
8720
8721 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8722
8723 arity = 0;
8724 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8725 {
8726 const struct insn_operand_data *insn_op;
8727
8728 if (arg == error_mark_node)
8729 return NULL_RTX;
8730 if (arity > MAX_ARGS)
8731 return NULL_RTX;
8732
8733 insn_op = &insn_data[icode].operand[arity + nonvoid];
8734
8735 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8736
8737 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8738 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8739 arity++;
8740 }
8741
8742 if (nonvoid)
8743 {
8744 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8745 if (!target
8746 || GET_MODE (target) != tmode
8747 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8748 target = gen_reg_rtx (tmode);
8749 }
8750
8751 switch (arity)
8752 {
8753 case 0:
8754 pat = GEN_FCN (icode) (target);
8755 break;
8756 case 1:
8757 if (nonvoid)
8758 pat = GEN_FCN (icode) (target, op[0]);
8759 else
8760 pat = GEN_FCN (icode) (op[0]);
8761 break;
8762 case 2:
8763 pat = GEN_FCN (icode) (target, op[0], op[1]);
8764 break;
8765 default:
8766 gcc_unreachable ();
8767 }
8768 if (!pat)
8769 return NULL_RTX;
8770 emit_insn (pat);
8771
8772 if (nonvoid)
8773 return target;
8774 else
8775 return const0_rtx;
8776 }
8777
8778
8779 /* Output assembly code for the trampoline template to
8780 stdio stream FILE.
8781
8782 On S/390, we use gpr 1 internally in the trampoline code;
8783 gpr 0 is used to hold the static chain. */
8784
8785 void
8786 s390_trampoline_template (FILE *file)
8787 {
8788 rtx op[2];
8789 op[0] = gen_rtx_REG (Pmode, 0);
8790 op[1] = gen_rtx_REG (Pmode, 1);
8791
8792 if (TARGET_64BIT)
8793 {
8794 output_asm_insn ("basr\t%1,0", op);
8795 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8796 output_asm_insn ("br\t%1", op);
8797 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8798 }
8799 else
8800 {
8801 output_asm_insn ("basr\t%1,0", op);
8802 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8803 output_asm_insn ("br\t%1", op);
8804 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8805 }
8806 }
8807
8808 /* Emit RTL insns to initialize the variable parts of a trampoline.
8809 FNADDR is an RTX for the address of the function's pure code.
8810 CXT is an RTX for the static chain value for the function. */
8811
8812 void
8813 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8814 {
8815 emit_move_insn (gen_rtx_MEM (Pmode,
8816 memory_address (Pmode,
8817 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8818 emit_move_insn (gen_rtx_MEM (Pmode,
8819 memory_address (Pmode,
8820 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8821 }
8822
8823 /* Output assembler code to FILE to increment profiler label # LABELNO
8824 for profiling a function entry. */
8825
8826 void
8827 s390_function_profiler (FILE *file, int labelno)
8828 {
8829 rtx op[7];
8830
8831 char label[128];
8832 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8833
8834 fprintf (file, "# function profiler \n");
8835
8836 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8837 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8838 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8839
8840 op[2] = gen_rtx_REG (Pmode, 1);
8841 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8842 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8843
8844 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8845 if (flag_pic)
8846 {
8847 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8848 op[4] = gen_rtx_CONST (Pmode, op[4]);
8849 }
8850
8851 if (TARGET_64BIT)
8852 {
8853 output_asm_insn ("stg\t%0,%1", op);
8854 output_asm_insn ("larl\t%2,%3", op);
8855 output_asm_insn ("brasl\t%0,%4", op);
8856 output_asm_insn ("lg\t%0,%1", op);
8857 }
8858 else if (!flag_pic)
8859 {
8860 op[6] = gen_label_rtx ();
8861
8862 output_asm_insn ("st\t%0,%1", op);
8863 output_asm_insn ("bras\t%2,%l6", op);
8864 output_asm_insn (".long\t%4", op);
8865 output_asm_insn (".long\t%3", op);
8866 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8867 output_asm_insn ("l\t%0,0(%2)", op);
8868 output_asm_insn ("l\t%2,4(%2)", op);
8869 output_asm_insn ("basr\t%0,%0", op);
8870 output_asm_insn ("l\t%0,%1", op);
8871 }
8872 else
8873 {
8874 op[5] = gen_label_rtx ();
8875 op[6] = gen_label_rtx ();
8876
8877 output_asm_insn ("st\t%0,%1", op);
8878 output_asm_insn ("bras\t%2,%l6", op);
8879 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8880 output_asm_insn (".long\t%4-%l5", op);
8881 output_asm_insn (".long\t%3-%l5", op);
8882 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8883 output_asm_insn ("lr\t%0,%2", op);
8884 output_asm_insn ("a\t%0,0(%2)", op);
8885 output_asm_insn ("a\t%2,4(%2)", op);
8886 output_asm_insn ("basr\t%0,%0", op);
8887 output_asm_insn ("l\t%0,%1", op);
8888 }
8889 }
8890
8891 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8892 into its SYMBOL_REF_FLAGS. */
8893
8894 static void
8895 s390_encode_section_info (tree decl, rtx rtl, int first)
8896 {
8897 default_encode_section_info (decl, rtl, first);
8898
8899 if (TREE_CODE (decl) == VAR_DECL)
8900 {
8901 /* If a variable has a forced alignment to < 2 bytes, mark it
8902 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
8903 operand. */
8904 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8905 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8906 if (!DECL_SIZE (decl)
8907 || !DECL_ALIGN (decl)
8908 || !host_integerp (DECL_SIZE (decl), 0)
8909 || (DECL_ALIGN (decl) <= 64
8910 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
8911 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8912 }
8913
8914 /* Literal pool references don't have a decl so they are handled
8915 differently here. We rely on the information in the MEM_ALIGN
8916 entry to decide upon natural alignment. */
8917 if (MEM_P (rtl)
8918 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
8919 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
8920 && (MEM_ALIGN (rtl) == 0
8921 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
8922 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8923 }
8924
8925 /* Output thunk to FILE that implements a C++ virtual function call (with
8926 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8927 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8928 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8929 relative to the resulting this pointer. */
8930
8931 static void
8932 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8933 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8934 tree function)
8935 {
8936 rtx op[10];
8937 int nonlocal = 0;
8938
8939 /* Operand 0 is the target function. */
8940 op[0] = XEXP (DECL_RTL (function), 0);
8941 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8942 {
8943 nonlocal = 1;
8944 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8945 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8946 op[0] = gen_rtx_CONST (Pmode, op[0]);
8947 }
8948
8949 /* Operand 1 is the 'this' pointer. */
8950 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8951 op[1] = gen_rtx_REG (Pmode, 3);
8952 else
8953 op[1] = gen_rtx_REG (Pmode, 2);
8954
8955 /* Operand 2 is the delta. */
8956 op[2] = GEN_INT (delta);
8957
8958 /* Operand 3 is the vcall_offset. */
8959 op[3] = GEN_INT (vcall_offset);
8960
8961 /* Operand 4 is the temporary register. */
8962 op[4] = gen_rtx_REG (Pmode, 1);
8963
8964 /* Operands 5 to 8 can be used as labels. */
8965 op[5] = NULL_RTX;
8966 op[6] = NULL_RTX;
8967 op[7] = NULL_RTX;
8968 op[8] = NULL_RTX;
8969
8970 /* Operand 9 can be used for temporary register. */
8971 op[9] = NULL_RTX;
8972
8973 /* Generate code. */
8974 if (TARGET_64BIT)
8975 {
8976 /* Setup literal pool pointer if required. */
8977 if ((!DISP_IN_RANGE (delta)
8978 && !CONST_OK_FOR_K (delta)
8979 && !CONST_OK_FOR_Os (delta))
8980 || (!DISP_IN_RANGE (vcall_offset)
8981 && !CONST_OK_FOR_K (vcall_offset)
8982 && !CONST_OK_FOR_Os (vcall_offset)))
8983 {
8984 op[5] = gen_label_rtx ();
8985 output_asm_insn ("larl\t%4,%5", op);
8986 }
8987
8988 /* Add DELTA to this pointer. */
8989 if (delta)
8990 {
8991 if (CONST_OK_FOR_J (delta))
8992 output_asm_insn ("la\t%1,%2(%1)", op);
8993 else if (DISP_IN_RANGE (delta))
8994 output_asm_insn ("lay\t%1,%2(%1)", op);
8995 else if (CONST_OK_FOR_K (delta))
8996 output_asm_insn ("aghi\t%1,%2", op);
8997 else if (CONST_OK_FOR_Os (delta))
8998 output_asm_insn ("agfi\t%1,%2", op);
8999 else
9000 {
9001 op[6] = gen_label_rtx ();
9002 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9003 }
9004 }
9005
9006 /* Perform vcall adjustment. */
9007 if (vcall_offset)
9008 {
9009 if (DISP_IN_RANGE (vcall_offset))
9010 {
9011 output_asm_insn ("lg\t%4,0(%1)", op);
9012 output_asm_insn ("ag\t%1,%3(%4)", op);
9013 }
9014 else if (CONST_OK_FOR_K (vcall_offset))
9015 {
9016 output_asm_insn ("lghi\t%4,%3", op);
9017 output_asm_insn ("ag\t%4,0(%1)", op);
9018 output_asm_insn ("ag\t%1,0(%4)", op);
9019 }
9020 else if (CONST_OK_FOR_Os (vcall_offset))
9021 {
9022 output_asm_insn ("lgfi\t%4,%3", op);
9023 output_asm_insn ("ag\t%4,0(%1)", op);
9024 output_asm_insn ("ag\t%1,0(%4)", op);
9025 }
9026 else
9027 {
9028 op[7] = gen_label_rtx ();
9029 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9030 output_asm_insn ("ag\t%4,0(%1)", op);
9031 output_asm_insn ("ag\t%1,0(%4)", op);
9032 }
9033 }
9034
9035 /* Jump to target. */
9036 output_asm_insn ("jg\t%0", op);
9037
9038 /* Output literal pool if required. */
9039 if (op[5])
9040 {
9041 output_asm_insn (".align\t4", op);
9042 targetm.asm_out.internal_label (file, "L",
9043 CODE_LABEL_NUMBER (op[5]));
9044 }
9045 if (op[6])
9046 {
9047 targetm.asm_out.internal_label (file, "L",
9048 CODE_LABEL_NUMBER (op[6]));
9049 output_asm_insn (".long\t%2", op);
9050 }
9051 if (op[7])
9052 {
9053 targetm.asm_out.internal_label (file, "L",
9054 CODE_LABEL_NUMBER (op[7]));
9055 output_asm_insn (".long\t%3", op);
9056 }
9057 }
9058 else
9059 {
9060 /* Setup base pointer if required. */
9061 if (!vcall_offset
9062 || (!DISP_IN_RANGE (delta)
9063 && !CONST_OK_FOR_K (delta)
9064 && !CONST_OK_FOR_Os (delta))
9065 || (!DISP_IN_RANGE (delta)
9066 && !CONST_OK_FOR_K (vcall_offset)
9067 && !CONST_OK_FOR_Os (vcall_offset)))
9068 {
9069 op[5] = gen_label_rtx ();
9070 output_asm_insn ("basr\t%4,0", op);
9071 targetm.asm_out.internal_label (file, "L",
9072 CODE_LABEL_NUMBER (op[5]));
9073 }
9074
9075 /* Add DELTA to this pointer. */
9076 if (delta)
9077 {
9078 if (CONST_OK_FOR_J (delta))
9079 output_asm_insn ("la\t%1,%2(%1)", op);
9080 else if (DISP_IN_RANGE (delta))
9081 output_asm_insn ("lay\t%1,%2(%1)", op);
9082 else if (CONST_OK_FOR_K (delta))
9083 output_asm_insn ("ahi\t%1,%2", op);
9084 else if (CONST_OK_FOR_Os (delta))
9085 output_asm_insn ("afi\t%1,%2", op);
9086 else
9087 {
9088 op[6] = gen_label_rtx ();
9089 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9090 }
9091 }
9092
9093 /* Perform vcall adjustment. */
9094 if (vcall_offset)
9095 {
9096 if (CONST_OK_FOR_J (vcall_offset))
9097 {
9098 output_asm_insn ("l\t%4,0(%1)", op);
9099 output_asm_insn ("a\t%1,%3(%4)", op);
9100 }
9101 else if (DISP_IN_RANGE (vcall_offset))
9102 {
9103 output_asm_insn ("l\t%4,0(%1)", op);
9104 output_asm_insn ("ay\t%1,%3(%4)", op);
9105 }
9106 else if (CONST_OK_FOR_K (vcall_offset))
9107 {
9108 output_asm_insn ("lhi\t%4,%3", op);
9109 output_asm_insn ("a\t%4,0(%1)", op);
9110 output_asm_insn ("a\t%1,0(%4)", op);
9111 }
9112 else if (CONST_OK_FOR_Os (vcall_offset))
9113 {
9114 output_asm_insn ("iilf\t%4,%3", op);
9115 output_asm_insn ("a\t%4,0(%1)", op);
9116 output_asm_insn ("a\t%1,0(%4)", op);
9117 }
9118 else
9119 {
9120 op[7] = gen_label_rtx ();
9121 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9122 output_asm_insn ("a\t%4,0(%1)", op);
9123 output_asm_insn ("a\t%1,0(%4)", op);
9124 }
9125
9126 /* We had to clobber the base pointer register.
9127 Re-setup the base pointer (with a different base). */
9128 op[5] = gen_label_rtx ();
9129 output_asm_insn ("basr\t%4,0", op);
9130 targetm.asm_out.internal_label (file, "L",
9131 CODE_LABEL_NUMBER (op[5]));
9132 }
9133
9134 /* Jump to target. */
9135 op[8] = gen_label_rtx ();
9136
9137 if (!flag_pic)
9138 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9139 else if (!nonlocal)
9140 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9141 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9142 else if (flag_pic == 1)
9143 {
9144 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9145 output_asm_insn ("l\t%4,%0(%4)", op);
9146 }
9147 else if (flag_pic == 2)
9148 {
9149 op[9] = gen_rtx_REG (Pmode, 0);
9150 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9151 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9152 output_asm_insn ("ar\t%4,%9", op);
9153 output_asm_insn ("l\t%4,0(%4)", op);
9154 }
9155
9156 output_asm_insn ("br\t%4", op);
9157
9158 /* Output literal pool. */
9159 output_asm_insn (".align\t4", op);
9160
9161 if (nonlocal && flag_pic == 2)
9162 output_asm_insn (".long\t%0", op);
9163 if (nonlocal)
9164 {
9165 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9166 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9167 }
9168
9169 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9170 if (!flag_pic)
9171 output_asm_insn (".long\t%0", op);
9172 else
9173 output_asm_insn (".long\t%0-%5", op);
9174
9175 if (op[6])
9176 {
9177 targetm.asm_out.internal_label (file, "L",
9178 CODE_LABEL_NUMBER (op[6]));
9179 output_asm_insn (".long\t%2", op);
9180 }
9181 if (op[7])
9182 {
9183 targetm.asm_out.internal_label (file, "L",
9184 CODE_LABEL_NUMBER (op[7]));
9185 output_asm_insn (".long\t%3", op);
9186 }
9187 }
9188 }
9189
9190 static bool
9191 s390_valid_pointer_mode (enum machine_mode mode)
9192 {
9193 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9194 }
9195
9196 /* Checks whether the given CALL_EXPR would use a caller
9197 saved register. This is used to decide whether sibling call
9198 optimization could be performed on the respective function
9199 call. */
9200
9201 static bool
9202 s390_call_saved_register_used (tree call_expr)
9203 {
9204 CUMULATIVE_ARGS cum;
9205 tree parameter;
9206 enum machine_mode mode;
9207 tree type;
9208 rtx parm_rtx;
9209 int reg, i;
9210
9211 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9212
9213 for (i = 0; i < call_expr_nargs (call_expr); i++)
9214 {
9215 parameter = CALL_EXPR_ARG (call_expr, i);
9216 gcc_assert (parameter);
9217
9218 /* For an undeclared variable passed as parameter we will get
9219 an ERROR_MARK node here. */
9220 if (TREE_CODE (parameter) == ERROR_MARK)
9221 return true;
9222
9223 type = TREE_TYPE (parameter);
9224 gcc_assert (type);
9225
9226 mode = TYPE_MODE (type);
9227 gcc_assert (mode);
9228
9229 if (pass_by_reference (&cum, mode, type, true))
9230 {
9231 mode = Pmode;
9232 type = build_pointer_type (type);
9233 }
9234
9235 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9236
9237 s390_function_arg_advance (&cum, mode, type, 0);
9238
9239 if (parm_rtx && REG_P (parm_rtx))
9240 {
9241 for (reg = 0;
9242 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9243 reg++)
9244 if (! call_used_regs[reg + REGNO (parm_rtx)])
9245 return true;
9246 }
9247 }
9248 return false;
9249 }
9250
9251 /* Return true if the given call expression can be
9252 turned into a sibling call.
9253 DECL holds the declaration of the function to be called whereas
9254 EXP is the call expression itself. */
9255
9256 static bool
9257 s390_function_ok_for_sibcall (tree decl, tree exp)
9258 {
9259 /* The TPF epilogue uses register 1. */
9260 if (TARGET_TPF_PROFILING)
9261 return false;
9262
9263 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9264 which would have to be restored before the sibcall. */
9265 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9266 return false;
9267
9268 /* Register 6 on s390 is available as an argument register but unfortunately
9269 "caller saved". This makes functions needing this register for arguments
9270 not suitable for sibcalls. */
9271 return !s390_call_saved_register_used (exp);
9272 }
9273
9274 /* Return the fixed registers used for condition codes. */
9275
9276 static bool
9277 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9278 {
9279 *p1 = CC_REGNUM;
9280 *p2 = INVALID_REGNUM;
9281
9282 return true;
9283 }
9284
9285 /* This function is used by the call expanders of the machine description.
9286 It emits the call insn itself together with the necessary operations
9287 to adjust the target address and returns the emitted insn.
9288 ADDR_LOCATION is the target address rtx
9289 TLS_CALL the location of the thread-local symbol
9290 RESULT_REG the register where the result of the call should be stored
9291 RETADDR_REG the register where the return address should be stored
9292 If this parameter is NULL_RTX the call is considered
9293 to be a sibling call. */
9294
9295 rtx
9296 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9297 rtx retaddr_reg)
9298 {
9299 bool plt_call = false;
9300 rtx insn;
9301 rtx call;
9302 rtx clobber;
9303 rtvec vec;
9304
9305 /* Direct function calls need special treatment. */
9306 if (GET_CODE (addr_location) == SYMBOL_REF)
9307 {
9308 /* When calling a global routine in PIC mode, we must
9309 replace the symbol itself with the PLT stub. */
9310 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9311 {
9312 addr_location = gen_rtx_UNSPEC (Pmode,
9313 gen_rtvec (1, addr_location),
9314 UNSPEC_PLT);
9315 addr_location = gen_rtx_CONST (Pmode, addr_location);
9316 plt_call = true;
9317 }
9318
9319 /* Unless we can use the bras(l) insn, force the
9320 routine address into a register. */
9321 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9322 {
9323 if (flag_pic)
9324 addr_location = legitimize_pic_address (addr_location, 0);
9325 else
9326 addr_location = force_reg (Pmode, addr_location);
9327 }
9328 }
9329
9330 /* If it is already an indirect call or the code above moved the
9331 SYMBOL_REF to somewhere else make sure the address can be found in
9332 register 1. */
9333 if (retaddr_reg == NULL_RTX
9334 && GET_CODE (addr_location) != SYMBOL_REF
9335 && !plt_call)
9336 {
9337 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9338 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9339 }
9340
9341 addr_location = gen_rtx_MEM (QImode, addr_location);
9342 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9343
9344 if (result_reg != NULL_RTX)
9345 call = gen_rtx_SET (VOIDmode, result_reg, call);
9346
9347 if (retaddr_reg != NULL_RTX)
9348 {
9349 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9350
9351 if (tls_call != NULL_RTX)
9352 vec = gen_rtvec (3, call, clobber,
9353 gen_rtx_USE (VOIDmode, tls_call));
9354 else
9355 vec = gen_rtvec (2, call, clobber);
9356
9357 call = gen_rtx_PARALLEL (VOIDmode, vec);
9358 }
9359
9360 insn = emit_call_insn (call);
9361
9362 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9363 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9364 {
9365 /* s390_function_ok_for_sibcall should
9366 have denied sibcalls in this case. */
9367 gcc_assert (retaddr_reg != NULL_RTX);
9368
9369 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9370 }
9371 return insn;
9372 }
9373
9374 /* Implement CONDITIONAL_REGISTER_USAGE. */
9375
9376 void
9377 s390_conditional_register_usage (void)
9378 {
9379 int i;
9380
9381 if (flag_pic)
9382 {
9383 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9384 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9385 }
9386 if (TARGET_CPU_ZARCH)
9387 {
9388 fixed_regs[BASE_REGNUM] = 0;
9389 call_used_regs[BASE_REGNUM] = 0;
9390 fixed_regs[RETURN_REGNUM] = 0;
9391 call_used_regs[RETURN_REGNUM] = 0;
9392 }
9393 if (TARGET_64BIT)
9394 {
9395 for (i = 24; i < 32; i++)
9396 call_used_regs[i] = call_really_used_regs[i] = 0;
9397 }
9398 else
9399 {
9400 for (i = 18; i < 20; i++)
9401 call_used_regs[i] = call_really_used_regs[i] = 0;
9402 }
9403
9404 if (TARGET_SOFT_FLOAT)
9405 {
9406 for (i = 16; i < 32; i++)
9407 call_used_regs[i] = fixed_regs[i] = 1;
9408 }
9409 }
9410
9411 /* Corresponding function to eh_return expander. */
9412
9413 static GTY(()) rtx s390_tpf_eh_return_symbol;
9414 void
9415 s390_emit_tpf_eh_return (rtx target)
9416 {
9417 rtx insn, reg;
9418
9419 if (!s390_tpf_eh_return_symbol)
9420 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9421
9422 reg = gen_rtx_REG (Pmode, 2);
9423
9424 emit_move_insn (reg, target);
9425 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9426 gen_rtx_REG (Pmode, RETURN_REGNUM));
9427 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9428
9429 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9430 }
9431
9432 /* Rework the prologue/epilogue to avoid saving/restoring
9433 registers unnecessarily. */
9434
9435 static void
9436 s390_optimize_prologue (void)
9437 {
9438 rtx insn, new_insn, next_insn;
9439
9440 /* Do a final recompute of the frame-related data. */
9441
9442 s390_update_frame_layout ();
9443
9444 /* If all special registers are in fact used, there's nothing we
9445 can do, so no point in walking the insn list. */
9446
9447 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9448 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9449 && (TARGET_CPU_ZARCH
9450 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9451 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9452 return;
9453
9454 /* Search for prologue/epilogue insns and replace them. */
9455
9456 for (insn = get_insns (); insn; insn = next_insn)
9457 {
9458 int first, last, off;
9459 rtx set, base, offset;
9460
9461 next_insn = NEXT_INSN (insn);
9462
9463 if (GET_CODE (insn) != INSN)
9464 continue;
9465
9466 if (GET_CODE (PATTERN (insn)) == PARALLEL
9467 && store_multiple_operation (PATTERN (insn), VOIDmode))
9468 {
9469 set = XVECEXP (PATTERN (insn), 0, 0);
9470 first = REGNO (SET_SRC (set));
9471 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9472 offset = const0_rtx;
9473 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9474 off = INTVAL (offset);
9475
9476 if (GET_CODE (base) != REG || off < 0)
9477 continue;
9478 if (cfun_frame_layout.first_save_gpr != -1
9479 && (cfun_frame_layout.first_save_gpr < first
9480 || cfun_frame_layout.last_save_gpr > last))
9481 continue;
9482 if (REGNO (base) != STACK_POINTER_REGNUM
9483 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9484 continue;
9485 if (first > BASE_REGNUM || last < BASE_REGNUM)
9486 continue;
9487
9488 if (cfun_frame_layout.first_save_gpr != -1)
9489 {
9490 new_insn = save_gprs (base,
9491 off + (cfun_frame_layout.first_save_gpr
9492 - first) * UNITS_PER_WORD,
9493 cfun_frame_layout.first_save_gpr,
9494 cfun_frame_layout.last_save_gpr);
9495 new_insn = emit_insn_before (new_insn, insn);
9496 INSN_ADDRESSES_NEW (new_insn, -1);
9497 }
9498
9499 remove_insn (insn);
9500 continue;
9501 }
9502
9503 if (cfun_frame_layout.first_save_gpr == -1
9504 && GET_CODE (PATTERN (insn)) == SET
9505 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9506 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9507 || (!TARGET_CPU_ZARCH
9508 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9509 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9510 {
9511 set = PATTERN (insn);
9512 first = REGNO (SET_SRC (set));
9513 offset = const0_rtx;
9514 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9515 off = INTVAL (offset);
9516
9517 if (GET_CODE (base) != REG || off < 0)
9518 continue;
9519 if (REGNO (base) != STACK_POINTER_REGNUM
9520 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9521 continue;
9522
9523 remove_insn (insn);
9524 continue;
9525 }
9526
9527 if (GET_CODE (PATTERN (insn)) == PARALLEL
9528 && load_multiple_operation (PATTERN (insn), VOIDmode))
9529 {
9530 set = XVECEXP (PATTERN (insn), 0, 0);
9531 first = REGNO (SET_DEST (set));
9532 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9533 offset = const0_rtx;
9534 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9535 off = INTVAL (offset);
9536
9537 if (GET_CODE (base) != REG || off < 0)
9538 continue;
9539 if (cfun_frame_layout.first_restore_gpr != -1
9540 && (cfun_frame_layout.first_restore_gpr < first
9541 || cfun_frame_layout.last_restore_gpr > last))
9542 continue;
9543 if (REGNO (base) != STACK_POINTER_REGNUM
9544 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9545 continue;
9546 if (first > BASE_REGNUM || last < BASE_REGNUM)
9547 continue;
9548
9549 if (cfun_frame_layout.first_restore_gpr != -1)
9550 {
9551 new_insn = restore_gprs (base,
9552 off + (cfun_frame_layout.first_restore_gpr
9553 - first) * UNITS_PER_WORD,
9554 cfun_frame_layout.first_restore_gpr,
9555 cfun_frame_layout.last_restore_gpr);
9556 new_insn = emit_insn_before (new_insn, insn);
9557 INSN_ADDRESSES_NEW (new_insn, -1);
9558 }
9559
9560 remove_insn (insn);
9561 continue;
9562 }
9563
9564 if (cfun_frame_layout.first_restore_gpr == -1
9565 && GET_CODE (PATTERN (insn)) == SET
9566 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9567 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9568 || (!TARGET_CPU_ZARCH
9569 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9570 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9571 {
9572 set = PATTERN (insn);
9573 first = REGNO (SET_DEST (set));
9574 offset = const0_rtx;
9575 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9576 off = INTVAL (offset);
9577
9578 if (GET_CODE (base) != REG || off < 0)
9579 continue;
9580 if (REGNO (base) != STACK_POINTER_REGNUM
9581 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9582 continue;
9583
9584 remove_insn (insn);
9585 continue;
9586 }
9587 }
9588 }
9589
9590 /* Perform machine-dependent processing. */
9591
9592 static void
9593 s390_reorg (void)
9594 {
9595 bool pool_overflow = false;
9596
9597 /* Make sure all splits have been performed; splits after
9598 machine_dependent_reorg might confuse insn length counts. */
9599 split_all_insns_noflow ();
9600
9601 /* From here on decomposed literal pool addresses must be accepted. */
9602 cfun->machine->decomposed_literal_pool_addresses_ok_p = true;
9603
9604 /* Install the main literal pool and the associated base
9605 register load insns.
9606
9607 In addition, there are two problematic situations we need
9608 to correct:
9609
9610 - the literal pool might be > 4096 bytes in size, so that
9611 some of its elements cannot be directly accessed
9612
9613 - a branch target might be > 64K away from the branch, so that
9614 it is not possible to use a PC-relative instruction.
9615
9616 To fix those, we split the single literal pool into multiple
9617 pool chunks, reloading the pool base register at various
9618 points throughout the function to ensure it always points to
9619 the pool chunk the following code expects, and / or replace
9620 PC-relative branches by absolute branches.
9621
9622 However, the two problems are interdependent: splitting the
9623 literal pool can move a branch further away from its target,
9624 causing the 64K limit to overflow, and on the other hand,
9625 replacing a PC-relative branch by an absolute branch means
9626 we need to put the branch target address into the literal
9627 pool, possibly causing it to overflow.
9628
9629 So, we loop trying to fix up both problems until we manage
9630 to satisfy both conditions at the same time. Note that the
9631 loop is guaranteed to terminate as every pass of the loop
9632 strictly decreases the total number of PC-relative branches
9633 in the function. (This is not completely true as there
9634 might be branch-over-pool insns introduced by chunkify_start.
9635 Those never need to be split however.) */
9636
9637 for (;;)
9638 {
9639 struct constant_pool *pool = NULL;
9640
9641 /* Collect the literal pool. */
9642 if (!pool_overflow)
9643 {
9644 pool = s390_mainpool_start ();
9645 if (!pool)
9646 pool_overflow = true;
9647 }
9648
9649 /* If literal pool overflowed, start to chunkify it. */
9650 if (pool_overflow)
9651 pool = s390_chunkify_start ();
9652
9653 /* Split out-of-range branches. If this has created new
9654 literal pool entries, cancel current chunk list and
9655 recompute it. zSeries machines have large branch
9656 instructions, so we never need to split a branch. */
9657 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9658 {
9659 if (pool_overflow)
9660 s390_chunkify_cancel (pool);
9661 else
9662 s390_mainpool_cancel (pool);
9663
9664 continue;
9665 }
9666
9667 /* If we made it up to here, both conditions are satisfied.
9668 Finish up literal pool related changes. */
9669 if (pool_overflow)
9670 s390_chunkify_finish (pool);
9671 else
9672 s390_mainpool_finish (pool);
9673
9674 /* We're done splitting branches. */
9675 cfun->machine->split_branches_pending_p = false;
9676 break;
9677 }
9678
9679 /* Generate out-of-pool execute target insns. */
9680 if (TARGET_CPU_ZARCH)
9681 {
9682 rtx insn, label, target;
9683
9684 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9685 {
9686 label = s390_execute_label (insn);
9687 if (!label)
9688 continue;
9689
9690 gcc_assert (label != const0_rtx);
9691
9692 target = emit_label (XEXP (label, 0));
9693 INSN_ADDRESSES_NEW (target, -1);
9694
9695 target = emit_insn (s390_execute_target (insn));
9696 INSN_ADDRESSES_NEW (target, -1);
9697 }
9698 }
9699
9700 /* Try to optimize prologue and epilogue further. */
9701 s390_optimize_prologue ();
9702 }
9703
9704
9705 /* Initialize GCC target structure. */
9706
9707 #undef TARGET_ASM_ALIGNED_HI_OP
9708 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9709 #undef TARGET_ASM_ALIGNED_DI_OP
9710 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9711 #undef TARGET_ASM_INTEGER
9712 #define TARGET_ASM_INTEGER s390_assemble_integer
9713
9714 #undef TARGET_ASM_OPEN_PAREN
9715 #define TARGET_ASM_OPEN_PAREN ""
9716
9717 #undef TARGET_ASM_CLOSE_PAREN
9718 #define TARGET_ASM_CLOSE_PAREN ""
9719
9720 #undef TARGET_DEFAULT_TARGET_FLAGS
9721 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9722 #undef TARGET_HANDLE_OPTION
9723 #define TARGET_HANDLE_OPTION s390_handle_option
9724
9725 #undef TARGET_ENCODE_SECTION_INFO
9726 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9727
9728 #ifdef HAVE_AS_TLS
9729 #undef TARGET_HAVE_TLS
9730 #define TARGET_HAVE_TLS true
9731 #endif
9732 #undef TARGET_CANNOT_FORCE_CONST_MEM
9733 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9734
9735 #undef TARGET_DELEGITIMIZE_ADDRESS
9736 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9737
9738 #undef TARGET_RETURN_IN_MEMORY
9739 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9740
9741 #undef TARGET_INIT_BUILTINS
9742 #define TARGET_INIT_BUILTINS s390_init_builtins
9743 #undef TARGET_EXPAND_BUILTIN
9744 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9745
9746 #undef TARGET_ASM_OUTPUT_MI_THUNK
9747 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9748 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9749 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
9750
9751 #undef TARGET_SCHED_ADJUST_PRIORITY
9752 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9753 #undef TARGET_SCHED_ISSUE_RATE
9754 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9755 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9756 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9757
9758 #undef TARGET_CANNOT_COPY_INSN_P
9759 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9760 #undef TARGET_RTX_COSTS
9761 #define TARGET_RTX_COSTS s390_rtx_costs
9762 #undef TARGET_ADDRESS_COST
9763 #define TARGET_ADDRESS_COST s390_address_cost
9764
9765 #undef TARGET_MACHINE_DEPENDENT_REORG
9766 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9767
9768 #undef TARGET_VALID_POINTER_MODE
9769 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9770
9771 #undef TARGET_BUILD_BUILTIN_VA_LIST
9772 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9773 #undef TARGET_EXPAND_BUILTIN_VA_START
9774 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
9775 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9776 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9777
9778 #undef TARGET_PROMOTE_FUNCTION_ARGS
9779 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
9780 #undef TARGET_PROMOTE_FUNCTION_RETURN
9781 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
9782 #undef TARGET_PASS_BY_REFERENCE
9783 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9784
9785 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9786 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9787
9788 #undef TARGET_FIXED_CONDITION_CODE_REGS
9789 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9790
9791 #undef TARGET_CC_MODES_COMPATIBLE
9792 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9793
9794 #undef TARGET_INVALID_WITHIN_DOLOOP
9795 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
9796
9797 #ifdef HAVE_AS_TLS
9798 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9799 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9800 #endif
9801
9802 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9803 #undef TARGET_MANGLE_TYPE
9804 #define TARGET_MANGLE_TYPE s390_mangle_type
9805 #endif
9806
9807 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9808 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9809
9810 #undef TARGET_SECONDARY_RELOAD
9811 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
9812
9813 #undef TARGET_LIBGCC_CMP_RETURN_MODE
9814 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
9815
9816 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
9817 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
9818
9819 struct gcc_target targetm = TARGET_INITIALIZER;
9820
9821 #include "gt-s390.h"