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[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (10), /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (10), /* MADBR */
213 COSTS_N_INSNS (10), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 extern int reload_completed;
225
226 /* Structure used to hold the components of a S/390 memory
227 address. A legitimate address on S/390 is of the general
228 form
229 base + index + displacement
230 where any of the components is optional.
231
232 base and index are registers of the class ADDR_REGS,
233 displacement is an unsigned 12-bit immediate constant. */
234
235 struct s390_address
236 {
237 rtx base;
238 rtx indx;
239 rtx disp;
240 bool pointer;
241 bool literal_pool;
242 };
243
244 /* Which cpu are we tuning for. */
245 enum processor_type s390_tune = PROCESSOR_max;
246 int s390_tune_flags;
247 /* Which instruction set architecture to use. */
248 enum processor_type s390_arch;
249 int s390_arch_flags;
250
251 HOST_WIDE_INT s390_warn_framesize = 0;
252 HOST_WIDE_INT s390_stack_size = 0;
253 HOST_WIDE_INT s390_stack_guard = 0;
254
255 /* The following structure is embedded in the machine
256 specific part of struct function. */
257
258 struct GTY (()) s390_frame_layout
259 {
260 /* Offset within stack frame. */
261 HOST_WIDE_INT gprs_offset;
262 HOST_WIDE_INT f0_offset;
263 HOST_WIDE_INT f4_offset;
264 HOST_WIDE_INT f8_offset;
265 HOST_WIDE_INT backchain_offset;
266
267 /* Number of first and last gpr where slots in the register
268 save area are reserved for. */
269 int first_save_gpr_slot;
270 int last_save_gpr_slot;
271
272 /* Number of first and last gpr to be saved, restored. */
273 int first_save_gpr;
274 int first_restore_gpr;
275 int last_save_gpr;
276 int last_restore_gpr;
277
278 /* Bits standing for floating point registers. Set, if the
279 respective register has to be saved. Starting with reg 16 (f0)
280 at the rightmost bit.
281 Bit 15 - 8 7 6 5 4 3 2 1 0
282 fpr 15 - 8 7 5 3 1 6 4 2 0
283 reg 31 - 24 23 22 21 20 19 18 17 16 */
284 unsigned int fpr_bitmap;
285
286 /* Number of floating point registers f8-f15 which must be saved. */
287 int high_fprs;
288
289 /* Set if return address needs to be saved.
290 This flag is set by s390_return_addr_rtx if it could not use
291 the initial value of r14 and therefore depends on r14 saved
292 to the stack. */
293 bool save_return_addr_p;
294
295 /* Size of stack frame. */
296 HOST_WIDE_INT frame_size;
297 };
298
299 /* Define the structure for the machine field in struct function. */
300
301 struct GTY(()) machine_function
302 {
303 struct s390_frame_layout frame_layout;
304
305 /* Literal pool base register. */
306 rtx base_reg;
307
308 /* True if we may need to perform branch splitting. */
309 bool split_branches_pending_p;
310
311 /* Some local-dynamic TLS symbol name. */
312 const char *some_ld_name;
313
314 bool has_landing_pad_p;
315 };
316
317 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
318
319 #define cfun_frame_layout (cfun->machine->frame_layout)
320 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
321 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
322 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
323 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
324 (1 << (BITNUM)))
325 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
326 (1 << (BITNUM))))
327
328 /* Number of GPRs and FPRs used for argument passing. */
329 #define GP_ARG_NUM_REG 5
330 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
331
332 /* A couple of shortcuts. */
333 #define CONST_OK_FOR_J(x) \
334 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
335 #define CONST_OK_FOR_K(x) \
336 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
337 #define CONST_OK_FOR_Os(x) \
338 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
339 #define CONST_OK_FOR_Op(x) \
340 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
341 #define CONST_OK_FOR_On(x) \
342 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
343
344 #define REGNO_PAIR_OK(REGNO, MODE) \
345 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
346
347 static enum machine_mode
348 s390_libgcc_cmp_return_mode (void)
349 {
350 return TARGET_64BIT ? DImode : SImode;
351 }
352
353 static enum machine_mode
354 s390_libgcc_shift_count_mode (void)
355 {
356 return TARGET_64BIT ? DImode : SImode;
357 }
358
359 /* Return true if the back end supports mode MODE. */
360 static bool
361 s390_scalar_mode_supported_p (enum machine_mode mode)
362 {
363 if (DECIMAL_FLOAT_MODE_P (mode))
364 return true;
365 else
366 return default_scalar_mode_supported_p (mode);
367 }
368
369 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
370
371 void
372 s390_set_has_landing_pad_p (bool value)
373 {
374 cfun->machine->has_landing_pad_p = value;
375 }
376
377 /* If two condition code modes are compatible, return a condition code
378 mode which is compatible with both. Otherwise, return
379 VOIDmode. */
380
381 static enum machine_mode
382 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
383 {
384 if (m1 == m2)
385 return m1;
386
387 switch (m1)
388 {
389 case CCZmode:
390 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
391 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
392 return m2;
393 return VOIDmode;
394
395 case CCSmode:
396 case CCUmode:
397 case CCTmode:
398 case CCSRmode:
399 case CCURmode:
400 case CCZ1mode:
401 if (m2 == CCZmode)
402 return m1;
403
404 return VOIDmode;
405
406 default:
407 return VOIDmode;
408 }
409 return VOIDmode;
410 }
411
412 /* Return true if SET either doesn't set the CC register, or else
413 the source and destination have matching CC modes and that
414 CC mode is at least as constrained as REQ_MODE. */
415
416 static bool
417 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
418 {
419 enum machine_mode set_mode;
420
421 gcc_assert (GET_CODE (set) == SET);
422
423 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
424 return 1;
425
426 set_mode = GET_MODE (SET_DEST (set));
427 switch (set_mode)
428 {
429 case CCSmode:
430 case CCSRmode:
431 case CCUmode:
432 case CCURmode:
433 case CCLmode:
434 case CCL1mode:
435 case CCL2mode:
436 case CCL3mode:
437 case CCT1mode:
438 case CCT2mode:
439 case CCT3mode:
440 if (req_mode != set_mode)
441 return 0;
442 break;
443
444 case CCZmode:
445 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
446 && req_mode != CCSRmode && req_mode != CCURmode)
447 return 0;
448 break;
449
450 case CCAPmode:
451 case CCANmode:
452 if (req_mode != CCAmode)
453 return 0;
454 break;
455
456 default:
457 gcc_unreachable ();
458 }
459
460 return (GET_MODE (SET_SRC (set)) == set_mode);
461 }
462
463 /* Return true if every SET in INSN that sets the CC register
464 has source and destination with matching CC modes and that
465 CC mode is at least as constrained as REQ_MODE.
466 If REQ_MODE is VOIDmode, always return false. */
467
468 bool
469 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
470 {
471 int i;
472
473 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
474 if (req_mode == VOIDmode)
475 return false;
476
477 if (GET_CODE (PATTERN (insn)) == SET)
478 return s390_match_ccmode_set (PATTERN (insn), req_mode);
479
480 if (GET_CODE (PATTERN (insn)) == PARALLEL)
481 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
482 {
483 rtx set = XVECEXP (PATTERN (insn), 0, i);
484 if (GET_CODE (set) == SET)
485 if (!s390_match_ccmode_set (set, req_mode))
486 return false;
487 }
488
489 return true;
490 }
491
492 /* If a test-under-mask instruction can be used to implement
493 (compare (and ... OP1) OP2), return the CC mode required
494 to do that. Otherwise, return VOIDmode.
495 MIXED is true if the instruction can distinguish between
496 CC1 and CC2 for mixed selected bits (TMxx), it is false
497 if the instruction cannot (TM). */
498
499 enum machine_mode
500 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
501 {
502 int bit0, bit1;
503
504 /* ??? Fixme: should work on CONST_DOUBLE as well. */
505 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
506 return VOIDmode;
507
508 /* Selected bits all zero: CC0.
509 e.g.: int a; if ((a & (16 + 128)) == 0) */
510 if (INTVAL (op2) == 0)
511 return CCTmode;
512
513 /* Selected bits all one: CC3.
514 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
515 if (INTVAL (op2) == INTVAL (op1))
516 return CCT3mode;
517
518 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
519 int a;
520 if ((a & (16 + 128)) == 16) -> CCT1
521 if ((a & (16 + 128)) == 128) -> CCT2 */
522 if (mixed)
523 {
524 bit1 = exact_log2 (INTVAL (op2));
525 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
526 if (bit0 != -1 && bit1 != -1)
527 return bit0 > bit1 ? CCT1mode : CCT2mode;
528 }
529
530 return VOIDmode;
531 }
532
533 /* Given a comparison code OP (EQ, NE, etc.) and the operands
534 OP0 and OP1 of a COMPARE, return the mode to be used for the
535 comparison. */
536
537 enum machine_mode
538 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
539 {
540 switch (code)
541 {
542 case EQ:
543 case NE:
544 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
545 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
546 return CCAPmode;
547 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
548 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
549 return CCAPmode;
550 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
551 || GET_CODE (op1) == NEG)
552 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
553 return CCLmode;
554
555 if (GET_CODE (op0) == AND)
556 {
557 /* Check whether we can potentially do it via TM. */
558 enum machine_mode ccmode;
559 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
560 if (ccmode != VOIDmode)
561 {
562 /* Relax CCTmode to CCZmode to allow fall-back to AND
563 if that turns out to be beneficial. */
564 return ccmode == CCTmode ? CCZmode : ccmode;
565 }
566 }
567
568 if (register_operand (op0, HImode)
569 && GET_CODE (op1) == CONST_INT
570 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
571 return CCT3mode;
572 if (register_operand (op0, QImode)
573 && GET_CODE (op1) == CONST_INT
574 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
575 return CCT3mode;
576
577 return CCZmode;
578
579 case LE:
580 case LT:
581 case GE:
582 case GT:
583 /* The only overflow condition of NEG and ABS happens when
584 -INT_MAX is used as parameter, which stays negative. So
585 we have an overflow from a positive value to a negative.
586 Using CCAP mode the resulting cc can be used for comparisons. */
587 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
588 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
589 return CCAPmode;
590
591 /* If constants are involved in an add instruction it is possible to use
592 the resulting cc for comparisons with zero. Knowing the sign of the
593 constant the overflow behavior gets predictable. e.g.:
594 int a, b; if ((b = a + c) > 0)
595 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
596 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
597 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
598 {
599 if (INTVAL (XEXP((op0), 1)) < 0)
600 return CCANmode;
601 else
602 return CCAPmode;
603 }
604 /* Fall through. */
605 case UNORDERED:
606 case ORDERED:
607 case UNEQ:
608 case UNLE:
609 case UNLT:
610 case UNGE:
611 case UNGT:
612 case LTGT:
613 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
614 && GET_CODE (op1) != CONST_INT)
615 return CCSRmode;
616 return CCSmode;
617
618 case LTU:
619 case GEU:
620 if (GET_CODE (op0) == PLUS
621 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
622 return CCL1mode;
623
624 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
625 && GET_CODE (op1) != CONST_INT)
626 return CCURmode;
627 return CCUmode;
628
629 case LEU:
630 case GTU:
631 if (GET_CODE (op0) == MINUS
632 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
633 return CCL2mode;
634
635 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
636 && GET_CODE (op1) != CONST_INT)
637 return CCURmode;
638 return CCUmode;
639
640 default:
641 gcc_unreachable ();
642 }
643 }
644
645 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
646 that we can implement more efficiently. */
647
648 void
649 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
650 {
651 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
652 if ((*code == EQ || *code == NE)
653 && *op1 == const0_rtx
654 && GET_CODE (*op0) == ZERO_EXTRACT
655 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
656 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
657 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
658 {
659 rtx inner = XEXP (*op0, 0);
660 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
661 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
662 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
663
664 if (len > 0 && len < modesize
665 && pos >= 0 && pos + len <= modesize
666 && modesize <= HOST_BITS_PER_WIDE_INT)
667 {
668 unsigned HOST_WIDE_INT block;
669 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
670 block <<= modesize - pos - len;
671
672 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
673 gen_int_mode (block, GET_MODE (inner)));
674 }
675 }
676
677 /* Narrow AND of memory against immediate to enable TM. */
678 if ((*code == EQ || *code == NE)
679 && *op1 == const0_rtx
680 && GET_CODE (*op0) == AND
681 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
682 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
683 {
684 rtx inner = XEXP (*op0, 0);
685 rtx mask = XEXP (*op0, 1);
686
687 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
688 if (GET_CODE (inner) == SUBREG
689 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
690 && (GET_MODE_SIZE (GET_MODE (inner))
691 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
692 && ((INTVAL (mask)
693 & GET_MODE_MASK (GET_MODE (inner))
694 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
695 == 0))
696 inner = SUBREG_REG (inner);
697
698 /* Do not change volatile MEMs. */
699 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
700 {
701 int part = s390_single_part (XEXP (*op0, 1),
702 GET_MODE (inner), QImode, 0);
703 if (part >= 0)
704 {
705 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
706 inner = adjust_address_nv (inner, QImode, part);
707 *op0 = gen_rtx_AND (QImode, inner, mask);
708 }
709 }
710 }
711
712 /* Narrow comparisons against 0xffff to HImode if possible. */
713 if ((*code == EQ || *code == NE)
714 && GET_CODE (*op1) == CONST_INT
715 && INTVAL (*op1) == 0xffff
716 && SCALAR_INT_MODE_P (GET_MODE (*op0))
717 && (nonzero_bits (*op0, GET_MODE (*op0))
718 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
719 {
720 *op0 = gen_lowpart (HImode, *op0);
721 *op1 = constm1_rtx;
722 }
723
724 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
725 if (GET_CODE (*op0) == UNSPEC
726 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
727 && XVECLEN (*op0, 0) == 1
728 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
729 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
730 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
731 && *op1 == const0_rtx)
732 {
733 enum rtx_code new_code = UNKNOWN;
734 switch (*code)
735 {
736 case EQ: new_code = EQ; break;
737 case NE: new_code = NE; break;
738 case LT: new_code = GTU; break;
739 case GT: new_code = LTU; break;
740 case LE: new_code = GEU; break;
741 case GE: new_code = LEU; break;
742 default: break;
743 }
744
745 if (new_code != UNKNOWN)
746 {
747 *op0 = XVECEXP (*op0, 0, 0);
748 *code = new_code;
749 }
750 }
751
752 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
753 if (GET_CODE (*op0) == UNSPEC
754 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
755 && XVECLEN (*op0, 0) == 1
756 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
757 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
758 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
759 && *op1 == const0_rtx)
760 {
761 enum rtx_code new_code = UNKNOWN;
762 switch (*code)
763 {
764 case EQ: new_code = EQ; break;
765 case NE: new_code = NE; break;
766 default: break;
767 }
768
769 if (new_code != UNKNOWN)
770 {
771 *op0 = XVECEXP (*op0, 0, 0);
772 *code = new_code;
773 }
774 }
775
776 /* Simplify cascaded EQ, NE with const0_rtx. */
777 if ((*code == NE || *code == EQ)
778 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
779 && GET_MODE (*op0) == SImode
780 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
781 && REG_P (XEXP (*op0, 0))
782 && XEXP (*op0, 1) == const0_rtx
783 && *op1 == const0_rtx)
784 {
785 if ((*code == EQ && GET_CODE (*op0) == NE)
786 || (*code == NE && GET_CODE (*op0) == EQ))
787 *code = EQ;
788 else
789 *code = NE;
790 *op0 = XEXP (*op0, 0);
791 }
792
793 /* Prefer register over memory as first operand. */
794 if (MEM_P (*op0) && REG_P (*op1))
795 {
796 rtx tem = *op0; *op0 = *op1; *op1 = tem;
797 *code = swap_condition (*code);
798 }
799 }
800
801 /* Emit a compare instruction suitable to implement the comparison
802 OP0 CODE OP1. Return the correct condition RTL to be placed in
803 the IF_THEN_ELSE of the conditional branch testing the result. */
804
805 rtx
806 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
807 {
808 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
809 rtx cc;
810
811 /* Do not output a redundant compare instruction if a compare_and_swap
812 pattern already computed the result and the machine modes are compatible. */
813 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
814 {
815 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
816 == GET_MODE (op0));
817 cc = op0;
818 }
819 else
820 {
821 cc = gen_rtx_REG (mode, CC_REGNUM);
822 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
823 }
824
825 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
826 }
827
828 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
829 matches CMP.
830 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
831 conditional branch testing the result. */
832
833 static rtx
834 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
835 {
836 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
837 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
838 }
839
840 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
841 unconditional jump, else a conditional jump under condition COND. */
842
843 void
844 s390_emit_jump (rtx target, rtx cond)
845 {
846 rtx insn;
847
848 target = gen_rtx_LABEL_REF (VOIDmode, target);
849 if (cond)
850 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
851
852 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
853 emit_jump_insn (insn);
854 }
855
856 /* Return branch condition mask to implement a branch
857 specified by CODE. Return -1 for invalid comparisons. */
858
859 int
860 s390_branch_condition_mask (rtx code)
861 {
862 const int CC0 = 1 << 3;
863 const int CC1 = 1 << 2;
864 const int CC2 = 1 << 1;
865 const int CC3 = 1 << 0;
866
867 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
868 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
869 gcc_assert (XEXP (code, 1) == const0_rtx);
870
871 switch (GET_MODE (XEXP (code, 0)))
872 {
873 case CCZmode:
874 case CCZ1mode:
875 switch (GET_CODE (code))
876 {
877 case EQ: return CC0;
878 case NE: return CC1 | CC2 | CC3;
879 default: return -1;
880 }
881 break;
882
883 case CCT1mode:
884 switch (GET_CODE (code))
885 {
886 case EQ: return CC1;
887 case NE: return CC0 | CC2 | CC3;
888 default: return -1;
889 }
890 break;
891
892 case CCT2mode:
893 switch (GET_CODE (code))
894 {
895 case EQ: return CC2;
896 case NE: return CC0 | CC1 | CC3;
897 default: return -1;
898 }
899 break;
900
901 case CCT3mode:
902 switch (GET_CODE (code))
903 {
904 case EQ: return CC3;
905 case NE: return CC0 | CC1 | CC2;
906 default: return -1;
907 }
908 break;
909
910 case CCLmode:
911 switch (GET_CODE (code))
912 {
913 case EQ: return CC0 | CC2;
914 case NE: return CC1 | CC3;
915 default: return -1;
916 }
917 break;
918
919 case CCL1mode:
920 switch (GET_CODE (code))
921 {
922 case LTU: return CC2 | CC3; /* carry */
923 case GEU: return CC0 | CC1; /* no carry */
924 default: return -1;
925 }
926 break;
927
928 case CCL2mode:
929 switch (GET_CODE (code))
930 {
931 case GTU: return CC0 | CC1; /* borrow */
932 case LEU: return CC2 | CC3; /* no borrow */
933 default: return -1;
934 }
935 break;
936
937 case CCL3mode:
938 switch (GET_CODE (code))
939 {
940 case EQ: return CC0 | CC2;
941 case NE: return CC1 | CC3;
942 case LTU: return CC1;
943 case GTU: return CC3;
944 case LEU: return CC1 | CC2;
945 case GEU: return CC2 | CC3;
946 default: return -1;
947 }
948
949 case CCUmode:
950 switch (GET_CODE (code))
951 {
952 case EQ: return CC0;
953 case NE: return CC1 | CC2 | CC3;
954 case LTU: return CC1;
955 case GTU: return CC2;
956 case LEU: return CC0 | CC1;
957 case GEU: return CC0 | CC2;
958 default: return -1;
959 }
960 break;
961
962 case CCURmode:
963 switch (GET_CODE (code))
964 {
965 case EQ: return CC0;
966 case NE: return CC2 | CC1 | CC3;
967 case LTU: return CC2;
968 case GTU: return CC1;
969 case LEU: return CC0 | CC2;
970 case GEU: return CC0 | CC1;
971 default: return -1;
972 }
973 break;
974
975 case CCAPmode:
976 switch (GET_CODE (code))
977 {
978 case EQ: return CC0;
979 case NE: return CC1 | CC2 | CC3;
980 case LT: return CC1 | CC3;
981 case GT: return CC2;
982 case LE: return CC0 | CC1 | CC3;
983 case GE: return CC0 | CC2;
984 default: return -1;
985 }
986 break;
987
988 case CCANmode:
989 switch (GET_CODE (code))
990 {
991 case EQ: return CC0;
992 case NE: return CC1 | CC2 | CC3;
993 case LT: return CC1;
994 case GT: return CC2 | CC3;
995 case LE: return CC0 | CC1;
996 case GE: return CC0 | CC2 | CC3;
997 default: return -1;
998 }
999 break;
1000
1001 case CCSmode:
1002 switch (GET_CODE (code))
1003 {
1004 case EQ: return CC0;
1005 case NE: return CC1 | CC2 | CC3;
1006 case LT: return CC1;
1007 case GT: return CC2;
1008 case LE: return CC0 | CC1;
1009 case GE: return CC0 | CC2;
1010 case UNORDERED: return CC3;
1011 case ORDERED: return CC0 | CC1 | CC2;
1012 case UNEQ: return CC0 | CC3;
1013 case UNLT: return CC1 | CC3;
1014 case UNGT: return CC2 | CC3;
1015 case UNLE: return CC0 | CC1 | CC3;
1016 case UNGE: return CC0 | CC2 | CC3;
1017 case LTGT: return CC1 | CC2;
1018 default: return -1;
1019 }
1020 break;
1021
1022 case CCSRmode:
1023 switch (GET_CODE (code))
1024 {
1025 case EQ: return CC0;
1026 case NE: return CC2 | CC1 | CC3;
1027 case LT: return CC2;
1028 case GT: return CC1;
1029 case LE: return CC0 | CC2;
1030 case GE: return CC0 | CC1;
1031 case UNORDERED: return CC3;
1032 case ORDERED: return CC0 | CC2 | CC1;
1033 case UNEQ: return CC0 | CC3;
1034 case UNLT: return CC2 | CC3;
1035 case UNGT: return CC1 | CC3;
1036 case UNLE: return CC0 | CC2 | CC3;
1037 case UNGE: return CC0 | CC1 | CC3;
1038 case LTGT: return CC2 | CC1;
1039 default: return -1;
1040 }
1041 break;
1042
1043 default:
1044 return -1;
1045 }
1046 }
1047
1048
1049 /* Return branch condition mask to implement a compare and branch
1050 specified by CODE. Return -1 for invalid comparisons. */
1051
1052 int
1053 s390_compare_and_branch_condition_mask (rtx code)
1054 {
1055 const int CC0 = 1 << 3;
1056 const int CC1 = 1 << 2;
1057 const int CC2 = 1 << 1;
1058
1059 switch (GET_CODE (code))
1060 {
1061 case EQ:
1062 return CC0;
1063 case NE:
1064 return CC1 | CC2;
1065 case LT:
1066 case LTU:
1067 return CC1;
1068 case GT:
1069 case GTU:
1070 return CC2;
1071 case LE:
1072 case LEU:
1073 return CC0 | CC1;
1074 case GE:
1075 case GEU:
1076 return CC0 | CC2;
1077 default:
1078 gcc_unreachable ();
1079 }
1080 return -1;
1081 }
1082
1083 /* If INV is false, return assembler mnemonic string to implement
1084 a branch specified by CODE. If INV is true, return mnemonic
1085 for the corresponding inverted branch. */
1086
1087 static const char *
1088 s390_branch_condition_mnemonic (rtx code, int inv)
1089 {
1090 int mask;
1091
1092 static const char *const mnemonic[16] =
1093 {
1094 NULL, "o", "h", "nle",
1095 "l", "nhe", "lh", "ne",
1096 "e", "nlh", "he", "nl",
1097 "le", "nh", "no", NULL
1098 };
1099
1100 if (GET_CODE (XEXP (code, 0)) == REG
1101 && REGNO (XEXP (code, 0)) == CC_REGNUM
1102 && XEXP (code, 1) == const0_rtx)
1103 mask = s390_branch_condition_mask (code);
1104 else
1105 mask = s390_compare_and_branch_condition_mask (code);
1106
1107 gcc_assert (mask >= 0);
1108
1109 if (inv)
1110 mask ^= 15;
1111
1112 gcc_assert (mask >= 1 && mask <= 14);
1113
1114 return mnemonic[mask];
1115 }
1116
1117 /* Return the part of op which has a value different from def.
1118 The size of the part is determined by mode.
1119 Use this function only if you already know that op really
1120 contains such a part. */
1121
1122 unsigned HOST_WIDE_INT
1123 s390_extract_part (rtx op, enum machine_mode mode, int def)
1124 {
1125 unsigned HOST_WIDE_INT value = 0;
1126 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1127 int part_bits = GET_MODE_BITSIZE (mode);
1128 unsigned HOST_WIDE_INT part_mask
1129 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1130 int i;
1131
1132 for (i = 0; i < max_parts; i++)
1133 {
1134 if (i == 0)
1135 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1136 else
1137 value >>= part_bits;
1138
1139 if ((value & part_mask) != (def & part_mask))
1140 return value & part_mask;
1141 }
1142
1143 gcc_unreachable ();
1144 }
1145
1146 /* If OP is an integer constant of mode MODE with exactly one
1147 part of mode PART_MODE unequal to DEF, return the number of that
1148 part. Otherwise, return -1. */
1149
1150 int
1151 s390_single_part (rtx op,
1152 enum machine_mode mode,
1153 enum machine_mode part_mode,
1154 int def)
1155 {
1156 unsigned HOST_WIDE_INT value = 0;
1157 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1158 unsigned HOST_WIDE_INT part_mask
1159 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1160 int i, part = -1;
1161
1162 if (GET_CODE (op) != CONST_INT)
1163 return -1;
1164
1165 for (i = 0; i < n_parts; i++)
1166 {
1167 if (i == 0)
1168 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1169 else
1170 value >>= GET_MODE_BITSIZE (part_mode);
1171
1172 if ((value & part_mask) != (def & part_mask))
1173 {
1174 if (part != -1)
1175 return -1;
1176 else
1177 part = i;
1178 }
1179 }
1180 return part == -1 ? -1 : n_parts - 1 - part;
1181 }
1182
1183 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1184 bits and no other bits are set in IN. POS and LENGTH can be used
1185 to obtain the start position and the length of the bitfield.
1186
1187 POS gives the position of the first bit of the bitfield counting
1188 from the lowest order bit starting with zero. In order to use this
1189 value for S/390 instructions this has to be converted to "bits big
1190 endian" style. */
1191
1192 bool
1193 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1194 int *pos, int *length)
1195 {
1196 int tmp_pos = 0;
1197 int tmp_length = 0;
1198 int i;
1199 unsigned HOST_WIDE_INT mask = 1ULL;
1200 bool contiguous = false;
1201
1202 for (i = 0; i < size; mask <<= 1, i++)
1203 {
1204 if (contiguous)
1205 {
1206 if (mask & in)
1207 tmp_length++;
1208 else
1209 break;
1210 }
1211 else
1212 {
1213 if (mask & in)
1214 {
1215 contiguous = true;
1216 tmp_length++;
1217 }
1218 else
1219 tmp_pos++;
1220 }
1221 }
1222
1223 if (!tmp_length)
1224 return false;
1225
1226 /* Calculate a mask for all bits beyond the contiguous bits. */
1227 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1228
1229 if (mask & in)
1230 return false;
1231
1232 if (tmp_length + tmp_pos - 1 > size)
1233 return false;
1234
1235 if (length)
1236 *length = tmp_length;
1237
1238 if (pos)
1239 *pos = tmp_pos;
1240
1241 return true;
1242 }
1243
1244 /* Check whether we can (and want to) split a double-word
1245 move in mode MODE from SRC to DST into two single-word
1246 moves, moving the subword FIRST_SUBWORD first. */
1247
1248 bool
1249 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1250 {
1251 /* Floating point registers cannot be split. */
1252 if (FP_REG_P (src) || FP_REG_P (dst))
1253 return false;
1254
1255 /* We don't need to split if operands are directly accessible. */
1256 if (s_operand (src, mode) || s_operand (dst, mode))
1257 return false;
1258
1259 /* Non-offsettable memory references cannot be split. */
1260 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1261 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1262 return false;
1263
1264 /* Moving the first subword must not clobber a register
1265 needed to move the second subword. */
1266 if (register_operand (dst, mode))
1267 {
1268 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1269 if (reg_overlap_mentioned_p (subreg, src))
1270 return false;
1271 }
1272
1273 return true;
1274 }
1275
1276 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1277 and [MEM2, MEM2 + SIZE] do overlap and false
1278 otherwise. */
1279
1280 bool
1281 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1282 {
1283 rtx addr1, addr2, addr_delta;
1284 HOST_WIDE_INT delta;
1285
1286 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1287 return true;
1288
1289 if (size == 0)
1290 return false;
1291
1292 addr1 = XEXP (mem1, 0);
1293 addr2 = XEXP (mem2, 0);
1294
1295 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1296
1297 /* This overlapping check is used by peepholes merging memory block operations.
1298 Overlapping operations would otherwise be recognized by the S/390 hardware
1299 and would fall back to a slower implementation. Allowing overlapping
1300 operations would lead to slow code but not to wrong code. Therefore we are
1301 somewhat optimistic if we cannot prove that the memory blocks are
1302 overlapping.
1303 That's why we return false here although this may accept operations on
1304 overlapping memory areas. */
1305 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1306 return false;
1307
1308 delta = INTVAL (addr_delta);
1309
1310 if (delta == 0
1311 || (delta > 0 && delta < size)
1312 || (delta < 0 && -delta < size))
1313 return true;
1314
1315 return false;
1316 }
1317
1318 /* Check whether the address of memory reference MEM2 equals exactly
1319 the address of memory reference MEM1 plus DELTA. Return true if
1320 we can prove this to be the case, false otherwise. */
1321
1322 bool
1323 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1324 {
1325 rtx addr1, addr2, addr_delta;
1326
1327 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1328 return false;
1329
1330 addr1 = XEXP (mem1, 0);
1331 addr2 = XEXP (mem2, 0);
1332
1333 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1334 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1335 return false;
1336
1337 return true;
1338 }
1339
1340 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1341
1342 void
1343 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1344 rtx *operands)
1345 {
1346 enum machine_mode wmode = mode;
1347 rtx dst = operands[0];
1348 rtx src1 = operands[1];
1349 rtx src2 = operands[2];
1350 rtx op, clob, tem;
1351
1352 /* If we cannot handle the operation directly, use a temp register. */
1353 if (!s390_logical_operator_ok_p (operands))
1354 dst = gen_reg_rtx (mode);
1355
1356 /* QImode and HImode patterns make sense only if we have a destination
1357 in memory. Otherwise perform the operation in SImode. */
1358 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1359 wmode = SImode;
1360
1361 /* Widen operands if required. */
1362 if (mode != wmode)
1363 {
1364 if (GET_CODE (dst) == SUBREG
1365 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1366 dst = tem;
1367 else if (REG_P (dst))
1368 dst = gen_rtx_SUBREG (wmode, dst, 0);
1369 else
1370 dst = gen_reg_rtx (wmode);
1371
1372 if (GET_CODE (src1) == SUBREG
1373 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1374 src1 = tem;
1375 else if (GET_MODE (src1) != VOIDmode)
1376 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1377
1378 if (GET_CODE (src2) == SUBREG
1379 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1380 src2 = tem;
1381 else if (GET_MODE (src2) != VOIDmode)
1382 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1383 }
1384
1385 /* Emit the instruction. */
1386 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1387 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1388 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1389
1390 /* Fix up the destination if needed. */
1391 if (dst != operands[0])
1392 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1393 }
1394
1395 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1396
1397 bool
1398 s390_logical_operator_ok_p (rtx *operands)
1399 {
1400 /* If the destination operand is in memory, it needs to coincide
1401 with one of the source operands. After reload, it has to be
1402 the first source operand. */
1403 if (GET_CODE (operands[0]) == MEM)
1404 return rtx_equal_p (operands[0], operands[1])
1405 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1406
1407 return true;
1408 }
1409
1410 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1411 operand IMMOP to switch from SS to SI type instructions. */
1412
1413 void
1414 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1415 {
1416 int def = code == AND ? -1 : 0;
1417 HOST_WIDE_INT mask;
1418 int part;
1419
1420 gcc_assert (GET_CODE (*memop) == MEM);
1421 gcc_assert (!MEM_VOLATILE_P (*memop));
1422
1423 mask = s390_extract_part (*immop, QImode, def);
1424 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1425 gcc_assert (part >= 0);
1426
1427 *memop = adjust_address (*memop, QImode, part);
1428 *immop = gen_int_mode (mask, QImode);
1429 }
1430
1431
1432 /* How to allocate a 'struct machine_function'. */
1433
1434 static struct machine_function *
1435 s390_init_machine_status (void)
1436 {
1437 return GGC_CNEW (struct machine_function);
1438 }
1439
1440 /* Change optimizations to be performed, depending on the
1441 optimization level.
1442
1443 LEVEL is the optimization level specified; 2 if `-O2' is
1444 specified, 1 if `-O' is specified, and 0 if neither is specified.
1445
1446 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1447
1448 void
1449 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1450 {
1451 /* ??? There are apparently still problems with -fcaller-saves. */
1452 flag_caller_saves = 0;
1453
1454 /* By default, always emit DWARF-2 unwind info. This allows debugging
1455 without maintaining a stack frame back-chain. */
1456 flag_asynchronous_unwind_tables = 1;
1457
1458 /* Use MVCLE instructions to decrease code size if requested. */
1459 if (size != 0)
1460 target_flags |= MASK_MVCLE;
1461 }
1462
1463 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1464 to the associated processor_type and processor_flags if so. */
1465
1466 static bool
1467 s390_handle_arch_option (const char *arg,
1468 enum processor_type *type,
1469 int *flags)
1470 {
1471 static struct pta
1472 {
1473 const char *const name; /* processor name or nickname. */
1474 const enum processor_type processor;
1475 const int flags; /* From enum processor_flags. */
1476 }
1477 const processor_alias_table[] =
1478 {
1479 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1480 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1481 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1482 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1483 | PF_LONG_DISPLACEMENT},
1484 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1485 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1486 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1487 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1488 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1489 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1490 };
1491 size_t i;
1492
1493 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1494 if (strcmp (arg, processor_alias_table[i].name) == 0)
1495 {
1496 *type = processor_alias_table[i].processor;
1497 *flags = processor_alias_table[i].flags;
1498 return true;
1499 }
1500 return false;
1501 }
1502
1503 /* Implement TARGET_HANDLE_OPTION. */
1504
1505 static bool
1506 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1507 {
1508 switch (code)
1509 {
1510 case OPT_march_:
1511 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1512
1513 case OPT_mstack_guard_:
1514 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1515 return false;
1516 if (exact_log2 (s390_stack_guard) == -1)
1517 error ("stack guard value must be an exact power of 2");
1518 return true;
1519
1520 case OPT_mstack_size_:
1521 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1522 return false;
1523 if (exact_log2 (s390_stack_size) == -1)
1524 error ("stack size must be an exact power of 2");
1525 return true;
1526
1527 case OPT_mtune_:
1528 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1529
1530 case OPT_mwarn_framesize_:
1531 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1532
1533 default:
1534 return true;
1535 }
1536 }
1537
1538 void
1539 override_options (void)
1540 {
1541 /* Set up function hooks. */
1542 init_machine_status = s390_init_machine_status;
1543
1544 /* Architecture mode defaults according to ABI. */
1545 if (!(target_flags_explicit & MASK_ZARCH))
1546 {
1547 if (TARGET_64BIT)
1548 target_flags |= MASK_ZARCH;
1549 else
1550 target_flags &= ~MASK_ZARCH;
1551 }
1552
1553 /* Determine processor architectural level. */
1554 if (!s390_arch_string)
1555 {
1556 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1557 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1558 }
1559
1560 /* Determine processor to tune for. */
1561 if (s390_tune == PROCESSOR_max)
1562 {
1563 s390_tune = s390_arch;
1564 s390_tune_flags = s390_arch_flags;
1565 }
1566
1567 /* Sanity checks. */
1568 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1569 error ("z/Architecture mode not supported on %s", s390_arch_string);
1570 if (TARGET_64BIT && !TARGET_ZARCH)
1571 error ("64-bit ABI not supported in ESA/390 mode");
1572
1573 if (TARGET_HARD_DFP && !TARGET_DFP)
1574 {
1575 if (target_flags_explicit & MASK_HARD_DFP)
1576 {
1577 if (!TARGET_CPU_DFP)
1578 error ("Hardware decimal floating point instructions"
1579 " not available on %s", s390_arch_string);
1580 if (!TARGET_ZARCH)
1581 error ("Hardware decimal floating point instructions"
1582 " not available in ESA/390 mode");
1583 }
1584 else
1585 target_flags &= ~MASK_HARD_DFP;
1586 }
1587
1588 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1589 {
1590 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1591 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1592
1593 target_flags &= ~MASK_HARD_DFP;
1594 }
1595
1596 /* Set processor cost function. */
1597 switch (s390_tune)
1598 {
1599 case PROCESSOR_2084_Z990:
1600 s390_cost = &z990_cost;
1601 break;
1602 case PROCESSOR_2094_Z9_109:
1603 s390_cost = &z9_109_cost;
1604 break;
1605 case PROCESSOR_2097_Z10:
1606 s390_cost = &z10_cost;
1607 break;
1608 default:
1609 s390_cost = &z900_cost;
1610 }
1611
1612 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1613 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1614 "in combination");
1615
1616 if (s390_stack_size)
1617 {
1618 if (s390_stack_guard >= s390_stack_size)
1619 error ("stack size must be greater than the stack guard value");
1620 else if (s390_stack_size > 1 << 16)
1621 error ("stack size must not be greater than 64k");
1622 }
1623 else if (s390_stack_guard)
1624 error ("-mstack-guard implies use of -mstack-size");
1625
1626 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1627 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1628 target_flags |= MASK_LONG_DOUBLE_128;
1629 #endif
1630 }
1631
1632 /* Map for smallest class containing reg regno. */
1633
1634 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1635 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1636 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1637 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1638 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1639 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1640 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1641 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1642 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1643 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1644 ACCESS_REGS, ACCESS_REGS
1645 };
1646
1647 /* Return attribute type of insn. */
1648
1649 static enum attr_type
1650 s390_safe_attr_type (rtx insn)
1651 {
1652 if (recog_memoized (insn) >= 0)
1653 return get_attr_type (insn);
1654 else
1655 return TYPE_NONE;
1656 }
1657
1658 /* Return true if DISP is a valid short displacement. */
1659
1660 static bool
1661 s390_short_displacement (rtx disp)
1662 {
1663 /* No displacement is OK. */
1664 if (!disp)
1665 return true;
1666
1667 /* Integer displacement in range. */
1668 if (GET_CODE (disp) == CONST_INT)
1669 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1670
1671 /* GOT offset is not OK, the GOT can be large. */
1672 if (GET_CODE (disp) == CONST
1673 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1674 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1675 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1676 return false;
1677
1678 /* All other symbolic constants are literal pool references,
1679 which are OK as the literal pool must be small. */
1680 if (GET_CODE (disp) == CONST)
1681 return true;
1682
1683 return false;
1684 }
1685
1686 /* Decompose a RTL expression ADDR for a memory address into
1687 its components, returned in OUT.
1688
1689 Returns false if ADDR is not a valid memory address, true
1690 otherwise. If OUT is NULL, don't return the components,
1691 but check for validity only.
1692
1693 Note: Only addresses in canonical form are recognized.
1694 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1695 canonical form so that they will be recognized. */
1696
1697 static int
1698 s390_decompose_address (rtx addr, struct s390_address *out)
1699 {
1700 HOST_WIDE_INT offset = 0;
1701 rtx base = NULL_RTX;
1702 rtx indx = NULL_RTX;
1703 rtx disp = NULL_RTX;
1704 rtx orig_disp;
1705 bool pointer = false;
1706 bool base_ptr = false;
1707 bool indx_ptr = false;
1708 bool literal_pool = false;
1709
1710 /* We may need to substitute the literal pool base register into the address
1711 below. However, at this point we do not know which register is going to
1712 be used as base, so we substitute the arg pointer register. This is going
1713 to be treated as holding a pointer below -- it shouldn't be used for any
1714 other purpose. */
1715 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1716
1717 /* Decompose address into base + index + displacement. */
1718
1719 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1720 base = addr;
1721
1722 else if (GET_CODE (addr) == PLUS)
1723 {
1724 rtx op0 = XEXP (addr, 0);
1725 rtx op1 = XEXP (addr, 1);
1726 enum rtx_code code0 = GET_CODE (op0);
1727 enum rtx_code code1 = GET_CODE (op1);
1728
1729 if (code0 == REG || code0 == UNSPEC)
1730 {
1731 if (code1 == REG || code1 == UNSPEC)
1732 {
1733 indx = op0; /* index + base */
1734 base = op1;
1735 }
1736
1737 else
1738 {
1739 base = op0; /* base + displacement */
1740 disp = op1;
1741 }
1742 }
1743
1744 else if (code0 == PLUS)
1745 {
1746 indx = XEXP (op0, 0); /* index + base + disp */
1747 base = XEXP (op0, 1);
1748 disp = op1;
1749 }
1750
1751 else
1752 {
1753 return false;
1754 }
1755 }
1756
1757 else
1758 disp = addr; /* displacement */
1759
1760 /* Extract integer part of displacement. */
1761 orig_disp = disp;
1762 if (disp)
1763 {
1764 if (GET_CODE (disp) == CONST_INT)
1765 {
1766 offset = INTVAL (disp);
1767 disp = NULL_RTX;
1768 }
1769 else if (GET_CODE (disp) == CONST
1770 && GET_CODE (XEXP (disp, 0)) == PLUS
1771 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1772 {
1773 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1774 disp = XEXP (XEXP (disp, 0), 0);
1775 }
1776 }
1777
1778 /* Strip off CONST here to avoid special case tests later. */
1779 if (disp && GET_CODE (disp) == CONST)
1780 disp = XEXP (disp, 0);
1781
1782 /* We can convert literal pool addresses to
1783 displacements by basing them off the base register. */
1784 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1785 {
1786 /* Either base or index must be free to hold the base register. */
1787 if (!base)
1788 base = fake_pool_base, literal_pool = true;
1789 else if (!indx)
1790 indx = fake_pool_base, literal_pool = true;
1791 else
1792 return false;
1793
1794 /* Mark up the displacement. */
1795 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1796 UNSPEC_LTREL_OFFSET);
1797 }
1798
1799 /* Validate base register. */
1800 if (base)
1801 {
1802 if (GET_CODE (base) == UNSPEC)
1803 switch (XINT (base, 1))
1804 {
1805 case UNSPEC_LTREF:
1806 if (!disp)
1807 disp = gen_rtx_UNSPEC (Pmode,
1808 gen_rtvec (1, XVECEXP (base, 0, 0)),
1809 UNSPEC_LTREL_OFFSET);
1810 else
1811 return false;
1812
1813 base = XVECEXP (base, 0, 1);
1814 break;
1815
1816 case UNSPEC_LTREL_BASE:
1817 if (XVECLEN (base, 0) == 1)
1818 base = fake_pool_base, literal_pool = true;
1819 else
1820 base = XVECEXP (base, 0, 1);
1821 break;
1822
1823 default:
1824 return false;
1825 }
1826
1827 if (!REG_P (base)
1828 || (GET_MODE (base) != SImode
1829 && GET_MODE (base) != Pmode))
1830 return false;
1831
1832 if (REGNO (base) == STACK_POINTER_REGNUM
1833 || REGNO (base) == FRAME_POINTER_REGNUM
1834 || ((reload_completed || reload_in_progress)
1835 && frame_pointer_needed
1836 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1837 || REGNO (base) == ARG_POINTER_REGNUM
1838 || (flag_pic
1839 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1840 pointer = base_ptr = true;
1841
1842 if ((reload_completed || reload_in_progress)
1843 && base == cfun->machine->base_reg)
1844 pointer = base_ptr = literal_pool = true;
1845 }
1846
1847 /* Validate index register. */
1848 if (indx)
1849 {
1850 if (GET_CODE (indx) == UNSPEC)
1851 switch (XINT (indx, 1))
1852 {
1853 case UNSPEC_LTREF:
1854 if (!disp)
1855 disp = gen_rtx_UNSPEC (Pmode,
1856 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1857 UNSPEC_LTREL_OFFSET);
1858 else
1859 return false;
1860
1861 indx = XVECEXP (indx, 0, 1);
1862 break;
1863
1864 case UNSPEC_LTREL_BASE:
1865 if (XVECLEN (indx, 0) == 1)
1866 indx = fake_pool_base, literal_pool = true;
1867 else
1868 indx = XVECEXP (indx, 0, 1);
1869 break;
1870
1871 default:
1872 return false;
1873 }
1874
1875 if (!REG_P (indx)
1876 || (GET_MODE (indx) != SImode
1877 && GET_MODE (indx) != Pmode))
1878 return false;
1879
1880 if (REGNO (indx) == STACK_POINTER_REGNUM
1881 || REGNO (indx) == FRAME_POINTER_REGNUM
1882 || ((reload_completed || reload_in_progress)
1883 && frame_pointer_needed
1884 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1885 || REGNO (indx) == ARG_POINTER_REGNUM
1886 || (flag_pic
1887 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1888 pointer = indx_ptr = true;
1889
1890 if ((reload_completed || reload_in_progress)
1891 && indx == cfun->machine->base_reg)
1892 pointer = indx_ptr = literal_pool = true;
1893 }
1894
1895 /* Prefer to use pointer as base, not index. */
1896 if (base && indx && !base_ptr
1897 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1898 {
1899 rtx tmp = base;
1900 base = indx;
1901 indx = tmp;
1902 }
1903
1904 /* Validate displacement. */
1905 if (!disp)
1906 {
1907 /* If virtual registers are involved, the displacement will change later
1908 anyway as the virtual registers get eliminated. This could make a
1909 valid displacement invalid, but it is more likely to make an invalid
1910 displacement valid, because we sometimes access the register save area
1911 via negative offsets to one of those registers.
1912 Thus we don't check the displacement for validity here. If after
1913 elimination the displacement turns out to be invalid after all,
1914 this is fixed up by reload in any case. */
1915 if (base != arg_pointer_rtx
1916 && indx != arg_pointer_rtx
1917 && base != return_address_pointer_rtx
1918 && indx != return_address_pointer_rtx
1919 && base != frame_pointer_rtx
1920 && indx != frame_pointer_rtx
1921 && base != virtual_stack_vars_rtx
1922 && indx != virtual_stack_vars_rtx)
1923 if (!DISP_IN_RANGE (offset))
1924 return false;
1925 }
1926 else
1927 {
1928 /* All the special cases are pointers. */
1929 pointer = true;
1930
1931 /* In the small-PIC case, the linker converts @GOT
1932 and @GOTNTPOFF offsets to possible displacements. */
1933 if (GET_CODE (disp) == UNSPEC
1934 && (XINT (disp, 1) == UNSPEC_GOT
1935 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1936 && flag_pic == 1)
1937 {
1938 ;
1939 }
1940
1941 /* Accept pool label offsets. */
1942 else if (GET_CODE (disp) == UNSPEC
1943 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1944 ;
1945
1946 /* Accept literal pool references. */
1947 else if (GET_CODE (disp) == UNSPEC
1948 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1949 {
1950 orig_disp = gen_rtx_CONST (Pmode, disp);
1951 if (offset)
1952 {
1953 /* If we have an offset, make sure it does not
1954 exceed the size of the constant pool entry. */
1955 rtx sym = XVECEXP (disp, 0, 0);
1956 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1957 return false;
1958
1959 orig_disp = plus_constant (orig_disp, offset);
1960 }
1961 }
1962
1963 else
1964 return false;
1965 }
1966
1967 if (!base && !indx)
1968 pointer = true;
1969
1970 if (out)
1971 {
1972 out->base = base;
1973 out->indx = indx;
1974 out->disp = orig_disp;
1975 out->pointer = pointer;
1976 out->literal_pool = literal_pool;
1977 }
1978
1979 return true;
1980 }
1981
1982 /* Decompose a RTL expression OP for a shift count into its components,
1983 and return the base register in BASE and the offset in OFFSET.
1984
1985 Return true if OP is a valid shift count, false if not. */
1986
1987 bool
1988 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1989 {
1990 HOST_WIDE_INT off = 0;
1991
1992 /* We can have an integer constant, an address register,
1993 or a sum of the two. */
1994 if (GET_CODE (op) == CONST_INT)
1995 {
1996 off = INTVAL (op);
1997 op = NULL_RTX;
1998 }
1999 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2000 {
2001 off = INTVAL (XEXP (op, 1));
2002 op = XEXP (op, 0);
2003 }
2004 while (op && GET_CODE (op) == SUBREG)
2005 op = SUBREG_REG (op);
2006
2007 if (op && GET_CODE (op) != REG)
2008 return false;
2009
2010 if (offset)
2011 *offset = off;
2012 if (base)
2013 *base = op;
2014
2015 return true;
2016 }
2017
2018
2019 /* Return true if CODE is a valid address without index. */
2020
2021 bool
2022 s390_legitimate_address_without_index_p (rtx op)
2023 {
2024 struct s390_address addr;
2025
2026 if (!s390_decompose_address (XEXP (op, 0), &addr))
2027 return false;
2028 if (addr.indx)
2029 return false;
2030
2031 return true;
2032 }
2033
2034
2035 /* Evaluates constraint strings described by the regular expression
2036 ([A|B](Q|R|S|T))|U|W and returns 1 if OP is a valid operand for the
2037 constraint given in STR, or 0 else. */
2038
2039 int
2040 s390_mem_constraint (const char *str, rtx op)
2041 {
2042 struct s390_address addr;
2043 char c = str[0];
2044
2045 /* Check for offsettable variants of memory constraints. */
2046 if (c == 'A')
2047 {
2048 /* Only accept non-volatile MEMs. */
2049 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2050 return 0;
2051
2052 if ((reload_completed || reload_in_progress)
2053 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2054 return 0;
2055
2056 c = str[1];
2057 }
2058
2059 /* Check for non-literal-pool variants of memory constraints. */
2060 else if (c == 'B')
2061 {
2062 if (GET_CODE (op) != MEM)
2063 return 0;
2064 if (!s390_decompose_address (XEXP (op, 0), &addr))
2065 return 0;
2066 if (addr.literal_pool)
2067 return 0;
2068
2069 c = str[1];
2070 }
2071
2072 switch (c)
2073 {
2074 case 'Q':
2075 if (GET_CODE (op) != MEM)
2076 return 0;
2077 if (!s390_decompose_address (XEXP (op, 0), &addr))
2078 return 0;
2079 if (addr.indx)
2080 return 0;
2081
2082 if (TARGET_LONG_DISPLACEMENT)
2083 {
2084 if (!s390_short_displacement (addr.disp))
2085 return 0;
2086 }
2087 break;
2088
2089 case 'R':
2090 if (GET_CODE (op) != MEM)
2091 return 0;
2092
2093 if (TARGET_LONG_DISPLACEMENT)
2094 {
2095 if (!s390_decompose_address (XEXP (op, 0), &addr))
2096 return 0;
2097 if (!s390_short_displacement (addr.disp))
2098 return 0;
2099 }
2100 break;
2101
2102 case 'S':
2103 if (!TARGET_LONG_DISPLACEMENT)
2104 return 0;
2105 if (GET_CODE (op) != MEM)
2106 return 0;
2107 if (!s390_decompose_address (XEXP (op, 0), &addr))
2108 return 0;
2109 if (addr.indx)
2110 return 0;
2111 if (s390_short_displacement (addr.disp))
2112 return 0;
2113 break;
2114
2115 case 'T':
2116 if (!TARGET_LONG_DISPLACEMENT)
2117 return 0;
2118 if (GET_CODE (op) != MEM)
2119 return 0;
2120 if (!s390_decompose_address (XEXP (op, 0), &addr))
2121 return 0;
2122 if (s390_short_displacement (addr.disp))
2123 return 0;
2124 break;
2125
2126 case 'U':
2127 if (TARGET_LONG_DISPLACEMENT)
2128 {
2129 if (!s390_decompose_address (op, &addr))
2130 return 0;
2131 if (!s390_short_displacement (addr.disp))
2132 return 0;
2133 }
2134 break;
2135
2136 case 'W':
2137 if (!TARGET_LONG_DISPLACEMENT)
2138 return 0;
2139 if (!s390_decompose_address (op, &addr))
2140 return 0;
2141 if (s390_short_displacement (addr.disp))
2142 return 0;
2143 break;
2144
2145 case 'Y':
2146 /* Simply check for the basic form of a shift count. Reload will
2147 take care of making sure we have a proper base register. */
2148 if (!s390_decompose_shift_count (op, NULL, NULL))
2149 return 0;
2150 break;
2151
2152 default:
2153 return 0;
2154 }
2155
2156 return 1;
2157 }
2158
2159
2160
2161 /* Evaluates constraint strings starting with letter O. Input
2162 parameter C is the second letter following the "O" in the constraint
2163 string. Returns 1 if VALUE meets the respective constraint and 0
2164 otherwise. */
2165
2166 int
2167 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2168 {
2169 if (!TARGET_EXTIMM)
2170 return 0;
2171
2172 switch (c)
2173 {
2174 case 's':
2175 return trunc_int_for_mode (value, SImode) == value;
2176
2177 case 'p':
2178 return value == 0
2179 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2180
2181 case 'n':
2182 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2183
2184 default:
2185 gcc_unreachable ();
2186 }
2187 }
2188
2189
2190 /* Evaluates constraint strings starting with letter N. Parameter STR
2191 contains the letters following letter "N" in the constraint string.
2192 Returns true if VALUE matches the constraint. */
2193
2194 int
2195 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2196 {
2197 enum machine_mode mode, part_mode;
2198 int def;
2199 int part, part_goal;
2200
2201
2202 if (str[0] == 'x')
2203 part_goal = -1;
2204 else
2205 part_goal = str[0] - '0';
2206
2207 switch (str[1])
2208 {
2209 case 'Q':
2210 part_mode = QImode;
2211 break;
2212 case 'H':
2213 part_mode = HImode;
2214 break;
2215 case 'S':
2216 part_mode = SImode;
2217 break;
2218 default:
2219 return 0;
2220 }
2221
2222 switch (str[2])
2223 {
2224 case 'H':
2225 mode = HImode;
2226 break;
2227 case 'S':
2228 mode = SImode;
2229 break;
2230 case 'D':
2231 mode = DImode;
2232 break;
2233 default:
2234 return 0;
2235 }
2236
2237 switch (str[3])
2238 {
2239 case '0':
2240 def = 0;
2241 break;
2242 case 'F':
2243 def = -1;
2244 break;
2245 default:
2246 return 0;
2247 }
2248
2249 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2250 return 0;
2251
2252 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2253 if (part < 0)
2254 return 0;
2255 if (part_goal != -1 && part_goal != part)
2256 return 0;
2257
2258 return 1;
2259 }
2260
2261
2262 /* Returns true if the input parameter VALUE is a float zero. */
2263
2264 int
2265 s390_float_const_zero_p (rtx value)
2266 {
2267 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2268 && value == CONST0_RTX (GET_MODE (value)));
2269 }
2270
2271
2272 /* Compute a (partial) cost for rtx X. Return true if the complete
2273 cost has been computed, and false if subexpressions should be
2274 scanned. In either case, *TOTAL contains the cost result.
2275 CODE contains GET_CODE (x), OUTER_CODE contains the code
2276 of the superexpression of x. */
2277
2278 static bool
2279 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2280 bool speed ATTRIBUTE_UNUSED)
2281 {
2282 switch (code)
2283 {
2284 case CONST:
2285 case CONST_INT:
2286 case LABEL_REF:
2287 case SYMBOL_REF:
2288 case CONST_DOUBLE:
2289 case MEM:
2290 *total = 0;
2291 return true;
2292
2293 case ASHIFT:
2294 case ASHIFTRT:
2295 case LSHIFTRT:
2296 case ROTATE:
2297 case ROTATERT:
2298 case AND:
2299 case IOR:
2300 case XOR:
2301 case NEG:
2302 case NOT:
2303 *total = COSTS_N_INSNS (1);
2304 return false;
2305
2306 case PLUS:
2307 case MINUS:
2308 /* Check for multiply and add. */
2309 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2310 && GET_CODE (XEXP (x, 0)) == MULT
2311 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2312 {
2313 /* This is the multiply and add case. */
2314 if (GET_MODE (x) == DFmode)
2315 *total = s390_cost->madbr;
2316 else
2317 *total = s390_cost->maebr;
2318 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2319 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2320 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2321 return true; /* Do not do an additional recursive descent. */
2322 }
2323 *total = COSTS_N_INSNS (1);
2324 return false;
2325
2326 case MULT:
2327 switch (GET_MODE (x))
2328 {
2329 case SImode:
2330 {
2331 rtx left = XEXP (x, 0);
2332 rtx right = XEXP (x, 1);
2333 if (GET_CODE (right) == CONST_INT
2334 && CONST_OK_FOR_K (INTVAL (right)))
2335 *total = s390_cost->mhi;
2336 else if (GET_CODE (left) == SIGN_EXTEND)
2337 *total = s390_cost->mh;
2338 else
2339 *total = s390_cost->ms; /* msr, ms, msy */
2340 break;
2341 }
2342 case DImode:
2343 {
2344 rtx left = XEXP (x, 0);
2345 rtx right = XEXP (x, 1);
2346 if (TARGET_64BIT)
2347 {
2348 if (GET_CODE (right) == CONST_INT
2349 && CONST_OK_FOR_K (INTVAL (right)))
2350 *total = s390_cost->mghi;
2351 else if (GET_CODE (left) == SIGN_EXTEND)
2352 *total = s390_cost->msgf;
2353 else
2354 *total = s390_cost->msg; /* msgr, msg */
2355 }
2356 else /* TARGET_31BIT */
2357 {
2358 if (GET_CODE (left) == SIGN_EXTEND
2359 && GET_CODE (right) == SIGN_EXTEND)
2360 /* mulsidi case: mr, m */
2361 *total = s390_cost->m;
2362 else if (GET_CODE (left) == ZERO_EXTEND
2363 && GET_CODE (right) == ZERO_EXTEND
2364 && TARGET_CPU_ZARCH)
2365 /* umulsidi case: ml, mlr */
2366 *total = s390_cost->ml;
2367 else
2368 /* Complex calculation is required. */
2369 *total = COSTS_N_INSNS (40);
2370 }
2371 break;
2372 }
2373 case SFmode:
2374 case DFmode:
2375 *total = s390_cost->mult_df;
2376 break;
2377 case TFmode:
2378 *total = s390_cost->mxbr;
2379 break;
2380 default:
2381 return false;
2382 }
2383 return false;
2384
2385 case UDIV:
2386 case UMOD:
2387 if (GET_MODE (x) == TImode) /* 128 bit division */
2388 *total = s390_cost->dlgr;
2389 else if (GET_MODE (x) == DImode)
2390 {
2391 rtx right = XEXP (x, 1);
2392 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2393 *total = s390_cost->dlr;
2394 else /* 64 by 64 bit division */
2395 *total = s390_cost->dlgr;
2396 }
2397 else if (GET_MODE (x) == SImode) /* 32 bit division */
2398 *total = s390_cost->dlr;
2399 return false;
2400
2401 case DIV:
2402 case MOD:
2403 if (GET_MODE (x) == DImode)
2404 {
2405 rtx right = XEXP (x, 1);
2406 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2407 if (TARGET_64BIT)
2408 *total = s390_cost->dsgfr;
2409 else
2410 *total = s390_cost->dr;
2411 else /* 64 by 64 bit division */
2412 *total = s390_cost->dsgr;
2413 }
2414 else if (GET_MODE (x) == SImode) /* 32 bit division */
2415 *total = s390_cost->dlr;
2416 else if (GET_MODE (x) == SFmode)
2417 {
2418 *total = s390_cost->debr;
2419 }
2420 else if (GET_MODE (x) == DFmode)
2421 {
2422 *total = s390_cost->ddbr;
2423 }
2424 else if (GET_MODE (x) == TFmode)
2425 {
2426 *total = s390_cost->dxbr;
2427 }
2428 return false;
2429
2430 case SQRT:
2431 if (GET_MODE (x) == SFmode)
2432 *total = s390_cost->sqebr;
2433 else if (GET_MODE (x) == DFmode)
2434 *total = s390_cost->sqdbr;
2435 else /* TFmode */
2436 *total = s390_cost->sqxbr;
2437 return false;
2438
2439 case SIGN_EXTEND:
2440 case ZERO_EXTEND:
2441 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2442 || outer_code == PLUS || outer_code == MINUS
2443 || outer_code == COMPARE)
2444 *total = 0;
2445 return false;
2446
2447 case COMPARE:
2448 *total = COSTS_N_INSNS (1);
2449 if (GET_CODE (XEXP (x, 0)) == AND
2450 && GET_CODE (XEXP (x, 1)) == CONST_INT
2451 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2452 {
2453 rtx op0 = XEXP (XEXP (x, 0), 0);
2454 rtx op1 = XEXP (XEXP (x, 0), 1);
2455 rtx op2 = XEXP (x, 1);
2456
2457 if (memory_operand (op0, GET_MODE (op0))
2458 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2459 return true;
2460 if (register_operand (op0, GET_MODE (op0))
2461 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2462 return true;
2463 }
2464 return false;
2465
2466 default:
2467 return false;
2468 }
2469 }
2470
2471 /* Return the cost of an address rtx ADDR. */
2472
2473 static int
2474 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2475 {
2476 struct s390_address ad;
2477 if (!s390_decompose_address (addr, &ad))
2478 return 1000;
2479
2480 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2481 }
2482
2483 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2484 otherwise return 0. */
2485
2486 int
2487 tls_symbolic_operand (rtx op)
2488 {
2489 if (GET_CODE (op) != SYMBOL_REF)
2490 return 0;
2491 return SYMBOL_REF_TLS_MODEL (op);
2492 }
2493 \f
2494 /* Split DImode access register reference REG (on 64-bit) into its constituent
2495 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2496 gen_highpart cannot be used as they assume all registers are word-sized,
2497 while our access registers have only half that size. */
2498
2499 void
2500 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2501 {
2502 gcc_assert (TARGET_64BIT);
2503 gcc_assert (ACCESS_REG_P (reg));
2504 gcc_assert (GET_MODE (reg) == DImode);
2505 gcc_assert (!(REGNO (reg) & 1));
2506
2507 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2508 *hi = gen_rtx_REG (SImode, REGNO (reg));
2509 }
2510
2511 /* Return true if OP contains a symbol reference */
2512
2513 bool
2514 symbolic_reference_mentioned_p (rtx op)
2515 {
2516 const char *fmt;
2517 int i;
2518
2519 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2520 return 1;
2521
2522 fmt = GET_RTX_FORMAT (GET_CODE (op));
2523 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2524 {
2525 if (fmt[i] == 'E')
2526 {
2527 int j;
2528
2529 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2530 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2531 return 1;
2532 }
2533
2534 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2535 return 1;
2536 }
2537
2538 return 0;
2539 }
2540
2541 /* Return true if OP contains a reference to a thread-local symbol. */
2542
2543 bool
2544 tls_symbolic_reference_mentioned_p (rtx op)
2545 {
2546 const char *fmt;
2547 int i;
2548
2549 if (GET_CODE (op) == SYMBOL_REF)
2550 return tls_symbolic_operand (op);
2551
2552 fmt = GET_RTX_FORMAT (GET_CODE (op));
2553 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2554 {
2555 if (fmt[i] == 'E')
2556 {
2557 int j;
2558
2559 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2560 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2561 return true;
2562 }
2563
2564 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2565 return true;
2566 }
2567
2568 return false;
2569 }
2570
2571
2572 /* Return true if OP is a legitimate general operand when
2573 generating PIC code. It is given that flag_pic is on
2574 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2575
2576 int
2577 legitimate_pic_operand_p (rtx op)
2578 {
2579 /* Accept all non-symbolic constants. */
2580 if (!SYMBOLIC_CONST (op))
2581 return 1;
2582
2583 /* Reject everything else; must be handled
2584 via emit_symbolic_move. */
2585 return 0;
2586 }
2587
2588 /* Returns true if the constant value OP is a legitimate general operand.
2589 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2590
2591 int
2592 legitimate_constant_p (rtx op)
2593 {
2594 /* Accept all non-symbolic constants. */
2595 if (!SYMBOLIC_CONST (op))
2596 return 1;
2597
2598 /* Accept immediate LARL operands. */
2599 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2600 return 1;
2601
2602 /* Thread-local symbols are never legal constants. This is
2603 so that emit_call knows that computing such addresses
2604 might require a function call. */
2605 if (TLS_SYMBOLIC_CONST (op))
2606 return 0;
2607
2608 /* In the PIC case, symbolic constants must *not* be
2609 forced into the literal pool. We accept them here,
2610 so that they will be handled by emit_symbolic_move. */
2611 if (flag_pic)
2612 return 1;
2613
2614 /* All remaining non-PIC symbolic constants are
2615 forced into the literal pool. */
2616 return 0;
2617 }
2618
2619 /* Determine if it's legal to put X into the constant pool. This
2620 is not possible if X contains the address of a symbol that is
2621 not constant (TLS) or not known at final link time (PIC). */
2622
2623 static bool
2624 s390_cannot_force_const_mem (rtx x)
2625 {
2626 switch (GET_CODE (x))
2627 {
2628 case CONST_INT:
2629 case CONST_DOUBLE:
2630 /* Accept all non-symbolic constants. */
2631 return false;
2632
2633 case LABEL_REF:
2634 /* Labels are OK iff we are non-PIC. */
2635 return flag_pic != 0;
2636
2637 case SYMBOL_REF:
2638 /* 'Naked' TLS symbol references are never OK,
2639 non-TLS symbols are OK iff we are non-PIC. */
2640 if (tls_symbolic_operand (x))
2641 return true;
2642 else
2643 return flag_pic != 0;
2644
2645 case CONST:
2646 return s390_cannot_force_const_mem (XEXP (x, 0));
2647 case PLUS:
2648 case MINUS:
2649 return s390_cannot_force_const_mem (XEXP (x, 0))
2650 || s390_cannot_force_const_mem (XEXP (x, 1));
2651
2652 case UNSPEC:
2653 switch (XINT (x, 1))
2654 {
2655 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2656 case UNSPEC_LTREL_OFFSET:
2657 case UNSPEC_GOT:
2658 case UNSPEC_GOTOFF:
2659 case UNSPEC_PLTOFF:
2660 case UNSPEC_TLSGD:
2661 case UNSPEC_TLSLDM:
2662 case UNSPEC_NTPOFF:
2663 case UNSPEC_DTPOFF:
2664 case UNSPEC_GOTNTPOFF:
2665 case UNSPEC_INDNTPOFF:
2666 return false;
2667
2668 /* If the literal pool shares the code section, be put
2669 execute template placeholders into the pool as well. */
2670 case UNSPEC_INSN:
2671 return TARGET_CPU_ZARCH;
2672
2673 default:
2674 return true;
2675 }
2676 break;
2677
2678 default:
2679 gcc_unreachable ();
2680 }
2681 }
2682
2683 /* Returns true if the constant value OP is a legitimate general
2684 operand during and after reload. The difference to
2685 legitimate_constant_p is that this function will not accept
2686 a constant that would need to be forced to the literal pool
2687 before it can be used as operand. */
2688
2689 bool
2690 legitimate_reload_constant_p (rtx op)
2691 {
2692 /* Accept la(y) operands. */
2693 if (GET_CODE (op) == CONST_INT
2694 && DISP_IN_RANGE (INTVAL (op)))
2695 return true;
2696
2697 /* Accept l(g)hi/l(g)fi operands. */
2698 if (GET_CODE (op) == CONST_INT
2699 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2700 return true;
2701
2702 /* Accept lliXX operands. */
2703 if (TARGET_ZARCH
2704 && GET_CODE (op) == CONST_INT
2705 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2706 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2707 return true;
2708
2709 if (TARGET_EXTIMM
2710 && GET_CODE (op) == CONST_INT
2711 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2712 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2713 return true;
2714
2715 /* Accept larl operands. */
2716 if (TARGET_CPU_ZARCH
2717 && larl_operand (op, VOIDmode))
2718 return true;
2719
2720 /* Accept lzXX operands. */
2721 if (GET_CODE (op) == CONST_DOUBLE
2722 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2723 return true;
2724
2725 /* Accept double-word operands that can be split. */
2726 if (GET_CODE (op) == CONST_INT
2727 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2728 {
2729 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2730 rtx hi = operand_subword (op, 0, 0, dword_mode);
2731 rtx lo = operand_subword (op, 1, 0, dword_mode);
2732 return legitimate_reload_constant_p (hi)
2733 && legitimate_reload_constant_p (lo);
2734 }
2735
2736 /* Everything else cannot be handled without reload. */
2737 return false;
2738 }
2739
2740 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2741 return the class of reg to actually use. */
2742
2743 enum reg_class
2744 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2745 {
2746 switch (GET_CODE (op))
2747 {
2748 /* Constants we cannot reload must be forced into the
2749 literal pool. */
2750
2751 case CONST_DOUBLE:
2752 case CONST_INT:
2753 if (legitimate_reload_constant_p (op))
2754 return rclass;
2755 else
2756 return NO_REGS;
2757
2758 /* If a symbolic constant or a PLUS is reloaded,
2759 it is most likely being used as an address, so
2760 prefer ADDR_REGS. If 'class' is not a superset
2761 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2762 case PLUS:
2763 case LABEL_REF:
2764 case SYMBOL_REF:
2765 case CONST:
2766 if (reg_class_subset_p (ADDR_REGS, rclass))
2767 return ADDR_REGS;
2768 else
2769 return NO_REGS;
2770
2771 default:
2772 break;
2773 }
2774
2775 return rclass;
2776 }
2777
2778 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2779 and return these parts in SYMREF and ADDEND. You can pass NULL in
2780 SYMREF and/or ADDEND if you are not interested in these values. */
2781
2782 static bool
2783 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2784 {
2785 HOST_WIDE_INT tmpaddend = 0;
2786
2787 if (GET_CODE (addr) == CONST)
2788 addr = XEXP (addr, 0);
2789
2790 if (GET_CODE (addr) == PLUS)
2791 {
2792 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2793 && CONST_INT_P (XEXP (addr, 1)))
2794 {
2795 tmpaddend = INTVAL (XEXP (addr, 1));
2796 addr = XEXP (addr, 0);
2797 }
2798 else
2799 return false;
2800 }
2801 else
2802 if (GET_CODE (addr) != SYMBOL_REF)
2803 return false;
2804
2805 if (symref)
2806 *symref = addr;
2807 if (addend)
2808 *addend = tmpaddend;
2809
2810 return true;
2811 }
2812
2813 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2814 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2815 aligned. */
2816
2817 bool
2818 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2819 {
2820 HOST_WIDE_INT addend;
2821 rtx symref;
2822
2823 if (!s390_symref_operand_p (addr, &symref, &addend))
2824 return false;
2825
2826 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2827 && !(addend & (alignment - 1)));
2828 }
2829
2830 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2831 operand SCRATCH is used to reload the even part of the address and
2832 adding one. */
2833
2834 void
2835 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2836 {
2837 HOST_WIDE_INT addend;
2838 rtx symref;
2839
2840 if (!s390_symref_operand_p (addr, &symref, &addend))
2841 gcc_unreachable ();
2842
2843 if (!(addend & 1))
2844 /* Easy case. The addend is even so larl will do fine. */
2845 emit_move_insn (reg, addr);
2846 else
2847 {
2848 /* We can leave the scratch register untouched if the target
2849 register is a valid base register. */
2850 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2851 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2852 scratch = reg;
2853
2854 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2855 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2856
2857 if (addend != 1)
2858 emit_move_insn (scratch,
2859 gen_rtx_CONST (Pmode,
2860 gen_rtx_PLUS (Pmode, symref,
2861 GEN_INT (addend - 1))));
2862 else
2863 emit_move_insn (scratch, symref);
2864
2865 /* Increment the address using la in order to avoid clobbering cc. */
2866 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2867 }
2868 }
2869
2870 /* Generate what is necessary to move between REG and MEM using
2871 SCRATCH. The direction is given by TOMEM. */
2872
2873 void
2874 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2875 {
2876 /* Reload might have pulled a constant out of the literal pool.
2877 Force it back in. */
2878 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2879 || GET_CODE (mem) == CONST)
2880 mem = force_const_mem (GET_MODE (reg), mem);
2881
2882 gcc_assert (MEM_P (mem));
2883
2884 /* For a load from memory we can leave the scratch register
2885 untouched if the target register is a valid base register. */
2886 if (!tomem
2887 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2888 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2889 && GET_MODE (reg) == GET_MODE (scratch))
2890 scratch = reg;
2891
2892 /* Load address into scratch register. Since we can't have a
2893 secondary reload for a secondary reload we have to cover the case
2894 where larl would need a secondary reload here as well. */
2895 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2896
2897 /* Now we can use a standard load/store to do the move. */
2898 if (tomem)
2899 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2900 else
2901 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2902 }
2903
2904 /* Inform reload about cases where moving X with a mode MODE to a register in
2905 RCLASS requires an extra scratch or immediate register. Return the class
2906 needed for the immediate register. */
2907
2908 static enum reg_class
2909 s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2910 enum machine_mode mode, secondary_reload_info *sri)
2911 {
2912 /* Intermediate register needed. */
2913 if (reg_classes_intersect_p (CC_REGS, rclass))
2914 return GENERAL_REGS;
2915
2916 if (TARGET_Z10)
2917 {
2918 /* On z10 several optimizer steps may generate larl operands with
2919 an odd addend. */
2920 if (in_p
2921 && s390_symref_operand_p (x, NULL, NULL)
2922 && mode == Pmode
2923 && !s390_check_symref_alignment (x, 2))
2924 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2925 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2926
2927 /* On z10 we need a scratch register when moving QI, TI or floating
2928 point mode values from or to a memory location with a SYMBOL_REF
2929 or if the symref addend of a SI or DI move is not aligned to the
2930 width of the access. */
2931 if (MEM_P (x)
2932 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2933 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2934 || (!TARGET_64BIT && mode == DImode)
2935 || ((mode == HImode || mode == SImode || mode == DImode)
2936 && (!s390_check_symref_alignment (XEXP (x, 0),
2937 GET_MODE_SIZE (mode))))))
2938 {
2939 #define __SECONDARY_RELOAD_CASE(M,m) \
2940 case M##mode: \
2941 if (TARGET_64BIT) \
2942 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2943 CODE_FOR_reload##m##di_tomem_z10; \
2944 else \
2945 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
2946 CODE_FOR_reload##m##si_tomem_z10; \
2947 break;
2948
2949 switch (GET_MODE (x))
2950 {
2951 __SECONDARY_RELOAD_CASE (QI, qi);
2952 __SECONDARY_RELOAD_CASE (HI, hi);
2953 __SECONDARY_RELOAD_CASE (SI, si);
2954 __SECONDARY_RELOAD_CASE (DI, di);
2955 __SECONDARY_RELOAD_CASE (TI, ti);
2956 __SECONDARY_RELOAD_CASE (SF, sf);
2957 __SECONDARY_RELOAD_CASE (DF, df);
2958 __SECONDARY_RELOAD_CASE (TF, tf);
2959 __SECONDARY_RELOAD_CASE (SD, sd);
2960 __SECONDARY_RELOAD_CASE (DD, dd);
2961 __SECONDARY_RELOAD_CASE (TD, td);
2962
2963 default:
2964 gcc_unreachable ();
2965 }
2966 #undef __SECONDARY_RELOAD_CASE
2967 }
2968 }
2969
2970 /* We need a scratch register when loading a PLUS expression which
2971 is not a legitimate operand of the LOAD ADDRESS instruction. */
2972 if (in_p && s390_plus_operand (x, mode))
2973 sri->icode = (TARGET_64BIT ?
2974 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
2975
2976 /* Performing a multiword move from or to memory we have to make sure the
2977 second chunk in memory is addressable without causing a displacement
2978 overflow. If that would be the case we calculate the address in
2979 a scratch register. */
2980 if (MEM_P (x)
2981 && GET_CODE (XEXP (x, 0)) == PLUS
2982 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2983 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
2984 + GET_MODE_SIZE (mode) - 1))
2985 {
2986 /* For GENERAL_REGS a displacement overflow is no problem if occurring
2987 in a s_operand address since we may fallback to lm/stm. So we only
2988 have to care about overflows in the b+i+d case. */
2989 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
2990 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
2991 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
2992 /* For FP_REGS no lm/stm is available so this check is triggered
2993 for displacement overflows in b+i+d and b+d like addresses. */
2994 || (reg_classes_intersect_p (FP_REGS, rclass)
2995 && s390_class_max_nregs (FP_REGS, mode) > 1))
2996 {
2997 if (in_p)
2998 sri->icode = (TARGET_64BIT ?
2999 CODE_FOR_reloaddi_nonoffmem_in :
3000 CODE_FOR_reloadsi_nonoffmem_in);
3001 else
3002 sri->icode = (TARGET_64BIT ?
3003 CODE_FOR_reloaddi_nonoffmem_out :
3004 CODE_FOR_reloadsi_nonoffmem_out);
3005 }
3006 }
3007
3008 /* A scratch address register is needed when a symbolic constant is
3009 copied to r0 compiling with -fPIC. In other cases the target
3010 register might be used as temporary (see legitimize_pic_address). */
3011 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3012 sri->icode = (TARGET_64BIT ?
3013 CODE_FOR_reloaddi_PIC_addr :
3014 CODE_FOR_reloadsi_PIC_addr);
3015
3016 /* Either scratch or no register needed. */
3017 return NO_REGS;
3018 }
3019
3020 /* Generate code to load SRC, which is PLUS that is not a
3021 legitimate operand for the LA instruction, into TARGET.
3022 SCRATCH may be used as scratch register. */
3023
3024 void
3025 s390_expand_plus_operand (rtx target, rtx src,
3026 rtx scratch)
3027 {
3028 rtx sum1, sum2;
3029 struct s390_address ad;
3030
3031 /* src must be a PLUS; get its two operands. */
3032 gcc_assert (GET_CODE (src) == PLUS);
3033 gcc_assert (GET_MODE (src) == Pmode);
3034
3035 /* Check if any of the two operands is already scheduled
3036 for replacement by reload. This can happen e.g. when
3037 float registers occur in an address. */
3038 sum1 = find_replacement (&XEXP (src, 0));
3039 sum2 = find_replacement (&XEXP (src, 1));
3040 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3041
3042 /* If the address is already strictly valid, there's nothing to do. */
3043 if (!s390_decompose_address (src, &ad)
3044 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3045 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3046 {
3047 /* Otherwise, one of the operands cannot be an address register;
3048 we reload its value into the scratch register. */
3049 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3050 {
3051 emit_move_insn (scratch, sum1);
3052 sum1 = scratch;
3053 }
3054 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3055 {
3056 emit_move_insn (scratch, sum2);
3057 sum2 = scratch;
3058 }
3059
3060 /* According to the way these invalid addresses are generated
3061 in reload.c, it should never happen (at least on s390) that
3062 *neither* of the PLUS components, after find_replacements
3063 was applied, is an address register. */
3064 if (sum1 == scratch && sum2 == scratch)
3065 {
3066 debug_rtx (src);
3067 gcc_unreachable ();
3068 }
3069
3070 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3071 }
3072
3073 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3074 is only ever performed on addresses, so we can mark the
3075 sum as legitimate for LA in any case. */
3076 s390_load_address (target, src);
3077 }
3078
3079
3080 /* Return true if ADDR is a valid memory address.
3081 STRICT specifies whether strict register checking applies. */
3082
3083 static bool
3084 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3085 {
3086 struct s390_address ad;
3087
3088 if (TARGET_Z10
3089 && larl_operand (addr, VOIDmode)
3090 && (mode == VOIDmode
3091 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3092 return true;
3093
3094 if (!s390_decompose_address (addr, &ad))
3095 return false;
3096
3097 if (strict)
3098 {
3099 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3100 return false;
3101
3102 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3103 return false;
3104 }
3105 else
3106 {
3107 if (ad.base
3108 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3109 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3110 return false;
3111
3112 if (ad.indx
3113 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3114 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3115 return false;
3116 }
3117 return true;
3118 }
3119
3120 /* Return true if OP is a valid operand for the LA instruction.
3121 In 31-bit, we need to prove that the result is used as an
3122 address, as LA performs only a 31-bit addition. */
3123
3124 bool
3125 legitimate_la_operand_p (rtx op)
3126 {
3127 struct s390_address addr;
3128 if (!s390_decompose_address (op, &addr))
3129 return false;
3130
3131 return (TARGET_64BIT || addr.pointer);
3132 }
3133
3134 /* Return true if it is valid *and* preferable to use LA to
3135 compute the sum of OP1 and OP2. */
3136
3137 bool
3138 preferred_la_operand_p (rtx op1, rtx op2)
3139 {
3140 struct s390_address addr;
3141
3142 if (op2 != const0_rtx)
3143 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3144
3145 if (!s390_decompose_address (op1, &addr))
3146 return false;
3147 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3148 return false;
3149 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3150 return false;
3151
3152 if (!TARGET_64BIT && !addr.pointer)
3153 return false;
3154
3155 if (addr.pointer)
3156 return true;
3157
3158 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3159 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3160 return true;
3161
3162 return false;
3163 }
3164
3165 /* Emit a forced load-address operation to load SRC into DST.
3166 This will use the LOAD ADDRESS instruction even in situations
3167 where legitimate_la_operand_p (SRC) returns false. */
3168
3169 void
3170 s390_load_address (rtx dst, rtx src)
3171 {
3172 if (TARGET_64BIT)
3173 emit_move_insn (dst, src);
3174 else
3175 emit_insn (gen_force_la_31 (dst, src));
3176 }
3177
3178 /* Return a legitimate reference for ORIG (an address) using the
3179 register REG. If REG is 0, a new pseudo is generated.
3180
3181 There are two types of references that must be handled:
3182
3183 1. Global data references must load the address from the GOT, via
3184 the PIC reg. An insn is emitted to do this load, and the reg is
3185 returned.
3186
3187 2. Static data references, constant pool addresses, and code labels
3188 compute the address as an offset from the GOT, whose base is in
3189 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3190 differentiate them from global data objects. The returned
3191 address is the PIC reg + an unspec constant.
3192
3193 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3194 reg also appears in the address. */
3195
3196 rtx
3197 legitimize_pic_address (rtx orig, rtx reg)
3198 {
3199 rtx addr = orig;
3200 rtx new_rtx = orig;
3201 rtx base;
3202
3203 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3204
3205 if (GET_CODE (addr) == LABEL_REF
3206 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3207 {
3208 /* This is a local symbol. */
3209 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3210 {
3211 /* Access local symbols PC-relative via LARL.
3212 This is the same as in the non-PIC case, so it is
3213 handled automatically ... */
3214 }
3215 else
3216 {
3217 /* Access local symbols relative to the GOT. */
3218
3219 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3220
3221 if (reload_in_progress || reload_completed)
3222 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3223
3224 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3225 addr = gen_rtx_CONST (Pmode, addr);
3226 addr = force_const_mem (Pmode, addr);
3227 emit_move_insn (temp, addr);
3228
3229 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3230 if (reg != 0)
3231 {
3232 s390_load_address (reg, new_rtx);
3233 new_rtx = reg;
3234 }
3235 }
3236 }
3237 else if (GET_CODE (addr) == SYMBOL_REF)
3238 {
3239 if (reg == 0)
3240 reg = gen_reg_rtx (Pmode);
3241
3242 if (flag_pic == 1)
3243 {
3244 /* Assume GOT offset < 4k. This is handled the same way
3245 in both 31- and 64-bit code (@GOT). */
3246
3247 if (reload_in_progress || reload_completed)
3248 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3249
3250 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3251 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3252 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3253 new_rtx = gen_const_mem (Pmode, new_rtx);
3254 emit_move_insn (reg, new_rtx);
3255 new_rtx = reg;
3256 }
3257 else if (TARGET_CPU_ZARCH)
3258 {
3259 /* If the GOT offset might be >= 4k, we determine the position
3260 of the GOT entry via a PC-relative LARL (@GOTENT). */
3261
3262 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3263
3264 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3265 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3266
3267 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3268 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3269 emit_move_insn (temp, new_rtx);
3270
3271 new_rtx = gen_const_mem (Pmode, temp);
3272 emit_move_insn (reg, new_rtx);
3273 new_rtx = reg;
3274 }
3275 else
3276 {
3277 /* If the GOT offset might be >= 4k, we have to load it
3278 from the literal pool (@GOT). */
3279
3280 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3281
3282 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3283 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3284
3285 if (reload_in_progress || reload_completed)
3286 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3287
3288 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3289 addr = gen_rtx_CONST (Pmode, addr);
3290 addr = force_const_mem (Pmode, addr);
3291 emit_move_insn (temp, addr);
3292
3293 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3294 new_rtx = gen_const_mem (Pmode, new_rtx);
3295 emit_move_insn (reg, new_rtx);
3296 new_rtx = reg;
3297 }
3298 }
3299 else
3300 {
3301 if (GET_CODE (addr) == CONST)
3302 {
3303 addr = XEXP (addr, 0);
3304 if (GET_CODE (addr) == UNSPEC)
3305 {
3306 gcc_assert (XVECLEN (addr, 0) == 1);
3307 switch (XINT (addr, 1))
3308 {
3309 /* If someone moved a GOT-relative UNSPEC
3310 out of the literal pool, force them back in. */
3311 case UNSPEC_GOTOFF:
3312 case UNSPEC_PLTOFF:
3313 new_rtx = force_const_mem (Pmode, orig);
3314 break;
3315
3316 /* @GOT is OK as is if small. */
3317 case UNSPEC_GOT:
3318 if (flag_pic == 2)
3319 new_rtx = force_const_mem (Pmode, orig);
3320 break;
3321
3322 /* @GOTENT is OK as is. */
3323 case UNSPEC_GOTENT:
3324 break;
3325
3326 /* @PLT is OK as is on 64-bit, must be converted to
3327 GOT-relative @PLTOFF on 31-bit. */
3328 case UNSPEC_PLT:
3329 if (!TARGET_CPU_ZARCH)
3330 {
3331 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3332
3333 if (reload_in_progress || reload_completed)
3334 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3335
3336 addr = XVECEXP (addr, 0, 0);
3337 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3338 UNSPEC_PLTOFF);
3339 addr = gen_rtx_CONST (Pmode, addr);
3340 addr = force_const_mem (Pmode, addr);
3341 emit_move_insn (temp, addr);
3342
3343 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3344 if (reg != 0)
3345 {
3346 s390_load_address (reg, new_rtx);
3347 new_rtx = reg;
3348 }
3349 }
3350 break;
3351
3352 /* Everything else cannot happen. */
3353 default:
3354 gcc_unreachable ();
3355 }
3356 }
3357 else
3358 gcc_assert (GET_CODE (addr) == PLUS);
3359 }
3360 if (GET_CODE (addr) == PLUS)
3361 {
3362 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3363
3364 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3365 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3366
3367 /* Check first to see if this is a constant offset
3368 from a local symbol reference. */
3369 if ((GET_CODE (op0) == LABEL_REF
3370 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3371 && GET_CODE (op1) == CONST_INT)
3372 {
3373 if (TARGET_CPU_ZARCH
3374 && larl_operand (op0, VOIDmode)
3375 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3376 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3377 {
3378 if (INTVAL (op1) & 1)
3379 {
3380 /* LARL can't handle odd offsets, so emit a
3381 pair of LARL and LA. */
3382 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3383
3384 if (!DISP_IN_RANGE (INTVAL (op1)))
3385 {
3386 HOST_WIDE_INT even = INTVAL (op1) - 1;
3387 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3388 op0 = gen_rtx_CONST (Pmode, op0);
3389 op1 = const1_rtx;
3390 }
3391
3392 emit_move_insn (temp, op0);
3393 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3394
3395 if (reg != 0)
3396 {
3397 s390_load_address (reg, new_rtx);
3398 new_rtx = reg;
3399 }
3400 }
3401 else
3402 {
3403 /* If the offset is even, we can just use LARL.
3404 This will happen automatically. */
3405 }
3406 }
3407 else
3408 {
3409 /* Access local symbols relative to the GOT. */
3410
3411 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3412
3413 if (reload_in_progress || reload_completed)
3414 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3415
3416 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3417 UNSPEC_GOTOFF);
3418 addr = gen_rtx_PLUS (Pmode, addr, op1);
3419 addr = gen_rtx_CONST (Pmode, addr);
3420 addr = force_const_mem (Pmode, addr);
3421 emit_move_insn (temp, addr);
3422
3423 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3424 if (reg != 0)
3425 {
3426 s390_load_address (reg, new_rtx);
3427 new_rtx = reg;
3428 }
3429 }
3430 }
3431
3432 /* Now, check whether it is a GOT relative symbol plus offset
3433 that was pulled out of the literal pool. Force it back in. */
3434
3435 else if (GET_CODE (op0) == UNSPEC
3436 && GET_CODE (op1) == CONST_INT
3437 && XINT (op0, 1) == UNSPEC_GOTOFF)
3438 {
3439 gcc_assert (XVECLEN (op0, 0) == 1);
3440
3441 new_rtx = force_const_mem (Pmode, orig);
3442 }
3443
3444 /* Otherwise, compute the sum. */
3445 else
3446 {
3447 base = legitimize_pic_address (XEXP (addr, 0), reg);
3448 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3449 base == reg ? NULL_RTX : reg);
3450 if (GET_CODE (new_rtx) == CONST_INT)
3451 new_rtx = plus_constant (base, INTVAL (new_rtx));
3452 else
3453 {
3454 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3455 {
3456 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3457 new_rtx = XEXP (new_rtx, 1);
3458 }
3459 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3460 }
3461
3462 if (GET_CODE (new_rtx) == CONST)
3463 new_rtx = XEXP (new_rtx, 0);
3464 new_rtx = force_operand (new_rtx, 0);
3465 }
3466 }
3467 }
3468 return new_rtx;
3469 }
3470
3471 /* Load the thread pointer into a register. */
3472
3473 rtx
3474 s390_get_thread_pointer (void)
3475 {
3476 rtx tp = gen_reg_rtx (Pmode);
3477
3478 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3479 mark_reg_pointer (tp, BITS_PER_WORD);
3480
3481 return tp;
3482 }
3483
3484 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3485 in s390_tls_symbol which always refers to __tls_get_offset.
3486 The returned offset is written to RESULT_REG and an USE rtx is
3487 generated for TLS_CALL. */
3488
3489 static GTY(()) rtx s390_tls_symbol;
3490
3491 static void
3492 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3493 {
3494 rtx insn;
3495
3496 gcc_assert (flag_pic);
3497
3498 if (!s390_tls_symbol)
3499 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3500
3501 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3502 gen_rtx_REG (Pmode, RETURN_REGNUM));
3503
3504 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3505 RTL_CONST_CALL_P (insn) = 1;
3506 }
3507
3508 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3509 this (thread-local) address. REG may be used as temporary. */
3510
3511 static rtx
3512 legitimize_tls_address (rtx addr, rtx reg)
3513 {
3514 rtx new_rtx, tls_call, temp, base, r2, insn;
3515
3516 if (GET_CODE (addr) == SYMBOL_REF)
3517 switch (tls_symbolic_operand (addr))
3518 {
3519 case TLS_MODEL_GLOBAL_DYNAMIC:
3520 start_sequence ();
3521 r2 = gen_rtx_REG (Pmode, 2);
3522 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3523 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3524 new_rtx = force_const_mem (Pmode, new_rtx);
3525 emit_move_insn (r2, new_rtx);
3526 s390_emit_tls_call_insn (r2, tls_call);
3527 insn = get_insns ();
3528 end_sequence ();
3529
3530 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3531 temp = gen_reg_rtx (Pmode);
3532 emit_libcall_block (insn, temp, r2, new_rtx);
3533
3534 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3535 if (reg != 0)
3536 {
3537 s390_load_address (reg, new_rtx);
3538 new_rtx = reg;
3539 }
3540 break;
3541
3542 case TLS_MODEL_LOCAL_DYNAMIC:
3543 start_sequence ();
3544 r2 = gen_rtx_REG (Pmode, 2);
3545 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3546 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3547 new_rtx = force_const_mem (Pmode, new_rtx);
3548 emit_move_insn (r2, new_rtx);
3549 s390_emit_tls_call_insn (r2, tls_call);
3550 insn = get_insns ();
3551 end_sequence ();
3552
3553 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3554 temp = gen_reg_rtx (Pmode);
3555 emit_libcall_block (insn, temp, r2, new_rtx);
3556
3557 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3558 base = gen_reg_rtx (Pmode);
3559 s390_load_address (base, new_rtx);
3560
3561 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3562 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3563 new_rtx = force_const_mem (Pmode, new_rtx);
3564 temp = gen_reg_rtx (Pmode);
3565 emit_move_insn (temp, new_rtx);
3566
3567 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3568 if (reg != 0)
3569 {
3570 s390_load_address (reg, new_rtx);
3571 new_rtx = reg;
3572 }
3573 break;
3574
3575 case TLS_MODEL_INITIAL_EXEC:
3576 if (flag_pic == 1)
3577 {
3578 /* Assume GOT offset < 4k. This is handled the same way
3579 in both 31- and 64-bit code. */
3580
3581 if (reload_in_progress || reload_completed)
3582 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3583
3584 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3585 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3586 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3587 new_rtx = gen_const_mem (Pmode, new_rtx);
3588 temp = gen_reg_rtx (Pmode);
3589 emit_move_insn (temp, new_rtx);
3590 }
3591 else if (TARGET_CPU_ZARCH)
3592 {
3593 /* If the GOT offset might be >= 4k, we determine the position
3594 of the GOT entry via a PC-relative LARL. */
3595
3596 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3597 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3598 temp = gen_reg_rtx (Pmode);
3599 emit_move_insn (temp, new_rtx);
3600
3601 new_rtx = gen_const_mem (Pmode, temp);
3602 temp = gen_reg_rtx (Pmode);
3603 emit_move_insn (temp, new_rtx);
3604 }
3605 else if (flag_pic)
3606 {
3607 /* If the GOT offset might be >= 4k, we have to load it
3608 from the literal pool. */
3609
3610 if (reload_in_progress || reload_completed)
3611 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3612
3613 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3614 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3615 new_rtx = force_const_mem (Pmode, new_rtx);
3616 temp = gen_reg_rtx (Pmode);
3617 emit_move_insn (temp, new_rtx);
3618
3619 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3620 new_rtx = gen_const_mem (Pmode, new_rtx);
3621
3622 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3623 temp = gen_reg_rtx (Pmode);
3624 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3625 }
3626 else
3627 {
3628 /* In position-dependent code, load the absolute address of
3629 the GOT entry from the literal pool. */
3630
3631 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3632 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3633 new_rtx = force_const_mem (Pmode, new_rtx);
3634 temp = gen_reg_rtx (Pmode);
3635 emit_move_insn (temp, new_rtx);
3636
3637 new_rtx = temp;
3638 new_rtx = gen_const_mem (Pmode, new_rtx);
3639 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3640 temp = gen_reg_rtx (Pmode);
3641 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3642 }
3643
3644 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3645 if (reg != 0)
3646 {
3647 s390_load_address (reg, new_rtx);
3648 new_rtx = reg;
3649 }
3650 break;
3651
3652 case TLS_MODEL_LOCAL_EXEC:
3653 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3654 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3655 new_rtx = force_const_mem (Pmode, new_rtx);
3656 temp = gen_reg_rtx (Pmode);
3657 emit_move_insn (temp, new_rtx);
3658
3659 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3660 if (reg != 0)
3661 {
3662 s390_load_address (reg, new_rtx);
3663 new_rtx = reg;
3664 }
3665 break;
3666
3667 default:
3668 gcc_unreachable ();
3669 }
3670
3671 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3672 {
3673 switch (XINT (XEXP (addr, 0), 1))
3674 {
3675 case UNSPEC_INDNTPOFF:
3676 gcc_assert (TARGET_CPU_ZARCH);
3677 new_rtx = addr;
3678 break;
3679
3680 default:
3681 gcc_unreachable ();
3682 }
3683 }
3684
3685 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3686 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3687 {
3688 new_rtx = XEXP (XEXP (addr, 0), 0);
3689 if (GET_CODE (new_rtx) != SYMBOL_REF)
3690 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3691
3692 new_rtx = legitimize_tls_address (new_rtx, reg);
3693 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3694 new_rtx = force_operand (new_rtx, 0);
3695 }
3696
3697 else
3698 gcc_unreachable (); /* for now ... */
3699
3700 return new_rtx;
3701 }
3702
3703 /* Emit insns making the address in operands[1] valid for a standard
3704 move to operands[0]. operands[1] is replaced by an address which
3705 should be used instead of the former RTX to emit the move
3706 pattern. */
3707
3708 void
3709 emit_symbolic_move (rtx *operands)
3710 {
3711 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3712
3713 if (GET_CODE (operands[0]) == MEM)
3714 operands[1] = force_reg (Pmode, operands[1]);
3715 else if (TLS_SYMBOLIC_CONST (operands[1]))
3716 operands[1] = legitimize_tls_address (operands[1], temp);
3717 else if (flag_pic)
3718 operands[1] = legitimize_pic_address (operands[1], temp);
3719 }
3720
3721 /* Try machine-dependent ways of modifying an illegitimate address X
3722 to be legitimate. If we find one, return the new, valid address.
3723
3724 OLDX is the address as it was before break_out_memory_refs was called.
3725 In some cases it is useful to look at this to decide what needs to be done.
3726
3727 MODE is the mode of the operand pointed to by X.
3728
3729 When -fpic is used, special handling is needed for symbolic references.
3730 See comments by legitimize_pic_address for details. */
3731
3732 static rtx
3733 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3734 enum machine_mode mode ATTRIBUTE_UNUSED)
3735 {
3736 rtx constant_term = const0_rtx;
3737
3738 if (TLS_SYMBOLIC_CONST (x))
3739 {
3740 x = legitimize_tls_address (x, 0);
3741
3742 if (s390_legitimate_address_p (mode, x, FALSE))
3743 return x;
3744 }
3745 else if (GET_CODE (x) == PLUS
3746 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3747 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3748 {
3749 return x;
3750 }
3751 else if (flag_pic)
3752 {
3753 if (SYMBOLIC_CONST (x)
3754 || (GET_CODE (x) == PLUS
3755 && (SYMBOLIC_CONST (XEXP (x, 0))
3756 || SYMBOLIC_CONST (XEXP (x, 1)))))
3757 x = legitimize_pic_address (x, 0);
3758
3759 if (s390_legitimate_address_p (mode, x, FALSE))
3760 return x;
3761 }
3762
3763 x = eliminate_constant_term (x, &constant_term);
3764
3765 /* Optimize loading of large displacements by splitting them
3766 into the multiple of 4K and the rest; this allows the
3767 former to be CSE'd if possible.
3768
3769 Don't do this if the displacement is added to a register
3770 pointing into the stack frame, as the offsets will
3771 change later anyway. */
3772
3773 if (GET_CODE (constant_term) == CONST_INT
3774 && !TARGET_LONG_DISPLACEMENT
3775 && !DISP_IN_RANGE (INTVAL (constant_term))
3776 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3777 {
3778 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3779 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3780
3781 rtx temp = gen_reg_rtx (Pmode);
3782 rtx val = force_operand (GEN_INT (upper), temp);
3783 if (val != temp)
3784 emit_move_insn (temp, val);
3785
3786 x = gen_rtx_PLUS (Pmode, x, temp);
3787 constant_term = GEN_INT (lower);
3788 }
3789
3790 if (GET_CODE (x) == PLUS)
3791 {
3792 if (GET_CODE (XEXP (x, 0)) == REG)
3793 {
3794 rtx temp = gen_reg_rtx (Pmode);
3795 rtx val = force_operand (XEXP (x, 1), temp);
3796 if (val != temp)
3797 emit_move_insn (temp, val);
3798
3799 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3800 }
3801
3802 else if (GET_CODE (XEXP (x, 1)) == REG)
3803 {
3804 rtx temp = gen_reg_rtx (Pmode);
3805 rtx val = force_operand (XEXP (x, 0), temp);
3806 if (val != temp)
3807 emit_move_insn (temp, val);
3808
3809 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3810 }
3811 }
3812
3813 if (constant_term != const0_rtx)
3814 x = gen_rtx_PLUS (Pmode, x, constant_term);
3815
3816 return x;
3817 }
3818
3819 /* Try a machine-dependent way of reloading an illegitimate address AD
3820 operand. If we find one, push the reload and and return the new address.
3821
3822 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3823 and TYPE is the reload type of the current reload. */
3824
3825 rtx
3826 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3827 int opnum, int type)
3828 {
3829 if (!optimize || TARGET_LONG_DISPLACEMENT)
3830 return NULL_RTX;
3831
3832 if (GET_CODE (ad) == PLUS)
3833 {
3834 rtx tem = simplify_binary_operation (PLUS, Pmode,
3835 XEXP (ad, 0), XEXP (ad, 1));
3836 if (tem)
3837 ad = tem;
3838 }
3839
3840 if (GET_CODE (ad) == PLUS
3841 && GET_CODE (XEXP (ad, 0)) == REG
3842 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3843 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3844 {
3845 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3846 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3847 rtx cst, tem, new_rtx;
3848
3849 cst = GEN_INT (upper);
3850 if (!legitimate_reload_constant_p (cst))
3851 cst = force_const_mem (Pmode, cst);
3852
3853 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3854 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3855
3856 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3857 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3858 opnum, (enum reload_type) type);
3859 return new_rtx;
3860 }
3861
3862 return NULL_RTX;
3863 }
3864
3865 /* Emit code to move LEN bytes from DST to SRC. */
3866
3867 void
3868 s390_expand_movmem (rtx dst, rtx src, rtx len)
3869 {
3870 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3871 {
3872 if (INTVAL (len) > 0)
3873 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3874 }
3875
3876 else if (TARGET_MVCLE)
3877 {
3878 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3879 }
3880
3881 else
3882 {
3883 rtx dst_addr, src_addr, count, blocks, temp;
3884 rtx loop_start_label = gen_label_rtx ();
3885 rtx loop_end_label = gen_label_rtx ();
3886 rtx end_label = gen_label_rtx ();
3887 enum machine_mode mode;
3888
3889 mode = GET_MODE (len);
3890 if (mode == VOIDmode)
3891 mode = Pmode;
3892
3893 dst_addr = gen_reg_rtx (Pmode);
3894 src_addr = gen_reg_rtx (Pmode);
3895 count = gen_reg_rtx (mode);
3896 blocks = gen_reg_rtx (mode);
3897
3898 convert_move (count, len, 1);
3899 emit_cmp_and_jump_insns (count, const0_rtx,
3900 EQ, NULL_RTX, mode, 1, end_label);
3901
3902 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3903 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3904 dst = change_address (dst, VOIDmode, dst_addr);
3905 src = change_address (src, VOIDmode, src_addr);
3906
3907 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3908 OPTAB_DIRECT);
3909 if (temp != count)
3910 emit_move_insn (count, temp);
3911
3912 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3913 OPTAB_DIRECT);
3914 if (temp != blocks)
3915 emit_move_insn (blocks, temp);
3916
3917 emit_cmp_and_jump_insns (blocks, const0_rtx,
3918 EQ, NULL_RTX, mode, 1, loop_end_label);
3919
3920 emit_label (loop_start_label);
3921
3922 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3923 s390_load_address (dst_addr,
3924 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3925 s390_load_address (src_addr,
3926 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3927
3928 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
3929 OPTAB_DIRECT);
3930 if (temp != blocks)
3931 emit_move_insn (blocks, temp);
3932
3933 emit_cmp_and_jump_insns (blocks, const0_rtx,
3934 EQ, NULL_RTX, mode, 1, loop_end_label);
3935
3936 emit_jump (loop_start_label);
3937 emit_label (loop_end_label);
3938
3939 emit_insn (gen_movmem_short (dst, src,
3940 convert_to_mode (Pmode, count, 1)));
3941 emit_label (end_label);
3942 }
3943 }
3944
3945 /* Emit code to set LEN bytes at DST to VAL.
3946 Make use of clrmem if VAL is zero. */
3947
3948 void
3949 s390_expand_setmem (rtx dst, rtx len, rtx val)
3950 {
3951 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
3952 return;
3953
3954 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3955
3956 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
3957 {
3958 if (val == const0_rtx && INTVAL (len) <= 256)
3959 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3960 else
3961 {
3962 /* Initialize memory by storing the first byte. */
3963 emit_move_insn (adjust_address (dst, QImode, 0), val);
3964
3965 if (INTVAL (len) > 1)
3966 {
3967 /* Initiate 1 byte overlap move.
3968 The first byte of DST is propagated through DSTP1.
3969 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3970 DST is set to size 1 so the rest of the memory location
3971 does not count as source operand. */
3972 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3973 set_mem_size (dst, const1_rtx);
3974
3975 emit_insn (gen_movmem_short (dstp1, dst,
3976 GEN_INT (INTVAL (len) - 2)));
3977 }
3978 }
3979 }
3980
3981 else if (TARGET_MVCLE)
3982 {
3983 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3984 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3985 }
3986
3987 else
3988 {
3989 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3990 rtx loop_start_label = gen_label_rtx ();
3991 rtx loop_end_label = gen_label_rtx ();
3992 rtx end_label = gen_label_rtx ();
3993 enum machine_mode mode;
3994
3995 mode = GET_MODE (len);
3996 if (mode == VOIDmode)
3997 mode = Pmode;
3998
3999 dst_addr = gen_reg_rtx (Pmode);
4000 src_addr = gen_reg_rtx (Pmode);
4001 count = gen_reg_rtx (mode);
4002 blocks = gen_reg_rtx (mode);
4003
4004 convert_move (count, len, 1);
4005 emit_cmp_and_jump_insns (count, const0_rtx,
4006 EQ, NULL_RTX, mode, 1, end_label);
4007
4008 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4009 dst = change_address (dst, VOIDmode, dst_addr);
4010
4011 if (val == const0_rtx)
4012 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4013 OPTAB_DIRECT);
4014 else
4015 {
4016 dstp1 = adjust_address (dst, VOIDmode, 1);
4017 set_mem_size (dst, const1_rtx);
4018
4019 /* Initialize memory by storing the first byte. */
4020 emit_move_insn (adjust_address (dst, QImode, 0), val);
4021
4022 /* If count is 1 we are done. */
4023 emit_cmp_and_jump_insns (count, const1_rtx,
4024 EQ, NULL_RTX, mode, 1, end_label);
4025
4026 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4027 OPTAB_DIRECT);
4028 }
4029 if (temp != count)
4030 emit_move_insn (count, temp);
4031
4032 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4033 OPTAB_DIRECT);
4034 if (temp != blocks)
4035 emit_move_insn (blocks, temp);
4036
4037 emit_cmp_and_jump_insns (blocks, const0_rtx,
4038 EQ, NULL_RTX, mode, 1, loop_end_label);
4039
4040 emit_label (loop_start_label);
4041
4042 if (val == const0_rtx)
4043 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4044 else
4045 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4046 s390_load_address (dst_addr,
4047 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4048
4049 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4050 OPTAB_DIRECT);
4051 if (temp != blocks)
4052 emit_move_insn (blocks, temp);
4053
4054 emit_cmp_and_jump_insns (blocks, const0_rtx,
4055 EQ, NULL_RTX, mode, 1, loop_end_label);
4056
4057 emit_jump (loop_start_label);
4058 emit_label (loop_end_label);
4059
4060 if (val == const0_rtx)
4061 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4062 else
4063 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4064 emit_label (end_label);
4065 }
4066 }
4067
4068 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4069 and return the result in TARGET. */
4070
4071 void
4072 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4073 {
4074 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4075 rtx tmp;
4076
4077 /* As the result of CMPINT is inverted compared to what we need,
4078 we have to swap the operands. */
4079 tmp = op0; op0 = op1; op1 = tmp;
4080
4081 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4082 {
4083 if (INTVAL (len) > 0)
4084 {
4085 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4086 emit_insn (gen_cmpint (target, ccreg));
4087 }
4088 else
4089 emit_move_insn (target, const0_rtx);
4090 }
4091 else if (TARGET_MVCLE)
4092 {
4093 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4094 emit_insn (gen_cmpint (target, ccreg));
4095 }
4096 else
4097 {
4098 rtx addr0, addr1, count, blocks, temp;
4099 rtx loop_start_label = gen_label_rtx ();
4100 rtx loop_end_label = gen_label_rtx ();
4101 rtx end_label = gen_label_rtx ();
4102 enum machine_mode mode;
4103
4104 mode = GET_MODE (len);
4105 if (mode == VOIDmode)
4106 mode = Pmode;
4107
4108 addr0 = gen_reg_rtx (Pmode);
4109 addr1 = gen_reg_rtx (Pmode);
4110 count = gen_reg_rtx (mode);
4111 blocks = gen_reg_rtx (mode);
4112
4113 convert_move (count, len, 1);
4114 emit_cmp_and_jump_insns (count, const0_rtx,
4115 EQ, NULL_RTX, mode, 1, end_label);
4116
4117 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4118 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4119 op0 = change_address (op0, VOIDmode, addr0);
4120 op1 = change_address (op1, VOIDmode, addr1);
4121
4122 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4123 OPTAB_DIRECT);
4124 if (temp != count)
4125 emit_move_insn (count, temp);
4126
4127 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4128 OPTAB_DIRECT);
4129 if (temp != blocks)
4130 emit_move_insn (blocks, temp);
4131
4132 emit_cmp_and_jump_insns (blocks, const0_rtx,
4133 EQ, NULL_RTX, mode, 1, loop_end_label);
4134
4135 emit_label (loop_start_label);
4136
4137 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4138 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4139 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4140 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4141 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4142 emit_jump_insn (temp);
4143
4144 s390_load_address (addr0,
4145 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4146 s390_load_address (addr1,
4147 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4148
4149 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4150 OPTAB_DIRECT);
4151 if (temp != blocks)
4152 emit_move_insn (blocks, temp);
4153
4154 emit_cmp_and_jump_insns (blocks, const0_rtx,
4155 EQ, NULL_RTX, mode, 1, loop_end_label);
4156
4157 emit_jump (loop_start_label);
4158 emit_label (loop_end_label);
4159
4160 emit_insn (gen_cmpmem_short (op0, op1,
4161 convert_to_mode (Pmode, count, 1)));
4162 emit_label (end_label);
4163
4164 emit_insn (gen_cmpint (target, ccreg));
4165 }
4166 }
4167
4168
4169 /* Expand conditional increment or decrement using alc/slb instructions.
4170 Should generate code setting DST to either SRC or SRC + INCREMENT,
4171 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4172 Returns true if successful, false otherwise.
4173
4174 That makes it possible to implement some if-constructs without jumps e.g.:
4175 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4176 unsigned int a, b, c;
4177 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4178 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4179 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4180 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4181
4182 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4183 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4184 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4185 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4186 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4187
4188 bool
4189 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4190 rtx dst, rtx src, rtx increment)
4191 {
4192 enum machine_mode cmp_mode;
4193 enum machine_mode cc_mode;
4194 rtx op_res;
4195 rtx insn;
4196 rtvec p;
4197 int ret;
4198
4199 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4200 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4201 cmp_mode = SImode;
4202 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4203 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4204 cmp_mode = DImode;
4205 else
4206 return false;
4207
4208 /* Try ADD LOGICAL WITH CARRY. */
4209 if (increment == const1_rtx)
4210 {
4211 /* Determine CC mode to use. */
4212 if (cmp_code == EQ || cmp_code == NE)
4213 {
4214 if (cmp_op1 != const0_rtx)
4215 {
4216 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4217 NULL_RTX, 0, OPTAB_WIDEN);
4218 cmp_op1 = const0_rtx;
4219 }
4220
4221 cmp_code = cmp_code == EQ ? LEU : GTU;
4222 }
4223
4224 if (cmp_code == LTU || cmp_code == LEU)
4225 {
4226 rtx tem = cmp_op0;
4227 cmp_op0 = cmp_op1;
4228 cmp_op1 = tem;
4229 cmp_code = swap_condition (cmp_code);
4230 }
4231
4232 switch (cmp_code)
4233 {
4234 case GTU:
4235 cc_mode = CCUmode;
4236 break;
4237
4238 case GEU:
4239 cc_mode = CCL3mode;
4240 break;
4241
4242 default:
4243 return false;
4244 }
4245
4246 /* Emit comparison instruction pattern. */
4247 if (!register_operand (cmp_op0, cmp_mode))
4248 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4249
4250 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4251 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4252 /* We use insn_invalid_p here to add clobbers if required. */
4253 ret = insn_invalid_p (emit_insn (insn));
4254 gcc_assert (!ret);
4255
4256 /* Emit ALC instruction pattern. */
4257 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4258 gen_rtx_REG (cc_mode, CC_REGNUM),
4259 const0_rtx);
4260
4261 if (src != const0_rtx)
4262 {
4263 if (!register_operand (src, GET_MODE (dst)))
4264 src = force_reg (GET_MODE (dst), src);
4265
4266 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4267 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4268 }
4269
4270 p = rtvec_alloc (2);
4271 RTVEC_ELT (p, 0) =
4272 gen_rtx_SET (VOIDmode, dst, op_res);
4273 RTVEC_ELT (p, 1) =
4274 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4275 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4276
4277 return true;
4278 }
4279
4280 /* Try SUBTRACT LOGICAL WITH BORROW. */
4281 if (increment == constm1_rtx)
4282 {
4283 /* Determine CC mode to use. */
4284 if (cmp_code == EQ || cmp_code == NE)
4285 {
4286 if (cmp_op1 != const0_rtx)
4287 {
4288 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4289 NULL_RTX, 0, OPTAB_WIDEN);
4290 cmp_op1 = const0_rtx;
4291 }
4292
4293 cmp_code = cmp_code == EQ ? LEU : GTU;
4294 }
4295
4296 if (cmp_code == GTU || cmp_code == GEU)
4297 {
4298 rtx tem = cmp_op0;
4299 cmp_op0 = cmp_op1;
4300 cmp_op1 = tem;
4301 cmp_code = swap_condition (cmp_code);
4302 }
4303
4304 switch (cmp_code)
4305 {
4306 case LEU:
4307 cc_mode = CCUmode;
4308 break;
4309
4310 case LTU:
4311 cc_mode = CCL3mode;
4312 break;
4313
4314 default:
4315 return false;
4316 }
4317
4318 /* Emit comparison instruction pattern. */
4319 if (!register_operand (cmp_op0, cmp_mode))
4320 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4321
4322 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4323 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4324 /* We use insn_invalid_p here to add clobbers if required. */
4325 ret = insn_invalid_p (emit_insn (insn));
4326 gcc_assert (!ret);
4327
4328 /* Emit SLB instruction pattern. */
4329 if (!register_operand (src, GET_MODE (dst)))
4330 src = force_reg (GET_MODE (dst), src);
4331
4332 op_res = gen_rtx_MINUS (GET_MODE (dst),
4333 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4334 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4335 gen_rtx_REG (cc_mode, CC_REGNUM),
4336 const0_rtx));
4337 p = rtvec_alloc (2);
4338 RTVEC_ELT (p, 0) =
4339 gen_rtx_SET (VOIDmode, dst, op_res);
4340 RTVEC_ELT (p, 1) =
4341 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4342 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4343
4344 return true;
4345 }
4346
4347 return false;
4348 }
4349
4350 /* Expand code for the insv template. Return true if successful. */
4351
4352 bool
4353 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4354 {
4355 int bitsize = INTVAL (op1);
4356 int bitpos = INTVAL (op2);
4357
4358 /* On z10 we can use the risbg instruction to implement insv. */
4359 if (TARGET_Z10
4360 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4361 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4362 {
4363 rtx op;
4364 rtx clobber;
4365
4366 op = gen_rtx_SET (GET_MODE(src),
4367 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4368 src);
4369 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4370 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4371
4372 return true;
4373 }
4374
4375 /* We need byte alignment. */
4376 if (bitsize % BITS_PER_UNIT)
4377 return false;
4378
4379 if (bitpos == 0
4380 && memory_operand (dest, VOIDmode)
4381 && (register_operand (src, word_mode)
4382 || const_int_operand (src, VOIDmode)))
4383 {
4384 /* Emit standard pattern if possible. */
4385 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4386 if (GET_MODE_BITSIZE (mode) == bitsize)
4387 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4388
4389 /* (set (ze (mem)) (const_int)). */
4390 else if (const_int_operand (src, VOIDmode))
4391 {
4392 int size = bitsize / BITS_PER_UNIT;
4393 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4394 GET_MODE_SIZE (word_mode) - size);
4395
4396 dest = adjust_address (dest, BLKmode, 0);
4397 set_mem_size (dest, GEN_INT (size));
4398 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4399 }
4400
4401 /* (set (ze (mem)) (reg)). */
4402 else if (register_operand (src, word_mode))
4403 {
4404 if (bitsize <= GET_MODE_BITSIZE (SImode))
4405 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4406 const0_rtx), src);
4407 else
4408 {
4409 /* Emit st,stcmh sequence. */
4410 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4411 int size = stcmh_width / BITS_PER_UNIT;
4412
4413 emit_move_insn (adjust_address (dest, SImode, size),
4414 gen_lowpart (SImode, src));
4415 set_mem_size (dest, GEN_INT (size));
4416 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4417 (stcmh_width), const0_rtx),
4418 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4419 (GET_MODE_BITSIZE (SImode))));
4420 }
4421 }
4422 else
4423 return false;
4424
4425 return true;
4426 }
4427
4428 /* (set (ze (reg)) (const_int)). */
4429 if (TARGET_ZARCH
4430 && register_operand (dest, word_mode)
4431 && (bitpos % 16) == 0
4432 && (bitsize % 16) == 0
4433 && const_int_operand (src, VOIDmode))
4434 {
4435 HOST_WIDE_INT val = INTVAL (src);
4436 int regpos = bitpos + bitsize;
4437
4438 while (regpos > bitpos)
4439 {
4440 enum machine_mode putmode;
4441 int putsize;
4442
4443 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4444 putmode = SImode;
4445 else
4446 putmode = HImode;
4447
4448 putsize = GET_MODE_BITSIZE (putmode);
4449 regpos -= putsize;
4450 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4451 GEN_INT (putsize),
4452 GEN_INT (regpos)),
4453 gen_int_mode (val, putmode));
4454 val >>= putsize;
4455 }
4456 gcc_assert (regpos == bitpos);
4457 return true;
4458 }
4459
4460 return false;
4461 }
4462
4463 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4464 register that holds VAL of mode MODE shifted by COUNT bits. */
4465
4466 static inline rtx
4467 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4468 {
4469 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4470 NULL_RTX, 1, OPTAB_DIRECT);
4471 return expand_simple_binop (SImode, ASHIFT, val, count,
4472 NULL_RTX, 1, OPTAB_DIRECT);
4473 }
4474
4475 /* Structure to hold the initial parameters for a compare_and_swap operation
4476 in HImode and QImode. */
4477
4478 struct alignment_context
4479 {
4480 rtx memsi; /* SI aligned memory location. */
4481 rtx shift; /* Bit offset with regard to lsb. */
4482 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4483 rtx modemaski; /* ~modemask */
4484 bool aligned; /* True if memory is aligned, false else. */
4485 };
4486
4487 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4488 structure AC for transparent simplifying, if the memory alignment is known
4489 to be at least 32bit. MEM is the memory location for the actual operation
4490 and MODE its mode. */
4491
4492 static void
4493 init_alignment_context (struct alignment_context *ac, rtx mem,
4494 enum machine_mode mode)
4495 {
4496 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4497 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4498
4499 if (ac->aligned)
4500 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4501 else
4502 {
4503 /* Alignment is unknown. */
4504 rtx byteoffset, addr, align;
4505
4506 /* Force the address into a register. */
4507 addr = force_reg (Pmode, XEXP (mem, 0));
4508
4509 /* Align it to SImode. */
4510 align = expand_simple_binop (Pmode, AND, addr,
4511 GEN_INT (-GET_MODE_SIZE (SImode)),
4512 NULL_RTX, 1, OPTAB_DIRECT);
4513 /* Generate MEM. */
4514 ac->memsi = gen_rtx_MEM (SImode, align);
4515 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4516 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4517 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4518
4519 /* Calculate shiftcount. */
4520 byteoffset = expand_simple_binop (Pmode, AND, addr,
4521 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4522 NULL_RTX, 1, OPTAB_DIRECT);
4523 /* As we already have some offset, evaluate the remaining distance. */
4524 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4525 NULL_RTX, 1, OPTAB_DIRECT);
4526
4527 }
4528 /* Shift is the byte count, but we need the bitcount. */
4529 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4530 NULL_RTX, 1, OPTAB_DIRECT);
4531 /* Calculate masks. */
4532 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4533 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4534 NULL_RTX, 1, OPTAB_DIRECT);
4535 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4536 }
4537
4538 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4539 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4540 to set if CMP == MEM.
4541 CMP is never in memory for compare_and_swap_cc because
4542 expand_bool_compare_and_swap puts it into a register for later compare. */
4543
4544 void
4545 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4546 {
4547 struct alignment_context ac;
4548 rtx cmpv, newv, val, resv, cc;
4549 rtx res = gen_reg_rtx (SImode);
4550 rtx csloop = gen_label_rtx ();
4551 rtx csend = gen_label_rtx ();
4552
4553 gcc_assert (register_operand (target, VOIDmode));
4554 gcc_assert (MEM_P (mem));
4555
4556 init_alignment_context (&ac, mem, mode);
4557
4558 /* Shift the values to the correct bit positions. */
4559 if (!(ac.aligned && MEM_P (cmp)))
4560 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4561 if (!(ac.aligned && MEM_P (new_rtx)))
4562 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4563
4564 /* Load full word. Subsequent loads are performed by CS. */
4565 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4566 NULL_RTX, 1, OPTAB_DIRECT);
4567
4568 /* Start CS loop. */
4569 emit_label (csloop);
4570 /* val = "<mem>00..0<mem>"
4571 * cmp = "00..0<cmp>00..0"
4572 * new = "00..0<new>00..0"
4573 */
4574
4575 /* Patch cmp and new with val at correct position. */
4576 if (ac.aligned && MEM_P (cmp))
4577 {
4578 cmpv = force_reg (SImode, val);
4579 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4580 }
4581 else
4582 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4583 NULL_RTX, 1, OPTAB_DIRECT));
4584 if (ac.aligned && MEM_P (new_rtx))
4585 {
4586 newv = force_reg (SImode, val);
4587 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4588 }
4589 else
4590 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4591 NULL_RTX, 1, OPTAB_DIRECT));
4592
4593 /* Jump to end if we're done (likely?). */
4594 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4595 cmpv, newv));
4596
4597 /* Check for changes outside mode. */
4598 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4599 NULL_RTX, 1, OPTAB_DIRECT);
4600 cc = s390_emit_compare (NE, resv, val);
4601 emit_move_insn (val, resv);
4602 /* Loop internal if so. */
4603 s390_emit_jump (csloop, cc);
4604
4605 emit_label (csend);
4606
4607 /* Return the correct part of the bitfield. */
4608 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4609 NULL_RTX, 1, OPTAB_DIRECT), 1);
4610 }
4611
4612 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4613 and VAL the value to play with. If AFTER is true then store the value
4614 MEM holds after the operation, if AFTER is false then store the value MEM
4615 holds before the operation. If TARGET is zero then discard that value, else
4616 store it to TARGET. */
4617
4618 void
4619 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4620 rtx target, rtx mem, rtx val, bool after)
4621 {
4622 struct alignment_context ac;
4623 rtx cmp;
4624 rtx new_rtx = gen_reg_rtx (SImode);
4625 rtx orig = gen_reg_rtx (SImode);
4626 rtx csloop = gen_label_rtx ();
4627
4628 gcc_assert (!target || register_operand (target, VOIDmode));
4629 gcc_assert (MEM_P (mem));
4630
4631 init_alignment_context (&ac, mem, mode);
4632
4633 /* Shift val to the correct bit positions.
4634 Preserve "icm", but prevent "ex icm". */
4635 if (!(ac.aligned && code == SET && MEM_P (val)))
4636 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4637
4638 /* Further preparation insns. */
4639 if (code == PLUS || code == MINUS)
4640 emit_move_insn (orig, val);
4641 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4642 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4643 NULL_RTX, 1, OPTAB_DIRECT);
4644
4645 /* Load full word. Subsequent loads are performed by CS. */
4646 cmp = force_reg (SImode, ac.memsi);
4647
4648 /* Start CS loop. */
4649 emit_label (csloop);
4650 emit_move_insn (new_rtx, cmp);
4651
4652 /* Patch new with val at correct position. */
4653 switch (code)
4654 {
4655 case PLUS:
4656 case MINUS:
4657 val = expand_simple_binop (SImode, code, new_rtx, orig,
4658 NULL_RTX, 1, OPTAB_DIRECT);
4659 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4660 NULL_RTX, 1, OPTAB_DIRECT);
4661 /* FALLTHRU */
4662 case SET:
4663 if (ac.aligned && MEM_P (val))
4664 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4665 else
4666 {
4667 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4668 NULL_RTX, 1, OPTAB_DIRECT);
4669 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4670 NULL_RTX, 1, OPTAB_DIRECT);
4671 }
4672 break;
4673 case AND:
4674 case IOR:
4675 case XOR:
4676 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4677 NULL_RTX, 1, OPTAB_DIRECT);
4678 break;
4679 case MULT: /* NAND */
4680 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4681 NULL_RTX, 1, OPTAB_DIRECT);
4682 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4683 NULL_RTX, 1, OPTAB_DIRECT);
4684 break;
4685 default:
4686 gcc_unreachable ();
4687 }
4688
4689 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4690 ac.memsi, cmp, new_rtx));
4691
4692 /* Return the correct part of the bitfield. */
4693 if (target)
4694 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4695 after ? new_rtx : cmp, ac.shift,
4696 NULL_RTX, 1, OPTAB_DIRECT), 1);
4697 }
4698
4699 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4700 We need to emit DTP-relative relocations. */
4701
4702 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4703
4704 static void
4705 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4706 {
4707 switch (size)
4708 {
4709 case 4:
4710 fputs ("\t.long\t", file);
4711 break;
4712 case 8:
4713 fputs ("\t.quad\t", file);
4714 break;
4715 default:
4716 gcc_unreachable ();
4717 }
4718 output_addr_const (file, x);
4719 fputs ("@DTPOFF", file);
4720 }
4721
4722 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4723 /* Implement TARGET_MANGLE_TYPE. */
4724
4725 static const char *
4726 s390_mangle_type (const_tree type)
4727 {
4728 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4729 && TARGET_LONG_DOUBLE_128)
4730 return "g";
4731
4732 /* For all other types, use normal C++ mangling. */
4733 return NULL;
4734 }
4735 #endif
4736
4737 /* In the name of slightly smaller debug output, and to cater to
4738 general assembler lossage, recognize various UNSPEC sequences
4739 and turn them back into a direct symbol reference. */
4740
4741 static rtx
4742 s390_delegitimize_address (rtx orig_x)
4743 {
4744 rtx x = orig_x, y;
4745
4746 if (GET_CODE (x) != MEM)
4747 return orig_x;
4748
4749 x = XEXP (x, 0);
4750 if (GET_CODE (x) == PLUS
4751 && GET_CODE (XEXP (x, 1)) == CONST
4752 && GET_CODE (XEXP (x, 0)) == REG
4753 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4754 {
4755 y = XEXP (XEXP (x, 1), 0);
4756 if (GET_CODE (y) == UNSPEC
4757 && XINT (y, 1) == UNSPEC_GOT)
4758 return XVECEXP (y, 0, 0);
4759 return orig_x;
4760 }
4761
4762 if (GET_CODE (x) == CONST)
4763 {
4764 y = XEXP (x, 0);
4765 if (GET_CODE (y) == UNSPEC
4766 && XINT (y, 1) == UNSPEC_GOTENT)
4767 return XVECEXP (y, 0, 0);
4768 return orig_x;
4769 }
4770
4771 return orig_x;
4772 }
4773
4774 /* Output operand OP to stdio stream FILE.
4775 OP is an address (register + offset) which is not used to address data;
4776 instead the rightmost bits are interpreted as the value. */
4777
4778 static void
4779 print_shift_count_operand (FILE *file, rtx op)
4780 {
4781 HOST_WIDE_INT offset;
4782 rtx base;
4783
4784 /* Extract base register and offset. */
4785 if (!s390_decompose_shift_count (op, &base, &offset))
4786 gcc_unreachable ();
4787
4788 /* Sanity check. */
4789 if (base)
4790 {
4791 gcc_assert (GET_CODE (base) == REG);
4792 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4793 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4794 }
4795
4796 /* Offsets are constricted to twelve bits. */
4797 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4798 if (base)
4799 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4800 }
4801
4802 /* See 'get_some_local_dynamic_name'. */
4803
4804 static int
4805 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4806 {
4807 rtx x = *px;
4808
4809 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4810 {
4811 x = get_pool_constant (x);
4812 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4813 }
4814
4815 if (GET_CODE (x) == SYMBOL_REF
4816 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4817 {
4818 cfun->machine->some_ld_name = XSTR (x, 0);
4819 return 1;
4820 }
4821
4822 return 0;
4823 }
4824
4825 /* Locate some local-dynamic symbol still in use by this function
4826 so that we can print its name in local-dynamic base patterns. */
4827
4828 static const char *
4829 get_some_local_dynamic_name (void)
4830 {
4831 rtx insn;
4832
4833 if (cfun->machine->some_ld_name)
4834 return cfun->machine->some_ld_name;
4835
4836 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4837 if (INSN_P (insn)
4838 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4839 return cfun->machine->some_ld_name;
4840
4841 gcc_unreachable ();
4842 }
4843
4844 /* Output machine-dependent UNSPECs occurring in address constant X
4845 in assembler syntax to stdio stream FILE. Returns true if the
4846 constant X could be recognized, false otherwise. */
4847
4848 bool
4849 s390_output_addr_const_extra (FILE *file, rtx x)
4850 {
4851 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4852 switch (XINT (x, 1))
4853 {
4854 case UNSPEC_GOTENT:
4855 output_addr_const (file, XVECEXP (x, 0, 0));
4856 fprintf (file, "@GOTENT");
4857 return true;
4858 case UNSPEC_GOT:
4859 output_addr_const (file, XVECEXP (x, 0, 0));
4860 fprintf (file, "@GOT");
4861 return true;
4862 case UNSPEC_GOTOFF:
4863 output_addr_const (file, XVECEXP (x, 0, 0));
4864 fprintf (file, "@GOTOFF");
4865 return true;
4866 case UNSPEC_PLT:
4867 output_addr_const (file, XVECEXP (x, 0, 0));
4868 fprintf (file, "@PLT");
4869 return true;
4870 case UNSPEC_PLTOFF:
4871 output_addr_const (file, XVECEXP (x, 0, 0));
4872 fprintf (file, "@PLTOFF");
4873 return true;
4874 case UNSPEC_TLSGD:
4875 output_addr_const (file, XVECEXP (x, 0, 0));
4876 fprintf (file, "@TLSGD");
4877 return true;
4878 case UNSPEC_TLSLDM:
4879 assemble_name (file, get_some_local_dynamic_name ());
4880 fprintf (file, "@TLSLDM");
4881 return true;
4882 case UNSPEC_DTPOFF:
4883 output_addr_const (file, XVECEXP (x, 0, 0));
4884 fprintf (file, "@DTPOFF");
4885 return true;
4886 case UNSPEC_NTPOFF:
4887 output_addr_const (file, XVECEXP (x, 0, 0));
4888 fprintf (file, "@NTPOFF");
4889 return true;
4890 case UNSPEC_GOTNTPOFF:
4891 output_addr_const (file, XVECEXP (x, 0, 0));
4892 fprintf (file, "@GOTNTPOFF");
4893 return true;
4894 case UNSPEC_INDNTPOFF:
4895 output_addr_const (file, XVECEXP (x, 0, 0));
4896 fprintf (file, "@INDNTPOFF");
4897 return true;
4898 }
4899
4900 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
4901 switch (XINT (x, 1))
4902 {
4903 case UNSPEC_POOL_OFFSET:
4904 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
4905 output_addr_const (file, x);
4906 return true;
4907 }
4908 return false;
4909 }
4910
4911 /* Output address operand ADDR in assembler syntax to
4912 stdio stream FILE. */
4913
4914 void
4915 print_operand_address (FILE *file, rtx addr)
4916 {
4917 struct s390_address ad;
4918
4919 if (s390_symref_operand_p (addr, NULL, NULL))
4920 {
4921 gcc_assert (TARGET_Z10);
4922 output_addr_const (file, addr);
4923 return;
4924 }
4925
4926 if (!s390_decompose_address (addr, &ad)
4927 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4928 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4929 output_operand_lossage ("cannot decompose address");
4930
4931 if (ad.disp)
4932 output_addr_const (file, ad.disp);
4933 else
4934 fprintf (file, "0");
4935
4936 if (ad.base && ad.indx)
4937 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4938 reg_names[REGNO (ad.base)]);
4939 else if (ad.base)
4940 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4941 }
4942
4943 /* Output operand X in assembler syntax to stdio stream FILE.
4944 CODE specified the format flag. The following format flags
4945 are recognized:
4946
4947 'C': print opcode suffix for branch condition.
4948 'D': print opcode suffix for inverse branch condition.
4949 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4950 'G': print the size of the operand in bytes.
4951 'O': print only the displacement of a memory reference.
4952 'R': print only the base register of a memory reference.
4953 'S': print S-type memory reference (base+displacement).
4954 'N': print the second word of a DImode operand.
4955 'M': print the second word of a TImode operand.
4956 'Y': print shift count operand.
4957
4958 'b': print integer X as if it's an unsigned byte.
4959 'c': print integer X as if it's an signed byte.
4960 'x': print integer X as if it's an unsigned halfword.
4961 'h': print integer X as if it's a signed halfword.
4962 'i': print the first nonzero HImode part of X.
4963 'j': print the first HImode part unequal to -1 of X.
4964 'k': print the first nonzero SImode part of X.
4965 'm': print the first SImode part unequal to -1 of X.
4966 'o': print integer X as if it's an unsigned 32bit word. */
4967
4968 void
4969 print_operand (FILE *file, rtx x, int code)
4970 {
4971 switch (code)
4972 {
4973 case 'C':
4974 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4975 return;
4976
4977 case 'D':
4978 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4979 return;
4980
4981 case 'J':
4982 if (GET_CODE (x) == SYMBOL_REF)
4983 {
4984 fprintf (file, "%s", ":tls_load:");
4985 output_addr_const (file, x);
4986 }
4987 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4988 {
4989 fprintf (file, "%s", ":tls_gdcall:");
4990 output_addr_const (file, XVECEXP (x, 0, 0));
4991 }
4992 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4993 {
4994 fprintf (file, "%s", ":tls_ldcall:");
4995 assemble_name (file, get_some_local_dynamic_name ());
4996 }
4997 else
4998 gcc_unreachable ();
4999 return;
5000
5001 case 'G':
5002 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5003 return;
5004
5005 case 'O':
5006 {
5007 struct s390_address ad;
5008 int ret;
5009
5010 gcc_assert (GET_CODE (x) == MEM);
5011 ret = s390_decompose_address (XEXP (x, 0), &ad);
5012 gcc_assert (ret);
5013 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5014 gcc_assert (!ad.indx);
5015
5016 if (ad.disp)
5017 output_addr_const (file, ad.disp);
5018 else
5019 fprintf (file, "0");
5020 }
5021 return;
5022
5023 case 'R':
5024 {
5025 struct s390_address ad;
5026 int ret;
5027
5028 gcc_assert (GET_CODE (x) == MEM);
5029 ret = s390_decompose_address (XEXP (x, 0), &ad);
5030 gcc_assert (ret);
5031 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5032 gcc_assert (!ad.indx);
5033
5034 if (ad.base)
5035 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5036 else
5037 fprintf (file, "0");
5038 }
5039 return;
5040
5041 case 'S':
5042 {
5043 struct s390_address ad;
5044 int ret;
5045
5046 gcc_assert (GET_CODE (x) == MEM);
5047 ret = s390_decompose_address (XEXP (x, 0), &ad);
5048 gcc_assert (ret);
5049 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5050 gcc_assert (!ad.indx);
5051
5052 if (ad.disp)
5053 output_addr_const (file, ad.disp);
5054 else
5055 fprintf (file, "0");
5056
5057 if (ad.base)
5058 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5059 }
5060 return;
5061
5062 case 'N':
5063 if (GET_CODE (x) == REG)
5064 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5065 else if (GET_CODE (x) == MEM)
5066 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5067 else
5068 gcc_unreachable ();
5069 break;
5070
5071 case 'M':
5072 if (GET_CODE (x) == REG)
5073 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5074 else if (GET_CODE (x) == MEM)
5075 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5076 else
5077 gcc_unreachable ();
5078 break;
5079
5080 case 'Y':
5081 print_shift_count_operand (file, x);
5082 return;
5083 }
5084
5085 switch (GET_CODE (x))
5086 {
5087 case REG:
5088 fprintf (file, "%s", reg_names[REGNO (x)]);
5089 break;
5090
5091 case MEM:
5092 output_address (XEXP (x, 0));
5093 break;
5094
5095 case CONST:
5096 case CODE_LABEL:
5097 case LABEL_REF:
5098 case SYMBOL_REF:
5099 output_addr_const (file, x);
5100 break;
5101
5102 case CONST_INT:
5103 if (code == 'b')
5104 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5105 else if (code == 'c')
5106 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5107 else if (code == 'x')
5108 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5109 else if (code == 'h')
5110 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5111 else if (code == 'i')
5112 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5113 s390_extract_part (x, HImode, 0));
5114 else if (code == 'j')
5115 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5116 s390_extract_part (x, HImode, -1));
5117 else if (code == 'k')
5118 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5119 s390_extract_part (x, SImode, 0));
5120 else if (code == 'm')
5121 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5122 s390_extract_part (x, SImode, -1));
5123 else if (code == 'o')
5124 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5125 else
5126 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5127 break;
5128
5129 case CONST_DOUBLE:
5130 gcc_assert (GET_MODE (x) == VOIDmode);
5131 if (code == 'b')
5132 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5133 else if (code == 'x')
5134 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5135 else if (code == 'h')
5136 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5137 else
5138 gcc_unreachable ();
5139 break;
5140
5141 default:
5142 fatal_insn ("UNKNOWN in print_operand !?", x);
5143 break;
5144 }
5145 }
5146
5147 /* Target hook for assembling integer objects. We need to define it
5148 here to work a round a bug in some versions of GAS, which couldn't
5149 handle values smaller than INT_MIN when printed in decimal. */
5150
5151 static bool
5152 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5153 {
5154 if (size == 8 && aligned_p
5155 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5156 {
5157 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5158 INTVAL (x));
5159 return true;
5160 }
5161 return default_assemble_integer (x, size, aligned_p);
5162 }
5163
5164 /* Returns true if register REGNO is used for forming
5165 a memory address in expression X. */
5166
5167 static bool
5168 reg_used_in_mem_p (int regno, rtx x)
5169 {
5170 enum rtx_code code = GET_CODE (x);
5171 int i, j;
5172 const char *fmt;
5173
5174 if (code == MEM)
5175 {
5176 if (refers_to_regno_p (regno, regno+1,
5177 XEXP (x, 0), 0))
5178 return true;
5179 }
5180 else if (code == SET
5181 && GET_CODE (SET_DEST (x)) == PC)
5182 {
5183 if (refers_to_regno_p (regno, regno+1,
5184 SET_SRC (x), 0))
5185 return true;
5186 }
5187
5188 fmt = GET_RTX_FORMAT (code);
5189 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5190 {
5191 if (fmt[i] == 'e'
5192 && reg_used_in_mem_p (regno, XEXP (x, i)))
5193 return true;
5194
5195 else if (fmt[i] == 'E')
5196 for (j = 0; j < XVECLEN (x, i); j++)
5197 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5198 return true;
5199 }
5200 return false;
5201 }
5202
5203 /* Returns true if expression DEP_RTX sets an address register
5204 used by instruction INSN to address memory. */
5205
5206 static bool
5207 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5208 {
5209 rtx target, pat;
5210
5211 if (GET_CODE (dep_rtx) == INSN)
5212 dep_rtx = PATTERN (dep_rtx);
5213
5214 if (GET_CODE (dep_rtx) == SET)
5215 {
5216 target = SET_DEST (dep_rtx);
5217 if (GET_CODE (target) == STRICT_LOW_PART)
5218 target = XEXP (target, 0);
5219 while (GET_CODE (target) == SUBREG)
5220 target = SUBREG_REG (target);
5221
5222 if (GET_CODE (target) == REG)
5223 {
5224 int regno = REGNO (target);
5225
5226 if (s390_safe_attr_type (insn) == TYPE_LA)
5227 {
5228 pat = PATTERN (insn);
5229 if (GET_CODE (pat) == PARALLEL)
5230 {
5231 gcc_assert (XVECLEN (pat, 0) == 2);
5232 pat = XVECEXP (pat, 0, 0);
5233 }
5234 gcc_assert (GET_CODE (pat) == SET);
5235 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5236 }
5237 else if (get_attr_atype (insn) == ATYPE_AGEN)
5238 return reg_used_in_mem_p (regno, PATTERN (insn));
5239 }
5240 }
5241 return false;
5242 }
5243
5244 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5245
5246 int
5247 s390_agen_dep_p (rtx dep_insn, rtx insn)
5248 {
5249 rtx dep_rtx = PATTERN (dep_insn);
5250 int i;
5251
5252 if (GET_CODE (dep_rtx) == SET
5253 && addr_generation_dependency_p (dep_rtx, insn))
5254 return 1;
5255 else if (GET_CODE (dep_rtx) == PARALLEL)
5256 {
5257 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5258 {
5259 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5260 return 1;
5261 }
5262 }
5263 return 0;
5264 }
5265
5266
5267 /* A C statement (sans semicolon) to update the integer scheduling priority
5268 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5269 reduce the priority to execute INSN later. Do not define this macro if
5270 you do not need to adjust the scheduling priorities of insns.
5271
5272 A STD instruction should be scheduled earlier,
5273 in order to use the bypass. */
5274
5275 static int
5276 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5277 {
5278 if (! INSN_P (insn))
5279 return priority;
5280
5281 if (s390_tune != PROCESSOR_2084_Z990
5282 && s390_tune != PROCESSOR_2094_Z9_109)
5283 return priority;
5284
5285 switch (s390_safe_attr_type (insn))
5286 {
5287 case TYPE_FSTOREDF:
5288 case TYPE_FSTORESF:
5289 priority = priority << 3;
5290 break;
5291 case TYPE_STORE:
5292 case TYPE_STM:
5293 priority = priority << 1;
5294 break;
5295 default:
5296 break;
5297 }
5298 return priority;
5299 }
5300
5301 /* The number of instructions that can be issued per cycle. */
5302
5303 static int
5304 s390_issue_rate (void)
5305 {
5306 switch (s390_tune)
5307 {
5308 case PROCESSOR_2084_Z990:
5309 case PROCESSOR_2094_Z9_109:
5310 return 3;
5311 case PROCESSOR_2097_Z10:
5312 return 2;
5313 default:
5314 return 1;
5315 }
5316 }
5317
5318 static int
5319 s390_first_cycle_multipass_dfa_lookahead (void)
5320 {
5321 return 4;
5322 }
5323
5324
5325 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5326 Fix up MEMs as required. */
5327
5328 static void
5329 annotate_constant_pool_refs (rtx *x)
5330 {
5331 int i, j;
5332 const char *fmt;
5333
5334 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5335 || !CONSTANT_POOL_ADDRESS_P (*x));
5336
5337 /* Literal pool references can only occur inside a MEM ... */
5338 if (GET_CODE (*x) == MEM)
5339 {
5340 rtx memref = XEXP (*x, 0);
5341
5342 if (GET_CODE (memref) == SYMBOL_REF
5343 && CONSTANT_POOL_ADDRESS_P (memref))
5344 {
5345 rtx base = cfun->machine->base_reg;
5346 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5347 UNSPEC_LTREF);
5348
5349 *x = replace_equiv_address (*x, addr);
5350 return;
5351 }
5352
5353 if (GET_CODE (memref) == CONST
5354 && GET_CODE (XEXP (memref, 0)) == PLUS
5355 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5356 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5357 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5358 {
5359 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5360 rtx sym = XEXP (XEXP (memref, 0), 0);
5361 rtx base = cfun->machine->base_reg;
5362 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5363 UNSPEC_LTREF);
5364
5365 *x = replace_equiv_address (*x, plus_constant (addr, off));
5366 return;
5367 }
5368 }
5369
5370 /* ... or a load-address type pattern. */
5371 if (GET_CODE (*x) == SET)
5372 {
5373 rtx addrref = SET_SRC (*x);
5374
5375 if (GET_CODE (addrref) == SYMBOL_REF
5376 && CONSTANT_POOL_ADDRESS_P (addrref))
5377 {
5378 rtx base = cfun->machine->base_reg;
5379 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5380 UNSPEC_LTREF);
5381
5382 SET_SRC (*x) = addr;
5383 return;
5384 }
5385
5386 if (GET_CODE (addrref) == CONST
5387 && GET_CODE (XEXP (addrref, 0)) == PLUS
5388 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5389 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5390 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5391 {
5392 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5393 rtx sym = XEXP (XEXP (addrref, 0), 0);
5394 rtx base = cfun->machine->base_reg;
5395 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5396 UNSPEC_LTREF);
5397
5398 SET_SRC (*x) = plus_constant (addr, off);
5399 return;
5400 }
5401 }
5402
5403 /* Annotate LTREL_BASE as well. */
5404 if (GET_CODE (*x) == UNSPEC
5405 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5406 {
5407 rtx base = cfun->machine->base_reg;
5408 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5409 UNSPEC_LTREL_BASE);
5410 return;
5411 }
5412
5413 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5414 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5415 {
5416 if (fmt[i] == 'e')
5417 {
5418 annotate_constant_pool_refs (&XEXP (*x, i));
5419 }
5420 else if (fmt[i] == 'E')
5421 {
5422 for (j = 0; j < XVECLEN (*x, i); j++)
5423 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5424 }
5425 }
5426 }
5427
5428 /* Split all branches that exceed the maximum distance.
5429 Returns true if this created a new literal pool entry. */
5430
5431 static int
5432 s390_split_branches (void)
5433 {
5434 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5435 int new_literal = 0, ret;
5436 rtx insn, pat, tmp, target;
5437 rtx *label;
5438
5439 /* We need correct insn addresses. */
5440
5441 shorten_branches (get_insns ());
5442
5443 /* Find all branches that exceed 64KB, and split them. */
5444
5445 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5446 {
5447 if (GET_CODE (insn) != JUMP_INSN)
5448 continue;
5449
5450 pat = PATTERN (insn);
5451 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5452 pat = XVECEXP (pat, 0, 0);
5453 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5454 continue;
5455
5456 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5457 {
5458 label = &SET_SRC (pat);
5459 }
5460 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5461 {
5462 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5463 label = &XEXP (SET_SRC (pat), 1);
5464 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5465 label = &XEXP (SET_SRC (pat), 2);
5466 else
5467 continue;
5468 }
5469 else
5470 continue;
5471
5472 if (get_attr_length (insn) <= 4)
5473 continue;
5474
5475 /* We are going to use the return register as scratch register,
5476 make sure it will be saved/restored by the prologue/epilogue. */
5477 cfun_frame_layout.save_return_addr_p = 1;
5478
5479 if (!flag_pic)
5480 {
5481 new_literal = 1;
5482 tmp = force_const_mem (Pmode, *label);
5483 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5484 INSN_ADDRESSES_NEW (tmp, -1);
5485 annotate_constant_pool_refs (&PATTERN (tmp));
5486
5487 target = temp_reg;
5488 }
5489 else
5490 {
5491 new_literal = 1;
5492 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5493 UNSPEC_LTREL_OFFSET);
5494 target = gen_rtx_CONST (Pmode, target);
5495 target = force_const_mem (Pmode, target);
5496 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5497 INSN_ADDRESSES_NEW (tmp, -1);
5498 annotate_constant_pool_refs (&PATTERN (tmp));
5499
5500 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5501 cfun->machine->base_reg),
5502 UNSPEC_LTREL_BASE);
5503 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5504 }
5505
5506 ret = validate_change (insn, label, target, 0);
5507 gcc_assert (ret);
5508 }
5509
5510 return new_literal;
5511 }
5512
5513
5514 /* Find an annotated literal pool symbol referenced in RTX X,
5515 and store it at REF. Will abort if X contains references to
5516 more than one such pool symbol; multiple references to the same
5517 symbol are allowed, however.
5518
5519 The rtx pointed to by REF must be initialized to NULL_RTX
5520 by the caller before calling this routine. */
5521
5522 static void
5523 find_constant_pool_ref (rtx x, rtx *ref)
5524 {
5525 int i, j;
5526 const char *fmt;
5527
5528 /* Ignore LTREL_BASE references. */
5529 if (GET_CODE (x) == UNSPEC
5530 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5531 return;
5532 /* Likewise POOL_ENTRY insns. */
5533 if (GET_CODE (x) == UNSPEC_VOLATILE
5534 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5535 return;
5536
5537 gcc_assert (GET_CODE (x) != SYMBOL_REF
5538 || !CONSTANT_POOL_ADDRESS_P (x));
5539
5540 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5541 {
5542 rtx sym = XVECEXP (x, 0, 0);
5543 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5544 && CONSTANT_POOL_ADDRESS_P (sym));
5545
5546 if (*ref == NULL_RTX)
5547 *ref = sym;
5548 else
5549 gcc_assert (*ref == sym);
5550
5551 return;
5552 }
5553
5554 fmt = GET_RTX_FORMAT (GET_CODE (x));
5555 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5556 {
5557 if (fmt[i] == 'e')
5558 {
5559 find_constant_pool_ref (XEXP (x, i), ref);
5560 }
5561 else if (fmt[i] == 'E')
5562 {
5563 for (j = 0; j < XVECLEN (x, i); j++)
5564 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5565 }
5566 }
5567 }
5568
5569 /* Replace every reference to the annotated literal pool
5570 symbol REF in X by its base plus OFFSET. */
5571
5572 static void
5573 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5574 {
5575 int i, j;
5576 const char *fmt;
5577
5578 gcc_assert (*x != ref);
5579
5580 if (GET_CODE (*x) == UNSPEC
5581 && XINT (*x, 1) == UNSPEC_LTREF
5582 && XVECEXP (*x, 0, 0) == ref)
5583 {
5584 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5585 return;
5586 }
5587
5588 if (GET_CODE (*x) == PLUS
5589 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5590 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5591 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5592 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5593 {
5594 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5595 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5596 return;
5597 }
5598
5599 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5600 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5601 {
5602 if (fmt[i] == 'e')
5603 {
5604 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5605 }
5606 else if (fmt[i] == 'E')
5607 {
5608 for (j = 0; j < XVECLEN (*x, i); j++)
5609 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5610 }
5611 }
5612 }
5613
5614 /* Check whether X contains an UNSPEC_LTREL_BASE.
5615 Return its constant pool symbol if found, NULL_RTX otherwise. */
5616
5617 static rtx
5618 find_ltrel_base (rtx x)
5619 {
5620 int i, j;
5621 const char *fmt;
5622
5623 if (GET_CODE (x) == UNSPEC
5624 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5625 return XVECEXP (x, 0, 0);
5626
5627 fmt = GET_RTX_FORMAT (GET_CODE (x));
5628 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5629 {
5630 if (fmt[i] == 'e')
5631 {
5632 rtx fnd = find_ltrel_base (XEXP (x, i));
5633 if (fnd)
5634 return fnd;
5635 }
5636 else if (fmt[i] == 'E')
5637 {
5638 for (j = 0; j < XVECLEN (x, i); j++)
5639 {
5640 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5641 if (fnd)
5642 return fnd;
5643 }
5644 }
5645 }
5646
5647 return NULL_RTX;
5648 }
5649
5650 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5651
5652 static void
5653 replace_ltrel_base (rtx *x)
5654 {
5655 int i, j;
5656 const char *fmt;
5657
5658 if (GET_CODE (*x) == UNSPEC
5659 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5660 {
5661 *x = XVECEXP (*x, 0, 1);
5662 return;
5663 }
5664
5665 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5666 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5667 {
5668 if (fmt[i] == 'e')
5669 {
5670 replace_ltrel_base (&XEXP (*x, i));
5671 }
5672 else if (fmt[i] == 'E')
5673 {
5674 for (j = 0; j < XVECLEN (*x, i); j++)
5675 replace_ltrel_base (&XVECEXP (*x, i, j));
5676 }
5677 }
5678 }
5679
5680
5681 /* We keep a list of constants which we have to add to internal
5682 constant tables in the middle of large functions. */
5683
5684 #define NR_C_MODES 11
5685 enum machine_mode constant_modes[NR_C_MODES] =
5686 {
5687 TFmode, TImode, TDmode,
5688 DFmode, DImode, DDmode,
5689 SFmode, SImode, SDmode,
5690 HImode,
5691 QImode
5692 };
5693
5694 struct constant
5695 {
5696 struct constant *next;
5697 rtx value;
5698 rtx label;
5699 };
5700
5701 struct constant_pool
5702 {
5703 struct constant_pool *next;
5704 rtx first_insn;
5705 rtx pool_insn;
5706 bitmap insns;
5707 rtx emit_pool_after;
5708
5709 struct constant *constants[NR_C_MODES];
5710 struct constant *execute;
5711 rtx label;
5712 int size;
5713 };
5714
5715 /* Allocate new constant_pool structure. */
5716
5717 static struct constant_pool *
5718 s390_alloc_pool (void)
5719 {
5720 struct constant_pool *pool;
5721 int i;
5722
5723 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5724 pool->next = NULL;
5725 for (i = 0; i < NR_C_MODES; i++)
5726 pool->constants[i] = NULL;
5727
5728 pool->execute = NULL;
5729 pool->label = gen_label_rtx ();
5730 pool->first_insn = NULL_RTX;
5731 pool->pool_insn = NULL_RTX;
5732 pool->insns = BITMAP_ALLOC (NULL);
5733 pool->size = 0;
5734 pool->emit_pool_after = NULL_RTX;
5735
5736 return pool;
5737 }
5738
5739 /* Create new constant pool covering instructions starting at INSN
5740 and chain it to the end of POOL_LIST. */
5741
5742 static struct constant_pool *
5743 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5744 {
5745 struct constant_pool *pool, **prev;
5746
5747 pool = s390_alloc_pool ();
5748 pool->first_insn = insn;
5749
5750 for (prev = pool_list; *prev; prev = &(*prev)->next)
5751 ;
5752 *prev = pool;
5753
5754 return pool;
5755 }
5756
5757 /* End range of instructions covered by POOL at INSN and emit
5758 placeholder insn representing the pool. */
5759
5760 static void
5761 s390_end_pool (struct constant_pool *pool, rtx insn)
5762 {
5763 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5764
5765 if (!insn)
5766 insn = get_last_insn ();
5767
5768 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5769 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5770 }
5771
5772 /* Add INSN to the list of insns covered by POOL. */
5773
5774 static void
5775 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5776 {
5777 bitmap_set_bit (pool->insns, INSN_UID (insn));
5778 }
5779
5780 /* Return pool out of POOL_LIST that covers INSN. */
5781
5782 static struct constant_pool *
5783 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5784 {
5785 struct constant_pool *pool;
5786
5787 for (pool = pool_list; pool; pool = pool->next)
5788 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5789 break;
5790
5791 return pool;
5792 }
5793
5794 /* Add constant VAL of mode MODE to the constant pool POOL. */
5795
5796 static void
5797 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5798 {
5799 struct constant *c;
5800 int i;
5801
5802 for (i = 0; i < NR_C_MODES; i++)
5803 if (constant_modes[i] == mode)
5804 break;
5805 gcc_assert (i != NR_C_MODES);
5806
5807 for (c = pool->constants[i]; c != NULL; c = c->next)
5808 if (rtx_equal_p (val, c->value))
5809 break;
5810
5811 if (c == NULL)
5812 {
5813 c = (struct constant *) xmalloc (sizeof *c);
5814 c->value = val;
5815 c->label = gen_label_rtx ();
5816 c->next = pool->constants[i];
5817 pool->constants[i] = c;
5818 pool->size += GET_MODE_SIZE (mode);
5819 }
5820 }
5821
5822 /* Return an rtx that represents the offset of X from the start of
5823 pool POOL. */
5824
5825 static rtx
5826 s390_pool_offset (struct constant_pool *pool, rtx x)
5827 {
5828 rtx label;
5829
5830 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5831 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5832 UNSPEC_POOL_OFFSET);
5833 return gen_rtx_CONST (GET_MODE (x), x);
5834 }
5835
5836 /* Find constant VAL of mode MODE in the constant pool POOL.
5837 Return an RTX describing the distance from the start of
5838 the pool to the location of the new constant. */
5839
5840 static rtx
5841 s390_find_constant (struct constant_pool *pool, rtx val,
5842 enum machine_mode mode)
5843 {
5844 struct constant *c;
5845 int i;
5846
5847 for (i = 0; i < NR_C_MODES; i++)
5848 if (constant_modes[i] == mode)
5849 break;
5850 gcc_assert (i != NR_C_MODES);
5851
5852 for (c = pool->constants[i]; c != NULL; c = c->next)
5853 if (rtx_equal_p (val, c->value))
5854 break;
5855
5856 gcc_assert (c);
5857
5858 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5859 }
5860
5861 /* Check whether INSN is an execute. Return the label_ref to its
5862 execute target template if so, NULL_RTX otherwise. */
5863
5864 static rtx
5865 s390_execute_label (rtx insn)
5866 {
5867 if (GET_CODE (insn) == INSN
5868 && GET_CODE (PATTERN (insn)) == PARALLEL
5869 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5870 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5871 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5872
5873 return NULL_RTX;
5874 }
5875
5876 /* Add execute target for INSN to the constant pool POOL. */
5877
5878 static void
5879 s390_add_execute (struct constant_pool *pool, rtx insn)
5880 {
5881 struct constant *c;
5882
5883 for (c = pool->execute; c != NULL; c = c->next)
5884 if (INSN_UID (insn) == INSN_UID (c->value))
5885 break;
5886
5887 if (c == NULL)
5888 {
5889 c = (struct constant *) xmalloc (sizeof *c);
5890 c->value = insn;
5891 c->label = gen_label_rtx ();
5892 c->next = pool->execute;
5893 pool->execute = c;
5894 pool->size += 6;
5895 }
5896 }
5897
5898 /* Find execute target for INSN in the constant pool POOL.
5899 Return an RTX describing the distance from the start of
5900 the pool to the location of the execute target. */
5901
5902 static rtx
5903 s390_find_execute (struct constant_pool *pool, rtx insn)
5904 {
5905 struct constant *c;
5906
5907 for (c = pool->execute; c != NULL; c = c->next)
5908 if (INSN_UID (insn) == INSN_UID (c->value))
5909 break;
5910
5911 gcc_assert (c);
5912
5913 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5914 }
5915
5916 /* For an execute INSN, extract the execute target template. */
5917
5918 static rtx
5919 s390_execute_target (rtx insn)
5920 {
5921 rtx pattern = PATTERN (insn);
5922 gcc_assert (s390_execute_label (insn));
5923
5924 if (XVECLEN (pattern, 0) == 2)
5925 {
5926 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5927 }
5928 else
5929 {
5930 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5931 int i;
5932
5933 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5934 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5935
5936 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5937 }
5938
5939 return pattern;
5940 }
5941
5942 /* Indicate that INSN cannot be duplicated. This is the case for
5943 execute insns that carry a unique label. */
5944
5945 static bool
5946 s390_cannot_copy_insn_p (rtx insn)
5947 {
5948 rtx label = s390_execute_label (insn);
5949 return label && label != const0_rtx;
5950 }
5951
5952 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5953 do not emit the pool base label. */
5954
5955 static void
5956 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5957 {
5958 struct constant *c;
5959 rtx insn = pool->pool_insn;
5960 int i;
5961
5962 /* Switch to rodata section. */
5963 if (TARGET_CPU_ZARCH)
5964 {
5965 insn = emit_insn_after (gen_pool_section_start (), insn);
5966 INSN_ADDRESSES_NEW (insn, -1);
5967 }
5968
5969 /* Ensure minimum pool alignment. */
5970 if (TARGET_CPU_ZARCH)
5971 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5972 else
5973 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5974 INSN_ADDRESSES_NEW (insn, -1);
5975
5976 /* Emit pool base label. */
5977 if (!remote_label)
5978 {
5979 insn = emit_label_after (pool->label, insn);
5980 INSN_ADDRESSES_NEW (insn, -1);
5981 }
5982
5983 /* Dump constants in descending alignment requirement order,
5984 ensuring proper alignment for every constant. */
5985 for (i = 0; i < NR_C_MODES; i++)
5986 for (c = pool->constants[i]; c; c = c->next)
5987 {
5988 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5989 rtx value = copy_rtx (c->value);
5990 if (GET_CODE (value) == CONST
5991 && GET_CODE (XEXP (value, 0)) == UNSPEC
5992 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5993 && XVECLEN (XEXP (value, 0), 0) == 1)
5994 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
5995
5996 insn = emit_label_after (c->label, insn);
5997 INSN_ADDRESSES_NEW (insn, -1);
5998
5999 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6000 gen_rtvec (1, value),
6001 UNSPECV_POOL_ENTRY);
6002 insn = emit_insn_after (value, insn);
6003 INSN_ADDRESSES_NEW (insn, -1);
6004 }
6005
6006 /* Ensure minimum alignment for instructions. */
6007 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6008 INSN_ADDRESSES_NEW (insn, -1);
6009
6010 /* Output in-pool execute template insns. */
6011 for (c = pool->execute; c; c = c->next)
6012 {
6013 insn = emit_label_after (c->label, insn);
6014 INSN_ADDRESSES_NEW (insn, -1);
6015
6016 insn = emit_insn_after (s390_execute_target (c->value), insn);
6017 INSN_ADDRESSES_NEW (insn, -1);
6018 }
6019
6020 /* Switch back to previous section. */
6021 if (TARGET_CPU_ZARCH)
6022 {
6023 insn = emit_insn_after (gen_pool_section_end (), insn);
6024 INSN_ADDRESSES_NEW (insn, -1);
6025 }
6026
6027 insn = emit_barrier_after (insn);
6028 INSN_ADDRESSES_NEW (insn, -1);
6029
6030 /* Remove placeholder insn. */
6031 remove_insn (pool->pool_insn);
6032 }
6033
6034 /* Free all memory used by POOL. */
6035
6036 static void
6037 s390_free_pool (struct constant_pool *pool)
6038 {
6039 struct constant *c, *next;
6040 int i;
6041
6042 for (i = 0; i < NR_C_MODES; i++)
6043 for (c = pool->constants[i]; c; c = next)
6044 {
6045 next = c->next;
6046 free (c);
6047 }
6048
6049 for (c = pool->execute; c; c = next)
6050 {
6051 next = c->next;
6052 free (c);
6053 }
6054
6055 BITMAP_FREE (pool->insns);
6056 free (pool);
6057 }
6058
6059
6060 /* Collect main literal pool. Return NULL on overflow. */
6061
6062 static struct constant_pool *
6063 s390_mainpool_start (void)
6064 {
6065 struct constant_pool *pool;
6066 rtx insn;
6067
6068 pool = s390_alloc_pool ();
6069
6070 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6071 {
6072 if (GET_CODE (insn) == INSN
6073 && GET_CODE (PATTERN (insn)) == SET
6074 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6075 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6076 {
6077 gcc_assert (!pool->pool_insn);
6078 pool->pool_insn = insn;
6079 }
6080
6081 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6082 {
6083 s390_add_execute (pool, insn);
6084 }
6085 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6086 {
6087 rtx pool_ref = NULL_RTX;
6088 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6089 if (pool_ref)
6090 {
6091 rtx constant = get_pool_constant (pool_ref);
6092 enum machine_mode mode = get_pool_mode (pool_ref);
6093 s390_add_constant (pool, constant, mode);
6094 }
6095 }
6096
6097 /* If hot/cold partitioning is enabled we have to make sure that
6098 the literal pool is emitted in the same section where the
6099 initialization of the literal pool base pointer takes place.
6100 emit_pool_after is only used in the non-overflow case on non
6101 Z cpus where we can emit the literal pool at the end of the
6102 function body within the text section. */
6103 if (NOTE_P (insn)
6104 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6105 && !pool->emit_pool_after)
6106 pool->emit_pool_after = PREV_INSN (insn);
6107 }
6108
6109 gcc_assert (pool->pool_insn || pool->size == 0);
6110
6111 if (pool->size >= 4096)
6112 {
6113 /* We're going to chunkify the pool, so remove the main
6114 pool placeholder insn. */
6115 remove_insn (pool->pool_insn);
6116
6117 s390_free_pool (pool);
6118 pool = NULL;
6119 }
6120
6121 /* If the functions ends with the section where the literal pool
6122 should be emitted set the marker to its end. */
6123 if (pool && !pool->emit_pool_after)
6124 pool->emit_pool_after = get_last_insn ();
6125
6126 return pool;
6127 }
6128
6129 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6130 Modify the current function to output the pool constants as well as
6131 the pool register setup instruction. */
6132
6133 static void
6134 s390_mainpool_finish (struct constant_pool *pool)
6135 {
6136 rtx base_reg = cfun->machine->base_reg;
6137 rtx insn;
6138
6139 /* If the pool is empty, we're done. */
6140 if (pool->size == 0)
6141 {
6142 /* We don't actually need a base register after all. */
6143 cfun->machine->base_reg = NULL_RTX;
6144
6145 if (pool->pool_insn)
6146 remove_insn (pool->pool_insn);
6147 s390_free_pool (pool);
6148 return;
6149 }
6150
6151 /* We need correct insn addresses. */
6152 shorten_branches (get_insns ());
6153
6154 /* On zSeries, we use a LARL to load the pool register. The pool is
6155 located in the .rodata section, so we emit it after the function. */
6156 if (TARGET_CPU_ZARCH)
6157 {
6158 insn = gen_main_base_64 (base_reg, pool->label);
6159 insn = emit_insn_after (insn, pool->pool_insn);
6160 INSN_ADDRESSES_NEW (insn, -1);
6161 remove_insn (pool->pool_insn);
6162
6163 insn = get_last_insn ();
6164 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6165 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6166
6167 s390_dump_pool (pool, 0);
6168 }
6169
6170 /* On S/390, if the total size of the function's code plus literal pool
6171 does not exceed 4096 bytes, we use BASR to set up a function base
6172 pointer, and emit the literal pool at the end of the function. */
6173 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6174 + pool->size + 8 /* alignment slop */ < 4096)
6175 {
6176 insn = gen_main_base_31_small (base_reg, pool->label);
6177 insn = emit_insn_after (insn, pool->pool_insn);
6178 INSN_ADDRESSES_NEW (insn, -1);
6179 remove_insn (pool->pool_insn);
6180
6181 insn = emit_label_after (pool->label, insn);
6182 INSN_ADDRESSES_NEW (insn, -1);
6183
6184 /* emit_pool_after will be set by s390_mainpool_start to the
6185 last insn of the section where the literal pool should be
6186 emitted. */
6187 insn = pool->emit_pool_after;
6188
6189 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6190 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6191
6192 s390_dump_pool (pool, 1);
6193 }
6194
6195 /* Otherwise, we emit an inline literal pool and use BASR to branch
6196 over it, setting up the pool register at the same time. */
6197 else
6198 {
6199 rtx pool_end = gen_label_rtx ();
6200
6201 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6202 insn = emit_insn_after (insn, pool->pool_insn);
6203 INSN_ADDRESSES_NEW (insn, -1);
6204 remove_insn (pool->pool_insn);
6205
6206 insn = emit_label_after (pool->label, insn);
6207 INSN_ADDRESSES_NEW (insn, -1);
6208
6209 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6210 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6211
6212 insn = emit_label_after (pool_end, pool->pool_insn);
6213 INSN_ADDRESSES_NEW (insn, -1);
6214
6215 s390_dump_pool (pool, 1);
6216 }
6217
6218
6219 /* Replace all literal pool references. */
6220
6221 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6222 {
6223 if (INSN_P (insn))
6224 replace_ltrel_base (&PATTERN (insn));
6225
6226 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6227 {
6228 rtx addr, pool_ref = NULL_RTX;
6229 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6230 if (pool_ref)
6231 {
6232 if (s390_execute_label (insn))
6233 addr = s390_find_execute (pool, insn);
6234 else
6235 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6236 get_pool_mode (pool_ref));
6237
6238 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6239 INSN_CODE (insn) = -1;
6240 }
6241 }
6242 }
6243
6244
6245 /* Free the pool. */
6246 s390_free_pool (pool);
6247 }
6248
6249 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6250 We have decided we cannot use this pool, so revert all changes
6251 to the current function that were done by s390_mainpool_start. */
6252 static void
6253 s390_mainpool_cancel (struct constant_pool *pool)
6254 {
6255 /* We didn't actually change the instruction stream, so simply
6256 free the pool memory. */
6257 s390_free_pool (pool);
6258 }
6259
6260
6261 /* Chunkify the literal pool. */
6262
6263 #define S390_POOL_CHUNK_MIN 0xc00
6264 #define S390_POOL_CHUNK_MAX 0xe00
6265
6266 static struct constant_pool *
6267 s390_chunkify_start (void)
6268 {
6269 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6270 int extra_size = 0;
6271 bitmap far_labels;
6272 rtx pending_ltrel = NULL_RTX;
6273 rtx insn;
6274
6275 rtx (*gen_reload_base) (rtx, rtx) =
6276 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6277
6278
6279 /* We need correct insn addresses. */
6280
6281 shorten_branches (get_insns ());
6282
6283 /* Scan all insns and move literals to pool chunks. */
6284
6285 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6286 {
6287 bool section_switch_p = false;
6288
6289 /* Check for pending LTREL_BASE. */
6290 if (INSN_P (insn))
6291 {
6292 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6293 if (ltrel_base)
6294 {
6295 gcc_assert (ltrel_base == pending_ltrel);
6296 pending_ltrel = NULL_RTX;
6297 }
6298 }
6299
6300 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6301 {
6302 if (!curr_pool)
6303 curr_pool = s390_start_pool (&pool_list, insn);
6304
6305 s390_add_execute (curr_pool, insn);
6306 s390_add_pool_insn (curr_pool, insn);
6307 }
6308 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6309 {
6310 rtx pool_ref = NULL_RTX;
6311 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6312 if (pool_ref)
6313 {
6314 rtx constant = get_pool_constant (pool_ref);
6315 enum machine_mode mode = get_pool_mode (pool_ref);
6316
6317 if (!curr_pool)
6318 curr_pool = s390_start_pool (&pool_list, insn);
6319
6320 s390_add_constant (curr_pool, constant, mode);
6321 s390_add_pool_insn (curr_pool, insn);
6322
6323 /* Don't split the pool chunk between a LTREL_OFFSET load
6324 and the corresponding LTREL_BASE. */
6325 if (GET_CODE (constant) == CONST
6326 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6327 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6328 {
6329 gcc_assert (!pending_ltrel);
6330 pending_ltrel = pool_ref;
6331 }
6332 }
6333 }
6334
6335 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6336 {
6337 if (curr_pool)
6338 s390_add_pool_insn (curr_pool, insn);
6339 /* An LTREL_BASE must follow within the same basic block. */
6340 gcc_assert (!pending_ltrel);
6341 }
6342
6343 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6344 section_switch_p = true;
6345
6346 if (!curr_pool
6347 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6348 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6349 continue;
6350
6351 if (TARGET_CPU_ZARCH)
6352 {
6353 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6354 continue;
6355
6356 s390_end_pool (curr_pool, NULL_RTX);
6357 curr_pool = NULL;
6358 }
6359 else
6360 {
6361 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6362 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6363 + extra_size;
6364
6365 /* We will later have to insert base register reload insns.
6366 Those will have an effect on code size, which we need to
6367 consider here. This calculation makes rather pessimistic
6368 worst-case assumptions. */
6369 if (GET_CODE (insn) == CODE_LABEL)
6370 extra_size += 6;
6371
6372 if (chunk_size < S390_POOL_CHUNK_MIN
6373 && curr_pool->size < S390_POOL_CHUNK_MIN
6374 && !section_switch_p)
6375 continue;
6376
6377 /* Pool chunks can only be inserted after BARRIERs ... */
6378 if (GET_CODE (insn) == BARRIER)
6379 {
6380 s390_end_pool (curr_pool, insn);
6381 curr_pool = NULL;
6382 extra_size = 0;
6383 }
6384
6385 /* ... so if we don't find one in time, create one. */
6386 else if (chunk_size > S390_POOL_CHUNK_MAX
6387 || curr_pool->size > S390_POOL_CHUNK_MAX
6388 || section_switch_p)
6389 {
6390 rtx label, jump, barrier;
6391
6392 if (!section_switch_p)
6393 {
6394 /* We can insert the barrier only after a 'real' insn. */
6395 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6396 continue;
6397 if (get_attr_length (insn) == 0)
6398 continue;
6399 /* Don't separate LTREL_BASE from the corresponding
6400 LTREL_OFFSET load. */
6401 if (pending_ltrel)
6402 continue;
6403 }
6404 else
6405 {
6406 gcc_assert (!pending_ltrel);
6407
6408 /* The old pool has to end before the section switch
6409 note in order to make it part of the current
6410 section. */
6411 insn = PREV_INSN (insn);
6412 }
6413
6414 label = gen_label_rtx ();
6415 jump = emit_jump_insn_after (gen_jump (label), insn);
6416 barrier = emit_barrier_after (jump);
6417 insn = emit_label_after (label, barrier);
6418 JUMP_LABEL (jump) = label;
6419 LABEL_NUSES (label) = 1;
6420
6421 INSN_ADDRESSES_NEW (jump, -1);
6422 INSN_ADDRESSES_NEW (barrier, -1);
6423 INSN_ADDRESSES_NEW (insn, -1);
6424
6425 s390_end_pool (curr_pool, barrier);
6426 curr_pool = NULL;
6427 extra_size = 0;
6428 }
6429 }
6430 }
6431
6432 if (curr_pool)
6433 s390_end_pool (curr_pool, NULL_RTX);
6434 gcc_assert (!pending_ltrel);
6435
6436 /* Find all labels that are branched into
6437 from an insn belonging to a different chunk. */
6438
6439 far_labels = BITMAP_ALLOC (NULL);
6440
6441 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6442 {
6443 /* Labels marked with LABEL_PRESERVE_P can be target
6444 of non-local jumps, so we have to mark them.
6445 The same holds for named labels.
6446
6447 Don't do that, however, if it is the label before
6448 a jump table. */
6449
6450 if (GET_CODE (insn) == CODE_LABEL
6451 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6452 {
6453 rtx vec_insn = next_real_insn (insn);
6454 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6455 PATTERN (vec_insn) : NULL_RTX;
6456 if (!vec_pat
6457 || !(GET_CODE (vec_pat) == ADDR_VEC
6458 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6459 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6460 }
6461
6462 /* If we have a direct jump (conditional or unconditional)
6463 or a casesi jump, check all potential targets. */
6464 else if (GET_CODE (insn) == JUMP_INSN)
6465 {
6466 rtx pat = PATTERN (insn);
6467 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6468 pat = XVECEXP (pat, 0, 0);
6469
6470 if (GET_CODE (pat) == SET)
6471 {
6472 rtx label = JUMP_LABEL (insn);
6473 if (label)
6474 {
6475 if (s390_find_pool (pool_list, label)
6476 != s390_find_pool (pool_list, insn))
6477 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6478 }
6479 }
6480 else if (GET_CODE (pat) == PARALLEL
6481 && XVECLEN (pat, 0) == 2
6482 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6483 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6484 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6485 {
6486 /* Find the jump table used by this casesi jump. */
6487 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6488 rtx vec_insn = next_real_insn (vec_label);
6489 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6490 PATTERN (vec_insn) : NULL_RTX;
6491 if (vec_pat
6492 && (GET_CODE (vec_pat) == ADDR_VEC
6493 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6494 {
6495 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6496
6497 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6498 {
6499 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6500
6501 if (s390_find_pool (pool_list, label)
6502 != s390_find_pool (pool_list, insn))
6503 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6504 }
6505 }
6506 }
6507 }
6508 }
6509
6510 /* Insert base register reload insns before every pool. */
6511
6512 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6513 {
6514 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6515 curr_pool->label);
6516 rtx insn = curr_pool->first_insn;
6517 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6518 }
6519
6520 /* Insert base register reload insns at every far label. */
6521
6522 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6523 if (GET_CODE (insn) == CODE_LABEL
6524 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6525 {
6526 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6527 if (pool)
6528 {
6529 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6530 pool->label);
6531 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6532 }
6533 }
6534
6535
6536 BITMAP_FREE (far_labels);
6537
6538
6539 /* Recompute insn addresses. */
6540
6541 init_insn_lengths ();
6542 shorten_branches (get_insns ());
6543
6544 return pool_list;
6545 }
6546
6547 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6548 After we have decided to use this list, finish implementing
6549 all changes to the current function as required. */
6550
6551 static void
6552 s390_chunkify_finish (struct constant_pool *pool_list)
6553 {
6554 struct constant_pool *curr_pool = NULL;
6555 rtx insn;
6556
6557
6558 /* Replace all literal pool references. */
6559
6560 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6561 {
6562 if (INSN_P (insn))
6563 replace_ltrel_base (&PATTERN (insn));
6564
6565 curr_pool = s390_find_pool (pool_list, insn);
6566 if (!curr_pool)
6567 continue;
6568
6569 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6570 {
6571 rtx addr, pool_ref = NULL_RTX;
6572 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6573 if (pool_ref)
6574 {
6575 if (s390_execute_label (insn))
6576 addr = s390_find_execute (curr_pool, insn);
6577 else
6578 addr = s390_find_constant (curr_pool,
6579 get_pool_constant (pool_ref),
6580 get_pool_mode (pool_ref));
6581
6582 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6583 INSN_CODE (insn) = -1;
6584 }
6585 }
6586 }
6587
6588 /* Dump out all literal pools. */
6589
6590 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6591 s390_dump_pool (curr_pool, 0);
6592
6593 /* Free pool list. */
6594
6595 while (pool_list)
6596 {
6597 struct constant_pool *next = pool_list->next;
6598 s390_free_pool (pool_list);
6599 pool_list = next;
6600 }
6601 }
6602
6603 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6604 We have decided we cannot use this list, so revert all changes
6605 to the current function that were done by s390_chunkify_start. */
6606
6607 static void
6608 s390_chunkify_cancel (struct constant_pool *pool_list)
6609 {
6610 struct constant_pool *curr_pool = NULL;
6611 rtx insn;
6612
6613 /* Remove all pool placeholder insns. */
6614
6615 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6616 {
6617 /* Did we insert an extra barrier? Remove it. */
6618 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6619 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6620 rtx label = NEXT_INSN (curr_pool->pool_insn);
6621
6622 if (jump && GET_CODE (jump) == JUMP_INSN
6623 && barrier && GET_CODE (barrier) == BARRIER
6624 && label && GET_CODE (label) == CODE_LABEL
6625 && GET_CODE (PATTERN (jump)) == SET
6626 && SET_DEST (PATTERN (jump)) == pc_rtx
6627 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6628 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6629 {
6630 remove_insn (jump);
6631 remove_insn (barrier);
6632 remove_insn (label);
6633 }
6634
6635 remove_insn (curr_pool->pool_insn);
6636 }
6637
6638 /* Remove all base register reload insns. */
6639
6640 for (insn = get_insns (); insn; )
6641 {
6642 rtx next_insn = NEXT_INSN (insn);
6643
6644 if (GET_CODE (insn) == INSN
6645 && GET_CODE (PATTERN (insn)) == SET
6646 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6647 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6648 remove_insn (insn);
6649
6650 insn = next_insn;
6651 }
6652
6653 /* Free pool list. */
6654
6655 while (pool_list)
6656 {
6657 struct constant_pool *next = pool_list->next;
6658 s390_free_pool (pool_list);
6659 pool_list = next;
6660 }
6661 }
6662
6663 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6664
6665 void
6666 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6667 {
6668 REAL_VALUE_TYPE r;
6669
6670 switch (GET_MODE_CLASS (mode))
6671 {
6672 case MODE_FLOAT:
6673 case MODE_DECIMAL_FLOAT:
6674 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6675
6676 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6677 assemble_real (r, mode, align);
6678 break;
6679
6680 case MODE_INT:
6681 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6682 mark_symbol_refs_as_used (exp);
6683 break;
6684
6685 default:
6686 gcc_unreachable ();
6687 }
6688 }
6689
6690
6691 /* Return an RTL expression representing the value of the return address
6692 for the frame COUNT steps up from the current frame. FRAME is the
6693 frame pointer of that frame. */
6694
6695 rtx
6696 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6697 {
6698 int offset;
6699 rtx addr;
6700
6701 /* Without backchain, we fail for all but the current frame. */
6702
6703 if (!TARGET_BACKCHAIN && count > 0)
6704 return NULL_RTX;
6705
6706 /* For the current frame, we need to make sure the initial
6707 value of RETURN_REGNUM is actually saved. */
6708
6709 if (count == 0)
6710 {
6711 /* On non-z architectures branch splitting could overwrite r14. */
6712 if (TARGET_CPU_ZARCH)
6713 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6714 else
6715 {
6716 cfun_frame_layout.save_return_addr_p = true;
6717 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6718 }
6719 }
6720
6721 if (TARGET_PACKED_STACK)
6722 offset = -2 * UNITS_PER_WORD;
6723 else
6724 offset = RETURN_REGNUM * UNITS_PER_WORD;
6725
6726 addr = plus_constant (frame, offset);
6727 addr = memory_address (Pmode, addr);
6728 return gen_rtx_MEM (Pmode, addr);
6729 }
6730
6731 /* Return an RTL expression representing the back chain stored in
6732 the current stack frame. */
6733
6734 rtx
6735 s390_back_chain_rtx (void)
6736 {
6737 rtx chain;
6738
6739 gcc_assert (TARGET_BACKCHAIN);
6740
6741 if (TARGET_PACKED_STACK)
6742 chain = plus_constant (stack_pointer_rtx,
6743 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6744 else
6745 chain = stack_pointer_rtx;
6746
6747 chain = gen_rtx_MEM (Pmode, chain);
6748 return chain;
6749 }
6750
6751 /* Find first call clobbered register unused in a function.
6752 This could be used as base register in a leaf function
6753 or for holding the return address before epilogue. */
6754
6755 static int
6756 find_unused_clobbered_reg (void)
6757 {
6758 int i;
6759 for (i = 0; i < 6; i++)
6760 if (!df_regs_ever_live_p (i))
6761 return i;
6762 return 0;
6763 }
6764
6765
6766 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6767 clobbered hard regs in SETREG. */
6768
6769 static void
6770 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6771 {
6772 int *regs_ever_clobbered = (int *)data;
6773 unsigned int i, regno;
6774 enum machine_mode mode = GET_MODE (setreg);
6775
6776 if (GET_CODE (setreg) == SUBREG)
6777 {
6778 rtx inner = SUBREG_REG (setreg);
6779 if (!GENERAL_REG_P (inner))
6780 return;
6781 regno = subreg_regno (setreg);
6782 }
6783 else if (GENERAL_REG_P (setreg))
6784 regno = REGNO (setreg);
6785 else
6786 return;
6787
6788 for (i = regno;
6789 i < regno + HARD_REGNO_NREGS (regno, mode);
6790 i++)
6791 regs_ever_clobbered[i] = 1;
6792 }
6793
6794 /* Walks through all basic blocks of the current function looking
6795 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6796 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6797 each of those regs. */
6798
6799 static void
6800 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6801 {
6802 basic_block cur_bb;
6803 rtx cur_insn;
6804 unsigned int i;
6805
6806 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6807
6808 /* For non-leaf functions we have to consider all call clobbered regs to be
6809 clobbered. */
6810 if (!current_function_is_leaf)
6811 {
6812 for (i = 0; i < 16; i++)
6813 regs_ever_clobbered[i] = call_really_used_regs[i];
6814 }
6815
6816 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6817 this work is done by liveness analysis (mark_regs_live_at_end).
6818 Special care is needed for functions containing landing pads. Landing pads
6819 may use the eh registers, but the code which sets these registers is not
6820 contained in that function. Hence s390_regs_ever_clobbered is not able to
6821 deal with this automatically. */
6822 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6823 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6824 if (crtl->calls_eh_return
6825 || (cfun->machine->has_landing_pad_p
6826 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6827 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6828
6829 /* For nonlocal gotos all call-saved registers have to be saved.
6830 This flag is also set for the unwinding code in libgcc.
6831 See expand_builtin_unwind_init. For regs_ever_live this is done by
6832 reload. */
6833 if (cfun->has_nonlocal_label)
6834 for (i = 0; i < 16; i++)
6835 if (!call_really_used_regs[i])
6836 regs_ever_clobbered[i] = 1;
6837
6838 FOR_EACH_BB (cur_bb)
6839 {
6840 FOR_BB_INSNS (cur_bb, cur_insn)
6841 {
6842 if (INSN_P (cur_insn))
6843 note_stores (PATTERN (cur_insn),
6844 s390_reg_clobbered_rtx,
6845 regs_ever_clobbered);
6846 }
6847 }
6848 }
6849
6850 /* Determine the frame area which actually has to be accessed
6851 in the function epilogue. The values are stored at the
6852 given pointers AREA_BOTTOM (address of the lowest used stack
6853 address) and AREA_TOP (address of the first item which does
6854 not belong to the stack frame). */
6855
6856 static void
6857 s390_frame_area (int *area_bottom, int *area_top)
6858 {
6859 int b, t;
6860 int i;
6861
6862 b = INT_MAX;
6863 t = INT_MIN;
6864
6865 if (cfun_frame_layout.first_restore_gpr != -1)
6866 {
6867 b = (cfun_frame_layout.gprs_offset
6868 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6869 t = b + (cfun_frame_layout.last_restore_gpr
6870 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6871 }
6872
6873 if (TARGET_64BIT && cfun_save_high_fprs_p)
6874 {
6875 b = MIN (b, cfun_frame_layout.f8_offset);
6876 t = MAX (t, (cfun_frame_layout.f8_offset
6877 + cfun_frame_layout.high_fprs * 8));
6878 }
6879
6880 if (!TARGET_64BIT)
6881 for (i = 2; i < 4; i++)
6882 if (cfun_fpr_bit_p (i))
6883 {
6884 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6885 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6886 }
6887
6888 *area_bottom = b;
6889 *area_top = t;
6890 }
6891
6892 /* Fill cfun->machine with info about register usage of current function.
6893 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6894
6895 static void
6896 s390_register_info (int clobbered_regs[])
6897 {
6898 int i, j;
6899
6900 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6901 cfun_frame_layout.fpr_bitmap = 0;
6902 cfun_frame_layout.high_fprs = 0;
6903 if (TARGET_64BIT)
6904 for (i = 24; i < 32; i++)
6905 if (df_regs_ever_live_p (i) && !global_regs[i])
6906 {
6907 cfun_set_fpr_bit (i - 16);
6908 cfun_frame_layout.high_fprs++;
6909 }
6910
6911 /* Find first and last gpr to be saved. We trust regs_ever_live
6912 data, except that we don't save and restore global registers.
6913
6914 Also, all registers with special meaning to the compiler need
6915 to be handled extra. */
6916
6917 s390_regs_ever_clobbered (clobbered_regs);
6918
6919 for (i = 0; i < 16; i++)
6920 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6921
6922 if (frame_pointer_needed)
6923 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6924
6925 if (flag_pic)
6926 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6927 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6928
6929 clobbered_regs[BASE_REGNUM]
6930 |= (cfun->machine->base_reg
6931 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6932
6933 clobbered_regs[RETURN_REGNUM]
6934 |= (!current_function_is_leaf
6935 || TARGET_TPF_PROFILING
6936 || cfun->machine->split_branches_pending_p
6937 || cfun_frame_layout.save_return_addr_p
6938 || crtl->calls_eh_return
6939 || cfun->stdarg);
6940
6941 clobbered_regs[STACK_POINTER_REGNUM]
6942 |= (!current_function_is_leaf
6943 || TARGET_TPF_PROFILING
6944 || cfun_save_high_fprs_p
6945 || get_frame_size () > 0
6946 || cfun->calls_alloca
6947 || cfun->stdarg);
6948
6949 for (i = 6; i < 16; i++)
6950 if (df_regs_ever_live_p (i) || clobbered_regs[i])
6951 break;
6952 for (j = 15; j > i; j--)
6953 if (df_regs_ever_live_p (j) || clobbered_regs[j])
6954 break;
6955
6956 if (i == 16)
6957 {
6958 /* Nothing to save/restore. */
6959 cfun_frame_layout.first_save_gpr_slot = -1;
6960 cfun_frame_layout.last_save_gpr_slot = -1;
6961 cfun_frame_layout.first_save_gpr = -1;
6962 cfun_frame_layout.first_restore_gpr = -1;
6963 cfun_frame_layout.last_save_gpr = -1;
6964 cfun_frame_layout.last_restore_gpr = -1;
6965 }
6966 else
6967 {
6968 /* Save slots for gprs from i to j. */
6969 cfun_frame_layout.first_save_gpr_slot = i;
6970 cfun_frame_layout.last_save_gpr_slot = j;
6971
6972 for (i = cfun_frame_layout.first_save_gpr_slot;
6973 i < cfun_frame_layout.last_save_gpr_slot + 1;
6974 i++)
6975 if (clobbered_regs[i])
6976 break;
6977
6978 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6979 if (clobbered_regs[j])
6980 break;
6981
6982 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6983 {
6984 /* Nothing to save/restore. */
6985 cfun_frame_layout.first_save_gpr = -1;
6986 cfun_frame_layout.first_restore_gpr = -1;
6987 cfun_frame_layout.last_save_gpr = -1;
6988 cfun_frame_layout.last_restore_gpr = -1;
6989 }
6990 else
6991 {
6992 /* Save / Restore from gpr i to j. */
6993 cfun_frame_layout.first_save_gpr = i;
6994 cfun_frame_layout.first_restore_gpr = i;
6995 cfun_frame_layout.last_save_gpr = j;
6996 cfun_frame_layout.last_restore_gpr = j;
6997 }
6998 }
6999
7000 if (cfun->stdarg)
7001 {
7002 /* Varargs functions need to save gprs 2 to 6. */
7003 if (cfun->va_list_gpr_size
7004 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7005 {
7006 int min_gpr = crtl->args.info.gprs;
7007 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7008 if (max_gpr > GP_ARG_NUM_REG)
7009 max_gpr = GP_ARG_NUM_REG;
7010
7011 if (cfun_frame_layout.first_save_gpr == -1
7012 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7013 {
7014 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7015 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7016 }
7017
7018 if (cfun_frame_layout.last_save_gpr == -1
7019 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7020 {
7021 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7022 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7023 }
7024 }
7025
7026 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7027 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7028 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7029 {
7030 int min_fpr = crtl->args.info.fprs;
7031 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7032 if (max_fpr > FP_ARG_NUM_REG)
7033 max_fpr = FP_ARG_NUM_REG;
7034
7035 /* ??? This is currently required to ensure proper location
7036 of the fpr save slots within the va_list save area. */
7037 if (TARGET_PACKED_STACK)
7038 min_fpr = 0;
7039
7040 for (i = min_fpr; i < max_fpr; i++)
7041 cfun_set_fpr_bit (i);
7042 }
7043 }
7044
7045 if (!TARGET_64BIT)
7046 for (i = 2; i < 4; i++)
7047 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7048 cfun_set_fpr_bit (i);
7049 }
7050
7051 /* Fill cfun->machine with info about frame of current function. */
7052
7053 static void
7054 s390_frame_info (void)
7055 {
7056 int i;
7057
7058 cfun_frame_layout.frame_size = get_frame_size ();
7059 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7060 fatal_error ("total size of local variables exceeds architecture limit");
7061
7062 if (!TARGET_PACKED_STACK)
7063 {
7064 cfun_frame_layout.backchain_offset = 0;
7065 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
7066 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7067 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7068 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7069 * UNITS_PER_WORD);
7070 }
7071 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7072 {
7073 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7074 - UNITS_PER_WORD);
7075 cfun_frame_layout.gprs_offset
7076 = (cfun_frame_layout.backchain_offset
7077 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7078 * UNITS_PER_WORD);
7079
7080 if (TARGET_64BIT)
7081 {
7082 cfun_frame_layout.f4_offset
7083 = (cfun_frame_layout.gprs_offset
7084 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7085
7086 cfun_frame_layout.f0_offset
7087 = (cfun_frame_layout.f4_offset
7088 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7089 }
7090 else
7091 {
7092 /* On 31 bit we have to care about alignment of the
7093 floating point regs to provide fastest access. */
7094 cfun_frame_layout.f0_offset
7095 = ((cfun_frame_layout.gprs_offset
7096 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7097 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7098
7099 cfun_frame_layout.f4_offset
7100 = (cfun_frame_layout.f0_offset
7101 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7102 }
7103 }
7104 else /* no backchain */
7105 {
7106 cfun_frame_layout.f4_offset
7107 = (STACK_POINTER_OFFSET
7108 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7109
7110 cfun_frame_layout.f0_offset
7111 = (cfun_frame_layout.f4_offset
7112 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7113
7114 cfun_frame_layout.gprs_offset
7115 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7116 }
7117
7118 if (current_function_is_leaf
7119 && !TARGET_TPF_PROFILING
7120 && cfun_frame_layout.frame_size == 0
7121 && !cfun_save_high_fprs_p
7122 && !cfun->calls_alloca
7123 && !cfun->stdarg)
7124 return;
7125
7126 if (!TARGET_PACKED_STACK)
7127 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7128 + crtl->outgoing_args_size
7129 + cfun_frame_layout.high_fprs * 8);
7130 else
7131 {
7132 if (TARGET_BACKCHAIN)
7133 cfun_frame_layout.frame_size += UNITS_PER_WORD;
7134
7135 /* No alignment trouble here because f8-f15 are only saved under
7136 64 bit. */
7137 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7138 cfun_frame_layout.f4_offset),
7139 cfun_frame_layout.gprs_offset)
7140 - cfun_frame_layout.high_fprs * 8);
7141
7142 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7143
7144 for (i = 0; i < 8; i++)
7145 if (cfun_fpr_bit_p (i))
7146 cfun_frame_layout.frame_size += 8;
7147
7148 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7149
7150 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7151 the frame size to sustain 8 byte alignment of stack frames. */
7152 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7153 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7154 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7155
7156 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7157 }
7158 }
7159
7160 /* Generate frame layout. Fills in register and frame data for the current
7161 function in cfun->machine. This routine can be called multiple times;
7162 it will re-do the complete frame layout every time. */
7163
7164 static void
7165 s390_init_frame_layout (void)
7166 {
7167 HOST_WIDE_INT frame_size;
7168 int base_used;
7169 int clobbered_regs[16];
7170
7171 /* On S/390 machines, we may need to perform branch splitting, which
7172 will require both base and return address register. We have no
7173 choice but to assume we're going to need them until right at the
7174 end of the machine dependent reorg phase. */
7175 if (!TARGET_CPU_ZARCH)
7176 cfun->machine->split_branches_pending_p = true;
7177
7178 do
7179 {
7180 frame_size = cfun_frame_layout.frame_size;
7181
7182 /* Try to predict whether we'll need the base register. */
7183 base_used = cfun->machine->split_branches_pending_p
7184 || crtl->uses_const_pool
7185 || (!DISP_IN_RANGE (frame_size)
7186 && !CONST_OK_FOR_K (frame_size));
7187
7188 /* Decide which register to use as literal pool base. In small
7189 leaf functions, try to use an unused call-clobbered register
7190 as base register to avoid save/restore overhead. */
7191 if (!base_used)
7192 cfun->machine->base_reg = NULL_RTX;
7193 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7194 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7195 else
7196 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7197
7198 s390_register_info (clobbered_regs);
7199 s390_frame_info ();
7200 }
7201 while (frame_size != cfun_frame_layout.frame_size);
7202 }
7203
7204 /* Update frame layout. Recompute actual register save data based on
7205 current info and update regs_ever_live for the special registers.
7206 May be called multiple times, but may never cause *more* registers
7207 to be saved than s390_init_frame_layout allocated room for. */
7208
7209 static void
7210 s390_update_frame_layout (void)
7211 {
7212 int clobbered_regs[16];
7213
7214 s390_register_info (clobbered_regs);
7215
7216 df_set_regs_ever_live (BASE_REGNUM,
7217 clobbered_regs[BASE_REGNUM] ? true : false);
7218 df_set_regs_ever_live (RETURN_REGNUM,
7219 clobbered_regs[RETURN_REGNUM] ? true : false);
7220 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7221 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7222
7223 if (cfun->machine->base_reg)
7224 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7225 }
7226
7227 /* Return true if it is legal to put a value with MODE into REGNO. */
7228
7229 bool
7230 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7231 {
7232 switch (REGNO_REG_CLASS (regno))
7233 {
7234 case FP_REGS:
7235 if (REGNO_PAIR_OK (regno, mode))
7236 {
7237 if (mode == SImode || mode == DImode)
7238 return true;
7239
7240 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7241 return true;
7242 }
7243 break;
7244 case ADDR_REGS:
7245 if (FRAME_REGNO_P (regno) && mode == Pmode)
7246 return true;
7247
7248 /* fallthrough */
7249 case GENERAL_REGS:
7250 if (REGNO_PAIR_OK (regno, mode))
7251 {
7252 if (TARGET_64BIT
7253 || (mode != TFmode && mode != TCmode && mode != TDmode))
7254 return true;
7255 }
7256 break;
7257 case CC_REGS:
7258 if (GET_MODE_CLASS (mode) == MODE_CC)
7259 return true;
7260 break;
7261 case ACCESS_REGS:
7262 if (REGNO_PAIR_OK (regno, mode))
7263 {
7264 if (mode == SImode || mode == Pmode)
7265 return true;
7266 }
7267 break;
7268 default:
7269 return false;
7270 }
7271
7272 return false;
7273 }
7274
7275 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7276
7277 bool
7278 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7279 {
7280 /* Once we've decided upon a register to use as base register, it must
7281 no longer be used for any other purpose. */
7282 if (cfun->machine->base_reg)
7283 if (REGNO (cfun->machine->base_reg) == old_reg
7284 || REGNO (cfun->machine->base_reg) == new_reg)
7285 return false;
7286
7287 return true;
7288 }
7289
7290 /* Maximum number of registers to represent a value of mode MODE
7291 in a register of class RCLASS. */
7292
7293 bool
7294 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7295 {
7296 switch (rclass)
7297 {
7298 case FP_REGS:
7299 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7300 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7301 else
7302 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7303 case ACCESS_REGS:
7304 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7305 default:
7306 break;
7307 }
7308 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7309 }
7310
7311 /* Return true if register FROM can be eliminated via register TO. */
7312
7313 bool
7314 s390_can_eliminate (int from, int to)
7315 {
7316 /* On zSeries machines, we have not marked the base register as fixed.
7317 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7318 If a function requires the base register, we say here that this
7319 elimination cannot be performed. This will cause reload to free
7320 up the base register (as if it were fixed). On the other hand,
7321 if the current function does *not* require the base register, we
7322 say here the elimination succeeds, which in turn allows reload
7323 to allocate the base register for any other purpose. */
7324 if (from == BASE_REGNUM && to == BASE_REGNUM)
7325 {
7326 if (TARGET_CPU_ZARCH)
7327 {
7328 s390_init_frame_layout ();
7329 return cfun->machine->base_reg == NULL_RTX;
7330 }
7331
7332 return false;
7333 }
7334
7335 /* Everything else must point into the stack frame. */
7336 gcc_assert (to == STACK_POINTER_REGNUM
7337 || to == HARD_FRAME_POINTER_REGNUM);
7338
7339 gcc_assert (from == FRAME_POINTER_REGNUM
7340 || from == ARG_POINTER_REGNUM
7341 || from == RETURN_ADDRESS_POINTER_REGNUM);
7342
7343 /* Make sure we actually saved the return address. */
7344 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7345 if (!crtl->calls_eh_return
7346 && !cfun->stdarg
7347 && !cfun_frame_layout.save_return_addr_p)
7348 return false;
7349
7350 return true;
7351 }
7352
7353 /* Return offset between register FROM and TO initially after prolog. */
7354
7355 HOST_WIDE_INT
7356 s390_initial_elimination_offset (int from, int to)
7357 {
7358 HOST_WIDE_INT offset;
7359 int index;
7360
7361 /* ??? Why are we called for non-eliminable pairs? */
7362 if (!s390_can_eliminate (from, to))
7363 return 0;
7364
7365 switch (from)
7366 {
7367 case FRAME_POINTER_REGNUM:
7368 offset = (get_frame_size()
7369 + STACK_POINTER_OFFSET
7370 + crtl->outgoing_args_size);
7371 break;
7372
7373 case ARG_POINTER_REGNUM:
7374 s390_init_frame_layout ();
7375 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7376 break;
7377
7378 case RETURN_ADDRESS_POINTER_REGNUM:
7379 s390_init_frame_layout ();
7380 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7381 gcc_assert (index >= 0);
7382 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7383 offset += index * UNITS_PER_WORD;
7384 break;
7385
7386 case BASE_REGNUM:
7387 offset = 0;
7388 break;
7389
7390 default:
7391 gcc_unreachable ();
7392 }
7393
7394 return offset;
7395 }
7396
7397 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7398 to register BASE. Return generated insn. */
7399
7400 static rtx
7401 save_fpr (rtx base, int offset, int regnum)
7402 {
7403 rtx addr;
7404 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7405
7406 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7407 set_mem_alias_set (addr, get_varargs_alias_set ());
7408 else
7409 set_mem_alias_set (addr, get_frame_alias_set ());
7410
7411 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7412 }
7413
7414 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7415 to register BASE. Return generated insn. */
7416
7417 static rtx
7418 restore_fpr (rtx base, int offset, int regnum)
7419 {
7420 rtx addr;
7421 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7422 set_mem_alias_set (addr, get_frame_alias_set ());
7423
7424 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7425 }
7426
7427 /* Generate insn to save registers FIRST to LAST into
7428 the register save area located at offset OFFSET
7429 relative to register BASE. */
7430
7431 static rtx
7432 save_gprs (rtx base, int offset, int first, int last)
7433 {
7434 rtx addr, insn, note;
7435 int i;
7436
7437 addr = plus_constant (base, offset);
7438 addr = gen_rtx_MEM (Pmode, addr);
7439
7440 set_mem_alias_set (addr, get_frame_alias_set ());
7441
7442 /* Special-case single register. */
7443 if (first == last)
7444 {
7445 if (TARGET_64BIT)
7446 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7447 else
7448 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7449
7450 RTX_FRAME_RELATED_P (insn) = 1;
7451 return insn;
7452 }
7453
7454
7455 insn = gen_store_multiple (addr,
7456 gen_rtx_REG (Pmode, first),
7457 GEN_INT (last - first + 1));
7458
7459 if (first <= 6 && cfun->stdarg)
7460 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7461 {
7462 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7463
7464 if (first + i <= 6)
7465 set_mem_alias_set (mem, get_varargs_alias_set ());
7466 }
7467
7468 /* We need to set the FRAME_RELATED flag on all SETs
7469 inside the store-multiple pattern.
7470
7471 However, we must not emit DWARF records for registers 2..5
7472 if they are stored for use by variable arguments ...
7473
7474 ??? Unfortunately, it is not enough to simply not the
7475 FRAME_RELATED flags for those SETs, because the first SET
7476 of the PARALLEL is always treated as if it had the flag
7477 set, even if it does not. Therefore we emit a new pattern
7478 without those registers as REG_FRAME_RELATED_EXPR note. */
7479
7480 if (first >= 6)
7481 {
7482 rtx pat = PATTERN (insn);
7483
7484 for (i = 0; i < XVECLEN (pat, 0); i++)
7485 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
7486 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7487
7488 RTX_FRAME_RELATED_P (insn) = 1;
7489 }
7490 else if (last >= 6)
7491 {
7492 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
7493 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7494 gen_rtx_REG (Pmode, 6),
7495 GEN_INT (last - 6 + 1));
7496 note = PATTERN (note);
7497
7498 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7499
7500 for (i = 0; i < XVECLEN (note, 0); i++)
7501 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
7502 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7503
7504 RTX_FRAME_RELATED_P (insn) = 1;
7505 }
7506
7507 return insn;
7508 }
7509
7510 /* Generate insn to restore registers FIRST to LAST from
7511 the register save area located at offset OFFSET
7512 relative to register BASE. */
7513
7514 static rtx
7515 restore_gprs (rtx base, int offset, int first, int last)
7516 {
7517 rtx addr, insn;
7518
7519 addr = plus_constant (base, offset);
7520 addr = gen_rtx_MEM (Pmode, addr);
7521 set_mem_alias_set (addr, get_frame_alias_set ());
7522
7523 /* Special-case single register. */
7524 if (first == last)
7525 {
7526 if (TARGET_64BIT)
7527 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7528 else
7529 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7530
7531 return insn;
7532 }
7533
7534 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7535 addr,
7536 GEN_INT (last - first + 1));
7537 return insn;
7538 }
7539
7540 /* Return insn sequence to load the GOT register. */
7541
7542 static GTY(()) rtx got_symbol;
7543 rtx
7544 s390_load_got (void)
7545 {
7546 rtx insns;
7547
7548 if (!got_symbol)
7549 {
7550 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7551 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7552 }
7553
7554 start_sequence ();
7555
7556 if (TARGET_CPU_ZARCH)
7557 {
7558 emit_move_insn (pic_offset_table_rtx, got_symbol);
7559 }
7560 else
7561 {
7562 rtx offset;
7563
7564 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7565 UNSPEC_LTREL_OFFSET);
7566 offset = gen_rtx_CONST (Pmode, offset);
7567 offset = force_const_mem (Pmode, offset);
7568
7569 emit_move_insn (pic_offset_table_rtx, offset);
7570
7571 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7572 UNSPEC_LTREL_BASE);
7573 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7574
7575 emit_move_insn (pic_offset_table_rtx, offset);
7576 }
7577
7578 insns = get_insns ();
7579 end_sequence ();
7580 return insns;
7581 }
7582
7583 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7584 and the change to the stack pointer. */
7585
7586 static void
7587 s390_emit_stack_tie (void)
7588 {
7589 rtx mem = gen_frame_mem (BLKmode,
7590 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7591
7592 emit_insn (gen_stack_tie (mem));
7593 }
7594
7595 /* Expand the prologue into a bunch of separate insns. */
7596
7597 void
7598 s390_emit_prologue (void)
7599 {
7600 rtx insn, addr;
7601 rtx temp_reg;
7602 int i;
7603 int offset;
7604 int next_fpr = 0;
7605
7606 /* Complete frame layout. */
7607
7608 s390_update_frame_layout ();
7609
7610 /* Annotate all constant pool references to let the scheduler know
7611 they implicitly use the base register. */
7612
7613 push_topmost_sequence ();
7614
7615 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7616 if (INSN_P (insn))
7617 {
7618 annotate_constant_pool_refs (&PATTERN (insn));
7619 df_insn_rescan (insn);
7620 }
7621
7622 pop_topmost_sequence ();
7623
7624 /* Choose best register to use for temp use within prologue.
7625 See below for why TPF must use the register 1. */
7626
7627 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7628 && !current_function_is_leaf
7629 && !TARGET_TPF_PROFILING)
7630 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7631 else
7632 temp_reg = gen_rtx_REG (Pmode, 1);
7633
7634 /* Save call saved gprs. */
7635 if (cfun_frame_layout.first_save_gpr != -1)
7636 {
7637 insn = save_gprs (stack_pointer_rtx,
7638 cfun_frame_layout.gprs_offset +
7639 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7640 - cfun_frame_layout.first_save_gpr_slot),
7641 cfun_frame_layout.first_save_gpr,
7642 cfun_frame_layout.last_save_gpr);
7643 emit_insn (insn);
7644 }
7645
7646 /* Dummy insn to mark literal pool slot. */
7647
7648 if (cfun->machine->base_reg)
7649 emit_insn (gen_main_pool (cfun->machine->base_reg));
7650
7651 offset = cfun_frame_layout.f0_offset;
7652
7653 /* Save f0 and f2. */
7654 for (i = 0; i < 2; i++)
7655 {
7656 if (cfun_fpr_bit_p (i))
7657 {
7658 save_fpr (stack_pointer_rtx, offset, i + 16);
7659 offset += 8;
7660 }
7661 else if (!TARGET_PACKED_STACK)
7662 offset += 8;
7663 }
7664
7665 /* Save f4 and f6. */
7666 offset = cfun_frame_layout.f4_offset;
7667 for (i = 2; i < 4; i++)
7668 {
7669 if (cfun_fpr_bit_p (i))
7670 {
7671 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7672 offset += 8;
7673
7674 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7675 therefore are not frame related. */
7676 if (!call_really_used_regs[i + 16])
7677 RTX_FRAME_RELATED_P (insn) = 1;
7678 }
7679 else if (!TARGET_PACKED_STACK)
7680 offset += 8;
7681 }
7682
7683 if (TARGET_PACKED_STACK
7684 && cfun_save_high_fprs_p
7685 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7686 {
7687 offset = (cfun_frame_layout.f8_offset
7688 + (cfun_frame_layout.high_fprs - 1) * 8);
7689
7690 for (i = 15; i > 7 && offset >= 0; i--)
7691 if (cfun_fpr_bit_p (i))
7692 {
7693 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7694
7695 RTX_FRAME_RELATED_P (insn) = 1;
7696 offset -= 8;
7697 }
7698 if (offset >= cfun_frame_layout.f8_offset)
7699 next_fpr = i + 16;
7700 }
7701
7702 if (!TARGET_PACKED_STACK)
7703 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7704
7705 /* Decrement stack pointer. */
7706
7707 if (cfun_frame_layout.frame_size > 0)
7708 {
7709 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7710 rtx real_frame_off;
7711
7712 if (s390_stack_size)
7713 {
7714 HOST_WIDE_INT stack_guard;
7715
7716 if (s390_stack_guard)
7717 stack_guard = s390_stack_guard;
7718 else
7719 {
7720 /* If no value for stack guard is provided the smallest power of 2
7721 larger than the current frame size is chosen. */
7722 stack_guard = 1;
7723 while (stack_guard < cfun_frame_layout.frame_size)
7724 stack_guard <<= 1;
7725 }
7726
7727 if (cfun_frame_layout.frame_size >= s390_stack_size)
7728 {
7729 warning (0, "frame size of function %qs is "
7730 HOST_WIDE_INT_PRINT_DEC
7731 " bytes exceeding user provided stack limit of "
7732 HOST_WIDE_INT_PRINT_DEC " bytes. "
7733 "An unconditional trap is added.",
7734 current_function_name(), cfun_frame_layout.frame_size,
7735 s390_stack_size);
7736 emit_insn (gen_trap ());
7737 }
7738 else
7739 {
7740 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7741 & ~(stack_guard - 1));
7742 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7743 GEN_INT (stack_check_mask));
7744 if (TARGET_64BIT)
7745 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7746 t, const0_rtx, const0_rtx));
7747 else
7748 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7749 t, const0_rtx, const0_rtx));
7750 }
7751 }
7752
7753 if (s390_warn_framesize > 0
7754 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7755 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7756 current_function_name (), cfun_frame_layout.frame_size);
7757
7758 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7759 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7760
7761 /* Save incoming stack pointer into temp reg. */
7762 if (TARGET_BACKCHAIN || next_fpr)
7763 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7764
7765 /* Subtract frame size from stack pointer. */
7766
7767 if (DISP_IN_RANGE (INTVAL (frame_off)))
7768 {
7769 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7770 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7771 frame_off));
7772 insn = emit_insn (insn);
7773 }
7774 else
7775 {
7776 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7777 frame_off = force_const_mem (Pmode, frame_off);
7778
7779 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7780 annotate_constant_pool_refs (&PATTERN (insn));
7781 }
7782
7783 RTX_FRAME_RELATED_P (insn) = 1;
7784 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7785 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7786 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7787 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7788 real_frame_off)));
7789
7790 /* Set backchain. */
7791
7792 if (TARGET_BACKCHAIN)
7793 {
7794 if (cfun_frame_layout.backchain_offset)
7795 addr = gen_rtx_MEM (Pmode,
7796 plus_constant (stack_pointer_rtx,
7797 cfun_frame_layout.backchain_offset));
7798 else
7799 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7800 set_mem_alias_set (addr, get_frame_alias_set ());
7801 insn = emit_insn (gen_move_insn (addr, temp_reg));
7802 }
7803
7804 /* If we support asynchronous exceptions (e.g. for Java),
7805 we need to make sure the backchain pointer is set up
7806 before any possibly trapping memory access. */
7807
7808 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7809 {
7810 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7811 emit_clobber (addr);
7812 }
7813 }
7814
7815 /* Save fprs 8 - 15 (64 bit ABI). */
7816
7817 if (cfun_save_high_fprs_p && next_fpr)
7818 {
7819 /* If the stack might be accessed through a different register
7820 we have to make sure that the stack pointer decrement is not
7821 moved below the use of the stack slots. */
7822 s390_emit_stack_tie ();
7823
7824 insn = emit_insn (gen_add2_insn (temp_reg,
7825 GEN_INT (cfun_frame_layout.f8_offset)));
7826
7827 offset = 0;
7828
7829 for (i = 24; i <= next_fpr; i++)
7830 if (cfun_fpr_bit_p (i - 16))
7831 {
7832 rtx addr = plus_constant (stack_pointer_rtx,
7833 cfun_frame_layout.frame_size
7834 + cfun_frame_layout.f8_offset
7835 + offset);
7836
7837 insn = save_fpr (temp_reg, offset, i);
7838 offset += 8;
7839 RTX_FRAME_RELATED_P (insn) = 1;
7840 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7841 gen_rtx_SET (VOIDmode,
7842 gen_rtx_MEM (DFmode, addr),
7843 gen_rtx_REG (DFmode, i)));
7844 }
7845 }
7846
7847 /* Set frame pointer, if needed. */
7848
7849 if (frame_pointer_needed)
7850 {
7851 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7852 RTX_FRAME_RELATED_P (insn) = 1;
7853 }
7854
7855 /* Set up got pointer, if needed. */
7856
7857 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7858 {
7859 rtx insns = s390_load_got ();
7860
7861 for (insn = insns; insn; insn = NEXT_INSN (insn))
7862 annotate_constant_pool_refs (&PATTERN (insn));
7863
7864 emit_insn (insns);
7865 }
7866
7867 if (TARGET_TPF_PROFILING)
7868 {
7869 /* Generate a BAS instruction to serve as a function
7870 entry intercept to facilitate the use of tracing
7871 algorithms located at the branch target. */
7872 emit_insn (gen_prologue_tpf ());
7873
7874 /* Emit a blockage here so that all code
7875 lies between the profiling mechanisms. */
7876 emit_insn (gen_blockage ());
7877 }
7878 }
7879
7880 /* Expand the epilogue into a bunch of separate insns. */
7881
7882 void
7883 s390_emit_epilogue (bool sibcall)
7884 {
7885 rtx frame_pointer, return_reg;
7886 int area_bottom, area_top, offset = 0;
7887 int next_offset;
7888 rtvec p;
7889 int i;
7890
7891 if (TARGET_TPF_PROFILING)
7892 {
7893
7894 /* Generate a BAS instruction to serve as a function
7895 entry intercept to facilitate the use of tracing
7896 algorithms located at the branch target. */
7897
7898 /* Emit a blockage here so that all code
7899 lies between the profiling mechanisms. */
7900 emit_insn (gen_blockage ());
7901
7902 emit_insn (gen_epilogue_tpf ());
7903 }
7904
7905 /* Check whether to use frame or stack pointer for restore. */
7906
7907 frame_pointer = (frame_pointer_needed
7908 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7909
7910 s390_frame_area (&area_bottom, &area_top);
7911
7912 /* Check whether we can access the register save area.
7913 If not, increment the frame pointer as required. */
7914
7915 if (area_top <= area_bottom)
7916 {
7917 /* Nothing to restore. */
7918 }
7919 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7920 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7921 {
7922 /* Area is in range. */
7923 offset = cfun_frame_layout.frame_size;
7924 }
7925 else
7926 {
7927 rtx insn, frame_off;
7928
7929 offset = area_bottom < 0 ? -area_bottom : 0;
7930 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7931
7932 if (DISP_IN_RANGE (INTVAL (frame_off)))
7933 {
7934 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7935 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7936 insn = emit_insn (insn);
7937 }
7938 else
7939 {
7940 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7941 frame_off = force_const_mem (Pmode, frame_off);
7942
7943 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7944 annotate_constant_pool_refs (&PATTERN (insn));
7945 }
7946 }
7947
7948 /* Restore call saved fprs. */
7949
7950 if (TARGET_64BIT)
7951 {
7952 if (cfun_save_high_fprs_p)
7953 {
7954 next_offset = cfun_frame_layout.f8_offset;
7955 for (i = 24; i < 32; i++)
7956 {
7957 if (cfun_fpr_bit_p (i - 16))
7958 {
7959 restore_fpr (frame_pointer,
7960 offset + next_offset, i);
7961 next_offset += 8;
7962 }
7963 }
7964 }
7965
7966 }
7967 else
7968 {
7969 next_offset = cfun_frame_layout.f4_offset;
7970 for (i = 18; i < 20; i++)
7971 {
7972 if (cfun_fpr_bit_p (i - 16))
7973 {
7974 restore_fpr (frame_pointer,
7975 offset + next_offset, i);
7976 next_offset += 8;
7977 }
7978 else if (!TARGET_PACKED_STACK)
7979 next_offset += 8;
7980 }
7981
7982 }
7983
7984 /* Return register. */
7985
7986 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7987
7988 /* Restore call saved gprs. */
7989
7990 if (cfun_frame_layout.first_restore_gpr != -1)
7991 {
7992 rtx insn, addr;
7993 int i;
7994
7995 /* Check for global register and save them
7996 to stack location from where they get restored. */
7997
7998 for (i = cfun_frame_layout.first_restore_gpr;
7999 i <= cfun_frame_layout.last_restore_gpr;
8000 i++)
8001 {
8002 /* These registers are special and need to be
8003 restored in any case. */
8004 if (i == STACK_POINTER_REGNUM
8005 || i == RETURN_REGNUM
8006 || i == BASE_REGNUM
8007 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
8008 continue;
8009
8010 if (global_regs[i])
8011 {
8012 addr = plus_constant (frame_pointer,
8013 offset + cfun_frame_layout.gprs_offset
8014 + (i - cfun_frame_layout.first_save_gpr_slot)
8015 * UNITS_PER_WORD);
8016 addr = gen_rtx_MEM (Pmode, addr);
8017 set_mem_alias_set (addr, get_frame_alias_set ());
8018 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8019 }
8020 }
8021
8022 if (! sibcall)
8023 {
8024 /* Fetch return address from stack before load multiple,
8025 this will do good for scheduling. */
8026
8027 if (cfun_frame_layout.save_return_addr_p
8028 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8029 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8030 {
8031 int return_regnum = find_unused_clobbered_reg();
8032 if (!return_regnum)
8033 return_regnum = 4;
8034 return_reg = gen_rtx_REG (Pmode, return_regnum);
8035
8036 addr = plus_constant (frame_pointer,
8037 offset + cfun_frame_layout.gprs_offset
8038 + (RETURN_REGNUM
8039 - cfun_frame_layout.first_save_gpr_slot)
8040 * UNITS_PER_WORD);
8041 addr = gen_rtx_MEM (Pmode, addr);
8042 set_mem_alias_set (addr, get_frame_alias_set ());
8043 emit_move_insn (return_reg, addr);
8044 }
8045 }
8046
8047 insn = restore_gprs (frame_pointer,
8048 offset + cfun_frame_layout.gprs_offset
8049 + (cfun_frame_layout.first_restore_gpr
8050 - cfun_frame_layout.first_save_gpr_slot)
8051 * UNITS_PER_WORD,
8052 cfun_frame_layout.first_restore_gpr,
8053 cfun_frame_layout.last_restore_gpr);
8054 emit_insn (insn);
8055 }
8056
8057 if (! sibcall)
8058 {
8059
8060 /* Return to caller. */
8061
8062 p = rtvec_alloc (2);
8063
8064 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8065 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8066 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8067 }
8068 }
8069
8070
8071 /* Return the size in bytes of a function argument of
8072 type TYPE and/or mode MODE. At least one of TYPE or
8073 MODE must be specified. */
8074
8075 static int
8076 s390_function_arg_size (enum machine_mode mode, const_tree type)
8077 {
8078 if (type)
8079 return int_size_in_bytes (type);
8080
8081 /* No type info available for some library calls ... */
8082 if (mode != BLKmode)
8083 return GET_MODE_SIZE (mode);
8084
8085 /* If we have neither type nor mode, abort */
8086 gcc_unreachable ();
8087 }
8088
8089 /* Return true if a function argument of type TYPE and mode MODE
8090 is to be passed in a floating-point register, if available. */
8091
8092 static bool
8093 s390_function_arg_float (enum machine_mode mode, tree type)
8094 {
8095 int size = s390_function_arg_size (mode, type);
8096 if (size > 8)
8097 return false;
8098
8099 /* Soft-float changes the ABI: no floating-point registers are used. */
8100 if (TARGET_SOFT_FLOAT)
8101 return false;
8102
8103 /* No type info available for some library calls ... */
8104 if (!type)
8105 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8106
8107 /* The ABI says that record types with a single member are treated
8108 just like that member would be. */
8109 while (TREE_CODE (type) == RECORD_TYPE)
8110 {
8111 tree field, single = NULL_TREE;
8112
8113 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8114 {
8115 if (TREE_CODE (field) != FIELD_DECL)
8116 continue;
8117
8118 if (single == NULL_TREE)
8119 single = TREE_TYPE (field);
8120 else
8121 return false;
8122 }
8123
8124 if (single == NULL_TREE)
8125 return false;
8126 else
8127 type = single;
8128 }
8129
8130 return TREE_CODE (type) == REAL_TYPE;
8131 }
8132
8133 /* Return true if a function argument of type TYPE and mode MODE
8134 is to be passed in an integer register, or a pair of integer
8135 registers, if available. */
8136
8137 static bool
8138 s390_function_arg_integer (enum machine_mode mode, tree type)
8139 {
8140 int size = s390_function_arg_size (mode, type);
8141 if (size > 8)
8142 return false;
8143
8144 /* No type info available for some library calls ... */
8145 if (!type)
8146 return GET_MODE_CLASS (mode) == MODE_INT
8147 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8148
8149 /* We accept small integral (and similar) types. */
8150 if (INTEGRAL_TYPE_P (type)
8151 || POINTER_TYPE_P (type)
8152 || TREE_CODE (type) == OFFSET_TYPE
8153 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8154 return true;
8155
8156 /* We also accept structs of size 1, 2, 4, 8 that are not
8157 passed in floating-point registers. */
8158 if (AGGREGATE_TYPE_P (type)
8159 && exact_log2 (size) >= 0
8160 && !s390_function_arg_float (mode, type))
8161 return true;
8162
8163 return false;
8164 }
8165
8166 /* Return 1 if a function argument of type TYPE and mode MODE
8167 is to be passed by reference. The ABI specifies that only
8168 structures of size 1, 2, 4, or 8 bytes are passed by value,
8169 all other structures (and complex numbers) are passed by
8170 reference. */
8171
8172 static bool
8173 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8174 enum machine_mode mode, const_tree type,
8175 bool named ATTRIBUTE_UNUSED)
8176 {
8177 int size = s390_function_arg_size (mode, type);
8178 if (size > 8)
8179 return true;
8180
8181 if (type)
8182 {
8183 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8184 return 1;
8185
8186 if (TREE_CODE (type) == COMPLEX_TYPE
8187 || TREE_CODE (type) == VECTOR_TYPE)
8188 return 1;
8189 }
8190
8191 return 0;
8192 }
8193
8194 /* Update the data in CUM to advance over an argument of mode MODE and
8195 data type TYPE. (TYPE is null for libcalls where that information
8196 may not be available.). The boolean NAMED specifies whether the
8197 argument is a named argument (as opposed to an unnamed argument
8198 matching an ellipsis). */
8199
8200 void
8201 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8202 tree type, int named ATTRIBUTE_UNUSED)
8203 {
8204 if (s390_function_arg_float (mode, type))
8205 {
8206 cum->fprs += 1;
8207 }
8208 else if (s390_function_arg_integer (mode, type))
8209 {
8210 int size = s390_function_arg_size (mode, type);
8211 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
8212 }
8213 else
8214 gcc_unreachable ();
8215 }
8216
8217 /* Define where to put the arguments to a function.
8218 Value is zero to push the argument on the stack,
8219 or a hard register in which to store the argument.
8220
8221 MODE is the argument's machine mode.
8222 TYPE is the data type of the argument (as a tree).
8223 This is null for libcalls where that information may
8224 not be available.
8225 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8226 the preceding args and about the function being called.
8227 NAMED is nonzero if this argument is a named parameter
8228 (otherwise it is an extra parameter matching an ellipsis).
8229
8230 On S/390, we use general purpose registers 2 through 6 to
8231 pass integer, pointer, and certain structure arguments, and
8232 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8233 to pass floating point arguments. All remaining arguments
8234 are pushed to the stack. */
8235
8236 rtx
8237 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8238 int named ATTRIBUTE_UNUSED)
8239 {
8240 if (s390_function_arg_float (mode, type))
8241 {
8242 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8243 return 0;
8244 else
8245 return gen_rtx_REG (mode, cum->fprs + 16);
8246 }
8247 else if (s390_function_arg_integer (mode, type))
8248 {
8249 int size = s390_function_arg_size (mode, type);
8250 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
8251
8252 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8253 return 0;
8254 else
8255 return gen_rtx_REG (mode, cum->gprs + 2);
8256 }
8257
8258 /* After the real arguments, expand_call calls us once again
8259 with a void_type_node type. Whatever we return here is
8260 passed as operand 2 to the call expanders.
8261
8262 We don't need this feature ... */
8263 else if (type == void_type_node)
8264 return const0_rtx;
8265
8266 gcc_unreachable ();
8267 }
8268
8269 /* Return true if return values of type TYPE should be returned
8270 in a memory buffer whose address is passed by the caller as
8271 hidden first argument. */
8272
8273 static bool
8274 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8275 {
8276 /* We accept small integral (and similar) types. */
8277 if (INTEGRAL_TYPE_P (type)
8278 || POINTER_TYPE_P (type)
8279 || TREE_CODE (type) == OFFSET_TYPE
8280 || TREE_CODE (type) == REAL_TYPE)
8281 return int_size_in_bytes (type) > 8;
8282
8283 /* Aggregates and similar constructs are always returned
8284 in memory. */
8285 if (AGGREGATE_TYPE_P (type)
8286 || TREE_CODE (type) == COMPLEX_TYPE
8287 || TREE_CODE (type) == VECTOR_TYPE)
8288 return true;
8289
8290 /* ??? We get called on all sorts of random stuff from
8291 aggregate_value_p. We can't abort, but it's not clear
8292 what's safe to return. Pretend it's a struct I guess. */
8293 return true;
8294 }
8295
8296 /* Define where to return a (scalar) value of type TYPE.
8297 If TYPE is null, define where to return a (scalar)
8298 value of mode MODE from a libcall. */
8299
8300 rtx
8301 s390_function_value (const_tree type, enum machine_mode mode)
8302 {
8303 if (type)
8304 {
8305 int unsignedp = TYPE_UNSIGNED (type);
8306 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
8307 }
8308
8309 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8310 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8311
8312 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8313 return gen_rtx_REG (mode, 16);
8314 else
8315 return gen_rtx_REG (mode, 2);
8316 }
8317
8318
8319 /* Create and return the va_list datatype.
8320
8321 On S/390, va_list is an array type equivalent to
8322
8323 typedef struct __va_list_tag
8324 {
8325 long __gpr;
8326 long __fpr;
8327 void *__overflow_arg_area;
8328 void *__reg_save_area;
8329 } va_list[1];
8330
8331 where __gpr and __fpr hold the number of general purpose
8332 or floating point arguments used up to now, respectively,
8333 __overflow_arg_area points to the stack location of the
8334 next argument passed on the stack, and __reg_save_area
8335 always points to the start of the register area in the
8336 call frame of the current function. The function prologue
8337 saves all registers used for argument passing into this
8338 area if the function uses variable arguments. */
8339
8340 static tree
8341 s390_build_builtin_va_list (void)
8342 {
8343 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8344
8345 record = lang_hooks.types.make_type (RECORD_TYPE);
8346
8347 type_decl =
8348 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
8349
8350 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
8351 long_integer_type_node);
8352 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
8353 long_integer_type_node);
8354 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
8355 ptr_type_node);
8356 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
8357 ptr_type_node);
8358
8359 va_list_gpr_counter_field = f_gpr;
8360 va_list_fpr_counter_field = f_fpr;
8361
8362 DECL_FIELD_CONTEXT (f_gpr) = record;
8363 DECL_FIELD_CONTEXT (f_fpr) = record;
8364 DECL_FIELD_CONTEXT (f_ovf) = record;
8365 DECL_FIELD_CONTEXT (f_sav) = record;
8366
8367 TREE_CHAIN (record) = type_decl;
8368 TYPE_NAME (record) = type_decl;
8369 TYPE_FIELDS (record) = f_gpr;
8370 TREE_CHAIN (f_gpr) = f_fpr;
8371 TREE_CHAIN (f_fpr) = f_ovf;
8372 TREE_CHAIN (f_ovf) = f_sav;
8373
8374 layout_type (record);
8375
8376 /* The correct type is an array type of one element. */
8377 return build_array_type (record, build_index_type (size_zero_node));
8378 }
8379
8380 /* Implement va_start by filling the va_list structure VALIST.
8381 STDARG_P is always true, and ignored.
8382 NEXTARG points to the first anonymous stack argument.
8383
8384 The following global variables are used to initialize
8385 the va_list structure:
8386
8387 crtl->args.info:
8388 holds number of gprs and fprs used for named arguments.
8389 crtl->args.arg_offset_rtx:
8390 holds the offset of the first anonymous stack argument
8391 (relative to the virtual arg pointer). */
8392
8393 static void
8394 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8395 {
8396 HOST_WIDE_INT n_gpr, n_fpr;
8397 int off;
8398 tree f_gpr, f_fpr, f_ovf, f_sav;
8399 tree gpr, fpr, ovf, sav, t;
8400
8401 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8402 f_fpr = TREE_CHAIN (f_gpr);
8403 f_ovf = TREE_CHAIN (f_fpr);
8404 f_sav = TREE_CHAIN (f_ovf);
8405
8406 valist = build_va_arg_indirect_ref (valist);
8407 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8408 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8409 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8410 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8411
8412 /* Count number of gp and fp argument registers used. */
8413
8414 n_gpr = crtl->args.info.gprs;
8415 n_fpr = crtl->args.info.fprs;
8416
8417 if (cfun->va_list_gpr_size)
8418 {
8419 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8420 build_int_cst (NULL_TREE, n_gpr));
8421 TREE_SIDE_EFFECTS (t) = 1;
8422 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8423 }
8424
8425 if (cfun->va_list_fpr_size)
8426 {
8427 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8428 build_int_cst (NULL_TREE, n_fpr));
8429 TREE_SIDE_EFFECTS (t) = 1;
8430 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8431 }
8432
8433 /* Find the overflow area. */
8434 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8435 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8436 {
8437 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8438
8439 off = INTVAL (crtl->args.arg_offset_rtx);
8440 off = off < 0 ? 0 : off;
8441 if (TARGET_DEBUG_ARG)
8442 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8443 (int)n_gpr, (int)n_fpr, off);
8444
8445 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8446
8447 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8448 TREE_SIDE_EFFECTS (t) = 1;
8449 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8450 }
8451
8452 /* Find the register save area. */
8453 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8454 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8455 {
8456 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8457 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8458 size_int (-RETURN_REGNUM * UNITS_PER_WORD));
8459
8460 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8461 TREE_SIDE_EFFECTS (t) = 1;
8462 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8463 }
8464 }
8465
8466 /* Implement va_arg by updating the va_list structure
8467 VALIST as required to retrieve an argument of type
8468 TYPE, and returning that argument.
8469
8470 Generates code equivalent to:
8471
8472 if (integral value) {
8473 if (size <= 4 && args.gpr < 5 ||
8474 size > 4 && args.gpr < 4 )
8475 ret = args.reg_save_area[args.gpr+8]
8476 else
8477 ret = *args.overflow_arg_area++;
8478 } else if (float value) {
8479 if (args.fgpr < 2)
8480 ret = args.reg_save_area[args.fpr+64]
8481 else
8482 ret = *args.overflow_arg_area++;
8483 } else if (aggregate value) {
8484 if (args.gpr < 5)
8485 ret = *args.reg_save_area[args.gpr]
8486 else
8487 ret = **args.overflow_arg_area++;
8488 } */
8489
8490 static tree
8491 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8492 gimple_seq *post_p ATTRIBUTE_UNUSED)
8493 {
8494 tree f_gpr, f_fpr, f_ovf, f_sav;
8495 tree gpr, fpr, ovf, sav, reg, t, u;
8496 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8497 tree lab_false, lab_over, addr;
8498
8499 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8500 f_fpr = TREE_CHAIN (f_gpr);
8501 f_ovf = TREE_CHAIN (f_fpr);
8502 f_sav = TREE_CHAIN (f_ovf);
8503
8504 valist = build_va_arg_indirect_ref (valist);
8505 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8506 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8507 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8508
8509 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8510 both appear on a lhs. */
8511 valist = unshare_expr (valist);
8512 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8513
8514 size = int_size_in_bytes (type);
8515
8516 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8517 {
8518 if (TARGET_DEBUG_ARG)
8519 {
8520 fprintf (stderr, "va_arg: aggregate type");
8521 debug_tree (type);
8522 }
8523
8524 /* Aggregates are passed by reference. */
8525 indirect_p = 1;
8526 reg = gpr;
8527 n_reg = 1;
8528
8529 /* kernel stack layout on 31 bit: It is assumed here that no padding
8530 will be added by s390_frame_info because for va_args always an even
8531 number of gprs has to be saved r15-r2 = 14 regs. */
8532 sav_ofs = 2 * UNITS_PER_WORD;
8533 sav_scale = UNITS_PER_WORD;
8534 size = UNITS_PER_WORD;
8535 max_reg = GP_ARG_NUM_REG - n_reg;
8536 }
8537 else if (s390_function_arg_float (TYPE_MODE (type), type))
8538 {
8539 if (TARGET_DEBUG_ARG)
8540 {
8541 fprintf (stderr, "va_arg: float type");
8542 debug_tree (type);
8543 }
8544
8545 /* FP args go in FP registers, if present. */
8546 indirect_p = 0;
8547 reg = fpr;
8548 n_reg = 1;
8549 sav_ofs = 16 * UNITS_PER_WORD;
8550 sav_scale = 8;
8551 max_reg = FP_ARG_NUM_REG - n_reg;
8552 }
8553 else
8554 {
8555 if (TARGET_DEBUG_ARG)
8556 {
8557 fprintf (stderr, "va_arg: other type");
8558 debug_tree (type);
8559 }
8560
8561 /* Otherwise into GP registers. */
8562 indirect_p = 0;
8563 reg = gpr;
8564 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8565
8566 /* kernel stack layout on 31 bit: It is assumed here that no padding
8567 will be added by s390_frame_info because for va_args always an even
8568 number of gprs has to be saved r15-r2 = 14 regs. */
8569 sav_ofs = 2 * UNITS_PER_WORD;
8570
8571 if (size < UNITS_PER_WORD)
8572 sav_ofs += UNITS_PER_WORD - size;
8573
8574 sav_scale = UNITS_PER_WORD;
8575 max_reg = GP_ARG_NUM_REG - n_reg;
8576 }
8577
8578 /* Pull the value out of the saved registers ... */
8579
8580 lab_false = create_artificial_label ();
8581 lab_over = create_artificial_label ();
8582 addr = create_tmp_var (ptr_type_node, "addr");
8583 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
8584
8585 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8586 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8587 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8588 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8589 gimplify_and_add (t, pre_p);
8590
8591 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8592 size_int (sav_ofs));
8593 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8594 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8595 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8596
8597 gimplify_assign (addr, t, pre_p);
8598
8599 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8600
8601 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8602
8603
8604 /* ... Otherwise out of the overflow area. */
8605
8606 t = ovf;
8607 if (size < UNITS_PER_WORD)
8608 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8609 size_int (UNITS_PER_WORD - size));
8610
8611 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8612
8613 gimplify_assign (addr, t, pre_p);
8614
8615 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8616 size_int (size));
8617 gimplify_assign (ovf, t, pre_p);
8618
8619 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8620
8621
8622 /* Increment register save count. */
8623
8624 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8625 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8626 gimplify_and_add (u, pre_p);
8627
8628 if (indirect_p)
8629 {
8630 t = build_pointer_type (build_pointer_type (type));
8631 addr = fold_convert (t, addr);
8632 addr = build_va_arg_indirect_ref (addr);
8633 }
8634 else
8635 {
8636 t = build_pointer_type (type);
8637 addr = fold_convert (t, addr);
8638 }
8639
8640 return build_va_arg_indirect_ref (addr);
8641 }
8642
8643
8644 /* Builtins. */
8645
8646 enum s390_builtin
8647 {
8648 S390_BUILTIN_THREAD_POINTER,
8649 S390_BUILTIN_SET_THREAD_POINTER,
8650
8651 S390_BUILTIN_max
8652 };
8653
8654 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8655 CODE_FOR_get_tp_64,
8656 CODE_FOR_set_tp_64
8657 };
8658
8659 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8660 CODE_FOR_get_tp_31,
8661 CODE_FOR_set_tp_31
8662 };
8663
8664 static void
8665 s390_init_builtins (void)
8666 {
8667 tree ftype;
8668
8669 ftype = build_function_type (ptr_type_node, void_list_node);
8670 add_builtin_function ("__builtin_thread_pointer", ftype,
8671 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8672 NULL, NULL_TREE);
8673
8674 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8675 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8676 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8677 NULL, NULL_TREE);
8678 }
8679
8680 /* Expand an expression EXP that calls a built-in function,
8681 with result going to TARGET if that's convenient
8682 (and in mode MODE if that's convenient).
8683 SUBTARGET may be used as the target for computing one of EXP's operands.
8684 IGNORE is nonzero if the value is to be ignored. */
8685
8686 static rtx
8687 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8688 enum machine_mode mode ATTRIBUTE_UNUSED,
8689 int ignore ATTRIBUTE_UNUSED)
8690 {
8691 #define MAX_ARGS 2
8692
8693 enum insn_code const *code_for_builtin =
8694 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8695
8696 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8697 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8698 enum insn_code icode;
8699 rtx op[MAX_ARGS], pat;
8700 int arity;
8701 bool nonvoid;
8702 tree arg;
8703 call_expr_arg_iterator iter;
8704
8705 if (fcode >= S390_BUILTIN_max)
8706 internal_error ("bad builtin fcode");
8707 icode = code_for_builtin[fcode];
8708 if (icode == 0)
8709 internal_error ("bad builtin fcode");
8710
8711 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8712
8713 arity = 0;
8714 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8715 {
8716 const struct insn_operand_data *insn_op;
8717
8718 if (arg == error_mark_node)
8719 return NULL_RTX;
8720 if (arity > MAX_ARGS)
8721 return NULL_RTX;
8722
8723 insn_op = &insn_data[icode].operand[arity + nonvoid];
8724
8725 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8726
8727 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8728 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8729 arity++;
8730 }
8731
8732 if (nonvoid)
8733 {
8734 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8735 if (!target
8736 || GET_MODE (target) != tmode
8737 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8738 target = gen_reg_rtx (tmode);
8739 }
8740
8741 switch (arity)
8742 {
8743 case 0:
8744 pat = GEN_FCN (icode) (target);
8745 break;
8746 case 1:
8747 if (nonvoid)
8748 pat = GEN_FCN (icode) (target, op[0]);
8749 else
8750 pat = GEN_FCN (icode) (op[0]);
8751 break;
8752 case 2:
8753 pat = GEN_FCN (icode) (target, op[0], op[1]);
8754 break;
8755 default:
8756 gcc_unreachable ();
8757 }
8758 if (!pat)
8759 return NULL_RTX;
8760 emit_insn (pat);
8761
8762 if (nonvoid)
8763 return target;
8764 else
8765 return const0_rtx;
8766 }
8767
8768
8769 /* Output assembly code for the trampoline template to
8770 stdio stream FILE.
8771
8772 On S/390, we use gpr 1 internally in the trampoline code;
8773 gpr 0 is used to hold the static chain. */
8774
8775 void
8776 s390_trampoline_template (FILE *file)
8777 {
8778 rtx op[2];
8779 op[0] = gen_rtx_REG (Pmode, 0);
8780 op[1] = gen_rtx_REG (Pmode, 1);
8781
8782 if (TARGET_64BIT)
8783 {
8784 output_asm_insn ("basr\t%1,0", op);
8785 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8786 output_asm_insn ("br\t%1", op);
8787 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8788 }
8789 else
8790 {
8791 output_asm_insn ("basr\t%1,0", op);
8792 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8793 output_asm_insn ("br\t%1", op);
8794 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8795 }
8796 }
8797
8798 /* Emit RTL insns to initialize the variable parts of a trampoline.
8799 FNADDR is an RTX for the address of the function's pure code.
8800 CXT is an RTX for the static chain value for the function. */
8801
8802 void
8803 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8804 {
8805 emit_move_insn (gen_rtx_MEM (Pmode,
8806 memory_address (Pmode,
8807 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8808 emit_move_insn (gen_rtx_MEM (Pmode,
8809 memory_address (Pmode,
8810 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8811 }
8812
8813 /* Output assembler code to FILE to increment profiler label # LABELNO
8814 for profiling a function entry. */
8815
8816 void
8817 s390_function_profiler (FILE *file, int labelno)
8818 {
8819 rtx op[7];
8820
8821 char label[128];
8822 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8823
8824 fprintf (file, "# function profiler \n");
8825
8826 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8827 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8828 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8829
8830 op[2] = gen_rtx_REG (Pmode, 1);
8831 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8832 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8833
8834 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8835 if (flag_pic)
8836 {
8837 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8838 op[4] = gen_rtx_CONST (Pmode, op[4]);
8839 }
8840
8841 if (TARGET_64BIT)
8842 {
8843 output_asm_insn ("stg\t%0,%1", op);
8844 output_asm_insn ("larl\t%2,%3", op);
8845 output_asm_insn ("brasl\t%0,%4", op);
8846 output_asm_insn ("lg\t%0,%1", op);
8847 }
8848 else if (!flag_pic)
8849 {
8850 op[6] = gen_label_rtx ();
8851
8852 output_asm_insn ("st\t%0,%1", op);
8853 output_asm_insn ("bras\t%2,%l6", op);
8854 output_asm_insn (".long\t%4", op);
8855 output_asm_insn (".long\t%3", op);
8856 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8857 output_asm_insn ("l\t%0,0(%2)", op);
8858 output_asm_insn ("l\t%2,4(%2)", op);
8859 output_asm_insn ("basr\t%0,%0", op);
8860 output_asm_insn ("l\t%0,%1", op);
8861 }
8862 else
8863 {
8864 op[5] = gen_label_rtx ();
8865 op[6] = gen_label_rtx ();
8866
8867 output_asm_insn ("st\t%0,%1", op);
8868 output_asm_insn ("bras\t%2,%l6", op);
8869 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8870 output_asm_insn (".long\t%4-%l5", op);
8871 output_asm_insn (".long\t%3-%l5", op);
8872 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8873 output_asm_insn ("lr\t%0,%2", op);
8874 output_asm_insn ("a\t%0,0(%2)", op);
8875 output_asm_insn ("a\t%2,4(%2)", op);
8876 output_asm_insn ("basr\t%0,%0", op);
8877 output_asm_insn ("l\t%0,%1", op);
8878 }
8879 }
8880
8881 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8882 into its SYMBOL_REF_FLAGS. */
8883
8884 static void
8885 s390_encode_section_info (tree decl, rtx rtl, int first)
8886 {
8887 default_encode_section_info (decl, rtl, first);
8888
8889 if (TREE_CODE (decl) == VAR_DECL)
8890 {
8891 /* If a variable has a forced alignment to < 2 bytes, mark it
8892 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
8893 operand. */
8894 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8895 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8896 if (!DECL_SIZE (decl)
8897 || !DECL_ALIGN (decl)
8898 || !host_integerp (DECL_SIZE (decl), 0)
8899 || (DECL_ALIGN (decl) <= 64
8900 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
8901 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8902 }
8903
8904 /* Literal pool references don't have a decl so they are handled
8905 differently here. We rely on the information in the MEM_ALIGN
8906 entry to decide upon natural alignment. */
8907 if (MEM_P (rtl)
8908 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
8909 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
8910 && (MEM_ALIGN (rtl) == 0
8911 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
8912 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8913 }
8914
8915 /* Output thunk to FILE that implements a C++ virtual function call (with
8916 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8917 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8918 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8919 relative to the resulting this pointer. */
8920
8921 static void
8922 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8923 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8924 tree function)
8925 {
8926 rtx op[10];
8927 int nonlocal = 0;
8928
8929 /* Operand 0 is the target function. */
8930 op[0] = XEXP (DECL_RTL (function), 0);
8931 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8932 {
8933 nonlocal = 1;
8934 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8935 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8936 op[0] = gen_rtx_CONST (Pmode, op[0]);
8937 }
8938
8939 /* Operand 1 is the 'this' pointer. */
8940 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8941 op[1] = gen_rtx_REG (Pmode, 3);
8942 else
8943 op[1] = gen_rtx_REG (Pmode, 2);
8944
8945 /* Operand 2 is the delta. */
8946 op[2] = GEN_INT (delta);
8947
8948 /* Operand 3 is the vcall_offset. */
8949 op[3] = GEN_INT (vcall_offset);
8950
8951 /* Operand 4 is the temporary register. */
8952 op[4] = gen_rtx_REG (Pmode, 1);
8953
8954 /* Operands 5 to 8 can be used as labels. */
8955 op[5] = NULL_RTX;
8956 op[6] = NULL_RTX;
8957 op[7] = NULL_RTX;
8958 op[8] = NULL_RTX;
8959
8960 /* Operand 9 can be used for temporary register. */
8961 op[9] = NULL_RTX;
8962
8963 /* Generate code. */
8964 if (TARGET_64BIT)
8965 {
8966 /* Setup literal pool pointer if required. */
8967 if ((!DISP_IN_RANGE (delta)
8968 && !CONST_OK_FOR_K (delta)
8969 && !CONST_OK_FOR_Os (delta))
8970 || (!DISP_IN_RANGE (vcall_offset)
8971 && !CONST_OK_FOR_K (vcall_offset)
8972 && !CONST_OK_FOR_Os (vcall_offset)))
8973 {
8974 op[5] = gen_label_rtx ();
8975 output_asm_insn ("larl\t%4,%5", op);
8976 }
8977
8978 /* Add DELTA to this pointer. */
8979 if (delta)
8980 {
8981 if (CONST_OK_FOR_J (delta))
8982 output_asm_insn ("la\t%1,%2(%1)", op);
8983 else if (DISP_IN_RANGE (delta))
8984 output_asm_insn ("lay\t%1,%2(%1)", op);
8985 else if (CONST_OK_FOR_K (delta))
8986 output_asm_insn ("aghi\t%1,%2", op);
8987 else if (CONST_OK_FOR_Os (delta))
8988 output_asm_insn ("agfi\t%1,%2", op);
8989 else
8990 {
8991 op[6] = gen_label_rtx ();
8992 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8993 }
8994 }
8995
8996 /* Perform vcall adjustment. */
8997 if (vcall_offset)
8998 {
8999 if (DISP_IN_RANGE (vcall_offset))
9000 {
9001 output_asm_insn ("lg\t%4,0(%1)", op);
9002 output_asm_insn ("ag\t%1,%3(%4)", op);
9003 }
9004 else if (CONST_OK_FOR_K (vcall_offset))
9005 {
9006 output_asm_insn ("lghi\t%4,%3", op);
9007 output_asm_insn ("ag\t%4,0(%1)", op);
9008 output_asm_insn ("ag\t%1,0(%4)", op);
9009 }
9010 else if (CONST_OK_FOR_Os (vcall_offset))
9011 {
9012 output_asm_insn ("lgfi\t%4,%3", op);
9013 output_asm_insn ("ag\t%4,0(%1)", op);
9014 output_asm_insn ("ag\t%1,0(%4)", op);
9015 }
9016 else
9017 {
9018 op[7] = gen_label_rtx ();
9019 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9020 output_asm_insn ("ag\t%4,0(%1)", op);
9021 output_asm_insn ("ag\t%1,0(%4)", op);
9022 }
9023 }
9024
9025 /* Jump to target. */
9026 output_asm_insn ("jg\t%0", op);
9027
9028 /* Output literal pool if required. */
9029 if (op[5])
9030 {
9031 output_asm_insn (".align\t4", op);
9032 targetm.asm_out.internal_label (file, "L",
9033 CODE_LABEL_NUMBER (op[5]));
9034 }
9035 if (op[6])
9036 {
9037 targetm.asm_out.internal_label (file, "L",
9038 CODE_LABEL_NUMBER (op[6]));
9039 output_asm_insn (".long\t%2", op);
9040 }
9041 if (op[7])
9042 {
9043 targetm.asm_out.internal_label (file, "L",
9044 CODE_LABEL_NUMBER (op[7]));
9045 output_asm_insn (".long\t%3", op);
9046 }
9047 }
9048 else
9049 {
9050 /* Setup base pointer if required. */
9051 if (!vcall_offset
9052 || (!DISP_IN_RANGE (delta)
9053 && !CONST_OK_FOR_K (delta)
9054 && !CONST_OK_FOR_Os (delta))
9055 || (!DISP_IN_RANGE (delta)
9056 && !CONST_OK_FOR_K (vcall_offset)
9057 && !CONST_OK_FOR_Os (vcall_offset)))
9058 {
9059 op[5] = gen_label_rtx ();
9060 output_asm_insn ("basr\t%4,0", op);
9061 targetm.asm_out.internal_label (file, "L",
9062 CODE_LABEL_NUMBER (op[5]));
9063 }
9064
9065 /* Add DELTA to this pointer. */
9066 if (delta)
9067 {
9068 if (CONST_OK_FOR_J (delta))
9069 output_asm_insn ("la\t%1,%2(%1)", op);
9070 else if (DISP_IN_RANGE (delta))
9071 output_asm_insn ("lay\t%1,%2(%1)", op);
9072 else if (CONST_OK_FOR_K (delta))
9073 output_asm_insn ("ahi\t%1,%2", op);
9074 else if (CONST_OK_FOR_Os (delta))
9075 output_asm_insn ("afi\t%1,%2", op);
9076 else
9077 {
9078 op[6] = gen_label_rtx ();
9079 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9080 }
9081 }
9082
9083 /* Perform vcall adjustment. */
9084 if (vcall_offset)
9085 {
9086 if (CONST_OK_FOR_J (vcall_offset))
9087 {
9088 output_asm_insn ("l\t%4,0(%1)", op);
9089 output_asm_insn ("a\t%1,%3(%4)", op);
9090 }
9091 else if (DISP_IN_RANGE (vcall_offset))
9092 {
9093 output_asm_insn ("l\t%4,0(%1)", op);
9094 output_asm_insn ("ay\t%1,%3(%4)", op);
9095 }
9096 else if (CONST_OK_FOR_K (vcall_offset))
9097 {
9098 output_asm_insn ("lhi\t%4,%3", op);
9099 output_asm_insn ("a\t%4,0(%1)", op);
9100 output_asm_insn ("a\t%1,0(%4)", op);
9101 }
9102 else if (CONST_OK_FOR_Os (vcall_offset))
9103 {
9104 output_asm_insn ("iilf\t%4,%3", op);
9105 output_asm_insn ("a\t%4,0(%1)", op);
9106 output_asm_insn ("a\t%1,0(%4)", op);
9107 }
9108 else
9109 {
9110 op[7] = gen_label_rtx ();
9111 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9112 output_asm_insn ("a\t%4,0(%1)", op);
9113 output_asm_insn ("a\t%1,0(%4)", op);
9114 }
9115
9116 /* We had to clobber the base pointer register.
9117 Re-setup the base pointer (with a different base). */
9118 op[5] = gen_label_rtx ();
9119 output_asm_insn ("basr\t%4,0", op);
9120 targetm.asm_out.internal_label (file, "L",
9121 CODE_LABEL_NUMBER (op[5]));
9122 }
9123
9124 /* Jump to target. */
9125 op[8] = gen_label_rtx ();
9126
9127 if (!flag_pic)
9128 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9129 else if (!nonlocal)
9130 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9131 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9132 else if (flag_pic == 1)
9133 {
9134 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9135 output_asm_insn ("l\t%4,%0(%4)", op);
9136 }
9137 else if (flag_pic == 2)
9138 {
9139 op[9] = gen_rtx_REG (Pmode, 0);
9140 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9141 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9142 output_asm_insn ("ar\t%4,%9", op);
9143 output_asm_insn ("l\t%4,0(%4)", op);
9144 }
9145
9146 output_asm_insn ("br\t%4", op);
9147
9148 /* Output literal pool. */
9149 output_asm_insn (".align\t4", op);
9150
9151 if (nonlocal && flag_pic == 2)
9152 output_asm_insn (".long\t%0", op);
9153 if (nonlocal)
9154 {
9155 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9156 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9157 }
9158
9159 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9160 if (!flag_pic)
9161 output_asm_insn (".long\t%0", op);
9162 else
9163 output_asm_insn (".long\t%0-%5", op);
9164
9165 if (op[6])
9166 {
9167 targetm.asm_out.internal_label (file, "L",
9168 CODE_LABEL_NUMBER (op[6]));
9169 output_asm_insn (".long\t%2", op);
9170 }
9171 if (op[7])
9172 {
9173 targetm.asm_out.internal_label (file, "L",
9174 CODE_LABEL_NUMBER (op[7]));
9175 output_asm_insn (".long\t%3", op);
9176 }
9177 }
9178 }
9179
9180 static bool
9181 s390_valid_pointer_mode (enum machine_mode mode)
9182 {
9183 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9184 }
9185
9186 /* Checks whether the given CALL_EXPR would use a caller
9187 saved register. This is used to decide whether sibling call
9188 optimization could be performed on the respective function
9189 call. */
9190
9191 static bool
9192 s390_call_saved_register_used (tree call_expr)
9193 {
9194 CUMULATIVE_ARGS cum;
9195 tree parameter;
9196 enum machine_mode mode;
9197 tree type;
9198 rtx parm_rtx;
9199 int reg, i;
9200
9201 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9202
9203 for (i = 0; i < call_expr_nargs (call_expr); i++)
9204 {
9205 parameter = CALL_EXPR_ARG (call_expr, i);
9206 gcc_assert (parameter);
9207
9208 /* For an undeclared variable passed as parameter we will get
9209 an ERROR_MARK node here. */
9210 if (TREE_CODE (parameter) == ERROR_MARK)
9211 return true;
9212
9213 type = TREE_TYPE (parameter);
9214 gcc_assert (type);
9215
9216 mode = TYPE_MODE (type);
9217 gcc_assert (mode);
9218
9219 if (pass_by_reference (&cum, mode, type, true))
9220 {
9221 mode = Pmode;
9222 type = build_pointer_type (type);
9223 }
9224
9225 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9226
9227 s390_function_arg_advance (&cum, mode, type, 0);
9228
9229 if (parm_rtx && REG_P (parm_rtx))
9230 {
9231 for (reg = 0;
9232 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9233 reg++)
9234 if (! call_used_regs[reg + REGNO (parm_rtx)])
9235 return true;
9236 }
9237 }
9238 return false;
9239 }
9240
9241 /* Return true if the given call expression can be
9242 turned into a sibling call.
9243 DECL holds the declaration of the function to be called whereas
9244 EXP is the call expression itself. */
9245
9246 static bool
9247 s390_function_ok_for_sibcall (tree decl, tree exp)
9248 {
9249 /* The TPF epilogue uses register 1. */
9250 if (TARGET_TPF_PROFILING)
9251 return false;
9252
9253 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9254 which would have to be restored before the sibcall. */
9255 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9256 return false;
9257
9258 /* Register 6 on s390 is available as an argument register but unfortunately
9259 "caller saved". This makes functions needing this register for arguments
9260 not suitable for sibcalls. */
9261 return !s390_call_saved_register_used (exp);
9262 }
9263
9264 /* Return the fixed registers used for condition codes. */
9265
9266 static bool
9267 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9268 {
9269 *p1 = CC_REGNUM;
9270 *p2 = INVALID_REGNUM;
9271
9272 return true;
9273 }
9274
9275 /* This function is used by the call expanders of the machine description.
9276 It emits the call insn itself together with the necessary operations
9277 to adjust the target address and returns the emitted insn.
9278 ADDR_LOCATION is the target address rtx
9279 TLS_CALL the location of the thread-local symbol
9280 RESULT_REG the register where the result of the call should be stored
9281 RETADDR_REG the register where the return address should be stored
9282 If this parameter is NULL_RTX the call is considered
9283 to be a sibling call. */
9284
9285 rtx
9286 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9287 rtx retaddr_reg)
9288 {
9289 bool plt_call = false;
9290 rtx insn;
9291 rtx call;
9292 rtx clobber;
9293 rtvec vec;
9294
9295 /* Direct function calls need special treatment. */
9296 if (GET_CODE (addr_location) == SYMBOL_REF)
9297 {
9298 /* When calling a global routine in PIC mode, we must
9299 replace the symbol itself with the PLT stub. */
9300 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9301 {
9302 addr_location = gen_rtx_UNSPEC (Pmode,
9303 gen_rtvec (1, addr_location),
9304 UNSPEC_PLT);
9305 addr_location = gen_rtx_CONST (Pmode, addr_location);
9306 plt_call = true;
9307 }
9308
9309 /* Unless we can use the bras(l) insn, force the
9310 routine address into a register. */
9311 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9312 {
9313 if (flag_pic)
9314 addr_location = legitimize_pic_address (addr_location, 0);
9315 else
9316 addr_location = force_reg (Pmode, addr_location);
9317 }
9318 }
9319
9320 /* If it is already an indirect call or the code above moved the
9321 SYMBOL_REF to somewhere else make sure the address can be found in
9322 register 1. */
9323 if (retaddr_reg == NULL_RTX
9324 && GET_CODE (addr_location) != SYMBOL_REF
9325 && !plt_call)
9326 {
9327 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9328 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9329 }
9330
9331 addr_location = gen_rtx_MEM (QImode, addr_location);
9332 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9333
9334 if (result_reg != NULL_RTX)
9335 call = gen_rtx_SET (VOIDmode, result_reg, call);
9336
9337 if (retaddr_reg != NULL_RTX)
9338 {
9339 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9340
9341 if (tls_call != NULL_RTX)
9342 vec = gen_rtvec (3, call, clobber,
9343 gen_rtx_USE (VOIDmode, tls_call));
9344 else
9345 vec = gen_rtvec (2, call, clobber);
9346
9347 call = gen_rtx_PARALLEL (VOIDmode, vec);
9348 }
9349
9350 insn = emit_call_insn (call);
9351
9352 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9353 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9354 {
9355 /* s390_function_ok_for_sibcall should
9356 have denied sibcalls in this case. */
9357 gcc_assert (retaddr_reg != NULL_RTX);
9358
9359 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9360 }
9361 return insn;
9362 }
9363
9364 /* Implement CONDITIONAL_REGISTER_USAGE. */
9365
9366 void
9367 s390_conditional_register_usage (void)
9368 {
9369 int i;
9370
9371 if (flag_pic)
9372 {
9373 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9374 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9375 }
9376 if (TARGET_CPU_ZARCH)
9377 {
9378 fixed_regs[BASE_REGNUM] = 0;
9379 call_used_regs[BASE_REGNUM] = 0;
9380 fixed_regs[RETURN_REGNUM] = 0;
9381 call_used_regs[RETURN_REGNUM] = 0;
9382 }
9383 if (TARGET_64BIT)
9384 {
9385 for (i = 24; i < 32; i++)
9386 call_used_regs[i] = call_really_used_regs[i] = 0;
9387 }
9388 else
9389 {
9390 for (i = 18; i < 20; i++)
9391 call_used_regs[i] = call_really_used_regs[i] = 0;
9392 }
9393
9394 if (TARGET_SOFT_FLOAT)
9395 {
9396 for (i = 16; i < 32; i++)
9397 call_used_regs[i] = fixed_regs[i] = 1;
9398 }
9399 }
9400
9401 /* Corresponding function to eh_return expander. */
9402
9403 static GTY(()) rtx s390_tpf_eh_return_symbol;
9404 void
9405 s390_emit_tpf_eh_return (rtx target)
9406 {
9407 rtx insn, reg;
9408
9409 if (!s390_tpf_eh_return_symbol)
9410 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9411
9412 reg = gen_rtx_REG (Pmode, 2);
9413
9414 emit_move_insn (reg, target);
9415 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9416 gen_rtx_REG (Pmode, RETURN_REGNUM));
9417 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9418
9419 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9420 }
9421
9422 /* Rework the prologue/epilogue to avoid saving/restoring
9423 registers unnecessarily. */
9424
9425 static void
9426 s390_optimize_prologue (void)
9427 {
9428 rtx insn, new_insn, next_insn;
9429
9430 /* Do a final recompute of the frame-related data. */
9431
9432 s390_update_frame_layout ();
9433
9434 /* If all special registers are in fact used, there's nothing we
9435 can do, so no point in walking the insn list. */
9436
9437 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9438 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9439 && (TARGET_CPU_ZARCH
9440 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9441 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9442 return;
9443
9444 /* Search for prologue/epilogue insns and replace them. */
9445
9446 for (insn = get_insns (); insn; insn = next_insn)
9447 {
9448 int first, last, off;
9449 rtx set, base, offset;
9450
9451 next_insn = NEXT_INSN (insn);
9452
9453 if (GET_CODE (insn) != INSN)
9454 continue;
9455
9456 if (GET_CODE (PATTERN (insn)) == PARALLEL
9457 && store_multiple_operation (PATTERN (insn), VOIDmode))
9458 {
9459 set = XVECEXP (PATTERN (insn), 0, 0);
9460 first = REGNO (SET_SRC (set));
9461 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9462 offset = const0_rtx;
9463 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9464 off = INTVAL (offset);
9465
9466 if (GET_CODE (base) != REG || off < 0)
9467 continue;
9468 if (cfun_frame_layout.first_save_gpr != -1
9469 && (cfun_frame_layout.first_save_gpr < first
9470 || cfun_frame_layout.last_save_gpr > last))
9471 continue;
9472 if (REGNO (base) != STACK_POINTER_REGNUM
9473 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9474 continue;
9475 if (first > BASE_REGNUM || last < BASE_REGNUM)
9476 continue;
9477
9478 if (cfun_frame_layout.first_save_gpr != -1)
9479 {
9480 new_insn = save_gprs (base,
9481 off + (cfun_frame_layout.first_save_gpr
9482 - first) * UNITS_PER_WORD,
9483 cfun_frame_layout.first_save_gpr,
9484 cfun_frame_layout.last_save_gpr);
9485 new_insn = emit_insn_before (new_insn, insn);
9486 INSN_ADDRESSES_NEW (new_insn, -1);
9487 }
9488
9489 remove_insn (insn);
9490 continue;
9491 }
9492
9493 if (cfun_frame_layout.first_save_gpr == -1
9494 && GET_CODE (PATTERN (insn)) == SET
9495 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9496 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9497 || (!TARGET_CPU_ZARCH
9498 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9499 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9500 {
9501 set = PATTERN (insn);
9502 first = REGNO (SET_SRC (set));
9503 offset = const0_rtx;
9504 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9505 off = INTVAL (offset);
9506
9507 if (GET_CODE (base) != REG || off < 0)
9508 continue;
9509 if (REGNO (base) != STACK_POINTER_REGNUM
9510 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9511 continue;
9512
9513 remove_insn (insn);
9514 continue;
9515 }
9516
9517 if (GET_CODE (PATTERN (insn)) == PARALLEL
9518 && load_multiple_operation (PATTERN (insn), VOIDmode))
9519 {
9520 set = XVECEXP (PATTERN (insn), 0, 0);
9521 first = REGNO (SET_DEST (set));
9522 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9523 offset = const0_rtx;
9524 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9525 off = INTVAL (offset);
9526
9527 if (GET_CODE (base) != REG || off < 0)
9528 continue;
9529 if (cfun_frame_layout.first_restore_gpr != -1
9530 && (cfun_frame_layout.first_restore_gpr < first
9531 || cfun_frame_layout.last_restore_gpr > last))
9532 continue;
9533 if (REGNO (base) != STACK_POINTER_REGNUM
9534 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9535 continue;
9536 if (first > BASE_REGNUM || last < BASE_REGNUM)
9537 continue;
9538
9539 if (cfun_frame_layout.first_restore_gpr != -1)
9540 {
9541 new_insn = restore_gprs (base,
9542 off + (cfun_frame_layout.first_restore_gpr
9543 - first) * UNITS_PER_WORD,
9544 cfun_frame_layout.first_restore_gpr,
9545 cfun_frame_layout.last_restore_gpr);
9546 new_insn = emit_insn_before (new_insn, insn);
9547 INSN_ADDRESSES_NEW (new_insn, -1);
9548 }
9549
9550 remove_insn (insn);
9551 continue;
9552 }
9553
9554 if (cfun_frame_layout.first_restore_gpr == -1
9555 && GET_CODE (PATTERN (insn)) == SET
9556 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9557 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9558 || (!TARGET_CPU_ZARCH
9559 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9560 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9561 {
9562 set = PATTERN (insn);
9563 first = REGNO (SET_DEST (set));
9564 offset = const0_rtx;
9565 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9566 off = INTVAL (offset);
9567
9568 if (GET_CODE (base) != REG || off < 0)
9569 continue;
9570 if (REGNO (base) != STACK_POINTER_REGNUM
9571 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9572 continue;
9573
9574 remove_insn (insn);
9575 continue;
9576 }
9577 }
9578 }
9579
9580 /* Returns 1 if INSN reads the value of REG for purposes not related
9581 to addressing of memory, and 0 otherwise. */
9582 static int
9583 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9584 {
9585 return reg_referenced_p (reg, PATTERN (insn))
9586 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9587 }
9588
9589 /* Starting from INSN find_cond_jump looks downwards in the insn
9590 stream for a single jump insn which is the last user of the
9591 condition code set in INSN. */
9592 static rtx
9593 find_cond_jump (rtx insn)
9594 {
9595 for (; insn; insn = NEXT_INSN (insn))
9596 {
9597 rtx ite, cc;
9598
9599 if (LABEL_P (insn))
9600 break;
9601
9602 if (!JUMP_P (insn))
9603 {
9604 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9605 break;
9606 continue;
9607 }
9608
9609 /* This will be triggered by a return. */
9610 if (GET_CODE (PATTERN (insn)) != SET)
9611 break;
9612
9613 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9614 ite = SET_SRC (PATTERN (insn));
9615
9616 if (GET_CODE (ite) != IF_THEN_ELSE)
9617 break;
9618
9619 cc = XEXP (XEXP (ite, 0), 0);
9620 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9621 break;
9622
9623 if (find_reg_note (insn, REG_DEAD, cc))
9624 return insn;
9625 break;
9626 }
9627
9628 return NULL_RTX;
9629 }
9630
9631 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9632 the semantics does not change. If NULL_RTX is passed as COND the
9633 function tries to find the conditional jump starting with INSN. */
9634 static void
9635 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9636 {
9637 rtx tmp = *op0;
9638
9639 if (cond == NULL_RTX)
9640 {
9641 rtx jump = find_cond_jump (NEXT_INSN (insn));
9642 jump = jump ? single_set (jump) : NULL_RTX;
9643
9644 if (jump == NULL_RTX)
9645 return;
9646
9647 cond = XEXP (XEXP (jump, 1), 0);
9648 }
9649
9650 *op0 = *op1;
9651 *op1 = tmp;
9652 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9653 }
9654
9655 /* On z10, instructions of the compare-and-branch family have the
9656 property to access the register occurring as second operand with
9657 its bits complemented. If such a compare is grouped with a second
9658 instruction that accesses the same register non-complemented, and
9659 if that register's value is delivered via a bypass, then the
9660 pipeline recycles, thereby causing significant performance decline.
9661 This function locates such situations and exchanges the two
9662 operands of the compare. */
9663 static void
9664 s390_z10_optimize_cmp (void)
9665 {
9666 rtx insn, prev_insn, next_insn;
9667 int added_NOPs = 0;
9668
9669 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9670 {
9671 rtx cond, *op0, *op1;
9672
9673 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
9674 continue;
9675
9676 if (GET_CODE (PATTERN (insn)) == PARALLEL)
9677 {
9678 /* Handle compare and branch and branch on count
9679 instructions. */
9680 rtx pattern = single_set (insn);
9681
9682 if (!pattern
9683 || SET_DEST (pattern) != pc_rtx
9684 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
9685 continue;
9686
9687 cond = XEXP (SET_SRC (pattern), 0);
9688 op0 = &XEXP (cond, 0);
9689 op1 = &XEXP (cond, 1);
9690 }
9691 else if (GET_CODE (PATTERN (insn)) == SET)
9692 {
9693 rtx src, dest;
9694
9695 /* Handle normal compare instructions. */
9696 src = SET_SRC (PATTERN (insn));
9697 dest = SET_DEST (PATTERN (insn));
9698
9699 if (!REG_P (dest)
9700 || !CC_REGNO_P (REGNO (dest))
9701 || GET_CODE (src) != COMPARE)
9702 continue;
9703
9704 /* s390_swap_cmp will try to find the conditional
9705 jump when passing NULL_RTX as condition. */
9706 cond = NULL_RTX;
9707 op0 = &XEXP (src, 0);
9708 op1 = &XEXP (src, 1);
9709 }
9710 else
9711 continue;
9712
9713 if (!REG_P (*op0) || !REG_P (*op1))
9714 continue;
9715
9716 /* Swap the COMPARE arguments and its mask if there is a
9717 conflicting access in the previous insn. */
9718 prev_insn = PREV_INSN (insn);
9719 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9720 && reg_referenced_p (*op1, PATTERN (prev_insn)))
9721 s390_swap_cmp (cond, op0, op1, insn);
9722
9723 /* Check if there is a conflict with the next insn. If there
9724 was no conflict with the previous insn, then swap the
9725 COMPARE arguments and its mask. If we already swapped
9726 the operands, or if swapping them would cause a conflict
9727 with the previous insn, issue a NOP after the COMPARE in
9728 order to separate the two instuctions. */
9729 next_insn = NEXT_INSN (insn);
9730 if (next_insn != NULL_RTX && INSN_P (next_insn)
9731 && s390_non_addr_reg_read_p (*op1, next_insn))
9732 {
9733 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9734 && s390_non_addr_reg_read_p (*op0, prev_insn))
9735 {
9736 if (REGNO (*op1) == 0)
9737 emit_insn_after (gen_nop1 (), insn);
9738 else
9739 emit_insn_after (gen_nop (), insn);
9740 added_NOPs = 1;
9741 }
9742 else
9743 s390_swap_cmp (cond, op0, op1, insn);
9744 }
9745 }
9746
9747 /* Adjust branches if we added new instructions. */
9748 if (added_NOPs)
9749 shorten_branches (get_insns ());
9750 }
9751
9752
9753 /* Perform machine-dependent processing. */
9754
9755 static void
9756 s390_reorg (void)
9757 {
9758 bool pool_overflow = false;
9759
9760 /* Make sure all splits have been performed; splits after
9761 machine_dependent_reorg might confuse insn length counts. */
9762 split_all_insns_noflow ();
9763
9764 /* Install the main literal pool and the associated base
9765 register load insns.
9766
9767 In addition, there are two problematic situations we need
9768 to correct:
9769
9770 - the literal pool might be > 4096 bytes in size, so that
9771 some of its elements cannot be directly accessed
9772
9773 - a branch target might be > 64K away from the branch, so that
9774 it is not possible to use a PC-relative instruction.
9775
9776 To fix those, we split the single literal pool into multiple
9777 pool chunks, reloading the pool base register at various
9778 points throughout the function to ensure it always points to
9779 the pool chunk the following code expects, and / or replace
9780 PC-relative branches by absolute branches.
9781
9782 However, the two problems are interdependent: splitting the
9783 literal pool can move a branch further away from its target,
9784 causing the 64K limit to overflow, and on the other hand,
9785 replacing a PC-relative branch by an absolute branch means
9786 we need to put the branch target address into the literal
9787 pool, possibly causing it to overflow.
9788
9789 So, we loop trying to fix up both problems until we manage
9790 to satisfy both conditions at the same time. Note that the
9791 loop is guaranteed to terminate as every pass of the loop
9792 strictly decreases the total number of PC-relative branches
9793 in the function. (This is not completely true as there
9794 might be branch-over-pool insns introduced by chunkify_start.
9795 Those never need to be split however.) */
9796
9797 for (;;)
9798 {
9799 struct constant_pool *pool = NULL;
9800
9801 /* Collect the literal pool. */
9802 if (!pool_overflow)
9803 {
9804 pool = s390_mainpool_start ();
9805 if (!pool)
9806 pool_overflow = true;
9807 }
9808
9809 /* If literal pool overflowed, start to chunkify it. */
9810 if (pool_overflow)
9811 pool = s390_chunkify_start ();
9812
9813 /* Split out-of-range branches. If this has created new
9814 literal pool entries, cancel current chunk list and
9815 recompute it. zSeries machines have large branch
9816 instructions, so we never need to split a branch. */
9817 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9818 {
9819 if (pool_overflow)
9820 s390_chunkify_cancel (pool);
9821 else
9822 s390_mainpool_cancel (pool);
9823
9824 continue;
9825 }
9826
9827 /* If we made it up to here, both conditions are satisfied.
9828 Finish up literal pool related changes. */
9829 if (pool_overflow)
9830 s390_chunkify_finish (pool);
9831 else
9832 s390_mainpool_finish (pool);
9833
9834 /* We're done splitting branches. */
9835 cfun->machine->split_branches_pending_p = false;
9836 break;
9837 }
9838
9839 /* Generate out-of-pool execute target insns. */
9840 if (TARGET_CPU_ZARCH)
9841 {
9842 rtx insn, label, target;
9843
9844 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9845 {
9846 label = s390_execute_label (insn);
9847 if (!label)
9848 continue;
9849
9850 gcc_assert (label != const0_rtx);
9851
9852 target = emit_label (XEXP (label, 0));
9853 INSN_ADDRESSES_NEW (target, -1);
9854
9855 target = emit_insn (s390_execute_target (insn));
9856 INSN_ADDRESSES_NEW (target, -1);
9857 }
9858 }
9859
9860 /* Try to optimize prologue and epilogue further. */
9861 s390_optimize_prologue ();
9862
9863 /* Eliminate z10-specific pipeline recycles related to some compare
9864 instructions. */
9865 if (s390_tune == PROCESSOR_2097_Z10)
9866 s390_z10_optimize_cmp ();
9867 }
9868
9869
9870 /* Initialize GCC target structure. */
9871
9872 #undef TARGET_ASM_ALIGNED_HI_OP
9873 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9874 #undef TARGET_ASM_ALIGNED_DI_OP
9875 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9876 #undef TARGET_ASM_INTEGER
9877 #define TARGET_ASM_INTEGER s390_assemble_integer
9878
9879 #undef TARGET_ASM_OPEN_PAREN
9880 #define TARGET_ASM_OPEN_PAREN ""
9881
9882 #undef TARGET_ASM_CLOSE_PAREN
9883 #define TARGET_ASM_CLOSE_PAREN ""
9884
9885 #undef TARGET_DEFAULT_TARGET_FLAGS
9886 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9887 #undef TARGET_HANDLE_OPTION
9888 #define TARGET_HANDLE_OPTION s390_handle_option
9889
9890 #undef TARGET_ENCODE_SECTION_INFO
9891 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9892
9893 #ifdef HAVE_AS_TLS
9894 #undef TARGET_HAVE_TLS
9895 #define TARGET_HAVE_TLS true
9896 #endif
9897 #undef TARGET_CANNOT_FORCE_CONST_MEM
9898 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9899
9900 #undef TARGET_DELEGITIMIZE_ADDRESS
9901 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9902
9903 #undef TARGET_LEGITIMIZE_ADDRESS
9904 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
9905
9906 #undef TARGET_RETURN_IN_MEMORY
9907 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9908
9909 #undef TARGET_INIT_BUILTINS
9910 #define TARGET_INIT_BUILTINS s390_init_builtins
9911 #undef TARGET_EXPAND_BUILTIN
9912 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9913
9914 #undef TARGET_ASM_OUTPUT_MI_THUNK
9915 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9916 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9917 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
9918
9919 #undef TARGET_SCHED_ADJUST_PRIORITY
9920 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9921 #undef TARGET_SCHED_ISSUE_RATE
9922 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9923 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9924 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9925
9926 #undef TARGET_CANNOT_COPY_INSN_P
9927 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9928 #undef TARGET_RTX_COSTS
9929 #define TARGET_RTX_COSTS s390_rtx_costs
9930 #undef TARGET_ADDRESS_COST
9931 #define TARGET_ADDRESS_COST s390_address_cost
9932
9933 #undef TARGET_MACHINE_DEPENDENT_REORG
9934 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9935
9936 #undef TARGET_VALID_POINTER_MODE
9937 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9938
9939 #undef TARGET_BUILD_BUILTIN_VA_LIST
9940 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9941 #undef TARGET_EXPAND_BUILTIN_VA_START
9942 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
9943 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9944 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9945
9946 #undef TARGET_PROMOTE_FUNCTION_ARGS
9947 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
9948 #undef TARGET_PROMOTE_FUNCTION_RETURN
9949 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
9950 #undef TARGET_PASS_BY_REFERENCE
9951 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9952
9953 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9954 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9955
9956 #undef TARGET_FIXED_CONDITION_CODE_REGS
9957 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9958
9959 #undef TARGET_CC_MODES_COMPATIBLE
9960 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9961
9962 #undef TARGET_INVALID_WITHIN_DOLOOP
9963 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
9964
9965 #ifdef HAVE_AS_TLS
9966 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9967 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9968 #endif
9969
9970 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9971 #undef TARGET_MANGLE_TYPE
9972 #define TARGET_MANGLE_TYPE s390_mangle_type
9973 #endif
9974
9975 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9976 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9977
9978 #undef TARGET_SECONDARY_RELOAD
9979 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
9980
9981 #undef TARGET_LIBGCC_CMP_RETURN_MODE
9982 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
9983
9984 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
9985 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
9986
9987 #undef TARGET_LEGITIMATE_ADDRESS_P
9988 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
9989
9990 struct gcc_target targetm = TARGET_INITIALIZER;
9991
9992 #include "gt-s390.h"