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s390.c (override_options): Default max-unrolled-insns to 100 for z10 tuning.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55 #include "params.h"
56
57
58 /* Define the specific costs for a given cpu. */
59
60 struct processor_costs
61 {
62 /* multiplication */
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
76 const int mxbr;
77 /* square root */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
84 /* division */
85 const int dxbr;
86 const int ddbr;
87 const int debr;
88 const int dlgr;
89 const int dlr;
90 const int dr;
91 const int dsgfr;
92 const int dsgr;
93 };
94
95 const struct processor_costs *s390_cost;
96
97 static const
98 struct processor_costs z900_cost =
99 {
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
127 };
128
129 static const
130 struct processor_costs z990_cost =
131 {
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
159 };
160
161 static const
162 struct processor_costs z9_109_cost =
163 {
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
191 };
192
193 static const
194 struct processor_costs z10_cost =
195 {
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (10), /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (10), /* MADBR */
214 COSTS_N_INSNS (10), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
223 };
224
225 extern int reload_completed;
226
227 /* Structure used to hold the components of a S/390 memory
228 address. A legitimate address on S/390 is of the general
229 form
230 base + index + displacement
231 where any of the components is optional.
232
233 base and index are registers of the class ADDR_REGS,
234 displacement is an unsigned 12-bit immediate constant. */
235
236 struct s390_address
237 {
238 rtx base;
239 rtx indx;
240 rtx disp;
241 bool pointer;
242 bool literal_pool;
243 };
244
245 /* Which cpu are we tuning for. */
246 enum processor_type s390_tune = PROCESSOR_max;
247 int s390_tune_flags;
248 /* Which instruction set architecture to use. */
249 enum processor_type s390_arch;
250 int s390_arch_flags;
251
252 HOST_WIDE_INT s390_warn_framesize = 0;
253 HOST_WIDE_INT s390_stack_size = 0;
254 HOST_WIDE_INT s390_stack_guard = 0;
255
256 /* The following structure is embedded in the machine
257 specific part of struct function. */
258
259 struct GTY (()) s390_frame_layout
260 {
261 /* Offset within stack frame. */
262 HOST_WIDE_INT gprs_offset;
263 HOST_WIDE_INT f0_offset;
264 HOST_WIDE_INT f4_offset;
265 HOST_WIDE_INT f8_offset;
266 HOST_WIDE_INT backchain_offset;
267
268 /* Number of first and last gpr where slots in the register
269 save area are reserved for. */
270 int first_save_gpr_slot;
271 int last_save_gpr_slot;
272
273 /* Number of first and last gpr to be saved, restored. */
274 int first_save_gpr;
275 int first_restore_gpr;
276 int last_save_gpr;
277 int last_restore_gpr;
278
279 /* Bits standing for floating point registers. Set, if the
280 respective register has to be saved. Starting with reg 16 (f0)
281 at the rightmost bit.
282 Bit 15 - 8 7 6 5 4 3 2 1 0
283 fpr 15 - 8 7 5 3 1 6 4 2 0
284 reg 31 - 24 23 22 21 20 19 18 17 16 */
285 unsigned int fpr_bitmap;
286
287 /* Number of floating point registers f8-f15 which must be saved. */
288 int high_fprs;
289
290 /* Set if return address needs to be saved.
291 This flag is set by s390_return_addr_rtx if it could not use
292 the initial value of r14 and therefore depends on r14 saved
293 to the stack. */
294 bool save_return_addr_p;
295
296 /* Size of stack frame. */
297 HOST_WIDE_INT frame_size;
298 };
299
300 /* Define the structure for the machine field in struct function. */
301
302 struct GTY(()) machine_function
303 {
304 struct s390_frame_layout frame_layout;
305
306 /* Literal pool base register. */
307 rtx base_reg;
308
309 /* True if we may need to perform branch splitting. */
310 bool split_branches_pending_p;
311
312 /* Some local-dynamic TLS symbol name. */
313 const char *some_ld_name;
314
315 bool has_landing_pad_p;
316 };
317
318 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
319
320 #define cfun_frame_layout (cfun->machine->frame_layout)
321 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
322 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
323 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
324 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
325 (1 << (BITNUM)))
326 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
327 (1 << (BITNUM))))
328
329 /* Number of GPRs and FPRs used for argument passing. */
330 #define GP_ARG_NUM_REG 5
331 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
332
333 /* A couple of shortcuts. */
334 #define CONST_OK_FOR_J(x) \
335 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
336 #define CONST_OK_FOR_K(x) \
337 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
338 #define CONST_OK_FOR_Os(x) \
339 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
340 #define CONST_OK_FOR_Op(x) \
341 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
342 #define CONST_OK_FOR_On(x) \
343 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
344
345 #define REGNO_PAIR_OK(REGNO, MODE) \
346 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
347
348 static enum machine_mode
349 s390_libgcc_cmp_return_mode (void)
350 {
351 return TARGET_64BIT ? DImode : SImode;
352 }
353
354 static enum machine_mode
355 s390_libgcc_shift_count_mode (void)
356 {
357 return TARGET_64BIT ? DImode : SImode;
358 }
359
360 /* Return true if the back end supports mode MODE. */
361 static bool
362 s390_scalar_mode_supported_p (enum machine_mode mode)
363 {
364 if (DECIMAL_FLOAT_MODE_P (mode))
365 return true;
366 else
367 return default_scalar_mode_supported_p (mode);
368 }
369
370 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
371
372 void
373 s390_set_has_landing_pad_p (bool value)
374 {
375 cfun->machine->has_landing_pad_p = value;
376 }
377
378 /* If two condition code modes are compatible, return a condition code
379 mode which is compatible with both. Otherwise, return
380 VOIDmode. */
381
382 static enum machine_mode
383 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
384 {
385 if (m1 == m2)
386 return m1;
387
388 switch (m1)
389 {
390 case CCZmode:
391 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
392 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
393 return m2;
394 return VOIDmode;
395
396 case CCSmode:
397 case CCUmode:
398 case CCTmode:
399 case CCSRmode:
400 case CCURmode:
401 case CCZ1mode:
402 if (m2 == CCZmode)
403 return m1;
404
405 return VOIDmode;
406
407 default:
408 return VOIDmode;
409 }
410 return VOIDmode;
411 }
412
413 /* Return true if SET either doesn't set the CC register, or else
414 the source and destination have matching CC modes and that
415 CC mode is at least as constrained as REQ_MODE. */
416
417 static bool
418 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
419 {
420 enum machine_mode set_mode;
421
422 gcc_assert (GET_CODE (set) == SET);
423
424 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
425 return 1;
426
427 set_mode = GET_MODE (SET_DEST (set));
428 switch (set_mode)
429 {
430 case CCSmode:
431 case CCSRmode:
432 case CCUmode:
433 case CCURmode:
434 case CCLmode:
435 case CCL1mode:
436 case CCL2mode:
437 case CCL3mode:
438 case CCT1mode:
439 case CCT2mode:
440 case CCT3mode:
441 if (req_mode != set_mode)
442 return 0;
443 break;
444
445 case CCZmode:
446 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
447 && req_mode != CCSRmode && req_mode != CCURmode)
448 return 0;
449 break;
450
451 case CCAPmode:
452 case CCANmode:
453 if (req_mode != CCAmode)
454 return 0;
455 break;
456
457 default:
458 gcc_unreachable ();
459 }
460
461 return (GET_MODE (SET_SRC (set)) == set_mode);
462 }
463
464 /* Return true if every SET in INSN that sets the CC register
465 has source and destination with matching CC modes and that
466 CC mode is at least as constrained as REQ_MODE.
467 If REQ_MODE is VOIDmode, always return false. */
468
469 bool
470 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
471 {
472 int i;
473
474 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
475 if (req_mode == VOIDmode)
476 return false;
477
478 if (GET_CODE (PATTERN (insn)) == SET)
479 return s390_match_ccmode_set (PATTERN (insn), req_mode);
480
481 if (GET_CODE (PATTERN (insn)) == PARALLEL)
482 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
483 {
484 rtx set = XVECEXP (PATTERN (insn), 0, i);
485 if (GET_CODE (set) == SET)
486 if (!s390_match_ccmode_set (set, req_mode))
487 return false;
488 }
489
490 return true;
491 }
492
493 /* If a test-under-mask instruction can be used to implement
494 (compare (and ... OP1) OP2), return the CC mode required
495 to do that. Otherwise, return VOIDmode.
496 MIXED is true if the instruction can distinguish between
497 CC1 and CC2 for mixed selected bits (TMxx), it is false
498 if the instruction cannot (TM). */
499
500 enum machine_mode
501 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
502 {
503 int bit0, bit1;
504
505 /* ??? Fixme: should work on CONST_DOUBLE as well. */
506 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
507 return VOIDmode;
508
509 /* Selected bits all zero: CC0.
510 e.g.: int a; if ((a & (16 + 128)) == 0) */
511 if (INTVAL (op2) == 0)
512 return CCTmode;
513
514 /* Selected bits all one: CC3.
515 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
516 if (INTVAL (op2) == INTVAL (op1))
517 return CCT3mode;
518
519 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
520 int a;
521 if ((a & (16 + 128)) == 16) -> CCT1
522 if ((a & (16 + 128)) == 128) -> CCT2 */
523 if (mixed)
524 {
525 bit1 = exact_log2 (INTVAL (op2));
526 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
527 if (bit0 != -1 && bit1 != -1)
528 return bit0 > bit1 ? CCT1mode : CCT2mode;
529 }
530
531 return VOIDmode;
532 }
533
534 /* Given a comparison code OP (EQ, NE, etc.) and the operands
535 OP0 and OP1 of a COMPARE, return the mode to be used for the
536 comparison. */
537
538 enum machine_mode
539 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
540 {
541 switch (code)
542 {
543 case EQ:
544 case NE:
545 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
546 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
547 return CCAPmode;
548 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
549 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
550 return CCAPmode;
551 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
552 || GET_CODE (op1) == NEG)
553 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
554 return CCLmode;
555
556 if (GET_CODE (op0) == AND)
557 {
558 /* Check whether we can potentially do it via TM. */
559 enum machine_mode ccmode;
560 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
561 if (ccmode != VOIDmode)
562 {
563 /* Relax CCTmode to CCZmode to allow fall-back to AND
564 if that turns out to be beneficial. */
565 return ccmode == CCTmode ? CCZmode : ccmode;
566 }
567 }
568
569 if (register_operand (op0, HImode)
570 && GET_CODE (op1) == CONST_INT
571 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
572 return CCT3mode;
573 if (register_operand (op0, QImode)
574 && GET_CODE (op1) == CONST_INT
575 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
576 return CCT3mode;
577
578 return CCZmode;
579
580 case LE:
581 case LT:
582 case GE:
583 case GT:
584 /* The only overflow condition of NEG and ABS happens when
585 -INT_MAX is used as parameter, which stays negative. So
586 we have an overflow from a positive value to a negative.
587 Using CCAP mode the resulting cc can be used for comparisons. */
588 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
589 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
590 return CCAPmode;
591
592 /* If constants are involved in an add instruction it is possible to use
593 the resulting cc for comparisons with zero. Knowing the sign of the
594 constant the overflow behavior gets predictable. e.g.:
595 int a, b; if ((b = a + c) > 0)
596 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
597 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
598 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
599 {
600 if (INTVAL (XEXP((op0), 1)) < 0)
601 return CCANmode;
602 else
603 return CCAPmode;
604 }
605 /* Fall through. */
606 case UNORDERED:
607 case ORDERED:
608 case UNEQ:
609 case UNLE:
610 case UNLT:
611 case UNGE:
612 case UNGT:
613 case LTGT:
614 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
615 && GET_CODE (op1) != CONST_INT)
616 return CCSRmode;
617 return CCSmode;
618
619 case LTU:
620 case GEU:
621 if (GET_CODE (op0) == PLUS
622 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
623 return CCL1mode;
624
625 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
626 && GET_CODE (op1) != CONST_INT)
627 return CCURmode;
628 return CCUmode;
629
630 case LEU:
631 case GTU:
632 if (GET_CODE (op0) == MINUS
633 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
634 return CCL2mode;
635
636 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
637 && GET_CODE (op1) != CONST_INT)
638 return CCURmode;
639 return CCUmode;
640
641 default:
642 gcc_unreachable ();
643 }
644 }
645
646 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
647 that we can implement more efficiently. */
648
649 void
650 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
651 {
652 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
653 if ((*code == EQ || *code == NE)
654 && *op1 == const0_rtx
655 && GET_CODE (*op0) == ZERO_EXTRACT
656 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
657 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
658 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
659 {
660 rtx inner = XEXP (*op0, 0);
661 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
662 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
663 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
664
665 if (len > 0 && len < modesize
666 && pos >= 0 && pos + len <= modesize
667 && modesize <= HOST_BITS_PER_WIDE_INT)
668 {
669 unsigned HOST_WIDE_INT block;
670 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
671 block <<= modesize - pos - len;
672
673 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
674 gen_int_mode (block, GET_MODE (inner)));
675 }
676 }
677
678 /* Narrow AND of memory against immediate to enable TM. */
679 if ((*code == EQ || *code == NE)
680 && *op1 == const0_rtx
681 && GET_CODE (*op0) == AND
682 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
683 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
684 {
685 rtx inner = XEXP (*op0, 0);
686 rtx mask = XEXP (*op0, 1);
687
688 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
689 if (GET_CODE (inner) == SUBREG
690 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
691 && (GET_MODE_SIZE (GET_MODE (inner))
692 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
693 && ((INTVAL (mask)
694 & GET_MODE_MASK (GET_MODE (inner))
695 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
696 == 0))
697 inner = SUBREG_REG (inner);
698
699 /* Do not change volatile MEMs. */
700 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
701 {
702 int part = s390_single_part (XEXP (*op0, 1),
703 GET_MODE (inner), QImode, 0);
704 if (part >= 0)
705 {
706 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
707 inner = adjust_address_nv (inner, QImode, part);
708 *op0 = gen_rtx_AND (QImode, inner, mask);
709 }
710 }
711 }
712
713 /* Narrow comparisons against 0xffff to HImode if possible. */
714 if ((*code == EQ || *code == NE)
715 && GET_CODE (*op1) == CONST_INT
716 && INTVAL (*op1) == 0xffff
717 && SCALAR_INT_MODE_P (GET_MODE (*op0))
718 && (nonzero_bits (*op0, GET_MODE (*op0))
719 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
720 {
721 *op0 = gen_lowpart (HImode, *op0);
722 *op1 = constm1_rtx;
723 }
724
725 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
726 if (GET_CODE (*op0) == UNSPEC
727 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
728 && XVECLEN (*op0, 0) == 1
729 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
730 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
731 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
732 && *op1 == const0_rtx)
733 {
734 enum rtx_code new_code = UNKNOWN;
735 switch (*code)
736 {
737 case EQ: new_code = EQ; break;
738 case NE: new_code = NE; break;
739 case LT: new_code = GTU; break;
740 case GT: new_code = LTU; break;
741 case LE: new_code = GEU; break;
742 case GE: new_code = LEU; break;
743 default: break;
744 }
745
746 if (new_code != UNKNOWN)
747 {
748 *op0 = XVECEXP (*op0, 0, 0);
749 *code = new_code;
750 }
751 }
752
753 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
754 if (GET_CODE (*op0) == UNSPEC
755 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
756 && XVECLEN (*op0, 0) == 1
757 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
758 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
759 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
760 && *op1 == const0_rtx)
761 {
762 enum rtx_code new_code = UNKNOWN;
763 switch (*code)
764 {
765 case EQ: new_code = EQ; break;
766 case NE: new_code = NE; break;
767 default: break;
768 }
769
770 if (new_code != UNKNOWN)
771 {
772 *op0 = XVECEXP (*op0, 0, 0);
773 *code = new_code;
774 }
775 }
776
777 /* Simplify cascaded EQ, NE with const0_rtx. */
778 if ((*code == NE || *code == EQ)
779 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
780 && GET_MODE (*op0) == SImode
781 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
782 && REG_P (XEXP (*op0, 0))
783 && XEXP (*op0, 1) == const0_rtx
784 && *op1 == const0_rtx)
785 {
786 if ((*code == EQ && GET_CODE (*op0) == NE)
787 || (*code == NE && GET_CODE (*op0) == EQ))
788 *code = EQ;
789 else
790 *code = NE;
791 *op0 = XEXP (*op0, 0);
792 }
793
794 /* Prefer register over memory as first operand. */
795 if (MEM_P (*op0) && REG_P (*op1))
796 {
797 rtx tem = *op0; *op0 = *op1; *op1 = tem;
798 *code = swap_condition (*code);
799 }
800 }
801
802 /* Emit a compare instruction suitable to implement the comparison
803 OP0 CODE OP1. Return the correct condition RTL to be placed in
804 the IF_THEN_ELSE of the conditional branch testing the result. */
805
806 rtx
807 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
808 {
809 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
810 rtx cc;
811
812 /* Do not output a redundant compare instruction if a compare_and_swap
813 pattern already computed the result and the machine modes are compatible. */
814 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
815 {
816 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
817 == GET_MODE (op0));
818 cc = op0;
819 }
820 else
821 {
822 cc = gen_rtx_REG (mode, CC_REGNUM);
823 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
824 }
825
826 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
827 }
828
829 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
830 matches CMP.
831 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
832 conditional branch testing the result. */
833
834 static rtx
835 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
836 {
837 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
838 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
839 }
840
841 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
842 unconditional jump, else a conditional jump under condition COND. */
843
844 void
845 s390_emit_jump (rtx target, rtx cond)
846 {
847 rtx insn;
848
849 target = gen_rtx_LABEL_REF (VOIDmode, target);
850 if (cond)
851 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
852
853 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
854 emit_jump_insn (insn);
855 }
856
857 /* Return branch condition mask to implement a branch
858 specified by CODE. Return -1 for invalid comparisons. */
859
860 int
861 s390_branch_condition_mask (rtx code)
862 {
863 const int CC0 = 1 << 3;
864 const int CC1 = 1 << 2;
865 const int CC2 = 1 << 1;
866 const int CC3 = 1 << 0;
867
868 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
869 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
870 gcc_assert (XEXP (code, 1) == const0_rtx);
871
872 switch (GET_MODE (XEXP (code, 0)))
873 {
874 case CCZmode:
875 case CCZ1mode:
876 switch (GET_CODE (code))
877 {
878 case EQ: return CC0;
879 case NE: return CC1 | CC2 | CC3;
880 default: return -1;
881 }
882 break;
883
884 case CCT1mode:
885 switch (GET_CODE (code))
886 {
887 case EQ: return CC1;
888 case NE: return CC0 | CC2 | CC3;
889 default: return -1;
890 }
891 break;
892
893 case CCT2mode:
894 switch (GET_CODE (code))
895 {
896 case EQ: return CC2;
897 case NE: return CC0 | CC1 | CC3;
898 default: return -1;
899 }
900 break;
901
902 case CCT3mode:
903 switch (GET_CODE (code))
904 {
905 case EQ: return CC3;
906 case NE: return CC0 | CC1 | CC2;
907 default: return -1;
908 }
909 break;
910
911 case CCLmode:
912 switch (GET_CODE (code))
913 {
914 case EQ: return CC0 | CC2;
915 case NE: return CC1 | CC3;
916 default: return -1;
917 }
918 break;
919
920 case CCL1mode:
921 switch (GET_CODE (code))
922 {
923 case LTU: return CC2 | CC3; /* carry */
924 case GEU: return CC0 | CC1; /* no carry */
925 default: return -1;
926 }
927 break;
928
929 case CCL2mode:
930 switch (GET_CODE (code))
931 {
932 case GTU: return CC0 | CC1; /* borrow */
933 case LEU: return CC2 | CC3; /* no borrow */
934 default: return -1;
935 }
936 break;
937
938 case CCL3mode:
939 switch (GET_CODE (code))
940 {
941 case EQ: return CC0 | CC2;
942 case NE: return CC1 | CC3;
943 case LTU: return CC1;
944 case GTU: return CC3;
945 case LEU: return CC1 | CC2;
946 case GEU: return CC2 | CC3;
947 default: return -1;
948 }
949
950 case CCUmode:
951 switch (GET_CODE (code))
952 {
953 case EQ: return CC0;
954 case NE: return CC1 | CC2 | CC3;
955 case LTU: return CC1;
956 case GTU: return CC2;
957 case LEU: return CC0 | CC1;
958 case GEU: return CC0 | CC2;
959 default: return -1;
960 }
961 break;
962
963 case CCURmode:
964 switch (GET_CODE (code))
965 {
966 case EQ: return CC0;
967 case NE: return CC2 | CC1 | CC3;
968 case LTU: return CC2;
969 case GTU: return CC1;
970 case LEU: return CC0 | CC2;
971 case GEU: return CC0 | CC1;
972 default: return -1;
973 }
974 break;
975
976 case CCAPmode:
977 switch (GET_CODE (code))
978 {
979 case EQ: return CC0;
980 case NE: return CC1 | CC2 | CC3;
981 case LT: return CC1 | CC3;
982 case GT: return CC2;
983 case LE: return CC0 | CC1 | CC3;
984 case GE: return CC0 | CC2;
985 default: return -1;
986 }
987 break;
988
989 case CCANmode:
990 switch (GET_CODE (code))
991 {
992 case EQ: return CC0;
993 case NE: return CC1 | CC2 | CC3;
994 case LT: return CC1;
995 case GT: return CC2 | CC3;
996 case LE: return CC0 | CC1;
997 case GE: return CC0 | CC2 | CC3;
998 default: return -1;
999 }
1000 break;
1001
1002 case CCSmode:
1003 switch (GET_CODE (code))
1004 {
1005 case EQ: return CC0;
1006 case NE: return CC1 | CC2 | CC3;
1007 case LT: return CC1;
1008 case GT: return CC2;
1009 case LE: return CC0 | CC1;
1010 case GE: return CC0 | CC2;
1011 case UNORDERED: return CC3;
1012 case ORDERED: return CC0 | CC1 | CC2;
1013 case UNEQ: return CC0 | CC3;
1014 case UNLT: return CC1 | CC3;
1015 case UNGT: return CC2 | CC3;
1016 case UNLE: return CC0 | CC1 | CC3;
1017 case UNGE: return CC0 | CC2 | CC3;
1018 case LTGT: return CC1 | CC2;
1019 default: return -1;
1020 }
1021 break;
1022
1023 case CCSRmode:
1024 switch (GET_CODE (code))
1025 {
1026 case EQ: return CC0;
1027 case NE: return CC2 | CC1 | CC3;
1028 case LT: return CC2;
1029 case GT: return CC1;
1030 case LE: return CC0 | CC2;
1031 case GE: return CC0 | CC1;
1032 case UNORDERED: return CC3;
1033 case ORDERED: return CC0 | CC2 | CC1;
1034 case UNEQ: return CC0 | CC3;
1035 case UNLT: return CC2 | CC3;
1036 case UNGT: return CC1 | CC3;
1037 case UNLE: return CC0 | CC2 | CC3;
1038 case UNGE: return CC0 | CC1 | CC3;
1039 case LTGT: return CC2 | CC1;
1040 default: return -1;
1041 }
1042 break;
1043
1044 default:
1045 return -1;
1046 }
1047 }
1048
1049
1050 /* Return branch condition mask to implement a compare and branch
1051 specified by CODE. Return -1 for invalid comparisons. */
1052
1053 int
1054 s390_compare_and_branch_condition_mask (rtx code)
1055 {
1056 const int CC0 = 1 << 3;
1057 const int CC1 = 1 << 2;
1058 const int CC2 = 1 << 1;
1059
1060 switch (GET_CODE (code))
1061 {
1062 case EQ:
1063 return CC0;
1064 case NE:
1065 return CC1 | CC2;
1066 case LT:
1067 case LTU:
1068 return CC1;
1069 case GT:
1070 case GTU:
1071 return CC2;
1072 case LE:
1073 case LEU:
1074 return CC0 | CC1;
1075 case GE:
1076 case GEU:
1077 return CC0 | CC2;
1078 default:
1079 gcc_unreachable ();
1080 }
1081 return -1;
1082 }
1083
1084 /* If INV is false, return assembler mnemonic string to implement
1085 a branch specified by CODE. If INV is true, return mnemonic
1086 for the corresponding inverted branch. */
1087
1088 static const char *
1089 s390_branch_condition_mnemonic (rtx code, int inv)
1090 {
1091 int mask;
1092
1093 static const char *const mnemonic[16] =
1094 {
1095 NULL, "o", "h", "nle",
1096 "l", "nhe", "lh", "ne",
1097 "e", "nlh", "he", "nl",
1098 "le", "nh", "no", NULL
1099 };
1100
1101 if (GET_CODE (XEXP (code, 0)) == REG
1102 && REGNO (XEXP (code, 0)) == CC_REGNUM
1103 && XEXP (code, 1) == const0_rtx)
1104 mask = s390_branch_condition_mask (code);
1105 else
1106 mask = s390_compare_and_branch_condition_mask (code);
1107
1108 gcc_assert (mask >= 0);
1109
1110 if (inv)
1111 mask ^= 15;
1112
1113 gcc_assert (mask >= 1 && mask <= 14);
1114
1115 return mnemonic[mask];
1116 }
1117
1118 /* Return the part of op which has a value different from def.
1119 The size of the part is determined by mode.
1120 Use this function only if you already know that op really
1121 contains such a part. */
1122
1123 unsigned HOST_WIDE_INT
1124 s390_extract_part (rtx op, enum machine_mode mode, int def)
1125 {
1126 unsigned HOST_WIDE_INT value = 0;
1127 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1128 int part_bits = GET_MODE_BITSIZE (mode);
1129 unsigned HOST_WIDE_INT part_mask
1130 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1131 int i;
1132
1133 for (i = 0; i < max_parts; i++)
1134 {
1135 if (i == 0)
1136 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1137 else
1138 value >>= part_bits;
1139
1140 if ((value & part_mask) != (def & part_mask))
1141 return value & part_mask;
1142 }
1143
1144 gcc_unreachable ();
1145 }
1146
1147 /* If OP is an integer constant of mode MODE with exactly one
1148 part of mode PART_MODE unequal to DEF, return the number of that
1149 part. Otherwise, return -1. */
1150
1151 int
1152 s390_single_part (rtx op,
1153 enum machine_mode mode,
1154 enum machine_mode part_mode,
1155 int def)
1156 {
1157 unsigned HOST_WIDE_INT value = 0;
1158 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1159 unsigned HOST_WIDE_INT part_mask
1160 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1161 int i, part = -1;
1162
1163 if (GET_CODE (op) != CONST_INT)
1164 return -1;
1165
1166 for (i = 0; i < n_parts; i++)
1167 {
1168 if (i == 0)
1169 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1170 else
1171 value >>= GET_MODE_BITSIZE (part_mode);
1172
1173 if ((value & part_mask) != (def & part_mask))
1174 {
1175 if (part != -1)
1176 return -1;
1177 else
1178 part = i;
1179 }
1180 }
1181 return part == -1 ? -1 : n_parts - 1 - part;
1182 }
1183
1184 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1185 bits and no other bits are set in IN. POS and LENGTH can be used
1186 to obtain the start position and the length of the bitfield.
1187
1188 POS gives the position of the first bit of the bitfield counting
1189 from the lowest order bit starting with zero. In order to use this
1190 value for S/390 instructions this has to be converted to "bits big
1191 endian" style. */
1192
1193 bool
1194 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1195 int *pos, int *length)
1196 {
1197 int tmp_pos = 0;
1198 int tmp_length = 0;
1199 int i;
1200 unsigned HOST_WIDE_INT mask = 1ULL;
1201 bool contiguous = false;
1202
1203 for (i = 0; i < size; mask <<= 1, i++)
1204 {
1205 if (contiguous)
1206 {
1207 if (mask & in)
1208 tmp_length++;
1209 else
1210 break;
1211 }
1212 else
1213 {
1214 if (mask & in)
1215 {
1216 contiguous = true;
1217 tmp_length++;
1218 }
1219 else
1220 tmp_pos++;
1221 }
1222 }
1223
1224 if (!tmp_length)
1225 return false;
1226
1227 /* Calculate a mask for all bits beyond the contiguous bits. */
1228 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1229
1230 if (mask & in)
1231 return false;
1232
1233 if (tmp_length + tmp_pos - 1 > size)
1234 return false;
1235
1236 if (length)
1237 *length = tmp_length;
1238
1239 if (pos)
1240 *pos = tmp_pos;
1241
1242 return true;
1243 }
1244
1245 /* Check whether we can (and want to) split a double-word
1246 move in mode MODE from SRC to DST into two single-word
1247 moves, moving the subword FIRST_SUBWORD first. */
1248
1249 bool
1250 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1251 {
1252 /* Floating point registers cannot be split. */
1253 if (FP_REG_P (src) || FP_REG_P (dst))
1254 return false;
1255
1256 /* We don't need to split if operands are directly accessible. */
1257 if (s_operand (src, mode) || s_operand (dst, mode))
1258 return false;
1259
1260 /* Non-offsettable memory references cannot be split. */
1261 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1262 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1263 return false;
1264
1265 /* Moving the first subword must not clobber a register
1266 needed to move the second subword. */
1267 if (register_operand (dst, mode))
1268 {
1269 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1270 if (reg_overlap_mentioned_p (subreg, src))
1271 return false;
1272 }
1273
1274 return true;
1275 }
1276
1277 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1278 and [MEM2, MEM2 + SIZE] do overlap and false
1279 otherwise. */
1280
1281 bool
1282 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1283 {
1284 rtx addr1, addr2, addr_delta;
1285 HOST_WIDE_INT delta;
1286
1287 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1288 return true;
1289
1290 if (size == 0)
1291 return false;
1292
1293 addr1 = XEXP (mem1, 0);
1294 addr2 = XEXP (mem2, 0);
1295
1296 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1297
1298 /* This overlapping check is used by peepholes merging memory block operations.
1299 Overlapping operations would otherwise be recognized by the S/390 hardware
1300 and would fall back to a slower implementation. Allowing overlapping
1301 operations would lead to slow code but not to wrong code. Therefore we are
1302 somewhat optimistic if we cannot prove that the memory blocks are
1303 overlapping.
1304 That's why we return false here although this may accept operations on
1305 overlapping memory areas. */
1306 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1307 return false;
1308
1309 delta = INTVAL (addr_delta);
1310
1311 if (delta == 0
1312 || (delta > 0 && delta < size)
1313 || (delta < 0 && -delta < size))
1314 return true;
1315
1316 return false;
1317 }
1318
1319 /* Check whether the address of memory reference MEM2 equals exactly
1320 the address of memory reference MEM1 plus DELTA. Return true if
1321 we can prove this to be the case, false otherwise. */
1322
1323 bool
1324 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1325 {
1326 rtx addr1, addr2, addr_delta;
1327
1328 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1329 return false;
1330
1331 addr1 = XEXP (mem1, 0);
1332 addr2 = XEXP (mem2, 0);
1333
1334 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1335 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1336 return false;
1337
1338 return true;
1339 }
1340
1341 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1342
1343 void
1344 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1345 rtx *operands)
1346 {
1347 enum machine_mode wmode = mode;
1348 rtx dst = operands[0];
1349 rtx src1 = operands[1];
1350 rtx src2 = operands[2];
1351 rtx op, clob, tem;
1352
1353 /* If we cannot handle the operation directly, use a temp register. */
1354 if (!s390_logical_operator_ok_p (operands))
1355 dst = gen_reg_rtx (mode);
1356
1357 /* QImode and HImode patterns make sense only if we have a destination
1358 in memory. Otherwise perform the operation in SImode. */
1359 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1360 wmode = SImode;
1361
1362 /* Widen operands if required. */
1363 if (mode != wmode)
1364 {
1365 if (GET_CODE (dst) == SUBREG
1366 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1367 dst = tem;
1368 else if (REG_P (dst))
1369 dst = gen_rtx_SUBREG (wmode, dst, 0);
1370 else
1371 dst = gen_reg_rtx (wmode);
1372
1373 if (GET_CODE (src1) == SUBREG
1374 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1375 src1 = tem;
1376 else if (GET_MODE (src1) != VOIDmode)
1377 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1378
1379 if (GET_CODE (src2) == SUBREG
1380 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1381 src2 = tem;
1382 else if (GET_MODE (src2) != VOIDmode)
1383 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1384 }
1385
1386 /* Emit the instruction. */
1387 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1388 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1389 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1390
1391 /* Fix up the destination if needed. */
1392 if (dst != operands[0])
1393 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1394 }
1395
1396 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1397
1398 bool
1399 s390_logical_operator_ok_p (rtx *operands)
1400 {
1401 /* If the destination operand is in memory, it needs to coincide
1402 with one of the source operands. After reload, it has to be
1403 the first source operand. */
1404 if (GET_CODE (operands[0]) == MEM)
1405 return rtx_equal_p (operands[0], operands[1])
1406 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1407
1408 return true;
1409 }
1410
1411 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1412 operand IMMOP to switch from SS to SI type instructions. */
1413
1414 void
1415 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1416 {
1417 int def = code == AND ? -1 : 0;
1418 HOST_WIDE_INT mask;
1419 int part;
1420
1421 gcc_assert (GET_CODE (*memop) == MEM);
1422 gcc_assert (!MEM_VOLATILE_P (*memop));
1423
1424 mask = s390_extract_part (*immop, QImode, def);
1425 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1426 gcc_assert (part >= 0);
1427
1428 *memop = adjust_address (*memop, QImode, part);
1429 *immop = gen_int_mode (mask, QImode);
1430 }
1431
1432
1433 /* How to allocate a 'struct machine_function'. */
1434
1435 static struct machine_function *
1436 s390_init_machine_status (void)
1437 {
1438 return GGC_CNEW (struct machine_function);
1439 }
1440
1441 /* Change optimizations to be performed, depending on the
1442 optimization level.
1443
1444 LEVEL is the optimization level specified; 2 if `-O2' is
1445 specified, 1 if `-O' is specified, and 0 if neither is specified.
1446
1447 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1448
1449 void
1450 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1451 {
1452 /* ??? There are apparently still problems with -fcaller-saves. */
1453 flag_caller_saves = 0;
1454
1455 /* By default, always emit DWARF-2 unwind info. This allows debugging
1456 without maintaining a stack frame back-chain. */
1457 flag_asynchronous_unwind_tables = 1;
1458
1459 /* Use MVCLE instructions to decrease code size if requested. */
1460 if (size != 0)
1461 target_flags |= MASK_MVCLE;
1462 }
1463
1464 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1465 to the associated processor_type and processor_flags if so. */
1466
1467 static bool
1468 s390_handle_arch_option (const char *arg,
1469 enum processor_type *type,
1470 int *flags)
1471 {
1472 static struct pta
1473 {
1474 const char *const name; /* processor name or nickname. */
1475 const enum processor_type processor;
1476 const int flags; /* From enum processor_flags. */
1477 }
1478 const processor_alias_table[] =
1479 {
1480 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1481 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1482 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1483 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1484 | PF_LONG_DISPLACEMENT},
1485 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1486 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1487 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1488 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1489 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1490 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1491 };
1492 size_t i;
1493
1494 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1495 if (strcmp (arg, processor_alias_table[i].name) == 0)
1496 {
1497 *type = processor_alias_table[i].processor;
1498 *flags = processor_alias_table[i].flags;
1499 return true;
1500 }
1501 return false;
1502 }
1503
1504 /* Implement TARGET_HANDLE_OPTION. */
1505
1506 static bool
1507 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1508 {
1509 switch (code)
1510 {
1511 case OPT_march_:
1512 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1513
1514 case OPT_mstack_guard_:
1515 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1516 return false;
1517 if (exact_log2 (s390_stack_guard) == -1)
1518 error ("stack guard value must be an exact power of 2");
1519 return true;
1520
1521 case OPT_mstack_size_:
1522 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1523 return false;
1524 if (exact_log2 (s390_stack_size) == -1)
1525 error ("stack size must be an exact power of 2");
1526 return true;
1527
1528 case OPT_mtune_:
1529 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1530
1531 case OPT_mwarn_framesize_:
1532 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1533
1534 default:
1535 return true;
1536 }
1537 }
1538
1539 void
1540 override_options (void)
1541 {
1542 /* Set up function hooks. */
1543 init_machine_status = s390_init_machine_status;
1544
1545 /* Architecture mode defaults according to ABI. */
1546 if (!(target_flags_explicit & MASK_ZARCH))
1547 {
1548 if (TARGET_64BIT)
1549 target_flags |= MASK_ZARCH;
1550 else
1551 target_flags &= ~MASK_ZARCH;
1552 }
1553
1554 /* Determine processor architectural level. */
1555 if (!s390_arch_string)
1556 {
1557 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1558 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1559 }
1560
1561 /* Determine processor to tune for. */
1562 if (s390_tune == PROCESSOR_max)
1563 {
1564 s390_tune = s390_arch;
1565 s390_tune_flags = s390_arch_flags;
1566 }
1567
1568 /* Sanity checks. */
1569 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1570 error ("z/Architecture mode not supported on %s", s390_arch_string);
1571 if (TARGET_64BIT && !TARGET_ZARCH)
1572 error ("64-bit ABI not supported in ESA/390 mode");
1573
1574 if (TARGET_HARD_DFP && !TARGET_DFP)
1575 {
1576 if (target_flags_explicit & MASK_HARD_DFP)
1577 {
1578 if (!TARGET_CPU_DFP)
1579 error ("Hardware decimal floating point instructions"
1580 " not available on %s", s390_arch_string);
1581 if (!TARGET_ZARCH)
1582 error ("Hardware decimal floating point instructions"
1583 " not available in ESA/390 mode");
1584 }
1585 else
1586 target_flags &= ~MASK_HARD_DFP;
1587 }
1588
1589 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1590 {
1591 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1592 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1593
1594 target_flags &= ~MASK_HARD_DFP;
1595 }
1596
1597 /* Set processor cost function. */
1598 switch (s390_tune)
1599 {
1600 case PROCESSOR_2084_Z990:
1601 s390_cost = &z990_cost;
1602 break;
1603 case PROCESSOR_2094_Z9_109:
1604 s390_cost = &z9_109_cost;
1605 break;
1606 case PROCESSOR_2097_Z10:
1607 s390_cost = &z10_cost;
1608 break;
1609 default:
1610 s390_cost = &z900_cost;
1611 }
1612
1613 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1614 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1615 "in combination");
1616
1617 if (s390_stack_size)
1618 {
1619 if (s390_stack_guard >= s390_stack_size)
1620 error ("stack size must be greater than the stack guard value");
1621 else if (s390_stack_size > 1 << 16)
1622 error ("stack size must not be greater than 64k");
1623 }
1624 else if (s390_stack_guard)
1625 error ("-mstack-guard implies use of -mstack-size");
1626
1627 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1628 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1629 target_flags |= MASK_LONG_DOUBLE_128;
1630 #endif
1631
1632 if (s390_tune == PROCESSOR_2097_Z10
1633 && !PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
1634 set_param_value ("max-unrolled-insns", 100);
1635 }
1636
1637 /* Map for smallest class containing reg regno. */
1638
1639 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1640 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1641 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1642 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1643 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1644 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1645 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1646 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1647 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1648 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1649 ACCESS_REGS, ACCESS_REGS
1650 };
1651
1652 /* Return attribute type of insn. */
1653
1654 static enum attr_type
1655 s390_safe_attr_type (rtx insn)
1656 {
1657 if (recog_memoized (insn) >= 0)
1658 return get_attr_type (insn);
1659 else
1660 return TYPE_NONE;
1661 }
1662
1663 /* Return true if DISP is a valid short displacement. */
1664
1665 static bool
1666 s390_short_displacement (rtx disp)
1667 {
1668 /* No displacement is OK. */
1669 if (!disp)
1670 return true;
1671
1672 /* Without the long displacement facility we don't need to
1673 distingiush between long and short displacement. */
1674 if (!TARGET_LONG_DISPLACEMENT)
1675 return true;
1676
1677 /* Integer displacement in range. */
1678 if (GET_CODE (disp) == CONST_INT)
1679 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1680
1681 /* GOT offset is not OK, the GOT can be large. */
1682 if (GET_CODE (disp) == CONST
1683 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1684 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1685 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1686 return false;
1687
1688 /* All other symbolic constants are literal pool references,
1689 which are OK as the literal pool must be small. */
1690 if (GET_CODE (disp) == CONST)
1691 return true;
1692
1693 return false;
1694 }
1695
1696 /* Decompose a RTL expression ADDR for a memory address into
1697 its components, returned in OUT.
1698
1699 Returns false if ADDR is not a valid memory address, true
1700 otherwise. If OUT is NULL, don't return the components,
1701 but check for validity only.
1702
1703 Note: Only addresses in canonical form are recognized.
1704 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1705 canonical form so that they will be recognized. */
1706
1707 static int
1708 s390_decompose_address (rtx addr, struct s390_address *out)
1709 {
1710 HOST_WIDE_INT offset = 0;
1711 rtx base = NULL_RTX;
1712 rtx indx = NULL_RTX;
1713 rtx disp = NULL_RTX;
1714 rtx orig_disp;
1715 bool pointer = false;
1716 bool base_ptr = false;
1717 bool indx_ptr = false;
1718 bool literal_pool = false;
1719
1720 /* We may need to substitute the literal pool base register into the address
1721 below. However, at this point we do not know which register is going to
1722 be used as base, so we substitute the arg pointer register. This is going
1723 to be treated as holding a pointer below -- it shouldn't be used for any
1724 other purpose. */
1725 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1726
1727 /* Decompose address into base + index + displacement. */
1728
1729 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1730 base = addr;
1731
1732 else if (GET_CODE (addr) == PLUS)
1733 {
1734 rtx op0 = XEXP (addr, 0);
1735 rtx op1 = XEXP (addr, 1);
1736 enum rtx_code code0 = GET_CODE (op0);
1737 enum rtx_code code1 = GET_CODE (op1);
1738
1739 if (code0 == REG || code0 == UNSPEC)
1740 {
1741 if (code1 == REG || code1 == UNSPEC)
1742 {
1743 indx = op0; /* index + base */
1744 base = op1;
1745 }
1746
1747 else
1748 {
1749 base = op0; /* base + displacement */
1750 disp = op1;
1751 }
1752 }
1753
1754 else if (code0 == PLUS)
1755 {
1756 indx = XEXP (op0, 0); /* index + base + disp */
1757 base = XEXP (op0, 1);
1758 disp = op1;
1759 }
1760
1761 else
1762 {
1763 return false;
1764 }
1765 }
1766
1767 else
1768 disp = addr; /* displacement */
1769
1770 /* Extract integer part of displacement. */
1771 orig_disp = disp;
1772 if (disp)
1773 {
1774 if (GET_CODE (disp) == CONST_INT)
1775 {
1776 offset = INTVAL (disp);
1777 disp = NULL_RTX;
1778 }
1779 else if (GET_CODE (disp) == CONST
1780 && GET_CODE (XEXP (disp, 0)) == PLUS
1781 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1782 {
1783 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1784 disp = XEXP (XEXP (disp, 0), 0);
1785 }
1786 }
1787
1788 /* Strip off CONST here to avoid special case tests later. */
1789 if (disp && GET_CODE (disp) == CONST)
1790 disp = XEXP (disp, 0);
1791
1792 /* We can convert literal pool addresses to
1793 displacements by basing them off the base register. */
1794 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1795 {
1796 /* Either base or index must be free to hold the base register. */
1797 if (!base)
1798 base = fake_pool_base, literal_pool = true;
1799 else if (!indx)
1800 indx = fake_pool_base, literal_pool = true;
1801 else
1802 return false;
1803
1804 /* Mark up the displacement. */
1805 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1806 UNSPEC_LTREL_OFFSET);
1807 }
1808
1809 /* Validate base register. */
1810 if (base)
1811 {
1812 if (GET_CODE (base) == UNSPEC)
1813 switch (XINT (base, 1))
1814 {
1815 case UNSPEC_LTREF:
1816 if (!disp)
1817 disp = gen_rtx_UNSPEC (Pmode,
1818 gen_rtvec (1, XVECEXP (base, 0, 0)),
1819 UNSPEC_LTREL_OFFSET);
1820 else
1821 return false;
1822
1823 base = XVECEXP (base, 0, 1);
1824 break;
1825
1826 case UNSPEC_LTREL_BASE:
1827 if (XVECLEN (base, 0) == 1)
1828 base = fake_pool_base, literal_pool = true;
1829 else
1830 base = XVECEXP (base, 0, 1);
1831 break;
1832
1833 default:
1834 return false;
1835 }
1836
1837 if (!REG_P (base)
1838 || (GET_MODE (base) != SImode
1839 && GET_MODE (base) != Pmode))
1840 return false;
1841
1842 if (REGNO (base) == STACK_POINTER_REGNUM
1843 || REGNO (base) == FRAME_POINTER_REGNUM
1844 || ((reload_completed || reload_in_progress)
1845 && frame_pointer_needed
1846 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1847 || REGNO (base) == ARG_POINTER_REGNUM
1848 || (flag_pic
1849 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1850 pointer = base_ptr = true;
1851
1852 if ((reload_completed || reload_in_progress)
1853 && base == cfun->machine->base_reg)
1854 pointer = base_ptr = literal_pool = true;
1855 }
1856
1857 /* Validate index register. */
1858 if (indx)
1859 {
1860 if (GET_CODE (indx) == UNSPEC)
1861 switch (XINT (indx, 1))
1862 {
1863 case UNSPEC_LTREF:
1864 if (!disp)
1865 disp = gen_rtx_UNSPEC (Pmode,
1866 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1867 UNSPEC_LTREL_OFFSET);
1868 else
1869 return false;
1870
1871 indx = XVECEXP (indx, 0, 1);
1872 break;
1873
1874 case UNSPEC_LTREL_BASE:
1875 if (XVECLEN (indx, 0) == 1)
1876 indx = fake_pool_base, literal_pool = true;
1877 else
1878 indx = XVECEXP (indx, 0, 1);
1879 break;
1880
1881 default:
1882 return false;
1883 }
1884
1885 if (!REG_P (indx)
1886 || (GET_MODE (indx) != SImode
1887 && GET_MODE (indx) != Pmode))
1888 return false;
1889
1890 if (REGNO (indx) == STACK_POINTER_REGNUM
1891 || REGNO (indx) == FRAME_POINTER_REGNUM
1892 || ((reload_completed || reload_in_progress)
1893 && frame_pointer_needed
1894 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1895 || REGNO (indx) == ARG_POINTER_REGNUM
1896 || (flag_pic
1897 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1898 pointer = indx_ptr = true;
1899
1900 if ((reload_completed || reload_in_progress)
1901 && indx == cfun->machine->base_reg)
1902 pointer = indx_ptr = literal_pool = true;
1903 }
1904
1905 /* Prefer to use pointer as base, not index. */
1906 if (base && indx && !base_ptr
1907 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1908 {
1909 rtx tmp = base;
1910 base = indx;
1911 indx = tmp;
1912 }
1913
1914 /* Validate displacement. */
1915 if (!disp)
1916 {
1917 /* If virtual registers are involved, the displacement will change later
1918 anyway as the virtual registers get eliminated. This could make a
1919 valid displacement invalid, but it is more likely to make an invalid
1920 displacement valid, because we sometimes access the register save area
1921 via negative offsets to one of those registers.
1922 Thus we don't check the displacement for validity here. If after
1923 elimination the displacement turns out to be invalid after all,
1924 this is fixed up by reload in any case. */
1925 if (base != arg_pointer_rtx
1926 && indx != arg_pointer_rtx
1927 && base != return_address_pointer_rtx
1928 && indx != return_address_pointer_rtx
1929 && base != frame_pointer_rtx
1930 && indx != frame_pointer_rtx
1931 && base != virtual_stack_vars_rtx
1932 && indx != virtual_stack_vars_rtx)
1933 if (!DISP_IN_RANGE (offset))
1934 return false;
1935 }
1936 else
1937 {
1938 /* All the special cases are pointers. */
1939 pointer = true;
1940
1941 /* In the small-PIC case, the linker converts @GOT
1942 and @GOTNTPOFF offsets to possible displacements. */
1943 if (GET_CODE (disp) == UNSPEC
1944 && (XINT (disp, 1) == UNSPEC_GOT
1945 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1946 && flag_pic == 1)
1947 {
1948 ;
1949 }
1950
1951 /* Accept pool label offsets. */
1952 else if (GET_CODE (disp) == UNSPEC
1953 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1954 ;
1955
1956 /* Accept literal pool references. */
1957 else if (GET_CODE (disp) == UNSPEC
1958 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1959 {
1960 orig_disp = gen_rtx_CONST (Pmode, disp);
1961 if (offset)
1962 {
1963 /* If we have an offset, make sure it does not
1964 exceed the size of the constant pool entry. */
1965 rtx sym = XVECEXP (disp, 0, 0);
1966 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1967 return false;
1968
1969 orig_disp = plus_constant (orig_disp, offset);
1970 }
1971 }
1972
1973 else
1974 return false;
1975 }
1976
1977 if (!base && !indx)
1978 pointer = true;
1979
1980 if (out)
1981 {
1982 out->base = base;
1983 out->indx = indx;
1984 out->disp = orig_disp;
1985 out->pointer = pointer;
1986 out->literal_pool = literal_pool;
1987 }
1988
1989 return true;
1990 }
1991
1992 /* Decompose a RTL expression OP for a shift count into its components,
1993 and return the base register in BASE and the offset in OFFSET.
1994
1995 Return true if OP is a valid shift count, false if not. */
1996
1997 bool
1998 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1999 {
2000 HOST_WIDE_INT off = 0;
2001
2002 /* We can have an integer constant, an address register,
2003 or a sum of the two. */
2004 if (GET_CODE (op) == CONST_INT)
2005 {
2006 off = INTVAL (op);
2007 op = NULL_RTX;
2008 }
2009 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2010 {
2011 off = INTVAL (XEXP (op, 1));
2012 op = XEXP (op, 0);
2013 }
2014 while (op && GET_CODE (op) == SUBREG)
2015 op = SUBREG_REG (op);
2016
2017 if (op && GET_CODE (op) != REG)
2018 return false;
2019
2020 if (offset)
2021 *offset = off;
2022 if (base)
2023 *base = op;
2024
2025 return true;
2026 }
2027
2028
2029 /* Return true if CODE is a valid address without index. */
2030
2031 bool
2032 s390_legitimate_address_without_index_p (rtx op)
2033 {
2034 struct s390_address addr;
2035
2036 if (!s390_decompose_address (XEXP (op, 0), &addr))
2037 return false;
2038 if (addr.indx)
2039 return false;
2040
2041 return true;
2042 }
2043
2044
2045 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2046 and return these parts in SYMREF and ADDEND. You can pass NULL in
2047 SYMREF and/or ADDEND if you are not interested in these values. */
2048
2049 static bool
2050 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2051 {
2052 HOST_WIDE_INT tmpaddend = 0;
2053
2054 if (GET_CODE (addr) == CONST)
2055 addr = XEXP (addr, 0);
2056
2057 if (GET_CODE (addr) == PLUS)
2058 {
2059 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2060 && CONST_INT_P (XEXP (addr, 1)))
2061 {
2062 tmpaddend = INTVAL (XEXP (addr, 1));
2063 addr = XEXP (addr, 0);
2064 }
2065 else
2066 return false;
2067 }
2068 else
2069 if (GET_CODE (addr) != SYMBOL_REF)
2070 return false;
2071
2072 if (symref)
2073 *symref = addr;
2074 if (addend)
2075 *addend = tmpaddend;
2076
2077 return true;
2078 }
2079
2080
2081 /* Return true if the address in OP is valid for constraint letter C
2082 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2083 pool MEMs should be accepted. Only the Q, R, S, T constraint
2084 letters are allowed for C. */
2085
2086 static int
2087 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2088 {
2089 struct s390_address addr;
2090 bool decomposed = false;
2091
2092 /* This check makes sure that no symbolic address (except literal
2093 pool references) are accepted by the R or T constraints. */
2094 if (s390_symref_operand_p (op, NULL, NULL))
2095 {
2096 if (!lit_pool_ok)
2097 return 0;
2098 if (!s390_decompose_address (op, &addr))
2099 return 0;
2100 if (!addr.literal_pool)
2101 return 0;
2102 decomposed = true;
2103 }
2104
2105 switch (c)
2106 {
2107 case 'Q': /* no index short displacement */
2108 if (!decomposed && !s390_decompose_address (op, &addr))
2109 return 0;
2110 if (addr.indx)
2111 return 0;
2112 if (!s390_short_displacement (addr.disp))
2113 return 0;
2114 break;
2115
2116 case 'R': /* with index short displacement */
2117 if (TARGET_LONG_DISPLACEMENT)
2118 {
2119 if (!decomposed && !s390_decompose_address (op, &addr))
2120 return 0;
2121 if (!s390_short_displacement (addr.disp))
2122 return 0;
2123 }
2124 /* Any invalid address here will be fixed up by reload,
2125 so accept it for the most generic constraint. */
2126 break;
2127
2128 case 'S': /* no index long displacement */
2129 if (!TARGET_LONG_DISPLACEMENT)
2130 return 0;
2131 if (!decomposed && !s390_decompose_address (op, &addr))
2132 return 0;
2133 if (addr.indx)
2134 return 0;
2135 if (s390_short_displacement (addr.disp))
2136 return 0;
2137 break;
2138
2139 case 'T': /* with index long displacement */
2140 if (!TARGET_LONG_DISPLACEMENT)
2141 return 0;
2142 /* Any invalid address here will be fixed up by reload,
2143 so accept it for the most generic constraint. */
2144 if ((decomposed || s390_decompose_address (op, &addr))
2145 && s390_short_displacement (addr.disp))
2146 return 0;
2147 break;
2148 default:
2149 return 0;
2150 }
2151 return 1;
2152 }
2153
2154
2155 /* Evaluates constraint strings described by the regular expression
2156 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2157 the constraint given in STR, or 0 else. */
2158
2159 int
2160 s390_mem_constraint (const char *str, rtx op)
2161 {
2162 char c = str[0];
2163
2164 switch (c)
2165 {
2166 case 'A':
2167 /* Check for offsettable variants of memory constraints. */
2168 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2169 return 0;
2170 if ((reload_completed || reload_in_progress)
2171 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2172 return 0;
2173 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2174 case 'B':
2175 /* Check for non-literal-pool variants of memory constraints. */
2176 if (!MEM_P (op))
2177 return 0;
2178 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2179 case 'Q':
2180 case 'R':
2181 case 'S':
2182 case 'T':
2183 if (GET_CODE (op) != MEM)
2184 return 0;
2185 return s390_check_qrst_address (c, XEXP (op, 0), true);
2186 case 'U':
2187 return (s390_check_qrst_address ('Q', op, true)
2188 || s390_check_qrst_address ('R', op, true));
2189 case 'W':
2190 return (s390_check_qrst_address ('S', op, true)
2191 || s390_check_qrst_address ('T', op, true));
2192 case 'Y':
2193 /* Simply check for the basic form of a shift count. Reload will
2194 take care of making sure we have a proper base register. */
2195 if (!s390_decompose_shift_count (op, NULL, NULL))
2196 return 0;
2197 break;
2198 case 'Z':
2199 return s390_check_qrst_address (str[1], op, true);
2200 default:
2201 return 0;
2202 }
2203 return 1;
2204 }
2205
2206
2207 /* Evaluates constraint strings starting with letter O. Input
2208 parameter C is the second letter following the "O" in the constraint
2209 string. Returns 1 if VALUE meets the respective constraint and 0
2210 otherwise. */
2211
2212 int
2213 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2214 {
2215 if (!TARGET_EXTIMM)
2216 return 0;
2217
2218 switch (c)
2219 {
2220 case 's':
2221 return trunc_int_for_mode (value, SImode) == value;
2222
2223 case 'p':
2224 return value == 0
2225 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2226
2227 case 'n':
2228 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2229
2230 default:
2231 gcc_unreachable ();
2232 }
2233 }
2234
2235
2236 /* Evaluates constraint strings starting with letter N. Parameter STR
2237 contains the letters following letter "N" in the constraint string.
2238 Returns true if VALUE matches the constraint. */
2239
2240 int
2241 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2242 {
2243 enum machine_mode mode, part_mode;
2244 int def;
2245 int part, part_goal;
2246
2247
2248 if (str[0] == 'x')
2249 part_goal = -1;
2250 else
2251 part_goal = str[0] - '0';
2252
2253 switch (str[1])
2254 {
2255 case 'Q':
2256 part_mode = QImode;
2257 break;
2258 case 'H':
2259 part_mode = HImode;
2260 break;
2261 case 'S':
2262 part_mode = SImode;
2263 break;
2264 default:
2265 return 0;
2266 }
2267
2268 switch (str[2])
2269 {
2270 case 'H':
2271 mode = HImode;
2272 break;
2273 case 'S':
2274 mode = SImode;
2275 break;
2276 case 'D':
2277 mode = DImode;
2278 break;
2279 default:
2280 return 0;
2281 }
2282
2283 switch (str[3])
2284 {
2285 case '0':
2286 def = 0;
2287 break;
2288 case 'F':
2289 def = -1;
2290 break;
2291 default:
2292 return 0;
2293 }
2294
2295 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2296 return 0;
2297
2298 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2299 if (part < 0)
2300 return 0;
2301 if (part_goal != -1 && part_goal != part)
2302 return 0;
2303
2304 return 1;
2305 }
2306
2307
2308 /* Returns true if the input parameter VALUE is a float zero. */
2309
2310 int
2311 s390_float_const_zero_p (rtx value)
2312 {
2313 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2314 && value == CONST0_RTX (GET_MODE (value)));
2315 }
2316
2317
2318 /* Compute a (partial) cost for rtx X. Return true if the complete
2319 cost has been computed, and false if subexpressions should be
2320 scanned. In either case, *TOTAL contains the cost result.
2321 CODE contains GET_CODE (x), OUTER_CODE contains the code
2322 of the superexpression of x. */
2323
2324 static bool
2325 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2326 bool speed ATTRIBUTE_UNUSED)
2327 {
2328 switch (code)
2329 {
2330 case CONST:
2331 case CONST_INT:
2332 case LABEL_REF:
2333 case SYMBOL_REF:
2334 case CONST_DOUBLE:
2335 case MEM:
2336 *total = 0;
2337 return true;
2338
2339 case ASHIFT:
2340 case ASHIFTRT:
2341 case LSHIFTRT:
2342 case ROTATE:
2343 case ROTATERT:
2344 case AND:
2345 case IOR:
2346 case XOR:
2347 case NEG:
2348 case NOT:
2349 *total = COSTS_N_INSNS (1);
2350 return false;
2351
2352 case PLUS:
2353 case MINUS:
2354 /* Check for multiply and add. */
2355 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2356 && GET_CODE (XEXP (x, 0)) == MULT
2357 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2358 {
2359 /* This is the multiply and add case. */
2360 if (GET_MODE (x) == DFmode)
2361 *total = s390_cost->madbr;
2362 else
2363 *total = s390_cost->maebr;
2364 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2365 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2366 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2367 return true; /* Do not do an additional recursive descent. */
2368 }
2369 *total = COSTS_N_INSNS (1);
2370 return false;
2371
2372 case MULT:
2373 switch (GET_MODE (x))
2374 {
2375 case SImode:
2376 {
2377 rtx left = XEXP (x, 0);
2378 rtx right = XEXP (x, 1);
2379 if (GET_CODE (right) == CONST_INT
2380 && CONST_OK_FOR_K (INTVAL (right)))
2381 *total = s390_cost->mhi;
2382 else if (GET_CODE (left) == SIGN_EXTEND)
2383 *total = s390_cost->mh;
2384 else
2385 *total = s390_cost->ms; /* msr, ms, msy */
2386 break;
2387 }
2388 case DImode:
2389 {
2390 rtx left = XEXP (x, 0);
2391 rtx right = XEXP (x, 1);
2392 if (TARGET_64BIT)
2393 {
2394 if (GET_CODE (right) == CONST_INT
2395 && CONST_OK_FOR_K (INTVAL (right)))
2396 *total = s390_cost->mghi;
2397 else if (GET_CODE (left) == SIGN_EXTEND)
2398 *total = s390_cost->msgf;
2399 else
2400 *total = s390_cost->msg; /* msgr, msg */
2401 }
2402 else /* TARGET_31BIT */
2403 {
2404 if (GET_CODE (left) == SIGN_EXTEND
2405 && GET_CODE (right) == SIGN_EXTEND)
2406 /* mulsidi case: mr, m */
2407 *total = s390_cost->m;
2408 else if (GET_CODE (left) == ZERO_EXTEND
2409 && GET_CODE (right) == ZERO_EXTEND
2410 && TARGET_CPU_ZARCH)
2411 /* umulsidi case: ml, mlr */
2412 *total = s390_cost->ml;
2413 else
2414 /* Complex calculation is required. */
2415 *total = COSTS_N_INSNS (40);
2416 }
2417 break;
2418 }
2419 case SFmode:
2420 case DFmode:
2421 *total = s390_cost->mult_df;
2422 break;
2423 case TFmode:
2424 *total = s390_cost->mxbr;
2425 break;
2426 default:
2427 return false;
2428 }
2429 return false;
2430
2431 case UDIV:
2432 case UMOD:
2433 if (GET_MODE (x) == TImode) /* 128 bit division */
2434 *total = s390_cost->dlgr;
2435 else if (GET_MODE (x) == DImode)
2436 {
2437 rtx right = XEXP (x, 1);
2438 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2439 *total = s390_cost->dlr;
2440 else /* 64 by 64 bit division */
2441 *total = s390_cost->dlgr;
2442 }
2443 else if (GET_MODE (x) == SImode) /* 32 bit division */
2444 *total = s390_cost->dlr;
2445 return false;
2446
2447 case DIV:
2448 case MOD:
2449 if (GET_MODE (x) == DImode)
2450 {
2451 rtx right = XEXP (x, 1);
2452 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2453 if (TARGET_64BIT)
2454 *total = s390_cost->dsgfr;
2455 else
2456 *total = s390_cost->dr;
2457 else /* 64 by 64 bit division */
2458 *total = s390_cost->dsgr;
2459 }
2460 else if (GET_MODE (x) == SImode) /* 32 bit division */
2461 *total = s390_cost->dlr;
2462 else if (GET_MODE (x) == SFmode)
2463 {
2464 *total = s390_cost->debr;
2465 }
2466 else if (GET_MODE (x) == DFmode)
2467 {
2468 *total = s390_cost->ddbr;
2469 }
2470 else if (GET_MODE (x) == TFmode)
2471 {
2472 *total = s390_cost->dxbr;
2473 }
2474 return false;
2475
2476 case SQRT:
2477 if (GET_MODE (x) == SFmode)
2478 *total = s390_cost->sqebr;
2479 else if (GET_MODE (x) == DFmode)
2480 *total = s390_cost->sqdbr;
2481 else /* TFmode */
2482 *total = s390_cost->sqxbr;
2483 return false;
2484
2485 case SIGN_EXTEND:
2486 case ZERO_EXTEND:
2487 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2488 || outer_code == PLUS || outer_code == MINUS
2489 || outer_code == COMPARE)
2490 *total = 0;
2491 return false;
2492
2493 case COMPARE:
2494 *total = COSTS_N_INSNS (1);
2495 if (GET_CODE (XEXP (x, 0)) == AND
2496 && GET_CODE (XEXP (x, 1)) == CONST_INT
2497 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2498 {
2499 rtx op0 = XEXP (XEXP (x, 0), 0);
2500 rtx op1 = XEXP (XEXP (x, 0), 1);
2501 rtx op2 = XEXP (x, 1);
2502
2503 if (memory_operand (op0, GET_MODE (op0))
2504 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2505 return true;
2506 if (register_operand (op0, GET_MODE (op0))
2507 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2508 return true;
2509 }
2510 return false;
2511
2512 default:
2513 return false;
2514 }
2515 }
2516
2517 /* Return the cost of an address rtx ADDR. */
2518
2519 static int
2520 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2521 {
2522 struct s390_address ad;
2523 if (!s390_decompose_address (addr, &ad))
2524 return 1000;
2525
2526 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2527 }
2528
2529 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2530 otherwise return 0. */
2531
2532 int
2533 tls_symbolic_operand (rtx op)
2534 {
2535 if (GET_CODE (op) != SYMBOL_REF)
2536 return 0;
2537 return SYMBOL_REF_TLS_MODEL (op);
2538 }
2539 \f
2540 /* Split DImode access register reference REG (on 64-bit) into its constituent
2541 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2542 gen_highpart cannot be used as they assume all registers are word-sized,
2543 while our access registers have only half that size. */
2544
2545 void
2546 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2547 {
2548 gcc_assert (TARGET_64BIT);
2549 gcc_assert (ACCESS_REG_P (reg));
2550 gcc_assert (GET_MODE (reg) == DImode);
2551 gcc_assert (!(REGNO (reg) & 1));
2552
2553 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2554 *hi = gen_rtx_REG (SImode, REGNO (reg));
2555 }
2556
2557 /* Return true if OP contains a symbol reference */
2558
2559 bool
2560 symbolic_reference_mentioned_p (rtx op)
2561 {
2562 const char *fmt;
2563 int i;
2564
2565 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2566 return 1;
2567
2568 fmt = GET_RTX_FORMAT (GET_CODE (op));
2569 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2570 {
2571 if (fmt[i] == 'E')
2572 {
2573 int j;
2574
2575 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2576 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2577 return 1;
2578 }
2579
2580 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2581 return 1;
2582 }
2583
2584 return 0;
2585 }
2586
2587 /* Return true if OP contains a reference to a thread-local symbol. */
2588
2589 bool
2590 tls_symbolic_reference_mentioned_p (rtx op)
2591 {
2592 const char *fmt;
2593 int i;
2594
2595 if (GET_CODE (op) == SYMBOL_REF)
2596 return tls_symbolic_operand (op);
2597
2598 fmt = GET_RTX_FORMAT (GET_CODE (op));
2599 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2600 {
2601 if (fmt[i] == 'E')
2602 {
2603 int j;
2604
2605 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2606 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2607 return true;
2608 }
2609
2610 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2611 return true;
2612 }
2613
2614 return false;
2615 }
2616
2617
2618 /* Return true if OP is a legitimate general operand when
2619 generating PIC code. It is given that flag_pic is on
2620 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2621
2622 int
2623 legitimate_pic_operand_p (rtx op)
2624 {
2625 /* Accept all non-symbolic constants. */
2626 if (!SYMBOLIC_CONST (op))
2627 return 1;
2628
2629 /* Reject everything else; must be handled
2630 via emit_symbolic_move. */
2631 return 0;
2632 }
2633
2634 /* Returns true if the constant value OP is a legitimate general operand.
2635 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2636
2637 int
2638 legitimate_constant_p (rtx op)
2639 {
2640 /* Accept all non-symbolic constants. */
2641 if (!SYMBOLIC_CONST (op))
2642 return 1;
2643
2644 /* Accept immediate LARL operands. */
2645 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2646 return 1;
2647
2648 /* Thread-local symbols are never legal constants. This is
2649 so that emit_call knows that computing such addresses
2650 might require a function call. */
2651 if (TLS_SYMBOLIC_CONST (op))
2652 return 0;
2653
2654 /* In the PIC case, symbolic constants must *not* be
2655 forced into the literal pool. We accept them here,
2656 so that they will be handled by emit_symbolic_move. */
2657 if (flag_pic)
2658 return 1;
2659
2660 /* All remaining non-PIC symbolic constants are
2661 forced into the literal pool. */
2662 return 0;
2663 }
2664
2665 /* Determine if it's legal to put X into the constant pool. This
2666 is not possible if X contains the address of a symbol that is
2667 not constant (TLS) or not known at final link time (PIC). */
2668
2669 static bool
2670 s390_cannot_force_const_mem (rtx x)
2671 {
2672 switch (GET_CODE (x))
2673 {
2674 case CONST_INT:
2675 case CONST_DOUBLE:
2676 /* Accept all non-symbolic constants. */
2677 return false;
2678
2679 case LABEL_REF:
2680 /* Labels are OK iff we are non-PIC. */
2681 return flag_pic != 0;
2682
2683 case SYMBOL_REF:
2684 /* 'Naked' TLS symbol references are never OK,
2685 non-TLS symbols are OK iff we are non-PIC. */
2686 if (tls_symbolic_operand (x))
2687 return true;
2688 else
2689 return flag_pic != 0;
2690
2691 case CONST:
2692 return s390_cannot_force_const_mem (XEXP (x, 0));
2693 case PLUS:
2694 case MINUS:
2695 return s390_cannot_force_const_mem (XEXP (x, 0))
2696 || s390_cannot_force_const_mem (XEXP (x, 1));
2697
2698 case UNSPEC:
2699 switch (XINT (x, 1))
2700 {
2701 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2702 case UNSPEC_LTREL_OFFSET:
2703 case UNSPEC_GOT:
2704 case UNSPEC_GOTOFF:
2705 case UNSPEC_PLTOFF:
2706 case UNSPEC_TLSGD:
2707 case UNSPEC_TLSLDM:
2708 case UNSPEC_NTPOFF:
2709 case UNSPEC_DTPOFF:
2710 case UNSPEC_GOTNTPOFF:
2711 case UNSPEC_INDNTPOFF:
2712 return false;
2713
2714 /* If the literal pool shares the code section, be put
2715 execute template placeholders into the pool as well. */
2716 case UNSPEC_INSN:
2717 return TARGET_CPU_ZARCH;
2718
2719 default:
2720 return true;
2721 }
2722 break;
2723
2724 default:
2725 gcc_unreachable ();
2726 }
2727 }
2728
2729 /* Returns true if the constant value OP is a legitimate general
2730 operand during and after reload. The difference to
2731 legitimate_constant_p is that this function will not accept
2732 a constant that would need to be forced to the literal pool
2733 before it can be used as operand. */
2734
2735 bool
2736 legitimate_reload_constant_p (rtx op)
2737 {
2738 /* Accept la(y) operands. */
2739 if (GET_CODE (op) == CONST_INT
2740 && DISP_IN_RANGE (INTVAL (op)))
2741 return true;
2742
2743 /* Accept l(g)hi/l(g)fi operands. */
2744 if (GET_CODE (op) == CONST_INT
2745 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2746 return true;
2747
2748 /* Accept lliXX operands. */
2749 if (TARGET_ZARCH
2750 && GET_CODE (op) == CONST_INT
2751 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2752 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2753 return true;
2754
2755 if (TARGET_EXTIMM
2756 && GET_CODE (op) == CONST_INT
2757 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2758 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2759 return true;
2760
2761 /* Accept larl operands. */
2762 if (TARGET_CPU_ZARCH
2763 && larl_operand (op, VOIDmode))
2764 return true;
2765
2766 /* Accept lzXX operands. */
2767 if (GET_CODE (op) == CONST_DOUBLE
2768 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2769 return true;
2770
2771 /* Accept double-word operands that can be split. */
2772 if (GET_CODE (op) == CONST_INT
2773 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2774 {
2775 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2776 rtx hi = operand_subword (op, 0, 0, dword_mode);
2777 rtx lo = operand_subword (op, 1, 0, dword_mode);
2778 return legitimate_reload_constant_p (hi)
2779 && legitimate_reload_constant_p (lo);
2780 }
2781
2782 /* Everything else cannot be handled without reload. */
2783 return false;
2784 }
2785
2786 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2787 return the class of reg to actually use. */
2788
2789 enum reg_class
2790 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2791 {
2792 switch (GET_CODE (op))
2793 {
2794 /* Constants we cannot reload must be forced into the
2795 literal pool. */
2796
2797 case CONST_DOUBLE:
2798 case CONST_INT:
2799 if (legitimate_reload_constant_p (op))
2800 return rclass;
2801 else
2802 return NO_REGS;
2803
2804 /* If a symbolic constant or a PLUS is reloaded,
2805 it is most likely being used as an address, so
2806 prefer ADDR_REGS. If 'class' is not a superset
2807 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2808 case PLUS:
2809 case LABEL_REF:
2810 case SYMBOL_REF:
2811 case CONST:
2812 if (reg_class_subset_p (ADDR_REGS, rclass))
2813 return ADDR_REGS;
2814 else
2815 return NO_REGS;
2816
2817 default:
2818 break;
2819 }
2820
2821 return rclass;
2822 }
2823
2824 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2825 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2826 aligned. */
2827
2828 bool
2829 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2830 {
2831 HOST_WIDE_INT addend;
2832 rtx symref;
2833
2834 if (!s390_symref_operand_p (addr, &symref, &addend))
2835 return false;
2836
2837 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2838 && !(addend & (alignment - 1)));
2839 }
2840
2841 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2842 operand SCRATCH is used to reload the even part of the address and
2843 adding one. */
2844
2845 void
2846 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2847 {
2848 HOST_WIDE_INT addend;
2849 rtx symref;
2850
2851 if (!s390_symref_operand_p (addr, &symref, &addend))
2852 gcc_unreachable ();
2853
2854 if (!(addend & 1))
2855 /* Easy case. The addend is even so larl will do fine. */
2856 emit_move_insn (reg, addr);
2857 else
2858 {
2859 /* We can leave the scratch register untouched if the target
2860 register is a valid base register. */
2861 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2862 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2863 scratch = reg;
2864
2865 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2866 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2867
2868 if (addend != 1)
2869 emit_move_insn (scratch,
2870 gen_rtx_CONST (Pmode,
2871 gen_rtx_PLUS (Pmode, symref,
2872 GEN_INT (addend - 1))));
2873 else
2874 emit_move_insn (scratch, symref);
2875
2876 /* Increment the address using la in order to avoid clobbering cc. */
2877 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2878 }
2879 }
2880
2881 /* Generate what is necessary to move between REG and MEM using
2882 SCRATCH. The direction is given by TOMEM. */
2883
2884 void
2885 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2886 {
2887 /* Reload might have pulled a constant out of the literal pool.
2888 Force it back in. */
2889 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2890 || GET_CODE (mem) == CONST)
2891 mem = force_const_mem (GET_MODE (reg), mem);
2892
2893 gcc_assert (MEM_P (mem));
2894
2895 /* For a load from memory we can leave the scratch register
2896 untouched if the target register is a valid base register. */
2897 if (!tomem
2898 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2899 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2900 && GET_MODE (reg) == GET_MODE (scratch))
2901 scratch = reg;
2902
2903 /* Load address into scratch register. Since we can't have a
2904 secondary reload for a secondary reload we have to cover the case
2905 where larl would need a secondary reload here as well. */
2906 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2907
2908 /* Now we can use a standard load/store to do the move. */
2909 if (tomem)
2910 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2911 else
2912 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2913 }
2914
2915 /* Inform reload about cases where moving X with a mode MODE to a register in
2916 RCLASS requires an extra scratch or immediate register. Return the class
2917 needed for the immediate register. */
2918
2919 static enum reg_class
2920 s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2921 enum machine_mode mode, secondary_reload_info *sri)
2922 {
2923 /* Intermediate register needed. */
2924 if (reg_classes_intersect_p (CC_REGS, rclass))
2925 return GENERAL_REGS;
2926
2927 if (TARGET_Z10)
2928 {
2929 /* On z10 several optimizer steps may generate larl operands with
2930 an odd addend. */
2931 if (in_p
2932 && s390_symref_operand_p (x, NULL, NULL)
2933 && mode == Pmode
2934 && !s390_check_symref_alignment (x, 2))
2935 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2936 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2937
2938 /* On z10 we need a scratch register when moving QI, TI or floating
2939 point mode values from or to a memory location with a SYMBOL_REF
2940 or if the symref addend of a SI or DI move is not aligned to the
2941 width of the access. */
2942 if (MEM_P (x)
2943 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2944 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2945 || (!TARGET_64BIT && mode == DImode)
2946 || ((mode == HImode || mode == SImode || mode == DImode)
2947 && (!s390_check_symref_alignment (XEXP (x, 0),
2948 GET_MODE_SIZE (mode))))))
2949 {
2950 #define __SECONDARY_RELOAD_CASE(M,m) \
2951 case M##mode: \
2952 if (TARGET_64BIT) \
2953 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2954 CODE_FOR_reload##m##di_tomem_z10; \
2955 else \
2956 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
2957 CODE_FOR_reload##m##si_tomem_z10; \
2958 break;
2959
2960 switch (GET_MODE (x))
2961 {
2962 __SECONDARY_RELOAD_CASE (QI, qi);
2963 __SECONDARY_RELOAD_CASE (HI, hi);
2964 __SECONDARY_RELOAD_CASE (SI, si);
2965 __SECONDARY_RELOAD_CASE (DI, di);
2966 __SECONDARY_RELOAD_CASE (TI, ti);
2967 __SECONDARY_RELOAD_CASE (SF, sf);
2968 __SECONDARY_RELOAD_CASE (DF, df);
2969 __SECONDARY_RELOAD_CASE (TF, tf);
2970 __SECONDARY_RELOAD_CASE (SD, sd);
2971 __SECONDARY_RELOAD_CASE (DD, dd);
2972 __SECONDARY_RELOAD_CASE (TD, td);
2973
2974 default:
2975 gcc_unreachable ();
2976 }
2977 #undef __SECONDARY_RELOAD_CASE
2978 }
2979 }
2980
2981 /* We need a scratch register when loading a PLUS expression which
2982 is not a legitimate operand of the LOAD ADDRESS instruction. */
2983 if (in_p && s390_plus_operand (x, mode))
2984 sri->icode = (TARGET_64BIT ?
2985 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
2986
2987 /* Performing a multiword move from or to memory we have to make sure the
2988 second chunk in memory is addressable without causing a displacement
2989 overflow. If that would be the case we calculate the address in
2990 a scratch register. */
2991 if (MEM_P (x)
2992 && GET_CODE (XEXP (x, 0)) == PLUS
2993 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2994 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
2995 + GET_MODE_SIZE (mode) - 1))
2996 {
2997 /* For GENERAL_REGS a displacement overflow is no problem if occurring
2998 in a s_operand address since we may fallback to lm/stm. So we only
2999 have to care about overflows in the b+i+d case. */
3000 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3001 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3002 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3003 /* For FP_REGS no lm/stm is available so this check is triggered
3004 for displacement overflows in b+i+d and b+d like addresses. */
3005 || (reg_classes_intersect_p (FP_REGS, rclass)
3006 && s390_class_max_nregs (FP_REGS, mode) > 1))
3007 {
3008 if (in_p)
3009 sri->icode = (TARGET_64BIT ?
3010 CODE_FOR_reloaddi_nonoffmem_in :
3011 CODE_FOR_reloadsi_nonoffmem_in);
3012 else
3013 sri->icode = (TARGET_64BIT ?
3014 CODE_FOR_reloaddi_nonoffmem_out :
3015 CODE_FOR_reloadsi_nonoffmem_out);
3016 }
3017 }
3018
3019 /* A scratch address register is needed when a symbolic constant is
3020 copied to r0 compiling with -fPIC. In other cases the target
3021 register might be used as temporary (see legitimize_pic_address). */
3022 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3023 sri->icode = (TARGET_64BIT ?
3024 CODE_FOR_reloaddi_PIC_addr :
3025 CODE_FOR_reloadsi_PIC_addr);
3026
3027 /* Either scratch or no register needed. */
3028 return NO_REGS;
3029 }
3030
3031 /* Generate code to load SRC, which is PLUS that is not a
3032 legitimate operand for the LA instruction, into TARGET.
3033 SCRATCH may be used as scratch register. */
3034
3035 void
3036 s390_expand_plus_operand (rtx target, rtx src,
3037 rtx scratch)
3038 {
3039 rtx sum1, sum2;
3040 struct s390_address ad;
3041
3042 /* src must be a PLUS; get its two operands. */
3043 gcc_assert (GET_CODE (src) == PLUS);
3044 gcc_assert (GET_MODE (src) == Pmode);
3045
3046 /* Check if any of the two operands is already scheduled
3047 for replacement by reload. This can happen e.g. when
3048 float registers occur in an address. */
3049 sum1 = find_replacement (&XEXP (src, 0));
3050 sum2 = find_replacement (&XEXP (src, 1));
3051 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3052
3053 /* If the address is already strictly valid, there's nothing to do. */
3054 if (!s390_decompose_address (src, &ad)
3055 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3056 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3057 {
3058 /* Otherwise, one of the operands cannot be an address register;
3059 we reload its value into the scratch register. */
3060 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3061 {
3062 emit_move_insn (scratch, sum1);
3063 sum1 = scratch;
3064 }
3065 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3066 {
3067 emit_move_insn (scratch, sum2);
3068 sum2 = scratch;
3069 }
3070
3071 /* According to the way these invalid addresses are generated
3072 in reload.c, it should never happen (at least on s390) that
3073 *neither* of the PLUS components, after find_replacements
3074 was applied, is an address register. */
3075 if (sum1 == scratch && sum2 == scratch)
3076 {
3077 debug_rtx (src);
3078 gcc_unreachable ();
3079 }
3080
3081 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3082 }
3083
3084 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3085 is only ever performed on addresses, so we can mark the
3086 sum as legitimate for LA in any case. */
3087 s390_load_address (target, src);
3088 }
3089
3090
3091 /* Return true if ADDR is a valid memory address.
3092 STRICT specifies whether strict register checking applies. */
3093
3094 static bool
3095 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3096 {
3097 struct s390_address ad;
3098
3099 if (TARGET_Z10
3100 && larl_operand (addr, VOIDmode)
3101 && (mode == VOIDmode
3102 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3103 return true;
3104
3105 if (!s390_decompose_address (addr, &ad))
3106 return false;
3107
3108 if (strict)
3109 {
3110 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3111 return false;
3112
3113 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3114 return false;
3115 }
3116 else
3117 {
3118 if (ad.base
3119 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3120 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3121 return false;
3122
3123 if (ad.indx
3124 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3125 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3126 return false;
3127 }
3128 return true;
3129 }
3130
3131 /* Return true if OP is a valid operand for the LA instruction.
3132 In 31-bit, we need to prove that the result is used as an
3133 address, as LA performs only a 31-bit addition. */
3134
3135 bool
3136 legitimate_la_operand_p (rtx op)
3137 {
3138 struct s390_address addr;
3139 if (!s390_decompose_address (op, &addr))
3140 return false;
3141
3142 return (TARGET_64BIT || addr.pointer);
3143 }
3144
3145 /* Return true if it is valid *and* preferable to use LA to
3146 compute the sum of OP1 and OP2. */
3147
3148 bool
3149 preferred_la_operand_p (rtx op1, rtx op2)
3150 {
3151 struct s390_address addr;
3152
3153 if (op2 != const0_rtx)
3154 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3155
3156 if (!s390_decompose_address (op1, &addr))
3157 return false;
3158 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3159 return false;
3160 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3161 return false;
3162
3163 if (!TARGET_64BIT && !addr.pointer)
3164 return false;
3165
3166 if (addr.pointer)
3167 return true;
3168
3169 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3170 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3171 return true;
3172
3173 return false;
3174 }
3175
3176 /* Emit a forced load-address operation to load SRC into DST.
3177 This will use the LOAD ADDRESS instruction even in situations
3178 where legitimate_la_operand_p (SRC) returns false. */
3179
3180 void
3181 s390_load_address (rtx dst, rtx src)
3182 {
3183 if (TARGET_64BIT)
3184 emit_move_insn (dst, src);
3185 else
3186 emit_insn (gen_force_la_31 (dst, src));
3187 }
3188
3189 /* Return a legitimate reference for ORIG (an address) using the
3190 register REG. If REG is 0, a new pseudo is generated.
3191
3192 There are two types of references that must be handled:
3193
3194 1. Global data references must load the address from the GOT, via
3195 the PIC reg. An insn is emitted to do this load, and the reg is
3196 returned.
3197
3198 2. Static data references, constant pool addresses, and code labels
3199 compute the address as an offset from the GOT, whose base is in
3200 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3201 differentiate them from global data objects. The returned
3202 address is the PIC reg + an unspec constant.
3203
3204 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3205 reg also appears in the address. */
3206
3207 rtx
3208 legitimize_pic_address (rtx orig, rtx reg)
3209 {
3210 rtx addr = orig;
3211 rtx new_rtx = orig;
3212 rtx base;
3213
3214 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3215
3216 if (GET_CODE (addr) == LABEL_REF
3217 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3218 {
3219 /* This is a local symbol. */
3220 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3221 {
3222 /* Access local symbols PC-relative via LARL.
3223 This is the same as in the non-PIC case, so it is
3224 handled automatically ... */
3225 }
3226 else
3227 {
3228 /* Access local symbols relative to the GOT. */
3229
3230 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3231
3232 if (reload_in_progress || reload_completed)
3233 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3234
3235 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3236 addr = gen_rtx_CONST (Pmode, addr);
3237 addr = force_const_mem (Pmode, addr);
3238 emit_move_insn (temp, addr);
3239
3240 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3241 if (reg != 0)
3242 {
3243 s390_load_address (reg, new_rtx);
3244 new_rtx = reg;
3245 }
3246 }
3247 }
3248 else if (GET_CODE (addr) == SYMBOL_REF)
3249 {
3250 if (reg == 0)
3251 reg = gen_reg_rtx (Pmode);
3252
3253 if (flag_pic == 1)
3254 {
3255 /* Assume GOT offset < 4k. This is handled the same way
3256 in both 31- and 64-bit code (@GOT). */
3257
3258 if (reload_in_progress || reload_completed)
3259 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3260
3261 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3262 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3263 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3264 new_rtx = gen_const_mem (Pmode, new_rtx);
3265 emit_move_insn (reg, new_rtx);
3266 new_rtx = reg;
3267 }
3268 else if (TARGET_CPU_ZARCH)
3269 {
3270 /* If the GOT offset might be >= 4k, we determine the position
3271 of the GOT entry via a PC-relative LARL (@GOTENT). */
3272
3273 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3274
3275 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3276 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3277
3278 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3279 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3280 emit_move_insn (temp, new_rtx);
3281
3282 new_rtx = gen_const_mem (Pmode, temp);
3283 emit_move_insn (reg, new_rtx);
3284 new_rtx = reg;
3285 }
3286 else
3287 {
3288 /* If the GOT offset might be >= 4k, we have to load it
3289 from the literal pool (@GOT). */
3290
3291 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3292
3293 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3294 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3295
3296 if (reload_in_progress || reload_completed)
3297 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3298
3299 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3300 addr = gen_rtx_CONST (Pmode, addr);
3301 addr = force_const_mem (Pmode, addr);
3302 emit_move_insn (temp, addr);
3303
3304 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3305 new_rtx = gen_const_mem (Pmode, new_rtx);
3306 emit_move_insn (reg, new_rtx);
3307 new_rtx = reg;
3308 }
3309 }
3310 else
3311 {
3312 if (GET_CODE (addr) == CONST)
3313 {
3314 addr = XEXP (addr, 0);
3315 if (GET_CODE (addr) == UNSPEC)
3316 {
3317 gcc_assert (XVECLEN (addr, 0) == 1);
3318 switch (XINT (addr, 1))
3319 {
3320 /* If someone moved a GOT-relative UNSPEC
3321 out of the literal pool, force them back in. */
3322 case UNSPEC_GOTOFF:
3323 case UNSPEC_PLTOFF:
3324 new_rtx = force_const_mem (Pmode, orig);
3325 break;
3326
3327 /* @GOT is OK as is if small. */
3328 case UNSPEC_GOT:
3329 if (flag_pic == 2)
3330 new_rtx = force_const_mem (Pmode, orig);
3331 break;
3332
3333 /* @GOTENT is OK as is. */
3334 case UNSPEC_GOTENT:
3335 break;
3336
3337 /* @PLT is OK as is on 64-bit, must be converted to
3338 GOT-relative @PLTOFF on 31-bit. */
3339 case UNSPEC_PLT:
3340 if (!TARGET_CPU_ZARCH)
3341 {
3342 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3343
3344 if (reload_in_progress || reload_completed)
3345 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3346
3347 addr = XVECEXP (addr, 0, 0);
3348 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3349 UNSPEC_PLTOFF);
3350 addr = gen_rtx_CONST (Pmode, addr);
3351 addr = force_const_mem (Pmode, addr);
3352 emit_move_insn (temp, addr);
3353
3354 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3355 if (reg != 0)
3356 {
3357 s390_load_address (reg, new_rtx);
3358 new_rtx = reg;
3359 }
3360 }
3361 break;
3362
3363 /* Everything else cannot happen. */
3364 default:
3365 gcc_unreachable ();
3366 }
3367 }
3368 else
3369 gcc_assert (GET_CODE (addr) == PLUS);
3370 }
3371 if (GET_CODE (addr) == PLUS)
3372 {
3373 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3374
3375 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3376 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3377
3378 /* Check first to see if this is a constant offset
3379 from a local symbol reference. */
3380 if ((GET_CODE (op0) == LABEL_REF
3381 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3382 && GET_CODE (op1) == CONST_INT)
3383 {
3384 if (TARGET_CPU_ZARCH
3385 && larl_operand (op0, VOIDmode)
3386 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3387 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3388 {
3389 if (INTVAL (op1) & 1)
3390 {
3391 /* LARL can't handle odd offsets, so emit a
3392 pair of LARL and LA. */
3393 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3394
3395 if (!DISP_IN_RANGE (INTVAL (op1)))
3396 {
3397 HOST_WIDE_INT even = INTVAL (op1) - 1;
3398 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3399 op0 = gen_rtx_CONST (Pmode, op0);
3400 op1 = const1_rtx;
3401 }
3402
3403 emit_move_insn (temp, op0);
3404 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3405
3406 if (reg != 0)
3407 {
3408 s390_load_address (reg, new_rtx);
3409 new_rtx = reg;
3410 }
3411 }
3412 else
3413 {
3414 /* If the offset is even, we can just use LARL.
3415 This will happen automatically. */
3416 }
3417 }
3418 else
3419 {
3420 /* Access local symbols relative to the GOT. */
3421
3422 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3423
3424 if (reload_in_progress || reload_completed)
3425 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3426
3427 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3428 UNSPEC_GOTOFF);
3429 addr = gen_rtx_PLUS (Pmode, addr, op1);
3430 addr = gen_rtx_CONST (Pmode, addr);
3431 addr = force_const_mem (Pmode, addr);
3432 emit_move_insn (temp, addr);
3433
3434 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3435 if (reg != 0)
3436 {
3437 s390_load_address (reg, new_rtx);
3438 new_rtx = reg;
3439 }
3440 }
3441 }
3442
3443 /* Now, check whether it is a GOT relative symbol plus offset
3444 that was pulled out of the literal pool. Force it back in. */
3445
3446 else if (GET_CODE (op0) == UNSPEC
3447 && GET_CODE (op1) == CONST_INT
3448 && XINT (op0, 1) == UNSPEC_GOTOFF)
3449 {
3450 gcc_assert (XVECLEN (op0, 0) == 1);
3451
3452 new_rtx = force_const_mem (Pmode, orig);
3453 }
3454
3455 /* Otherwise, compute the sum. */
3456 else
3457 {
3458 base = legitimize_pic_address (XEXP (addr, 0), reg);
3459 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3460 base == reg ? NULL_RTX : reg);
3461 if (GET_CODE (new_rtx) == CONST_INT)
3462 new_rtx = plus_constant (base, INTVAL (new_rtx));
3463 else
3464 {
3465 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3466 {
3467 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3468 new_rtx = XEXP (new_rtx, 1);
3469 }
3470 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3471 }
3472
3473 if (GET_CODE (new_rtx) == CONST)
3474 new_rtx = XEXP (new_rtx, 0);
3475 new_rtx = force_operand (new_rtx, 0);
3476 }
3477 }
3478 }
3479 return new_rtx;
3480 }
3481
3482 /* Load the thread pointer into a register. */
3483
3484 rtx
3485 s390_get_thread_pointer (void)
3486 {
3487 rtx tp = gen_reg_rtx (Pmode);
3488
3489 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3490 mark_reg_pointer (tp, BITS_PER_WORD);
3491
3492 return tp;
3493 }
3494
3495 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3496 in s390_tls_symbol which always refers to __tls_get_offset.
3497 The returned offset is written to RESULT_REG and an USE rtx is
3498 generated for TLS_CALL. */
3499
3500 static GTY(()) rtx s390_tls_symbol;
3501
3502 static void
3503 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3504 {
3505 rtx insn;
3506
3507 gcc_assert (flag_pic);
3508
3509 if (!s390_tls_symbol)
3510 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3511
3512 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3513 gen_rtx_REG (Pmode, RETURN_REGNUM));
3514
3515 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3516 RTL_CONST_CALL_P (insn) = 1;
3517 }
3518
3519 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3520 this (thread-local) address. REG may be used as temporary. */
3521
3522 static rtx
3523 legitimize_tls_address (rtx addr, rtx reg)
3524 {
3525 rtx new_rtx, tls_call, temp, base, r2, insn;
3526
3527 if (GET_CODE (addr) == SYMBOL_REF)
3528 switch (tls_symbolic_operand (addr))
3529 {
3530 case TLS_MODEL_GLOBAL_DYNAMIC:
3531 start_sequence ();
3532 r2 = gen_rtx_REG (Pmode, 2);
3533 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3534 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3535 new_rtx = force_const_mem (Pmode, new_rtx);
3536 emit_move_insn (r2, new_rtx);
3537 s390_emit_tls_call_insn (r2, tls_call);
3538 insn = get_insns ();
3539 end_sequence ();
3540
3541 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3542 temp = gen_reg_rtx (Pmode);
3543 emit_libcall_block (insn, temp, r2, new_rtx);
3544
3545 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3546 if (reg != 0)
3547 {
3548 s390_load_address (reg, new_rtx);
3549 new_rtx = reg;
3550 }
3551 break;
3552
3553 case TLS_MODEL_LOCAL_DYNAMIC:
3554 start_sequence ();
3555 r2 = gen_rtx_REG (Pmode, 2);
3556 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3557 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3558 new_rtx = force_const_mem (Pmode, new_rtx);
3559 emit_move_insn (r2, new_rtx);
3560 s390_emit_tls_call_insn (r2, tls_call);
3561 insn = get_insns ();
3562 end_sequence ();
3563
3564 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3565 temp = gen_reg_rtx (Pmode);
3566 emit_libcall_block (insn, temp, r2, new_rtx);
3567
3568 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3569 base = gen_reg_rtx (Pmode);
3570 s390_load_address (base, new_rtx);
3571
3572 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3573 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3574 new_rtx = force_const_mem (Pmode, new_rtx);
3575 temp = gen_reg_rtx (Pmode);
3576 emit_move_insn (temp, new_rtx);
3577
3578 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3579 if (reg != 0)
3580 {
3581 s390_load_address (reg, new_rtx);
3582 new_rtx = reg;
3583 }
3584 break;
3585
3586 case TLS_MODEL_INITIAL_EXEC:
3587 if (flag_pic == 1)
3588 {
3589 /* Assume GOT offset < 4k. This is handled the same way
3590 in both 31- and 64-bit code. */
3591
3592 if (reload_in_progress || reload_completed)
3593 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3594
3595 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3596 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3597 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3598 new_rtx = gen_const_mem (Pmode, new_rtx);
3599 temp = gen_reg_rtx (Pmode);
3600 emit_move_insn (temp, new_rtx);
3601 }
3602 else if (TARGET_CPU_ZARCH)
3603 {
3604 /* If the GOT offset might be >= 4k, we determine the position
3605 of the GOT entry via a PC-relative LARL. */
3606
3607 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3608 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3609 temp = gen_reg_rtx (Pmode);
3610 emit_move_insn (temp, new_rtx);
3611
3612 new_rtx = gen_const_mem (Pmode, temp);
3613 temp = gen_reg_rtx (Pmode);
3614 emit_move_insn (temp, new_rtx);
3615 }
3616 else if (flag_pic)
3617 {
3618 /* If the GOT offset might be >= 4k, we have to load it
3619 from the literal pool. */
3620
3621 if (reload_in_progress || reload_completed)
3622 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3623
3624 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3625 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3626 new_rtx = force_const_mem (Pmode, new_rtx);
3627 temp = gen_reg_rtx (Pmode);
3628 emit_move_insn (temp, new_rtx);
3629
3630 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3631 new_rtx = gen_const_mem (Pmode, new_rtx);
3632
3633 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3634 temp = gen_reg_rtx (Pmode);
3635 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3636 }
3637 else
3638 {
3639 /* In position-dependent code, load the absolute address of
3640 the GOT entry from the literal pool. */
3641
3642 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3643 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3644 new_rtx = force_const_mem (Pmode, new_rtx);
3645 temp = gen_reg_rtx (Pmode);
3646 emit_move_insn (temp, new_rtx);
3647
3648 new_rtx = temp;
3649 new_rtx = gen_const_mem (Pmode, new_rtx);
3650 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3651 temp = gen_reg_rtx (Pmode);
3652 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3653 }
3654
3655 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3656 if (reg != 0)
3657 {
3658 s390_load_address (reg, new_rtx);
3659 new_rtx = reg;
3660 }
3661 break;
3662
3663 case TLS_MODEL_LOCAL_EXEC:
3664 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3665 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3666 new_rtx = force_const_mem (Pmode, new_rtx);
3667 temp = gen_reg_rtx (Pmode);
3668 emit_move_insn (temp, new_rtx);
3669
3670 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3671 if (reg != 0)
3672 {
3673 s390_load_address (reg, new_rtx);
3674 new_rtx = reg;
3675 }
3676 break;
3677
3678 default:
3679 gcc_unreachable ();
3680 }
3681
3682 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3683 {
3684 switch (XINT (XEXP (addr, 0), 1))
3685 {
3686 case UNSPEC_INDNTPOFF:
3687 gcc_assert (TARGET_CPU_ZARCH);
3688 new_rtx = addr;
3689 break;
3690
3691 default:
3692 gcc_unreachable ();
3693 }
3694 }
3695
3696 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3697 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3698 {
3699 new_rtx = XEXP (XEXP (addr, 0), 0);
3700 if (GET_CODE (new_rtx) != SYMBOL_REF)
3701 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3702
3703 new_rtx = legitimize_tls_address (new_rtx, reg);
3704 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3705 new_rtx = force_operand (new_rtx, 0);
3706 }
3707
3708 else
3709 gcc_unreachable (); /* for now ... */
3710
3711 return new_rtx;
3712 }
3713
3714 /* Emit insns making the address in operands[1] valid for a standard
3715 move to operands[0]. operands[1] is replaced by an address which
3716 should be used instead of the former RTX to emit the move
3717 pattern. */
3718
3719 void
3720 emit_symbolic_move (rtx *operands)
3721 {
3722 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3723
3724 if (GET_CODE (operands[0]) == MEM)
3725 operands[1] = force_reg (Pmode, operands[1]);
3726 else if (TLS_SYMBOLIC_CONST (operands[1]))
3727 operands[1] = legitimize_tls_address (operands[1], temp);
3728 else if (flag_pic)
3729 operands[1] = legitimize_pic_address (operands[1], temp);
3730 }
3731
3732 /* Try machine-dependent ways of modifying an illegitimate address X
3733 to be legitimate. If we find one, return the new, valid address.
3734
3735 OLDX is the address as it was before break_out_memory_refs was called.
3736 In some cases it is useful to look at this to decide what needs to be done.
3737
3738 MODE is the mode of the operand pointed to by X.
3739
3740 When -fpic is used, special handling is needed for symbolic references.
3741 See comments by legitimize_pic_address for details. */
3742
3743 static rtx
3744 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3745 enum machine_mode mode ATTRIBUTE_UNUSED)
3746 {
3747 rtx constant_term = const0_rtx;
3748
3749 if (TLS_SYMBOLIC_CONST (x))
3750 {
3751 x = legitimize_tls_address (x, 0);
3752
3753 if (s390_legitimate_address_p (mode, x, FALSE))
3754 return x;
3755 }
3756 else if (GET_CODE (x) == PLUS
3757 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3758 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3759 {
3760 return x;
3761 }
3762 else if (flag_pic)
3763 {
3764 if (SYMBOLIC_CONST (x)
3765 || (GET_CODE (x) == PLUS
3766 && (SYMBOLIC_CONST (XEXP (x, 0))
3767 || SYMBOLIC_CONST (XEXP (x, 1)))))
3768 x = legitimize_pic_address (x, 0);
3769
3770 if (s390_legitimate_address_p (mode, x, FALSE))
3771 return x;
3772 }
3773
3774 x = eliminate_constant_term (x, &constant_term);
3775
3776 /* Optimize loading of large displacements by splitting them
3777 into the multiple of 4K and the rest; this allows the
3778 former to be CSE'd if possible.
3779
3780 Don't do this if the displacement is added to a register
3781 pointing into the stack frame, as the offsets will
3782 change later anyway. */
3783
3784 if (GET_CODE (constant_term) == CONST_INT
3785 && !TARGET_LONG_DISPLACEMENT
3786 && !DISP_IN_RANGE (INTVAL (constant_term))
3787 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3788 {
3789 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3790 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3791
3792 rtx temp = gen_reg_rtx (Pmode);
3793 rtx val = force_operand (GEN_INT (upper), temp);
3794 if (val != temp)
3795 emit_move_insn (temp, val);
3796
3797 x = gen_rtx_PLUS (Pmode, x, temp);
3798 constant_term = GEN_INT (lower);
3799 }
3800
3801 if (GET_CODE (x) == PLUS)
3802 {
3803 if (GET_CODE (XEXP (x, 0)) == REG)
3804 {
3805 rtx temp = gen_reg_rtx (Pmode);
3806 rtx val = force_operand (XEXP (x, 1), temp);
3807 if (val != temp)
3808 emit_move_insn (temp, val);
3809
3810 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3811 }
3812
3813 else if (GET_CODE (XEXP (x, 1)) == REG)
3814 {
3815 rtx temp = gen_reg_rtx (Pmode);
3816 rtx val = force_operand (XEXP (x, 0), temp);
3817 if (val != temp)
3818 emit_move_insn (temp, val);
3819
3820 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3821 }
3822 }
3823
3824 if (constant_term != const0_rtx)
3825 x = gen_rtx_PLUS (Pmode, x, constant_term);
3826
3827 return x;
3828 }
3829
3830 /* Try a machine-dependent way of reloading an illegitimate address AD
3831 operand. If we find one, push the reload and and return the new address.
3832
3833 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3834 and TYPE is the reload type of the current reload. */
3835
3836 rtx
3837 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3838 int opnum, int type)
3839 {
3840 if (!optimize || TARGET_LONG_DISPLACEMENT)
3841 return NULL_RTX;
3842
3843 if (GET_CODE (ad) == PLUS)
3844 {
3845 rtx tem = simplify_binary_operation (PLUS, Pmode,
3846 XEXP (ad, 0), XEXP (ad, 1));
3847 if (tem)
3848 ad = tem;
3849 }
3850
3851 if (GET_CODE (ad) == PLUS
3852 && GET_CODE (XEXP (ad, 0)) == REG
3853 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3854 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3855 {
3856 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3857 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3858 rtx cst, tem, new_rtx;
3859
3860 cst = GEN_INT (upper);
3861 if (!legitimate_reload_constant_p (cst))
3862 cst = force_const_mem (Pmode, cst);
3863
3864 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3865 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3866
3867 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3868 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3869 opnum, (enum reload_type) type);
3870 return new_rtx;
3871 }
3872
3873 return NULL_RTX;
3874 }
3875
3876 /* Emit code to move LEN bytes from DST to SRC. */
3877
3878 void
3879 s390_expand_movmem (rtx dst, rtx src, rtx len)
3880 {
3881 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3882 {
3883 if (INTVAL (len) > 0)
3884 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3885 }
3886
3887 else if (TARGET_MVCLE)
3888 {
3889 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3890 }
3891
3892 else
3893 {
3894 rtx dst_addr, src_addr, count, blocks, temp;
3895 rtx loop_start_label = gen_label_rtx ();
3896 rtx loop_end_label = gen_label_rtx ();
3897 rtx end_label = gen_label_rtx ();
3898 enum machine_mode mode;
3899
3900 mode = GET_MODE (len);
3901 if (mode == VOIDmode)
3902 mode = Pmode;
3903
3904 dst_addr = gen_reg_rtx (Pmode);
3905 src_addr = gen_reg_rtx (Pmode);
3906 count = gen_reg_rtx (mode);
3907 blocks = gen_reg_rtx (mode);
3908
3909 convert_move (count, len, 1);
3910 emit_cmp_and_jump_insns (count, const0_rtx,
3911 EQ, NULL_RTX, mode, 1, end_label);
3912
3913 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3914 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3915 dst = change_address (dst, VOIDmode, dst_addr);
3916 src = change_address (src, VOIDmode, src_addr);
3917
3918 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3919 OPTAB_DIRECT);
3920 if (temp != count)
3921 emit_move_insn (count, temp);
3922
3923 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3924 OPTAB_DIRECT);
3925 if (temp != blocks)
3926 emit_move_insn (blocks, temp);
3927
3928 emit_cmp_and_jump_insns (blocks, const0_rtx,
3929 EQ, NULL_RTX, mode, 1, loop_end_label);
3930
3931 emit_label (loop_start_label);
3932
3933 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3934 s390_load_address (dst_addr,
3935 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3936 s390_load_address (src_addr,
3937 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3938
3939 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
3940 OPTAB_DIRECT);
3941 if (temp != blocks)
3942 emit_move_insn (blocks, temp);
3943
3944 emit_cmp_and_jump_insns (blocks, const0_rtx,
3945 EQ, NULL_RTX, mode, 1, loop_end_label);
3946
3947 emit_jump (loop_start_label);
3948 emit_label (loop_end_label);
3949
3950 emit_insn (gen_movmem_short (dst, src,
3951 convert_to_mode (Pmode, count, 1)));
3952 emit_label (end_label);
3953 }
3954 }
3955
3956 /* Emit code to set LEN bytes at DST to VAL.
3957 Make use of clrmem if VAL is zero. */
3958
3959 void
3960 s390_expand_setmem (rtx dst, rtx len, rtx val)
3961 {
3962 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
3963 return;
3964
3965 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3966
3967 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
3968 {
3969 if (val == const0_rtx && INTVAL (len) <= 256)
3970 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3971 else
3972 {
3973 /* Initialize memory by storing the first byte. */
3974 emit_move_insn (adjust_address (dst, QImode, 0), val);
3975
3976 if (INTVAL (len) > 1)
3977 {
3978 /* Initiate 1 byte overlap move.
3979 The first byte of DST is propagated through DSTP1.
3980 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3981 DST is set to size 1 so the rest of the memory location
3982 does not count as source operand. */
3983 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3984 set_mem_size (dst, const1_rtx);
3985
3986 emit_insn (gen_movmem_short (dstp1, dst,
3987 GEN_INT (INTVAL (len) - 2)));
3988 }
3989 }
3990 }
3991
3992 else if (TARGET_MVCLE)
3993 {
3994 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3995 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3996 }
3997
3998 else
3999 {
4000 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
4001 rtx loop_start_label = gen_label_rtx ();
4002 rtx loop_end_label = gen_label_rtx ();
4003 rtx end_label = gen_label_rtx ();
4004 enum machine_mode mode;
4005
4006 mode = GET_MODE (len);
4007 if (mode == VOIDmode)
4008 mode = Pmode;
4009
4010 dst_addr = gen_reg_rtx (Pmode);
4011 src_addr = gen_reg_rtx (Pmode);
4012 count = gen_reg_rtx (mode);
4013 blocks = gen_reg_rtx (mode);
4014
4015 convert_move (count, len, 1);
4016 emit_cmp_and_jump_insns (count, const0_rtx,
4017 EQ, NULL_RTX, mode, 1, end_label);
4018
4019 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4020 dst = change_address (dst, VOIDmode, dst_addr);
4021
4022 if (val == const0_rtx)
4023 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4024 OPTAB_DIRECT);
4025 else
4026 {
4027 dstp1 = adjust_address (dst, VOIDmode, 1);
4028 set_mem_size (dst, const1_rtx);
4029
4030 /* Initialize memory by storing the first byte. */
4031 emit_move_insn (adjust_address (dst, QImode, 0), val);
4032
4033 /* If count is 1 we are done. */
4034 emit_cmp_and_jump_insns (count, const1_rtx,
4035 EQ, NULL_RTX, mode, 1, end_label);
4036
4037 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4038 OPTAB_DIRECT);
4039 }
4040 if (temp != count)
4041 emit_move_insn (count, temp);
4042
4043 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4044 OPTAB_DIRECT);
4045 if (temp != blocks)
4046 emit_move_insn (blocks, temp);
4047
4048 emit_cmp_and_jump_insns (blocks, const0_rtx,
4049 EQ, NULL_RTX, mode, 1, loop_end_label);
4050
4051 emit_label (loop_start_label);
4052
4053 if (val == const0_rtx)
4054 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4055 else
4056 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4057 s390_load_address (dst_addr,
4058 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4059
4060 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4061 OPTAB_DIRECT);
4062 if (temp != blocks)
4063 emit_move_insn (blocks, temp);
4064
4065 emit_cmp_and_jump_insns (blocks, const0_rtx,
4066 EQ, NULL_RTX, mode, 1, loop_end_label);
4067
4068 emit_jump (loop_start_label);
4069 emit_label (loop_end_label);
4070
4071 if (val == const0_rtx)
4072 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4073 else
4074 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4075 emit_label (end_label);
4076 }
4077 }
4078
4079 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4080 and return the result in TARGET. */
4081
4082 void
4083 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4084 {
4085 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4086 rtx tmp;
4087
4088 /* As the result of CMPINT is inverted compared to what we need,
4089 we have to swap the operands. */
4090 tmp = op0; op0 = op1; op1 = tmp;
4091
4092 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4093 {
4094 if (INTVAL (len) > 0)
4095 {
4096 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4097 emit_insn (gen_cmpint (target, ccreg));
4098 }
4099 else
4100 emit_move_insn (target, const0_rtx);
4101 }
4102 else if (TARGET_MVCLE)
4103 {
4104 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4105 emit_insn (gen_cmpint (target, ccreg));
4106 }
4107 else
4108 {
4109 rtx addr0, addr1, count, blocks, temp;
4110 rtx loop_start_label = gen_label_rtx ();
4111 rtx loop_end_label = gen_label_rtx ();
4112 rtx end_label = gen_label_rtx ();
4113 enum machine_mode mode;
4114
4115 mode = GET_MODE (len);
4116 if (mode == VOIDmode)
4117 mode = Pmode;
4118
4119 addr0 = gen_reg_rtx (Pmode);
4120 addr1 = gen_reg_rtx (Pmode);
4121 count = gen_reg_rtx (mode);
4122 blocks = gen_reg_rtx (mode);
4123
4124 convert_move (count, len, 1);
4125 emit_cmp_and_jump_insns (count, const0_rtx,
4126 EQ, NULL_RTX, mode, 1, end_label);
4127
4128 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4129 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4130 op0 = change_address (op0, VOIDmode, addr0);
4131 op1 = change_address (op1, VOIDmode, addr1);
4132
4133 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4134 OPTAB_DIRECT);
4135 if (temp != count)
4136 emit_move_insn (count, temp);
4137
4138 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4139 OPTAB_DIRECT);
4140 if (temp != blocks)
4141 emit_move_insn (blocks, temp);
4142
4143 emit_cmp_and_jump_insns (blocks, const0_rtx,
4144 EQ, NULL_RTX, mode, 1, loop_end_label);
4145
4146 emit_label (loop_start_label);
4147
4148 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4149 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4150 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4151 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4152 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4153 emit_jump_insn (temp);
4154
4155 s390_load_address (addr0,
4156 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4157 s390_load_address (addr1,
4158 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4159
4160 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4161 OPTAB_DIRECT);
4162 if (temp != blocks)
4163 emit_move_insn (blocks, temp);
4164
4165 emit_cmp_and_jump_insns (blocks, const0_rtx,
4166 EQ, NULL_RTX, mode, 1, loop_end_label);
4167
4168 emit_jump (loop_start_label);
4169 emit_label (loop_end_label);
4170
4171 emit_insn (gen_cmpmem_short (op0, op1,
4172 convert_to_mode (Pmode, count, 1)));
4173 emit_label (end_label);
4174
4175 emit_insn (gen_cmpint (target, ccreg));
4176 }
4177 }
4178
4179
4180 /* Expand conditional increment or decrement using alc/slb instructions.
4181 Should generate code setting DST to either SRC or SRC + INCREMENT,
4182 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4183 Returns true if successful, false otherwise.
4184
4185 That makes it possible to implement some if-constructs without jumps e.g.:
4186 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4187 unsigned int a, b, c;
4188 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4189 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4190 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4191 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4192
4193 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4194 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4195 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4196 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4197 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4198
4199 bool
4200 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4201 rtx dst, rtx src, rtx increment)
4202 {
4203 enum machine_mode cmp_mode;
4204 enum machine_mode cc_mode;
4205 rtx op_res;
4206 rtx insn;
4207 rtvec p;
4208 int ret;
4209
4210 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4211 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4212 cmp_mode = SImode;
4213 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4214 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4215 cmp_mode = DImode;
4216 else
4217 return false;
4218
4219 /* Try ADD LOGICAL WITH CARRY. */
4220 if (increment == const1_rtx)
4221 {
4222 /* Determine CC mode to use. */
4223 if (cmp_code == EQ || cmp_code == NE)
4224 {
4225 if (cmp_op1 != const0_rtx)
4226 {
4227 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4228 NULL_RTX, 0, OPTAB_WIDEN);
4229 cmp_op1 = const0_rtx;
4230 }
4231
4232 cmp_code = cmp_code == EQ ? LEU : GTU;
4233 }
4234
4235 if (cmp_code == LTU || cmp_code == LEU)
4236 {
4237 rtx tem = cmp_op0;
4238 cmp_op0 = cmp_op1;
4239 cmp_op1 = tem;
4240 cmp_code = swap_condition (cmp_code);
4241 }
4242
4243 switch (cmp_code)
4244 {
4245 case GTU:
4246 cc_mode = CCUmode;
4247 break;
4248
4249 case GEU:
4250 cc_mode = CCL3mode;
4251 break;
4252
4253 default:
4254 return false;
4255 }
4256
4257 /* Emit comparison instruction pattern. */
4258 if (!register_operand (cmp_op0, cmp_mode))
4259 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4260
4261 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4262 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4263 /* We use insn_invalid_p here to add clobbers if required. */
4264 ret = insn_invalid_p (emit_insn (insn));
4265 gcc_assert (!ret);
4266
4267 /* Emit ALC instruction pattern. */
4268 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4269 gen_rtx_REG (cc_mode, CC_REGNUM),
4270 const0_rtx);
4271
4272 if (src != const0_rtx)
4273 {
4274 if (!register_operand (src, GET_MODE (dst)))
4275 src = force_reg (GET_MODE (dst), src);
4276
4277 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4278 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4279 }
4280
4281 p = rtvec_alloc (2);
4282 RTVEC_ELT (p, 0) =
4283 gen_rtx_SET (VOIDmode, dst, op_res);
4284 RTVEC_ELT (p, 1) =
4285 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4286 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4287
4288 return true;
4289 }
4290
4291 /* Try SUBTRACT LOGICAL WITH BORROW. */
4292 if (increment == constm1_rtx)
4293 {
4294 /* Determine CC mode to use. */
4295 if (cmp_code == EQ || cmp_code == NE)
4296 {
4297 if (cmp_op1 != const0_rtx)
4298 {
4299 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4300 NULL_RTX, 0, OPTAB_WIDEN);
4301 cmp_op1 = const0_rtx;
4302 }
4303
4304 cmp_code = cmp_code == EQ ? LEU : GTU;
4305 }
4306
4307 if (cmp_code == GTU || cmp_code == GEU)
4308 {
4309 rtx tem = cmp_op0;
4310 cmp_op0 = cmp_op1;
4311 cmp_op1 = tem;
4312 cmp_code = swap_condition (cmp_code);
4313 }
4314
4315 switch (cmp_code)
4316 {
4317 case LEU:
4318 cc_mode = CCUmode;
4319 break;
4320
4321 case LTU:
4322 cc_mode = CCL3mode;
4323 break;
4324
4325 default:
4326 return false;
4327 }
4328
4329 /* Emit comparison instruction pattern. */
4330 if (!register_operand (cmp_op0, cmp_mode))
4331 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4332
4333 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4334 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4335 /* We use insn_invalid_p here to add clobbers if required. */
4336 ret = insn_invalid_p (emit_insn (insn));
4337 gcc_assert (!ret);
4338
4339 /* Emit SLB instruction pattern. */
4340 if (!register_operand (src, GET_MODE (dst)))
4341 src = force_reg (GET_MODE (dst), src);
4342
4343 op_res = gen_rtx_MINUS (GET_MODE (dst),
4344 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4345 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4346 gen_rtx_REG (cc_mode, CC_REGNUM),
4347 const0_rtx));
4348 p = rtvec_alloc (2);
4349 RTVEC_ELT (p, 0) =
4350 gen_rtx_SET (VOIDmode, dst, op_res);
4351 RTVEC_ELT (p, 1) =
4352 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4353 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4354
4355 return true;
4356 }
4357
4358 return false;
4359 }
4360
4361 /* Expand code for the insv template. Return true if successful. */
4362
4363 bool
4364 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4365 {
4366 int bitsize = INTVAL (op1);
4367 int bitpos = INTVAL (op2);
4368
4369 /* On z10 we can use the risbg instruction to implement insv. */
4370 if (TARGET_Z10
4371 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4372 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4373 {
4374 rtx op;
4375 rtx clobber;
4376
4377 op = gen_rtx_SET (GET_MODE(src),
4378 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4379 src);
4380 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4381 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4382
4383 return true;
4384 }
4385
4386 /* We need byte alignment. */
4387 if (bitsize % BITS_PER_UNIT)
4388 return false;
4389
4390 if (bitpos == 0
4391 && memory_operand (dest, VOIDmode)
4392 && (register_operand (src, word_mode)
4393 || const_int_operand (src, VOIDmode)))
4394 {
4395 /* Emit standard pattern if possible. */
4396 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4397 if (GET_MODE_BITSIZE (mode) == bitsize)
4398 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4399
4400 /* (set (ze (mem)) (const_int)). */
4401 else if (const_int_operand (src, VOIDmode))
4402 {
4403 int size = bitsize / BITS_PER_UNIT;
4404 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4405 GET_MODE_SIZE (word_mode) - size);
4406
4407 dest = adjust_address (dest, BLKmode, 0);
4408 set_mem_size (dest, GEN_INT (size));
4409 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4410 }
4411
4412 /* (set (ze (mem)) (reg)). */
4413 else if (register_operand (src, word_mode))
4414 {
4415 if (bitsize <= GET_MODE_BITSIZE (SImode))
4416 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4417 const0_rtx), src);
4418 else
4419 {
4420 /* Emit st,stcmh sequence. */
4421 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4422 int size = stcmh_width / BITS_PER_UNIT;
4423
4424 emit_move_insn (adjust_address (dest, SImode, size),
4425 gen_lowpart (SImode, src));
4426 set_mem_size (dest, GEN_INT (size));
4427 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4428 (stcmh_width), const0_rtx),
4429 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4430 (GET_MODE_BITSIZE (SImode))));
4431 }
4432 }
4433 else
4434 return false;
4435
4436 return true;
4437 }
4438
4439 /* (set (ze (reg)) (const_int)). */
4440 if (TARGET_ZARCH
4441 && register_operand (dest, word_mode)
4442 && (bitpos % 16) == 0
4443 && (bitsize % 16) == 0
4444 && const_int_operand (src, VOIDmode))
4445 {
4446 HOST_WIDE_INT val = INTVAL (src);
4447 int regpos = bitpos + bitsize;
4448
4449 while (regpos > bitpos)
4450 {
4451 enum machine_mode putmode;
4452 int putsize;
4453
4454 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4455 putmode = SImode;
4456 else
4457 putmode = HImode;
4458
4459 putsize = GET_MODE_BITSIZE (putmode);
4460 regpos -= putsize;
4461 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4462 GEN_INT (putsize),
4463 GEN_INT (regpos)),
4464 gen_int_mode (val, putmode));
4465 val >>= putsize;
4466 }
4467 gcc_assert (regpos == bitpos);
4468 return true;
4469 }
4470
4471 return false;
4472 }
4473
4474 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4475 register that holds VAL of mode MODE shifted by COUNT bits. */
4476
4477 static inline rtx
4478 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4479 {
4480 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4481 NULL_RTX, 1, OPTAB_DIRECT);
4482 return expand_simple_binop (SImode, ASHIFT, val, count,
4483 NULL_RTX, 1, OPTAB_DIRECT);
4484 }
4485
4486 /* Structure to hold the initial parameters for a compare_and_swap operation
4487 in HImode and QImode. */
4488
4489 struct alignment_context
4490 {
4491 rtx memsi; /* SI aligned memory location. */
4492 rtx shift; /* Bit offset with regard to lsb. */
4493 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4494 rtx modemaski; /* ~modemask */
4495 bool aligned; /* True if memory is aligned, false else. */
4496 };
4497
4498 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4499 structure AC for transparent simplifying, if the memory alignment is known
4500 to be at least 32bit. MEM is the memory location for the actual operation
4501 and MODE its mode. */
4502
4503 static void
4504 init_alignment_context (struct alignment_context *ac, rtx mem,
4505 enum machine_mode mode)
4506 {
4507 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4508 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4509
4510 if (ac->aligned)
4511 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4512 else
4513 {
4514 /* Alignment is unknown. */
4515 rtx byteoffset, addr, align;
4516
4517 /* Force the address into a register. */
4518 addr = force_reg (Pmode, XEXP (mem, 0));
4519
4520 /* Align it to SImode. */
4521 align = expand_simple_binop (Pmode, AND, addr,
4522 GEN_INT (-GET_MODE_SIZE (SImode)),
4523 NULL_RTX, 1, OPTAB_DIRECT);
4524 /* Generate MEM. */
4525 ac->memsi = gen_rtx_MEM (SImode, align);
4526 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4527 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4528 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4529
4530 /* Calculate shiftcount. */
4531 byteoffset = expand_simple_binop (Pmode, AND, addr,
4532 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4533 NULL_RTX, 1, OPTAB_DIRECT);
4534 /* As we already have some offset, evaluate the remaining distance. */
4535 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4536 NULL_RTX, 1, OPTAB_DIRECT);
4537
4538 }
4539 /* Shift is the byte count, but we need the bitcount. */
4540 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4541 NULL_RTX, 1, OPTAB_DIRECT);
4542 /* Calculate masks. */
4543 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4544 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4545 NULL_RTX, 1, OPTAB_DIRECT);
4546 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4547 }
4548
4549 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4550 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4551 to set if CMP == MEM.
4552 CMP is never in memory for compare_and_swap_cc because
4553 expand_bool_compare_and_swap puts it into a register for later compare. */
4554
4555 void
4556 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4557 {
4558 struct alignment_context ac;
4559 rtx cmpv, newv, val, resv, cc;
4560 rtx res = gen_reg_rtx (SImode);
4561 rtx csloop = gen_label_rtx ();
4562 rtx csend = gen_label_rtx ();
4563
4564 gcc_assert (register_operand (target, VOIDmode));
4565 gcc_assert (MEM_P (mem));
4566
4567 init_alignment_context (&ac, mem, mode);
4568
4569 /* Shift the values to the correct bit positions. */
4570 if (!(ac.aligned && MEM_P (cmp)))
4571 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4572 if (!(ac.aligned && MEM_P (new_rtx)))
4573 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4574
4575 /* Load full word. Subsequent loads are performed by CS. */
4576 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4577 NULL_RTX, 1, OPTAB_DIRECT);
4578
4579 /* Start CS loop. */
4580 emit_label (csloop);
4581 /* val = "<mem>00..0<mem>"
4582 * cmp = "00..0<cmp>00..0"
4583 * new = "00..0<new>00..0"
4584 */
4585
4586 /* Patch cmp and new with val at correct position. */
4587 if (ac.aligned && MEM_P (cmp))
4588 {
4589 cmpv = force_reg (SImode, val);
4590 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4591 }
4592 else
4593 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4594 NULL_RTX, 1, OPTAB_DIRECT));
4595 if (ac.aligned && MEM_P (new_rtx))
4596 {
4597 newv = force_reg (SImode, val);
4598 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4599 }
4600 else
4601 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4602 NULL_RTX, 1, OPTAB_DIRECT));
4603
4604 /* Jump to end if we're done (likely?). */
4605 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4606 cmpv, newv));
4607
4608 /* Check for changes outside mode. */
4609 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4610 NULL_RTX, 1, OPTAB_DIRECT);
4611 cc = s390_emit_compare (NE, resv, val);
4612 emit_move_insn (val, resv);
4613 /* Loop internal if so. */
4614 s390_emit_jump (csloop, cc);
4615
4616 emit_label (csend);
4617
4618 /* Return the correct part of the bitfield. */
4619 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4620 NULL_RTX, 1, OPTAB_DIRECT), 1);
4621 }
4622
4623 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4624 and VAL the value to play with. If AFTER is true then store the value
4625 MEM holds after the operation, if AFTER is false then store the value MEM
4626 holds before the operation. If TARGET is zero then discard that value, else
4627 store it to TARGET. */
4628
4629 void
4630 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4631 rtx target, rtx mem, rtx val, bool after)
4632 {
4633 struct alignment_context ac;
4634 rtx cmp;
4635 rtx new_rtx = gen_reg_rtx (SImode);
4636 rtx orig = gen_reg_rtx (SImode);
4637 rtx csloop = gen_label_rtx ();
4638
4639 gcc_assert (!target || register_operand (target, VOIDmode));
4640 gcc_assert (MEM_P (mem));
4641
4642 init_alignment_context (&ac, mem, mode);
4643
4644 /* Shift val to the correct bit positions.
4645 Preserve "icm", but prevent "ex icm". */
4646 if (!(ac.aligned && code == SET && MEM_P (val)))
4647 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4648
4649 /* Further preparation insns. */
4650 if (code == PLUS || code == MINUS)
4651 emit_move_insn (orig, val);
4652 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4653 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4654 NULL_RTX, 1, OPTAB_DIRECT);
4655
4656 /* Load full word. Subsequent loads are performed by CS. */
4657 cmp = force_reg (SImode, ac.memsi);
4658
4659 /* Start CS loop. */
4660 emit_label (csloop);
4661 emit_move_insn (new_rtx, cmp);
4662
4663 /* Patch new with val at correct position. */
4664 switch (code)
4665 {
4666 case PLUS:
4667 case MINUS:
4668 val = expand_simple_binop (SImode, code, new_rtx, orig,
4669 NULL_RTX, 1, OPTAB_DIRECT);
4670 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4671 NULL_RTX, 1, OPTAB_DIRECT);
4672 /* FALLTHRU */
4673 case SET:
4674 if (ac.aligned && MEM_P (val))
4675 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4676 else
4677 {
4678 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4679 NULL_RTX, 1, OPTAB_DIRECT);
4680 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4681 NULL_RTX, 1, OPTAB_DIRECT);
4682 }
4683 break;
4684 case AND:
4685 case IOR:
4686 case XOR:
4687 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4688 NULL_RTX, 1, OPTAB_DIRECT);
4689 break;
4690 case MULT: /* NAND */
4691 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4692 NULL_RTX, 1, OPTAB_DIRECT);
4693 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4694 NULL_RTX, 1, OPTAB_DIRECT);
4695 break;
4696 default:
4697 gcc_unreachable ();
4698 }
4699
4700 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4701 ac.memsi, cmp, new_rtx));
4702
4703 /* Return the correct part of the bitfield. */
4704 if (target)
4705 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4706 after ? new_rtx : cmp, ac.shift,
4707 NULL_RTX, 1, OPTAB_DIRECT), 1);
4708 }
4709
4710 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4711 We need to emit DTP-relative relocations. */
4712
4713 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4714
4715 static void
4716 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4717 {
4718 switch (size)
4719 {
4720 case 4:
4721 fputs ("\t.long\t", file);
4722 break;
4723 case 8:
4724 fputs ("\t.quad\t", file);
4725 break;
4726 default:
4727 gcc_unreachable ();
4728 }
4729 output_addr_const (file, x);
4730 fputs ("@DTPOFF", file);
4731 }
4732
4733 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4734 /* Implement TARGET_MANGLE_TYPE. */
4735
4736 static const char *
4737 s390_mangle_type (const_tree type)
4738 {
4739 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4740 && TARGET_LONG_DOUBLE_128)
4741 return "g";
4742
4743 /* For all other types, use normal C++ mangling. */
4744 return NULL;
4745 }
4746 #endif
4747
4748 /* In the name of slightly smaller debug output, and to cater to
4749 general assembler lossage, recognize various UNSPEC sequences
4750 and turn them back into a direct symbol reference. */
4751
4752 static rtx
4753 s390_delegitimize_address (rtx orig_x)
4754 {
4755 rtx x = orig_x, y;
4756
4757 if (GET_CODE (x) != MEM)
4758 return orig_x;
4759
4760 x = XEXP (x, 0);
4761 if (GET_CODE (x) == PLUS
4762 && GET_CODE (XEXP (x, 1)) == CONST
4763 && GET_CODE (XEXP (x, 0)) == REG
4764 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4765 {
4766 y = XEXP (XEXP (x, 1), 0);
4767 if (GET_CODE (y) == UNSPEC
4768 && XINT (y, 1) == UNSPEC_GOT)
4769 return XVECEXP (y, 0, 0);
4770 return orig_x;
4771 }
4772
4773 if (GET_CODE (x) == CONST)
4774 {
4775 y = XEXP (x, 0);
4776 if (GET_CODE (y) == UNSPEC
4777 && XINT (y, 1) == UNSPEC_GOTENT)
4778 return XVECEXP (y, 0, 0);
4779 return orig_x;
4780 }
4781
4782 return orig_x;
4783 }
4784
4785 /* Output operand OP to stdio stream FILE.
4786 OP is an address (register + offset) which is not used to address data;
4787 instead the rightmost bits are interpreted as the value. */
4788
4789 static void
4790 print_shift_count_operand (FILE *file, rtx op)
4791 {
4792 HOST_WIDE_INT offset;
4793 rtx base;
4794
4795 /* Extract base register and offset. */
4796 if (!s390_decompose_shift_count (op, &base, &offset))
4797 gcc_unreachable ();
4798
4799 /* Sanity check. */
4800 if (base)
4801 {
4802 gcc_assert (GET_CODE (base) == REG);
4803 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4804 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4805 }
4806
4807 /* Offsets are constricted to twelve bits. */
4808 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4809 if (base)
4810 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4811 }
4812
4813 /* See 'get_some_local_dynamic_name'. */
4814
4815 static int
4816 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4817 {
4818 rtx x = *px;
4819
4820 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4821 {
4822 x = get_pool_constant (x);
4823 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4824 }
4825
4826 if (GET_CODE (x) == SYMBOL_REF
4827 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4828 {
4829 cfun->machine->some_ld_name = XSTR (x, 0);
4830 return 1;
4831 }
4832
4833 return 0;
4834 }
4835
4836 /* Locate some local-dynamic symbol still in use by this function
4837 so that we can print its name in local-dynamic base patterns. */
4838
4839 static const char *
4840 get_some_local_dynamic_name (void)
4841 {
4842 rtx insn;
4843
4844 if (cfun->machine->some_ld_name)
4845 return cfun->machine->some_ld_name;
4846
4847 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4848 if (INSN_P (insn)
4849 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4850 return cfun->machine->some_ld_name;
4851
4852 gcc_unreachable ();
4853 }
4854
4855 /* Output machine-dependent UNSPECs occurring in address constant X
4856 in assembler syntax to stdio stream FILE. Returns true if the
4857 constant X could be recognized, false otherwise. */
4858
4859 bool
4860 s390_output_addr_const_extra (FILE *file, rtx x)
4861 {
4862 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4863 switch (XINT (x, 1))
4864 {
4865 case UNSPEC_GOTENT:
4866 output_addr_const (file, XVECEXP (x, 0, 0));
4867 fprintf (file, "@GOTENT");
4868 return true;
4869 case UNSPEC_GOT:
4870 output_addr_const (file, XVECEXP (x, 0, 0));
4871 fprintf (file, "@GOT");
4872 return true;
4873 case UNSPEC_GOTOFF:
4874 output_addr_const (file, XVECEXP (x, 0, 0));
4875 fprintf (file, "@GOTOFF");
4876 return true;
4877 case UNSPEC_PLT:
4878 output_addr_const (file, XVECEXP (x, 0, 0));
4879 fprintf (file, "@PLT");
4880 return true;
4881 case UNSPEC_PLTOFF:
4882 output_addr_const (file, XVECEXP (x, 0, 0));
4883 fprintf (file, "@PLTOFF");
4884 return true;
4885 case UNSPEC_TLSGD:
4886 output_addr_const (file, XVECEXP (x, 0, 0));
4887 fprintf (file, "@TLSGD");
4888 return true;
4889 case UNSPEC_TLSLDM:
4890 assemble_name (file, get_some_local_dynamic_name ());
4891 fprintf (file, "@TLSLDM");
4892 return true;
4893 case UNSPEC_DTPOFF:
4894 output_addr_const (file, XVECEXP (x, 0, 0));
4895 fprintf (file, "@DTPOFF");
4896 return true;
4897 case UNSPEC_NTPOFF:
4898 output_addr_const (file, XVECEXP (x, 0, 0));
4899 fprintf (file, "@NTPOFF");
4900 return true;
4901 case UNSPEC_GOTNTPOFF:
4902 output_addr_const (file, XVECEXP (x, 0, 0));
4903 fprintf (file, "@GOTNTPOFF");
4904 return true;
4905 case UNSPEC_INDNTPOFF:
4906 output_addr_const (file, XVECEXP (x, 0, 0));
4907 fprintf (file, "@INDNTPOFF");
4908 return true;
4909 }
4910
4911 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
4912 switch (XINT (x, 1))
4913 {
4914 case UNSPEC_POOL_OFFSET:
4915 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
4916 output_addr_const (file, x);
4917 return true;
4918 }
4919 return false;
4920 }
4921
4922 /* Output address operand ADDR in assembler syntax to
4923 stdio stream FILE. */
4924
4925 void
4926 print_operand_address (FILE *file, rtx addr)
4927 {
4928 struct s390_address ad;
4929
4930 if (s390_symref_operand_p (addr, NULL, NULL))
4931 {
4932 gcc_assert (TARGET_Z10);
4933 output_addr_const (file, addr);
4934 return;
4935 }
4936
4937 if (!s390_decompose_address (addr, &ad)
4938 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4939 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4940 output_operand_lossage ("cannot decompose address");
4941
4942 if (ad.disp)
4943 output_addr_const (file, ad.disp);
4944 else
4945 fprintf (file, "0");
4946
4947 if (ad.base && ad.indx)
4948 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4949 reg_names[REGNO (ad.base)]);
4950 else if (ad.base)
4951 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4952 }
4953
4954 /* Output operand X in assembler syntax to stdio stream FILE.
4955 CODE specified the format flag. The following format flags
4956 are recognized:
4957
4958 'C': print opcode suffix for branch condition.
4959 'D': print opcode suffix for inverse branch condition.
4960 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4961 'G': print the size of the operand in bytes.
4962 'O': print only the displacement of a memory reference.
4963 'R': print only the base register of a memory reference.
4964 'S': print S-type memory reference (base+displacement).
4965 'N': print the second word of a DImode operand.
4966 'M': print the second word of a TImode operand.
4967 'Y': print shift count operand.
4968
4969 'b': print integer X as if it's an unsigned byte.
4970 'c': print integer X as if it's an signed byte.
4971 'x': print integer X as if it's an unsigned halfword.
4972 'h': print integer X as if it's a signed halfword.
4973 'i': print the first nonzero HImode part of X.
4974 'j': print the first HImode part unequal to -1 of X.
4975 'k': print the first nonzero SImode part of X.
4976 'm': print the first SImode part unequal to -1 of X.
4977 'o': print integer X as if it's an unsigned 32bit word. */
4978
4979 void
4980 print_operand (FILE *file, rtx x, int code)
4981 {
4982 switch (code)
4983 {
4984 case 'C':
4985 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4986 return;
4987
4988 case 'D':
4989 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4990 return;
4991
4992 case 'J':
4993 if (GET_CODE (x) == SYMBOL_REF)
4994 {
4995 fprintf (file, "%s", ":tls_load:");
4996 output_addr_const (file, x);
4997 }
4998 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4999 {
5000 fprintf (file, "%s", ":tls_gdcall:");
5001 output_addr_const (file, XVECEXP (x, 0, 0));
5002 }
5003 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5004 {
5005 fprintf (file, "%s", ":tls_ldcall:");
5006 assemble_name (file, get_some_local_dynamic_name ());
5007 }
5008 else
5009 gcc_unreachable ();
5010 return;
5011
5012 case 'G':
5013 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5014 return;
5015
5016 case 'O':
5017 {
5018 struct s390_address ad;
5019 int ret;
5020
5021 gcc_assert (GET_CODE (x) == MEM);
5022 ret = s390_decompose_address (XEXP (x, 0), &ad);
5023 gcc_assert (ret);
5024 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5025 gcc_assert (!ad.indx);
5026
5027 if (ad.disp)
5028 output_addr_const (file, ad.disp);
5029 else
5030 fprintf (file, "0");
5031 }
5032 return;
5033
5034 case 'R':
5035 {
5036 struct s390_address ad;
5037 int ret;
5038
5039 gcc_assert (GET_CODE (x) == MEM);
5040 ret = s390_decompose_address (XEXP (x, 0), &ad);
5041 gcc_assert (ret);
5042 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5043 gcc_assert (!ad.indx);
5044
5045 if (ad.base)
5046 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5047 else
5048 fprintf (file, "0");
5049 }
5050 return;
5051
5052 case 'S':
5053 {
5054 struct s390_address ad;
5055 int ret;
5056
5057 gcc_assert (GET_CODE (x) == MEM);
5058 ret = s390_decompose_address (XEXP (x, 0), &ad);
5059 gcc_assert (ret);
5060 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5061 gcc_assert (!ad.indx);
5062
5063 if (ad.disp)
5064 output_addr_const (file, ad.disp);
5065 else
5066 fprintf (file, "0");
5067
5068 if (ad.base)
5069 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5070 }
5071 return;
5072
5073 case 'N':
5074 if (GET_CODE (x) == REG)
5075 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5076 else if (GET_CODE (x) == MEM)
5077 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5078 else
5079 gcc_unreachable ();
5080 break;
5081
5082 case 'M':
5083 if (GET_CODE (x) == REG)
5084 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5085 else if (GET_CODE (x) == MEM)
5086 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5087 else
5088 gcc_unreachable ();
5089 break;
5090
5091 case 'Y':
5092 print_shift_count_operand (file, x);
5093 return;
5094 }
5095
5096 switch (GET_CODE (x))
5097 {
5098 case REG:
5099 fprintf (file, "%s", reg_names[REGNO (x)]);
5100 break;
5101
5102 case MEM:
5103 output_address (XEXP (x, 0));
5104 break;
5105
5106 case CONST:
5107 case CODE_LABEL:
5108 case LABEL_REF:
5109 case SYMBOL_REF:
5110 output_addr_const (file, x);
5111 break;
5112
5113 case CONST_INT:
5114 if (code == 'b')
5115 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5116 else if (code == 'c')
5117 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5118 else if (code == 'x')
5119 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5120 else if (code == 'h')
5121 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5122 else if (code == 'i')
5123 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5124 s390_extract_part (x, HImode, 0));
5125 else if (code == 'j')
5126 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5127 s390_extract_part (x, HImode, -1));
5128 else if (code == 'k')
5129 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5130 s390_extract_part (x, SImode, 0));
5131 else if (code == 'm')
5132 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5133 s390_extract_part (x, SImode, -1));
5134 else if (code == 'o')
5135 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5136 else
5137 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5138 break;
5139
5140 case CONST_DOUBLE:
5141 gcc_assert (GET_MODE (x) == VOIDmode);
5142 if (code == 'b')
5143 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5144 else if (code == 'x')
5145 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5146 else if (code == 'h')
5147 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5148 else
5149 gcc_unreachable ();
5150 break;
5151
5152 default:
5153 fatal_insn ("UNKNOWN in print_operand !?", x);
5154 break;
5155 }
5156 }
5157
5158 /* Target hook for assembling integer objects. We need to define it
5159 here to work a round a bug in some versions of GAS, which couldn't
5160 handle values smaller than INT_MIN when printed in decimal. */
5161
5162 static bool
5163 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5164 {
5165 if (size == 8 && aligned_p
5166 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5167 {
5168 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5169 INTVAL (x));
5170 return true;
5171 }
5172 return default_assemble_integer (x, size, aligned_p);
5173 }
5174
5175 /* Returns true if register REGNO is used for forming
5176 a memory address in expression X. */
5177
5178 static bool
5179 reg_used_in_mem_p (int regno, rtx x)
5180 {
5181 enum rtx_code code = GET_CODE (x);
5182 int i, j;
5183 const char *fmt;
5184
5185 if (code == MEM)
5186 {
5187 if (refers_to_regno_p (regno, regno+1,
5188 XEXP (x, 0), 0))
5189 return true;
5190 }
5191 else if (code == SET
5192 && GET_CODE (SET_DEST (x)) == PC)
5193 {
5194 if (refers_to_regno_p (regno, regno+1,
5195 SET_SRC (x), 0))
5196 return true;
5197 }
5198
5199 fmt = GET_RTX_FORMAT (code);
5200 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5201 {
5202 if (fmt[i] == 'e'
5203 && reg_used_in_mem_p (regno, XEXP (x, i)))
5204 return true;
5205
5206 else if (fmt[i] == 'E')
5207 for (j = 0; j < XVECLEN (x, i); j++)
5208 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5209 return true;
5210 }
5211 return false;
5212 }
5213
5214 /* Returns true if expression DEP_RTX sets an address register
5215 used by instruction INSN to address memory. */
5216
5217 static bool
5218 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5219 {
5220 rtx target, pat;
5221
5222 if (GET_CODE (dep_rtx) == INSN)
5223 dep_rtx = PATTERN (dep_rtx);
5224
5225 if (GET_CODE (dep_rtx) == SET)
5226 {
5227 target = SET_DEST (dep_rtx);
5228 if (GET_CODE (target) == STRICT_LOW_PART)
5229 target = XEXP (target, 0);
5230 while (GET_CODE (target) == SUBREG)
5231 target = SUBREG_REG (target);
5232
5233 if (GET_CODE (target) == REG)
5234 {
5235 int regno = REGNO (target);
5236
5237 if (s390_safe_attr_type (insn) == TYPE_LA)
5238 {
5239 pat = PATTERN (insn);
5240 if (GET_CODE (pat) == PARALLEL)
5241 {
5242 gcc_assert (XVECLEN (pat, 0) == 2);
5243 pat = XVECEXP (pat, 0, 0);
5244 }
5245 gcc_assert (GET_CODE (pat) == SET);
5246 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5247 }
5248 else if (get_attr_atype (insn) == ATYPE_AGEN)
5249 return reg_used_in_mem_p (regno, PATTERN (insn));
5250 }
5251 }
5252 return false;
5253 }
5254
5255 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5256
5257 int
5258 s390_agen_dep_p (rtx dep_insn, rtx insn)
5259 {
5260 rtx dep_rtx = PATTERN (dep_insn);
5261 int i;
5262
5263 if (GET_CODE (dep_rtx) == SET
5264 && addr_generation_dependency_p (dep_rtx, insn))
5265 return 1;
5266 else if (GET_CODE (dep_rtx) == PARALLEL)
5267 {
5268 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5269 {
5270 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5271 return 1;
5272 }
5273 }
5274 return 0;
5275 }
5276
5277
5278 /* A C statement (sans semicolon) to update the integer scheduling priority
5279 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5280 reduce the priority to execute INSN later. Do not define this macro if
5281 you do not need to adjust the scheduling priorities of insns.
5282
5283 A STD instruction should be scheduled earlier,
5284 in order to use the bypass. */
5285
5286 static int
5287 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5288 {
5289 if (! INSN_P (insn))
5290 return priority;
5291
5292 if (s390_tune != PROCESSOR_2084_Z990
5293 && s390_tune != PROCESSOR_2094_Z9_109)
5294 return priority;
5295
5296 switch (s390_safe_attr_type (insn))
5297 {
5298 case TYPE_FSTOREDF:
5299 case TYPE_FSTORESF:
5300 priority = priority << 3;
5301 break;
5302 case TYPE_STORE:
5303 case TYPE_STM:
5304 priority = priority << 1;
5305 break;
5306 default:
5307 break;
5308 }
5309 return priority;
5310 }
5311
5312 /* The number of instructions that can be issued per cycle. */
5313
5314 static int
5315 s390_issue_rate (void)
5316 {
5317 switch (s390_tune)
5318 {
5319 case PROCESSOR_2084_Z990:
5320 case PROCESSOR_2094_Z9_109:
5321 return 3;
5322 case PROCESSOR_2097_Z10:
5323 return 2;
5324 default:
5325 return 1;
5326 }
5327 }
5328
5329 static int
5330 s390_first_cycle_multipass_dfa_lookahead (void)
5331 {
5332 return 4;
5333 }
5334
5335
5336 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5337 Fix up MEMs as required. */
5338
5339 static void
5340 annotate_constant_pool_refs (rtx *x)
5341 {
5342 int i, j;
5343 const char *fmt;
5344
5345 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5346 || !CONSTANT_POOL_ADDRESS_P (*x));
5347
5348 /* Literal pool references can only occur inside a MEM ... */
5349 if (GET_CODE (*x) == MEM)
5350 {
5351 rtx memref = XEXP (*x, 0);
5352
5353 if (GET_CODE (memref) == SYMBOL_REF
5354 && CONSTANT_POOL_ADDRESS_P (memref))
5355 {
5356 rtx base = cfun->machine->base_reg;
5357 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5358 UNSPEC_LTREF);
5359
5360 *x = replace_equiv_address (*x, addr);
5361 return;
5362 }
5363
5364 if (GET_CODE (memref) == CONST
5365 && GET_CODE (XEXP (memref, 0)) == PLUS
5366 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5367 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5368 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5369 {
5370 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5371 rtx sym = XEXP (XEXP (memref, 0), 0);
5372 rtx base = cfun->machine->base_reg;
5373 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5374 UNSPEC_LTREF);
5375
5376 *x = replace_equiv_address (*x, plus_constant (addr, off));
5377 return;
5378 }
5379 }
5380
5381 /* ... or a load-address type pattern. */
5382 if (GET_CODE (*x) == SET)
5383 {
5384 rtx addrref = SET_SRC (*x);
5385
5386 if (GET_CODE (addrref) == SYMBOL_REF
5387 && CONSTANT_POOL_ADDRESS_P (addrref))
5388 {
5389 rtx base = cfun->machine->base_reg;
5390 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5391 UNSPEC_LTREF);
5392
5393 SET_SRC (*x) = addr;
5394 return;
5395 }
5396
5397 if (GET_CODE (addrref) == CONST
5398 && GET_CODE (XEXP (addrref, 0)) == PLUS
5399 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5400 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5401 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5402 {
5403 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5404 rtx sym = XEXP (XEXP (addrref, 0), 0);
5405 rtx base = cfun->machine->base_reg;
5406 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5407 UNSPEC_LTREF);
5408
5409 SET_SRC (*x) = plus_constant (addr, off);
5410 return;
5411 }
5412 }
5413
5414 /* Annotate LTREL_BASE as well. */
5415 if (GET_CODE (*x) == UNSPEC
5416 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5417 {
5418 rtx base = cfun->machine->base_reg;
5419 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5420 UNSPEC_LTREL_BASE);
5421 return;
5422 }
5423
5424 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5425 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5426 {
5427 if (fmt[i] == 'e')
5428 {
5429 annotate_constant_pool_refs (&XEXP (*x, i));
5430 }
5431 else if (fmt[i] == 'E')
5432 {
5433 for (j = 0; j < XVECLEN (*x, i); j++)
5434 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5435 }
5436 }
5437 }
5438
5439 /* Split all branches that exceed the maximum distance.
5440 Returns true if this created a new literal pool entry. */
5441
5442 static int
5443 s390_split_branches (void)
5444 {
5445 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5446 int new_literal = 0, ret;
5447 rtx insn, pat, tmp, target;
5448 rtx *label;
5449
5450 /* We need correct insn addresses. */
5451
5452 shorten_branches (get_insns ());
5453
5454 /* Find all branches that exceed 64KB, and split them. */
5455
5456 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5457 {
5458 if (GET_CODE (insn) != JUMP_INSN)
5459 continue;
5460
5461 pat = PATTERN (insn);
5462 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5463 pat = XVECEXP (pat, 0, 0);
5464 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5465 continue;
5466
5467 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5468 {
5469 label = &SET_SRC (pat);
5470 }
5471 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5472 {
5473 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5474 label = &XEXP (SET_SRC (pat), 1);
5475 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5476 label = &XEXP (SET_SRC (pat), 2);
5477 else
5478 continue;
5479 }
5480 else
5481 continue;
5482
5483 if (get_attr_length (insn) <= 4)
5484 continue;
5485
5486 /* We are going to use the return register as scratch register,
5487 make sure it will be saved/restored by the prologue/epilogue. */
5488 cfun_frame_layout.save_return_addr_p = 1;
5489
5490 if (!flag_pic)
5491 {
5492 new_literal = 1;
5493 tmp = force_const_mem (Pmode, *label);
5494 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5495 INSN_ADDRESSES_NEW (tmp, -1);
5496 annotate_constant_pool_refs (&PATTERN (tmp));
5497
5498 target = temp_reg;
5499 }
5500 else
5501 {
5502 new_literal = 1;
5503 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5504 UNSPEC_LTREL_OFFSET);
5505 target = gen_rtx_CONST (Pmode, target);
5506 target = force_const_mem (Pmode, target);
5507 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5508 INSN_ADDRESSES_NEW (tmp, -1);
5509 annotate_constant_pool_refs (&PATTERN (tmp));
5510
5511 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5512 cfun->machine->base_reg),
5513 UNSPEC_LTREL_BASE);
5514 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5515 }
5516
5517 ret = validate_change (insn, label, target, 0);
5518 gcc_assert (ret);
5519 }
5520
5521 return new_literal;
5522 }
5523
5524
5525 /* Find an annotated literal pool symbol referenced in RTX X,
5526 and store it at REF. Will abort if X contains references to
5527 more than one such pool symbol; multiple references to the same
5528 symbol are allowed, however.
5529
5530 The rtx pointed to by REF must be initialized to NULL_RTX
5531 by the caller before calling this routine. */
5532
5533 static void
5534 find_constant_pool_ref (rtx x, rtx *ref)
5535 {
5536 int i, j;
5537 const char *fmt;
5538
5539 /* Ignore LTREL_BASE references. */
5540 if (GET_CODE (x) == UNSPEC
5541 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5542 return;
5543 /* Likewise POOL_ENTRY insns. */
5544 if (GET_CODE (x) == UNSPEC_VOLATILE
5545 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5546 return;
5547
5548 gcc_assert (GET_CODE (x) != SYMBOL_REF
5549 || !CONSTANT_POOL_ADDRESS_P (x));
5550
5551 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5552 {
5553 rtx sym = XVECEXP (x, 0, 0);
5554 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5555 && CONSTANT_POOL_ADDRESS_P (sym));
5556
5557 if (*ref == NULL_RTX)
5558 *ref = sym;
5559 else
5560 gcc_assert (*ref == sym);
5561
5562 return;
5563 }
5564
5565 fmt = GET_RTX_FORMAT (GET_CODE (x));
5566 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5567 {
5568 if (fmt[i] == 'e')
5569 {
5570 find_constant_pool_ref (XEXP (x, i), ref);
5571 }
5572 else if (fmt[i] == 'E')
5573 {
5574 for (j = 0; j < XVECLEN (x, i); j++)
5575 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5576 }
5577 }
5578 }
5579
5580 /* Replace every reference to the annotated literal pool
5581 symbol REF in X by its base plus OFFSET. */
5582
5583 static void
5584 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5585 {
5586 int i, j;
5587 const char *fmt;
5588
5589 gcc_assert (*x != ref);
5590
5591 if (GET_CODE (*x) == UNSPEC
5592 && XINT (*x, 1) == UNSPEC_LTREF
5593 && XVECEXP (*x, 0, 0) == ref)
5594 {
5595 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5596 return;
5597 }
5598
5599 if (GET_CODE (*x) == PLUS
5600 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5601 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5602 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5603 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5604 {
5605 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5606 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5607 return;
5608 }
5609
5610 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5611 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5612 {
5613 if (fmt[i] == 'e')
5614 {
5615 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5616 }
5617 else if (fmt[i] == 'E')
5618 {
5619 for (j = 0; j < XVECLEN (*x, i); j++)
5620 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5621 }
5622 }
5623 }
5624
5625 /* Check whether X contains an UNSPEC_LTREL_BASE.
5626 Return its constant pool symbol if found, NULL_RTX otherwise. */
5627
5628 static rtx
5629 find_ltrel_base (rtx x)
5630 {
5631 int i, j;
5632 const char *fmt;
5633
5634 if (GET_CODE (x) == UNSPEC
5635 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5636 return XVECEXP (x, 0, 0);
5637
5638 fmt = GET_RTX_FORMAT (GET_CODE (x));
5639 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5640 {
5641 if (fmt[i] == 'e')
5642 {
5643 rtx fnd = find_ltrel_base (XEXP (x, i));
5644 if (fnd)
5645 return fnd;
5646 }
5647 else if (fmt[i] == 'E')
5648 {
5649 for (j = 0; j < XVECLEN (x, i); j++)
5650 {
5651 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5652 if (fnd)
5653 return fnd;
5654 }
5655 }
5656 }
5657
5658 return NULL_RTX;
5659 }
5660
5661 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5662
5663 static void
5664 replace_ltrel_base (rtx *x)
5665 {
5666 int i, j;
5667 const char *fmt;
5668
5669 if (GET_CODE (*x) == UNSPEC
5670 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5671 {
5672 *x = XVECEXP (*x, 0, 1);
5673 return;
5674 }
5675
5676 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5677 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5678 {
5679 if (fmt[i] == 'e')
5680 {
5681 replace_ltrel_base (&XEXP (*x, i));
5682 }
5683 else if (fmt[i] == 'E')
5684 {
5685 for (j = 0; j < XVECLEN (*x, i); j++)
5686 replace_ltrel_base (&XVECEXP (*x, i, j));
5687 }
5688 }
5689 }
5690
5691
5692 /* We keep a list of constants which we have to add to internal
5693 constant tables in the middle of large functions. */
5694
5695 #define NR_C_MODES 11
5696 enum machine_mode constant_modes[NR_C_MODES] =
5697 {
5698 TFmode, TImode, TDmode,
5699 DFmode, DImode, DDmode,
5700 SFmode, SImode, SDmode,
5701 HImode,
5702 QImode
5703 };
5704
5705 struct constant
5706 {
5707 struct constant *next;
5708 rtx value;
5709 rtx label;
5710 };
5711
5712 struct constant_pool
5713 {
5714 struct constant_pool *next;
5715 rtx first_insn;
5716 rtx pool_insn;
5717 bitmap insns;
5718 rtx emit_pool_after;
5719
5720 struct constant *constants[NR_C_MODES];
5721 struct constant *execute;
5722 rtx label;
5723 int size;
5724 };
5725
5726 /* Allocate new constant_pool structure. */
5727
5728 static struct constant_pool *
5729 s390_alloc_pool (void)
5730 {
5731 struct constant_pool *pool;
5732 int i;
5733
5734 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5735 pool->next = NULL;
5736 for (i = 0; i < NR_C_MODES; i++)
5737 pool->constants[i] = NULL;
5738
5739 pool->execute = NULL;
5740 pool->label = gen_label_rtx ();
5741 pool->first_insn = NULL_RTX;
5742 pool->pool_insn = NULL_RTX;
5743 pool->insns = BITMAP_ALLOC (NULL);
5744 pool->size = 0;
5745 pool->emit_pool_after = NULL_RTX;
5746
5747 return pool;
5748 }
5749
5750 /* Create new constant pool covering instructions starting at INSN
5751 and chain it to the end of POOL_LIST. */
5752
5753 static struct constant_pool *
5754 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5755 {
5756 struct constant_pool *pool, **prev;
5757
5758 pool = s390_alloc_pool ();
5759 pool->first_insn = insn;
5760
5761 for (prev = pool_list; *prev; prev = &(*prev)->next)
5762 ;
5763 *prev = pool;
5764
5765 return pool;
5766 }
5767
5768 /* End range of instructions covered by POOL at INSN and emit
5769 placeholder insn representing the pool. */
5770
5771 static void
5772 s390_end_pool (struct constant_pool *pool, rtx insn)
5773 {
5774 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5775
5776 if (!insn)
5777 insn = get_last_insn ();
5778
5779 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5780 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5781 }
5782
5783 /* Add INSN to the list of insns covered by POOL. */
5784
5785 static void
5786 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5787 {
5788 bitmap_set_bit (pool->insns, INSN_UID (insn));
5789 }
5790
5791 /* Return pool out of POOL_LIST that covers INSN. */
5792
5793 static struct constant_pool *
5794 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5795 {
5796 struct constant_pool *pool;
5797
5798 for (pool = pool_list; pool; pool = pool->next)
5799 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5800 break;
5801
5802 return pool;
5803 }
5804
5805 /* Add constant VAL of mode MODE to the constant pool POOL. */
5806
5807 static void
5808 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5809 {
5810 struct constant *c;
5811 int i;
5812
5813 for (i = 0; i < NR_C_MODES; i++)
5814 if (constant_modes[i] == mode)
5815 break;
5816 gcc_assert (i != NR_C_MODES);
5817
5818 for (c = pool->constants[i]; c != NULL; c = c->next)
5819 if (rtx_equal_p (val, c->value))
5820 break;
5821
5822 if (c == NULL)
5823 {
5824 c = (struct constant *) xmalloc (sizeof *c);
5825 c->value = val;
5826 c->label = gen_label_rtx ();
5827 c->next = pool->constants[i];
5828 pool->constants[i] = c;
5829 pool->size += GET_MODE_SIZE (mode);
5830 }
5831 }
5832
5833 /* Return an rtx that represents the offset of X from the start of
5834 pool POOL. */
5835
5836 static rtx
5837 s390_pool_offset (struct constant_pool *pool, rtx x)
5838 {
5839 rtx label;
5840
5841 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5842 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5843 UNSPEC_POOL_OFFSET);
5844 return gen_rtx_CONST (GET_MODE (x), x);
5845 }
5846
5847 /* Find constant VAL of mode MODE in the constant pool POOL.
5848 Return an RTX describing the distance from the start of
5849 the pool to the location of the new constant. */
5850
5851 static rtx
5852 s390_find_constant (struct constant_pool *pool, rtx val,
5853 enum machine_mode mode)
5854 {
5855 struct constant *c;
5856 int i;
5857
5858 for (i = 0; i < NR_C_MODES; i++)
5859 if (constant_modes[i] == mode)
5860 break;
5861 gcc_assert (i != NR_C_MODES);
5862
5863 for (c = pool->constants[i]; c != NULL; c = c->next)
5864 if (rtx_equal_p (val, c->value))
5865 break;
5866
5867 gcc_assert (c);
5868
5869 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5870 }
5871
5872 /* Check whether INSN is an execute. Return the label_ref to its
5873 execute target template if so, NULL_RTX otherwise. */
5874
5875 static rtx
5876 s390_execute_label (rtx insn)
5877 {
5878 if (GET_CODE (insn) == INSN
5879 && GET_CODE (PATTERN (insn)) == PARALLEL
5880 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5881 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5882 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5883
5884 return NULL_RTX;
5885 }
5886
5887 /* Add execute target for INSN to the constant pool POOL. */
5888
5889 static void
5890 s390_add_execute (struct constant_pool *pool, rtx insn)
5891 {
5892 struct constant *c;
5893
5894 for (c = pool->execute; c != NULL; c = c->next)
5895 if (INSN_UID (insn) == INSN_UID (c->value))
5896 break;
5897
5898 if (c == NULL)
5899 {
5900 c = (struct constant *) xmalloc (sizeof *c);
5901 c->value = insn;
5902 c->label = gen_label_rtx ();
5903 c->next = pool->execute;
5904 pool->execute = c;
5905 pool->size += 6;
5906 }
5907 }
5908
5909 /* Find execute target for INSN in the constant pool POOL.
5910 Return an RTX describing the distance from the start of
5911 the pool to the location of the execute target. */
5912
5913 static rtx
5914 s390_find_execute (struct constant_pool *pool, rtx insn)
5915 {
5916 struct constant *c;
5917
5918 for (c = pool->execute; c != NULL; c = c->next)
5919 if (INSN_UID (insn) == INSN_UID (c->value))
5920 break;
5921
5922 gcc_assert (c);
5923
5924 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5925 }
5926
5927 /* For an execute INSN, extract the execute target template. */
5928
5929 static rtx
5930 s390_execute_target (rtx insn)
5931 {
5932 rtx pattern = PATTERN (insn);
5933 gcc_assert (s390_execute_label (insn));
5934
5935 if (XVECLEN (pattern, 0) == 2)
5936 {
5937 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5938 }
5939 else
5940 {
5941 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5942 int i;
5943
5944 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5945 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5946
5947 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5948 }
5949
5950 return pattern;
5951 }
5952
5953 /* Indicate that INSN cannot be duplicated. This is the case for
5954 execute insns that carry a unique label. */
5955
5956 static bool
5957 s390_cannot_copy_insn_p (rtx insn)
5958 {
5959 rtx label = s390_execute_label (insn);
5960 return label && label != const0_rtx;
5961 }
5962
5963 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5964 do not emit the pool base label. */
5965
5966 static void
5967 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5968 {
5969 struct constant *c;
5970 rtx insn = pool->pool_insn;
5971 int i;
5972
5973 /* Switch to rodata section. */
5974 if (TARGET_CPU_ZARCH)
5975 {
5976 insn = emit_insn_after (gen_pool_section_start (), insn);
5977 INSN_ADDRESSES_NEW (insn, -1);
5978 }
5979
5980 /* Ensure minimum pool alignment. */
5981 if (TARGET_CPU_ZARCH)
5982 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5983 else
5984 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5985 INSN_ADDRESSES_NEW (insn, -1);
5986
5987 /* Emit pool base label. */
5988 if (!remote_label)
5989 {
5990 insn = emit_label_after (pool->label, insn);
5991 INSN_ADDRESSES_NEW (insn, -1);
5992 }
5993
5994 /* Dump constants in descending alignment requirement order,
5995 ensuring proper alignment for every constant. */
5996 for (i = 0; i < NR_C_MODES; i++)
5997 for (c = pool->constants[i]; c; c = c->next)
5998 {
5999 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6000 rtx value = copy_rtx (c->value);
6001 if (GET_CODE (value) == CONST
6002 && GET_CODE (XEXP (value, 0)) == UNSPEC
6003 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6004 && XVECLEN (XEXP (value, 0), 0) == 1)
6005 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6006
6007 insn = emit_label_after (c->label, insn);
6008 INSN_ADDRESSES_NEW (insn, -1);
6009
6010 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6011 gen_rtvec (1, value),
6012 UNSPECV_POOL_ENTRY);
6013 insn = emit_insn_after (value, insn);
6014 INSN_ADDRESSES_NEW (insn, -1);
6015 }
6016
6017 /* Ensure minimum alignment for instructions. */
6018 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6019 INSN_ADDRESSES_NEW (insn, -1);
6020
6021 /* Output in-pool execute template insns. */
6022 for (c = pool->execute; c; c = c->next)
6023 {
6024 insn = emit_label_after (c->label, insn);
6025 INSN_ADDRESSES_NEW (insn, -1);
6026
6027 insn = emit_insn_after (s390_execute_target (c->value), insn);
6028 INSN_ADDRESSES_NEW (insn, -1);
6029 }
6030
6031 /* Switch back to previous section. */
6032 if (TARGET_CPU_ZARCH)
6033 {
6034 insn = emit_insn_after (gen_pool_section_end (), insn);
6035 INSN_ADDRESSES_NEW (insn, -1);
6036 }
6037
6038 insn = emit_barrier_after (insn);
6039 INSN_ADDRESSES_NEW (insn, -1);
6040
6041 /* Remove placeholder insn. */
6042 remove_insn (pool->pool_insn);
6043 }
6044
6045 /* Free all memory used by POOL. */
6046
6047 static void
6048 s390_free_pool (struct constant_pool *pool)
6049 {
6050 struct constant *c, *next;
6051 int i;
6052
6053 for (i = 0; i < NR_C_MODES; i++)
6054 for (c = pool->constants[i]; c; c = next)
6055 {
6056 next = c->next;
6057 free (c);
6058 }
6059
6060 for (c = pool->execute; c; c = next)
6061 {
6062 next = c->next;
6063 free (c);
6064 }
6065
6066 BITMAP_FREE (pool->insns);
6067 free (pool);
6068 }
6069
6070
6071 /* Collect main literal pool. Return NULL on overflow. */
6072
6073 static struct constant_pool *
6074 s390_mainpool_start (void)
6075 {
6076 struct constant_pool *pool;
6077 rtx insn;
6078
6079 pool = s390_alloc_pool ();
6080
6081 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6082 {
6083 if (GET_CODE (insn) == INSN
6084 && GET_CODE (PATTERN (insn)) == SET
6085 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6086 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6087 {
6088 gcc_assert (!pool->pool_insn);
6089 pool->pool_insn = insn;
6090 }
6091
6092 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6093 {
6094 s390_add_execute (pool, insn);
6095 }
6096 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6097 {
6098 rtx pool_ref = NULL_RTX;
6099 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6100 if (pool_ref)
6101 {
6102 rtx constant = get_pool_constant (pool_ref);
6103 enum machine_mode mode = get_pool_mode (pool_ref);
6104 s390_add_constant (pool, constant, mode);
6105 }
6106 }
6107
6108 /* If hot/cold partitioning is enabled we have to make sure that
6109 the literal pool is emitted in the same section where the
6110 initialization of the literal pool base pointer takes place.
6111 emit_pool_after is only used in the non-overflow case on non
6112 Z cpus where we can emit the literal pool at the end of the
6113 function body within the text section. */
6114 if (NOTE_P (insn)
6115 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6116 && !pool->emit_pool_after)
6117 pool->emit_pool_after = PREV_INSN (insn);
6118 }
6119
6120 gcc_assert (pool->pool_insn || pool->size == 0);
6121
6122 if (pool->size >= 4096)
6123 {
6124 /* We're going to chunkify the pool, so remove the main
6125 pool placeholder insn. */
6126 remove_insn (pool->pool_insn);
6127
6128 s390_free_pool (pool);
6129 pool = NULL;
6130 }
6131
6132 /* If the functions ends with the section where the literal pool
6133 should be emitted set the marker to its end. */
6134 if (pool && !pool->emit_pool_after)
6135 pool->emit_pool_after = get_last_insn ();
6136
6137 return pool;
6138 }
6139
6140 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6141 Modify the current function to output the pool constants as well as
6142 the pool register setup instruction. */
6143
6144 static void
6145 s390_mainpool_finish (struct constant_pool *pool)
6146 {
6147 rtx base_reg = cfun->machine->base_reg;
6148 rtx insn;
6149
6150 /* If the pool is empty, we're done. */
6151 if (pool->size == 0)
6152 {
6153 /* We don't actually need a base register after all. */
6154 cfun->machine->base_reg = NULL_RTX;
6155
6156 if (pool->pool_insn)
6157 remove_insn (pool->pool_insn);
6158 s390_free_pool (pool);
6159 return;
6160 }
6161
6162 /* We need correct insn addresses. */
6163 shorten_branches (get_insns ());
6164
6165 /* On zSeries, we use a LARL to load the pool register. The pool is
6166 located in the .rodata section, so we emit it after the function. */
6167 if (TARGET_CPU_ZARCH)
6168 {
6169 insn = gen_main_base_64 (base_reg, pool->label);
6170 insn = emit_insn_after (insn, pool->pool_insn);
6171 INSN_ADDRESSES_NEW (insn, -1);
6172 remove_insn (pool->pool_insn);
6173
6174 insn = get_last_insn ();
6175 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6176 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6177
6178 s390_dump_pool (pool, 0);
6179 }
6180
6181 /* On S/390, if the total size of the function's code plus literal pool
6182 does not exceed 4096 bytes, we use BASR to set up a function base
6183 pointer, and emit the literal pool at the end of the function. */
6184 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6185 + pool->size + 8 /* alignment slop */ < 4096)
6186 {
6187 insn = gen_main_base_31_small (base_reg, pool->label);
6188 insn = emit_insn_after (insn, pool->pool_insn);
6189 INSN_ADDRESSES_NEW (insn, -1);
6190 remove_insn (pool->pool_insn);
6191
6192 insn = emit_label_after (pool->label, insn);
6193 INSN_ADDRESSES_NEW (insn, -1);
6194
6195 /* emit_pool_after will be set by s390_mainpool_start to the
6196 last insn of the section where the literal pool should be
6197 emitted. */
6198 insn = pool->emit_pool_after;
6199
6200 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6201 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6202
6203 s390_dump_pool (pool, 1);
6204 }
6205
6206 /* Otherwise, we emit an inline literal pool and use BASR to branch
6207 over it, setting up the pool register at the same time. */
6208 else
6209 {
6210 rtx pool_end = gen_label_rtx ();
6211
6212 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6213 insn = emit_insn_after (insn, pool->pool_insn);
6214 INSN_ADDRESSES_NEW (insn, -1);
6215 remove_insn (pool->pool_insn);
6216
6217 insn = emit_label_after (pool->label, insn);
6218 INSN_ADDRESSES_NEW (insn, -1);
6219
6220 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6221 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6222
6223 insn = emit_label_after (pool_end, pool->pool_insn);
6224 INSN_ADDRESSES_NEW (insn, -1);
6225
6226 s390_dump_pool (pool, 1);
6227 }
6228
6229
6230 /* Replace all literal pool references. */
6231
6232 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6233 {
6234 if (INSN_P (insn))
6235 replace_ltrel_base (&PATTERN (insn));
6236
6237 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6238 {
6239 rtx addr, pool_ref = NULL_RTX;
6240 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6241 if (pool_ref)
6242 {
6243 if (s390_execute_label (insn))
6244 addr = s390_find_execute (pool, insn);
6245 else
6246 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6247 get_pool_mode (pool_ref));
6248
6249 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6250 INSN_CODE (insn) = -1;
6251 }
6252 }
6253 }
6254
6255
6256 /* Free the pool. */
6257 s390_free_pool (pool);
6258 }
6259
6260 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6261 We have decided we cannot use this pool, so revert all changes
6262 to the current function that were done by s390_mainpool_start. */
6263 static void
6264 s390_mainpool_cancel (struct constant_pool *pool)
6265 {
6266 /* We didn't actually change the instruction stream, so simply
6267 free the pool memory. */
6268 s390_free_pool (pool);
6269 }
6270
6271
6272 /* Chunkify the literal pool. */
6273
6274 #define S390_POOL_CHUNK_MIN 0xc00
6275 #define S390_POOL_CHUNK_MAX 0xe00
6276
6277 static struct constant_pool *
6278 s390_chunkify_start (void)
6279 {
6280 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6281 int extra_size = 0;
6282 bitmap far_labels;
6283 rtx pending_ltrel = NULL_RTX;
6284 rtx insn;
6285
6286 rtx (*gen_reload_base) (rtx, rtx) =
6287 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6288
6289
6290 /* We need correct insn addresses. */
6291
6292 shorten_branches (get_insns ());
6293
6294 /* Scan all insns and move literals to pool chunks. */
6295
6296 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6297 {
6298 bool section_switch_p = false;
6299
6300 /* Check for pending LTREL_BASE. */
6301 if (INSN_P (insn))
6302 {
6303 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6304 if (ltrel_base)
6305 {
6306 gcc_assert (ltrel_base == pending_ltrel);
6307 pending_ltrel = NULL_RTX;
6308 }
6309 }
6310
6311 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6312 {
6313 if (!curr_pool)
6314 curr_pool = s390_start_pool (&pool_list, insn);
6315
6316 s390_add_execute (curr_pool, insn);
6317 s390_add_pool_insn (curr_pool, insn);
6318 }
6319 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6320 {
6321 rtx pool_ref = NULL_RTX;
6322 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6323 if (pool_ref)
6324 {
6325 rtx constant = get_pool_constant (pool_ref);
6326 enum machine_mode mode = get_pool_mode (pool_ref);
6327
6328 if (!curr_pool)
6329 curr_pool = s390_start_pool (&pool_list, insn);
6330
6331 s390_add_constant (curr_pool, constant, mode);
6332 s390_add_pool_insn (curr_pool, insn);
6333
6334 /* Don't split the pool chunk between a LTREL_OFFSET load
6335 and the corresponding LTREL_BASE. */
6336 if (GET_CODE (constant) == CONST
6337 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6338 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6339 {
6340 gcc_assert (!pending_ltrel);
6341 pending_ltrel = pool_ref;
6342 }
6343 }
6344 }
6345
6346 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6347 {
6348 if (curr_pool)
6349 s390_add_pool_insn (curr_pool, insn);
6350 /* An LTREL_BASE must follow within the same basic block. */
6351 gcc_assert (!pending_ltrel);
6352 }
6353
6354 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6355 section_switch_p = true;
6356
6357 if (!curr_pool
6358 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6359 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6360 continue;
6361
6362 if (TARGET_CPU_ZARCH)
6363 {
6364 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6365 continue;
6366
6367 s390_end_pool (curr_pool, NULL_RTX);
6368 curr_pool = NULL;
6369 }
6370 else
6371 {
6372 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6373 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6374 + extra_size;
6375
6376 /* We will later have to insert base register reload insns.
6377 Those will have an effect on code size, which we need to
6378 consider here. This calculation makes rather pessimistic
6379 worst-case assumptions. */
6380 if (GET_CODE (insn) == CODE_LABEL)
6381 extra_size += 6;
6382
6383 if (chunk_size < S390_POOL_CHUNK_MIN
6384 && curr_pool->size < S390_POOL_CHUNK_MIN
6385 && !section_switch_p)
6386 continue;
6387
6388 /* Pool chunks can only be inserted after BARRIERs ... */
6389 if (GET_CODE (insn) == BARRIER)
6390 {
6391 s390_end_pool (curr_pool, insn);
6392 curr_pool = NULL;
6393 extra_size = 0;
6394 }
6395
6396 /* ... so if we don't find one in time, create one. */
6397 else if (chunk_size > S390_POOL_CHUNK_MAX
6398 || curr_pool->size > S390_POOL_CHUNK_MAX
6399 || section_switch_p)
6400 {
6401 rtx label, jump, barrier;
6402
6403 if (!section_switch_p)
6404 {
6405 /* We can insert the barrier only after a 'real' insn. */
6406 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6407 continue;
6408 if (get_attr_length (insn) == 0)
6409 continue;
6410 /* Don't separate LTREL_BASE from the corresponding
6411 LTREL_OFFSET load. */
6412 if (pending_ltrel)
6413 continue;
6414 }
6415 else
6416 {
6417 gcc_assert (!pending_ltrel);
6418
6419 /* The old pool has to end before the section switch
6420 note in order to make it part of the current
6421 section. */
6422 insn = PREV_INSN (insn);
6423 }
6424
6425 label = gen_label_rtx ();
6426 jump = emit_jump_insn_after (gen_jump (label), insn);
6427 barrier = emit_barrier_after (jump);
6428 insn = emit_label_after (label, barrier);
6429 JUMP_LABEL (jump) = label;
6430 LABEL_NUSES (label) = 1;
6431
6432 INSN_ADDRESSES_NEW (jump, -1);
6433 INSN_ADDRESSES_NEW (barrier, -1);
6434 INSN_ADDRESSES_NEW (insn, -1);
6435
6436 s390_end_pool (curr_pool, barrier);
6437 curr_pool = NULL;
6438 extra_size = 0;
6439 }
6440 }
6441 }
6442
6443 if (curr_pool)
6444 s390_end_pool (curr_pool, NULL_RTX);
6445 gcc_assert (!pending_ltrel);
6446
6447 /* Find all labels that are branched into
6448 from an insn belonging to a different chunk. */
6449
6450 far_labels = BITMAP_ALLOC (NULL);
6451
6452 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6453 {
6454 /* Labels marked with LABEL_PRESERVE_P can be target
6455 of non-local jumps, so we have to mark them.
6456 The same holds for named labels.
6457
6458 Don't do that, however, if it is the label before
6459 a jump table. */
6460
6461 if (GET_CODE (insn) == CODE_LABEL
6462 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6463 {
6464 rtx vec_insn = next_real_insn (insn);
6465 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6466 PATTERN (vec_insn) : NULL_RTX;
6467 if (!vec_pat
6468 || !(GET_CODE (vec_pat) == ADDR_VEC
6469 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6470 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6471 }
6472
6473 /* If we have a direct jump (conditional or unconditional)
6474 or a casesi jump, check all potential targets. */
6475 else if (GET_CODE (insn) == JUMP_INSN)
6476 {
6477 rtx pat = PATTERN (insn);
6478 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6479 pat = XVECEXP (pat, 0, 0);
6480
6481 if (GET_CODE (pat) == SET)
6482 {
6483 rtx label = JUMP_LABEL (insn);
6484 if (label)
6485 {
6486 if (s390_find_pool (pool_list, label)
6487 != s390_find_pool (pool_list, insn))
6488 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6489 }
6490 }
6491 else if (GET_CODE (pat) == PARALLEL
6492 && XVECLEN (pat, 0) == 2
6493 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6494 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6495 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6496 {
6497 /* Find the jump table used by this casesi jump. */
6498 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6499 rtx vec_insn = next_real_insn (vec_label);
6500 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6501 PATTERN (vec_insn) : NULL_RTX;
6502 if (vec_pat
6503 && (GET_CODE (vec_pat) == ADDR_VEC
6504 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6505 {
6506 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6507
6508 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6509 {
6510 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6511
6512 if (s390_find_pool (pool_list, label)
6513 != s390_find_pool (pool_list, insn))
6514 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6515 }
6516 }
6517 }
6518 }
6519 }
6520
6521 /* Insert base register reload insns before every pool. */
6522
6523 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6524 {
6525 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6526 curr_pool->label);
6527 rtx insn = curr_pool->first_insn;
6528 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6529 }
6530
6531 /* Insert base register reload insns at every far label. */
6532
6533 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6534 if (GET_CODE (insn) == CODE_LABEL
6535 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6536 {
6537 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6538 if (pool)
6539 {
6540 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6541 pool->label);
6542 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6543 }
6544 }
6545
6546
6547 BITMAP_FREE (far_labels);
6548
6549
6550 /* Recompute insn addresses. */
6551
6552 init_insn_lengths ();
6553 shorten_branches (get_insns ());
6554
6555 return pool_list;
6556 }
6557
6558 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6559 After we have decided to use this list, finish implementing
6560 all changes to the current function as required. */
6561
6562 static void
6563 s390_chunkify_finish (struct constant_pool *pool_list)
6564 {
6565 struct constant_pool *curr_pool = NULL;
6566 rtx insn;
6567
6568
6569 /* Replace all literal pool references. */
6570
6571 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6572 {
6573 if (INSN_P (insn))
6574 replace_ltrel_base (&PATTERN (insn));
6575
6576 curr_pool = s390_find_pool (pool_list, insn);
6577 if (!curr_pool)
6578 continue;
6579
6580 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6581 {
6582 rtx addr, pool_ref = NULL_RTX;
6583 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6584 if (pool_ref)
6585 {
6586 if (s390_execute_label (insn))
6587 addr = s390_find_execute (curr_pool, insn);
6588 else
6589 addr = s390_find_constant (curr_pool,
6590 get_pool_constant (pool_ref),
6591 get_pool_mode (pool_ref));
6592
6593 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6594 INSN_CODE (insn) = -1;
6595 }
6596 }
6597 }
6598
6599 /* Dump out all literal pools. */
6600
6601 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6602 s390_dump_pool (curr_pool, 0);
6603
6604 /* Free pool list. */
6605
6606 while (pool_list)
6607 {
6608 struct constant_pool *next = pool_list->next;
6609 s390_free_pool (pool_list);
6610 pool_list = next;
6611 }
6612 }
6613
6614 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6615 We have decided we cannot use this list, so revert all changes
6616 to the current function that were done by s390_chunkify_start. */
6617
6618 static void
6619 s390_chunkify_cancel (struct constant_pool *pool_list)
6620 {
6621 struct constant_pool *curr_pool = NULL;
6622 rtx insn;
6623
6624 /* Remove all pool placeholder insns. */
6625
6626 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6627 {
6628 /* Did we insert an extra barrier? Remove it. */
6629 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6630 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6631 rtx label = NEXT_INSN (curr_pool->pool_insn);
6632
6633 if (jump && GET_CODE (jump) == JUMP_INSN
6634 && barrier && GET_CODE (barrier) == BARRIER
6635 && label && GET_CODE (label) == CODE_LABEL
6636 && GET_CODE (PATTERN (jump)) == SET
6637 && SET_DEST (PATTERN (jump)) == pc_rtx
6638 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6639 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6640 {
6641 remove_insn (jump);
6642 remove_insn (barrier);
6643 remove_insn (label);
6644 }
6645
6646 remove_insn (curr_pool->pool_insn);
6647 }
6648
6649 /* Remove all base register reload insns. */
6650
6651 for (insn = get_insns (); insn; )
6652 {
6653 rtx next_insn = NEXT_INSN (insn);
6654
6655 if (GET_CODE (insn) == INSN
6656 && GET_CODE (PATTERN (insn)) == SET
6657 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6658 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6659 remove_insn (insn);
6660
6661 insn = next_insn;
6662 }
6663
6664 /* Free pool list. */
6665
6666 while (pool_list)
6667 {
6668 struct constant_pool *next = pool_list->next;
6669 s390_free_pool (pool_list);
6670 pool_list = next;
6671 }
6672 }
6673
6674 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6675
6676 void
6677 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6678 {
6679 REAL_VALUE_TYPE r;
6680
6681 switch (GET_MODE_CLASS (mode))
6682 {
6683 case MODE_FLOAT:
6684 case MODE_DECIMAL_FLOAT:
6685 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6686
6687 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6688 assemble_real (r, mode, align);
6689 break;
6690
6691 case MODE_INT:
6692 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6693 mark_symbol_refs_as_used (exp);
6694 break;
6695
6696 default:
6697 gcc_unreachable ();
6698 }
6699 }
6700
6701
6702 /* Return an RTL expression representing the value of the return address
6703 for the frame COUNT steps up from the current frame. FRAME is the
6704 frame pointer of that frame. */
6705
6706 rtx
6707 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6708 {
6709 int offset;
6710 rtx addr;
6711
6712 /* Without backchain, we fail for all but the current frame. */
6713
6714 if (!TARGET_BACKCHAIN && count > 0)
6715 return NULL_RTX;
6716
6717 /* For the current frame, we need to make sure the initial
6718 value of RETURN_REGNUM is actually saved. */
6719
6720 if (count == 0)
6721 {
6722 /* On non-z architectures branch splitting could overwrite r14. */
6723 if (TARGET_CPU_ZARCH)
6724 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6725 else
6726 {
6727 cfun_frame_layout.save_return_addr_p = true;
6728 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6729 }
6730 }
6731
6732 if (TARGET_PACKED_STACK)
6733 offset = -2 * UNITS_PER_WORD;
6734 else
6735 offset = RETURN_REGNUM * UNITS_PER_WORD;
6736
6737 addr = plus_constant (frame, offset);
6738 addr = memory_address (Pmode, addr);
6739 return gen_rtx_MEM (Pmode, addr);
6740 }
6741
6742 /* Return an RTL expression representing the back chain stored in
6743 the current stack frame. */
6744
6745 rtx
6746 s390_back_chain_rtx (void)
6747 {
6748 rtx chain;
6749
6750 gcc_assert (TARGET_BACKCHAIN);
6751
6752 if (TARGET_PACKED_STACK)
6753 chain = plus_constant (stack_pointer_rtx,
6754 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6755 else
6756 chain = stack_pointer_rtx;
6757
6758 chain = gen_rtx_MEM (Pmode, chain);
6759 return chain;
6760 }
6761
6762 /* Find first call clobbered register unused in a function.
6763 This could be used as base register in a leaf function
6764 or for holding the return address before epilogue. */
6765
6766 static int
6767 find_unused_clobbered_reg (void)
6768 {
6769 int i;
6770 for (i = 0; i < 6; i++)
6771 if (!df_regs_ever_live_p (i))
6772 return i;
6773 return 0;
6774 }
6775
6776
6777 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6778 clobbered hard regs in SETREG. */
6779
6780 static void
6781 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6782 {
6783 int *regs_ever_clobbered = (int *)data;
6784 unsigned int i, regno;
6785 enum machine_mode mode = GET_MODE (setreg);
6786
6787 if (GET_CODE (setreg) == SUBREG)
6788 {
6789 rtx inner = SUBREG_REG (setreg);
6790 if (!GENERAL_REG_P (inner))
6791 return;
6792 regno = subreg_regno (setreg);
6793 }
6794 else if (GENERAL_REG_P (setreg))
6795 regno = REGNO (setreg);
6796 else
6797 return;
6798
6799 for (i = regno;
6800 i < regno + HARD_REGNO_NREGS (regno, mode);
6801 i++)
6802 regs_ever_clobbered[i] = 1;
6803 }
6804
6805 /* Walks through all basic blocks of the current function looking
6806 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6807 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6808 each of those regs. */
6809
6810 static void
6811 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6812 {
6813 basic_block cur_bb;
6814 rtx cur_insn;
6815 unsigned int i;
6816
6817 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6818
6819 /* For non-leaf functions we have to consider all call clobbered regs to be
6820 clobbered. */
6821 if (!current_function_is_leaf)
6822 {
6823 for (i = 0; i < 16; i++)
6824 regs_ever_clobbered[i] = call_really_used_regs[i];
6825 }
6826
6827 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6828 this work is done by liveness analysis (mark_regs_live_at_end).
6829 Special care is needed for functions containing landing pads. Landing pads
6830 may use the eh registers, but the code which sets these registers is not
6831 contained in that function. Hence s390_regs_ever_clobbered is not able to
6832 deal with this automatically. */
6833 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6834 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6835 if (crtl->calls_eh_return
6836 || (cfun->machine->has_landing_pad_p
6837 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6838 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6839
6840 /* For nonlocal gotos all call-saved registers have to be saved.
6841 This flag is also set for the unwinding code in libgcc.
6842 See expand_builtin_unwind_init. For regs_ever_live this is done by
6843 reload. */
6844 if (cfun->has_nonlocal_label)
6845 for (i = 0; i < 16; i++)
6846 if (!call_really_used_regs[i])
6847 regs_ever_clobbered[i] = 1;
6848
6849 FOR_EACH_BB (cur_bb)
6850 {
6851 FOR_BB_INSNS (cur_bb, cur_insn)
6852 {
6853 if (INSN_P (cur_insn))
6854 note_stores (PATTERN (cur_insn),
6855 s390_reg_clobbered_rtx,
6856 regs_ever_clobbered);
6857 }
6858 }
6859 }
6860
6861 /* Determine the frame area which actually has to be accessed
6862 in the function epilogue. The values are stored at the
6863 given pointers AREA_BOTTOM (address of the lowest used stack
6864 address) and AREA_TOP (address of the first item which does
6865 not belong to the stack frame). */
6866
6867 static void
6868 s390_frame_area (int *area_bottom, int *area_top)
6869 {
6870 int b, t;
6871 int i;
6872
6873 b = INT_MAX;
6874 t = INT_MIN;
6875
6876 if (cfun_frame_layout.first_restore_gpr != -1)
6877 {
6878 b = (cfun_frame_layout.gprs_offset
6879 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6880 t = b + (cfun_frame_layout.last_restore_gpr
6881 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6882 }
6883
6884 if (TARGET_64BIT && cfun_save_high_fprs_p)
6885 {
6886 b = MIN (b, cfun_frame_layout.f8_offset);
6887 t = MAX (t, (cfun_frame_layout.f8_offset
6888 + cfun_frame_layout.high_fprs * 8));
6889 }
6890
6891 if (!TARGET_64BIT)
6892 for (i = 2; i < 4; i++)
6893 if (cfun_fpr_bit_p (i))
6894 {
6895 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6896 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6897 }
6898
6899 *area_bottom = b;
6900 *area_top = t;
6901 }
6902
6903 /* Fill cfun->machine with info about register usage of current function.
6904 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6905
6906 static void
6907 s390_register_info (int clobbered_regs[])
6908 {
6909 int i, j;
6910
6911 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6912 cfun_frame_layout.fpr_bitmap = 0;
6913 cfun_frame_layout.high_fprs = 0;
6914 if (TARGET_64BIT)
6915 for (i = 24; i < 32; i++)
6916 if (df_regs_ever_live_p (i) && !global_regs[i])
6917 {
6918 cfun_set_fpr_bit (i - 16);
6919 cfun_frame_layout.high_fprs++;
6920 }
6921
6922 /* Find first and last gpr to be saved. We trust regs_ever_live
6923 data, except that we don't save and restore global registers.
6924
6925 Also, all registers with special meaning to the compiler need
6926 to be handled extra. */
6927
6928 s390_regs_ever_clobbered (clobbered_regs);
6929
6930 for (i = 0; i < 16; i++)
6931 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6932
6933 if (frame_pointer_needed)
6934 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6935
6936 if (flag_pic)
6937 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6938 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6939
6940 clobbered_regs[BASE_REGNUM]
6941 |= (cfun->machine->base_reg
6942 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6943
6944 clobbered_regs[RETURN_REGNUM]
6945 |= (!current_function_is_leaf
6946 || TARGET_TPF_PROFILING
6947 || cfun->machine->split_branches_pending_p
6948 || cfun_frame_layout.save_return_addr_p
6949 || crtl->calls_eh_return
6950 || cfun->stdarg);
6951
6952 clobbered_regs[STACK_POINTER_REGNUM]
6953 |= (!current_function_is_leaf
6954 || TARGET_TPF_PROFILING
6955 || cfun_save_high_fprs_p
6956 || get_frame_size () > 0
6957 || cfun->calls_alloca
6958 || cfun->stdarg);
6959
6960 for (i = 6; i < 16; i++)
6961 if (df_regs_ever_live_p (i) || clobbered_regs[i])
6962 break;
6963 for (j = 15; j > i; j--)
6964 if (df_regs_ever_live_p (j) || clobbered_regs[j])
6965 break;
6966
6967 if (i == 16)
6968 {
6969 /* Nothing to save/restore. */
6970 cfun_frame_layout.first_save_gpr_slot = -1;
6971 cfun_frame_layout.last_save_gpr_slot = -1;
6972 cfun_frame_layout.first_save_gpr = -1;
6973 cfun_frame_layout.first_restore_gpr = -1;
6974 cfun_frame_layout.last_save_gpr = -1;
6975 cfun_frame_layout.last_restore_gpr = -1;
6976 }
6977 else
6978 {
6979 /* Save slots for gprs from i to j. */
6980 cfun_frame_layout.first_save_gpr_slot = i;
6981 cfun_frame_layout.last_save_gpr_slot = j;
6982
6983 for (i = cfun_frame_layout.first_save_gpr_slot;
6984 i < cfun_frame_layout.last_save_gpr_slot + 1;
6985 i++)
6986 if (clobbered_regs[i])
6987 break;
6988
6989 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6990 if (clobbered_regs[j])
6991 break;
6992
6993 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6994 {
6995 /* Nothing to save/restore. */
6996 cfun_frame_layout.first_save_gpr = -1;
6997 cfun_frame_layout.first_restore_gpr = -1;
6998 cfun_frame_layout.last_save_gpr = -1;
6999 cfun_frame_layout.last_restore_gpr = -1;
7000 }
7001 else
7002 {
7003 /* Save / Restore from gpr i to j. */
7004 cfun_frame_layout.first_save_gpr = i;
7005 cfun_frame_layout.first_restore_gpr = i;
7006 cfun_frame_layout.last_save_gpr = j;
7007 cfun_frame_layout.last_restore_gpr = j;
7008 }
7009 }
7010
7011 if (cfun->stdarg)
7012 {
7013 /* Varargs functions need to save gprs 2 to 6. */
7014 if (cfun->va_list_gpr_size
7015 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7016 {
7017 int min_gpr = crtl->args.info.gprs;
7018 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7019 if (max_gpr > GP_ARG_NUM_REG)
7020 max_gpr = GP_ARG_NUM_REG;
7021
7022 if (cfun_frame_layout.first_save_gpr == -1
7023 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7024 {
7025 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7026 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7027 }
7028
7029 if (cfun_frame_layout.last_save_gpr == -1
7030 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7031 {
7032 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7033 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7034 }
7035 }
7036
7037 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7038 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7039 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7040 {
7041 int min_fpr = crtl->args.info.fprs;
7042 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7043 if (max_fpr > FP_ARG_NUM_REG)
7044 max_fpr = FP_ARG_NUM_REG;
7045
7046 /* ??? This is currently required to ensure proper location
7047 of the fpr save slots within the va_list save area. */
7048 if (TARGET_PACKED_STACK)
7049 min_fpr = 0;
7050
7051 for (i = min_fpr; i < max_fpr; i++)
7052 cfun_set_fpr_bit (i);
7053 }
7054 }
7055
7056 if (!TARGET_64BIT)
7057 for (i = 2; i < 4; i++)
7058 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7059 cfun_set_fpr_bit (i);
7060 }
7061
7062 /* Fill cfun->machine with info about frame of current function. */
7063
7064 static void
7065 s390_frame_info (void)
7066 {
7067 int i;
7068
7069 cfun_frame_layout.frame_size = get_frame_size ();
7070 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7071 fatal_error ("total size of local variables exceeds architecture limit");
7072
7073 if (!TARGET_PACKED_STACK)
7074 {
7075 cfun_frame_layout.backchain_offset = 0;
7076 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
7077 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7078 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7079 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7080 * UNITS_PER_WORD);
7081 }
7082 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7083 {
7084 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7085 - UNITS_PER_WORD);
7086 cfun_frame_layout.gprs_offset
7087 = (cfun_frame_layout.backchain_offset
7088 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7089 * UNITS_PER_WORD);
7090
7091 if (TARGET_64BIT)
7092 {
7093 cfun_frame_layout.f4_offset
7094 = (cfun_frame_layout.gprs_offset
7095 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7096
7097 cfun_frame_layout.f0_offset
7098 = (cfun_frame_layout.f4_offset
7099 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7100 }
7101 else
7102 {
7103 /* On 31 bit we have to care about alignment of the
7104 floating point regs to provide fastest access. */
7105 cfun_frame_layout.f0_offset
7106 = ((cfun_frame_layout.gprs_offset
7107 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7108 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7109
7110 cfun_frame_layout.f4_offset
7111 = (cfun_frame_layout.f0_offset
7112 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7113 }
7114 }
7115 else /* no backchain */
7116 {
7117 cfun_frame_layout.f4_offset
7118 = (STACK_POINTER_OFFSET
7119 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7120
7121 cfun_frame_layout.f0_offset
7122 = (cfun_frame_layout.f4_offset
7123 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7124
7125 cfun_frame_layout.gprs_offset
7126 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7127 }
7128
7129 if (current_function_is_leaf
7130 && !TARGET_TPF_PROFILING
7131 && cfun_frame_layout.frame_size == 0
7132 && !cfun_save_high_fprs_p
7133 && !cfun->calls_alloca
7134 && !cfun->stdarg)
7135 return;
7136
7137 if (!TARGET_PACKED_STACK)
7138 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7139 + crtl->outgoing_args_size
7140 + cfun_frame_layout.high_fprs * 8);
7141 else
7142 {
7143 if (TARGET_BACKCHAIN)
7144 cfun_frame_layout.frame_size += UNITS_PER_WORD;
7145
7146 /* No alignment trouble here because f8-f15 are only saved under
7147 64 bit. */
7148 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7149 cfun_frame_layout.f4_offset),
7150 cfun_frame_layout.gprs_offset)
7151 - cfun_frame_layout.high_fprs * 8);
7152
7153 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7154
7155 for (i = 0; i < 8; i++)
7156 if (cfun_fpr_bit_p (i))
7157 cfun_frame_layout.frame_size += 8;
7158
7159 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7160
7161 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7162 the frame size to sustain 8 byte alignment of stack frames. */
7163 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7164 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7165 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7166
7167 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7168 }
7169 }
7170
7171 /* Generate frame layout. Fills in register and frame data for the current
7172 function in cfun->machine. This routine can be called multiple times;
7173 it will re-do the complete frame layout every time. */
7174
7175 static void
7176 s390_init_frame_layout (void)
7177 {
7178 HOST_WIDE_INT frame_size;
7179 int base_used;
7180 int clobbered_regs[16];
7181
7182 /* On S/390 machines, we may need to perform branch splitting, which
7183 will require both base and return address register. We have no
7184 choice but to assume we're going to need them until right at the
7185 end of the machine dependent reorg phase. */
7186 if (!TARGET_CPU_ZARCH)
7187 cfun->machine->split_branches_pending_p = true;
7188
7189 do
7190 {
7191 frame_size = cfun_frame_layout.frame_size;
7192
7193 /* Try to predict whether we'll need the base register. */
7194 base_used = cfun->machine->split_branches_pending_p
7195 || crtl->uses_const_pool
7196 || (!DISP_IN_RANGE (frame_size)
7197 && !CONST_OK_FOR_K (frame_size));
7198
7199 /* Decide which register to use as literal pool base. In small
7200 leaf functions, try to use an unused call-clobbered register
7201 as base register to avoid save/restore overhead. */
7202 if (!base_used)
7203 cfun->machine->base_reg = NULL_RTX;
7204 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7205 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7206 else
7207 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7208
7209 s390_register_info (clobbered_regs);
7210 s390_frame_info ();
7211 }
7212 while (frame_size != cfun_frame_layout.frame_size);
7213 }
7214
7215 /* Update frame layout. Recompute actual register save data based on
7216 current info and update regs_ever_live for the special registers.
7217 May be called multiple times, but may never cause *more* registers
7218 to be saved than s390_init_frame_layout allocated room for. */
7219
7220 static void
7221 s390_update_frame_layout (void)
7222 {
7223 int clobbered_regs[16];
7224
7225 s390_register_info (clobbered_regs);
7226
7227 df_set_regs_ever_live (BASE_REGNUM,
7228 clobbered_regs[BASE_REGNUM] ? true : false);
7229 df_set_regs_ever_live (RETURN_REGNUM,
7230 clobbered_regs[RETURN_REGNUM] ? true : false);
7231 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7232 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7233
7234 if (cfun->machine->base_reg)
7235 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7236 }
7237
7238 /* Return true if it is legal to put a value with MODE into REGNO. */
7239
7240 bool
7241 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7242 {
7243 switch (REGNO_REG_CLASS (regno))
7244 {
7245 case FP_REGS:
7246 if (REGNO_PAIR_OK (regno, mode))
7247 {
7248 if (mode == SImode || mode == DImode)
7249 return true;
7250
7251 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7252 return true;
7253 }
7254 break;
7255 case ADDR_REGS:
7256 if (FRAME_REGNO_P (regno) && mode == Pmode)
7257 return true;
7258
7259 /* fallthrough */
7260 case GENERAL_REGS:
7261 if (REGNO_PAIR_OK (regno, mode))
7262 {
7263 if (TARGET_64BIT
7264 || (mode != TFmode && mode != TCmode && mode != TDmode))
7265 return true;
7266 }
7267 break;
7268 case CC_REGS:
7269 if (GET_MODE_CLASS (mode) == MODE_CC)
7270 return true;
7271 break;
7272 case ACCESS_REGS:
7273 if (REGNO_PAIR_OK (regno, mode))
7274 {
7275 if (mode == SImode || mode == Pmode)
7276 return true;
7277 }
7278 break;
7279 default:
7280 return false;
7281 }
7282
7283 return false;
7284 }
7285
7286 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7287
7288 bool
7289 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7290 {
7291 /* Once we've decided upon a register to use as base register, it must
7292 no longer be used for any other purpose. */
7293 if (cfun->machine->base_reg)
7294 if (REGNO (cfun->machine->base_reg) == old_reg
7295 || REGNO (cfun->machine->base_reg) == new_reg)
7296 return false;
7297
7298 return true;
7299 }
7300
7301 /* Maximum number of registers to represent a value of mode MODE
7302 in a register of class RCLASS. */
7303
7304 bool
7305 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7306 {
7307 switch (rclass)
7308 {
7309 case FP_REGS:
7310 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7311 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7312 else
7313 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7314 case ACCESS_REGS:
7315 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7316 default:
7317 break;
7318 }
7319 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7320 }
7321
7322 /* Return true if register FROM can be eliminated via register TO. */
7323
7324 bool
7325 s390_can_eliminate (int from, int to)
7326 {
7327 /* On zSeries machines, we have not marked the base register as fixed.
7328 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7329 If a function requires the base register, we say here that this
7330 elimination cannot be performed. This will cause reload to free
7331 up the base register (as if it were fixed). On the other hand,
7332 if the current function does *not* require the base register, we
7333 say here the elimination succeeds, which in turn allows reload
7334 to allocate the base register for any other purpose. */
7335 if (from == BASE_REGNUM && to == BASE_REGNUM)
7336 {
7337 if (TARGET_CPU_ZARCH)
7338 {
7339 s390_init_frame_layout ();
7340 return cfun->machine->base_reg == NULL_RTX;
7341 }
7342
7343 return false;
7344 }
7345
7346 /* Everything else must point into the stack frame. */
7347 gcc_assert (to == STACK_POINTER_REGNUM
7348 || to == HARD_FRAME_POINTER_REGNUM);
7349
7350 gcc_assert (from == FRAME_POINTER_REGNUM
7351 || from == ARG_POINTER_REGNUM
7352 || from == RETURN_ADDRESS_POINTER_REGNUM);
7353
7354 /* Make sure we actually saved the return address. */
7355 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7356 if (!crtl->calls_eh_return
7357 && !cfun->stdarg
7358 && !cfun_frame_layout.save_return_addr_p)
7359 return false;
7360
7361 return true;
7362 }
7363
7364 /* Return offset between register FROM and TO initially after prolog. */
7365
7366 HOST_WIDE_INT
7367 s390_initial_elimination_offset (int from, int to)
7368 {
7369 HOST_WIDE_INT offset;
7370 int index;
7371
7372 /* ??? Why are we called for non-eliminable pairs? */
7373 if (!s390_can_eliminate (from, to))
7374 return 0;
7375
7376 switch (from)
7377 {
7378 case FRAME_POINTER_REGNUM:
7379 offset = (get_frame_size()
7380 + STACK_POINTER_OFFSET
7381 + crtl->outgoing_args_size);
7382 break;
7383
7384 case ARG_POINTER_REGNUM:
7385 s390_init_frame_layout ();
7386 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7387 break;
7388
7389 case RETURN_ADDRESS_POINTER_REGNUM:
7390 s390_init_frame_layout ();
7391 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7392 gcc_assert (index >= 0);
7393 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7394 offset += index * UNITS_PER_WORD;
7395 break;
7396
7397 case BASE_REGNUM:
7398 offset = 0;
7399 break;
7400
7401 default:
7402 gcc_unreachable ();
7403 }
7404
7405 return offset;
7406 }
7407
7408 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7409 to register BASE. Return generated insn. */
7410
7411 static rtx
7412 save_fpr (rtx base, int offset, int regnum)
7413 {
7414 rtx addr;
7415 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7416
7417 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7418 set_mem_alias_set (addr, get_varargs_alias_set ());
7419 else
7420 set_mem_alias_set (addr, get_frame_alias_set ());
7421
7422 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7423 }
7424
7425 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7426 to register BASE. Return generated insn. */
7427
7428 static rtx
7429 restore_fpr (rtx base, int offset, int regnum)
7430 {
7431 rtx addr;
7432 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7433 set_mem_alias_set (addr, get_frame_alias_set ());
7434
7435 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7436 }
7437
7438 /* Return true if REGNO is a global register, but not one
7439 of the special ones that need to be saved/restored in anyway. */
7440
7441 static inline bool
7442 global_not_special_regno_p (int regno)
7443 {
7444 return (global_regs[regno]
7445 /* These registers are special and need to be
7446 restored in any case. */
7447 && !(regno == STACK_POINTER_REGNUM
7448 || regno == RETURN_REGNUM
7449 || regno == BASE_REGNUM
7450 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7451 }
7452
7453 /* Generate insn to save registers FIRST to LAST into
7454 the register save area located at offset OFFSET
7455 relative to register BASE. */
7456
7457 static rtx
7458 save_gprs (rtx base, int offset, int first, int last)
7459 {
7460 rtx addr, insn, note;
7461 int i;
7462
7463 addr = plus_constant (base, offset);
7464 addr = gen_rtx_MEM (Pmode, addr);
7465
7466 set_mem_alias_set (addr, get_frame_alias_set ());
7467
7468 /* Special-case single register. */
7469 if (first == last)
7470 {
7471 if (TARGET_64BIT)
7472 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7473 else
7474 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7475
7476 if (!global_not_special_regno_p (first))
7477 RTX_FRAME_RELATED_P (insn) = 1;
7478 return insn;
7479 }
7480
7481
7482 insn = gen_store_multiple (addr,
7483 gen_rtx_REG (Pmode, first),
7484 GEN_INT (last - first + 1));
7485
7486 if (first <= 6 && cfun->stdarg)
7487 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7488 {
7489 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7490
7491 if (first + i <= 6)
7492 set_mem_alias_set (mem, get_varargs_alias_set ());
7493 }
7494
7495 /* We need to set the FRAME_RELATED flag on all SETs
7496 inside the store-multiple pattern.
7497
7498 However, we must not emit DWARF records for registers 2..5
7499 if they are stored for use by variable arguments ...
7500
7501 ??? Unfortunately, it is not enough to simply not the
7502 FRAME_RELATED flags for those SETs, because the first SET
7503 of the PARALLEL is always treated as if it had the flag
7504 set, even if it does not. Therefore we emit a new pattern
7505 without those registers as REG_FRAME_RELATED_EXPR note. */
7506
7507 if (first >= 6 && !global_not_special_regno_p (first))
7508 {
7509 rtx pat = PATTERN (insn);
7510
7511 for (i = 0; i < XVECLEN (pat, 0); i++)
7512 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7513 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7514 0, i)))))
7515 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7516
7517 RTX_FRAME_RELATED_P (insn) = 1;
7518 }
7519 else if (last >= 6)
7520 {
7521 int start;
7522
7523 for (start = first >= 6 ? first : 6; start <= last; start++)
7524 if (!global_not_special_regno_p (start))
7525 break;
7526
7527 if (start > last)
7528 return insn;
7529
7530 addr = plus_constant (base, offset + (start - first) * UNITS_PER_WORD);
7531 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7532 gen_rtx_REG (Pmode, start),
7533 GEN_INT (last - start + 1));
7534 note = PATTERN (note);
7535
7536 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7537
7538 for (i = 0; i < XVECLEN (note, 0); i++)
7539 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7540 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7541 0, i)))))
7542 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7543
7544 RTX_FRAME_RELATED_P (insn) = 1;
7545 }
7546
7547 return insn;
7548 }
7549
7550 /* Generate insn to restore registers FIRST to LAST from
7551 the register save area located at offset OFFSET
7552 relative to register BASE. */
7553
7554 static rtx
7555 restore_gprs (rtx base, int offset, int first, int last)
7556 {
7557 rtx addr, insn;
7558
7559 addr = plus_constant (base, offset);
7560 addr = gen_rtx_MEM (Pmode, addr);
7561 set_mem_alias_set (addr, get_frame_alias_set ());
7562
7563 /* Special-case single register. */
7564 if (first == last)
7565 {
7566 if (TARGET_64BIT)
7567 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7568 else
7569 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7570
7571 return insn;
7572 }
7573
7574 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7575 addr,
7576 GEN_INT (last - first + 1));
7577 return insn;
7578 }
7579
7580 /* Return insn sequence to load the GOT register. */
7581
7582 static GTY(()) rtx got_symbol;
7583 rtx
7584 s390_load_got (void)
7585 {
7586 rtx insns;
7587
7588 if (!got_symbol)
7589 {
7590 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7591 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7592 }
7593
7594 start_sequence ();
7595
7596 if (TARGET_CPU_ZARCH)
7597 {
7598 emit_move_insn (pic_offset_table_rtx, got_symbol);
7599 }
7600 else
7601 {
7602 rtx offset;
7603
7604 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7605 UNSPEC_LTREL_OFFSET);
7606 offset = gen_rtx_CONST (Pmode, offset);
7607 offset = force_const_mem (Pmode, offset);
7608
7609 emit_move_insn (pic_offset_table_rtx, offset);
7610
7611 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7612 UNSPEC_LTREL_BASE);
7613 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7614
7615 emit_move_insn (pic_offset_table_rtx, offset);
7616 }
7617
7618 insns = get_insns ();
7619 end_sequence ();
7620 return insns;
7621 }
7622
7623 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7624 and the change to the stack pointer. */
7625
7626 static void
7627 s390_emit_stack_tie (void)
7628 {
7629 rtx mem = gen_frame_mem (BLKmode,
7630 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7631
7632 emit_insn (gen_stack_tie (mem));
7633 }
7634
7635 /* Expand the prologue into a bunch of separate insns. */
7636
7637 void
7638 s390_emit_prologue (void)
7639 {
7640 rtx insn, addr;
7641 rtx temp_reg;
7642 int i;
7643 int offset;
7644 int next_fpr = 0;
7645
7646 /* Complete frame layout. */
7647
7648 s390_update_frame_layout ();
7649
7650 /* Annotate all constant pool references to let the scheduler know
7651 they implicitly use the base register. */
7652
7653 push_topmost_sequence ();
7654
7655 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7656 if (INSN_P (insn))
7657 {
7658 annotate_constant_pool_refs (&PATTERN (insn));
7659 df_insn_rescan (insn);
7660 }
7661
7662 pop_topmost_sequence ();
7663
7664 /* Choose best register to use for temp use within prologue.
7665 See below for why TPF must use the register 1. */
7666
7667 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7668 && !current_function_is_leaf
7669 && !TARGET_TPF_PROFILING)
7670 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7671 else
7672 temp_reg = gen_rtx_REG (Pmode, 1);
7673
7674 /* Save call saved gprs. */
7675 if (cfun_frame_layout.first_save_gpr != -1)
7676 {
7677 insn = save_gprs (stack_pointer_rtx,
7678 cfun_frame_layout.gprs_offset +
7679 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7680 - cfun_frame_layout.first_save_gpr_slot),
7681 cfun_frame_layout.first_save_gpr,
7682 cfun_frame_layout.last_save_gpr);
7683 emit_insn (insn);
7684 }
7685
7686 /* Dummy insn to mark literal pool slot. */
7687
7688 if (cfun->machine->base_reg)
7689 emit_insn (gen_main_pool (cfun->machine->base_reg));
7690
7691 offset = cfun_frame_layout.f0_offset;
7692
7693 /* Save f0 and f2. */
7694 for (i = 0; i < 2; i++)
7695 {
7696 if (cfun_fpr_bit_p (i))
7697 {
7698 save_fpr (stack_pointer_rtx, offset, i + 16);
7699 offset += 8;
7700 }
7701 else if (!TARGET_PACKED_STACK)
7702 offset += 8;
7703 }
7704
7705 /* Save f4 and f6. */
7706 offset = cfun_frame_layout.f4_offset;
7707 for (i = 2; i < 4; i++)
7708 {
7709 if (cfun_fpr_bit_p (i))
7710 {
7711 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7712 offset += 8;
7713
7714 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7715 therefore are not frame related. */
7716 if (!call_really_used_regs[i + 16])
7717 RTX_FRAME_RELATED_P (insn) = 1;
7718 }
7719 else if (!TARGET_PACKED_STACK)
7720 offset += 8;
7721 }
7722
7723 if (TARGET_PACKED_STACK
7724 && cfun_save_high_fprs_p
7725 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7726 {
7727 offset = (cfun_frame_layout.f8_offset
7728 + (cfun_frame_layout.high_fprs - 1) * 8);
7729
7730 for (i = 15; i > 7 && offset >= 0; i--)
7731 if (cfun_fpr_bit_p (i))
7732 {
7733 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7734
7735 RTX_FRAME_RELATED_P (insn) = 1;
7736 offset -= 8;
7737 }
7738 if (offset >= cfun_frame_layout.f8_offset)
7739 next_fpr = i + 16;
7740 }
7741
7742 if (!TARGET_PACKED_STACK)
7743 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7744
7745 /* Decrement stack pointer. */
7746
7747 if (cfun_frame_layout.frame_size > 0)
7748 {
7749 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7750 rtx real_frame_off;
7751
7752 if (s390_stack_size)
7753 {
7754 HOST_WIDE_INT stack_guard;
7755
7756 if (s390_stack_guard)
7757 stack_guard = s390_stack_guard;
7758 else
7759 {
7760 /* If no value for stack guard is provided the smallest power of 2
7761 larger than the current frame size is chosen. */
7762 stack_guard = 1;
7763 while (stack_guard < cfun_frame_layout.frame_size)
7764 stack_guard <<= 1;
7765 }
7766
7767 if (cfun_frame_layout.frame_size >= s390_stack_size)
7768 {
7769 warning (0, "frame size of function %qs is "
7770 HOST_WIDE_INT_PRINT_DEC
7771 " bytes exceeding user provided stack limit of "
7772 HOST_WIDE_INT_PRINT_DEC " bytes. "
7773 "An unconditional trap is added.",
7774 current_function_name(), cfun_frame_layout.frame_size,
7775 s390_stack_size);
7776 emit_insn (gen_trap ());
7777 }
7778 else
7779 {
7780 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7781 & ~(stack_guard - 1));
7782 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7783 GEN_INT (stack_check_mask));
7784 if (TARGET_64BIT)
7785 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7786 t, const0_rtx, const0_rtx));
7787 else
7788 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7789 t, const0_rtx, const0_rtx));
7790 }
7791 }
7792
7793 if (s390_warn_framesize > 0
7794 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7795 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7796 current_function_name (), cfun_frame_layout.frame_size);
7797
7798 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7799 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7800
7801 /* Save incoming stack pointer into temp reg. */
7802 if (TARGET_BACKCHAIN || next_fpr)
7803 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7804
7805 /* Subtract frame size from stack pointer. */
7806
7807 if (DISP_IN_RANGE (INTVAL (frame_off)))
7808 {
7809 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7810 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7811 frame_off));
7812 insn = emit_insn (insn);
7813 }
7814 else
7815 {
7816 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7817 frame_off = force_const_mem (Pmode, frame_off);
7818
7819 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7820 annotate_constant_pool_refs (&PATTERN (insn));
7821 }
7822
7823 RTX_FRAME_RELATED_P (insn) = 1;
7824 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7825 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7826 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7827 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7828 real_frame_off)));
7829
7830 /* Set backchain. */
7831
7832 if (TARGET_BACKCHAIN)
7833 {
7834 if (cfun_frame_layout.backchain_offset)
7835 addr = gen_rtx_MEM (Pmode,
7836 plus_constant (stack_pointer_rtx,
7837 cfun_frame_layout.backchain_offset));
7838 else
7839 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7840 set_mem_alias_set (addr, get_frame_alias_set ());
7841 insn = emit_insn (gen_move_insn (addr, temp_reg));
7842 }
7843
7844 /* If we support asynchronous exceptions (e.g. for Java),
7845 we need to make sure the backchain pointer is set up
7846 before any possibly trapping memory access. */
7847
7848 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7849 {
7850 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7851 emit_clobber (addr);
7852 }
7853 }
7854
7855 /* Save fprs 8 - 15 (64 bit ABI). */
7856
7857 if (cfun_save_high_fprs_p && next_fpr)
7858 {
7859 /* If the stack might be accessed through a different register
7860 we have to make sure that the stack pointer decrement is not
7861 moved below the use of the stack slots. */
7862 s390_emit_stack_tie ();
7863
7864 insn = emit_insn (gen_add2_insn (temp_reg,
7865 GEN_INT (cfun_frame_layout.f8_offset)));
7866
7867 offset = 0;
7868
7869 for (i = 24; i <= next_fpr; i++)
7870 if (cfun_fpr_bit_p (i - 16))
7871 {
7872 rtx addr = plus_constant (stack_pointer_rtx,
7873 cfun_frame_layout.frame_size
7874 + cfun_frame_layout.f8_offset
7875 + offset);
7876
7877 insn = save_fpr (temp_reg, offset, i);
7878 offset += 8;
7879 RTX_FRAME_RELATED_P (insn) = 1;
7880 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7881 gen_rtx_SET (VOIDmode,
7882 gen_rtx_MEM (DFmode, addr),
7883 gen_rtx_REG (DFmode, i)));
7884 }
7885 }
7886
7887 /* Set frame pointer, if needed. */
7888
7889 if (frame_pointer_needed)
7890 {
7891 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7892 RTX_FRAME_RELATED_P (insn) = 1;
7893 }
7894
7895 /* Set up got pointer, if needed. */
7896
7897 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7898 {
7899 rtx insns = s390_load_got ();
7900
7901 for (insn = insns; insn; insn = NEXT_INSN (insn))
7902 annotate_constant_pool_refs (&PATTERN (insn));
7903
7904 emit_insn (insns);
7905 }
7906
7907 if (TARGET_TPF_PROFILING)
7908 {
7909 /* Generate a BAS instruction to serve as a function
7910 entry intercept to facilitate the use of tracing
7911 algorithms located at the branch target. */
7912 emit_insn (gen_prologue_tpf ());
7913
7914 /* Emit a blockage here so that all code
7915 lies between the profiling mechanisms. */
7916 emit_insn (gen_blockage ());
7917 }
7918 }
7919
7920 /* Expand the epilogue into a bunch of separate insns. */
7921
7922 void
7923 s390_emit_epilogue (bool sibcall)
7924 {
7925 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
7926 int area_bottom, area_top, offset = 0;
7927 int next_offset;
7928 rtvec p;
7929 int i;
7930
7931 if (TARGET_TPF_PROFILING)
7932 {
7933
7934 /* Generate a BAS instruction to serve as a function
7935 entry intercept to facilitate the use of tracing
7936 algorithms located at the branch target. */
7937
7938 /* Emit a blockage here so that all code
7939 lies between the profiling mechanisms. */
7940 emit_insn (gen_blockage ());
7941
7942 emit_insn (gen_epilogue_tpf ());
7943 }
7944
7945 /* Check whether to use frame or stack pointer for restore. */
7946
7947 frame_pointer = (frame_pointer_needed
7948 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7949
7950 s390_frame_area (&area_bottom, &area_top);
7951
7952 /* Check whether we can access the register save area.
7953 If not, increment the frame pointer as required. */
7954
7955 if (area_top <= area_bottom)
7956 {
7957 /* Nothing to restore. */
7958 }
7959 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7960 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7961 {
7962 /* Area is in range. */
7963 offset = cfun_frame_layout.frame_size;
7964 }
7965 else
7966 {
7967 rtx insn, frame_off, cfa;
7968
7969 offset = area_bottom < 0 ? -area_bottom : 0;
7970 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7971
7972 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
7973 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7974 if (DISP_IN_RANGE (INTVAL (frame_off)))
7975 {
7976 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7977 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7978 insn = emit_insn (insn);
7979 }
7980 else
7981 {
7982 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7983 frame_off = force_const_mem (Pmode, frame_off);
7984
7985 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7986 annotate_constant_pool_refs (&PATTERN (insn));
7987 }
7988 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
7989 RTX_FRAME_RELATED_P (insn) = 1;
7990 }
7991
7992 /* Restore call saved fprs. */
7993
7994 if (TARGET_64BIT)
7995 {
7996 if (cfun_save_high_fprs_p)
7997 {
7998 next_offset = cfun_frame_layout.f8_offset;
7999 for (i = 24; i < 32; i++)
8000 {
8001 if (cfun_fpr_bit_p (i - 16))
8002 {
8003 restore_fpr (frame_pointer,
8004 offset + next_offset, i);
8005 cfa_restores
8006 = alloc_reg_note (REG_CFA_RESTORE,
8007 gen_rtx_REG (DFmode, i), cfa_restores);
8008 next_offset += 8;
8009 }
8010 }
8011 }
8012
8013 }
8014 else
8015 {
8016 next_offset = cfun_frame_layout.f4_offset;
8017 for (i = 18; i < 20; i++)
8018 {
8019 if (cfun_fpr_bit_p (i - 16))
8020 {
8021 restore_fpr (frame_pointer,
8022 offset + next_offset, i);
8023 cfa_restores
8024 = alloc_reg_note (REG_CFA_RESTORE,
8025 gen_rtx_REG (DFmode, i), cfa_restores);
8026 next_offset += 8;
8027 }
8028 else if (!TARGET_PACKED_STACK)
8029 next_offset += 8;
8030 }
8031
8032 }
8033
8034 /* Return register. */
8035
8036 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8037
8038 /* Restore call saved gprs. */
8039
8040 if (cfun_frame_layout.first_restore_gpr != -1)
8041 {
8042 rtx insn, addr;
8043 int i;
8044
8045 /* Check for global register and save them
8046 to stack location from where they get restored. */
8047
8048 for (i = cfun_frame_layout.first_restore_gpr;
8049 i <= cfun_frame_layout.last_restore_gpr;
8050 i++)
8051 {
8052 if (global_not_special_regno_p (i))
8053 {
8054 addr = plus_constant (frame_pointer,
8055 offset + cfun_frame_layout.gprs_offset
8056 + (i - cfun_frame_layout.first_save_gpr_slot)
8057 * UNITS_PER_WORD);
8058 addr = gen_rtx_MEM (Pmode, addr);
8059 set_mem_alias_set (addr, get_frame_alias_set ());
8060 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8061 }
8062 else
8063 cfa_restores
8064 = alloc_reg_note (REG_CFA_RESTORE,
8065 gen_rtx_REG (Pmode, i), cfa_restores);
8066 }
8067
8068 if (! sibcall)
8069 {
8070 /* Fetch return address from stack before load multiple,
8071 this will do good for scheduling. */
8072
8073 if (cfun_frame_layout.save_return_addr_p
8074 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8075 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8076 {
8077 int return_regnum = find_unused_clobbered_reg();
8078 if (!return_regnum)
8079 return_regnum = 4;
8080 return_reg = gen_rtx_REG (Pmode, return_regnum);
8081
8082 addr = plus_constant (frame_pointer,
8083 offset + cfun_frame_layout.gprs_offset
8084 + (RETURN_REGNUM
8085 - cfun_frame_layout.first_save_gpr_slot)
8086 * UNITS_PER_WORD);
8087 addr = gen_rtx_MEM (Pmode, addr);
8088 set_mem_alias_set (addr, get_frame_alias_set ());
8089 emit_move_insn (return_reg, addr);
8090 }
8091 }
8092
8093 insn = restore_gprs (frame_pointer,
8094 offset + cfun_frame_layout.gprs_offset
8095 + (cfun_frame_layout.first_restore_gpr
8096 - cfun_frame_layout.first_save_gpr_slot)
8097 * UNITS_PER_WORD,
8098 cfun_frame_layout.first_restore_gpr,
8099 cfun_frame_layout.last_restore_gpr);
8100 insn = emit_insn (insn);
8101 REG_NOTES (insn) = cfa_restores;
8102 add_reg_note (insn, REG_CFA_DEF_CFA,
8103 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8104 RTX_FRAME_RELATED_P (insn) = 1;
8105 }
8106
8107 if (! sibcall)
8108 {
8109
8110 /* Return to caller. */
8111
8112 p = rtvec_alloc (2);
8113
8114 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8115 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8116 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8117 }
8118 }
8119
8120
8121 /* Return the size in bytes of a function argument of
8122 type TYPE and/or mode MODE. At least one of TYPE or
8123 MODE must be specified. */
8124
8125 static int
8126 s390_function_arg_size (enum machine_mode mode, const_tree type)
8127 {
8128 if (type)
8129 return int_size_in_bytes (type);
8130
8131 /* No type info available for some library calls ... */
8132 if (mode != BLKmode)
8133 return GET_MODE_SIZE (mode);
8134
8135 /* If we have neither type nor mode, abort */
8136 gcc_unreachable ();
8137 }
8138
8139 /* Return true if a function argument of type TYPE and mode MODE
8140 is to be passed in a floating-point register, if available. */
8141
8142 static bool
8143 s390_function_arg_float (enum machine_mode mode, tree type)
8144 {
8145 int size = s390_function_arg_size (mode, type);
8146 if (size > 8)
8147 return false;
8148
8149 /* Soft-float changes the ABI: no floating-point registers are used. */
8150 if (TARGET_SOFT_FLOAT)
8151 return false;
8152
8153 /* No type info available for some library calls ... */
8154 if (!type)
8155 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8156
8157 /* The ABI says that record types with a single member are treated
8158 just like that member would be. */
8159 while (TREE_CODE (type) == RECORD_TYPE)
8160 {
8161 tree field, single = NULL_TREE;
8162
8163 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8164 {
8165 if (TREE_CODE (field) != FIELD_DECL)
8166 continue;
8167
8168 if (single == NULL_TREE)
8169 single = TREE_TYPE (field);
8170 else
8171 return false;
8172 }
8173
8174 if (single == NULL_TREE)
8175 return false;
8176 else
8177 type = single;
8178 }
8179
8180 return TREE_CODE (type) == REAL_TYPE;
8181 }
8182
8183 /* Return true if a function argument of type TYPE and mode MODE
8184 is to be passed in an integer register, or a pair of integer
8185 registers, if available. */
8186
8187 static bool
8188 s390_function_arg_integer (enum machine_mode mode, tree type)
8189 {
8190 int size = s390_function_arg_size (mode, type);
8191 if (size > 8)
8192 return false;
8193
8194 /* No type info available for some library calls ... */
8195 if (!type)
8196 return GET_MODE_CLASS (mode) == MODE_INT
8197 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8198
8199 /* We accept small integral (and similar) types. */
8200 if (INTEGRAL_TYPE_P (type)
8201 || POINTER_TYPE_P (type)
8202 || TREE_CODE (type) == OFFSET_TYPE
8203 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8204 return true;
8205
8206 /* We also accept structs of size 1, 2, 4, 8 that are not
8207 passed in floating-point registers. */
8208 if (AGGREGATE_TYPE_P (type)
8209 && exact_log2 (size) >= 0
8210 && !s390_function_arg_float (mode, type))
8211 return true;
8212
8213 return false;
8214 }
8215
8216 /* Return 1 if a function argument of type TYPE and mode MODE
8217 is to be passed by reference. The ABI specifies that only
8218 structures of size 1, 2, 4, or 8 bytes are passed by value,
8219 all other structures (and complex numbers) are passed by
8220 reference. */
8221
8222 static bool
8223 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8224 enum machine_mode mode, const_tree type,
8225 bool named ATTRIBUTE_UNUSED)
8226 {
8227 int size = s390_function_arg_size (mode, type);
8228 if (size > 8)
8229 return true;
8230
8231 if (type)
8232 {
8233 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8234 return 1;
8235
8236 if (TREE_CODE (type) == COMPLEX_TYPE
8237 || TREE_CODE (type) == VECTOR_TYPE)
8238 return 1;
8239 }
8240
8241 return 0;
8242 }
8243
8244 /* Update the data in CUM to advance over an argument of mode MODE and
8245 data type TYPE. (TYPE is null for libcalls where that information
8246 may not be available.). The boolean NAMED specifies whether the
8247 argument is a named argument (as opposed to an unnamed argument
8248 matching an ellipsis). */
8249
8250 void
8251 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8252 tree type, int named ATTRIBUTE_UNUSED)
8253 {
8254 if (s390_function_arg_float (mode, type))
8255 {
8256 cum->fprs += 1;
8257 }
8258 else if (s390_function_arg_integer (mode, type))
8259 {
8260 int size = s390_function_arg_size (mode, type);
8261 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
8262 }
8263 else
8264 gcc_unreachable ();
8265 }
8266
8267 /* Define where to put the arguments to a function.
8268 Value is zero to push the argument on the stack,
8269 or a hard register in which to store the argument.
8270
8271 MODE is the argument's machine mode.
8272 TYPE is the data type of the argument (as a tree).
8273 This is null for libcalls where that information may
8274 not be available.
8275 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8276 the preceding args and about the function being called.
8277 NAMED is nonzero if this argument is a named parameter
8278 (otherwise it is an extra parameter matching an ellipsis).
8279
8280 On S/390, we use general purpose registers 2 through 6 to
8281 pass integer, pointer, and certain structure arguments, and
8282 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8283 to pass floating point arguments. All remaining arguments
8284 are pushed to the stack. */
8285
8286 rtx
8287 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8288 int named ATTRIBUTE_UNUSED)
8289 {
8290 if (s390_function_arg_float (mode, type))
8291 {
8292 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8293 return 0;
8294 else
8295 return gen_rtx_REG (mode, cum->fprs + 16);
8296 }
8297 else if (s390_function_arg_integer (mode, type))
8298 {
8299 int size = s390_function_arg_size (mode, type);
8300 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
8301
8302 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8303 return 0;
8304 else
8305 return gen_rtx_REG (mode, cum->gprs + 2);
8306 }
8307
8308 /* After the real arguments, expand_call calls us once again
8309 with a void_type_node type. Whatever we return here is
8310 passed as operand 2 to the call expanders.
8311
8312 We don't need this feature ... */
8313 else if (type == void_type_node)
8314 return const0_rtx;
8315
8316 gcc_unreachable ();
8317 }
8318
8319 /* Return true if return values of type TYPE should be returned
8320 in a memory buffer whose address is passed by the caller as
8321 hidden first argument. */
8322
8323 static bool
8324 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8325 {
8326 /* We accept small integral (and similar) types. */
8327 if (INTEGRAL_TYPE_P (type)
8328 || POINTER_TYPE_P (type)
8329 || TREE_CODE (type) == OFFSET_TYPE
8330 || TREE_CODE (type) == REAL_TYPE)
8331 return int_size_in_bytes (type) > 8;
8332
8333 /* Aggregates and similar constructs are always returned
8334 in memory. */
8335 if (AGGREGATE_TYPE_P (type)
8336 || TREE_CODE (type) == COMPLEX_TYPE
8337 || TREE_CODE (type) == VECTOR_TYPE)
8338 return true;
8339
8340 /* ??? We get called on all sorts of random stuff from
8341 aggregate_value_p. We can't abort, but it's not clear
8342 what's safe to return. Pretend it's a struct I guess. */
8343 return true;
8344 }
8345
8346 /* Define where to return a (scalar) value of type TYPE.
8347 If TYPE is null, define where to return a (scalar)
8348 value of mode MODE from a libcall. */
8349
8350 rtx
8351 s390_function_value (const_tree type, enum machine_mode mode)
8352 {
8353 if (type)
8354 {
8355 int unsignedp = TYPE_UNSIGNED (type);
8356 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
8357 }
8358
8359 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8360 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8361
8362 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8363 return gen_rtx_REG (mode, 16);
8364 else
8365 return gen_rtx_REG (mode, 2);
8366 }
8367
8368
8369 /* Create and return the va_list datatype.
8370
8371 On S/390, va_list is an array type equivalent to
8372
8373 typedef struct __va_list_tag
8374 {
8375 long __gpr;
8376 long __fpr;
8377 void *__overflow_arg_area;
8378 void *__reg_save_area;
8379 } va_list[1];
8380
8381 where __gpr and __fpr hold the number of general purpose
8382 or floating point arguments used up to now, respectively,
8383 __overflow_arg_area points to the stack location of the
8384 next argument passed on the stack, and __reg_save_area
8385 always points to the start of the register area in the
8386 call frame of the current function. The function prologue
8387 saves all registers used for argument passing into this
8388 area if the function uses variable arguments. */
8389
8390 static tree
8391 s390_build_builtin_va_list (void)
8392 {
8393 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8394
8395 record = lang_hooks.types.make_type (RECORD_TYPE);
8396
8397 type_decl =
8398 build_decl (BUILTINS_LOCATION,
8399 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8400
8401 f_gpr = build_decl (BUILTINS_LOCATION,
8402 FIELD_DECL, get_identifier ("__gpr"),
8403 long_integer_type_node);
8404 f_fpr = build_decl (BUILTINS_LOCATION,
8405 FIELD_DECL, get_identifier ("__fpr"),
8406 long_integer_type_node);
8407 f_ovf = build_decl (BUILTINS_LOCATION,
8408 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8409 ptr_type_node);
8410 f_sav = build_decl (BUILTINS_LOCATION,
8411 FIELD_DECL, get_identifier ("__reg_save_area"),
8412 ptr_type_node);
8413
8414 va_list_gpr_counter_field = f_gpr;
8415 va_list_fpr_counter_field = f_fpr;
8416
8417 DECL_FIELD_CONTEXT (f_gpr) = record;
8418 DECL_FIELD_CONTEXT (f_fpr) = record;
8419 DECL_FIELD_CONTEXT (f_ovf) = record;
8420 DECL_FIELD_CONTEXT (f_sav) = record;
8421
8422 TREE_CHAIN (record) = type_decl;
8423 TYPE_NAME (record) = type_decl;
8424 TYPE_FIELDS (record) = f_gpr;
8425 TREE_CHAIN (f_gpr) = f_fpr;
8426 TREE_CHAIN (f_fpr) = f_ovf;
8427 TREE_CHAIN (f_ovf) = f_sav;
8428
8429 layout_type (record);
8430
8431 /* The correct type is an array type of one element. */
8432 return build_array_type (record, build_index_type (size_zero_node));
8433 }
8434
8435 /* Implement va_start by filling the va_list structure VALIST.
8436 STDARG_P is always true, and ignored.
8437 NEXTARG points to the first anonymous stack argument.
8438
8439 The following global variables are used to initialize
8440 the va_list structure:
8441
8442 crtl->args.info:
8443 holds number of gprs and fprs used for named arguments.
8444 crtl->args.arg_offset_rtx:
8445 holds the offset of the first anonymous stack argument
8446 (relative to the virtual arg pointer). */
8447
8448 static void
8449 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8450 {
8451 HOST_WIDE_INT n_gpr, n_fpr;
8452 int off;
8453 tree f_gpr, f_fpr, f_ovf, f_sav;
8454 tree gpr, fpr, ovf, sav, t;
8455
8456 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8457 f_fpr = TREE_CHAIN (f_gpr);
8458 f_ovf = TREE_CHAIN (f_fpr);
8459 f_sav = TREE_CHAIN (f_ovf);
8460
8461 valist = build_va_arg_indirect_ref (valist);
8462 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8463 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8464 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8465 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8466
8467 /* Count number of gp and fp argument registers used. */
8468
8469 n_gpr = crtl->args.info.gprs;
8470 n_fpr = crtl->args.info.fprs;
8471
8472 if (cfun->va_list_gpr_size)
8473 {
8474 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8475 build_int_cst (NULL_TREE, n_gpr));
8476 TREE_SIDE_EFFECTS (t) = 1;
8477 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8478 }
8479
8480 if (cfun->va_list_fpr_size)
8481 {
8482 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8483 build_int_cst (NULL_TREE, n_fpr));
8484 TREE_SIDE_EFFECTS (t) = 1;
8485 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8486 }
8487
8488 /* Find the overflow area. */
8489 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8490 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8491 {
8492 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8493
8494 off = INTVAL (crtl->args.arg_offset_rtx);
8495 off = off < 0 ? 0 : off;
8496 if (TARGET_DEBUG_ARG)
8497 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8498 (int)n_gpr, (int)n_fpr, off);
8499
8500 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8501
8502 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8503 TREE_SIDE_EFFECTS (t) = 1;
8504 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8505 }
8506
8507 /* Find the register save area. */
8508 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8509 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8510 {
8511 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8512 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8513 size_int (-RETURN_REGNUM * UNITS_PER_WORD));
8514
8515 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8516 TREE_SIDE_EFFECTS (t) = 1;
8517 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8518 }
8519 }
8520
8521 /* Implement va_arg by updating the va_list structure
8522 VALIST as required to retrieve an argument of type
8523 TYPE, and returning that argument.
8524
8525 Generates code equivalent to:
8526
8527 if (integral value) {
8528 if (size <= 4 && args.gpr < 5 ||
8529 size > 4 && args.gpr < 4 )
8530 ret = args.reg_save_area[args.gpr+8]
8531 else
8532 ret = *args.overflow_arg_area++;
8533 } else if (float value) {
8534 if (args.fgpr < 2)
8535 ret = args.reg_save_area[args.fpr+64]
8536 else
8537 ret = *args.overflow_arg_area++;
8538 } else if (aggregate value) {
8539 if (args.gpr < 5)
8540 ret = *args.reg_save_area[args.gpr]
8541 else
8542 ret = **args.overflow_arg_area++;
8543 } */
8544
8545 static tree
8546 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8547 gimple_seq *post_p ATTRIBUTE_UNUSED)
8548 {
8549 tree f_gpr, f_fpr, f_ovf, f_sav;
8550 tree gpr, fpr, ovf, sav, reg, t, u;
8551 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8552 tree lab_false, lab_over, addr;
8553
8554 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8555 f_fpr = TREE_CHAIN (f_gpr);
8556 f_ovf = TREE_CHAIN (f_fpr);
8557 f_sav = TREE_CHAIN (f_ovf);
8558
8559 valist = build_va_arg_indirect_ref (valist);
8560 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8561 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8562 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8563
8564 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8565 both appear on a lhs. */
8566 valist = unshare_expr (valist);
8567 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8568
8569 size = int_size_in_bytes (type);
8570
8571 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8572 {
8573 if (TARGET_DEBUG_ARG)
8574 {
8575 fprintf (stderr, "va_arg: aggregate type");
8576 debug_tree (type);
8577 }
8578
8579 /* Aggregates are passed by reference. */
8580 indirect_p = 1;
8581 reg = gpr;
8582 n_reg = 1;
8583
8584 /* kernel stack layout on 31 bit: It is assumed here that no padding
8585 will be added by s390_frame_info because for va_args always an even
8586 number of gprs has to be saved r15-r2 = 14 regs. */
8587 sav_ofs = 2 * UNITS_PER_WORD;
8588 sav_scale = UNITS_PER_WORD;
8589 size = UNITS_PER_WORD;
8590 max_reg = GP_ARG_NUM_REG - n_reg;
8591 }
8592 else if (s390_function_arg_float (TYPE_MODE (type), type))
8593 {
8594 if (TARGET_DEBUG_ARG)
8595 {
8596 fprintf (stderr, "va_arg: float type");
8597 debug_tree (type);
8598 }
8599
8600 /* FP args go in FP registers, if present. */
8601 indirect_p = 0;
8602 reg = fpr;
8603 n_reg = 1;
8604 sav_ofs = 16 * UNITS_PER_WORD;
8605 sav_scale = 8;
8606 max_reg = FP_ARG_NUM_REG - n_reg;
8607 }
8608 else
8609 {
8610 if (TARGET_DEBUG_ARG)
8611 {
8612 fprintf (stderr, "va_arg: other type");
8613 debug_tree (type);
8614 }
8615
8616 /* Otherwise into GP registers. */
8617 indirect_p = 0;
8618 reg = gpr;
8619 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8620
8621 /* kernel stack layout on 31 bit: It is assumed here that no padding
8622 will be added by s390_frame_info because for va_args always an even
8623 number of gprs has to be saved r15-r2 = 14 regs. */
8624 sav_ofs = 2 * UNITS_PER_WORD;
8625
8626 if (size < UNITS_PER_WORD)
8627 sav_ofs += UNITS_PER_WORD - size;
8628
8629 sav_scale = UNITS_PER_WORD;
8630 max_reg = GP_ARG_NUM_REG - n_reg;
8631 }
8632
8633 /* Pull the value out of the saved registers ... */
8634
8635 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8636 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8637 addr = create_tmp_var (ptr_type_node, "addr");
8638
8639 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8640 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8641 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8642 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8643 gimplify_and_add (t, pre_p);
8644
8645 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8646 size_int (sav_ofs));
8647 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8648 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8649 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8650
8651 gimplify_assign (addr, t, pre_p);
8652
8653 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8654
8655 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8656
8657
8658 /* ... Otherwise out of the overflow area. */
8659
8660 t = ovf;
8661 if (size < UNITS_PER_WORD)
8662 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8663 size_int (UNITS_PER_WORD - size));
8664
8665 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8666
8667 gimplify_assign (addr, t, pre_p);
8668
8669 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8670 size_int (size));
8671 gimplify_assign (ovf, t, pre_p);
8672
8673 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8674
8675
8676 /* Increment register save count. */
8677
8678 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8679 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8680 gimplify_and_add (u, pre_p);
8681
8682 if (indirect_p)
8683 {
8684 t = build_pointer_type_for_mode (build_pointer_type (type),
8685 ptr_mode, true);
8686 addr = fold_convert (t, addr);
8687 addr = build_va_arg_indirect_ref (addr);
8688 }
8689 else
8690 {
8691 t = build_pointer_type_for_mode (type, ptr_mode, true);
8692 addr = fold_convert (t, addr);
8693 }
8694
8695 return build_va_arg_indirect_ref (addr);
8696 }
8697
8698
8699 /* Builtins. */
8700
8701 enum s390_builtin
8702 {
8703 S390_BUILTIN_THREAD_POINTER,
8704 S390_BUILTIN_SET_THREAD_POINTER,
8705
8706 S390_BUILTIN_max
8707 };
8708
8709 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8710 CODE_FOR_get_tp_64,
8711 CODE_FOR_set_tp_64
8712 };
8713
8714 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8715 CODE_FOR_get_tp_31,
8716 CODE_FOR_set_tp_31
8717 };
8718
8719 static void
8720 s390_init_builtins (void)
8721 {
8722 tree ftype;
8723
8724 ftype = build_function_type (ptr_type_node, void_list_node);
8725 add_builtin_function ("__builtin_thread_pointer", ftype,
8726 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8727 NULL, NULL_TREE);
8728
8729 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8730 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8731 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8732 NULL, NULL_TREE);
8733 }
8734
8735 /* Expand an expression EXP that calls a built-in function,
8736 with result going to TARGET if that's convenient
8737 (and in mode MODE if that's convenient).
8738 SUBTARGET may be used as the target for computing one of EXP's operands.
8739 IGNORE is nonzero if the value is to be ignored. */
8740
8741 static rtx
8742 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8743 enum machine_mode mode ATTRIBUTE_UNUSED,
8744 int ignore ATTRIBUTE_UNUSED)
8745 {
8746 #define MAX_ARGS 2
8747
8748 enum insn_code const *code_for_builtin =
8749 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8750
8751 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8752 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8753 enum insn_code icode;
8754 rtx op[MAX_ARGS], pat;
8755 int arity;
8756 bool nonvoid;
8757 tree arg;
8758 call_expr_arg_iterator iter;
8759
8760 if (fcode >= S390_BUILTIN_max)
8761 internal_error ("bad builtin fcode");
8762 icode = code_for_builtin[fcode];
8763 if (icode == 0)
8764 internal_error ("bad builtin fcode");
8765
8766 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8767
8768 arity = 0;
8769 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8770 {
8771 const struct insn_operand_data *insn_op;
8772
8773 if (arg == error_mark_node)
8774 return NULL_RTX;
8775 if (arity > MAX_ARGS)
8776 return NULL_RTX;
8777
8778 insn_op = &insn_data[icode].operand[arity + nonvoid];
8779
8780 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8781
8782 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8783 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8784 arity++;
8785 }
8786
8787 if (nonvoid)
8788 {
8789 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8790 if (!target
8791 || GET_MODE (target) != tmode
8792 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8793 target = gen_reg_rtx (tmode);
8794 }
8795
8796 switch (arity)
8797 {
8798 case 0:
8799 pat = GEN_FCN (icode) (target);
8800 break;
8801 case 1:
8802 if (nonvoid)
8803 pat = GEN_FCN (icode) (target, op[0]);
8804 else
8805 pat = GEN_FCN (icode) (op[0]);
8806 break;
8807 case 2:
8808 pat = GEN_FCN (icode) (target, op[0], op[1]);
8809 break;
8810 default:
8811 gcc_unreachable ();
8812 }
8813 if (!pat)
8814 return NULL_RTX;
8815 emit_insn (pat);
8816
8817 if (nonvoid)
8818 return target;
8819 else
8820 return const0_rtx;
8821 }
8822
8823
8824 /* Output assembly code for the trampoline template to
8825 stdio stream FILE.
8826
8827 On S/390, we use gpr 1 internally in the trampoline code;
8828 gpr 0 is used to hold the static chain. */
8829
8830 void
8831 s390_trampoline_template (FILE *file)
8832 {
8833 rtx op[2];
8834 op[0] = gen_rtx_REG (Pmode, 0);
8835 op[1] = gen_rtx_REG (Pmode, 1);
8836
8837 if (TARGET_64BIT)
8838 {
8839 output_asm_insn ("basr\t%1,0", op);
8840 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8841 output_asm_insn ("br\t%1", op);
8842 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8843 }
8844 else
8845 {
8846 output_asm_insn ("basr\t%1,0", op);
8847 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8848 output_asm_insn ("br\t%1", op);
8849 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8850 }
8851 }
8852
8853 /* Emit RTL insns to initialize the variable parts of a trampoline.
8854 FNADDR is an RTX for the address of the function's pure code.
8855 CXT is an RTX for the static chain value for the function. */
8856
8857 void
8858 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8859 {
8860 emit_move_insn (gen_rtx_MEM (Pmode,
8861 memory_address (Pmode,
8862 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8863 emit_move_insn (gen_rtx_MEM (Pmode,
8864 memory_address (Pmode,
8865 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8866 }
8867
8868 /* Output assembler code to FILE to increment profiler label # LABELNO
8869 for profiling a function entry. */
8870
8871 void
8872 s390_function_profiler (FILE *file, int labelno)
8873 {
8874 rtx op[7];
8875
8876 char label[128];
8877 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8878
8879 fprintf (file, "# function profiler \n");
8880
8881 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8882 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8883 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8884
8885 op[2] = gen_rtx_REG (Pmode, 1);
8886 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8887 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8888
8889 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8890 if (flag_pic)
8891 {
8892 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8893 op[4] = gen_rtx_CONST (Pmode, op[4]);
8894 }
8895
8896 if (TARGET_64BIT)
8897 {
8898 output_asm_insn ("stg\t%0,%1", op);
8899 output_asm_insn ("larl\t%2,%3", op);
8900 output_asm_insn ("brasl\t%0,%4", op);
8901 output_asm_insn ("lg\t%0,%1", op);
8902 }
8903 else if (!flag_pic)
8904 {
8905 op[6] = gen_label_rtx ();
8906
8907 output_asm_insn ("st\t%0,%1", op);
8908 output_asm_insn ("bras\t%2,%l6", op);
8909 output_asm_insn (".long\t%4", op);
8910 output_asm_insn (".long\t%3", op);
8911 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8912 output_asm_insn ("l\t%0,0(%2)", op);
8913 output_asm_insn ("l\t%2,4(%2)", op);
8914 output_asm_insn ("basr\t%0,%0", op);
8915 output_asm_insn ("l\t%0,%1", op);
8916 }
8917 else
8918 {
8919 op[5] = gen_label_rtx ();
8920 op[6] = gen_label_rtx ();
8921
8922 output_asm_insn ("st\t%0,%1", op);
8923 output_asm_insn ("bras\t%2,%l6", op);
8924 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8925 output_asm_insn (".long\t%4-%l5", op);
8926 output_asm_insn (".long\t%3-%l5", op);
8927 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8928 output_asm_insn ("lr\t%0,%2", op);
8929 output_asm_insn ("a\t%0,0(%2)", op);
8930 output_asm_insn ("a\t%2,4(%2)", op);
8931 output_asm_insn ("basr\t%0,%0", op);
8932 output_asm_insn ("l\t%0,%1", op);
8933 }
8934 }
8935
8936 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8937 into its SYMBOL_REF_FLAGS. */
8938
8939 static void
8940 s390_encode_section_info (tree decl, rtx rtl, int first)
8941 {
8942 default_encode_section_info (decl, rtl, first);
8943
8944 if (TREE_CODE (decl) == VAR_DECL)
8945 {
8946 /* If a variable has a forced alignment to < 2 bytes, mark it
8947 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
8948 operand. */
8949 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8950 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8951 if (!DECL_SIZE (decl)
8952 || !DECL_ALIGN (decl)
8953 || !host_integerp (DECL_SIZE (decl), 0)
8954 || (DECL_ALIGN (decl) <= 64
8955 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
8956 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8957 }
8958
8959 /* Literal pool references don't have a decl so they are handled
8960 differently here. We rely on the information in the MEM_ALIGN
8961 entry to decide upon natural alignment. */
8962 if (MEM_P (rtl)
8963 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
8964 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
8965 && (MEM_ALIGN (rtl) == 0
8966 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
8967 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8968 }
8969
8970 /* Output thunk to FILE that implements a C++ virtual function call (with
8971 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8972 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8973 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8974 relative to the resulting this pointer. */
8975
8976 static void
8977 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8978 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8979 tree function)
8980 {
8981 rtx op[10];
8982 int nonlocal = 0;
8983
8984 /* Operand 0 is the target function. */
8985 op[0] = XEXP (DECL_RTL (function), 0);
8986 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8987 {
8988 nonlocal = 1;
8989 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8990 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8991 op[0] = gen_rtx_CONST (Pmode, op[0]);
8992 }
8993
8994 /* Operand 1 is the 'this' pointer. */
8995 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8996 op[1] = gen_rtx_REG (Pmode, 3);
8997 else
8998 op[1] = gen_rtx_REG (Pmode, 2);
8999
9000 /* Operand 2 is the delta. */
9001 op[2] = GEN_INT (delta);
9002
9003 /* Operand 3 is the vcall_offset. */
9004 op[3] = GEN_INT (vcall_offset);
9005
9006 /* Operand 4 is the temporary register. */
9007 op[4] = gen_rtx_REG (Pmode, 1);
9008
9009 /* Operands 5 to 8 can be used as labels. */
9010 op[5] = NULL_RTX;
9011 op[6] = NULL_RTX;
9012 op[7] = NULL_RTX;
9013 op[8] = NULL_RTX;
9014
9015 /* Operand 9 can be used for temporary register. */
9016 op[9] = NULL_RTX;
9017
9018 /* Generate code. */
9019 if (TARGET_64BIT)
9020 {
9021 /* Setup literal pool pointer if required. */
9022 if ((!DISP_IN_RANGE (delta)
9023 && !CONST_OK_FOR_K (delta)
9024 && !CONST_OK_FOR_Os (delta))
9025 || (!DISP_IN_RANGE (vcall_offset)
9026 && !CONST_OK_FOR_K (vcall_offset)
9027 && !CONST_OK_FOR_Os (vcall_offset)))
9028 {
9029 op[5] = gen_label_rtx ();
9030 output_asm_insn ("larl\t%4,%5", op);
9031 }
9032
9033 /* Add DELTA to this pointer. */
9034 if (delta)
9035 {
9036 if (CONST_OK_FOR_J (delta))
9037 output_asm_insn ("la\t%1,%2(%1)", op);
9038 else if (DISP_IN_RANGE (delta))
9039 output_asm_insn ("lay\t%1,%2(%1)", op);
9040 else if (CONST_OK_FOR_K (delta))
9041 output_asm_insn ("aghi\t%1,%2", op);
9042 else if (CONST_OK_FOR_Os (delta))
9043 output_asm_insn ("agfi\t%1,%2", op);
9044 else
9045 {
9046 op[6] = gen_label_rtx ();
9047 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9048 }
9049 }
9050
9051 /* Perform vcall adjustment. */
9052 if (vcall_offset)
9053 {
9054 if (DISP_IN_RANGE (vcall_offset))
9055 {
9056 output_asm_insn ("lg\t%4,0(%1)", op);
9057 output_asm_insn ("ag\t%1,%3(%4)", op);
9058 }
9059 else if (CONST_OK_FOR_K (vcall_offset))
9060 {
9061 output_asm_insn ("lghi\t%4,%3", op);
9062 output_asm_insn ("ag\t%4,0(%1)", op);
9063 output_asm_insn ("ag\t%1,0(%4)", op);
9064 }
9065 else if (CONST_OK_FOR_Os (vcall_offset))
9066 {
9067 output_asm_insn ("lgfi\t%4,%3", op);
9068 output_asm_insn ("ag\t%4,0(%1)", op);
9069 output_asm_insn ("ag\t%1,0(%4)", op);
9070 }
9071 else
9072 {
9073 op[7] = gen_label_rtx ();
9074 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9075 output_asm_insn ("ag\t%4,0(%1)", op);
9076 output_asm_insn ("ag\t%1,0(%4)", op);
9077 }
9078 }
9079
9080 /* Jump to target. */
9081 output_asm_insn ("jg\t%0", op);
9082
9083 /* Output literal pool if required. */
9084 if (op[5])
9085 {
9086 output_asm_insn (".align\t4", op);
9087 targetm.asm_out.internal_label (file, "L",
9088 CODE_LABEL_NUMBER (op[5]));
9089 }
9090 if (op[6])
9091 {
9092 targetm.asm_out.internal_label (file, "L",
9093 CODE_LABEL_NUMBER (op[6]));
9094 output_asm_insn (".long\t%2", op);
9095 }
9096 if (op[7])
9097 {
9098 targetm.asm_out.internal_label (file, "L",
9099 CODE_LABEL_NUMBER (op[7]));
9100 output_asm_insn (".long\t%3", op);
9101 }
9102 }
9103 else
9104 {
9105 /* Setup base pointer if required. */
9106 if (!vcall_offset
9107 || (!DISP_IN_RANGE (delta)
9108 && !CONST_OK_FOR_K (delta)
9109 && !CONST_OK_FOR_Os (delta))
9110 || (!DISP_IN_RANGE (delta)
9111 && !CONST_OK_FOR_K (vcall_offset)
9112 && !CONST_OK_FOR_Os (vcall_offset)))
9113 {
9114 op[5] = gen_label_rtx ();
9115 output_asm_insn ("basr\t%4,0", op);
9116 targetm.asm_out.internal_label (file, "L",
9117 CODE_LABEL_NUMBER (op[5]));
9118 }
9119
9120 /* Add DELTA to this pointer. */
9121 if (delta)
9122 {
9123 if (CONST_OK_FOR_J (delta))
9124 output_asm_insn ("la\t%1,%2(%1)", op);
9125 else if (DISP_IN_RANGE (delta))
9126 output_asm_insn ("lay\t%1,%2(%1)", op);
9127 else if (CONST_OK_FOR_K (delta))
9128 output_asm_insn ("ahi\t%1,%2", op);
9129 else if (CONST_OK_FOR_Os (delta))
9130 output_asm_insn ("afi\t%1,%2", op);
9131 else
9132 {
9133 op[6] = gen_label_rtx ();
9134 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9135 }
9136 }
9137
9138 /* Perform vcall adjustment. */
9139 if (vcall_offset)
9140 {
9141 if (CONST_OK_FOR_J (vcall_offset))
9142 {
9143 output_asm_insn ("l\t%4,0(%1)", op);
9144 output_asm_insn ("a\t%1,%3(%4)", op);
9145 }
9146 else if (DISP_IN_RANGE (vcall_offset))
9147 {
9148 output_asm_insn ("l\t%4,0(%1)", op);
9149 output_asm_insn ("ay\t%1,%3(%4)", op);
9150 }
9151 else if (CONST_OK_FOR_K (vcall_offset))
9152 {
9153 output_asm_insn ("lhi\t%4,%3", op);
9154 output_asm_insn ("a\t%4,0(%1)", op);
9155 output_asm_insn ("a\t%1,0(%4)", op);
9156 }
9157 else if (CONST_OK_FOR_Os (vcall_offset))
9158 {
9159 output_asm_insn ("iilf\t%4,%3", op);
9160 output_asm_insn ("a\t%4,0(%1)", op);
9161 output_asm_insn ("a\t%1,0(%4)", op);
9162 }
9163 else
9164 {
9165 op[7] = gen_label_rtx ();
9166 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9167 output_asm_insn ("a\t%4,0(%1)", op);
9168 output_asm_insn ("a\t%1,0(%4)", op);
9169 }
9170
9171 /* We had to clobber the base pointer register.
9172 Re-setup the base pointer (with a different base). */
9173 op[5] = gen_label_rtx ();
9174 output_asm_insn ("basr\t%4,0", op);
9175 targetm.asm_out.internal_label (file, "L",
9176 CODE_LABEL_NUMBER (op[5]));
9177 }
9178
9179 /* Jump to target. */
9180 op[8] = gen_label_rtx ();
9181
9182 if (!flag_pic)
9183 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9184 else if (!nonlocal)
9185 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9186 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9187 else if (flag_pic == 1)
9188 {
9189 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9190 output_asm_insn ("l\t%4,%0(%4)", op);
9191 }
9192 else if (flag_pic == 2)
9193 {
9194 op[9] = gen_rtx_REG (Pmode, 0);
9195 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9196 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9197 output_asm_insn ("ar\t%4,%9", op);
9198 output_asm_insn ("l\t%4,0(%4)", op);
9199 }
9200
9201 output_asm_insn ("br\t%4", op);
9202
9203 /* Output literal pool. */
9204 output_asm_insn (".align\t4", op);
9205
9206 if (nonlocal && flag_pic == 2)
9207 output_asm_insn (".long\t%0", op);
9208 if (nonlocal)
9209 {
9210 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9211 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9212 }
9213
9214 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9215 if (!flag_pic)
9216 output_asm_insn (".long\t%0", op);
9217 else
9218 output_asm_insn (".long\t%0-%5", op);
9219
9220 if (op[6])
9221 {
9222 targetm.asm_out.internal_label (file, "L",
9223 CODE_LABEL_NUMBER (op[6]));
9224 output_asm_insn (".long\t%2", op);
9225 }
9226 if (op[7])
9227 {
9228 targetm.asm_out.internal_label (file, "L",
9229 CODE_LABEL_NUMBER (op[7]));
9230 output_asm_insn (".long\t%3", op);
9231 }
9232 }
9233 }
9234
9235 static bool
9236 s390_valid_pointer_mode (enum machine_mode mode)
9237 {
9238 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9239 }
9240
9241 /* Checks whether the given CALL_EXPR would use a caller
9242 saved register. This is used to decide whether sibling call
9243 optimization could be performed on the respective function
9244 call. */
9245
9246 static bool
9247 s390_call_saved_register_used (tree call_expr)
9248 {
9249 CUMULATIVE_ARGS cum;
9250 tree parameter;
9251 enum machine_mode mode;
9252 tree type;
9253 rtx parm_rtx;
9254 int reg, i;
9255
9256 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9257
9258 for (i = 0; i < call_expr_nargs (call_expr); i++)
9259 {
9260 parameter = CALL_EXPR_ARG (call_expr, i);
9261 gcc_assert (parameter);
9262
9263 /* For an undeclared variable passed as parameter we will get
9264 an ERROR_MARK node here. */
9265 if (TREE_CODE (parameter) == ERROR_MARK)
9266 return true;
9267
9268 type = TREE_TYPE (parameter);
9269 gcc_assert (type);
9270
9271 mode = TYPE_MODE (type);
9272 gcc_assert (mode);
9273
9274 if (pass_by_reference (&cum, mode, type, true))
9275 {
9276 mode = Pmode;
9277 type = build_pointer_type (type);
9278 }
9279
9280 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9281
9282 s390_function_arg_advance (&cum, mode, type, 0);
9283
9284 if (parm_rtx && REG_P (parm_rtx))
9285 {
9286 for (reg = 0;
9287 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9288 reg++)
9289 if (! call_used_regs[reg + REGNO (parm_rtx)])
9290 return true;
9291 }
9292 }
9293 return false;
9294 }
9295
9296 /* Return true if the given call expression can be
9297 turned into a sibling call.
9298 DECL holds the declaration of the function to be called whereas
9299 EXP is the call expression itself. */
9300
9301 static bool
9302 s390_function_ok_for_sibcall (tree decl, tree exp)
9303 {
9304 /* The TPF epilogue uses register 1. */
9305 if (TARGET_TPF_PROFILING)
9306 return false;
9307
9308 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9309 which would have to be restored before the sibcall. */
9310 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9311 return false;
9312
9313 /* Register 6 on s390 is available as an argument register but unfortunately
9314 "caller saved". This makes functions needing this register for arguments
9315 not suitable for sibcalls. */
9316 return !s390_call_saved_register_used (exp);
9317 }
9318
9319 /* Return the fixed registers used for condition codes. */
9320
9321 static bool
9322 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9323 {
9324 *p1 = CC_REGNUM;
9325 *p2 = INVALID_REGNUM;
9326
9327 return true;
9328 }
9329
9330 /* This function is used by the call expanders of the machine description.
9331 It emits the call insn itself together with the necessary operations
9332 to adjust the target address and returns the emitted insn.
9333 ADDR_LOCATION is the target address rtx
9334 TLS_CALL the location of the thread-local symbol
9335 RESULT_REG the register where the result of the call should be stored
9336 RETADDR_REG the register where the return address should be stored
9337 If this parameter is NULL_RTX the call is considered
9338 to be a sibling call. */
9339
9340 rtx
9341 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9342 rtx retaddr_reg)
9343 {
9344 bool plt_call = false;
9345 rtx insn;
9346 rtx call;
9347 rtx clobber;
9348 rtvec vec;
9349
9350 /* Direct function calls need special treatment. */
9351 if (GET_CODE (addr_location) == SYMBOL_REF)
9352 {
9353 /* When calling a global routine in PIC mode, we must
9354 replace the symbol itself with the PLT stub. */
9355 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9356 {
9357 addr_location = gen_rtx_UNSPEC (Pmode,
9358 gen_rtvec (1, addr_location),
9359 UNSPEC_PLT);
9360 addr_location = gen_rtx_CONST (Pmode, addr_location);
9361 plt_call = true;
9362 }
9363
9364 /* Unless we can use the bras(l) insn, force the
9365 routine address into a register. */
9366 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9367 {
9368 if (flag_pic)
9369 addr_location = legitimize_pic_address (addr_location, 0);
9370 else
9371 addr_location = force_reg (Pmode, addr_location);
9372 }
9373 }
9374
9375 /* If it is already an indirect call or the code above moved the
9376 SYMBOL_REF to somewhere else make sure the address can be found in
9377 register 1. */
9378 if (retaddr_reg == NULL_RTX
9379 && GET_CODE (addr_location) != SYMBOL_REF
9380 && !plt_call)
9381 {
9382 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9383 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9384 }
9385
9386 addr_location = gen_rtx_MEM (QImode, addr_location);
9387 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9388
9389 if (result_reg != NULL_RTX)
9390 call = gen_rtx_SET (VOIDmode, result_reg, call);
9391
9392 if (retaddr_reg != NULL_RTX)
9393 {
9394 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9395
9396 if (tls_call != NULL_RTX)
9397 vec = gen_rtvec (3, call, clobber,
9398 gen_rtx_USE (VOIDmode, tls_call));
9399 else
9400 vec = gen_rtvec (2, call, clobber);
9401
9402 call = gen_rtx_PARALLEL (VOIDmode, vec);
9403 }
9404
9405 insn = emit_call_insn (call);
9406
9407 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9408 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9409 {
9410 /* s390_function_ok_for_sibcall should
9411 have denied sibcalls in this case. */
9412 gcc_assert (retaddr_reg != NULL_RTX);
9413
9414 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9415 }
9416 return insn;
9417 }
9418
9419 /* Implement CONDITIONAL_REGISTER_USAGE. */
9420
9421 void
9422 s390_conditional_register_usage (void)
9423 {
9424 int i;
9425
9426 if (flag_pic)
9427 {
9428 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9429 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9430 }
9431 if (TARGET_CPU_ZARCH)
9432 {
9433 fixed_regs[BASE_REGNUM] = 0;
9434 call_used_regs[BASE_REGNUM] = 0;
9435 fixed_regs[RETURN_REGNUM] = 0;
9436 call_used_regs[RETURN_REGNUM] = 0;
9437 }
9438 if (TARGET_64BIT)
9439 {
9440 for (i = 24; i < 32; i++)
9441 call_used_regs[i] = call_really_used_regs[i] = 0;
9442 }
9443 else
9444 {
9445 for (i = 18; i < 20; i++)
9446 call_used_regs[i] = call_really_used_regs[i] = 0;
9447 }
9448
9449 if (TARGET_SOFT_FLOAT)
9450 {
9451 for (i = 16; i < 32; i++)
9452 call_used_regs[i] = fixed_regs[i] = 1;
9453 }
9454 }
9455
9456 /* Corresponding function to eh_return expander. */
9457
9458 static GTY(()) rtx s390_tpf_eh_return_symbol;
9459 void
9460 s390_emit_tpf_eh_return (rtx target)
9461 {
9462 rtx insn, reg;
9463
9464 if (!s390_tpf_eh_return_symbol)
9465 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9466
9467 reg = gen_rtx_REG (Pmode, 2);
9468
9469 emit_move_insn (reg, target);
9470 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9471 gen_rtx_REG (Pmode, RETURN_REGNUM));
9472 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9473
9474 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9475 }
9476
9477 /* Rework the prologue/epilogue to avoid saving/restoring
9478 registers unnecessarily. */
9479
9480 static void
9481 s390_optimize_prologue (void)
9482 {
9483 rtx insn, new_insn, next_insn;
9484
9485 /* Do a final recompute of the frame-related data. */
9486
9487 s390_update_frame_layout ();
9488
9489 /* If all special registers are in fact used, there's nothing we
9490 can do, so no point in walking the insn list. */
9491
9492 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9493 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9494 && (TARGET_CPU_ZARCH
9495 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9496 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9497 return;
9498
9499 /* Search for prologue/epilogue insns and replace them. */
9500
9501 for (insn = get_insns (); insn; insn = next_insn)
9502 {
9503 int first, last, off;
9504 rtx set, base, offset;
9505
9506 next_insn = NEXT_INSN (insn);
9507
9508 if (GET_CODE (insn) != INSN)
9509 continue;
9510
9511 if (GET_CODE (PATTERN (insn)) == PARALLEL
9512 && store_multiple_operation (PATTERN (insn), VOIDmode))
9513 {
9514 set = XVECEXP (PATTERN (insn), 0, 0);
9515 first = REGNO (SET_SRC (set));
9516 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9517 offset = const0_rtx;
9518 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9519 off = INTVAL (offset);
9520
9521 if (GET_CODE (base) != REG || off < 0)
9522 continue;
9523 if (cfun_frame_layout.first_save_gpr != -1
9524 && (cfun_frame_layout.first_save_gpr < first
9525 || cfun_frame_layout.last_save_gpr > last))
9526 continue;
9527 if (REGNO (base) != STACK_POINTER_REGNUM
9528 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9529 continue;
9530 if (first > BASE_REGNUM || last < BASE_REGNUM)
9531 continue;
9532
9533 if (cfun_frame_layout.first_save_gpr != -1)
9534 {
9535 new_insn = save_gprs (base,
9536 off + (cfun_frame_layout.first_save_gpr
9537 - first) * UNITS_PER_WORD,
9538 cfun_frame_layout.first_save_gpr,
9539 cfun_frame_layout.last_save_gpr);
9540 new_insn = emit_insn_before (new_insn, insn);
9541 INSN_ADDRESSES_NEW (new_insn, -1);
9542 }
9543
9544 remove_insn (insn);
9545 continue;
9546 }
9547
9548 if (cfun_frame_layout.first_save_gpr == -1
9549 && GET_CODE (PATTERN (insn)) == SET
9550 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9551 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9552 || (!TARGET_CPU_ZARCH
9553 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9554 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9555 {
9556 set = PATTERN (insn);
9557 first = REGNO (SET_SRC (set));
9558 offset = const0_rtx;
9559 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9560 off = INTVAL (offset);
9561
9562 if (GET_CODE (base) != REG || off < 0)
9563 continue;
9564 if (REGNO (base) != STACK_POINTER_REGNUM
9565 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9566 continue;
9567
9568 remove_insn (insn);
9569 continue;
9570 }
9571
9572 if (GET_CODE (PATTERN (insn)) == PARALLEL
9573 && load_multiple_operation (PATTERN (insn), VOIDmode))
9574 {
9575 set = XVECEXP (PATTERN (insn), 0, 0);
9576 first = REGNO (SET_DEST (set));
9577 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9578 offset = const0_rtx;
9579 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9580 off = INTVAL (offset);
9581
9582 if (GET_CODE (base) != REG || off < 0)
9583 continue;
9584 if (cfun_frame_layout.first_restore_gpr != -1
9585 && (cfun_frame_layout.first_restore_gpr < first
9586 || cfun_frame_layout.last_restore_gpr > last))
9587 continue;
9588 if (REGNO (base) != STACK_POINTER_REGNUM
9589 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9590 continue;
9591 if (first > BASE_REGNUM || last < BASE_REGNUM)
9592 continue;
9593
9594 if (cfun_frame_layout.first_restore_gpr != -1)
9595 {
9596 new_insn = restore_gprs (base,
9597 off + (cfun_frame_layout.first_restore_gpr
9598 - first) * UNITS_PER_WORD,
9599 cfun_frame_layout.first_restore_gpr,
9600 cfun_frame_layout.last_restore_gpr);
9601 new_insn = emit_insn_before (new_insn, insn);
9602 INSN_ADDRESSES_NEW (new_insn, -1);
9603 }
9604
9605 remove_insn (insn);
9606 continue;
9607 }
9608
9609 if (cfun_frame_layout.first_restore_gpr == -1
9610 && GET_CODE (PATTERN (insn)) == SET
9611 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9612 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9613 || (!TARGET_CPU_ZARCH
9614 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9615 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9616 {
9617 set = PATTERN (insn);
9618 first = REGNO (SET_DEST (set));
9619 offset = const0_rtx;
9620 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9621 off = INTVAL (offset);
9622
9623 if (GET_CODE (base) != REG || off < 0)
9624 continue;
9625 if (REGNO (base) != STACK_POINTER_REGNUM
9626 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9627 continue;
9628
9629 remove_insn (insn);
9630 continue;
9631 }
9632 }
9633 }
9634
9635 /* Returns 1 if INSN reads the value of REG for purposes not related
9636 to addressing of memory, and 0 otherwise. */
9637 static int
9638 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9639 {
9640 return reg_referenced_p (reg, PATTERN (insn))
9641 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9642 }
9643
9644 /* Starting from INSN find_cond_jump looks downwards in the insn
9645 stream for a single jump insn which is the last user of the
9646 condition code set in INSN. */
9647 static rtx
9648 find_cond_jump (rtx insn)
9649 {
9650 for (; insn; insn = NEXT_INSN (insn))
9651 {
9652 rtx ite, cc;
9653
9654 if (LABEL_P (insn))
9655 break;
9656
9657 if (!JUMP_P (insn))
9658 {
9659 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9660 break;
9661 continue;
9662 }
9663
9664 /* This will be triggered by a return. */
9665 if (GET_CODE (PATTERN (insn)) != SET)
9666 break;
9667
9668 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9669 ite = SET_SRC (PATTERN (insn));
9670
9671 if (GET_CODE (ite) != IF_THEN_ELSE)
9672 break;
9673
9674 cc = XEXP (XEXP (ite, 0), 0);
9675 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9676 break;
9677
9678 if (find_reg_note (insn, REG_DEAD, cc))
9679 return insn;
9680 break;
9681 }
9682
9683 return NULL_RTX;
9684 }
9685
9686 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9687 the semantics does not change. If NULL_RTX is passed as COND the
9688 function tries to find the conditional jump starting with INSN. */
9689 static void
9690 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9691 {
9692 rtx tmp = *op0;
9693
9694 if (cond == NULL_RTX)
9695 {
9696 rtx jump = find_cond_jump (NEXT_INSN (insn));
9697 jump = jump ? single_set (jump) : NULL_RTX;
9698
9699 if (jump == NULL_RTX)
9700 return;
9701
9702 cond = XEXP (XEXP (jump, 1), 0);
9703 }
9704
9705 *op0 = *op1;
9706 *op1 = tmp;
9707 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9708 }
9709
9710 /* On z10, instructions of the compare-and-branch family have the
9711 property to access the register occurring as second operand with
9712 its bits complemented. If such a compare is grouped with a second
9713 instruction that accesses the same register non-complemented, and
9714 if that register's value is delivered via a bypass, then the
9715 pipeline recycles, thereby causing significant performance decline.
9716 This function locates such situations and exchanges the two
9717 operands of the compare. */
9718 static void
9719 s390_z10_optimize_cmp (void)
9720 {
9721 rtx insn, prev_insn, next_insn;
9722 int added_NOPs = 0;
9723
9724 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9725 {
9726 rtx cond, *op0, *op1;
9727
9728 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
9729 continue;
9730
9731 if (GET_CODE (PATTERN (insn)) == PARALLEL)
9732 {
9733 /* Handle compare and branch and branch on count
9734 instructions. */
9735 rtx pattern = single_set (insn);
9736
9737 if (!pattern
9738 || SET_DEST (pattern) != pc_rtx
9739 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
9740 continue;
9741
9742 cond = XEXP (SET_SRC (pattern), 0);
9743 op0 = &XEXP (cond, 0);
9744 op1 = &XEXP (cond, 1);
9745 }
9746 else if (GET_CODE (PATTERN (insn)) == SET)
9747 {
9748 rtx src, dest;
9749
9750 /* Handle normal compare instructions. */
9751 src = SET_SRC (PATTERN (insn));
9752 dest = SET_DEST (PATTERN (insn));
9753
9754 if (!REG_P (dest)
9755 || !CC_REGNO_P (REGNO (dest))
9756 || GET_CODE (src) != COMPARE)
9757 continue;
9758
9759 /* s390_swap_cmp will try to find the conditional
9760 jump when passing NULL_RTX as condition. */
9761 cond = NULL_RTX;
9762 op0 = &XEXP (src, 0);
9763 op1 = &XEXP (src, 1);
9764 }
9765 else
9766 continue;
9767
9768 if (!REG_P (*op0) || !REG_P (*op1))
9769 continue;
9770
9771 /* Swap the COMPARE arguments and its mask if there is a
9772 conflicting access in the previous insn. */
9773 prev_insn = PREV_INSN (insn);
9774 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9775 && reg_referenced_p (*op1, PATTERN (prev_insn)))
9776 s390_swap_cmp (cond, op0, op1, insn);
9777
9778 /* Check if there is a conflict with the next insn. If there
9779 was no conflict with the previous insn, then swap the
9780 COMPARE arguments and its mask. If we already swapped
9781 the operands, or if swapping them would cause a conflict
9782 with the previous insn, issue a NOP after the COMPARE in
9783 order to separate the two instuctions. */
9784 next_insn = NEXT_INSN (insn);
9785 if (next_insn != NULL_RTX && INSN_P (next_insn)
9786 && s390_non_addr_reg_read_p (*op1, next_insn))
9787 {
9788 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9789 && s390_non_addr_reg_read_p (*op0, prev_insn))
9790 {
9791 if (REGNO (*op1) == 0)
9792 emit_insn_after (gen_nop1 (), insn);
9793 else
9794 emit_insn_after (gen_nop (), insn);
9795 added_NOPs = 1;
9796 }
9797 else
9798 s390_swap_cmp (cond, op0, op1, insn);
9799 }
9800 }
9801
9802 /* Adjust branches if we added new instructions. */
9803 if (added_NOPs)
9804 shorten_branches (get_insns ());
9805 }
9806
9807
9808 /* Perform machine-dependent processing. */
9809
9810 static void
9811 s390_reorg (void)
9812 {
9813 bool pool_overflow = false;
9814
9815 /* Make sure all splits have been performed; splits after
9816 machine_dependent_reorg might confuse insn length counts. */
9817 split_all_insns_noflow ();
9818
9819 /* Install the main literal pool and the associated base
9820 register load insns.
9821
9822 In addition, there are two problematic situations we need
9823 to correct:
9824
9825 - the literal pool might be > 4096 bytes in size, so that
9826 some of its elements cannot be directly accessed
9827
9828 - a branch target might be > 64K away from the branch, so that
9829 it is not possible to use a PC-relative instruction.
9830
9831 To fix those, we split the single literal pool into multiple
9832 pool chunks, reloading the pool base register at various
9833 points throughout the function to ensure it always points to
9834 the pool chunk the following code expects, and / or replace
9835 PC-relative branches by absolute branches.
9836
9837 However, the two problems are interdependent: splitting the
9838 literal pool can move a branch further away from its target,
9839 causing the 64K limit to overflow, and on the other hand,
9840 replacing a PC-relative branch by an absolute branch means
9841 we need to put the branch target address into the literal
9842 pool, possibly causing it to overflow.
9843
9844 So, we loop trying to fix up both problems until we manage
9845 to satisfy both conditions at the same time. Note that the
9846 loop is guaranteed to terminate as every pass of the loop
9847 strictly decreases the total number of PC-relative branches
9848 in the function. (This is not completely true as there
9849 might be branch-over-pool insns introduced by chunkify_start.
9850 Those never need to be split however.) */
9851
9852 for (;;)
9853 {
9854 struct constant_pool *pool = NULL;
9855
9856 /* Collect the literal pool. */
9857 if (!pool_overflow)
9858 {
9859 pool = s390_mainpool_start ();
9860 if (!pool)
9861 pool_overflow = true;
9862 }
9863
9864 /* If literal pool overflowed, start to chunkify it. */
9865 if (pool_overflow)
9866 pool = s390_chunkify_start ();
9867
9868 /* Split out-of-range branches. If this has created new
9869 literal pool entries, cancel current chunk list and
9870 recompute it. zSeries machines have large branch
9871 instructions, so we never need to split a branch. */
9872 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9873 {
9874 if (pool_overflow)
9875 s390_chunkify_cancel (pool);
9876 else
9877 s390_mainpool_cancel (pool);
9878
9879 continue;
9880 }
9881
9882 /* If we made it up to here, both conditions are satisfied.
9883 Finish up literal pool related changes. */
9884 if (pool_overflow)
9885 s390_chunkify_finish (pool);
9886 else
9887 s390_mainpool_finish (pool);
9888
9889 /* We're done splitting branches. */
9890 cfun->machine->split_branches_pending_p = false;
9891 break;
9892 }
9893
9894 /* Generate out-of-pool execute target insns. */
9895 if (TARGET_CPU_ZARCH)
9896 {
9897 rtx insn, label, target;
9898
9899 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9900 {
9901 label = s390_execute_label (insn);
9902 if (!label)
9903 continue;
9904
9905 gcc_assert (label != const0_rtx);
9906
9907 target = emit_label (XEXP (label, 0));
9908 INSN_ADDRESSES_NEW (target, -1);
9909
9910 target = emit_insn (s390_execute_target (insn));
9911 INSN_ADDRESSES_NEW (target, -1);
9912 }
9913 }
9914
9915 /* Try to optimize prologue and epilogue further. */
9916 s390_optimize_prologue ();
9917
9918 /* Eliminate z10-specific pipeline recycles related to some compare
9919 instructions. */
9920 if (s390_tune == PROCESSOR_2097_Z10)
9921 s390_z10_optimize_cmp ();
9922 }
9923
9924
9925 /* Initialize GCC target structure. */
9926
9927 #undef TARGET_ASM_ALIGNED_HI_OP
9928 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9929 #undef TARGET_ASM_ALIGNED_DI_OP
9930 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9931 #undef TARGET_ASM_INTEGER
9932 #define TARGET_ASM_INTEGER s390_assemble_integer
9933
9934 #undef TARGET_ASM_OPEN_PAREN
9935 #define TARGET_ASM_OPEN_PAREN ""
9936
9937 #undef TARGET_ASM_CLOSE_PAREN
9938 #define TARGET_ASM_CLOSE_PAREN ""
9939
9940 #undef TARGET_DEFAULT_TARGET_FLAGS
9941 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9942 #undef TARGET_HANDLE_OPTION
9943 #define TARGET_HANDLE_OPTION s390_handle_option
9944
9945 #undef TARGET_ENCODE_SECTION_INFO
9946 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9947
9948 #ifdef HAVE_AS_TLS
9949 #undef TARGET_HAVE_TLS
9950 #define TARGET_HAVE_TLS true
9951 #endif
9952 #undef TARGET_CANNOT_FORCE_CONST_MEM
9953 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9954
9955 #undef TARGET_DELEGITIMIZE_ADDRESS
9956 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9957
9958 #undef TARGET_LEGITIMIZE_ADDRESS
9959 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
9960
9961 #undef TARGET_RETURN_IN_MEMORY
9962 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9963
9964 #undef TARGET_INIT_BUILTINS
9965 #define TARGET_INIT_BUILTINS s390_init_builtins
9966 #undef TARGET_EXPAND_BUILTIN
9967 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9968
9969 #undef TARGET_ASM_OUTPUT_MI_THUNK
9970 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9971 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9972 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
9973
9974 #undef TARGET_SCHED_ADJUST_PRIORITY
9975 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9976 #undef TARGET_SCHED_ISSUE_RATE
9977 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9978 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9979 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9980
9981 #undef TARGET_CANNOT_COPY_INSN_P
9982 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9983 #undef TARGET_RTX_COSTS
9984 #define TARGET_RTX_COSTS s390_rtx_costs
9985 #undef TARGET_ADDRESS_COST
9986 #define TARGET_ADDRESS_COST s390_address_cost
9987
9988 #undef TARGET_MACHINE_DEPENDENT_REORG
9989 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9990
9991 #undef TARGET_VALID_POINTER_MODE
9992 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9993
9994 #undef TARGET_BUILD_BUILTIN_VA_LIST
9995 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9996 #undef TARGET_EXPAND_BUILTIN_VA_START
9997 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
9998 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9999 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10000
10001 #undef TARGET_PROMOTE_FUNCTION_ARGS
10002 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
10003 #undef TARGET_PROMOTE_FUNCTION_RETURN
10004 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
10005 #undef TARGET_PASS_BY_REFERENCE
10006 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10007
10008 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10009 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10010
10011 #undef TARGET_FIXED_CONDITION_CODE_REGS
10012 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10013
10014 #undef TARGET_CC_MODES_COMPATIBLE
10015 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10016
10017 #undef TARGET_INVALID_WITHIN_DOLOOP
10018 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10019
10020 #ifdef HAVE_AS_TLS
10021 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10022 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10023 #endif
10024
10025 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10026 #undef TARGET_MANGLE_TYPE
10027 #define TARGET_MANGLE_TYPE s390_mangle_type
10028 #endif
10029
10030 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10031 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10032
10033 #undef TARGET_SECONDARY_RELOAD
10034 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10035
10036 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10037 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10038
10039 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10040 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10041
10042 #undef TARGET_LEGITIMATE_ADDRESS_P
10043 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10044
10045 struct gcc_target targetm = TARGET_INITIALIZER;
10046
10047 #include "gt-s390.h"