gcc/config/s390/s390.h

   1 /* Definitions of target machine for GNU compiler, for IBM S/390
   2    Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   3    2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   4    Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   5                   Ulrich Weigand (uweigand@de.ibm.com).
   6                   Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify it under
  11 the terms of the GNU General Public License as published by the Free
  12 Software Foundation; either version 3, or (at your option) any later
  13 version.
  14
  15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18 for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not see
  22 <http://www.gnu.org/licenses/>.  */
  23
  24 #ifndef _S390_H
  25 #define _S390_H
  26
  27 /* Which processor to generate code or schedule for. The cpu attribute
  28    defines a list that mirrors this list, so changes to s390.md must be
  29    made at the same time.  */
  30
  31 enum processor_type
  32 {
  33   PROCESSOR_9672_G5,
  34   PROCESSOR_9672_G6,
  35   PROCESSOR_2064_Z900,
  36   PROCESSOR_2084_Z990,
  37   PROCESSOR_2094_Z9_109,
  38   PROCESSOR_2097_Z10,
  39   PROCESSOR_max
  40 };
  41
  42 /* Optional architectural facilities supported by the processor.  */
  43
  44 enum processor_flags
  45 {
  46   PF_IEEE_FLOAT = 1,
  47   PF_ZARCH = 2,
  48   PF_LONG_DISPLACEMENT = 4,
  49   PF_EXTIMM = 8,
  50   PF_DFP = 16,
  51   PF_Z10 = 32
  52 };
  53
  54 extern enum processor_type s390_tune;
  55 extern int s390_tune_flags;
  56
  57 /* This is necessary to avoid a warning about comparing different enum
  58    types.  */
  59 #define s390_tune_attr ((enum attr_cpu)s390_tune)
  60
  61 extern enum processor_type s390_arch;
  62 extern int s390_arch_flags;
  63
  64 /* These flags indicate that the generated code should run on a cpu
  65    providing the respective hardware facility regardless of the
  66    current cpu mode (ESA or z/Architecture).  */
  67
  68 #define TARGET_CPU_IEEE_FLOAT \
  69         (s390_arch_flags & PF_IEEE_FLOAT)
  70 #define TARGET_CPU_ZARCH \
  71         (s390_arch_flags & PF_ZARCH)
  72 #define TARGET_CPU_LONG_DISPLACEMENT \
  73         (s390_arch_flags & PF_LONG_DISPLACEMENT)
  74 #define TARGET_CPU_EXTIMM \
  75         (s390_arch_flags & PF_EXTIMM)
  76 #define TARGET_CPU_DFP \
  77         (s390_arch_flags & PF_DFP)
  78 #define TARGET_CPU_Z10 \
  79         (s390_arch_flags & PF_Z10)
  80
  81 /* These flags indicate that the generated code should run on a cpu
  82    providing the respective hardware facility when run in
  83    z/Architecture mode.  */
  84
  85 #define TARGET_LONG_DISPLACEMENT \
  86        (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
  87 #define TARGET_EXTIMM \
  88        (TARGET_ZARCH && TARGET_CPU_EXTIMM)
  89 #define TARGET_DFP \
  90        (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
  91 #define TARGET_Z10 \
  92        (TARGET_ZARCH && TARGET_CPU_Z10)
  93
  94 /* Run-time target specification.  */
  95
  96 /* Defaults for option flags defined only on some subtargets.  */
  97 #ifndef TARGET_TPF_PROFILING
  98 #define TARGET_TPF_PROFILING 0
  99 #endif
 100
 101 /* This will be overridden by OS headers.  */
 102 #define TARGET_TPF 0
 103
 104 /* Target CPU builtins.  */
 105 #define TARGET_CPU_CPP_BUILTINS()                       \
 106   do                                                    \
 107     {                                                   \
 108       builtin_assert ("cpu=s390");                      \
 109       builtin_assert ("machine=s390");                  \
 110       builtin_define ("__s390__");                      \
 111       if (TARGET_ZARCH)                                 \
 112         builtin_define ("__zarch__");                   \
 113       if (TARGET_64BIT)                                 \
 114         builtin_define ("__s390x__");                   \
 115       if (TARGET_LONG_DOUBLE_128)                       \
 116         builtin_define ("__LONG_DOUBLE_128__");         \
 117     }                                                   \
 118   while (0)
 119
 120 #ifdef DEFAULT_TARGET_64BIT
 121 #define TARGET_DEFAULT             (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP)
 122 #else
 123 #define TARGET_DEFAULT             0
 124 #endif
 125
 126 /* Support for configure-time defaults.  */
 127 #define OPTION_DEFAULT_SPECS                                    \
 128   { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" },                 \
 129   { "arch", "%{!march=*:-march=%(VALUE)}" },                    \
 130   { "tune", "%{!mtune=*:-mtune=%(VALUE)}" }
 131
 132 /* Defaulting rules.  */
 133 #ifdef DEFAULT_TARGET_64BIT
 134 #define DRIVER_SELF_SPECS                                       \
 135   "%{!m31:%{!m64:-m64}}",                                       \
 136   "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",             \
 137   "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
 138 #else
 139 #define DRIVER_SELF_SPECS                                       \
 140   "%{!m31:%{!m64:-m31}}",                                       \
 141   "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",             \
 142   "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
 143 #endif
 144
 145 /* Target version string.  Overridden by the OS header.  */
 146 #ifdef DEFAULT_TARGET_64BIT
 147 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
 148 #else
 149 #define TARGET_VERSION fprintf (stderr, " (S/390)");
 150 #endif
 151
 152 /* Hook to override options.  */
 153 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE)
 154
 155 /* Frame pointer is not used for debugging.  */
 156 #define CAN_DEBUG_WITHOUT_FP
 157
 158 /* Constants needed to control the TEST DATA CLASS (TDC) instruction.  */
 159 #define S390_TDC_POSITIVE_ZERO                     (1 << 11)
 160 #define S390_TDC_NEGATIVE_ZERO                     (1 << 10)
 161 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER    (1 << 9)
 162 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER    (1 << 8)
 163 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER  (1 << 7)
 164 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER  (1 << 6)
 165 #define S390_TDC_POSITIVE_INFINITY                 (1 << 5)
 166 #define S390_TDC_NEGATIVE_INFINITY                 (1 << 4)
 167 #define S390_TDC_POSITIVE_QUIET_NAN                (1 << 3)
 168 #define S390_TDC_NEGATIVE_QUIET_NAN                (1 << 2)
 169 #define S390_TDC_POSITIVE_SIGNALING_NAN            (1 << 1)
 170 #define S390_TDC_NEGATIVE_SIGNALING_NAN            (1 << 0)
 171
 172 /* The following values are different for DFP.  */
 173 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9)
 174 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8)
 175 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER   (1 << 7)
 176 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER   (1 << 6)
 177
 178 /* For signbit, the BFP-DFP-difference makes no difference. */
 179 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
 180                           | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
 181                           | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
 182                           | S390_TDC_NEGATIVE_INFINITY \
 183                           | S390_TDC_NEGATIVE_QUIET_NAN \
 184                           | S390_TDC_NEGATIVE_SIGNALING_NAN )
 185
 186 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
 187                           | S390_TDC_NEGATIVE_INFINITY )
 188
 189 /* Target machine storage layout.  */
 190
 191 /* Everything is big-endian.  */
 192 #define BITS_BIG_ENDIAN 1
 193 #define BYTES_BIG_ENDIAN 1
 194 #define WORDS_BIG_ENDIAN 1
 195
 196 #define STACK_SIZE_MODE (Pmode)
 197
 198 #ifndef IN_LIBGCC2
 199
 200 /* Width of a word, in units (bytes).  */
 201   #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4)
 202
 203 /* Width of a pointer.  To be used instead of UNITS_PER_WORD in
 204    ABI-relevant contexts.  This always matches
 205    GET_MODE_SIZE (Pmode).  */
 206   #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4)
 207   #define MIN_UNITS_PER_WORD 4
 208   #define MAX_BITS_PER_WORD 64
 209 #else
 210
 211   /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether
 212      the library should export TImode functions or not.  Thus, we have
 213      to redefine UNITS_PER_WORD depending on __s390x__ for libgcc.  */
 214   #ifdef __s390x__
 215     #define UNITS_PER_WORD 8
 216   #else
 217     #define UNITS_PER_WORD 4
 218   #endif
 219 #endif
 220
 221 /* Width of a pointer, in bits.  */
 222 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
 223
 224 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 225 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
 226
 227 /* Boundary (in *bits*) on which stack pointer should be aligned.  */
 228 #define STACK_BOUNDARY 64
 229
 230 /* Allocation boundary (in *bits*) for the code of a function.  */
 231 #define FUNCTION_BOUNDARY 32
 232
 233 /* There is no point aligning anything to a rounder boundary than this.  */
 234 #define BIGGEST_ALIGNMENT 64
 235
 236 /* Alignment of field after `int : 0' in a structure.  */
 237 #define EMPTY_FIELD_BOUNDARY 32
 238
 239 /* Alignment on even addresses for LARL instruction.  */
 240 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
 241 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
 242
 243 /* Alignment is not required by the hardware.  */
 244 #define STRICT_ALIGNMENT 0
 245
 246 /* Mode of stack savearea.
 247    FUNCTION is VOIDmode because calling convention maintains SP.
 248    BLOCK needs Pmode for SP.
 249    NONLOCAL needs twice Pmode to maintain both backchain and SP.  */
 250 #define STACK_SAVEAREA_MODE(LEVEL)      \
 251   (LEVEL == SAVE_FUNCTION ? VOIDmode    \
 252   : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
 253
 254
 255 /* Type layout.  */
 256
 257 /* Sizes in bits of the source language data types.  */
 258 #define SHORT_TYPE_SIZE 16
 259 #define INT_TYPE_SIZE 32
 260 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
 261 #define LONG_LONG_TYPE_SIZE 64
 262 #define FLOAT_TYPE_SIZE 32
 263 #define DOUBLE_TYPE_SIZE 64
 264 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
 265
 266 /* Define this to set long double type size to use in libgcc2.c, which can
 267    not depend on target_flags.  */
 268 #ifdef __LONG_DOUBLE_128__
 269 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
 270 #else
 271 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
 272 #endif
 273
 274 /* Work around target_flags dependency in ada/targtyps.c.  */
 275 #define WIDEST_HARDWARE_FP_SIZE 64
 276
 277 /* We use "unsigned char" as default.  */
 278 #define DEFAULT_SIGNED_CHAR 0
 279
 280
 281 /* Register usage.  */
 282
 283 /* We have 16 general purpose registers (registers 0-15),
 284    and 16 floating point registers (registers 16-31).
 285    (On non-IEEE machines, we have only 4 fp registers.)
 286
 287    Amongst the general purpose registers, some are used
 288    for specific purposes:
 289    GPR 11: Hard frame pointer (if needed)
 290    GPR 12: Global offset table pointer (if needed)
 291    GPR 13: Literal pool base register
 292    GPR 14: Return address register
 293    GPR 15: Stack pointer
 294
 295    Registers 32-35 are 'fake' hard registers that do not
 296    correspond to actual hardware:
 297    Reg 32: Argument pointer
 298    Reg 33: Condition code
 299    Reg 34: Frame pointer
 300    Reg 35: Return address pointer
 301
 302    Registers 36 and 37 are mapped to access registers
 303    0 and 1, used to implement thread-local storage.  */
 304
 305 #define FIRST_PSEUDO_REGISTER 38
 306
 307 /* Standard register usage.  */
 308 #define GENERAL_REGNO_P(N)      ((int)(N) >= 0 && (N) < 16)
 309 #define ADDR_REGNO_P(N)         ((N) >= 1 && (N) < 16)
 310 #define FP_REGNO_P(N)           ((N) >= 16 && (N) < 32)
 311 #define CC_REGNO_P(N)           ((N) == 33)
 312 #define FRAME_REGNO_P(N)        ((N) == 32 || (N) == 34 || (N) == 35)
 313 #define ACCESS_REGNO_P(N)       ((N) == 36 || (N) == 37)
 314
 315 #define GENERAL_REG_P(X)        (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
 316 #define ADDR_REG_P(X)           (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
 317 #define FP_REG_P(X)             (REG_P (X) && FP_REGNO_P (REGNO (X)))
 318 #define CC_REG_P(X)             (REG_P (X) && CC_REGNO_P (REGNO (X)))
 319 #define FRAME_REG_P(X)          (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
 320 #define ACCESS_REG_P(X)         (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
 321
 322 /* Set up fixed registers and calling convention:
 323
 324    GPRs 0-5 are always call-clobbered,
 325    GPRs 6-15 are always call-saved.
 326    GPR 12 is fixed if used as GOT pointer.
 327    GPR 13 is always fixed (as literal pool pointer).
 328    GPR 14 is always fixed on S/390 machines (as return address).
 329    GPR 15 is always fixed (as stack pointer).
 330    The 'fake' hard registers are call-clobbered and fixed.
 331    The access registers are call-saved and fixed.
 332
 333    On 31-bit, FPRs 18-19 are call-clobbered;
 334    on 64-bit, FPRs 24-31 are call-clobbered.
 335    The remaining FPRs are call-saved.  */
 336
 337 #define FIXED_REGISTERS                         \
 338 { 0, 0, 0, 0,                                   \
 339   0, 0, 0, 0,                                   \
 340   0, 0, 0, 0,                                   \
 341   0, 1, 1, 1,                                   \
 342   0, 0, 0, 0,                                   \
 343   0, 0, 0, 0,                                   \
 344   0, 0, 0, 0,                                   \
 345   0, 0, 0, 0,                                   \
 346   1, 1, 1, 1,                                   \
 347   1, 1 }
 348
 349 #define CALL_USED_REGISTERS                     \
 350 { 1, 1, 1, 1,                                   \
 351   1, 1, 0, 0,                                   \
 352   0, 0, 0, 0,                                   \
 353   0, 1, 1, 1,                                   \
 354   1, 1, 1, 1,                                   \
 355   1, 1, 1, 1,                                   \
 356   1, 1, 1, 1,                                   \
 357   1, 1, 1, 1,                                   \
 358   1, 1, 1, 1,                                   \
 359   1, 1 }
 360
 361 #define CALL_REALLY_USED_REGISTERS              \
 362 { 1, 1, 1, 1,                                   \
 363   1, 1, 0, 0,                                   \
 364   0, 0, 0, 0,                                   \
 365   0, 0, 0, 0,                                   \
 366   1, 1, 1, 1,                                   \
 367   1, 1, 1, 1,                                   \
 368   1, 1, 1, 1,                                   \
 369   1, 1, 1, 1,                                   \
 370   1, 1, 1, 1,                                   \
 371   0, 0 }
 372
 373 #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage ()
 374
 375 /* Preferred register allocation order.  */
 376 #define REG_ALLOC_ORDER                                         \
 377 {  1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13,            \
 378    16, 17, 18, 19, 20, 21, 22, 23,                              \
 379    24, 25, 26, 27, 28, 29, 30, 31,                              \
 380    15, 32, 33, 34, 35, 36, 37 }
 381
 382
 383 /* Fitting values into registers.  */
 384
 385 /* Integer modes <= word size fit into any GPR.
 386    Integer modes > word size fit into successive GPRs, starting with
 387    an even-numbered register.
 388    SImode and DImode fit into FPRs as well.
 389
 390    Floating point modes <= word size fit into any FPR or GPR.
 391    Floating point modes > word size (i.e. DFmode on 32-bit) fit
 392    into any FPR, or an even-odd GPR pair.
 393    TFmode fits only into an even-odd FPR pair.
 394
 395    Complex floating point modes fit either into two FPRs, or into
 396    successive GPRs (again starting with an even number).
 397    TCmode fits only into two successive even-odd FPR pairs.
 398
 399    Condition code modes fit only into the CC register.  */
 400
 401 /* Because all registers in a class have the same size HARD_REGNO_NREGS
 402    is equivalent to CLASS_MAX_NREGS.  */
 403 #define HARD_REGNO_NREGS(REGNO, MODE)                           \
 404   s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE))
 405
 406 #define HARD_REGNO_MODE_OK(REGNO, MODE)         \
 407   s390_hard_regno_mode_ok ((REGNO), (MODE))
 408
 409 #define HARD_REGNO_RENAME_OK(FROM, TO)          \
 410   s390_hard_regno_rename_ok (FROM, TO)
 411
 412 #define MODES_TIEABLE_P(MODE1, MODE2)           \
 413    (((MODE1) == SFmode || (MODE1) == DFmode)    \
 414    == ((MODE2) == SFmode || (MODE2) == DFmode))
 415
 416 /* When generating code that runs in z/Architecture mode,
 417    but conforms to the 31-bit ABI, GPRs can hold 8 bytes;
 418    the ABI guarantees only that the lower 4 bytes are
 419    saved across calls, however.  */
 420 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE)             \
 421   (!TARGET_64BIT && TARGET_ZARCH                                \
 422    && GET_MODE_SIZE (MODE) > 4                                  \
 423    && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32))
 424
 425 /* Maximum number of registers to represent a value of mode MODE
 426    in a register of class CLASS.  */
 427 #define CLASS_MAX_NREGS(CLASS, MODE)                                    \
 428   s390_class_max_nregs ((CLASS), (MODE))
 429
 430 /* If a 4-byte value is loaded into a FPR, it is placed into the
 431    *upper* half of the register, not the lower.  Therefore, we
 432    cannot use SUBREGs to switch between modes in FP registers.
 433    Likewise for access registers, since they have only half the
 434    word size on 64-bit.  */
 435 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)                       \
 436   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)                           \
 437    ? ((reg_classes_intersect_p (FP_REGS, CLASS)                         \
 438        && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8))         \
 439       || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0)
 440
 441 /* Register classes.  */
 442
 443 /* We use the following register classes:
 444    GENERAL_REGS     All general purpose registers
 445    ADDR_REGS        All general purpose registers except %r0
 446                     (These registers can be used in address generation)
 447    FP_REGS          All floating point registers
 448    CC_REGS          The condition code register
 449    ACCESS_REGS      The access registers
 450
 451    GENERAL_FP_REGS  Union of GENERAL_REGS and FP_REGS
 452    ADDR_FP_REGS     Union of ADDR_REGS and FP_REGS
 453    GENERAL_CC_REGS  Union of GENERAL_REGS and CC_REGS
 454    ADDR_CC_REGS     Union of ADDR_REGS and CC_REGS
 455
 456    NO_REGS          No registers
 457    ALL_REGS         All registers
 458
 459    Note that the 'fake' frame pointer and argument pointer registers
 460    are included amongst the address registers here.  */
 461
 462 enum reg_class
 463 {
 464   NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
 465   ADDR_CC_REGS, GENERAL_CC_REGS,
 466   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
 467   ALL_REGS, LIM_REG_CLASSES
 468 };
 469 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 470
 471 #define REG_CLASS_NAMES                                                 \
 472 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS",     \
 473   "ADDR_CC_REGS", "GENERAL_CC_REGS",                                    \
 474   "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
 475
 476 /* Class -> register mapping.  */
 477 #define REG_CLASS_CONTENTS \
 478 {                                                       \
 479   { 0x00000000, 0x00000000 },   /* NO_REGS */           \
 480   { 0x00000000, 0x00000002 },   /* CC_REGS */           \
 481   { 0x0000fffe, 0x0000000d },   /* ADDR_REGS */         \
 482   { 0x0000ffff, 0x0000000d },   /* GENERAL_REGS */      \
 483   { 0x00000000, 0x00000030 },   /* ACCESS_REGS */       \
 484   { 0x0000fffe, 0x0000000f },   /* ADDR_CC_REGS */      \
 485   { 0x0000ffff, 0x0000000f },   /* GENERAL_CC_REGS */   \
 486   { 0xffff0000, 0x00000000 },   /* FP_REGS */           \
 487   { 0xfffffffe, 0x0000000d },   /* ADDR_FP_REGS */      \
 488   { 0xffffffff, 0x0000000d },   /* GENERAL_FP_REGS */   \
 489   { 0xffffffff, 0x0000003f },   /* ALL_REGS */          \
 490 }
 491
 492 /* The following macro defines cover classes for Integrated Register
 493    Allocator.  Cover classes is a set of non-intersected register
 494    classes covering all hard registers used for register allocation
 495    purpose.  Any move between two registers of a cover class should be
 496    cheaper than load or store of the registers.  The macro value is
 497    array of register classes with LIM_REG_CLASSES used as the end
 498    marker.  */
 499
 500 #define IRA_COVER_CLASSES                                                    \
 501 {                                                                            \
 502   GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES               \
 503 }
 504
 505 /* In some case register allocation order is not enough for IRA to
 506    generate a good code.  The following macro (if defined) increases
 507    cost of REGNO for a pseudo approximately by pseudo usage frequency
 508    multiplied by the macro value.
 509
 510    We avoid usage of BASE_REGNUM by nonzero macro value because the
 511    reload can decide not to use the hard register because some
 512    constant was forced to be in memory.  */
 513 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno)       \
 514   (regno == BASE_REGNUM ? 0.0 : 0.5)
 515
 516 /* Register -> class mapping.  */
 517 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
 518 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
 519
 520 /* ADDR_REGS can be used as base or index register.  */
 521 #define INDEX_REG_CLASS ADDR_REGS
 522 #define BASE_REG_CLASS ADDR_REGS
 523
 524 /* Check whether REGNO is a hard register of the suitable class
 525    or a pseudo register currently allocated to one such.  */
 526 #define REGNO_OK_FOR_INDEX_P(REGNO)                                     \
 527     (((REGNO) < FIRST_PSEUDO_REGISTER                                   \
 528       && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS)                        \
 529      || ADDR_REGNO_P (reg_renumber[REGNO]))
 530 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
 531
 532
 533 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
 534    return the class of reg to actually use.  */
 535 #define PREFERRED_RELOAD_CLASS(X, CLASS)        \
 536   s390_preferred_reload_class ((X), (CLASS))
 537
 538 /* We need secondary memory to move data between GPRs and FPRs.  With
 539    DFP the ldgr lgdr instructions are available.  But these
 540    instructions do not handle GPR pairs so it is not possible for 31
 541    bit.  */
 542 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
 543  ((CLASS1) != (CLASS2)                                \
 544   && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)     \
 545   && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8))
 546
 547 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
 548    because the movsi and movsf patterns don't handle r/f moves.  */
 549 #define SECONDARY_MEMORY_NEEDED_MODE(MODE)              \
 550  (GET_MODE_BITSIZE (MODE) < 32                          \
 551   ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)        \
 552   : MODE)
 553
 554
 555 /* Stack layout and calling conventions.  */
 556
 557 /* Our stack grows from higher to lower addresses.  However, local variables
 558    are accessed by positive offsets, and function arguments are stored at
 559    increasing addresses.  */
 560 #define STACK_GROWS_DOWNWARD
 561 #define FRAME_GROWS_DOWNWARD 1
 562 /* #undef ARGS_GROW_DOWNWARD */
 563
 564 /* The basic stack layout looks like this: the stack pointer points
 565    to the register save area for called functions.  Above that area
 566    is the location to place outgoing arguments.  Above those follow
 567    dynamic allocations (alloca), and finally the local variables.  */
 568
 569 /* Offset from stack-pointer to first location of outgoing args.  */
 570 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
 571
 572 /* Offset within stack frame to start allocating local variables at.  */
 573 #define STARTING_FRAME_OFFSET 0
 574
 575 /* Offset from the stack pointer register to an item dynamically
 576    allocated on the stack, e.g., by `alloca'.  */
 577 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
 578   (STACK_POINTER_OFFSET + crtl->outgoing_args_size)
 579
 580 /* Offset of first parameter from the argument pointer register value.
 581    We have a fake argument pointer register that points directly to
 582    the argument area.  */
 583 #define FIRST_PARM_OFFSET(FNDECL) 0
 584
 585 /* Defining this macro makes __builtin_frame_address(0) and
 586    __builtin_return_address(0) work with -fomit-frame-pointer.  */
 587 #define INITIAL_FRAME_ADDRESS_RTX                                             \
 588   (plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
 589
 590 /* The return address of the current frame is retrieved
 591    from the initial value of register RETURN_REGNUM.
 592    For frames farther back, we use the stack slot where
 593    the corresponding RETURN_REGNUM register was saved.  */
 594 #define DYNAMIC_CHAIN_ADDRESS(FRAME)                                          \
 595   (TARGET_PACKED_STACK ?                                                      \
 596    plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME))
 597
 598 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
 599    builtin_frame_address.  Otherwise arg pointer -
 600    STACK_POINTER_OFFSET would be returned for
 601    __builtin_frame_address(0) what might result in an address pointing
 602    somewhere into the middle of the local variables since the packed
 603    stack layout generally does not need all the bytes in the register
 604    save area.  */
 605 #define FRAME_ADDR_RTX(FRAME)                   \
 606   DYNAMIC_CHAIN_ADDRESS ((FRAME))
 607
 608 #define RETURN_ADDR_RTX(COUNT, FRAME)                                         \
 609   s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
 610
 611 /* In 31-bit mode, we need to mask off the high bit of return addresses.  */
 612 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
 613
 614
 615 /* Exception handling.  */
 616
 617 /* Describe calling conventions for DWARF-2 exception handling.  */
 618 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, RETURN_REGNUM)
 619 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
 620 #define DWARF_FRAME_RETURN_COLUMN  14
 621
 622 /* Describe how we implement __builtin_eh_return.  */
 623 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
 624 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
 625
 626 /* Select a format to encode pointers in exception handling data.  */
 627 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL)                          \
 628   (flag_pic                                                                 \
 629     ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
 630    : DW_EH_PE_absptr)
 631
 632 /* Register save slot alignment.  */
 633 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG)
 634
 635
 636 /* Frame registers.  */
 637
 638 #define STACK_POINTER_REGNUM 15
 639 #define FRAME_POINTER_REGNUM 34
 640 #define HARD_FRAME_POINTER_REGNUM 11
 641 #define ARG_POINTER_REGNUM 32
 642 #define RETURN_ADDRESS_POINTER_REGNUM 35
 643
 644 /* The static chain must be call-clobbered, but not used for
 645    function argument passing.  As register 1 is clobbered by
 646    the trampoline code, we only have one option.  */
 647 #define STATIC_CHAIN_REGNUM 0
 648
 649 /* Number of hardware registers that go into the DWARF-2 unwind info.
 650    To avoid ABI incompatibility, this number must not change even as
 651    'fake' hard registers are added or removed.  */
 652 #define DWARF_FRAME_REGISTERS 34
 653
 654
 655 /* Frame pointer and argument pointer elimination.  */
 656
 657 #define ELIMINABLE_REGS                                         \
 658 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },                \
 659  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },           \
 660  { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },                  \
 661  { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },             \
 662  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM },       \
 663  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },  \
 664  { BASE_REGNUM, BASE_REGNUM }}
 665
 666 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 667   (OFFSET) = s390_initial_elimination_offset ((FROM), (TO))
 668
 669
 670 /* Stack arguments.  */
 671
 672 /* We need current_function_outgoing_args to be valid.  */
 673 #define ACCUMULATE_OUTGOING_ARGS 1
 674
 675
 676 /* Register arguments.  */
 677
 678 typedef struct s390_arg_structure
 679 {
 680   int gprs;                     /* gpr so far */
 681   int fprs;                     /* fpr so far */
 682 }
 683 CUMULATIVE_ARGS;
 684
 685 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
 686   ((CUM).gprs=0, (CUM).fprs=0)
 687
 688 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)                    \
 689   s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
 690
 691 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)   \
 692   s390_function_arg (&CUM, MODE, TYPE, NAMED)
 693
 694 /* Arguments can be placed in general registers 2 to 6, or in floating
 695    point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64
 696    bit.  */
 697 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
 698   (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19)))
 699
 700
 701 /* Scalar return values.  */
 702
 703 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 704   s390_function_value ((VALTYPE), (FUNC), VOIDmode)
 705
 706 #define LIBCALL_VALUE(MODE) \
 707   s390_function_value (NULL, NULL, (MODE))
 708
 709 /* Only gpr 2 and fpr 0 are ever used as return registers.  */
 710 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
 711
 712
 713 /* Function entry and exit.  */
 714
 715 /* When returning from a function, the stack pointer does not matter.  */
 716 #define EXIT_IGNORE_STACK       1
 717
 718
 719 /* Profiling.  */
 720
 721 #define FUNCTION_PROFILER(FILE, LABELNO)                        \
 722   s390_function_profiler ((FILE), ((LABELNO)))
 723
 724 #define PROFILE_BEFORE_PROLOGUE 1
 725
 726
 727 /* Trampolines for nested functions.  */
 728
 729 #define TRAMPOLINE_SIZE         (TARGET_64BIT ? 32 : 16)
 730 #define TRAMPOLINE_ALIGNMENT    BITS_PER_WORD
 731
 732 /* Addressing modes, and classification of registers for them.  */
 733
 734 /* Recognize any constant value that is a valid address.  */
 735 #define CONSTANT_ADDRESS_P(X) 0
 736
 737 /* Maximum number of registers that can appear in a valid memory address.  */
 738 #define MAX_REGS_PER_ADDRESS 2
 739
 740 /* This definition replaces the formerly used 'm' constraint with a
 741    different constraint letter in order to avoid changing semantics of
 742    the 'm' constraint when accepting new address formats in
 743    TARGET_LEGITIMATE_ADDRESS_P.  The constraint letter defined here
 744    must not be used in insn definitions or inline assemblies.  */
 745 #define TARGET_MEM_CONSTRAINT 'e'
 746
 747 /* Try a machine-dependent way of reloading an illegitimate address
 748    operand.  If we find one, push the reload and jump to WIN.  This
 749    macro is used in only one place: `find_reloads_address' in reload.c.  */
 750 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN)      \
 751 do {                                                                    \
 752   rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE));       \
 753   if (new_rtx)                                                          \
 754     {                                                                   \
 755       (AD) = new_rtx;                                                   \
 756       goto WIN;                                                         \
 757     }                                                                   \
 758 } while (0)
 759
 760 /* Nonzero if the constant value X is a legitimate general operand.
 761    It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
 762 #define LEGITIMATE_CONSTANT_P(X) \
 763      legitimate_constant_p (X)
 764
 765 /* Helper macro for s390.c and s390.md to check for symbolic constants.  */
 766 #define SYMBOLIC_CONST(X)       \
 767 (GET_CODE (X) == SYMBOL_REF                                             \
 768  || GET_CODE (X) == LABEL_REF                                           \
 769  || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
 770
 771 #define TLS_SYMBOLIC_CONST(X)   \
 772 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X))       \
 773  || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
 774
 775
 776 /* Condition codes.  */
 777
 778 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
 779    return the mode to be used for the comparison.  */
 780 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
 781
 782 /* Canonicalize a comparison from one we don't have to one we do have.  */
 783 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
 784   s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1))
 785
 786 /* Relative costs of operations.  */
 787
 788 /* On s390, copy between fprs and gprs is expensive.  */
 789 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)                        \
 790   ((   (   reg_classes_intersect_p ((CLASS1), GENERAL_REGS)             \
 791         && reg_classes_intersect_p ((CLASS2), FP_REGS))                 \
 792     || (   reg_classes_intersect_p ((CLASS1), FP_REGS)                  \
 793         && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
 794
 795 /* A C expression for the cost of moving data of mode M between a
 796    register and memory.  A value of 2 is the default; this cost is
 797    relative to those in `REGISTER_MOVE_COST'.  */
 798 #define MEMORY_MOVE_COST(M, C, I) 1
 799
 800 /* A C expression for the cost of a branch instruction.  A value of 1
 801    is the default; other values are interpreted relative to that.  */
 802 #define BRANCH_COST(speed_p, predictable_p) 1
 803
 804 /* Nonzero if access to memory by bytes is slow and undesirable.  */
 805 #define SLOW_BYTE_ACCESS 1
 806
 807 /* An integer expression for the size in bits of the largest integer machine
 808    mode that should actually be used.  We allow pairs of registers.  */
 809 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 810
 811 /* The maximum number of bytes that a single instruction can move quickly
 812    between memory and registers or between two memory locations.  */
 813 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8)
 814 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
 815 #define MAX_MOVE_MAX 16
 816
 817 /* Determine whether to use move_by_pieces or block move insn.  */
 818 #define MOVE_BY_PIECES_P(SIZE, ALIGN)           \
 819   ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4   \
 820     || (TARGET_ZARCH && (SIZE) == 8) )
 821
 822 /* Determine whether to use clear_by_pieces or block clear insn.  */
 823 #define CLEAR_BY_PIECES_P(SIZE, ALIGN)          \
 824   ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4   \
 825     || (TARGET_ZARCH && (SIZE) == 8) )
 826
 827 /* This macro is used to determine whether store_by_pieces should be
 828    called to "memcpy" storage when the source is a constant string.  */
 829 #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN)
 830
 831 /* Likewise to decide whether to "memset" storage with byte values
 832    other than zero.  */
 833 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN)
 834
 835 /* Don't perform CSE on function addresses.  */
 836 #define NO_FUNCTION_CSE
 837
 838 /* This value is used in tree-sra to decide whether it might benefical
 839    to split a struct move into several word-size moves.  For S/390
 840    only small values make sense here since struct moves are relatively
 841    cheap thanks to mvc so the small default value choosen for archs
 842    with memmove patterns should be ok.  But this value is multiplied
 843    in tree-sra with UNITS_PER_WORD to make a decision so we adjust it
 844    here to compensate for that factor since mvc costs exactly the same
 845    on 31 and 64 bit.  */
 846 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4)
 847
 848
 849 /* Sections.  */
 850
 851 /* Output before read-only data.  */
 852 #define TEXT_SECTION_ASM_OP ".text"
 853
 854 /* Output before writable (initialized) data.  */
 855 #define DATA_SECTION_ASM_OP ".data"
 856
 857 /* Output before writable (uninitialized) data.  */
 858 #define BSS_SECTION_ASM_OP ".bss"
 859
 860 /* S/390 constant pool breaks the devices in crtstuff.c to control section
 861    in where code resides.  We have to write it as asm code.  */
 862 #ifndef __s390x__
 863 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
 864     asm (SECTION_OP "\n\
 865         bras\t%r2,1f\n\
 866 0:      .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
 867 1:      l\t%r3,0(%r2)\n\
 868         bas\t%r14,0(%r3,%r2)\n\
 869         .previous");
 870 #endif
 871
 872
 873 /* Position independent code.  */
 874
 875 extern int flag_pic;
 876
 877 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
 878
 879 #define LEGITIMATE_PIC_OPERAND_P(X)  legitimate_pic_operand_p (X)
 880
 881
 882 /* Assembler file format.  */
 883
 884 /* Character to start a comment.  */
 885 #define ASM_COMMENT_START "#"
 886
 887 /* Declare an uninitialized external linkage data object.  */
 888 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
 889   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
 890
 891 /* Globalizing directive for a label.  */
 892 #define GLOBAL_ASM_OP ".globl "
 893
 894 /* Advance the location counter to a multiple of 2**LOG bytes.  */
 895 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
 896   if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
 897
 898 /* Advance the location counter by SIZE bytes.  */
 899 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
 900   fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
 901
 902 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h.  */
 903 #define LOCAL_LABEL_PREFIX "."
 904
 905 /* How to refer to registers in assembler output.  This sequence is
 906    indexed by compiler's hard-register-number (see above).  */
 907 #define REGISTER_NAMES                                                  \
 908 { "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",        \
 909   "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",       \
 910   "%f0",  "%f2",  "%f4",  "%f6",  "%f1",  "%f3",  "%f5",  "%f7",        \
 911   "%f8",  "%f10", "%f12", "%f14", "%f9",  "%f11", "%f13", "%f15",       \
 912   "%ap",  "%cc",  "%fp",  "%rp",  "%a0",  "%a1"                         \
 913 }
 914
 915 /* Print operand X (an rtx) in assembler syntax to file FILE.  */
 916 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
 917 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
 918
 919 /* Output machine-dependent UNSPECs in address constants.  */
 920 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL)          \
 921 do {                                                    \
 922   if (!s390_output_addr_const_extra (FILE, (X)))        \
 923     goto FAIL;                                          \
 924 } while (0);
 925
 926 /* Output an element of a case-vector that is absolute.  */
 927 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)                            \
 928 do {                                                                    \
 929   char buf[32];                                                         \
 930   fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE));                \
 931   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE));                      \
 932   assemble_name ((FILE), buf);                                          \
 933   fputc ('\n', (FILE));                                                 \
 934 } while (0)
 935
 936 /* Output an element of a case-vector that is relative.  */
 937 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)                \
 938 do {                                                                    \
 939   char buf[32];                                                         \
 940   fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE));                \
 941   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE));                      \
 942   assemble_name ((FILE), buf);                                          \
 943   fputc ('-', (FILE));                                                  \
 944   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL));                        \
 945   assemble_name ((FILE), buf);                                          \
 946   fputc ('\n', (FILE));                                                 \
 947 } while (0)
 948
 949
 950 /* Miscellaneous parameters.  */
 951
 952 /* Specify the machine mode that this machine uses for the index in the
 953    tablejump instruction.  */
 954 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
 955
 956 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
 957    is done just by pretending it is already truncated.  */
 958 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1
 959
 960 /* Specify the machine mode that pointers have.
 961    After generation of rtl, the compiler makes no further distinction
 962    between pointers and any other objects of this machine mode.  */
 963 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
 964
 965 /* This is -1 for "pointer mode" extend.  See ptr_extend in s390.md.  */
 966 #define POINTERS_EXTEND_UNSIGNED -1
 967
 968 /* A function address in a call instruction is a byte address (for
 969    indexing purposes) so give the MEM rtx a byte's mode.  */
 970 #define FUNCTION_MODE QImode
 971
 972 /* Specify the value which is used when clz operand is zero.  */
 973 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
 974
 975 /* Machine-specific symbol_ref flags.  */
 976 #define SYMBOL_FLAG_ALIGN1                (SYMBOL_FLAG_MACH_DEP << 0)
 977 #define SYMBOL_REF_ALIGN1_P(X)          \
 978   ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1))
 979 #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1)
 980 #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \
 981   ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED))
 982
 983 /* Check whether integer displacement is in range.  */
 984 #define DISP_IN_RANGE(d) \
 985   (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
 986                            : ((d) >= 0 && (d) <= 4095))
 987
 988 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c.  */
 989 #define READ_CAN_USE_WRITE_PREFETCH 1
 990 #endif