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[gcc.git] / gcc / config / s390 / s390.h
1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 02110-1301, USA. */
23
24 #ifndef _S390_H
25 #define _S390_H
26
27 /* Override the __fixdfdi etc. routines when building libgcc2.
28 ??? This should be done in a cleaner way ... */
29 #if defined (IN_LIBGCC2) && !defined (__s390x__)
30 #include <config/s390/fixdfdi.h>
31 #endif
32
33 /* Which processor to generate code or schedule for. The cpu attribute
34 defines a list that mirrors this list, so changes to s390.md must be
35 made at the same time. */
36
37 enum processor_type
38 {
39 PROCESSOR_9672_G5,
40 PROCESSOR_9672_G6,
41 PROCESSOR_2064_Z900,
42 PROCESSOR_2084_Z990,
43 PROCESSOR_2094_Z9_109,
44 PROCESSOR_max
45 };
46
47 /* Optional architectural facilities supported by the processor. */
48
49 enum processor_flags
50 {
51 PF_IEEE_FLOAT = 1,
52 PF_ZARCH = 2,
53 PF_LONG_DISPLACEMENT = 4,
54 PF_EXTIMM = 8
55 };
56
57 extern enum processor_type s390_tune;
58 extern enum processor_flags s390_tune_flags;
59
60 extern enum processor_type s390_arch;
61 extern enum processor_flags s390_arch_flags;
62
63 #define TARGET_CPU_IEEE_FLOAT \
64 (s390_arch_flags & PF_IEEE_FLOAT)
65 #define TARGET_CPU_ZARCH \
66 (s390_arch_flags & PF_ZARCH)
67 #define TARGET_CPU_LONG_DISPLACEMENT \
68 (s390_arch_flags & PF_LONG_DISPLACEMENT)
69 #define TARGET_CPU_EXTIMM \
70 (s390_arch_flags & PF_EXTIMM)
71
72 #define TARGET_LONG_DISPLACEMENT \
73 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
74 #define TARGET_EXTIMM \
75 (TARGET_ZARCH && TARGET_CPU_EXTIMM)
76
77 /* Run-time target specification. */
78
79 /* Defaults for option flags defined only on some subtargets. */
80 #ifndef TARGET_TPF_PROFILING
81 #define TARGET_TPF_PROFILING 0
82 #endif
83
84 /* This will be overridden by OS headers. */
85 #define TARGET_TPF 0
86
87 /* Target CPU builtins. */
88 #define TARGET_CPU_CPP_BUILTINS() \
89 do \
90 { \
91 builtin_assert ("cpu=s390"); \
92 builtin_assert ("machine=s390"); \
93 builtin_define ("__s390__"); \
94 if (TARGET_64BIT) \
95 builtin_define ("__s390x__"); \
96 if (TARGET_LONG_DOUBLE_128) \
97 builtin_define ("__LONG_DOUBLE_128__"); \
98 } \
99 while (0)
100
101 /* ??? Once this actually works, it could be made a runtime option. */
102 #define TARGET_IBM_FLOAT 0
103 #define TARGET_IEEE_FLOAT 1
104
105 #ifdef DEFAULT_TARGET_64BIT
106 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_FLOAT)
107 #else
108 #define TARGET_DEFAULT MASK_HARD_FLOAT
109 #endif
110
111 /* Support for configure-time defaults. */
112 #define OPTION_DEFAULT_SPECS \
113 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \
114 { "arch", "%{!march=*:-march=%(VALUE)}" }, \
115 { "tune", "%{!mtune=*:-mtune=%(VALUE)}" }
116
117 /* Defaulting rules. */
118 #ifdef DEFAULT_TARGET_64BIT
119 #define DRIVER_SELF_SPECS \
120 "%{!m31:%{!m64:-m64}}", \
121 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \
122 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
123 #else
124 #define DRIVER_SELF_SPECS \
125 "%{!m31:%{!m64:-m31}}", \
126 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \
127 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
128 #endif
129
130 /* Target version string. Overridden by the OS header. */
131 #ifdef DEFAULT_TARGET_64BIT
132 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
133 #else
134 #define TARGET_VERSION fprintf (stderr, " (S/390)");
135 #endif
136
137 /* Hooks to override options. */
138 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE)
139 #define OVERRIDE_OPTIONS override_options ()
140
141 /* Frame pointer is not used for debugging. */
142 #define CAN_DEBUG_WITHOUT_FP
143
144
145 /* In libgcc2, determine target settings as compile-time constants. */
146 #ifdef IN_LIBGCC2
147 #undef TARGET_64BIT
148 #ifdef __s390x__
149 #define TARGET_64BIT 1
150 #else
151 #define TARGET_64BIT 0
152 #endif
153 #endif
154
155
156 /* Target machine storage layout. */
157
158 /* Everything is big-endian. */
159 #define BITS_BIG_ENDIAN 1
160 #define BYTES_BIG_ENDIAN 1
161 #define WORDS_BIG_ENDIAN 1
162
163 /* Width of a word, in units (bytes). */
164 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
165 #ifndef IN_LIBGCC2
166 #define MIN_UNITS_PER_WORD 4
167 #endif
168 #define MAX_BITS_PER_WORD 64
169
170 /* Function arguments and return values are promoted to word size. */
171 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
172 if (INTEGRAL_MODE_P (MODE) && \
173 GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \
174 (MODE) = Pmode; \
175 }
176
177 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
178 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
179
180 /* Boundary (in *bits*) on which stack pointer should be aligned. */
181 #define STACK_BOUNDARY 64
182
183 /* Allocation boundary (in *bits*) for the code of a function. */
184 #define FUNCTION_BOUNDARY 32
185
186 /* There is no point aligning anything to a rounder boundary than this. */
187 #define BIGGEST_ALIGNMENT 64
188
189 /* Alignment of field after `int : 0' in a structure. */
190 #define EMPTY_FIELD_BOUNDARY 32
191
192 /* Alignment on even addresses for LARL instruction. */
193 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
194 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
195
196 /* Alignment is not required by the hardware. */
197 #define STRICT_ALIGNMENT 0
198
199 /* Mode of stack savearea.
200 FUNCTION is VOIDmode because calling convention maintains SP.
201 BLOCK needs Pmode for SP.
202 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
203 #define STACK_SAVEAREA_MODE(LEVEL) \
204 (LEVEL == SAVE_FUNCTION ? VOIDmode \
205 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
206
207 /* Define target floating point format. */
208 #define TARGET_FLOAT_FORMAT \
209 (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT)
210
211
212 /* Type layout. */
213
214 /* Sizes in bits of the source language data types. */
215 #define SHORT_TYPE_SIZE 16
216 #define INT_TYPE_SIZE 32
217 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
218 #define LONG_LONG_TYPE_SIZE 64
219 #define FLOAT_TYPE_SIZE 32
220 #define DOUBLE_TYPE_SIZE 64
221 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
222
223 /* Define this to set long double type size to use in libgcc2.c, which can
224 not depend on target_flags. */
225 #ifdef __LONG_DOUBLE_128__
226 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
227 #else
228 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
229 #endif
230
231 /* Work around target_flags dependency in ada/targtyps.c. */
232 #define WIDEST_HARDWARE_FP_SIZE 64
233
234 /* We use "unsigned char" as default. */
235 #define DEFAULT_SIGNED_CHAR 0
236
237
238 /* Register usage. */
239
240 /* We have 16 general purpose registers (registers 0-15),
241 and 16 floating point registers (registers 16-31).
242 (On non-IEEE machines, we have only 4 fp registers.)
243
244 Amongst the general purpose registers, some are used
245 for specific purposes:
246 GPR 11: Hard frame pointer (if needed)
247 GPR 12: Global offset table pointer (if needed)
248 GPR 13: Literal pool base register
249 GPR 14: Return address register
250 GPR 15: Stack pointer
251
252 Registers 32-35 are 'fake' hard registers that do not
253 correspond to actual hardware:
254 Reg 32: Argument pointer
255 Reg 33: Condition code
256 Reg 34: Frame pointer
257 Reg 35: Return address pointer
258
259 Registers 36 and 37 are mapped to access registers
260 0 and 1, used to implement thread-local storage. */
261
262 #define FIRST_PSEUDO_REGISTER 38
263
264 /* Standard register usage. */
265 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
266 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
267 #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
268 #define CC_REGNO_P(N) ((N) == 33)
269 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35)
270 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37)
271
272 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
273 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
274 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
275 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
276 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
277 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
278
279 /* Set up fixed registers and calling convention:
280
281 GPRs 0-5 are always call-clobbered,
282 GPRs 6-15 are always call-saved.
283 GPR 12 is fixed if used as GOT pointer.
284 GPR 13 is always fixed (as literal pool pointer).
285 GPR 14 is always fixed on S/390 machines (as return address).
286 GPR 15 is always fixed (as stack pointer).
287 The 'fake' hard registers are call-clobbered and fixed.
288 The access registers are call-saved and fixed.
289
290 On 31-bit, FPRs 18-19 are call-clobbered;
291 on 64-bit, FPRs 24-31 are call-clobbered.
292 The remaining FPRs are call-saved. */
293
294 #define FIXED_REGISTERS \
295 { 0, 0, 0, 0, \
296 0, 0, 0, 0, \
297 0, 0, 0, 0, \
298 0, 1, 1, 1, \
299 0, 0, 0, 0, \
300 0, 0, 0, 0, \
301 0, 0, 0, 0, \
302 0, 0, 0, 0, \
303 1, 1, 1, 1, \
304 1, 1 }
305
306 #define CALL_USED_REGISTERS \
307 { 1, 1, 1, 1, \
308 1, 1, 0, 0, \
309 0, 0, 0, 0, \
310 0, 1, 1, 1, \
311 1, 1, 1, 1, \
312 1, 1, 1, 1, \
313 1, 1, 1, 1, \
314 1, 1, 1, 1, \
315 1, 1, 1, 1, \
316 1, 1 }
317
318 #define CALL_REALLY_USED_REGISTERS \
319 { 1, 1, 1, 1, \
320 1, 1, 0, 0, \
321 0, 0, 0, 0, \
322 0, 0, 0, 0, \
323 1, 1, 1, 1, \
324 1, 1, 1, 1, \
325 1, 1, 1, 1, \
326 1, 1, 1, 1, \
327 1, 1, 1, 1, \
328 0, 0 }
329
330 #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage ()
331
332 /* Preferred register allocation order. */
333 #define REG_ALLOC_ORDER \
334 { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \
335 16, 17, 18, 19, 20, 21, 22, 23, \
336 24, 25, 26, 27, 28, 29, 30, 31, \
337 15, 32, 33, 34, 35, 36, 37 }
338
339
340 /* Fitting values into registers. */
341
342 /* Integer modes <= word size fit into any GPR.
343 Integer modes > word size fit into successive GPRs, starting with
344 an even-numbered register.
345 SImode and DImode fit into FPRs as well.
346
347 Floating point modes <= word size fit into any FPR or GPR.
348 Floating point modes > word size (i.e. DFmode on 32-bit) fit
349 into any FPR, or an even-odd GPR pair.
350 TFmode fits only into an even-odd FPR pair.
351
352 Complex floating point modes fit either into two FPRs, or into
353 successive GPRs (again starting with an even number).
354 TCmode fits only into two successive even-odd FPR pairs.
355
356 Condition code modes fit only into the CC register. */
357
358 /* Because all registers in a class have the same size HARD_REGNO_NREGS
359 is equivalent to CLASS_MAX_NREGS. */
360 #define HARD_REGNO_NREGS(REGNO, MODE) \
361 s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE))
362
363 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
364 s390_hard_regno_mode_ok ((REGNO), (MODE))
365
366 #define HARD_REGNO_RENAME_OK(FROM, TO) \
367 s390_hard_regno_rename_ok (FROM, TO)
368
369 #define MODES_TIEABLE_P(MODE1, MODE2) \
370 (((MODE1) == SFmode || (MODE1) == DFmode) \
371 == ((MODE2) == SFmode || (MODE2) == DFmode))
372
373 /* Maximum number of registers to represent a value of mode MODE
374 in a register of class CLASS. */
375 #define CLASS_MAX_NREGS(CLASS, MODE) \
376 s390_class_max_nregs ((CLASS), (MODE))
377
378 /* If a 4-byte value is loaded into a FPR, it is placed into the
379 *upper* half of the register, not the lower. Therefore, we
380 cannot use SUBREGs to switch between modes in FP registers.
381 Likewise for access registers, since they have only half the
382 word size on 64-bit. */
383 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
384 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
385 ? ((reg_classes_intersect_p (FP_REGS, CLASS) \
386 && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \
387 || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0)
388
389 /* Register classes. */
390
391 /* We use the following register classes:
392 GENERAL_REGS All general purpose registers
393 ADDR_REGS All general purpose registers except %r0
394 (These registers can be used in address generation)
395 FP_REGS All floating point registers
396 CC_REGS The condition code register
397 ACCESS_REGS The access registers
398
399 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
400 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
401 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS
402 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS
403
404 NO_REGS No registers
405 ALL_REGS All registers
406
407 Note that the 'fake' frame pointer and argument pointer registers
408 are included amongst the address registers here. */
409
410 enum reg_class
411 {
412 NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
413 ADDR_CC_REGS, GENERAL_CC_REGS,
414 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
415 ALL_REGS, LIM_REG_CLASSES
416 };
417 #define N_REG_CLASSES (int) LIM_REG_CLASSES
418
419 #define REG_CLASS_NAMES \
420 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \
421 "ADDR_CC_REGS", "GENERAL_CC_REGS", \
422 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
423
424 /* Class -> register mapping. */
425 #define REG_CLASS_CONTENTS \
426 { \
427 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
428 { 0x00000000, 0x00000002 }, /* CC_REGS */ \
429 { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \
430 { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \
431 { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \
432 { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \
433 { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \
434 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \
435 { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \
436 { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \
437 { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \
438 }
439
440 /* Register -> class mapping. */
441 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
442 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
443
444 /* ADDR_REGS can be used as base or index register. */
445 #define INDEX_REG_CLASS ADDR_REGS
446 #define BASE_REG_CLASS ADDR_REGS
447
448 /* Check whether REGNO is a hard register of the suitable class
449 or a pseudo register currently allocated to one such. */
450 #define REGNO_OK_FOR_INDEX_P(REGNO) \
451 (((REGNO) < FIRST_PSEUDO_REGISTER \
452 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
453 || ADDR_REGNO_P (reg_renumber[REGNO]))
454 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
455
456
457 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
458 return the class of reg to actually use. */
459 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
460 s390_preferred_reload_class ((X), (CLASS))
461
462 /* We need a secondary reload when loading a PLUS which is
463 not a valid operand for LOAD ADDRESS. */
464 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
465 s390_secondary_input_reload_class ((CLASS), (MODE), (IN))
466
467 /* We need a secondary reload when storing a double-word
468 to a non-offsettable memory address. */
469 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
470 s390_secondary_output_reload_class ((CLASS), (MODE), (OUT))
471
472 /* We need secondary memory to move data between GPRs and FPRs. */
473 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
474 ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS))
475
476 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
477 because the movsi and movsf patterns don't handle r/f moves. */
478 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
479 (GET_MODE_BITSIZE (MODE) < 32 \
480 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
481 : MODE)
482
483
484 /* Stack layout and calling conventions. */
485
486 /* Our stack grows from higher to lower addresses. However, local variables
487 are accessed by positive offsets, and function arguments are stored at
488 increasing addresses. */
489 #define STACK_GROWS_DOWNWARD
490 #define FRAME_GROWS_DOWNWARD 1
491 /* #undef ARGS_GROW_DOWNWARD */
492
493 /* The basic stack layout looks like this: the stack pointer points
494 to the register save area for called functions. Above that area
495 is the location to place outgoing arguments. Above those follow
496 dynamic allocations (alloca), and finally the local variables. */
497
498 /* Offset from stack-pointer to first location of outgoing args. */
499 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
500
501 /* Offset within stack frame to start allocating local variables at. */
502 #define STARTING_FRAME_OFFSET 0
503
504 /* Offset from the stack pointer register to an item dynamically
505 allocated on the stack, e.g., by `alloca'. */
506 extern int current_function_outgoing_args_size;
507 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
508 (STACK_POINTER_OFFSET + current_function_outgoing_args_size)
509
510 /* Offset of first parameter from the argument pointer register value.
511 We have a fake argument pointer register that points directly to
512 the argument area. */
513 #define FIRST_PARM_OFFSET(FNDECL) 0
514
515 /* Defining this macro makes __builtin_frame_address(0) and
516 __builtin_return_address(0) work with -fomit-frame-pointer. */
517 #define INITIAL_FRAME_ADDRESS_RTX \
518 (TARGET_PACKED_STACK ? \
519 plus_constant (arg_pointer_rtx, -UNITS_PER_WORD) : \
520 plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
521
522 /* The return address of the current frame is retrieved
523 from the initial value of register RETURN_REGNUM.
524 For frames farther back, we use the stack slot where
525 the corresponding RETURN_REGNUM register was saved. */
526 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
527 (TARGET_PACKED_STACK ? \
528 plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_WORD) : (FRAME))
529
530 #define RETURN_ADDR_RTX(COUNT, FRAME) \
531 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
532
533 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
534 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
535
536
537 /* Exception handling. */
538
539 /* Describe calling conventions for DWARF-2 exception handling. */
540 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
541 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
542 #define DWARF_FRAME_RETURN_COLUMN 14
543
544 /* Describe how we implement __builtin_eh_return. */
545 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
546 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
547
548 /* Select a format to encode pointers in exception handling data. */
549 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
550 (flag_pic \
551 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
552 : DW_EH_PE_absptr)
553
554
555 /* Frame registers. */
556
557 #define STACK_POINTER_REGNUM 15
558 #define FRAME_POINTER_REGNUM 34
559 #define HARD_FRAME_POINTER_REGNUM 11
560 #define ARG_POINTER_REGNUM 32
561 #define RETURN_ADDRESS_POINTER_REGNUM 35
562
563 /* The static chain must be call-clobbered, but not used for
564 function argument passing. As register 1 is clobbered by
565 the trampoline code, we only have one option. */
566 #define STATIC_CHAIN_REGNUM 0
567
568 /* Number of hardware registers that go into the DWARF-2 unwind info.
569 To avoid ABI incompatibility, this number must not change even as
570 'fake' hard registers are added or removed. */
571 #define DWARF_FRAME_REGISTERS 34
572
573
574 /* Frame pointer and argument pointer elimination. */
575
576 #define FRAME_POINTER_REQUIRED 0
577
578 #define ELIMINABLE_REGS \
579 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
580 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
581 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
582 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
583 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
584 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
585 { BASE_REGNUM, BASE_REGNUM }}
586
587 #define CAN_ELIMINATE(FROM, TO) \
588 s390_can_eliminate ((FROM), (TO))
589
590 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
591 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO))
592
593
594 /* Stack arguments. */
595
596 /* We need current_function_outgoing_args to be valid. */
597 #define ACCUMULATE_OUTGOING_ARGS 1
598
599 /* Return doesn't modify the stack. */
600 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
601
602
603 /* Register arguments. */
604
605 typedef struct s390_arg_structure
606 {
607 int gprs; /* gpr so far */
608 int fprs; /* fpr so far */
609 }
610 CUMULATIVE_ARGS;
611
612 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
613 ((CUM).gprs=0, (CUM).fprs=0)
614
615 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
616 s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
617
618 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
619 s390_function_arg (&CUM, MODE, TYPE, NAMED)
620
621 /* Arguments can be placed in general registers 2 to 6,
622 or in floating point registers 0 and 2. */
623 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
624 (N) == 16 || (N) == 17)
625
626
627 /* Scalar return values. */
628
629 #define FUNCTION_VALUE(VALTYPE, FUNC) \
630 s390_function_value ((VALTYPE), VOIDmode)
631
632 #define LIBCALL_VALUE(MODE) \
633 s390_function_value (NULL, (MODE))
634
635 /* Only gpr 2 and fpr 0 are ever used as return registers. */
636 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
637
638
639 /* Function entry and exit. */
640
641 /* When returning from a function, the stack pointer does not matter. */
642 #define EXIT_IGNORE_STACK 1
643
644
645 /* Profiling. */
646
647 #define FUNCTION_PROFILER(FILE, LABELNO) \
648 s390_function_profiler ((FILE), ((LABELNO)))
649
650 #define PROFILE_BEFORE_PROLOGUE 1
651
652
653 /* Implementing the varargs macros. */
654
655 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
656 s390_va_start (valist, nextarg)
657
658 /* Trampolines for nested functions. */
659
660 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16)
661
662 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
663 s390_initialize_trampoline ((ADDR), (FNADDR), (CXT))
664
665 #define TRAMPOLINE_TEMPLATE(FILE) \
666 s390_trampoline_template (FILE)
667
668
669 /* Addressing modes, and classification of registers for them. */
670
671 /* Recognize any constant value that is a valid address. */
672 #define CONSTANT_ADDRESS_P(X) 0
673
674 /* Maximum number of registers that can appear in a valid memory address. */
675 #define MAX_REGS_PER_ADDRESS 2
676
677 /* S/390 has no mode dependent addresses. */
678 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
679
680 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
681 valid memory address for an instruction.
682 The MODE argument is the machine mode for the MEM expression
683 that wants to use this address. */
684 #ifdef REG_OK_STRICT
685 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
686 { \
687 if (legitimate_address_p (MODE, X, 1)) \
688 goto ADDR; \
689 }
690 #else
691 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
692 { \
693 if (legitimate_address_p (MODE, X, 0)) \
694 goto ADDR; \
695 }
696 #endif
697
698 /* Try machine-dependent ways of modifying an illegitimate address
699 to be legitimate. If we find one, return the new, valid address.
700 This macro is used in only one place: `memory_address' in explow.c. */
701 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
702 { \
703 (X) = legitimize_address (X, OLDX, MODE); \
704 if (memory_address_p (MODE, X)) \
705 goto WIN; \
706 }
707
708 /* Try a machine-dependent way of reloading an illegitimate address
709 operand. If we find one, push the reload and jump to WIN. This
710 macro is used in only one place: `find_reloads_address' in reload.c. */
711 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
712 do { \
713 rtx new = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \
714 if (new) \
715 { \
716 (AD) = new; \
717 goto WIN; \
718 } \
719 } while (0)
720
721 /* Nonzero if the constant value X is a legitimate general operand.
722 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
723 #define LEGITIMATE_CONSTANT_P(X) \
724 legitimate_constant_p (X)
725
726 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
727 #define SYMBOLIC_CONST(X) \
728 (GET_CODE (X) == SYMBOL_REF \
729 || GET_CODE (X) == LABEL_REF \
730 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
731
732 #define TLS_SYMBOLIC_CONST(X) \
733 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
734 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
735
736
737 /* Condition codes. */
738
739 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
740 return the mode to be used for the comparison. */
741 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
742
743 /* Canonicalize a comparison from one we don't have to one we do have. */
744 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
745 s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1))
746
747 /* Define the information needed to generate branch and scc insns. This is
748 stored from the compare operation. Note that we can't use "rtx" here
749 since it hasn't been defined! */
750 extern struct rtx_def *s390_compare_op0, *s390_compare_op1, *s390_compare_emitted;
751
752
753 /* Relative costs of operations. */
754
755 /* On s390, copy between fprs and gprs is expensive. */
756 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
757 (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \
758 && reg_classes_intersect_p ((CLASS2), FP_REGS)) \
759 || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \
760 && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
761
762 /* A C expression for the cost of moving data of mode M between a
763 register and memory. A value of 2 is the default; this cost is
764 relative to those in `REGISTER_MOVE_COST'. */
765 #define MEMORY_MOVE_COST(M, C, I) 1
766
767 /* A C expression for the cost of a branch instruction. A value of 1
768 is the default; other values are interpreted relative to that. */
769 #define BRANCH_COST 1
770
771 /* Nonzero if access to memory by bytes is slow and undesirable. */
772 #define SLOW_BYTE_ACCESS 1
773
774 /* An integer expression for the size in bits of the largest integer machine
775 mode that should actually be used. We allow pairs of registers. */
776 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
777
778 /* The maximum number of bytes that a single instruction can move quickly
779 between memory and registers or between two memory locations. */
780 #define MOVE_MAX (TARGET_64BIT ? 16 : 8)
781 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
782 #define MAX_MOVE_MAX 16
783
784 /* Determine whether to use move_by_pieces or block move insn. */
785 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
786 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
787 || (TARGET_64BIT && (SIZE) == 8) )
788
789 /* Determine whether to use clear_by_pieces or block clear insn. */
790 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
791 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
792 || (TARGET_64BIT && (SIZE) == 8) )
793
794 /* This macro is used to determine whether store_by_pieces should be
795 called to "memset" storage with byte values other than zero, or
796 to "memcpy" storage when the source is a constant string. */
797 #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN)
798
799 /* Don't perform CSE on function addresses. */
800 #define NO_FUNCTION_CSE
801
802
803 /* Sections. */
804
805 /* Output before read-only data. */
806 #define TEXT_SECTION_ASM_OP ".text"
807
808 /* Output before writable (initialized) data. */
809 #define DATA_SECTION_ASM_OP ".data"
810
811 /* Output before writable (uninitialized) data. */
812 #define BSS_SECTION_ASM_OP ".bss"
813
814 /* S/390 constant pool breaks the devices in crtstuff.c to control section
815 in where code resides. We have to write it as asm code. */
816 #ifndef __s390x__
817 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
818 asm (SECTION_OP "\n\
819 bras\t%r2,1f\n\
820 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
821 1: l\t%r3,0(%r2)\n\
822 bas\t%r14,0(%r3,%r2)\n\
823 .previous");
824 #endif
825
826
827 /* Position independent code. */
828
829 extern int flag_pic;
830
831 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
832
833 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
834
835
836 /* Assembler file format. */
837
838 /* Character to start a comment. */
839 #define ASM_COMMENT_START "#"
840
841 /* Declare an uninitialized external linkage data object. */
842 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
843 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
844
845 /* Globalizing directive for a label. */
846 #define GLOBAL_ASM_OP ".globl "
847
848 /* Advance the location counter to a multiple of 2**LOG bytes. */
849 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
850 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
851
852 /* Advance the location counter by SIZE bytes. */
853 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
854 fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
855
856 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
857 #define LOCAL_LABEL_PREFIX "."
858
859 /* How to refer to registers in assembler output. This sequence is
860 indexed by compiler's hard-register-number (see above). */
861 #define REGISTER_NAMES \
862 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
863 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
864 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
865 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
866 "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \
867 }
868
869 /* Print operand X (an rtx) in assembler syntax to file FILE. */
870 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
871 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
872
873 /* Output machine-dependent UNSPECs in address constants. */
874 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
875 do { \
876 if (!s390_output_addr_const_extra (FILE, (X))) \
877 goto FAIL; \
878 } while (0);
879
880 /* Output an element of a case-vector that is absolute. */
881 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
882 do { \
883 char buf[32]; \
884 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
885 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
886 assemble_name ((FILE), buf); \
887 fputc ('\n', (FILE)); \
888 } while (0)
889
890 /* Output an element of a case-vector that is relative. */
891 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
892 do { \
893 char buf[32]; \
894 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
895 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
896 assemble_name ((FILE), buf); \
897 fputc ('-', (FILE)); \
898 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \
899 assemble_name ((FILE), buf); \
900 fputc ('\n', (FILE)); \
901 } while (0)
902
903
904 /* Miscellaneous parameters. */
905
906 /* Specify the machine mode that this machine uses for the index in the
907 tablejump instruction. */
908 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
909
910 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
911 is done just by pretending it is already truncated. */
912 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
913
914 /* Specify the machine mode that pointers have.
915 After generation of rtl, the compiler makes no further distinction
916 between pointers and any other objects of this machine mode. */
917 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
918
919 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */
920 #define POINTERS_EXTEND_UNSIGNED -1
921
922 /* A function address in a call instruction is a byte address (for
923 indexing purposes) so give the MEM rtx a byte's mode. */
924 #define FUNCTION_MODE QImode
925
926 /* Specify the value which is used when clz operand is zero. */
927 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
928
929 /* Machine-specific symbol_ref flags. */
930 #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0)
931
932 /* Check whether integer displacement is in range. */
933 #define DISP_IN_RANGE(d) \
934 (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
935 : ((d) >= 0 && (d) <= 4095))
936
937 #endif