projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Makefile.in (cse.o): Depend on TARGET_H.
[gcc.git] / gcc / config / s390 / s390.h
1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com).
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #ifndef _S390_H
23 #define _S390_H
24
25 /* Override the __fixdfdi etc. routines when building libgcc2.
26 ??? This should be done in a cleaner way ... */
27 #ifdef IN_LIBGCC2
28 #include <s390/fixdfdi.h>
29 #endif
30
31 /* Which processor to generate code or schedule for. The cpu attribute
32 defines a list that mirrors this list, so changes to s390.md must be
33 made at the same time. */
34
35 enum processor_type
36 {
37 PROCESSOR_9672_G5,
38 PROCESSOR_9672_G6,
39 PROCESSOR_2064_Z900,
40 PROCESSOR_max
41 };
42
43 extern enum processor_type s390_cpu;
44 extern const char *s390_tune_string;
45
46 extern enum processor_type s390_arch;
47 extern const char *s390_arch_string;
48
49 #define TARGET_CPU_DEFAULT_9672 0
50 #define TARGET_CPU_DEFAULT_2064 2
51
52 #define TARGET_CPU_DEFAULT_NAMES {"g5", "g6", "z900"}
53
54 /* Run-time target specification. */
55
56 /* Target CPU builtins. */
57 #define TARGET_CPU_CPP_BUILTINS() \
58 do \
59 { \
60 builtin_assert ("cpu=s390"); \
61 builtin_assert ("machine=s390"); \
62 builtin_define ("__s390__"); \
63 if (TARGET_64BIT) \
64 builtin_define ("__s390x__"); \
65 } \
66 while (0)
67
68 /* Optional target features. */
69 extern int target_flags;
70
71 #define MASK_HARD_FLOAT 0x01
72 #define MASK_BACKCHAIN 0x02
73 #define MASK_SMALL_EXEC 0x04
74 #define MASK_DEBUG_ARG 0x08
75 #define MASK_64BIT 0x10
76 #define MASK_ZARCH 0x20
77 #define MASK_MVCLE 0x40
78
79 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
80 #define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT))
81 #define TARGET_BACKCHAIN (target_flags & MASK_BACKCHAIN)
82 #define TARGET_SMALL_EXEC (target_flags & MASK_SMALL_EXEC)
83 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
84 #define TARGET_64BIT (target_flags & MASK_64BIT)
85 #define TARGET_ZARCH (target_flags & MASK_ZARCH)
86 #define TARGET_MVCLE (target_flags & MASK_MVCLE)
87
88 /* ??? Once this actually works, it could be made a runtime option. */
89 #define TARGET_IBM_FLOAT 0
90 #define TARGET_IEEE_FLOAT 1
91
92 #ifdef DEFAULT_TARGET_64BIT
93 #define TARGET_DEFAULT 0x33
94 #else
95 #define TARGET_DEFAULT 0x3
96 #endif
97
98 #define TARGET_SWITCHES \
99 { { "hard-float", 1, N_("Use hardware fp")}, \
100 { "soft-float", -1, N_("Don't use hardware fp")}, \
101 { "backchain", 2, N_("Set backchain")}, \
102 { "no-backchain", -2, N_("Don't set backchain (faster, but debug harder")}, \
103 { "small-exec", 4, N_("Use bras for execucable < 64k")}, \
104 { "no-small-exec",-4, N_("Don't use bras")}, \
105 { "debug", 8, N_("Additional debug prints")}, \
106 { "no-debug", -8, N_("Don't print additional debug prints")}, \
107 { "64", 16, N_("64 bit ABI")}, \
108 { "31", -16, N_("31 bit ABI")}, \
109 { "zarch", 32, N_("z/Architecture")}, \
110 { "esa", -32, N_("ESA/390 architecture")}, \
111 { "mvcle", 64, N_("mvcle use")}, \
112 { "no-mvcle", -64, N_("mvc&ex")}, \
113 { "", TARGET_DEFAULT, 0 } }
114
115 #define TARGET_OPTIONS \
116 { { "tune=", &s390_tune_string, \
117 N_("Schedule code for given CPU")}, \
118 { "arch=", &s390_arch_string, \
119 N_("Generate code for given CPU")}, \
120 }
121
122 /* Target version string. Overridden by the OS header. */
123 #ifdef DEFAULT_TARGET_64BIT
124 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
125 #else
126 #define TARGET_VERSION fprintf (stderr, " (S/390)");
127 #endif
128
129 /* Hooks to override options. */
130 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE)
131 #define OVERRIDE_OPTIONS override_options ()
132
133 /* Frame pointer is not used for debugging. */
134 #define CAN_DEBUG_WITHOUT_FP
135
136
137 /* Target machine storage layout. */
138
139 /* Everything is big-endian. */
140 #define BITS_BIG_ENDIAN 1
141 #define BYTES_BIG_ENDIAN 1
142 #define WORDS_BIG_ENDIAN 1
143
144 /* Width of a word, in units (bytes). */
145 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
146 #define MIN_UNITS_PER_WORD 4
147 #define MAX_BITS_PER_WORD 64
148
149 /* Function arguments and return values are promoted to word size. */
150 #define PROMOTE_FUNCTION_ARGS
151 #define PROMOTE_FUNCTION_RETURN
152 #define PROMOTE_FOR_CALL_ONLY
153
154 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
155 if (INTEGRAL_MODE_P (MODE) && \
156 GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \
157 (MODE) = Pmode; \
158 }
159
160 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
161 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
162
163 /* Boundary (in *bits*) on which stack pointer should be aligned. */
164 #define STACK_BOUNDARY 64
165
166 /* Allocation boundary (in *bits*) for the code of a function. */
167 #define FUNCTION_BOUNDARY 32
168
169 /* There is no point aligning anything to a rounder boundary than this. */
170 #define BIGGEST_ALIGNMENT 64
171
172 /* Alignment of field after `int : 0' in a structure. */
173 #define EMPTY_FIELD_BOUNDARY 32
174
175 /* Alignment on even addresses for LARL instruction. */
176 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
177 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
178
179 /* Alignment is not required by the hardware. */
180 #define STRICT_ALIGNMENT 0
181
182 /* Mode of stack savearea.
183 FUNCTION is VOIDmode because calling convention maintains SP.
184 BLOCK needs Pmode for SP.
185 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
186 #define STACK_SAVEAREA_MODE(LEVEL) \
187 (LEVEL == SAVE_FUNCTION ? VOIDmode \
188 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
189
190 /* Define target floating point format. */
191 #define TARGET_FLOAT_FORMAT \
192 (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT)
193
194
195 /* Type layout. */
196
197 /* Sizes in bits of the source language data types. */
198 #define SHORT_TYPE_SIZE 16
199 #define INT_TYPE_SIZE 32
200 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
201 #define MAX_LONG_TYPE_SIZE 64
202 #define LONG_LONG_TYPE_SIZE 64
203 #define FLOAT_TYPE_SIZE 32
204 #define DOUBLE_TYPE_SIZE 64
205 #define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */
206
207 /* We use "unsigned char" as default. */
208 #define DEFAULT_SIGNED_CHAR 0
209
210
211 /* Register usage. */
212
213 /* We have 16 general purpose registers (registers 0-15),
214 and 16 floating point registers (registers 16-31).
215 (On non-IEEE machines, we have only 4 fp registers.)
216
217 Amongst the general purpose registers, some are used
218 for specific purposes:
219 GPR 11: Hard frame pointer (if needed)
220 GPR 12: Global offset table pointer (if needed)
221 GPR 13: Literal pool base register
222 GPR 14: Return address register
223 GPR 15: Stack pointer
224
225 Registers 32-34 are 'fake' hard registers that do not
226 correspond to actual hardware:
227 Reg 32: Argument pointer
228 Reg 33: Condition code
229 Reg 34: Frame pointer */
230
231 #define FIRST_PSEUDO_REGISTER 35
232
233 /* Standard register usage. */
234 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
235 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
236 #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
237 #define CC_REGNO_P(N) ((N) == 33)
238 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34)
239
240 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
241 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
242 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
243 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
244 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
245
246 #define BASE_REGISTER 13
247 #define RETURN_REGNUM 14
248 #define CC_REGNUM 33
249
250 /* Set up fixed registers and calling convention:
251
252 GPRs 0-5 are always call-clobbered,
253 GPRs 6-15 are always call-saved.
254 GPR 12 is fixed if used as GOT pointer.
255 GPR 13 is always fixed (as literal pool pointer).
256 GPR 14 is always fixed (as return address).
257 GPR 15 is always fixed (as stack pointer).
258 The 'fake' hard registers are call-clobbered and fixed.
259
260 On 31-bit, FPRs 18-19 are call-clobbered;
261 on 64-bit, FPRs 24-31 are call-clobbered.
262 The remaining FPRs are call-saved. */
263
264 #define FIXED_REGISTERS \
265 { 0, 0, 0, 0, \
266 0, 0, 0, 0, \
267 0, 0, 0, 0, \
268 0, 1, 1, 1, \
269 0, 0, 0, 0, \
270 0, 0, 0, 0, \
271 0, 0, 0, 0, \
272 0, 0, 0, 0, \
273 1, 1, 1 }
274
275 #define CALL_USED_REGISTERS \
276 { 1, 1, 1, 1, \
277 1, 1, 0, 0, \
278 0, 0, 0, 0, \
279 0, 1, 1, 1, \
280 1, 1, 1, 1, \
281 1, 1, 1, 1, \
282 1, 1, 1, 1, \
283 1, 1, 1, 1, \
284 1, 1, 1 }
285
286 #define CALL_REALLY_USED_REGISTERS \
287 { 1, 1, 1, 1, \
288 1, 1, 0, 0, \
289 0, 0, 0, 0, \
290 0, 0, 0, 0, \
291 1, 1, 1, 1, \
292 1, 1, 1, 1, \
293 1, 1, 1, 1, \
294 1, 1, 1, 1, \
295 1, 1, 1 }
296
297 #define CONDITIONAL_REGISTER_USAGE \
298 do \
299 { \
300 int i; \
301 \
302 if (flag_pic) \
303 { \
304 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
305 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
306 } \
307 if (TARGET_64BIT) \
308 { \
309 for (i = 24; i < 32; i++) \
310 call_used_regs[i] = call_really_used_regs[i] = 0; \
311 } \
312 else \
313 { \
314 for (i = 18; i < 20; i++) \
315 call_used_regs[i] = call_really_used_regs[i] = 0; \
316 } \
317 } while (0)
318
319 /* Preferred register allocation order. */
320 #define REG_ALLOC_ORDER \
321 { 1, 2, 3, 4, 5, 0, 14, 13, 12, 11, 10, 9, 8, 7, 6, \
322 16, 17, 18, 19, 20, 21, 22, 23, \
323 24, 25, 26, 27, 28, 29, 30, 31, \
324 15, 32, 33, 34 }
325
326
327 /* Fitting values into registers. */
328
329 /* Integer modes <= word size fit into any GPR.
330 Integer modes > word size fit into successive GPRs, starting with
331 an even-numbered register.
332 SImode and DImode fit into FPRs as well.
333
334 Floating point modes <= word size fit into any FPR or GPR.
335 Floating point modes > word size (i.e. DFmode on 32-bit) fit
336 into any FPR, or an even-odd GPR pair.
337
338 Complex floating point modes fit either into two FPRs, or into
339 successive GPRs (again starting with an even number).
340
341 Condition code modes fit only into the CC register. */
342
343 #define HARD_REGNO_NREGS(REGNO, MODE) \
344 (FP_REGNO_P(REGNO)? \
345 (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
346 GENERAL_REGNO_P(REGNO)? \
347 ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \
348 1)
349
350 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
351 (FP_REGNO_P(REGNO)? \
352 ((MODE) == SImode || (MODE) == DImode || \
353 GET_MODE_CLASS(MODE) == MODE_FLOAT || \
354 GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \
355 GENERAL_REGNO_P(REGNO)? \
356 (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \
357 CC_REGNO_P(REGNO)? \
358 GET_MODE_CLASS (MODE) == MODE_CC : \
359 FRAME_REGNO_P(REGNO)? \
360 (enum machine_mode) (MODE) == Pmode : \
361 0)
362
363 #define MODES_TIEABLE_P(MODE1, MODE2) \
364 (((MODE1) == SFmode || (MODE1) == DFmode) \
365 == ((MODE2) == SFmode || (MODE2) == DFmode))
366
367 /* Maximum number of registers to represent a value of mode MODE
368 in a register of class CLASS. */
369 #define CLASS_MAX_NREGS(CLASS, MODE) \
370 ((CLASS) == FP_REGS ? \
371 (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
372 (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
373
374 /* If a 4-byte value is loaded into a FPR, it is placed into the
375 *upper* half of the register, not the lower. Therefore, we
376 cannot use SUBREGs to switch between modes in FP registers. */
377 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \
378 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) ? FP_REGS : NO_REGS)
379
380 /* Register classes. */
381
382 /* We use the following register classes:
383 GENERAL_REGS All general purpose registers
384 ADDR_REGS All general purpose registers except %r0
385 (These registers can be used in address generation)
386 FP_REGS All floating point registers
387
388 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
389 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
390
391 NO_REGS No registers
392 ALL_REGS All registers
393
394 Note that the 'fake' frame pointer and argument pointer registers
395 are included amongst the address registers here. The condition
396 code register is only included in ALL_REGS. */
397
398 enum reg_class
399 {
400 NO_REGS, ADDR_REGS, GENERAL_REGS,
401 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
402 ALL_REGS, LIM_REG_CLASSES
403 };
404 #define N_REG_CLASSES (int) LIM_REG_CLASSES
405
406 #define REG_CLASS_NAMES \
407 { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \
408 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
409
410 /* Class -> register mapping. */
411 #define REG_CLASS_CONTENTS \
412 { \
413 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
414 { 0x0000fffe, 0x00000005 }, /* ADDR_REGS */ \
415 { 0x0000ffff, 0x00000005 }, /* GENERAL_REGS */ \
416 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \
417 { 0xfffffffe, 0x00000005 }, /* ADDR_FP_REGS */ \
418 { 0xffffffff, 0x00000005 }, /* GENERAL_FP_REGS */ \
419 { 0xffffffff, 0x00000007 }, /* ALL_REGS */ \
420 }
421
422 /* Register -> class mapping. */
423 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
424 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
425
426 /* ADDR_REGS can be used as base or index register. */
427 #define INDEX_REG_CLASS ADDR_REGS
428 #define BASE_REG_CLASS ADDR_REGS
429
430 /* Check whether REGNO is a hard register of the suitable class
431 or a pseudo register currently allocated to one such. */
432 #define REGNO_OK_FOR_INDEX_P(REGNO) \
433 (((REGNO) < FIRST_PSEUDO_REGISTER \
434 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
435 || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16))
436 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
437
438
439 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
440 return the class of reg to actually use. */
441 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
442 s390_preferred_reload_class ((X), (CLASS))
443
444 /* We need a secondary reload when loading a PLUS which is
445 not a valid operand for LOAD ADDRESS. */
446 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
447 s390_secondary_input_reload_class ((CLASS), (MODE), (IN))
448
449 /* We need secondary memory to move data between GPRs and FPRs. */
450 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
451 ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS))
452
453 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
454 because the movsi and movsf patterns don't handle r/f moves. */
455 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
456 (GET_MODE_BITSIZE (MODE) < 32 \
457 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
458 : MODE)
459
460
461 /* Define various machine-dependent constraint letters. */
462
463 #define REG_CLASS_FROM_LETTER(C) \
464 ((C) == 'a' ? ADDR_REGS : \
465 (C) == 'd' ? GENERAL_REGS : \
466 (C) == 'f' ? FP_REGS : NO_REGS)
467
468 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
469 ((C) == 'I' ? (unsigned long) (VALUE) < 256 : \
470 (C) == 'J' ? (unsigned long) (VALUE) < 4096 : \
471 (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : \
472 (C) == 'L' ? (unsigned long) (VALUE) < 65536 : 0)
473
474 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
475
476 #define EXTRA_CONSTRAINT(OP, C) \
477 ((C) == 'Q' ? q_constraint (OP) : \
478 (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0)
479
480 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'Q')
481
482
483 /* Stack layout and calling conventions. */
484
485 /* Our stack grows from higher to lower addresses. However, local variables
486 are accessed by positive offsets, and function arguments are stored at
487 increasing addresses. */
488 #define STACK_GROWS_DOWNWARD
489 /* #undef FRAME_GROWS_DOWNWARD */
490 /* #undef ARGS_GROW_DOWNWARD */
491
492 /* The basic stack layout looks like this: the stack pointer points
493 to the register save area for called functions. Above that area
494 is the location to place outgoing arguments. Above those follow
495 dynamic allocations (alloca), and finally the local variables. */
496
497 /* Offset from stack-pointer to first location of outgoing args. */
498 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
499
500 /* Offset within stack frame to start allocating local variables at. */
501 extern int current_function_outgoing_args_size;
502 #define STARTING_FRAME_OFFSET \
503 (STACK_POINTER_OFFSET + current_function_outgoing_args_size)
504
505 /* Offset from the stack pointer register to an item dynamically
506 allocated on the stack, e.g., by `alloca'. */
507 #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET)
508
509 /* Offset of first parameter from the argument pointer register value.
510 We have a fake argument pointer register that points directly to
511 the argument area. */
512 #define FIRST_PARM_OFFSET(FNDECL) 0
513
514 /* The return address of the current frame is retrieved
515 from the initial value of register RETURN_REGNUM.
516 For frames farther back, we use the stack slot where
517 the corresponding RETURN_REGNUM register was saved. */
518
519 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
520 ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \
521 plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
522
523 #define RETURN_ADDR_RTX(COUNT, FRAME) \
524 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
525
526 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
527 #define MASK_RETURN_ADDR (TARGET_64BIT ? GEN_INT (-1) : GEN_INT (0x7fffffff))
528
529
530 /* Exception handling. */
531
532 /* Describe calling conventions for DWARF-2 exception handling. */
533 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
534 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
535 #define DWARF_FRAME_RETURN_COLUMN 14
536
537 /* Describe how we implement __builtin_eh_return. */
538 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
539 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
540 #define EH_RETURN_HANDLER_RTX \
541 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \
542 TARGET_64BIT? -48 : -40))
543
544 /* Select a format to encode pointers in exception handling data. */
545 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
546 (flag_pic \
547 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
548 : DW_EH_PE_absptr)
549
550
551 /* Frame registers. */
552
553 #define STACK_POINTER_REGNUM 15
554 #define FRAME_POINTER_REGNUM 34
555 #define HARD_FRAME_POINTER_REGNUM 11
556 #define ARG_POINTER_REGNUM 32
557
558 /* The static chain must be call-clobbered, but not used for
559 function argument passing. As register 1 is clobbered by
560 the trampoline code, we only have one option. */
561 #define STATIC_CHAIN_REGNUM 0
562
563 /* Number of hardware registers that go into the DWARF-2 unwind info.
564 To avoid ABI incompatibility, this number must not change even as
565 'fake' hard registers are added or removed. */
566 #define DWARF_FRAME_REGISTERS 34
567
568
569 /* Frame pointer and argument pointer elimination. */
570
571 #define FRAME_POINTER_REQUIRED 0
572
573 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0
574
575 #define ELIMINABLE_REGS \
576 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
577 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
578 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
579 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
580
581 #define CAN_ELIMINATE(FROM, TO) (1)
582
583 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
584 { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
585 { (OFFSET) = 0; } \
586 else if ((FROM) == FRAME_POINTER_REGNUM \
587 && (TO) == HARD_FRAME_POINTER_REGNUM) \
588 { (OFFSET) = 0; } \
589 else if ((FROM) == ARG_POINTER_REGNUM \
590 && (TO) == HARD_FRAME_POINTER_REGNUM) \
591 { (OFFSET) = s390_arg_frame_offset (); } \
592 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
593 { (OFFSET) = s390_arg_frame_offset (); } \
594 else \
595 abort(); \
596 }
597
598
599 /* Stack arguments. */
600
601 /* We need current_function_outgoing_args to be valid. */
602 #define ACCUMULATE_OUTGOING_ARGS 1
603
604 /* Return doesn't modify the stack. */
605 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
606
607
608 /* Register arguments. */
609
610 typedef struct s390_arg_structure
611 {
612 int gprs; /* gpr so far */
613 int fprs; /* fpr so far */
614 }
615 CUMULATIVE_ARGS;
616
617 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN) \
618 ((CUM).gprs=0, (CUM).fprs=0)
619
620 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
621 s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
622
623 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
624 s390_function_arg (&CUM, MODE, TYPE, NAMED)
625
626 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
627 s390_function_arg_pass_by_reference (MODE, TYPE)
628
629 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
630
631 /* Arguments can be placed in general registers 2 to 6,
632 or in floating point registers 0 and 2. */
633 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
634 (N) == 16 || (N) == 17)
635
636
637 /* Scalar return values. */
638
639 /* We return scalars in general purpose register 2 for integral values,
640 and floating point register 0 for fp values. */
641 #define FUNCTION_VALUE(VALTYPE, FUNC) \
642 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
643 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
644 || POINTER_TYPE_P (VALTYPE) \
645 ? word_mode : TYPE_MODE (VALTYPE), \
646 TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 16 : 2)
647
648 /* Define how to find the value returned by a library function assuming
649 the value has mode MODE. */
650 #define RET_REG(MODE) ((GET_MODE_CLASS (MODE) == MODE_INT \
651 || TARGET_SOFT_FLOAT ) ? 2 : 16)
652 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RET_REG (MODE))
653
654 /* Only gpr 2 and fpr 0 are ever used as return registers. */
655 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
656
657
658 /* Aggregate return values. */
659
660 /* The definition of this macro implies that there are cases where
661 a scalar value cannot be returned in registers. */
662 #define RETURN_IN_MEMORY(type) \
663 (TYPE_MODE (type) == BLKmode || \
664 GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_INT || \
665 GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT)
666
667 /* Structure value address is passed as invisible first argument (gpr 2). */
668 #define STRUCT_VALUE 0
669
670
671 /* Function entry and exit. */
672
673 /* When returning from a function, the stack pointer does not matter. */
674 #define EXIT_IGNORE_STACK 1
675
676
677 /* Profiling. */
678
679 #define FUNCTION_PROFILER(FILE, LABELNO) \
680 s390_function_profiler ((FILE), ((LABELNO)))
681
682 #define PROFILE_BEFORE_PROLOGUE 1
683
684
685 /* Implementing the varargs macros. */
686
687 #define BUILD_VA_LIST_TYPE(VALIST) \
688 (VALIST) = s390_build_va_list ()
689
690 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
691 s390_va_start (valist, nextarg)
692
693 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
694 s390_va_arg (valist, type)
695
696
697 /* Trampolines for nested functions. */
698
699 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20)
700
701 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
702 s390_initialize_trampoline ((ADDR), (FNADDR), (CXT))
703
704 #define TRAMPOLINE_TEMPLATE(FILE) \
705 s390_trampoline_template (FILE)
706
707
708 /* Library calls. */
709
710 /* We should use memcpy, not bcopy. */
711 #define TARGET_MEM_FUNCTIONS
712
713
714 /* Addressing modes, and classification of registers for them. */
715
716 /* Recognize any constant value that is a valid address. */
717 #define CONSTANT_ADDRESS_P(X) 0
718
719 /* Maximum number of registers that can appear in a valid memory address. */
720 #define MAX_REGS_PER_ADDRESS 2
721
722 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check
723 its validity for a certain class. We have two alternate definitions
724 for each of them. The usual definition accepts all pseudo regs; the
725 other rejects them all. The symbol REG_OK_STRICT causes the latter
726 definition to be used.
727
728 Most source files want to accept pseudo regs in the hope that they will
729 get allocated to the class that the insn wants them to be in.
730 Some source files that are used after register allocation
731 need to be strict. */
732
733 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
734 ((GET_MODE (X) == Pmode) && \
735 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \
736 || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))
737
738 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
739
740 #define REG_OK_FOR_INDEX_STRICT_P(X) \
741 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X))))
742
743 #define REG_OK_FOR_BASE_STRICT_P(X) \
744 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X))))
745
746 #ifndef REG_OK_STRICT
747 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
748 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
749 #else
750 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
751 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
752 #endif
753
754 /* S/390 has no mode dependent addresses. */
755 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
756
757 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
758 valid memory address for an instruction.
759 The MODE argument is the machine mode for the MEM expression
760 that wants to use this address. */
761 #ifdef REG_OK_STRICT
762 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
763 { \
764 if (legitimate_address_p (MODE, X, 1)) \
765 goto ADDR; \
766 }
767 #else
768 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
769 { \
770 if (legitimate_address_p (MODE, X, 0)) \
771 goto ADDR; \
772 }
773 #endif
774
775 /* Try machine-dependent ways of modifying an illegitimate address
776 to be legitimate. If we find one, return the new, valid address.
777 This macro is used in only one place: `memory_address' in explow.c. */
778 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
779 { \
780 (X) = legitimize_address (X, OLDX, MODE); \
781 if (memory_address_p (MODE, X)) \
782 goto WIN; \
783 }
784
785 /* Nonzero if the constant value X is a legitimate general operand.
786 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
787 #define LEGITIMATE_CONSTANT_P(X) \
788 legitimate_constant_p (X)
789
790 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
791 #define SYMBOLIC_CONST(X) \
792 (GET_CODE (X) == SYMBOL_REF \
793 || GET_CODE (X) == LABEL_REF \
794 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
795
796 #define TLS_SYMBOLIC_CONST(X) \
797 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
798 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
799
800
801 /* Condition codes. */
802
803 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
804 return the mode to be used for the comparison. */
805 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
806
807 /* Define the information needed to generate branch and scc insns. This is
808 stored from the compare operation. Note that we can't use "rtx" here
809 since it hasn't been defined! */
810 extern struct rtx_def *s390_compare_op0, *s390_compare_op1;
811
812
813 /* Relative costs of operations. */
814
815 /* An expression giving the cost of an addressing mode that contains
816 ADDRESS. If not defined, the cost is computed from the ADDRESS
817 expression and the `CONST_COSTS' values. */
818 #define ADDRESS_COST(RTX) s390_address_cost ((RTX))
819
820 /* On s390, copy between fprs and gprs is expensive. */
821 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
822 (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \
823 && reg_classes_intersect_p ((CLASS2), FP_REGS)) \
824 || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \
825 && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
826
827 /* A C expression for the cost of moving data of mode M between a
828 register and memory. A value of 2 is the default; this cost is
829 relative to those in `REGISTER_MOVE_COST'. */
830 #define MEMORY_MOVE_COST(M, C, I) 1
831
832 /* A C expression for the cost of a branch instruction. A value of 1
833 is the default; other values are interpreted relative to that. */
834 #define BRANCH_COST 1
835
836 /* Nonzero if access to memory by bytes is slow and undesirable. */
837 #define SLOW_BYTE_ACCESS 1
838
839 /* The maximum number of bytes that a single instruction can move quickly
840 between memory and registers or between two memory locations. */
841 #define MOVE_MAX (TARGET_64BIT ? 16 : 8)
842 #define MAX_MOVE_MAX 16
843
844 /* Determine whether to use move_by_pieces or block move insn. */
845 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
846 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
847 || (TARGET_64BIT && (SIZE) == 8) )
848
849 /* Determine whether to use clear_by_pieces or block clear insn. */
850 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
851 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
852 || (TARGET_64BIT && (SIZE) == 8) )
853
854 /* Don't perform CSE on function addresses. */
855 #define NO_FUNCTION_CSE
856
857
858 /* Sections. */
859
860 /* Output before read-only data. */
861 #define TEXT_SECTION_ASM_OP ".text"
862
863 /* Output before writable (initialized) data. */
864 #define DATA_SECTION_ASM_OP ".data"
865
866 /* Output before writable (uninitialized) data. */
867 #define BSS_SECTION_ASM_OP ".bss"
868
869 /* S/390 constant pool breaks the devices in crtstuff.c to control section
870 in where code resides. We have to write it as asm code. */
871 #ifndef __s390x__
872 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
873 asm (SECTION_OP "\n\
874 bras\t%r2,1f\n\
875 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
876 1: l\t%r3,0(%r2)\n\
877 bas\t%r14,0(%r3,%r2)\n\
878 .previous");
879 #endif
880
881
882 /* Position independent code. */
883
884 extern int flag_pic;
885
886 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
887
888 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
889
890
891 /* Assembler file format. */
892
893 /* Character to start a comment. */
894 #define ASM_COMMENT_START "#"
895
896 /* Declare an uninitialized external linkage data object. */
897 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
898 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
899
900 /* Globalizing directive for a label. */
901 #define GLOBAL_ASM_OP ".globl "
902
903 /* Advance the location counter to a multiple of 2**LOG bytes. */
904 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
905 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
906
907 /* Advance the location counter by SIZE bytes. */
908 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
909 fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE))
910
911 /* Output a reference to a user-level label named NAME. */
912 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
913 asm_fprintf ((FILE), "%U%s", (*targetm.strip_name_encoding) (NAME))
914
915 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
916 #define LOCAL_LABEL_PREFIX "."
917
918 /* Either simplify a location expression, or return the original. */
919 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
920 s390_simplify_dwarf_addr (X)
921
922 /* How to refer to registers in assembler output. This sequence is
923 indexed by compiler's hard-register-number (see above). */
924 #define REGISTER_NAMES \
925 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
926 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
927 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
928 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
929 "%ap", "%cc", "%fp" \
930 }
931
932 /* Print operand X (an rtx) in assembler syntax to file FILE. */
933 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
934 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
935
936 /* Output an element of a case-vector that is absolute. */
937 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
938 do { \
939 char buf[32]; \
940 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
941 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
942 assemble_name ((FILE), buf); \
943 fputc ('\n', (FILE)); \
944 } while (0)
945
946 /* Output an element of a case-vector that is relative. */
947 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
948 do { \
949 char buf[32]; \
950 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
951 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
952 assemble_name ((FILE), buf); \
953 fputc ('-', (FILE)); \
954 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \
955 assemble_name ((FILE), buf); \
956 fputc ('\n', (FILE)); \
957 } while (0)
958
959
960 /* Constant Pool for all symbols operands which are changed with
961 force_const_mem during insn generation (expand_insn). */
962
963 extern int s390_pool_count;
964 extern int s390_nr_constants;
965
966 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, fndecl, size) \
967 { \
968 struct pool_constant *pool; \
969 \
970 if (s390_pool_count == -1) \
971 { \
972 s390_nr_constants = 0; \
973 for (pool = first_pool; pool; pool = pool->next) \
974 if (pool->mark) s390_nr_constants++; \
975 return; \
976 } \
977 }
978
979 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, EXP, MODE, ALIGN, LABELNO, WIN) \
980 { \
981 fprintf (FILE, ".LC%d:\n", LABELNO); \
982 \
983 /* Output the value of the constant itself. */ \
984 switch (GET_MODE_CLASS (MODE)) \
985 { \
986 case MODE_FLOAT: \
987 if (GET_CODE (EXP) != CONST_DOUBLE) \
988 abort (); \
989 \
990 REAL_VALUE_FROM_CONST_DOUBLE (r, EXP); \
991 assemble_real (r, MODE, ALIGN); \
992 break; \
993 \
994 case MODE_INT: \
995 case MODE_PARTIAL_INT: \
996 if (GET_CODE (EXP) == CONST \
997 || GET_CODE (EXP) == SYMBOL_REF \
998 || GET_CODE (EXP) == LABEL_REF) \
999 { \
1000 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), FILE); \
1001 s390_output_symbolic_const (FILE, EXP); \
1002 fputc ('\n', (FILE)); \
1003 } \
1004 else \
1005 { \
1006 assemble_integer (EXP, GET_MODE_SIZE (MODE), ALIGN, 1); \
1007 if (GET_MODE_SIZE (MODE) == 1) \
1008 ASM_OUTPUT_SKIP ((FILE), 1); \
1009 } \
1010 break; \
1011 \
1012 default: \
1013 abort (); \
1014 } \
1015 goto WIN; \
1016 }
1017
1018
1019 /* Miscellaneous parameters. */
1020
1021 /* Define the codes that are matched by predicates in aux-output.c. */
1022 #define PREDICATE_CODES \
1023 {"s_operand", { SUBREG, MEM }}, \
1024 {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \
1025 {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \
1026 {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \
1027 {"load_multiple_operation", {PARALLEL}}, \
1028 {"store_multiple_operation", {PARALLEL}}, \
1029 {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \
1030 {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \
1031 CONST_INT, CONST_DOUBLE }}, \
1032 {"s390_plus_operand", { PLUS }},
1033
1034 /* Specify the machine mode that this machine uses for the index in the
1035 tablejump instruction. */
1036 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
1037
1038 /* Load from integral MODE < SI from memory into register makes sign_extend
1039 or zero_extend
1040 In our case sign_extension happens for Halfwords, other no extension. */
1041 #define LOAD_EXTEND_OP(MODE) \
1042 (TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \
1043 (MODE) == HImode ? SIGN_EXTEND : NIL) \
1044 : ((MODE) == HImode ? SIGN_EXTEND : NIL))
1045
1046 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1047 is done just by pretending it is already truncated. */
1048 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1049
1050 /* Specify the machine mode that pointers have.
1051 After generation of rtl, the compiler makes no further distinction
1052 between pointers and any other objects of this machine mode. */
1053 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
1054
1055 /* A function address in a call instruction is a byte address (for
1056 indexing purposes) so give the MEM rtx a byte's mode. */
1057 #define FUNCTION_MODE QImode
1058
1059 /* This macro definition sets up a default value for `main' to return. */
1060 #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node)
1061
1062 /* In rare cases, correct code generation requires extra machine dependent
1063 processing between the second jump optimization pass and delayed branch
1064 scheduling. On those machines, define this macro as a C statement to act on
1065 the code starting at INSN. */
1066 #define MACHINE_DEPENDENT_REORG(INSN) s390_machine_dependent_reorg (INSN)
1067
1068 #endif