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s390.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY): Second parameter of ASM_OUTPUT_SKIP must...
[gcc.git] / gcc / config / s390 / s390.h
1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com).
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #ifndef _S390_H
23 #define _S390_H
24
25 /* Override the __fixdfdi etc. routines when building libgcc2.
26 ??? This should be done in a cleaner way ... */
27 #if defined (IN_LIBGCC2) && !defined (__s390x__)
28 #include <s390/fixdfdi.h>
29 #endif
30
31 /* Which processor to generate code or schedule for. The cpu attribute
32 defines a list that mirrors this list, so changes to s390.md must be
33 made at the same time. */
34
35 enum processor_type
36 {
37 PROCESSOR_9672_G5,
38 PROCESSOR_9672_G6,
39 PROCESSOR_2064_Z900,
40 PROCESSOR_max
41 };
42
43 extern enum processor_type s390_cpu;
44 extern const char *s390_tune_string;
45
46 extern enum processor_type s390_arch;
47 extern const char *s390_arch_string;
48
49 #define TARGET_CPU_DEFAULT_9672 0
50 #define TARGET_CPU_DEFAULT_2064 2
51
52 #define TARGET_CPU_DEFAULT_NAMES {"g5", "g6", "z900"}
53
54 /* Run-time target specification. */
55
56 /* Target CPU builtins. */
57 #define TARGET_CPU_CPP_BUILTINS() \
58 do \
59 { \
60 builtin_assert ("cpu=s390"); \
61 builtin_assert ("machine=s390"); \
62 builtin_define ("__s390__"); \
63 if (TARGET_64BIT) \
64 builtin_define ("__s390x__"); \
65 } \
66 while (0)
67
68 /* Optional target features. */
69 extern int target_flags;
70
71 #define MASK_HARD_FLOAT 0x01
72 #define MASK_BACKCHAIN 0x02
73 #define MASK_SMALL_EXEC 0x04
74 #define MASK_DEBUG_ARG 0x08
75 #define MASK_64BIT 0x10
76 #define MASK_ZARCH 0x20
77 #define MASK_MVCLE 0x40
78
79 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
80 #define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT))
81 #define TARGET_BACKCHAIN (target_flags & MASK_BACKCHAIN)
82 #define TARGET_SMALL_EXEC (target_flags & MASK_SMALL_EXEC)
83 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
84 #define TARGET_64BIT (target_flags & MASK_64BIT)
85 #define TARGET_ZARCH (target_flags & MASK_ZARCH)
86 #define TARGET_MVCLE (target_flags & MASK_MVCLE)
87
88 /* ??? Once this actually works, it could be made a runtime option. */
89 #define TARGET_IBM_FLOAT 0
90 #define TARGET_IEEE_FLOAT 1
91
92 #ifdef DEFAULT_TARGET_64BIT
93 #define TARGET_DEFAULT 0x33
94 #else
95 #define TARGET_DEFAULT 0x3
96 #endif
97
98 #define TARGET_SWITCHES \
99 { { "hard-float", 1, N_("Use hardware fp")}, \
100 { "soft-float", -1, N_("Don't use hardware fp")}, \
101 { "backchain", 2, N_("Set backchain")}, \
102 { "no-backchain", -2, N_("Don't set backchain (faster, but debug harder")}, \
103 { "small-exec", 4, N_("Use bras for executable < 64k")}, \
104 { "no-small-exec",-4, N_("Don't use bras")}, \
105 { "debug", 8, N_("Additional debug prints")}, \
106 { "no-debug", -8, N_("Don't print additional debug prints")}, \
107 { "64", 16, N_("64 bit ABI")}, \
108 { "31", -16, N_("31 bit ABI")}, \
109 { "zarch", 32, N_("z/Architecture")}, \
110 { "esa", -32, N_("ESA/390 architecture")}, \
111 { "mvcle", 64, N_("mvcle use")}, \
112 { "no-mvcle", -64, N_("mvc&ex")}, \
113 { "", TARGET_DEFAULT, 0 } }
114
115 #define TARGET_OPTIONS \
116 { { "tune=", &s390_tune_string, \
117 N_("Schedule code for given CPU"), 0}, \
118 { "arch=", &s390_arch_string, \
119 N_("Generate code for given CPU"), 0}, \
120 }
121
122 /* Target version string. Overridden by the OS header. */
123 #ifdef DEFAULT_TARGET_64BIT
124 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
125 #else
126 #define TARGET_VERSION fprintf (stderr, " (S/390)");
127 #endif
128
129 /* Hooks to override options. */
130 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE)
131 #define OVERRIDE_OPTIONS override_options ()
132
133 /* Frame pointer is not used for debugging. */
134 #define CAN_DEBUG_WITHOUT_FP
135
136
137 /* In libgcc2, determine target settings as compile-time constants. */
138 #ifdef IN_LIBGCC2
139 #undef TARGET_64BIT
140 #ifdef __s390x__
141 #define TARGET_64BIT 1
142 #else
143 #define TARGET_64BIT 0
144 #endif
145 #endif
146
147
148 /* Target machine storage layout. */
149
150 /* Everything is big-endian. */
151 #define BITS_BIG_ENDIAN 1
152 #define BYTES_BIG_ENDIAN 1
153 #define WORDS_BIG_ENDIAN 1
154
155 /* Width of a word, in units (bytes). */
156 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
157 #ifndef IN_LIBGCC2
158 #define MIN_UNITS_PER_WORD 4
159 #endif
160 #define MAX_BITS_PER_WORD 64
161
162 /* Function arguments and return values are promoted to word size. */
163 #define PROMOTE_FUNCTION_ARGS
164 #define PROMOTE_FUNCTION_RETURN
165 #define PROMOTE_FOR_CALL_ONLY
166
167 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
168 if (INTEGRAL_MODE_P (MODE) && \
169 GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \
170 (MODE) = Pmode; \
171 }
172
173 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
174 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
175
176 /* Boundary (in *bits*) on which stack pointer should be aligned. */
177 #define STACK_BOUNDARY 64
178
179 /* Allocation boundary (in *bits*) for the code of a function. */
180 #define FUNCTION_BOUNDARY 32
181
182 /* There is no point aligning anything to a rounder boundary than this. */
183 #define BIGGEST_ALIGNMENT 64
184
185 /* Alignment of field after `int : 0' in a structure. */
186 #define EMPTY_FIELD_BOUNDARY 32
187
188 /* Alignment on even addresses for LARL instruction. */
189 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
190 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
191
192 /* Alignment is not required by the hardware. */
193 #define STRICT_ALIGNMENT 0
194
195 /* Mode of stack savearea.
196 FUNCTION is VOIDmode because calling convention maintains SP.
197 BLOCK needs Pmode for SP.
198 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
199 #define STACK_SAVEAREA_MODE(LEVEL) \
200 (LEVEL == SAVE_FUNCTION ? VOIDmode \
201 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
202
203 /* Define target floating point format. */
204 #define TARGET_FLOAT_FORMAT \
205 (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT)
206
207
208 /* Type layout. */
209
210 /* Sizes in bits of the source language data types. */
211 #define SHORT_TYPE_SIZE 16
212 #define INT_TYPE_SIZE 32
213 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
214 #define MAX_LONG_TYPE_SIZE 64
215 #define LONG_LONG_TYPE_SIZE 64
216 #define FLOAT_TYPE_SIZE 32
217 #define DOUBLE_TYPE_SIZE 64
218 #define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */
219
220 /* We use "unsigned char" as default. */
221 #define DEFAULT_SIGNED_CHAR 0
222
223
224 /* Register usage. */
225
226 /* We have 16 general purpose registers (registers 0-15),
227 and 16 floating point registers (registers 16-31).
228 (On non-IEEE machines, we have only 4 fp registers.)
229
230 Amongst the general purpose registers, some are used
231 for specific purposes:
232 GPR 11: Hard frame pointer (if needed)
233 GPR 12: Global offset table pointer (if needed)
234 GPR 13: Literal pool base register
235 GPR 14: Return address register
236 GPR 15: Stack pointer
237
238 Registers 32-34 are 'fake' hard registers that do not
239 correspond to actual hardware:
240 Reg 32: Argument pointer
241 Reg 33: Condition code
242 Reg 34: Frame pointer */
243
244 #define FIRST_PSEUDO_REGISTER 35
245
246 /* Standard register usage. */
247 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
248 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
249 #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
250 #define CC_REGNO_P(N) ((N) == 33)
251 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34)
252
253 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
254 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
255 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
256 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
257 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
258
259 #define BASE_REGISTER 13
260 #define RETURN_REGNUM 14
261 #define CC_REGNUM 33
262
263 /* Set up fixed registers and calling convention:
264
265 GPRs 0-5 are always call-clobbered,
266 GPRs 6-15 are always call-saved.
267 GPR 12 is fixed if used as GOT pointer.
268 GPR 13 is always fixed (as literal pool pointer).
269 GPR 14 is always fixed (as return address).
270 GPR 15 is always fixed (as stack pointer).
271 The 'fake' hard registers are call-clobbered and fixed.
272
273 On 31-bit, FPRs 18-19 are call-clobbered;
274 on 64-bit, FPRs 24-31 are call-clobbered.
275 The remaining FPRs are call-saved. */
276
277 #define FIXED_REGISTERS \
278 { 0, 0, 0, 0, \
279 0, 0, 0, 0, \
280 0, 0, 0, 0, \
281 0, 1, 1, 1, \
282 0, 0, 0, 0, \
283 0, 0, 0, 0, \
284 0, 0, 0, 0, \
285 0, 0, 0, 0, \
286 1, 1, 1 }
287
288 #define CALL_USED_REGISTERS \
289 { 1, 1, 1, 1, \
290 1, 1, 0, 0, \
291 0, 0, 0, 0, \
292 0, 1, 1, 1, \
293 1, 1, 1, 1, \
294 1, 1, 1, 1, \
295 1, 1, 1, 1, \
296 1, 1, 1, 1, \
297 1, 1, 1 }
298
299 #define CALL_REALLY_USED_REGISTERS \
300 { 1, 1, 1, 1, \
301 1, 1, 0, 0, \
302 0, 0, 0, 0, \
303 0, 0, 0, 0, \
304 1, 1, 1, 1, \
305 1, 1, 1, 1, \
306 1, 1, 1, 1, \
307 1, 1, 1, 1, \
308 1, 1, 1 }
309
310 #define CONDITIONAL_REGISTER_USAGE \
311 do \
312 { \
313 int i; \
314 \
315 if (flag_pic) \
316 { \
317 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
318 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
319 } \
320 if (TARGET_64BIT) \
321 { \
322 for (i = 24; i < 32; i++) \
323 call_used_regs[i] = call_really_used_regs[i] = 0; \
324 } \
325 else \
326 { \
327 for (i = 18; i < 20; i++) \
328 call_used_regs[i] = call_really_used_regs[i] = 0; \
329 } \
330 } while (0)
331
332 /* Preferred register allocation order. */
333 #define REG_ALLOC_ORDER \
334 { 1, 2, 3, 4, 5, 0, 14, 13, 12, 11, 10, 9, 8, 7, 6, \
335 16, 17, 18, 19, 20, 21, 22, 23, \
336 24, 25, 26, 27, 28, 29, 30, 31, \
337 15, 32, 33, 34 }
338
339
340 /* Fitting values into registers. */
341
342 /* Integer modes <= word size fit into any GPR.
343 Integer modes > word size fit into successive GPRs, starting with
344 an even-numbered register.
345 SImode and DImode fit into FPRs as well.
346
347 Floating point modes <= word size fit into any FPR or GPR.
348 Floating point modes > word size (i.e. DFmode on 32-bit) fit
349 into any FPR, or an even-odd GPR pair.
350
351 Complex floating point modes fit either into two FPRs, or into
352 successive GPRs (again starting with an even number).
353
354 Condition code modes fit only into the CC register. */
355
356 #define HARD_REGNO_NREGS(REGNO, MODE) \
357 (FP_REGNO_P(REGNO)? \
358 (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
359 GENERAL_REGNO_P(REGNO)? \
360 ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \
361 1)
362
363 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
364 (FP_REGNO_P(REGNO)? \
365 ((MODE) == SImode || (MODE) == DImode || \
366 GET_MODE_CLASS(MODE) == MODE_FLOAT || \
367 GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \
368 GENERAL_REGNO_P(REGNO)? \
369 (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \
370 CC_REGNO_P(REGNO)? \
371 GET_MODE_CLASS (MODE) == MODE_CC : \
372 FRAME_REGNO_P(REGNO)? \
373 (enum machine_mode) (MODE) == Pmode : \
374 0)
375
376 #define MODES_TIEABLE_P(MODE1, MODE2) \
377 (((MODE1) == SFmode || (MODE1) == DFmode) \
378 == ((MODE2) == SFmode || (MODE2) == DFmode))
379
380 /* Maximum number of registers to represent a value of mode MODE
381 in a register of class CLASS. */
382 #define CLASS_MAX_NREGS(CLASS, MODE) \
383 ((CLASS) == FP_REGS ? \
384 (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
385 (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
386
387 /* If a 4-byte value is loaded into a FPR, it is placed into the
388 *upper* half of the register, not the lower. Therefore, we
389 cannot use SUBREGs to switch between modes in FP registers. */
390 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
391 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
392 ? reg_classes_intersect_p (FP_REGS, CLASS) : 0)
393
394 /* Register classes. */
395
396 /* We use the following register classes:
397 GENERAL_REGS All general purpose registers
398 ADDR_REGS All general purpose registers except %r0
399 (These registers can be used in address generation)
400 FP_REGS All floating point registers
401
402 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
403 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
404
405 NO_REGS No registers
406 ALL_REGS All registers
407
408 Note that the 'fake' frame pointer and argument pointer registers
409 are included amongst the address registers here. The condition
410 code register is only included in ALL_REGS. */
411
412 enum reg_class
413 {
414 NO_REGS, ADDR_REGS, GENERAL_REGS,
415 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
416 ALL_REGS, LIM_REG_CLASSES
417 };
418 #define N_REG_CLASSES (int) LIM_REG_CLASSES
419
420 #define REG_CLASS_NAMES \
421 { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \
422 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
423
424 /* Class -> register mapping. */
425 #define REG_CLASS_CONTENTS \
426 { \
427 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
428 { 0x0000fffe, 0x00000005 }, /* ADDR_REGS */ \
429 { 0x0000ffff, 0x00000005 }, /* GENERAL_REGS */ \
430 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \
431 { 0xfffffffe, 0x00000005 }, /* ADDR_FP_REGS */ \
432 { 0xffffffff, 0x00000005 }, /* GENERAL_FP_REGS */ \
433 { 0xffffffff, 0x00000007 }, /* ALL_REGS */ \
434 }
435
436 /* Register -> class mapping. */
437 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
438 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
439
440 /* ADDR_REGS can be used as base or index register. */
441 #define INDEX_REG_CLASS ADDR_REGS
442 #define BASE_REG_CLASS ADDR_REGS
443
444 /* Check whether REGNO is a hard register of the suitable class
445 or a pseudo register currently allocated to one such. */
446 #define REGNO_OK_FOR_INDEX_P(REGNO) \
447 (((REGNO) < FIRST_PSEUDO_REGISTER \
448 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
449 || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16))
450 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
451
452
453 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
454 return the class of reg to actually use. */
455 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
456 s390_preferred_reload_class ((X), (CLASS))
457
458 /* We need a secondary reload when loading a PLUS which is
459 not a valid operand for LOAD ADDRESS. */
460 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
461 s390_secondary_input_reload_class ((CLASS), (MODE), (IN))
462
463 /* We need secondary memory to move data between GPRs and FPRs. */
464 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
465 ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS))
466
467 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
468 because the movsi and movsf patterns don't handle r/f moves. */
469 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
470 (GET_MODE_BITSIZE (MODE) < 32 \
471 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
472 : MODE)
473
474
475 /* Define various machine-dependent constraint letters. */
476
477 #define REG_CLASS_FROM_LETTER(C) \
478 ((C) == 'a' ? ADDR_REGS : \
479 (C) == 'd' ? GENERAL_REGS : \
480 (C) == 'f' ? FP_REGS : NO_REGS)
481
482 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
483 ((C) == 'I' ? (unsigned long) (VALUE) < 256 : \
484 (C) == 'J' ? (unsigned long) (VALUE) < 4096 : \
485 (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : \
486 (C) == 'L' ? (unsigned long) (VALUE) < 65536 : 0)
487
488 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
489
490 #define EXTRA_CONSTRAINT(OP, C) \
491 ((C) == 'Q' ? q_constraint (OP) : \
492 (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0)
493
494 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'Q')
495
496
497 /* Stack layout and calling conventions. */
498
499 /* Our stack grows from higher to lower addresses. However, local variables
500 are accessed by positive offsets, and function arguments are stored at
501 increasing addresses. */
502 #define STACK_GROWS_DOWNWARD
503 /* #undef FRAME_GROWS_DOWNWARD */
504 /* #undef ARGS_GROW_DOWNWARD */
505
506 /* The basic stack layout looks like this: the stack pointer points
507 to the register save area for called functions. Above that area
508 is the location to place outgoing arguments. Above those follow
509 dynamic allocations (alloca), and finally the local variables. */
510
511 /* Offset from stack-pointer to first location of outgoing args. */
512 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
513
514 /* Offset within stack frame to start allocating local variables at. */
515 extern int current_function_outgoing_args_size;
516 #define STARTING_FRAME_OFFSET \
517 (STACK_POINTER_OFFSET + current_function_outgoing_args_size)
518
519 /* Offset from the stack pointer register to an item dynamically
520 allocated on the stack, e.g., by `alloca'. */
521 #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET)
522
523 /* Offset of first parameter from the argument pointer register value.
524 We have a fake argument pointer register that points directly to
525 the argument area. */
526 #define FIRST_PARM_OFFSET(FNDECL) 0
527
528 /* The return address of the current frame is retrieved
529 from the initial value of register RETURN_REGNUM.
530 For frames farther back, we use the stack slot where
531 the corresponding RETURN_REGNUM register was saved. */
532
533 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
534 ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \
535 plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
536
537 #define RETURN_ADDR_RTX(COUNT, FRAME) \
538 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
539
540 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
541 #define MASK_RETURN_ADDR (TARGET_64BIT ? GEN_INT (-1) : GEN_INT (0x7fffffff))
542
543
544 /* Exception handling. */
545
546 /* Describe calling conventions for DWARF-2 exception handling. */
547 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
548 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
549 #define DWARF_FRAME_RETURN_COLUMN 14
550
551 /* Describe how we implement __builtin_eh_return. */
552 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
553 #define EH_RETURN_HANDLER_RTX \
554 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \
555 TARGET_64BIT? -48 : -40))
556
557 /* Select a format to encode pointers in exception handling data. */
558 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
559 (flag_pic \
560 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
561 : DW_EH_PE_absptr)
562
563
564 /* Frame registers. */
565
566 #define STACK_POINTER_REGNUM 15
567 #define FRAME_POINTER_REGNUM 34
568 #define HARD_FRAME_POINTER_REGNUM 11
569 #define ARG_POINTER_REGNUM 32
570
571 /* The static chain must be call-clobbered, but not used for
572 function argument passing. As register 1 is clobbered by
573 the trampoline code, we only have one option. */
574 #define STATIC_CHAIN_REGNUM 0
575
576 /* Number of hardware registers that go into the DWARF-2 unwind info.
577 To avoid ABI incompatibility, this number must not change even as
578 'fake' hard registers are added or removed. */
579 #define DWARF_FRAME_REGISTERS 34
580
581
582 /* Frame pointer and argument pointer elimination. */
583
584 #define FRAME_POINTER_REQUIRED 0
585
586 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0
587
588 #define ELIMINABLE_REGS \
589 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
590 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
591 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
592 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
593
594 #define CAN_ELIMINATE(FROM, TO) (1)
595
596 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
597 { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
598 { (OFFSET) = 0; } \
599 else if ((FROM) == FRAME_POINTER_REGNUM \
600 && (TO) == HARD_FRAME_POINTER_REGNUM) \
601 { (OFFSET) = 0; } \
602 else if ((FROM) == ARG_POINTER_REGNUM \
603 && (TO) == HARD_FRAME_POINTER_REGNUM) \
604 { (OFFSET) = s390_arg_frame_offset (); } \
605 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
606 { (OFFSET) = s390_arg_frame_offset (); } \
607 else \
608 abort(); \
609 }
610
611
612 /* Stack arguments. */
613
614 /* We need current_function_outgoing_args to be valid. */
615 #define ACCUMULATE_OUTGOING_ARGS 1
616
617 /* Return doesn't modify the stack. */
618 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
619
620
621 /* Register arguments. */
622
623 typedef struct s390_arg_structure
624 {
625 int gprs; /* gpr so far */
626 int fprs; /* fpr so far */
627 }
628 CUMULATIVE_ARGS;
629
630 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN) \
631 ((CUM).gprs=0, (CUM).fprs=0)
632
633 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
634 s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
635
636 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
637 s390_function_arg (&CUM, MODE, TYPE, NAMED)
638
639 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
640 s390_function_arg_pass_by_reference (MODE, TYPE)
641
642 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
643
644 /* Arguments can be placed in general registers 2 to 6,
645 or in floating point registers 0 and 2. */
646 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
647 (N) == 16 || (N) == 17)
648
649
650 /* Scalar return values. */
651
652 /* We return scalars in general purpose register 2 for integral values,
653 and floating point register 0 for fp values. */
654 #define FUNCTION_VALUE(VALTYPE, FUNC) \
655 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
656 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
657 || POINTER_TYPE_P (VALTYPE) \
658 ? word_mode : TYPE_MODE (VALTYPE), \
659 TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 16 : 2)
660
661 /* Define how to find the value returned by a library function assuming
662 the value has mode MODE. */
663 #define RET_REG(MODE) ((GET_MODE_CLASS (MODE) == MODE_INT \
664 || TARGET_SOFT_FLOAT ) ? 2 : 16)
665 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RET_REG (MODE))
666
667 /* Only gpr 2 and fpr 0 are ever used as return registers. */
668 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
669
670
671 /* Aggregate return values. */
672
673 /* The definition of this macro implies that there are cases where
674 a scalar value cannot be returned in registers. */
675 #define RETURN_IN_MEMORY(type) \
676 (TYPE_MODE (type) == BLKmode || \
677 GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_INT || \
678 GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT)
679
680 /* Structure value address is passed as invisible first argument (gpr 2). */
681 #define STRUCT_VALUE 0
682
683
684 /* Function entry and exit. */
685
686 /* When returning from a function, the stack pointer does not matter. */
687 #define EXIT_IGNORE_STACK 1
688
689
690 /* Profiling. */
691
692 #define FUNCTION_PROFILER(FILE, LABELNO) \
693 s390_function_profiler ((FILE), ((LABELNO)))
694
695 #define PROFILE_BEFORE_PROLOGUE 1
696
697
698 /* Implementing the varargs macros. */
699
700 #define BUILD_VA_LIST_TYPE(VALIST) \
701 (VALIST) = s390_build_va_list ()
702
703 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
704 s390_va_start (valist, nextarg)
705
706 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
707 s390_va_arg (valist, type)
708
709
710 /* Trampolines for nested functions. */
711
712 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20)
713
714 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
715 s390_initialize_trampoline ((ADDR), (FNADDR), (CXT))
716
717 #define TRAMPOLINE_TEMPLATE(FILE) \
718 s390_trampoline_template (FILE)
719
720
721 /* Library calls. */
722
723 /* We should use memcpy, not bcopy. */
724 #define TARGET_MEM_FUNCTIONS
725
726
727 /* Addressing modes, and classification of registers for them. */
728
729 /* Recognize any constant value that is a valid address. */
730 #define CONSTANT_ADDRESS_P(X) 0
731
732 /* Maximum number of registers that can appear in a valid memory address. */
733 #define MAX_REGS_PER_ADDRESS 2
734
735 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check
736 its validity for a certain class. We have two alternate definitions
737 for each of them. The usual definition accepts all pseudo regs; the
738 other rejects them all. The symbol REG_OK_STRICT causes the latter
739 definition to be used.
740
741 Most source files want to accept pseudo regs in the hope that they will
742 get allocated to the class that the insn wants them to be in.
743 Some source files that are used after register allocation
744 need to be strict. */
745
746 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
747 ((GET_MODE (X) == Pmode) && \
748 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \
749 || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))
750
751 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
752
753 #define REG_OK_FOR_INDEX_STRICT_P(X) \
754 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X))))
755
756 #define REG_OK_FOR_BASE_STRICT_P(X) \
757 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X))))
758
759 #ifndef REG_OK_STRICT
760 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
761 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
762 #else
763 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
764 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
765 #endif
766
767 /* S/390 has no mode dependent addresses. */
768 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
769
770 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
771 valid memory address for an instruction.
772 The MODE argument is the machine mode for the MEM expression
773 that wants to use this address. */
774 #ifdef REG_OK_STRICT
775 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
776 { \
777 if (legitimate_address_p (MODE, X, 1)) \
778 goto ADDR; \
779 }
780 #else
781 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
782 { \
783 if (legitimate_address_p (MODE, X, 0)) \
784 goto ADDR; \
785 }
786 #endif
787
788 /* Try machine-dependent ways of modifying an illegitimate address
789 to be legitimate. If we find one, return the new, valid address.
790 This macro is used in only one place: `memory_address' in explow.c. */
791 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
792 { \
793 (X) = legitimize_address (X, OLDX, MODE); \
794 if (memory_address_p (MODE, X)) \
795 goto WIN; \
796 }
797
798 /* Nonzero if the constant value X is a legitimate general operand.
799 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
800 #define LEGITIMATE_CONSTANT_P(X) \
801 legitimate_constant_p (X)
802
803 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
804 #define SYMBOLIC_CONST(X) \
805 (GET_CODE (X) == SYMBOL_REF \
806 || GET_CODE (X) == LABEL_REF \
807 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
808
809 #define TLS_SYMBOLIC_CONST(X) \
810 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
811 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
812
813
814 /* Condition codes. */
815
816 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
817 return the mode to be used for the comparison. */
818 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
819
820 /* Define the information needed to generate branch and scc insns. This is
821 stored from the compare operation. Note that we can't use "rtx" here
822 since it hasn't been defined! */
823 extern struct rtx_def *s390_compare_op0, *s390_compare_op1;
824
825
826 /* Relative costs of operations. */
827
828 /* On s390, copy between fprs and gprs is expensive. */
829 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
830 (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \
831 && reg_classes_intersect_p ((CLASS2), FP_REGS)) \
832 || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \
833 && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
834
835 /* A C expression for the cost of moving data of mode M between a
836 register and memory. A value of 2 is the default; this cost is
837 relative to those in `REGISTER_MOVE_COST'. */
838 #define MEMORY_MOVE_COST(M, C, I) 1
839
840 /* A C expression for the cost of a branch instruction. A value of 1
841 is the default; other values are interpreted relative to that. */
842 #define BRANCH_COST 1
843
844 /* Nonzero if access to memory by bytes is slow and undesirable. */
845 #define SLOW_BYTE_ACCESS 1
846
847 /* The maximum number of bytes that a single instruction can move quickly
848 between memory and registers or between two memory locations. */
849 #define MOVE_MAX (TARGET_64BIT ? 16 : 8)
850 #define MAX_MOVE_MAX 16
851
852 /* Determine whether to use move_by_pieces or block move insn. */
853 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
854 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
855 || (TARGET_64BIT && (SIZE) == 8) )
856
857 /* Determine whether to use clear_by_pieces or block clear insn. */
858 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
859 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
860 || (TARGET_64BIT && (SIZE) == 8) )
861
862 /* Don't perform CSE on function addresses. */
863 #define NO_FUNCTION_CSE
864
865
866 /* Sections. */
867
868 /* Output before read-only data. */
869 #define TEXT_SECTION_ASM_OP ".text"
870
871 /* Output before writable (initialized) data. */
872 #define DATA_SECTION_ASM_OP ".data"
873
874 /* Output before writable (uninitialized) data. */
875 #define BSS_SECTION_ASM_OP ".bss"
876
877 /* S/390 constant pool breaks the devices in crtstuff.c to control section
878 in where code resides. We have to write it as asm code. */
879 #ifndef __s390x__
880 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
881 asm (SECTION_OP "\n\
882 bras\t%r2,1f\n\
883 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
884 1: l\t%r3,0(%r2)\n\
885 bas\t%r14,0(%r3,%r2)\n\
886 .previous");
887 #endif
888
889
890 /* Position independent code. */
891
892 extern int flag_pic;
893
894 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
895
896 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
897
898
899 /* Assembler file format. */
900
901 /* Character to start a comment. */
902 #define ASM_COMMENT_START "#"
903
904 /* Declare an uninitialized external linkage data object. */
905 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
906 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
907
908 /* Globalizing directive for a label. */
909 #define GLOBAL_ASM_OP ".globl "
910
911 /* Advance the location counter to a multiple of 2**LOG bytes. */
912 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
913 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
914
915 /* Advance the location counter by SIZE bytes. */
916 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
917 fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
918
919 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
920 #define LOCAL_LABEL_PREFIX "."
921
922 /* How to refer to registers in assembler output. This sequence is
923 indexed by compiler's hard-register-number (see above). */
924 #define REGISTER_NAMES \
925 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
926 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
927 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
928 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
929 "%ap", "%cc", "%fp" \
930 }
931
932 /* Emit a dtp-relative reference to a TLS variable. */
933
934 #ifdef HAVE_AS_TLS
935 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
936 s390_output_dwarf_dtprel (FILE, SIZE, X)
937 #endif
938
939 /* Print operand X (an rtx) in assembler syntax to file FILE. */
940 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
941 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
942
943 /* Output an element of a case-vector that is absolute. */
944 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
945 do { \
946 char buf[32]; \
947 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
948 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
949 assemble_name ((FILE), buf); \
950 fputc ('\n', (FILE)); \
951 } while (0)
952
953 /* Output an element of a case-vector that is relative. */
954 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
955 do { \
956 char buf[32]; \
957 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
958 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
959 assemble_name ((FILE), buf); \
960 fputc ('-', (FILE)); \
961 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \
962 assemble_name ((FILE), buf); \
963 fputc ('\n', (FILE)); \
964 } while (0)
965
966
967 /* Constant Pool for all symbols operands which are changed with
968 force_const_mem during insn generation (expand_insn). */
969
970 extern int s390_pool_count;
971 extern int s390_nr_constants;
972
973 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, fndecl, size) \
974 { \
975 struct pool_constant *pool; \
976 \
977 if (s390_pool_count == -1) \
978 { \
979 s390_nr_constants = 0; \
980 for (pool = first_pool; pool; pool = pool->next) \
981 if (pool->mark) s390_nr_constants++; \
982 return; \
983 } \
984 }
985
986 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, EXP, MODE, ALIGN, LABELNO, WIN) \
987 { \
988 fprintf (FILE, ".LC%d:\n", LABELNO); \
989 \
990 /* Output the value of the constant itself. */ \
991 switch (GET_MODE_CLASS (MODE)) \
992 { \
993 case MODE_FLOAT: \
994 if (GET_CODE (EXP) != CONST_DOUBLE) \
995 abort (); \
996 \
997 REAL_VALUE_FROM_CONST_DOUBLE (r, EXP); \
998 assemble_real (r, MODE, ALIGN); \
999 break; \
1000 \
1001 case MODE_INT: \
1002 case MODE_PARTIAL_INT: \
1003 if (GET_CODE (EXP) == CONST \
1004 || GET_CODE (EXP) == SYMBOL_REF \
1005 || GET_CODE (EXP) == LABEL_REF) \
1006 { \
1007 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), FILE); \
1008 s390_output_symbolic_const (FILE, EXP); \
1009 fputc ('\n', (FILE)); \
1010 } \
1011 else \
1012 { \
1013 assemble_integer (EXP, GET_MODE_SIZE (MODE), ALIGN, 1); \
1014 if (GET_MODE_SIZE (MODE) == 1) \
1015 ASM_OUTPUT_SKIP ((FILE), (unsigned HOST_WIDE_INT)1); \
1016 } \
1017 break; \
1018 \
1019 default: \
1020 abort (); \
1021 } \
1022 goto WIN; \
1023 }
1024
1025
1026 /* Miscellaneous parameters. */
1027
1028 /* Define the codes that are matched by predicates in aux-output.c. */
1029 #define PREDICATE_CODES \
1030 {"s_operand", { SUBREG, MEM }}, \
1031 {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \
1032 {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \
1033 {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \
1034 {"load_multiple_operation", {PARALLEL}}, \
1035 {"store_multiple_operation", {PARALLEL}}, \
1036 {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \
1037 {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \
1038 CONST_INT, CONST_DOUBLE }}, \
1039 {"s390_plus_operand", { PLUS }},
1040
1041 /* Specify the machine mode that this machine uses for the index in the
1042 tablejump instruction. */
1043 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
1044
1045 /* Load from integral MODE < SI from memory into register makes sign_extend
1046 or zero_extend
1047 In our case sign_extension happens for Halfwords, other no extension. */
1048 #define LOAD_EXTEND_OP(MODE) \
1049 (TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \
1050 (MODE) == HImode ? SIGN_EXTEND : NIL) \
1051 : ((MODE) == HImode ? SIGN_EXTEND : NIL))
1052
1053 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1054 is done just by pretending it is already truncated. */
1055 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1056
1057 /* Specify the machine mode that pointers have.
1058 After generation of rtl, the compiler makes no further distinction
1059 between pointers and any other objects of this machine mode. */
1060 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
1061
1062 /* A function address in a call instruction is a byte address (for
1063 indexing purposes) so give the MEM rtx a byte's mode. */
1064 #define FUNCTION_MODE QImode
1065
1066 /* This macro definition sets up a default value for `main' to return. */
1067 #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node)
1068
1069 /* In rare cases, correct code generation requires extra machine dependent
1070 processing between the second jump optimization pass and delayed branch
1071 scheduling. On those machines, define this macro as a C statement to act on
1072 the code starting at INSN. */
1073 #define MACHINE_DEPENDENT_REORG(INSN) s390_machine_dependent_reorg (INSN)
1074
1075 #endif