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hard-reg-set.h (REG_CANNOT_CHANGE_MODE_P): New.
[gcc.git] / gcc / config / s390 / s390.h
1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com).
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #ifndef _S390_H
23 #define _S390_H
24
25 /* Override the __fixdfdi etc. routines when building libgcc2.
26 ??? This should be done in a cleaner way ... */
27 #ifdef IN_LIBGCC2
28 #include <s390/fixdfdi.h>
29 #endif
30
31
32 /* Run-time target specification. */
33
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do \
37 { \
38 builtin_assert ("cpu=s390"); \
39 builtin_assert ("machine=s390"); \
40 builtin_define ("__s390__"); \
41 if (TARGET_64BIT) \
42 builtin_define ("__s390x__"); \
43 } \
44 while (0)
45
46 /* Optional target features. */
47 extern int target_flags;
48
49 #define TARGET_HARD_FLOAT (target_flags & 1)
50 #define TARGET_SOFT_FLOAT (!(target_flags & 1))
51 #define TARGET_BACKCHAIN (target_flags & 2)
52 #define TARGET_SMALL_EXEC (target_flags & 4)
53 #define TARGET_DEBUG_ARG (target_flags & 8)
54 #define TARGET_64BIT (target_flags & 16)
55 #define TARGET_MVCLE (target_flags & 32)
56
57 /* ??? Once this actually works, it could be made a runtime option. */
58 #define TARGET_IBM_FLOAT 0
59 #define TARGET_IEEE_FLOAT 1
60
61 #ifdef DEFAULT_TARGET_64BIT
62 #define TARGET_DEFAULT 0x13
63 #else
64 #define TARGET_DEFAULT 0x3
65 #endif
66
67 #define TARGET_SWITCHES \
68 { { "hard-float", 1, N_("Use hardware fp")}, \
69 { "soft-float", -1, N_("Don't use hardware fp")}, \
70 { "backchain", 2, N_("Set backchain")}, \
71 { "no-backchain", -2, N_("Don't set backchain (faster, but debug harder")}, \
72 { "small-exec", 4, N_("Use bras for execucable < 64k")}, \
73 { "no-small-exec",-4, N_("Don't use bras")}, \
74 { "debug", 8, N_("Additional debug prints")}, \
75 { "no-debug", -8, N_("Don't print additional debug prints")}, \
76 { "64", 16, N_("64 bit mode")}, \
77 { "31", -16, N_("31 bit mode")}, \
78 { "mvcle", 32, N_("mvcle use")}, \
79 { "no-mvcle", -32, N_("mvc&ex")}, \
80 { "", TARGET_DEFAULT, 0 } }
81
82 /* Target version string. Overridden by the OS header. */
83 #ifdef DEFAULT_TARGET_64BIT
84 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
85 #else
86 #define TARGET_VERSION fprintf (stderr, " (S/390)");
87 #endif
88
89 /* Hooks to override options. */
90 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE)
91 #define OVERRIDE_OPTIONS override_options ()
92
93 /* Frame pointer is not used for debugging. */
94 #define CAN_DEBUG_WITHOUT_FP
95
96
97 /* Target machine storage layout. */
98
99 /* Everything is big-endian. */
100 #define BITS_BIG_ENDIAN 1
101 #define BYTES_BIG_ENDIAN 1
102 #define WORDS_BIG_ENDIAN 1
103
104 /* Width of a word, in units (bytes). */
105 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
106 #define MIN_UNITS_PER_WORD 4
107 #define MAX_BITS_PER_WORD 64
108
109 /* Function arguments and return values are promoted to word size. */
110 #define PROMOTE_FUNCTION_ARGS
111 #define PROMOTE_FUNCTION_RETURN
112 #define PROMOTE_FOR_CALL_ONLY
113
114 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
115 if (INTEGRAL_MODE_P (MODE) && \
116 GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \
117 (MODE) = Pmode; \
118 }
119
120 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
121 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
122
123 /* Boundary (in *bits*) on which stack pointer should be aligned. */
124 #define STACK_BOUNDARY 64
125
126 /* Allocation boundary (in *bits*) for the code of a function. */
127 #define FUNCTION_BOUNDARY 32
128
129 /* There is no point aligning anything to a rounder boundary than this. */
130 #define BIGGEST_ALIGNMENT 64
131
132 /* Alignment of field after `int : 0' in a structure. */
133 #define EMPTY_FIELD_BOUNDARY 32
134
135 /* Alignment on even addresses for LARL instruction. */
136 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
137 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
138
139 /* Alignment is not required by the hardware. */
140 #define STRICT_ALIGNMENT 0
141
142 /* Mode of stack savearea.
143 FUNCTION is VOIDmode because calling convention maintains SP.
144 BLOCK needs Pmode for SP.
145 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
146 #define STACK_SAVEAREA_MODE(LEVEL) \
147 (LEVEL == SAVE_FUNCTION ? VOIDmode \
148 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
149
150 /* Define target floating point format. */
151 #define TARGET_FLOAT_FORMAT \
152 (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT)
153
154
155 /* Type layout. */
156
157 /* Sizes in bits of the source language data types. */
158 #define SHORT_TYPE_SIZE 16
159 #define INT_TYPE_SIZE 32
160 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
161 #define MAX_LONG_TYPE_SIZE 64
162 #define LONG_LONG_TYPE_SIZE 64
163 #define FLOAT_TYPE_SIZE 32
164 #define DOUBLE_TYPE_SIZE 64
165 #define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */
166
167 /* We use "unsigned char" as default. */
168 #define DEFAULT_SIGNED_CHAR 0
169
170
171 /* Register usage. */
172
173 /* We have 16 general purpose registers (registers 0-15),
174 and 16 floating point registers (registers 16-31).
175 (On non-IEEE machines, we have only 4 fp registers.)
176
177 Amongst the general purpose registers, some are used
178 for specific purposes:
179 GPR 11: Hard frame pointer (if needed)
180 GPR 12: Global offset table pointer (if needed)
181 GPR 13: Literal pool base register
182 GPR 14: Return address register
183 GPR 15: Stack pointer
184
185 Registers 32-34 are 'fake' hard registers that do not
186 correspond to actual hardware:
187 Reg 32: Argument pointer
188 Reg 33: Condition code
189 Reg 34: Frame pointer */
190
191 #define FIRST_PSEUDO_REGISTER 35
192
193 /* Standard register usage. */
194 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
195 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
196 #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
197 #define CC_REGNO_P(N) ((N) == 33)
198
199 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
200 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
201 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
202 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
203
204 #define BASE_REGISTER 13
205 #define RETURN_REGNUM 14
206 #define CC_REGNUM 33
207
208 /* Set up fixed registers and calling convention:
209
210 GPRs 0-5 are always call-clobbered,
211 GPRs 6-15 are always call-saved.
212 GPR 12 is fixed if used as GOT pointer.
213 GPR 13 is always fixed (as literal pool pointer).
214 GPR 14 is always fixed (as return address).
215 GPR 15 is always fixed (as stack pointer).
216 The 'fake' hard registers are call-clobbered and fixed.
217
218 On 31-bit, FPRs 18-19 are call-clobbered;
219 on 64-bit, FPRs 24-31 are call-clobbered.
220 The remaining FPRs are call-saved. */
221
222 #define FIXED_REGISTERS \
223 { 0, 0, 0, 0, \
224 0, 0, 0, 0, \
225 0, 0, 0, 0, \
226 0, 1, 1, 1, \
227 0, 0, 0, 0, \
228 0, 0, 0, 0, \
229 0, 0, 0, 0, \
230 0, 0, 0, 0, \
231 1, 1, 1 }
232
233 #define CALL_USED_REGISTERS \
234 { 1, 1, 1, 1, \
235 1, 1, 0, 0, \
236 0, 0, 0, 0, \
237 0, 1, 1, 1, \
238 1, 1, 1, 1, \
239 1, 1, 1, 1, \
240 1, 1, 1, 1, \
241 1, 1, 1, 1, \
242 1, 1, 1 }
243
244 #define CALL_REALLY_USED_REGISTERS \
245 { 1, 1, 1, 1, \
246 1, 1, 0, 0, \
247 0, 0, 0, 0, \
248 0, 0, 0, 0, \
249 1, 1, 1, 1, \
250 1, 1, 1, 1, \
251 1, 1, 1, 1, \
252 1, 1, 1, 1, \
253 1, 1, 1 }
254
255 #define CONDITIONAL_REGISTER_USAGE \
256 do \
257 { \
258 int i; \
259 \
260 if (flag_pic) \
261 { \
262 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
263 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
264 } \
265 if (TARGET_64BIT) \
266 { \
267 for (i = 24; i < 32; i++) \
268 call_used_regs[i] = call_really_used_regs[i] = 0; \
269 } \
270 else \
271 { \
272 for (i = 18; i < 20; i++) \
273 call_used_regs[i] = call_really_used_regs[i] = 0; \
274 } \
275 } while (0)
276
277 /* Preferred register allocation order. */
278 #define REG_ALLOC_ORDER \
279 { 1, 2, 3, 4, 5, 0, 14, 13, 12, 11, 10, 9, 8, 7, 6, \
280 16, 17, 18, 19, 20, 21, 22, 23, \
281 24, 25, 26, 27, 28, 29, 30, 31, \
282 15, 32, 33, 34 }
283
284
285 /* Fitting values into registers. */
286
287 /* Integer modes <= word size fit into any GPR.
288 Integer modes > word size fit into successive GPRs, starting with
289 an even-numbered register.
290 SImode and DImode fit into FPRs as well.
291
292 Floating point modes <= word size fit into any FPR or GPR.
293 Floating point modes > word size (i.e. DFmode on 32-bit) fit
294 into any FPR, or an even-odd GPR pair.
295
296 Complex floating point modes fit either into two FPRs, or into
297 successive GPRs (again starting with an even number).
298
299 Condition code modes fit only into the CC register. */
300
301 #define HARD_REGNO_NREGS(REGNO, MODE) \
302 (FP_REGNO_P(REGNO)? \
303 (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
304 GENERAL_REGNO_P(REGNO)? \
305 ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \
306 1)
307
308 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
309 (FP_REGNO_P(REGNO)? \
310 ((MODE) == SImode || (MODE) == DImode || \
311 GET_MODE_CLASS(MODE) == MODE_FLOAT || \
312 GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \
313 GENERAL_REGNO_P(REGNO)? \
314 (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \
315 CC_REGNO_P(REGNO)? \
316 GET_MODE_CLASS (MODE) == MODE_CC : \
317 0)
318
319 #define MODES_TIEABLE_P(MODE1, MODE2) \
320 (((MODE1) == SFmode || (MODE1) == DFmode) \
321 == ((MODE2) == SFmode || (MODE2) == DFmode))
322
323 /* Maximum number of registers to represent a value of mode MODE
324 in a register of class CLASS. */
325 #define CLASS_MAX_NREGS(CLASS, MODE) \
326 ((CLASS) == FP_REGS ? \
327 (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
328 (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
329
330 /* If a 4-byte value is loaded into a FPR, it is placed into the
331 *upper* half of the register, not the lower. Therefore, we
332 cannot use SUBREGs to switch between modes in FP registers. */
333 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \
334 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) ? FP_REGS : NO_REGS)
335
336 /* Register classes. */
337
338 /* We use the following register classes:
339 GENERAL_REGS All general purpose registers
340 ADDR_REGS All general purpose registers except %r0
341 (These registers can be used in address generation)
342 FP_REGS All floating point registers
343
344 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
345 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
346
347 NO_REGS No registers
348 ALL_REGS All registers
349
350 Note that the 'fake' frame pointer and argument pointer registers
351 are included amongst the address registers here. The condition
352 code register is only included in ALL_REGS. */
353
354 enum reg_class
355 {
356 NO_REGS, ADDR_REGS, GENERAL_REGS,
357 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
358 ALL_REGS, LIM_REG_CLASSES
359 };
360 #define N_REG_CLASSES (int) LIM_REG_CLASSES
361
362 #define REG_CLASS_NAMES \
363 { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \
364 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
365
366 /* Class -> register mapping. */
367 #define REG_CLASS_CONTENTS \
368 { \
369 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
370 { 0x0000fffe, 0x00000005 }, /* ADDR_REGS */ \
371 { 0x0000ffff, 0x00000005 }, /* GENERAL_REGS */ \
372 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \
373 { 0xfffffffe, 0x00000005 }, /* ADDR_FP_REGS */ \
374 { 0xffffffff, 0x00000005 }, /* GENERAL_FP_REGS */ \
375 { 0xffffffff, 0x00000007 }, /* ALL_REGS */ \
376 }
377
378 /* Register -> class mapping. */
379 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
380 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
381
382 /* ADDR_REGS can be used as base or index register. */
383 #define INDEX_REG_CLASS ADDR_REGS
384 #define BASE_REG_CLASS ADDR_REGS
385
386 /* Check whether REGNO is a hard register of the suitable class
387 or a pseudo register currently allocated to one such. */
388 #define REGNO_OK_FOR_INDEX_P(REGNO) \
389 (((REGNO) < FIRST_PSEUDO_REGISTER \
390 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
391 || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16))
392 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
393
394
395 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
396 return the class of reg to actually use. */
397 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
398 s390_preferred_reload_class ((X), (CLASS))
399
400 /* We need a secondary reload when loading a PLUS which is
401 not a valid operand for LOAD ADDRESS. */
402 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
403 s390_secondary_input_reload_class ((CLASS), (MODE), (IN))
404
405 /* We need secondary memory to move data between GPRs and FPRs. */
406 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
407 ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS))
408
409 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
410 because the movsi and movsf patterns don't handle r/f moves. */
411 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
412 (GET_MODE_BITSIZE (MODE) < 32 \
413 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
414 : MODE)
415
416
417 /* Define various machine-dependent constraint letters. */
418
419 #define REG_CLASS_FROM_LETTER(C) \
420 ((C) == 'a' ? ADDR_REGS : \
421 (C) == 'd' ? GENERAL_REGS : \
422 (C) == 'f' ? FP_REGS : NO_REGS)
423
424 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
425 ((C) == 'I' ? (unsigned long) (VALUE) < 256 : \
426 (C) == 'J' ? (unsigned long) (VALUE) < 4096 : \
427 (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : \
428 (C) == 'L' ? (unsigned long) (VALUE) < 65536 : 0)
429
430 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
431
432 #define EXTRA_CONSTRAINT(OP, C) \
433 ((C) == 'Q' ? q_constraint (OP) : \
434 (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0)
435
436 #define EXTRA_MEMORY_CONSTRAINT(C) ((C) == 'Q')
437
438
439 /* Stack layout and calling conventions. */
440
441 /* Our stack grows from higher to lower addresses. However, local variables
442 are accessed by positive offsets, and function arguments are stored at
443 increasing addresses. */
444 #define STACK_GROWS_DOWNWARD
445 /* #undef FRAME_GROWS_DOWNWARD */
446 /* #undef ARGS_GROW_DOWNWARD */
447
448 /* The basic stack layout looks like this: the stack pointer points
449 to the register save area for called functions. Above that area
450 is the location to place outgoing arguments. Above those follow
451 dynamic allocations (alloca), and finally the local variables. */
452
453 /* Offset from stack-pointer to first location of outgoing args. */
454 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
455
456 /* Offset within stack frame to start allocating local variables at. */
457 extern int current_function_outgoing_args_size;
458 #define STARTING_FRAME_OFFSET \
459 (STACK_POINTER_OFFSET + current_function_outgoing_args_size)
460
461 /* Offset from the stack pointer register to an item dynamically
462 allocated on the stack, e.g., by `alloca'. */
463 #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET)
464
465 /* Offset of first parameter from the argument pointer register value.
466 We have a fake argument pointer register that points directly to
467 the argument area. */
468 #define FIRST_PARM_OFFSET(FNDECL) 0
469
470 /* The return address of the current frame is retrieved
471 from the initial value of register RETURN_REGNUM.
472 For frames farther back, we use the stack slot where
473 the corresponding RETURN_REGNUM register was saved. */
474
475 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
476 ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \
477 plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
478
479 #define RETURN_ADDR_RTX(COUNT, FRAME) \
480 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
481
482 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
483 #define MASK_RETURN_ADDR (TARGET_64BIT ? GEN_INT (-1) : GEN_INT (0x7fffffff))
484
485
486 /* Exception handling. */
487
488 /* Describe calling conventions for DWARF-2 exception handling. */
489 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
490 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
491 #define DWARF_FRAME_RETURN_COLUMN 14
492
493 /* Describe how we implement __builtin_eh_return. */
494 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
495 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
496 #define EH_RETURN_HANDLER_RTX \
497 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \
498 TARGET_64BIT? -48 : -40))
499
500
501 /* Frame registers. */
502
503 #define STACK_POINTER_REGNUM 15
504 #define FRAME_POINTER_REGNUM 34
505 #define HARD_FRAME_POINTER_REGNUM 11
506 #define ARG_POINTER_REGNUM 32
507
508 /* The static chain must be call-clobbered, but not used for
509 function argument passing. As register 1 is clobbered by
510 the trampoline code, we only have one option. */
511 #define STATIC_CHAIN_REGNUM 0
512
513 /* Number of hardware registers that go into the DWARF-2 unwind info.
514 To avoid ABI incompatibility, this number must not change even as
515 'fake' hard registers are added or removed. */
516 #define DWARF_FRAME_REGISTERS 34
517
518
519 /* Frame pointer and argument pointer elimination. */
520
521 #define FRAME_POINTER_REQUIRED 0
522
523 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0
524
525 #define ELIMINABLE_REGS \
526 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
527 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
528 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
529 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
530
531 #define CAN_ELIMINATE(FROM, TO) (1)
532
533 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
534 { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
535 { (OFFSET) = 0; } \
536 else if ((FROM) == FRAME_POINTER_REGNUM \
537 && (TO) == HARD_FRAME_POINTER_REGNUM) \
538 { (OFFSET) = 0; } \
539 else if ((FROM) == ARG_POINTER_REGNUM \
540 && (TO) == HARD_FRAME_POINTER_REGNUM) \
541 { (OFFSET) = s390_arg_frame_offset (); } \
542 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
543 { (OFFSET) = s390_arg_frame_offset (); } \
544 else \
545 abort(); \
546 }
547
548
549 /* Stack arguments. */
550
551 /* We need current_function_outgoing_args to be valid. */
552 #define ACCUMULATE_OUTGOING_ARGS 1
553
554 /* Return doesn't modify the stack. */
555 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
556
557
558 /* Register arguments. */
559
560 typedef struct s390_arg_structure
561 {
562 int gprs; /* gpr so far */
563 int fprs; /* fpr so far */
564 }
565 CUMULATIVE_ARGS;
566
567 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN) \
568 ((CUM).gprs=0, (CUM).fprs=0)
569
570 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
571 s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
572
573 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
574 s390_function_arg (&CUM, MODE, TYPE, NAMED)
575
576 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
577 s390_function_arg_pass_by_reference (MODE, TYPE)
578
579 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
580
581 /* Arguments can be placed in general registers 2 to 6,
582 or in floating point registers 0 and 2. */
583 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
584 (N) == 16 || (N) == 17)
585
586
587 /* Scalar return values. */
588
589 /* We return scalars in general purpose register 2 for integral values,
590 and floating point register 0 for fp values. */
591 #define FUNCTION_VALUE(VALTYPE, FUNC) \
592 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
593 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
594 || POINTER_TYPE_P (VALTYPE) \
595 ? word_mode : TYPE_MODE (VALTYPE), \
596 TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 16 : 2)
597
598 /* Define how to find the value returned by a library function assuming
599 the value has mode MODE. */
600 #define RET_REG(MODE) ((GET_MODE_CLASS (MODE) == MODE_INT \
601 || TARGET_SOFT_FLOAT ) ? 2 : 16)
602 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RET_REG (MODE))
603
604 /* Only gpr 2 and fpr 0 are ever used as return registers. */
605 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
606
607
608 /* Aggregate return values. */
609
610 /* The definition of this macro implies that there are cases where
611 a scalar value cannot be returned in registers. */
612 #define RETURN_IN_MEMORY(type) \
613 (TYPE_MODE (type) == BLKmode || \
614 GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_INT || \
615 GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT)
616
617 /* Structure value address is passed as invisible first argument (gpr 2). */
618 #define STRUCT_VALUE 0
619
620
621 /* Function entry and exit. */
622
623 /* When returning from a function, the stack pointer does not matter. */
624 #define EXIT_IGNORE_STACK 1
625
626
627 /* Profiling. */
628
629 #define FUNCTION_PROFILER(FILE, LABELNO) \
630 s390_function_profiler ((FILE), ((LABELNO)))
631
632 #define PROFILE_BEFORE_PROLOGUE 1
633
634
635 /* Implementing the varargs macros. */
636
637 #define BUILD_VA_LIST_TYPE(VALIST) \
638 (VALIST) = s390_build_va_list ()
639
640 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
641 s390_va_start (valist, nextarg)
642
643 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
644 s390_va_arg (valist, type)
645
646
647 /* Trampolines for nested functions. */
648
649 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20)
650
651 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
652 s390_initialize_trampoline ((ADDR), (FNADDR), (CXT))
653
654 #define TRAMPOLINE_TEMPLATE(FILE) \
655 s390_trampoline_template (FILE)
656
657
658 /* Library calls. */
659
660 /* We should use memcpy, not bcopy. */
661 #define TARGET_MEM_FUNCTIONS
662
663
664 /* Addressing modes, and classification of registers for them. */
665
666 /* Recognize any constant value that is a valid address. */
667 #define CONSTANT_ADDRESS_P(X) 0
668
669 /* Maximum number of registers that can appear in a valid memory address. */
670 #define MAX_REGS_PER_ADDRESS 2
671
672 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check
673 its validity for a certain class. We have two alternate definitions
674 for each of them. The usual definition accepts all pseudo regs; the
675 other rejects them all. The symbol REG_OK_STRICT causes the latter
676 definition to be used.
677
678 Most source files want to accept pseudo regs in the hope that they will
679 get allocated to the class that the insn wants them to be in.
680 Some source files that are used after register allocation
681 need to be strict. */
682
683 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
684 ((GET_MODE (X) == Pmode) && \
685 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \
686 || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))
687
688 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
689
690 #define REG_OK_FOR_INDEX_STRICT_P(X) \
691 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X))))
692
693 #define REG_OK_FOR_BASE_STRICT_P(X) \
694 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X))))
695
696 #ifndef REG_OK_STRICT
697 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
698 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
699 #else
700 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
701 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
702 #endif
703
704 /* S/390 has no mode dependent addresses. */
705 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
706
707 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
708 valid memory address for an instruction.
709 The MODE argument is the machine mode for the MEM expression
710 that wants to use this address. */
711 #ifdef REG_OK_STRICT
712 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
713 { \
714 if (legitimate_address_p (MODE, X, 1)) \
715 goto ADDR; \
716 }
717 #else
718 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
719 { \
720 if (legitimate_address_p (MODE, X, 0)) \
721 goto ADDR; \
722 }
723 #endif
724
725 /* Try machine-dependent ways of modifying an illegitimate address
726 to be legitimate. If we find one, return the new, valid address.
727 This macro is used in only one place: `memory_address' in explow.c. */
728 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
729 { \
730 (X) = legitimize_address (X, OLDX, MODE); \
731 if (memory_address_p (MODE, X)) \
732 goto WIN; \
733 }
734
735 /* Nonzero if the constant value X is a legitimate general operand.
736 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
737 #define LEGITIMATE_CONSTANT_P(X) \
738 legitimate_constant_p (X)
739
740 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
741 #define SYMBOLIC_CONST(X) \
742 (GET_CODE (X) == SYMBOL_REF \
743 || GET_CODE (X) == LABEL_REF \
744 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
745
746
747 /* Condition codes. */
748
749 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
750 return the mode to be used for the comparison. */
751 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
752
753 /* Define the information needed to generate branch and scc insns. This is
754 stored from the compare operation. Note that we can't use "rtx" here
755 since it hasn't been defined! */
756 extern struct rtx_def *s390_compare_op0, *s390_compare_op1;
757
758
759 /* Relative costs of operations. */
760
761 /* A part of a C `switch' statement that describes the relative costs
762 of constant RTL expressions. It must contain `case' labels for
763 expression codes `const_int', `const', `symbol_ref', `label_ref'
764 and `const_double'. Each case must ultimately reach a `return'
765 statement to return the relative cost of the use of that kind of
766 constant value in an expression. The cost may depend on the
767 precise value of the constant, which is available for examination
768 in X, and the rtx code of the expression in which it is contained,
769 found in OUTER_CODE.
770
771 CODE is the expression code--redundant, since it can be obtained
772 with `GET_CODE (X)'. */
773 /* Force_const_mem does not work out of reload, because the saveable_obstack
774 is set to reload_obstack, which does not live long enough.
775 Because of this we cannot use force_const_mem in addsi3.
776 This leads to problems with gen_add2_insn with a constant greater
777 than a short. Because of that we give an addition of greater
778 constants a cost of 3 (reload1.c 10096). */
779
780 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
781 case CONST: \
782 if ((GET_CODE (XEXP (RTX, 0)) == MINUS) && \
783 (GET_CODE (XEXP (XEXP (RTX, 0), 1)) != CONST_INT)) \
784 return 1000; \
785 case CONST_INT: \
786 if ((OUTER_CODE == PLUS) && \
787 ((INTVAL (RTX) > 32767) || \
788 (INTVAL (RTX) < -32768))) \
789 return COSTS_N_INSNS (3); \
790 case LABEL_REF: \
791 case SYMBOL_REF: \
792 case CONST_DOUBLE: \
793 return 0; \
794
795
796 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
797 This can be used, for example, to indicate how costly a multiply
798 instruction is. In writing this macro, you can use the construct
799 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
800 instructions. OUTER_CODE is the code of the expression in which X
801 is contained. */
802
803 #define RTX_COSTS(X, CODE, OUTER_CODE) \
804 case ASHIFT: \
805 case ASHIFTRT: \
806 case LSHIFTRT: \
807 case PLUS: \
808 case AND: \
809 case IOR: \
810 case XOR: \
811 case MINUS: \
812 case NEG: \
813 case NOT: \
814 return COSTS_N_INSNS (1); \
815 case MULT: \
816 if (GET_MODE (XEXP (X, 0)) == DImode) \
817 return COSTS_N_INSNS (40); \
818 else \
819 return COSTS_N_INSNS (7); \
820 case DIV: \
821 case UDIV: \
822 case MOD: \
823 case UMOD: \
824 return COSTS_N_INSNS (33);
825
826
827 /* An expression giving the cost of an addressing mode that contains
828 ADDRESS. If not defined, the cost is computed from the ADDRESS
829 expression and the `CONST_COSTS' values. */
830 #define ADDRESS_COST(RTX) s390_address_cost ((RTX))
831
832 /* On s390, copy between fprs and gprs is expensive. */
833 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
834 (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \
835 && reg_classes_intersect_p ((CLASS2), FP_REGS)) \
836 || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \
837 && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
838
839 /* A C expression for the cost of moving data of mode M between a
840 register and memory. A value of 2 is the default; this cost is
841 relative to those in `REGISTER_MOVE_COST'. */
842 #define MEMORY_MOVE_COST(M, C, I) 1
843
844 /* A C expression for the cost of a branch instruction. A value of 1
845 is the default; other values are interpreted relative to that. */
846 #define BRANCH_COST 1
847
848 /* Nonzero if access to memory by bytes is slow and undesirable. */
849 #define SLOW_BYTE_ACCESS 1
850
851 /* The maximum number of bytes that a single instruction can move quickly
852 between memory and registers or between two memory locations. */
853 #define MOVE_MAX (TARGET_64BIT ? 16 : 8)
854 #define MAX_MOVE_MAX 16
855
856 /* Determine whether to use move_by_pieces or block move insn. */
857 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
858 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
859 || (TARGET_64BIT && (SIZE) == 8) )
860
861 /* Determine whether to use clear_by_pieces or block clear insn. */
862 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
863 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
864 || (TARGET_64BIT && (SIZE) == 8) )
865
866 /* Don't perform CSE on function addresses. */
867 #define NO_FUNCTION_CSE
868
869
870 /* Sections. */
871
872 /* Output before read-only data. */
873 #define TEXT_SECTION_ASM_OP ".text"
874
875 /* Output before writable (initialized) data. */
876 #define DATA_SECTION_ASM_OP ".data"
877
878 /* Output before writable (uninitialized) data. */
879 #define BSS_SECTION_ASM_OP ".bss"
880
881 /* S/390 constant pool breaks the devices in crtstuff.c to control section
882 in where code resides. We have to write it as asm code. */
883 #ifndef __s390x__
884 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
885 asm (SECTION_OP "\n\
886 bras\t%r2,1f\n\
887 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
888 1: l\t%r3,0(%r2)\n\
889 bas\t%r14,0(%r3,%r2)\n\
890 .previous");
891 #endif
892
893
894 /* Position independent code. */
895
896 extern int flag_pic;
897
898 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
899
900 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
901
902
903 /* Assembler file format. */
904
905 /* Character to start a comment. */
906 #define ASM_COMMENT_START "#"
907
908 /* Declare an uninitialized external linkage data object. */
909 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
910 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
911
912 /* Globalizing directive for a label. */
913 #define GLOBAL_ASM_OP ".globl "
914
915 /* Advance the location counter to a multiple of 2**LOG bytes. */
916 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
917 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
918
919 /* Advance the location counter by SIZE bytes. */
920 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
921 fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE))
922
923 /* Store in OUTPUT a string (made with alloca) containing
924 an assembler-name for a local static variable named NAME.
925 LABELNO is an integer which is different for each call. */
926 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
927 ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
928 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
929
930 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
931 #define LOCAL_LABEL_PREFIX "."
932
933 /* Either simplify a location expression, or return the original. */
934 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
935 s390_simplify_dwarf_addr (X)
936
937 /* How to refer to registers in assembler output. This sequence is
938 indexed by compiler's hard-register-number (see above). */
939 #define REGISTER_NAMES \
940 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
941 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
942 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
943 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
944 "%ap", "%cc", "%fp" \
945 }
946
947 /* Print operand X (an rtx) in assembler syntax to file FILE. */
948 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
949 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
950
951 /* Output an element of a case-vector that is absolute. */
952 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
953 do { \
954 char buf[32]; \
955 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
956 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
957 assemble_name ((FILE), buf); \
958 fputc ('\n', (FILE)); \
959 } while (0)
960
961 /* Output an element of a case-vector that is relative. */
962 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
963 do { \
964 char buf[32]; \
965 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
966 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
967 assemble_name ((FILE), buf); \
968 fputc ('-', (FILE)); \
969 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \
970 assemble_name ((FILE), buf); \
971 fputc ('\n', (FILE)); \
972 } while (0)
973
974
975 /* Constant Pool for all symbols operands which are changed with
976 force_const_mem during insn generation (expand_insn). */
977
978 extern int s390_pool_count;
979 extern int s390_nr_constants;
980
981 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, fndecl, size) \
982 { \
983 struct pool_constant *pool; \
984 \
985 if (s390_pool_count == -1) \
986 { \
987 s390_nr_constants = 0; \
988 for (pool = first_pool; pool; pool = pool->next) \
989 if (pool->mark) s390_nr_constants++; \
990 return; \
991 } \
992 }
993
994 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, EXP, MODE, ALIGN, LABELNO, WIN) \
995 { \
996 fprintf (FILE, ".LC%d:\n", LABELNO); \
997 \
998 /* Output the value of the constant itself. */ \
999 switch (GET_MODE_CLASS (MODE)) \
1000 { \
1001 case MODE_FLOAT: \
1002 if (GET_CODE (EXP) != CONST_DOUBLE) \
1003 abort (); \
1004 \
1005 REAL_VALUE_FROM_CONST_DOUBLE (r, EXP); \
1006 assemble_real (r, MODE, ALIGN); \
1007 break; \
1008 \
1009 case MODE_INT: \
1010 case MODE_PARTIAL_INT: \
1011 if (flag_pic \
1012 && (GET_CODE (EXP) == CONST \
1013 || GET_CODE (EXP) == SYMBOL_REF \
1014 || GET_CODE (EXP) == LABEL_REF )) \
1015 { \
1016 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), FILE); \
1017 s390_output_symbolic_const (FILE, EXP); \
1018 fputc ('\n', (FILE)); \
1019 } \
1020 else \
1021 { \
1022 assemble_integer (EXP, GET_MODE_SIZE (MODE), ALIGN, 1); \
1023 if (GET_MODE_SIZE (MODE) == 1) \
1024 ASM_OUTPUT_SKIP ((FILE), 1); \
1025 } \
1026 break; \
1027 \
1028 default: \
1029 abort (); \
1030 } \
1031 goto WIN; \
1032 }
1033
1034
1035 /* Miscellaneous parameters. */
1036
1037 /* Define the codes that are matched by predicates in aux-output.c. */
1038 #define PREDICATE_CODES \
1039 {"s_operand", { SUBREG, MEM }}, \
1040 {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \
1041 {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \
1042 {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \
1043 {"load_multiple_operation", {PARALLEL}}, \
1044 {"store_multiple_operation", {PARALLEL}}, \
1045 {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \
1046 {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \
1047 CONST_INT, CONST_DOUBLE }}, \
1048 {"s390_plus_operand", { PLUS }},
1049
1050 /* Specify the machine mode that this machine uses for the index in the
1051 tablejump instruction. */
1052 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
1053
1054 /* Load from integral MODE < SI from memory into register makes sign_extend
1055 or zero_extend
1056 In our case sign_extension happens for Halfwords, other no extension. */
1057 #define LOAD_EXTEND_OP(MODE) \
1058 (TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \
1059 (MODE) == HImode ? SIGN_EXTEND : NIL) \
1060 : ((MODE) == HImode ? SIGN_EXTEND : NIL))
1061
1062 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1063 is done just by pretending it is already truncated. */
1064 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1065
1066 /* Specify the machine mode that pointers have.
1067 After generation of rtl, the compiler makes no further distinction
1068 between pointers and any other objects of this machine mode. */
1069 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
1070
1071 /* A function address in a call instruction is a byte address (for
1072 indexing purposes) so give the MEM rtx a byte's mode. */
1073 #define FUNCTION_MODE QImode
1074
1075 /* This macro definition sets up a default value for `main' to return. */
1076 #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node)
1077
1078 /* In rare cases, correct code generation requires extra machine dependent
1079 processing between the second jump optimization pass and delayed branch
1080 scheduling. On those machines, define this macro as a C statement to act on
1081 the code starting at INSN. */
1082 #define MACHINE_DEPENDENT_REORG(INSN) s390_machine_dependent_reorg (INSN)
1083
1084 #endif