1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
60 (define_c_enum "unspec" [
68 ; GOT/PLT and lt-relative accesses
89 ; TLS relocation specifiers
105 ; Stack Smashing Protector
109 ; Test Data Class (TDC)
118 ;; UNSPEC_VOLATILE usage
121 (define_c_enum "unspecv" [
148 ; Registers with special meaning
152 ; Sibling call register.
154 ; Literal pool base register.
156 ; Return address register.
158 ; Condition code register.
160 ; Thread local storage pointer register.
164 ; Hardware register names
168 ; General purpose registers
170 ; Floating point registers.
176 ;; PFPO GPR0 argument format
181 ; PFPO operation type
182 (PFPO_CONVERT 0x1000000)
184 (PFPO_OP_TYPE_SF 0x5)
185 (PFPO_OP_TYPE_DF 0x6)
186 (PFPO_OP_TYPE_TF 0x7)
187 (PFPO_OP_TYPE_SD 0x8)
188 (PFPO_OP_TYPE_DD 0x9)
189 (PFPO_OP_TYPE_TD 0xa)
190 ; Bitposition of operand types
191 (PFPO_OP0_TYPE_SHIFT 16)
192 (PFPO_OP1_TYPE_SHIFT 8)
196 ;; Instruction operand type as used in the Principles of Operation.
197 ;; Used to determine defaults for length and other attribute values.
199 (define_attr "op_type"
200 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
203 ;; Instruction type attribute used for scheduling.
205 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
206 cs,vs,store,sem,idiv,
207 imulhi,imulsi,imuldi,
208 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
209 floadtf,floaddf,floadsf,fstoredf,fstoresf,
210 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
211 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
213 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
214 itoftf, itofdf, itofsf, itofdd, itoftd,
215 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
216 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
218 (cond [(eq_attr "op_type" "NN") (const_string "other")
219 (eq_attr "op_type" "SS") (const_string "cs")]
220 (const_string "integer")))
222 ;; Another attribute used for scheduling purposes:
223 ;; agen: Instruction uses the address generation unit
224 ;; reg: Instruction does not use the agen unit
226 (define_attr "atype" "agen,reg"
227 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
229 (const_string "agen")))
231 ;; Properties concerning Z10 execution grouping and value forwarding.
232 ;; z10_super: instruction is superscalar.
233 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
234 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
235 ;; target register. It can forward this value to a second instruction that reads
236 ;; the same register if that second instruction is issued in the same group.
237 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
238 ;; instruction in the S pipe writes to the register, then the T instruction
239 ;; can immediately read the new value.
240 ;; z10_fr: union of Z10_fwd and z10_rec.
241 ;; z10_c: second operand of instruction is a register and read with complemented bits.
243 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
246 (define_attr "z10prop" "none,
247 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
248 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
250 z10_fr, z10_fr_A3, z10_fr_E1,
252 (const_string "none"))
254 ;; Properties concerning Z196 decoding
255 ;; z196_alone: must group alone
256 ;; z196_end: ends a group
257 ;; z196_cracked: instruction is cracked or expanded
258 (define_attr "z196prop" "none,
259 z196_alone, z196_ends,
261 (const_string "none"))
265 (define_attr "length" ""
266 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
267 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
271 ;; Processor type. This attribute must exactly match the processor_type
272 ;; enumeration in s390.h. The current machine description does not
273 ;; distinguish between g5 and g6, but there are differences between the two
274 ;; CPUs could in theory be modeled.
276 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196"
277 (const (symbol_ref "s390_tune_attr")))
279 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196"
280 (const_string "standard"))
282 (define_attr "enabled" ""
283 (cond [(eq_attr "cpu_facility" "standard")
286 (and (eq_attr "cpu_facility" "ieee")
287 (match_test "TARGET_CPU_IEEE_FLOAT"))
290 (and (eq_attr "cpu_facility" "zarch")
291 (match_test "TARGET_ZARCH"))
294 (and (eq_attr "cpu_facility" "longdisp")
295 (match_test "TARGET_LONG_DISPLACEMENT"))
298 (and (eq_attr "cpu_facility" "extimm")
299 (match_test "TARGET_EXTIMM"))
302 (and (eq_attr "cpu_facility" "dfp")
303 (match_test "TARGET_DFP"))
306 (and (eq_attr "cpu_facility" "z10")
307 (match_test "TARGET_Z10"))
310 (and (eq_attr "cpu_facility" "z196")
311 (match_test "TARGET_Z196"))
315 ;; Pipeline description for z900. For lack of anything better,
316 ;; this description is also used for the g5 and g6.
319 ;; Pipeline description for z990, z9-109 and z9-ec.
322 ;; Pipeline description for z10
325 ;; Pipeline description for z196
329 (include "predicates.md")
331 ;; Constraint definitions
332 (include "constraints.md")
339 ;; These mode iterators allow floating point patterns to be generated from the
341 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
342 (SD "TARGET_HARD_DFP")])
343 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
344 (define_mode_iterator FPALL [TF DF SF TD DD SD])
345 (define_mode_iterator BFP [TF DF SF])
346 (define_mode_iterator DFP [TD DD])
347 (define_mode_iterator DFP_ALL [TD DD SD])
348 (define_mode_iterator DSF [DF SF])
349 (define_mode_iterator SD_SF [SF SD])
350 (define_mode_iterator DD_DF [DF DD])
351 (define_mode_iterator TD_TF [TF TD])
353 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
354 ;; from the same template.
355 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
356 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
357 (define_mode_iterator DSI [DI SI])
358 (define_mode_iterator TDI [TI DI])
360 ;; These mode iterators allow :P to be used for patterns that operate on
361 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
362 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
364 ;; These macros refer to the actual word_mode of the configuration.
365 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
366 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
367 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
369 ;; Used by the umul pattern to express modes having half the size.
370 (define_mode_attr DWH [(TI "DI") (DI "SI")])
371 (define_mode_attr dwh [(TI "di") (DI "si")])
373 ;; This mode iterator allows the QI and HI patterns to be defined from
374 ;; the same template.
375 (define_mode_iterator HQI [HI QI])
377 ;; This mode iterator allows the integer patterns to be defined from the
379 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
380 (define_mode_iterator INTALL [TI DI SI HI QI])
381 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
383 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
384 ;; the same template.
385 (define_code_iterator SHIFT [ashift lshiftrt])
387 ;; This iterator and attribute allow to combine most atomic operations.
388 (define_code_iterator ATOMIC [and ior xor plus minus mult])
389 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
390 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
391 (plus "add") (minus "sub") (mult "nand")])
392 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
394 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
395 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
396 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
398 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
399 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
401 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
403 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
404 ;; Likewise for "<RXe>".
405 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
406 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
408 ;; The decimal floating point variants of add, sub, div and mul support 3
409 ;; fp register operands. The following attributes allow to merge the bfp and
410 ;; dfp variants in a single insn definition.
412 ;; This attribute is used to set op_type accordingly.
413 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
414 (DD "RRR") (SD "RRR")])
416 ;; This attribute is used in the operand constraint list in order to have the
417 ;; first and the second operand match for bfp modes.
418 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
420 ;; This attribute is used in the operand list of the instruction to have an
421 ;; additional operand for the dfp instructions.
422 (define_mode_attr op1 [(TF "") (DF "") (SF "")
423 (TD "%1,") (DD "%1,") (SD "%1,")])
426 ;; This attribute is used in the operand constraint list
427 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
428 ;; TFmode values are represented by a fp register pair. Since the
429 ;; sign bit instructions only handle single source and target fp registers
430 ;; these instructions can only be used for TFmode values if the source and
431 ;; target operand uses the same fp register.
432 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
434 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
435 ;; This is used to disable the memory alternative in TFmode patterns.
436 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
438 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
439 ;; within instruction mnemonics.
440 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
442 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
443 ;; modes and to an empty string for bfp modes.
444 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
446 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
447 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
448 ;; version only operates on one register.
449 (define_mode_attr d0 [(DI "d") (SI "0")])
451 ;; In combination with d0 this allows to combine instructions of which the 31bit
452 ;; version only operates on one register. The DImode version needs an additional
453 ;; register for the assembler output.
454 (define_mode_attr 1 [(DI "%1,") (SI "")])
456 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
457 ;; 'ashift' and "srdl" in 'lshiftrt'.
458 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
460 ;; In SHIFT templates, this attribute holds the correct standard name for the
461 ;; pattern itself and the corresponding function calls.
462 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
464 ;; This attribute handles differences in the instruction 'type' and will result
465 ;; in "RRE" for DImode and "RR" for SImode.
466 (define_mode_attr E [(DI "E") (SI "")])
468 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
469 ;; to result in "RXY" for DImode and "RX" for SImode.
470 (define_mode_attr Y [(DI "Y") (SI "")])
472 ;; This attribute handles differences in the instruction 'type' and will result
473 ;; in "RSE" for TImode and "RS" for DImode.
474 (define_mode_attr TE [(TI "E") (DI "")])
476 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
477 ;; and "lcr" in SImode.
478 (define_mode_attr g [(DI "g") (SI "")])
480 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
481 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
482 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
483 ;; variant for long displacements.
484 (define_mode_attr y [(DI "g") (SI "y")])
486 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
487 ;; and "cds" in DImode.
488 (define_mode_attr tg [(TI "g") (DI "")])
490 ;; In TDI templates, a string like "c<d>sg".
491 (define_mode_attr td [(TI "d") (DI "")])
493 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
494 ;; and "cfdbr" in SImode.
495 (define_mode_attr gf [(DI "g") (SI "f")])
497 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
498 ;; and sllk for SI. This way it is possible to merge the new z196 SI
499 ;; 3 operands shift instructions into the existing patterns.
500 (define_mode_attr gk [(DI "g") (SI "k")])
502 ;; ICM mask required to load MODE value into the lowest subreg
503 ;; of a SImode register.
504 (define_mode_attr icm_lo [(HI "3") (QI "1")])
506 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
507 ;; HImode and "llgc" in QImode.
508 (define_mode_attr hc [(HI "h") (QI "c")])
510 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
512 (define_mode_attr DBL [(DI "TI") (SI "DI")])
514 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
515 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
516 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
518 ;; Maximum unsigned integer that fits in MODE.
519 (define_mode_attr max_uint [(HI "65535") (QI "255")])
522 ;;- Compare instructions.
525 ; Test-under-Mask instructions
527 (define_insn "*tmqi_mem"
528 [(set (reg CC_REGNUM)
529 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
530 (match_operand:QI 1 "immediate_operand" "n,n"))
531 (match_operand:QI 2 "immediate_operand" "n,n")))]
532 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
536 [(set_attr "op_type" "SI,SIY")
537 (set_attr "z10prop" "z10_super,z10_super")])
539 (define_insn "*tmdi_reg"
540 [(set (reg CC_REGNUM)
541 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
542 (match_operand:DI 1 "immediate_operand"
543 "N0HD0,N1HD0,N2HD0,N3HD0"))
544 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
546 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
547 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
553 [(set_attr "op_type" "RI")
554 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
556 (define_insn "*tmsi_reg"
557 [(set (reg CC_REGNUM)
558 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
559 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
560 (match_operand:SI 2 "immediate_operand" "n,n")))]
561 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
562 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
566 [(set_attr "op_type" "RI")
567 (set_attr "z10prop" "z10_super,z10_super")])
569 (define_insn "*tm<mode>_full"
570 [(set (reg CC_REGNUM)
571 (compare (match_operand:HQI 0 "register_operand" "d")
572 (match_operand:HQI 1 "immediate_operand" "n")))]
573 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
575 [(set_attr "op_type" "RI")
576 (set_attr "z10prop" "z10_super")])
580 ; Load-and-Test instructions
583 ; tst(di|si) instruction pattern(s).
585 (define_insn "*tstdi_sign"
586 [(set (reg CC_REGNUM)
590 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
591 (const_int 32)) (const_int 32))
592 (match_operand:DI 1 "const0_operand" "")))
593 (set (match_operand:DI 2 "register_operand" "=d,d")
594 (sign_extend:DI (match_dup 0)))]
595 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
598 [(set_attr "op_type" "RRE,RXY")
599 (set_attr "cpu_facility" "*,z10")
600 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
603 (define_insn "*tst<mode>_extimm"
604 [(set (reg CC_REGNUM)
605 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
606 (match_operand:GPR 1 "const0_operand" "")))
607 (set (match_operand:GPR 2 "register_operand" "=d,d")
609 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
613 [(set_attr "op_type" "RR<E>,RXY")
614 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
617 (define_insn "*tst<mode>_cconly_extimm"
618 [(set (reg CC_REGNUM)
619 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
620 (match_operand:GPR 1 "const0_operand" "")))
621 (clobber (match_scratch:GPR 2 "=X,d"))]
622 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
626 [(set_attr "op_type" "RR<E>,RXY")
627 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
629 (define_insn "*tstdi"
630 [(set (reg CC_REGNUM)
631 (compare (match_operand:DI 0 "register_operand" "d")
632 (match_operand:DI 1 "const0_operand" "")))
633 (set (match_operand:DI 2 "register_operand" "=d")
635 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
637 [(set_attr "op_type" "RRE")
638 (set_attr "z10prop" "z10_fr_E1")])
640 (define_insn "*tstsi"
641 [(set (reg CC_REGNUM)
642 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
643 (match_operand:SI 1 "const0_operand" "")))
644 (set (match_operand:SI 2 "register_operand" "=d,d,d")
646 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
651 [(set_attr "op_type" "RR,RS,RSY")
652 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
654 (define_insn "*tstsi_cconly"
655 [(set (reg CC_REGNUM)
656 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
657 (match_operand:SI 1 "const0_operand" "")))
658 (clobber (match_scratch:SI 2 "=X,d,d"))]
659 "s390_match_ccmode(insn, CCSmode)"
664 [(set_attr "op_type" "RR,RS,RSY")
665 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
667 (define_insn "*tstdi_cconly_31"
668 [(set (reg CC_REGNUM)
669 (compare (match_operand:DI 0 "register_operand" "d")
670 (match_operand:DI 1 "const0_operand" "")))]
671 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
673 [(set_attr "op_type" "RS")
674 (set_attr "atype" "reg")])
677 (define_insn "*tst<mode>_cconly2"
678 [(set (reg CC_REGNUM)
679 (compare (match_operand:GPR 0 "register_operand" "d")
680 (match_operand:GPR 1 "const0_operand" "")))]
681 "s390_match_ccmode(insn, CCSmode)"
683 [(set_attr "op_type" "RR<E>")
684 (set_attr "z10prop" "z10_fr_E1")])
686 ; tst(hi|qi) instruction pattern(s).
688 (define_insn "*tst<mode>CCT"
689 [(set (reg CC_REGNUM)
690 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
691 (match_operand:HQI 1 "const0_operand" "")))
692 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
694 "s390_match_ccmode(insn, CCTmode)"
697 icmy\t%2,<icm_lo>,%S0
699 [(set_attr "op_type" "RS,RSY,RI")
700 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
702 (define_insn "*tsthiCCT_cconly"
703 [(set (reg CC_REGNUM)
704 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
705 (match_operand:HI 1 "const0_operand" "")))
706 (clobber (match_scratch:HI 2 "=d,d,X"))]
707 "s390_match_ccmode(insn, CCTmode)"
712 [(set_attr "op_type" "RS,RSY,RI")
713 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
715 (define_insn "*tstqiCCT_cconly"
716 [(set (reg CC_REGNUM)
717 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
718 (match_operand:QI 1 "const0_operand" "")))]
719 "s390_match_ccmode(insn, CCTmode)"
724 [(set_attr "op_type" "SI,SIY,RI")
725 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
727 (define_insn "*tst<mode>"
728 [(set (reg CC_REGNUM)
729 (compare (match_operand:HQI 0 "s_operand" "Q,S")
730 (match_operand:HQI 1 "const0_operand" "")))
731 (set (match_operand:HQI 2 "register_operand" "=d,d")
733 "s390_match_ccmode(insn, CCSmode)"
736 icmy\t%2,<icm_lo>,%S0"
737 [(set_attr "op_type" "RS,RSY")
738 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
740 (define_insn "*tst<mode>_cconly"
741 [(set (reg CC_REGNUM)
742 (compare (match_operand:HQI 0 "s_operand" "Q,S")
743 (match_operand:HQI 1 "const0_operand" "")))
744 (clobber (match_scratch:HQI 2 "=d,d"))]
745 "s390_match_ccmode(insn, CCSmode)"
748 icmy\t%2,<icm_lo>,%S0"
749 [(set_attr "op_type" "RS,RSY")
750 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
753 ; Compare (equality) instructions
755 (define_insn "*cmpdi_cct"
756 [(set (reg CC_REGNUM)
757 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
758 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
759 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
766 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
767 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
769 (define_insn "*cmpsi_cct"
770 [(set (reg CC_REGNUM)
771 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
772 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
773 "s390_match_ccmode (insn, CCTmode)"
781 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
782 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
784 ; Compare (signed) instructions
786 (define_insn "*cmpdi_ccs_sign"
787 [(set (reg CC_REGNUM)
788 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
790 (match_operand:DI 0 "register_operand" "d, d,d")))]
791 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
796 [(set_attr "op_type" "RRE,RXY,RIL")
797 (set_attr "z10prop" "z10_c,*,*")
798 (set_attr "type" "*,*,larl")])
802 (define_insn "*cmpsi_ccs_sign"
803 [(set (reg CC_REGNUM)
804 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
805 (match_operand:SI 0 "register_operand" "d,d,d")))]
806 "s390_match_ccmode(insn, CCSRmode)"
811 [(set_attr "op_type" "RX,RXY,RIL")
812 (set_attr "cpu_facility" "*,*,z10")
813 (set_attr "type" "*,*,larl")
814 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
816 (define_insn "*cmphi_ccs_z10"
817 [(set (reg CC_REGNUM)
818 (compare (match_operand:HI 0 "s_operand" "Q")
819 (match_operand:HI 1 "immediate_operand" "K")))]
820 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
822 [(set_attr "op_type" "SIL")
823 (set_attr "z196prop" "z196_cracked")])
825 (define_insn "*cmpdi_ccs_signhi_rl"
826 [(set (reg CC_REGNUM)
827 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
828 (match_operand:GPR 0 "register_operand" "d,d")))]
829 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
833 [(set_attr "op_type" "RXY,RIL")
834 (set_attr "type" "*,larl")])
836 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
837 (define_insn "*cmp<mode>_ccs"
838 [(set (reg CC_REGNUM)
839 (compare (match_operand:GPR 0 "nonimmediate_operand"
841 (match_operand:GPR 1 "general_operand"
843 "s390_match_ccmode(insn, CCSmode)"
852 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
853 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
854 (set_attr "type" "*,*,*,*,*,*,larl")
855 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
858 ; Compare (unsigned) instructions
860 (define_insn "*cmpsi_ccu_zerohi_rlsi"
861 [(set (reg CC_REGNUM)
862 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
863 "larl_operand" "X")))
864 (match_operand:SI 0 "register_operand" "d")))]
865 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
867 [(set_attr "op_type" "RIL")
868 (set_attr "type" "larl")
869 (set_attr "z10prop" "z10_super")])
872 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
873 [(set (reg CC_REGNUM)
874 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
875 "larl_operand" "X")))
876 (match_operand:GPR 0 "register_operand" "d")))]
877 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
879 [(set_attr "op_type" "RIL")
880 (set_attr "type" "larl")
881 (set_attr "z10prop" "z10_super")])
883 (define_insn "*cmpdi_ccu_zero"
884 [(set (reg CC_REGNUM)
885 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
887 (match_operand:DI 0 "register_operand" "d, d,d")))]
888 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
893 [(set_attr "op_type" "RRE,RXY,RIL")
894 (set_attr "cpu_facility" "*,*,z10")
895 (set_attr "type" "*,*,larl")
896 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
898 (define_insn "*cmpdi_ccu"
899 [(set (reg CC_REGNUM)
900 (compare (match_operand:DI 0 "nonimmediate_operand"
902 (match_operand:DI 1 "general_operand"
903 "d,Op,b,D,RT,BQ,Q")))]
904 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
913 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
914 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
915 (set_attr "type" "*,*,larl,*,*,*,*")
916 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
918 (define_insn "*cmpsi_ccu"
919 [(set (reg CC_REGNUM)
920 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
921 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
922 "s390_match_ccmode (insn, CCUmode)"
932 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
933 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
934 (set_attr "type" "*,*,larl,*,*,*,*,*")
935 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
937 (define_insn "*cmphi_ccu"
938 [(set (reg CC_REGNUM)
939 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
940 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
941 "s390_match_ccmode (insn, CCUmode)
942 && !register_operand (operands[1], HImode)"
949 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
950 (set_attr "cpu_facility" "*,*,z10,*,*")
951 (set_attr "z10prop" "*,*,z10_super,*,*")])
953 (define_insn "*cmpqi_ccu"
954 [(set (reg CC_REGNUM)
955 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
956 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
957 "s390_match_ccmode (insn, CCUmode)
958 && !register_operand (operands[1], QImode)"
966 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
967 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
970 ; Block compare (CLC) instruction patterns.
973 [(set (reg CC_REGNUM)
974 (compare (match_operand:BLK 0 "memory_operand" "Q")
975 (match_operand:BLK 1 "memory_operand" "Q")))
976 (use (match_operand 2 "const_int_operand" "n"))]
977 "s390_match_ccmode (insn, CCUmode)
978 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
979 "clc\t%O0(%2,%R0),%S1"
980 [(set_attr "op_type" "SS")])
983 [(set (reg CC_REGNUM)
984 (compare (match_operand 0 "memory_operand" "")
985 (match_operand 1 "memory_operand" "")))]
987 && s390_match_ccmode (insn, CCUmode)
988 && GET_MODE (operands[0]) == GET_MODE (operands[1])
989 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
991 [(set (match_dup 0) (match_dup 1))
992 (use (match_dup 2))])]
994 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
995 operands[0] = adjust_address (operands[0], BLKmode, 0);
996 operands[1] = adjust_address (operands[1], BLKmode, 0);
998 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
999 operands[0], operands[1]);
1000 operands[0] = SET_DEST (PATTERN (curr_insn));
1004 ; (TF|DF|SF|TD|DD|SD) instructions
1006 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1007 (define_insn "*cmp<mode>_ccs_0"
1008 [(set (reg CC_REGNUM)
1009 (compare (match_operand:FP 0 "register_operand" "f")
1010 (match_operand:FP 1 "const0_operand" "")))]
1011 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1012 "lt<xde><bt>r\t%0,%0"
1013 [(set_attr "op_type" "RRE")
1014 (set_attr "type" "fsimp<mode>")])
1016 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1017 (define_insn "*cmp<mode>_ccs"
1018 [(set (reg CC_REGNUM)
1019 (compare (match_operand:FP 0 "register_operand" "f,f")
1020 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1021 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1025 [(set_attr "op_type" "RRE,RXE")
1026 (set_attr "type" "fsimp<mode>")])
1029 ; Compare and Branch instructions
1031 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1032 ; The following instructions do a complementary access of their second
1033 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1034 (define_insn "*cmp_and_br_signed_<mode>"
1036 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1037 [(match_operand:GPR 1 "register_operand" "d,d")
1038 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1039 (label_ref (match_operand 3 "" ""))
1041 (clobber (reg:CC CC_REGNUM))]
1042 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1044 if (get_attr_length (insn) == 6)
1045 return which_alternative ?
1046 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1048 return which_alternative ?
1049 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1051 [(set_attr "op_type" "RIE")
1052 (set_attr "type" "branch")
1053 (set_attr "z10prop" "z10_super_c,z10_super")
1054 (set (attr "length")
1055 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1056 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1057 ; 10 byte for cgr/jg
1059 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1060 ; The following instructions do a complementary access of their second
1061 ; operand (z10 only): clrj, clgrj, clr, clgr
1062 (define_insn "*cmp_and_br_unsigned_<mode>"
1064 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1065 [(match_operand:GPR 1 "register_operand" "d,d")
1066 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1067 (label_ref (match_operand 3 "" ""))
1069 (clobber (reg:CC CC_REGNUM))]
1070 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1072 if (get_attr_length (insn) == 6)
1073 return which_alternative ?
1074 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1076 return which_alternative ?
1077 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1079 [(set_attr "op_type" "RIE")
1080 (set_attr "type" "branch")
1081 (set_attr "z10prop" "z10_super_c,z10_super")
1082 (set (attr "length")
1083 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1084 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1085 ; 10 byte for clgr/jg
1087 ; And now the same two patterns as above but with a negated CC mask.
1089 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1090 ; The following instructions do a complementary access of their second
1091 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1092 (define_insn "*icmp_and_br_signed_<mode>"
1094 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1095 [(match_operand:GPR 1 "register_operand" "d,d")
1096 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1098 (label_ref (match_operand 3 "" ""))))
1099 (clobber (reg:CC CC_REGNUM))]
1100 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1102 if (get_attr_length (insn) == 6)
1103 return which_alternative ?
1104 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1106 return which_alternative ?
1107 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1109 [(set_attr "op_type" "RIE")
1110 (set_attr "type" "branch")
1111 (set_attr "z10prop" "z10_super_c,z10_super")
1112 (set (attr "length")
1113 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1114 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1115 ; 10 byte for cgr/jg
1117 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1118 ; The following instructions do a complementary access of their second
1119 ; operand (z10 only): clrj, clgrj, clr, clgr
1120 (define_insn "*icmp_and_br_unsigned_<mode>"
1122 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1123 [(match_operand:GPR 1 "register_operand" "d,d")
1124 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1126 (label_ref (match_operand 3 "" ""))))
1127 (clobber (reg:CC CC_REGNUM))]
1128 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1130 if (get_attr_length (insn) == 6)
1131 return which_alternative ?
1132 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1134 return which_alternative ?
1135 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1137 [(set_attr "op_type" "RIE")
1138 (set_attr "type" "branch")
1139 (set_attr "z10prop" "z10_super_c,z10_super")
1140 (set (attr "length")
1141 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1142 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1143 ; 10 byte for clgr/jg
1146 ;;- Move instructions.
1150 ; movti instruction pattern(s).
1153 (define_insn "movti"
1154 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1155 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1162 [(set_attr "op_type" "RSY,RSY,*,*")
1163 (set_attr "type" "lm,stm,*,*")])
1166 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1167 (match_operand:TI 1 "general_operand" ""))]
1168 "TARGET_ZARCH && reload_completed
1169 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1170 [(set (match_dup 2) (match_dup 4))
1171 (set (match_dup 3) (match_dup 5))]
1173 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1174 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1175 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1176 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1180 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1181 (match_operand:TI 1 "general_operand" ""))]
1182 "TARGET_ZARCH && reload_completed
1183 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1184 [(set (match_dup 2) (match_dup 4))
1185 (set (match_dup 3) (match_dup 5))]
1187 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1188 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1189 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1190 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1194 [(set (match_operand:TI 0 "register_operand" "")
1195 (match_operand:TI 1 "memory_operand" ""))]
1196 "TARGET_ZARCH && reload_completed
1197 && !s_operand (operands[1], VOIDmode)"
1198 [(set (match_dup 0) (match_dup 1))]
1200 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1201 addr = gen_lowpart (Pmode, addr);
1202 s390_load_address (addr, XEXP (operands[1], 0));
1203 operands[1] = replace_equiv_address (operands[1], addr);
1208 ; Patterns used for secondary reloads
1211 ; z10 provides move instructions accepting larl memory operands.
1212 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1213 ; These patterns are also used for unaligned SI and DI accesses.
1215 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1216 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1217 (match_operand:INTALL 1 "register_operand" "=d")
1218 (match_operand:P 2 "register_operand" "=&a")])]
1221 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1225 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1226 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1227 (match_operand:INTALL 1 "memory_operand" "")
1228 (match_operand:P 2 "register_operand" "=a")])]
1231 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1235 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1236 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1237 (match_operand:FPALL 1 "register_operand" "=d")
1238 (match_operand:P 2 "register_operand" "=&a")])]
1241 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1245 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1246 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1247 (match_operand:FPALL 1 "memory_operand" "")
1248 (match_operand:P 2 "register_operand" "=a")])]
1251 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1255 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1256 [(parallel [(match_operand:P 0 "register_operand" "=d")
1257 (match_operand:P 1 "larl_operand" "")
1258 (match_operand:P 2 "register_operand" "=a")])]
1261 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1265 ; Handles loading a PLUS (load address) expression
1267 (define_expand "reload<mode>_plus"
1268 [(parallel [(match_operand:P 0 "register_operand" "=a")
1269 (match_operand:P 1 "s390_plus_operand" "")
1270 (match_operand:P 2 "register_operand" "=&a")])]
1273 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1277 ; Handles assessing a non-offsetable memory address
1279 (define_expand "reload<mode>_nonoffmem_in"
1280 [(parallel [(match_operand 0 "register_operand" "")
1281 (match_operand 1 "" "")
1282 (match_operand:P 2 "register_operand" "=&a")])]
1285 gcc_assert (MEM_P (operands[1]));
1286 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1287 operands[1] = replace_equiv_address (operands[1], operands[2]);
1288 emit_move_insn (operands[0], operands[1]);
1292 (define_expand "reload<mode>_nonoffmem_out"
1293 [(parallel [(match_operand 0 "" "")
1294 (match_operand 1 "register_operand" "")
1295 (match_operand:P 2 "register_operand" "=&a")])]
1298 gcc_assert (MEM_P (operands[0]));
1299 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1300 operands[0] = replace_equiv_address (operands[0], operands[2]);
1301 emit_move_insn (operands[0], operands[1]);
1305 (define_expand "reload<mode>_PIC_addr"
1306 [(parallel [(match_operand 0 "register_operand" "=d")
1307 (match_operand 1 "larl_operand" "")
1308 (match_operand:P 2 "register_operand" "=a")])]
1311 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1312 emit_move_insn (operands[0], new_rtx);
1316 ; movdi instruction pattern(s).
1319 (define_expand "movdi"
1320 [(set (match_operand:DI 0 "general_operand" "")
1321 (match_operand:DI 1 "general_operand" ""))]
1324 /* Handle symbolic constants. */
1326 && (SYMBOLIC_CONST (operands[1])
1327 || (GET_CODE (operands[1]) == PLUS
1328 && XEXP (operands[1], 0) == pic_offset_table_rtx
1329 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1330 emit_symbolic_move (operands);
1333 (define_insn "*movdi_larl"
1334 [(set (match_operand:DI 0 "register_operand" "=d")
1335 (match_operand:DI 1 "larl_operand" "X"))]
1337 && !FP_REG_P (operands[0])"
1339 [(set_attr "op_type" "RIL")
1340 (set_attr "type" "larl")
1341 (set_attr "z10prop" "z10_super_A1")])
1343 (define_insn "*movdi_64"
1344 [(set (match_operand:DI 0 "nonimmediate_operand"
1345 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1346 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1347 (match_operand:DI 1 "general_operand"
1348 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1349 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1378 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1379 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1380 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1381 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1383 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1384 z10,*,*,*,*,*,longdisp,*,longdisp,
1386 (set_attr "z10prop" "z10_fwd_A1,
1415 [(set (match_operand:DI 0 "register_operand" "")
1416 (match_operand:DI 1 "register_operand" ""))]
1417 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1418 [(set (match_dup 2) (match_dup 3))
1419 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1420 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1421 "operands[2] = gen_lowpart (SImode, operands[0]);
1422 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1425 [(set (match_operand:DI 0 "register_operand" "")
1426 (match_operand:DI 1 "register_operand" ""))]
1427 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1428 && dead_or_set_p (insn, operands[1])"
1429 [(set (match_dup 3) (match_dup 2))
1430 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1431 (set (match_dup 4) (match_dup 2))]
1432 "operands[2] = gen_lowpart (SImode, operands[1]);
1433 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1436 [(set (match_operand:DI 0 "register_operand" "")
1437 (match_operand:DI 1 "register_operand" ""))]
1438 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1439 && !dead_or_set_p (insn, operands[1])"
1440 [(set (match_dup 3) (match_dup 2))
1441 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1442 (set (match_dup 4) (match_dup 2))
1443 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1444 "operands[2] = gen_lowpart (SImode, operands[1]);
1445 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1447 (define_insn "*movdi_31"
1448 [(set (match_operand:DI 0 "nonimmediate_operand"
1449 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1450 (match_operand:DI 1 "general_operand"
1451 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1466 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1467 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1468 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1470 ; For a load from a symbol ref we can use one of the target registers
1471 ; together with larl to load the address.
1473 [(set (match_operand:DI 0 "register_operand" "")
1474 (match_operand:DI 1 "memory_operand" ""))]
1475 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1476 && larl_operand (XEXP (operands[1], 0), SImode)"
1477 [(set (match_dup 2) (match_dup 3))
1478 (set (match_dup 0) (match_dup 1))]
1480 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1481 operands[3] = XEXP (operands[1], 0);
1482 operands[1] = replace_equiv_address (operands[1], operands[2]);
1486 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1487 (match_operand:DI 1 "general_operand" ""))]
1488 "!TARGET_ZARCH && reload_completed
1489 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1490 [(set (match_dup 2) (match_dup 4))
1491 (set (match_dup 3) (match_dup 5))]
1493 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1494 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1495 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1496 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1500 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1501 (match_operand:DI 1 "general_operand" ""))]
1502 "!TARGET_ZARCH && reload_completed
1503 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1504 [(set (match_dup 2) (match_dup 4))
1505 (set (match_dup 3) (match_dup 5))]
1507 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1508 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1509 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1510 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1514 [(set (match_operand:DI 0 "register_operand" "")
1515 (match_operand:DI 1 "memory_operand" ""))]
1516 "!TARGET_ZARCH && reload_completed
1517 && !FP_REG_P (operands[0])
1518 && !s_operand (operands[1], VOIDmode)"
1519 [(set (match_dup 0) (match_dup 1))]
1521 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1522 s390_load_address (addr, XEXP (operands[1], 0));
1523 operands[1] = replace_equiv_address (operands[1], addr);
1527 [(set (match_operand:DI 0 "register_operand" "")
1528 (mem:DI (match_operand 1 "address_operand" "")))]
1530 && !FP_REG_P (operands[0])
1531 && GET_CODE (operands[1]) == SYMBOL_REF
1532 && CONSTANT_POOL_ADDRESS_P (operands[1])
1533 && get_pool_mode (operands[1]) == DImode
1534 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1535 [(set (match_dup 0) (match_dup 2))]
1536 "operands[2] = get_pool_constant (operands[1]);")
1538 (define_insn "*la_64"
1539 [(set (match_operand:DI 0 "register_operand" "=d,d")
1540 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1545 [(set_attr "op_type" "RX,RXY")
1546 (set_attr "type" "la")
1547 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1551 [(set (match_operand:DI 0 "register_operand" "")
1552 (match_operand:QI 1 "address_operand" ""))
1553 (clobber (reg:CC CC_REGNUM))])]
1555 && preferred_la_operand_p (operands[1], const0_rtx)"
1556 [(set (match_dup 0) (match_dup 1))]
1560 [(set (match_operand:DI 0 "register_operand" "")
1561 (match_operand:DI 1 "register_operand" ""))
1564 (plus:DI (match_dup 0)
1565 (match_operand:DI 2 "nonmemory_operand" "")))
1566 (clobber (reg:CC CC_REGNUM))])]
1568 && !reg_overlap_mentioned_p (operands[0], operands[2])
1569 && preferred_la_operand_p (operands[1], operands[2])"
1570 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1574 ; movsi instruction pattern(s).
1577 (define_expand "movsi"
1578 [(set (match_operand:SI 0 "general_operand" "")
1579 (match_operand:SI 1 "general_operand" ""))]
1582 /* Handle symbolic constants. */
1584 && (SYMBOLIC_CONST (operands[1])
1585 || (GET_CODE (operands[1]) == PLUS
1586 && XEXP (operands[1], 0) == pic_offset_table_rtx
1587 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1588 emit_symbolic_move (operands);
1591 (define_insn "*movsi_larl"
1592 [(set (match_operand:SI 0 "register_operand" "=d")
1593 (match_operand:SI 1 "larl_operand" "X"))]
1594 "!TARGET_64BIT && TARGET_CPU_ZARCH
1595 && !FP_REG_P (operands[0])"
1597 [(set_attr "op_type" "RIL")
1598 (set_attr "type" "larl")
1599 (set_attr "z10prop" "z10_fwd_A1")])
1601 (define_insn "*movsi_zarch"
1602 [(set (match_operand:SI 0 "nonimmediate_operand"
1603 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1604 (match_operand:SI 1 "general_operand"
1605 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1630 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1631 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1632 (set_attr "type" "*,
1654 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1655 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1656 (set_attr "z10prop" "z10_fwd_A1,
1679 (define_insn "*movsi_esa"
1680 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1681 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1695 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1696 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1697 (set_attr "z10prop" "z10_fwd_A1,
1711 [(set (match_operand:SI 0 "register_operand" "")
1712 (mem:SI (match_operand 1 "address_operand" "")))]
1713 "!FP_REG_P (operands[0])
1714 && GET_CODE (operands[1]) == SYMBOL_REF
1715 && CONSTANT_POOL_ADDRESS_P (operands[1])
1716 && get_pool_mode (operands[1]) == SImode
1717 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1718 [(set (match_dup 0) (match_dup 2))]
1719 "operands[2] = get_pool_constant (operands[1]);")
1721 (define_insn "*la_31"
1722 [(set (match_operand:SI 0 "register_operand" "=d,d")
1723 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1724 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1728 [(set_attr "op_type" "RX,RXY")
1729 (set_attr "type" "la")
1730 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1734 [(set (match_operand:SI 0 "register_operand" "")
1735 (match_operand:QI 1 "address_operand" ""))
1736 (clobber (reg:CC CC_REGNUM))])]
1738 && preferred_la_operand_p (operands[1], const0_rtx)"
1739 [(set (match_dup 0) (match_dup 1))]
1743 [(set (match_operand:SI 0 "register_operand" "")
1744 (match_operand:SI 1 "register_operand" ""))
1747 (plus:SI (match_dup 0)
1748 (match_operand:SI 2 "nonmemory_operand" "")))
1749 (clobber (reg:CC CC_REGNUM))])]
1751 && !reg_overlap_mentioned_p (operands[0], operands[2])
1752 && preferred_la_operand_p (operands[1], operands[2])"
1753 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1756 (define_insn "*la_31_and"
1757 [(set (match_operand:SI 0 "register_operand" "=d,d")
1758 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1759 (const_int 2147483647)))]
1764 [(set_attr "op_type" "RX,RXY")
1765 (set_attr "type" "la")
1766 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1768 (define_insn_and_split "*la_31_and_cc"
1769 [(set (match_operand:SI 0 "register_operand" "=d")
1770 (and:SI (match_operand:QI 1 "address_operand" "p")
1771 (const_int 2147483647)))
1772 (clobber (reg:CC CC_REGNUM))]
1775 "&& reload_completed"
1777 (and:SI (match_dup 1) (const_int 2147483647)))]
1779 [(set_attr "op_type" "RX")
1780 (set_attr "type" "la")])
1782 (define_insn "force_la_31"
1783 [(set (match_operand:SI 0 "register_operand" "=d,d")
1784 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1785 (use (const_int 0))]
1790 [(set_attr "op_type" "RX")
1791 (set_attr "type" "la")
1792 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1795 ; movhi instruction pattern(s).
1798 (define_expand "movhi"
1799 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1800 (match_operand:HI 1 "general_operand" ""))]
1803 /* Make it explicit that loading a register from memory
1804 always sign-extends (at least) to SImode. */
1805 if (optimize && can_create_pseudo_p ()
1806 && register_operand (operands[0], VOIDmode)
1807 && GET_CODE (operands[1]) == MEM)
1809 rtx tmp = gen_reg_rtx (SImode);
1810 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1811 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1812 operands[1] = gen_lowpart (HImode, tmp);
1816 (define_insn "*movhi"
1817 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1818 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1830 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1831 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1832 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1833 (set_attr "z10prop" "z10_fr_E1,
1844 [(set (match_operand:HI 0 "register_operand" "")
1845 (mem:HI (match_operand 1 "address_operand" "")))]
1846 "GET_CODE (operands[1]) == SYMBOL_REF
1847 && CONSTANT_POOL_ADDRESS_P (operands[1])
1848 && get_pool_mode (operands[1]) == HImode
1849 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1850 [(set (match_dup 0) (match_dup 2))]
1851 "operands[2] = get_pool_constant (operands[1]);")
1854 ; movqi instruction pattern(s).
1857 (define_expand "movqi"
1858 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1859 (match_operand:QI 1 "general_operand" ""))]
1862 /* On z/Architecture, zero-extending from memory to register
1863 is just as fast as a QImode load. */
1864 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1865 && register_operand (operands[0], VOIDmode)
1866 && GET_CODE (operands[1]) == MEM)
1868 rtx tmp = gen_reg_rtx (DImode);
1869 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1870 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1871 operands[1] = gen_lowpart (QImode, tmp);
1875 (define_insn "*movqi"
1876 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1877 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1889 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1890 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1891 (set_attr "z10prop" "z10_fr_E1,
1902 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1903 (mem:QI (match_operand 1 "address_operand" "")))]
1904 "GET_CODE (operands[1]) == SYMBOL_REF
1905 && CONSTANT_POOL_ADDRESS_P (operands[1])
1906 && get_pool_mode (operands[1]) == QImode
1907 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1908 [(set (match_dup 0) (match_dup 2))]
1909 "operands[2] = get_pool_constant (operands[1]);")
1912 ; movstrictqi instruction pattern(s).
1915 (define_insn "*movstrictqi"
1916 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1917 (match_operand:QI 1 "memory_operand" "R,T"))]
1922 [(set_attr "op_type" "RX,RXY")
1923 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1926 ; movstricthi instruction pattern(s).
1929 (define_insn "*movstricthi"
1930 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1931 (match_operand:HI 1 "memory_operand" "Q,S"))
1932 (clobber (reg:CC CC_REGNUM))]
1937 [(set_attr "op_type" "RS,RSY")
1938 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1941 ; movstrictsi instruction pattern(s).
1944 (define_insn "movstrictsi"
1945 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1946 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1953 [(set_attr "op_type" "RR,RX,RXY,RRE")
1954 (set_attr "type" "lr,load,load,*")
1955 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1958 ; mov(tf|td) instruction pattern(s).
1961 (define_expand "mov<mode>"
1962 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1963 (match_operand:TD_TF 1 "general_operand" ""))]
1967 (define_insn "*mov<mode>_64"
1968 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1969 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1980 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1981 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
1982 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
1984 (define_insn "*mov<mode>_31"
1985 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1986 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1993 [(set_attr "op_type" "RRE,RRE,*,*")
1994 (set_attr "type" "fsimptf,fsimptf,*,*")
1995 (set_attr "cpu_facility" "z196,*,*,*")])
1997 ; TFmode in GPRs splitters
2000 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2001 (match_operand:TD_TF 1 "general_operand" ""))]
2002 "TARGET_ZARCH && reload_completed
2003 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2004 [(set (match_dup 2) (match_dup 4))
2005 (set (match_dup 3) (match_dup 5))]
2007 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2008 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2009 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2010 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2014 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2015 (match_operand:TD_TF 1 "general_operand" ""))]
2016 "TARGET_ZARCH && reload_completed
2017 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2018 [(set (match_dup 2) (match_dup 4))
2019 (set (match_dup 3) (match_dup 5))]
2021 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2022 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2023 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2024 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2028 [(set (match_operand:TD_TF 0 "register_operand" "")
2029 (match_operand:TD_TF 1 "memory_operand" ""))]
2030 "TARGET_ZARCH && reload_completed
2031 && !FP_REG_P (operands[0])
2032 && !s_operand (operands[1], VOIDmode)"
2033 [(set (match_dup 0) (match_dup 1))]
2035 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2036 addr = gen_lowpart (Pmode, addr);
2037 s390_load_address (addr, XEXP (operands[1], 0));
2038 operands[1] = replace_equiv_address (operands[1], addr);
2041 ; TFmode in BFPs splitters
2044 [(set (match_operand:TD_TF 0 "register_operand" "")
2045 (match_operand:TD_TF 1 "memory_operand" ""))]
2046 "reload_completed && offsettable_memref_p (operands[1])
2047 && FP_REG_P (operands[0])"
2048 [(set (match_dup 2) (match_dup 4))
2049 (set (match_dup 3) (match_dup 5))]
2051 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2053 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2055 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2056 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2060 [(set (match_operand:TD_TF 0 "memory_operand" "")
2061 (match_operand:TD_TF 1 "register_operand" ""))]
2062 "reload_completed && offsettable_memref_p (operands[0])
2063 && FP_REG_P (operands[1])"
2064 [(set (match_dup 2) (match_dup 4))
2065 (set (match_dup 3) (match_dup 5))]
2067 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2068 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2069 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2071 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2076 ; mov(df|dd) instruction pattern(s).
2079 (define_expand "mov<mode>"
2080 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2081 (match_operand:DD_DF 1 "general_operand" ""))]
2085 (define_insn "*mov<mode>_64dfp"
2086 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2087 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2088 (match_operand:DD_DF 1 "general_operand"
2089 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2104 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2105 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2106 fstoredf,fstoredf,*,lr,load,store")
2107 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2108 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2110 (define_insn "*mov<mode>_64"
2111 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2112 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2125 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2126 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2127 fstore<mode>,fstore<mode>,*,lr,load,store")
2128 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2129 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2131 (define_insn "*mov<mode>_31"
2132 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2133 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2134 (match_operand:DD_DF 1 "general_operand"
2135 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2150 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2151 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2152 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2153 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2156 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2157 (match_operand:DD_DF 1 "general_operand" ""))]
2158 "!TARGET_ZARCH && reload_completed
2159 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2160 [(set (match_dup 2) (match_dup 4))
2161 (set (match_dup 3) (match_dup 5))]
2163 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2164 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2165 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2166 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2170 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2171 (match_operand:DD_DF 1 "general_operand" ""))]
2172 "!TARGET_ZARCH && reload_completed
2173 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2174 [(set (match_dup 2) (match_dup 4))
2175 (set (match_dup 3) (match_dup 5))]
2177 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2178 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2179 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2180 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2184 [(set (match_operand:DD_DF 0 "register_operand" "")
2185 (match_operand:DD_DF 1 "memory_operand" ""))]
2186 "!TARGET_ZARCH && reload_completed
2187 && !FP_REG_P (operands[0])
2188 && !s_operand (operands[1], VOIDmode)"
2189 [(set (match_dup 0) (match_dup 1))]
2191 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2192 s390_load_address (addr, XEXP (operands[1], 0));
2193 operands[1] = replace_equiv_address (operands[1], addr);
2197 ; mov(sf|sd) instruction pattern(s).
2200 (define_insn "mov<mode>"
2201 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2202 "=f,f,f,f,R,T,d,d,d,d,R,T")
2203 (match_operand:SD_SF 1 "general_operand"
2204 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2219 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2220 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2221 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2222 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2223 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2226 ; movcc instruction pattern
2229 (define_insn "movcc"
2230 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2231 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2241 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2242 (set_attr "type" "lr,*,*,store,store,load,load")
2243 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2244 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2247 ; Block move (MVC) patterns.
2251 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2252 (match_operand:BLK 1 "memory_operand" "Q"))
2253 (use (match_operand 2 "const_int_operand" "n"))]
2254 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2255 "mvc\t%O0(%2,%R0),%S1"
2256 [(set_attr "op_type" "SS")])
2258 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2259 ; order to have it implemented with mvc.
2262 [(set (match_operand:QI 0 "memory_operand" "")
2263 (match_operand:QI 1 "memory_operand" ""))]
2266 [(set (match_dup 0) (match_dup 1))
2267 (use (const_int 1))])]
2269 operands[0] = adjust_address (operands[0], BLKmode, 0);
2270 operands[1] = adjust_address (operands[1], BLKmode, 0);
2276 [(set (match_operand:BLK 0 "memory_operand" "")
2277 (match_operand:BLK 1 "memory_operand" ""))
2278 (use (match_operand 2 "const_int_operand" ""))])
2280 [(set (match_operand:BLK 3 "memory_operand" "")
2281 (match_operand:BLK 4 "memory_operand" ""))
2282 (use (match_operand 5 "const_int_operand" ""))])]
2283 "s390_offset_p (operands[0], operands[3], operands[2])
2284 && s390_offset_p (operands[1], operands[4], operands[2])
2285 && !s390_overlap_p (operands[0], operands[1],
2286 INTVAL (operands[2]) + INTVAL (operands[5]))
2287 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2289 [(set (match_dup 6) (match_dup 7))
2290 (use (match_dup 8))])]
2291 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2292 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2293 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2297 ; load_multiple pattern(s).
2299 ; ??? Due to reload problems with replacing registers inside match_parallel
2300 ; we currently support load_multiple/store_multiple only after reload.
2303 (define_expand "load_multiple"
2304 [(match_par_dup 3 [(set (match_operand 0 "" "")
2305 (match_operand 1 "" ""))
2306 (use (match_operand 2 "" ""))])]
2309 enum machine_mode mode;
2315 /* Support only loading a constant number of fixed-point registers from
2316 memory and only bother with this if more than two */
2317 if (GET_CODE (operands[2]) != CONST_INT
2318 || INTVAL (operands[2]) < 2
2319 || INTVAL (operands[2]) > 16
2320 || GET_CODE (operands[1]) != MEM
2321 || GET_CODE (operands[0]) != REG
2322 || REGNO (operands[0]) >= 16)
2325 count = INTVAL (operands[2]);
2326 regno = REGNO (operands[0]);
2327 mode = GET_MODE (operands[0]);
2328 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2331 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2332 if (!can_create_pseudo_p ())
2334 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2336 from = XEXP (operands[1], 0);
2339 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2340 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2341 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2343 from = XEXP (XEXP (operands[1], 0), 0);
2344 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2351 from = force_reg (Pmode, XEXP (operands[1], 0));
2355 for (i = 0; i < count; i++)
2356 XVECEXP (operands[3], 0, i)
2357 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2358 change_address (operands[1], mode,
2359 plus_constant (Pmode, from,
2360 off + i * GET_MODE_SIZE (mode))));
2363 (define_insn "*load_multiple_di"
2364 [(match_parallel 0 "load_multiple_operation"
2365 [(set (match_operand:DI 1 "register_operand" "=r")
2366 (match_operand:DI 2 "s_operand" "QS"))])]
2367 "reload_completed && TARGET_ZARCH"
2369 int words = XVECLEN (operands[0], 0);
2370 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2371 return "lmg\t%1,%0,%S2";
2373 [(set_attr "op_type" "RSY")
2374 (set_attr "type" "lm")])
2376 (define_insn "*load_multiple_si"
2377 [(match_parallel 0 "load_multiple_operation"
2378 [(set (match_operand:SI 1 "register_operand" "=r,r")
2379 (match_operand:SI 2 "s_operand" "Q,S"))])]
2382 int words = XVECLEN (operands[0], 0);
2383 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2384 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2386 [(set_attr "op_type" "RS,RSY")
2387 (set_attr "type" "lm")])
2390 ; store multiple pattern(s).
2393 (define_expand "store_multiple"
2394 [(match_par_dup 3 [(set (match_operand 0 "" "")
2395 (match_operand 1 "" ""))
2396 (use (match_operand 2 "" ""))])]
2399 enum machine_mode mode;
2405 /* Support only storing a constant number of fixed-point registers to
2406 memory and only bother with this if more than two. */
2407 if (GET_CODE (operands[2]) != CONST_INT
2408 || INTVAL (operands[2]) < 2
2409 || INTVAL (operands[2]) > 16
2410 || GET_CODE (operands[0]) != MEM
2411 || GET_CODE (operands[1]) != REG
2412 || REGNO (operands[1]) >= 16)
2415 count = INTVAL (operands[2]);
2416 regno = REGNO (operands[1]);
2417 mode = GET_MODE (operands[1]);
2418 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2421 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2423 if (!can_create_pseudo_p ())
2425 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2427 to = XEXP (operands[0], 0);
2430 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2431 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2432 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2434 to = XEXP (XEXP (operands[0], 0), 0);
2435 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2442 to = force_reg (Pmode, XEXP (operands[0], 0));
2446 for (i = 0; i < count; i++)
2447 XVECEXP (operands[3], 0, i)
2448 = gen_rtx_SET (VOIDmode,
2449 change_address (operands[0], mode,
2450 plus_constant (Pmode, to,
2451 off + i * GET_MODE_SIZE (mode))),
2452 gen_rtx_REG (mode, regno + i));
2455 (define_insn "*store_multiple_di"
2456 [(match_parallel 0 "store_multiple_operation"
2457 [(set (match_operand:DI 1 "s_operand" "=QS")
2458 (match_operand:DI 2 "register_operand" "r"))])]
2459 "reload_completed && TARGET_ZARCH"
2461 int words = XVECLEN (operands[0], 0);
2462 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2463 return "stmg\t%2,%0,%S1";
2465 [(set_attr "op_type" "RSY")
2466 (set_attr "type" "stm")])
2469 (define_insn "*store_multiple_si"
2470 [(match_parallel 0 "store_multiple_operation"
2471 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2472 (match_operand:SI 2 "register_operand" "r,r"))])]
2475 int words = XVECLEN (operands[0], 0);
2476 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2477 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2479 [(set_attr "op_type" "RS,RSY")
2480 (set_attr "type" "stm")])
2483 ;; String instructions.
2486 (define_insn "*execute_rl"
2487 [(match_parallel 0 ""
2488 [(unspec [(match_operand 1 "register_operand" "a")
2489 (match_operand 2 "" "")
2490 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2491 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2492 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2494 [(set_attr "op_type" "RIL")
2495 (set_attr "type" "cs")])
2497 (define_insn "*execute"
2498 [(match_parallel 0 ""
2499 [(unspec [(match_operand 1 "register_operand" "a")
2500 (match_operand:BLK 2 "memory_operand" "R")
2501 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2502 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2503 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2505 [(set_attr "op_type" "RX")
2506 (set_attr "type" "cs")])
2510 ; strlenM instruction pattern(s).
2513 (define_expand "strlen<mode>"
2514 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2517 (unspec:P [(const_int 0)
2518 (match_operand:BLK 1 "memory_operand" "")
2520 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2521 (clobber (scratch:P))
2522 (clobber (reg:CC CC_REGNUM))])
2524 [(set (match_operand:P 0 "register_operand" "")
2525 (minus:P (match_dup 4) (match_dup 5)))
2526 (clobber (reg:CC CC_REGNUM))])]
2529 operands[4] = gen_reg_rtx (Pmode);
2530 operands[5] = gen_reg_rtx (Pmode);
2531 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2532 operands[1] = replace_equiv_address (operands[1], operands[5]);
2535 (define_insn "*strlen<mode>"
2536 [(set (match_operand:P 0 "register_operand" "=a")
2537 (unspec:P [(match_operand:P 2 "general_operand" "0")
2538 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2540 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2541 (clobber (match_scratch:P 1 "=a"))
2542 (clobber (reg:CC CC_REGNUM))]
2544 "srst\t%0,%1\;jo\t.-4"
2545 [(set_attr "length" "8")
2546 (set_attr "type" "vs")])
2549 ; cmpstrM instruction pattern(s).
2552 (define_expand "cmpstrsi"
2553 [(set (reg:SI 0) (const_int 0))
2555 [(clobber (match_operand 3 "" ""))
2556 (clobber (match_dup 4))
2557 (set (reg:CCU CC_REGNUM)
2558 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2559 (match_operand:BLK 2 "memory_operand" "")))
2562 [(set (match_operand:SI 0 "register_operand" "=d")
2563 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2564 (clobber (reg:CC CC_REGNUM))])]
2567 /* As the result of CMPINT is inverted compared to what we need,
2568 we have to swap the operands. */
2569 rtx op1 = operands[2];
2570 rtx op2 = operands[1];
2571 rtx addr1 = gen_reg_rtx (Pmode);
2572 rtx addr2 = gen_reg_rtx (Pmode);
2574 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2575 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2576 operands[1] = replace_equiv_address_nv (op1, addr1);
2577 operands[2] = replace_equiv_address_nv (op2, addr2);
2578 operands[3] = addr1;
2579 operands[4] = addr2;
2582 (define_insn "*cmpstr<mode>"
2583 [(clobber (match_operand:P 0 "register_operand" "=d"))
2584 (clobber (match_operand:P 1 "register_operand" "=d"))
2585 (set (reg:CCU CC_REGNUM)
2586 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2587 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2590 "clst\t%0,%1\;jo\t.-4"
2591 [(set_attr "length" "8")
2592 (set_attr "type" "vs")])
2595 ; movstr instruction pattern.
2598 (define_expand "movstr"
2599 [(set (reg:SI 0) (const_int 0))
2601 [(clobber (match_dup 3))
2602 (set (match_operand:BLK 1 "memory_operand" "")
2603 (match_operand:BLK 2 "memory_operand" ""))
2604 (set (match_operand 0 "register_operand" "")
2605 (unspec [(match_dup 1)
2607 (reg:SI 0)] UNSPEC_MVST))
2608 (clobber (reg:CC CC_REGNUM))])]
2611 rtx addr1 = gen_reg_rtx (Pmode);
2612 rtx addr2 = gen_reg_rtx (Pmode);
2614 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2615 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2616 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2617 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2618 operands[3] = addr2;
2621 (define_insn "*movstr"
2622 [(clobber (match_operand:P 2 "register_operand" "=d"))
2623 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2624 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2625 (set (match_operand:P 0 "register_operand" "=d")
2626 (unspec [(mem:BLK (match_dup 1))
2627 (mem:BLK (match_dup 3))
2628 (reg:SI 0)] UNSPEC_MVST))
2629 (clobber (reg:CC CC_REGNUM))]
2631 "mvst\t%1,%2\;jo\t.-4"
2632 [(set_attr "length" "8")
2633 (set_attr "type" "vs")])
2637 ; movmemM instruction pattern(s).
2640 (define_expand "movmem<mode>"
2641 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2642 (match_operand:BLK 1 "memory_operand" "")) ; source
2643 (use (match_operand:GPR 2 "general_operand" "")) ; count
2644 (match_operand 3 "" "")]
2647 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2653 ; Move a block that is up to 256 bytes in length.
2654 ; The block length is taken as (operands[2] % 256) + 1.
2656 (define_expand "movmem_short"
2658 [(set (match_operand:BLK 0 "memory_operand" "")
2659 (match_operand:BLK 1 "memory_operand" ""))
2660 (use (match_operand 2 "nonmemory_operand" ""))
2661 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2662 (clobber (match_dup 3))])]
2664 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2666 (define_insn "*movmem_short"
2667 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2668 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2669 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2670 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2671 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2672 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2674 [(set_attr "type" "cs")
2675 (set_attr "cpu_facility" "*,*,z10,*")])
2678 [(set (match_operand:BLK 0 "memory_operand" "")
2679 (match_operand:BLK 1 "memory_operand" ""))
2680 (use (match_operand 2 "const_int_operand" ""))
2681 (use (match_operand 3 "immediate_operand" ""))
2682 (clobber (scratch))]
2685 [(set (match_dup 0) (match_dup 1))
2686 (use (match_dup 2))])]
2687 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2690 [(set (match_operand:BLK 0 "memory_operand" "")
2691 (match_operand:BLK 1 "memory_operand" ""))
2692 (use (match_operand 2 "register_operand" ""))
2693 (use (match_operand 3 "memory_operand" ""))
2694 (clobber (scratch))]
2697 [(unspec [(match_dup 2) (match_dup 3)
2698 (const_int 0)] UNSPEC_EXECUTE)
2699 (set (match_dup 0) (match_dup 1))
2700 (use (const_int 1))])]
2704 [(set (match_operand:BLK 0 "memory_operand" "")
2705 (match_operand:BLK 1 "memory_operand" ""))
2706 (use (match_operand 2 "register_operand" ""))
2707 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2708 (clobber (scratch))]
2709 "TARGET_Z10 && reload_completed"
2711 [(unspec [(match_dup 2) (const_int 0)
2712 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2713 (set (match_dup 0) (match_dup 1))
2714 (use (const_int 1))])]
2715 "operands[3] = gen_label_rtx ();")
2718 [(set (match_operand:BLK 0 "memory_operand" "")
2719 (match_operand:BLK 1 "memory_operand" ""))
2720 (use (match_operand 2 "register_operand" ""))
2721 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2722 (clobber (match_operand 3 "register_operand" ""))]
2723 "reload_completed && TARGET_CPU_ZARCH"
2724 [(set (match_dup 3) (label_ref (match_dup 4)))
2726 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2727 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2728 (set (match_dup 0) (match_dup 1))
2729 (use (const_int 1))])]
2730 "operands[4] = gen_label_rtx ();")
2732 ; Move a block of arbitrary length.
2734 (define_expand "movmem_long"
2736 [(clobber (match_dup 2))
2737 (clobber (match_dup 3))
2738 (set (match_operand:BLK 0 "memory_operand" "")
2739 (match_operand:BLK 1 "memory_operand" ""))
2740 (use (match_operand 2 "general_operand" ""))
2742 (clobber (reg:CC CC_REGNUM))])]
2745 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2746 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2747 rtx reg0 = gen_reg_rtx (dreg_mode);
2748 rtx reg1 = gen_reg_rtx (dreg_mode);
2749 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2750 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2751 rtx len0 = gen_lowpart (Pmode, reg0);
2752 rtx len1 = gen_lowpart (Pmode, reg1);
2754 emit_clobber (reg0);
2755 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2756 emit_move_insn (len0, operands[2]);
2758 emit_clobber (reg1);
2759 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2760 emit_move_insn (len1, operands[2]);
2762 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2763 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2768 (define_insn "*movmem_long"
2769 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2770 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2771 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2772 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2775 (clobber (reg:CC CC_REGNUM))]
2776 "TARGET_64BIT || !TARGET_ZARCH"
2777 "mvcle\t%0,%1,0\;jo\t.-4"
2778 [(set_attr "length" "8")
2779 (set_attr "type" "vs")])
2781 (define_insn "*movmem_long_31z"
2782 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2783 (clobber (match_operand:TI 1 "register_operand" "=d"))
2784 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2785 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2788 (clobber (reg:CC CC_REGNUM))]
2789 "!TARGET_64BIT && TARGET_ZARCH"
2790 "mvcle\t%0,%1,0\;jo\t.-4"
2791 [(set_attr "length" "8")
2792 (set_attr "type" "vs")])
2799 (define_expand "signbit<mode>2"
2800 [(set (reg:CCZ CC_REGNUM)
2801 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2804 (set (match_operand:SI 0 "register_operand" "=d")
2805 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2808 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2811 (define_expand "isinf<mode>2"
2812 [(set (reg:CCZ CC_REGNUM)
2813 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2816 (set (match_operand:SI 0 "register_operand" "=d")
2817 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2820 operands[2] = GEN_INT (S390_TDC_INFINITY);
2823 ; This insn is used to generate all variants of the Test Data Class
2824 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2825 ; is the register to be tested and the second one is the bit mask
2826 ; specifying the required test(s).
2828 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2829 (define_insn "*TDC_insn_<mode>"
2830 [(set (reg:CCZ CC_REGNUM)
2831 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2832 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2834 "t<_d>c<xde><bt>\t%0,%1"
2835 [(set_attr "op_type" "RXE")
2836 (set_attr "type" "fsimp<mode>")])
2838 (define_insn_and_split "*ccz_to_int"
2839 [(set (match_operand:SI 0 "register_operand" "=d")
2840 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2841 UNSPEC_CCZ_TO_INT))]
2845 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2849 ; setmemM instruction pattern(s).
2852 (define_expand "setmem<mode>"
2853 [(set (match_operand:BLK 0 "memory_operand" "")
2854 (match_operand:QI 2 "general_operand" ""))
2855 (use (match_operand:GPR 1 "general_operand" ""))
2856 (match_operand 3 "" "")]
2858 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2860 ; Clear a block that is up to 256 bytes in length.
2861 ; The block length is taken as (operands[1] % 256) + 1.
2863 (define_expand "clrmem_short"
2865 [(set (match_operand:BLK 0 "memory_operand" "")
2867 (use (match_operand 1 "nonmemory_operand" ""))
2868 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2869 (clobber (match_dup 2))
2870 (clobber (reg:CC CC_REGNUM))])]
2872 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2874 (define_insn "*clrmem_short"
2875 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2877 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2878 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2879 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2880 (clobber (reg:CC CC_REGNUM))]
2881 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2883 [(set_attr "type" "cs")
2884 (set_attr "cpu_facility" "*,*,z10,*")])
2887 [(set (match_operand:BLK 0 "memory_operand" "")
2889 (use (match_operand 1 "const_int_operand" ""))
2890 (use (match_operand 2 "immediate_operand" ""))
2892 (clobber (reg:CC CC_REGNUM))]
2895 [(set (match_dup 0) (const_int 0))
2897 (clobber (reg:CC CC_REGNUM))])]
2898 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2901 [(set (match_operand:BLK 0 "memory_operand" "")
2903 (use (match_operand 1 "register_operand" ""))
2904 (use (match_operand 2 "memory_operand" ""))
2906 (clobber (reg:CC CC_REGNUM))]
2909 [(unspec [(match_dup 1) (match_dup 2)
2910 (const_int 0)] UNSPEC_EXECUTE)
2911 (set (match_dup 0) (const_int 0))
2913 (clobber (reg:CC CC_REGNUM))])]
2917 [(set (match_operand:BLK 0 "memory_operand" "")
2919 (use (match_operand 1 "register_operand" ""))
2920 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2922 (clobber (reg:CC CC_REGNUM))]
2923 "TARGET_Z10 && reload_completed"
2925 [(unspec [(match_dup 1) (const_int 0)
2926 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2927 (set (match_dup 0) (const_int 0))
2929 (clobber (reg:CC CC_REGNUM))])]
2930 "operands[3] = gen_label_rtx ();")
2933 [(set (match_operand:BLK 0 "memory_operand" "")
2935 (use (match_operand 1 "register_operand" ""))
2936 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2937 (clobber (match_operand 2 "register_operand" ""))
2938 (clobber (reg:CC CC_REGNUM))]
2939 "reload_completed && TARGET_CPU_ZARCH"
2940 [(set (match_dup 2) (label_ref (match_dup 3)))
2942 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2943 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2944 (set (match_dup 0) (const_int 0))
2946 (clobber (reg:CC CC_REGNUM))])]
2947 "operands[3] = gen_label_rtx ();")
2949 ; Initialize a block of arbitrary length with (operands[2] % 256).
2951 (define_expand "setmem_long"
2953 [(clobber (match_dup 1))
2954 (set (match_operand:BLK 0 "memory_operand" "")
2955 (match_operand 2 "shift_count_or_setmem_operand" ""))
2956 (use (match_operand 1 "general_operand" ""))
2958 (clobber (reg:CC CC_REGNUM))])]
2961 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2962 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2963 rtx reg0 = gen_reg_rtx (dreg_mode);
2964 rtx reg1 = gen_reg_rtx (dreg_mode);
2965 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2966 rtx len0 = gen_lowpart (Pmode, reg0);
2968 emit_clobber (reg0);
2969 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2970 emit_move_insn (len0, operands[1]);
2972 emit_move_insn (reg1, const0_rtx);
2974 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2979 (define_insn "*setmem_long"
2980 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2981 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2982 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2984 (use (match_operand:<DBL> 1 "register_operand" "d"))
2985 (clobber (reg:CC CC_REGNUM))]
2986 "TARGET_64BIT || !TARGET_ZARCH"
2987 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2988 [(set_attr "length" "8")
2989 (set_attr "type" "vs")])
2991 (define_insn "*setmem_long_and"
2992 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2993 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2994 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2995 (match_operand 4 "const_int_operand" "n")))
2997 (use (match_operand:<DBL> 1 "register_operand" "d"))
2998 (clobber (reg:CC CC_REGNUM))]
2999 "(TARGET_64BIT || !TARGET_ZARCH) &&
3000 (INTVAL (operands[4]) & 255) == 255"
3001 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3002 [(set_attr "length" "8")
3003 (set_attr "type" "vs")])
3005 (define_insn "*setmem_long_31z"
3006 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3007 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3008 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3010 (use (match_operand:TI 1 "register_operand" "d"))
3011 (clobber (reg:CC CC_REGNUM))]
3012 "!TARGET_64BIT && TARGET_ZARCH"
3013 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3014 [(set_attr "length" "8")
3015 (set_attr "type" "vs")])
3018 ; cmpmemM instruction pattern(s).
3021 (define_expand "cmpmemsi"
3022 [(set (match_operand:SI 0 "register_operand" "")
3023 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3024 (match_operand:BLK 2 "memory_operand" "") ) )
3025 (use (match_operand:SI 3 "general_operand" ""))
3026 (use (match_operand:SI 4 "" ""))]
3029 if (s390_expand_cmpmem (operands[0], operands[1],
3030 operands[2], operands[3]))
3036 ; Compare a block that is up to 256 bytes in length.
3037 ; The block length is taken as (operands[2] % 256) + 1.
3039 (define_expand "cmpmem_short"
3041 [(set (reg:CCU CC_REGNUM)
3042 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3043 (match_operand:BLK 1 "memory_operand" "")))
3044 (use (match_operand 2 "nonmemory_operand" ""))
3045 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3046 (clobber (match_dup 3))])]
3048 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3050 (define_insn "*cmpmem_short"
3051 [(set (reg:CCU CC_REGNUM)
3052 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3053 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3054 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3055 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3056 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3057 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3059 [(set_attr "type" "cs")
3060 (set_attr "cpu_facility" "*,*,z10,*")])
3063 [(set (reg:CCU CC_REGNUM)
3064 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3065 (match_operand:BLK 1 "memory_operand" "")))
3066 (use (match_operand 2 "const_int_operand" ""))
3067 (use (match_operand 3 "immediate_operand" ""))
3068 (clobber (scratch))]
3071 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3072 (use (match_dup 2))])]
3073 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3076 [(set (reg:CCU CC_REGNUM)
3077 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3078 (match_operand:BLK 1 "memory_operand" "")))
3079 (use (match_operand 2 "register_operand" ""))
3080 (use (match_operand 3 "memory_operand" ""))
3081 (clobber (scratch))]
3084 [(unspec [(match_dup 2) (match_dup 3)
3085 (const_int 0)] UNSPEC_EXECUTE)
3086 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3087 (use (const_int 1))])]
3091 [(set (reg:CCU CC_REGNUM)
3092 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3093 (match_operand:BLK 1 "memory_operand" "")))
3094 (use (match_operand 2 "register_operand" ""))
3095 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3096 (clobber (scratch))]
3097 "TARGET_Z10 && reload_completed"
3099 [(unspec [(match_dup 2) (const_int 0)
3100 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3101 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3102 (use (const_int 1))])]
3103 "operands[4] = gen_label_rtx ();")
3106 [(set (reg:CCU CC_REGNUM)
3107 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3108 (match_operand:BLK 1 "memory_operand" "")))
3109 (use (match_operand 2 "register_operand" ""))
3110 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3111 (clobber (match_operand 3 "register_operand" ""))]
3112 "reload_completed && TARGET_CPU_ZARCH"
3113 [(set (match_dup 3) (label_ref (match_dup 4)))
3115 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3116 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3117 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3118 (use (const_int 1))])]
3119 "operands[4] = gen_label_rtx ();")
3121 ; Compare a block of arbitrary length.
3123 (define_expand "cmpmem_long"
3125 [(clobber (match_dup 2))
3126 (clobber (match_dup 3))
3127 (set (reg:CCU CC_REGNUM)
3128 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3129 (match_operand:BLK 1 "memory_operand" "")))
3130 (use (match_operand 2 "general_operand" ""))
3131 (use (match_dup 3))])]
3134 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3135 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3136 rtx reg0 = gen_reg_rtx (dreg_mode);
3137 rtx reg1 = gen_reg_rtx (dreg_mode);
3138 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3139 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3140 rtx len0 = gen_lowpart (Pmode, reg0);
3141 rtx len1 = gen_lowpart (Pmode, reg1);
3143 emit_clobber (reg0);
3144 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3145 emit_move_insn (len0, operands[2]);
3147 emit_clobber (reg1);
3148 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3149 emit_move_insn (len1, operands[2]);
3151 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3152 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3157 (define_insn "*cmpmem_long"
3158 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3159 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3160 (set (reg:CCU CC_REGNUM)
3161 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3162 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3164 (use (match_dup 3))]
3165 "TARGET_64BIT || !TARGET_ZARCH"
3166 "clcle\t%0,%1,0\;jo\t.-4"
3167 [(set_attr "length" "8")
3168 (set_attr "type" "vs")])
3170 (define_insn "*cmpmem_long_31z"
3171 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3172 (clobber (match_operand:TI 1 "register_operand" "=d"))
3173 (set (reg:CCU CC_REGNUM)
3174 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3175 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3177 (use (match_dup 3))]
3178 "!TARGET_64BIT && TARGET_ZARCH"
3179 "clcle\t%0,%1,0\;jo\t.-4"
3180 [(set_attr "op_type" "NN")
3181 (set_attr "type" "vs")
3182 (set_attr "length" "8")])
3184 ; Convert CCUmode condition code to integer.
3185 ; Result is zero if EQ, positive if LTU, negative if GTU.
3187 (define_insn_and_split "cmpint"
3188 [(set (match_operand:SI 0 "register_operand" "=d")
3189 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3191 (clobber (reg:CC CC_REGNUM))]
3195 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3197 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3198 (clobber (reg:CC CC_REGNUM))])])
3200 (define_insn_and_split "*cmpint_cc"
3201 [(set (reg CC_REGNUM)
3202 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3205 (set (match_operand:SI 0 "register_operand" "=d")
3206 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3207 "s390_match_ccmode (insn, CCSmode)"
3209 "&& reload_completed"
3210 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3212 [(set (match_dup 2) (match_dup 3))
3213 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3215 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3216 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3217 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3220 (define_insn_and_split "*cmpint_sign"
3221 [(set (match_operand:DI 0 "register_operand" "=d")
3222 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3223 UNSPEC_CCU_TO_INT)))
3224 (clobber (reg:CC CC_REGNUM))]
3227 "&& reload_completed"
3228 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3230 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3231 (clobber (reg:CC CC_REGNUM))])])
3233 (define_insn_and_split "*cmpint_sign_cc"
3234 [(set (reg CC_REGNUM)
3235 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3236 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3237 UNSPEC_CCU_TO_INT) 0)
3238 (const_int 32)) (const_int 32))
3240 (set (match_operand:DI 0 "register_operand" "=d")
3241 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3242 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3244 "&& reload_completed"
3245 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3247 [(set (match_dup 2) (match_dup 3))
3248 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3250 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3251 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3252 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3257 ;;- Conversion instructions.
3260 (define_insn "*sethighpartsi"
3261 [(set (match_operand:SI 0 "register_operand" "=d,d")
3262 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3263 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3264 (clobber (reg:CC CC_REGNUM))]
3269 [(set_attr "op_type" "RS,RSY")
3270 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3272 (define_insn "*sethighpartdi_64"
3273 [(set (match_operand:DI 0 "register_operand" "=d")
3274 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3275 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3276 (clobber (reg:CC CC_REGNUM))]
3279 [(set_attr "op_type" "RSY")
3280 (set_attr "z10prop" "z10_super")])
3282 (define_insn "*sethighpartdi_31"
3283 [(set (match_operand:DI 0 "register_operand" "=d,d")
3284 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3285 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3286 (clobber (reg:CC CC_REGNUM))]
3291 [(set_attr "op_type" "RS,RSY")
3292 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3295 (define_insn_and_split "*extzv<mode>"
3296 [(set (match_operand:GPR 0 "register_operand" "=d")
3297 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3298 (match_operand 2 "const_int_operand" "n")
3300 (clobber (reg:CC CC_REGNUM))]
3301 "INTVAL (operands[2]) > 0
3302 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3304 "&& reload_completed"
3306 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3307 (clobber (reg:CC CC_REGNUM))])
3308 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3310 int bitsize = INTVAL (operands[2]);
3311 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3312 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3314 operands[1] = adjust_address (operands[1], BLKmode, 0);
3315 set_mem_size (operands[1], size);
3316 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3317 operands[3] = GEN_INT (mask);
3320 (define_insn_and_split "*extv<mode>"
3321 [(set (match_operand:GPR 0 "register_operand" "=d")
3322 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3323 (match_operand 2 "const_int_operand" "n")
3325 (clobber (reg:CC CC_REGNUM))]
3326 "INTVAL (operands[2]) > 0
3327 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3329 "&& reload_completed"
3331 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3332 (clobber (reg:CC CC_REGNUM))])
3334 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3335 (clobber (reg:CC CC_REGNUM))])]
3337 int bitsize = INTVAL (operands[2]);
3338 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3339 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3341 operands[1] = adjust_address (operands[1], BLKmode, 0);
3342 set_mem_size (operands[1], size);
3343 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3344 operands[3] = GEN_INT (mask);
3348 ; insv instruction patterns
3351 (define_expand "insv"
3352 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3353 (match_operand 1 "const_int_operand" "")
3354 (match_operand 2 "const_int_operand" ""))
3355 (match_operand 3 "general_operand" ""))]
3358 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3363 (define_insn "*insv<mode>_z10"
3364 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3365 (match_operand 1 "const_int_operand" "I")
3366 (match_operand 2 "const_int_operand" "I"))
3367 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3368 (clobber (reg:CC CC_REGNUM))]
3370 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3371 GET_MODE_BITSIZE (<MODE>mode)"
3373 int start = INTVAL (operands[2]);
3374 int size = INTVAL (operands[1]);
3375 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3377 operands[2] = GEN_INT (offset + start); /* start bit position */
3378 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3379 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3380 start - size); /* left shift count */
3382 return "risbg\t%0,%3,%b2,%b1,%b4";
3384 [(set_attr "op_type" "RIE")
3385 (set_attr "z10prop" "z10_super_E1")])
3387 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3388 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3389 (define_insn "*insv<mode>_z10_noshift"
3390 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3391 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3392 (match_operand 2 "const_int_operand" "n"))
3393 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3394 (match_operand 4 "const_int_operand" "n"))))
3395 (clobber (reg:CC CC_REGNUM))]
3397 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3398 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3399 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3405 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3406 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3408 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3409 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3410 operands[7] = const0_rtx; /* left shift count */
3412 return "risbg\t%0,%1,%b5,%b6,%b7";
3414 [(set_attr "op_type" "RIE")
3415 (set_attr "z10prop" "z10_super_E1")])
3417 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3418 (define_insn "*insv<mode>_or_z10_noshift"
3419 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3420 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3421 (match_operand 2 "const_int_operand" "n"))
3422 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3423 (clobber (reg:CC CC_REGNUM))]
3425 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3426 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3431 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3432 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3434 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3435 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3436 operands[6] = const0_rtx; /* left shift count */
3438 return "rosbg\t%0,%1,%b4,%b5,%b6";
3440 [(set_attr "op_type" "RIE")])
3442 (define_insn "*insv<mode>_mem_reg"
3443 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3444 (match_operand 1 "const_int_operand" "n,n")
3446 (match_operand:W 2 "register_operand" "d,d"))]
3447 "INTVAL (operands[1]) > 0
3448 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3449 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3451 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3453 operands[1] = GEN_INT ((1ul << size) - 1);
3454 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3455 : "stcmy\t%2,%1,%S0";
3457 [(set_attr "op_type" "RS,RSY")
3458 (set_attr "z10prop" "z10_super,z10_super")])
3460 (define_insn "*insvdi_mem_reghigh"
3461 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3462 (match_operand 1 "const_int_operand" "n")
3464 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3467 && INTVAL (operands[1]) > 0
3468 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3469 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3471 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3473 operands[1] = GEN_INT ((1ul << size) - 1);
3474 return "stcmh\t%2,%1,%S0";
3476 [(set_attr "op_type" "RSY")
3477 (set_attr "z10prop" "z10_super")])
3479 (define_insn "*insvdi_reg_imm"
3480 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3482 (match_operand 1 "const_int_operand" "n"))
3483 (match_operand:DI 2 "const_int_operand" "n"))]
3485 && INTVAL (operands[1]) >= 0
3486 && INTVAL (operands[1]) < BITS_PER_WORD
3487 && INTVAL (operands[1]) % 16 == 0"
3489 switch (BITS_PER_WORD - INTVAL (operands[1]))
3491 case 64: return "iihh\t%0,%x2"; break;
3492 case 48: return "iihl\t%0,%x2"; break;
3493 case 32: return "iilh\t%0,%x2"; break;
3494 case 16: return "iill\t%0,%x2"; break;
3495 default: gcc_unreachable();
3498 [(set_attr "op_type" "RI")
3499 (set_attr "z10prop" "z10_super_E1")])
3501 ; Update the left-most 32 bit of a DI.
3502 (define_insn "*insv_h_di_reg_extimm"
3503 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3506 (match_operand:DI 1 "const_int_operand" "n"))]
3509 [(set_attr "op_type" "RIL")
3510 (set_attr "z10prop" "z10_fwd_E1")])
3512 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3513 (define_insn "*insv_l<mode>_reg_extimm"
3514 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3516 (match_operand 1 "const_int_operand" "n"))
3517 (match_operand:P 2 "const_int_operand" "n"))]
3519 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3521 [(set_attr "op_type" "RIL")
3522 (set_attr "z10prop" "z10_fwd_A1")])
3525 ; extendsidi2 instruction pattern(s).
3528 (define_expand "extendsidi2"
3529 [(set (match_operand:DI 0 "register_operand" "")
3530 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3535 emit_clobber (operands[0]);
3536 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3537 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3538 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3543 (define_insn "*extendsidi2"
3544 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3545 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3551 [(set_attr "op_type" "RRE,RXY,RIL")
3552 (set_attr "type" "*,*,larl")
3553 (set_attr "cpu_facility" "*,*,z10")
3554 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3557 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3560 (define_expand "extend<HQI:mode><DSI:mode>2"
3561 [(set (match_operand:DSI 0 "register_operand" "")
3562 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3565 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3567 rtx tmp = gen_reg_rtx (SImode);
3568 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3569 emit_insn (gen_extendsidi2 (operands[0], tmp));
3572 else if (!TARGET_EXTIMM)
3574 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3575 GET_MODE_BITSIZE (<HQI:MODE>mode));
3577 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3578 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3579 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3585 ; extendhidi2 instruction pattern(s).
3588 (define_insn "*extendhidi2_extimm"
3589 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3590 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3591 "TARGET_ZARCH && TARGET_EXTIMM"
3596 [(set_attr "op_type" "RRE,RXY,RIL")
3597 (set_attr "type" "*,*,larl")
3598 (set_attr "cpu_facility" "extimm,extimm,z10")
3599 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3601 (define_insn "*extendhidi2"
3602 [(set (match_operand:DI 0 "register_operand" "=d")
3603 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3606 [(set_attr "op_type" "RXY")
3607 (set_attr "z10prop" "z10_super_E1")])
3610 ; extendhisi2 instruction pattern(s).
3613 (define_insn "*extendhisi2_extimm"
3614 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3615 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3622 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3623 (set_attr "type" "*,*,*,larl")
3624 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3625 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3627 (define_insn "*extendhisi2"
3628 [(set (match_operand:SI 0 "register_operand" "=d,d")
3629 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3634 [(set_attr "op_type" "RX,RXY")
3635 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3638 ; extendqi(si|di)2 instruction pattern(s).
3641 ; lbr, lgbr, lb, lgb
3642 (define_insn "*extendqi<mode>2_extimm"
3643 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3644 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3649 [(set_attr "op_type" "RRE,RXY")
3650 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3653 (define_insn "*extendqi<mode>2"
3654 [(set (match_operand:GPR 0 "register_operand" "=d")
3655 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3656 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3658 [(set_attr "op_type" "RXY")
3659 (set_attr "z10prop" "z10_super_E1")])
3661 (define_insn_and_split "*extendqi<mode>2_short_displ"
3662 [(set (match_operand:GPR 0 "register_operand" "=d")
3663 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3664 (clobber (reg:CC CC_REGNUM))]
3665 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3667 "&& reload_completed"
3669 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3670 (clobber (reg:CC CC_REGNUM))])
3672 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3673 (clobber (reg:CC CC_REGNUM))])]
3675 operands[1] = adjust_address (operands[1], BLKmode, 0);
3676 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3677 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3678 - GET_MODE_BITSIZE (QImode));
3682 ; zero_extendsidi2 instruction pattern(s).
3685 (define_expand "zero_extendsidi2"
3686 [(set (match_operand:DI 0 "register_operand" "")
3687 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3692 emit_clobber (operands[0]);
3693 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3694 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3699 (define_insn "*zero_extendsidi2"
3700 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3701 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3707 [(set_attr "op_type" "RRE,RXY,RIL")
3708 (set_attr "type" "*,*,larl")
3709 (set_attr "cpu_facility" "*,*,z10")
3710 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3713 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3716 (define_insn "*llgt_sidi"
3717 [(set (match_operand:DI 0 "register_operand" "=d")
3718 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3719 (const_int 2147483647)))]
3722 [(set_attr "op_type" "RXE")
3723 (set_attr "z10prop" "z10_super_E1")])
3725 (define_insn_and_split "*llgt_sidi_split"
3726 [(set (match_operand:DI 0 "register_operand" "=d")
3727 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3728 (const_int 2147483647)))
3729 (clobber (reg:CC CC_REGNUM))]
3732 "&& reload_completed"
3734 (and:DI (subreg:DI (match_dup 1) 0)
3735 (const_int 2147483647)))]
3738 (define_insn "*llgt_sisi"
3739 [(set (match_operand:SI 0 "register_operand" "=d,d")
3740 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3741 (const_int 2147483647)))]
3746 [(set_attr "op_type" "RRE,RXE")
3747 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3749 (define_insn "*llgt_didi"
3750 [(set (match_operand:DI 0 "register_operand" "=d,d")
3751 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3752 (const_int 2147483647)))]
3757 [(set_attr "op_type" "RRE,RXE")
3758 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3761 [(set (match_operand:DSI 0 "register_operand" "")
3762 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3763 (const_int 2147483647)))
3764 (clobber (reg:CC CC_REGNUM))]
3765 "TARGET_ZARCH && reload_completed"
3767 (and:DSI (match_dup 1)
3768 (const_int 2147483647)))]
3772 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3775 (define_expand "zero_extend<mode>di2"
3776 [(set (match_operand:DI 0 "register_operand" "")
3777 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3782 rtx tmp = gen_reg_rtx (SImode);
3783 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3784 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3787 else if (!TARGET_EXTIMM)
3789 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3790 GET_MODE_BITSIZE(<MODE>mode));
3791 operands[1] = gen_lowpart (DImode, operands[1]);
3792 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3793 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3798 (define_expand "zero_extend<mode>si2"
3799 [(set (match_operand:SI 0 "register_operand" "")
3800 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3805 operands[1] = gen_lowpart (SImode, operands[1]);
3806 emit_insn (gen_andsi3 (operands[0], operands[1],
3807 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3813 (define_insn "*zero_extendhi<mode>2_z10"
3814 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3815 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3821 [(set_attr "op_type" "RXY,RRE,RIL")
3822 (set_attr "type" "*,*,larl")
3823 (set_attr "cpu_facility" "*,*,z10")
3824 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3826 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3827 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3828 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3829 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3834 [(set_attr "op_type" "RRE,RXY")
3835 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3838 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3839 [(set (match_operand:GPR 0 "register_operand" "=d")
3840 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3841 "TARGET_ZARCH && !TARGET_EXTIMM"
3843 [(set_attr "op_type" "RXY")
3844 (set_attr "z10prop" "z10_fwd_A3")])
3846 (define_insn_and_split "*zero_extendhisi2_31"
3847 [(set (match_operand:SI 0 "register_operand" "=&d")
3848 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3849 (clobber (reg:CC CC_REGNUM))]
3852 "&& reload_completed"
3853 [(set (match_dup 0) (const_int 0))
3855 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3856 (clobber (reg:CC CC_REGNUM))])]
3857 "operands[2] = gen_lowpart (HImode, operands[0]);")
3859 (define_insn_and_split "*zero_extendqisi2_31"
3860 [(set (match_operand:SI 0 "register_operand" "=&d")
3861 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3864 "&& reload_completed"
3865 [(set (match_dup 0) (const_int 0))
3866 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3867 "operands[2] = gen_lowpart (QImode, operands[0]);")
3870 ; zero_extendqihi2 instruction pattern(s).
3873 (define_expand "zero_extendqihi2"
3874 [(set (match_operand:HI 0 "register_operand" "")
3875 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3876 "TARGET_ZARCH && !TARGET_EXTIMM"
3878 operands[1] = gen_lowpart (HImode, operands[1]);
3879 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3883 (define_insn "*zero_extendqihi2_64"
3884 [(set (match_operand:HI 0 "register_operand" "=d")
3885 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3886 "TARGET_ZARCH && !TARGET_EXTIMM"
3888 [(set_attr "op_type" "RXY")
3889 (set_attr "z10prop" "z10_fwd_A3")])
3891 (define_insn_and_split "*zero_extendqihi2_31"
3892 [(set (match_operand:HI 0 "register_operand" "=&d")
3893 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3896 "&& reload_completed"
3897 [(set (match_dup 0) (const_int 0))
3898 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3899 "operands[2] = gen_lowpart (QImode, operands[0]);")
3902 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3905 (define_expand "fixuns_truncdddi2"
3907 [(set (match_operand:DI 0 "register_operand" "")
3908 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3909 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3910 (clobber (reg:CC CC_REGNUM))])]
3916 rtx label1 = gen_label_rtx ();
3917 rtx label2 = gen_label_rtx ();
3918 rtx temp = gen_reg_rtx (TDmode);
3919 REAL_VALUE_TYPE cmp, sub;
3921 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3922 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3924 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3925 solution is doing the check and the subtraction in TD mode and using a
3926 TD -> DI convert afterwards. */
3927 emit_insn (gen_extendddtd2 (temp, operands[1]));
3928 temp = force_reg (TDmode, temp);
3929 emit_cmp_and_jump_insns (temp,
3930 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3931 LT, NULL_RTX, VOIDmode, 0, label1);
3932 emit_insn (gen_subtd3 (temp, temp,
3933 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3934 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3937 emit_label (label1);
3938 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3939 emit_label (label2);
3944 (define_expand "fixuns_trunctddi2"
3946 [(set (match_operand:DI 0 "register_operand" "")
3947 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
3948 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3949 (clobber (reg:CC CC_REGNUM))])]
3955 rtx label1 = gen_label_rtx ();
3956 rtx label2 = gen_label_rtx ();
3957 rtx temp = gen_reg_rtx (TDmode);
3958 REAL_VALUE_TYPE cmp, sub;
3960 operands[1] = force_reg (TDmode, operands[1]);
3961 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3962 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3964 emit_cmp_and_jump_insns (operands[1],
3965 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3966 LT, NULL_RTX, VOIDmode, 0, label1);
3967 emit_insn (gen_subtd3 (temp, operands[1],
3968 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3969 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3972 emit_label (label1);
3973 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3974 emit_label (label2);
3980 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
3981 ; instruction pattern(s).
3984 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3986 [(set (match_operand:GPR 0 "register_operand" "")
3987 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
3988 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3989 (clobber (reg:CC CC_REGNUM))])]
3994 rtx label1 = gen_label_rtx ();
3995 rtx label2 = gen_label_rtx ();
3996 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3997 REAL_VALUE_TYPE cmp, sub;
3999 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4000 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
4001 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
4003 emit_cmp_and_jump_insns (operands[1],
4004 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4005 LT, NULL_RTX, VOIDmode, 0, label1);
4006 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4007 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4008 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4012 emit_label (label1);
4013 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4014 operands[1], GEN_INT (5)));
4015 emit_label (label2);
4020 ; fixuns_trunc(td|dd)si2 expander
4021 (define_expand "fixuns_trunc<mode>si2"
4023 [(set (match_operand:SI 0 "register_operand" "")
4024 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4025 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4026 (clobber (reg:CC CC_REGNUM))])]
4027 "TARGET_Z196 && TARGET_HARD_DFP"
4030 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4032 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4033 ; clfdtr, clfxtr, clgdtr, clgxtr
4034 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4035 [(set (match_operand:GPR 0 "register_operand" "=r")
4036 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4037 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4038 (clobber (reg:CC CC_REGNUM))]
4040 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4041 [(set_attr "op_type" "RRF")
4042 (set_attr "type" "ftoi")])
4044 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4045 [(set (match_operand:GPR 0 "register_operand" "")
4046 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4049 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4054 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4055 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4056 [(set (match_operand:GPR 0 "register_operand" "=d")
4057 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4058 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4059 (clobber (reg:CC CC_REGNUM))]
4061 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4062 [(set_attr "op_type" "RRE")
4063 (set_attr "type" "ftoi")])
4067 ; fix_trunc(td|dd)di2 instruction pattern(s).
4070 (define_expand "fix_trunc<mode>di2"
4071 [(set (match_operand:DI 0 "register_operand" "")
4072 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4073 "TARGET_ZARCH && TARGET_HARD_DFP"
4075 operands[1] = force_reg (<MODE>mode, operands[1]);
4076 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4082 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4083 [(set (match_operand:DI 0 "register_operand" "=d")
4084 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4085 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4086 (clobber (reg:CC CC_REGNUM))]
4087 "TARGET_ZARCH && TARGET_HARD_DFP"
4088 "cg<DFP:xde>tr\t%0,%h2,%1"
4089 [(set_attr "op_type" "RRF")
4090 (set_attr "type" "ftoidfp")])
4094 ; fix_trunctf(si|di)2 instruction pattern(s).
4097 (define_expand "fix_trunctf<mode>2"
4098 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4099 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4100 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4101 (clobber (reg:CC CC_REGNUM))])]
4107 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4110 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4111 (define_insn "floatdi<mode>2"
4112 [(set (match_operand:FP 0 "register_operand" "=f")
4113 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4114 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4115 "c<xde>g<bt>r\t%0,%1"
4116 [(set_attr "op_type" "RRE")
4117 (set_attr "type" "itof<mode>" )])
4119 ; cxfbr, cdfbr, cefbr
4120 (define_insn "floatsi<mode>2"
4121 [(set (match_operand:BFP 0 "register_operand" "=f")
4122 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4125 [(set_attr "op_type" "RRE")
4126 (set_attr "type" "itof<mode>" )])
4129 (define_insn "floatsi<mode>2"
4130 [(set (match_operand:DFP 0 "register_operand" "=f")
4131 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4132 "TARGET_Z196 && TARGET_HARD_FLOAT"
4133 "c<xde>ftr\t%0,0,%1,0"
4134 [(set_attr "op_type" "RRE")
4135 (set_attr "type" "itof<mode>" )])
4138 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4141 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4142 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4143 (define_insn "floatuns<GPR:mode><FP:mode>2"
4144 [(set (match_operand:FP 0 "register_operand" "=f")
4145 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4146 "TARGET_Z196 && TARGET_HARD_FLOAT"
4147 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4148 [(set_attr "op_type" "RRE")
4149 (set_attr "type" "itof<FP:mode>" )])
4152 ; truncdfsf2 instruction pattern(s).
4155 (define_insn "truncdfsf2"
4156 [(set (match_operand:SF 0 "register_operand" "=f")
4157 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4160 [(set_attr "op_type" "RRE")
4161 (set_attr "type" "ftruncdf")])
4164 ; trunctf(df|sf)2 instruction pattern(s).
4168 (define_insn "trunctf<mode>2"
4169 [(set (match_operand:DSF 0 "register_operand" "=f")
4170 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4171 (clobber (match_scratch:TF 2 "=f"))]
4173 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4174 [(set_attr "length" "6")
4175 (set_attr "type" "ftrunctf")])
4178 ; trunctddd2 and truncddsd2 instruction pattern(s).
4181 (define_insn "trunctddd2"
4182 [(set (match_operand:DD 0 "register_operand" "=f")
4183 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4184 (clobber (match_scratch:TD 2 "=f"))]
4186 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4187 [(set_attr "length" "6")
4188 (set_attr "type" "ftruncdd")])
4190 (define_insn "truncddsd2"
4191 [(set (match_operand:SD 0 "register_operand" "=f")
4192 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4195 [(set_attr "op_type" "RRF")
4196 (set_attr "type" "ftruncsd")])
4199 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4202 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4203 (define_insn "extend<DSF:mode><BFP:mode>2"
4204 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4205 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4207 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4209 l<BFP:xde><DSF:xde>br\t%0,%1
4210 l<BFP:xde><DSF:xde>b\t%0,%1"
4211 [(set_attr "op_type" "RRE,RXE")
4212 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4215 ; extendddtd2 and extendsddd2 instruction pattern(s).
4218 (define_insn "extendddtd2"
4219 [(set (match_operand:TD 0 "register_operand" "=f")
4220 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4223 [(set_attr "op_type" "RRF")
4224 (set_attr "type" "fsimptf")])
4226 (define_insn "extendsddd2"
4227 [(set (match_operand:DD 0 "register_operand" "=f")
4228 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4231 [(set_attr "op_type" "RRF")
4232 (set_attr "type" "fsimptf")])
4234 ; Binary <-> Decimal floating point trunc patterns
4237 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4238 [(set (reg:DFP_ALL FPR0_REGNUM)
4239 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4240 (use (reg:SI GPR0_REGNUM))
4241 (clobber (reg:CC CC_REGNUM))]
4245 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4246 [(set (reg:BFP FPR0_REGNUM)
4247 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4248 (use (reg:SI GPR0_REGNUM))
4249 (clobber (reg:CC CC_REGNUM))]
4253 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4254 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4255 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4257 [(set (reg:DFP_ALL FPR0_REGNUM)
4258 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4259 (use (reg:SI GPR0_REGNUM))
4260 (clobber (reg:CC CC_REGNUM))])
4261 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4262 (reg:DFP_ALL FPR0_REGNUM))]
4264 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4266 HOST_WIDE_INT flags;
4268 flags = (PFPO_CONVERT |
4269 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4270 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4272 operands[2] = GEN_INT (flags);
4275 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4276 [(set (reg:DFP_ALL FPR2_REGNUM)
4277 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4278 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4280 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4281 (use (reg:SI GPR0_REGNUM))
4282 (clobber (reg:CC CC_REGNUM))])
4283 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4285 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4287 HOST_WIDE_INT flags;
4289 flags = (PFPO_CONVERT |
4290 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4291 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4293 operands[2] = GEN_INT (flags);
4297 ; Binary <-> Decimal floating point extend patterns
4300 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4301 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4302 (use (reg:SI GPR0_REGNUM))
4303 (clobber (reg:CC CC_REGNUM))]
4307 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4308 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4309 (use (reg:SI GPR0_REGNUM))
4310 (clobber (reg:CC CC_REGNUM))]
4314 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4315 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4316 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4318 [(set (reg:DFP_ALL FPR0_REGNUM)
4319 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4320 (use (reg:SI GPR0_REGNUM))
4321 (clobber (reg:CC CC_REGNUM))])
4322 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4323 (reg:DFP_ALL FPR0_REGNUM))]
4325 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4327 HOST_WIDE_INT flags;
4329 flags = (PFPO_CONVERT |
4330 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4331 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4333 operands[2] = GEN_INT (flags);
4336 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4337 [(set (reg:DFP_ALL FPR2_REGNUM)
4338 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4339 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4341 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4342 (use (reg:SI GPR0_REGNUM))
4343 (clobber (reg:CC CC_REGNUM))])
4344 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4346 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4348 HOST_WIDE_INT flags;
4350 flags = (PFPO_CONVERT |
4351 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4352 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4354 operands[2] = GEN_INT (flags);
4359 ;; ARITHMETIC OPERATIONS
4361 ; arithmetic operations set the ConditionCode,
4362 ; because of unpredictable Bits in Register for Halfword and Byte
4363 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4366 ;;- Add instructions.
4370 ; addti3 instruction pattern(s).
4373 (define_insn_and_split "addti3"
4374 [(set (match_operand:TI 0 "register_operand" "=&d")
4375 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4376 (match_operand:TI 2 "general_operand" "do") ) )
4377 (clobber (reg:CC CC_REGNUM))]
4380 "&& reload_completed"
4382 [(set (reg:CCL1 CC_REGNUM)
4383 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4385 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4387 [(set (match_dup 3) (plus:DI
4388 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4389 (match_dup 4)) (match_dup 5)))
4390 (clobber (reg:CC CC_REGNUM))])]
4391 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4392 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4393 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4394 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4395 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4396 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4399 ; adddi3 instruction pattern(s).
4402 (define_expand "adddi3"
4404 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4405 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4406 (match_operand:DI 2 "general_operand" "")))
4407 (clobber (reg:CC CC_REGNUM))])]
4411 (define_insn "*adddi3_sign"
4412 [(set (match_operand:DI 0 "register_operand" "=d,d")
4413 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4414 (match_operand:DI 1 "register_operand" "0,0")))
4415 (clobber (reg:CC CC_REGNUM))]
4420 [(set_attr "op_type" "RRE,RXY")
4421 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4423 (define_insn "*adddi3_zero_cc"
4424 [(set (reg CC_REGNUM)
4425 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4426 (match_operand:DI 1 "register_operand" "0,0"))
4428 (set (match_operand:DI 0 "register_operand" "=d,d")
4429 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4430 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4434 [(set_attr "op_type" "RRE,RXY")
4435 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4437 (define_insn "*adddi3_zero_cconly"
4438 [(set (reg CC_REGNUM)
4439 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4440 (match_operand:DI 1 "register_operand" "0,0"))
4442 (clobber (match_scratch:DI 0 "=d,d"))]
4443 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4447 [(set_attr "op_type" "RRE,RXY")
4448 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4450 (define_insn "*adddi3_zero"
4451 [(set (match_operand:DI 0 "register_operand" "=d,d")
4452 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4453 (match_operand:DI 1 "register_operand" "0,0")))
4454 (clobber (reg:CC CC_REGNUM))]
4459 [(set_attr "op_type" "RRE,RXY")
4460 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4462 (define_insn_and_split "*adddi3_31z"
4463 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4464 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4465 (match_operand:DI 2 "general_operand" "do") ) )
4466 (clobber (reg:CC CC_REGNUM))]
4467 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4469 "&& reload_completed"
4471 [(set (reg:CCL1 CC_REGNUM)
4472 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4474 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4476 [(set (match_dup 3) (plus:SI
4477 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4478 (match_dup 4)) (match_dup 5)))
4479 (clobber (reg:CC CC_REGNUM))])]
4480 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4481 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4482 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4483 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4484 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4485 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4487 (define_insn_and_split "*adddi3_31"
4488 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4489 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4490 (match_operand:DI 2 "general_operand" "do") ) )
4491 (clobber (reg:CC CC_REGNUM))]
4494 "&& reload_completed"
4496 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4497 (clobber (reg:CC CC_REGNUM))])
4499 [(set (reg:CCL1 CC_REGNUM)
4500 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4502 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4504 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4506 (label_ref (match_dup 9))))
4508 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4509 (clobber (reg:CC CC_REGNUM))])
4511 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4512 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4513 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4514 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4515 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4516 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4517 operands[9] = gen_label_rtx ();")
4520 ; addsi3 instruction pattern(s).
4523 (define_expand "addsi3"
4525 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4526 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4527 (match_operand:SI 2 "general_operand" "")))
4528 (clobber (reg:CC CC_REGNUM))])]
4532 (define_insn "*addsi3_sign"
4533 [(set (match_operand:SI 0 "register_operand" "=d,d")
4534 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4535 (match_operand:SI 1 "register_operand" "0,0")))
4536 (clobber (reg:CC CC_REGNUM))]
4541 [(set_attr "op_type" "RX,RXY")
4542 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4545 ; add(di|si)3 instruction pattern(s).
4548 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4549 (define_insn "*add<mode>3"
4550 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4551 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4552 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4553 (clobber (reg:CC CC_REGNUM))]
4565 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4566 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4567 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4568 z10_super_E1,z10_super_E1,z10_super_E1")])
4570 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4571 (define_insn "*add<mode>3_carry1_cc"
4572 [(set (reg CC_REGNUM)
4573 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4574 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4576 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4577 (plus:GPR (match_dup 1) (match_dup 2)))]
4578 "s390_match_ccmode (insn, CCL1mode)"
4584 al<g>hsik\t%0,%1,%h2
4588 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4589 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4590 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4591 z10_super_E1,z10_super_E1,z10_super_E1")])
4593 ; alr, al, aly, algr, alg, alrk, algrk
4594 (define_insn "*add<mode>3_carry1_cconly"
4595 [(set (reg CC_REGNUM)
4596 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4597 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4599 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4600 "s390_match_ccmode (insn, CCL1mode)"
4606 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4607 (set_attr "cpu_facility" "*,z196,*,*")
4608 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4610 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4611 (define_insn "*add<mode>3_carry2_cc"
4612 [(set (reg CC_REGNUM)
4613 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4614 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4616 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4617 (plus:GPR (match_dup 1) (match_dup 2)))]
4618 "s390_match_ccmode (insn, CCL1mode)"
4624 al<g>hsik\t%0,%1,%h2
4628 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4629 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4630 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4631 z10_super_E1,z10_super_E1,z10_super_E1")])
4633 ; alr, al, aly, algr, alg, alrk, algrk
4634 (define_insn "*add<mode>3_carry2_cconly"
4635 [(set (reg CC_REGNUM)
4636 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4637 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4639 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4640 "s390_match_ccmode (insn, CCL1mode)"
4646 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4647 (set_attr "cpu_facility" "*,z196,*,*")
4648 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4650 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4651 (define_insn "*add<mode>3_cc"
4652 [(set (reg CC_REGNUM)
4653 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4654 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4656 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4657 (plus:GPR (match_dup 1) (match_dup 2)))]
4658 "s390_match_ccmode (insn, CCLmode)"
4664 al<g>hsik\t%0,%1,%h2
4668 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4669 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4670 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4671 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4673 ; alr, al, aly, algr, alg, alrk, algrk
4674 (define_insn "*add<mode>3_cconly"
4675 [(set (reg CC_REGNUM)
4676 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4677 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4679 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4680 "s390_match_ccmode (insn, CCLmode)"
4686 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4687 (set_attr "cpu_facility" "*,z196,*,*")
4688 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4690 ; alr, al, aly, algr, alg, alrk, algrk
4691 (define_insn "*add<mode>3_cconly2"
4692 [(set (reg CC_REGNUM)
4693 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4694 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4695 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4696 "s390_match_ccmode(insn, CCLmode)"
4702 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4703 (set_attr "cpu_facility" "*,z196,*,*")
4704 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4706 ; ahi, afi, aghi, agfi, asi, agsi
4707 (define_insn "*add<mode>3_imm_cc"
4708 [(set (reg CC_REGNUM)
4709 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4710 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4712 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4713 (plus:GPR (match_dup 1) (match_dup 2)))]
4714 "s390_match_ccmode (insn, CCAmode)
4715 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4716 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4717 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4718 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4724 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4725 (set_attr "cpu_facility" "*,z196,extimm,z10")
4726 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4729 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4732 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4733 (define_insn "add<mode>3"
4734 [(set (match_operand:FP 0 "register_operand" "=f, f")
4735 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4736 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4737 (clobber (reg:CC CC_REGNUM))]
4740 a<xde><bt>r\t%0,<op1>%2
4742 [(set_attr "op_type" "<RRer>,RXE")
4743 (set_attr "type" "fsimp<mode>")])
4745 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4746 (define_insn "*add<mode>3_cc"
4747 [(set (reg CC_REGNUM)
4748 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4749 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4750 (match_operand:FP 3 "const0_operand" "")))
4751 (set (match_operand:FP 0 "register_operand" "=f,f")
4752 (plus:FP (match_dup 1) (match_dup 2)))]
4753 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4755 a<xde><bt>r\t%0,<op1>%2
4757 [(set_attr "op_type" "<RRer>,RXE")
4758 (set_attr "type" "fsimp<mode>")])
4760 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4761 (define_insn "*add<mode>3_cconly"
4762 [(set (reg CC_REGNUM)
4763 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4764 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4765 (match_operand:FP 3 "const0_operand" "")))
4766 (clobber (match_scratch:FP 0 "=f,f"))]
4767 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4769 a<xde><bt>r\t%0,<op1>%2
4771 [(set_attr "op_type" "<RRer>,RXE")
4772 (set_attr "type" "fsimp<mode>")])
4776 ;;- Subtract instructions.
4780 ; subti3 instruction pattern(s).
4783 (define_insn_and_split "subti3"
4784 [(set (match_operand:TI 0 "register_operand" "=&d")
4785 (minus:TI (match_operand:TI 1 "register_operand" "0")
4786 (match_operand:TI 2 "general_operand" "do") ) )
4787 (clobber (reg:CC CC_REGNUM))]
4790 "&& reload_completed"
4792 [(set (reg:CCL2 CC_REGNUM)
4793 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4795 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4797 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4798 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4799 (clobber (reg:CC CC_REGNUM))])]
4800 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4801 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4802 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4803 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4804 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4805 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4808 ; subdi3 instruction pattern(s).
4811 (define_expand "subdi3"
4813 [(set (match_operand:DI 0 "register_operand" "")
4814 (minus:DI (match_operand:DI 1 "register_operand" "")
4815 (match_operand:DI 2 "general_operand" "")))
4816 (clobber (reg:CC CC_REGNUM))])]
4820 (define_insn "*subdi3_sign"
4821 [(set (match_operand:DI 0 "register_operand" "=d,d")
4822 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4823 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4824 (clobber (reg:CC CC_REGNUM))]
4829 [(set_attr "op_type" "RRE,RXY")
4830 (set_attr "z10prop" "z10_c,*")
4831 (set_attr "z196prop" "z196_cracked")])
4833 (define_insn "*subdi3_zero_cc"
4834 [(set (reg CC_REGNUM)
4835 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4836 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4838 (set (match_operand:DI 0 "register_operand" "=d,d")
4839 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4840 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4844 [(set_attr "op_type" "RRE,RXY")
4845 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4847 (define_insn "*subdi3_zero_cconly"
4848 [(set (reg CC_REGNUM)
4849 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4850 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4852 (clobber (match_scratch:DI 0 "=d,d"))]
4853 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4857 [(set_attr "op_type" "RRE,RXY")
4858 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4860 (define_insn "*subdi3_zero"
4861 [(set (match_operand:DI 0 "register_operand" "=d,d")
4862 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4863 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4864 (clobber (reg:CC CC_REGNUM))]
4869 [(set_attr "op_type" "RRE,RXY")
4870 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4872 (define_insn_and_split "*subdi3_31z"
4873 [(set (match_operand:DI 0 "register_operand" "=&d")
4874 (minus:DI (match_operand:DI 1 "register_operand" "0")
4875 (match_operand:DI 2 "general_operand" "do") ) )
4876 (clobber (reg:CC CC_REGNUM))]
4877 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4879 "&& reload_completed"
4881 [(set (reg:CCL2 CC_REGNUM)
4882 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4884 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4886 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4887 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4888 (clobber (reg:CC CC_REGNUM))])]
4889 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4890 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4891 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4892 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4893 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4894 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4896 (define_insn_and_split "*subdi3_31"
4897 [(set (match_operand:DI 0 "register_operand" "=&d")
4898 (minus:DI (match_operand:DI 1 "register_operand" "0")
4899 (match_operand:DI 2 "general_operand" "do") ) )
4900 (clobber (reg:CC CC_REGNUM))]
4903 "&& reload_completed"
4905 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4906 (clobber (reg:CC CC_REGNUM))])
4908 [(set (reg:CCL2 CC_REGNUM)
4909 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4911 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4913 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4915 (label_ref (match_dup 9))))
4917 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4918 (clobber (reg:CC CC_REGNUM))])
4920 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4921 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4922 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4923 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4924 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4925 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4926 operands[9] = gen_label_rtx ();")
4929 ; subsi3 instruction pattern(s).
4932 (define_expand "subsi3"
4934 [(set (match_operand:SI 0 "register_operand" "")
4935 (minus:SI (match_operand:SI 1 "register_operand" "")
4936 (match_operand:SI 2 "general_operand" "")))
4937 (clobber (reg:CC CC_REGNUM))])]
4941 (define_insn "*subsi3_sign"
4942 [(set (match_operand:SI 0 "register_operand" "=d,d")
4943 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4944 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4945 (clobber (reg:CC CC_REGNUM))]
4950 [(set_attr "op_type" "RX,RXY")
4951 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4954 ; sub(di|si)3 instruction pattern(s).
4957 ; sr, s, sy, sgr, sg, srk, sgrk
4958 (define_insn "*sub<mode>3"
4959 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4960 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4961 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
4962 (clobber (reg:CC CC_REGNUM))]
4969 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4970 (set_attr "cpu_facility" "*,z196,*,*")
4971 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
4973 ; slr, sl, sly, slgr, slg, slrk, slgrk
4974 (define_insn "*sub<mode>3_borrow_cc"
4975 [(set (reg CC_REGNUM)
4976 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4977 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4979 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4980 (minus:GPR (match_dup 1) (match_dup 2)))]
4981 "s390_match_ccmode (insn, CCL2mode)"
4987 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4988 (set_attr "cpu_facility" "*,z196,*,*")
4989 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
4991 ; slr, sl, sly, slgr, slg, slrk, slgrk
4992 (define_insn "*sub<mode>3_borrow_cconly"
4993 [(set (reg CC_REGNUM)
4994 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4995 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4997 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4998 "s390_match_ccmode (insn, CCL2mode)"
5004 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5005 (set_attr "cpu_facility" "*,z196,*,*")
5006 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5008 ; slr, sl, sly, slgr, slg, slrk, slgrk
5009 (define_insn "*sub<mode>3_cc"
5010 [(set (reg CC_REGNUM)
5011 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5012 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5014 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5015 (minus:GPR (match_dup 1) (match_dup 2)))]
5016 "s390_match_ccmode (insn, CCLmode)"
5022 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5023 (set_attr "cpu_facility" "*,z196,*,*")
5024 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5026 ; slr, sl, sly, slgr, slg, slrk, slgrk
5027 (define_insn "*sub<mode>3_cc2"
5028 [(set (reg CC_REGNUM)
5029 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5030 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5031 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5032 (minus:GPR (match_dup 1) (match_dup 2)))]
5033 "s390_match_ccmode (insn, CCL3mode)"
5039 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5040 (set_attr "cpu_facility" "*,z196,*,*")
5041 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5043 ; slr, sl, sly, slgr, slg, slrk, slgrk
5044 (define_insn "*sub<mode>3_cconly"
5045 [(set (reg CC_REGNUM)
5046 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5047 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5049 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5050 "s390_match_ccmode (insn, CCLmode)"
5056 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5057 (set_attr "cpu_facility" "*,z196,*,*")
5058 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5061 ; slr, sl, sly, slgr, slg, slrk, slgrk
5062 (define_insn "*sub<mode>3_cconly2"
5063 [(set (reg CC_REGNUM)
5064 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5065 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5066 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5067 "s390_match_ccmode (insn, CCL3mode)"
5073 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5074 (set_attr "cpu_facility" "*,z196,*,*")
5075 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5079 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5082 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5083 (define_insn "sub<mode>3"
5084 [(set (match_operand:FP 0 "register_operand" "=f, f")
5085 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5086 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5087 (clobber (reg:CC CC_REGNUM))]
5090 s<xde><bt>r\t%0,<op1>%2
5092 [(set_attr "op_type" "<RRer>,RXE")
5093 (set_attr "type" "fsimp<mode>")])
5095 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5096 (define_insn "*sub<mode>3_cc"
5097 [(set (reg CC_REGNUM)
5098 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5099 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5100 (match_operand:FP 3 "const0_operand" "")))
5101 (set (match_operand:FP 0 "register_operand" "=f,f")
5102 (minus:FP (match_dup 1) (match_dup 2)))]
5103 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5105 s<xde><bt>r\t%0,<op1>%2
5107 [(set_attr "op_type" "<RRer>,RXE")
5108 (set_attr "type" "fsimp<mode>")])
5110 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5111 (define_insn "*sub<mode>3_cconly"
5112 [(set (reg CC_REGNUM)
5113 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5114 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5115 (match_operand:FP 3 "const0_operand" "")))
5116 (clobber (match_scratch:FP 0 "=f,f"))]
5117 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5119 s<xde><bt>r\t%0,<op1>%2
5121 [(set_attr "op_type" "<RRer>,RXE")
5122 (set_attr "type" "fsimp<mode>")])
5126 ;;- Conditional add/subtract instructions.
5130 ; add(di|si)cc instruction pattern(s).
5133 ; the following 4 patterns are used when the result of an add with
5134 ; carry is checked for an overflow condition
5136 ; op1 + op2 + c < op1
5138 ; alcr, alc, alcgr, alcg
5139 (define_insn "*add<mode>3_alc_carry1_cc"
5140 [(set (reg CC_REGNUM)
5142 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5143 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5144 (match_operand:GPR 2 "general_operand" "d,RT"))
5146 (set (match_operand:GPR 0 "register_operand" "=d,d")
5147 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5148 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5152 [(set_attr "op_type" "RRE,RXY")
5153 (set_attr "z196prop" "z196_alone,z196_alone")])
5155 ; alcr, alc, alcgr, alcg
5156 (define_insn "*add<mode>3_alc_carry1_cconly"
5157 [(set (reg CC_REGNUM)
5159 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5160 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5161 (match_operand:GPR 2 "general_operand" "d,RT"))
5163 (clobber (match_scratch:GPR 0 "=d,d"))]
5164 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5168 [(set_attr "op_type" "RRE,RXY")
5169 (set_attr "z196prop" "z196_alone,z196_alone")])
5171 ; op1 + op2 + c < op2
5173 ; alcr, alc, alcgr, alcg
5174 (define_insn "*add<mode>3_alc_carry2_cc"
5175 [(set (reg CC_REGNUM)
5177 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5178 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5179 (match_operand:GPR 2 "general_operand" "d,RT"))
5181 (set (match_operand:GPR 0 "register_operand" "=d,d")
5182 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5183 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5187 [(set_attr "op_type" "RRE,RXY")])
5189 ; alcr, alc, alcgr, alcg
5190 (define_insn "*add<mode>3_alc_carry2_cconly"
5191 [(set (reg CC_REGNUM)
5193 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5194 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5195 (match_operand:GPR 2 "general_operand" "d,RT"))
5197 (clobber (match_scratch:GPR 0 "=d,d"))]
5198 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5202 [(set_attr "op_type" "RRE,RXY")])
5204 ; alcr, alc, alcgr, alcg
5205 (define_insn "*add<mode>3_alc_cc"
5206 [(set (reg CC_REGNUM)
5208 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5209 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5210 (match_operand:GPR 2 "general_operand" "d,RT"))
5212 (set (match_operand:GPR 0 "register_operand" "=d,d")
5213 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5214 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5218 [(set_attr "op_type" "RRE,RXY")])
5220 ; alcr, alc, alcgr, alcg
5221 (define_insn "*add<mode>3_alc"
5222 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5223 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5224 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5225 (match_operand:GPR 2 "general_operand" "d,RT")))
5226 (clobber (reg:CC CC_REGNUM))]
5231 [(set_attr "op_type" "RRE,RXY")])
5233 ; slbr, slb, slbgr, slbg
5234 (define_insn "*sub<mode>3_slb_cc"
5235 [(set (reg CC_REGNUM)
5237 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5238 (match_operand:GPR 2 "general_operand" "d,RT"))
5239 (match_operand:GPR 3 "s390_slb_comparison" ""))
5241 (set (match_operand:GPR 0 "register_operand" "=d,d")
5242 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5243 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5247 [(set_attr "op_type" "RRE,RXY")
5248 (set_attr "z10prop" "z10_c,*")])
5250 ; slbr, slb, slbgr, slbg
5251 (define_insn "*sub<mode>3_slb"
5252 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5253 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5254 (match_operand:GPR 2 "general_operand" "d,RT"))
5255 (match_operand:GPR 3 "s390_slb_comparison" "")))
5256 (clobber (reg:CC CC_REGNUM))]
5261 [(set_attr "op_type" "RRE,RXY")
5262 (set_attr "z10prop" "z10_c,*")])
5264 (define_expand "add<mode>cc"
5265 [(match_operand:GPR 0 "register_operand" "")
5266 (match_operand 1 "comparison_operator" "")
5267 (match_operand:GPR 2 "register_operand" "")
5268 (match_operand:GPR 3 "const_int_operand" "")]
5270 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5271 XEXP (operands[1], 0), XEXP (operands[1], 1),
5272 operands[0], operands[2],
5273 operands[3])) FAIL; DONE;")
5276 ; scond instruction pattern(s).
5279 (define_insn_and_split "*scond<mode>"
5280 [(set (match_operand:GPR 0 "register_operand" "=&d")
5281 (match_operand:GPR 1 "s390_alc_comparison" ""))
5282 (clobber (reg:CC CC_REGNUM))]
5285 "&& reload_completed"
5286 [(set (match_dup 0) (const_int 0))
5288 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5290 (clobber (reg:CC CC_REGNUM))])]
5293 (define_insn_and_split "*scond<mode>_neg"
5294 [(set (match_operand:GPR 0 "register_operand" "=&d")
5295 (match_operand:GPR 1 "s390_slb_comparison" ""))
5296 (clobber (reg:CC CC_REGNUM))]
5299 "&& reload_completed"
5300 [(set (match_dup 0) (const_int 0))
5302 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5304 (clobber (reg:CC CC_REGNUM))])
5306 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5307 (clobber (reg:CC CC_REGNUM))])]
5311 (define_expand "cstore<mode>4"
5312 [(set (match_operand:SI 0 "register_operand" "")
5313 (match_operator:SI 1 "s390_scond_operator"
5314 [(match_operand:GPR 2 "register_operand" "")
5315 (match_operand:GPR 3 "general_operand" "")]))]
5317 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5318 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5320 (define_expand "cstorecc4"
5322 [(set (match_operand:SI 0 "register_operand" "")
5323 (match_operator:SI 1 "s390_eqne_operator"
5324 [(match_operand:CCZ1 2 "register_operand")
5325 (match_operand 3 "const0_operand")]))
5326 (clobber (reg:CC CC_REGNUM))])]
5328 "emit_insn (gen_sne (operands[0], operands[2]));
5329 if (GET_CODE (operands[1]) == EQ)
5330 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5333 (define_insn_and_split "sne"
5334 [(set (match_operand:SI 0 "register_operand" "=d")
5335 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5337 (clobber (reg:CC CC_REGNUM))]
5342 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5343 (clobber (reg:CC CC_REGNUM))])])
5347 ;; - Conditional move instructions (introduced with z196)
5350 (define_expand "mov<mode>cc"
5351 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5352 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5353 (match_operand:GPR 2 "nonimmediate_operand" "")
5354 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5356 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5357 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5359 ; locr, loc, stoc, locgr, locg, stocg
5360 (define_insn_and_split "*mov<mode>cc"
5361 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5363 (match_operator 1 "s390_comparison"
5364 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5366 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5367 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5377 "&& reload_completed
5378 && MEM_P (operands[3]) && MEM_P (operands[4])"
5381 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5386 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5390 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5393 ;;- Multiply instructions.
5397 ; muldi3 instruction pattern(s).
5400 (define_insn "*muldi3_sign"
5401 [(set (match_operand:DI 0 "register_operand" "=d,d")
5402 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5403 (match_operand:DI 1 "register_operand" "0,0")))]
5408 [(set_attr "op_type" "RRE,RXY")
5409 (set_attr "type" "imuldi")])
5411 (define_insn "muldi3"
5412 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5413 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5414 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5421 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5422 (set_attr "type" "imuldi")
5423 (set_attr "cpu_facility" "*,*,*,z10")])
5426 ; mulsi3 instruction pattern(s).
5429 (define_insn "*mulsi3_sign"
5430 [(set (match_operand:SI 0 "register_operand" "=d,d")
5431 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5432 (match_operand:SI 1 "register_operand" "0,0")))]
5437 [(set_attr "op_type" "RX,RXY")
5438 (set_attr "type" "imulhi")
5439 (set_attr "cpu_facility" "*,z10")])
5441 (define_insn "mulsi3"
5442 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5443 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5444 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5452 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5453 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5454 (set_attr "cpu_facility" "*,*,*,*,z10")])
5457 ; mulsidi3 instruction pattern(s).
5460 (define_insn "mulsidi3"
5461 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5462 (mult:DI (sign_extend:DI
5463 (match_operand:SI 1 "register_operand" "%0,0,0"))
5465 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5471 [(set_attr "op_type" "RR,RX,RXY")
5472 (set_attr "type" "imulsi")
5473 (set_attr "cpu_facility" "*,*,z10")])
5476 ; umul instruction pattern(s).
5479 ; mlr, ml, mlgr, mlg
5480 (define_insn "umul<dwh><mode>3"
5481 [(set (match_operand:DW 0 "register_operand" "=d, d")
5482 (mult:DW (zero_extend:DW
5483 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5485 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5490 [(set_attr "op_type" "RRE,RXY")
5491 (set_attr "type" "imul<dwh>")])
5494 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5497 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5498 (define_insn "mul<mode>3"
5499 [(set (match_operand:FP 0 "register_operand" "=f,f")
5500 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5501 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5504 m<xdee><bt>r\t%0,<op1>%2
5506 [(set_attr "op_type" "<RRer>,RXE")
5507 (set_attr "type" "fmul<mode>")])
5509 ; madbr, maebr, maxb, madb, maeb
5510 (define_insn "fma<mode>4"
5511 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5512 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5513 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5514 (match_operand:DSF 3 "register_operand" "0,0")))]
5519 [(set_attr "op_type" "RRE,RXE")
5520 (set_attr "type" "fmadd<mode>")])
5522 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5523 (define_insn "fms<mode>4"
5524 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5525 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5526 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5527 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5532 [(set_attr "op_type" "RRE,RXE")
5533 (set_attr "type" "fmadd<mode>")])
5536 ;;- Divide and modulo instructions.
5540 ; divmoddi4 instruction pattern(s).
5543 (define_expand "divmoddi4"
5544 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5545 (div:DI (match_operand:DI 1 "register_operand" "")
5546 (match_operand:DI 2 "general_operand" "")))
5547 (set (match_operand:DI 3 "general_operand" "")
5548 (mod:DI (match_dup 1) (match_dup 2)))])
5549 (clobber (match_dup 4))]
5552 rtx insn, div_equal, mod_equal;
5554 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5555 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5557 operands[4] = gen_reg_rtx(TImode);
5558 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5560 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5561 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5563 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5564 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5569 (define_insn "divmodtidi3"
5570 [(set (match_operand:TI 0 "register_operand" "=d,d")
5574 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5575 (match_operand:DI 2 "general_operand" "d,RT")))
5577 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5582 [(set_attr "op_type" "RRE,RXY")
5583 (set_attr "type" "idiv")])
5585 (define_insn "divmodtisi3"
5586 [(set (match_operand:TI 0 "register_operand" "=d,d")
5590 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5592 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5595 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5600 [(set_attr "op_type" "RRE,RXY")
5601 (set_attr "type" "idiv")])
5604 ; udivmoddi4 instruction pattern(s).
5607 (define_expand "udivmoddi4"
5608 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5609 (udiv:DI (match_operand:DI 1 "general_operand" "")
5610 (match_operand:DI 2 "nonimmediate_operand" "")))
5611 (set (match_operand:DI 3 "general_operand" "")
5612 (umod:DI (match_dup 1) (match_dup 2)))])
5613 (clobber (match_dup 4))]
5616 rtx insn, div_equal, mod_equal, equal;
5618 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5619 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5620 equal = gen_rtx_IOR (TImode,
5621 gen_rtx_ASHIFT (TImode,
5622 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5624 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5626 operands[4] = gen_reg_rtx(TImode);
5627 emit_clobber (operands[4]);
5628 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5629 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5631 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5632 set_unique_reg_note (insn, REG_EQUAL, equal);
5634 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5635 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5637 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5638 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5643 (define_insn "udivmodtidi3"
5644 [(set (match_operand:TI 0 "register_operand" "=d,d")
5649 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5651 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5655 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5660 [(set_attr "op_type" "RRE,RXY")
5661 (set_attr "type" "idiv")])
5664 ; divmodsi4 instruction pattern(s).
5667 (define_expand "divmodsi4"
5668 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5669 (div:SI (match_operand:SI 1 "general_operand" "")
5670 (match_operand:SI 2 "nonimmediate_operand" "")))
5671 (set (match_operand:SI 3 "general_operand" "")
5672 (mod:SI (match_dup 1) (match_dup 2)))])
5673 (clobber (match_dup 4))]
5676 rtx insn, div_equal, mod_equal, equal;
5678 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5679 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5680 equal = gen_rtx_IOR (DImode,
5681 gen_rtx_ASHIFT (DImode,
5682 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5684 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5686 operands[4] = gen_reg_rtx(DImode);
5687 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5689 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5690 set_unique_reg_note (insn, REG_EQUAL, equal);
5692 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5693 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5695 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5696 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5701 (define_insn "divmoddisi3"
5702 [(set (match_operand:DI 0 "register_operand" "=d,d")
5707 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5709 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5713 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5718 [(set_attr "op_type" "RR,RX")
5719 (set_attr "type" "idiv")])
5722 ; udivsi3 and umodsi3 instruction pattern(s).
5725 (define_expand "udivmodsi4"
5726 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5727 (udiv:SI (match_operand:SI 1 "general_operand" "")
5728 (match_operand:SI 2 "nonimmediate_operand" "")))
5729 (set (match_operand:SI 3 "general_operand" "")
5730 (umod:SI (match_dup 1) (match_dup 2)))])
5731 (clobber (match_dup 4))]
5732 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5734 rtx insn, div_equal, mod_equal, equal;
5736 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5737 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5738 equal = gen_rtx_IOR (DImode,
5739 gen_rtx_ASHIFT (DImode,
5740 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5742 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5744 operands[4] = gen_reg_rtx(DImode);
5745 emit_clobber (operands[4]);
5746 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5747 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5749 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5750 set_unique_reg_note (insn, REG_EQUAL, equal);
5752 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5753 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5755 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5756 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5761 (define_insn "udivmoddisi3"
5762 [(set (match_operand:DI 0 "register_operand" "=d,d")
5767 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5769 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5773 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5774 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5778 [(set_attr "op_type" "RRE,RXY")
5779 (set_attr "type" "idiv")])
5781 (define_expand "udivsi3"
5782 [(set (match_operand:SI 0 "register_operand" "=d")
5783 (udiv:SI (match_operand:SI 1 "general_operand" "")
5784 (match_operand:SI 2 "general_operand" "")))
5785 (clobber (match_dup 3))]
5786 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5788 rtx insn, udiv_equal, umod_equal, equal;
5790 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5791 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5792 equal = gen_rtx_IOR (DImode,
5793 gen_rtx_ASHIFT (DImode,
5794 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5796 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5798 operands[3] = gen_reg_rtx (DImode);
5800 if (CONSTANT_P (operands[2]))
5802 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5804 rtx label1 = gen_label_rtx ();
5806 operands[1] = make_safe_from (operands[1], operands[0]);
5807 emit_move_insn (operands[0], const0_rtx);
5808 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5810 emit_move_insn (operands[0], const1_rtx);
5811 emit_label (label1);
5815 operands[2] = force_reg (SImode, operands[2]);
5816 operands[2] = make_safe_from (operands[2], operands[0]);
5818 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5819 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5821 set_unique_reg_note (insn, REG_EQUAL, equal);
5823 insn = emit_move_insn (operands[0],
5824 gen_lowpart (SImode, operands[3]));
5825 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5830 rtx label1 = gen_label_rtx ();
5831 rtx label2 = gen_label_rtx ();
5832 rtx label3 = gen_label_rtx ();
5834 operands[1] = force_reg (SImode, operands[1]);
5835 operands[1] = make_safe_from (operands[1], operands[0]);
5836 operands[2] = force_reg (SImode, operands[2]);
5837 operands[2] = make_safe_from (operands[2], operands[0]);
5839 emit_move_insn (operands[0], const0_rtx);
5840 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5842 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5844 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5846 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5847 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5849 set_unique_reg_note (insn, REG_EQUAL, equal);
5851 insn = emit_move_insn (operands[0],
5852 gen_lowpart (SImode, operands[3]));
5853 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5856 emit_label (label1);
5857 emit_move_insn (operands[0], operands[1]);
5859 emit_label (label2);
5860 emit_move_insn (operands[0], const1_rtx);
5861 emit_label (label3);
5863 emit_move_insn (operands[0], operands[0]);
5867 (define_expand "umodsi3"
5868 [(set (match_operand:SI 0 "register_operand" "=d")
5869 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5870 (match_operand:SI 2 "nonimmediate_operand" "")))
5871 (clobber (match_dup 3))]
5872 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5874 rtx insn, udiv_equal, umod_equal, equal;
5876 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5877 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5878 equal = gen_rtx_IOR (DImode,
5879 gen_rtx_ASHIFT (DImode,
5880 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5882 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5884 operands[3] = gen_reg_rtx (DImode);
5886 if (CONSTANT_P (operands[2]))
5888 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5890 rtx label1 = gen_label_rtx ();
5892 operands[1] = make_safe_from (operands[1], operands[0]);
5893 emit_move_insn (operands[0], operands[1]);
5894 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5896 emit_insn (gen_abssi2 (operands[0], operands[2]));
5897 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5898 emit_label (label1);
5902 operands[2] = force_reg (SImode, operands[2]);
5903 operands[2] = make_safe_from (operands[2], operands[0]);
5905 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5906 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5908 set_unique_reg_note (insn, REG_EQUAL, equal);
5910 insn = emit_move_insn (operands[0],
5911 gen_highpart (SImode, operands[3]));
5912 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5917 rtx label1 = gen_label_rtx ();
5918 rtx label2 = gen_label_rtx ();
5919 rtx label3 = gen_label_rtx ();
5921 operands[1] = force_reg (SImode, operands[1]);
5922 operands[1] = make_safe_from (operands[1], operands[0]);
5923 operands[2] = force_reg (SImode, operands[2]);
5924 operands[2] = make_safe_from (operands[2], operands[0]);
5926 emit_move_insn(operands[0], operands[1]);
5927 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5929 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5931 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5933 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5934 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5936 set_unique_reg_note (insn, REG_EQUAL, equal);
5938 insn = emit_move_insn (operands[0],
5939 gen_highpart (SImode, operands[3]));
5940 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5943 emit_label (label1);
5944 emit_move_insn (operands[0], const0_rtx);
5946 emit_label (label2);
5947 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5948 emit_label (label3);
5954 ; div(df|sf)3 instruction pattern(s).
5957 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5958 (define_insn "div<mode>3"
5959 [(set (match_operand:FP 0 "register_operand" "=f,f")
5960 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5961 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5964 d<xde><bt>r\t%0,<op1>%2
5966 [(set_attr "op_type" "<RRer>,RXE")
5967 (set_attr "type" "fdiv<mode>")])
5971 ;;- And instructions.
5974 (define_expand "and<mode>3"
5975 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5976 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5977 (match_operand:INT 2 "general_operand" "")))
5978 (clobber (reg:CC CC_REGNUM))]
5980 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5983 ; anddi3 instruction pattern(s).
5986 (define_insn "*anddi3_cc"
5987 [(set (reg CC_REGNUM)
5988 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
5989 (match_operand:DI 2 "general_operand" " d,d,RT"))
5991 (set (match_operand:DI 0 "register_operand" "=d,d, d")
5992 (and:DI (match_dup 1) (match_dup 2)))]
5993 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
5998 [(set_attr "op_type" "RRE,RRF,RXY")
5999 (set_attr "cpu_facility" "*,z196,*")
6000 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6002 (define_insn "*anddi3_cconly"
6003 [(set (reg CC_REGNUM)
6004 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6005 (match_operand:DI 2 "general_operand" " d,d,RT"))
6007 (clobber (match_scratch:DI 0 "=d,d, d"))]
6008 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
6009 /* Do not steal TM patterns. */
6010 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6015 [(set_attr "op_type" "RRE,RRF,RXY")
6016 (set_attr "cpu_facility" "*,z196,*")
6017 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6019 (define_insn "*anddi3"
6020 [(set (match_operand:DI 0 "nonimmediate_operand"
6021 "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
6022 (and:DI (match_operand:DI 1 "nonimmediate_operand"
6023 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6024 (match_operand:DI 2 "general_operand"
6025 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
6026 (clobber (reg:CC CC_REGNUM))]
6027 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6042 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6043 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
6044 (set_attr "z10prop" "*,
6059 [(set (match_operand:DI 0 "s_operand" "")
6060 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6061 (clobber (reg:CC CC_REGNUM))]
6064 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6065 (clobber (reg:CC CC_REGNUM))])]
6066 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6070 ; andsi3 instruction pattern(s).
6073 (define_insn "*andsi3_cc"
6074 [(set (reg CC_REGNUM)
6075 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6076 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6078 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6079 (and:SI (match_dup 1) (match_dup 2)))]
6080 "s390_match_ccmode(insn, CCTmode)"
6087 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6088 (set_attr "cpu_facility" "*,*,z196,*,*")
6089 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6091 (define_insn "*andsi3_cconly"
6092 [(set (reg CC_REGNUM)
6093 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6094 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6096 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6097 "s390_match_ccmode(insn, CCTmode)
6098 /* Do not steal TM patterns. */
6099 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6106 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6107 (set_attr "cpu_facility" "*,*,z196,*,*")
6108 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6109 z10_super_E1,z10_super_E1")])
6111 (define_insn "*andsi3_zarch"
6112 [(set (match_operand:SI 0 "nonimmediate_operand"
6113 "=d,d, d, d, d,d,d,d,d, AQ,Q")
6114 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6115 "%d,o, 0, 0, 0,0,d,0,0, 0,0")
6116 (match_operand:SI 2 "general_operand"
6117 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
6118 (clobber (reg:CC CC_REGNUM))]
6119 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6132 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6133 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
6134 (set_attr "z10prop" "*,
6146 (define_insn "*andsi3_esa"
6147 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6148 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6149 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6150 (clobber (reg:CC CC_REGNUM))]
6151 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6157 [(set_attr "op_type" "RR,RX,SI,SS")
6158 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6162 [(set (match_operand:SI 0 "s_operand" "")
6163 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6164 (clobber (reg:CC CC_REGNUM))]
6167 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6168 (clobber (reg:CC CC_REGNUM))])]
6169 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6172 ; andhi3 instruction pattern(s).
6175 (define_insn "*andhi3_zarch"
6176 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6177 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6178 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6179 (clobber (reg:CC CC_REGNUM))]
6180 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6187 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6188 (set_attr "cpu_facility" "*,z196,*,*,*")
6189 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6192 (define_insn "*andhi3_esa"
6193 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6194 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6195 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6196 (clobber (reg:CC CC_REGNUM))]
6197 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6202 [(set_attr "op_type" "RR,SI,SS")
6203 (set_attr "z10prop" "z10_super_E1,*,*")
6207 [(set (match_operand:HI 0 "s_operand" "")
6208 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6209 (clobber (reg:CC CC_REGNUM))]
6212 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6213 (clobber (reg:CC CC_REGNUM))])]
6214 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6217 ; andqi3 instruction pattern(s).
6220 (define_insn "*andqi3_zarch"
6221 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6222 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6223 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6224 (clobber (reg:CC CC_REGNUM))]
6225 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6233 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6234 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6235 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6237 (define_insn "*andqi3_esa"
6238 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6239 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6240 (match_operand:QI 2 "general_operand" "d,n,Q")))
6241 (clobber (reg:CC CC_REGNUM))]
6242 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6247 [(set_attr "op_type" "RR,SI,SS")
6248 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6251 ; Block and (NC) patterns.
6255 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6256 (and:BLK (match_dup 0)
6257 (match_operand:BLK 1 "memory_operand" "Q")))
6258 (use (match_operand 2 "const_int_operand" "n"))
6259 (clobber (reg:CC CC_REGNUM))]
6260 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6261 "nc\t%O0(%2,%R0),%S1"
6262 [(set_attr "op_type" "SS")
6263 (set_attr "z196prop" "z196_cracked")])
6266 [(set (match_operand 0 "memory_operand" "")
6268 (match_operand 1 "memory_operand" "")))
6269 (clobber (reg:CC CC_REGNUM))]
6271 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6272 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6274 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6276 (clobber (reg:CC CC_REGNUM))])]
6278 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6279 operands[0] = adjust_address (operands[0], BLKmode, 0);
6280 operands[1] = adjust_address (operands[1], BLKmode, 0);
6285 [(set (match_operand:BLK 0 "memory_operand" "")
6286 (and:BLK (match_dup 0)
6287 (match_operand:BLK 1 "memory_operand" "")))
6288 (use (match_operand 2 "const_int_operand" ""))
6289 (clobber (reg:CC CC_REGNUM))])
6291 [(set (match_operand:BLK 3 "memory_operand" "")
6292 (and:BLK (match_dup 3)
6293 (match_operand:BLK 4 "memory_operand" "")))
6294 (use (match_operand 5 "const_int_operand" ""))
6295 (clobber (reg:CC CC_REGNUM))])]
6296 "s390_offset_p (operands[0], operands[3], operands[2])
6297 && s390_offset_p (operands[1], operands[4], operands[2])
6298 && !s390_overlap_p (operands[0], operands[1],
6299 INTVAL (operands[2]) + INTVAL (operands[5]))
6300 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6302 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6304 (clobber (reg:CC CC_REGNUM))])]
6305 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6306 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6307 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6311 ;;- Bit set (inclusive or) instructions.
6314 (define_expand "ior<mode>3"
6315 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6316 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6317 (match_operand:INT 2 "general_operand" "")))
6318 (clobber (reg:CC CC_REGNUM))]
6320 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6323 ; iordi3 instruction pattern(s).
6326 (define_insn "*iordi3_cc"
6327 [(set (reg CC_REGNUM)
6328 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6329 (match_operand:DI 2 "general_operand" " d,d,RT"))
6331 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6332 (ior:DI (match_dup 1) (match_dup 2)))]
6333 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6338 [(set_attr "op_type" "RRE,RRF,RXY")
6339 (set_attr "cpu_facility" "*,z196,*")
6340 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6342 (define_insn "*iordi3_cconly"
6343 [(set (reg CC_REGNUM)
6344 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6345 (match_operand:DI 2 "general_operand" " d,d,RT"))
6347 (clobber (match_scratch:DI 0 "=d,d,d"))]
6348 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6353 [(set_attr "op_type" "RRE,RRF,RXY")
6354 (set_attr "cpu_facility" "*,z196,*")
6355 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6357 (define_insn "*iordi3"
6358 [(set (match_operand:DI 0 "nonimmediate_operand"
6359 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6360 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6361 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6362 (match_operand:DI 2 "general_operand"
6363 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6364 (clobber (reg:CC CC_REGNUM))]
6365 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6378 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6379 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6380 (set_attr "z10prop" "z10_super_E1,
6393 [(set (match_operand:DI 0 "s_operand" "")
6394 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6395 (clobber (reg:CC CC_REGNUM))]
6398 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6399 (clobber (reg:CC CC_REGNUM))])]
6400 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6403 ; iorsi3 instruction pattern(s).
6406 (define_insn "*iorsi3_cc"
6407 [(set (reg CC_REGNUM)
6408 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6409 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6411 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6412 (ior:SI (match_dup 1) (match_dup 2)))]
6413 "s390_match_ccmode(insn, CCTmode)"
6420 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6421 (set_attr "cpu_facility" "*,*,z196,*,*")
6422 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6424 (define_insn "*iorsi3_cconly"
6425 [(set (reg CC_REGNUM)
6426 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6427 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6429 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6430 "s390_match_ccmode(insn, CCTmode)"
6437 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6438 (set_attr "cpu_facility" "*,*,z196,*,*")
6439 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6441 (define_insn "*iorsi3_zarch"
6442 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6443 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6444 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6445 (clobber (reg:CC CC_REGNUM))]
6446 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6457 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6458 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6459 (set_attr "z10prop" "z10_super_E1,
6469 (define_insn "*iorsi3_esa"
6470 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6471 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6472 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6473 (clobber (reg:CC CC_REGNUM))]
6474 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6480 [(set_attr "op_type" "RR,RX,SI,SS")
6481 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6484 [(set (match_operand:SI 0 "s_operand" "")
6485 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6486 (clobber (reg:CC CC_REGNUM))]
6489 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6490 (clobber (reg:CC CC_REGNUM))])]
6491 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6494 ; iorhi3 instruction pattern(s).
6497 (define_insn "*iorhi3_zarch"
6498 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6499 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6500 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6501 (clobber (reg:CC CC_REGNUM))]
6502 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6509 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6510 (set_attr "cpu_facility" "*,z196,*,*,*")
6511 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6513 (define_insn "*iorhi3_esa"
6514 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6515 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6516 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6517 (clobber (reg:CC CC_REGNUM))]
6518 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6523 [(set_attr "op_type" "RR,SI,SS")
6524 (set_attr "z10prop" "z10_super_E1,*,*")])
6527 [(set (match_operand:HI 0 "s_operand" "")
6528 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6529 (clobber (reg:CC CC_REGNUM))]
6532 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6533 (clobber (reg:CC CC_REGNUM))])]
6534 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6537 ; iorqi3 instruction pattern(s).
6540 (define_insn "*iorqi3_zarch"
6541 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6542 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6543 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6544 (clobber (reg:CC CC_REGNUM))]
6545 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6553 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6554 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6555 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6556 z10_super,z10_super,*")])
6558 (define_insn "*iorqi3_esa"
6559 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6560 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6561 (match_operand:QI 2 "general_operand" "d,n,Q")))
6562 (clobber (reg:CC CC_REGNUM))]
6563 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6568 [(set_attr "op_type" "RR,SI,SS")
6569 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6572 ; Block inclusive or (OC) patterns.
6576 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6577 (ior:BLK (match_dup 0)
6578 (match_operand:BLK 1 "memory_operand" "Q")))
6579 (use (match_operand 2 "const_int_operand" "n"))
6580 (clobber (reg:CC CC_REGNUM))]
6581 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6582 "oc\t%O0(%2,%R0),%S1"
6583 [(set_attr "op_type" "SS")
6584 (set_attr "z196prop" "z196_cracked")])
6587 [(set (match_operand 0 "memory_operand" "")
6589 (match_operand 1 "memory_operand" "")))
6590 (clobber (reg:CC CC_REGNUM))]
6592 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6593 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6595 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6597 (clobber (reg:CC CC_REGNUM))])]
6599 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6600 operands[0] = adjust_address (operands[0], BLKmode, 0);
6601 operands[1] = adjust_address (operands[1], BLKmode, 0);
6606 [(set (match_operand:BLK 0 "memory_operand" "")
6607 (ior:BLK (match_dup 0)
6608 (match_operand:BLK 1 "memory_operand" "")))
6609 (use (match_operand 2 "const_int_operand" ""))
6610 (clobber (reg:CC CC_REGNUM))])
6612 [(set (match_operand:BLK 3 "memory_operand" "")
6613 (ior:BLK (match_dup 3)
6614 (match_operand:BLK 4 "memory_operand" "")))
6615 (use (match_operand 5 "const_int_operand" ""))
6616 (clobber (reg:CC CC_REGNUM))])]
6617 "s390_offset_p (operands[0], operands[3], operands[2])
6618 && s390_offset_p (operands[1], operands[4], operands[2])
6619 && !s390_overlap_p (operands[0], operands[1],
6620 INTVAL (operands[2]) + INTVAL (operands[5]))
6621 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6623 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6625 (clobber (reg:CC CC_REGNUM))])]
6626 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6627 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6628 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6632 ;;- Xor instructions.
6635 (define_expand "xor<mode>3"
6636 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6637 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6638 (match_operand:INT 2 "general_operand" "")))
6639 (clobber (reg:CC CC_REGNUM))]
6641 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6644 ; xordi3 instruction pattern(s).
6647 (define_insn "*xordi3_cc"
6648 [(set (reg CC_REGNUM)
6649 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6650 (match_operand:DI 2 "general_operand" " d,d,RT"))
6652 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6653 (xor:DI (match_dup 1) (match_dup 2)))]
6654 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6659 [(set_attr "op_type" "RRE,RRF,RXY")
6660 (set_attr "cpu_facility" "*,z196,*")
6661 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6663 (define_insn "*xordi3_cconly"
6664 [(set (reg CC_REGNUM)
6665 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6666 (match_operand:DI 2 "general_operand" " d,d,RT"))
6668 (clobber (match_scratch:DI 0 "=d,d, d"))]
6669 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6674 [(set_attr "op_type" "RRE,RRF,RXY")
6675 (set_attr "cpu_facility" "*,z196,*")
6676 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6678 (define_insn "*xordi3"
6679 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6680 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6681 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6682 (clobber (reg:CC CC_REGNUM))]
6683 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6692 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6693 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6694 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6695 *,z10_super_E1,*,*")])
6698 [(set (match_operand:DI 0 "s_operand" "")
6699 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6700 (clobber (reg:CC CC_REGNUM))]
6703 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6704 (clobber (reg:CC CC_REGNUM))])]
6705 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6708 ; xorsi3 instruction pattern(s).
6711 (define_insn "*xorsi3_cc"
6712 [(set (reg CC_REGNUM)
6713 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6714 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6716 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6717 (xor:SI (match_dup 1) (match_dup 2)))]
6718 "s390_match_ccmode(insn, CCTmode)"
6725 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6726 (set_attr "cpu_facility" "*,*,z196,*,*")
6727 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6728 z10_super_E1,z10_super_E1")])
6730 (define_insn "*xorsi3_cconly"
6731 [(set (reg CC_REGNUM)
6732 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6733 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6735 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6736 "s390_match_ccmode(insn, CCTmode)"
6743 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6744 (set_attr "cpu_facility" "*,*,z196,*,*")
6745 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6746 z10_super_E1,z10_super_E1")])
6748 (define_insn "*xorsi3"
6749 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6750 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6751 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6752 (clobber (reg:CC CC_REGNUM))]
6753 "s390_logical_operator_ok_p (operands)"
6762 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6763 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6764 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6765 z10_super_E1,z10_super_E1,*,*")])
6768 [(set (match_operand:SI 0 "s_operand" "")
6769 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6770 (clobber (reg:CC CC_REGNUM))]
6773 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6774 (clobber (reg:CC CC_REGNUM))])]
6775 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6778 ; xorhi3 instruction pattern(s).
6781 (define_insn "*xorhi3"
6782 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6783 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6784 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6785 (clobber (reg:CC CC_REGNUM))]
6786 "s390_logical_operator_ok_p (operands)"
6793 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6794 (set_attr "cpu_facility" "*,*,z196,*,*")
6795 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6798 [(set (match_operand:HI 0 "s_operand" "")
6799 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6800 (clobber (reg:CC CC_REGNUM))]
6803 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6804 (clobber (reg:CC CC_REGNUM))])]
6805 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6808 ; xorqi3 instruction pattern(s).
6811 (define_insn "*xorqi3"
6812 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6813 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
6814 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
6815 (clobber (reg:CC CC_REGNUM))]
6816 "s390_logical_operator_ok_p (operands)"
6824 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
6825 (set_attr "cpu_facility" "*,*,z196,*,*,*")
6826 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
6830 ; Block exclusive or (XC) patterns.
6834 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6835 (xor:BLK (match_dup 0)
6836 (match_operand:BLK 1 "memory_operand" "Q")))
6837 (use (match_operand 2 "const_int_operand" "n"))
6838 (clobber (reg:CC CC_REGNUM))]
6839 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6840 "xc\t%O0(%2,%R0),%S1"
6841 [(set_attr "op_type" "SS")])
6844 [(set (match_operand 0 "memory_operand" "")
6846 (match_operand 1 "memory_operand" "")))
6847 (clobber (reg:CC CC_REGNUM))]
6849 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6850 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6852 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6854 (clobber (reg:CC CC_REGNUM))])]
6856 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6857 operands[0] = adjust_address (operands[0], BLKmode, 0);
6858 operands[1] = adjust_address (operands[1], BLKmode, 0);
6863 [(set (match_operand:BLK 0 "memory_operand" "")
6864 (xor:BLK (match_dup 0)
6865 (match_operand:BLK 1 "memory_operand" "")))
6866 (use (match_operand 2 "const_int_operand" ""))
6867 (clobber (reg:CC CC_REGNUM))])
6869 [(set (match_operand:BLK 3 "memory_operand" "")
6870 (xor:BLK (match_dup 3)
6871 (match_operand:BLK 4 "memory_operand" "")))
6872 (use (match_operand 5 "const_int_operand" ""))
6873 (clobber (reg:CC CC_REGNUM))])]
6874 "s390_offset_p (operands[0], operands[3], operands[2])
6875 && s390_offset_p (operands[1], operands[4], operands[2])
6876 && !s390_overlap_p (operands[0], operands[1],
6877 INTVAL (operands[2]) + INTVAL (operands[5]))
6878 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6880 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6882 (clobber (reg:CC CC_REGNUM))])]
6883 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6884 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6885 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6888 ; Block xor (XC) patterns with src == dest.
6891 (define_insn "*xc_zero"
6892 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6894 (use (match_operand 1 "const_int_operand" "n"))
6895 (clobber (reg:CC CC_REGNUM))]
6896 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6897 "xc\t%O0(%1,%R0),%S0"
6898 [(set_attr "op_type" "SS")
6899 (set_attr "z196prop" "z196_cracked")])
6903 [(set (match_operand:BLK 0 "memory_operand" "")
6905 (use (match_operand 1 "const_int_operand" ""))
6906 (clobber (reg:CC CC_REGNUM))])
6908 [(set (match_operand:BLK 2 "memory_operand" "")
6910 (use (match_operand 3 "const_int_operand" ""))
6911 (clobber (reg:CC CC_REGNUM))])]
6912 "s390_offset_p (operands[0], operands[2], operands[1])
6913 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6915 [(set (match_dup 4) (const_int 0))
6917 (clobber (reg:CC CC_REGNUM))])]
6918 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6919 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6923 ;;- Negate instructions.
6927 ; neg(di|si)2 instruction pattern(s).
6930 (define_expand "neg<mode>2"
6932 [(set (match_operand:DSI 0 "register_operand" "=d")
6933 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6934 (clobber (reg:CC CC_REGNUM))])]
6938 (define_insn "*negdi2_sign_cc"
6939 [(set (reg CC_REGNUM)
6940 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6941 (match_operand:SI 1 "register_operand" "d") 0)
6942 (const_int 32)) (const_int 32)))
6944 (set (match_operand:DI 0 "register_operand" "=d")
6945 (neg:DI (sign_extend:DI (match_dup 1))))]
6946 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6948 [(set_attr "op_type" "RRE")
6949 (set_attr "z10prop" "z10_c")])
6951 (define_insn "*negdi2_sign"
6952 [(set (match_operand:DI 0 "register_operand" "=d")
6953 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6954 (clobber (reg:CC CC_REGNUM))]
6957 [(set_attr "op_type" "RRE")
6958 (set_attr "z10prop" "z10_c")])
6961 (define_insn "*neg<mode>2_cc"
6962 [(set (reg CC_REGNUM)
6963 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6965 (set (match_operand:GPR 0 "register_operand" "=d")
6966 (neg:GPR (match_dup 1)))]
6967 "s390_match_ccmode (insn, CCAmode)"
6969 [(set_attr "op_type" "RR<E>")
6970 (set_attr "z10prop" "z10_super_c_E1")])
6973 (define_insn "*neg<mode>2_cconly"
6974 [(set (reg CC_REGNUM)
6975 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6977 (clobber (match_scratch:GPR 0 "=d"))]
6978 "s390_match_ccmode (insn, CCAmode)"
6980 [(set_attr "op_type" "RR<E>")
6981 (set_attr "z10prop" "z10_super_c_E1")])
6984 (define_insn "*neg<mode>2"
6985 [(set (match_operand:GPR 0 "register_operand" "=d")
6986 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6987 (clobber (reg:CC CC_REGNUM))]
6990 [(set_attr "op_type" "RR<E>")
6991 (set_attr "z10prop" "z10_super_c_E1")])
6993 (define_insn_and_split "*negdi2_31"
6994 [(set (match_operand:DI 0 "register_operand" "=d")
6995 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6996 (clobber (reg:CC CC_REGNUM))]
6999 "&& reload_completed"
7001 [(set (match_dup 2) (neg:SI (match_dup 3)))
7002 (clobber (reg:CC CC_REGNUM))])
7004 [(set (reg:CCAP CC_REGNUM)
7005 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7006 (set (match_dup 4) (neg:SI (match_dup 5)))])
7008 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7010 (label_ref (match_dup 6))))
7012 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7013 (clobber (reg:CC CC_REGNUM))])
7015 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7016 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7017 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7018 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7019 operands[6] = gen_label_rtx ();")
7022 ; neg(df|sf)2 instruction pattern(s).
7025 (define_expand "neg<mode>2"
7027 [(set (match_operand:BFP 0 "register_operand" "=f")
7028 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7029 (clobber (reg:CC CC_REGNUM))])]
7033 ; lcxbr, lcdbr, lcebr
7034 (define_insn "*neg<mode>2_cc"
7035 [(set (reg CC_REGNUM)
7036 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7037 (match_operand:BFP 2 "const0_operand" "")))
7038 (set (match_operand:BFP 0 "register_operand" "=f")
7039 (neg:BFP (match_dup 1)))]
7040 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7042 [(set_attr "op_type" "RRE")
7043 (set_attr "type" "fsimp<mode>")])
7045 ; lcxbr, lcdbr, lcebr
7046 (define_insn "*neg<mode>2_cconly"
7047 [(set (reg CC_REGNUM)
7048 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7049 (match_operand:BFP 2 "const0_operand" "")))
7050 (clobber (match_scratch:BFP 0 "=f"))]
7051 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7053 [(set_attr "op_type" "RRE")
7054 (set_attr "type" "fsimp<mode>")])
7057 (define_insn "*neg<mode>2_nocc"
7058 [(set (match_operand:FP 0 "register_operand" "=f")
7059 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7062 [(set_attr "op_type" "RRE")
7063 (set_attr "type" "fsimp<mode>")])
7065 ; lcxbr, lcdbr, lcebr
7066 (define_insn "*neg<mode>2"
7067 [(set (match_operand:BFP 0 "register_operand" "=f")
7068 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7069 (clobber (reg:CC CC_REGNUM))]
7072 [(set_attr "op_type" "RRE")
7073 (set_attr "type" "fsimp<mode>")])
7077 ;;- Absolute value instructions.
7081 ; abs(di|si)2 instruction pattern(s).
7084 (define_insn "*absdi2_sign_cc"
7085 [(set (reg CC_REGNUM)
7086 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7087 (match_operand:SI 1 "register_operand" "d") 0)
7088 (const_int 32)) (const_int 32)))
7090 (set (match_operand:DI 0 "register_operand" "=d")
7091 (abs:DI (sign_extend:DI (match_dup 1))))]
7092 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7094 [(set_attr "op_type" "RRE")
7095 (set_attr "z10prop" "z10_c")])
7097 (define_insn "*absdi2_sign"
7098 [(set (match_operand:DI 0 "register_operand" "=d")
7099 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7100 (clobber (reg:CC CC_REGNUM))]
7103 [(set_attr "op_type" "RRE")
7104 (set_attr "z10prop" "z10_c")])
7107 (define_insn "*abs<mode>2_cc"
7108 [(set (reg CC_REGNUM)
7109 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7111 (set (match_operand:GPR 0 "register_operand" "=d")
7112 (abs:GPR (match_dup 1)))]
7113 "s390_match_ccmode (insn, CCAmode)"
7115 [(set_attr "op_type" "RR<E>")
7116 (set_attr "z10prop" "z10_c")])
7119 (define_insn "*abs<mode>2_cconly"
7120 [(set (reg CC_REGNUM)
7121 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7123 (clobber (match_scratch:GPR 0 "=d"))]
7124 "s390_match_ccmode (insn, CCAmode)"
7126 [(set_attr "op_type" "RR<E>")
7127 (set_attr "z10prop" "z10_c")])
7130 (define_insn "abs<mode>2"
7131 [(set (match_operand:GPR 0 "register_operand" "=d")
7132 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7133 (clobber (reg:CC CC_REGNUM))]
7136 [(set_attr "op_type" "RR<E>")
7137 (set_attr "z10prop" "z10_c")])
7140 ; abs(df|sf)2 instruction pattern(s).
7143 (define_expand "abs<mode>2"
7145 [(set (match_operand:BFP 0 "register_operand" "=f")
7146 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7147 (clobber (reg:CC CC_REGNUM))])]
7151 ; lpxbr, lpdbr, lpebr
7152 (define_insn "*abs<mode>2_cc"
7153 [(set (reg CC_REGNUM)
7154 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7155 (match_operand:BFP 2 "const0_operand" "")))
7156 (set (match_operand:BFP 0 "register_operand" "=f")
7157 (abs:BFP (match_dup 1)))]
7158 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7160 [(set_attr "op_type" "RRE")
7161 (set_attr "type" "fsimp<mode>")])
7163 ; lpxbr, lpdbr, lpebr
7164 (define_insn "*abs<mode>2_cconly"
7165 [(set (reg CC_REGNUM)
7166 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7167 (match_operand:BFP 2 "const0_operand" "")))
7168 (clobber (match_scratch:BFP 0 "=f"))]
7169 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7171 [(set_attr "op_type" "RRE")
7172 (set_attr "type" "fsimp<mode>")])
7175 (define_insn "*abs<mode>2_nocc"
7176 [(set (match_operand:FP 0 "register_operand" "=f")
7177 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7180 [(set_attr "op_type" "RRE")
7181 (set_attr "type" "fsimp<mode>")])
7183 ; lpxbr, lpdbr, lpebr
7184 (define_insn "*abs<mode>2"
7185 [(set (match_operand:BFP 0 "register_operand" "=f")
7186 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7187 (clobber (reg:CC CC_REGNUM))]
7190 [(set_attr "op_type" "RRE")
7191 (set_attr "type" "fsimp<mode>")])
7195 ;;- Negated absolute value instructions
7202 (define_insn "*negabsdi2_sign_cc"
7203 [(set (reg CC_REGNUM)
7204 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7205 (match_operand:SI 1 "register_operand" "d") 0)
7206 (const_int 32)) (const_int 32))))
7208 (set (match_operand:DI 0 "register_operand" "=d")
7209 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7210 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7212 [(set_attr "op_type" "RRE")
7213 (set_attr "z10prop" "z10_c")])
7215 (define_insn "*negabsdi2_sign"
7216 [(set (match_operand:DI 0 "register_operand" "=d")
7217 (neg:DI (abs:DI (sign_extend:DI
7218 (match_operand:SI 1 "register_operand" "d")))))
7219 (clobber (reg:CC CC_REGNUM))]
7222 [(set_attr "op_type" "RRE")
7223 (set_attr "z10prop" "z10_c")])
7226 (define_insn "*negabs<mode>2_cc"
7227 [(set (reg CC_REGNUM)
7228 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7230 (set (match_operand:GPR 0 "register_operand" "=d")
7231 (neg:GPR (abs:GPR (match_dup 1))))]
7232 "s390_match_ccmode (insn, CCAmode)"
7234 [(set_attr "op_type" "RR<E>")
7235 (set_attr "z10prop" "z10_c")])
7238 (define_insn "*negabs<mode>2_cconly"
7239 [(set (reg CC_REGNUM)
7240 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7242 (clobber (match_scratch:GPR 0 "=d"))]
7243 "s390_match_ccmode (insn, CCAmode)"
7245 [(set_attr "op_type" "RR<E>")
7246 (set_attr "z10prop" "z10_c")])
7249 (define_insn "*negabs<mode>2"
7250 [(set (match_operand:GPR 0 "register_operand" "=d")
7251 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7252 (clobber (reg:CC CC_REGNUM))]
7255 [(set_attr "op_type" "RR<E>")
7256 (set_attr "z10prop" "z10_c")])
7262 ; lnxbr, lndbr, lnebr
7263 (define_insn "*negabs<mode>2_cc"
7264 [(set (reg CC_REGNUM)
7265 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7266 (match_operand:BFP 2 "const0_operand" "")))
7267 (set (match_operand:BFP 0 "register_operand" "=f")
7268 (neg:BFP (abs:BFP (match_dup 1))))]
7269 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7271 [(set_attr "op_type" "RRE")
7272 (set_attr "type" "fsimp<mode>")])
7274 ; lnxbr, lndbr, lnebr
7275 (define_insn "*negabs<mode>2_cconly"
7276 [(set (reg CC_REGNUM)
7277 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7278 (match_operand:BFP 2 "const0_operand" "")))
7279 (clobber (match_scratch:BFP 0 "=f"))]
7280 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7282 [(set_attr "op_type" "RRE")
7283 (set_attr "type" "fsimp<mode>")])
7286 (define_insn "*negabs<mode>2_nocc"
7287 [(set (match_operand:FP 0 "register_operand" "=f")
7288 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7291 [(set_attr "op_type" "RRE")
7292 (set_attr "type" "fsimp<mode>")])
7294 ; lnxbr, lndbr, lnebr
7295 (define_insn "*negabs<mode>2"
7296 [(set (match_operand:BFP 0 "register_operand" "=f")
7297 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7298 (clobber (reg:CC CC_REGNUM))]
7301 [(set_attr "op_type" "RRE")
7302 (set_attr "type" "fsimp<mode>")])
7305 ;;- Square root instructions.
7309 ; sqrt(df|sf)2 instruction pattern(s).
7312 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7313 (define_insn "sqrt<mode>2"
7314 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7315 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7320 [(set_attr "op_type" "RRE,RXE")
7321 (set_attr "type" "fsqrt<mode>")])
7325 ;;- One complement instructions.
7329 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7332 (define_expand "one_cmpl<mode>2"
7334 [(set (match_operand:INT 0 "register_operand" "")
7335 (xor:INT (match_operand:INT 1 "register_operand" "")
7337 (clobber (reg:CC CC_REGNUM))])]
7343 ;; Find leftmost bit instructions.
7346 (define_expand "clzdi2"
7347 [(set (match_operand:DI 0 "register_operand" "=d")
7348 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7349 "TARGET_EXTIMM && TARGET_ZARCH"
7351 rtx insn, clz_equal;
7352 rtx wide_reg = gen_reg_rtx (TImode);
7353 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7355 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7357 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7359 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7360 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7365 (define_insn "clztidi2"
7366 [(set (match_operand:TI 0 "register_operand" "=d")
7370 (xor:DI (match_operand:DI 1 "register_operand" "d")
7371 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7372 (subreg:SI (clz:DI (match_dup 1)) 4))))
7375 (zero_extend:TI (clz:DI (match_dup 1)))))
7376 (clobber (reg:CC CC_REGNUM))]
7377 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7378 == (unsigned HOST_WIDE_INT) 1 << 63
7379 && TARGET_EXTIMM && TARGET_ZARCH"
7381 [(set_attr "op_type" "RRE")])
7385 ;;- Rotate instructions.
7389 ; rotl(di|si)3 instruction pattern(s).
7393 (define_insn "rotl<mode>3"
7394 [(set (match_operand:GPR 0 "register_operand" "=d")
7395 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7396 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7399 [(set_attr "op_type" "RSE")
7400 (set_attr "atype" "reg")
7401 (set_attr "z10prop" "z10_super_E1")])
7404 (define_insn "*rotl<mode>3_and"
7405 [(set (match_operand:GPR 0 "register_operand" "=d")
7406 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7407 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7408 (match_operand:SI 3 "const_int_operand" "n"))))]
7409 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7411 [(set_attr "op_type" "RSE")
7412 (set_attr "atype" "reg")
7413 (set_attr "z10prop" "z10_super_E1")])
7417 ;;- Shift instructions.
7421 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7422 ; Left shifts and logical right shifts
7424 (define_expand "<shift><mode>3"
7425 [(set (match_operand:DSI 0 "register_operand" "")
7426 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7427 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7432 (define_insn "*<shift>di3_31"
7433 [(set (match_operand:DI 0 "register_operand" "=d")
7434 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7435 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7438 [(set_attr "op_type" "RS")
7439 (set_attr "atype" "reg")
7440 (set_attr "z196prop" "z196_cracked")])
7442 ; sll, srl, sllg, srlg, sllk, srlk
7443 (define_insn "*<shift><mode>3"
7444 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7445 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7446 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7449 s<lr>l<g>\t%0,<1>%Y2
7450 s<lr>l<gk>\t%0,%1,%Y2"
7451 [(set_attr "op_type" "RS<E>,RSY")
7452 (set_attr "atype" "reg,reg")
7453 (set_attr "cpu_facility" "*,z196")
7454 (set_attr "z10prop" "z10_super_E1,*")])
7457 (define_insn "*<shift>di3_31_and"
7458 [(set (match_operand:DI 0 "register_operand" "=d")
7459 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7460 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7461 (match_operand:SI 3 "const_int_operand" "n"))))]
7462 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7464 [(set_attr "op_type" "RS")
7465 (set_attr "atype" "reg")])
7467 ; sll, srl, sllg, srlg, sllk, srlk
7468 (define_insn "*<shift><mode>3_and"
7469 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7470 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7471 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7472 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7473 "(INTVAL (operands[3]) & 63) == 63"
7475 s<lr>l<g>\t%0,<1>%Y2
7476 s<lr>l<gk>\t%0,%1,%Y2"
7477 [(set_attr "op_type" "RS<E>,RSY")
7478 (set_attr "atype" "reg,reg")
7479 (set_attr "cpu_facility" "*,z196")
7480 (set_attr "z10prop" "z10_super_E1,*")])
7483 ; ashr(di|si)3 instruction pattern(s).
7484 ; Arithmetic right shifts
7486 (define_expand "ashr<mode>3"
7488 [(set (match_operand:DSI 0 "register_operand" "")
7489 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7490 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7491 (clobber (reg:CC CC_REGNUM))])]
7495 (define_insn "*ashrdi3_cc_31"
7496 [(set (reg CC_REGNUM)
7497 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7498 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7500 (set (match_operand:DI 0 "register_operand" "=d")
7501 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7502 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7504 [(set_attr "op_type" "RS")
7505 (set_attr "atype" "reg")])
7507 (define_insn "*ashrdi3_cconly_31"
7508 [(set (reg CC_REGNUM)
7509 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7510 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7512 (clobber (match_scratch:DI 0 "=d"))]
7513 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7515 [(set_attr "op_type" "RS")
7516 (set_attr "atype" "reg")])
7518 (define_insn "*ashrdi3_31"
7519 [(set (match_operand:DI 0 "register_operand" "=d")
7520 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7521 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7522 (clobber (reg:CC CC_REGNUM))]
7525 [(set_attr "op_type" "RS")
7526 (set_attr "atype" "reg")])
7529 (define_insn "*ashr<mode>3_cc"
7530 [(set (reg CC_REGNUM)
7531 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7532 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7534 (set (match_operand:GPR 0 "register_operand" "=d,d")
7535 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7536 "s390_match_ccmode(insn, CCSmode)"
7540 [(set_attr "op_type" "RS<E>,RSY")
7541 (set_attr "atype" "reg,reg")
7542 (set_attr "cpu_facility" "*,z196")
7543 (set_attr "z10prop" "z10_super_E1,*")])
7546 (define_insn "*ashr<mode>3_cconly"
7547 [(set (reg CC_REGNUM)
7548 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7549 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7551 (clobber (match_scratch:GPR 0 "=d,d"))]
7552 "s390_match_ccmode(insn, CCSmode)"
7556 [(set_attr "op_type" "RS<E>,RSY")
7557 (set_attr "atype" "reg,reg")
7558 (set_attr "cpu_facility" "*,z196")
7559 (set_attr "z10prop" "z10_super_E1,*")])
7562 (define_insn "*ashr<mode>3"
7563 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7564 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7565 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7566 (clobber (reg:CC CC_REGNUM))]
7571 [(set_attr "op_type" "RS<E>,RSY")
7572 (set_attr "atype" "reg,reg")
7573 (set_attr "cpu_facility" "*,z196")
7574 (set_attr "z10prop" "z10_super_E1,*")])
7577 ; shift pattern with implicit ANDs
7579 (define_insn "*ashrdi3_cc_31_and"
7580 [(set (reg CC_REGNUM)
7581 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7582 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7583 (match_operand:SI 3 "const_int_operand" "n")))
7585 (set (match_operand:DI 0 "register_operand" "=d")
7586 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7587 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7588 && (INTVAL (operands[3]) & 63) == 63"
7590 [(set_attr "op_type" "RS")
7591 (set_attr "atype" "reg")])
7593 (define_insn "*ashrdi3_cconly_31_and"
7594 [(set (reg CC_REGNUM)
7595 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7596 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7597 (match_operand:SI 3 "const_int_operand" "n")))
7599 (clobber (match_scratch:DI 0 "=d"))]
7600 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7601 && (INTVAL (operands[3]) & 63) == 63"
7603 [(set_attr "op_type" "RS")
7604 (set_attr "atype" "reg")])
7606 (define_insn "*ashrdi3_31_and"
7607 [(set (match_operand:DI 0 "register_operand" "=d")
7608 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7609 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7610 (match_operand:SI 3 "const_int_operand" "n"))))
7611 (clobber (reg:CC CC_REGNUM))]
7612 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7614 [(set_attr "op_type" "RS")
7615 (set_attr "atype" "reg")])
7618 (define_insn "*ashr<mode>3_cc_and"
7619 [(set (reg CC_REGNUM)
7620 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7621 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7622 (match_operand:SI 3 "const_int_operand" "n,n")))
7624 (set (match_operand:GPR 0 "register_operand" "=d,d")
7625 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7626 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7630 [(set_attr "op_type" "RS<E>,RSY")
7631 (set_attr "atype" "reg,reg")
7632 (set_attr "cpu_facility" "*,z196")
7633 (set_attr "z10prop" "z10_super_E1,*")])
7636 (define_insn "*ashr<mode>3_cconly_and"
7637 [(set (reg CC_REGNUM)
7638 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7639 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7640 (match_operand:SI 3 "const_int_operand" "n,n")))
7642 (clobber (match_scratch:GPR 0 "=d,d"))]
7643 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7647 [(set_attr "op_type" "RS<E>,RSY")
7648 (set_attr "atype" "reg,reg")
7649 (set_attr "cpu_facility" "*,z196")
7650 (set_attr "z10prop" "z10_super_E1,*")])
7653 (define_insn "*ashr<mode>3_and"
7654 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7655 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7656 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7657 (match_operand:SI 3 "const_int_operand" "n,n"))))
7658 (clobber (reg:CC CC_REGNUM))]
7659 "(INTVAL (operands[3]) & 63) == 63"
7663 [(set_attr "op_type" "RS<E>,RSY")
7664 (set_attr "atype" "reg,reg")
7665 (set_attr "cpu_facility" "*,z196")
7666 (set_attr "z10prop" "z10_super_E1,*")])
7670 ;; Branch instruction patterns.
7673 (define_expand "cbranch<mode>4"
7675 (if_then_else (match_operator 0 "comparison_operator"
7676 [(match_operand:GPR 1 "register_operand" "")
7677 (match_operand:GPR 2 "general_operand" "")])
7678 (label_ref (match_operand 3 "" ""))
7681 "s390_emit_jump (operands[3],
7682 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7685 (define_expand "cbranch<mode>4"
7687 (if_then_else (match_operator 0 "comparison_operator"
7688 [(match_operand:FP 1 "register_operand" "")
7689 (match_operand:FP 2 "general_operand" "")])
7690 (label_ref (match_operand 3 "" ""))
7693 "s390_emit_jump (operands[3],
7694 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7697 (define_expand "cbranchcc4"
7699 (if_then_else (match_operator 0 "s390_eqne_operator"
7700 [(match_operand 1 "cc_reg_operand" "")
7701 (match_operand 2 "const0_operand" "")])
7702 (label_ref (match_operand 3 "" ""))
7705 "s390_emit_jump (operands[3],
7706 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7712 ;;- Conditional jump instructions.
7715 (define_insn "*cjump_64"
7718 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7719 (label_ref (match_operand 0 "" ""))
7723 if (get_attr_length (insn) == 4)
7726 return "jg%C1\t%l0";
7728 [(set_attr "op_type" "RI")
7729 (set_attr "type" "branch")
7730 (set (attr "length")
7731 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7732 (const_int 4) (const_int 6)))])
7734 (define_insn "*cjump_31"
7737 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7738 (label_ref (match_operand 0 "" ""))
7742 gcc_assert (get_attr_length (insn) == 4);
7745 [(set_attr "op_type" "RI")
7746 (set_attr "type" "branch")
7747 (set (attr "length")
7748 (if_then_else (not (match_test "flag_pic"))
7749 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7750 (const_int 4) (const_int 6))
7751 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7752 (const_int 4) (const_int 8))))])
7754 (define_insn "*cjump_long"
7757 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7758 (match_operand 0 "address_operand" "ZQZR")
7762 if (get_attr_op_type (insn) == OP_TYPE_RR)
7767 [(set (attr "op_type")
7768 (if_then_else (match_operand 0 "register_operand" "")
7769 (const_string "RR") (const_string "RX")))
7770 (set_attr "type" "branch")
7771 (set_attr "atype" "agen")])
7775 ;;- Negated conditional jump instructions.
7778 (define_insn "*icjump_64"
7781 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7783 (label_ref (match_operand 0 "" ""))))]
7786 if (get_attr_length (insn) == 4)
7789 return "jg%D1\t%l0";
7791 [(set_attr "op_type" "RI")
7792 (set_attr "type" "branch")
7793 (set (attr "length")
7794 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7795 (const_int 4) (const_int 6)))])
7797 (define_insn "*icjump_31"
7800 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7802 (label_ref (match_operand 0 "" ""))))]
7805 gcc_assert (get_attr_length (insn) == 4);
7808 [(set_attr "op_type" "RI")
7809 (set_attr "type" "branch")
7810 (set (attr "length")
7811 (if_then_else (not (match_test "flag_pic"))
7812 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7813 (const_int 4) (const_int 6))
7814 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7815 (const_int 4) (const_int 8))))])
7817 (define_insn "*icjump_long"
7820 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7822 (match_operand 0 "address_operand" "ZQZR")))]
7825 if (get_attr_op_type (insn) == OP_TYPE_RR)
7830 [(set (attr "op_type")
7831 (if_then_else (match_operand 0 "register_operand" "")
7832 (const_string "RR") (const_string "RX")))
7833 (set_attr "type" "branch")
7834 (set_attr "atype" "agen")])
7837 ;;- Trap instructions.
7841 [(trap_if (const_int 1) (const_int 0))]
7844 [(set_attr "op_type" "RI")
7845 (set_attr "type" "branch")])
7847 (define_expand "ctrap<mode>4"
7848 [(trap_if (match_operator 0 "comparison_operator"
7849 [(match_operand:GPR 1 "register_operand" "")
7850 (match_operand:GPR 2 "general_operand" "")])
7851 (match_operand 3 "const0_operand" ""))]
7854 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7855 operands[1], operands[2]);
7856 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7860 (define_expand "ctrap<mode>4"
7861 [(trap_if (match_operator 0 "comparison_operator"
7862 [(match_operand:FP 1 "register_operand" "")
7863 (match_operand:FP 2 "general_operand" "")])
7864 (match_operand 3 "const0_operand" ""))]
7867 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7868 operands[1], operands[2]);
7869 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7873 (define_insn "condtrap"
7874 [(trap_if (match_operator 0 "s390_comparison"
7875 [(match_operand 1 "cc_reg_operand" "c")
7880 [(set_attr "op_type" "RI")
7881 (set_attr "type" "branch")])
7883 ; crt, cgrt, cit, cgit
7884 (define_insn "*cmp_and_trap_signed_int<mode>"
7885 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7886 [(match_operand:GPR 1 "register_operand" "d,d")
7887 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7893 [(set_attr "op_type" "RRF,RIE")
7894 (set_attr "type" "branch")
7895 (set_attr "z10prop" "z10_super_c,z10_super")])
7897 ; clrt, clgrt, clfit, clgit
7898 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7899 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7900 [(match_operand:GPR 1 "register_operand" "d,d")
7901 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7906 cl<gf>it%C0\t%1,%x2"
7907 [(set_attr "op_type" "RRF,RIE")
7908 (set_attr "type" "branch")
7909 (set_attr "z10prop" "z10_super_c,z10_super")])
7912 ;;- Loop instructions.
7914 ;; This is all complicated by the fact that since this is a jump insn
7915 ;; we must handle our own output reloads.
7919 ; This splitter will be matched by combine and has to add the 2 moves
7920 ; necessary to load the compare and the increment values into a
7921 ; register pair as needed by brxle.
7923 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7926 (match_operator 6 "s390_brx_operator"
7927 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
7928 (match_operand:GPR 2 "general_operand" ""))
7929 (match_operand:GPR 3 "register_operand" "")])
7930 (label_ref (match_operand 0 "" ""))
7932 (set (match_operand:GPR 4 "nonimmediate_operand" "")
7933 (plus:GPR (match_dup 1) (match_dup 2)))
7934 (clobber (match_scratch:GPR 5 ""))]
7937 "!reload_completed && !reload_in_progress"
7938 [(set (match_dup 7) (match_dup 2)) ; the increment
7939 (set (match_dup 8) (match_dup 3)) ; the comparison value
7940 (parallel [(set (pc)
7943 [(plus:GPR (match_dup 1) (match_dup 7))
7945 (label_ref (match_dup 0))
7948 (plus:GPR (match_dup 1) (match_dup 7)))
7949 (clobber (match_dup 5))
7950 (clobber (reg:CC CC_REGNUM))])]
7952 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
7953 operands[7] = gen_lowpart (<GPR:MODE>mode,
7954 gen_highpart (word_mode, dreg));
7955 operands[8] = gen_lowpart (<GPR:MODE>mode,
7956 gen_lowpart (word_mode, dreg));
7961 (define_insn_and_split "*brxg_64bit"
7964 (match_operator 5 "s390_brx_operator"
7965 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
7966 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
7967 (subreg:DI (match_dup 2) 8)])
7968 (label_ref (match_operand 0 "" ""))
7970 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
7971 (plus:DI (match_dup 1)
7972 (subreg:DI (match_dup 2) 0)))
7973 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
7974 (clobber (reg:CC CC_REGNUM))]
7977 if (which_alternative != 0)
7979 else if (get_attr_length (insn) == 6)
7980 return "brx%E5g\t%1,%2,%l0";
7982 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
7984 "&& reload_completed
7985 && (!REG_P (operands[3])
7986 || !rtx_equal_p (operands[1], operands[3]))"
7987 [(set (match_dup 4) (match_dup 1))
7988 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
7989 (clobber (reg:CC CC_REGNUM))])
7990 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
7991 (set (match_dup 3) (match_dup 4))
7992 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7993 (label_ref (match_dup 0))
7996 [(set_attr "op_type" "RIE")
7997 (set_attr "type" "branch")
7998 (set (attr "length")
7999 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8000 (const_int 6) (const_int 16)))])
8004 (define_insn_and_split "*brx_64bit"
8007 (match_operator 5 "s390_brx_operator"
8008 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8009 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8010 (subreg:SI (match_dup 2) 12)])
8011 (label_ref (match_operand 0 "" ""))
8013 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8014 (plus:SI (match_dup 1)
8015 (subreg:SI (match_dup 2) 4)))
8016 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8017 (clobber (reg:CC CC_REGNUM))]
8020 if (which_alternative != 0)
8022 else if (get_attr_length (insn) == 6)
8023 return "brx%C5\t%1,%2,%l0";
8025 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8027 "&& reload_completed
8028 && (!REG_P (operands[3])
8029 || !rtx_equal_p (operands[1], operands[3]))"
8030 [(set (match_dup 4) (match_dup 1))
8031 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8032 (clobber (reg:CC CC_REGNUM))])
8033 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8034 (set (match_dup 3) (match_dup 4))
8035 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8036 (label_ref (match_dup 0))
8039 [(set_attr "op_type" "RSI")
8040 (set_attr "type" "branch")
8041 (set (attr "length")
8042 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8043 (const_int 6) (const_int 14)))])
8047 (define_insn_and_split "*brx_31bit"
8050 (match_operator 5 "s390_brx_operator"
8051 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8052 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8053 (subreg:SI (match_dup 2) 4)])
8054 (label_ref (match_operand 0 "" ""))
8056 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8057 (plus:SI (match_dup 1)
8058 (subreg:SI (match_dup 2) 0)))
8059 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8060 (clobber (reg:CC CC_REGNUM))]
8061 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8063 if (which_alternative != 0)
8065 else if (get_attr_length (insn) == 6)
8066 return "brx%C5\t%1,%2,%l0";
8068 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8070 "&& reload_completed
8071 && (!REG_P (operands[3])
8072 || !rtx_equal_p (operands[1], operands[3]))"
8073 [(set (match_dup 4) (match_dup 1))
8074 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8075 (clobber (reg:CC CC_REGNUM))])
8076 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8077 (set (match_dup 3) (match_dup 4))
8078 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8079 (label_ref (match_dup 0))
8082 [(set_attr "op_type" "RSI")
8083 (set_attr "type" "branch")
8084 (set (attr "length")
8085 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8086 (const_int 6) (const_int 14)))])
8091 (define_expand "doloop_end"
8092 [(use (match_operand 0 "" "")) ; loop pseudo
8093 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8094 (use (match_operand 2 "" "")) ; max iterations
8095 (use (match_operand 3 "" "")) ; loop level
8096 (use (match_operand 4 "" ""))] ; label
8099 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8100 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8101 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8102 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8103 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8104 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8111 (define_insn_and_split "doloop_si64"
8114 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8116 (label_ref (match_operand 0 "" ""))
8118 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8119 (plus:SI (match_dup 1) (const_int -1)))
8120 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8121 (clobber (reg:CC CC_REGNUM))]
8124 if (which_alternative != 0)
8126 else if (get_attr_length (insn) == 4)
8127 return "brct\t%1,%l0";
8129 return "ahi\t%1,-1\;jgne\t%l0";
8131 "&& reload_completed
8132 && (! REG_P (operands[2])
8133 || ! rtx_equal_p (operands[1], operands[2]))"
8134 [(set (match_dup 3) (match_dup 1))
8135 (parallel [(set (reg:CCAN CC_REGNUM)
8136 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8138 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8139 (set (match_dup 2) (match_dup 3))
8140 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8141 (label_ref (match_dup 0))
8144 [(set_attr "op_type" "RI")
8145 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8146 ; hurt us in the (rare) case of ahi.
8147 (set_attr "z10prop" "z10_super_E1")
8148 (set_attr "type" "branch")
8149 (set (attr "length")
8150 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8151 (const_int 4) (const_int 10)))])
8153 (define_insn_and_split "doloop_si31"
8156 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8158 (label_ref (match_operand 0 "" ""))
8160 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8161 (plus:SI (match_dup 1) (const_int -1)))
8162 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8163 (clobber (reg:CC CC_REGNUM))]
8166 if (which_alternative != 0)
8168 else if (get_attr_length (insn) == 4)
8169 return "brct\t%1,%l0";
8173 "&& reload_completed
8174 && (! REG_P (operands[2])
8175 || ! rtx_equal_p (operands[1], operands[2]))"
8176 [(set (match_dup 3) (match_dup 1))
8177 (parallel [(set (reg:CCAN CC_REGNUM)
8178 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8180 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8181 (set (match_dup 2) (match_dup 3))
8182 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8183 (label_ref (match_dup 0))
8186 [(set_attr "op_type" "RI")
8187 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8188 ; hurt us in the (rare) case of ahi.
8189 (set_attr "z10prop" "z10_super_E1")
8190 (set_attr "type" "branch")
8191 (set (attr "length")
8192 (if_then_else (not (match_test "flag_pic"))
8193 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8194 (const_int 4) (const_int 6))
8195 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8196 (const_int 4) (const_int 8))))])
8198 (define_insn "*doloop_si_long"
8201 (ne (match_operand:SI 1 "register_operand" "d")
8203 (match_operand 0 "address_operand" "ZQZR")
8205 (set (match_operand:SI 2 "register_operand" "=1")
8206 (plus:SI (match_dup 1) (const_int -1)))
8207 (clobber (match_scratch:SI 3 "=X"))
8208 (clobber (reg:CC CC_REGNUM))]
8211 if (get_attr_op_type (insn) == OP_TYPE_RR)
8212 return "bctr\t%1,%0";
8214 return "bct\t%1,%a0";
8216 [(set (attr "op_type")
8217 (if_then_else (match_operand 0 "register_operand" "")
8218 (const_string "RR") (const_string "RX")))
8219 (set_attr "type" "branch")
8220 (set_attr "atype" "agen")
8221 (set_attr "z10prop" "z10_c")
8222 (set_attr "z196prop" "z196_cracked")])
8224 (define_insn_and_split "doloop_di"
8227 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8229 (label_ref (match_operand 0 "" ""))
8231 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8232 (plus:DI (match_dup 1) (const_int -1)))
8233 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8234 (clobber (reg:CC CC_REGNUM))]
8237 if (which_alternative != 0)
8239 else if (get_attr_length (insn) == 4)
8240 return "brctg\t%1,%l0";
8242 return "aghi\t%1,-1\;jgne\t%l0";
8244 "&& reload_completed
8245 && (! REG_P (operands[2])
8246 || ! rtx_equal_p (operands[1], operands[2]))"
8247 [(set (match_dup 3) (match_dup 1))
8248 (parallel [(set (reg:CCAN CC_REGNUM)
8249 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8251 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8252 (set (match_dup 2) (match_dup 3))
8253 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8254 (label_ref (match_dup 0))
8257 [(set_attr "op_type" "RI")
8258 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8259 ; hurt us in the (rare) case of ahi.
8260 (set_attr "z10prop" "z10_super_E1")
8261 (set_attr "type" "branch")
8262 (set (attr "length")
8263 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8264 (const_int 4) (const_int 10)))])
8267 ;;- Unconditional jump instructions.
8271 ; jump instruction pattern(s).
8274 (define_expand "jump"
8275 [(match_operand 0 "" "")]
8277 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8279 (define_insn "*jump64"
8280 [(set (pc) (label_ref (match_operand 0 "" "")))]
8283 if (get_attr_length (insn) == 4)
8288 [(set_attr "op_type" "RI")
8289 (set_attr "type" "branch")
8290 (set (attr "length")
8291 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8292 (const_int 4) (const_int 6)))])
8294 (define_insn "*jump31"
8295 [(set (pc) (label_ref (match_operand 0 "" "")))]
8298 gcc_assert (get_attr_length (insn) == 4);
8301 [(set_attr "op_type" "RI")
8302 (set_attr "type" "branch")
8303 (set (attr "length")
8304 (if_then_else (not (match_test "flag_pic"))
8305 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8306 (const_int 4) (const_int 6))
8307 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8308 (const_int 4) (const_int 8))))])
8311 ; indirect-jump instruction pattern(s).
8314 (define_insn "indirect_jump"
8315 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8318 if (get_attr_op_type (insn) == OP_TYPE_RR)
8323 [(set (attr "op_type")
8324 (if_then_else (match_operand 0 "register_operand" "")
8325 (const_string "RR") (const_string "RX")))
8326 (set_attr "type" "branch")
8327 (set_attr "atype" "agen")])
8330 ; casesi instruction pattern(s).
8333 (define_insn "casesi_jump"
8334 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8335 (use (label_ref (match_operand 1 "" "")))]
8338 if (get_attr_op_type (insn) == OP_TYPE_RR)
8343 [(set (attr "op_type")
8344 (if_then_else (match_operand 0 "register_operand" "")
8345 (const_string "RR") (const_string "RX")))
8346 (set_attr "type" "branch")
8347 (set_attr "atype" "agen")])
8349 (define_expand "casesi"
8350 [(match_operand:SI 0 "general_operand" "")
8351 (match_operand:SI 1 "general_operand" "")
8352 (match_operand:SI 2 "general_operand" "")
8353 (label_ref (match_operand 3 "" ""))
8354 (label_ref (match_operand 4 "" ""))]
8357 rtx index = gen_reg_rtx (SImode);
8358 rtx base = gen_reg_rtx (Pmode);
8359 rtx target = gen_reg_rtx (Pmode);
8361 emit_move_insn (index, operands[0]);
8362 emit_insn (gen_subsi3 (index, index, operands[1]));
8363 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8366 if (Pmode != SImode)
8367 index = convert_to_mode (Pmode, index, 1);
8368 if (GET_CODE (index) != REG)
8369 index = copy_to_mode_reg (Pmode, index);
8372 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8374 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8376 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8378 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8379 emit_move_insn (target, index);
8382 target = gen_rtx_PLUS (Pmode, base, target);
8383 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8390 ;;- Jump to subroutine.
8395 ; untyped call instruction pattern(s).
8398 ;; Call subroutine returning any type.
8399 (define_expand "untyped_call"
8400 [(parallel [(call (match_operand 0 "" "")
8402 (match_operand 1 "" "")
8403 (match_operand 2 "" "")])]
8408 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8410 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8412 rtx set = XVECEXP (operands[2], 0, i);
8413 emit_move_insn (SET_DEST (set), SET_SRC (set));
8416 /* The optimizer does not know that the call sets the function value
8417 registers we stored in the result block. We avoid problems by
8418 claiming that all hard registers are used and clobbered at this
8420 emit_insn (gen_blockage ());
8425 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8426 ;; all of memory. This blocks insns from being moved across this point.
8428 (define_insn "blockage"
8429 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8432 [(set_attr "type" "none")
8433 (set_attr "length" "0")])
8439 (define_expand "sibcall"
8440 [(call (match_operand 0 "" "")
8441 (match_operand 1 "" ""))]
8444 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8448 (define_insn "*sibcall_br"
8449 [(call (mem:QI (reg SIBCALL_REGNUM))
8450 (match_operand 0 "const_int_operand" "n"))]
8451 "SIBLING_CALL_P (insn)
8452 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8454 [(set_attr "op_type" "RR")
8455 (set_attr "type" "branch")
8456 (set_attr "atype" "agen")])
8458 (define_insn "*sibcall_brc"
8459 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8460 (match_operand 1 "const_int_operand" "n"))]
8461 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8463 [(set_attr "op_type" "RI")
8464 (set_attr "type" "branch")])
8466 (define_insn "*sibcall_brcl"
8467 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8468 (match_operand 1 "const_int_operand" "n"))]
8469 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8471 [(set_attr "op_type" "RIL")
8472 (set_attr "type" "branch")])
8475 ; sibcall_value patterns
8478 (define_expand "sibcall_value"
8479 [(set (match_operand 0 "" "")
8480 (call (match_operand 1 "" "")
8481 (match_operand 2 "" "")))]
8484 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8488 (define_insn "*sibcall_value_br"
8489 [(set (match_operand 0 "" "")
8490 (call (mem:QI (reg SIBCALL_REGNUM))
8491 (match_operand 1 "const_int_operand" "n")))]
8492 "SIBLING_CALL_P (insn)
8493 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8495 [(set_attr "op_type" "RR")
8496 (set_attr "type" "branch")
8497 (set_attr "atype" "agen")])
8499 (define_insn "*sibcall_value_brc"
8500 [(set (match_operand 0 "" "")
8501 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8502 (match_operand 2 "const_int_operand" "n")))]
8503 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8505 [(set_attr "op_type" "RI")
8506 (set_attr "type" "branch")])
8508 (define_insn "*sibcall_value_brcl"
8509 [(set (match_operand 0 "" "")
8510 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8511 (match_operand 2 "const_int_operand" "n")))]
8512 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8514 [(set_attr "op_type" "RIL")
8515 (set_attr "type" "branch")])
8519 ; call instruction pattern(s).
8522 (define_expand "call"
8523 [(call (match_operand 0 "" "")
8524 (match_operand 1 "" ""))
8525 (use (match_operand 2 "" ""))]
8528 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8529 gen_rtx_REG (Pmode, RETURN_REGNUM));
8533 (define_insn "*bras"
8534 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8535 (match_operand 1 "const_int_operand" "n"))
8536 (clobber (match_operand 2 "register_operand" "=r"))]
8537 "!SIBLING_CALL_P (insn)
8538 && TARGET_SMALL_EXEC
8539 && GET_MODE (operands[2]) == Pmode"
8541 [(set_attr "op_type" "RI")
8542 (set_attr "type" "jsr")
8543 (set_attr "z196prop" "z196_cracked")])
8545 (define_insn "*brasl"
8546 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8547 (match_operand 1 "const_int_operand" "n"))
8548 (clobber (match_operand 2 "register_operand" "=r"))]
8549 "!SIBLING_CALL_P (insn)
8551 && GET_MODE (operands[2]) == Pmode"
8553 [(set_attr "op_type" "RIL")
8554 (set_attr "type" "jsr")
8555 (set_attr "z196prop" "z196_cracked")])
8557 (define_insn "*basr"
8558 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8559 (match_operand 1 "const_int_operand" "n"))
8560 (clobber (match_operand 2 "register_operand" "=r"))]
8561 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8563 if (get_attr_op_type (insn) == OP_TYPE_RR)
8564 return "basr\t%2,%0";
8566 return "bas\t%2,%a0";
8568 [(set (attr "op_type")
8569 (if_then_else (match_operand 0 "register_operand" "")
8570 (const_string "RR") (const_string "RX")))
8571 (set_attr "type" "jsr")
8572 (set_attr "atype" "agen")
8573 (set_attr "z196prop" "z196_cracked")])
8576 ; call_value instruction pattern(s).
8579 (define_expand "call_value"
8580 [(set (match_operand 0 "" "")
8581 (call (match_operand 1 "" "")
8582 (match_operand 2 "" "")))
8583 (use (match_operand 3 "" ""))]
8586 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8587 gen_rtx_REG (Pmode, RETURN_REGNUM));
8591 (define_insn "*bras_r"
8592 [(set (match_operand 0 "" "")
8593 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8594 (match_operand:SI 2 "const_int_operand" "n")))
8595 (clobber (match_operand 3 "register_operand" "=r"))]
8596 "!SIBLING_CALL_P (insn)
8597 && TARGET_SMALL_EXEC
8598 && GET_MODE (operands[3]) == Pmode"
8600 [(set_attr "op_type" "RI")
8601 (set_attr "type" "jsr")
8602 (set_attr "z196prop" "z196_cracked")])
8604 (define_insn "*brasl_r"
8605 [(set (match_operand 0 "" "")
8606 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8607 (match_operand 2 "const_int_operand" "n")))
8608 (clobber (match_operand 3 "register_operand" "=r"))]
8609 "!SIBLING_CALL_P (insn)
8611 && GET_MODE (operands[3]) == Pmode"
8613 [(set_attr "op_type" "RIL")
8614 (set_attr "type" "jsr")
8615 (set_attr "z196prop" "z196_cracked")])
8617 (define_insn "*basr_r"
8618 [(set (match_operand 0 "" "")
8619 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8620 (match_operand 2 "const_int_operand" "n")))
8621 (clobber (match_operand 3 "register_operand" "=r"))]
8622 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8624 if (get_attr_op_type (insn) == OP_TYPE_RR)
8625 return "basr\t%3,%1";
8627 return "bas\t%3,%a1";
8629 [(set (attr "op_type")
8630 (if_then_else (match_operand 1 "register_operand" "")
8631 (const_string "RR") (const_string "RX")))
8632 (set_attr "type" "jsr")
8633 (set_attr "atype" "agen")
8634 (set_attr "z196prop" "z196_cracked")])
8637 ;;- Thread-local storage support.
8640 (define_expand "get_tp_64"
8641 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8645 (define_expand "get_tp_31"
8646 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8650 (define_expand "set_tp_64"
8651 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8652 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8656 (define_expand "set_tp_31"
8657 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8658 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8662 (define_insn "*set_tp"
8663 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8666 [(set_attr "type" "none")
8667 (set_attr "length" "0")])
8669 (define_insn "*tls_load_64"
8670 [(set (match_operand:DI 0 "register_operand" "=d")
8671 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8672 (match_operand:DI 2 "" "")]
8676 [(set_attr "op_type" "RXE")
8677 (set_attr "z10prop" "z10_fwd_A3")])
8679 (define_insn "*tls_load_31"
8680 [(set (match_operand:SI 0 "register_operand" "=d,d")
8681 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8682 (match_operand:SI 2 "" "")]
8688 [(set_attr "op_type" "RX,RXY")
8689 (set_attr "type" "load")
8690 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8692 (define_insn "*bras_tls"
8693 [(set (match_operand 0 "" "")
8694 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8695 (match_operand 2 "const_int_operand" "n")))
8696 (clobber (match_operand 3 "register_operand" "=r"))
8697 (use (match_operand 4 "" ""))]
8698 "!SIBLING_CALL_P (insn)
8699 && TARGET_SMALL_EXEC
8700 && GET_MODE (operands[3]) == Pmode"
8702 [(set_attr "op_type" "RI")
8703 (set_attr "type" "jsr")
8704 (set_attr "z196prop" "z196_cracked")])
8706 (define_insn "*brasl_tls"
8707 [(set (match_operand 0 "" "")
8708 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8709 (match_operand 2 "const_int_operand" "n")))
8710 (clobber (match_operand 3 "register_operand" "=r"))
8711 (use (match_operand 4 "" ""))]
8712 "!SIBLING_CALL_P (insn)
8714 && GET_MODE (operands[3]) == Pmode"
8716 [(set_attr "op_type" "RIL")
8717 (set_attr "type" "jsr")
8718 (set_attr "z196prop" "z196_cracked")])
8720 (define_insn "*basr_tls"
8721 [(set (match_operand 0 "" "")
8722 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8723 (match_operand 2 "const_int_operand" "n")))
8724 (clobber (match_operand 3 "register_operand" "=r"))
8725 (use (match_operand 4 "" ""))]
8726 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8728 if (get_attr_op_type (insn) == OP_TYPE_RR)
8729 return "basr\t%3,%1%J4";
8731 return "bas\t%3,%a1%J4";
8733 [(set (attr "op_type")
8734 (if_then_else (match_operand 1 "register_operand" "")
8735 (const_string "RR") (const_string "RX")))
8736 (set_attr "type" "jsr")
8737 (set_attr "atype" "agen")
8738 (set_attr "z196prop" "z196_cracked")])
8741 ;;- Atomic operations
8745 ; memory barrier patterns.
8748 (define_expand "mem_signal_fence"
8749 [(match_operand:SI 0 "const_int_operand")] ;; model
8752 /* The s390 memory model is strong enough not to require any
8753 barrier in order to synchronize a thread with itself. */
8757 (define_expand "mem_thread_fence"
8758 [(match_operand:SI 0 "const_int_operand")] ;; model
8761 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8762 enough not to require barriers of any kind. */
8763 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
8765 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8766 MEM_VOLATILE_P (mem) = 1;
8767 emit_insn (gen_mem_thread_fence_1 (mem));
8772 ; Although bcr is superscalar on Z10, this variant will never
8773 ; become part of an execution group.
8774 (define_insn "mem_thread_fence_1"
8775 [(set (match_operand:BLK 0 "" "")
8776 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8779 [(set_attr "op_type" "RR")])
8782 ; atomic load/store operations
8785 ; Atomic loads need not examine the memory model at all.
8786 (define_expand "atomic_load<mode>"
8787 [(match_operand:DINT 0 "register_operand") ;; output
8788 (match_operand:DINT 1 "memory_operand") ;; memory
8789 (match_operand:SI 2 "const_int_operand")] ;; model
8792 if (<MODE>mode == TImode)
8793 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
8794 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8795 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
8797 emit_move_insn (operands[0], operands[1]);
8801 ; Different from movdi_31 in that we want no splitters.
8802 (define_insn "atomic_loaddi_1"
8803 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
8804 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
8812 [(set_attr "op_type" "RS,RSY,RS,RSY")
8813 (set_attr "type" "lm,lm,floaddf,floaddf")])
8815 (define_insn "atomic_loadti_1"
8816 [(set (match_operand:TI 0 "register_operand" "=r")
8817 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
8821 [(set_attr "op_type" "RXY")
8822 (set_attr "type" "other")])
8824 ; Atomic stores must(?) enforce sequential consistency.
8825 (define_expand "atomic_store<mode>"
8826 [(match_operand:DINT 0 "memory_operand") ;; memory
8827 (match_operand:DINT 1 "register_operand") ;; input
8828 (match_operand:SI 2 "const_int_operand")] ;; model
8831 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
8833 if (<MODE>mode == TImode)
8834 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
8835 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8836 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
8838 emit_move_insn (operands[0], operands[1]);
8839 if (model == MEMMODEL_SEQ_CST)
8840 emit_insn (gen_mem_thread_fence (operands[2]));
8844 ; Different from movdi_31 in that we want no splitters.
8845 (define_insn "atomic_storedi_1"
8846 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
8847 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
8855 [(set_attr "op_type" "RS,RSY,RS,RSY")
8856 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
8858 (define_insn "atomic_storeti_1"
8859 [(set (match_operand:TI 0 "memory_operand" "=RT")
8860 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
8864 [(set_attr "op_type" "RXY")
8865 (set_attr "type" "other")])
8868 ; compare and swap patterns.
8871 (define_expand "atomic_compare_and_swap<mode>"
8872 [(match_operand:SI 0 "register_operand") ;; bool success output
8873 (match_operand:DGPR 1 "register_operand") ;; oldval output
8874 (match_operand:DGPR 2 "memory_operand") ;; memory
8875 (match_operand:DGPR 3 "register_operand") ;; expected intput
8876 (match_operand:DGPR 4 "register_operand") ;; newval intput
8877 (match_operand:SI 5 "const_int_operand") ;; is_weak
8878 (match_operand:SI 6 "const_int_operand") ;; success model
8879 (match_operand:SI 7 "const_int_operand")] ;; failure model
8883 emit_insn (gen_atomic_compare_and_swap<mode>_internal
8884 (operands[1], operands[2], operands[3], operands[4]));
8885 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
8886 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
8887 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
8891 (define_expand "atomic_compare_and_swap<mode>"
8892 [(match_operand:SI 0 "register_operand") ;; bool success output
8893 (match_operand:HQI 1 "register_operand") ;; oldval output
8894 (match_operand:HQI 2 "memory_operand") ;; memory
8895 (match_operand:HQI 3 "general_operand") ;; expected intput
8896 (match_operand:HQI 4 "general_operand") ;; newval intput
8897 (match_operand:SI 5 "const_int_operand") ;; is_weak
8898 (match_operand:SI 6 "const_int_operand") ;; success model
8899 (match_operand:SI 7 "const_int_operand")] ;; failure model
8902 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
8903 operands[3], operands[4], INTVAL (operands[5]));
8907 (define_expand "atomic_compare_and_swap<mode>_internal"
8909 [(set (match_operand:DGPR 0 "register_operand")
8910 (match_operand:DGPR 1 "memory_operand"))
8912 (unspec_volatile:DGPR
8914 (match_operand:DGPR 2 "register_operand")
8915 (match_operand:DGPR 3 "register_operand")]
8917 (set (reg:CCZ1 CC_REGNUM)
8918 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8922 (define_insn "*atomic_compare_and_swap<mode>_1"
8923 [(set (match_operand:TDI 0 "register_operand" "=r")
8924 (match_operand:TDI 1 "memory_operand" "+QS"))
8926 (unspec_volatile:TDI
8928 (match_operand:TDI 2 "register_operand" "0")
8929 (match_operand:TDI 3 "register_operand" "r")]
8931 (set (reg:CCZ1 CC_REGNUM)
8932 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8934 "c<td>sg\t%0,%3,%S1"
8935 [(set_attr "op_type" "RSY")
8936 (set_attr "type" "sem")])
8939 (define_insn "*atomic_compare_and_swapdi_2"
8940 [(set (match_operand:DI 0 "register_operand" "=r,r")
8941 (match_operand:DI 1 "memory_operand" "+Q,S"))
8945 (match_operand:DI 2 "register_operand" "0,0")
8946 (match_operand:DI 3 "register_operand" "r,r")]
8948 (set (reg:CCZ1 CC_REGNUM)
8949 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8954 [(set_attr "op_type" "RS,RSY")
8955 (set_attr "type" "sem")])
8958 (define_insn "*atomic_compare_and_swapsi_3"
8959 [(set (match_operand:SI 0 "register_operand" "=r,r")
8960 (match_operand:SI 1 "memory_operand" "+Q,S"))
8964 (match_operand:SI 2 "register_operand" "0,0")
8965 (match_operand:SI 3 "register_operand" "r,r")]
8967 (set (reg:CCZ1 CC_REGNUM)
8968 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8973 [(set_attr "op_type" "RS,RSY")
8974 (set_attr "type" "sem")])
8977 ; Other atomic instruction patterns.
8980 ; z196 load and add, xor, or and and instructions
8982 (define_expand "atomic_fetch_<atomic><mode>"
8983 [(match_operand:GPR 0 "register_operand") ;; val out
8985 (match_operand:GPR 1 "memory_operand") ;; memory
8986 (match_operand:GPR 2 "register_operand")) ;; val in
8987 (match_operand:SI 3 "const_int_operand")] ;; model
8990 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
8991 (operands[0], operands[1], operands[2]));
8995 ; lan, lang, lao, laog, lax, laxg, laa, laag
8996 (define_insn "atomic_fetch_<atomic><mode>_iaf"
8997 [(set (match_operand:GPR 0 "register_operand" "=d")
8998 (match_operand:GPR 1 "memory_operand" "+QS"))
9000 (unspec_volatile:GPR
9001 [(ATOMIC_Z196:GPR (match_dup 1)
9002 (match_operand:GPR 2 "general_operand" "d"))]
9004 (clobber (reg:CC CC_REGNUM))]
9006 "la<noxa><g>\t%0,%2,%1"
9007 [(set_attr "op_type" "RSY")
9008 (set_attr "type" "sem")])
9010 ;; For SImode and larger, the optabs.c code will do just fine in
9011 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9012 ;; better by expanding our own loop.
9014 (define_expand "atomic_<atomic><mode>"
9016 (match_operand:HQI 0 "memory_operand") ;; memory
9017 (match_operand:HQI 1 "general_operand")) ;; val in
9018 (match_operand:SI 2 "const_int_operand")] ;; model
9021 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9022 operands[1], false);
9026 (define_expand "atomic_fetch_<atomic><mode>"
9027 [(match_operand:HQI 0 "register_operand") ;; val out
9029 (match_operand:HQI 1 "memory_operand") ;; memory
9030 (match_operand:HQI 2 "general_operand")) ;; val in
9031 (match_operand:SI 3 "const_int_operand")] ;; model
9034 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9035 operands[2], false);
9039 (define_expand "atomic_<atomic>_fetch<mode>"
9040 [(match_operand:HQI 0 "register_operand") ;; val out
9042 (match_operand:HQI 1 "memory_operand") ;; memory
9043 (match_operand:HQI 2 "general_operand")) ;; val in
9044 (match_operand:SI 3 "const_int_operand")] ;; model
9047 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9052 (define_expand "atomic_exchange<mode>"
9053 [(match_operand:HQI 0 "register_operand") ;; val out
9054 (match_operand:HQI 1 "memory_operand") ;; memory
9055 (match_operand:HQI 2 "general_operand") ;; val in
9056 (match_operand:SI 3 "const_int_operand")] ;; model
9059 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9060 operands[2], false);
9065 ;;- Miscellaneous instructions.
9069 ; allocate stack instruction pattern(s).
9072 (define_expand "allocate_stack"
9073 [(match_operand 0 "general_operand" "")
9074 (match_operand 1 "general_operand" "")]
9077 rtx temp = gen_reg_rtx (Pmode);
9079 emit_move_insn (temp, s390_back_chain_rtx ());
9080 anti_adjust_stack (operands[1]);
9081 emit_move_insn (s390_back_chain_rtx (), temp);
9083 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9089 ; setjmp instruction pattern.
9092 (define_expand "builtin_setjmp_receiver"
9093 [(match_operand 0 "" "")]
9096 emit_insn (s390_load_got ());
9097 emit_use (pic_offset_table_rtx);
9101 ;; These patterns say how to save and restore the stack pointer. We need not
9102 ;; save the stack pointer at function level since we are careful to
9103 ;; preserve the backchain. At block level, we have to restore the backchain
9104 ;; when we restore the stack pointer.
9106 ;; For nonlocal gotos, we must save both the stack pointer and its
9107 ;; backchain and restore both. Note that in the nonlocal case, the
9108 ;; save area is a memory location.
9110 (define_expand "save_stack_function"
9111 [(match_operand 0 "general_operand" "")
9112 (match_operand 1 "general_operand" "")]
9116 (define_expand "restore_stack_function"
9117 [(match_operand 0 "general_operand" "")
9118 (match_operand 1 "general_operand" "")]
9122 (define_expand "restore_stack_block"
9123 [(match_operand 0 "register_operand" "")
9124 (match_operand 1 "register_operand" "")]
9127 rtx temp = gen_reg_rtx (Pmode);
9129 emit_move_insn (temp, s390_back_chain_rtx ());
9130 emit_move_insn (operands[0], operands[1]);
9131 emit_move_insn (s390_back_chain_rtx (), temp);
9136 (define_expand "save_stack_nonlocal"
9137 [(match_operand 0 "memory_operand" "")
9138 (match_operand 1 "register_operand" "")]
9141 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9143 /* Copy the backchain to the first word, sp to the second and the
9144 literal pool base to the third. */
9146 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9147 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9148 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9150 if (TARGET_BACKCHAIN)
9151 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9153 emit_move_insn (save_sp, operands[1]);
9154 emit_move_insn (save_bp, base);
9159 (define_expand "restore_stack_nonlocal"
9160 [(match_operand 0 "register_operand" "")
9161 (match_operand 1 "memory_operand" "")]
9164 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9165 rtx temp = NULL_RTX;
9167 /* Restore the backchain from the first word, sp from the second and the
9168 literal pool base from the third. */
9170 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9171 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9172 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9174 if (TARGET_BACKCHAIN)
9175 temp = force_reg (Pmode, save_bc);
9177 emit_move_insn (base, save_bp);
9178 emit_move_insn (operands[0], save_sp);
9181 emit_move_insn (s390_back_chain_rtx (), temp);
9187 (define_expand "exception_receiver"
9191 s390_set_has_landing_pad_p (true);
9196 ; nop instruction pattern(s).
9203 [(set_attr "op_type" "RR")
9204 (set_attr "z10prop" "z10_fr_E1")])
9210 [(set_attr "op_type" "RR")])
9214 ; Special literal pool access instruction pattern(s).
9217 (define_insn "*pool_entry"
9218 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9219 UNSPECV_POOL_ENTRY)]
9222 enum machine_mode mode = GET_MODE (PATTERN (insn));
9223 unsigned int align = GET_MODE_BITSIZE (mode);
9224 s390_output_pool_entry (operands[0], mode, align);
9227 [(set (attr "length")
9228 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9230 (define_insn "pool_align"
9231 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9232 UNSPECV_POOL_ALIGN)]
9235 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9237 (define_insn "pool_section_start"
9238 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9241 [(set_attr "length" "0")])
9243 (define_insn "pool_section_end"
9244 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9247 [(set_attr "length" "0")])
9249 (define_insn "main_base_31_small"
9250 [(set (match_operand 0 "register_operand" "=a")
9251 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9252 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9254 [(set_attr "op_type" "RR")
9255 (set_attr "type" "la")
9256 (set_attr "z196prop" "z196_cracked")])
9258 (define_insn "main_base_31_large"
9259 [(set (match_operand 0 "register_operand" "=a")
9260 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9261 (set (pc) (label_ref (match_operand 2 "" "")))]
9262 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9264 [(set_attr "op_type" "RI")
9265 (set_attr "z196prop" "z196_cracked")])
9267 (define_insn "main_base_64"
9268 [(set (match_operand 0 "register_operand" "=a")
9269 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9270 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9272 [(set_attr "op_type" "RIL")
9273 (set_attr "type" "larl")
9274 (set_attr "z10prop" "z10_fwd_A1")])
9276 (define_insn "main_pool"
9277 [(set (match_operand 0 "register_operand" "=a")
9278 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9279 "GET_MODE (operands[0]) == Pmode"
9284 (if_then_else (match_test "TARGET_CPU_ZARCH")
9285 (const_string "larl") (const_string "la")))])
9287 (define_insn "reload_base_31"
9288 [(set (match_operand 0 "register_operand" "=a")
9289 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9290 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9291 "basr\t%0,0\;la\t%0,%1-.(%0)"
9292 [(set_attr "length" "6")
9293 (set_attr "type" "la")
9294 (set_attr "z196prop" "z196_cracked")])
9296 (define_insn "reload_base_64"
9297 [(set (match_operand 0 "register_operand" "=a")
9298 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9299 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9301 [(set_attr "op_type" "RIL")
9302 (set_attr "type" "larl")
9303 (set_attr "z10prop" "z10_fwd_A1")])
9306 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9311 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9314 ;; Insns related to generating the function prologue and epilogue.
9318 (define_expand "prologue"
9319 [(use (const_int 0))]
9321 "s390_emit_prologue (); DONE;")
9323 (define_expand "epilogue"
9324 [(use (const_int 1))]
9326 "s390_emit_epilogue (false); DONE;")
9328 (define_expand "sibcall_epilogue"
9329 [(use (const_int 0))]
9331 "s390_emit_epilogue (true); DONE;")
9333 (define_insn "*return"
9335 (use (match_operand 0 "register_operand" "a"))]
9336 "GET_MODE (operands[0]) == Pmode"
9338 [(set_attr "op_type" "RR")
9339 (set_attr "type" "jsr")
9340 (set_attr "atype" "agen")])
9343 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9344 ;; pointer. This is used for compatibility.
9346 (define_expand "ptr_extend"
9347 [(set (match_operand:DI 0 "register_operand" "=r")
9348 (match_operand:SI 1 "register_operand" "r"))]
9351 emit_insn (gen_anddi3 (operands[0],
9352 gen_lowpart (DImode, operands[1]),
9353 GEN_INT (0x7fffffff)));
9357 ;; Instruction definition to expand eh_return macro to support
9358 ;; swapping in special linkage return addresses.
9360 (define_expand "eh_return"
9361 [(use (match_operand 0 "register_operand" ""))]
9364 s390_emit_tpf_eh_return (operands[0]);
9369 ; Stack Protector Patterns
9372 (define_expand "stack_protect_set"
9373 [(set (match_operand 0 "memory_operand" "")
9374 (match_operand 1 "memory_operand" ""))]
9377 #ifdef TARGET_THREAD_SSP_OFFSET
9379 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9380 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9383 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9385 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9390 (define_insn "stack_protect_set<mode>"
9391 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9392 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9394 "mvc\t%O0(%G0,%R0),%S1"
9395 [(set_attr "op_type" "SS")])
9397 (define_expand "stack_protect_test"
9398 [(set (reg:CC CC_REGNUM)
9399 (compare (match_operand 0 "memory_operand" "")
9400 (match_operand 1 "memory_operand" "")))
9401 (match_operand 2 "" "")]
9405 #ifdef TARGET_THREAD_SSP_OFFSET
9407 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9408 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9411 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9413 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9415 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9416 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9417 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9421 (define_insn "stack_protect_test<mode>"
9422 [(set (reg:CCZ CC_REGNUM)
9423 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9424 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9426 "clc\t%O0(%G0,%R0),%S1"
9427 [(set_attr "op_type" "SS")])
9429 ; This is used in s390_emit_prologue in order to prevent insns
9430 ; adjusting the stack pointer to be moved over insns writing stack
9431 ; slots using a copy of the stack pointer in a different register.
9432 (define_insn "stack_tie"
9433 [(set (match_operand:BLK 0 "memory_operand" "+m")
9434 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9437 [(set_attr "length" "0")])
9441 ; Data prefetch patterns
9444 (define_insn "prefetch"
9445 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9446 (match_operand:SI 1 "const_int_operand" " n,n")
9447 (match_operand:SI 2 "const_int_operand" " n,n"))]
9450 switch (which_alternative)
9453 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9455 if (larl_operand (operands[0], Pmode))
9456 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9459 /* This might be reached for symbolic operands with an odd
9460 addend. We simply omit the prefetch for such rare cases. */
9465 [(set_attr "type" "load,larl")
9466 (set_attr "op_type" "RXY,RIL")
9467 (set_attr "z10prop" "z10_super")
9468 (set_attr "z196prop" "z196_alone")])
9472 ; Byte swap instructions
9475 (define_insn "bswap<mode>2"
9476 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9477 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9482 [(set_attr "type" "*,load")
9483 (set_attr "op_type" "RRE,RXY")
9484 (set_attr "z10prop" "z10_super")])
9488 ; Population count instruction
9491 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9492 ; portions and stores the result in the corresponding bytes in op0.
9493 (define_insn "*popcount<mode>"
9494 [(set (match_operand:INT 0 "register_operand" "=d")
9495 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9496 (clobber (reg:CC CC_REGNUM))]
9499 [(set_attr "op_type" "RRE")])
9501 (define_expand "popcountdi2"
9503 (parallel [(set (match_operand:DI 0 "register_operand" "")
9504 (unspec:DI [(match_operand:DI 1 "register_operand")]
9506 (clobber (reg:CC CC_REGNUM))])
9508 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9510 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9511 (clobber (reg:CC CC_REGNUM))])
9514 (ashift:DI (match_dup 0) (const_int 16)))
9516 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9517 (clobber (reg:CC CC_REGNUM))])
9519 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9521 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9522 (clobber (reg:CC CC_REGNUM))])
9524 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9525 "TARGET_Z196 && TARGET_64BIT"
9526 "operands[2] = gen_reg_rtx (DImode);")
9528 (define_expand "popcountsi2"
9530 (parallel [(set (match_operand:SI 0 "register_operand" "")
9531 (unspec:SI [(match_operand:SI 1 "register_operand")]
9533 (clobber (reg:CC CC_REGNUM))])
9536 (ashift:SI (match_dup 0) (const_int 16)))
9538 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9539 (clobber (reg:CC CC_REGNUM))])
9541 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9543 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9544 (clobber (reg:CC CC_REGNUM))])
9546 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9548 "operands[2] = gen_reg_rtx (SImode);")
9550 (define_expand "popcounthi2"
9552 (parallel [(set (match_operand:HI 0 "register_operand" "")
9553 (unspec:HI [(match_operand:HI 1 "register_operand")]
9555 (clobber (reg:CC CC_REGNUM))])
9558 (ashift:SI (match_dup 0) (const_int 8)))
9560 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9561 (clobber (reg:CC CC_REGNUM))])
9563 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9565 "operands[2] = gen_reg_rtx (SImode);")
9567 (define_expand "popcountqi2"
9569 (parallel [(set (match_operand:QI 0 "register_operand" "")
9570 (unspec:QI [(match_operand:QI 1 "register_operand")]
9572 (clobber (reg:CC CC_REGNUM))])]
9577 ;;- Copy sign instructions
9580 (define_insn "copysign<mode>3"
9581 [(set (match_operand:FP 0 "register_operand" "=f")
9582 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9583 (match_operand:FP 2 "register_operand" "f")]
9587 [(set_attr "op_type" "RRF")
9588 (set_attr "type" "fsimp<mode>")])