1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
88 ; TLS relocation specifiers
93 (UNSPEC_GOTNTPOFF 504)
94 (UNSPEC_INDNTPOFF 505)
97 (UNSPEC_TLSLDM_NTPOFF 511)
104 ; Stack Smashing Protector
108 ; Test Data Class (TDC)
109 (UNSPEC_TDC_INSN 800)
113 (UNSPEC_COPYSIGN 901)
117 ;; UNSPEC_VOLATILE usage
125 (UNSPECV_TPF_PROLOGUE 20)
126 (UNSPECV_TPF_EPILOGUE 21)
130 (UNSPECV_POOL_SECTION 201)
131 (UNSPECV_POOL_ALIGN 202)
132 (UNSPECV_POOL_ENTRY 203)
133 (UNSPECV_MAIN_POOL 300)
140 (UNSPECV_ATOMIC_OP 701)
147 ; Registers with special meaning
151 ; Sibling call register.
153 ; Literal pool base register.
155 ; Return address register.
157 ; Condition code register.
159 ; Thread local storage pointer register.
163 ; Hardware register names
167 ; General purpose registers
169 ; Floating point registers.
175 ;; PFPO GPR0 argument format
180 ; PFPO operation type
181 (PFPO_CONVERT 0x1000000)
183 (PFPO_OP_TYPE_SF 0x5)
184 (PFPO_OP_TYPE_DF 0x6)
185 (PFPO_OP_TYPE_TF 0x7)
186 (PFPO_OP_TYPE_SD 0x8)
187 (PFPO_OP_TYPE_DD 0x9)
188 (PFPO_OP_TYPE_TD 0xa)
189 ; Bitposition of operand types
190 (PFPO_OP0_TYPE_SHIFT 16)
191 (PFPO_OP1_TYPE_SHIFT 8)
195 ;; Instruction operand type as used in the Principles of Operation.
196 ;; Used to determine defaults for length and other attribute values.
198 (define_attr "op_type"
199 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
202 ;; Instruction type attribute used for scheduling.
204 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
205 cs,vs,store,sem,idiv,
206 imulhi,imulsi,imuldi,
207 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
208 floadtf,floaddf,floadsf,fstoredf,fstoresf,
209 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
210 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
212 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
213 itoftf, itofdf, itofsf, itofdd, itoftd,
214 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
215 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
217 (cond [(eq_attr "op_type" "NN") (const_string "other")
218 (eq_attr "op_type" "SS") (const_string "cs")]
219 (const_string "integer")))
221 ;; Another attribute used for scheduling purposes:
222 ;; agen: Instruction uses the address generation unit
223 ;; reg: Instruction does not use the agen unit
225 (define_attr "atype" "agen,reg"
226 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
228 (const_string "agen")))
230 ;; Properties concerning Z10 execution grouping and value forwarding.
231 ;; z10_super: instruction is superscalar.
232 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
233 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
234 ;; target register. It can forward this value to a second instruction that reads
235 ;; the same register if that second instruction is issued in the same group.
236 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
237 ;; instruction in the S pipe writes to the register, then the T instruction
238 ;; can immediately read the new value.
239 ;; z10_fr: union of Z10_fwd and z10_rec.
240 ;; z10_c: second operand of instruction is a register and read with complemented bits.
242 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
245 (define_attr "z10prop" "none,
246 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
247 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
249 z10_fr, z10_fr_A3, z10_fr_E1,
251 (const_string "none"))
253 ;; Properties concerning Z196 decoding
254 ;; z196_alone: must group alone
255 ;; z196_end: ends a group
256 ;; z196_cracked: instruction is cracked or expanded
257 (define_attr "z196prop" "none,
258 z196_alone, z196_ends,
260 (const_string "none"))
264 (define_attr "length" ""
265 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
266 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
270 ;; Processor type. This attribute must exactly match the processor_type
271 ;; enumeration in s390.h. The current machine description does not
272 ;; distinguish between g5 and g6, but there are differences between the two
273 ;; CPUs could in theory be modeled.
275 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10,z196"
276 (const (symbol_ref "s390_tune_attr")))
278 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196"
279 (const_string "standard"))
281 (define_attr "enabled" ""
282 (cond [(eq_attr "cpu_facility" "standard")
285 (and (eq_attr "cpu_facility" "ieee")
286 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
289 (and (eq_attr "cpu_facility" "zarch")
290 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
293 (and (eq_attr "cpu_facility" "longdisp")
294 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
297 (and (eq_attr "cpu_facility" "extimm")
298 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
301 (and (eq_attr "cpu_facility" "dfp")
302 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
305 (and (eq_attr "cpu_facility" "z10")
306 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
309 (and (eq_attr "cpu_facility" "z196")
310 (ne (symbol_ref "TARGET_Z196") (const_int 0)))
314 ;; Pipeline description for z900. For lack of anything better,
315 ;; this description is also used for the g5 and g6.
318 ;; Pipeline description for z990, z9-109 and z9-ec.
321 ;; Pipeline description for z10
324 ;; Pipeline description for z196
328 (include "predicates.md")
330 ;; Constraint definitions
331 (include "constraints.md")
338 ;; These mode iterators allow floating point patterns to be generated from the
340 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
341 (SD "TARGET_HARD_DFP")])
342 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
343 (define_mode_iterator FPALL [TF DF SF TD DD SD])
344 (define_mode_iterator BFP [TF DF SF])
345 (define_mode_iterator DFP [TD DD])
346 (define_mode_iterator DFP_ALL [TD DD SD])
347 (define_mode_iterator DSF [DF SF])
348 (define_mode_iterator SD_SF [SF SD])
349 (define_mode_iterator DD_DF [DF DD])
350 (define_mode_iterator TD_TF [TF TD])
352 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
353 ;; from the same template.
354 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
356 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
357 ;; from the same template.
358 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
359 (define_mode_iterator DSI [DI SI])
361 ;; These mode iterators allow :P to be used for patterns that operate on
362 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
363 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
365 ;; These macros refer to the actual word_mode of the configuration. This is equal
366 ;; to Pmode except on 31-bit machines in zarch mode.
367 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
368 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
370 ;; This mode iterator allows the QI and HI patterns to be defined from
371 ;; the same template.
372 (define_mode_iterator HQI [HI QI])
374 ;; This mode iterator allows the integer patterns to be defined from the
376 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
377 (define_mode_iterator INTALL [TI DI SI HI QI])
379 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
380 ;; the same template.
381 (define_code_iterator SHIFT [ashift lshiftrt])
383 ;; This iterator and attribute allow to combine most atomic operations.
384 (define_code_iterator ATOMIC [and ior xor plus minus mult])
385 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
386 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
387 (plus "add") (minus "sub") (mult "nand")])
388 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
390 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
391 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
392 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
394 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
395 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
397 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
399 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
400 ;; Likewise for "<RXe>".
401 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
402 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
404 ;; The decimal floating point variants of add, sub, div and mul support 3
405 ;; fp register operands. The following attributes allow to merge the bfp and
406 ;; dfp variants in a single insn definition.
408 ;; This attribute is used to set op_type accordingly.
409 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
410 (DD "RRR") (SD "RRR")])
412 ;; This attribute is used in the operand constraint list in order to have the
413 ;; first and the second operand match for bfp modes.
414 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
416 ;; This attribute is used in the operand list of the instruction to have an
417 ;; additional operand for the dfp instructions.
418 (define_mode_attr op1 [(TF "") (DF "") (SF "")
419 (TD "%1,") (DD "%1,") (SD "%1,")])
422 ;; This attribute is used in the operand constraint list
423 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
424 ;; TFmode values are represented by a fp register pair. Since the
425 ;; sign bit instructions only handle single source and target fp registers
426 ;; these instructions can only be used for TFmode values if the source and
427 ;; target operand uses the same fp register.
428 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
430 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
431 ;; This is used to disable the memory alternative in TFmode patterns.
432 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
434 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
435 ;; within instruction mnemonics.
436 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
438 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
439 ;; modes and to an empty string for bfp modes.
440 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
442 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
443 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
444 ;; version only operates on one register.
445 (define_mode_attr d0 [(DI "d") (SI "0")])
447 ;; In combination with d0 this allows to combine instructions of which the 31bit
448 ;; version only operates on one register. The DImode version needs an additional
449 ;; register for the assembler output.
450 (define_mode_attr 1 [(DI "%1,") (SI "")])
452 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
453 ;; 'ashift' and "srdl" in 'lshiftrt'.
454 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
456 ;; In SHIFT templates, this attribute holds the correct standard name for the
457 ;; pattern itself and the corresponding function calls.
458 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
460 ;; This attribute handles differences in the instruction 'type' and will result
461 ;; in "RRE" for DImode and "RR" for SImode.
462 (define_mode_attr E [(DI "E") (SI "")])
464 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
465 ;; to result in "RXY" for DImode and "RX" for SImode.
466 (define_mode_attr Y [(DI "Y") (SI "")])
468 ;; This attribute handles differences in the instruction 'type' and will result
469 ;; in "RSE" for TImode and "RS" for DImode.
470 (define_mode_attr TE [(TI "E") (DI "")])
472 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
473 ;; and "lcr" in SImode.
474 (define_mode_attr g [(DI "g") (SI "")])
476 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
477 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
478 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
479 ;; variant for long displacements.
480 (define_mode_attr y [(DI "g") (SI "y")])
482 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
483 ;; and "cds" in DImode.
484 (define_mode_attr tg [(TI "g") (DI "")])
486 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
487 ;; and "cfdbr" in SImode.
488 (define_mode_attr gf [(DI "g") (SI "f")])
490 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
491 ;; and sllk for SI. This way it is possible to merge the new z196 SI
492 ;; 3 operands shift instructions into the existing patterns.
493 (define_mode_attr gk [(DI "g") (SI "k")])
495 ;; ICM mask required to load MODE value into the lowest subreg
496 ;; of a SImode register.
497 (define_mode_attr icm_lo [(HI "3") (QI "1")])
499 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
500 ;; HImode and "llgc" in QImode.
501 (define_mode_attr hc [(HI "h") (QI "c")])
503 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
505 (define_mode_attr DBL [(DI "TI") (SI "DI")])
507 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
508 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
509 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
511 ;; Maximum unsigned integer that fits in MODE.
512 (define_mode_attr max_uint [(HI "65535") (QI "255")])
515 ;;- Compare instructions.
518 ; Test-under-Mask instructions
520 (define_insn "*tmqi_mem"
521 [(set (reg CC_REGNUM)
522 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
523 (match_operand:QI 1 "immediate_operand" "n,n"))
524 (match_operand:QI 2 "immediate_operand" "n,n")))]
525 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
529 [(set_attr "op_type" "SI,SIY")
530 (set_attr "z10prop" "z10_super,z10_super")])
532 (define_insn "*tmdi_reg"
533 [(set (reg CC_REGNUM)
534 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
535 (match_operand:DI 1 "immediate_operand"
536 "N0HD0,N1HD0,N2HD0,N3HD0"))
537 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
539 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
540 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
546 [(set_attr "op_type" "RI")
547 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
549 (define_insn "*tmsi_reg"
550 [(set (reg CC_REGNUM)
551 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
552 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
553 (match_operand:SI 2 "immediate_operand" "n,n")))]
554 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
555 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
559 [(set_attr "op_type" "RI")
560 (set_attr "z10prop" "z10_super,z10_super")])
562 (define_insn "*tm<mode>_full"
563 [(set (reg CC_REGNUM)
564 (compare (match_operand:HQI 0 "register_operand" "d")
565 (match_operand:HQI 1 "immediate_operand" "n")))]
566 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
568 [(set_attr "op_type" "RI")
569 (set_attr "z10prop" "z10_super")])
573 ; Load-and-Test instructions
576 ; tst(di|si) instruction pattern(s).
578 (define_insn "*tstdi_sign"
579 [(set (reg CC_REGNUM)
583 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
584 (const_int 32)) (const_int 32))
585 (match_operand:DI 1 "const0_operand" "")))
586 (set (match_operand:DI 2 "register_operand" "=d,d")
587 (sign_extend:DI (match_dup 0)))]
588 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
591 [(set_attr "op_type" "RRE,RXY")
592 (set_attr "cpu_facility" "*,z10")
593 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
596 (define_insn "*tst<mode>_extimm"
597 [(set (reg CC_REGNUM)
598 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
599 (match_operand:GPR 1 "const0_operand" "")))
600 (set (match_operand:GPR 2 "register_operand" "=d,d")
602 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
606 [(set_attr "op_type" "RR<E>,RXY")
607 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
610 (define_insn "*tst<mode>_cconly_extimm"
611 [(set (reg CC_REGNUM)
612 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
613 (match_operand:GPR 1 "const0_operand" "")))
614 (clobber (match_scratch:GPR 2 "=X,d"))]
615 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
619 [(set_attr "op_type" "RR<E>,RXY")
620 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
622 (define_insn "*tstdi"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:DI 0 "register_operand" "d")
625 (match_operand:DI 1 "const0_operand" "")))
626 (set (match_operand:DI 2 "register_operand" "=d")
628 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
630 [(set_attr "op_type" "RRE")
631 (set_attr "z10prop" "z10_fr_E1")])
633 (define_insn "*tstsi"
634 [(set (reg CC_REGNUM)
635 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
636 (match_operand:SI 1 "const0_operand" "")))
637 (set (match_operand:SI 2 "register_operand" "=d,d,d")
639 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
644 [(set_attr "op_type" "RR,RS,RSY")
645 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
647 (define_insn "*tstsi_cconly"
648 [(set (reg CC_REGNUM)
649 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
650 (match_operand:SI 1 "const0_operand" "")))
651 (clobber (match_scratch:SI 2 "=X,d,d"))]
652 "s390_match_ccmode(insn, CCSmode)"
657 [(set_attr "op_type" "RR,RS,RSY")
658 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
660 (define_insn "*tstdi_cconly_31"
661 [(set (reg CC_REGNUM)
662 (compare (match_operand:DI 0 "register_operand" "d")
663 (match_operand:DI 1 "const0_operand" "")))]
664 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
666 [(set_attr "op_type" "RS")
667 (set_attr "atype" "reg")])
670 (define_insn "*tst<mode>_cconly2"
671 [(set (reg CC_REGNUM)
672 (compare (match_operand:GPR 0 "register_operand" "d")
673 (match_operand:GPR 1 "const0_operand" "")))]
674 "s390_match_ccmode(insn, CCSmode)"
676 [(set_attr "op_type" "RR<E>")
677 (set_attr "z10prop" "z10_fr_E1")])
679 ; tst(hi|qi) instruction pattern(s).
681 (define_insn "*tst<mode>CCT"
682 [(set (reg CC_REGNUM)
683 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
684 (match_operand:HQI 1 "const0_operand" "")))
685 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
687 "s390_match_ccmode(insn, CCTmode)"
690 icmy\t%2,<icm_lo>,%S0
692 [(set_attr "op_type" "RS,RSY,RI")
693 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
695 (define_insn "*tsthiCCT_cconly"
696 [(set (reg CC_REGNUM)
697 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
698 (match_operand:HI 1 "const0_operand" "")))
699 (clobber (match_scratch:HI 2 "=d,d,X"))]
700 "s390_match_ccmode(insn, CCTmode)"
705 [(set_attr "op_type" "RS,RSY,RI")
706 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
708 (define_insn "*tstqiCCT_cconly"
709 [(set (reg CC_REGNUM)
710 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
711 (match_operand:QI 1 "const0_operand" "")))]
712 "s390_match_ccmode(insn, CCTmode)"
717 [(set_attr "op_type" "SI,SIY,RI")
718 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
720 (define_insn "*tst<mode>"
721 [(set (reg CC_REGNUM)
722 (compare (match_operand:HQI 0 "s_operand" "Q,S")
723 (match_operand:HQI 1 "const0_operand" "")))
724 (set (match_operand:HQI 2 "register_operand" "=d,d")
726 "s390_match_ccmode(insn, CCSmode)"
729 icmy\t%2,<icm_lo>,%S0"
730 [(set_attr "op_type" "RS,RSY")
731 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
733 (define_insn "*tst<mode>_cconly"
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:HQI 0 "s_operand" "Q,S")
736 (match_operand:HQI 1 "const0_operand" "")))
737 (clobber (match_scratch:HQI 2 "=d,d"))]
738 "s390_match_ccmode(insn, CCSmode)"
741 icmy\t%2,<icm_lo>,%S0"
742 [(set_attr "op_type" "RS,RSY")
743 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
746 ; Compare (equality) instructions
748 (define_insn "*cmpdi_cct"
749 [(set (reg CC_REGNUM)
750 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
751 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
752 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
759 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
760 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
762 (define_insn "*cmpsi_cct"
763 [(set (reg CC_REGNUM)
764 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
765 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
766 "s390_match_ccmode (insn, CCTmode)"
774 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
775 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
777 ; Compare (signed) instructions
779 (define_insn "*cmpdi_ccs_sign"
780 [(set (reg CC_REGNUM)
781 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
783 (match_operand:DI 0 "register_operand" "d, d,d")))]
784 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
789 [(set_attr "op_type" "RRE,RXY,RIL")
790 (set_attr "z10prop" "z10_c,*,*")
791 (set_attr "type" "*,*,larl")])
795 (define_insn "*cmpsi_ccs_sign"
796 [(set (reg CC_REGNUM)
797 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
798 (match_operand:SI 0 "register_operand" "d,d,d")))]
799 "s390_match_ccmode(insn, CCSRmode)"
804 [(set_attr "op_type" "RX,RXY,RIL")
805 (set_attr "cpu_facility" "*,*,z10")
806 (set_attr "type" "*,*,larl")
807 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
809 (define_insn "*cmphi_ccs_z10"
810 [(set (reg CC_REGNUM)
811 (compare (match_operand:HI 0 "s_operand" "Q")
812 (match_operand:HI 1 "immediate_operand" "K")))]
813 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
815 [(set_attr "op_type" "SIL")
816 (set_attr "z196prop" "z196_cracked")])
818 (define_insn "*cmpdi_ccs_signhi_rl"
819 [(set (reg CC_REGNUM)
820 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
821 (match_operand:GPR 0 "register_operand" "d,d")))]
822 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
826 [(set_attr "op_type" "RXY,RIL")
827 (set_attr "type" "*,larl")])
829 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
830 (define_insn "*cmp<mode>_ccs"
831 [(set (reg CC_REGNUM)
832 (compare (match_operand:GPR 0 "nonimmediate_operand"
834 (match_operand:GPR 1 "general_operand"
836 "s390_match_ccmode(insn, CCSmode)"
845 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
846 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
847 (set_attr "type" "*,*,*,*,*,*,larl")
848 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
851 ; Compare (unsigned) instructions
853 (define_insn "*cmpsi_ccu_zerohi_rlsi"
854 [(set (reg CC_REGNUM)
855 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
856 "larl_operand" "X")))
857 (match_operand:SI 0 "register_operand" "d")))]
858 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
860 [(set_attr "op_type" "RIL")
861 (set_attr "type" "larl")
862 (set_attr "z10prop" "z10_super")])
865 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
866 [(set (reg CC_REGNUM)
867 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
868 "larl_operand" "X")))
869 (match_operand:GPR 0 "register_operand" "d")))]
870 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
872 [(set_attr "op_type" "RIL")
873 (set_attr "type" "larl")
874 (set_attr "z10prop" "z10_super")])
876 (define_insn "*cmpdi_ccu_zero"
877 [(set (reg CC_REGNUM)
878 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
880 (match_operand:DI 0 "register_operand" "d, d,d")))]
881 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
886 [(set_attr "op_type" "RRE,RXY,RIL")
887 (set_attr "cpu_facility" "*,*,z10")
888 (set_attr "type" "*,*,larl")
889 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
891 (define_insn "*cmpdi_ccu"
892 [(set (reg CC_REGNUM)
893 (compare (match_operand:DI 0 "nonimmediate_operand"
895 (match_operand:DI 1 "general_operand"
896 "d,Op,b,D,RT,BQ,Q")))]
897 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
906 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
907 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
908 (set_attr "type" "*,*,larl,*,*,*,*")
909 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
911 (define_insn "*cmpsi_ccu"
912 [(set (reg CC_REGNUM)
913 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
914 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
915 "s390_match_ccmode (insn, CCUmode)"
925 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
926 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
927 (set_attr "type" "*,*,larl,*,*,*,*,*")
928 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
930 (define_insn "*cmphi_ccu"
931 [(set (reg CC_REGNUM)
932 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
933 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
934 "s390_match_ccmode (insn, CCUmode)
935 && !register_operand (operands[1], HImode)"
942 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
943 (set_attr "cpu_facility" "*,*,z10,*,*")
944 (set_attr "z10prop" "*,*,z10_super,*,*")])
946 (define_insn "*cmpqi_ccu"
947 [(set (reg CC_REGNUM)
948 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
949 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
950 "s390_match_ccmode (insn, CCUmode)
951 && !register_operand (operands[1], QImode)"
959 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
960 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
963 ; Block compare (CLC) instruction patterns.
966 [(set (reg CC_REGNUM)
967 (compare (match_operand:BLK 0 "memory_operand" "Q")
968 (match_operand:BLK 1 "memory_operand" "Q")))
969 (use (match_operand 2 "const_int_operand" "n"))]
970 "s390_match_ccmode (insn, CCUmode)
971 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
972 "clc\t%O0(%2,%R0),%S1"
973 [(set_attr "op_type" "SS")])
976 [(set (reg CC_REGNUM)
977 (compare (match_operand 0 "memory_operand" "")
978 (match_operand 1 "memory_operand" "")))]
980 && s390_match_ccmode (insn, CCUmode)
981 && GET_MODE (operands[0]) == GET_MODE (operands[1])
982 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
984 [(set (match_dup 0) (match_dup 1))
985 (use (match_dup 2))])]
987 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
988 operands[0] = adjust_address (operands[0], BLKmode, 0);
989 operands[1] = adjust_address (operands[1], BLKmode, 0);
991 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
992 operands[0], operands[1]);
993 operands[0] = SET_DEST (PATTERN (curr_insn));
997 ; (TF|DF|SF|TD|DD|SD) instructions
999 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1000 (define_insn "*cmp<mode>_ccs_0"
1001 [(set (reg CC_REGNUM)
1002 (compare (match_operand:FP 0 "register_operand" "f")
1003 (match_operand:FP 1 "const0_operand" "")))]
1004 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1005 "lt<xde><bt>r\t%0,%0"
1006 [(set_attr "op_type" "RRE")
1007 (set_attr "type" "fsimp<mode>")])
1009 ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
1010 (define_insn "*cmp<mode>_ccs"
1011 [(set (reg CC_REGNUM)
1012 (compare (match_operand:FP 0 "register_operand" "f,f")
1013 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1014 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1018 [(set_attr "op_type" "RRE,RXE")
1019 (set_attr "type" "fsimp<mode>")])
1022 ; Compare and Branch instructions
1024 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1025 ; The following instructions do a complementary access of their second
1026 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1027 (define_insn "*cmp_and_br_signed_<mode>"
1029 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1030 [(match_operand:GPR 1 "register_operand" "d,d")
1031 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1032 (label_ref (match_operand 3 "" ""))
1034 (clobber (reg:CC CC_REGNUM))]
1035 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1037 if (get_attr_length (insn) == 6)
1038 return which_alternative ?
1039 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1041 return which_alternative ?
1042 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1044 [(set_attr "op_type" "RIE")
1045 (set_attr "type" "branch")
1046 (set_attr "z10prop" "z10_super_c,z10_super")
1047 (set (attr "length")
1048 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1049 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1050 ; 10 byte for cgr/jg
1052 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1053 ; The following instructions do a complementary access of their second
1054 ; operand (z10 only): clrj, clgrj, clr, clgr
1055 (define_insn "*cmp_and_br_unsigned_<mode>"
1057 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1058 [(match_operand:GPR 1 "register_operand" "d,d")
1059 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1060 (label_ref (match_operand 3 "" ""))
1062 (clobber (reg:CC CC_REGNUM))]
1063 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1065 if (get_attr_length (insn) == 6)
1066 return which_alternative ?
1067 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1069 return which_alternative ?
1070 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1072 [(set_attr "op_type" "RIE")
1073 (set_attr "type" "branch")
1074 (set_attr "z10prop" "z10_super_c,z10_super")
1075 (set (attr "length")
1076 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1077 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1078 ; 10 byte for clgr/jg
1080 ; And now the same two patterns as above but with a negated CC mask.
1082 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1083 ; The following instructions do a complementary access of their second
1084 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1085 (define_insn "*icmp_and_br_signed_<mode>"
1087 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1088 [(match_operand:GPR 1 "register_operand" "d,d")
1089 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1091 (label_ref (match_operand 3 "" ""))))
1092 (clobber (reg:CC CC_REGNUM))]
1093 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1095 if (get_attr_length (insn) == 6)
1096 return which_alternative ?
1097 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1099 return which_alternative ?
1100 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1102 [(set_attr "op_type" "RIE")
1103 (set_attr "type" "branch")
1104 (set_attr "z10prop" "z10_super_c,z10_super")
1105 (set (attr "length")
1106 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1107 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1108 ; 10 byte for cgr/jg
1110 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1111 ; The following instructions do a complementary access of their second
1112 ; operand (z10 only): clrj, clgrj, clr, clgr
1113 (define_insn "*icmp_and_br_unsigned_<mode>"
1115 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1116 [(match_operand:GPR 1 "register_operand" "d,d")
1117 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1119 (label_ref (match_operand 3 "" ""))))
1120 (clobber (reg:CC CC_REGNUM))]
1121 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1123 if (get_attr_length (insn) == 6)
1124 return which_alternative ?
1125 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1127 return which_alternative ?
1128 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1130 [(set_attr "op_type" "RIE")
1131 (set_attr "type" "branch")
1132 (set_attr "z10prop" "z10_super_c,z10_super")
1133 (set (attr "length")
1134 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1135 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1136 ; 10 byte for clgr/jg
1139 ;;- Move instructions.
1143 ; movti instruction pattern(s).
1146 (define_insn "movti"
1147 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1148 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1155 [(set_attr "op_type" "RSY,RSY,*,*")
1156 (set_attr "type" "lm,stm,*,*")])
1159 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1160 (match_operand:TI 1 "general_operand" ""))]
1161 "TARGET_ZARCH && reload_completed
1162 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1163 [(set (match_dup 2) (match_dup 4))
1164 (set (match_dup 3) (match_dup 5))]
1166 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1167 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1168 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1169 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1173 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1174 (match_operand:TI 1 "general_operand" ""))]
1175 "TARGET_ZARCH && reload_completed
1176 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1177 [(set (match_dup 2) (match_dup 4))
1178 (set (match_dup 3) (match_dup 5))]
1180 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1181 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1182 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1183 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1187 [(set (match_operand:TI 0 "register_operand" "")
1188 (match_operand:TI 1 "memory_operand" ""))]
1189 "TARGET_ZARCH && reload_completed
1190 && !s_operand (operands[1], VOIDmode)"
1191 [(set (match_dup 0) (match_dup 1))]
1193 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1194 addr = gen_lowpart (Pmode, addr);
1195 s390_load_address (addr, XEXP (operands[1], 0));
1196 operands[1] = replace_equiv_address (operands[1], addr);
1201 ; Patterns used for secondary reloads
1204 ; z10 provides move instructions accepting larl memory operands.
1205 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1206 ; These patterns are also used for unaligned SI and DI accesses.
1208 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1209 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1210 (match_operand:INTALL 1 "register_operand" "=d")
1211 (match_operand:P 2 "register_operand" "=&a")])]
1214 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1218 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1219 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1220 (match_operand:INTALL 1 "memory_operand" "")
1221 (match_operand:P 2 "register_operand" "=a")])]
1224 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1228 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1229 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1230 (match_operand:FPALL 1 "register_operand" "=d")
1231 (match_operand:P 2 "register_operand" "=&a")])]
1234 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1238 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1239 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1240 (match_operand:FPALL 1 "memory_operand" "")
1241 (match_operand:P 2 "register_operand" "=a")])]
1244 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1248 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1249 [(parallel [(match_operand:P 0 "register_operand" "=d")
1250 (match_operand:P 1 "larl_operand" "")
1251 (match_operand:P 2 "register_operand" "=a")])]
1254 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1258 ; Handles loading a PLUS (load address) expression
1260 (define_expand "reload<mode>_plus"
1261 [(parallel [(match_operand:P 0 "register_operand" "=a")
1262 (match_operand:P 1 "s390_plus_operand" "")
1263 (match_operand:P 2 "register_operand" "=&a")])]
1266 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1270 ; Handles assessing a non-offsetable memory address
1272 (define_expand "reload<mode>_nonoffmem_in"
1273 [(parallel [(match_operand 0 "register_operand" "")
1274 (match_operand 1 "" "")
1275 (match_operand:P 2 "register_operand" "=&a")])]
1278 gcc_assert (MEM_P (operands[1]));
1279 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1280 operands[1] = replace_equiv_address (operands[1], operands[2]);
1281 emit_move_insn (operands[0], operands[1]);
1285 (define_expand "reload<mode>_nonoffmem_out"
1286 [(parallel [(match_operand 0 "" "")
1287 (match_operand 1 "register_operand" "")
1288 (match_operand:P 2 "register_operand" "=&a")])]
1291 gcc_assert (MEM_P (operands[0]));
1292 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1293 operands[0] = replace_equiv_address (operands[0], operands[2]);
1294 emit_move_insn (operands[0], operands[1]);
1298 (define_expand "reload<mode>_PIC_addr"
1299 [(parallel [(match_operand 0 "register_operand" "=d")
1300 (match_operand 1 "larl_operand" "")
1301 (match_operand:P 2 "register_operand" "=a")])]
1304 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1305 emit_move_insn (operands[0], new_rtx);
1309 ; movdi instruction pattern(s).
1312 (define_expand "movdi"
1313 [(set (match_operand:DI 0 "general_operand" "")
1314 (match_operand:DI 1 "general_operand" ""))]
1317 /* Handle symbolic constants. */
1319 && (SYMBOLIC_CONST (operands[1])
1320 || (GET_CODE (operands[1]) == PLUS
1321 && XEXP (operands[1], 0) == pic_offset_table_rtx
1322 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1323 emit_symbolic_move (operands);
1326 (define_insn "*movdi_larl"
1327 [(set (match_operand:DI 0 "register_operand" "=d")
1328 (match_operand:DI 1 "larl_operand" "X"))]
1330 && !FP_REG_P (operands[0])"
1332 [(set_attr "op_type" "RIL")
1333 (set_attr "type" "larl")
1334 (set_attr "z10prop" "z10_super_A1")])
1336 (define_insn "*movdi_64"
1337 [(set (match_operand:DI 0 "nonimmediate_operand"
1338 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1339 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1340 (match_operand:DI 1 "general_operand"
1341 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1342 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1371 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1372 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1373 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1374 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1376 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1377 z10,*,*,*,*,*,longdisp,*,longdisp,
1379 (set_attr "z10prop" "z10_fwd_A1,
1408 [(set (match_operand:DI 0 "register_operand" "")
1409 (match_operand:DI 1 "register_operand" ""))]
1410 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1411 [(set (match_dup 2) (match_dup 3))
1412 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1413 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1414 "operands[2] = gen_lowpart (SImode, operands[0]);
1415 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1418 [(set (match_operand:DI 0 "register_operand" "")
1419 (match_operand:DI 1 "register_operand" ""))]
1420 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1421 && dead_or_set_p (insn, operands[1])"
1422 [(set (match_dup 3) (match_dup 2))
1423 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1424 (set (match_dup 4) (match_dup 2))]
1425 "operands[2] = gen_lowpart (SImode, operands[1]);
1426 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1429 [(set (match_operand:DI 0 "register_operand" "")
1430 (match_operand:DI 1 "register_operand" ""))]
1431 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1432 && !dead_or_set_p (insn, operands[1])"
1433 [(set (match_dup 3) (match_dup 2))
1434 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1435 (set (match_dup 4) (match_dup 2))
1436 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1437 "operands[2] = gen_lowpart (SImode, operands[1]);
1438 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1440 (define_insn "*movdi_31"
1441 [(set (match_operand:DI 0 "nonimmediate_operand"
1442 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1443 (match_operand:DI 1 "general_operand"
1444 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1459 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1460 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1461 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1463 ; For a load from a symbol ref we can use one of the target registers
1464 ; together with larl to load the address.
1466 [(set (match_operand:DI 0 "register_operand" "")
1467 (match_operand:DI 1 "memory_operand" ""))]
1468 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1469 && larl_operand (XEXP (operands[1], 0), SImode)"
1470 [(set (match_dup 2) (match_dup 3))
1471 (set (match_dup 0) (match_dup 1))]
1473 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1474 operands[3] = XEXP (operands[1], 0);
1475 operands[1] = replace_equiv_address (operands[1], operands[2]);
1479 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1480 (match_operand:DI 1 "general_operand" ""))]
1481 "!TARGET_ZARCH && reload_completed
1482 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1483 [(set (match_dup 2) (match_dup 4))
1484 (set (match_dup 3) (match_dup 5))]
1486 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1487 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1488 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1489 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1493 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1494 (match_operand:DI 1 "general_operand" ""))]
1495 "!TARGET_ZARCH && reload_completed
1496 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1497 [(set (match_dup 2) (match_dup 4))
1498 (set (match_dup 3) (match_dup 5))]
1500 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1501 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1502 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1503 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1507 [(set (match_operand:DI 0 "register_operand" "")
1508 (match_operand:DI 1 "memory_operand" ""))]
1509 "!TARGET_ZARCH && reload_completed
1510 && !FP_REG_P (operands[0])
1511 && !s_operand (operands[1], VOIDmode)"
1512 [(set (match_dup 0) (match_dup 1))]
1514 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1515 s390_load_address (addr, XEXP (operands[1], 0));
1516 operands[1] = replace_equiv_address (operands[1], addr);
1520 [(set (match_operand:DI 0 "register_operand" "")
1521 (mem:DI (match_operand 1 "address_operand" "")))]
1523 && !FP_REG_P (operands[0])
1524 && GET_CODE (operands[1]) == SYMBOL_REF
1525 && CONSTANT_POOL_ADDRESS_P (operands[1])
1526 && get_pool_mode (operands[1]) == DImode
1527 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1528 [(set (match_dup 0) (match_dup 2))]
1529 "operands[2] = get_pool_constant (operands[1]);")
1531 (define_insn "*la_64"
1532 [(set (match_operand:DI 0 "register_operand" "=d,d")
1533 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1538 [(set_attr "op_type" "RX,RXY")
1539 (set_attr "type" "la")
1540 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1544 [(set (match_operand:DI 0 "register_operand" "")
1545 (match_operand:QI 1 "address_operand" ""))
1546 (clobber (reg:CC CC_REGNUM))])]
1548 && preferred_la_operand_p (operands[1], const0_rtx)"
1549 [(set (match_dup 0) (match_dup 1))]
1553 [(set (match_operand:DI 0 "register_operand" "")
1554 (match_operand:DI 1 "register_operand" ""))
1557 (plus:DI (match_dup 0)
1558 (match_operand:DI 2 "nonmemory_operand" "")))
1559 (clobber (reg:CC CC_REGNUM))])]
1561 && !reg_overlap_mentioned_p (operands[0], operands[2])
1562 && preferred_la_operand_p (operands[1], operands[2])"
1563 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1567 ; movsi instruction pattern(s).
1570 (define_expand "movsi"
1571 [(set (match_operand:SI 0 "general_operand" "")
1572 (match_operand:SI 1 "general_operand" ""))]
1575 /* Handle symbolic constants. */
1577 && (SYMBOLIC_CONST (operands[1])
1578 || (GET_CODE (operands[1]) == PLUS
1579 && XEXP (operands[1], 0) == pic_offset_table_rtx
1580 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1581 emit_symbolic_move (operands);
1584 (define_insn "*movsi_larl"
1585 [(set (match_operand:SI 0 "register_operand" "=d")
1586 (match_operand:SI 1 "larl_operand" "X"))]
1587 "!TARGET_64BIT && TARGET_CPU_ZARCH
1588 && !FP_REG_P (operands[0])"
1590 [(set_attr "op_type" "RIL")
1591 (set_attr "type" "larl")
1592 (set_attr "z10prop" "z10_fwd_A1")])
1594 (define_insn "*movsi_zarch"
1595 [(set (match_operand:SI 0 "nonimmediate_operand"
1596 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1597 (match_operand:SI 1 "general_operand"
1598 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1623 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1624 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1625 (set_attr "type" "*,
1647 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1648 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1649 (set_attr "z10prop" "z10_fwd_A1,
1672 (define_insn "*movsi_esa"
1673 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1674 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1688 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1689 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1690 (set_attr "z10prop" "z10_fwd_A1,
1704 [(set (match_operand:SI 0 "register_operand" "")
1705 (mem:SI (match_operand 1 "address_operand" "")))]
1706 "!FP_REG_P (operands[0])
1707 && GET_CODE (operands[1]) == SYMBOL_REF
1708 && CONSTANT_POOL_ADDRESS_P (operands[1])
1709 && get_pool_mode (operands[1]) == SImode
1710 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1711 [(set (match_dup 0) (match_dup 2))]
1712 "operands[2] = get_pool_constant (operands[1]);")
1714 (define_insn "*la_31"
1715 [(set (match_operand:SI 0 "register_operand" "=d,d")
1716 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1717 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1721 [(set_attr "op_type" "RX,RXY")
1722 (set_attr "type" "la")
1723 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1727 [(set (match_operand:SI 0 "register_operand" "")
1728 (match_operand:QI 1 "address_operand" ""))
1729 (clobber (reg:CC CC_REGNUM))])]
1731 && preferred_la_operand_p (operands[1], const0_rtx)"
1732 [(set (match_dup 0) (match_dup 1))]
1736 [(set (match_operand:SI 0 "register_operand" "")
1737 (match_operand:SI 1 "register_operand" ""))
1740 (plus:SI (match_dup 0)
1741 (match_operand:SI 2 "nonmemory_operand" "")))
1742 (clobber (reg:CC CC_REGNUM))])]
1744 && !reg_overlap_mentioned_p (operands[0], operands[2])
1745 && preferred_la_operand_p (operands[1], operands[2])"
1746 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1749 (define_insn "*la_31_and"
1750 [(set (match_operand:SI 0 "register_operand" "=d,d")
1751 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1752 (const_int 2147483647)))]
1757 [(set_attr "op_type" "RX,RXY")
1758 (set_attr "type" "la")
1759 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1761 (define_insn_and_split "*la_31_and_cc"
1762 [(set (match_operand:SI 0 "register_operand" "=d")
1763 (and:SI (match_operand:QI 1 "address_operand" "p")
1764 (const_int 2147483647)))
1765 (clobber (reg:CC CC_REGNUM))]
1768 "&& reload_completed"
1770 (and:SI (match_dup 1) (const_int 2147483647)))]
1772 [(set_attr "op_type" "RX")
1773 (set_attr "type" "la")])
1775 (define_insn "force_la_31"
1776 [(set (match_operand:SI 0 "register_operand" "=d,d")
1777 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1778 (use (const_int 0))]
1783 [(set_attr "op_type" "RX")
1784 (set_attr "type" "la")
1785 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1788 ; movhi instruction pattern(s).
1791 (define_expand "movhi"
1792 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1793 (match_operand:HI 1 "general_operand" ""))]
1796 /* Make it explicit that loading a register from memory
1797 always sign-extends (at least) to SImode. */
1798 if (optimize && can_create_pseudo_p ()
1799 && register_operand (operands[0], VOIDmode)
1800 && GET_CODE (operands[1]) == MEM)
1802 rtx tmp = gen_reg_rtx (SImode);
1803 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1804 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1805 operands[1] = gen_lowpart (HImode, tmp);
1809 (define_insn "*movhi"
1810 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1811 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1823 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1824 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1825 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1826 (set_attr "z10prop" "z10_fr_E1,
1837 [(set (match_operand:HI 0 "register_operand" "")
1838 (mem:HI (match_operand 1 "address_operand" "")))]
1839 "GET_CODE (operands[1]) == SYMBOL_REF
1840 && CONSTANT_POOL_ADDRESS_P (operands[1])
1841 && get_pool_mode (operands[1]) == HImode
1842 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1843 [(set (match_dup 0) (match_dup 2))]
1844 "operands[2] = get_pool_constant (operands[1]);")
1847 ; movqi instruction pattern(s).
1850 (define_expand "movqi"
1851 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1852 (match_operand:QI 1 "general_operand" ""))]
1855 /* On z/Architecture, zero-extending from memory to register
1856 is just as fast as a QImode load. */
1857 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1858 && register_operand (operands[0], VOIDmode)
1859 && GET_CODE (operands[1]) == MEM)
1861 rtx tmp = gen_reg_rtx (DImode);
1862 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1863 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1864 operands[1] = gen_lowpart (QImode, tmp);
1868 (define_insn "*movqi"
1869 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1870 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1882 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1883 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1884 (set_attr "z10prop" "z10_fr_E1,
1895 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1896 (mem:QI (match_operand 1 "address_operand" "")))]
1897 "GET_CODE (operands[1]) == SYMBOL_REF
1898 && CONSTANT_POOL_ADDRESS_P (operands[1])
1899 && get_pool_mode (operands[1]) == QImode
1900 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1901 [(set (match_dup 0) (match_dup 2))]
1902 "operands[2] = get_pool_constant (operands[1]);")
1905 ; movstrictqi instruction pattern(s).
1908 (define_insn "*movstrictqi"
1909 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1910 (match_operand:QI 1 "memory_operand" "R,T"))]
1915 [(set_attr "op_type" "RX,RXY")
1916 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1919 ; movstricthi instruction pattern(s).
1922 (define_insn "*movstricthi"
1923 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1924 (match_operand:HI 1 "memory_operand" "Q,S"))
1925 (clobber (reg:CC CC_REGNUM))]
1930 [(set_attr "op_type" "RS,RSY")
1931 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1934 ; movstrictsi instruction pattern(s).
1937 (define_insn "movstrictsi"
1938 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1939 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1946 [(set_attr "op_type" "RR,RX,RXY,RRE")
1947 (set_attr "type" "lr,load,load,*")
1948 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1951 ; mov(tf|td) instruction pattern(s).
1954 (define_expand "mov<mode>"
1955 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1956 (match_operand:TD_TF 1 "general_operand" ""))]
1960 (define_insn "*mov<mode>_64"
1961 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1962 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1973 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1974 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
1975 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
1977 (define_insn "*mov<mode>_31"
1978 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1979 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1986 [(set_attr "op_type" "RRE,RRE,*,*")
1987 (set_attr "type" "fsimptf,fsimptf,*,*")
1988 (set_attr "cpu_facility" "z196,*,*,*")])
1990 ; TFmode in GPRs splitters
1993 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1994 (match_operand:TD_TF 1 "general_operand" ""))]
1995 "TARGET_ZARCH && reload_completed
1996 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1997 [(set (match_dup 2) (match_dup 4))
1998 (set (match_dup 3) (match_dup 5))]
2000 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2001 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2002 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2003 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2007 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2008 (match_operand:TD_TF 1 "general_operand" ""))]
2009 "TARGET_ZARCH && reload_completed
2010 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2011 [(set (match_dup 2) (match_dup 4))
2012 (set (match_dup 3) (match_dup 5))]
2014 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2015 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2016 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2017 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2021 [(set (match_operand:TD_TF 0 "register_operand" "")
2022 (match_operand:TD_TF 1 "memory_operand" ""))]
2023 "TARGET_ZARCH && reload_completed
2024 && !FP_REG_P (operands[0])
2025 && !s_operand (operands[1], VOIDmode)"
2026 [(set (match_dup 0) (match_dup 1))]
2028 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2029 s390_load_address (addr, XEXP (operands[1], 0));
2030 operands[1] = replace_equiv_address (operands[1], addr);
2033 ; TFmode in BFPs splitters
2036 [(set (match_operand:TD_TF 0 "register_operand" "")
2037 (match_operand:TD_TF 1 "memory_operand" ""))]
2038 "reload_completed && offsettable_memref_p (operands[1])
2039 && FP_REG_P (operands[0])"
2040 [(set (match_dup 2) (match_dup 4))
2041 (set (match_dup 3) (match_dup 5))]
2043 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2045 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2047 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2048 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2052 [(set (match_operand:TD_TF 0 "memory_operand" "")
2053 (match_operand:TD_TF 1 "register_operand" ""))]
2054 "reload_completed && offsettable_memref_p (operands[0])
2055 && FP_REG_P (operands[1])"
2056 [(set (match_dup 2) (match_dup 4))
2057 (set (match_dup 3) (match_dup 5))]
2059 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2060 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2061 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2063 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2068 ; mov(df|dd) instruction pattern(s).
2071 (define_expand "mov<mode>"
2072 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2073 (match_operand:DD_DF 1 "general_operand" ""))]
2077 (define_insn "*mov<mode>_64dfp"
2078 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2079 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2080 (match_operand:DD_DF 1 "general_operand"
2081 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2096 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2097 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2098 fstoredf,fstoredf,*,lr,load,store")
2099 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2100 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2102 (define_insn "*mov<mode>_64"
2103 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2104 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2117 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2118 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2119 fstore<mode>,fstore<mode>,*,lr,load,store")
2120 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2121 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2123 (define_insn "*mov<mode>_31"
2124 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2125 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2126 (match_operand:DD_DF 1 "general_operand"
2127 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2142 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2143 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2144 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2145 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2148 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2149 (match_operand:DD_DF 1 "general_operand" ""))]
2150 "!TARGET_ZARCH && reload_completed
2151 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2152 [(set (match_dup 2) (match_dup 4))
2153 (set (match_dup 3) (match_dup 5))]
2155 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2156 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2157 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2158 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2162 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2163 (match_operand:DD_DF 1 "general_operand" ""))]
2164 "!TARGET_ZARCH && reload_completed
2165 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2166 [(set (match_dup 2) (match_dup 4))
2167 (set (match_dup 3) (match_dup 5))]
2169 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2170 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2171 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2172 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2176 [(set (match_operand:DD_DF 0 "register_operand" "")
2177 (match_operand:DD_DF 1 "memory_operand" ""))]
2178 "!TARGET_ZARCH && reload_completed
2179 && !FP_REG_P (operands[0])
2180 && !s_operand (operands[1], VOIDmode)"
2181 [(set (match_dup 0) (match_dup 1))]
2183 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2184 s390_load_address (addr, XEXP (operands[1], 0));
2185 operands[1] = replace_equiv_address (operands[1], addr);
2189 ; mov(sf|sd) instruction pattern(s).
2192 (define_insn "mov<mode>"
2193 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2194 "=f,f,f,f,R,T,d,d,d,d,R,T")
2195 (match_operand:SD_SF 1 "general_operand"
2196 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2211 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2212 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2213 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2214 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2215 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2218 ; movcc instruction pattern
2221 (define_insn "movcc"
2222 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2223 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2233 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2234 (set_attr "type" "lr,*,*,store,store,load,load")
2235 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2236 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2239 ; Block move (MVC) patterns.
2243 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2244 (match_operand:BLK 1 "memory_operand" "Q"))
2245 (use (match_operand 2 "const_int_operand" "n"))]
2246 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2247 "mvc\t%O0(%2,%R0),%S1"
2248 [(set_attr "op_type" "SS")])
2250 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2251 ; order to have it implemented with mvc.
2254 [(set (match_operand:QI 0 "memory_operand" "")
2255 (match_operand:QI 1 "memory_operand" ""))]
2258 [(set (match_dup 0) (match_dup 1))
2259 (use (const_int 1))])]
2261 operands[0] = adjust_address (operands[0], BLKmode, 0);
2262 operands[1] = adjust_address (operands[1], BLKmode, 0);
2268 [(set (match_operand:BLK 0 "memory_operand" "")
2269 (match_operand:BLK 1 "memory_operand" ""))
2270 (use (match_operand 2 "const_int_operand" ""))])
2272 [(set (match_operand:BLK 3 "memory_operand" "")
2273 (match_operand:BLK 4 "memory_operand" ""))
2274 (use (match_operand 5 "const_int_operand" ""))])]
2275 "s390_offset_p (operands[0], operands[3], operands[2])
2276 && s390_offset_p (operands[1], operands[4], operands[2])
2277 && !s390_overlap_p (operands[0], operands[1],
2278 INTVAL (operands[2]) + INTVAL (operands[5]))
2279 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2281 [(set (match_dup 6) (match_dup 7))
2282 (use (match_dup 8))])]
2283 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2284 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2285 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2289 ; load_multiple pattern(s).
2291 ; ??? Due to reload problems with replacing registers inside match_parallel
2292 ; we currently support load_multiple/store_multiple only after reload.
2295 (define_expand "load_multiple"
2296 [(match_par_dup 3 [(set (match_operand 0 "" "")
2297 (match_operand 1 "" ""))
2298 (use (match_operand 2 "" ""))])]
2301 enum machine_mode mode;
2307 /* Support only loading a constant number of fixed-point registers from
2308 memory and only bother with this if more than two */
2309 if (GET_CODE (operands[2]) != CONST_INT
2310 || INTVAL (operands[2]) < 2
2311 || INTVAL (operands[2]) > 16
2312 || GET_CODE (operands[1]) != MEM
2313 || GET_CODE (operands[0]) != REG
2314 || REGNO (operands[0]) >= 16)
2317 count = INTVAL (operands[2]);
2318 regno = REGNO (operands[0]);
2319 mode = GET_MODE (operands[0]);
2320 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2323 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2324 if (!can_create_pseudo_p ())
2326 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2328 from = XEXP (operands[1], 0);
2331 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2332 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2333 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2335 from = XEXP (XEXP (operands[1], 0), 0);
2336 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2343 from = force_reg (Pmode, XEXP (operands[1], 0));
2347 for (i = 0; i < count; i++)
2348 XVECEXP (operands[3], 0, i)
2349 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2350 change_address (operands[1], mode,
2351 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2354 (define_insn "*load_multiple_di"
2355 [(match_parallel 0 "load_multiple_operation"
2356 [(set (match_operand:DI 1 "register_operand" "=r")
2357 (match_operand:DI 2 "s_operand" "QS"))])]
2358 "reload_completed && TARGET_ZARCH"
2360 int words = XVECLEN (operands[0], 0);
2361 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2362 return "lmg\t%1,%0,%S2";
2364 [(set_attr "op_type" "RSY")
2365 (set_attr "type" "lm")])
2367 (define_insn "*load_multiple_si"
2368 [(match_parallel 0 "load_multiple_operation"
2369 [(set (match_operand:SI 1 "register_operand" "=r,r")
2370 (match_operand:SI 2 "s_operand" "Q,S"))])]
2373 int words = XVECLEN (operands[0], 0);
2374 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2375 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2377 [(set_attr "op_type" "RS,RSY")
2378 (set_attr "type" "lm")])
2381 ; store multiple pattern(s).
2384 (define_expand "store_multiple"
2385 [(match_par_dup 3 [(set (match_operand 0 "" "")
2386 (match_operand 1 "" ""))
2387 (use (match_operand 2 "" ""))])]
2390 enum machine_mode mode;
2396 /* Support only storing a constant number of fixed-point registers to
2397 memory and only bother with this if more than two. */
2398 if (GET_CODE (operands[2]) != CONST_INT
2399 || INTVAL (operands[2]) < 2
2400 || INTVAL (operands[2]) > 16
2401 || GET_CODE (operands[0]) != MEM
2402 || GET_CODE (operands[1]) != REG
2403 || REGNO (operands[1]) >= 16)
2406 count = INTVAL (operands[2]);
2407 regno = REGNO (operands[1]);
2408 mode = GET_MODE (operands[1]);
2409 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2412 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2414 if (!can_create_pseudo_p ())
2416 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2418 to = XEXP (operands[0], 0);
2421 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2422 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2423 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2425 to = XEXP (XEXP (operands[0], 0), 0);
2426 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2433 to = force_reg (Pmode, XEXP (operands[0], 0));
2437 for (i = 0; i < count; i++)
2438 XVECEXP (operands[3], 0, i)
2439 = gen_rtx_SET (VOIDmode,
2440 change_address (operands[0], mode,
2441 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2442 gen_rtx_REG (mode, regno + i));
2445 (define_insn "*store_multiple_di"
2446 [(match_parallel 0 "store_multiple_operation"
2447 [(set (match_operand:DI 1 "s_operand" "=QS")
2448 (match_operand:DI 2 "register_operand" "r"))])]
2449 "reload_completed && TARGET_ZARCH"
2451 int words = XVECLEN (operands[0], 0);
2452 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2453 return "stmg\t%2,%0,%S1";
2455 [(set_attr "op_type" "RSY")
2456 (set_attr "type" "stm")])
2459 (define_insn "*store_multiple_si"
2460 [(match_parallel 0 "store_multiple_operation"
2461 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2462 (match_operand:SI 2 "register_operand" "r,r"))])]
2465 int words = XVECLEN (operands[0], 0);
2466 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2467 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2469 [(set_attr "op_type" "RS,RSY")
2470 (set_attr "type" "stm")])
2473 ;; String instructions.
2476 (define_insn "*execute_rl"
2477 [(match_parallel 0 ""
2478 [(unspec [(match_operand 1 "register_operand" "a")
2479 (match_operand 2 "" "")
2480 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2481 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2482 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2484 [(set_attr "op_type" "RIL")
2485 (set_attr "type" "cs")])
2487 (define_insn "*execute"
2488 [(match_parallel 0 ""
2489 [(unspec [(match_operand 1 "register_operand" "a")
2490 (match_operand:BLK 2 "memory_operand" "R")
2491 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2492 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2493 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2495 [(set_attr "op_type" "RX")
2496 (set_attr "type" "cs")])
2500 ; strlenM instruction pattern(s).
2503 (define_expand "strlen<mode>"
2504 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2507 (unspec:P [(const_int 0)
2508 (match_operand:BLK 1 "memory_operand" "")
2510 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2511 (clobber (scratch:P))
2512 (clobber (reg:CC CC_REGNUM))])
2514 [(set (match_operand:P 0 "register_operand" "")
2515 (minus:P (match_dup 4) (match_dup 5)))
2516 (clobber (reg:CC CC_REGNUM))])]
2519 operands[4] = gen_reg_rtx (Pmode);
2520 operands[5] = gen_reg_rtx (Pmode);
2521 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2522 operands[1] = replace_equiv_address (operands[1], operands[5]);
2525 (define_insn "*strlen<mode>"
2526 [(set (match_operand:P 0 "register_operand" "=a")
2527 (unspec:P [(match_operand:P 2 "general_operand" "0")
2528 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2530 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2531 (clobber (match_scratch:P 1 "=a"))
2532 (clobber (reg:CC CC_REGNUM))]
2534 "srst\t%0,%1\;jo\t.-4"
2535 [(set_attr "length" "8")
2536 (set_attr "type" "vs")])
2539 ; cmpstrM instruction pattern(s).
2542 (define_expand "cmpstrsi"
2543 [(set (reg:SI 0) (const_int 0))
2545 [(clobber (match_operand 3 "" ""))
2546 (clobber (match_dup 4))
2547 (set (reg:CCU CC_REGNUM)
2548 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2549 (match_operand:BLK 2 "memory_operand" "")))
2552 [(set (match_operand:SI 0 "register_operand" "=d")
2553 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2554 (clobber (reg:CC CC_REGNUM))])]
2557 /* As the result of CMPINT is inverted compared to what we need,
2558 we have to swap the operands. */
2559 rtx op1 = operands[2];
2560 rtx op2 = operands[1];
2561 rtx addr1 = gen_reg_rtx (Pmode);
2562 rtx addr2 = gen_reg_rtx (Pmode);
2564 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2565 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2566 operands[1] = replace_equiv_address_nv (op1, addr1);
2567 operands[2] = replace_equiv_address_nv (op2, addr2);
2568 operands[3] = addr1;
2569 operands[4] = addr2;
2572 (define_insn "*cmpstr<mode>"
2573 [(clobber (match_operand:P 0 "register_operand" "=d"))
2574 (clobber (match_operand:P 1 "register_operand" "=d"))
2575 (set (reg:CCU CC_REGNUM)
2576 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2577 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2580 "clst\t%0,%1\;jo\t.-4"
2581 [(set_attr "length" "8")
2582 (set_attr "type" "vs")])
2585 ; movstr instruction pattern.
2588 (define_expand "movstr"
2589 [(set (reg:SI 0) (const_int 0))
2591 [(clobber (match_dup 3))
2592 (set (match_operand:BLK 1 "memory_operand" "")
2593 (match_operand:BLK 2 "memory_operand" ""))
2594 (set (match_operand 0 "register_operand" "")
2595 (unspec [(match_dup 1)
2597 (reg:SI 0)] UNSPEC_MVST))
2598 (clobber (reg:CC CC_REGNUM))])]
2601 rtx addr1 = gen_reg_rtx (Pmode);
2602 rtx addr2 = gen_reg_rtx (Pmode);
2604 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2605 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2606 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2607 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2608 operands[3] = addr2;
2611 (define_insn "*movstr"
2612 [(clobber (match_operand:P 2 "register_operand" "=d"))
2613 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2614 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2615 (set (match_operand:P 0 "register_operand" "=d")
2616 (unspec [(mem:BLK (match_dup 1))
2617 (mem:BLK (match_dup 3))
2618 (reg:SI 0)] UNSPEC_MVST))
2619 (clobber (reg:CC CC_REGNUM))]
2621 "mvst\t%1,%2\;jo\t.-4"
2622 [(set_attr "length" "8")
2623 (set_attr "type" "vs")])
2627 ; movmemM instruction pattern(s).
2630 (define_expand "movmem<mode>"
2631 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2632 (match_operand:BLK 1 "memory_operand" "")) ; source
2633 (use (match_operand:GPR 2 "general_operand" "")) ; count
2634 (match_operand 3 "" "")]
2636 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2638 ; Move a block that is up to 256 bytes in length.
2639 ; The block length is taken as (operands[2] % 256) + 1.
2641 (define_expand "movmem_short"
2643 [(set (match_operand:BLK 0 "memory_operand" "")
2644 (match_operand:BLK 1 "memory_operand" ""))
2645 (use (match_operand 2 "nonmemory_operand" ""))
2646 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2647 (clobber (match_dup 3))])]
2649 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2651 (define_insn "*movmem_short"
2652 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2653 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2654 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2655 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2656 (clobber (match_scratch 4 "=X,X,X,&a"))]
2657 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2658 && GET_MODE (operands[4]) == Pmode"
2660 [(set_attr "type" "cs")
2661 (set_attr "cpu_facility" "*,*,z10,*")])
2664 [(set (match_operand:BLK 0 "memory_operand" "")
2665 (match_operand:BLK 1 "memory_operand" ""))
2666 (use (match_operand 2 "const_int_operand" ""))
2667 (use (match_operand 3 "immediate_operand" ""))
2668 (clobber (scratch))]
2671 [(set (match_dup 0) (match_dup 1))
2672 (use (match_dup 2))])]
2673 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2676 [(set (match_operand:BLK 0 "memory_operand" "")
2677 (match_operand:BLK 1 "memory_operand" ""))
2678 (use (match_operand 2 "register_operand" ""))
2679 (use (match_operand 3 "memory_operand" ""))
2680 (clobber (scratch))]
2683 [(unspec [(match_dup 2) (match_dup 3)
2684 (const_int 0)] UNSPEC_EXECUTE)
2685 (set (match_dup 0) (match_dup 1))
2686 (use (const_int 1))])]
2690 [(set (match_operand:BLK 0 "memory_operand" "")
2691 (match_operand:BLK 1 "memory_operand" ""))
2692 (use (match_operand 2 "register_operand" ""))
2693 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2694 (clobber (scratch))]
2695 "TARGET_Z10 && reload_completed"
2697 [(unspec [(match_dup 2) (const_int 0)
2698 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2699 (set (match_dup 0) (match_dup 1))
2700 (use (const_int 1))])]
2701 "operands[3] = gen_label_rtx ();")
2704 [(set (match_operand:BLK 0 "memory_operand" "")
2705 (match_operand:BLK 1 "memory_operand" ""))
2706 (use (match_operand 2 "register_operand" ""))
2707 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2708 (clobber (match_operand 3 "register_operand" ""))]
2709 "reload_completed && TARGET_CPU_ZARCH"
2710 [(set (match_dup 3) (label_ref (match_dup 4)))
2712 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2713 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2714 (set (match_dup 0) (match_dup 1))
2715 (use (const_int 1))])]
2716 "operands[4] = gen_label_rtx ();")
2718 ; Move a block of arbitrary length.
2720 (define_expand "movmem_long"
2722 [(clobber (match_dup 2))
2723 (clobber (match_dup 3))
2724 (set (match_operand:BLK 0 "memory_operand" "")
2725 (match_operand:BLK 1 "memory_operand" ""))
2726 (use (match_operand 2 "general_operand" ""))
2728 (clobber (reg:CC CC_REGNUM))])]
2731 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2732 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2733 rtx reg0 = gen_reg_rtx (dreg_mode);
2734 rtx reg1 = gen_reg_rtx (dreg_mode);
2735 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2736 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2737 rtx len0 = gen_lowpart (Pmode, reg0);
2738 rtx len1 = gen_lowpart (Pmode, reg1);
2740 emit_clobber (reg0);
2741 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2742 emit_move_insn (len0, operands[2]);
2744 emit_clobber (reg1);
2745 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2746 emit_move_insn (len1, operands[2]);
2748 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2749 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2754 (define_insn "*movmem_long"
2755 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2756 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2757 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2758 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2761 (clobber (reg:CC CC_REGNUM))]
2762 "TARGET_64BIT || !TARGET_ZARCH"
2763 "mvcle\t%0,%1,0\;jo\t.-4"
2764 [(set_attr "length" "8")
2765 (set_attr "type" "vs")])
2767 (define_insn "*movmem_long_31z"
2768 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2769 (clobber (match_operand:TI 1 "register_operand" "=d"))
2770 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2771 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2774 (clobber (reg:CC CC_REGNUM))]
2775 "!TARGET_64BIT && TARGET_ZARCH"
2776 "mvcle\t%0,%1,0\;jo\t.-4"
2777 [(set_attr "length" "8")
2778 (set_attr "type" "vs")])
2785 (define_expand "signbit<mode>2"
2786 [(set (reg:CCZ CC_REGNUM)
2787 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2790 (set (match_operand:SI 0 "register_operand" "=d")
2791 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2794 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2797 (define_expand "isinf<mode>2"
2798 [(set (reg:CCZ CC_REGNUM)
2799 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2802 (set (match_operand:SI 0 "register_operand" "=d")
2803 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2806 operands[2] = GEN_INT (S390_TDC_INFINITY);
2809 ; This insn is used to generate all variants of the Test Data Class
2810 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2811 ; is the register to be tested and the second one is the bit mask
2812 ; specifying the required test(s).
2814 (define_insn "*TDC_insn_<mode>"
2815 [(set (reg:CCZ CC_REGNUM)
2816 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2817 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2819 "t<_d>c<xde><bt>\t%0,%1"
2820 [(set_attr "op_type" "RXE")
2821 (set_attr "type" "fsimp<mode>")])
2823 (define_insn_and_split "*ccz_to_int"
2824 [(set (match_operand:SI 0 "register_operand" "=d")
2825 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2826 UNSPEC_CCZ_TO_INT))]
2830 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2834 ; setmemM instruction pattern(s).
2837 (define_expand "setmem<mode>"
2838 [(set (match_operand:BLK 0 "memory_operand" "")
2839 (match_operand:QI 2 "general_operand" ""))
2840 (use (match_operand:GPR 1 "general_operand" ""))
2841 (match_operand 3 "" "")]
2843 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2845 ; Clear a block that is up to 256 bytes in length.
2846 ; The block length is taken as (operands[1] % 256) + 1.
2848 (define_expand "clrmem_short"
2850 [(set (match_operand:BLK 0 "memory_operand" "")
2852 (use (match_operand 1 "nonmemory_operand" ""))
2853 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2854 (clobber (match_dup 2))
2855 (clobber (reg:CC CC_REGNUM))])]
2857 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2859 (define_insn "*clrmem_short"
2860 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2862 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2863 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2864 (clobber (match_scratch 3 "=X,X,X,&a"))
2865 (clobber (reg:CC CC_REGNUM))]
2866 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2867 && GET_MODE (operands[3]) == Pmode"
2869 [(set_attr "type" "cs")
2870 (set_attr "cpu_facility" "*,*,z10,*")])
2873 [(set (match_operand:BLK 0 "memory_operand" "")
2875 (use (match_operand 1 "const_int_operand" ""))
2876 (use (match_operand 2 "immediate_operand" ""))
2878 (clobber (reg:CC CC_REGNUM))]
2881 [(set (match_dup 0) (const_int 0))
2883 (clobber (reg:CC CC_REGNUM))])]
2884 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2887 [(set (match_operand:BLK 0 "memory_operand" "")
2889 (use (match_operand 1 "register_operand" ""))
2890 (use (match_operand 2 "memory_operand" ""))
2892 (clobber (reg:CC CC_REGNUM))]
2895 [(unspec [(match_dup 1) (match_dup 2)
2896 (const_int 0)] UNSPEC_EXECUTE)
2897 (set (match_dup 0) (const_int 0))
2899 (clobber (reg:CC CC_REGNUM))])]
2903 [(set (match_operand:BLK 0 "memory_operand" "")
2905 (use (match_operand 1 "register_operand" ""))
2906 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2908 (clobber (reg:CC CC_REGNUM))]
2909 "TARGET_Z10 && reload_completed"
2911 [(unspec [(match_dup 1) (const_int 0)
2912 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2913 (set (match_dup 0) (const_int 0))
2915 (clobber (reg:CC CC_REGNUM))])]
2916 "operands[3] = gen_label_rtx ();")
2919 [(set (match_operand:BLK 0 "memory_operand" "")
2921 (use (match_operand 1 "register_operand" ""))
2922 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2923 (clobber (match_operand 2 "register_operand" ""))
2924 (clobber (reg:CC CC_REGNUM))]
2925 "reload_completed && TARGET_CPU_ZARCH"
2926 [(set (match_dup 2) (label_ref (match_dup 3)))
2928 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2929 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2930 (set (match_dup 0) (const_int 0))
2932 (clobber (reg:CC CC_REGNUM))])]
2933 "operands[3] = gen_label_rtx ();")
2935 ; Initialize a block of arbitrary length with (operands[2] % 256).
2937 (define_expand "setmem_long"
2939 [(clobber (match_dup 1))
2940 (set (match_operand:BLK 0 "memory_operand" "")
2941 (match_operand 2 "shift_count_or_setmem_operand" ""))
2942 (use (match_operand 1 "general_operand" ""))
2944 (clobber (reg:CC CC_REGNUM))])]
2947 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2948 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2949 rtx reg0 = gen_reg_rtx (dreg_mode);
2950 rtx reg1 = gen_reg_rtx (dreg_mode);
2951 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2952 rtx len0 = gen_lowpart (Pmode, reg0);
2954 emit_clobber (reg0);
2955 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2956 emit_move_insn (len0, operands[1]);
2958 emit_move_insn (reg1, const0_rtx);
2960 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2965 (define_insn "*setmem_long"
2966 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2967 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2968 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2970 (use (match_operand:<DBL> 1 "register_operand" "d"))
2971 (clobber (reg:CC CC_REGNUM))]
2972 "TARGET_64BIT || !TARGET_ZARCH"
2973 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2974 [(set_attr "length" "8")
2975 (set_attr "type" "vs")])
2977 (define_insn "*setmem_long_and"
2978 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2979 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2980 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2981 (match_operand 4 "const_int_operand" "n")))
2983 (use (match_operand:<DBL> 1 "register_operand" "d"))
2984 (clobber (reg:CC CC_REGNUM))]
2985 "(TARGET_64BIT || !TARGET_ZARCH) &&
2986 (INTVAL (operands[4]) & 255) == 255"
2987 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2988 [(set_attr "length" "8")
2989 (set_attr "type" "vs")])
2991 (define_insn "*setmem_long_31z"
2992 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2993 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
2994 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2996 (use (match_operand:TI 1 "register_operand" "d"))
2997 (clobber (reg:CC CC_REGNUM))]
2998 "!TARGET_64BIT && TARGET_ZARCH"
2999 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3000 [(set_attr "length" "8")
3001 (set_attr "type" "vs")])
3004 ; cmpmemM instruction pattern(s).
3007 (define_expand "cmpmemsi"
3008 [(set (match_operand:SI 0 "register_operand" "")
3009 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3010 (match_operand:BLK 2 "memory_operand" "") ) )
3011 (use (match_operand:SI 3 "general_operand" ""))
3012 (use (match_operand:SI 4 "" ""))]
3014 "s390_expand_cmpmem (operands[0], operands[1],
3015 operands[2], operands[3]); DONE;")
3017 ; Compare a block that is up to 256 bytes in length.
3018 ; The block length is taken as (operands[2] % 256) + 1.
3020 (define_expand "cmpmem_short"
3022 [(set (reg:CCU CC_REGNUM)
3023 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3024 (match_operand:BLK 1 "memory_operand" "")))
3025 (use (match_operand 2 "nonmemory_operand" ""))
3026 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3027 (clobber (match_dup 3))])]
3029 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3031 (define_insn "*cmpmem_short"
3032 [(set (reg:CCU CC_REGNUM)
3033 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3034 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3035 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3036 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3037 (clobber (match_scratch 4 "=X,X,X,&a"))]
3038 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
3039 && GET_MODE (operands[4]) == Pmode"
3041 [(set_attr "type" "cs")
3042 (set_attr "cpu_facility" "*,*,z10,*")])
3045 [(set (reg:CCU CC_REGNUM)
3046 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3047 (match_operand:BLK 1 "memory_operand" "")))
3048 (use (match_operand 2 "const_int_operand" ""))
3049 (use (match_operand 3 "immediate_operand" ""))
3050 (clobber (scratch))]
3053 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3054 (use (match_dup 2))])]
3055 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3058 [(set (reg:CCU CC_REGNUM)
3059 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3060 (match_operand:BLK 1 "memory_operand" "")))
3061 (use (match_operand 2 "register_operand" ""))
3062 (use (match_operand 3 "memory_operand" ""))
3063 (clobber (scratch))]
3066 [(unspec [(match_dup 2) (match_dup 3)
3067 (const_int 0)] UNSPEC_EXECUTE)
3068 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3069 (use (const_int 1))])]
3073 [(set (reg:CCU CC_REGNUM)
3074 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3075 (match_operand:BLK 1 "memory_operand" "")))
3076 (use (match_operand 2 "register_operand" ""))
3077 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3078 (clobber (scratch))]
3079 "TARGET_Z10 && reload_completed"
3081 [(unspec [(match_dup 2) (const_int 0)
3082 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3083 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3084 (use (const_int 1))])]
3085 "operands[4] = gen_label_rtx ();")
3088 [(set (reg:CCU CC_REGNUM)
3089 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3090 (match_operand:BLK 1 "memory_operand" "")))
3091 (use (match_operand 2 "register_operand" ""))
3092 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3093 (clobber (match_operand 3 "register_operand" ""))]
3094 "reload_completed && TARGET_CPU_ZARCH"
3095 [(set (match_dup 3) (label_ref (match_dup 4)))
3097 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3098 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3099 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3100 (use (const_int 1))])]
3101 "operands[4] = gen_label_rtx ();")
3103 ; Compare a block of arbitrary length.
3105 (define_expand "cmpmem_long"
3107 [(clobber (match_dup 2))
3108 (clobber (match_dup 3))
3109 (set (reg:CCU CC_REGNUM)
3110 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3111 (match_operand:BLK 1 "memory_operand" "")))
3112 (use (match_operand 2 "general_operand" ""))
3113 (use (match_dup 3))])]
3116 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3117 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3118 rtx reg0 = gen_reg_rtx (dreg_mode);
3119 rtx reg1 = gen_reg_rtx (dreg_mode);
3120 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3121 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3122 rtx len0 = gen_lowpart (Pmode, reg0);
3123 rtx len1 = gen_lowpart (Pmode, reg1);
3125 emit_clobber (reg0);
3126 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3127 emit_move_insn (len0, operands[2]);
3129 emit_clobber (reg1);
3130 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3131 emit_move_insn (len1, operands[2]);
3133 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3134 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3139 (define_insn "*cmpmem_long"
3140 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3141 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3142 (set (reg:CCU CC_REGNUM)
3143 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3144 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3146 (use (match_dup 3))]
3147 "TARGET_64BIT || !TARGET_ZARCH"
3148 "clcle\t%0,%1,0\;jo\t.-4"
3149 [(set_attr "length" "8")
3150 (set_attr "type" "vs")])
3152 (define_insn "*cmpmem_long_31z"
3153 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3154 (clobber (match_operand:TI 1 "register_operand" "=d"))
3155 (set (reg:CCU CC_REGNUM)
3156 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3157 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3159 (use (match_dup 3))]
3160 "!TARGET_64BIT && TARGET_ZARCH"
3161 "clcle\t%0,%1,0\;jo\t.-4"
3162 [(set_attr "op_type" "NN")
3163 (set_attr "type" "vs")
3164 (set_attr "length" "8")])
3166 ; Convert CCUmode condition code to integer.
3167 ; Result is zero if EQ, positive if LTU, negative if GTU.
3169 (define_insn_and_split "cmpint"
3170 [(set (match_operand:SI 0 "register_operand" "=d")
3171 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3173 (clobber (reg:CC CC_REGNUM))]
3177 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3179 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3180 (clobber (reg:CC CC_REGNUM))])])
3182 (define_insn_and_split "*cmpint_cc"
3183 [(set (reg CC_REGNUM)
3184 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3187 (set (match_operand:SI 0 "register_operand" "=d")
3188 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3189 "s390_match_ccmode (insn, CCSmode)"
3191 "&& reload_completed"
3192 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3194 [(set (match_dup 2) (match_dup 3))
3195 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3197 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3198 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3199 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3202 (define_insn_and_split "*cmpint_sign"
3203 [(set (match_operand:DI 0 "register_operand" "=d")
3204 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3205 UNSPEC_CCU_TO_INT)))
3206 (clobber (reg:CC CC_REGNUM))]
3209 "&& reload_completed"
3210 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3212 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3213 (clobber (reg:CC CC_REGNUM))])])
3215 (define_insn_and_split "*cmpint_sign_cc"
3216 [(set (reg CC_REGNUM)
3217 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3218 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3219 UNSPEC_CCU_TO_INT) 0)
3220 (const_int 32)) (const_int 32))
3222 (set (match_operand:DI 0 "register_operand" "=d")
3223 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3224 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3226 "&& reload_completed"
3227 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3229 [(set (match_dup 2) (match_dup 3))
3230 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3232 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3233 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3234 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3239 ;;- Conversion instructions.
3242 (define_insn "*sethighpartsi"
3243 [(set (match_operand:SI 0 "register_operand" "=d,d")
3244 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3245 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3246 (clobber (reg:CC CC_REGNUM))]
3251 [(set_attr "op_type" "RS,RSY")
3252 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3254 (define_insn "*sethighpartdi_64"
3255 [(set (match_operand:DI 0 "register_operand" "=d")
3256 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3257 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3258 (clobber (reg:CC CC_REGNUM))]
3261 [(set_attr "op_type" "RSY")
3262 (set_attr "z10prop" "z10_super")])
3264 (define_insn "*sethighpartdi_31"
3265 [(set (match_operand:DI 0 "register_operand" "=d,d")
3266 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3267 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3268 (clobber (reg:CC CC_REGNUM))]
3273 [(set_attr "op_type" "RS,RSY")
3274 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3277 (define_insn_and_split "*extzv<mode>"
3278 [(set (match_operand:GPR 0 "register_operand" "=d")
3279 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3280 (match_operand 2 "const_int_operand" "n")
3282 (clobber (reg:CC CC_REGNUM))]
3283 "INTVAL (operands[2]) > 0
3284 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3286 "&& reload_completed"
3288 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3289 (clobber (reg:CC CC_REGNUM))])
3290 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3292 int bitsize = INTVAL (operands[2]);
3293 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3294 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3296 operands[1] = adjust_address (operands[1], BLKmode, 0);
3297 set_mem_size (operands[1], GEN_INT (size));
3298 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3299 operands[3] = GEN_INT (mask);
3302 (define_insn_and_split "*extv<mode>"
3303 [(set (match_operand:GPR 0 "register_operand" "=d")
3304 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3305 (match_operand 2 "const_int_operand" "n")
3307 (clobber (reg:CC CC_REGNUM))]
3308 "INTVAL (operands[2]) > 0
3309 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3311 "&& reload_completed"
3313 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3314 (clobber (reg:CC CC_REGNUM))])
3316 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3317 (clobber (reg:CC CC_REGNUM))])]
3319 int bitsize = INTVAL (operands[2]);
3320 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3321 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3323 operands[1] = adjust_address (operands[1], BLKmode, 0);
3324 set_mem_size (operands[1], GEN_INT (size));
3325 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3326 operands[3] = GEN_INT (mask);
3330 ; insv instruction patterns
3333 (define_expand "insv"
3334 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3335 (match_operand 1 "const_int_operand" "")
3336 (match_operand 2 "const_int_operand" ""))
3337 (match_operand 3 "general_operand" ""))]
3340 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3345 (define_insn "*insv<mode>_z10"
3346 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3347 (match_operand 1 "const_int_operand" "I")
3348 (match_operand 2 "const_int_operand" "I"))
3349 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3350 (clobber (reg:CC CC_REGNUM))]
3352 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3353 GET_MODE_BITSIZE (<MODE>mode)"
3355 int start = INTVAL (operands[2]);
3356 int size = INTVAL (operands[1]);
3357 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3359 operands[2] = GEN_INT (offset + start); /* start bit position */
3360 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3361 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3362 start - size); /* left shift count */
3364 return "risbg\t%0,%3,%b2,%b1,%b4";
3366 [(set_attr "op_type" "RIE")
3367 (set_attr "z10prop" "z10_super_E1")])
3369 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3370 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3371 (define_insn "*insv<mode>_z10_noshift"
3372 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3373 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3374 (match_operand 2 "const_int_operand" "n"))
3375 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3376 (match_operand 4 "const_int_operand" "n"))))
3377 (clobber (reg:CC CC_REGNUM))]
3379 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3380 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3381 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3387 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3388 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3390 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3391 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3392 operands[7] = const0_rtx; /* left shift count */
3394 return "risbg\t%0,%1,%b5,%b6,%b7";
3396 [(set_attr "op_type" "RIE")
3397 (set_attr "z10prop" "z10_super_E1")])
3399 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3400 (define_insn "*insv<mode>_or_z10_noshift"
3401 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3402 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3403 (match_operand 2 "const_int_operand" "n"))
3404 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3405 (clobber (reg:CC CC_REGNUM))]
3407 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3408 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3413 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3414 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3416 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3417 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3418 operands[6] = const0_rtx; /* left shift count */
3420 return "rosbg\t%0,%1,%b4,%b5,%b6";
3422 [(set_attr "op_type" "RIE")])
3424 (define_insn "*insv<mode>_mem_reg"
3425 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3426 (match_operand 1 "const_int_operand" "n,n")
3428 (match_operand:W 2 "register_operand" "d,d"))]
3429 "INTVAL (operands[1]) > 0
3430 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3431 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3433 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3435 operands[1] = GEN_INT ((1ul << size) - 1);
3436 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3437 : "stcmy\t%2,%1,%S0";
3439 [(set_attr "op_type" "RS,RSY")
3440 (set_attr "z10prop" "z10_super,z10_super")])
3442 (define_insn "*insvdi_mem_reghigh"
3443 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3444 (match_operand 1 "const_int_operand" "n")
3446 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3449 && INTVAL (operands[1]) > 0
3450 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3451 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3453 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3455 operands[1] = GEN_INT ((1ul << size) - 1);
3456 return "stcmh\t%2,%1,%S0";
3458 [(set_attr "op_type" "RSY")
3459 (set_attr "z10prop" "z10_super")])
3461 (define_insn "*insvdi_reg_imm"
3462 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3464 (match_operand 1 "const_int_operand" "n"))
3465 (match_operand:DI 2 "const_int_operand" "n"))]
3467 && INTVAL (operands[1]) >= 0
3468 && INTVAL (operands[1]) < BITS_PER_WORD
3469 && INTVAL (operands[1]) % 16 == 0"
3471 switch (BITS_PER_WORD - INTVAL (operands[1]))
3473 case 64: return "iihh\t%0,%x2"; break;
3474 case 48: return "iihl\t%0,%x2"; break;
3475 case 32: return "iilh\t%0,%x2"; break;
3476 case 16: return "iill\t%0,%x2"; break;
3477 default: gcc_unreachable();
3480 [(set_attr "op_type" "RI")
3481 (set_attr "z10prop" "z10_super_E1")])
3483 ; Update the left-most 32 bit of a DI.
3484 (define_insn "*insv_h_di_reg_extimm"
3485 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3488 (match_operand:DI 1 "const_int_operand" "n"))]
3491 [(set_attr "op_type" "RIL")
3492 (set_attr "z10prop" "z10_fwd_E1")])
3494 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3495 (define_insn "*insv_l<mode>_reg_extimm"
3496 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3498 (match_operand 1 "const_int_operand" "n"))
3499 (match_operand:P 2 "const_int_operand" "n"))]
3501 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3503 [(set_attr "op_type" "RIL")
3504 (set_attr "z10prop" "z10_fwd_A1")])
3507 ; extendsidi2 instruction pattern(s).
3510 (define_expand "extendsidi2"
3511 [(set (match_operand:DI 0 "register_operand" "")
3512 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3517 emit_clobber (operands[0]);
3518 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3519 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3520 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3525 (define_insn "*extendsidi2"
3526 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3527 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3533 [(set_attr "op_type" "RRE,RXY,RIL")
3534 (set_attr "type" "*,*,larl")
3535 (set_attr "cpu_facility" "*,*,z10")
3536 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3539 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3542 (define_expand "extend<HQI:mode><DSI:mode>2"
3543 [(set (match_operand:DSI 0 "register_operand" "")
3544 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3547 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3549 rtx tmp = gen_reg_rtx (SImode);
3550 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3551 emit_insn (gen_extendsidi2 (operands[0], tmp));
3554 else if (!TARGET_EXTIMM)
3556 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3557 GET_MODE_BITSIZE (<HQI:MODE>mode));
3559 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3560 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3561 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3567 ; extendhidi2 instruction pattern(s).
3570 (define_insn "*extendhidi2_extimm"
3571 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3572 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3573 "TARGET_ZARCH && TARGET_EXTIMM"
3578 [(set_attr "op_type" "RRE,RXY,RIL")
3579 (set_attr "type" "*,*,larl")
3580 (set_attr "cpu_facility" "extimm,extimm,z10")
3581 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3583 (define_insn "*extendhidi2"
3584 [(set (match_operand:DI 0 "register_operand" "=d")
3585 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3588 [(set_attr "op_type" "RXY")
3589 (set_attr "z10prop" "z10_super_E1")])
3592 ; extendhisi2 instruction pattern(s).
3595 (define_insn "*extendhisi2_extimm"
3596 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3597 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3604 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3605 (set_attr "type" "*,*,*,larl")
3606 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3607 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3609 (define_insn "*extendhisi2"
3610 [(set (match_operand:SI 0 "register_operand" "=d,d")
3611 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3616 [(set_attr "op_type" "RX,RXY")
3617 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3620 ; extendqi(si|di)2 instruction pattern(s).
3623 ; lbr, lgbr, lb, lgb
3624 (define_insn "*extendqi<mode>2_extimm"
3625 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3626 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3631 [(set_attr "op_type" "RRE,RXY")
3632 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3635 (define_insn "*extendqi<mode>2"
3636 [(set (match_operand:GPR 0 "register_operand" "=d")
3637 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3638 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3640 [(set_attr "op_type" "RXY")
3641 (set_attr "z10prop" "z10_super_E1")])
3643 (define_insn_and_split "*extendqi<mode>2_short_displ"
3644 [(set (match_operand:GPR 0 "register_operand" "=d")
3645 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3646 (clobber (reg:CC CC_REGNUM))]
3647 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3649 "&& reload_completed"
3651 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3652 (clobber (reg:CC CC_REGNUM))])
3654 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3655 (clobber (reg:CC CC_REGNUM))])]
3657 operands[1] = adjust_address (operands[1], BLKmode, 0);
3658 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3659 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3660 - GET_MODE_BITSIZE (QImode));
3664 ; zero_extendsidi2 instruction pattern(s).
3667 (define_expand "zero_extendsidi2"
3668 [(set (match_operand:DI 0 "register_operand" "")
3669 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3674 emit_clobber (operands[0]);
3675 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3676 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3681 (define_insn "*zero_extendsidi2"
3682 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3683 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3689 [(set_attr "op_type" "RRE,RXY,RIL")
3690 (set_attr "type" "*,*,larl")
3691 (set_attr "cpu_facility" "*,*,z10")
3692 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3695 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3698 (define_insn "*llgt_sidi"
3699 [(set (match_operand:DI 0 "register_operand" "=d")
3700 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3701 (const_int 2147483647)))]
3704 [(set_attr "op_type" "RXE")
3705 (set_attr "z10prop" "z10_super_E1")])
3707 (define_insn_and_split "*llgt_sidi_split"
3708 [(set (match_operand:DI 0 "register_operand" "=d")
3709 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3710 (const_int 2147483647)))
3711 (clobber (reg:CC CC_REGNUM))]
3714 "&& reload_completed"
3716 (and:DI (subreg:DI (match_dup 1) 0)
3717 (const_int 2147483647)))]
3720 (define_insn "*llgt_sisi"
3721 [(set (match_operand:SI 0 "register_operand" "=d,d")
3722 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3723 (const_int 2147483647)))]
3728 [(set_attr "op_type" "RRE,RXE")
3729 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3731 (define_insn "*llgt_didi"
3732 [(set (match_operand:DI 0 "register_operand" "=d,d")
3733 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3734 (const_int 2147483647)))]
3739 [(set_attr "op_type" "RRE,RXE")
3740 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3743 [(set (match_operand:DSI 0 "register_operand" "")
3744 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3745 (const_int 2147483647)))
3746 (clobber (reg:CC CC_REGNUM))]
3747 "TARGET_ZARCH && reload_completed"
3749 (and:DSI (match_dup 1)
3750 (const_int 2147483647)))]
3754 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3757 (define_expand "zero_extend<mode>di2"
3758 [(set (match_operand:DI 0 "register_operand" "")
3759 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3764 rtx tmp = gen_reg_rtx (SImode);
3765 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3766 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3769 else if (!TARGET_EXTIMM)
3771 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3772 GET_MODE_BITSIZE(<MODE>mode));
3773 operands[1] = gen_lowpart (DImode, operands[1]);
3774 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3775 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3780 (define_expand "zero_extend<mode>si2"
3781 [(set (match_operand:SI 0 "register_operand" "")
3782 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3787 operands[1] = gen_lowpart (SImode, operands[1]);
3788 emit_insn (gen_andsi3 (operands[0], operands[1],
3789 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3795 (define_insn "*zero_extendhi<mode>2_z10"
3796 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3797 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3803 [(set_attr "op_type" "RXY,RRE,RIL")
3804 (set_attr "type" "*,*,larl")
3805 (set_attr "cpu_facility" "*,*,z10")
3806 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3808 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3809 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3810 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3811 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3816 [(set_attr "op_type" "RRE,RXY")
3817 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3820 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3821 [(set (match_operand:GPR 0 "register_operand" "=d")
3822 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3823 "TARGET_ZARCH && !TARGET_EXTIMM"
3825 [(set_attr "op_type" "RXY")
3826 (set_attr "z10prop" "z10_fwd_A3")])
3828 (define_insn_and_split "*zero_extendhisi2_31"
3829 [(set (match_operand:SI 0 "register_operand" "=&d")
3830 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3831 (clobber (reg:CC CC_REGNUM))]
3834 "&& reload_completed"
3835 [(set (match_dup 0) (const_int 0))
3837 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3838 (clobber (reg:CC CC_REGNUM))])]
3839 "operands[2] = gen_lowpart (HImode, operands[0]);")
3841 (define_insn_and_split "*zero_extendqisi2_31"
3842 [(set (match_operand:SI 0 "register_operand" "=&d")
3843 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3846 "&& reload_completed"
3847 [(set (match_dup 0) (const_int 0))
3848 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3849 "operands[2] = gen_lowpart (QImode, operands[0]);")
3852 ; zero_extendqihi2 instruction pattern(s).
3855 (define_expand "zero_extendqihi2"
3856 [(set (match_operand:HI 0 "register_operand" "")
3857 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3858 "TARGET_ZARCH && !TARGET_EXTIMM"
3860 operands[1] = gen_lowpart (HImode, operands[1]);
3861 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3865 (define_insn "*zero_extendqihi2_64"
3866 [(set (match_operand:HI 0 "register_operand" "=d")
3867 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3868 "TARGET_ZARCH && !TARGET_EXTIMM"
3870 [(set_attr "op_type" "RXY")
3871 (set_attr "z10prop" "z10_fwd_A3")])
3873 (define_insn_and_split "*zero_extendqihi2_31"
3874 [(set (match_operand:HI 0 "register_operand" "=&d")
3875 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3878 "&& reload_completed"
3879 [(set (match_dup 0) (const_int 0))
3880 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3881 "operands[2] = gen_lowpart (QImode, operands[0]);")
3884 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3887 (define_expand "fixuns_truncdddi2"
3889 [(set (match_operand:DI 0 "register_operand" "")
3890 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3891 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3892 (clobber (reg:CC CC_REGNUM))])]
3898 rtx label1 = gen_label_rtx ();
3899 rtx label2 = gen_label_rtx ();
3900 rtx temp = gen_reg_rtx (TDmode);
3901 REAL_VALUE_TYPE cmp, sub;
3903 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3904 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3906 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3907 solution is doing the check and the subtraction in TD mode and using a
3908 TD -> DI convert afterwards. */
3909 emit_insn (gen_extendddtd2 (temp, operands[1]));
3910 temp = force_reg (TDmode, temp);
3911 emit_cmp_and_jump_insns (temp,
3912 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3913 LT, NULL_RTX, VOIDmode, 0, label1);
3914 emit_insn (gen_subtd3 (temp, temp,
3915 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3916 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3919 emit_label (label1);
3920 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3921 emit_label (label2);
3926 (define_expand "fixuns_trunctddi2"
3928 [(set (match_operand:DI 0 "register_operand" "")
3929 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
3930 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3931 (clobber (reg:CC CC_REGNUM))])]
3937 rtx label1 = gen_label_rtx ();
3938 rtx label2 = gen_label_rtx ();
3939 rtx temp = gen_reg_rtx (TDmode);
3940 REAL_VALUE_TYPE cmp, sub;
3942 operands[1] = force_reg (TDmode, operands[1]);
3943 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3944 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3946 emit_cmp_and_jump_insns (operands[1],
3947 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3948 LT, NULL_RTX, VOIDmode, 0, label1);
3949 emit_insn (gen_subtd3 (temp, operands[1],
3950 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3951 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3954 emit_label (label1);
3955 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3956 emit_label (label2);
3962 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
3963 ; instruction pattern(s).
3966 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3968 [(set (match_operand:GPR 0 "register_operand" "")
3969 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
3970 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3971 (clobber (reg:CC CC_REGNUM))])]
3976 rtx label1 = gen_label_rtx ();
3977 rtx label2 = gen_label_rtx ();
3978 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3979 REAL_VALUE_TYPE cmp, sub;
3981 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3982 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3983 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3985 emit_cmp_and_jump_insns (operands[1],
3986 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
3987 LT, NULL_RTX, VOIDmode, 0, label1);
3988 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3989 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3990 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3994 emit_label (label1);
3995 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3996 operands[1], GEN_INT (5)));
3997 emit_label (label2);
4002 ; fixuns_trunc(td|dd)si2 expander
4003 (define_expand "fixuns_trunc<mode>si2"
4005 [(set (match_operand:SI 0 "register_operand" "")
4006 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4007 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4008 (clobber (reg:CC CC_REGNUM))])]
4009 "TARGET_Z196 && TARGET_HARD_FLOAT"
4012 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4014 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4015 ; clfdtr, clfxtr, clgdtr, clgxtr
4016 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4017 [(set (match_operand:GPR 0 "register_operand" "=r")
4018 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4019 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4020 (clobber (reg:CC CC_REGNUM))]
4022 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4023 [(set_attr "op_type" "RRF")
4024 (set_attr "type" "ftoi")])
4026 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4027 [(set (match_operand:GPR 0 "register_operand" "")
4028 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4031 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4036 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4037 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4038 [(set (match_operand:GPR 0 "register_operand" "=d")
4039 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4040 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4041 (clobber (reg:CC CC_REGNUM))]
4043 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4044 [(set_attr "op_type" "RRE")
4045 (set_attr "type" "ftoi")])
4049 ; fix_trunc(td|dd)di2 instruction pattern(s).
4052 (define_expand "fix_trunc<mode>di2"
4053 [(set (match_operand:DI 0 "register_operand" "")
4054 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4055 "TARGET_ZARCH && TARGET_HARD_DFP"
4057 operands[1] = force_reg (<MODE>mode, operands[1]);
4058 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4064 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4065 [(set (match_operand:DI 0 "register_operand" "=d")
4066 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4067 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4068 (clobber (reg:CC CC_REGNUM))]
4069 "TARGET_ZARCH && TARGET_HARD_DFP"
4070 "cg<DFP:xde>tr\t%0,%h2,%1"
4071 [(set_attr "op_type" "RRF")
4072 (set_attr "type" "ftoidfp")])
4076 ; fix_trunctf(si|di)2 instruction pattern(s).
4079 (define_expand "fix_trunctf<mode>2"
4080 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4081 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4082 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4083 (clobber (reg:CC CC_REGNUM))])]
4089 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4092 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4093 (define_insn "floatdi<mode>2"
4094 [(set (match_operand:FP 0 "register_operand" "=f")
4095 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4096 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4097 "c<xde>g<bt>r\t%0,%1"
4098 [(set_attr "op_type" "RRE")
4099 (set_attr "type" "itof<mode>" )])
4101 ; cxfbr, cdfbr, cefbr
4102 (define_insn "floatsi<mode>2"
4103 [(set (match_operand:BFP 0 "register_operand" "=f")
4104 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4107 [(set_attr "op_type" "RRE")
4108 (set_attr "type" "itof<mode>" )])
4111 (define_insn "floatsi<mode>2"
4112 [(set (match_operand:DFP 0 "register_operand" "=f")
4113 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4114 "TARGET_Z196 && TARGET_HARD_FLOAT"
4115 "c<xde>ftr\t%0,0,%1,0"
4116 [(set_attr "op_type" "RRE")
4117 (set_attr "type" "itof<mode>" )])
4120 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4123 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4124 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4125 (define_insn "floatuns<GPR:mode><FP:mode>2"
4126 [(set (match_operand:FP 0 "register_operand" "=f")
4127 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4128 "TARGET_Z196 && TARGET_HARD_FLOAT"
4129 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4130 [(set_attr "op_type" "RRE")
4131 (set_attr "type" "itof<FP:mode>" )])
4134 ; truncdfsf2 instruction pattern(s).
4137 (define_insn "truncdfsf2"
4138 [(set (match_operand:SF 0 "register_operand" "=f")
4139 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4142 [(set_attr "op_type" "RRE")
4143 (set_attr "type" "ftruncdf")])
4146 ; trunctf(df|sf)2 instruction pattern(s).
4150 (define_insn "trunctf<mode>2"
4151 [(set (match_operand:DSF 0 "register_operand" "=f")
4152 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4153 (clobber (match_scratch:TF 2 "=f"))]
4155 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4156 [(set_attr "length" "6")
4157 (set_attr "type" "ftrunctf")])
4160 ; trunctddd2 and truncddsd2 instruction pattern(s).
4163 (define_insn "trunctddd2"
4164 [(set (match_operand:DD 0 "register_operand" "=f")
4165 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4166 (clobber (match_scratch:TD 2 "=f"))]
4168 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4169 [(set_attr "length" "6")
4170 (set_attr "type" "ftruncdd")])
4172 (define_insn "truncddsd2"
4173 [(set (match_operand:SD 0 "register_operand" "=f")
4174 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4177 [(set_attr "op_type" "RRF")
4178 (set_attr "type" "ftruncsd")])
4181 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4184 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4185 (define_insn "extend<DSF:mode><BFP:mode>2"
4186 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4187 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4189 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4191 l<BFP:xde><DSF:xde>br\t%0,%1
4192 l<BFP:xde><DSF:xde>b\t%0,%1"
4193 [(set_attr "op_type" "RRE,RXE")
4194 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4197 ; extendddtd2 and extendsddd2 instruction pattern(s).
4200 (define_insn "extendddtd2"
4201 [(set (match_operand:TD 0 "register_operand" "=f")
4202 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4205 [(set_attr "op_type" "RRF")
4206 (set_attr "type" "fsimptf")])
4208 (define_insn "extendsddd2"
4209 [(set (match_operand:DD 0 "register_operand" "=f")
4210 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4213 [(set_attr "op_type" "RRF")
4214 (set_attr "type" "fsimptf")])
4216 ; Binary <-> Decimal floating point trunc patterns
4219 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4220 [(set (reg:DFP_ALL FPR0_REGNUM)
4221 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4222 (use (reg:SI GPR0_REGNUM))
4223 (clobber (reg:CC CC_REGNUM))]
4227 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4228 [(set (reg:BFP FPR0_REGNUM)
4229 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4230 (use (reg:SI GPR0_REGNUM))
4231 (clobber (reg:CC CC_REGNUM))]
4235 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4236 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4237 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4239 [(set (reg:DFP_ALL FPR0_REGNUM)
4240 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4241 (use (reg:SI GPR0_REGNUM))
4242 (clobber (reg:CC CC_REGNUM))])
4243 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4244 (reg:DFP_ALL FPR0_REGNUM))]
4246 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4248 HOST_WIDE_INT flags;
4250 flags = (PFPO_CONVERT |
4251 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4252 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4254 operands[2] = GEN_INT (flags);
4257 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4258 [(set (reg:DFP_ALL FPR2_REGNUM)
4259 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4260 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4262 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4263 (use (reg:SI GPR0_REGNUM))
4264 (clobber (reg:CC CC_REGNUM))])
4265 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4267 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4269 HOST_WIDE_INT flags;
4271 flags = (PFPO_CONVERT |
4272 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4273 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4275 operands[2] = GEN_INT (flags);
4279 ; Binary <-> Decimal floating point extend patterns
4282 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4283 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4284 (use (reg:SI GPR0_REGNUM))
4285 (clobber (reg:CC CC_REGNUM))]
4289 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4290 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4291 (use (reg:SI GPR0_REGNUM))
4292 (clobber (reg:CC CC_REGNUM))]
4296 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4297 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4298 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4300 [(set (reg:DFP_ALL FPR0_REGNUM)
4301 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4302 (use (reg:SI GPR0_REGNUM))
4303 (clobber (reg:CC CC_REGNUM))])
4304 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4305 (reg:DFP_ALL FPR0_REGNUM))]
4307 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4309 HOST_WIDE_INT flags;
4311 flags = (PFPO_CONVERT |
4312 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4313 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4315 operands[2] = GEN_INT (flags);
4318 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4319 [(set (reg:DFP_ALL FPR2_REGNUM)
4320 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4321 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4323 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4324 (use (reg:SI GPR0_REGNUM))
4325 (clobber (reg:CC CC_REGNUM))])
4326 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4328 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4330 HOST_WIDE_INT flags;
4332 flags = (PFPO_CONVERT |
4333 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4334 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4336 operands[2] = GEN_INT (flags);
4341 ;; ARITHMETIC OPERATIONS
4343 ; arithmetic operations set the ConditionCode,
4344 ; because of unpredictable Bits in Register for Halfword and Byte
4345 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4348 ;;- Add instructions.
4352 ; addti3 instruction pattern(s).
4355 (define_insn_and_split "addti3"
4356 [(set (match_operand:TI 0 "register_operand" "=&d")
4357 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4358 (match_operand:TI 2 "general_operand" "do") ) )
4359 (clobber (reg:CC CC_REGNUM))]
4362 "&& reload_completed"
4364 [(set (reg:CCL1 CC_REGNUM)
4365 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4367 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4369 [(set (match_dup 3) (plus:DI
4370 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4371 (match_dup 4)) (match_dup 5)))
4372 (clobber (reg:CC CC_REGNUM))])]
4373 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4374 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4375 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4376 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4377 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4378 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4381 ; adddi3 instruction pattern(s).
4384 (define_expand "adddi3"
4386 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4387 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4388 (match_operand:DI 2 "general_operand" "")))
4389 (clobber (reg:CC CC_REGNUM))])]
4393 (define_insn "*adddi3_sign"
4394 [(set (match_operand:DI 0 "register_operand" "=d,d")
4395 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4396 (match_operand:DI 1 "register_operand" "0,0")))
4397 (clobber (reg:CC CC_REGNUM))]
4402 [(set_attr "op_type" "RRE,RXY")
4403 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4405 (define_insn "*adddi3_zero_cc"
4406 [(set (reg CC_REGNUM)
4407 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4408 (match_operand:DI 1 "register_operand" "0,0"))
4410 (set (match_operand:DI 0 "register_operand" "=d,d")
4411 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4412 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4416 [(set_attr "op_type" "RRE,RXY")
4417 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4419 (define_insn "*adddi3_zero_cconly"
4420 [(set (reg CC_REGNUM)
4421 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4422 (match_operand:DI 1 "register_operand" "0,0"))
4424 (clobber (match_scratch:DI 0 "=d,d"))]
4425 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4429 [(set_attr "op_type" "RRE,RXY")
4430 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4432 (define_insn "*adddi3_zero"
4433 [(set (match_operand:DI 0 "register_operand" "=d,d")
4434 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4435 (match_operand:DI 1 "register_operand" "0,0")))
4436 (clobber (reg:CC CC_REGNUM))]
4441 [(set_attr "op_type" "RRE,RXY")
4442 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4444 (define_insn_and_split "*adddi3_31z"
4445 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4446 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4447 (match_operand:DI 2 "general_operand" "do") ) )
4448 (clobber (reg:CC CC_REGNUM))]
4449 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4451 "&& reload_completed"
4453 [(set (reg:CCL1 CC_REGNUM)
4454 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4456 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4458 [(set (match_dup 3) (plus:SI
4459 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4460 (match_dup 4)) (match_dup 5)))
4461 (clobber (reg:CC CC_REGNUM))])]
4462 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4463 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4464 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4465 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4466 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4467 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4469 (define_insn_and_split "*adddi3_31"
4470 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4471 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4472 (match_operand:DI 2 "general_operand" "do") ) )
4473 (clobber (reg:CC CC_REGNUM))]
4476 "&& reload_completed"
4478 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4479 (clobber (reg:CC CC_REGNUM))])
4481 [(set (reg:CCL1 CC_REGNUM)
4482 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4484 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4486 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4488 (label_ref (match_dup 9))))
4490 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4491 (clobber (reg:CC CC_REGNUM))])
4493 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4494 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4495 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4496 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4497 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4498 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4499 operands[9] = gen_label_rtx ();")
4502 ; addsi3 instruction pattern(s).
4505 (define_expand "addsi3"
4507 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4508 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4509 (match_operand:SI 2 "general_operand" "")))
4510 (clobber (reg:CC CC_REGNUM))])]
4514 (define_insn "*addsi3_sign"
4515 [(set (match_operand:SI 0 "register_operand" "=d,d")
4516 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4517 (match_operand:SI 1 "register_operand" "0,0")))
4518 (clobber (reg:CC CC_REGNUM))]
4523 [(set_attr "op_type" "RX,RXY")
4524 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4527 ; add(di|si)3 instruction pattern(s).
4530 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4531 (define_insn "*add<mode>3"
4532 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4533 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4534 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4535 (clobber (reg:CC CC_REGNUM))]
4547 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4548 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4549 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4550 z10_super_E1,z10_super_E1,z10_super_E1")])
4552 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4553 (define_insn "*add<mode>3_carry1_cc"
4554 [(set (reg CC_REGNUM)
4555 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4556 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4558 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4559 (plus:GPR (match_dup 1) (match_dup 2)))]
4560 "s390_match_ccmode (insn, CCL1mode)"
4566 al<g>hsik\t%0,%1,%h2
4570 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4571 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4572 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4573 z10_super_E1,z10_super_E1,z10_super_E1")])
4575 ; alr, al, aly, algr, alg, alrk, algrk
4576 (define_insn "*add<mode>3_carry1_cconly"
4577 [(set (reg CC_REGNUM)
4578 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4579 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4581 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4582 "s390_match_ccmode (insn, CCL1mode)"
4588 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4589 (set_attr "cpu_facility" "*,z196,*,*")
4590 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4592 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4593 (define_insn "*add<mode>3_carry2_cc"
4594 [(set (reg CC_REGNUM)
4595 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4596 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4598 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4599 (plus:GPR (match_dup 1) (match_dup 2)))]
4600 "s390_match_ccmode (insn, CCL1mode)"
4606 al<g>hsik\t%0,%1,%h2
4610 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4611 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4612 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4613 z10_super_E1,z10_super_E1,z10_super_E1")])
4615 ; alr, al, aly, algr, alg, alrk, algrk
4616 (define_insn "*add<mode>3_carry2_cconly"
4617 [(set (reg CC_REGNUM)
4618 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4619 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4621 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4622 "s390_match_ccmode (insn, CCL1mode)"
4628 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4629 (set_attr "cpu_facility" "*,z196,*,*")
4630 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4632 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4633 (define_insn "*add<mode>3_cc"
4634 [(set (reg CC_REGNUM)
4635 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4636 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4638 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4639 (plus:GPR (match_dup 1) (match_dup 2)))]
4640 "s390_match_ccmode (insn, CCLmode)"
4646 al<g>hsik\t%0,%1,%h2
4650 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4651 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4652 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4653 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4655 ; alr, al, aly, algr, alg, alrk, algrk
4656 (define_insn "*add<mode>3_cconly"
4657 [(set (reg CC_REGNUM)
4658 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4659 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4661 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4662 "s390_match_ccmode (insn, CCLmode)"
4668 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4669 (set_attr "cpu_facility" "*,z196,*,*")
4670 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4672 ; alr, al, aly, algr, alg, alrk, algrk
4673 (define_insn "*add<mode>3_cconly2"
4674 [(set (reg CC_REGNUM)
4675 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4676 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4677 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4678 "s390_match_ccmode(insn, CCLmode)"
4684 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4685 (set_attr "cpu_facility" "*,z196,*,*")
4686 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4688 ; ahi, afi, aghi, agfi, asi, agsi
4689 (define_insn "*add<mode>3_imm_cc"
4690 [(set (reg CC_REGNUM)
4691 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4692 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4694 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4695 (plus:GPR (match_dup 1) (match_dup 2)))]
4696 "s390_match_ccmode (insn, CCAmode)
4697 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4698 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4699 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4700 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4706 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4707 (set_attr "cpu_facility" "*,z196,extimm,z10")
4708 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4711 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4714 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4715 (define_insn "add<mode>3"
4716 [(set (match_operand:FP 0 "register_operand" "=f, f")
4717 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4718 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4719 (clobber (reg:CC CC_REGNUM))]
4722 a<xde><bt>r\t%0,<op1>%2
4724 [(set_attr "op_type" "<RRer>,RXE")
4725 (set_attr "type" "fsimp<mode>")])
4727 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4728 (define_insn "*add<mode>3_cc"
4729 [(set (reg CC_REGNUM)
4730 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4731 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4732 (match_operand:FP 3 "const0_operand" "")))
4733 (set (match_operand:FP 0 "register_operand" "=f,f")
4734 (plus:FP (match_dup 1) (match_dup 2)))]
4735 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4737 a<xde><bt>r\t%0,<op1>%2
4739 [(set_attr "op_type" "<RRer>,RXE")
4740 (set_attr "type" "fsimp<mode>")])
4742 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4743 (define_insn "*add<mode>3_cconly"
4744 [(set (reg CC_REGNUM)
4745 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4746 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4747 (match_operand:FP 3 "const0_operand" "")))
4748 (clobber (match_scratch:FP 0 "=f,f"))]
4749 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4751 a<xde><bt>r\t%0,<op1>%2
4753 [(set_attr "op_type" "<RRer>,RXE")
4754 (set_attr "type" "fsimp<mode>")])
4758 ;;- Subtract instructions.
4762 ; subti3 instruction pattern(s).
4765 (define_insn_and_split "subti3"
4766 [(set (match_operand:TI 0 "register_operand" "=&d")
4767 (minus:TI (match_operand:TI 1 "register_operand" "0")
4768 (match_operand:TI 2 "general_operand" "do") ) )
4769 (clobber (reg:CC CC_REGNUM))]
4772 "&& reload_completed"
4774 [(set (reg:CCL2 CC_REGNUM)
4775 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4777 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4779 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4780 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4781 (clobber (reg:CC CC_REGNUM))])]
4782 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4783 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4784 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4785 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4786 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4787 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4790 ; subdi3 instruction pattern(s).
4793 (define_expand "subdi3"
4795 [(set (match_operand:DI 0 "register_operand" "")
4796 (minus:DI (match_operand:DI 1 "register_operand" "")
4797 (match_operand:DI 2 "general_operand" "")))
4798 (clobber (reg:CC CC_REGNUM))])]
4802 (define_insn "*subdi3_sign"
4803 [(set (match_operand:DI 0 "register_operand" "=d,d")
4804 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4805 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4806 (clobber (reg:CC CC_REGNUM))]
4811 [(set_attr "op_type" "RRE,RXY")
4812 (set_attr "z10prop" "z10_c,*")
4813 (set_attr "z196prop" "z196_cracked")])
4815 (define_insn "*subdi3_zero_cc"
4816 [(set (reg CC_REGNUM)
4817 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4818 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4820 (set (match_operand:DI 0 "register_operand" "=d,d")
4821 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4822 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4826 [(set_attr "op_type" "RRE,RXY")
4827 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4829 (define_insn "*subdi3_zero_cconly"
4830 [(set (reg CC_REGNUM)
4831 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4832 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4834 (clobber (match_scratch:DI 0 "=d,d"))]
4835 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4839 [(set_attr "op_type" "RRE,RXY")
4840 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4842 (define_insn "*subdi3_zero"
4843 [(set (match_operand:DI 0 "register_operand" "=d,d")
4844 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4845 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4846 (clobber (reg:CC CC_REGNUM))]
4851 [(set_attr "op_type" "RRE,RXY")
4852 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4854 (define_insn_and_split "*subdi3_31z"
4855 [(set (match_operand:DI 0 "register_operand" "=&d")
4856 (minus:DI (match_operand:DI 1 "register_operand" "0")
4857 (match_operand:DI 2 "general_operand" "do") ) )
4858 (clobber (reg:CC CC_REGNUM))]
4859 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4861 "&& reload_completed"
4863 [(set (reg:CCL2 CC_REGNUM)
4864 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4866 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4868 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4869 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4870 (clobber (reg:CC CC_REGNUM))])]
4871 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4872 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4873 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4874 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4875 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4876 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4878 (define_insn_and_split "*subdi3_31"
4879 [(set (match_operand:DI 0 "register_operand" "=&d")
4880 (minus:DI (match_operand:DI 1 "register_operand" "0")
4881 (match_operand:DI 2 "general_operand" "do") ) )
4882 (clobber (reg:CC CC_REGNUM))]
4885 "&& reload_completed"
4887 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4888 (clobber (reg:CC CC_REGNUM))])
4890 [(set (reg:CCL2 CC_REGNUM)
4891 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4893 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4895 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4897 (label_ref (match_dup 9))))
4899 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4900 (clobber (reg:CC CC_REGNUM))])
4902 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4903 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4904 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4905 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4906 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4907 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4908 operands[9] = gen_label_rtx ();")
4911 ; subsi3 instruction pattern(s).
4914 (define_expand "subsi3"
4916 [(set (match_operand:SI 0 "register_operand" "")
4917 (minus:SI (match_operand:SI 1 "register_operand" "")
4918 (match_operand:SI 2 "general_operand" "")))
4919 (clobber (reg:CC CC_REGNUM))])]
4923 (define_insn "*subsi3_sign"
4924 [(set (match_operand:SI 0 "register_operand" "=d,d")
4925 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4926 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4927 (clobber (reg:CC CC_REGNUM))]
4932 [(set_attr "op_type" "RX,RXY")
4933 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4936 ; sub(di|si)3 instruction pattern(s).
4939 ; sr, s, sy, sgr, sg, srk, sgrk
4940 (define_insn "*sub<mode>3"
4941 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4942 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4943 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
4944 (clobber (reg:CC CC_REGNUM))]
4951 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4952 (set_attr "cpu_facility" "*,z196,*,*")
4953 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
4955 ; slr, sl, sly, slgr, slg, slrk, slgrk
4956 (define_insn "*sub<mode>3_borrow_cc"
4957 [(set (reg CC_REGNUM)
4958 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4959 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4961 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4962 (minus:GPR (match_dup 1) (match_dup 2)))]
4963 "s390_match_ccmode (insn, CCL2mode)"
4969 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4970 (set_attr "cpu_facility" "*,z196,*,*")
4971 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
4973 ; slr, sl, sly, slgr, slg, slrk, slgrk
4974 (define_insn "*sub<mode>3_borrow_cconly"
4975 [(set (reg CC_REGNUM)
4976 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4977 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4979 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4980 "s390_match_ccmode (insn, CCL2mode)"
4986 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4987 (set_attr "cpu_facility" "*,z196,*,*")
4988 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
4990 ; slr, sl, sly, slgr, slg, slrk, slgrk
4991 (define_insn "*sub<mode>3_cc"
4992 [(set (reg CC_REGNUM)
4993 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4994 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4996 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4997 (minus:GPR (match_dup 1) (match_dup 2)))]
4998 "s390_match_ccmode (insn, CCLmode)"
5004 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5005 (set_attr "cpu_facility" "*,z196,*,*")
5006 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5008 ; slr, sl, sly, slgr, slg, slrk, slgrk
5009 (define_insn "*sub<mode>3_cc2"
5010 [(set (reg CC_REGNUM)
5011 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5012 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5013 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5014 (minus:GPR (match_dup 1) (match_dup 2)))]
5015 "s390_match_ccmode (insn, CCL3mode)"
5021 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5022 (set_attr "cpu_facility" "*,z196,*,*")
5023 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5025 ; slr, sl, sly, slgr, slg, slrk, slgrk
5026 (define_insn "*sub<mode>3_cconly"
5027 [(set (reg CC_REGNUM)
5028 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5029 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5031 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5032 "s390_match_ccmode (insn, CCLmode)"
5038 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5039 (set_attr "cpu_facility" "*,z196,*,*")
5040 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5043 ; slr, sl, sly, slgr, slg, slrk, slgrk
5044 (define_insn "*sub<mode>3_cconly2"
5045 [(set (reg CC_REGNUM)
5046 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5047 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5048 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5049 "s390_match_ccmode (insn, CCL3mode)"
5055 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5056 (set_attr "cpu_facility" "*,z196,*,*")
5057 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5061 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5064 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5065 (define_insn "sub<mode>3"
5066 [(set (match_operand:FP 0 "register_operand" "=f, f")
5067 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5068 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5069 (clobber (reg:CC CC_REGNUM))]
5072 s<xde><bt>r\t%0,<op1>%2
5074 [(set_attr "op_type" "<RRer>,RXE")
5075 (set_attr "type" "fsimp<mode>")])
5077 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5078 (define_insn "*sub<mode>3_cc"
5079 [(set (reg CC_REGNUM)
5080 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5081 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5082 (match_operand:FP 3 "const0_operand" "")))
5083 (set (match_operand:FP 0 "register_operand" "=f,f")
5084 (minus:FP (match_dup 1) (match_dup 2)))]
5085 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5087 s<xde><bt>r\t%0,<op1>%2
5089 [(set_attr "op_type" "<RRer>,RXE")
5090 (set_attr "type" "fsimp<mode>")])
5092 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5093 (define_insn "*sub<mode>3_cconly"
5094 [(set (reg CC_REGNUM)
5095 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5096 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5097 (match_operand:FP 3 "const0_operand" "")))
5098 (clobber (match_scratch:FP 0 "=f,f"))]
5099 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5101 s<xde><bt>r\t%0,<op1>%2
5103 [(set_attr "op_type" "<RRer>,RXE")
5104 (set_attr "type" "fsimp<mode>")])
5108 ;;- Conditional add/subtract instructions.
5112 ; add(di|si)cc instruction pattern(s).
5115 ; the following 4 patterns are used when the result of an add with
5116 ; carry is checked for an overflow condition
5118 ; op1 + op2 + c < op1
5120 ; alcr, alc, alcgr, alcg
5121 (define_insn "*add<mode>3_alc_carry1_cc"
5122 [(set (reg CC_REGNUM)
5124 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5125 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5126 (match_operand:GPR 2 "general_operand" "d,RT"))
5128 (set (match_operand:GPR 0 "register_operand" "=d,d")
5129 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5130 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5134 [(set_attr "op_type" "RRE,RXY")
5135 (set_attr "z196prop" "z196_alone,z196_alone")])
5137 ; alcr, alc, alcgr, alcg
5138 (define_insn "*add<mode>3_alc_carry1_cconly"
5139 [(set (reg CC_REGNUM)
5141 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5142 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5143 (match_operand:GPR 2 "general_operand" "d,RT"))
5145 (clobber (match_scratch:GPR 0 "=d,d"))]
5146 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5150 [(set_attr "op_type" "RRE,RXY")
5151 (set_attr "z196prop" "z196_alone,z196_alone")])
5153 ; op1 + op2 + c < op2
5155 ; alcr, alc, alcgr, alcg
5156 (define_insn "*add<mode>3_alc_carry2_cc"
5157 [(set (reg CC_REGNUM)
5159 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5160 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5161 (match_operand:GPR 2 "general_operand" "d,RT"))
5163 (set (match_operand:GPR 0 "register_operand" "=d,d")
5164 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5165 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5169 [(set_attr "op_type" "RRE,RXY")])
5171 ; alcr, alc, alcgr, alcg
5172 (define_insn "*add<mode>3_alc_carry2_cconly"
5173 [(set (reg CC_REGNUM)
5175 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5176 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5177 (match_operand:GPR 2 "general_operand" "d,RT"))
5179 (clobber (match_scratch:GPR 0 "=d,d"))]
5180 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5184 [(set_attr "op_type" "RRE,RXY")])
5186 ; alcr, alc, alcgr, alcg
5187 (define_insn "*add<mode>3_alc_cc"
5188 [(set (reg CC_REGNUM)
5190 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5191 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5192 (match_operand:GPR 2 "general_operand" "d,RT"))
5194 (set (match_operand:GPR 0 "register_operand" "=d,d")
5195 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5196 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5200 [(set_attr "op_type" "RRE,RXY")])
5202 ; alcr, alc, alcgr, alcg
5203 (define_insn "*add<mode>3_alc"
5204 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5205 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5206 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5207 (match_operand:GPR 2 "general_operand" "d,RT")))
5208 (clobber (reg:CC CC_REGNUM))]
5213 [(set_attr "op_type" "RRE,RXY")])
5215 ; slbr, slb, slbgr, slbg
5216 (define_insn "*sub<mode>3_slb_cc"
5217 [(set (reg CC_REGNUM)
5219 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5220 (match_operand:GPR 2 "general_operand" "d,RT"))
5221 (match_operand:GPR 3 "s390_slb_comparison" ""))
5223 (set (match_operand:GPR 0 "register_operand" "=d,d")
5224 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5225 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5229 [(set_attr "op_type" "RRE,RXY")
5230 (set_attr "z10prop" "z10_c,*")])
5232 ; slbr, slb, slbgr, slbg
5233 (define_insn "*sub<mode>3_slb"
5234 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5235 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5236 (match_operand:GPR 2 "general_operand" "d,RT"))
5237 (match_operand:GPR 3 "s390_slb_comparison" "")))
5238 (clobber (reg:CC CC_REGNUM))]
5243 [(set_attr "op_type" "RRE,RXY")
5244 (set_attr "z10prop" "z10_c,*")])
5246 (define_expand "add<mode>cc"
5247 [(match_operand:GPR 0 "register_operand" "")
5248 (match_operand 1 "comparison_operator" "")
5249 (match_operand:GPR 2 "register_operand" "")
5250 (match_operand:GPR 3 "const_int_operand" "")]
5252 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5253 XEXP (operands[1], 0), XEXP (operands[1], 1),
5254 operands[0], operands[2],
5255 operands[3])) FAIL; DONE;")
5258 ; scond instruction pattern(s).
5261 (define_insn_and_split "*scond<mode>"
5262 [(set (match_operand:GPR 0 "register_operand" "=&d")
5263 (match_operand:GPR 1 "s390_alc_comparison" ""))
5264 (clobber (reg:CC CC_REGNUM))]
5267 "&& reload_completed"
5268 [(set (match_dup 0) (const_int 0))
5270 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5272 (clobber (reg:CC CC_REGNUM))])]
5275 (define_insn_and_split "*scond<mode>_neg"
5276 [(set (match_operand:GPR 0 "register_operand" "=&d")
5277 (match_operand:GPR 1 "s390_slb_comparison" ""))
5278 (clobber (reg:CC CC_REGNUM))]
5281 "&& reload_completed"
5282 [(set (match_dup 0) (const_int 0))
5284 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5286 (clobber (reg:CC CC_REGNUM))])
5288 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5289 (clobber (reg:CC CC_REGNUM))])]
5293 (define_expand "cstore<mode>4"
5294 [(set (match_operand:SI 0 "register_operand" "")
5295 (match_operator:SI 1 "s390_scond_operator"
5296 [(match_operand:GPR 2 "register_operand" "")
5297 (match_operand:GPR 3 "general_operand" "")]))]
5299 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5300 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5302 (define_expand "cstorecc4"
5304 [(set (match_operand:SI 0 "register_operand" "")
5305 (match_operator:SI 1 "s390_eqne_operator"
5306 [(match_operand:CCZ1 2 "register_operand")
5307 (match_operand 3 "const0_operand")]))
5308 (clobber (reg:CC CC_REGNUM))])]
5310 "emit_insn (gen_sne (operands[0], operands[2]));
5311 if (GET_CODE (operands[1]) == EQ)
5312 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5315 (define_insn_and_split "sne"
5316 [(set (match_operand:SI 0 "register_operand" "=d")
5317 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5319 (clobber (reg:CC CC_REGNUM))]
5324 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5325 (clobber (reg:CC CC_REGNUM))])])
5329 ;; - Conditional move instructions (introduced with z196)
5332 (define_expand "mov<mode>cc"
5333 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5334 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5335 (match_operand:GPR 2 "nonimmediate_operand" "")
5336 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5338 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5339 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5341 ; locr, loc, stoc, locgr, lgoc, stgoc
5342 (define_insn_and_split "*mov<mode>cc"
5343 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5345 (match_operator 1 "s390_comparison"
5346 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5348 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5349 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5359 "&& reload_completed
5360 && MEM_P (operands[3]) && MEM_P (operands[4])"
5363 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5368 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5372 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5375 ;;- Multiply instructions.
5379 ; muldi3 instruction pattern(s).
5382 (define_insn "*muldi3_sign"
5383 [(set (match_operand:DI 0 "register_operand" "=d,d")
5384 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5385 (match_operand:DI 1 "register_operand" "0,0")))]
5390 [(set_attr "op_type" "RRE,RXY")
5391 (set_attr "type" "imuldi")])
5393 (define_insn "muldi3"
5394 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5395 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5396 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5403 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5404 (set_attr "type" "imuldi")
5405 (set_attr "cpu_facility" "*,*,*,z10")])
5408 ; mulsi3 instruction pattern(s).
5411 (define_insn "*mulsi3_sign"
5412 [(set (match_operand:SI 0 "register_operand" "=d,d")
5413 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5414 (match_operand:SI 1 "register_operand" "0,0")))]
5419 [(set_attr "op_type" "RX,RXY")
5420 (set_attr "type" "imulhi")
5421 (set_attr "cpu_facility" "*,z10")])
5423 (define_insn "mulsi3"
5424 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5425 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5426 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5434 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5435 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5436 (set_attr "cpu_facility" "*,*,*,*,z10")])
5439 ; mulsidi3 instruction pattern(s).
5442 (define_insn "mulsidi3"
5443 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5444 (mult:DI (sign_extend:DI
5445 (match_operand:SI 1 "register_operand" "%0,0,0"))
5447 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5453 [(set_attr "op_type" "RR,RX,RXY")
5454 (set_attr "type" "imulsi")
5455 (set_attr "cpu_facility" "*,*,z10")])
5458 ; umulsidi3 instruction pattern(s).
5461 (define_insn "umulsidi3"
5462 [(set (match_operand:DI 0 "register_operand" "=d,d")
5463 (mult:DI (zero_extend:DI
5464 (match_operand:SI 1 "register_operand" "%0,0"))
5466 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5467 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5471 [(set_attr "op_type" "RRE,RXY")
5472 (set_attr "type" "imulsi")])
5475 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5478 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5479 (define_insn "mul<mode>3"
5480 [(set (match_operand:FP 0 "register_operand" "=f,f")
5481 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5482 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5485 m<xdee><bt>r\t%0,<op1>%2
5487 [(set_attr "op_type" "<RRer>,RXE")
5488 (set_attr "type" "fmul<mode>")])
5490 ; madbr, maebr, maxb, madb, maeb
5491 (define_insn "*fmadd<mode>"
5492 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5493 (plus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5494 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5495 (match_operand:DSF 3 "register_operand" "0,0")))]
5496 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5500 [(set_attr "op_type" "RRE,RXE")
5501 (set_attr "type" "fmadd<mode>")])
5503 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5504 (define_insn "*fmsub<mode>"
5505 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5506 (minus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "f,f")
5507 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5508 (match_operand:DSF 3 "register_operand" "0,0")))]
5509 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5513 [(set_attr "op_type" "RRE,RXE")
5514 (set_attr "type" "fmadd<mode>")])
5517 ;;- Divide and modulo instructions.
5521 ; divmoddi4 instruction pattern(s).
5524 (define_expand "divmoddi4"
5525 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5526 (div:DI (match_operand:DI 1 "register_operand" "")
5527 (match_operand:DI 2 "general_operand" "")))
5528 (set (match_operand:DI 3 "general_operand" "")
5529 (mod:DI (match_dup 1) (match_dup 2)))])
5530 (clobber (match_dup 4))]
5533 rtx insn, div_equal, mod_equal;
5535 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5536 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5538 operands[4] = gen_reg_rtx(TImode);
5539 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5541 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5542 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5544 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5545 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5550 (define_insn "divmodtidi3"
5551 [(set (match_operand:TI 0 "register_operand" "=d,d")
5555 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5556 (match_operand:DI 2 "general_operand" "d,RT")))
5558 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5563 [(set_attr "op_type" "RRE,RXY")
5564 (set_attr "type" "idiv")])
5566 (define_insn "divmodtisi3"
5567 [(set (match_operand:TI 0 "register_operand" "=d,d")
5571 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5573 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5576 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5581 [(set_attr "op_type" "RRE,RXY")
5582 (set_attr "type" "idiv")])
5585 ; udivmoddi4 instruction pattern(s).
5588 (define_expand "udivmoddi4"
5589 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5590 (udiv:DI (match_operand:DI 1 "general_operand" "")
5591 (match_operand:DI 2 "nonimmediate_operand" "")))
5592 (set (match_operand:DI 3 "general_operand" "")
5593 (umod:DI (match_dup 1) (match_dup 2)))])
5594 (clobber (match_dup 4))]
5597 rtx insn, div_equal, mod_equal, equal;
5599 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5600 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5601 equal = gen_rtx_IOR (TImode,
5602 gen_rtx_ASHIFT (TImode,
5603 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5605 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5607 operands[4] = gen_reg_rtx(TImode);
5608 emit_clobber (operands[4]);
5609 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5610 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5612 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5613 set_unique_reg_note (insn, REG_EQUAL, equal);
5615 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5616 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5618 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5619 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5624 (define_insn "udivmodtidi3"
5625 [(set (match_operand:TI 0 "register_operand" "=d,d")
5630 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5632 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5636 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5641 [(set_attr "op_type" "RRE,RXY")
5642 (set_attr "type" "idiv")])
5645 ; divmodsi4 instruction pattern(s).
5648 (define_expand "divmodsi4"
5649 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5650 (div:SI (match_operand:SI 1 "general_operand" "")
5651 (match_operand:SI 2 "nonimmediate_operand" "")))
5652 (set (match_operand:SI 3 "general_operand" "")
5653 (mod:SI (match_dup 1) (match_dup 2)))])
5654 (clobber (match_dup 4))]
5657 rtx insn, div_equal, mod_equal, equal;
5659 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5660 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5661 equal = gen_rtx_IOR (DImode,
5662 gen_rtx_ASHIFT (DImode,
5663 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5665 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5667 operands[4] = gen_reg_rtx(DImode);
5668 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5670 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5671 set_unique_reg_note (insn, REG_EQUAL, equal);
5673 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5674 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5676 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5677 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5682 (define_insn "divmoddisi3"
5683 [(set (match_operand:DI 0 "register_operand" "=d,d")
5688 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5690 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5694 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5699 [(set_attr "op_type" "RR,RX")
5700 (set_attr "type" "idiv")])
5703 ; udivsi3 and umodsi3 instruction pattern(s).
5706 (define_expand "udivmodsi4"
5707 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5708 (udiv:SI (match_operand:SI 1 "general_operand" "")
5709 (match_operand:SI 2 "nonimmediate_operand" "")))
5710 (set (match_operand:SI 3 "general_operand" "")
5711 (umod:SI (match_dup 1) (match_dup 2)))])
5712 (clobber (match_dup 4))]
5713 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5715 rtx insn, div_equal, mod_equal, equal;
5717 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5718 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5719 equal = gen_rtx_IOR (DImode,
5720 gen_rtx_ASHIFT (DImode,
5721 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5723 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5725 operands[4] = gen_reg_rtx(DImode);
5726 emit_clobber (operands[4]);
5727 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5728 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5730 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5731 set_unique_reg_note (insn, REG_EQUAL, equal);
5733 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5734 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5736 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5737 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5742 (define_insn "udivmoddisi3"
5743 [(set (match_operand:DI 0 "register_operand" "=d,d")
5748 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5750 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5754 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5755 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5759 [(set_attr "op_type" "RRE,RXY")
5760 (set_attr "type" "idiv")])
5762 (define_expand "udivsi3"
5763 [(set (match_operand:SI 0 "register_operand" "=d")
5764 (udiv:SI (match_operand:SI 1 "general_operand" "")
5765 (match_operand:SI 2 "general_operand" "")))
5766 (clobber (match_dup 3))]
5767 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5769 rtx insn, udiv_equal, umod_equal, equal;
5771 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5772 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5773 equal = gen_rtx_IOR (DImode,
5774 gen_rtx_ASHIFT (DImode,
5775 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5777 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5779 operands[3] = gen_reg_rtx (DImode);
5781 if (CONSTANT_P (operands[2]))
5783 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5785 rtx label1 = gen_label_rtx ();
5787 operands[1] = make_safe_from (operands[1], operands[0]);
5788 emit_move_insn (operands[0], const0_rtx);
5789 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5791 emit_move_insn (operands[0], const1_rtx);
5792 emit_label (label1);
5796 operands[2] = force_reg (SImode, operands[2]);
5797 operands[2] = make_safe_from (operands[2], operands[0]);
5799 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5800 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5802 set_unique_reg_note (insn, REG_EQUAL, equal);
5804 insn = emit_move_insn (operands[0],
5805 gen_lowpart (SImode, operands[3]));
5806 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5811 rtx label1 = gen_label_rtx ();
5812 rtx label2 = gen_label_rtx ();
5813 rtx label3 = gen_label_rtx ();
5815 operands[1] = force_reg (SImode, operands[1]);
5816 operands[1] = make_safe_from (operands[1], operands[0]);
5817 operands[2] = force_reg (SImode, operands[2]);
5818 operands[2] = make_safe_from (operands[2], operands[0]);
5820 emit_move_insn (operands[0], const0_rtx);
5821 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5823 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5825 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5827 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5828 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5830 set_unique_reg_note (insn, REG_EQUAL, equal);
5832 insn = emit_move_insn (operands[0],
5833 gen_lowpart (SImode, operands[3]));
5834 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5837 emit_label (label1);
5838 emit_move_insn (operands[0], operands[1]);
5840 emit_label (label2);
5841 emit_move_insn (operands[0], const1_rtx);
5842 emit_label (label3);
5844 emit_move_insn (operands[0], operands[0]);
5848 (define_expand "umodsi3"
5849 [(set (match_operand:SI 0 "register_operand" "=d")
5850 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5851 (match_operand:SI 2 "nonimmediate_operand" "")))
5852 (clobber (match_dup 3))]
5853 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5855 rtx insn, udiv_equal, umod_equal, equal;
5857 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5858 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5859 equal = gen_rtx_IOR (DImode,
5860 gen_rtx_ASHIFT (DImode,
5861 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5863 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5865 operands[3] = gen_reg_rtx (DImode);
5867 if (CONSTANT_P (operands[2]))
5869 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5871 rtx label1 = gen_label_rtx ();
5873 operands[1] = make_safe_from (operands[1], operands[0]);
5874 emit_move_insn (operands[0], operands[1]);
5875 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5877 emit_insn (gen_abssi2 (operands[0], operands[2]));
5878 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5879 emit_label (label1);
5883 operands[2] = force_reg (SImode, operands[2]);
5884 operands[2] = make_safe_from (operands[2], operands[0]);
5886 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5887 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5889 set_unique_reg_note (insn, REG_EQUAL, equal);
5891 insn = emit_move_insn (operands[0],
5892 gen_highpart (SImode, operands[3]));
5893 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5898 rtx label1 = gen_label_rtx ();
5899 rtx label2 = gen_label_rtx ();
5900 rtx label3 = gen_label_rtx ();
5902 operands[1] = force_reg (SImode, operands[1]);
5903 operands[1] = make_safe_from (operands[1], operands[0]);
5904 operands[2] = force_reg (SImode, operands[2]);
5905 operands[2] = make_safe_from (operands[2], operands[0]);
5907 emit_move_insn(operands[0], operands[1]);
5908 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5910 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5912 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5914 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5915 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5917 set_unique_reg_note (insn, REG_EQUAL, equal);
5919 insn = emit_move_insn (operands[0],
5920 gen_highpart (SImode, operands[3]));
5921 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5924 emit_label (label1);
5925 emit_move_insn (operands[0], const0_rtx);
5927 emit_label (label2);
5928 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5929 emit_label (label3);
5935 ; div(df|sf)3 instruction pattern(s).
5938 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5939 (define_insn "div<mode>3"
5940 [(set (match_operand:FP 0 "register_operand" "=f,f")
5941 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5942 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5945 d<xde><bt>r\t%0,<op1>%2
5947 [(set_attr "op_type" "<RRer>,RXE")
5948 (set_attr "type" "fdiv<mode>")])
5952 ;;- And instructions.
5955 (define_expand "and<mode>3"
5956 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5957 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5958 (match_operand:INT 2 "general_operand" "")))
5959 (clobber (reg:CC CC_REGNUM))]
5961 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5964 ; anddi3 instruction pattern(s).
5967 (define_insn "*anddi3_cc"
5968 [(set (reg CC_REGNUM)
5969 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
5970 (match_operand:DI 2 "general_operand" " d,d,RT"))
5972 (set (match_operand:DI 0 "register_operand" "=d,d, d")
5973 (and:DI (match_dup 1) (match_dup 2)))]
5974 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
5979 [(set_attr "op_type" "RRE,RRF,RXY")
5980 (set_attr "cpu_facility" "*,z196,*")
5981 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
5983 (define_insn "*anddi3_cconly"
5984 [(set (reg CC_REGNUM)
5985 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
5986 (match_operand:DI 2 "general_operand" " d,d,RT"))
5988 (clobber (match_scratch:DI 0 "=d,d, d"))]
5989 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
5990 /* Do not steal TM patterns. */
5991 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5996 [(set_attr "op_type" "RRE,RRF,RXY")
5997 (set_attr "cpu_facility" "*,z196,*")
5998 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6000 (define_insn "*anddi3"
6001 [(set (match_operand:DI 0 "nonimmediate_operand"
6002 "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
6003 (and:DI (match_operand:DI 1 "nonimmediate_operand"
6004 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6005 (match_operand:DI 2 "general_operand"
6006 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
6007 (clobber (reg:CC CC_REGNUM))]
6008 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6023 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6024 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
6025 (set_attr "z10prop" "*,
6040 [(set (match_operand:DI 0 "s_operand" "")
6041 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6042 (clobber (reg:CC CC_REGNUM))]
6045 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6046 (clobber (reg:CC CC_REGNUM))])]
6047 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6051 ; andsi3 instruction pattern(s).
6054 (define_insn "*andsi3_cc"
6055 [(set (reg CC_REGNUM)
6056 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6057 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6059 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6060 (and:SI (match_dup 1) (match_dup 2)))]
6061 "s390_match_ccmode(insn, CCTmode)"
6068 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6069 (set_attr "cpu_facility" "*,*,z196,*,*")
6070 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6072 (define_insn "*andsi3_cconly"
6073 [(set (reg CC_REGNUM)
6074 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6075 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6077 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6078 "s390_match_ccmode(insn, CCTmode)
6079 /* Do not steal TM patterns. */
6080 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6087 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6088 (set_attr "cpu_facility" "*,*,z196,*,*")
6089 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6090 z10_super_E1,z10_super_E1")])
6092 (define_insn "*andsi3_zarch"
6093 [(set (match_operand:SI 0 "nonimmediate_operand"
6094 "=d,d, d, d, d,d,d,d,d, AQ,Q")
6095 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6096 "%d,o, 0, 0, 0,0,d,0,0, 0,0")
6097 (match_operand:SI 2 "general_operand"
6098 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
6099 (clobber (reg:CC CC_REGNUM))]
6100 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6113 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6114 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
6115 (set_attr "z10prop" "*,
6127 (define_insn "*andsi3_esa"
6128 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6129 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6130 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6131 (clobber (reg:CC CC_REGNUM))]
6132 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6138 [(set_attr "op_type" "RR,RX,SI,SS")
6139 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6143 [(set (match_operand:SI 0 "s_operand" "")
6144 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6145 (clobber (reg:CC CC_REGNUM))]
6148 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6149 (clobber (reg:CC CC_REGNUM))])]
6150 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6153 ; andhi3 instruction pattern(s).
6156 (define_insn "*andhi3_zarch"
6157 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6158 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6159 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6160 (clobber (reg:CC CC_REGNUM))]
6161 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6168 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6169 (set_attr "cpu_facility" "*,z196,*,*,*")
6170 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6173 (define_insn "*andhi3_esa"
6174 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6175 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6176 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6177 (clobber (reg:CC CC_REGNUM))]
6178 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6183 [(set_attr "op_type" "RR,SI,SS")
6184 (set_attr "z10prop" "z10_super_E1,*,*")
6188 [(set (match_operand:HI 0 "s_operand" "")
6189 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6190 (clobber (reg:CC CC_REGNUM))]
6193 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6194 (clobber (reg:CC CC_REGNUM))])]
6195 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6198 ; andqi3 instruction pattern(s).
6201 (define_insn "*andqi3_zarch"
6202 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6203 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6204 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6205 (clobber (reg:CC CC_REGNUM))]
6206 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6214 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6215 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6216 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6218 (define_insn "*andqi3_esa"
6219 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6220 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6221 (match_operand:QI 2 "general_operand" "d,n,Q")))
6222 (clobber (reg:CC CC_REGNUM))]
6223 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6228 [(set_attr "op_type" "RR,SI,SS")
6229 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6232 ; Block and (NC) patterns.
6236 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6237 (and:BLK (match_dup 0)
6238 (match_operand:BLK 1 "memory_operand" "Q")))
6239 (use (match_operand 2 "const_int_operand" "n"))
6240 (clobber (reg:CC CC_REGNUM))]
6241 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6242 "nc\t%O0(%2,%R0),%S1"
6243 [(set_attr "op_type" "SS")
6244 (set_attr "z196prop" "z196_cracked")])
6247 [(set (match_operand 0 "memory_operand" "")
6249 (match_operand 1 "memory_operand" "")))
6250 (clobber (reg:CC CC_REGNUM))]
6252 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6253 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6255 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6257 (clobber (reg:CC CC_REGNUM))])]
6259 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6260 operands[0] = adjust_address (operands[0], BLKmode, 0);
6261 operands[1] = adjust_address (operands[1], BLKmode, 0);
6266 [(set (match_operand:BLK 0 "memory_operand" "")
6267 (and:BLK (match_dup 0)
6268 (match_operand:BLK 1 "memory_operand" "")))
6269 (use (match_operand 2 "const_int_operand" ""))
6270 (clobber (reg:CC CC_REGNUM))])
6272 [(set (match_operand:BLK 3 "memory_operand" "")
6273 (and:BLK (match_dup 3)
6274 (match_operand:BLK 4 "memory_operand" "")))
6275 (use (match_operand 5 "const_int_operand" ""))
6276 (clobber (reg:CC CC_REGNUM))])]
6277 "s390_offset_p (operands[0], operands[3], operands[2])
6278 && s390_offset_p (operands[1], operands[4], operands[2])
6279 && !s390_overlap_p (operands[0], operands[1],
6280 INTVAL (operands[2]) + INTVAL (operands[5]))
6281 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6283 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6285 (clobber (reg:CC CC_REGNUM))])]
6286 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6287 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6288 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6292 ;;- Bit set (inclusive or) instructions.
6295 (define_expand "ior<mode>3"
6296 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6297 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6298 (match_operand:INT 2 "general_operand" "")))
6299 (clobber (reg:CC CC_REGNUM))]
6301 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6304 ; iordi3 instruction pattern(s).
6307 (define_insn "*iordi3_cc"
6308 [(set (reg CC_REGNUM)
6309 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6310 (match_operand:DI 2 "general_operand" " d,d,RT"))
6312 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6313 (ior:DI (match_dup 1) (match_dup 2)))]
6314 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6319 [(set_attr "op_type" "RRE,RRF,RXY")
6320 (set_attr "cpu_facility" "*,z196,*")
6321 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6323 (define_insn "*iordi3_cconly"
6324 [(set (reg CC_REGNUM)
6325 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6326 (match_operand:DI 2 "general_operand" " d,d,RT"))
6328 (clobber (match_scratch:DI 0 "=d,d,d"))]
6329 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6334 [(set_attr "op_type" "RRE,RRF,RXY")
6335 (set_attr "cpu_facility" "*,z196,*")
6336 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6338 (define_insn "*iordi3"
6339 [(set (match_operand:DI 0 "nonimmediate_operand"
6340 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6341 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6342 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6343 (match_operand:DI 2 "general_operand"
6344 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6345 (clobber (reg:CC CC_REGNUM))]
6346 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6359 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6360 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6361 (set_attr "z10prop" "z10_super_E1,
6374 [(set (match_operand:DI 0 "s_operand" "")
6375 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6376 (clobber (reg:CC CC_REGNUM))]
6379 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6380 (clobber (reg:CC CC_REGNUM))])]
6381 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6384 ; iorsi3 instruction pattern(s).
6387 (define_insn "*iorsi3_cc"
6388 [(set (reg CC_REGNUM)
6389 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6390 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6392 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6393 (ior:SI (match_dup 1) (match_dup 2)))]
6394 "s390_match_ccmode(insn, CCTmode)"
6401 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6402 (set_attr "cpu_facility" "*,*,z196,*,*")
6403 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6405 (define_insn "*iorsi3_cconly"
6406 [(set (reg CC_REGNUM)
6407 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6408 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6410 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6411 "s390_match_ccmode(insn, CCTmode)"
6418 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6419 (set_attr "cpu_facility" "*,*,z196,*,*")
6420 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6422 (define_insn "*iorsi3_zarch"
6423 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6424 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6425 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6426 (clobber (reg:CC CC_REGNUM))]
6427 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6438 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6439 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6440 (set_attr "z10prop" "z10_super_E1,
6450 (define_insn "*iorsi3_esa"
6451 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6452 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6453 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6454 (clobber (reg:CC CC_REGNUM))]
6455 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6461 [(set_attr "op_type" "RR,RX,SI,SS")
6462 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6465 [(set (match_operand:SI 0 "s_operand" "")
6466 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6467 (clobber (reg:CC CC_REGNUM))]
6470 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6471 (clobber (reg:CC CC_REGNUM))])]
6472 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6475 ; iorhi3 instruction pattern(s).
6478 (define_insn "*iorhi3_zarch"
6479 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6480 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6481 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6482 (clobber (reg:CC CC_REGNUM))]
6483 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6490 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6491 (set_attr "cpu_facility" "*,z196,*,*,*")
6492 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6494 (define_insn "*iorhi3_esa"
6495 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6496 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6497 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6498 (clobber (reg:CC CC_REGNUM))]
6499 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6504 [(set_attr "op_type" "RR,SI,SS")
6505 (set_attr "z10prop" "z10_super_E1,*,*")])
6508 [(set (match_operand:HI 0 "s_operand" "")
6509 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6510 (clobber (reg:CC CC_REGNUM))]
6513 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6514 (clobber (reg:CC CC_REGNUM))])]
6515 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6518 ; iorqi3 instruction pattern(s).
6521 (define_insn "*iorqi3_zarch"
6522 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6523 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6524 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6525 (clobber (reg:CC CC_REGNUM))]
6526 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6534 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6535 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6536 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6537 z10_super,z10_super,*")])
6539 (define_insn "*iorqi3_esa"
6540 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6541 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6542 (match_operand:QI 2 "general_operand" "d,n,Q")))
6543 (clobber (reg:CC CC_REGNUM))]
6544 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6549 [(set_attr "op_type" "RR,SI,SS")
6550 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6553 ; Block inclusive or (OC) patterns.
6557 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6558 (ior:BLK (match_dup 0)
6559 (match_operand:BLK 1 "memory_operand" "Q")))
6560 (use (match_operand 2 "const_int_operand" "n"))
6561 (clobber (reg:CC CC_REGNUM))]
6562 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6563 "oc\t%O0(%2,%R0),%S1"
6564 [(set_attr "op_type" "SS")
6565 (set_attr "z196prop" "z196_cracked")])
6568 [(set (match_operand 0 "memory_operand" "")
6570 (match_operand 1 "memory_operand" "")))
6571 (clobber (reg:CC CC_REGNUM))]
6573 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6574 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6576 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6578 (clobber (reg:CC CC_REGNUM))])]
6580 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6581 operands[0] = adjust_address (operands[0], BLKmode, 0);
6582 operands[1] = adjust_address (operands[1], BLKmode, 0);
6587 [(set (match_operand:BLK 0 "memory_operand" "")
6588 (ior:BLK (match_dup 0)
6589 (match_operand:BLK 1 "memory_operand" "")))
6590 (use (match_operand 2 "const_int_operand" ""))
6591 (clobber (reg:CC CC_REGNUM))])
6593 [(set (match_operand:BLK 3 "memory_operand" "")
6594 (ior:BLK (match_dup 3)
6595 (match_operand:BLK 4 "memory_operand" "")))
6596 (use (match_operand 5 "const_int_operand" ""))
6597 (clobber (reg:CC CC_REGNUM))])]
6598 "s390_offset_p (operands[0], operands[3], operands[2])
6599 && s390_offset_p (operands[1], operands[4], operands[2])
6600 && !s390_overlap_p (operands[0], operands[1],
6601 INTVAL (operands[2]) + INTVAL (operands[5]))
6602 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6604 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6606 (clobber (reg:CC CC_REGNUM))])]
6607 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6608 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6609 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6613 ;;- Xor instructions.
6616 (define_expand "xor<mode>3"
6617 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6618 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6619 (match_operand:INT 2 "general_operand" "")))
6620 (clobber (reg:CC CC_REGNUM))]
6622 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6625 ; xordi3 instruction pattern(s).
6628 (define_insn "*xordi3_cc"
6629 [(set (reg CC_REGNUM)
6630 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6631 (match_operand:DI 2 "general_operand" " d,d,RT"))
6633 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6634 (xor:DI (match_dup 1) (match_dup 2)))]
6635 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6640 [(set_attr "op_type" "RRE,RRF,RXY")
6641 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6643 (define_insn "*xordi3_cconly"
6644 [(set (reg CC_REGNUM)
6645 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6646 (match_operand:DI 2 "general_operand" " d,d,RT"))
6648 (clobber (match_scratch:DI 0 "=d,d, d"))]
6649 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6654 [(set_attr "op_type" "RRE,RRF,RXY")
6655 (set_attr "cpu_facility" "*,z196,*")
6656 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6658 (define_insn "*xordi3"
6659 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6660 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6661 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6662 (clobber (reg:CC CC_REGNUM))]
6663 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6672 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6673 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6674 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6675 *,z10_super_E1,*,*")])
6678 [(set (match_operand:DI 0 "s_operand" "")
6679 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6680 (clobber (reg:CC CC_REGNUM))]
6683 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6684 (clobber (reg:CC CC_REGNUM))])]
6685 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6688 ; xorsi3 instruction pattern(s).
6691 (define_insn "*xorsi3_cc"
6692 [(set (reg CC_REGNUM)
6693 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6694 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6696 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6697 (xor:SI (match_dup 1) (match_dup 2)))]
6698 "s390_match_ccmode(insn, CCTmode)"
6705 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6706 (set_attr "cpu_facility" "*,*,z196,*,*")
6707 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6708 z10_super_E1,z10_super_E1")])
6710 (define_insn "*xorsi3_cconly"
6711 [(set (reg CC_REGNUM)
6712 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6713 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6715 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6716 "s390_match_ccmode(insn, CCTmode)"
6723 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6724 (set_attr "cpu_facility" "*,*,z196,*,*")
6725 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6726 z10_super_E1,z10_super_E1")])
6728 (define_insn "*xorsi3"
6729 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6730 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6731 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6732 (clobber (reg:CC CC_REGNUM))]
6733 "s390_logical_operator_ok_p (operands)"
6742 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6743 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6744 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6745 z10_super_E1,z10_super_E1,*,*")])
6748 [(set (match_operand:SI 0 "s_operand" "")
6749 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6750 (clobber (reg:CC CC_REGNUM))]
6753 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6754 (clobber (reg:CC CC_REGNUM))])]
6755 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6758 ; xorhi3 instruction pattern(s).
6761 (define_insn "*xorhi3"
6762 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6763 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6764 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6765 (clobber (reg:CC CC_REGNUM))]
6766 "s390_logical_operator_ok_p (operands)"
6773 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6774 (set_attr "cpu_facility" "*,*,z196,*,*")
6775 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6778 [(set (match_operand:HI 0 "s_operand" "")
6779 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6780 (clobber (reg:CC CC_REGNUM))]
6783 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6784 (clobber (reg:CC CC_REGNUM))])]
6785 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6788 ; xorqi3 instruction pattern(s).
6791 (define_insn "*xorqi3"
6792 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6793 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
6794 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
6795 (clobber (reg:CC CC_REGNUM))]
6796 "s390_logical_operator_ok_p (operands)"
6804 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
6805 (set_attr "cpu_facility" "*,*,z196,*,*,*")
6806 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
6810 ; Block exclusive or (XC) patterns.
6814 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6815 (xor:BLK (match_dup 0)
6816 (match_operand:BLK 1 "memory_operand" "Q")))
6817 (use (match_operand 2 "const_int_operand" "n"))
6818 (clobber (reg:CC CC_REGNUM))]
6819 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6820 "xc\t%O0(%2,%R0),%S1"
6821 [(set_attr "op_type" "SS")])
6824 [(set (match_operand 0 "memory_operand" "")
6826 (match_operand 1 "memory_operand" "")))
6827 (clobber (reg:CC CC_REGNUM))]
6829 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6830 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6832 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6834 (clobber (reg:CC CC_REGNUM))])]
6836 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6837 operands[0] = adjust_address (operands[0], BLKmode, 0);
6838 operands[1] = adjust_address (operands[1], BLKmode, 0);
6843 [(set (match_operand:BLK 0 "memory_operand" "")
6844 (xor:BLK (match_dup 0)
6845 (match_operand:BLK 1 "memory_operand" "")))
6846 (use (match_operand 2 "const_int_operand" ""))
6847 (clobber (reg:CC CC_REGNUM))])
6849 [(set (match_operand:BLK 3 "memory_operand" "")
6850 (xor:BLK (match_dup 3)
6851 (match_operand:BLK 4 "memory_operand" "")))
6852 (use (match_operand 5 "const_int_operand" ""))
6853 (clobber (reg:CC CC_REGNUM))])]
6854 "s390_offset_p (operands[0], operands[3], operands[2])
6855 && s390_offset_p (operands[1], operands[4], operands[2])
6856 && !s390_overlap_p (operands[0], operands[1],
6857 INTVAL (operands[2]) + INTVAL (operands[5]))
6858 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6860 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6862 (clobber (reg:CC CC_REGNUM))])]
6863 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6864 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6865 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6868 ; Block xor (XC) patterns with src == dest.
6871 (define_insn "*xc_zero"
6872 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6874 (use (match_operand 1 "const_int_operand" "n"))
6875 (clobber (reg:CC CC_REGNUM))]
6876 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6877 "xc\t%O0(%1,%R0),%S0"
6878 [(set_attr "op_type" "SS")
6879 (set_attr "z196prop" "z196_cracked")])
6883 [(set (match_operand:BLK 0 "memory_operand" "")
6885 (use (match_operand 1 "const_int_operand" ""))
6886 (clobber (reg:CC CC_REGNUM))])
6888 [(set (match_operand:BLK 2 "memory_operand" "")
6890 (use (match_operand 3 "const_int_operand" ""))
6891 (clobber (reg:CC CC_REGNUM))])]
6892 "s390_offset_p (operands[0], operands[2], operands[1])
6893 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6895 [(set (match_dup 4) (const_int 0))
6897 (clobber (reg:CC CC_REGNUM))])]
6898 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6899 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6903 ;;- Negate instructions.
6907 ; neg(di|si)2 instruction pattern(s).
6910 (define_expand "neg<mode>2"
6912 [(set (match_operand:DSI 0 "register_operand" "=d")
6913 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6914 (clobber (reg:CC CC_REGNUM))])]
6918 (define_insn "*negdi2_sign_cc"
6919 [(set (reg CC_REGNUM)
6920 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6921 (match_operand:SI 1 "register_operand" "d") 0)
6922 (const_int 32)) (const_int 32)))
6924 (set (match_operand:DI 0 "register_operand" "=d")
6925 (neg:DI (sign_extend:DI (match_dup 1))))]
6926 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6928 [(set_attr "op_type" "RRE")
6929 (set_attr "z10prop" "z10_c")])
6931 (define_insn "*negdi2_sign"
6932 [(set (match_operand:DI 0 "register_operand" "=d")
6933 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6934 (clobber (reg:CC CC_REGNUM))]
6937 [(set_attr "op_type" "RRE")
6938 (set_attr "z10prop" "z10_c")])
6941 (define_insn "*neg<mode>2_cc"
6942 [(set (reg CC_REGNUM)
6943 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6945 (set (match_operand:GPR 0 "register_operand" "=d")
6946 (neg:GPR (match_dup 1)))]
6947 "s390_match_ccmode (insn, CCAmode)"
6949 [(set_attr "op_type" "RR<E>")
6950 (set_attr "z10prop" "z10_super_c_E1")])
6953 (define_insn "*neg<mode>2_cconly"
6954 [(set (reg CC_REGNUM)
6955 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6957 (clobber (match_scratch:GPR 0 "=d"))]
6958 "s390_match_ccmode (insn, CCAmode)"
6960 [(set_attr "op_type" "RR<E>")
6961 (set_attr "z10prop" "z10_super_c_E1")])
6964 (define_insn "*neg<mode>2"
6965 [(set (match_operand:GPR 0 "register_operand" "=d")
6966 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6967 (clobber (reg:CC CC_REGNUM))]
6970 [(set_attr "op_type" "RR<E>")
6971 (set_attr "z10prop" "z10_super_c_E1")])
6973 (define_insn_and_split "*negdi2_31"
6974 [(set (match_operand:DI 0 "register_operand" "=d")
6975 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6976 (clobber (reg:CC CC_REGNUM))]
6979 "&& reload_completed"
6981 [(set (match_dup 2) (neg:SI (match_dup 3)))
6982 (clobber (reg:CC CC_REGNUM))])
6984 [(set (reg:CCAP CC_REGNUM)
6985 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6986 (set (match_dup 4) (neg:SI (match_dup 5)))])
6988 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6990 (label_ref (match_dup 6))))
6992 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6993 (clobber (reg:CC CC_REGNUM))])
6995 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6996 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6997 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6998 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6999 operands[6] = gen_label_rtx ();")
7002 ; neg(df|sf)2 instruction pattern(s).
7005 (define_expand "neg<mode>2"
7007 [(set (match_operand:BFP 0 "register_operand" "=f")
7008 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7009 (clobber (reg:CC CC_REGNUM))])]
7013 ; lcxbr, lcdbr, lcebr
7014 (define_insn "*neg<mode>2_cc"
7015 [(set (reg CC_REGNUM)
7016 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7017 (match_operand:BFP 2 "const0_operand" "")))
7018 (set (match_operand:BFP 0 "register_operand" "=f")
7019 (neg:BFP (match_dup 1)))]
7020 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7022 [(set_attr "op_type" "RRE")
7023 (set_attr "type" "fsimp<mode>")])
7025 ; lcxbr, lcdbr, lcebr
7026 (define_insn "*neg<mode>2_cconly"
7027 [(set (reg CC_REGNUM)
7028 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7029 (match_operand:BFP 2 "const0_operand" "")))
7030 (clobber (match_scratch:BFP 0 "=f"))]
7031 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7033 [(set_attr "op_type" "RRE")
7034 (set_attr "type" "fsimp<mode>")])
7037 (define_insn "*neg<mode>2_nocc"
7038 [(set (match_operand:FP 0 "register_operand" "=f")
7039 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7042 [(set_attr "op_type" "RRE")
7043 (set_attr "type" "fsimp<mode>")])
7045 ; lcxbr, lcdbr, lcebr
7046 (define_insn "*neg<mode>2"
7047 [(set (match_operand:BFP 0 "register_operand" "=f")
7048 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7049 (clobber (reg:CC CC_REGNUM))]
7052 [(set_attr "op_type" "RRE")
7053 (set_attr "type" "fsimp<mode>")])
7057 ;;- Absolute value instructions.
7061 ; abs(di|si)2 instruction pattern(s).
7064 (define_insn "*absdi2_sign_cc"
7065 [(set (reg CC_REGNUM)
7066 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7067 (match_operand:SI 1 "register_operand" "d") 0)
7068 (const_int 32)) (const_int 32)))
7070 (set (match_operand:DI 0 "register_operand" "=d")
7071 (abs:DI (sign_extend:DI (match_dup 1))))]
7072 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7074 [(set_attr "op_type" "RRE")
7075 (set_attr "z10prop" "z10_c")])
7077 (define_insn "*absdi2_sign"
7078 [(set (match_operand:DI 0 "register_operand" "=d")
7079 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7080 (clobber (reg:CC CC_REGNUM))]
7083 [(set_attr "op_type" "RRE")
7084 (set_attr "z10prop" "z10_c")])
7087 (define_insn "*abs<mode>2_cc"
7088 [(set (reg CC_REGNUM)
7089 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7091 (set (match_operand:GPR 0 "register_operand" "=d")
7092 (abs:GPR (match_dup 1)))]
7093 "s390_match_ccmode (insn, CCAmode)"
7095 [(set_attr "op_type" "RR<E>")
7096 (set_attr "z10prop" "z10_c")])
7099 (define_insn "*abs<mode>2_cconly"
7100 [(set (reg CC_REGNUM)
7101 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7103 (clobber (match_scratch:GPR 0 "=d"))]
7104 "s390_match_ccmode (insn, CCAmode)"
7106 [(set_attr "op_type" "RR<E>")
7107 (set_attr "z10prop" "z10_c")])
7110 (define_insn "abs<mode>2"
7111 [(set (match_operand:GPR 0 "register_operand" "=d")
7112 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7113 (clobber (reg:CC CC_REGNUM))]
7116 [(set_attr "op_type" "RR<E>")
7117 (set_attr "z10prop" "z10_c")])
7120 ; abs(df|sf)2 instruction pattern(s).
7123 (define_expand "abs<mode>2"
7125 [(set (match_operand:BFP 0 "register_operand" "=f")
7126 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7127 (clobber (reg:CC CC_REGNUM))])]
7131 ; lpxbr, lpdbr, lpebr
7132 (define_insn "*abs<mode>2_cc"
7133 [(set (reg CC_REGNUM)
7134 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7135 (match_operand:BFP 2 "const0_operand" "")))
7136 (set (match_operand:BFP 0 "register_operand" "=f")
7137 (abs:BFP (match_dup 1)))]
7138 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7140 [(set_attr "op_type" "RRE")
7141 (set_attr "type" "fsimp<mode>")])
7143 ; lpxbr, lpdbr, lpebr
7144 (define_insn "*abs<mode>2_cconly"
7145 [(set (reg CC_REGNUM)
7146 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7147 (match_operand:BFP 2 "const0_operand" "")))
7148 (clobber (match_scratch:BFP 0 "=f"))]
7149 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7151 [(set_attr "op_type" "RRE")
7152 (set_attr "type" "fsimp<mode>")])
7155 (define_insn "*abs<mode>2_nocc"
7156 [(set (match_operand:FP 0 "register_operand" "=f")
7157 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7160 [(set_attr "op_type" "RRE")
7161 (set_attr "type" "fsimp<mode>")])
7163 ; lpxbr, lpdbr, lpebr
7164 (define_insn "*abs<mode>2"
7165 [(set (match_operand:BFP 0 "register_operand" "=f")
7166 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7167 (clobber (reg:CC CC_REGNUM))]
7170 [(set_attr "op_type" "RRE")
7171 (set_attr "type" "fsimp<mode>")])
7175 ;;- Negated absolute value instructions
7182 (define_insn "*negabsdi2_sign_cc"
7183 [(set (reg CC_REGNUM)
7184 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7185 (match_operand:SI 1 "register_operand" "d") 0)
7186 (const_int 32)) (const_int 32))))
7188 (set (match_operand:DI 0 "register_operand" "=d")
7189 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7190 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7192 [(set_attr "op_type" "RRE")
7193 (set_attr "z10prop" "z10_c")])
7195 (define_insn "*negabsdi2_sign"
7196 [(set (match_operand:DI 0 "register_operand" "=d")
7197 (neg:DI (abs:DI (sign_extend:DI
7198 (match_operand:SI 1 "register_operand" "d")))))
7199 (clobber (reg:CC CC_REGNUM))]
7202 [(set_attr "op_type" "RRE")
7203 (set_attr "z10prop" "z10_c")])
7206 (define_insn "*negabs<mode>2_cc"
7207 [(set (reg CC_REGNUM)
7208 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7210 (set (match_operand:GPR 0 "register_operand" "=d")
7211 (neg:GPR (abs:GPR (match_dup 1))))]
7212 "s390_match_ccmode (insn, CCAmode)"
7214 [(set_attr "op_type" "RR<E>")
7215 (set_attr "z10prop" "z10_c")])
7218 (define_insn "*negabs<mode>2_cconly"
7219 [(set (reg CC_REGNUM)
7220 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7222 (clobber (match_scratch:GPR 0 "=d"))]
7223 "s390_match_ccmode (insn, CCAmode)"
7225 [(set_attr "op_type" "RR<E>")
7226 (set_attr "z10prop" "z10_c")])
7229 (define_insn "*negabs<mode>2"
7230 [(set (match_operand:GPR 0 "register_operand" "=d")
7231 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7232 (clobber (reg:CC CC_REGNUM))]
7235 [(set_attr "op_type" "RR<E>")
7236 (set_attr "z10prop" "z10_c")])
7242 ; lnxbr, lndbr, lnebr
7243 (define_insn "*negabs<mode>2_cc"
7244 [(set (reg CC_REGNUM)
7245 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7246 (match_operand:BFP 2 "const0_operand" "")))
7247 (set (match_operand:BFP 0 "register_operand" "=f")
7248 (neg:BFP (abs:BFP (match_dup 1))))]
7249 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7251 [(set_attr "op_type" "RRE")
7252 (set_attr "type" "fsimp<mode>")])
7254 ; lnxbr, lndbr, lnebr
7255 (define_insn "*negabs<mode>2_cconly"
7256 [(set (reg CC_REGNUM)
7257 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7258 (match_operand:BFP 2 "const0_operand" "")))
7259 (clobber (match_scratch:BFP 0 "=f"))]
7260 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7262 [(set_attr "op_type" "RRE")
7263 (set_attr "type" "fsimp<mode>")])
7266 (define_insn "*negabs<mode>2_nocc"
7267 [(set (match_operand:FP 0 "register_operand" "=f")
7268 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7271 [(set_attr "op_type" "RRE")
7272 (set_attr "type" "fsimp<mode>")])
7274 ; lnxbr, lndbr, lnebr
7275 (define_insn "*negabs<mode>2"
7276 [(set (match_operand:BFP 0 "register_operand" "=f")
7277 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7278 (clobber (reg:CC CC_REGNUM))]
7281 [(set_attr "op_type" "RRE")
7282 (set_attr "type" "fsimp<mode>")])
7285 ;;- Square root instructions.
7289 ; sqrt(df|sf)2 instruction pattern(s).
7292 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7293 (define_insn "sqrt<mode>2"
7294 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7295 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7300 [(set_attr "op_type" "RRE,RXE")
7301 (set_attr "type" "fsqrt<mode>")])
7305 ;;- One complement instructions.
7309 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7312 (define_expand "one_cmpl<mode>2"
7314 [(set (match_operand:INT 0 "register_operand" "")
7315 (xor:INT (match_operand:INT 1 "register_operand" "")
7317 (clobber (reg:CC CC_REGNUM))])]
7323 ;; Find leftmost bit instructions.
7326 (define_expand "clzdi2"
7327 [(set (match_operand:DI 0 "register_operand" "=d")
7328 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7329 "TARGET_EXTIMM && TARGET_ZARCH"
7331 rtx insn, clz_equal;
7332 rtx wide_reg = gen_reg_rtx (TImode);
7333 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7335 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7337 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7339 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7340 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7345 (define_insn "clztidi2"
7346 [(set (match_operand:TI 0 "register_operand" "=d")
7350 (xor:DI (match_operand:DI 1 "register_operand" "d")
7351 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7352 (subreg:SI (clz:DI (match_dup 1)) 4))))
7355 (zero_extend:TI (clz:DI (match_dup 1)))))
7356 (clobber (reg:CC CC_REGNUM))]
7357 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7358 == (unsigned HOST_WIDE_INT) 1 << 63
7359 && TARGET_EXTIMM && TARGET_ZARCH"
7361 [(set_attr "op_type" "RRE")])
7365 ;;- Rotate instructions.
7369 ; rotl(di|si)3 instruction pattern(s).
7373 (define_insn "rotl<mode>3"
7374 [(set (match_operand:GPR 0 "register_operand" "=d")
7375 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7376 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7379 [(set_attr "op_type" "RSE")
7380 (set_attr "atype" "reg")
7381 (set_attr "z10prop" "z10_super_E1")])
7384 (define_insn "*rotl<mode>3_and"
7385 [(set (match_operand:GPR 0 "register_operand" "=d")
7386 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7387 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7388 (match_operand:SI 3 "const_int_operand" "n"))))]
7389 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7391 [(set_attr "op_type" "RSE")
7392 (set_attr "atype" "reg")
7393 (set_attr "z10prop" "z10_super_E1")])
7397 ;;- Shift instructions.
7401 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7402 ; Left shifts and logical right shifts
7404 (define_expand "<shift><mode>3"
7405 [(set (match_operand:DSI 0 "register_operand" "")
7406 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7407 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7412 (define_insn "*<shift>di3_31"
7413 [(set (match_operand:DI 0 "register_operand" "=d")
7414 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7415 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7418 [(set_attr "op_type" "RS")
7419 (set_attr "atype" "reg")
7420 (set_attr "z196prop" "z196_cracked")])
7422 ; sll, srl, sllg, srlg, sllk, srlk
7423 (define_insn "*<shift><mode>3"
7424 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7425 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7426 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7429 s<lr>l<g>\t%0,<1>%Y2
7430 s<lr>l<gk>\t%0,%1,%Y2"
7431 [(set_attr "op_type" "RS<E>,RSY")
7432 (set_attr "atype" "reg,reg")
7433 (set_attr "cpu_facility" "*,z196")
7434 (set_attr "z10prop" "z10_super_E1,*")])
7437 (define_insn "*<shift>di3_31_and"
7438 [(set (match_operand:DI 0 "register_operand" "=d")
7439 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7440 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7441 (match_operand:SI 3 "const_int_operand" "n"))))]
7442 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7444 [(set_attr "op_type" "RS")
7445 (set_attr "atype" "reg")])
7447 ; sll, srl, sllg, srlg, sllk, srlk
7448 (define_insn "*<shift><mode>3_and"
7449 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7450 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7451 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7452 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7453 "(INTVAL (operands[3]) & 63) == 63"
7455 s<lr>l<g>\t%0,<1>%Y2
7456 s<lr>l<gk>\t%0,%1,%Y2"
7457 [(set_attr "op_type" "RS<E>,RSY")
7458 (set_attr "atype" "reg,reg")
7459 (set_attr "cpu_facility" "*,z196")
7460 (set_attr "z10prop" "z10_super_E1,*")])
7463 ; ashr(di|si)3 instruction pattern(s).
7464 ; Arithmetic right shifts
7466 (define_expand "ashr<mode>3"
7468 [(set (match_operand:DSI 0 "register_operand" "")
7469 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7470 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7471 (clobber (reg:CC CC_REGNUM))])]
7475 (define_insn "*ashrdi3_cc_31"
7476 [(set (reg CC_REGNUM)
7477 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7478 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7480 (set (match_operand:DI 0 "register_operand" "=d")
7481 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7482 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7484 [(set_attr "op_type" "RS")
7485 (set_attr "atype" "reg")])
7487 (define_insn "*ashrdi3_cconly_31"
7488 [(set (reg CC_REGNUM)
7489 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7490 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7492 (clobber (match_scratch:DI 0 "=d"))]
7493 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7495 [(set_attr "op_type" "RS")
7496 (set_attr "atype" "reg")])
7498 (define_insn "*ashrdi3_31"
7499 [(set (match_operand:DI 0 "register_operand" "=d")
7500 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7501 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7502 (clobber (reg:CC CC_REGNUM))]
7505 [(set_attr "op_type" "RS")
7506 (set_attr "atype" "reg")])
7509 (define_insn "*ashr<mode>3_cc"
7510 [(set (reg CC_REGNUM)
7511 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7512 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7514 (set (match_operand:GPR 0 "register_operand" "=d,d")
7515 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7516 "s390_match_ccmode(insn, CCSmode)"
7520 [(set_attr "op_type" "RS<E>,RSY")
7521 (set_attr "atype" "reg,reg")
7522 (set_attr "cpu_facility" "*,z196")
7523 (set_attr "z10prop" "z10_super_E1,*")])
7526 (define_insn "*ashr<mode>3_cconly"
7527 [(set (reg CC_REGNUM)
7528 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7529 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7531 (clobber (match_scratch:GPR 0 "=d,d"))]
7532 "s390_match_ccmode(insn, CCSmode)"
7536 [(set_attr "op_type" "RS<E>,RSY")
7537 (set_attr "atype" "reg,reg")
7538 (set_attr "cpu_facility" "*,z196")
7539 (set_attr "z10prop" "z10_super_E1,*")])
7542 (define_insn "*ashr<mode>3"
7543 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7544 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7545 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7546 (clobber (reg:CC CC_REGNUM))]
7551 [(set_attr "op_type" "RS<E>,RSY")
7552 (set_attr "atype" "reg,reg")
7553 (set_attr "cpu_facility" "*,z196")
7554 (set_attr "z10prop" "z10_super_E1,*")])
7557 ; shift pattern with implicit ANDs
7559 (define_insn "*ashrdi3_cc_31_and"
7560 [(set (reg CC_REGNUM)
7561 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7562 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7563 (match_operand:SI 3 "const_int_operand" "n")))
7565 (set (match_operand:DI 0 "register_operand" "=d")
7566 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7567 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7568 && (INTVAL (operands[3]) & 63) == 63"
7570 [(set_attr "op_type" "RS")
7571 (set_attr "atype" "reg")])
7573 (define_insn "*ashrdi3_cconly_31_and"
7574 [(set (reg CC_REGNUM)
7575 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7576 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7577 (match_operand:SI 3 "const_int_operand" "n")))
7579 (clobber (match_scratch:DI 0 "=d"))]
7580 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7581 && (INTVAL (operands[3]) & 63) == 63"
7583 [(set_attr "op_type" "RS")
7584 (set_attr "atype" "reg")])
7586 (define_insn "*ashrdi3_31_and"
7587 [(set (match_operand:DI 0 "register_operand" "=d")
7588 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7589 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7590 (match_operand:SI 3 "const_int_operand" "n"))))
7591 (clobber (reg:CC CC_REGNUM))]
7592 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7594 [(set_attr "op_type" "RS")
7595 (set_attr "atype" "reg")])
7598 (define_insn "*ashr<mode>3_cc_and"
7599 [(set (reg CC_REGNUM)
7600 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7601 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7602 (match_operand:SI 3 "const_int_operand" "n,n")))
7604 (set (match_operand:GPR 0 "register_operand" "=d,d")
7605 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7606 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7610 [(set_attr "op_type" "RS<E>,RSY")
7611 (set_attr "atype" "reg,reg")
7612 (set_attr "cpu_facility" "*,z196")
7613 (set_attr "z10prop" "z10_super_E1,*")])
7616 (define_insn "*ashr<mode>3_cconly_and"
7617 [(set (reg CC_REGNUM)
7618 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7619 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7620 (match_operand:SI 3 "const_int_operand" "n,n")))
7622 (clobber (match_scratch:GPR 0 "=d,d"))]
7623 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7627 [(set_attr "op_type" "RS<E>,RSY")
7628 (set_attr "atype" "reg,reg")
7629 (set_attr "cpu_facility" "*,z196")
7630 (set_attr "z10prop" "z10_super_E1,*")])
7633 (define_insn "*ashr<mode>3_and"
7634 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7635 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7636 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7637 (match_operand:SI 3 "const_int_operand" "n,n"))))
7638 (clobber (reg:CC CC_REGNUM))]
7639 "(INTVAL (operands[3]) & 63) == 63"
7643 [(set_attr "op_type" "RS<E>,RSY")
7644 (set_attr "atype" "reg,reg")
7645 (set_attr "z10prop" "z10_super_E1,*")])
7649 ;; Branch instruction patterns.
7652 (define_expand "cbranch<mode>4"
7654 (if_then_else (match_operator 0 "comparison_operator"
7655 [(match_operand:GPR 1 "register_operand" "")
7656 (match_operand:GPR 2 "general_operand" "")])
7657 (label_ref (match_operand 3 "" ""))
7660 "s390_emit_jump (operands[3],
7661 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7664 (define_expand "cbranch<mode>4"
7666 (if_then_else (match_operator 0 "comparison_operator"
7667 [(match_operand:FP 1 "register_operand" "")
7668 (match_operand:FP 2 "general_operand" "")])
7669 (label_ref (match_operand 3 "" ""))
7672 "s390_emit_jump (operands[3],
7673 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7676 (define_expand "cbranchcc4"
7678 (if_then_else (match_operator 0 "s390_eqne_operator"
7679 [(match_operand 1 "cc_reg_operand" "")
7680 (match_operand 2 "const0_operand" "")])
7681 (label_ref (match_operand 3 "" ""))
7684 "s390_emit_jump (operands[3],
7685 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7691 ;;- Conditional jump instructions.
7694 (define_insn "*cjump_64"
7697 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7698 (label_ref (match_operand 0 "" ""))
7702 if (get_attr_length (insn) == 4)
7705 return "jg%C1\t%l0";
7707 [(set_attr "op_type" "RI")
7708 (set_attr "type" "branch")
7709 (set (attr "length")
7710 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7711 (const_int 4) (const_int 6)))])
7713 (define_insn "*cjump_31"
7716 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7717 (label_ref (match_operand 0 "" ""))
7721 gcc_assert (get_attr_length (insn) == 4);
7724 [(set_attr "op_type" "RI")
7725 (set_attr "type" "branch")
7726 (set (attr "length")
7727 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7728 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7729 (const_int 4) (const_int 6))
7730 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7731 (const_int 4) (const_int 8))))])
7733 (define_insn "*cjump_long"
7736 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7737 (match_operand 0 "address_operand" "ZQZR")
7741 if (get_attr_op_type (insn) == OP_TYPE_RR)
7746 [(set (attr "op_type")
7747 (if_then_else (match_operand 0 "register_operand" "")
7748 (const_string "RR") (const_string "RX")))
7749 (set_attr "type" "branch")
7750 (set_attr "atype" "agen")])
7754 ;;- Negated conditional jump instructions.
7757 (define_insn "*icjump_64"
7760 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7762 (label_ref (match_operand 0 "" ""))))]
7765 if (get_attr_length (insn) == 4)
7768 return "jg%D1\t%l0";
7770 [(set_attr "op_type" "RI")
7771 (set_attr "type" "branch")
7772 (set (attr "length")
7773 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7774 (const_int 4) (const_int 6)))])
7776 (define_insn "*icjump_31"
7779 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7781 (label_ref (match_operand 0 "" ""))))]
7784 gcc_assert (get_attr_length (insn) == 4);
7787 [(set_attr "op_type" "RI")
7788 (set_attr "type" "branch")
7789 (set (attr "length")
7790 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7791 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7792 (const_int 4) (const_int 6))
7793 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7794 (const_int 4) (const_int 8))))])
7796 (define_insn "*icjump_long"
7799 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7801 (match_operand 0 "address_operand" "ZQZR")))]
7804 if (get_attr_op_type (insn) == OP_TYPE_RR)
7809 [(set (attr "op_type")
7810 (if_then_else (match_operand 0 "register_operand" "")
7811 (const_string "RR") (const_string "RX")))
7812 (set_attr "type" "branch")
7813 (set_attr "atype" "agen")])
7816 ;;- Trap instructions.
7820 [(trap_if (const_int 1) (const_int 0))]
7823 [(set_attr "op_type" "RI")
7824 (set_attr "type" "branch")])
7826 (define_expand "ctrap<mode>4"
7827 [(trap_if (match_operator 0 "comparison_operator"
7828 [(match_operand:GPR 1 "register_operand" "")
7829 (match_operand:GPR 2 "general_operand" "")])
7830 (match_operand 3 "const0_operand" ""))]
7833 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7834 operands[1], operands[2]);
7835 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7839 (define_expand "ctrap<mode>4"
7840 [(trap_if (match_operator 0 "comparison_operator"
7841 [(match_operand:FP 1 "register_operand" "")
7842 (match_operand:FP 2 "general_operand" "")])
7843 (match_operand 3 "const0_operand" ""))]
7846 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7847 operands[1], operands[2]);
7848 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7852 (define_insn "condtrap"
7853 [(trap_if (match_operator 0 "s390_comparison"
7854 [(match_operand 1 "cc_reg_operand" "c")
7859 [(set_attr "op_type" "RI")
7860 (set_attr "type" "branch")])
7862 ; crt, cgrt, cit, cgit
7863 (define_insn "*cmp_and_trap_signed_int<mode>"
7864 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7865 [(match_operand:GPR 1 "register_operand" "d,d")
7866 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7872 [(set_attr "op_type" "RRF,RIE")
7873 (set_attr "type" "branch")
7874 (set_attr "z10prop" "z10_super_c,z10_super")])
7876 ; clrt, clgrt, clfit, clgit
7877 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7878 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7879 [(match_operand:GPR 1 "register_operand" "d,d")
7880 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7885 cl<gf>it%C0\t%1,%x2"
7886 [(set_attr "op_type" "RRF,RIE")
7887 (set_attr "type" "branch")
7888 (set_attr "z10prop" "z10_super_c,z10_super")])
7891 ;;- Loop instructions.
7893 ;; This is all complicated by the fact that since this is a jump insn
7894 ;; we must handle our own output reloads.
7898 ; This splitter will be matched by combine and has to add the 2 moves
7899 ; necessary to load the compare and the increment values into a
7900 ; register pair as needed by brxle.
7902 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7905 (match_operator 6 "s390_brx_operator"
7906 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
7907 (match_operand:GPR 2 "general_operand" ""))
7908 (match_operand:GPR 3 "register_operand" "")])
7909 (label_ref (match_operand 0 "" ""))
7911 (set (match_operand:GPR 4 "nonimmediate_operand" "")
7912 (plus:GPR (match_dup 1) (match_dup 2)))
7913 (clobber (match_scratch:GPR 5 ""))]
7916 "!reload_completed && !reload_in_progress"
7917 [(set (match_dup 7) (match_dup 2)) ; the increment
7918 (set (match_dup 8) (match_dup 3)) ; the comparison value
7919 (parallel [(set (pc)
7922 [(plus:GPR (match_dup 1) (match_dup 7))
7924 (label_ref (match_dup 0))
7927 (plus:GPR (match_dup 1) (match_dup 7)))
7928 (clobber (match_dup 5))
7929 (clobber (reg:CC CC_REGNUM))])]
7931 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
7932 operands[7] = gen_lowpart (<GPR:MODE>mode,
7933 gen_highpart (word_mode, dreg));
7934 operands[8] = gen_lowpart (<GPR:MODE>mode,
7935 gen_lowpart (word_mode, dreg));
7940 (define_insn_and_split "*brxg_64bit"
7943 (match_operator 5 "s390_brx_operator"
7944 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
7945 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
7946 (subreg:DI (match_dup 2) 8)])
7947 (label_ref (match_operand 0 "" ""))
7949 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
7950 (plus:DI (match_dup 1)
7951 (subreg:DI (match_dup 2) 0)))
7952 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
7953 (clobber (reg:CC CC_REGNUM))]
7956 if (which_alternative != 0)
7958 else if (get_attr_length (insn) == 6)
7959 return "brx%E5g\t%1,%2,%l0";
7961 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
7963 "&& reload_completed
7964 && (!REG_P (operands[3])
7965 || !rtx_equal_p (operands[1], operands[3]))"
7966 [(set (match_dup 4) (match_dup 1))
7967 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
7968 (clobber (reg:CC CC_REGNUM))])
7969 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
7970 (set (match_dup 3) (match_dup 4))
7971 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7972 (label_ref (match_dup 0))
7975 [(set_attr "op_type" "RIE")
7976 (set_attr "type" "branch")
7977 (set (attr "length")
7978 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7979 (const_int 6) (const_int 16)))])
7983 (define_insn_and_split "*brx_64bit"
7986 (match_operator 5 "s390_brx_operator"
7987 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7988 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
7989 (subreg:SI (match_dup 2) 12)])
7990 (label_ref (match_operand 0 "" ""))
7992 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7993 (plus:SI (match_dup 1)
7994 (subreg:SI (match_dup 2) 4)))
7995 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7996 (clobber (reg:CC CC_REGNUM))]
7999 if (which_alternative != 0)
8001 else if (get_attr_length (insn) == 6)
8002 return "brx%C5\t%1,%2,%l0";
8004 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8006 "&& reload_completed
8007 && (!REG_P (operands[3])
8008 || !rtx_equal_p (operands[1], operands[3]))"
8009 [(set (match_dup 4) (match_dup 1))
8010 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8011 (clobber (reg:CC CC_REGNUM))])
8012 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8013 (set (match_dup 3) (match_dup 4))
8014 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8015 (label_ref (match_dup 0))
8018 [(set_attr "op_type" "RSI")
8019 (set_attr "type" "branch")
8020 (set (attr "length")
8021 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8022 (const_int 6) (const_int 14)))])
8026 (define_insn_and_split "*brx_31bit"
8029 (match_operator 5 "s390_brx_operator"
8030 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8031 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8032 (subreg:SI (match_dup 2) 4)])
8033 (label_ref (match_operand 0 "" ""))
8035 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8036 (plus:SI (match_dup 1)
8037 (subreg:SI (match_dup 2) 0)))
8038 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8039 (clobber (reg:CC CC_REGNUM))]
8040 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8042 if (which_alternative != 0)
8044 else if (get_attr_length (insn) == 6)
8045 return "brx%C5\t%1,%2,%l0";
8047 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8049 "&& reload_completed
8050 && (!REG_P (operands[3])
8051 || !rtx_equal_p (operands[1], operands[3]))"
8052 [(set (match_dup 4) (match_dup 1))
8053 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8054 (clobber (reg:CC CC_REGNUM))])
8055 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8056 (set (match_dup 3) (match_dup 4))
8057 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8058 (label_ref (match_dup 0))
8061 [(set_attr "op_type" "RSI")
8062 (set_attr "type" "branch")
8063 (set (attr "length")
8064 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8065 (const_int 6) (const_int 14)))])
8070 (define_expand "doloop_end"
8071 [(use (match_operand 0 "" "")) ; loop pseudo
8072 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8073 (use (match_operand 2 "" "")) ; max iterations
8074 (use (match_operand 3 "" "")) ; loop level
8075 (use (match_operand 4 "" ""))] ; label
8078 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8079 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8080 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8081 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8082 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8083 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8090 (define_insn_and_split "doloop_si64"
8093 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8095 (label_ref (match_operand 0 "" ""))
8097 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8098 (plus:SI (match_dup 1) (const_int -1)))
8099 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8100 (clobber (reg:CC CC_REGNUM))]
8103 if (which_alternative != 0)
8105 else if (get_attr_length (insn) == 4)
8106 return "brct\t%1,%l0";
8108 return "ahi\t%1,-1\;jgne\t%l0";
8110 "&& reload_completed
8111 && (! REG_P (operands[2])
8112 || ! rtx_equal_p (operands[1], operands[2]))"
8113 [(set (match_dup 3) (match_dup 1))
8114 (parallel [(set (reg:CCAN CC_REGNUM)
8115 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8117 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8118 (set (match_dup 2) (match_dup 3))
8119 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8120 (label_ref (match_dup 0))
8123 [(set_attr "op_type" "RI")
8124 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8125 ; hurt us in the (rare) case of ahi.
8126 (set_attr "z10prop" "z10_super_E1")
8127 (set_attr "type" "branch")
8128 (set (attr "length")
8129 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8130 (const_int 4) (const_int 10)))])
8132 (define_insn_and_split "doloop_si31"
8135 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8137 (label_ref (match_operand 0 "" ""))
8139 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8140 (plus:SI (match_dup 1) (const_int -1)))
8141 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8142 (clobber (reg:CC CC_REGNUM))]
8145 if (which_alternative != 0)
8147 else if (get_attr_length (insn) == 4)
8148 return "brct\t%1,%l0";
8152 "&& reload_completed
8153 && (! REG_P (operands[2])
8154 || ! rtx_equal_p (operands[1], operands[2]))"
8155 [(set (match_dup 3) (match_dup 1))
8156 (parallel [(set (reg:CCAN CC_REGNUM)
8157 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8159 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8160 (set (match_dup 2) (match_dup 3))
8161 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8162 (label_ref (match_dup 0))
8165 [(set_attr "op_type" "RI")
8166 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8167 ; hurt us in the (rare) case of ahi.
8168 (set_attr "z10prop" "z10_super_E1")
8169 (set_attr "type" "branch")
8170 (set (attr "length")
8171 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
8172 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8173 (const_int 4) (const_int 6))
8174 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8175 (const_int 4) (const_int 8))))])
8177 (define_insn "*doloop_si_long"
8180 (ne (match_operand:SI 1 "register_operand" "d")
8182 (match_operand 0 "address_operand" "ZQZR")
8184 (set (match_operand:SI 2 "register_operand" "=1")
8185 (plus:SI (match_dup 1) (const_int -1)))
8186 (clobber (match_scratch:SI 3 "=X"))
8187 (clobber (reg:CC CC_REGNUM))]
8190 if (get_attr_op_type (insn) == OP_TYPE_RR)
8191 return "bctr\t%1,%0";
8193 return "bct\t%1,%a0";
8195 [(set (attr "op_type")
8196 (if_then_else (match_operand 0 "register_operand" "")
8197 (const_string "RR") (const_string "RX")))
8198 (set_attr "type" "branch")
8199 (set_attr "atype" "agen")
8200 (set_attr "z10prop" "z10_c")
8201 (set_attr "z196prop" "z196_cracked")])
8203 (define_insn_and_split "doloop_di"
8206 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8208 (label_ref (match_operand 0 "" ""))
8210 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8211 (plus:DI (match_dup 1) (const_int -1)))
8212 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8213 (clobber (reg:CC CC_REGNUM))]
8216 if (which_alternative != 0)
8218 else if (get_attr_length (insn) == 4)
8219 return "brctg\t%1,%l0";
8221 return "aghi\t%1,-1\;jgne\t%l0";
8223 "&& reload_completed
8224 && (! REG_P (operands[2])
8225 || ! rtx_equal_p (operands[1], operands[2]))"
8226 [(set (match_dup 3) (match_dup 1))
8227 (parallel [(set (reg:CCAN CC_REGNUM)
8228 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8230 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8231 (set (match_dup 2) (match_dup 3))
8232 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8233 (label_ref (match_dup 0))
8236 [(set_attr "op_type" "RI")
8237 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8238 ; hurt us in the (rare) case of ahi.
8239 (set_attr "z10prop" "z10_super_E1")
8240 (set_attr "type" "branch")
8241 (set (attr "length")
8242 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8243 (const_int 4) (const_int 10)))])
8246 ;;- Unconditional jump instructions.
8250 ; jump instruction pattern(s).
8253 (define_expand "jump"
8254 [(match_operand 0 "" "")]
8256 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8258 (define_insn "*jump64"
8259 [(set (pc) (label_ref (match_operand 0 "" "")))]
8262 if (get_attr_length (insn) == 4)
8267 [(set_attr "op_type" "RI")
8268 (set_attr "type" "branch")
8269 (set (attr "length")
8270 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8271 (const_int 4) (const_int 6)))])
8273 (define_insn "*jump31"
8274 [(set (pc) (label_ref (match_operand 0 "" "")))]
8277 gcc_assert (get_attr_length (insn) == 4);
8280 [(set_attr "op_type" "RI")
8281 (set_attr "type" "branch")
8282 (set (attr "length")
8283 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
8284 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8285 (const_int 4) (const_int 6))
8286 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8287 (const_int 4) (const_int 8))))])
8290 ; indirect-jump instruction pattern(s).
8293 (define_insn "indirect_jump"
8294 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8297 if (get_attr_op_type (insn) == OP_TYPE_RR)
8302 [(set (attr "op_type")
8303 (if_then_else (match_operand 0 "register_operand" "")
8304 (const_string "RR") (const_string "RX")))
8305 (set_attr "type" "branch")
8306 (set_attr "atype" "agen")])
8309 ; casesi instruction pattern(s).
8312 (define_insn "casesi_jump"
8313 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8314 (use (label_ref (match_operand 1 "" "")))]
8317 if (get_attr_op_type (insn) == OP_TYPE_RR)
8322 [(set (attr "op_type")
8323 (if_then_else (match_operand 0 "register_operand" "")
8324 (const_string "RR") (const_string "RX")))
8325 (set_attr "type" "branch")
8326 (set_attr "atype" "agen")])
8328 (define_expand "casesi"
8329 [(match_operand:SI 0 "general_operand" "")
8330 (match_operand:SI 1 "general_operand" "")
8331 (match_operand:SI 2 "general_operand" "")
8332 (label_ref (match_operand 3 "" ""))
8333 (label_ref (match_operand 4 "" ""))]
8336 rtx index = gen_reg_rtx (SImode);
8337 rtx base = gen_reg_rtx (Pmode);
8338 rtx target = gen_reg_rtx (Pmode);
8340 emit_move_insn (index, operands[0]);
8341 emit_insn (gen_subsi3 (index, index, operands[1]));
8342 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8345 if (Pmode != SImode)
8346 index = convert_to_mode (Pmode, index, 1);
8347 if (GET_CODE (index) != REG)
8348 index = copy_to_mode_reg (Pmode, index);
8351 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8353 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8355 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8357 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8358 emit_move_insn (target, index);
8361 target = gen_rtx_PLUS (Pmode, base, target);
8362 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8369 ;;- Jump to subroutine.
8374 ; untyped call instruction pattern(s).
8377 ;; Call subroutine returning any type.
8378 (define_expand "untyped_call"
8379 [(parallel [(call (match_operand 0 "" "")
8381 (match_operand 1 "" "")
8382 (match_operand 2 "" "")])]
8387 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8389 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8391 rtx set = XVECEXP (operands[2], 0, i);
8392 emit_move_insn (SET_DEST (set), SET_SRC (set));
8395 /* The optimizer does not know that the call sets the function value
8396 registers we stored in the result block. We avoid problems by
8397 claiming that all hard registers are used and clobbered at this
8399 emit_insn (gen_blockage ());
8404 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8405 ;; all of memory. This blocks insns from being moved across this point.
8407 (define_insn "blockage"
8408 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8411 [(set_attr "type" "none")
8412 (set_attr "length" "0")])
8418 (define_expand "sibcall"
8419 [(call (match_operand 0 "" "")
8420 (match_operand 1 "" ""))]
8423 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8427 (define_insn "*sibcall_br"
8428 [(call (mem:QI (reg SIBCALL_REGNUM))
8429 (match_operand 0 "const_int_operand" "n"))]
8430 "SIBLING_CALL_P (insn)
8431 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8433 [(set_attr "op_type" "RR")
8434 (set_attr "type" "branch")
8435 (set_attr "atype" "agen")])
8437 (define_insn "*sibcall_brc"
8438 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8439 (match_operand 1 "const_int_operand" "n"))]
8440 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8442 [(set_attr "op_type" "RI")
8443 (set_attr "type" "branch")])
8445 (define_insn "*sibcall_brcl"
8446 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8447 (match_operand 1 "const_int_operand" "n"))]
8448 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8450 [(set_attr "op_type" "RIL")
8451 (set_attr "type" "branch")])
8454 ; sibcall_value patterns
8457 (define_expand "sibcall_value"
8458 [(set (match_operand 0 "" "")
8459 (call (match_operand 1 "" "")
8460 (match_operand 2 "" "")))]
8463 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8467 (define_insn "*sibcall_value_br"
8468 [(set (match_operand 0 "" "")
8469 (call (mem:QI (reg SIBCALL_REGNUM))
8470 (match_operand 1 "const_int_operand" "n")))]
8471 "SIBLING_CALL_P (insn)
8472 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8474 [(set_attr "op_type" "RR")
8475 (set_attr "type" "branch")
8476 (set_attr "atype" "agen")])
8478 (define_insn "*sibcall_value_brc"
8479 [(set (match_operand 0 "" "")
8480 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8481 (match_operand 2 "const_int_operand" "n")))]
8482 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8484 [(set_attr "op_type" "RI")
8485 (set_attr "type" "branch")])
8487 (define_insn "*sibcall_value_brcl"
8488 [(set (match_operand 0 "" "")
8489 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8490 (match_operand 2 "const_int_operand" "n")))]
8491 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8493 [(set_attr "op_type" "RIL")
8494 (set_attr "type" "branch")])
8498 ; call instruction pattern(s).
8501 (define_expand "call"
8502 [(call (match_operand 0 "" "")
8503 (match_operand 1 "" ""))
8504 (use (match_operand 2 "" ""))]
8507 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8508 gen_rtx_REG (Pmode, RETURN_REGNUM));
8512 (define_insn "*bras"
8513 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8514 (match_operand 1 "const_int_operand" "n"))
8515 (clobber (match_operand 2 "register_operand" "=r"))]
8516 "!SIBLING_CALL_P (insn)
8517 && TARGET_SMALL_EXEC
8518 && GET_MODE (operands[2]) == Pmode"
8520 [(set_attr "op_type" "RI")
8521 (set_attr "type" "jsr")
8522 (set_attr "z196prop" "z196_cracked")])
8524 (define_insn "*brasl"
8525 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8526 (match_operand 1 "const_int_operand" "n"))
8527 (clobber (match_operand 2 "register_operand" "=r"))]
8528 "!SIBLING_CALL_P (insn)
8530 && GET_MODE (operands[2]) == Pmode"
8532 [(set_attr "op_type" "RIL")
8533 (set_attr "type" "jsr")
8534 (set_attr "z196prop" "z196_cracked")])
8536 (define_insn "*basr"
8537 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8538 (match_operand 1 "const_int_operand" "n"))
8539 (clobber (match_operand 2 "register_operand" "=r"))]
8540 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8542 if (get_attr_op_type (insn) == OP_TYPE_RR)
8543 return "basr\t%2,%0";
8545 return "bas\t%2,%a0";
8547 [(set (attr "op_type")
8548 (if_then_else (match_operand 0 "register_operand" "")
8549 (const_string "RR") (const_string "RX")))
8550 (set_attr "type" "jsr")
8551 (set_attr "atype" "agen")
8552 (set_attr "z196prop" "z196_cracked")])
8555 ; call_value instruction pattern(s).
8558 (define_expand "call_value"
8559 [(set (match_operand 0 "" "")
8560 (call (match_operand 1 "" "")
8561 (match_operand 2 "" "")))
8562 (use (match_operand 3 "" ""))]
8565 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8566 gen_rtx_REG (Pmode, RETURN_REGNUM));
8570 (define_insn "*bras_r"
8571 [(set (match_operand 0 "" "")
8572 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8573 (match_operand:SI 2 "const_int_operand" "n")))
8574 (clobber (match_operand 3 "register_operand" "=r"))]
8575 "!SIBLING_CALL_P (insn)
8576 && TARGET_SMALL_EXEC
8577 && GET_MODE (operands[3]) == Pmode"
8579 [(set_attr "op_type" "RI")
8580 (set_attr "type" "jsr")
8581 (set_attr "z196prop" "z196_cracked")])
8583 (define_insn "*brasl_r"
8584 [(set (match_operand 0 "" "")
8585 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8586 (match_operand 2 "const_int_operand" "n")))
8587 (clobber (match_operand 3 "register_operand" "=r"))]
8588 "!SIBLING_CALL_P (insn)
8590 && GET_MODE (operands[3]) == Pmode"
8592 [(set_attr "op_type" "RIL")
8593 (set_attr "type" "jsr")
8594 (set_attr "z196prop" "z196_cracked")])
8596 (define_insn "*basr_r"
8597 [(set (match_operand 0 "" "")
8598 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8599 (match_operand 2 "const_int_operand" "n")))
8600 (clobber (match_operand 3 "register_operand" "=r"))]
8601 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8603 if (get_attr_op_type (insn) == OP_TYPE_RR)
8604 return "basr\t%3,%1";
8606 return "bas\t%3,%a1";
8608 [(set (attr "op_type")
8609 (if_then_else (match_operand 1 "register_operand" "")
8610 (const_string "RR") (const_string "RX")))
8611 (set_attr "type" "jsr")
8612 (set_attr "atype" "agen")
8613 (set_attr "z196prop" "z196_cracked")])
8616 ;;- Thread-local storage support.
8619 (define_expand "get_tp_64"
8620 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8624 (define_expand "get_tp_31"
8625 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8629 (define_expand "set_tp_64"
8630 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8631 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8635 (define_expand "set_tp_31"
8636 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8637 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8641 (define_insn "*set_tp"
8642 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8645 [(set_attr "type" "none")
8646 (set_attr "length" "0")])
8648 (define_insn "*tls_load_64"
8649 [(set (match_operand:DI 0 "register_operand" "=d")
8650 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8651 (match_operand:DI 2 "" "")]
8655 [(set_attr "op_type" "RXE")
8656 (set_attr "z10prop" "z10_fwd_A3")])
8658 (define_insn "*tls_load_31"
8659 [(set (match_operand:SI 0 "register_operand" "=d,d")
8660 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8661 (match_operand:SI 2 "" "")]
8667 [(set_attr "op_type" "RX,RXY")
8668 (set_attr "type" "load")
8669 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8671 (define_insn "*bras_tls"
8672 [(set (match_operand 0 "" "")
8673 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8674 (match_operand 2 "const_int_operand" "n")))
8675 (clobber (match_operand 3 "register_operand" "=r"))
8676 (use (match_operand 4 "" ""))]
8677 "!SIBLING_CALL_P (insn)
8678 && TARGET_SMALL_EXEC
8679 && GET_MODE (operands[3]) == Pmode"
8681 [(set_attr "op_type" "RI")
8682 (set_attr "type" "jsr")
8683 (set_attr "z196prop" "z196_cracked")])
8685 (define_insn "*brasl_tls"
8686 [(set (match_operand 0 "" "")
8687 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8688 (match_operand 2 "const_int_operand" "n")))
8689 (clobber (match_operand 3 "register_operand" "=r"))
8690 (use (match_operand 4 "" ""))]
8691 "!SIBLING_CALL_P (insn)
8693 && GET_MODE (operands[3]) == Pmode"
8695 [(set_attr "op_type" "RIL")
8696 (set_attr "type" "jsr")
8697 (set_attr "z196prop" "z196_cracked")])
8699 (define_insn "*basr_tls"
8700 [(set (match_operand 0 "" "")
8701 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8702 (match_operand 2 "const_int_operand" "n")))
8703 (clobber (match_operand 3 "register_operand" "=r"))
8704 (use (match_operand 4 "" ""))]
8705 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8707 if (get_attr_op_type (insn) == OP_TYPE_RR)
8708 return "basr\t%3,%1%J4";
8710 return "bas\t%3,%a1%J4";
8712 [(set (attr "op_type")
8713 (if_then_else (match_operand 1 "register_operand" "")
8714 (const_string "RR") (const_string "RX")))
8715 (set_attr "type" "jsr")
8716 (set_attr "atype" "agen")
8717 (set_attr "z196prop" "z196_cracked")])
8720 ;;- Atomic operations
8724 ; memory barrier pattern.
8727 (define_expand "memory_barrier"
8729 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8732 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8733 MEM_VOLATILE_P (operands[0]) = 1;
8736 (define_insn "*memory_barrier"
8737 [(set (match_operand:BLK 0 "" "")
8738 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8741 [(set_attr "op_type" "RR")])
8743 ; Although bcr is superscalar on Z10, this variant will never become part of
8744 ; an execution group.
8747 ; compare and swap patterns.
8750 (define_expand "sync_compare_and_swap<mode>"
8752 [(set (match_operand:TDSI 0 "register_operand" "")
8753 (match_operand:TDSI 1 "memory_operand" ""))
8755 (unspec_volatile:TDSI
8757 (match_operand:TDSI 2 "register_operand" "")
8758 (match_operand:TDSI 3 "register_operand" "")]
8760 (set (reg:CCZ1 CC_REGNUM)
8761 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8764 (define_expand "sync_compare_and_swap<mode>"
8766 [(set (match_operand:HQI 0 "register_operand" "")
8767 (match_operand:HQI 1 "memory_operand" ""))
8769 (unspec_volatile:HQI
8771 (match_operand:HQI 2 "general_operand" "")
8772 (match_operand:HQI 3 "general_operand" "")]
8774 (clobber (reg:CC CC_REGNUM))])]
8776 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8777 operands[2], operands[3]); DONE;")
8780 (define_insn "*sync_compare_and_swap<mode>"
8781 [(set (match_operand:DW 0 "register_operand" "=r")
8782 (match_operand:DW 1 "memory_operand" "+Q"))
8786 (match_operand:DW 2 "register_operand" "0")
8787 (match_operand:DW 3 "register_operand" "r")]
8789 (set (reg:CCZ1 CC_REGNUM)
8790 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8792 "cds<tg>\t%0,%3,%S1"
8793 [(set_attr "op_type" "RS<TE>")
8794 (set_attr "type" "sem")])
8797 (define_insn "*sync_compare_and_swap<mode>"
8798 [(set (match_operand:GPR 0 "register_operand" "=r")
8799 (match_operand:GPR 1 "memory_operand" "+Q"))
8801 (unspec_volatile:GPR
8803 (match_operand:GPR 2 "register_operand" "0")
8804 (match_operand:GPR 3 "register_operand" "r")]
8806 (set (reg:CCZ1 CC_REGNUM)
8807 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8810 [(set_attr "op_type" "RS<E>")
8811 (set_attr "type" "sem")])
8815 ; Other atomic instruction patterns.
8818 (define_expand "sync_lock_test_and_set<mode>"
8819 [(match_operand:HQI 0 "register_operand")
8820 (match_operand:HQI 1 "memory_operand")
8821 (match_operand:HQI 2 "general_operand")]
8823 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8824 operands[2], false); DONE;")
8826 ; z196 load and add, xor, or and and instructions
8828 ; lan, lang, lao, laog, lax, laxg, laa, laag
8829 (define_insn "sync_<atomic><mode>"
8831 [(set (match_operand:GPR 0 "memory_operand" "+QS")
8832 (unspec_volatile:GPR
8833 [(ATOMIC_Z196:GPR (match_dup 0)
8834 (match_operand:GPR 1 "general_operand" "d"))]
8836 (clobber (match_scratch:GPR 2 "=d"))
8837 (clobber (reg:CC CC_REGNUM))])]
8839 "la<noxa><g>\t%2,%1,%0")
8841 ; lan, lang, lao, laog, lax, laxg, laa, laag
8842 (define_insn "sync_old_<atomic><mode>"
8844 [(set (match_operand:GPR 0 "register_operand" "=d")
8845 (match_operand:GPR 1 "memory_operand" "+QS"))
8848 [(ATOMIC_Z196:GPR (match_dup 1)
8849 (match_operand:GPR 2 "general_operand" "d"))]
8851 (clobber (reg:CC CC_REGNUM))])]
8853 "la<noxa><g>\t%0,%2,%1")
8856 (define_expand "sync_<atomic><mode>"
8857 [(set (match_operand:HQI 0 "memory_operand")
8858 (ATOMIC:HQI (match_dup 0)
8859 (match_operand:HQI 1 "general_operand")))]
8861 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8862 operands[1], false); DONE;")
8864 (define_expand "sync_old_<atomic><mode>"
8865 [(set (match_operand:HQI 0 "register_operand")
8866 (match_operand:HQI 1 "memory_operand"))
8868 (ATOMIC:HQI (match_dup 1)
8869 (match_operand:HQI 2 "general_operand")))]
8871 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8872 operands[2], false); DONE;")
8874 (define_expand "sync_new_<atomic><mode>"
8875 [(set (match_operand:HQI 0 "register_operand")
8876 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8877 (match_operand:HQI 2 "general_operand")))
8878 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8880 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8881 operands[2], true); DONE;")
8884 ;;- Miscellaneous instructions.
8888 ; allocate stack instruction pattern(s).
8891 (define_expand "allocate_stack"
8892 [(match_operand 0 "general_operand" "")
8893 (match_operand 1 "general_operand" "")]
8896 rtx temp = gen_reg_rtx (Pmode);
8898 emit_move_insn (temp, s390_back_chain_rtx ());
8899 anti_adjust_stack (operands[1]);
8900 emit_move_insn (s390_back_chain_rtx (), temp);
8902 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8908 ; setjmp instruction pattern.
8911 (define_expand "builtin_setjmp_receiver"
8912 [(match_operand 0 "" "")]
8915 emit_insn (s390_load_got ());
8916 emit_use (pic_offset_table_rtx);
8920 ;; These patterns say how to save and restore the stack pointer. We need not
8921 ;; save the stack pointer at function level since we are careful to
8922 ;; preserve the backchain. At block level, we have to restore the backchain
8923 ;; when we restore the stack pointer.
8925 ;; For nonlocal gotos, we must save both the stack pointer and its
8926 ;; backchain and restore both. Note that in the nonlocal case, the
8927 ;; save area is a memory location.
8929 (define_expand "save_stack_function"
8930 [(match_operand 0 "general_operand" "")
8931 (match_operand 1 "general_operand" "")]
8935 (define_expand "restore_stack_function"
8936 [(match_operand 0 "general_operand" "")
8937 (match_operand 1 "general_operand" "")]
8941 (define_expand "restore_stack_block"
8942 [(match_operand 0 "register_operand" "")
8943 (match_operand 1 "register_operand" "")]
8946 rtx temp = gen_reg_rtx (Pmode);
8948 emit_move_insn (temp, s390_back_chain_rtx ());
8949 emit_move_insn (operands[0], operands[1]);
8950 emit_move_insn (s390_back_chain_rtx (), temp);
8955 (define_expand "save_stack_nonlocal"
8956 [(match_operand 0 "memory_operand" "")
8957 (match_operand 1 "register_operand" "")]
8960 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8962 /* Copy the backchain to the first word, sp to the second and the
8963 literal pool base to the third. */
8965 rtx save_bc = adjust_address (operands[0], Pmode, 0);
8966 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
8967 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
8969 if (TARGET_BACKCHAIN)
8970 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
8972 emit_move_insn (save_sp, operands[1]);
8973 emit_move_insn (save_bp, base);
8978 (define_expand "restore_stack_nonlocal"
8979 [(match_operand 0 "register_operand" "")
8980 (match_operand 1 "memory_operand" "")]
8983 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8984 rtx temp = NULL_RTX;
8986 /* Restore the backchain from the first word, sp from the second and the
8987 literal pool base from the third. */
8989 rtx save_bc = adjust_address (operands[1], Pmode, 0);
8990 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
8991 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
8993 if (TARGET_BACKCHAIN)
8994 temp = force_reg (Pmode, save_bc);
8996 emit_move_insn (base, save_bp);
8997 emit_move_insn (operands[0], save_sp);
9000 emit_move_insn (s390_back_chain_rtx (), temp);
9006 (define_expand "exception_receiver"
9010 s390_set_has_landing_pad_p (true);
9015 ; nop instruction pattern(s).
9022 [(set_attr "op_type" "RR")
9023 (set_attr "z10prop" "z10_fr_E1")])
9029 [(set_attr "op_type" "RR")])
9033 ; Special literal pool access instruction pattern(s).
9036 (define_insn "*pool_entry"
9037 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9038 UNSPECV_POOL_ENTRY)]
9041 enum machine_mode mode = GET_MODE (PATTERN (insn));
9042 unsigned int align = GET_MODE_BITSIZE (mode);
9043 s390_output_pool_entry (operands[0], mode, align);
9046 [(set (attr "length")
9047 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9049 (define_insn "pool_align"
9050 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9051 UNSPECV_POOL_ALIGN)]
9054 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9056 (define_insn "pool_section_start"
9057 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9060 [(set_attr "length" "0")])
9062 (define_insn "pool_section_end"
9063 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9066 [(set_attr "length" "0")])
9068 (define_insn "main_base_31_small"
9069 [(set (match_operand 0 "register_operand" "=a")
9070 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9071 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9073 [(set_attr "op_type" "RR")
9074 (set_attr "type" "la")
9075 (set_attr "z196prop" "z196_cracked")])
9077 (define_insn "main_base_31_large"
9078 [(set (match_operand 0 "register_operand" "=a")
9079 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9080 (set (pc) (label_ref (match_operand 2 "" "")))]
9081 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9083 [(set_attr "op_type" "RI")
9084 (set_attr "z196prop" "z196_cracked")])
9086 (define_insn "main_base_64"
9087 [(set (match_operand 0 "register_operand" "=a")
9088 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9089 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9091 [(set_attr "op_type" "RIL")
9092 (set_attr "type" "larl")
9093 (set_attr "z10prop" "z10_fwd_A1")])
9095 (define_insn "main_pool"
9096 [(set (match_operand 0 "register_operand" "=a")
9097 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9098 "GET_MODE (operands[0]) == Pmode"
9103 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
9104 (const_string "larl") (const_string "la")))])
9106 (define_insn "reload_base_31"
9107 [(set (match_operand 0 "register_operand" "=a")
9108 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9109 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9110 "basr\t%0,0\;la\t%0,%1-.(%0)"
9111 [(set_attr "length" "6")
9112 (set_attr "type" "la")
9113 (set_attr "z196prop" "z196_cracked")])
9115 (define_insn "reload_base_64"
9116 [(set (match_operand 0 "register_operand" "=a")
9117 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9118 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9120 [(set_attr "op_type" "RIL")
9121 (set_attr "type" "larl")
9122 (set_attr "z10prop" "z10_fwd_A1")])
9125 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9130 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9133 ;; Insns related to generating the function prologue and epilogue.
9137 (define_expand "prologue"
9138 [(use (const_int 0))]
9140 "s390_emit_prologue (); DONE;")
9142 (define_expand "epilogue"
9143 [(use (const_int 1))]
9145 "s390_emit_epilogue (false); DONE;")
9147 (define_expand "sibcall_epilogue"
9148 [(use (const_int 0))]
9150 "s390_emit_epilogue (true); DONE;")
9152 (define_insn "*return"
9154 (use (match_operand 0 "register_operand" "a"))]
9155 "GET_MODE (operands[0]) == Pmode"
9157 [(set_attr "op_type" "RR")
9158 (set_attr "type" "jsr")
9159 (set_attr "atype" "agen")])
9162 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9163 ;; pointer. This is used for compatibility.
9165 (define_expand "ptr_extend"
9166 [(set (match_operand:DI 0 "register_operand" "=r")
9167 (match_operand:SI 1 "register_operand" "r"))]
9170 emit_insn (gen_anddi3 (operands[0],
9171 gen_lowpart (DImode, operands[1]),
9172 GEN_INT (0x7fffffff)));
9176 ;; Instruction definition to expand eh_return macro to support
9177 ;; swapping in special linkage return addresses.
9179 (define_expand "eh_return"
9180 [(use (match_operand 0 "register_operand" ""))]
9183 s390_emit_tpf_eh_return (operands[0]);
9188 ; Stack Protector Patterns
9191 (define_expand "stack_protect_set"
9192 [(set (match_operand 0 "memory_operand" "")
9193 (match_operand 1 "memory_operand" ""))]
9196 #ifdef TARGET_THREAD_SSP_OFFSET
9198 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9199 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9202 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9204 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9209 (define_insn "stack_protect_set<mode>"
9210 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9211 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9213 "mvc\t%O0(%G0,%R0),%S1"
9214 [(set_attr "op_type" "SS")])
9216 (define_expand "stack_protect_test"
9217 [(set (reg:CC CC_REGNUM)
9218 (compare (match_operand 0 "memory_operand" "")
9219 (match_operand 1 "memory_operand" "")))
9220 (match_operand 2 "" "")]
9224 #ifdef TARGET_THREAD_SSP_OFFSET
9226 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9227 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9230 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9232 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9234 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9235 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9236 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9240 (define_insn "stack_protect_test<mode>"
9241 [(set (reg:CCZ CC_REGNUM)
9242 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9243 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9245 "clc\t%O0(%G0,%R0),%S1"
9246 [(set_attr "op_type" "SS")])
9248 ; This is used in s390_emit_prologue in order to prevent insns
9249 ; adjusting the stack pointer to be moved over insns writing stack
9250 ; slots using a copy of the stack pointer in a different register.
9251 (define_insn "stack_tie"
9252 [(set (match_operand:BLK 0 "memory_operand" "+m")
9253 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9256 [(set_attr "length" "0")])
9260 ; Data prefetch patterns
9263 (define_insn "prefetch"
9264 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9265 (match_operand:SI 1 "const_int_operand" " n,n")
9266 (match_operand:SI 2 "const_int_operand" " n,n"))]
9269 switch (which_alternative)
9272 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9274 if (larl_operand (operands[0], Pmode))
9275 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9278 /* This might be reached for symbolic operands with an odd
9279 addend. We simply omit the prefetch for such rare cases. */
9284 [(set_attr "type" "load,larl")
9285 (set_attr "op_type" "RXY,RIL")
9286 (set_attr "z10prop" "z10_super")
9287 (set_attr "z196prop" "z196_alone")])
9291 ; Byte swap instructions
9294 (define_insn "bswap<mode>2"
9295 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9296 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9301 [(set_attr "type" "*,load")
9302 (set_attr "op_type" "RRE,RXY")
9303 (set_attr "z10prop" "z10_super")])
9307 ; Population count instruction
9310 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9311 ; portions and stores the result in the corresponding bytes in op0.
9312 (define_insn "*popcount<mode>"
9313 [(set (match_operand:INT 0 "register_operand" "=d")
9314 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9315 (clobber (reg:CC CC_REGNUM))]
9318 [(set_attr "op_type" "RRE")])
9320 (define_expand "popcountdi2"
9322 (parallel [(set (match_operand:DI 0 "register_operand" "")
9323 (unspec:DI [(match_operand:DI 1 "register_operand")]
9325 (clobber (reg:CC CC_REGNUM))])
9327 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9329 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9330 (clobber (reg:CC CC_REGNUM))])
9332 (set (match_operand:DI 2 "register_operand" "")
9333 (ashift:DI (match_dup 0) (const_int 16)))
9335 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9336 (clobber (reg:CC CC_REGNUM))])
9338 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9340 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9341 (clobber (reg:CC CC_REGNUM))])
9343 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9344 "TARGET_Z196 && TARGET_64BIT"
9345 "operands[2] = gen_reg_rtx (DImode);")
9347 (define_expand "popcountsi2"
9349 (parallel [(set (match_operand:SI 0 "register_operand" "")
9350 (unspec:SI [(match_operand:SI 1 "register_operand")]
9352 (clobber (reg:CC CC_REGNUM))])
9354 (set (match_operand:SI 2 "register_operand" "")
9355 (ashift:SI (match_dup 0) (const_int 16)))
9357 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9358 (clobber (reg:CC CC_REGNUM))])
9360 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9362 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9363 (clobber (reg:CC CC_REGNUM))])
9365 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9367 "operands[2] = gen_reg_rtx (SImode);")
9369 (define_expand "popcounthi2"
9371 (parallel [(set (match_operand:HI 0 "register_operand" "")
9372 (unspec:HI [(match_operand:HI 1 "register_operand")]
9374 (clobber (reg:CC CC_REGNUM))])
9376 (set (match_operand:SI 2 "register_operand" "")
9377 (ashift:SI (match_dup 0) (const_int 8)))
9379 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9380 (clobber (reg:CC CC_REGNUM))])
9382 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9384 "operands[2] = gen_reg_rtx (SImode);")
9386 (define_expand "popcountqi2"
9388 (parallel [(set (match_operand:QI 0 "register_operand" "")
9389 (unspec:QI [(match_operand:QI 1 "register_operand")]
9391 (clobber (reg:CC CC_REGNUM))])]
9396 ;;- Copy sign instructions
9399 (define_insn "copysign<mode>3"
9400 [(set (match_operand:FP 0 "register_operand" "=f")
9401 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9402 (match_operand:FP 2 "register_operand" "f")]
9406 [(set_attr "op_type" "RRF")
9407 (set_attr "type" "fsimp<mode>")])