1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
88 ; TLS relocation specifiers
93 (UNSPEC_GOTNTPOFF 504)
94 (UNSPEC_INDNTPOFF 505)
97 (UNSPEC_TLSLDM_NTPOFF 511)
104 ; Stack Smashing Protector
108 ; Copy sign instructions
109 (UNSPEC_COPYSIGN 800)
111 ; Test Data Class (TDC)
112 (UNSPEC_TDC_INSN 900)
116 ;; UNSPEC_VOLATILE usage
124 (UNSPECV_TPF_PROLOGUE 20)
125 (UNSPECV_TPF_EPILOGUE 21)
129 (UNSPECV_POOL_SECTION 201)
130 (UNSPECV_POOL_ALIGN 202)
131 (UNSPECV_POOL_ENTRY 203)
132 (UNSPECV_MAIN_POOL 300)
145 ; Registers with special meaning
149 ; Sibling call register.
151 ; Literal pool base register.
153 ; Return address register.
155 ; Condition code register.
157 ; Thread local storage pointer register.
161 ; Hardware register names
165 ; General purpose registers
167 ; Floating point registers.
173 ;; PFPO GPR0 argument format
178 ; PFPO operation type
179 (PFPO_CONVERT 0x1000000)
181 (PFPO_OP_TYPE_SF 0x5)
182 (PFPO_OP_TYPE_DF 0x6)
183 (PFPO_OP_TYPE_TF 0x7)
184 (PFPO_OP_TYPE_SD 0x8)
185 (PFPO_OP_TYPE_DD 0x9)
186 (PFPO_OP_TYPE_TD 0xa)
187 ; Bitposition of operand types
188 (PFPO_OP0_TYPE_SHIFT 16)
189 (PFPO_OP1_TYPE_SHIFT 8)
193 ;; Instruction operand type as used in the Principles of Operation.
194 ;; Used to determine defaults for length and other attribute values.
196 (define_attr "op_type"
197 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
200 ;; Instruction type attribute used for scheduling.
202 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
203 cs,vs,store,sem,idiv,
204 imulhi,imulsi,imuldi,
205 branch,jsr,fsimptf,fsimpdf,fsimpsf,
206 floadtf,floaddf,floadsf,fstoredf,fstoresf,
207 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
208 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
209 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
210 itoftf, itofdf, itofsf, itofdd, itoftd,
211 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
212 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
214 (cond [(eq_attr "op_type" "NN") (const_string "other")
215 (eq_attr "op_type" "SS") (const_string "cs")]
216 (const_string "integer")))
218 ;; Another attribute used for scheduling purposes:
219 ;; agen: Instruction uses the address generation unit
220 ;; reg: Instruction does not use the agen unit
222 (define_attr "atype" "agen,reg"
223 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
225 (const_string "agen")))
227 ;; Properties concerning Z10 execution grouping and value forwarding.
228 ;; z10_super: instruction is superscalar.
229 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
230 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
231 ;; target register. It can forward this value to a second instruction that reads
232 ;; the same register if that second instruction is issued in the same group.
233 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
234 ;; instruction in the S pipe writes to the register, then the T instruction
235 ;; can immediately read the new value.
236 ;; z10_fr: union of Z10_fwd and z10_rec.
237 ;; z10_c: second operand of instruction is a register and read with complemented bits.
238 ;; z10_cobra: its a compare and branch instruction
240 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
243 (define_attr "z10prop" "none,
244 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
245 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
247 z10_fr, z10_fr_A3, z10_fr_E1,
249 (const_string "none"))
254 (define_attr "length" ""
255 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
256 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
260 ;; Processor type. This attribute must exactly match the processor_type
261 ;; enumeration in s390.h. The current machine description does not
262 ;; distinguish between g5 and g6, but there are differences between the two
263 ;; CPUs could in theory be modeled.
265 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
266 (const (symbol_ref "s390_tune")))
268 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
269 (const_string "standard"))
271 (define_attr "enabled" ""
272 (cond [(eq_attr "cpu_facility" "standard")
275 (and (eq_attr "cpu_facility" "ieee")
276 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
279 (and (eq_attr "cpu_facility" "zarch")
280 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
283 (and (eq_attr "cpu_facility" "longdisp")
284 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
287 (and (eq_attr "cpu_facility" "extimm")
288 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
291 (and (eq_attr "cpu_facility" "dfp")
292 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
295 (and (eq_attr "cpu_facility" "z10")
296 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
300 ;; Pipeline description for z900. For lack of anything better,
301 ;; this description is also used for the g5 and g6.
304 ;; Pipeline description for z990, z9-109 and z9-ec.
307 ;; Pipeline description for z10
311 (include "predicates.md")
313 ;; Constraint definitions
314 (include "constraints.md")
321 ;; These mode iterators allow floating point patterns to be generated from the
323 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
324 (SD "TARGET_HARD_DFP")])
325 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
326 (define_mode_iterator FPALL [TF DF SF TD DD SD])
327 (define_mode_iterator BFP [TF DF SF])
328 (define_mode_iterator DFP [TD DD])
329 (define_mode_iterator DFP_ALL [TD DD SD])
330 (define_mode_iterator DSF [DF SF])
331 (define_mode_iterator SD_SF [SF SD])
332 (define_mode_iterator DD_DF [DF DD])
333 (define_mode_iterator TD_TF [TF TD])
335 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
336 ;; from the same template.
337 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
339 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
340 ;; from the same template.
341 (define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
342 (define_mode_iterator DSI [DI SI])
344 ;; These mode iterators allow :P to be used for patterns that operate on
345 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
346 (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
347 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
349 ;; This mode iterator allows the QI and HI patterns to be defined from
350 ;; the same template.
351 (define_mode_iterator HQI [HI QI])
353 ;; This mode iterator allows the integer patterns to be defined from the
355 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
356 (define_mode_iterator INTALL [TI DI SI HI QI])
358 ;; This iterator allows to unify all 'bCOND' expander patterns.
359 (define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
360 ordered uneq unlt ungt unle unge ltgt])
362 ;; This iterator allows to unify all 'sCOND' patterns.
363 (define_code_iterator SCOND [ltu gtu leu geu])
365 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
366 ;; the same template.
367 (define_code_iterator SHIFT [ashift lshiftrt])
369 ;; This iterator and attribute allow to combine most atomic operations.
370 (define_code_iterator ATOMIC [and ior xor plus minus mult])
371 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
372 (plus "add") (minus "sub") (mult "nand")])
374 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
375 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
376 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
378 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
379 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
381 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
383 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
384 ;; Likewise for "<RXe>".
385 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
386 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
388 ;; The decimal floating point variants of add, sub, div and mul support 3
389 ;; fp register operands. The following attributes allow to merge the bfp and
390 ;; dfp variants in a single insn definition.
392 ;; This attribute is used to set op_type accordingly.
393 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
394 (DD "RRR") (SD "RRR")])
396 ;; This attribute is used in the operand constraint list in order to have the
397 ;; first and the second operand match for bfp modes.
398 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
400 ;; This attribute is used in the operand list of the instruction to have an
401 ;; additional operand for the dfp instructions.
402 (define_mode_attr op1 [(TF "") (DF "") (SF "")
403 (TD "%1,") (DD "%1,") (SD "%1,")])
406 ;; This attribute is used in the operand constraint list
407 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
408 ;; TFmode values are represented by a fp register pair. Since the
409 ;; sign bit instructions only handle single source and target fp registers
410 ;; these instructions can only be used for TFmode values if the source and
411 ;; target operand uses the same fp register.
412 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
414 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
415 ;; This is used to disable the memory alternative in TFmode patterns.
416 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
418 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
419 ;; within instruction mnemonics.
420 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
422 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
423 ;; modes and to an empty string for bfp modes.
424 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
426 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
427 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
428 ;; version only operates on one register.
429 (define_mode_attr d0 [(DI "d") (SI "0")])
431 ;; In combination with d0 this allows to combine instructions of which the 31bit
432 ;; version only operates on one register. The DImode version needs an additional
433 ;; register for the assembler output.
434 (define_mode_attr 1 [(DI "%1,") (SI "")])
436 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
437 ;; 'ashift' and "srdl" in 'lshiftrt'.
438 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
440 ;; In SHIFT templates, this attribute holds the correct standard name for the
441 ;; pattern itself and the corresponding function calls.
442 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
444 ;; This attribute handles differences in the instruction 'type' and will result
445 ;; in "RRE" for DImode and "RR" for SImode.
446 (define_mode_attr E [(DI "E") (SI "")])
448 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
449 ;; to result in "RXY" for DImode and "RX" for SImode.
450 (define_mode_attr Y [(DI "Y") (SI "")])
452 ;; This attribute handles differences in the instruction 'type' and will result
453 ;; in "RSE" for TImode and "RS" for DImode.
454 (define_mode_attr TE [(TI "E") (DI "")])
456 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
457 ;; and "lcr" in SImode.
458 (define_mode_attr g [(DI "g") (SI "")])
460 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
461 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
462 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
463 ;; variant for long displacements.
464 (define_mode_attr y [(DI "g") (SI "y")])
466 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
467 ;; and "cds" in DImode.
468 (define_mode_attr tg [(TI "g") (DI "")])
470 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
471 ;; and "cfdbr" in SImode.
472 (define_mode_attr gf [(DI "g") (SI "f")])
474 ;; ICM mask required to load MODE value into the lowest subreg
475 ;; of a SImode register.
476 (define_mode_attr icm_lo [(HI "3") (QI "1")])
478 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
479 ;; HImode and "llgc" in QImode.
480 (define_mode_attr hc [(HI "h") (QI "c")])
482 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
484 (define_mode_attr DBL [(DI "TI") (SI "DI")])
486 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
487 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
488 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
490 ;; Maximum unsigned integer that fits in MODE.
491 (define_mode_attr max_uint [(HI "65535") (QI "255")])
494 ;;- Compare instructions.
497 (define_expand "cmp<mode>"
498 [(set (reg:CC CC_REGNUM)
499 (compare:CC (match_operand:GPR 0 "register_operand" "")
500 (match_operand:GPR 1 "general_operand" "")))]
503 s390_compare_op0 = operands[0];
504 s390_compare_op1 = operands[1];
508 (define_expand "cmp<mode>"
509 [(set (reg:CC CC_REGNUM)
510 (compare:CC (match_operand:FP 0 "register_operand" "")
511 (match_operand:FP 1 "general_operand" "")))]
514 s390_compare_op0 = operands[0];
515 s390_compare_op1 = operands[1];
520 ; Test-under-Mask instructions
522 (define_insn "*tmqi_mem"
523 [(set (reg CC_REGNUM)
524 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
525 (match_operand:QI 1 "immediate_operand" "n,n"))
526 (match_operand:QI 2 "immediate_operand" "n,n")))]
527 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
531 [(set_attr "op_type" "SI,SIY")
532 (set_attr "z10prop" "z10_super,z10_super")])
534 (define_insn "*tmdi_reg"
535 [(set (reg CC_REGNUM)
536 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
537 (match_operand:DI 1 "immediate_operand"
538 "N0HD0,N1HD0,N2HD0,N3HD0"))
539 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
541 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
542 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
548 [(set_attr "op_type" "RI")
549 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
551 (define_insn "*tmsi_reg"
552 [(set (reg CC_REGNUM)
553 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
554 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
555 (match_operand:SI 2 "immediate_operand" "n,n")))]
556 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
557 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
561 [(set_attr "op_type" "RI")
562 (set_attr "z10prop" "z10_super,z10_super")])
564 (define_insn "*tm<mode>_full"
565 [(set (reg CC_REGNUM)
566 (compare (match_operand:HQI 0 "register_operand" "d")
567 (match_operand:HQI 1 "immediate_operand" "n")))]
568 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
570 [(set_attr "op_type" "RI")
571 (set_attr "z10prop" "z10_super")])
575 ; Load-and-Test instructions
578 ; tst(di|si) instruction pattern(s).
580 (define_insn "*tstdi_sign"
581 [(set (reg CC_REGNUM)
585 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
586 (const_int 32)) (const_int 32))
587 (match_operand:DI 1 "const0_operand" "")))
588 (set (match_operand:DI 2 "register_operand" "=d,d")
589 (sign_extend:DI (match_dup 0)))]
590 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
593 [(set_attr "op_type" "RRE,RXY")
594 (set_attr "cpu_facility" "*,z10")
595 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
598 (define_insn "*tst<mode>_extimm"
599 [(set (reg CC_REGNUM)
600 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
601 (match_operand:GPR 1 "const0_operand" "")))
602 (set (match_operand:GPR 2 "register_operand" "=d,d")
604 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
608 [(set_attr "op_type" "RR<E>,RXY")
609 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
612 (define_insn "*tst<mode>_cconly_extimm"
613 [(set (reg CC_REGNUM)
614 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
615 (match_operand:GPR 1 "const0_operand" "")))
616 (clobber (match_scratch:GPR 2 "=X,d"))]
617 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
621 [(set_attr "op_type" "RR<E>,RXY")
622 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
624 (define_insn "*tstdi"
625 [(set (reg CC_REGNUM)
626 (compare (match_operand:DI 0 "register_operand" "d")
627 (match_operand:DI 1 "const0_operand" "")))
628 (set (match_operand:DI 2 "register_operand" "=d")
630 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
632 [(set_attr "op_type" "RRE")
633 (set_attr "z10prop" "z10_fr_E1")])
635 (define_insn "*tstsi"
636 [(set (reg CC_REGNUM)
637 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
638 (match_operand:SI 1 "const0_operand" "")))
639 (set (match_operand:SI 2 "register_operand" "=d,d,d")
641 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
646 [(set_attr "op_type" "RR,RS,RSY")
647 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
649 (define_insn "*tstsi_cconly"
650 [(set (reg CC_REGNUM)
651 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
652 (match_operand:SI 1 "const0_operand" "")))
653 (clobber (match_scratch:SI 2 "=X,d,d"))]
654 "s390_match_ccmode(insn, CCSmode)"
659 [(set_attr "op_type" "RR,RS,RSY")
660 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
662 (define_insn "*tstdi_cconly_31"
663 [(set (reg CC_REGNUM)
664 (compare (match_operand:DI 0 "register_operand" "d")
665 (match_operand:DI 1 "const0_operand" "")))]
666 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
668 [(set_attr "op_type" "RS")
669 (set_attr "atype" "reg")])
672 (define_insn "*tst<mode>_cconly2"
673 [(set (reg CC_REGNUM)
674 (compare (match_operand:GPR 0 "register_operand" "d")
675 (match_operand:GPR 1 "const0_operand" "")))]
676 "s390_match_ccmode(insn, CCSmode)"
678 [(set_attr "op_type" "RR<E>")
679 (set_attr "z10prop" "z10_fr_E1")])
681 ; tst(hi|qi) instruction pattern(s).
683 (define_insn "*tst<mode>CCT"
684 [(set (reg CC_REGNUM)
685 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
686 (match_operand:HQI 1 "const0_operand" "")))
687 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
689 "s390_match_ccmode(insn, CCTmode)"
692 icmy\t%2,<icm_lo>,%S0
694 [(set_attr "op_type" "RS,RSY,RI")
695 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
697 (define_insn "*tsthiCCT_cconly"
698 [(set (reg CC_REGNUM)
699 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
700 (match_operand:HI 1 "const0_operand" "")))
701 (clobber (match_scratch:HI 2 "=d,d,X"))]
702 "s390_match_ccmode(insn, CCTmode)"
707 [(set_attr "op_type" "RS,RSY,RI")
708 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
710 (define_insn "*tstqiCCT_cconly"
711 [(set (reg CC_REGNUM)
712 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
713 (match_operand:QI 1 "const0_operand" "")))]
714 "s390_match_ccmode(insn, CCTmode)"
719 [(set_attr "op_type" "SI,SIY,RI")
720 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
722 (define_insn "*tst<mode>"
723 [(set (reg CC_REGNUM)
724 (compare (match_operand:HQI 0 "s_operand" "Q,S")
725 (match_operand:HQI 1 "const0_operand" "")))
726 (set (match_operand:HQI 2 "register_operand" "=d,d")
728 "s390_match_ccmode(insn, CCSmode)"
731 icmy\t%2,<icm_lo>,%S0"
732 [(set_attr "op_type" "RS,RSY")
733 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
735 (define_insn "*tst<mode>_cconly"
736 [(set (reg CC_REGNUM)
737 (compare (match_operand:HQI 0 "s_operand" "Q,S")
738 (match_operand:HQI 1 "const0_operand" "")))
739 (clobber (match_scratch:HQI 2 "=d,d"))]
740 "s390_match_ccmode(insn, CCSmode)"
743 icmy\t%2,<icm_lo>,%S0"
744 [(set_attr "op_type" "RS,RSY")
745 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
748 ; Compare (equality) instructions
750 (define_insn "*cmpdi_cct"
751 [(set (reg CC_REGNUM)
752 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
753 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
754 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
761 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
762 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
764 (define_insn "*cmpsi_cct"
765 [(set (reg CC_REGNUM)
766 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
767 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
768 "s390_match_ccmode (insn, CCTmode)"
776 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
777 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super,z10_super,*")])
779 ; Compare (signed) instructions
781 (define_insn "*cmpdi_ccs_sign"
782 [(set (reg CC_REGNUM)
783 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
785 (match_operand:DI 0 "register_operand" "d, d,d")))]
786 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
791 [(set_attr "op_type" "RRE,RXY,RIL")
792 (set_attr "z10prop" "z10_c,*,*")
793 (set_attr "type" "*,*,larl")])
797 (define_insn "*cmpsi_ccs_sign"
798 [(set (reg CC_REGNUM)
799 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
800 (match_operand:SI 0 "register_operand" "d,d,d")))]
801 "s390_match_ccmode(insn, CCSRmode)"
806 [(set_attr "op_type" "RX,RXY,RIL")
807 (set_attr "cpu_facility" "*,*,z10")
808 (set_attr "type" "*,*,larl")])
810 (define_insn "*cmphi_ccs_z10"
811 [(set (reg CC_REGNUM)
812 (compare (match_operand:HI 0 "s_operand" "Q")
813 (match_operand:HI 1 "immediate_operand" "K")))]
814 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
816 [(set_attr "op_type" "SIL")])
818 (define_insn "*cmpdi_ccs_signhi_rl"
819 [(set (reg CC_REGNUM)
820 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
821 (match_operand:GPR 0 "register_operand" "d,d")))]
822 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
826 [(set_attr "op_type" "RXY,RIL")
827 (set_attr "type" "*,larl")])
829 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
830 (define_insn "*cmp<mode>_ccs"
831 [(set (reg CC_REGNUM)
832 (compare (match_operand:GPR 0 "nonimmediate_operand"
834 (match_operand:GPR 1 "general_operand"
836 "s390_match_ccmode(insn, CCSmode)"
845 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
846 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
847 (set_attr "type" "*,*,*,*,*,*,larl")
848 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
851 ; Compare (unsigned) instructions
853 (define_insn "*cmpsi_ccu_zerohi_rlsi"
854 [(set (reg CC_REGNUM)
855 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
856 "larl_operand" "X")))
857 (match_operand:SI 0 "register_operand" "d")))]
858 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
860 [(set_attr "op_type" "RIL")
861 (set_attr "type" "larl")
862 (set_attr "z10prop" "z10_super")])
865 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
866 [(set (reg CC_REGNUM)
867 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
868 "larl_operand" "X")))
869 (match_operand:GPR 0 "register_operand" "d")))]
870 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
872 [(set_attr "op_type" "RIL")
873 (set_attr "type" "larl")
874 (set_attr "z10prop" "z10_super")])
876 (define_insn "*cmpdi_ccu_zero"
877 [(set (reg CC_REGNUM)
878 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
880 (match_operand:DI 0 "register_operand" "d, d,d")))]
881 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
886 [(set_attr "op_type" "RRE,RXY,RIL")
887 (set_attr "cpu_facility" "*,*,z10")
888 (set_attr "type" "*,*,larl")
889 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
891 (define_insn "*cmpdi_ccu"
892 [(set (reg CC_REGNUM)
893 (compare (match_operand:DI 0 "nonimmediate_operand"
895 (match_operand:DI 1 "general_operand"
896 "d,Op,b,D,RT,BQ,Q")))]
897 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
906 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
907 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
908 (set_attr "type" "*,*,larl,*,*,*,*")
909 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
911 (define_insn "*cmpsi_ccu"
912 [(set (reg CC_REGNUM)
913 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
914 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
915 "s390_match_ccmode (insn, CCUmode)"
925 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
926 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
927 (set_attr "type" "*,*,larl,*,*,*,*,*")
928 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
930 (define_insn "*cmphi_ccu"
931 [(set (reg CC_REGNUM)
932 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
933 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
934 "s390_match_ccmode (insn, CCUmode)
935 && !register_operand (operands[1], HImode)"
942 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
943 (set_attr "cpu_facility" "*,*,z10,*,*")
944 (set_attr "z10prop" "*,*,z10_super,*,*")])
946 (define_insn "*cmpqi_ccu"
947 [(set (reg CC_REGNUM)
948 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
949 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
950 "s390_match_ccmode (insn, CCUmode)
951 && !register_operand (operands[1], QImode)"
959 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
960 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
963 ; Block compare (CLC) instruction patterns.
966 [(set (reg CC_REGNUM)
967 (compare (match_operand:BLK 0 "memory_operand" "Q")
968 (match_operand:BLK 1 "memory_operand" "Q")))
969 (use (match_operand 2 "const_int_operand" "n"))]
970 "s390_match_ccmode (insn, CCUmode)
971 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
972 "clc\t%O0(%2,%R0),%S1"
973 [(set_attr "op_type" "SS")])
976 [(set (reg CC_REGNUM)
977 (compare (match_operand 0 "memory_operand" "")
978 (match_operand 1 "memory_operand" "")))]
980 && s390_match_ccmode (insn, CCUmode)
981 && GET_MODE (operands[0]) == GET_MODE (operands[1])
982 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
984 [(set (match_dup 0) (match_dup 1))
985 (use (match_dup 2))])]
987 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
988 operands[0] = adjust_address (operands[0], BLKmode, 0);
989 operands[1] = adjust_address (operands[1], BLKmode, 0);
991 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
992 operands[0], operands[1]);
993 operands[0] = SET_DEST (PATTERN (curr_insn));
997 ; (TF|DF|SF|TD|DD|SD) instructions
999 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1000 (define_insn "*cmp<mode>_ccs_0"
1001 [(set (reg CC_REGNUM)
1002 (compare (match_operand:FP 0 "register_operand" "f")
1003 (match_operand:FP 1 "const0_operand" "")))]
1004 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1005 "lt<xde><bt>r\t%0,%0"
1006 [(set_attr "op_type" "RRE")
1007 (set_attr "type" "fsimp<mode>")])
1009 ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
1010 (define_insn "*cmp<mode>_ccs"
1011 [(set (reg CC_REGNUM)
1012 (compare (match_operand:FP 0 "register_operand" "f,f")
1013 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1014 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1018 [(set_attr "op_type" "RRE,RXE")
1019 (set_attr "type" "fsimp<mode>")])
1022 ; Compare and Branch instructions
1024 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1025 ; The following instructions do a complementary access of their second
1026 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1027 (define_insn "*cmp_and_br_signed_<mode>"
1029 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1030 [(match_operand:GPR 1 "register_operand" "d,d")
1031 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1032 (label_ref (match_operand 3 "" ""))
1034 (clobber (reg:CC CC_REGNUM))]
1037 if (get_attr_length (insn) == 6)
1038 return which_alternative ?
1039 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1041 return which_alternative ?
1042 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1044 [(set_attr "op_type" "RIE")
1045 (set_attr "type" "branch")
1046 (set_attr "z10prop" "z10_cobra,z10_super")
1047 (set (attr "length")
1048 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1049 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1050 ; 10 byte for cgr/jg
1052 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1053 ; The following instructions do a complementary access of their second
1054 ; operand (z10 only): clrj, clgrj, clr, clgr
1055 (define_insn "*cmp_and_br_unsigned_<mode>"
1057 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1058 [(match_operand:GPR 1 "register_operand" "d,d")
1059 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1060 (label_ref (match_operand 3 "" ""))
1062 (clobber (reg:CC CC_REGNUM))]
1065 if (get_attr_length (insn) == 6)
1066 return which_alternative ?
1067 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1069 return which_alternative ?
1070 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1072 [(set_attr "op_type" "RIE")
1073 (set_attr "type" "branch")
1074 (set_attr "z10prop" "z10_cobra,z10_super")
1075 (set (attr "length")
1076 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1077 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1078 ; 10 byte for clgr/jg
1081 ;;- Move instructions.
1085 ; movti instruction pattern(s).
1088 (define_insn "movti"
1089 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1090 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1097 [(set_attr "op_type" "RSY,RSY,*,*")
1098 (set_attr "type" "lm,stm,*,*")])
1101 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1102 (match_operand:TI 1 "general_operand" ""))]
1103 "TARGET_64BIT && reload_completed
1104 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1105 [(set (match_dup 2) (match_dup 4))
1106 (set (match_dup 3) (match_dup 5))]
1108 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1109 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1110 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1111 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1115 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1116 (match_operand:TI 1 "general_operand" ""))]
1117 "TARGET_64BIT && reload_completed
1118 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1119 [(set (match_dup 2) (match_dup 4))
1120 (set (match_dup 3) (match_dup 5))]
1122 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1123 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1124 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1125 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1129 [(set (match_operand:TI 0 "register_operand" "")
1130 (match_operand:TI 1 "memory_operand" ""))]
1131 "TARGET_64BIT && reload_completed
1132 && !s_operand (operands[1], VOIDmode)"
1133 [(set (match_dup 0) (match_dup 1))]
1135 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1136 s390_load_address (addr, XEXP (operands[1], 0));
1137 operands[1] = replace_equiv_address (operands[1], addr);
1142 ; Patterns used for secondary reloads
1145 ; z10 provides move instructions accepting larl memory operands.
1146 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1147 ; These patterns are also used for unaligned SI and DI accesses.
1149 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1150 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1151 (match_operand:INTALL 1 "register_operand" "=d")
1152 (match_operand:P 2 "register_operand" "=&a")])]
1155 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1159 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1160 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1161 (match_operand:INTALL 1 "memory_operand" "")
1162 (match_operand:P 2 "register_operand" "=a")])]
1165 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1169 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1170 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1171 (match_operand:FPALL 1 "register_operand" "=d")
1172 (match_operand:P 2 "register_operand" "=&a")])]
1175 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1179 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1180 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1181 (match_operand:FPALL 1 "memory_operand" "")
1182 (match_operand:P 2 "register_operand" "=a")])]
1185 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1189 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1190 [(parallel [(match_operand:P 0 "register_operand" "=d")
1191 (match_operand:P 1 "larl_operand" "")
1192 (match_operand:P 2 "register_operand" "=a")])]
1195 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1199 ; Handles loading a PLUS (load address) expression
1201 (define_expand "reload<mode>_plus"
1202 [(parallel [(match_operand:P 0 "register_operand" "=a")
1203 (match_operand:P 1 "s390_plus_operand" "")
1204 (match_operand:P 2 "register_operand" "=&a")])]
1207 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1211 ; Handles assessing a non-offsetable memory address
1213 (define_expand "reload<mode>_nonoffmem_in"
1214 [(parallel [(match_operand 0 "register_operand" "")
1215 (match_operand 1 "" "")
1216 (match_operand:P 2 "register_operand" "=&a")])]
1219 gcc_assert (MEM_P (operands[1]));
1220 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1221 operands[1] = replace_equiv_address (operands[1], operands[2]);
1222 emit_move_insn (operands[0], operands[1]);
1226 (define_expand "reload<mode>_nonoffmem_out"
1227 [(parallel [(match_operand 0 "" "")
1228 (match_operand 1 "register_operand" "")
1229 (match_operand:P 2 "register_operand" "=&a")])]
1232 gcc_assert (MEM_P (operands[0]));
1233 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1234 operands[0] = replace_equiv_address (operands[0], operands[2]);
1235 emit_move_insn (operands[0], operands[1]);
1239 (define_expand "reload<mode>_PIC_addr"
1240 [(parallel [(match_operand 0 "register_operand" "=d")
1241 (match_operand 1 "larl_operand" "")
1242 (match_operand:P 2 "register_operand" "=a")])]
1245 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1246 emit_move_insn (operands[0], new_rtx);
1250 ; movdi instruction pattern(s).
1253 (define_expand "movdi"
1254 [(set (match_operand:DI 0 "general_operand" "")
1255 (match_operand:DI 1 "general_operand" ""))]
1258 /* Handle symbolic constants. */
1260 && (SYMBOLIC_CONST (operands[1])
1261 || (GET_CODE (operands[1]) == PLUS
1262 && XEXP (operands[1], 0) == pic_offset_table_rtx
1263 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1264 emit_symbolic_move (operands);
1267 (define_insn "*movdi_larl"
1268 [(set (match_operand:DI 0 "register_operand" "=d")
1269 (match_operand:DI 1 "larl_operand" "X"))]
1271 && !FP_REG_P (operands[0])"
1273 [(set_attr "op_type" "RIL")
1274 (set_attr "type" "larl")
1275 (set_attr "z10prop" "z10_super_A1")])
1277 (define_insn "*movdi_64"
1278 [(set (match_operand:DI 0 "nonimmediate_operand"
1279 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1280 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1281 (match_operand:DI 1 "general_operand"
1282 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1283 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1312 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1313 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1314 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1315 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1317 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1318 z10,*,*,*,*,*,longdisp,*,longdisp,
1320 (set_attr "z10prop" "z10_fwd_A1,
1349 [(set (match_operand:DI 0 "register_operand" "")
1350 (match_operand:DI 1 "register_operand" ""))]
1351 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1352 [(set (match_dup 2) (match_dup 3))
1353 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1354 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1355 "operands[2] = gen_lowpart (SImode, operands[0]);
1356 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1359 [(set (match_operand:DI 0 "register_operand" "")
1360 (match_operand:DI 1 "register_operand" ""))]
1361 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1362 && dead_or_set_p (insn, operands[1])"
1363 [(set (match_dup 3) (match_dup 2))
1364 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1365 (set (match_dup 4) (match_dup 2))]
1366 "operands[2] = gen_lowpart (SImode, operands[1]);
1367 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1370 [(set (match_operand:DI 0 "register_operand" "")
1371 (match_operand:DI 1 "register_operand" ""))]
1372 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1373 && !dead_or_set_p (insn, operands[1])"
1374 [(set (match_dup 3) (match_dup 2))
1375 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1376 (set (match_dup 4) (match_dup 2))
1377 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1378 "operands[2] = gen_lowpart (SImode, operands[1]);
1379 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1381 (define_insn "*movdi_31"
1382 [(set (match_operand:DI 0 "nonimmediate_operand"
1383 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1384 (match_operand:DI 1 "general_operand"
1385 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1400 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1401 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1402 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1404 ; For a load from a symbol ref we can use one of the target registers
1405 ; together with larl to load the address.
1407 [(set (match_operand:DI 0 "register_operand" "")
1408 (match_operand:DI 1 "memory_operand" ""))]
1409 "!TARGET_64BIT && reload_completed && TARGET_Z10
1410 && larl_operand (XEXP (operands[1], 0), SImode)"
1411 [(set (match_dup 2) (match_dup 3))
1412 (set (match_dup 0) (match_dup 1))]
1414 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1415 operands[3] = XEXP (operands[1], 0);
1416 operands[1] = replace_equiv_address (operands[1], operands[2]);
1420 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1421 (match_operand:DI 1 "general_operand" ""))]
1422 "!TARGET_64BIT && reload_completed
1423 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1424 [(set (match_dup 2) (match_dup 4))
1425 (set (match_dup 3) (match_dup 5))]
1427 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1428 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1429 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1430 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1434 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1435 (match_operand:DI 1 "general_operand" ""))]
1436 "!TARGET_64BIT && reload_completed
1437 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1438 [(set (match_dup 2) (match_dup 4))
1439 (set (match_dup 3) (match_dup 5))]
1441 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1442 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1443 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1444 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1448 [(set (match_operand:DI 0 "register_operand" "")
1449 (match_operand:DI 1 "memory_operand" ""))]
1450 "!TARGET_64BIT && reload_completed
1451 && !FP_REG_P (operands[0])
1452 && !s_operand (operands[1], VOIDmode)"
1453 [(set (match_dup 0) (match_dup 1))]
1455 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1456 s390_load_address (addr, XEXP (operands[1], 0));
1457 operands[1] = replace_equiv_address (operands[1], addr);
1461 [(set (match_operand:DI 0 "register_operand" "")
1462 (mem:DI (match_operand 1 "address_operand" "")))]
1464 && !FP_REG_P (operands[0])
1465 && GET_CODE (operands[1]) == SYMBOL_REF
1466 && CONSTANT_POOL_ADDRESS_P (operands[1])
1467 && get_pool_mode (operands[1]) == DImode
1468 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1469 [(set (match_dup 0) (match_dup 2))]
1470 "operands[2] = get_pool_constant (operands[1]);")
1472 (define_insn "*la_64"
1473 [(set (match_operand:DI 0 "register_operand" "=d,d")
1474 (match_operand:QI 1 "address_operand" "U,W"))]
1479 [(set_attr "op_type" "RX,RXY")
1480 (set_attr "type" "la")
1481 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1485 [(set (match_operand:DI 0 "register_operand" "")
1486 (match_operand:QI 1 "address_operand" ""))
1487 (clobber (reg:CC CC_REGNUM))])]
1489 && preferred_la_operand_p (operands[1], const0_rtx)"
1490 [(set (match_dup 0) (match_dup 1))]
1494 [(set (match_operand:DI 0 "register_operand" "")
1495 (match_operand:DI 1 "register_operand" ""))
1498 (plus:DI (match_dup 0)
1499 (match_operand:DI 2 "nonmemory_operand" "")))
1500 (clobber (reg:CC CC_REGNUM))])]
1502 && !reg_overlap_mentioned_p (operands[0], operands[2])
1503 && preferred_la_operand_p (operands[1], operands[2])"
1504 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1508 ; movsi instruction pattern(s).
1511 (define_expand "movsi"
1512 [(set (match_operand:SI 0 "general_operand" "")
1513 (match_operand:SI 1 "general_operand" ""))]
1516 /* Handle symbolic constants. */
1518 && (SYMBOLIC_CONST (operands[1])
1519 || (GET_CODE (operands[1]) == PLUS
1520 && XEXP (operands[1], 0) == pic_offset_table_rtx
1521 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1522 emit_symbolic_move (operands);
1525 (define_insn "*movsi_larl"
1526 [(set (match_operand:SI 0 "register_operand" "=d")
1527 (match_operand:SI 1 "larl_operand" "X"))]
1528 "!TARGET_64BIT && TARGET_CPU_ZARCH
1529 && !FP_REG_P (operands[0])"
1531 [(set_attr "op_type" "RIL")
1532 (set_attr "type" "larl")
1533 (set_attr "z10prop" "z10_fwd_A1")])
1535 (define_insn "*movsi_zarch"
1536 [(set (match_operand:SI 0 "nonimmediate_operand"
1537 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1538 (match_operand:SI 1 "general_operand"
1539 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1564 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1565 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1566 (set_attr "type" "*,
1588 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1589 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1590 (set_attr "z10prop" "z10_fwd_A1,
1613 (define_insn "*movsi_esa"
1614 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1615 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1629 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1630 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1631 (set_attr "z10prop" "z10_fwd_A1,
1645 [(set (match_operand:SI 0 "register_operand" "")
1646 (mem:SI (match_operand 1 "address_operand" "")))]
1647 "!FP_REG_P (operands[0])
1648 && GET_CODE (operands[1]) == SYMBOL_REF
1649 && CONSTANT_POOL_ADDRESS_P (operands[1])
1650 && get_pool_mode (operands[1]) == SImode
1651 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1652 [(set (match_dup 0) (match_dup 2))]
1653 "operands[2] = get_pool_constant (operands[1]);")
1655 (define_insn "*la_31"
1656 [(set (match_operand:SI 0 "register_operand" "=d,d")
1657 (match_operand:QI 1 "address_operand" "U,W"))]
1658 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1662 [(set_attr "op_type" "RX,RXY")
1663 (set_attr "type" "la")
1664 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1668 [(set (match_operand:SI 0 "register_operand" "")
1669 (match_operand:QI 1 "address_operand" ""))
1670 (clobber (reg:CC CC_REGNUM))])]
1672 && preferred_la_operand_p (operands[1], const0_rtx)"
1673 [(set (match_dup 0) (match_dup 1))]
1677 [(set (match_operand:SI 0 "register_operand" "")
1678 (match_operand:SI 1 "register_operand" ""))
1681 (plus:SI (match_dup 0)
1682 (match_operand:SI 2 "nonmemory_operand" "")))
1683 (clobber (reg:CC CC_REGNUM))])]
1685 && !reg_overlap_mentioned_p (operands[0], operands[2])
1686 && preferred_la_operand_p (operands[1], operands[2])"
1687 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1690 (define_insn "*la_31_and"
1691 [(set (match_operand:SI 0 "register_operand" "=d,d")
1692 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1693 (const_int 2147483647)))]
1698 [(set_attr "op_type" "RX,RXY")
1699 (set_attr "type" "la")
1700 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1702 (define_insn_and_split "*la_31_and_cc"
1703 [(set (match_operand:SI 0 "register_operand" "=d")
1704 (and:SI (match_operand:QI 1 "address_operand" "p")
1705 (const_int 2147483647)))
1706 (clobber (reg:CC CC_REGNUM))]
1709 "&& reload_completed"
1711 (and:SI (match_dup 1) (const_int 2147483647)))]
1713 [(set_attr "op_type" "RX")
1714 (set_attr "type" "la")])
1716 (define_insn "force_la_31"
1717 [(set (match_operand:SI 0 "register_operand" "=d,d")
1718 (match_operand:QI 1 "address_operand" "U,W"))
1719 (use (const_int 0))]
1724 [(set_attr "op_type" "RX")
1725 (set_attr "type" "la")
1726 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1729 ; movhi instruction pattern(s).
1732 (define_expand "movhi"
1733 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1734 (match_operand:HI 1 "general_operand" ""))]
1737 /* Make it explicit that loading a register from memory
1738 always sign-extends (at least) to SImode. */
1739 if (optimize && can_create_pseudo_p ()
1740 && register_operand (operands[0], VOIDmode)
1741 && GET_CODE (operands[1]) == MEM)
1743 rtx tmp = gen_reg_rtx (SImode);
1744 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1745 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1746 operands[1] = gen_lowpart (HImode, tmp);
1750 (define_insn "*movhi"
1751 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1752 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1764 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1765 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1766 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1767 (set_attr "z10prop" "z10_fr_E1,
1778 [(set (match_operand:HI 0 "register_operand" "")
1779 (mem:HI (match_operand 1 "address_operand" "")))]
1780 "GET_CODE (operands[1]) == SYMBOL_REF
1781 && CONSTANT_POOL_ADDRESS_P (operands[1])
1782 && get_pool_mode (operands[1]) == HImode
1783 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1784 [(set (match_dup 0) (match_dup 2))]
1785 "operands[2] = get_pool_constant (operands[1]);")
1788 ; movqi instruction pattern(s).
1791 (define_expand "movqi"
1792 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1793 (match_operand:QI 1 "general_operand" ""))]
1796 /* On z/Architecture, zero-extending from memory to register
1797 is just as fast as a QImode load. */
1798 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1799 && register_operand (operands[0], VOIDmode)
1800 && GET_CODE (operands[1]) == MEM)
1802 rtx tmp = gen_reg_rtx (word_mode);
1803 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1804 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1805 operands[1] = gen_lowpart (QImode, tmp);
1809 (define_insn "*movqi"
1810 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
1811 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
1822 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
1823 (set_attr "type" "lr,*,*,*,store,store,store,store")
1824 (set_attr "z10prop" "z10_fr_E1,
1834 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1835 (mem:QI (match_operand 1 "address_operand" "")))]
1836 "GET_CODE (operands[1]) == SYMBOL_REF
1837 && CONSTANT_POOL_ADDRESS_P (operands[1])
1838 && get_pool_mode (operands[1]) == QImode
1839 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1840 [(set (match_dup 0) (match_dup 2))]
1841 "operands[2] = get_pool_constant (operands[1]);")
1844 ; movstrictqi instruction pattern(s).
1847 (define_insn "*movstrictqi"
1848 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1849 (match_operand:QI 1 "memory_operand" "R,T"))]
1854 [(set_attr "op_type" "RX,RXY")
1855 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1858 ; movstricthi instruction pattern(s).
1861 (define_insn "*movstricthi"
1862 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1863 (match_operand:HI 1 "memory_operand" "Q,S"))
1864 (clobber (reg:CC CC_REGNUM))]
1869 [(set_attr "op_type" "RS,RSY")
1870 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1873 ; movstrictsi instruction pattern(s).
1876 (define_insn "movstrictsi"
1877 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1878 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1885 [(set_attr "op_type" "RR,RX,RXY,RRE")
1886 (set_attr "type" "lr,load,load,*")
1887 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1890 ; mov(tf|td) instruction pattern(s).
1893 (define_expand "mov<mode>"
1894 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1895 (match_operand:TD_TF 1 "general_operand" ""))]
1899 (define_insn "*mov<mode>_64"
1900 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1901 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1912 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1913 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")])
1915 (define_insn "*mov<mode>_31"
1916 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1917 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1924 [(set_attr "op_type" "RRE,RRE,*,*")
1925 (set_attr "type" "fsimptf,fsimptf,*,*")])
1927 ; TFmode in GPRs splitters
1930 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1931 (match_operand:TD_TF 1 "general_operand" ""))]
1932 "TARGET_64BIT && reload_completed
1933 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1934 [(set (match_dup 2) (match_dup 4))
1935 (set (match_dup 3) (match_dup 5))]
1937 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1938 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1939 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1940 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1944 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1945 (match_operand:TD_TF 1 "general_operand" ""))]
1946 "TARGET_64BIT && reload_completed
1947 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1948 [(set (match_dup 2) (match_dup 4))
1949 (set (match_dup 3) (match_dup 5))]
1951 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1952 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1953 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1954 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1958 [(set (match_operand:TD_TF 0 "register_operand" "")
1959 (match_operand:TD_TF 1 "memory_operand" ""))]
1960 "TARGET_64BIT && reload_completed
1961 && !FP_REG_P (operands[0])
1962 && !s_operand (operands[1], VOIDmode)"
1963 [(set (match_dup 0) (match_dup 1))]
1965 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1966 s390_load_address (addr, XEXP (operands[1], 0));
1967 operands[1] = replace_equiv_address (operands[1], addr);
1970 ; TFmode in BFPs splitters
1973 [(set (match_operand:TD_TF 0 "register_operand" "")
1974 (match_operand:TD_TF 1 "memory_operand" ""))]
1975 "reload_completed && offsettable_memref_p (operands[1])
1976 && FP_REG_P (operands[0])"
1977 [(set (match_dup 2) (match_dup 4))
1978 (set (match_dup 3) (match_dup 5))]
1980 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1982 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1984 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
1985 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
1989 [(set (match_operand:TD_TF 0 "memory_operand" "")
1990 (match_operand:TD_TF 1 "register_operand" ""))]
1991 "reload_completed && offsettable_memref_p (operands[0])
1992 && FP_REG_P (operands[1])"
1993 [(set (match_dup 2) (match_dup 4))
1994 (set (match_dup 3) (match_dup 5))]
1996 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
1997 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
1998 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2000 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2005 ; mov(df|dd) instruction pattern(s).
2008 (define_expand "mov<mode>"
2009 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2010 (match_operand:DD_DF 1 "general_operand" ""))]
2014 (define_insn "*mov<mode>_64dfp"
2015 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2016 "=f,f,f,d,f,f,R,T,d, d,RT")
2017 (match_operand:DD_DF 1 "general_operand"
2018 " G,f,d,f,R,T,f,f,d,RT, d"))]
2019 "TARGET_64BIT && TARGET_DFP"
2032 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
2033 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2034 fstoredf,fstoredf,lr,load,store")
2035 (set_attr "z10prop" "*,
2048 (define_insn "*mov<mode>_64"
2049 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
2050 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
2062 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
2063 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2064 fstore<mode>,fstore<mode>,lr,load,store")
2065 (set_attr "z10prop" "*,
2075 (define_insn "*mov<mode>_31"
2076 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2077 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2078 (match_operand:DD_DF 1 "general_operand"
2079 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2094 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2095 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2096 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2099 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2100 (match_operand:DD_DF 1 "general_operand" ""))]
2101 "!TARGET_64BIT && reload_completed
2102 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2103 [(set (match_dup 2) (match_dup 4))
2104 (set (match_dup 3) (match_dup 5))]
2106 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2107 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2108 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2109 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2113 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2114 (match_operand:DD_DF 1 "general_operand" ""))]
2115 "!TARGET_64BIT && reload_completed
2116 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2117 [(set (match_dup 2) (match_dup 4))
2118 (set (match_dup 3) (match_dup 5))]
2120 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2121 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2122 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2123 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2127 [(set (match_operand:DD_DF 0 "register_operand" "")
2128 (match_operand:DD_DF 1 "memory_operand" ""))]
2129 "!TARGET_64BIT && reload_completed
2130 && !FP_REG_P (operands[0])
2131 && !s_operand (operands[1], VOIDmode)"
2132 [(set (match_dup 0) (match_dup 1))]
2134 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2135 s390_load_address (addr, XEXP (operands[1], 0));
2136 operands[1] = replace_equiv_address (operands[1], addr);
2140 ; mov(sf|sd) instruction pattern(s).
2143 (define_insn "mov<mode>"
2144 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2145 "=f,f,f,f,R,T,d,d,d,R,T")
2146 (match_operand:SD_SF 1 "general_operand"
2147 " G,f,R,T,f,f,d,R,T,d,d"))]
2161 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
2162 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2163 fstore<mode>,fstore<mode>,lr,load,load,store,store")
2164 (set_attr "z10prop" "*,
2177 ; movcc instruction pattern
2180 (define_insn "movcc"
2181 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2182 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2192 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2193 (set_attr "type" "lr,*,*,store,store,load,load")
2194 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
2197 ; Block move (MVC) patterns.
2201 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2202 (match_operand:BLK 1 "memory_operand" "Q"))
2203 (use (match_operand 2 "const_int_operand" "n"))]
2204 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2205 "mvc\t%O0(%2,%R0),%S1"
2206 [(set_attr "op_type" "SS")])
2210 [(set (match_operand:BLK 0 "memory_operand" "")
2211 (match_operand:BLK 1 "memory_operand" ""))
2212 (use (match_operand 2 "const_int_operand" ""))])
2214 [(set (match_operand:BLK 3 "memory_operand" "")
2215 (match_operand:BLK 4 "memory_operand" ""))
2216 (use (match_operand 5 "const_int_operand" ""))])]
2217 "s390_offset_p (operands[0], operands[3], operands[2])
2218 && s390_offset_p (operands[1], operands[4], operands[2])
2219 && !s390_overlap_p (operands[0], operands[1],
2220 INTVAL (operands[2]) + INTVAL (operands[5]))
2221 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2223 [(set (match_dup 6) (match_dup 7))
2224 (use (match_dup 8))])]
2225 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2226 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2227 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2231 ; load_multiple pattern(s).
2233 ; ??? Due to reload problems with replacing registers inside match_parallel
2234 ; we currently support load_multiple/store_multiple only after reload.
2237 (define_expand "load_multiple"
2238 [(match_par_dup 3 [(set (match_operand 0 "" "")
2239 (match_operand 1 "" ""))
2240 (use (match_operand 2 "" ""))])]
2243 enum machine_mode mode;
2249 /* Support only loading a constant number of fixed-point registers from
2250 memory and only bother with this if more than two */
2251 if (GET_CODE (operands[2]) != CONST_INT
2252 || INTVAL (operands[2]) < 2
2253 || INTVAL (operands[2]) > 16
2254 || GET_CODE (operands[1]) != MEM
2255 || GET_CODE (operands[0]) != REG
2256 || REGNO (operands[0]) >= 16)
2259 count = INTVAL (operands[2]);
2260 regno = REGNO (operands[0]);
2261 mode = GET_MODE (operands[0]);
2262 if (mode != SImode && mode != word_mode)
2265 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2266 if (!can_create_pseudo_p ())
2268 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2270 from = XEXP (operands[1], 0);
2273 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2274 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2275 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2277 from = XEXP (XEXP (operands[1], 0), 0);
2278 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2285 from = force_reg (Pmode, XEXP (operands[1], 0));
2289 for (i = 0; i < count; i++)
2290 XVECEXP (operands[3], 0, i)
2291 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2292 change_address (operands[1], mode,
2293 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2296 (define_insn "*load_multiple_di"
2297 [(match_parallel 0 "load_multiple_operation"
2298 [(set (match_operand:DI 1 "register_operand" "=r")
2299 (match_operand:DI 2 "s_operand" "QS"))])]
2300 "reload_completed && word_mode == DImode"
2302 int words = XVECLEN (operands[0], 0);
2303 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2304 return "lmg\t%1,%0,%S2";
2306 [(set_attr "op_type" "RSY")
2307 (set_attr "type" "lm")])
2309 (define_insn "*load_multiple_si"
2310 [(match_parallel 0 "load_multiple_operation"
2311 [(set (match_operand:SI 1 "register_operand" "=r,r")
2312 (match_operand:SI 2 "s_operand" "Q,S"))])]
2315 int words = XVECLEN (operands[0], 0);
2316 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2317 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2319 [(set_attr "op_type" "RS,RSY")
2320 (set_attr "type" "lm")])
2323 ; store multiple pattern(s).
2326 (define_expand "store_multiple"
2327 [(match_par_dup 3 [(set (match_operand 0 "" "")
2328 (match_operand 1 "" ""))
2329 (use (match_operand 2 "" ""))])]
2332 enum machine_mode mode;
2338 /* Support only storing a constant number of fixed-point registers to
2339 memory and only bother with this if more than two. */
2340 if (GET_CODE (operands[2]) != CONST_INT
2341 || INTVAL (operands[2]) < 2
2342 || INTVAL (operands[2]) > 16
2343 || GET_CODE (operands[0]) != MEM
2344 || GET_CODE (operands[1]) != REG
2345 || REGNO (operands[1]) >= 16)
2348 count = INTVAL (operands[2]);
2349 regno = REGNO (operands[1]);
2350 mode = GET_MODE (operands[1]);
2351 if (mode != SImode && mode != word_mode)
2354 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2356 if (!can_create_pseudo_p ())
2358 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2360 to = XEXP (operands[0], 0);
2363 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2364 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2365 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2367 to = XEXP (XEXP (operands[0], 0), 0);
2368 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2375 to = force_reg (Pmode, XEXP (operands[0], 0));
2379 for (i = 0; i < count; i++)
2380 XVECEXP (operands[3], 0, i)
2381 = gen_rtx_SET (VOIDmode,
2382 change_address (operands[0], mode,
2383 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2384 gen_rtx_REG (mode, regno + i));
2387 (define_insn "*store_multiple_di"
2388 [(match_parallel 0 "store_multiple_operation"
2389 [(set (match_operand:DI 1 "s_operand" "=QS")
2390 (match_operand:DI 2 "register_operand" "r"))])]
2391 "reload_completed && word_mode == DImode"
2393 int words = XVECLEN (operands[0], 0);
2394 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2395 return "stmg\t%2,%0,%S1";
2397 [(set_attr "op_type" "RSY")
2398 (set_attr "type" "stm")])
2401 (define_insn "*store_multiple_si"
2402 [(match_parallel 0 "store_multiple_operation"
2403 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2404 (match_operand:SI 2 "register_operand" "r,r"))])]
2407 int words = XVECLEN (operands[0], 0);
2408 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2409 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2411 [(set_attr "op_type" "RS,RSY")
2412 (set_attr "type" "stm")])
2415 ;; String instructions.
2418 (define_insn "*execute_rl"
2419 [(match_parallel 0 ""
2420 [(unspec [(match_operand 1 "register_operand" "a")
2421 (match_operand 2 "" "")
2422 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2423 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2424 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2426 [(set_attr "op_type" "RIL")
2427 (set_attr "type" "cs")])
2429 (define_insn "*execute"
2430 [(match_parallel 0 ""
2431 [(unspec [(match_operand 1 "register_operand" "a")
2432 (match_operand:BLK 2 "memory_operand" "R")
2433 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2434 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2435 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2437 [(set_attr "op_type" "RX")
2438 (set_attr "type" "cs")])
2442 ; strlenM instruction pattern(s).
2445 (define_expand "strlen<mode>"
2446 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2449 (unspec:P [(const_int 0)
2450 (match_operand:BLK 1 "memory_operand" "")
2452 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2453 (clobber (scratch:P))
2454 (clobber (reg:CC CC_REGNUM))])
2456 [(set (match_operand:P 0 "register_operand" "")
2457 (minus:P (match_dup 4) (match_dup 5)))
2458 (clobber (reg:CC CC_REGNUM))])]
2461 operands[4] = gen_reg_rtx (Pmode);
2462 operands[5] = gen_reg_rtx (Pmode);
2463 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2464 operands[1] = replace_equiv_address (operands[1], operands[5]);
2467 (define_insn "*strlen<mode>"
2468 [(set (match_operand:P 0 "register_operand" "=a")
2469 (unspec:P [(match_operand:P 2 "general_operand" "0")
2470 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2472 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2473 (clobber (match_scratch:P 1 "=a"))
2474 (clobber (reg:CC CC_REGNUM))]
2476 "srst\t%0,%1\;jo\t.-4"
2477 [(set_attr "length" "8")
2478 (set_attr "type" "vs")])
2481 ; cmpstrM instruction pattern(s).
2484 (define_expand "cmpstrsi"
2485 [(set (reg:SI 0) (const_int 0))
2487 [(clobber (match_operand 3 "" ""))
2488 (clobber (match_dup 4))
2489 (set (reg:CCU CC_REGNUM)
2490 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2491 (match_operand:BLK 2 "memory_operand" "")))
2494 [(set (match_operand:SI 0 "register_operand" "=d")
2495 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2496 (clobber (reg:CC CC_REGNUM))])]
2499 /* As the result of CMPINT is inverted compared to what we need,
2500 we have to swap the operands. */
2501 rtx op1 = operands[2];
2502 rtx op2 = operands[1];
2503 rtx addr1 = gen_reg_rtx (Pmode);
2504 rtx addr2 = gen_reg_rtx (Pmode);
2506 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2507 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2508 operands[1] = replace_equiv_address_nv (op1, addr1);
2509 operands[2] = replace_equiv_address_nv (op2, addr2);
2510 operands[3] = addr1;
2511 operands[4] = addr2;
2514 (define_insn "*cmpstr<mode>"
2515 [(clobber (match_operand:P 0 "register_operand" "=d"))
2516 (clobber (match_operand:P 1 "register_operand" "=d"))
2517 (set (reg:CCU CC_REGNUM)
2518 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2519 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2522 "clst\t%0,%1\;jo\t.-4"
2523 [(set_attr "length" "8")
2524 (set_attr "type" "vs")])
2527 ; movstr instruction pattern.
2530 (define_expand "movstr"
2531 [(set (reg:SI 0) (const_int 0))
2533 [(clobber (match_dup 3))
2534 (set (match_operand:BLK 1 "memory_operand" "")
2535 (match_operand:BLK 2 "memory_operand" ""))
2536 (set (match_operand 0 "register_operand" "")
2537 (unspec [(match_dup 1)
2539 (reg:SI 0)] UNSPEC_MVST))
2540 (clobber (reg:CC CC_REGNUM))])]
2543 rtx addr1 = gen_reg_rtx (Pmode);
2544 rtx addr2 = gen_reg_rtx (Pmode);
2546 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2547 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2548 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2549 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2550 operands[3] = addr2;
2553 (define_insn "*movstr"
2554 [(clobber (match_operand:P 2 "register_operand" "=d"))
2555 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2556 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2557 (set (match_operand:P 0 "register_operand" "=d")
2558 (unspec [(mem:BLK (match_dup 1))
2559 (mem:BLK (match_dup 3))
2560 (reg:SI 0)] UNSPEC_MVST))
2561 (clobber (reg:CC CC_REGNUM))]
2563 "mvst\t%1,%2\;jo\t.-4"
2564 [(set_attr "length" "8")
2565 (set_attr "type" "vs")])
2569 ; movmemM instruction pattern(s).
2572 (define_expand "movmem<mode>"
2573 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2574 (match_operand:BLK 1 "memory_operand" "")) ; source
2575 (use (match_operand:GPR 2 "general_operand" "")) ; count
2576 (match_operand 3 "" "")]
2578 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2580 ; Move a block that is up to 256 bytes in length.
2581 ; The block length is taken as (operands[2] % 256) + 1.
2583 (define_expand "movmem_short"
2585 [(set (match_operand:BLK 0 "memory_operand" "")
2586 (match_operand:BLK 1 "memory_operand" ""))
2587 (use (match_operand 2 "nonmemory_operand" ""))
2588 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2589 (clobber (match_dup 3))])]
2591 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2593 (define_insn "*movmem_short"
2594 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2595 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2596 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2597 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2598 (clobber (match_scratch 4 "=X,X,X,&a"))]
2599 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2600 && GET_MODE (operands[4]) == Pmode"
2602 [(set_attr "type" "cs")
2603 (set_attr "cpu_facility" "*,*,z10,*")])
2606 [(set (match_operand:BLK 0 "memory_operand" "")
2607 (match_operand:BLK 1 "memory_operand" ""))
2608 (use (match_operand 2 "const_int_operand" ""))
2609 (use (match_operand 3 "immediate_operand" ""))
2610 (clobber (scratch))]
2613 [(set (match_dup 0) (match_dup 1))
2614 (use (match_dup 2))])]
2615 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2618 [(set (match_operand:BLK 0 "memory_operand" "")
2619 (match_operand:BLK 1 "memory_operand" ""))
2620 (use (match_operand 2 "register_operand" ""))
2621 (use (match_operand 3 "memory_operand" ""))
2622 (clobber (scratch))]
2625 [(unspec [(match_dup 2) (match_dup 3)
2626 (const_int 0)] UNSPEC_EXECUTE)
2627 (set (match_dup 0) (match_dup 1))
2628 (use (const_int 1))])]
2632 [(set (match_operand:BLK 0 "memory_operand" "")
2633 (match_operand:BLK 1 "memory_operand" ""))
2634 (use (match_operand 2 "register_operand" ""))
2635 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2636 (clobber (scratch))]
2637 "TARGET_Z10 && reload_completed"
2639 [(unspec [(match_dup 2) (const_int 0)
2640 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2641 (set (match_dup 0) (match_dup 1))
2642 (use (const_int 1))])]
2643 "operands[3] = gen_label_rtx ();")
2646 [(set (match_operand:BLK 0 "memory_operand" "")
2647 (match_operand:BLK 1 "memory_operand" ""))
2648 (use (match_operand 2 "register_operand" ""))
2649 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2650 (clobber (match_operand 3 "register_operand" ""))]
2651 "reload_completed && TARGET_CPU_ZARCH"
2652 [(set (match_dup 3) (label_ref (match_dup 4)))
2654 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2655 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2656 (set (match_dup 0) (match_dup 1))
2657 (use (const_int 1))])]
2658 "operands[4] = gen_label_rtx ();")
2660 ; Move a block of arbitrary length.
2662 (define_expand "movmem_long"
2664 [(clobber (match_dup 2))
2665 (clobber (match_dup 3))
2666 (set (match_operand:BLK 0 "memory_operand" "")
2667 (match_operand:BLK 1 "memory_operand" ""))
2668 (use (match_operand 2 "general_operand" ""))
2670 (clobber (reg:CC CC_REGNUM))])]
2673 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2674 rtx reg0 = gen_reg_rtx (dword_mode);
2675 rtx reg1 = gen_reg_rtx (dword_mode);
2676 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2677 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2678 rtx len0 = gen_lowpart (Pmode, reg0);
2679 rtx len1 = gen_lowpart (Pmode, reg1);
2681 emit_clobber (reg0);
2682 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2683 emit_move_insn (len0, operands[2]);
2685 emit_clobber (reg1);
2686 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2687 emit_move_insn (len1, operands[2]);
2689 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2690 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2695 (define_insn "*movmem_long"
2696 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2697 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2698 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2699 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2702 (clobber (reg:CC CC_REGNUM))]
2704 "mvcle\t%0,%1,0\;jo\t.-4"
2705 [(set_attr "length" "8")
2706 (set_attr "type" "vs")])
2713 (define_expand "signbit<mode>2"
2714 [(set (reg:CCZ CC_REGNUM)
2715 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2718 (set (match_operand:SI 0 "register_operand" "=d")
2719 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2722 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2725 (define_expand "isinf<mode>2"
2726 [(set (reg:CCZ CC_REGNUM)
2727 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2730 (set (match_operand:SI 0 "register_operand" "=d")
2731 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2734 operands[2] = GEN_INT (S390_TDC_INFINITY);
2737 ; This insn is used to generate all variants of the Test Data Class
2738 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2739 ; is the register to be tested and the second one is the bit mask
2740 ; specifying the required test(s).
2742 (define_insn "*TDC_insn_<mode>"
2743 [(set (reg:CCZ CC_REGNUM)
2744 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2745 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2747 "t<_d>c<xde><bt>\t%0,%1"
2748 [(set_attr "op_type" "RXE")
2749 (set_attr "type" "fsimp<mode>")])
2751 (define_insn_and_split "*ccz_to_int"
2752 [(set (match_operand:SI 0 "register_operand" "=d")
2753 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2754 UNSPEC_CCZ_TO_INT))]
2758 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2762 ; setmemM instruction pattern(s).
2765 (define_expand "setmem<mode>"
2766 [(set (match_operand:BLK 0 "memory_operand" "")
2767 (match_operand:QI 2 "general_operand" ""))
2768 (use (match_operand:GPR 1 "general_operand" ""))
2769 (match_operand 3 "" "")]
2771 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2773 ; Clear a block that is up to 256 bytes in length.
2774 ; The block length is taken as (operands[1] % 256) + 1.
2776 (define_expand "clrmem_short"
2778 [(set (match_operand:BLK 0 "memory_operand" "")
2780 (use (match_operand 1 "nonmemory_operand" ""))
2781 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2782 (clobber (match_dup 2))
2783 (clobber (reg:CC CC_REGNUM))])]
2785 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2787 (define_insn "*clrmem_short"
2788 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2790 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2791 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2792 (clobber (match_scratch 3 "=X,X,X,&a"))
2793 (clobber (reg:CC CC_REGNUM))]
2794 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2795 && GET_MODE (operands[3]) == Pmode"
2797 [(set_attr "type" "cs")
2798 (set_attr "cpu_facility" "*,*,z10,*")])
2801 [(set (match_operand:BLK 0 "memory_operand" "")
2803 (use (match_operand 1 "const_int_operand" ""))
2804 (use (match_operand 2 "immediate_operand" ""))
2806 (clobber (reg:CC CC_REGNUM))]
2809 [(set (match_dup 0) (const_int 0))
2811 (clobber (reg:CC CC_REGNUM))])]
2812 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2815 [(set (match_operand:BLK 0 "memory_operand" "")
2817 (use (match_operand 1 "register_operand" ""))
2818 (use (match_operand 2 "memory_operand" ""))
2820 (clobber (reg:CC CC_REGNUM))]
2823 [(unspec [(match_dup 1) (match_dup 2)
2824 (const_int 0)] UNSPEC_EXECUTE)
2825 (set (match_dup 0) (const_int 0))
2827 (clobber (reg:CC CC_REGNUM))])]
2831 [(set (match_operand:BLK 0 "memory_operand" "")
2833 (use (match_operand 1 "register_operand" ""))
2834 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2836 (clobber (reg:CC CC_REGNUM))]
2837 "TARGET_Z10 && reload_completed"
2839 [(unspec [(match_dup 1) (const_int 0)
2840 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2841 (set (match_dup 0) (const_int 0))
2843 (clobber (reg:CC CC_REGNUM))])]
2844 "operands[3] = gen_label_rtx ();")
2847 [(set (match_operand:BLK 0 "memory_operand" "")
2849 (use (match_operand 1 "register_operand" ""))
2850 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2851 (clobber (match_operand 2 "register_operand" ""))
2852 (clobber (reg:CC CC_REGNUM))]
2853 "reload_completed && TARGET_CPU_ZARCH"
2854 [(set (match_dup 2) (label_ref (match_dup 3)))
2856 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2857 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2858 (set (match_dup 0) (const_int 0))
2860 (clobber (reg:CC CC_REGNUM))])]
2861 "operands[3] = gen_label_rtx ();")
2863 ; Initialize a block of arbitrary length with (operands[2] % 256).
2865 (define_expand "setmem_long"
2867 [(clobber (match_dup 1))
2868 (set (match_operand:BLK 0 "memory_operand" "")
2869 (match_operand 2 "shift_count_or_setmem_operand" ""))
2870 (use (match_operand 1 "general_operand" ""))
2872 (clobber (reg:CC CC_REGNUM))])]
2875 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2876 rtx reg0 = gen_reg_rtx (dword_mode);
2877 rtx reg1 = gen_reg_rtx (dword_mode);
2878 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2879 rtx len0 = gen_lowpart (Pmode, reg0);
2881 emit_clobber (reg0);
2882 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2883 emit_move_insn (len0, operands[1]);
2885 emit_move_insn (reg1, const0_rtx);
2887 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2892 (define_insn "*setmem_long"
2893 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2894 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2895 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2897 (use (match_operand:<DBL> 1 "register_operand" "d"))
2898 (clobber (reg:CC CC_REGNUM))]
2900 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2901 [(set_attr "length" "8")
2902 (set_attr "type" "vs")])
2904 (define_insn "*setmem_long_and"
2905 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2906 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2907 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2908 (match_operand 4 "const_int_operand" "n")))
2910 (use (match_operand:<DBL> 1 "register_operand" "d"))
2911 (clobber (reg:CC CC_REGNUM))]
2912 "(INTVAL (operands[4]) & 255) == 255"
2913 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2914 [(set_attr "length" "8")
2915 (set_attr "type" "vs")])
2917 ; cmpmemM instruction pattern(s).
2920 (define_expand "cmpmemsi"
2921 [(set (match_operand:SI 0 "register_operand" "")
2922 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2923 (match_operand:BLK 2 "memory_operand" "") ) )
2924 (use (match_operand:SI 3 "general_operand" ""))
2925 (use (match_operand:SI 4 "" ""))]
2927 "s390_expand_cmpmem (operands[0], operands[1],
2928 operands[2], operands[3]); DONE;")
2930 ; Compare a block that is up to 256 bytes in length.
2931 ; The block length is taken as (operands[2] % 256) + 1.
2933 (define_expand "cmpmem_short"
2935 [(set (reg:CCU CC_REGNUM)
2936 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2937 (match_operand:BLK 1 "memory_operand" "")))
2938 (use (match_operand 2 "nonmemory_operand" ""))
2939 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2940 (clobber (match_dup 3))])]
2942 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2944 (define_insn "*cmpmem_short"
2945 [(set (reg:CCU CC_REGNUM)
2946 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
2947 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
2948 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2949 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2950 (clobber (match_scratch 4 "=X,X,X,&a"))]
2951 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2952 && GET_MODE (operands[4]) == Pmode"
2954 [(set_attr "type" "cs")
2955 (set_attr "cpu_facility" "*,*,z10,*")])
2958 [(set (reg:CCU CC_REGNUM)
2959 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2960 (match_operand:BLK 1 "memory_operand" "")))
2961 (use (match_operand 2 "const_int_operand" ""))
2962 (use (match_operand 3 "immediate_operand" ""))
2963 (clobber (scratch))]
2966 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2967 (use (match_dup 2))])]
2968 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2971 [(set (reg:CCU CC_REGNUM)
2972 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2973 (match_operand:BLK 1 "memory_operand" "")))
2974 (use (match_operand 2 "register_operand" ""))
2975 (use (match_operand 3 "memory_operand" ""))
2976 (clobber (scratch))]
2979 [(unspec [(match_dup 2) (match_dup 3)
2980 (const_int 0)] UNSPEC_EXECUTE)
2981 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2982 (use (const_int 1))])]
2986 [(set (reg:CCU CC_REGNUM)
2987 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2988 (match_operand:BLK 1 "memory_operand" "")))
2989 (use (match_operand 2 "register_operand" ""))
2990 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2991 (clobber (scratch))]
2992 "TARGET_Z10 && reload_completed"
2994 [(unspec [(match_dup 2) (const_int 0)
2995 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2996 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2997 (use (const_int 1))])]
2998 "operands[4] = gen_label_rtx ();")
3001 [(set (reg:CCU CC_REGNUM)
3002 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3003 (match_operand:BLK 1 "memory_operand" "")))
3004 (use (match_operand 2 "register_operand" ""))
3005 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3006 (clobber (match_operand 3 "register_operand" ""))]
3007 "reload_completed && TARGET_CPU_ZARCH"
3008 [(set (match_dup 3) (label_ref (match_dup 4)))
3010 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3011 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3012 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3013 (use (const_int 1))])]
3014 "operands[4] = gen_label_rtx ();")
3016 ; Compare a block of arbitrary length.
3018 (define_expand "cmpmem_long"
3020 [(clobber (match_dup 2))
3021 (clobber (match_dup 3))
3022 (set (reg:CCU CC_REGNUM)
3023 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3024 (match_operand:BLK 1 "memory_operand" "")))
3025 (use (match_operand 2 "general_operand" ""))
3026 (use (match_dup 3))])]
3029 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
3030 rtx reg0 = gen_reg_rtx (dword_mode);
3031 rtx reg1 = gen_reg_rtx (dword_mode);
3032 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
3033 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
3034 rtx len0 = gen_lowpart (Pmode, reg0);
3035 rtx len1 = gen_lowpart (Pmode, reg1);
3037 emit_clobber (reg0);
3038 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3039 emit_move_insn (len0, operands[2]);
3041 emit_clobber (reg1);
3042 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3043 emit_move_insn (len1, operands[2]);
3045 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3046 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3051 (define_insn "*cmpmem_long"
3052 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3053 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3054 (set (reg:CCU CC_REGNUM)
3055 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3056 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3058 (use (match_dup 3))]
3060 "clcle\t%0,%1,0\;jo\t.-4"
3061 [(set_attr "length" "8")
3062 (set_attr "type" "vs")])
3064 ; Convert CCUmode condition code to integer.
3065 ; Result is zero if EQ, positive if LTU, negative if GTU.
3067 (define_insn_and_split "cmpint"
3068 [(set (match_operand:SI 0 "register_operand" "=d")
3069 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3071 (clobber (reg:CC CC_REGNUM))]
3075 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3077 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3078 (clobber (reg:CC CC_REGNUM))])])
3080 (define_insn_and_split "*cmpint_cc"
3081 [(set (reg CC_REGNUM)
3082 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3085 (set (match_operand:SI 0 "register_operand" "=d")
3086 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3087 "s390_match_ccmode (insn, CCSmode)"
3089 "&& reload_completed"
3090 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3092 [(set (match_dup 2) (match_dup 3))
3093 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3095 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3096 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3097 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3100 (define_insn_and_split "*cmpint_sign"
3101 [(set (match_operand:DI 0 "register_operand" "=d")
3102 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3103 UNSPEC_CCU_TO_INT)))
3104 (clobber (reg:CC CC_REGNUM))]
3107 "&& reload_completed"
3108 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3110 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3111 (clobber (reg:CC CC_REGNUM))])])
3113 (define_insn_and_split "*cmpint_sign_cc"
3114 [(set (reg CC_REGNUM)
3115 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3116 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3117 UNSPEC_CCU_TO_INT) 0)
3118 (const_int 32)) (const_int 32))
3120 (set (match_operand:DI 0 "register_operand" "=d")
3121 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3122 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
3124 "&& reload_completed"
3125 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3127 [(set (match_dup 2) (match_dup 3))
3128 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3130 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3131 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3132 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3137 ;;- Conversion instructions.
3140 (define_insn "*sethighpartsi"
3141 [(set (match_operand:SI 0 "register_operand" "=d,d")
3142 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3143 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3144 (clobber (reg:CC CC_REGNUM))]
3149 [(set_attr "op_type" "RS,RSY")
3150 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3152 (define_insn "*sethighpartdi_64"
3153 [(set (match_operand:DI 0 "register_operand" "=d")
3154 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3155 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3156 (clobber (reg:CC CC_REGNUM))]
3159 [(set_attr "op_type" "RSY")
3160 (set_attr "z10prop" "z10_super")])
3162 (define_insn "*sethighpartdi_31"
3163 [(set (match_operand:DI 0 "register_operand" "=d,d")
3164 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3165 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3166 (clobber (reg:CC CC_REGNUM))]
3171 [(set_attr "op_type" "RS,RSY")
3172 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3175 (define_insn_and_split "*extzv<mode>"
3176 [(set (match_operand:GPR 0 "register_operand" "=d")
3177 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3178 (match_operand 2 "const_int_operand" "n")
3180 (clobber (reg:CC CC_REGNUM))]
3181 "INTVAL (operands[2]) > 0
3182 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3184 "&& reload_completed"
3186 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3187 (clobber (reg:CC CC_REGNUM))])
3188 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3190 int bitsize = INTVAL (operands[2]);
3191 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3192 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3194 operands[1] = adjust_address (operands[1], BLKmode, 0);
3195 set_mem_size (operands[1], GEN_INT (size));
3196 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3197 operands[3] = GEN_INT (mask);
3200 (define_insn_and_split "*extv<mode>"
3201 [(set (match_operand:GPR 0 "register_operand" "=d")
3202 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3203 (match_operand 2 "const_int_operand" "n")
3205 (clobber (reg:CC CC_REGNUM))]
3206 "INTVAL (operands[2]) > 0
3207 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3209 "&& reload_completed"
3211 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3212 (clobber (reg:CC CC_REGNUM))])
3214 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3215 (clobber (reg:CC CC_REGNUM))])]
3217 int bitsize = INTVAL (operands[2]);
3218 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3219 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3221 operands[1] = adjust_address (operands[1], BLKmode, 0);
3222 set_mem_size (operands[1], GEN_INT (size));
3223 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3224 operands[3] = GEN_INT (mask);
3228 ; insv instruction patterns
3231 (define_expand "insv"
3232 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3233 (match_operand 1 "const_int_operand" "")
3234 (match_operand 2 "const_int_operand" ""))
3235 (match_operand 3 "general_operand" ""))]
3238 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3243 (define_insn "*insv<mode>_z10"
3244 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3245 (match_operand 1 "const_int_operand" "I")
3246 (match_operand 2 "const_int_operand" "I"))
3247 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3248 (clobber (reg:CC CC_REGNUM))]
3250 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3251 GET_MODE_BITSIZE (<MODE>mode)"
3253 int start = INTVAL (operands[2]);
3254 int size = INTVAL (operands[1]);
3255 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3257 operands[2] = GEN_INT (offset + start); /* start bit position */
3258 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3259 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3260 start - size); /* left shift count */
3262 return "risbg\t%0,%3,%b2,%b1,%b4";
3264 [(set_attr "op_type" "RIE")
3265 (set_attr "z10prop" "z10_super_E1")])
3267 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3268 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3269 (define_insn "*insv<mode>_z10_noshift"
3270 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3271 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3272 (match_operand 2 "const_int_operand" "n"))
3273 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3274 (match_operand 4 "const_int_operand" "n"))))
3275 (clobber (reg:CC CC_REGNUM))]
3277 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3278 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3279 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3285 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3286 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3288 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3289 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3290 operands[7] = const0_rtx; /* left shift count */
3292 return "risbg\t%0,%1,%b5,%b6,%b7";
3294 [(set_attr "op_type" "RIE")
3295 (set_attr "z10prop" "z10_super_E1")])
3297 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3298 (define_insn "*insv<mode>_or_z10_noshift"
3299 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3300 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3301 (match_operand 2 "const_int_operand" "n"))
3302 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3303 (clobber (reg:CC CC_REGNUM))]
3305 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3306 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3311 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3312 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3314 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3315 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3316 operands[6] = const0_rtx; /* left shift count */
3318 return "rosbg\t%0,%1,%b4,%b5,%b6";
3320 [(set_attr "op_type" "RIE")])
3322 (define_insn "*insv<mode>_mem_reg"
3323 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
3324 (match_operand 1 "const_int_operand" "n,n")
3326 (match_operand:P 2 "register_operand" "d,d"))]
3327 "INTVAL (operands[1]) > 0
3328 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3329 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3331 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3333 operands[1] = GEN_INT ((1ul << size) - 1);
3334 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3335 : "stcmy\t%2,%1,%S0";
3337 [(set_attr "op_type" "RS,RSY")
3338 (set_attr "z10prop" "z10_super,z10_super")])
3340 (define_insn "*insvdi_mem_reghigh"
3341 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3342 (match_operand 1 "const_int_operand" "n")
3344 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3347 && INTVAL (operands[1]) > 0
3348 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3349 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3351 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3353 operands[1] = GEN_INT ((1ul << size) - 1);
3354 return "stcmh\t%2,%1,%S0";
3356 [(set_attr "op_type" "RSY")
3357 (set_attr "z10prop" "z10_super")])
3359 (define_insn "*insv<mode>_reg_imm"
3360 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3362 (match_operand 1 "const_int_operand" "n"))
3363 (match_operand:P 2 "const_int_operand" "n"))]
3365 && INTVAL (operands[1]) >= 0
3366 && INTVAL (operands[1]) < BITS_PER_WORD
3367 && INTVAL (operands[1]) % 16 == 0"
3369 switch (BITS_PER_WORD - INTVAL (operands[1]))
3371 case 64: return "iihh\t%0,%x2"; break;
3372 case 48: return "iihl\t%0,%x2"; break;
3373 case 32: return "iilh\t%0,%x2"; break;
3374 case 16: return "iill\t%0,%x2"; break;
3375 default: gcc_unreachable();
3378 [(set_attr "op_type" "RI")
3379 (set_attr "z10prop" "z10_super_E1")])
3382 (define_insn "*insv<mode>_reg_extimm"
3383 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3385 (match_operand 1 "const_int_operand" "n"))
3386 (match_operand:P 2 "const_int_operand" "n"))]
3388 && INTVAL (operands[1]) >= 0
3389 && INTVAL (operands[1]) < BITS_PER_WORD
3390 && INTVAL (operands[1]) % 32 == 0"
3392 switch (BITS_PER_WORD - INTVAL (operands[1]))
3394 case 64: return "iihf\t%0,%o2"; break;
3395 case 32: return "iilf\t%0,%o2"; break;
3396 default: gcc_unreachable();
3399 [(set_attr "op_type" "RIL")
3400 (set_attr "z10prop" "z10_fwd_E1")])
3404 ; extendsidi2 instruction pattern(s).
3407 (define_expand "extendsidi2"
3408 [(set (match_operand:DI 0 "register_operand" "")
3409 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3414 emit_clobber (operands[0]);
3415 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3416 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3417 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3422 (define_insn "*extendsidi2"
3423 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3424 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3430 [(set_attr "op_type" "RRE,RXY,RIL")
3431 (set_attr "type" "*,*,larl")
3432 (set_attr "cpu_facility" "*,*,z10")
3433 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3436 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3439 (define_expand "extend<HQI:mode><DSI:mode>2"
3440 [(set (match_operand:DSI 0 "register_operand" "")
3441 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3444 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
3446 rtx tmp = gen_reg_rtx (SImode);
3447 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3448 emit_insn (gen_extendsidi2 (operands[0], tmp));
3451 else if (!TARGET_EXTIMM)
3453 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3454 GET_MODE_BITSIZE (<HQI:MODE>mode));
3456 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3457 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3458 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3464 ; extendhidi2 instruction pattern(s).
3467 (define_insn "*extendhidi2_extimm"
3468 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3469 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3470 "TARGET_64BIT && TARGET_EXTIMM"
3475 [(set_attr "op_type" "RRE,RXY,RIL")
3476 (set_attr "type" "*,*,larl")
3477 (set_attr "cpu_facility" "extimm,extimm,z10")
3478 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3480 (define_insn "*extendhidi2"
3481 [(set (match_operand:DI 0 "register_operand" "=d")
3482 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3485 [(set_attr "op_type" "RXY")
3486 (set_attr "z10prop" "z10_super_E1")])
3489 ; extendhisi2 instruction pattern(s).
3492 (define_insn "*extendhisi2_extimm"
3493 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3494 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3501 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3502 (set_attr "type" "*,*,*,larl")
3503 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3504 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3506 (define_insn "*extendhisi2"
3507 [(set (match_operand:SI 0 "register_operand" "=d,d")
3508 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3513 [(set_attr "op_type" "RX,RXY")
3514 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3517 ; extendqi(si|di)2 instruction pattern(s).
3520 ; lbr, lgbr, lb, lgb
3521 (define_insn "*extendqi<mode>2_extimm"
3522 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3523 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3528 [(set_attr "op_type" "RRE,RXY")
3529 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3532 (define_insn "*extendqi<mode>2"
3533 [(set (match_operand:GPR 0 "register_operand" "=d")
3534 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3535 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3537 [(set_attr "op_type" "RXY")
3538 (set_attr "z10prop" "z10_super_E1")])
3540 (define_insn_and_split "*extendqi<mode>2_short_displ"
3541 [(set (match_operand:GPR 0 "register_operand" "=d")
3542 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3543 (clobber (reg:CC CC_REGNUM))]
3544 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3546 "&& reload_completed"
3548 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3549 (clobber (reg:CC CC_REGNUM))])
3551 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3552 (clobber (reg:CC CC_REGNUM))])]
3554 operands[1] = adjust_address (operands[1], BLKmode, 0);
3555 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3556 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3557 - GET_MODE_BITSIZE (QImode));
3561 ; zero_extendsidi2 instruction pattern(s).
3564 (define_expand "zero_extendsidi2"
3565 [(set (match_operand:DI 0 "register_operand" "")
3566 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3571 emit_clobber (operands[0]);
3572 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3573 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3578 (define_insn "*zero_extendsidi2"
3579 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3580 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3586 [(set_attr "op_type" "RRE,RXY,RIL")
3587 (set_attr "type" "*,*,larl")
3588 (set_attr "cpu_facility" "*,*,z10")
3589 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3592 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3595 (define_insn "*llgt_sidi"
3596 [(set (match_operand:DI 0 "register_operand" "=d")
3597 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3598 (const_int 2147483647)))]
3601 [(set_attr "op_type" "RXE")
3602 (set_attr "z10prop" "z10_super_E1")])
3604 (define_insn_and_split "*llgt_sidi_split"
3605 [(set (match_operand:DI 0 "register_operand" "=d")
3606 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3607 (const_int 2147483647)))
3608 (clobber (reg:CC CC_REGNUM))]
3611 "&& reload_completed"
3613 (and:DI (subreg:DI (match_dup 1) 0)
3614 (const_int 2147483647)))]
3617 (define_insn "*llgt_sisi"
3618 [(set (match_operand:SI 0 "register_operand" "=d,d")
3619 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3620 (const_int 2147483647)))]
3625 [(set_attr "op_type" "RRE,RXE")
3626 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3628 (define_insn "*llgt_didi"
3629 [(set (match_operand:DI 0 "register_operand" "=d,d")
3630 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3631 (const_int 2147483647)))]
3636 [(set_attr "op_type" "RRE,RXE")
3637 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3640 [(set (match_operand:GPR 0 "register_operand" "")
3641 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3642 (const_int 2147483647)))
3643 (clobber (reg:CC CC_REGNUM))]
3644 "TARGET_ZARCH && reload_completed"
3646 (and:GPR (match_dup 1)
3647 (const_int 2147483647)))]
3651 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3654 (define_expand "zero_extend<mode>di2"
3655 [(set (match_operand:DI 0 "register_operand" "")
3656 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3661 rtx tmp = gen_reg_rtx (SImode);
3662 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3663 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3666 else if (!TARGET_EXTIMM)
3668 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3669 GET_MODE_BITSIZE(<MODE>mode));
3670 operands[1] = gen_lowpart (DImode, operands[1]);
3671 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3672 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3677 (define_expand "zero_extend<mode>si2"
3678 [(set (match_operand:SI 0 "register_operand" "")
3679 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3684 operands[1] = gen_lowpart (SImode, operands[1]);
3685 emit_insn (gen_andsi3 (operands[0], operands[1],
3686 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3692 (define_insn "*zero_extendhi<mode>2_z10"
3693 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3694 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3700 [(set_attr "op_type" "RXY,RRE,RIL")
3701 (set_attr "type" "*,*,larl")
3702 (set_attr "cpu_facility" "*,*,z10")
3703 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3705 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3706 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3707 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3708 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3713 [(set_attr "op_type" "RRE,RXY")
3714 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3717 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3718 [(set (match_operand:GPR 0 "register_operand" "=d")
3719 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3720 "TARGET_ZARCH && !TARGET_EXTIMM"
3722 [(set_attr "op_type" "RXY")
3723 (set_attr "z10prop" "z10_fwd_A3")])
3725 (define_insn_and_split "*zero_extendhisi2_31"
3726 [(set (match_operand:SI 0 "register_operand" "=&d")
3727 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3728 (clobber (reg:CC CC_REGNUM))]
3731 "&& reload_completed"
3732 [(set (match_dup 0) (const_int 0))
3734 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3735 (clobber (reg:CC CC_REGNUM))])]
3736 "operands[2] = gen_lowpart (HImode, operands[0]);")
3738 (define_insn_and_split "*zero_extendqisi2_31"
3739 [(set (match_operand:SI 0 "register_operand" "=&d")
3740 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3743 "&& reload_completed"
3744 [(set (match_dup 0) (const_int 0))
3745 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3746 "operands[2] = gen_lowpart (QImode, operands[0]);")
3749 ; zero_extendqihi2 instruction pattern(s).
3752 (define_expand "zero_extendqihi2"
3753 [(set (match_operand:HI 0 "register_operand" "")
3754 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3755 "TARGET_ZARCH && !TARGET_EXTIMM"
3757 operands[1] = gen_lowpart (HImode, operands[1]);
3758 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3762 (define_insn "*zero_extendqihi2_64"
3763 [(set (match_operand:HI 0 "register_operand" "=d")
3764 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3765 "TARGET_ZARCH && !TARGET_EXTIMM"
3767 [(set_attr "op_type" "RXY")
3768 (set_attr "z10prop" "z10_fwd_A3")])
3770 (define_insn_and_split "*zero_extendqihi2_31"
3771 [(set (match_operand:HI 0 "register_operand" "=&d")
3772 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3775 "&& reload_completed"
3776 [(set (match_dup 0) (const_int 0))
3777 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3778 "operands[2] = gen_lowpart (QImode, operands[0]);")
3781 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3784 (define_expand "fixuns_truncdddi2"
3786 [(set (match_operand:DI 0 "register_operand" "")
3787 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3788 (clobber (match_scratch:TD 2 "=f"))])]
3792 rtx label1 = gen_label_rtx ();
3793 rtx label2 = gen_label_rtx ();
3794 rtx temp = gen_reg_rtx (TDmode);
3795 REAL_VALUE_TYPE cmp, sub;
3797 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3798 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3800 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3801 solution is doing the check and the subtraction in TD mode and using a
3802 TD -> DI convert afterwards. */
3803 emit_insn (gen_extendddtd2 (temp, operands[1]));
3804 temp = force_reg (TDmode, temp);
3805 emit_insn (gen_cmptd (temp,
3806 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3807 emit_jump_insn (gen_blt (label1));
3808 emit_insn (gen_subtd3 (temp, temp,
3809 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3810 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3813 emit_label (label1);
3814 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3815 emit_label (label2);
3819 (define_expand "fixuns_trunctddi2"
3820 [(set (match_operand:DI 0 "register_operand" "")
3821 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3824 rtx label1 = gen_label_rtx ();
3825 rtx label2 = gen_label_rtx ();
3826 rtx temp = gen_reg_rtx (TDmode);
3827 REAL_VALUE_TYPE cmp, sub;
3829 operands[1] = force_reg (TDmode, operands[1]);
3830 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3831 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3833 emit_insn (gen_cmptd (operands[1],
3834 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3835 emit_jump_insn (gen_blt (label1));
3836 emit_insn (gen_subtd3 (temp, operands[1],
3837 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3838 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3841 emit_label (label1);
3842 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3843 emit_label (label2);
3848 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3849 ; instruction pattern(s).
3852 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3853 [(set (match_operand:GPR 0 "register_operand" "")
3854 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3857 rtx label1 = gen_label_rtx ();
3858 rtx label2 = gen_label_rtx ();
3859 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3860 REAL_VALUE_TYPE cmp, sub;
3862 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3863 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3864 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3866 emit_insn (gen_cmp<BFP:mode> (operands[1],
3867 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
3868 emit_jump_insn (gen_blt (label1));
3869 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3870 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3871 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3875 emit_label (label1);
3876 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3877 operands[1], GEN_INT (5)));
3878 emit_label (label2);
3882 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3883 [(set (match_operand:GPR 0 "register_operand" "")
3884 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3887 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3892 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3893 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3894 [(set (match_operand:GPR 0 "register_operand" "=d")
3895 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3896 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3897 (clobber (reg:CC CC_REGNUM))]
3899 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3900 [(set_attr "op_type" "RRE")
3901 (set_attr "type" "ftoi")])
3905 ; fix_trunc(td|dd)di2 instruction pattern(s).
3908 (define_expand "fix_trunc<mode>di2"
3909 [(set (match_operand:DI 0 "register_operand" "")
3910 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3911 "TARGET_64BIT && TARGET_HARD_DFP"
3913 operands[1] = force_reg (<MODE>mode, operands[1]);
3914 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3920 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3921 [(set (match_operand:DI 0 "register_operand" "=d")
3922 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3923 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3924 (clobber (reg:CC CC_REGNUM))]
3925 "TARGET_64BIT && TARGET_HARD_DFP"
3926 "cg<DFP:xde>tr\t%0,%h2,%1"
3927 [(set_attr "op_type" "RRF")
3928 (set_attr "type" "ftoidfp")])
3932 ; fix_trunctf(si|di)2 instruction pattern(s).
3935 (define_expand "fix_trunctf<mode>2"
3936 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3937 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3938 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3939 (clobber (reg:CC CC_REGNUM))])]
3945 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
3948 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
3949 (define_insn "floatdi<mode>2"
3950 [(set (match_operand:FP 0 "register_operand" "=f")
3951 (float:FP (match_operand:DI 1 "register_operand" "d")))]
3952 "TARGET_64BIT && TARGET_HARD_FLOAT"
3953 "c<xde>g<bt>r\t%0,%1"
3954 [(set_attr "op_type" "RRE")
3955 (set_attr "type" "itof<mode>" )])
3957 ; cxfbr, cdfbr, cefbr
3958 (define_insn "floatsi<mode>2"
3959 [(set (match_operand:BFP 0 "register_operand" "=f")
3960 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
3963 [(set_attr "op_type" "RRE")
3964 (set_attr "type" "itof<mode>" )])
3968 ; truncdfsf2 instruction pattern(s).
3971 (define_insn "truncdfsf2"
3972 [(set (match_operand:SF 0 "register_operand" "=f")
3973 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3976 [(set_attr "op_type" "RRE")
3977 (set_attr "type" "ftruncdf")])
3980 ; trunctf(df|sf)2 instruction pattern(s).
3984 (define_insn "trunctf<mode>2"
3985 [(set (match_operand:DSF 0 "register_operand" "=f")
3986 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
3987 (clobber (match_scratch:TF 2 "=f"))]
3989 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
3990 [(set_attr "length" "6")
3991 (set_attr "type" "ftrunctf")])
3994 ; trunctddd2 and truncddsd2 instruction pattern(s).
3997 (define_insn "trunctddd2"
3998 [(set (match_operand:DD 0 "register_operand" "=f")
3999 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4000 (clobber (match_scratch:TD 2 "=f"))]
4002 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4003 [(set_attr "length" "6")
4004 (set_attr "type" "ftruncdd")])
4006 (define_insn "truncddsd2"
4007 [(set (match_operand:SD 0 "register_operand" "=f")
4008 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4011 [(set_attr "op_type" "RRF")
4012 (set_attr "type" "ftruncsd")])
4015 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4018 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4019 (define_insn "extend<DSF:mode><BFP:mode>2"
4020 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4021 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4023 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4025 l<BFP:xde><DSF:xde>br\t%0,%1
4026 l<BFP:xde><DSF:xde>b\t%0,%1"
4027 [(set_attr "op_type" "RRE,RXE")
4028 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4031 ; extendddtd2 and extendsddd2 instruction pattern(s).
4034 (define_insn "extendddtd2"
4035 [(set (match_operand:TD 0 "register_operand" "=f")
4036 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4039 [(set_attr "op_type" "RRF")
4040 (set_attr "type" "fsimptf")])
4042 (define_insn "extendsddd2"
4043 [(set (match_operand:DD 0 "register_operand" "=f")
4044 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4047 [(set_attr "op_type" "RRF")
4048 (set_attr "type" "fsimptf")])
4050 ; Binary <-> Decimal floating point trunc patterns
4053 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4054 [(set (reg:DFP_ALL FPR0_REGNUM)
4055 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4056 (use (reg:SI GPR0_REGNUM))
4057 (clobber (reg:CC CC_REGNUM))]
4061 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4062 [(set (reg:BFP FPR0_REGNUM)
4063 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4064 (use (reg:SI GPR0_REGNUM))
4065 (clobber (reg:CC CC_REGNUM))]
4069 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4070 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4071 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4073 [(set (reg:DFP_ALL FPR0_REGNUM)
4074 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4075 (use (reg:SI GPR0_REGNUM))
4076 (clobber (reg:CC CC_REGNUM))])
4077 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4078 (reg:DFP_ALL FPR0_REGNUM))]
4080 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4082 HOST_WIDE_INT flags;
4084 flags = (PFPO_CONVERT |
4085 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4086 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4088 operands[2] = GEN_INT (flags);
4091 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4092 [(set (reg:DFP_ALL FPR2_REGNUM)
4093 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4094 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4096 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4097 (use (reg:SI GPR0_REGNUM))
4098 (clobber (reg:CC CC_REGNUM))])
4099 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4101 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4103 HOST_WIDE_INT flags;
4105 flags = (PFPO_CONVERT |
4106 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4107 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4109 operands[2] = GEN_INT (flags);
4113 ; Binary <-> Decimal floating point extend patterns
4116 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4117 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4118 (use (reg:SI GPR0_REGNUM))
4119 (clobber (reg:CC CC_REGNUM))]
4123 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4124 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4125 (use (reg:SI GPR0_REGNUM))
4126 (clobber (reg:CC CC_REGNUM))]
4130 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4131 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4132 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4134 [(set (reg:DFP_ALL FPR0_REGNUM)
4135 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4136 (use (reg:SI GPR0_REGNUM))
4137 (clobber (reg:CC CC_REGNUM))])
4138 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4139 (reg:DFP_ALL FPR0_REGNUM))]
4141 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4143 HOST_WIDE_INT flags;
4145 flags = (PFPO_CONVERT |
4146 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4147 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4149 operands[2] = GEN_INT (flags);
4152 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4153 [(set (reg:DFP_ALL FPR2_REGNUM)
4154 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4155 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4157 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4158 (use (reg:SI GPR0_REGNUM))
4159 (clobber (reg:CC CC_REGNUM))])
4160 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4162 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4164 HOST_WIDE_INT flags;
4166 flags = (PFPO_CONVERT |
4167 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4168 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4170 operands[2] = GEN_INT (flags);
4175 ;; ARITHMETIC OPERATIONS
4177 ; arithmetic operations set the ConditionCode,
4178 ; because of unpredictable Bits in Register for Halfword and Byte
4179 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4182 ;;- Add instructions.
4186 ; addti3 instruction pattern(s).
4189 (define_insn_and_split "addti3"
4190 [(set (match_operand:TI 0 "register_operand" "=&d")
4191 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4192 (match_operand:TI 2 "general_operand" "do") ) )
4193 (clobber (reg:CC CC_REGNUM))]
4196 "&& reload_completed"
4198 [(set (reg:CCL1 CC_REGNUM)
4199 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4201 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4203 [(set (match_dup 3) (plus:DI
4204 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4205 (match_dup 4)) (match_dup 5)))
4206 (clobber (reg:CC CC_REGNUM))])]
4207 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4208 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4209 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4210 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4211 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4212 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4215 ; adddi3 instruction pattern(s).
4218 (define_expand "adddi3"
4220 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4221 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4222 (match_operand:DI 2 "general_operand" "")))
4223 (clobber (reg:CC CC_REGNUM))])]
4227 (define_insn "*adddi3_sign"
4228 [(set (match_operand:DI 0 "register_operand" "=d,d")
4229 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4230 (match_operand:DI 1 "register_operand" "0,0")))
4231 (clobber (reg:CC CC_REGNUM))]
4236 [(set_attr "op_type" "RRE,RXY")])
4238 (define_insn "*adddi3_zero_cc"
4239 [(set (reg CC_REGNUM)
4240 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4241 (match_operand:DI 1 "register_operand" "0,0"))
4243 (set (match_operand:DI 0 "register_operand" "=d,d")
4244 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4245 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4249 [(set_attr "op_type" "RRE,RXY")
4250 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4252 (define_insn "*adddi3_zero_cconly"
4253 [(set (reg CC_REGNUM)
4254 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4255 (match_operand:DI 1 "register_operand" "0,0"))
4257 (clobber (match_scratch:DI 0 "=d,d"))]
4258 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4262 [(set_attr "op_type" "RRE,RXY")
4263 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4265 (define_insn "*adddi3_zero"
4266 [(set (match_operand:DI 0 "register_operand" "=d,d")
4267 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4268 (match_operand:DI 1 "register_operand" "0,0")))
4269 (clobber (reg:CC CC_REGNUM))]
4274 [(set_attr "op_type" "RRE,RXY")
4275 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4277 (define_insn_and_split "*adddi3_31z"
4278 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4279 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4280 (match_operand:DI 2 "general_operand" "do") ) )
4281 (clobber (reg:CC CC_REGNUM))]
4282 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4284 "&& reload_completed"
4286 [(set (reg:CCL1 CC_REGNUM)
4287 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4289 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4291 [(set (match_dup 3) (plus:SI
4292 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4293 (match_dup 4)) (match_dup 5)))
4294 (clobber (reg:CC CC_REGNUM))])]
4295 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4296 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4297 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4298 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4299 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4300 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4302 (define_insn_and_split "*adddi3_31"
4303 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4304 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4305 (match_operand:DI 2 "general_operand" "do") ) )
4306 (clobber (reg:CC CC_REGNUM))]
4309 "&& reload_completed"
4311 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4312 (clobber (reg:CC CC_REGNUM))])
4314 [(set (reg:CCL1 CC_REGNUM)
4315 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4317 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4319 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4321 (label_ref (match_dup 9))))
4323 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4324 (clobber (reg:CC CC_REGNUM))])
4326 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4327 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4328 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4329 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4330 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4331 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4332 operands[9] = gen_label_rtx ();")
4335 ; addsi3 instruction pattern(s).
4338 (define_expand "addsi3"
4340 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4341 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4342 (match_operand:SI 2 "general_operand" "")))
4343 (clobber (reg:CC CC_REGNUM))])]
4347 (define_insn "*addsi3_sign"
4348 [(set (match_operand:SI 0 "register_operand" "=d,d")
4349 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4350 (match_operand:SI 1 "register_operand" "0,0")))
4351 (clobber (reg:CC CC_REGNUM))]
4356 [(set_attr "op_type" "RX,RXY")])
4359 ; add(di|si)3 instruction pattern(s).
4362 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4363 (define_insn "*add<mode>3"
4364 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
4365 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4366 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
4367 (clobber (reg:CC CC_REGNUM))]
4377 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
4378 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
4379 (set_attr "z10prop" "z10_super_E1,
4387 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4388 (define_insn "*add<mode>3_carry1_cc"
4389 [(set (reg CC_REGNUM)
4390 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4391 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4393 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
4394 (plus:GPR (match_dup 1) (match_dup 2)))]
4395 "s390_match_ccmode (insn, CCL1mode)"
4403 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4404 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4405 (set_attr "z10prop" "z10_super_E1,
4412 ; alr, al, aly, algr, alg
4413 (define_insn "*add<mode>3_carry1_cconly"
4414 [(set (reg CC_REGNUM)
4415 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4416 (match_operand:GPR 2 "general_operand" "d,R,T"))
4418 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4419 "s390_match_ccmode (insn, CCL1mode)"
4424 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4425 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4427 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4428 (define_insn "*add<mode>3_carry2_cc"
4429 [(set (reg CC_REGNUM)
4430 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4431 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4433 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4434 (plus:GPR (match_dup 1) (match_dup 2)))]
4435 "s390_match_ccmode (insn, CCL1mode)"
4443 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4444 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4445 (set_attr "z10prop" "z10_super_E1,
4452 ; alr, al, aly, algr, alg
4453 (define_insn "*add<mode>3_carry2_cconly"
4454 [(set (reg CC_REGNUM)
4455 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4456 (match_operand:GPR 2 "general_operand" "d,R,T"))
4458 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4459 "s390_match_ccmode (insn, CCL1mode)"
4464 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4465 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4467 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4468 (define_insn "*add<mode>3_cc"
4469 [(set (reg CC_REGNUM)
4470 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4471 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4473 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4474 (plus:GPR (match_dup 1) (match_dup 2)))]
4475 "s390_match_ccmode (insn, CCLmode)"
4483 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4484 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4485 (set_attr "z10prop" "z10_super_E1,
4492 ; alr, al, aly, algr, alg
4493 (define_insn "*add<mode>3_cconly"
4494 [(set (reg CC_REGNUM)
4495 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4496 (match_operand:GPR 2 "general_operand" "d,R,T"))
4498 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4499 "s390_match_ccmode (insn, CCLmode)"
4504 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4505 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4507 ; alr, al, aly, algr, alg
4508 (define_insn "*add<mode>3_cconly2"
4509 [(set (reg CC_REGNUM)
4510 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4511 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
4512 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4513 "s390_match_ccmode(insn, CCLmode)"
4518 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4519 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4521 ; ahi, afi, aghi, agfi, asi, agsi
4522 (define_insn "*add<mode>3_imm_cc"
4523 [(set (reg CC_REGNUM)
4524 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
4525 (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
4527 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
4528 (plus:GPR (match_dup 1) (match_dup 2)))]
4529 "s390_match_ccmode (insn, CCAmode)
4530 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4531 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4532 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4533 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4538 [(set_attr "op_type" "RI,RIL,SIY")
4539 (set_attr "cpu_facility" "*,extimm,z10")
4540 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4543 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4546 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4547 (define_insn "add<mode>3"
4548 [(set (match_operand:FP 0 "register_operand" "=f, f")
4549 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4550 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4551 (clobber (reg:CC CC_REGNUM))]
4554 a<xde><bt>r\t%0,<op1>%2
4556 [(set_attr "op_type" "<RRer>,RXE")
4557 (set_attr "type" "fsimp<mode>")])
4559 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4560 (define_insn "*add<mode>3_cc"
4561 [(set (reg CC_REGNUM)
4562 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4563 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4564 (match_operand:FP 3 "const0_operand" "")))
4565 (set (match_operand:FP 0 "register_operand" "=f,f")
4566 (plus:FP (match_dup 1) (match_dup 2)))]
4567 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4569 a<xde><bt>r\t%0,<op1>%2
4571 [(set_attr "op_type" "<RRer>,RXE")
4572 (set_attr "type" "fsimp<mode>")])
4574 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4575 (define_insn "*add<mode>3_cconly"
4576 [(set (reg CC_REGNUM)
4577 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4578 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4579 (match_operand:FP 3 "const0_operand" "")))
4580 (clobber (match_scratch:FP 0 "=f,f"))]
4581 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4583 a<xde><bt>r\t%0,<op1>%2
4585 [(set_attr "op_type" "<RRer>,RXE")
4586 (set_attr "type" "fsimp<mode>")])
4590 ;;- Subtract instructions.
4594 ; subti3 instruction pattern(s).
4597 (define_insn_and_split "subti3"
4598 [(set (match_operand:TI 0 "register_operand" "=&d")
4599 (minus:TI (match_operand:TI 1 "register_operand" "0")
4600 (match_operand:TI 2 "general_operand" "do") ) )
4601 (clobber (reg:CC CC_REGNUM))]
4604 "&& reload_completed"
4606 [(set (reg:CCL2 CC_REGNUM)
4607 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4609 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4611 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4612 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4613 (clobber (reg:CC CC_REGNUM))])]
4614 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4615 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4616 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4617 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4618 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4619 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4622 ; subdi3 instruction pattern(s).
4625 (define_expand "subdi3"
4627 [(set (match_operand:DI 0 "register_operand" "")
4628 (minus:DI (match_operand:DI 1 "register_operand" "")
4629 (match_operand:DI 2 "general_operand" "")))
4630 (clobber (reg:CC CC_REGNUM))])]
4634 (define_insn "*subdi3_sign"
4635 [(set (match_operand:DI 0 "register_operand" "=d,d")
4636 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4637 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4638 (clobber (reg:CC CC_REGNUM))]
4643 [(set_attr "op_type" "RRE,RXY")
4644 (set_attr "z10prop" "z10_c,*")])
4646 (define_insn "*subdi3_zero_cc"
4647 [(set (reg CC_REGNUM)
4648 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4649 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4651 (set (match_operand:DI 0 "register_operand" "=d,d")
4652 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4653 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4657 [(set_attr "op_type" "RRE,RXY")
4658 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4660 (define_insn "*subdi3_zero_cconly"
4661 [(set (reg CC_REGNUM)
4662 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4663 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4665 (clobber (match_scratch:DI 0 "=d,d"))]
4666 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4670 [(set_attr "op_type" "RRE,RXY")
4671 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4673 (define_insn "*subdi3_zero"
4674 [(set (match_operand:DI 0 "register_operand" "=d,d")
4675 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4676 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4677 (clobber (reg:CC CC_REGNUM))]
4682 [(set_attr "op_type" "RRE,RXY")
4683 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4685 (define_insn_and_split "*subdi3_31z"
4686 [(set (match_operand:DI 0 "register_operand" "=&d")
4687 (minus:DI (match_operand:DI 1 "register_operand" "0")
4688 (match_operand:DI 2 "general_operand" "do") ) )
4689 (clobber (reg:CC CC_REGNUM))]
4690 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4692 "&& reload_completed"
4694 [(set (reg:CCL2 CC_REGNUM)
4695 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4697 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4699 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4700 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4701 (clobber (reg:CC CC_REGNUM))])]
4702 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4703 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4704 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4705 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4706 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4707 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4709 (define_insn_and_split "*subdi3_31"
4710 [(set (match_operand:DI 0 "register_operand" "=&d")
4711 (minus:DI (match_operand:DI 1 "register_operand" "0")
4712 (match_operand:DI 2 "general_operand" "do") ) )
4713 (clobber (reg:CC CC_REGNUM))]
4716 "&& reload_completed"
4718 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4719 (clobber (reg:CC CC_REGNUM))])
4721 [(set (reg:CCL2 CC_REGNUM)
4722 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4724 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4726 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4728 (label_ref (match_dup 9))))
4730 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4731 (clobber (reg:CC CC_REGNUM))])
4733 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4734 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4735 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4736 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4737 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4738 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4739 operands[9] = gen_label_rtx ();")
4742 ; subsi3 instruction pattern(s).
4745 (define_expand "subsi3"
4747 [(set (match_operand:SI 0 "register_operand" "")
4748 (minus:SI (match_operand:SI 1 "register_operand" "")
4749 (match_operand:SI 2 "general_operand" "")))
4750 (clobber (reg:CC CC_REGNUM))])]
4754 (define_insn "*subsi3_sign"
4755 [(set (match_operand:SI 0 "register_operand" "=d,d")
4756 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4757 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4758 (clobber (reg:CC CC_REGNUM))]
4763 [(set_attr "op_type" "RX,RXY")])
4766 ; sub(di|si)3 instruction pattern(s).
4769 ; sr, s, sy, sgr, sg
4770 (define_insn "*sub<mode>3"
4771 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4772 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4773 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4774 (clobber (reg:CC CC_REGNUM))]
4780 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4781 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4783 ; slr, sl, sly, slgr, slg
4784 (define_insn "*sub<mode>3_borrow_cc"
4785 [(set (reg CC_REGNUM)
4786 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4787 (match_operand:GPR 2 "general_operand" "d,R,T"))
4789 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4790 (minus:GPR (match_dup 1) (match_dup 2)))]
4791 "s390_match_ccmode (insn, CCL2mode)"
4796 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4797 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4799 ; slr, sl, sly, slgr, slg
4800 (define_insn "*sub<mode>3_borrow_cconly"
4801 [(set (reg CC_REGNUM)
4802 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4803 (match_operand:GPR 2 "general_operand" "d,R,T"))
4805 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4806 "s390_match_ccmode (insn, CCL2mode)"
4811 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4812 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4814 ; slr, sl, sly, slgr, slg
4815 (define_insn "*sub<mode>3_cc"
4816 [(set (reg CC_REGNUM)
4817 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4818 (match_operand:GPR 2 "general_operand" "d,R,T"))
4820 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4821 (minus:GPR (match_dup 1) (match_dup 2)))]
4822 "s390_match_ccmode (insn, CCLmode)"
4827 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4828 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4830 ; slr, sl, sly, slgr, slg
4831 (define_insn "*sub<mode>3_cc2"
4832 [(set (reg CC_REGNUM)
4833 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4834 (match_operand:GPR 2 "general_operand" "d,R,T")))
4835 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4836 (minus:GPR (match_dup 1) (match_dup 2)))]
4837 "s390_match_ccmode (insn, CCL3mode)"
4842 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4843 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4845 ; slr, sl, sly, slgr, slg
4846 (define_insn "*sub<mode>3_cconly"
4847 [(set (reg CC_REGNUM)
4848 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4849 (match_operand:GPR 2 "general_operand" "d,R,T"))
4851 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4852 "s390_match_ccmode (insn, CCLmode)"
4857 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4858 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4861 ; slr, sl, sly, slgr, slg
4862 (define_insn "*sub<mode>3_cconly2"
4863 [(set (reg CC_REGNUM)
4864 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4865 (match_operand:GPR 2 "general_operand" "d,R,T")))
4866 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4867 "s390_match_ccmode (insn, CCL3mode)"
4872 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4873 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4877 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4880 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4881 (define_insn "sub<mode>3"
4882 [(set (match_operand:FP 0 "register_operand" "=f, f")
4883 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4884 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4885 (clobber (reg:CC CC_REGNUM))]
4888 s<xde><bt>r\t%0,<op1>%2
4890 [(set_attr "op_type" "<RRer>,RXE")
4891 (set_attr "type" "fsimp<mode>")])
4893 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4894 (define_insn "*sub<mode>3_cc"
4895 [(set (reg CC_REGNUM)
4896 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4897 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4898 (match_operand:FP 3 "const0_operand" "")))
4899 (set (match_operand:FP 0 "register_operand" "=f,f")
4900 (minus:FP (match_dup 1) (match_dup 2)))]
4901 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4903 s<xde><bt>r\t%0,<op1>%2
4905 [(set_attr "op_type" "<RRer>,RXE")
4906 (set_attr "type" "fsimp<mode>")])
4908 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4909 (define_insn "*sub<mode>3_cconly"
4910 [(set (reg CC_REGNUM)
4911 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4912 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4913 (match_operand:FP 3 "const0_operand" "")))
4914 (clobber (match_scratch:FP 0 "=f,f"))]
4915 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4917 s<xde><bt>r\t%0,<op1>%2
4919 [(set_attr "op_type" "<RRer>,RXE")
4920 (set_attr "type" "fsimp<mode>")])
4924 ;;- Conditional add/subtract instructions.
4928 ; add(di|si)cc instruction pattern(s).
4931 ; the following 4 patterns are used when the result of an add with
4932 ; carry is checked for an overflow condition
4934 ; op1 + op2 + c < op1
4936 ; alcr, alc, alcgr, alcg
4937 (define_insn "*add<mode>3_alc_carry1_cc"
4938 [(set (reg CC_REGNUM)
4940 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4941 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4942 (match_operand:GPR 2 "general_operand" "d,RT"))
4944 (set (match_operand:GPR 0 "register_operand" "=d,d")
4945 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4946 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4950 [(set_attr "op_type" "RRE,RXY")])
4952 ; alcr, alc, alcgr, alcg
4953 (define_insn "*add<mode>3_alc_carry1_cconly"
4954 [(set (reg CC_REGNUM)
4956 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4957 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4958 (match_operand:GPR 2 "general_operand" "d,RT"))
4960 (clobber (match_scratch:GPR 0 "=d,d"))]
4961 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4965 [(set_attr "op_type" "RRE,RXY")])
4967 ; op1 + op2 + c < op2
4969 ; alcr, alc, alcgr, alcg
4970 (define_insn "*add<mode>3_alc_carry2_cc"
4971 [(set (reg CC_REGNUM)
4973 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4974 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4975 (match_operand:GPR 2 "general_operand" "d,RT"))
4977 (set (match_operand:GPR 0 "register_operand" "=d,d")
4978 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4979 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4983 [(set_attr "op_type" "RRE,RXY")])
4985 ; alcr, alc, alcgr, alcg
4986 (define_insn "*add<mode>3_alc_carry2_cconly"
4987 [(set (reg CC_REGNUM)
4989 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4990 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4991 (match_operand:GPR 2 "general_operand" "d,RT"))
4993 (clobber (match_scratch:GPR 0 "=d,d"))]
4994 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4998 [(set_attr "op_type" "RRE,RXY")])
5000 ; alcr, alc, alcgr, alcg
5001 (define_insn "*add<mode>3_alc_cc"
5002 [(set (reg CC_REGNUM)
5004 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5005 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5006 (match_operand:GPR 2 "general_operand" "d,RT"))
5008 (set (match_operand:GPR 0 "register_operand" "=d,d")
5009 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5010 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5014 [(set_attr "op_type" "RRE,RXY")])
5016 ; alcr, alc, alcgr, alcg
5017 (define_insn "*add<mode>3_alc"
5018 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5019 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5020 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5021 (match_operand:GPR 2 "general_operand" "d,RT")))
5022 (clobber (reg:CC CC_REGNUM))]
5027 [(set_attr "op_type" "RRE,RXY")])
5029 ; slbr, slb, slbgr, slbg
5030 (define_insn "*sub<mode>3_slb_cc"
5031 [(set (reg CC_REGNUM)
5033 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5034 (match_operand:GPR 2 "general_operand" "d,RT"))
5035 (match_operand:GPR 3 "s390_slb_comparison" ""))
5037 (set (match_operand:GPR 0 "register_operand" "=d,d")
5038 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5039 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5043 [(set_attr "op_type" "RRE,RXY")
5044 (set_attr "z10prop" "z10_c,*")])
5046 ; slbr, slb, slbgr, slbg
5047 (define_insn "*sub<mode>3_slb"
5048 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5049 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5050 (match_operand:GPR 2 "general_operand" "d,RT"))
5051 (match_operand:GPR 3 "s390_slb_comparison" "")))
5052 (clobber (reg:CC CC_REGNUM))]
5057 [(set_attr "op_type" "RRE,RXY")
5058 (set_attr "z10prop" "z10_c,*")])
5060 (define_expand "add<mode>cc"
5061 [(match_operand:GPR 0 "register_operand" "")
5062 (match_operand 1 "comparison_operator" "")
5063 (match_operand:GPR 2 "register_operand" "")
5064 (match_operand:GPR 3 "const_int_operand" "")]
5066 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5067 s390_compare_op0, s390_compare_op1,
5068 operands[0], operands[2],
5069 operands[3])) FAIL; DONE;")
5072 ; scond instruction pattern(s).
5075 (define_insn_and_split "*scond<mode>"
5076 [(set (match_operand:GPR 0 "register_operand" "=&d")
5077 (match_operand:GPR 1 "s390_alc_comparison" ""))
5078 (clobber (reg:CC CC_REGNUM))]
5081 "&& reload_completed"
5082 [(set (match_dup 0) (const_int 0))
5084 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5086 (clobber (reg:CC CC_REGNUM))])]
5089 (define_insn_and_split "*scond<mode>_neg"
5090 [(set (match_operand:GPR 0 "register_operand" "=&d")
5091 (match_operand:GPR 1 "s390_slb_comparison" ""))
5092 (clobber (reg:CC CC_REGNUM))]
5095 "&& reload_completed"
5096 [(set (match_dup 0) (const_int 0))
5098 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5100 (clobber (reg:CC CC_REGNUM))])
5102 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5103 (clobber (reg:CC CC_REGNUM))])]
5107 (define_expand "s<code>"
5108 [(set (match_operand:SI 0 "register_operand" "")
5109 (SCOND (match_dup 0)
5112 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
5113 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5115 (define_expand "seq"
5117 [(set (match_operand:SI 0 "register_operand" "=d")
5119 (clobber (reg:CC CC_REGNUM))])
5121 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
5122 (clobber (reg:CC CC_REGNUM))])]
5125 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
5127 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
5128 PUT_MODE (operands[1], SImode);
5131 (define_insn_and_split "*sne"
5132 [(set (match_operand:SI 0 "register_operand" "=d")
5133 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5135 (clobber (reg:CC CC_REGNUM))]
5140 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5141 (clobber (reg:CC CC_REGNUM))])])
5145 ;;- Multiply instructions.
5149 ; muldi3 instruction pattern(s).
5152 (define_insn "*muldi3_sign"
5153 [(set (match_operand:DI 0 "register_operand" "=d,d")
5154 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5155 (match_operand:DI 1 "register_operand" "0,0")))]
5160 [(set_attr "op_type" "RRE,RXY")
5161 (set_attr "type" "imuldi")])
5163 (define_insn "muldi3"
5164 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5165 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5166 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5173 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5174 (set_attr "type" "imuldi")
5175 (set_attr "cpu_facility" "*,*,*,z10")])
5178 ; mulsi3 instruction pattern(s).
5181 (define_insn "*mulsi3_sign"
5182 [(set (match_operand:SI 0 "register_operand" "=d,d")
5183 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5184 (match_operand:SI 1 "register_operand" "0,0")))]
5189 [(set_attr "op_type" "RX,RXY")
5190 (set_attr "type" "imulhi")
5191 (set_attr "cpu_facility" "*,z10")])
5193 (define_insn "mulsi3"
5194 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5195 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5196 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5204 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5205 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5206 (set_attr "cpu_facility" "*,*,*,*,z10")])
5209 ; mulsidi3 instruction pattern(s).
5212 (define_insn "mulsidi3"
5213 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5214 (mult:DI (sign_extend:DI
5215 (match_operand:SI 1 "register_operand" "%0,0,0"))
5217 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5223 [(set_attr "op_type" "RR,RX,RXY")
5224 (set_attr "type" "imulsi")
5225 (set_attr "cpu_facility" "*,*,z10")])
5228 ; umulsidi3 instruction pattern(s).
5231 (define_insn "umulsidi3"
5232 [(set (match_operand:DI 0 "register_operand" "=d,d")
5233 (mult:DI (zero_extend:DI
5234 (match_operand:SI 1 "register_operand" "%0,0"))
5236 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5237 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5241 [(set_attr "op_type" "RRE,RXY")
5242 (set_attr "type" "imulsi")])
5245 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5248 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5249 (define_insn "mul<mode>3"
5250 [(set (match_operand:FP 0 "register_operand" "=f,f")
5251 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5252 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5255 m<xdee><bt>r\t%0,<op1>%2
5257 [(set_attr "op_type" "<RRer>,RXE")
5258 (set_attr "type" "fmul<mode>")])
5260 ; madbr, maebr, maxb, madb, maeb
5261 (define_insn "*fmadd<mode>"
5262 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5263 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
5264 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5265 (match_operand:DSF 3 "register_operand" "0,0")))]
5266 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5270 [(set_attr "op_type" "RRE,RXE")
5271 (set_attr "type" "fmul<mode>")])
5273 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5274 (define_insn "*fmsub<mode>"
5275 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5276 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
5277 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5278 (match_operand:DSF 3 "register_operand" "0,0")))]
5279 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5283 [(set_attr "op_type" "RRE,RXE")
5284 (set_attr "type" "fmul<mode>")])
5287 ;;- Divide and modulo instructions.
5291 ; divmoddi4 instruction pattern(s).
5294 (define_expand "divmoddi4"
5295 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5296 (div:DI (match_operand:DI 1 "register_operand" "")
5297 (match_operand:DI 2 "general_operand" "")))
5298 (set (match_operand:DI 3 "general_operand" "")
5299 (mod:DI (match_dup 1) (match_dup 2)))])
5300 (clobber (match_dup 4))]
5303 rtx insn, div_equal, mod_equal;
5305 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5306 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5308 operands[4] = gen_reg_rtx(TImode);
5309 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5311 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5312 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5314 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5315 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5320 (define_insn "divmodtidi3"
5321 [(set (match_operand:TI 0 "register_operand" "=d,d")
5325 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5326 (match_operand:DI 2 "general_operand" "d,RT")))
5328 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5333 [(set_attr "op_type" "RRE,RXY")
5334 (set_attr "type" "idiv")])
5336 (define_insn "divmodtisi3"
5337 [(set (match_operand:TI 0 "register_operand" "=d,d")
5341 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5343 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5346 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5351 [(set_attr "op_type" "RRE,RXY")
5352 (set_attr "type" "idiv")])
5355 ; udivmoddi4 instruction pattern(s).
5358 (define_expand "udivmoddi4"
5359 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5360 (udiv:DI (match_operand:DI 1 "general_operand" "")
5361 (match_operand:DI 2 "nonimmediate_operand" "")))
5362 (set (match_operand:DI 3 "general_operand" "")
5363 (umod:DI (match_dup 1) (match_dup 2)))])
5364 (clobber (match_dup 4))]
5367 rtx insn, div_equal, mod_equal, equal;
5369 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5370 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5371 equal = gen_rtx_IOR (TImode,
5372 gen_rtx_ASHIFT (TImode,
5373 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5375 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5377 operands[4] = gen_reg_rtx(TImode);
5378 emit_clobber (operands[4]);
5379 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5380 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5382 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5383 set_unique_reg_note (insn, REG_EQUAL, equal);
5385 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5386 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5388 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5389 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5394 (define_insn "udivmodtidi3"
5395 [(set (match_operand:TI 0 "register_operand" "=d,d")
5400 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5402 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5406 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5411 [(set_attr "op_type" "RRE,RXY")
5412 (set_attr "type" "idiv")])
5415 ; divmodsi4 instruction pattern(s).
5418 (define_expand "divmodsi4"
5419 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5420 (div:SI (match_operand:SI 1 "general_operand" "")
5421 (match_operand:SI 2 "nonimmediate_operand" "")))
5422 (set (match_operand:SI 3 "general_operand" "")
5423 (mod:SI (match_dup 1) (match_dup 2)))])
5424 (clobber (match_dup 4))]
5427 rtx insn, div_equal, mod_equal, equal;
5429 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5430 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5431 equal = gen_rtx_IOR (DImode,
5432 gen_rtx_ASHIFT (DImode,
5433 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5435 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5437 operands[4] = gen_reg_rtx(DImode);
5438 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5440 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5441 set_unique_reg_note (insn, REG_EQUAL, equal);
5443 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5444 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5446 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5447 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5452 (define_insn "divmoddisi3"
5453 [(set (match_operand:DI 0 "register_operand" "=d,d")
5458 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5460 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5464 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5469 [(set_attr "op_type" "RR,RX")
5470 (set_attr "type" "idiv")])
5473 ; udivsi3 and umodsi3 instruction pattern(s).
5476 (define_expand "udivmodsi4"
5477 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5478 (udiv:SI (match_operand:SI 1 "general_operand" "")
5479 (match_operand:SI 2 "nonimmediate_operand" "")))
5480 (set (match_operand:SI 3 "general_operand" "")
5481 (umod:SI (match_dup 1) (match_dup 2)))])
5482 (clobber (match_dup 4))]
5483 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5485 rtx insn, div_equal, mod_equal, equal;
5487 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5488 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5489 equal = gen_rtx_IOR (DImode,
5490 gen_rtx_ASHIFT (DImode,
5491 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5493 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5495 operands[4] = gen_reg_rtx(DImode);
5496 emit_clobber (operands[4]);
5497 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5498 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5500 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5501 set_unique_reg_note (insn, REG_EQUAL, equal);
5503 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5504 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5506 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5507 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5512 (define_insn "udivmoddisi3"
5513 [(set (match_operand:DI 0 "register_operand" "=d,d")
5518 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5520 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5524 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5525 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5529 [(set_attr "op_type" "RRE,RXY")
5530 (set_attr "type" "idiv")])
5532 (define_expand "udivsi3"
5533 [(set (match_operand:SI 0 "register_operand" "=d")
5534 (udiv:SI (match_operand:SI 1 "general_operand" "")
5535 (match_operand:SI 2 "general_operand" "")))
5536 (clobber (match_dup 3))]
5537 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5539 rtx insn, udiv_equal, umod_equal, equal;
5541 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5542 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5543 equal = gen_rtx_IOR (DImode,
5544 gen_rtx_ASHIFT (DImode,
5545 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5547 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5549 operands[3] = gen_reg_rtx (DImode);
5551 if (CONSTANT_P (operands[2]))
5553 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5555 rtx label1 = gen_label_rtx ();
5557 operands[1] = make_safe_from (operands[1], operands[0]);
5558 emit_move_insn (operands[0], const0_rtx);
5559 emit_insn (gen_cmpsi (operands[1], operands[2]));
5560 emit_jump_insn (gen_bltu (label1));
5561 emit_move_insn (operands[0], const1_rtx);
5562 emit_label (label1);
5566 operands[2] = force_reg (SImode, operands[2]);
5567 operands[2] = make_safe_from (operands[2], operands[0]);
5569 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5570 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5572 set_unique_reg_note (insn, REG_EQUAL, equal);
5574 insn = emit_move_insn (operands[0],
5575 gen_lowpart (SImode, operands[3]));
5576 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5581 rtx label1 = gen_label_rtx ();
5582 rtx label2 = gen_label_rtx ();
5583 rtx label3 = gen_label_rtx ();
5585 operands[1] = force_reg (SImode, operands[1]);
5586 operands[1] = make_safe_from (operands[1], operands[0]);
5587 operands[2] = force_reg (SImode, operands[2]);
5588 operands[2] = make_safe_from (operands[2], operands[0]);
5590 emit_move_insn (operands[0], const0_rtx);
5591 emit_insn (gen_cmpsi (operands[2], operands[1]));
5592 emit_jump_insn (gen_bgtu (label3));
5593 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5594 emit_jump_insn (gen_blt (label2));
5595 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5596 emit_jump_insn (gen_beq (label1));
5597 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5598 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5600 set_unique_reg_note (insn, REG_EQUAL, equal);
5602 insn = emit_move_insn (operands[0],
5603 gen_lowpart (SImode, operands[3]));
5604 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5607 emit_label (label1);
5608 emit_move_insn (operands[0], operands[1]);
5610 emit_label (label2);
5611 emit_move_insn (operands[0], const1_rtx);
5612 emit_label (label3);
5614 emit_move_insn (operands[0], operands[0]);
5618 (define_expand "umodsi3"
5619 [(set (match_operand:SI 0 "register_operand" "=d")
5620 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5621 (match_operand:SI 2 "nonimmediate_operand" "")))
5622 (clobber (match_dup 3))]
5623 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5625 rtx insn, udiv_equal, umod_equal, equal;
5627 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5628 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5629 equal = gen_rtx_IOR (DImode,
5630 gen_rtx_ASHIFT (DImode,
5631 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5633 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5635 operands[3] = gen_reg_rtx (DImode);
5637 if (CONSTANT_P (operands[2]))
5639 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5641 rtx label1 = gen_label_rtx ();
5643 operands[1] = make_safe_from (operands[1], operands[0]);
5644 emit_move_insn (operands[0], operands[1]);
5645 emit_insn (gen_cmpsi (operands[0], operands[2]));
5646 emit_jump_insn (gen_bltu (label1));
5647 emit_insn (gen_abssi2 (operands[0], operands[2]));
5648 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5649 emit_label (label1);
5653 operands[2] = force_reg (SImode, operands[2]);
5654 operands[2] = make_safe_from (operands[2], operands[0]);
5656 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5657 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5659 set_unique_reg_note (insn, REG_EQUAL, equal);
5661 insn = emit_move_insn (operands[0],
5662 gen_highpart (SImode, operands[3]));
5663 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5668 rtx label1 = gen_label_rtx ();
5669 rtx label2 = gen_label_rtx ();
5670 rtx label3 = gen_label_rtx ();
5672 operands[1] = force_reg (SImode, operands[1]);
5673 operands[1] = make_safe_from (operands[1], operands[0]);
5674 operands[2] = force_reg (SImode, operands[2]);
5675 operands[2] = make_safe_from (operands[2], operands[0]);
5677 emit_move_insn(operands[0], operands[1]);
5678 emit_insn (gen_cmpsi (operands[2], operands[1]));
5679 emit_jump_insn (gen_bgtu (label3));
5680 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5681 emit_jump_insn (gen_blt (label2));
5682 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5683 emit_jump_insn (gen_beq (label1));
5684 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5685 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5687 set_unique_reg_note (insn, REG_EQUAL, equal);
5689 insn = emit_move_insn (operands[0],
5690 gen_highpart (SImode, operands[3]));
5691 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5694 emit_label (label1);
5695 emit_move_insn (operands[0], const0_rtx);
5697 emit_label (label2);
5698 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5699 emit_label (label3);
5705 ; div(df|sf)3 instruction pattern(s).
5708 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5709 (define_insn "div<mode>3"
5710 [(set (match_operand:FP 0 "register_operand" "=f,f")
5711 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5712 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5715 d<xde><bt>r\t%0,<op1>%2
5717 [(set_attr "op_type" "<RRer>,RXE")
5718 (set_attr "type" "fdiv<mode>")])
5722 ;;- And instructions.
5725 (define_expand "and<mode>3"
5726 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5727 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5728 (match_operand:INT 2 "general_operand" "")))
5729 (clobber (reg:CC CC_REGNUM))]
5731 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5734 ; anddi3 instruction pattern(s).
5737 (define_insn "*anddi3_cc"
5738 [(set (reg CC_REGNUM)
5739 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5740 (match_operand:DI 2 "general_operand" "d,RT"))
5742 (set (match_operand:DI 0 "register_operand" "=d,d")
5743 (and:DI (match_dup 1) (match_dup 2)))]
5744 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5748 [(set_attr "op_type" "RRE,RXY")
5749 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5751 (define_insn "*anddi3_cconly"
5752 [(set (reg CC_REGNUM)
5753 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5754 (match_operand:DI 2 "general_operand" "d,RT"))
5756 (clobber (match_scratch:DI 0 "=d,d"))]
5757 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5758 /* Do not steal TM patterns. */
5759 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5763 [(set_attr "op_type" "RRE,RXY")
5764 (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
5766 (define_insn "*anddi3"
5767 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5768 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5769 "%d,o,0,0,0,0,0,0,0,0,0,0")
5770 (match_operand:DI 2 "general_operand"
5771 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5772 (clobber (reg:CC CC_REGNUM))]
5773 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5787 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
5788 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
5789 (set_attr "z10prop" "*,
5803 [(set (match_operand:DI 0 "s_operand" "")
5804 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5805 (clobber (reg:CC CC_REGNUM))]
5808 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5809 (clobber (reg:CC CC_REGNUM))])]
5810 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5814 ; andsi3 instruction pattern(s).
5817 (define_insn "*andsi3_cc"
5818 [(set (reg CC_REGNUM)
5819 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5820 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5822 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5823 (and:SI (match_dup 1) (match_dup 2)))]
5824 "s390_match_ccmode(insn, CCTmode)"
5830 [(set_attr "op_type" "RIL,RR,RX,RXY")
5831 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5833 (define_insn "*andsi3_cconly"
5834 [(set (reg CC_REGNUM)
5835 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5836 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5838 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5839 "s390_match_ccmode(insn, CCTmode)
5840 /* Do not steal TM patterns. */
5841 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5847 [(set_attr "op_type" "RIL,RR,RX,RXY")
5848 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5850 (define_insn "*andsi3_zarch"
5851 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5852 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5853 "%d,o,0,0,0,0,0,0,0,0")
5854 (match_operand:SI 2 "general_operand"
5855 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5856 (clobber (reg:CC CC_REGNUM))]
5857 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5869 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
5870 (set_attr "z10prop" "*,
5881 (define_insn "*andsi3_esa"
5882 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5883 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5884 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5885 (clobber (reg:CC CC_REGNUM))]
5886 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5892 [(set_attr "op_type" "RR,RX,SI,SS")
5893 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
5897 [(set (match_operand:SI 0 "s_operand" "")
5898 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5899 (clobber (reg:CC CC_REGNUM))]
5902 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5903 (clobber (reg:CC CC_REGNUM))])]
5904 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5907 ; andhi3 instruction pattern(s).
5910 (define_insn "*andhi3_zarch"
5911 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5912 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5913 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5914 (clobber (reg:CC CC_REGNUM))]
5915 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5921 [(set_attr "op_type" "RR,RI,SI,SS")
5922 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
5925 (define_insn "*andhi3_esa"
5926 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5927 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5928 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5929 (clobber (reg:CC CC_REGNUM))]
5930 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5935 [(set_attr "op_type" "RR,SI,SS")
5936 (set_attr "z10prop" "z10_super_E1,*,*")
5940 [(set (match_operand:HI 0 "s_operand" "")
5941 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5942 (clobber (reg:CC CC_REGNUM))]
5945 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5946 (clobber (reg:CC CC_REGNUM))])]
5947 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5950 ; andqi3 instruction pattern(s).
5953 (define_insn "*andqi3_zarch"
5954 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5955 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5956 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5957 (clobber (reg:CC CC_REGNUM))]
5958 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5965 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
5966 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
5968 (define_insn "*andqi3_esa"
5969 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5970 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5971 (match_operand:QI 2 "general_operand" "d,n,Q")))
5972 (clobber (reg:CC CC_REGNUM))]
5973 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5978 [(set_attr "op_type" "RR,SI,SS")
5979 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
5982 ; Block and (NC) patterns.
5986 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5987 (and:BLK (match_dup 0)
5988 (match_operand:BLK 1 "memory_operand" "Q")))
5989 (use (match_operand 2 "const_int_operand" "n"))
5990 (clobber (reg:CC CC_REGNUM))]
5991 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5992 "nc\t%O0(%2,%R0),%S1"
5993 [(set_attr "op_type" "SS")])
5996 [(set (match_operand 0 "memory_operand" "")
5998 (match_operand 1 "memory_operand" "")))
5999 (clobber (reg:CC CC_REGNUM))]
6001 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6002 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6004 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6006 (clobber (reg:CC CC_REGNUM))])]
6008 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6009 operands[0] = adjust_address (operands[0], BLKmode, 0);
6010 operands[1] = adjust_address (operands[1], BLKmode, 0);
6015 [(set (match_operand:BLK 0 "memory_operand" "")
6016 (and:BLK (match_dup 0)
6017 (match_operand:BLK 1 "memory_operand" "")))
6018 (use (match_operand 2 "const_int_operand" ""))
6019 (clobber (reg:CC CC_REGNUM))])
6021 [(set (match_operand:BLK 3 "memory_operand" "")
6022 (and:BLK (match_dup 3)
6023 (match_operand:BLK 4 "memory_operand" "")))
6024 (use (match_operand 5 "const_int_operand" ""))
6025 (clobber (reg:CC CC_REGNUM))])]
6026 "s390_offset_p (operands[0], operands[3], operands[2])
6027 && s390_offset_p (operands[1], operands[4], operands[2])
6028 && !s390_overlap_p (operands[0], operands[1],
6029 INTVAL (operands[2]) + INTVAL (operands[5]))
6030 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6032 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6034 (clobber (reg:CC CC_REGNUM))])]
6035 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6036 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6037 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6041 ;;- Bit set (inclusive or) instructions.
6044 (define_expand "ior<mode>3"
6045 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6046 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6047 (match_operand:INT 2 "general_operand" "")))
6048 (clobber (reg:CC CC_REGNUM))]
6050 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6053 ; iordi3 instruction pattern(s).
6056 (define_insn "*iordi3_cc"
6057 [(set (reg CC_REGNUM)
6058 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6059 (match_operand:DI 2 "general_operand" "d,RT"))
6061 (set (match_operand:DI 0 "register_operand" "=d,d")
6062 (ior:DI (match_dup 1) (match_dup 2)))]
6063 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6067 [(set_attr "op_type" "RRE,RXY")
6068 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6070 (define_insn "*iordi3_cconly"
6071 [(set (reg CC_REGNUM)
6072 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6073 (match_operand:DI 2 "general_operand" "d,RT"))
6075 (clobber (match_scratch:DI 0 "=d,d"))]
6076 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6080 [(set_attr "op_type" "RRE,RXY")
6081 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6083 (define_insn "*iordi3"
6084 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6085 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6086 (match_operand:DI 2 "general_operand"
6087 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6088 (clobber (reg:CC CC_REGNUM))]
6089 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6101 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
6102 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
6103 (set_attr "z10prop" "z10_super_E1,
6115 [(set (match_operand:DI 0 "s_operand" "")
6116 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6117 (clobber (reg:CC CC_REGNUM))]
6120 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6121 (clobber (reg:CC CC_REGNUM))])]
6122 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6125 ; iorsi3 instruction pattern(s).
6128 (define_insn "*iorsi3_cc"
6129 [(set (reg CC_REGNUM)
6130 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6131 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6133 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6134 (ior:SI (match_dup 1) (match_dup 2)))]
6135 "s390_match_ccmode(insn, CCTmode)"
6141 [(set_attr "op_type" "RIL,RR,RX,RXY")
6142 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6144 (define_insn "*iorsi3_cconly"
6145 [(set (reg CC_REGNUM)
6146 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6147 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6149 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6150 "s390_match_ccmode(insn, CCTmode)"
6156 [(set_attr "op_type" "RIL,RR,RX,RXY")
6157 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6159 (define_insn "*iorsi3_zarch"
6160 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
6161 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
6162 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
6163 (clobber (reg:CC CC_REGNUM))]
6164 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6174 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
6175 (set_attr "z10prop" "z10_super_E1,
6184 (define_insn "*iorsi3_esa"
6185 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6186 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6187 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6188 (clobber (reg:CC CC_REGNUM))]
6189 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6195 [(set_attr "op_type" "RR,RX,SI,SS")
6196 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6199 [(set (match_operand:SI 0 "s_operand" "")
6200 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6201 (clobber (reg:CC CC_REGNUM))]
6204 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6205 (clobber (reg:CC CC_REGNUM))])]
6206 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6209 ; iorhi3 instruction pattern(s).
6212 (define_insn "*iorhi3_zarch"
6213 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6214 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6215 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
6216 (clobber (reg:CC CC_REGNUM))]
6217 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6223 [(set_attr "op_type" "RR,RI,SI,SS")
6224 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6226 (define_insn "*iorhi3_esa"
6227 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6228 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6229 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6230 (clobber (reg:CC CC_REGNUM))]
6231 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6236 [(set_attr "op_type" "RR,SI,SS")
6237 (set_attr "z10prop" "z10_super_E1,*,*")])
6240 [(set (match_operand:HI 0 "s_operand" "")
6241 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6242 (clobber (reg:CC CC_REGNUM))]
6245 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6246 (clobber (reg:CC CC_REGNUM))])]
6247 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6250 ; iorqi3 instruction pattern(s).
6253 (define_insn "*iorqi3_zarch"
6254 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6255 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6256 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6257 (clobber (reg:CC CC_REGNUM))]
6258 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6265 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6266 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6268 (define_insn "*iorqi3_esa"
6269 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6270 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6271 (match_operand:QI 2 "general_operand" "d,n,Q")))
6272 (clobber (reg:CC CC_REGNUM))]
6273 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6278 [(set_attr "op_type" "RR,SI,SS")
6279 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6282 ; Block inclusive or (OC) patterns.
6286 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6287 (ior:BLK (match_dup 0)
6288 (match_operand:BLK 1 "memory_operand" "Q")))
6289 (use (match_operand 2 "const_int_operand" "n"))
6290 (clobber (reg:CC CC_REGNUM))]
6291 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6292 "oc\t%O0(%2,%R0),%S1"
6293 [(set_attr "op_type" "SS")])
6296 [(set (match_operand 0 "memory_operand" "")
6298 (match_operand 1 "memory_operand" "")))
6299 (clobber (reg:CC CC_REGNUM))]
6301 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6302 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6304 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6306 (clobber (reg:CC CC_REGNUM))])]
6308 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6309 operands[0] = adjust_address (operands[0], BLKmode, 0);
6310 operands[1] = adjust_address (operands[1], BLKmode, 0);
6315 [(set (match_operand:BLK 0 "memory_operand" "")
6316 (ior:BLK (match_dup 0)
6317 (match_operand:BLK 1 "memory_operand" "")))
6318 (use (match_operand 2 "const_int_operand" ""))
6319 (clobber (reg:CC CC_REGNUM))])
6321 [(set (match_operand:BLK 3 "memory_operand" "")
6322 (ior:BLK (match_dup 3)
6323 (match_operand:BLK 4 "memory_operand" "")))
6324 (use (match_operand 5 "const_int_operand" ""))
6325 (clobber (reg:CC CC_REGNUM))])]
6326 "s390_offset_p (operands[0], operands[3], operands[2])
6327 && s390_offset_p (operands[1], operands[4], operands[2])
6328 && !s390_overlap_p (operands[0], operands[1],
6329 INTVAL (operands[2]) + INTVAL (operands[5]))
6330 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6332 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6334 (clobber (reg:CC CC_REGNUM))])]
6335 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6336 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6337 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6341 ;;- Xor instructions.
6344 (define_expand "xor<mode>3"
6345 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6346 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6347 (match_operand:INT 2 "general_operand" "")))
6348 (clobber (reg:CC CC_REGNUM))]
6350 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6353 ; xordi3 instruction pattern(s).
6356 (define_insn "*xordi3_cc"
6357 [(set (reg CC_REGNUM)
6358 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6359 (match_operand:DI 2 "general_operand" "d,RT"))
6361 (set (match_operand:DI 0 "register_operand" "=d,d")
6362 (xor:DI (match_dup 1) (match_dup 2)))]
6363 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6367 [(set_attr "op_type" "RRE,RXY")
6368 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6370 (define_insn "*xordi3_cconly"
6371 [(set (reg CC_REGNUM)
6372 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6373 (match_operand:DI 2 "general_operand" "d,RT"))
6375 (clobber (match_scratch:DI 0 "=d,d"))]
6376 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6380 [(set_attr "op_type" "RRE,RXY")
6381 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6383 (define_insn "*xordi3"
6384 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6385 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6386 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6387 (clobber (reg:CC CC_REGNUM))]
6388 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6396 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
6397 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
6398 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6401 [(set (match_operand:DI 0 "s_operand" "")
6402 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6403 (clobber (reg:CC CC_REGNUM))]
6406 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6407 (clobber (reg:CC CC_REGNUM))])]
6408 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6411 ; xorsi3 instruction pattern(s).
6414 (define_insn "*xorsi3_cc"
6415 [(set (reg CC_REGNUM)
6416 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6417 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6419 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6420 (xor:SI (match_dup 1) (match_dup 2)))]
6421 "s390_match_ccmode(insn, CCTmode)"
6427 [(set_attr "op_type" "RIL,RR,RX,RXY")
6428 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6430 (define_insn "*xorsi3_cconly"
6431 [(set (reg CC_REGNUM)
6432 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6433 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6435 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6436 "s390_match_ccmode(insn, CCTmode)"
6442 [(set_attr "op_type" "RIL,RR,RX,RXY")
6443 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6445 (define_insn "*xorsi3"
6446 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6447 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6448 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
6449 (clobber (reg:CC CC_REGNUM))]
6450 "s390_logical_operator_ok_p (operands)"
6458 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
6459 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6462 [(set (match_operand:SI 0 "s_operand" "")
6463 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6464 (clobber (reg:CC CC_REGNUM))]
6467 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6468 (clobber (reg:CC CC_REGNUM))])]
6469 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6472 ; xorhi3 instruction pattern(s).
6475 (define_insn "*xorhi3"
6476 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6477 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6478 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6479 (clobber (reg:CC CC_REGNUM))]
6480 "s390_logical_operator_ok_p (operands)"
6486 [(set_attr "op_type" "RIL,RR,SI,SS")
6487 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6490 [(set (match_operand:HI 0 "s_operand" "")
6491 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6492 (clobber (reg:CC CC_REGNUM))]
6495 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6496 (clobber (reg:CC CC_REGNUM))])]
6497 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6500 ; xorqi3 instruction pattern(s).
6503 (define_insn "*xorqi3"
6504 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6505 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6506 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6507 (clobber (reg:CC CC_REGNUM))]
6508 "s390_logical_operator_ok_p (operands)"
6515 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
6516 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6520 ; Block exclusive or (XC) patterns.
6524 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6525 (xor:BLK (match_dup 0)
6526 (match_operand:BLK 1 "memory_operand" "Q")))
6527 (use (match_operand 2 "const_int_operand" "n"))
6528 (clobber (reg:CC CC_REGNUM))]
6529 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6530 "xc\t%O0(%2,%R0),%S1"
6531 [(set_attr "op_type" "SS")])
6534 [(set (match_operand 0 "memory_operand" "")
6536 (match_operand 1 "memory_operand" "")))
6537 (clobber (reg:CC CC_REGNUM))]
6539 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6540 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6542 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6544 (clobber (reg:CC CC_REGNUM))])]
6546 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6547 operands[0] = adjust_address (operands[0], BLKmode, 0);
6548 operands[1] = adjust_address (operands[1], BLKmode, 0);
6553 [(set (match_operand:BLK 0 "memory_operand" "")
6554 (xor:BLK (match_dup 0)
6555 (match_operand:BLK 1 "memory_operand" "")))
6556 (use (match_operand 2 "const_int_operand" ""))
6557 (clobber (reg:CC CC_REGNUM))])
6559 [(set (match_operand:BLK 3 "memory_operand" "")
6560 (xor:BLK (match_dup 3)
6561 (match_operand:BLK 4 "memory_operand" "")))
6562 (use (match_operand 5 "const_int_operand" ""))
6563 (clobber (reg:CC CC_REGNUM))])]
6564 "s390_offset_p (operands[0], operands[3], operands[2])
6565 && s390_offset_p (operands[1], operands[4], operands[2])
6566 && !s390_overlap_p (operands[0], operands[1],
6567 INTVAL (operands[2]) + INTVAL (operands[5]))
6568 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6570 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6572 (clobber (reg:CC CC_REGNUM))])]
6573 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6574 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6575 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6578 ; Block xor (XC) patterns with src == dest.
6581 (define_insn "*xc_zero"
6582 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6584 (use (match_operand 1 "const_int_operand" "n"))
6585 (clobber (reg:CC CC_REGNUM))]
6586 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6587 "xc\t%O0(%1,%R0),%S0"
6588 [(set_attr "op_type" "SS")])
6592 [(set (match_operand:BLK 0 "memory_operand" "")
6594 (use (match_operand 1 "const_int_operand" ""))
6595 (clobber (reg:CC CC_REGNUM))])
6597 [(set (match_operand:BLK 2 "memory_operand" "")
6599 (use (match_operand 3 "const_int_operand" ""))
6600 (clobber (reg:CC CC_REGNUM))])]
6601 "s390_offset_p (operands[0], operands[2], operands[1])
6602 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6604 [(set (match_dup 4) (const_int 0))
6606 (clobber (reg:CC CC_REGNUM))])]
6607 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6608 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6612 ;;- Negate instructions.
6616 ; neg(di|si)2 instruction pattern(s).
6619 (define_expand "neg<mode>2"
6621 [(set (match_operand:DSI 0 "register_operand" "=d")
6622 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6623 (clobber (reg:CC CC_REGNUM))])]
6627 (define_insn "*negdi2_sign_cc"
6628 [(set (reg CC_REGNUM)
6629 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6630 (match_operand:SI 1 "register_operand" "d") 0)
6631 (const_int 32)) (const_int 32)))
6633 (set (match_operand:DI 0 "register_operand" "=d")
6634 (neg:DI (sign_extend:DI (match_dup 1))))]
6635 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6637 [(set_attr "op_type" "RRE")
6638 (set_attr "z10prop" "z10_c")])
6640 (define_insn "*negdi2_sign"
6641 [(set (match_operand:DI 0 "register_operand" "=d")
6642 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6643 (clobber (reg:CC CC_REGNUM))]
6646 [(set_attr "op_type" "RRE")
6647 (set_attr "z10prop" "z10_c")])
6650 (define_insn "*neg<mode>2_cc"
6651 [(set (reg CC_REGNUM)
6652 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6654 (set (match_operand:GPR 0 "register_operand" "=d")
6655 (neg:GPR (match_dup 1)))]
6656 "s390_match_ccmode (insn, CCAmode)"
6658 [(set_attr "op_type" "RR<E>")
6659 (set_attr "z10prop" "z10_super_c_E1")])
6662 (define_insn "*neg<mode>2_cconly"
6663 [(set (reg CC_REGNUM)
6664 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6666 (clobber (match_scratch:GPR 0 "=d"))]
6667 "s390_match_ccmode (insn, CCAmode)"
6669 [(set_attr "op_type" "RR<E>")
6670 (set_attr "z10prop" "z10_super_c_E1")])
6673 (define_insn "*neg<mode>2"
6674 [(set (match_operand:GPR 0 "register_operand" "=d")
6675 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6676 (clobber (reg:CC CC_REGNUM))]
6679 [(set_attr "op_type" "RR<E>")
6680 (set_attr "z10prop" "z10_super_c_E1")])
6682 (define_insn_and_split "*negdi2_31"
6683 [(set (match_operand:DI 0 "register_operand" "=d")
6684 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6685 (clobber (reg:CC CC_REGNUM))]
6688 "&& reload_completed"
6690 [(set (match_dup 2) (neg:SI (match_dup 3)))
6691 (clobber (reg:CC CC_REGNUM))])
6693 [(set (reg:CCAP CC_REGNUM)
6694 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6695 (set (match_dup 4) (neg:SI (match_dup 5)))])
6697 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6699 (label_ref (match_dup 6))))
6701 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6702 (clobber (reg:CC CC_REGNUM))])
6704 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6705 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6706 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6707 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6708 operands[6] = gen_label_rtx ();")
6711 ; neg(df|sf)2 instruction pattern(s).
6714 (define_expand "neg<mode>2"
6716 [(set (match_operand:BFP 0 "register_operand" "=f")
6717 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6718 (clobber (reg:CC CC_REGNUM))])]
6722 ; lcxbr, lcdbr, lcebr
6723 (define_insn "*neg<mode>2_cc"
6724 [(set (reg CC_REGNUM)
6725 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6726 (match_operand:BFP 2 "const0_operand" "")))
6727 (set (match_operand:BFP 0 "register_operand" "=f")
6728 (neg:BFP (match_dup 1)))]
6729 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6731 [(set_attr "op_type" "RRE")
6732 (set_attr "type" "fsimp<mode>")])
6734 ; lcxbr, lcdbr, lcebr
6735 (define_insn "*neg<mode>2_cconly"
6736 [(set (reg CC_REGNUM)
6737 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6738 (match_operand:BFP 2 "const0_operand" "")))
6739 (clobber (match_scratch:BFP 0 "=f"))]
6740 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6742 [(set_attr "op_type" "RRE")
6743 (set_attr "type" "fsimp<mode>")])
6746 (define_insn "*neg<mode>2_nocc"
6747 [(set (match_operand:FP 0 "register_operand" "=f")
6748 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6751 [(set_attr "op_type" "RRE")
6752 (set_attr "type" "fsimp<mode>")])
6754 ; lcxbr, lcdbr, lcebr
6755 (define_insn "*neg<mode>2"
6756 [(set (match_operand:BFP 0 "register_operand" "=f")
6757 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6758 (clobber (reg:CC CC_REGNUM))]
6761 [(set_attr "op_type" "RRE")
6762 (set_attr "type" "fsimp<mode>")])
6766 ;;- Absolute value instructions.
6770 ; abs(di|si)2 instruction pattern(s).
6773 (define_insn "*absdi2_sign_cc"
6774 [(set (reg CC_REGNUM)
6775 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6776 (match_operand:SI 1 "register_operand" "d") 0)
6777 (const_int 32)) (const_int 32)))
6779 (set (match_operand:DI 0 "register_operand" "=d")
6780 (abs:DI (sign_extend:DI (match_dup 1))))]
6781 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6783 [(set_attr "op_type" "RRE")
6784 (set_attr "z10prop" "z10_c")])
6786 (define_insn "*absdi2_sign"
6787 [(set (match_operand:DI 0 "register_operand" "=d")
6788 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6789 (clobber (reg:CC CC_REGNUM))]
6792 [(set_attr "op_type" "RRE")
6793 (set_attr "z10prop" "z10_c")])
6796 (define_insn "*abs<mode>2_cc"
6797 [(set (reg CC_REGNUM)
6798 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6800 (set (match_operand:GPR 0 "register_operand" "=d")
6801 (abs:GPR (match_dup 1)))]
6802 "s390_match_ccmode (insn, CCAmode)"
6804 [(set_attr "op_type" "RR<E>")
6805 (set_attr "z10prop" "z10_c")])
6808 (define_insn "*abs<mode>2_cconly"
6809 [(set (reg CC_REGNUM)
6810 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6812 (clobber (match_scratch:GPR 0 "=d"))]
6813 "s390_match_ccmode (insn, CCAmode)"
6815 [(set_attr "op_type" "RR<E>")
6816 (set_attr "z10prop" "z10_c")])
6819 (define_insn "abs<mode>2"
6820 [(set (match_operand:GPR 0 "register_operand" "=d")
6821 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6822 (clobber (reg:CC CC_REGNUM))]
6825 [(set_attr "op_type" "RR<E>")
6826 (set_attr "z10prop" "z10_c")])
6829 ; abs(df|sf)2 instruction pattern(s).
6832 (define_expand "abs<mode>2"
6834 [(set (match_operand:BFP 0 "register_operand" "=f")
6835 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6836 (clobber (reg:CC CC_REGNUM))])]
6840 ; lpxbr, lpdbr, lpebr
6841 (define_insn "*abs<mode>2_cc"
6842 [(set (reg CC_REGNUM)
6843 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6844 (match_operand:BFP 2 "const0_operand" "")))
6845 (set (match_operand:BFP 0 "register_operand" "=f")
6846 (abs:BFP (match_dup 1)))]
6847 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6849 [(set_attr "op_type" "RRE")
6850 (set_attr "type" "fsimp<mode>")])
6852 ; lpxbr, lpdbr, lpebr
6853 (define_insn "*abs<mode>2_cconly"
6854 [(set (reg CC_REGNUM)
6855 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6856 (match_operand:BFP 2 "const0_operand" "")))
6857 (clobber (match_scratch:BFP 0 "=f"))]
6858 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6860 [(set_attr "op_type" "RRE")
6861 (set_attr "type" "fsimp<mode>")])
6864 (define_insn "*abs<mode>2_nocc"
6865 [(set (match_operand:FP 0 "register_operand" "=f")
6866 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6869 [(set_attr "op_type" "RRE")
6870 (set_attr "type" "fsimp<mode>")])
6872 ; lpxbr, lpdbr, lpebr
6873 (define_insn "*abs<mode>2"
6874 [(set (match_operand:BFP 0 "register_operand" "=f")
6875 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6876 (clobber (reg:CC CC_REGNUM))]
6879 [(set_attr "op_type" "RRE")
6880 (set_attr "type" "fsimp<mode>")])
6884 ;;- Negated absolute value instructions
6891 (define_insn "*negabsdi2_sign_cc"
6892 [(set (reg CC_REGNUM)
6893 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6894 (match_operand:SI 1 "register_operand" "d") 0)
6895 (const_int 32)) (const_int 32))))
6897 (set (match_operand:DI 0 "register_operand" "=d")
6898 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6899 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6901 [(set_attr "op_type" "RRE")
6902 (set_attr "z10prop" "z10_c")])
6904 (define_insn "*negabsdi2_sign"
6905 [(set (match_operand:DI 0 "register_operand" "=d")
6906 (neg:DI (abs:DI (sign_extend:DI
6907 (match_operand:SI 1 "register_operand" "d")))))
6908 (clobber (reg:CC CC_REGNUM))]
6911 [(set_attr "op_type" "RRE")
6912 (set_attr "z10prop" "z10_c")])
6915 (define_insn "*negabs<mode>2_cc"
6916 [(set (reg CC_REGNUM)
6917 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6919 (set (match_operand:GPR 0 "register_operand" "=d")
6920 (neg:GPR (abs:GPR (match_dup 1))))]
6921 "s390_match_ccmode (insn, CCAmode)"
6923 [(set_attr "op_type" "RR<E>")
6924 (set_attr "z10prop" "z10_c")])
6927 (define_insn "*negabs<mode>2_cconly"
6928 [(set (reg CC_REGNUM)
6929 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6931 (clobber (match_scratch:GPR 0 "=d"))]
6932 "s390_match_ccmode (insn, CCAmode)"
6934 [(set_attr "op_type" "RR<E>")
6935 (set_attr "z10prop" "z10_c")])
6938 (define_insn "*negabs<mode>2"
6939 [(set (match_operand:GPR 0 "register_operand" "=d")
6940 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6941 (clobber (reg:CC CC_REGNUM))]
6944 [(set_attr "op_type" "RR<E>")
6945 (set_attr "z10prop" "z10_c")])
6951 ; lnxbr, lndbr, lnebr
6952 (define_insn "*negabs<mode>2_cc"
6953 [(set (reg CC_REGNUM)
6954 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6955 (match_operand:BFP 2 "const0_operand" "")))
6956 (set (match_operand:BFP 0 "register_operand" "=f")
6957 (neg:BFP (abs:BFP (match_dup 1))))]
6958 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6960 [(set_attr "op_type" "RRE")
6961 (set_attr "type" "fsimp<mode>")])
6963 ; lnxbr, lndbr, lnebr
6964 (define_insn "*negabs<mode>2_cconly"
6965 [(set (reg CC_REGNUM)
6966 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6967 (match_operand:BFP 2 "const0_operand" "")))
6968 (clobber (match_scratch:BFP 0 "=f"))]
6969 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6971 [(set_attr "op_type" "RRE")
6972 (set_attr "type" "fsimp<mode>")])
6975 (define_insn "*negabs<mode>2_nocc"
6976 [(set (match_operand:FP 0 "register_operand" "=f")
6977 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
6980 [(set_attr "op_type" "RRE")
6981 (set_attr "type" "fsimp<mode>")])
6983 ; lnxbr, lndbr, lnebr
6984 (define_insn "*negabs<mode>2"
6985 [(set (match_operand:BFP 0 "register_operand" "=f")
6986 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
6987 (clobber (reg:CC CC_REGNUM))]
6990 [(set_attr "op_type" "RRE")
6991 (set_attr "type" "fsimp<mode>")])
6994 ;;- Copy sign instructions
6998 (define_insn "copysign<mode>3"
6999 [(set (match_operand:FP 0 "register_operand" "=f")
7000 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
7001 (match_operand:FP 2 "register_operand" "f")]
7005 [(set_attr "op_type" "RRF")
7006 (set_attr "type" "fsimp<mode>")])
7009 ;;- Square root instructions.
7013 ; sqrt(df|sf)2 instruction pattern(s).
7016 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7017 (define_insn "sqrt<mode>2"
7018 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7019 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7024 [(set_attr "op_type" "RRE,RXE")
7025 (set_attr "type" "fsqrt<mode>")])
7029 ;;- One complement instructions.
7033 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7036 (define_expand "one_cmpl<mode>2"
7038 [(set (match_operand:INT 0 "register_operand" "")
7039 (xor:INT (match_operand:INT 1 "register_operand" "")
7041 (clobber (reg:CC CC_REGNUM))])]
7047 ;; Find leftmost bit instructions.
7050 (define_expand "clzdi2"
7051 [(set (match_operand:DI 0 "register_operand" "=d")
7052 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7053 "TARGET_EXTIMM && TARGET_64BIT"
7055 rtx insn, clz_equal;
7056 rtx wide_reg = gen_reg_rtx (TImode);
7057 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7059 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7061 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7063 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7064 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7069 (define_insn "clztidi2"
7070 [(set (match_operand:TI 0 "register_operand" "=d")
7074 (xor:DI (match_operand:DI 1 "register_operand" "d")
7075 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7076 (subreg:SI (clz:DI (match_dup 1)) 4))))
7079 (zero_extend:TI (clz:DI (match_dup 1)))))
7080 (clobber (reg:CC CC_REGNUM))]
7081 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7082 == (unsigned HOST_WIDE_INT) 1 << 63
7083 && TARGET_EXTIMM && TARGET_64BIT"
7085 [(set_attr "op_type" "RRE")])
7089 ;;- Rotate instructions.
7093 ; rotl(di|si)3 instruction pattern(s).
7097 (define_insn "rotl<mode>3"
7098 [(set (match_operand:GPR 0 "register_operand" "=d")
7099 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7100 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7103 [(set_attr "op_type" "RSE")
7104 (set_attr "atype" "reg")
7105 (set_attr "z10prop" "z10_super_E1")])
7108 (define_insn "*rotl<mode>3_and"
7109 [(set (match_operand:GPR 0 "register_operand" "=d")
7110 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7111 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7112 (match_operand:SI 3 "const_int_operand" "n"))))]
7113 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7115 [(set_attr "op_type" "RSE")
7116 (set_attr "atype" "reg")
7117 (set_attr "z10prop" "z10_super_E1")])
7121 ;;- Shift instructions.
7125 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7128 (define_expand "<shift><mode>3"
7129 [(set (match_operand:DSI 0 "register_operand" "")
7130 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7131 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7136 (define_insn "*<shift>di3_31"
7137 [(set (match_operand:DI 0 "register_operand" "=d")
7138 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7139 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7142 [(set_attr "op_type" "RS")
7143 (set_attr "atype" "reg")])
7145 ; sll, srl, sllg, srlg
7146 (define_insn "*<shift><mode>3"
7147 [(set (match_operand:GPR 0 "register_operand" "=d")
7148 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7149 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7151 "s<lr>l<g>\t%0,<1>%Y2"
7152 [(set_attr "op_type" "RS<E>")
7153 (set_attr "atype" "reg")
7154 (set_attr "z10prop" "z10_super_E1")])
7157 (define_insn "*<shift>di3_31_and"
7158 [(set (match_operand:DI 0 "register_operand" "=d")
7159 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7160 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7161 (match_operand:SI 3 "const_int_operand" "n"))))]
7162 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7164 [(set_attr "op_type" "RS")
7165 (set_attr "atype" "reg")])
7167 ; sll, srl, sllg, srlg
7168 (define_insn "*<shift><mode>3_and"
7169 [(set (match_operand:GPR 0 "register_operand" "=d")
7170 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7171 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7172 (match_operand:SI 3 "const_int_operand" "n"))))]
7173 "(INTVAL (operands[3]) & 63) == 63"
7174 "s<lr>l<g>\t%0,<1>%Y2"
7175 [(set_attr "op_type" "RS<E>")
7176 (set_attr "atype" "reg")
7177 (set_attr "z10prop" "z10_super_E1")])
7180 ; ashr(di|si)3 instruction pattern(s).
7183 (define_expand "ashr<mode>3"
7185 [(set (match_operand:DSI 0 "register_operand" "")
7186 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7187 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7188 (clobber (reg:CC CC_REGNUM))])]
7192 (define_insn "*ashrdi3_cc_31"
7193 [(set (reg CC_REGNUM)
7194 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7195 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7197 (set (match_operand:DI 0 "register_operand" "=d")
7198 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7199 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7201 [(set_attr "op_type" "RS")
7202 (set_attr "atype" "reg")])
7204 (define_insn "*ashrdi3_cconly_31"
7205 [(set (reg CC_REGNUM)
7206 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7207 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7209 (clobber (match_scratch:DI 0 "=d"))]
7210 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7212 [(set_attr "op_type" "RS")
7213 (set_attr "atype" "reg")])
7215 (define_insn "*ashrdi3_31"
7216 [(set (match_operand:DI 0 "register_operand" "=d")
7217 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7218 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7219 (clobber (reg:CC CC_REGNUM))]
7222 [(set_attr "op_type" "RS")
7223 (set_attr "atype" "reg")])
7226 (define_insn "*ashr<mode>3_cc"
7227 [(set (reg CC_REGNUM)
7228 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7229 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7231 (set (match_operand:GPR 0 "register_operand" "=d")
7232 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7233 "s390_match_ccmode(insn, CCSmode)"
7235 [(set_attr "op_type" "RS<E>")
7236 (set_attr "atype" "reg")
7237 (set_attr "z10prop" "z10_super_E1")])
7240 (define_insn "*ashr<mode>3_cconly"
7241 [(set (reg CC_REGNUM)
7242 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7243 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7245 (clobber (match_scratch:GPR 0 "=d"))]
7246 "s390_match_ccmode(insn, CCSmode)"
7248 [(set_attr "op_type" "RS<E>")
7249 (set_attr "atype" "reg")
7250 (set_attr "z10prop" "z10_super_E1")])
7253 (define_insn "*ashr<mode>3"
7254 [(set (match_operand:GPR 0 "register_operand" "=d")
7255 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7256 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7257 (clobber (reg:CC CC_REGNUM))]
7260 [(set_attr "op_type" "RS<E>")
7261 (set_attr "atype" "reg")
7262 (set_attr "z10prop" "z10_super_E1")])
7265 ; shift pattern with implicit ANDs
7267 (define_insn "*ashrdi3_cc_31_and"
7268 [(set (reg CC_REGNUM)
7269 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7270 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7271 (match_operand:SI 3 "const_int_operand" "n")))
7273 (set (match_operand:DI 0 "register_operand" "=d")
7274 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7275 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7276 && (INTVAL (operands[3]) & 63) == 63"
7278 [(set_attr "op_type" "RS")
7279 (set_attr "atype" "reg")])
7281 (define_insn "*ashrdi3_cconly_31_and"
7282 [(set (reg CC_REGNUM)
7283 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7284 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7285 (match_operand:SI 3 "const_int_operand" "n")))
7287 (clobber (match_scratch:DI 0 "=d"))]
7288 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7289 && (INTVAL (operands[3]) & 63) == 63"
7291 [(set_attr "op_type" "RS")
7292 (set_attr "atype" "reg")])
7294 (define_insn "*ashrdi3_31_and"
7295 [(set (match_operand:DI 0 "register_operand" "=d")
7296 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7297 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7298 (match_operand:SI 3 "const_int_operand" "n"))))
7299 (clobber (reg:CC CC_REGNUM))]
7300 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7302 [(set_attr "op_type" "RS")
7303 (set_attr "atype" "reg")])
7306 (define_insn "*ashr<mode>3_cc_and"
7307 [(set (reg CC_REGNUM)
7308 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7309 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7310 (match_operand:SI 3 "const_int_operand" "n")))
7312 (set (match_operand:GPR 0 "register_operand" "=d")
7313 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7314 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7316 [(set_attr "op_type" "RS<E>")
7317 (set_attr "atype" "reg")
7318 (set_attr "z10prop" "z10_super_E1")])
7321 (define_insn "*ashr<mode>3_cconly_and"
7322 [(set (reg CC_REGNUM)
7323 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7324 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7325 (match_operand:SI 3 "const_int_operand" "n")))
7327 (clobber (match_scratch:GPR 0 "=d"))]
7328 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7330 [(set_attr "op_type" "RS<E>")
7331 (set_attr "atype" "reg")
7332 (set_attr "z10prop" "z10_super_E1")])
7335 (define_insn "*ashr<mode>3_and"
7336 [(set (match_operand:GPR 0 "register_operand" "=d")
7337 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7338 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7339 (match_operand:SI 3 "const_int_operand" "n"))))
7340 (clobber (reg:CC CC_REGNUM))]
7341 "(INTVAL (operands[3]) & 63) == 63"
7343 [(set_attr "op_type" "RS<E>")
7344 (set_attr "atype" "reg")
7345 (set_attr "z10prop" "z10_super_E1")])
7349 ;; Branch instruction patterns.
7352 (define_expand "b<code>"
7354 (if_then_else (COMPARE (match_operand 0 "" "")
7359 "s390_emit_jump (operands[0],
7360 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
7364 ;;- Conditional jump instructions.
7367 (define_insn "*cjump_64"
7370 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7371 (label_ref (match_operand 0 "" ""))
7375 if (get_attr_length (insn) == 4)
7378 return "jg%C1\t%l0";
7380 [(set_attr "op_type" "RI")
7381 (set_attr "type" "branch")
7382 (set (attr "length")
7383 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7384 (const_int 4) (const_int 6)))])
7386 (define_insn "*cjump_31"
7389 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7390 (label_ref (match_operand 0 "" ""))
7394 gcc_assert (get_attr_length (insn) == 4);
7397 [(set_attr "op_type" "RI")
7398 (set_attr "type" "branch")
7399 (set (attr "length")
7400 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7401 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7402 (const_int 4) (const_int 6))
7403 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7404 (const_int 4) (const_int 8))))])
7406 (define_insn "*cjump_long"
7409 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7410 (match_operand 0 "address_operand" "U")
7414 if (get_attr_op_type (insn) == OP_TYPE_RR)
7419 [(set (attr "op_type")
7420 (if_then_else (match_operand 0 "register_operand" "")
7421 (const_string "RR") (const_string "RX")))
7422 (set_attr "type" "branch")
7423 (set_attr "atype" "agen")])
7427 ;;- Negated conditional jump instructions.
7430 (define_insn "*icjump_64"
7433 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7435 (label_ref (match_operand 0 "" ""))))]
7438 if (get_attr_length (insn) == 4)
7441 return "jg%D1\t%l0";
7443 [(set_attr "op_type" "RI")
7444 (set_attr "type" "branch")
7445 (set (attr "length")
7446 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7447 (const_int 4) (const_int 6)))])
7449 (define_insn "*icjump_31"
7452 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7454 (label_ref (match_operand 0 "" ""))))]
7457 gcc_assert (get_attr_length (insn) == 4);
7460 [(set_attr "op_type" "RI")
7461 (set_attr "type" "branch")
7462 (set (attr "length")
7463 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7464 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7465 (const_int 4) (const_int 6))
7466 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7467 (const_int 4) (const_int 8))))])
7469 (define_insn "*icjump_long"
7472 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7474 (match_operand 0 "address_operand" "U")))]
7477 if (get_attr_op_type (insn) == OP_TYPE_RR)
7482 [(set (attr "op_type")
7483 (if_then_else (match_operand 0 "register_operand" "")
7484 (const_string "RR") (const_string "RX")))
7485 (set_attr "type" "branch")
7486 (set_attr "atype" "agen")])
7489 ;;- Trap instructions.
7493 [(trap_if (const_int 1) (const_int 0))]
7496 [(set_attr "op_type" "RI")
7497 (set_attr "type" "branch")])
7499 (define_expand "conditional_trap"
7500 [(trap_if (match_operand 0 "comparison_operator" "")
7501 (match_operand 1 "general_operand" ""))]
7504 if (operands[1] != const0_rtx) FAIL;
7505 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
7506 s390_compare_op0, s390_compare_op1);
7509 (define_insn "*trap"
7510 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7514 [(set_attr "op_type" "RI")
7515 (set_attr "type" "branch")])
7517 ; crt, cgrt, cit, cgit
7518 (define_insn "*cmp_and_trap_signed_int<mode>"
7519 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7520 [(match_operand:GPR 1 "register_operand" "d,d")
7521 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7527 [(set_attr "op_type" "RRF,RIE")
7528 (set_attr "type" "branch")
7529 (set_attr "z10prop" "z10_super_c,z10_super")])
7531 ; clrt, clgrt, clfit, clgit
7532 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7533 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7534 [(match_operand:GPR 1 "register_operand" "d,d")
7535 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7540 cl<gf>it%C0\t%1,%x2"
7541 [(set_attr "op_type" "RRF,RIE")
7542 (set_attr "type" "branch")
7543 (set_attr "z10prop" "z10_super_c,z10_super")])
7546 ;;- Loop instructions.
7548 ;; This is all complicated by the fact that since this is a jump insn
7549 ;; we must handle our own output reloads.
7551 (define_expand "doloop_end"
7552 [(use (match_operand 0 "" "")) ; loop pseudo
7553 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7554 (use (match_operand 2 "" "")) ; max iterations
7555 (use (match_operand 3 "" "")) ; loop level
7556 (use (match_operand 4 "" ""))] ; label
7559 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7560 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7561 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7562 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7563 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7564 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7571 (define_insn_and_split "doloop_si64"
7574 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7576 (label_ref (match_operand 0 "" ""))
7578 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7579 (plus:SI (match_dup 1) (const_int -1)))
7580 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7581 (clobber (reg:CC CC_REGNUM))]
7584 if (which_alternative != 0)
7586 else if (get_attr_length (insn) == 4)
7587 return "brct\t%1,%l0";
7589 return "ahi\t%1,-1\;jgne\t%l0";
7591 "&& reload_completed
7592 && (! REG_P (operands[2])
7593 || ! rtx_equal_p (operands[1], operands[2]))"
7594 [(set (match_dup 3) (match_dup 1))
7595 (parallel [(set (reg:CCAN CC_REGNUM)
7596 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7598 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7599 (set (match_dup 2) (match_dup 3))
7600 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7601 (label_ref (match_dup 0))
7604 [(set_attr "op_type" "RI")
7605 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7606 ; hurt us in the (rare) case of ahi.
7607 (set_attr "z10prop" "z10_super_E1")
7608 (set_attr "type" "branch")
7609 (set (attr "length")
7610 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7611 (const_int 4) (const_int 10)))])
7613 (define_insn_and_split "doloop_si31"
7616 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7618 (label_ref (match_operand 0 "" ""))
7620 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7621 (plus:SI (match_dup 1) (const_int -1)))
7622 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7623 (clobber (reg:CC CC_REGNUM))]
7626 if (which_alternative != 0)
7628 else if (get_attr_length (insn) == 4)
7629 return "brct\t%1,%l0";
7633 "&& reload_completed
7634 && (! REG_P (operands[2])
7635 || ! rtx_equal_p (operands[1], operands[2]))"
7636 [(set (match_dup 3) (match_dup 1))
7637 (parallel [(set (reg:CCAN CC_REGNUM)
7638 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7640 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7641 (set (match_dup 2) (match_dup 3))
7642 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7643 (label_ref (match_dup 0))
7646 [(set_attr "op_type" "RI")
7647 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7648 ; hurt us in the (rare) case of ahi.
7649 (set_attr "z10prop" "z10_super_E1")
7650 (set_attr "type" "branch")
7651 (set (attr "length")
7652 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7653 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7654 (const_int 4) (const_int 6))
7655 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7656 (const_int 4) (const_int 8))))])
7658 (define_insn "*doloop_si_long"
7661 (ne (match_operand:SI 1 "register_operand" "d")
7663 (match_operand 0 "address_operand" "U")
7665 (set (match_operand:SI 2 "register_operand" "=1")
7666 (plus:SI (match_dup 1) (const_int -1)))
7667 (clobber (match_scratch:SI 3 "=X"))
7668 (clobber (reg:CC CC_REGNUM))]
7671 if (get_attr_op_type (insn) == OP_TYPE_RR)
7672 return "bctr\t%1,%0";
7674 return "bct\t%1,%a0";
7676 [(set (attr "op_type")
7677 (if_then_else (match_operand 0 "register_operand" "")
7678 (const_string "RR") (const_string "RX")))
7679 (set_attr "type" "branch")
7680 (set_attr "atype" "agen")
7681 (set_attr "z10prop" "z10_cobra")])
7683 (define_insn_and_split "doloop_di"
7686 (ne (match_operand:DI 1 "register_operand" "d,d,d")
7688 (label_ref (match_operand 0 "" ""))
7690 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7691 (plus:DI (match_dup 1) (const_int -1)))
7692 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7693 (clobber (reg:CC CC_REGNUM))]
7696 if (which_alternative != 0)
7698 else if (get_attr_length (insn) == 4)
7699 return "brctg\t%1,%l0";
7701 return "aghi\t%1,-1\;jgne\t%l0";
7703 "&& reload_completed
7704 && (! REG_P (operands[2])
7705 || ! rtx_equal_p (operands[1], operands[2]))"
7706 [(set (match_dup 3) (match_dup 1))
7707 (parallel [(set (reg:CCAN CC_REGNUM)
7708 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7710 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7711 (set (match_dup 2) (match_dup 3))
7712 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7713 (label_ref (match_dup 0))
7716 [(set_attr "op_type" "RI")
7717 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7718 ; hurt us in the (rare) case of ahi.
7719 (set_attr "z10prop" "z10_super_E1")
7720 (set_attr "type" "branch")
7721 (set (attr "length")
7722 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7723 (const_int 4) (const_int 10)))])
7726 ;;- Unconditional jump instructions.
7730 ; jump instruction pattern(s).
7733 (define_expand "jump"
7734 [(match_operand 0 "" "")]
7736 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7738 (define_insn "*jump64"
7739 [(set (pc) (label_ref (match_operand 0 "" "")))]
7742 if (get_attr_length (insn) == 4)
7747 [(set_attr "op_type" "RI")
7748 (set_attr "type" "branch")
7749 (set (attr "length")
7750 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7751 (const_int 4) (const_int 6)))])
7753 (define_insn "*jump31"
7754 [(set (pc) (label_ref (match_operand 0 "" "")))]
7757 gcc_assert (get_attr_length (insn) == 4);
7760 [(set_attr "op_type" "RI")
7761 (set_attr "type" "branch")
7762 (set (attr "length")
7763 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7764 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7765 (const_int 4) (const_int 6))
7766 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7767 (const_int 4) (const_int 8))))])
7770 ; indirect-jump instruction pattern(s).
7773 (define_insn "indirect_jump"
7774 [(set (pc) (match_operand 0 "address_operand" "U"))]
7777 if (get_attr_op_type (insn) == OP_TYPE_RR)
7782 [(set (attr "op_type")
7783 (if_then_else (match_operand 0 "register_operand" "")
7784 (const_string "RR") (const_string "RX")))
7785 (set_attr "type" "branch")
7786 (set_attr "atype" "agen")])
7789 ; casesi instruction pattern(s).
7792 (define_insn "casesi_jump"
7793 [(set (pc) (match_operand 0 "address_operand" "U"))
7794 (use (label_ref (match_operand 1 "" "")))]
7797 if (get_attr_op_type (insn) == OP_TYPE_RR)
7802 [(set (attr "op_type")
7803 (if_then_else (match_operand 0 "register_operand" "")
7804 (const_string "RR") (const_string "RX")))
7805 (set_attr "type" "branch")
7806 (set_attr "atype" "agen")])
7808 (define_expand "casesi"
7809 [(match_operand:SI 0 "general_operand" "")
7810 (match_operand:SI 1 "general_operand" "")
7811 (match_operand:SI 2 "general_operand" "")
7812 (label_ref (match_operand 3 "" ""))
7813 (label_ref (match_operand 4 "" ""))]
7816 rtx index = gen_reg_rtx (SImode);
7817 rtx base = gen_reg_rtx (Pmode);
7818 rtx target = gen_reg_rtx (Pmode);
7820 emit_move_insn (index, operands[0]);
7821 emit_insn (gen_subsi3 (index, index, operands[1]));
7822 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7825 if (Pmode != SImode)
7826 index = convert_to_mode (Pmode, index, 1);
7827 if (GET_CODE (index) != REG)
7828 index = copy_to_mode_reg (Pmode, index);
7831 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7833 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7835 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7837 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7838 emit_move_insn (target, index);
7841 target = gen_rtx_PLUS (Pmode, base, target);
7842 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7849 ;;- Jump to subroutine.
7854 ; untyped call instruction pattern(s).
7857 ;; Call subroutine returning any type.
7858 (define_expand "untyped_call"
7859 [(parallel [(call (match_operand 0 "" "")
7861 (match_operand 1 "" "")
7862 (match_operand 2 "" "")])]
7867 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7869 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7871 rtx set = XVECEXP (operands[2], 0, i);
7872 emit_move_insn (SET_DEST (set), SET_SRC (set));
7875 /* The optimizer does not know that the call sets the function value
7876 registers we stored in the result block. We avoid problems by
7877 claiming that all hard registers are used and clobbered at this
7879 emit_insn (gen_blockage ());
7884 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7885 ;; all of memory. This blocks insns from being moved across this point.
7887 (define_insn "blockage"
7888 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7891 [(set_attr "type" "none")
7892 (set_attr "length" "0")])
7898 (define_expand "sibcall"
7899 [(call (match_operand 0 "" "")
7900 (match_operand 1 "" ""))]
7903 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7907 (define_insn "*sibcall_br"
7908 [(call (mem:QI (reg SIBCALL_REGNUM))
7909 (match_operand 0 "const_int_operand" "n"))]
7910 "SIBLING_CALL_P (insn)
7911 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7913 [(set_attr "op_type" "RR")
7914 (set_attr "type" "branch")
7915 (set_attr "atype" "agen")])
7917 (define_insn "*sibcall_brc"
7918 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7919 (match_operand 1 "const_int_operand" "n"))]
7920 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7922 [(set_attr "op_type" "RI")
7923 (set_attr "type" "branch")])
7925 (define_insn "*sibcall_brcl"
7926 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7927 (match_operand 1 "const_int_operand" "n"))]
7928 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7930 [(set_attr "op_type" "RIL")
7931 (set_attr "type" "branch")])
7934 ; sibcall_value patterns
7937 (define_expand "sibcall_value"
7938 [(set (match_operand 0 "" "")
7939 (call (match_operand 1 "" "")
7940 (match_operand 2 "" "")))]
7943 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7947 (define_insn "*sibcall_value_br"
7948 [(set (match_operand 0 "" "")
7949 (call (mem:QI (reg SIBCALL_REGNUM))
7950 (match_operand 1 "const_int_operand" "n")))]
7951 "SIBLING_CALL_P (insn)
7952 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7954 [(set_attr "op_type" "RR")
7955 (set_attr "type" "branch")
7956 (set_attr "atype" "agen")])
7958 (define_insn "*sibcall_value_brc"
7959 [(set (match_operand 0 "" "")
7960 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7961 (match_operand 2 "const_int_operand" "n")))]
7962 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7964 [(set_attr "op_type" "RI")
7965 (set_attr "type" "branch")])
7967 (define_insn "*sibcall_value_brcl"
7968 [(set (match_operand 0 "" "")
7969 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7970 (match_operand 2 "const_int_operand" "n")))]
7971 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7973 [(set_attr "op_type" "RIL")
7974 (set_attr "type" "branch")])
7978 ; call instruction pattern(s).
7981 (define_expand "call"
7982 [(call (match_operand 0 "" "")
7983 (match_operand 1 "" ""))
7984 (use (match_operand 2 "" ""))]
7987 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7988 gen_rtx_REG (Pmode, RETURN_REGNUM));
7992 (define_insn "*bras"
7993 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7994 (match_operand 1 "const_int_operand" "n"))
7995 (clobber (match_operand 2 "register_operand" "=r"))]
7996 "!SIBLING_CALL_P (insn)
7997 && TARGET_SMALL_EXEC
7998 && GET_MODE (operands[2]) == Pmode"
8000 [(set_attr "op_type" "RI")
8001 (set_attr "type" "jsr")])
8003 (define_insn "*brasl"
8004 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8005 (match_operand 1 "const_int_operand" "n"))
8006 (clobber (match_operand 2 "register_operand" "=r"))]
8007 "!SIBLING_CALL_P (insn)
8009 && GET_MODE (operands[2]) == Pmode"
8011 [(set_attr "op_type" "RIL")
8012 (set_attr "type" "jsr")])
8014 (define_insn "*basr"
8015 [(call (mem:QI (match_operand 0 "address_operand" "U"))
8016 (match_operand 1 "const_int_operand" "n"))
8017 (clobber (match_operand 2 "register_operand" "=r"))]
8018 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8020 if (get_attr_op_type (insn) == OP_TYPE_RR)
8021 return "basr\t%2,%0";
8023 return "bas\t%2,%a0";
8025 [(set (attr "op_type")
8026 (if_then_else (match_operand 0 "register_operand" "")
8027 (const_string "RR") (const_string "RX")))
8028 (set_attr "type" "jsr")
8029 (set_attr "atype" "agen")])
8032 ; call_value instruction pattern(s).
8035 (define_expand "call_value"
8036 [(set (match_operand 0 "" "")
8037 (call (match_operand 1 "" "")
8038 (match_operand 2 "" "")))
8039 (use (match_operand 3 "" ""))]
8042 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8043 gen_rtx_REG (Pmode, RETURN_REGNUM));
8047 (define_insn "*bras_r"
8048 [(set (match_operand 0 "" "")
8049 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8050 (match_operand:SI 2 "const_int_operand" "n")))
8051 (clobber (match_operand 3 "register_operand" "=r"))]
8052 "!SIBLING_CALL_P (insn)
8053 && TARGET_SMALL_EXEC
8054 && GET_MODE (operands[3]) == Pmode"
8056 [(set_attr "op_type" "RI")
8057 (set_attr "type" "jsr")])
8059 (define_insn "*brasl_r"
8060 [(set (match_operand 0 "" "")
8061 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8062 (match_operand 2 "const_int_operand" "n")))
8063 (clobber (match_operand 3 "register_operand" "=r"))]
8064 "!SIBLING_CALL_P (insn)
8066 && GET_MODE (operands[3]) == Pmode"
8068 [(set_attr "op_type" "RIL")
8069 (set_attr "type" "jsr")])
8071 (define_insn "*basr_r"
8072 [(set (match_operand 0 "" "")
8073 (call (mem:QI (match_operand 1 "address_operand" "U"))
8074 (match_operand 2 "const_int_operand" "n")))
8075 (clobber (match_operand 3 "register_operand" "=r"))]
8076 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8078 if (get_attr_op_type (insn) == OP_TYPE_RR)
8079 return "basr\t%3,%1";
8081 return "bas\t%3,%a1";
8083 [(set (attr "op_type")
8084 (if_then_else (match_operand 1 "register_operand" "")
8085 (const_string "RR") (const_string "RX")))
8086 (set_attr "type" "jsr")
8087 (set_attr "atype" "agen")])
8090 ;;- Thread-local storage support.
8093 (define_expand "get_tp_64"
8094 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8098 (define_expand "get_tp_31"
8099 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8103 (define_expand "set_tp_64"
8104 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8105 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8109 (define_expand "set_tp_31"
8110 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8111 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8115 (define_insn "*set_tp"
8116 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8119 [(set_attr "type" "none")
8120 (set_attr "length" "0")])
8122 (define_insn "*tls_load_64"
8123 [(set (match_operand:DI 0 "register_operand" "=d")
8124 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8125 (match_operand:DI 2 "" "")]
8129 [(set_attr "op_type" "RXE")
8130 (set_attr "z10prop" "z10_fwd_A3")])
8132 (define_insn "*tls_load_31"
8133 [(set (match_operand:SI 0 "register_operand" "=d,d")
8134 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8135 (match_operand:SI 2 "" "")]
8141 [(set_attr "op_type" "RX,RXY")
8142 (set_attr "type" "load")
8143 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8145 (define_insn "*bras_tls"
8146 [(set (match_operand 0 "" "")
8147 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8148 (match_operand 2 "const_int_operand" "n")))
8149 (clobber (match_operand 3 "register_operand" "=r"))
8150 (use (match_operand 4 "" ""))]
8151 "!SIBLING_CALL_P (insn)
8152 && TARGET_SMALL_EXEC
8153 && GET_MODE (operands[3]) == Pmode"
8155 [(set_attr "op_type" "RI")
8156 (set_attr "type" "jsr")])
8158 (define_insn "*brasl_tls"
8159 [(set (match_operand 0 "" "")
8160 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8161 (match_operand 2 "const_int_operand" "n")))
8162 (clobber (match_operand 3 "register_operand" "=r"))
8163 (use (match_operand 4 "" ""))]
8164 "!SIBLING_CALL_P (insn)
8166 && GET_MODE (operands[3]) == Pmode"
8168 [(set_attr "op_type" "RIL")
8169 (set_attr "type" "jsr")])
8171 (define_insn "*basr_tls"
8172 [(set (match_operand 0 "" "")
8173 (call (mem:QI (match_operand 1 "address_operand" "U"))
8174 (match_operand 2 "const_int_operand" "n")))
8175 (clobber (match_operand 3 "register_operand" "=r"))
8176 (use (match_operand 4 "" ""))]
8177 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8179 if (get_attr_op_type (insn) == OP_TYPE_RR)
8180 return "basr\t%3,%1%J4";
8182 return "bas\t%3,%a1%J4";
8184 [(set (attr "op_type")
8185 (if_then_else (match_operand 1 "register_operand" "")
8186 (const_string "RR") (const_string "RX")))
8187 (set_attr "type" "jsr")
8188 (set_attr "atype" "agen")])
8191 ;;- Atomic operations
8195 ; memory barrier pattern.
8198 (define_expand "memory_barrier"
8200 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8203 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8204 MEM_VOLATILE_P (operands[0]) = 1;
8207 (define_insn "*memory_barrier"
8208 [(set (match_operand:BLK 0 "" "")
8209 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8212 [(set_attr "op_type" "RR")])
8214 ; Although bcr is superscalar on Z10, this variant will never become part of
8215 ; an execution group.
8218 ; compare and swap patterns.
8221 (define_expand "sync_compare_and_swap<mode>"
8223 [(set (match_operand:TDSI 0 "register_operand" "")
8224 (match_operand:TDSI 1 "memory_operand" ""))
8226 (unspec_volatile:TDSI
8228 (match_operand:TDSI 2 "register_operand" "")
8229 (match_operand:TDSI 3 "register_operand" "")]
8231 (set (reg:CCZ1 CC_REGNUM)
8232 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8235 (define_expand "sync_compare_and_swap<mode>"
8237 [(set (match_operand:HQI 0 "register_operand" "")
8238 (match_operand:HQI 1 "memory_operand" ""))
8240 (unspec_volatile:HQI
8242 (match_operand:HQI 2 "general_operand" "")
8243 (match_operand:HQI 3 "general_operand" "")]
8245 (set (reg:CCZ1 CC_REGNUM)
8246 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8248 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8249 operands[2], operands[3]); DONE;")
8251 (define_expand "sync_compare_and_swap_cc<mode>"
8253 [(set (match_operand:TDSI 0 "register_operand" "")
8254 (match_operand:TDSI 1 "memory_operand" ""))
8256 (unspec_volatile:TDSI
8258 (match_operand:TDSI 2 "register_operand" "")
8259 (match_operand:TDSI 3 "register_operand" "")]
8262 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8265 /* Emulate compare. */
8266 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
8267 s390_compare_op0 = operands[1];
8268 s390_compare_op1 = operands[2];
8269 s390_compare_emitted = operands[4];
8273 (define_insn "*sync_compare_and_swap<mode>"
8274 [(set (match_operand:DP 0 "register_operand" "=r")
8275 (match_operand:DP 1 "memory_operand" "+Q"))
8279 (match_operand:DP 2 "register_operand" "0")
8280 (match_operand:DP 3 "register_operand" "r")]
8282 (set (reg:CCZ1 CC_REGNUM)
8283 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8285 "cds<tg>\t%0,%3,%S1"
8286 [(set_attr "op_type" "RS<TE>")
8287 (set_attr "type" "sem")])
8290 (define_insn "*sync_compare_and_swap<mode>"
8291 [(set (match_operand:GPR 0 "register_operand" "=r")
8292 (match_operand:GPR 1 "memory_operand" "+Q"))
8294 (unspec_volatile:GPR
8296 (match_operand:GPR 2 "register_operand" "0")
8297 (match_operand:GPR 3 "register_operand" "r")]
8299 (set (reg:CCZ1 CC_REGNUM)
8300 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8303 [(set_attr "op_type" "RS<E>")
8304 (set_attr "type" "sem")])
8308 ; Other atomic instruction patterns.
8311 (define_expand "sync_lock_test_and_set<mode>"
8312 [(match_operand:HQI 0 "register_operand")
8313 (match_operand:HQI 1 "memory_operand")
8314 (match_operand:HQI 2 "general_operand")]
8316 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8317 operands[2], false); DONE;")
8319 (define_expand "sync_<atomic><mode>"
8320 [(set (match_operand:HQI 0 "memory_operand")
8321 (ATOMIC:HQI (match_dup 0)
8322 (match_operand:HQI 1 "general_operand")))]
8324 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8325 operands[1], false); DONE;")
8327 (define_expand "sync_old_<atomic><mode>"
8328 [(set (match_operand:HQI 0 "register_operand")
8329 (match_operand:HQI 1 "memory_operand"))
8331 (ATOMIC:HQI (match_dup 1)
8332 (match_operand:HQI 2 "general_operand")))]
8334 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8335 operands[2], false); DONE;")
8337 (define_expand "sync_new_<atomic><mode>"
8338 [(set (match_operand:HQI 0 "register_operand")
8339 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8340 (match_operand:HQI 2 "general_operand")))
8341 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8343 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8344 operands[2], true); DONE;")
8347 ;;- Miscellaneous instructions.
8351 ; allocate stack instruction pattern(s).
8354 (define_expand "allocate_stack"
8355 [(match_operand 0 "general_operand" "")
8356 (match_operand 1 "general_operand" "")]
8359 rtx temp = gen_reg_rtx (Pmode);
8361 emit_move_insn (temp, s390_back_chain_rtx ());
8362 anti_adjust_stack (operands[1]);
8363 emit_move_insn (s390_back_chain_rtx (), temp);
8365 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8371 ; setjmp instruction pattern.
8374 (define_expand "builtin_setjmp_receiver"
8375 [(match_operand 0 "" "")]
8378 emit_insn (s390_load_got ());
8379 emit_use (pic_offset_table_rtx);
8383 ;; These patterns say how to save and restore the stack pointer. We need not
8384 ;; save the stack pointer at function level since we are careful to
8385 ;; preserve the backchain. At block level, we have to restore the backchain
8386 ;; when we restore the stack pointer.
8388 ;; For nonlocal gotos, we must save both the stack pointer and its
8389 ;; backchain and restore both. Note that in the nonlocal case, the
8390 ;; save area is a memory location.
8392 (define_expand "save_stack_function"
8393 [(match_operand 0 "general_operand" "")
8394 (match_operand 1 "general_operand" "")]
8398 (define_expand "restore_stack_function"
8399 [(match_operand 0 "general_operand" "")
8400 (match_operand 1 "general_operand" "")]
8404 (define_expand "restore_stack_block"
8405 [(match_operand 0 "register_operand" "")
8406 (match_operand 1 "register_operand" "")]
8409 rtx temp = gen_reg_rtx (Pmode);
8411 emit_move_insn (temp, s390_back_chain_rtx ());
8412 emit_move_insn (operands[0], operands[1]);
8413 emit_move_insn (s390_back_chain_rtx (), temp);
8418 (define_expand "save_stack_nonlocal"
8419 [(match_operand 0 "memory_operand" "")
8420 (match_operand 1 "register_operand" "")]
8423 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8424 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8426 /* Copy the backchain to the first word, sp to the second and the
8427 literal pool base to the third. */
8429 if (TARGET_BACKCHAIN)
8431 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
8432 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
8435 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
8436 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
8441 (define_expand "restore_stack_nonlocal"
8442 [(match_operand 0 "register_operand" "")
8443 (match_operand 1 "memory_operand" "")]
8446 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8447 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8448 rtx temp = NULL_RTX;
8450 /* Restore the backchain from the first word, sp from the second and the
8451 literal pool base from the third. */
8453 if (TARGET_BACKCHAIN)
8454 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
8456 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
8457 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
8460 emit_move_insn (s390_back_chain_rtx (), temp);
8466 (define_expand "exception_receiver"
8470 s390_set_has_landing_pad_p (true);
8475 ; nop instruction pattern(s).
8482 [(set_attr "op_type" "RR")
8483 (set_attr "z10prop" "z10_fr_E1")])
8489 [(set_attr "op_type" "RR")])
8493 ; Special literal pool access instruction pattern(s).
8496 (define_insn "*pool_entry"
8497 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8498 UNSPECV_POOL_ENTRY)]
8501 enum machine_mode mode = GET_MODE (PATTERN (insn));
8502 unsigned int align = GET_MODE_BITSIZE (mode);
8503 s390_output_pool_entry (operands[0], mode, align);
8506 [(set (attr "length")
8507 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8509 (define_insn "pool_align"
8510 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8511 UNSPECV_POOL_ALIGN)]
8514 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8516 (define_insn "pool_section_start"
8517 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8520 [(set_attr "length" "0")])
8522 (define_insn "pool_section_end"
8523 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8526 [(set_attr "length" "0")])
8528 (define_insn "main_base_31_small"
8529 [(set (match_operand 0 "register_operand" "=a")
8530 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8531 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8533 [(set_attr "op_type" "RR")
8534 (set_attr "type" "la")])
8536 (define_insn "main_base_31_large"
8537 [(set (match_operand 0 "register_operand" "=a")
8538 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8539 (set (pc) (label_ref (match_operand 2 "" "")))]
8540 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8542 [(set_attr "op_type" "RI")])
8544 (define_insn "main_base_64"
8545 [(set (match_operand 0 "register_operand" "=a")
8546 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8547 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8549 [(set_attr "op_type" "RIL")
8550 (set_attr "type" "larl")
8551 (set_attr "z10prop" "z10_fwd_A1")])
8553 (define_insn "main_pool"
8554 [(set (match_operand 0 "register_operand" "=a")
8555 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8556 "GET_MODE (operands[0]) == Pmode"
8561 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8562 (const_string "larl") (const_string "la")))])
8564 (define_insn "reload_base_31"
8565 [(set (match_operand 0 "register_operand" "=a")
8566 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8567 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8568 "basr\t%0,0\;la\t%0,%1-.(%0)"
8569 [(set_attr "length" "6")
8570 (set_attr "type" "la")])
8572 (define_insn "reload_base_64"
8573 [(set (match_operand 0 "register_operand" "=a")
8574 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8575 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8577 [(set_attr "op_type" "RIL")
8578 (set_attr "type" "larl")
8579 (set_attr "z10prop" "z10_fwd_A1")])
8582 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8587 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8590 ;; Insns related to generating the function prologue and epilogue.
8594 (define_expand "prologue"
8595 [(use (const_int 0))]
8597 "s390_emit_prologue (); DONE;")
8599 (define_expand "epilogue"
8600 [(use (const_int 1))]
8602 "s390_emit_epilogue (false); DONE;")
8604 (define_expand "sibcall_epilogue"
8605 [(use (const_int 0))]
8607 "s390_emit_epilogue (true); DONE;")
8609 (define_insn "*return"
8611 (use (match_operand 0 "register_operand" "a"))]
8612 "GET_MODE (operands[0]) == Pmode"
8614 [(set_attr "op_type" "RR")
8615 (set_attr "type" "jsr")
8616 (set_attr "atype" "agen")])
8619 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8620 ;; pointer. This is used for compatibility.
8622 (define_expand "ptr_extend"
8623 [(set (match_operand:DI 0 "register_operand" "=r")
8624 (match_operand:SI 1 "register_operand" "r"))]
8627 emit_insn (gen_anddi3 (operands[0],
8628 gen_lowpart (DImode, operands[1]),
8629 GEN_INT (0x7fffffff)));
8633 ;; Instruction definition to expand eh_return macro to support
8634 ;; swapping in special linkage return addresses.
8636 (define_expand "eh_return"
8637 [(use (match_operand 0 "register_operand" ""))]
8640 s390_emit_tpf_eh_return (operands[0]);
8645 ; Stack Protector Patterns
8648 (define_expand "stack_protect_set"
8649 [(set (match_operand 0 "memory_operand" "")
8650 (match_operand 1 "memory_operand" ""))]
8653 #ifdef TARGET_THREAD_SSP_OFFSET
8655 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8656 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8659 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8661 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8666 (define_insn "stack_protect_set<mode>"
8667 [(set (match_operand:DSI 0 "memory_operand" "=Q")
8668 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8670 "mvc\t%O0(%G0,%R0),%S1"
8671 [(set_attr "op_type" "SS")])
8673 (define_expand "stack_protect_test"
8674 [(set (reg:CC CC_REGNUM)
8675 (compare (match_operand 0 "memory_operand" "")
8676 (match_operand 1 "memory_operand" "")))
8677 (match_operand 2 "" "")]
8680 #ifdef TARGET_THREAD_SSP_OFFSET
8682 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8683 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8685 s390_compare_op0 = operands[0];
8686 s390_compare_op1 = operands[1];
8687 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
8690 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8692 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8694 emit_jump_insn (gen_beq (operands[2]));
8699 (define_insn "stack_protect_test<mode>"
8700 [(set (reg:CCZ CC_REGNUM)
8701 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8702 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8704 "clc\t%O0(%G0,%R0),%S1"
8705 [(set_attr "op_type" "SS")])
8707 ; This is used in s390_emit_prologue in order to prevent insns
8708 ; adjusting the stack pointer to be moved over insns writing stack
8709 ; slots using a copy of the stack pointer in a different register.
8710 (define_insn "stack_tie"
8711 [(set (match_operand:BLK 0 "memory_operand" "+m")
8712 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
8715 [(set_attr "length" "0")])
8719 ; Data prefetch patterns
8722 (define_insn "prefetch"
8723 [(prefetch (match_operand 0 "address_operand" "UW,X")
8724 (match_operand:SI 1 "const_int_operand" "n,n")
8725 (match_operand:SI 2 "const_int_operand" "n,n"))]
8728 if (larl_operand (operands[0], Pmode))
8729 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
8731 if (s390_mem_constraint ("W", operands[0])
8732 || s390_mem_constraint ("U", operands[0]))
8733 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
8735 /* This point might be reached if op0 is a larl operand with an
8736 uneven addend. In this case we simply omit issuing a prefetch
8741 [(set_attr "type" "load,larl")
8742 (set_attr "op_type" "RXY,RIL")
8743 (set_attr "z10prop" "z10_super")])