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s390.md ("movti", [...]): Use 'o' instead of 'm' constraint in forced-split alternatives.
[gcc.git] / gcc / config / s390 / s390.md
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
21
22 ;;
23 ;; Special constraints for s/390 machine description:
24 ;;
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
32 ;;
33 ;; Special formats used for outputting 390 instructions.
34 ;;
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
41 ;;
42 ;; We have a special constraint for pattern matching.
43 ;;
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
45 ;;
46
47 ;;
48 ;; UNSPEC usage
49 ;;
50
51 (define_constants
52 [; TLS relocation specifiers
53 (UNSPEC_TLSGD 500)
54 (UNSPEC_TLSLDM 501)
55 (UNSPEC_NTPOFF 502)
56 (UNSPEC_DTPOFF 503)
57 (UNSPEC_GOTNTPOFF 504)
58 (UNSPEC_INDNTPOFF 505)
59
60 ; TLS support
61 (UNSPEC_TP 510)
62 (UNSPEC_TLSLDM_NTPOFF 511)
63 (UNSPEC_TLS_LOAD 512)
64 ])
65
66 ;;
67 ;; UNSPEC_VOLATILE usage
68 ;;
69
70 (define_constants
71 [; TLS support
72 (UNSPECV_SET_TP 500)
73 ])
74
75
76 ;; Processor type. This attribute must exactly match the processor_type
77 ;; enumeration in s390.h.
78
79 (define_attr "cpu" "g5,g6,z900"
80 (const (symbol_ref "s390_cpu")))
81
82 ;; Define an insn type attribute. This is used in function unit delay
83 ;; computations.
84
85 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
86 cs,vs,store,imul,idiv,
87 branch,jsr,fsimpd,fsimps,
88 floadd,floads,fstored, fstores,
89 fmuld,fmuls,fdivd,fdivs,
90 ftoi,itof,fsqrtd,fsqrts,
91 other,o2,o3"
92 (const_string "integer"))
93
94 ;; Operand type. Used to default length attribute values
95
96 (define_attr "op_type"
97 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
98 (const_string "RX"))
99
100 ;; Insn are devide in two classes:
101 ;; agen: Insn using agen
102 ;; reg: Insn not using agen
103
104 (define_attr "atype" "agen,reg"
105 (cond [ (eq_attr "op_type" "E") (const_string "reg")
106 (eq_attr "op_type" "RR") (const_string "reg")
107 (eq_attr "op_type" "RX") (const_string "agen")
108 (eq_attr "op_type" "RI") (const_string "reg")
109 (eq_attr "op_type" "RRE") (const_string "reg")
110 (eq_attr "op_type" "RS") (const_string "agen")
111 (eq_attr "op_type" "RSI") (const_string "agen")
112 (eq_attr "op_type" "S") (const_string "agen")
113 (eq_attr "op_type" "SI") (const_string "agen")
114 (eq_attr "op_type" "SS") (const_string "agen")
115 (eq_attr "op_type" "SSE") (const_string "agen")
116 (eq_attr "op_type" "RXE") (const_string "agen")
117 (eq_attr "op_type" "RSE") (const_string "agen")
118 (eq_attr "op_type" "RIL") (const_string "agen")]
119 (const_string "reg")))
120
121 ;; Generic pipeline function unit.
122
123 (define_function_unit "integer" 1 0
124 (eq_attr "type" "none") 0 0)
125
126 (define_function_unit "integer" 1 0
127 (eq_attr "type" "integer") 1 1)
128
129 (define_function_unit "integer" 1 0
130 (eq_attr "type" "fsimpd") 1 1)
131
132 (define_function_unit "integer" 1 0
133 (eq_attr "type" "fsimps") 1 1)
134
135 (define_function_unit "integer" 1 0
136 (eq_attr "type" "load") 1 1)
137
138 (define_function_unit "integer" 1 0
139 (eq_attr "type" "floadd") 1 1)
140
141 (define_function_unit "integer" 1 0
142 (eq_attr "type" "floads") 1 1)
143
144 (define_function_unit "integer" 1 0
145 (eq_attr "type" "la") 1 1)
146
147 (define_function_unit "integer" 1 0
148 (eq_attr "type" "larl") 1 1)
149
150 (define_function_unit "integer" 1 0
151 (eq_attr "type" "lr") 1 1)
152
153 (define_function_unit "integer" 1 0
154 (eq_attr "type" "branch") 1 1)
155
156 (define_function_unit "integer" 1 0
157 (eq_attr "type" "store") 1 1)
158
159 (define_function_unit "integer" 1 0
160 (eq_attr "type" "fstored") 1 1)
161
162 (define_function_unit "integer" 1 0
163 (eq_attr "type" "fstores") 1 1)
164
165 (define_function_unit "integer" 1 0
166 (eq_attr "type" "lm") 2 2)
167
168 (define_function_unit "integer" 1 0
169 (eq_attr "type" "stm") 2 2)
170
171 (define_function_unit "integer" 1 0
172 (eq_attr "type" "cs") 5 5)
173
174 (define_function_unit "integer" 1 0
175 (eq_attr "type" "vs") 30 30)
176
177 (define_function_unit "integer" 1 0
178 (eq_attr "type" "jsr") 5 5)
179
180 (define_function_unit "integer" 1 0
181 (eq_attr "type" "imul") 7 7)
182
183 (define_function_unit "integer" 1 0
184 (eq_attr "type" "fmuld") 6 6)
185
186 (define_function_unit "integer" 1 0
187 (eq_attr "type" "fmuls") 6 6)
188
189 (define_function_unit "integer" 1 0
190 (eq_attr "type" "idiv") 33 33)
191
192 (define_function_unit "integer" 1 0
193 (eq_attr "type" "fdivd") 33 33)
194
195 (define_function_unit "integer" 1 0
196 (eq_attr "type" "fdivs") 33 33)
197
198 (define_function_unit "integer" 1 0
199 (eq_attr "type" "fsqrtd") 30 30)
200
201 (define_function_unit "integer" 1 0
202 (eq_attr "type" "fsqrts") 30 30)
203
204 (define_function_unit "integer" 1 0
205 (eq_attr "type" "ftoi") 2 2)
206
207 (define_function_unit "integer" 1 0
208 (eq_attr "type" "itof") 2 2)
209
210 (define_function_unit "integer" 1 0
211 (eq_attr "type" "o2") 2 2)
212
213 (define_function_unit "integer" 1 0
214 (eq_attr "type" "o3") 3 3)
215
216 (define_function_unit "integer" 1 0
217 (eq_attr "type" "other") 5 5)
218
219 ;; Pipeline description for z900
220
221 (include "2064.md")
222
223 ;; Length in bytes.
224
225 (define_attr "length" ""
226 (cond [ (eq_attr "op_type" "E") (const_int 2)
227 (eq_attr "op_type" "RR") (const_int 2)
228 (eq_attr "op_type" "RX") (const_int 4)
229 (eq_attr "op_type" "RI") (const_int 4)
230 (eq_attr "op_type" "RRE") (const_int 4)
231 (eq_attr "op_type" "RS") (const_int 4)
232 (eq_attr "op_type" "RSI") (const_int 4)
233 (eq_attr "op_type" "S") (const_int 4)
234 (eq_attr "op_type" "SI") (const_int 4)
235 (eq_attr "op_type" "SS") (const_int 6)
236 (eq_attr "op_type" "SSE") (const_int 6)
237 (eq_attr "op_type" "RXE") (const_int 6)
238 (eq_attr "op_type" "RSE") (const_int 6)
239 (eq_attr "op_type" "RIL") (const_int 6)]
240 (const_int 4)))
241
242 ;; Define attributes for `asm' insns.
243
244 (define_asm_attributes [(set_attr "type" "other")
245 (set_attr "op_type" "NN")])
246
247 ;;
248 ;; Condition Codes
249 ;;
250 ;
251 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
252 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
253 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
254 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
255 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
256
257 ; CCZ -> CCL / CCZ1
258 ; CCZ1 -> CCA/CCU/CCS/CCT
259 ; CCS -> CCA
260
261 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
262 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
263
264
265 ;;
266 ;;- Compare instructions.
267 ;;
268
269 (define_expand "cmpdi"
270 [(set (reg:CC 33)
271 (compare:CC (match_operand:DI 0 "register_operand" "")
272 (match_operand:DI 1 "general_operand" "")))]
273 "TARGET_64BIT"
274 "
275 {
276 s390_compare_op0 = operands[0];
277 s390_compare_op1 = operands[1];
278 DONE;
279 }")
280
281 (define_expand "cmpsi"
282 [(set (reg:CC 33)
283 (compare:CC (match_operand:SI 0 "register_operand" "")
284 (match_operand:SI 1 "general_operand" "")))]
285 ""
286 "
287 {
288 s390_compare_op0 = operands[0];
289 s390_compare_op1 = operands[1];
290 DONE;
291 }")
292
293 (define_expand "cmpdf"
294 [(set (reg:CC 33)
295 (compare:CC (match_operand:DF 0 "register_operand" "")
296 (match_operand:DF 1 "general_operand" "")))]
297 "TARGET_HARD_FLOAT"
298 "
299 {
300 s390_compare_op0 = operands[0];
301 s390_compare_op1 = operands[1];
302 DONE;
303 }")
304
305 (define_expand "cmpsf"
306 [(set (reg:CC 33)
307 (compare:CC (match_operand:SF 0 "register_operand" "")
308 (match_operand:SF 1 "general_operand" "")))]
309 "TARGET_HARD_FLOAT"
310 "
311 {
312 s390_compare_op0 = operands[0];
313 s390_compare_op1 = operands[1];
314 DONE;
315 }")
316
317
318 ; Test-under-Mask (zero_extract) instructions
319
320 (define_insn "*tmdi_ext"
321 [(set (reg 33)
322 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
323 (match_operand:DI 1 "const_int_operand" "n")
324 (match_operand:DI 2 "const_int_operand" "n"))
325 (const_int 0)))]
326 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
327 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
328 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
329 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
330 == INTVAL (operands[2]) >> 4"
331 "*
332 {
333 int part = INTVAL (operands[2]) >> 4;
334 int block = (1 << INTVAL (operands[1])) - 1;
335 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
336
337 operands[2] = GEN_INT (block << shift);
338
339 switch (part)
340 {
341 case 0: return \"tmhh\\t%0,%x2\";
342 case 1: return \"tmhl\\t%0,%x2\";
343 case 2: return \"tmlh\\t%0,%x2\";
344 case 3: return \"tmll\\t%0,%x2\";
345 default: abort ();
346 }
347 }"
348 [(set_attr "op_type" "RI")])
349
350 (define_insn "*tmsi_ext"
351 [(set (reg 33)
352 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
353 (match_operand:SI 1 "const_int_operand" "n")
354 (match_operand:SI 2 "const_int_operand" "n"))
355 (const_int 0)))]
356 "s390_match_ccmode(insn, CCTmode)
357 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
358 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
359 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
360 == INTVAL (operands[2]) >> 4"
361 "*
362 {
363 int part = INTVAL (operands[2]) >> 4;
364 int block = (1 << INTVAL (operands[1])) - 1;
365 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
366
367 operands[2] = GEN_INT (block << shift);
368
369 switch (part)
370 {
371 case 0: return \"tmh\\t%0,%x2\";
372 case 1: return \"tml\\t%0,%x2\";
373 default: abort ();
374 }
375 }"
376 [(set_attr "op_type" "RI")])
377
378 (define_insn "*tmqi_ext"
379 [(set (reg 33)
380 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
381 (match_operand:SI 1 "const_int_operand" "n")
382 (match_operand:SI 2 "const_int_operand" "n"))
383 (const_int 0)))]
384 "s390_match_ccmode(insn, CCTmode)
385 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
386 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
387 "*
388 {
389 int block = (1 << INTVAL (operands[1])) - 1;
390 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
391
392 operands[2] = GEN_INT (block << shift);
393 return \"tm\\t%0,%b2\";
394 }"
395 [(set_attr "op_type" "SI")])
396
397 ; Test-under-Mask instructions
398
399 (define_insn "*tmdi_mem"
400 [(set (reg 33)
401 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
402 (match_operand:DI 1 "immediate_operand" "n"))
403 (match_operand:DI 2 "immediate_operand" "n")))]
404 "TARGET_64BIT
405 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
406 && s390_single_qi (operands[1], DImode, 0) >= 0"
407 "*
408 {
409 int part = s390_single_qi (operands[1], DImode, 0);
410 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
411
412 operands[0] = gen_rtx_MEM (QImode,
413 plus_constant (XEXP (operands[0], 0), part));
414 return \"tm\\t%0,%b1\";
415 }"
416 [(set_attr "op_type" "SI")])
417
418 (define_insn "*tmsi_mem"
419 [(set (reg 33)
420 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
421 (match_operand:SI 1 "immediate_operand" "n"))
422 (match_operand:SI 2 "immediate_operand" "n")))]
423 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
424 && s390_single_qi (operands[1], SImode, 0) >= 0"
425 "*
426 {
427 int part = s390_single_qi (operands[1], SImode, 0);
428 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
429
430 operands[0] = gen_rtx_MEM (QImode,
431 plus_constant (XEXP (operands[0], 0), part));
432 return \"tm\\t%0,%b1\";
433 }"
434 [(set_attr "op_type" "SI")])
435
436 (define_insn "*tmhi_mem"
437 [(set (reg 33)
438 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
439 (match_operand:SI 1 "immediate_operand" "n"))
440 (match_operand:SI 2 "immediate_operand" "n")))]
441 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
442 && s390_single_qi (operands[1], HImode, 0) >= 0"
443 "*
444 {
445 int part = s390_single_qi (operands[1], HImode, 0);
446 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
447
448 operands[0] = gen_rtx_MEM (QImode,
449 plus_constant (XEXP (operands[0], 0), part));
450 return \"tm\\t%0,%b1\";
451 }"
452 [(set_attr "op_type" "SI")])
453
454 (define_insn "*tmqi_mem"
455 [(set (reg 33)
456 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
457 (match_operand:SI 1 "immediate_operand" "n"))
458 (match_operand:SI 2 "immediate_operand" "n")))]
459 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
460 "tm\\t%0,%b1"
461 [(set_attr "op_type" "SI")])
462
463 (define_insn "*tmdi_reg"
464 [(set (reg 33)
465 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
466 (match_operand:DI 1 "immediate_operand" "n"))
467 (match_operand:DI 2 "immediate_operand" "n")))]
468 "TARGET_64BIT
469 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
470 && s390_single_hi (operands[1], DImode, 0) >= 0"
471 "*
472 {
473 int part = s390_single_hi (operands[1], DImode, 0);
474 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
475
476 switch (part)
477 {
478 case 0: return \"tmhh\\t%0,%x1\";
479 case 1: return \"tmhl\\t%0,%x1\";
480 case 2: return \"tmlh\\t%0,%x1\";
481 case 3: return \"tmll\\t%0,%x1\";
482 default: abort ();
483 }
484 }"
485 [(set_attr "op_type" "RI")])
486
487 (define_insn "*tmsi_reg"
488 [(set (reg 33)
489 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
490 (match_operand:SI 1 "immediate_operand" "n"))
491 (match_operand:SI 2 "immediate_operand" "n")))]
492 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
493 && s390_single_hi (operands[1], SImode, 0) >= 0"
494 "*
495 {
496 int part = s390_single_hi (operands[1], SImode, 0);
497 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
498
499 switch (part)
500 {
501 case 0: return \"tmh\\t%0,%x1\";
502 case 1: return \"tml\\t%0,%x1\";
503 default: abort ();
504 }
505 }"
506 [(set_attr "op_type" "RI")])
507
508 (define_insn "*tmhi_full"
509 [(set (reg 33)
510 (compare (match_operand:HI 0 "register_operand" "d")
511 (match_operand:HI 1 "immediate_operand" "n")))]
512 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
513 "tml\\t%0,65535"
514 [(set_attr "op_type" "RX")])
515
516 (define_insn "*tmqi_full"
517 [(set (reg 33)
518 (compare (match_operand:QI 0 "register_operand" "d")
519 (match_operand:QI 1 "immediate_operand" "n")))]
520 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
521 "tml\\t%0,255"
522 [(set_attr "op_type" "RI")])
523
524
525 ; Load-and-Test instructions
526
527 (define_insn "*tstdi_sign"
528 [(set (reg 33)
529 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
530 (const_int 32)) (const_int 32))
531 (match_operand:DI 1 "const0_operand" "")))
532 (set (match_operand:DI 2 "register_operand" "=d")
533 (sign_extend:DI (match_dup 0)))]
534 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
535 "ltgfr\\t%2,%0"
536 [(set_attr "op_type" "RRE")])
537
538 (define_insn "*tstdi"
539 [(set (reg 33)
540 (compare (match_operand:DI 0 "register_operand" "d")
541 (match_operand:DI 1 "const0_operand" "")))
542 (set (match_operand:DI 2 "register_operand" "=d")
543 (match_dup 0))]
544 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
545 "ltgr\\t%2,%0"
546 [(set_attr "op_type" "RRE")])
547
548 (define_insn "*tstdi_cconly"
549 [(set (reg 33)
550 (compare (match_operand:DI 0 "register_operand" "d")
551 (match_operand:DI 1 "const0_operand" "")))]
552 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
553 "ltgr\\t%0,%0"
554 [(set_attr "op_type" "RRE")])
555
556 (define_insn "*tstdi_cconly_31"
557 [(set (reg 33)
558 (compare (match_operand:DI 0 "register_operand" "d")
559 (match_operand:DI 1 "const0_operand" "")))]
560 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
561 "srda\\t%0,0"
562 [(set_attr "op_type" "RS")
563 (set_attr "atype" "reg")])
564
565
566 (define_insn "*tstsi"
567 [(set (reg 33)
568 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
569 (match_operand:SI 1 "const0_operand" "")))
570 (set (match_operand:SI 2 "register_operand" "=d,d")
571 (match_dup 0))]
572 "s390_match_ccmode(insn, CCSmode)"
573 "@
574 ltr\\t%2,%0
575 icm\\t%2,15,%0"
576 [(set_attr "op_type" "RR,RS")])
577
578 (define_insn "*tstsi_cconly"
579 [(set (reg 33)
580 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
581 (match_operand:SI 1 "const0_operand" "")))
582 (clobber (match_scratch:SI 2 "=X,d"))]
583 "s390_match_ccmode(insn, CCSmode)"
584 "@
585 ltr\\t%0,%0
586 icm\\t%2,15,%0"
587 [(set_attr "op_type" "RR,RS")])
588
589 (define_insn "*tstsi_cconly2"
590 [(set (reg 33)
591 (compare (match_operand:SI 0 "register_operand" "d")
592 (match_operand:SI 1 "const0_operand" "")))]
593 "s390_match_ccmode(insn, CCSmode)"
594 "ltr\\t%0,%0"
595 [(set_attr "op_type" "RR")])
596
597 (define_insn "*tsthiCCT"
598 [(set (reg 33)
599 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
600 (match_operand:HI 1 "const0_operand" "")))
601 (set (match_operand:HI 2 "register_operand" "=d,0")
602 (match_dup 0))]
603 "s390_match_ccmode(insn, CCTmode)"
604 "@
605 icm\\t%2,3,%0
606 tml\\t%0,65535"
607 [(set_attr "op_type" "RS,RI")])
608
609 (define_insn "*tsthiCCT_cconly"
610 [(set (reg 33)
611 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,d")
612 (match_operand:HI 1 "const0_operand" "")))
613 (clobber (match_scratch:HI 2 "=d,X"))]
614 "s390_match_ccmode(insn, CCTmode)"
615 "@
616 icm\\t%2,3,%0
617 tml\\t%0,65535"
618 [(set_attr "op_type" "RS,RI")])
619
620 (define_insn "*tsthi"
621 [(set (reg 33)
622 (compare (match_operand:HI 0 "s_operand" "Q")
623 (match_operand:HI 1 "const0_operand" "")))
624 (set (match_operand:HI 2 "register_operand" "=d")
625 (match_dup 0))]
626 "s390_match_ccmode(insn, CCSmode)"
627 "icm\\t%2,3,%0"
628 [(set_attr "op_type" "RS")])
629
630 (define_insn "*tsthi_cconly"
631 [(set (reg 33)
632 (compare (match_operand:HI 0 "s_operand" "Q")
633 (match_operand:HI 1 "const0_operand" "")))
634 (clobber (match_scratch:HI 2 "=d"))]
635 "s390_match_ccmode(insn, CCSmode)"
636 "icm\\t%2,3,%0"
637 [(set_attr "op_type" "RS")])
638
639 (define_insn "*tstqiCCT"
640 [(set (reg 33)
641 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
642 (match_operand:QI 1 "const0_operand" "")))
643 (set (match_operand:QI 2 "register_operand" "=d,0")
644 (match_dup 0))]
645 "s390_match_ccmode(insn, CCTmode)"
646 "@
647 icm\\t%2,1,%0
648 tml\\t%0,255"
649 [(set_attr "op_type" "RS,RI")])
650
651 (define_insn "*tstqiCCT_cconly"
652 [(set (reg 33)
653 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
654 (match_operand:QI 1 "const0_operand" "")))]
655 "s390_match_ccmode(insn, CCTmode)"
656 "@
657 cli\\t%0,0
658 tml\\t%0,255"
659 [(set_attr "op_type" "SI,RI")])
660
661 (define_insn "*tstqi"
662 [(set (reg 33)
663 (compare (match_operand:QI 0 "s_operand" "Q")
664 (match_operand:QI 1 "const0_operand" "")))
665 (set (match_operand:QI 2 "register_operand" "=d")
666 (match_dup 0))]
667 "s390_match_ccmode(insn, CCSmode)"
668 "icm\\t%2,1,%0"
669 [(set_attr "op_type" "RS")])
670
671 (define_insn "*tstqi_cconly"
672 [(set (reg 33)
673 (compare (match_operand:QI 0 "s_operand" "Q")
674 (match_operand:QI 1 "const0_operand" "")))
675 (clobber (match_scratch:QI 2 "=d"))]
676 "s390_match_ccmode(insn, CCSmode)"
677 "icm\\t%2,1,%0"
678 [(set_attr "op_type" "RS")])
679
680 ; Compare (signed) instructions
681
682 (define_insn "*cmpdi_ccs_sign"
683 [(set (reg 33)
684 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
685 (match_operand:DI 0 "register_operand" "d,d")))]
686 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
687 "@
688 cgfr\\t%0,%1
689 cgf\\t%0,%1"
690 [(set_attr "op_type" "RRE,RXE")])
691
692 (define_insn "*cmpdi_ccs"
693 [(set (reg 33)
694 (compare (match_operand:DI 0 "register_operand" "d,d,d")
695 (match_operand:DI 1 "general_operand" "d,K,m")))]
696 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
697 "@
698 cgr\\t%0,%1
699 cghi\\t%0,%c1
700 cg\\t%0,%1"
701 [(set_attr "op_type" "RRE,RI,RXE")])
702
703 (define_insn "*cmpsi_ccs_sign"
704 [(set (reg 33)
705 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
706 (match_operand:SI 0 "register_operand" "d")))]
707 "s390_match_ccmode(insn, CCSRmode)"
708 "ch\\t%0,%1"
709 [(set_attr "op_type" "RX")])
710
711 (define_insn "*cmpsi_ccs"
712 [(set (reg 33)
713 (compare (match_operand:SI 0 "register_operand" "d,d,d")
714 (match_operand:SI 1 "general_operand" "d,K,m")))]
715 "s390_match_ccmode(insn, CCSmode)"
716 "@
717 cr\\t%0,%1
718 chi\\t%0,%c1
719 c\\t%0,%1"
720 [(set_attr "op_type" "RR,RI,RX")])
721
722
723 ; Compare (unsigned) instructions
724
725 (define_insn "*cmpdi_ccu_zero"
726 [(set (reg 33)
727 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
728 (match_operand:DI 0 "register_operand" "d,d")))]
729 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
730 "@
731 clgfr\\t%0,%1
732 clgf\\t%0,%1"
733 [(set_attr "op_type" "RRE,RXE")])
734
735 (define_insn "*cmpdi_ccu"
736 [(set (reg 33)
737 (compare (match_operand:DI 0 "register_operand" "d,d")
738 (match_operand:DI 1 "general_operand" "d,m")))]
739 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
740 "@
741 clgr\\t%0,%1
742 clg\\t%0,%1"
743 [(set_attr "op_type" "RRE,RXE")])
744
745 (define_insn "*cmpsi_ccu"
746 [(set (reg 33)
747 (compare (match_operand:SI 0 "register_operand" "d,d")
748 (match_operand:SI 1 "general_operand" "d,m")))]
749 "s390_match_ccmode(insn, CCUmode)"
750 "@
751 clr\\t%0,%1
752 cl\\t%0,%1"
753 [(set_attr "op_type" "RR,RX")])
754
755 (define_insn "*cmphi_ccu"
756 [(set (reg 33)
757 (compare (match_operand:HI 0 "register_operand" "d")
758 (match_operand:HI 1 "s_imm_operand" "Q")))]
759 "s390_match_ccmode(insn, CCUmode)"
760 "clm\\t%0,3,%1"
761 [(set_attr "op_type" "RS")])
762
763 (define_insn "*cmpqi_ccu"
764 [(set (reg 33)
765 (compare (match_operand:QI 0 "register_operand" "d")
766 (match_operand:QI 1 "s_imm_operand" "Q")))]
767 "s390_match_ccmode(insn, CCUmode)"
768 "clm\\t%0,1,%1"
769 [(set_attr "op_type" "RS")])
770
771 (define_insn "*cli"
772 [(set (reg 33)
773 (compare (match_operand:QI 0 "memory_operand" "Q")
774 (match_operand:QI 1 "immediate_operand" "n")))]
775 "s390_match_ccmode (insn, CCUmode)"
776 "cli\\t%0,%b1"
777 [(set_attr "op_type" "SI")])
778
779 (define_insn "*cmpdi_ccu_mem"
780 [(set (reg 33)
781 (compare (match_operand:DI 0 "s_operand" "Q")
782 (match_operand:DI 1 "s_imm_operand" "Q")))]
783 "s390_match_ccmode(insn, CCUmode)"
784 "clc\\t%O0(8,%R0),%1"
785 [(set_attr "op_type" "SS")])
786
787 (define_insn "*cmpsi_ccu_mem"
788 [(set (reg 33)
789 (compare (match_operand:SI 0 "s_operand" "Q")
790 (match_operand:SI 1 "s_imm_operand" "Q")))]
791 "s390_match_ccmode(insn, CCUmode)"
792 "clc\\t%O0(4,%R0),%1"
793 [(set_attr "op_type" "SS")])
794
795 (define_insn "*cmphi_ccu_mem"
796 [(set (reg 33)
797 (compare (match_operand:HI 0 "s_operand" "Q")
798 (match_operand:HI 1 "s_imm_operand" "Q")))]
799 "s390_match_ccmode(insn, CCUmode)"
800 "clc\\t%O0(2,%R0),%1"
801 [(set_attr "op_type" "SS")])
802
803 (define_insn "*cmpqi_ccu_mem"
804 [(set (reg 33)
805 (compare (match_operand:QI 0 "s_operand" "Q")
806 (match_operand:QI 1 "s_imm_operand" "Q")))]
807 "s390_match_ccmode(insn, CCUmode)"
808 "clc\\t%O0(1,%R0),%1"
809 [(set_attr "op_type" "SS")])
810
811
812 ; DF instructions
813
814 (define_insn "*cmpdf_ccs_0"
815 [(set (reg 33)
816 (compare (match_operand:DF 0 "register_operand" "f")
817 (match_operand:DF 1 "const0_operand" "")))]
818 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
819 "ltdbr\\t%0,%0"
820 [(set_attr "op_type" "RRE")
821 (set_attr "type" "fsimpd")])
822
823 (define_insn "*cmpdf_ccs_0_ibm"
824 [(set (reg 33)
825 (compare (match_operand:DF 0 "register_operand" "f")
826 (match_operand:DF 1 "const0_operand" "")))]
827 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
828 "ltdr\\t%0,%0"
829 [(set_attr "op_type" "RR")
830 (set_attr "type" "fsimpd")])
831
832 (define_insn "*cmpdf_ccs"
833 [(set (reg 33)
834 (compare (match_operand:DF 0 "register_operand" "f,f")
835 (match_operand:DF 1 "general_operand" "f,m")))]
836 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
837 "@
838 cdbr\\t%0,%1
839 cdb\\t%0,%1"
840 [(set_attr "op_type" "RRE,RXE")
841 (set_attr "type" "fsimpd")])
842
843 (define_insn "*cmpdf_ccs_ibm"
844 [(set (reg 33)
845 (compare (match_operand:DF 0 "register_operand" "f,f")
846 (match_operand:DF 1 "general_operand" "f,m")))]
847 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
848 "@
849 cdr\\t%0,%1
850 cd\\t%0,%1"
851 [(set_attr "op_type" "RR,RX")
852 (set_attr "type" "fsimpd")])
853
854
855 ; SF instructions
856
857 (define_insn "*cmpsf_ccs_0"
858 [(set (reg 33)
859 (compare (match_operand:SF 0 "register_operand" "f")
860 (match_operand:SF 1 "const0_operand" "")))]
861 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
862 "ltebr\\t%0,%0"
863 [(set_attr "op_type" "RRE")
864 (set_attr "type" "fsimps")])
865
866 (define_insn "*cmpsf_ccs_0_ibm"
867 [(set (reg 33)
868 (compare (match_operand:SF 0 "register_operand" "f")
869 (match_operand:SF 1 "const0_operand" "")))]
870 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
871 "lter\\t%0,%0"
872 [(set_attr "op_type" "RR")
873 (set_attr "type" "fsimps")])
874
875 (define_insn "*cmpsf_ccs"
876 [(set (reg 33)
877 (compare (match_operand:SF 0 "register_operand" "f,f")
878 (match_operand:SF 1 "general_operand" "f,m")))]
879 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
880 "@
881 cebr\\t%0,%1
882 ceb\\t%0,%1"
883 [(set_attr "op_type" "RRE,RXE")
884 (set_attr "type" "fsimps")])
885
886 (define_insn "*cmpsf_ccs"
887 [(set (reg 33)
888 (compare (match_operand:SF 0 "register_operand" "f,f")
889 (match_operand:SF 1 "general_operand" "f,m")))]
890 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
891 "@
892 cer\\t%0,%1
893 ce\\t%0,%1"
894 [(set_attr "op_type" "RR,RX")
895 (set_attr "type" "fsimps")])
896
897
898 ;;
899 ;;- Move instructions.
900 ;;
901
902 ;
903 ; movti instruction pattern(s).
904 ;
905
906 (define_insn "movti"
907 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,o,Q")
908 (match_operand:TI 1 "general_operand" "Q,d,dKo,d,Q"))]
909 "TARGET_64BIT"
910 "@
911 lmg\\t%0,%N0,%1
912 stmg\\t%1,%N1,%0
913 #
914 #
915 mvc\\t%O0(16,%R0),%1"
916 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
917 (set_attr "type" "lm,stm,*,*,cs")])
918
919 (define_split
920 [(set (match_operand:TI 0 "nonimmediate_operand" "")
921 (match_operand:TI 1 "general_operand" ""))]
922 "TARGET_64BIT && reload_completed
923 && !s_operand (operands[0], VOIDmode)
924 && !s_operand (operands[1], VOIDmode)
925 && (register_operand (operands[0], VOIDmode)
926 || register_operand (operands[1], VOIDmode))
927 && (!register_operand (operands[0], VOIDmode)
928 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
929 operands[1])
930 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
931 operands[1]))"
932 [(set (match_dup 2) (match_dup 4))
933 (set (match_dup 3) (match_dup 5))]
934 "
935 {
936 if (!register_operand (operands[0], VOIDmode)
937 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
938 operands[1]))
939 {
940 operands[2] = operand_subword (operands[0], 0, 0, TImode);
941 operands[3] = operand_subword (operands[0], 1, 0, TImode);
942 operands[4] = operand_subword (operands[1], 0, 0, TImode);
943 operands[5] = operand_subword (operands[1], 1, 0, TImode);
944 }
945 else
946 {
947 operands[2] = operand_subword (operands[0], 1, 0, TImode);
948 operands[3] = operand_subword (operands[0], 0, 0, TImode);
949 operands[4] = operand_subword (operands[1], 1, 0, TImode);
950 operands[5] = operand_subword (operands[1], 0, 0, TImode);
951 }
952 }")
953
954 (define_split
955 [(set (match_operand:TI 0 "register_operand" "")
956 (match_operand:TI 1 "memory_operand" ""))]
957 "TARGET_64BIT && reload_completed
958 && !s_operand (operands[1], VOIDmode)"
959 [(set (match_dup 0) (match_dup 1))]
960 "
961 {
962 rtx addr = operand_subword (operands[0], 1, 0, TImode);
963 s390_load_address (addr, XEXP (operands[1], 0));
964 operands[1] = replace_equiv_address (operands[1], addr);
965 }")
966
967 ;
968 ; movdi instruction pattern(s).
969 ;
970
971 (define_expand "movdi"
972 [(set (match_operand:DI 0 "general_operand" "")
973 (match_operand:DI 1 "general_operand" ""))]
974 ""
975 "
976 {
977 /* Handle symbolic constants. */
978 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
979 emit_symbolic_move (operands);
980
981 /* During and after reload, we need to force constants
982 to the literal pool ourselves, if necessary. */
983 if ((reload_in_progress || reload_completed)
984 && CONSTANT_P (operands[1])
985 && (!legitimate_reload_constant_p (operands[1])
986 || FP_REG_P (operands[0])))
987 operands[1] = force_const_mem (DImode, operands[1]);
988 }")
989
990 (define_insn "*movdi_lhi"
991 [(set (match_operand:DI 0 "register_operand" "=d")
992 (match_operand:DI 1 "immediate_operand" "K"))]
993 "TARGET_64BIT
994 && GET_CODE (operands[1]) == CONST_INT
995 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
996 && !FP_REG_P (operands[0])"
997 "lghi\\t%0,%h1"
998 [(set_attr "op_type" "RI")])
999
1000 (define_insn "*movdi_lli"
1001 [(set (match_operand:DI 0 "register_operand" "=d")
1002 (match_operand:DI 1 "immediate_operand" "n"))]
1003 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
1004 && !FP_REG_P (operands[0])"
1005 "*
1006 {
1007 int part = s390_single_hi (operands[1], DImode, 0);
1008 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
1009
1010 switch (part)
1011 {
1012 case 0: return \"llihh\\t%0,%x1\";
1013 case 1: return \"llihl\\t%0,%x1\";
1014 case 2: return \"llilh\\t%0,%x1\";
1015 case 3: return \"llill\\t%0,%x1\";
1016 default: abort ();
1017 }
1018 }"
1019 [(set_attr "op_type" "RI")])
1020
1021 (define_insn "*movdi_larl"
1022 [(set (match_operand:DI 0 "register_operand" "=d")
1023 (match_operand:DI 1 "larl_operand" "X"))]
1024 "TARGET_64BIT
1025 && !FP_REG_P (operands[0])"
1026 "larl\\t%0,%1"
1027 [(set_attr "op_type" "RIL")
1028 (set_attr "type" "larl")])
1029
1030 (define_insn "*movdi_64"
1031 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
1032 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
1033 "TARGET_64BIT"
1034 "@
1035 lgr\\t%0,%1
1036 lg\\t%0,%1
1037 stg\\t%1,%0
1038 ldr\\t%0,%1
1039 ld\\t%0,%1
1040 std\\t%1,%0
1041 mvc\\t%O0(8,%R0),%1"
1042 [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
1043 (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")])
1044
1045 (define_insn "*movdi_31"
1046 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!m,Q")
1047 (match_operand:DI 1 "general_operand" "Q,d,dKo,d,*f,m,*f,Q"))]
1048 "!TARGET_64BIT"
1049 "@
1050 lm\\t%0,%N0,%1
1051 stm\\t%1,%N1,%0
1052 #
1053 #
1054 ldr\\t%0,%1
1055 ld\\t%0,%1
1056 std\\t%1,%0
1057 mvc\\t%O0(8,%R0),%1"
1058 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
1059 (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")])
1060
1061 (define_split
1062 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1063 (match_operand:DI 1 "general_operand" ""))]
1064 "!TARGET_64BIT && reload_completed
1065 && !FP_REG_P (operands[0])
1066 && !FP_REG_P (operands[1])
1067 && !s_operand (operands[0], VOIDmode)
1068 && !s_operand (operands[1], VOIDmode)
1069 && (register_operand (operands[0], VOIDmode)
1070 || register_operand (operands[1], VOIDmode))
1071 && (!register_operand (operands[0], VOIDmode)
1072 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1073 operands[1])
1074 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
1075 operands[1]))"
1076 [(set (match_dup 2) (match_dup 4))
1077 (set (match_dup 3) (match_dup 5))]
1078 "
1079 {
1080 if (!register_operand (operands[0], VOIDmode)
1081 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1082 operands[1]))
1083 {
1084 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1085 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1086 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1087 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1088 }
1089 else
1090 {
1091 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1092 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1093 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1094 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1095 }
1096 }")
1097
1098 (define_split
1099 [(set (match_operand:DI 0 "register_operand" "")
1100 (match_operand:DI 1 "memory_operand" ""))]
1101 "!TARGET_64BIT && reload_completed
1102 && !FP_REG_P (operands[0])
1103 && !FP_REG_P (operands[1])
1104 && !s_operand (operands[1], VOIDmode)"
1105 [(set (match_dup 0) (match_dup 1))]
1106 "
1107 {
1108 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1109 s390_load_address (addr, XEXP (operands[1], 0));
1110 operands[1] = replace_equiv_address (operands[1], addr);
1111 }")
1112
1113 (define_peephole2
1114 [(set (match_operand:DI 0 "register_operand" "")
1115 (mem:DI (match_operand 1 "address_operand" "")))]
1116 "TARGET_64BIT
1117 && !FP_REG_P (operands[0])
1118 && GET_CODE (operands[1]) == SYMBOL_REF
1119 && CONSTANT_POOL_ADDRESS_P (operands[1])
1120 && get_pool_mode (operands[1]) == DImode
1121 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1122 [(set (match_dup 0) (match_dup 2))]
1123 "operands[2] = get_pool_constant (operands[1]);")
1124
1125 ;
1126 ; movsi instruction pattern(s).
1127 ;
1128
1129 (define_expand "movsi"
1130 [(set (match_operand:SI 0 "general_operand" "")
1131 (match_operand:SI 1 "general_operand" ""))]
1132 ""
1133 "
1134 {
1135 /* Handle symbolic constants. */
1136 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1137 emit_symbolic_move (operands);
1138
1139 /* expr.c tries to load an effective address using
1140 force_reg. This fails because we don't have a
1141 generic load_address pattern. Convert the move
1142 to a proper arithmetic operation instead, unless
1143 it is guaranteed to be OK. */
1144 if (GET_CODE (operands[1]) == PLUS
1145 && !legitimate_la_operand_p (operands[1]))
1146 {
1147 operands[1] = force_operand (operands[1], operands[0]);
1148 if (operands[1] == operands[0])
1149 DONE;
1150 }
1151
1152 /* During and after reload, we need to force constants
1153 to the literal pool ourselves, if necessary. */
1154 if ((reload_in_progress || reload_completed)
1155 && CONSTANT_P (operands[1])
1156 && (!legitimate_reload_constant_p (operands[1])
1157 || FP_REG_P (operands[0])))
1158 operands[1] = force_const_mem (SImode, operands[1]);
1159 }")
1160
1161 (define_insn "*movsi_lhi"
1162 [(set (match_operand:SI 0 "register_operand" "=d")
1163 (match_operand:SI 1 "immediate_operand" "K"))]
1164 "GET_CODE (operands[1]) == CONST_INT
1165 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1166 && !FP_REG_P (operands[0])"
1167 "lhi\\t%0,%h1"
1168 [(set_attr "op_type" "RI")])
1169
1170 (define_insn "*movsi_lli"
1171 [(set (match_operand:SI 0 "register_operand" "=d")
1172 (match_operand:SI 1 "immediate_operand" "n"))]
1173 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1174 && !FP_REG_P (operands[0])"
1175 "*
1176 {
1177 int part = s390_single_hi (operands[1], SImode, 0);
1178 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1179
1180 switch (part)
1181 {
1182 case 0: return \"llilh\\t%0,%x1\";
1183 case 1: return \"llill\\t%0,%x1\";
1184 default: abort ();
1185 }
1186 }"
1187 [(set_attr "op_type" "RI")])
1188
1189 (define_insn "*movsi"
1190 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
1191 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
1192 ""
1193 "@
1194 lr\\t%0,%1
1195 l\\t%0,%1
1196 st\\t%1,%0
1197 ler\\t%0,%1
1198 le\\t%0,%1
1199 ste\\t%1,%0
1200 mvc\\t%O0(4,%R0),%1"
1201 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1202 (set_attr "type" "lr,load,store,floads,floads,fstores,cs")])
1203
1204 (define_peephole2
1205 [(set (match_operand:SI 0 "register_operand" "")
1206 (mem:SI (match_operand 1 "address_operand" "")))]
1207 "!FP_REG_P (operands[0])
1208 && GET_CODE (operands[1]) == SYMBOL_REF
1209 && CONSTANT_POOL_ADDRESS_P (operands[1])
1210 && get_pool_mode (operands[1]) == SImode
1211 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1212 [(set (match_dup 0) (match_dup 2))]
1213 "operands[2] = get_pool_constant (operands[1]);")
1214
1215 ;
1216 ; movhi instruction pattern(s).
1217 ;
1218
1219 (define_insn "movhi"
1220 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,?Q")
1221 (match_operand:HI 1 "general_operand" "d,n,m,d,?Q"))]
1222 ""
1223 "@
1224 lr\\t%0,%1
1225 lhi\\t%0,%h1
1226 lh\\t%0,%1
1227 sth\\t%1,%0
1228 mvc\\t%O0(2,%R0),%1"
1229 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1230 (set_attr "type" "lr,*,*,store,cs")])
1231
1232 (define_peephole2
1233 [(set (match_operand:HI 0 "register_operand" "")
1234 (mem:HI (match_operand 1 "address_operand" "")))]
1235 "GET_CODE (operands[1]) == SYMBOL_REF
1236 && CONSTANT_POOL_ADDRESS_P (operands[1])
1237 && get_pool_mode (operands[1]) == HImode
1238 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1239 [(set (match_dup 0) (match_dup 2))]
1240 "operands[2] = get_pool_constant (operands[1]);")
1241
1242 ;
1243 ; movqi instruction pattern(s).
1244 ;
1245
1246 (define_insn "movqi_64"
1247 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
1248 (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
1249 "TARGET_64BIT"
1250 "@
1251 lr\\t%0,%1
1252 lhi\\t%0,%b1
1253 llgc\\t%0,%1
1254 stc\\t%1,%0
1255 mvi\\t%0,%b1
1256 mvc\\t%O0(1,%R0),%1"
1257 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1258 (set_attr "type" "lr,*,*,store,store,cs")])
1259
1260 (define_insn "movqi"
1261 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
1262 (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
1263 ""
1264 "@
1265 lr\\t%0,%1
1266 lhi\\t%0,%b1
1267 ic\\t%0,%1
1268 stc\\t%1,%0
1269 mvi\\t%0,%b1
1270 mvc\\t%O0(1,%R0),%1"
1271 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1272 (set_attr "type" "lr,*,*,store,store,cs")])
1273
1274 (define_peephole2
1275 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1276 (mem:QI (match_operand 1 "address_operand" "")))]
1277 "GET_CODE (operands[1]) == SYMBOL_REF
1278 && CONSTANT_POOL_ADDRESS_P (operands[1])
1279 && get_pool_mode (operands[1]) == QImode
1280 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1281 [(set (match_dup 0) (match_dup 2))]
1282 "operands[2] = get_pool_constant (operands[1]);")
1283
1284 ;
1285 ; movstrictqi instruction pattern(s).
1286 ;
1287
1288 (define_insn "*movstrictqi"
1289 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1290 (match_operand:QI 1 "memory_operand" "m"))]
1291 ""
1292 "ic\\t%0,%1"
1293 [(set_attr "op_type" "RX")])
1294
1295 ;
1296 ; movstricthi instruction pattern(s).
1297 ;
1298
1299 (define_insn "*movstricthi"
1300 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1301 (match_operand:HI 1 "s_imm_operand" "Q"))
1302 (clobber (reg:CC 33))]
1303 ""
1304 "icm\\t%0,3,%1"
1305 [(set_attr "op_type" "RS")])
1306
1307
1308 ;
1309 ; movstrictsi instruction pattern(s).
1310 ;
1311
1312 (define_insn "movstrictsi"
1313 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1314 (match_operand:SI 1 "general_operand" "d,m"))]
1315 "TARGET_64BIT"
1316 "@
1317 lr\\t%0,%1
1318 l\\t%0,%1"
1319 [(set_attr "op_type" "RR,RS")
1320 (set_attr "type" "lr,load")])
1321
1322
1323 ;
1324 ; movdf instruction pattern(s).
1325 ;
1326
1327 (define_expand "movdf"
1328 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1329 (match_operand:DF 1 "general_operand" ""))]
1330 ""
1331 "
1332 {
1333 /* During and after reload, we need to force constants
1334 to the literal pool ourselves, if necessary. */
1335 if ((reload_in_progress || reload_completed)
1336 && CONSTANT_P (operands[1]))
1337 operands[1] = force_const_mem (DFmode, operands[1]);
1338 }")
1339
1340 (define_insn "*movdf_64"
1341 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
1342 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
1343 "TARGET_64BIT"
1344 "@
1345 ldr\\t%0,%1
1346 ld\\t%0,%1
1347 std\\t%1,%0
1348 lgr\\t%0,%1
1349 lg\\t%0,%1
1350 stg\\t%1,%0
1351 mvc\\t%O0(8,%R0),%1"
1352 [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
1353 (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")])
1354
1355 (define_insn "*movdf_31"
1356 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,o,Q")
1357 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKo,d,Q"))]
1358 "!TARGET_64BIT"
1359 "@
1360 ldr\\t%0,%1
1361 ld\\t%0,%1
1362 std\\t%1,%0
1363 lm\\t%0,%N0,%1
1364 stm\\t%1,%N1,%0
1365 #
1366 #
1367 mvc\\t%O0(8,%R0),%1"
1368 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1369 (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")])
1370
1371 (define_split
1372 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1373 (match_operand:DF 1 "general_operand" ""))]
1374 "!TARGET_64BIT && reload_completed
1375 && !FP_REG_P (operands[0])
1376 && !FP_REG_P (operands[1])
1377 && !s_operand (operands[0], VOIDmode)
1378 && !s_operand (operands[1], VOIDmode)
1379 && (register_operand (operands[0], VOIDmode)
1380 || register_operand (operands[1], VOIDmode))
1381 && (!register_operand (operands[0], VOIDmode)
1382 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1383 operands[1])
1384 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1385 operands[1]))"
1386 [(set (match_dup 2) (match_dup 4))
1387 (set (match_dup 3) (match_dup 5))]
1388 "
1389 {
1390 if (!register_operand (operands[0], VOIDmode)
1391 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1392 operands[1]))
1393 {
1394 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1395 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1396 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1397 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1398 }
1399 else
1400 {
1401 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1402 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1403 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1404 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1405 }
1406 }")
1407
1408 (define_split
1409 [(set (match_operand:DF 0 "register_operand" "")
1410 (match_operand:DF 1 "memory_operand" ""))]
1411 "!TARGET_64BIT && reload_completed
1412 && !FP_REG_P (operands[0])
1413 && !FP_REG_P (operands[1])
1414 && !s_operand (operands[1], VOIDmode)"
1415 [(set (match_dup 0) (match_dup 1))]
1416 "
1417 {
1418 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1419 s390_load_address (addr, XEXP (operands[1], 0));
1420 operands[1] = replace_equiv_address (operands[1], addr);
1421 }")
1422
1423 ;
1424 ; movsf instruction pattern(s).
1425 ;
1426
1427 (define_expand "movsf"
1428 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1429 (match_operand:SF 1 "general_operand" ""))]
1430 ""
1431 "
1432 {
1433 /* During and after reload, we need to force constants
1434 to the literal pool ourselves, if necessary. */
1435 if ((reload_in_progress || reload_completed)
1436 && CONSTANT_P (operands[1]))
1437 operands[1] = force_const_mem (SFmode, operands[1]);
1438 }")
1439
1440 (define_insn "*movsf"
1441 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
1442 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
1443 ""
1444 "@
1445 ler\\t%0,%1
1446 le\\t%0,%1
1447 ste\\t%1,%0
1448 lr\\t%0,%1
1449 l\\t%0,%1
1450 st\\t%1,%0
1451 mvc\\t%O0(4,%R0),%1"
1452 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1453 (set_attr "type" "floads,floads,fstores,lr,load,store,cs")])
1454
1455 ;
1456 ; load_multiple pattern(s).
1457 ;
1458
1459 (define_expand "load_multiple"
1460 [(match_par_dup 3 [(set (match_operand 0 "" "")
1461 (match_operand 1 "" ""))
1462 (use (match_operand 2 "" ""))])]
1463 ""
1464 "
1465 {
1466 int regno;
1467 int count;
1468 rtx from;
1469 int i, off;
1470
1471 /* Support only loading a constant number of fixed-point registers from
1472 memory and only bother with this if more than two */
1473 if (GET_CODE (operands[2]) != CONST_INT
1474 || INTVAL (operands[2]) < 2
1475 || INTVAL (operands[2]) > 16
1476 || GET_CODE (operands[1]) != MEM
1477 || GET_CODE (operands[0]) != REG
1478 || REGNO (operands[0]) >= 16)
1479 FAIL;
1480
1481 count = INTVAL (operands[2]);
1482 regno = REGNO (operands[0]);
1483
1484 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1485 if (no_new_pseudos)
1486 {
1487 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1488 {
1489 from = XEXP (operands[1], 0);
1490 off = 0;
1491 }
1492 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1493 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1494 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1495 {
1496 from = XEXP (XEXP (operands[1], 0), 0);
1497 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1498 }
1499 else
1500 FAIL;
1501
1502 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1503 FAIL;
1504 }
1505 else
1506 {
1507 from = force_reg (Pmode, XEXP (operands[1], 0));
1508 off = 0;
1509 }
1510
1511 for (i = 0; i < count; i++)
1512 XVECEXP (operands[3], 0, i)
1513 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1514 change_address (operands[1], Pmode,
1515 plus_constant (from,
1516 off + i * UNITS_PER_WORD)));
1517 }")
1518
1519 (define_insn "*load_multiple_di"
1520 [(match_parallel 0 "load_multiple_operation"
1521 [(set (match_operand:DI 1 "register_operand" "=r")
1522 (match_operand:DI 2 "s_operand" "Q"))])]
1523 ""
1524 "*
1525 {
1526 int words = XVECLEN (operands[0], 0);
1527
1528 if (XVECLEN (operands[0], 0) == 1)
1529 return \"lg\\t%1,0(%2)\";
1530
1531 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1532 return \"lmg\\t%1,%0,%2\";
1533 }"
1534 [(set_attr "op_type" "RXE")
1535 (set_attr "type" "lm")])
1536
1537 (define_insn "*load_multiple_si"
1538 [(match_parallel 0 "load_multiple_operation"
1539 [(set (match_operand:SI 1 "register_operand" "=r")
1540 (match_operand:SI 2 "s_operand" "Q"))])]
1541 ""
1542 "*
1543 {
1544 int words = XVECLEN (operands[0], 0);
1545
1546 if (XVECLEN (operands[0], 0) == 1)
1547 return \"l\\t%1,0(%2)\";
1548
1549 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1550 return \"lm\\t%1,%0,%2\";
1551 }"
1552 [(set_attr "op_type" "RXE")
1553 (set_attr "type" "lm")])
1554
1555 ;
1556 ; store multiple pattern(s).
1557 ;
1558
1559 (define_expand "store_multiple"
1560 [(match_par_dup 3 [(set (match_operand 0 "" "")
1561 (match_operand 1 "" ""))
1562 (use (match_operand 2 "" ""))])]
1563 ""
1564 "
1565 {
1566 int regno;
1567 int count;
1568 rtx to;
1569 int i, off;
1570
1571 /* Support only storing a constant number of fixed-point registers to
1572 memory and only bother with this if more than two. */
1573 if (GET_CODE (operands[2]) != CONST_INT
1574 || INTVAL (operands[2]) < 2
1575 || INTVAL (operands[2]) > 16
1576 || GET_CODE (operands[0]) != MEM
1577 || GET_CODE (operands[1]) != REG
1578 || REGNO (operands[1]) >= 16)
1579 FAIL;
1580
1581 count = INTVAL (operands[2]);
1582 regno = REGNO (operands[1]);
1583
1584 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1585
1586 if (no_new_pseudos)
1587 {
1588 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1589 {
1590 to = XEXP (operands[0], 0);
1591 off = 0;
1592 }
1593 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1594 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1595 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1596 {
1597 to = XEXP (XEXP (operands[0], 0), 0);
1598 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1599 }
1600 else
1601 FAIL;
1602
1603 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1604 FAIL;
1605 }
1606 else
1607 {
1608 to = force_reg (Pmode, XEXP (operands[0], 0));
1609 off = 0;
1610 }
1611
1612 for (i = 0; i < count; i++)
1613 XVECEXP (operands[3], 0, i)
1614 = gen_rtx_SET (VOIDmode,
1615 change_address (operands[0], Pmode,
1616 plus_constant (to,
1617 off + i * UNITS_PER_WORD)),
1618 gen_rtx_REG (Pmode, regno + i));
1619 }")
1620
1621 (define_insn "*store_multiple_di"
1622 [(match_parallel 0 "store_multiple_operation"
1623 [(set (match_operand:DI 1 "s_operand" "=Q")
1624 (match_operand:DI 2 "register_operand" "r"))])]
1625 ""
1626 "*
1627 {
1628 int words = XVECLEN (operands[0], 0);
1629
1630 if (XVECLEN (operands[0], 0) == 1)
1631 return \"stg\\t%1,0(%2)\";
1632
1633 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1634 return \"stmg\\t%2,%0,%1\";
1635 }"
1636 [(set_attr "op_type" "RXE")
1637 (set_attr "type" "stm")])
1638
1639
1640 (define_insn "*store_multiple_si"
1641 [(match_parallel 0 "store_multiple_operation"
1642 [(set (match_operand:SI 1 "s_operand" "=Q")
1643 (match_operand:SI 2 "register_operand" "r"))])]
1644 ""
1645 "*
1646 {
1647 int words = XVECLEN (operands[0], 0);
1648
1649 if (XVECLEN (operands[0], 0) == 1)
1650 return \"st\\t%1,0(%2)\";
1651
1652 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1653 return \"stm\\t%2,%0,%1\";
1654 }"
1655 [(set_attr "op_type" "RXE")
1656 (set_attr "type" "stm")])
1657
1658 ;;
1659 ;; String instructions.
1660 ;;
1661
1662 ;
1663 ; movstrM instruction pattern(s).
1664 ;
1665
1666 (define_expand "movstrdi"
1667 [(set (match_operand:BLK 0 "memory_operand" "")
1668 (match_operand:BLK 1 "memory_operand" ""))
1669 (use (match_operand:DI 2 "general_operand" ""))
1670 (match_operand 3 "" "")]
1671 "TARGET_64BIT"
1672 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1673
1674 (define_expand "movstrsi"
1675 [(set (match_operand:BLK 0 "memory_operand" "")
1676 (match_operand:BLK 1 "memory_operand" ""))
1677 (use (match_operand:SI 2 "general_operand" ""))
1678 (match_operand 3 "" "")]
1679 ""
1680 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1681
1682 ; Move a block that is up to 256 bytes in length.
1683 ; The block length is taken as (operands[2] % 256) + 1.
1684
1685 (define_insn "movstr_short_64"
1686 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1687 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1688 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1689 (clobber (match_scratch:DI 3 "=X,&a"))]
1690 "TARGET_64BIT"
1691 "*
1692 {
1693 switch (which_alternative)
1694 {
1695 case 0:
1696 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1697
1698 case 1:
1699 output_asm_insn (\"bras\\t%3,.+10\", operands);
1700 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1701 return \"ex\\t%2,0(%3)\";
1702
1703 default:
1704 abort ();
1705 }
1706 }"
1707 [(set_attr "op_type" "SS,NN")
1708 (set_attr "type" "cs,cs")
1709 (set_attr "atype" "*,agen")
1710 (set_attr "length" "*,14")])
1711
1712 (define_insn "movstr_short_31"
1713 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1714 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1715 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1716 (clobber (match_scratch:SI 3 "=X,&a"))]
1717 "!TARGET_64BIT"
1718 "*
1719 {
1720 switch (which_alternative)
1721 {
1722 case 0:
1723 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1724
1725 case 1:
1726 output_asm_insn (\"bras\\t%3,.+10\", operands);
1727 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1728 return \"ex\\t%2,0(%3)\";
1729
1730 default:
1731 abort ();
1732 }
1733 }"
1734 [(set_attr "op_type" "SS,NN")
1735 (set_attr "type" "cs,cs")
1736 (set_attr "atype" "*,agen")
1737 (set_attr "length" "*,14")])
1738
1739 ; Move a block of arbitrary length.
1740
1741 (define_insn "movstr_long_64"
1742 [(set (match_operand:TI 0 "register_operand" "=d")
1743 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1744 (lshiftrt:TI (match_dup 2) (const_int 64)))
1745 (const_int 64)))
1746 (set (match_operand:TI 1 "register_operand" "=d")
1747 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1748 (lshiftrt:TI (match_dup 3) (const_int 64)))
1749 (const_int 64)))
1750 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1751 (mem:BLK (subreg:DI (match_dup 3) 0)))
1752 (clobber (reg:CC 33))]
1753 "TARGET_64BIT"
1754 "mvcle\\t%0,%1,0\;jo\\t.-4"
1755 [(set_attr "op_type" "NN")
1756 (set_attr "type" "vs")
1757 (set_attr "length" "8")])
1758
1759 (define_insn "movstr_long_31"
1760 [(set (match_operand:DI 0 "register_operand" "=d")
1761 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1762 (lshiftrt:DI (match_dup 2) (const_int 32)))
1763 (const_int 32)))
1764 (set (match_operand:DI 1 "register_operand" "=d")
1765 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1766 (lshiftrt:DI (match_dup 3) (const_int 32)))
1767 (const_int 32)))
1768 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1769 (mem:BLK (subreg:SI (match_dup 3) 0)))
1770 (clobber (reg:CC 33))]
1771 "!TARGET_64BIT"
1772 "mvcle\\t%0,%1,0\;jo\\t.-4"
1773 [(set_attr "op_type" "NN")
1774 (set_attr "type" "vs")
1775 (set_attr "length" "8")])
1776
1777 ;
1778 ; clrstrM instruction pattern(s).
1779 ;
1780
1781 (define_expand "clrstrdi"
1782 [(set (match_operand:BLK 0 "memory_operand" "")
1783 (const_int 0))
1784 (use (match_operand:DI 1 "general_operand" ""))
1785 (match_operand 2 "" "")]
1786 "TARGET_64BIT"
1787 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1788
1789 (define_expand "clrstrsi"
1790 [(set (match_operand:BLK 0 "memory_operand" "")
1791 (const_int 0))
1792 (use (match_operand:SI 1 "general_operand" ""))
1793 (match_operand 2 "" "")]
1794 ""
1795 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1796
1797 ; Clear a block that is up to 256 bytes in length.
1798 ; The block length is taken as (operands[2] % 256) + 1.
1799
1800 (define_insn "clrstr_short_64"
1801 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1802 (const_int 0))
1803 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1804 (clobber (match_scratch:DI 2 "=X,&a"))
1805 (clobber (reg:CC 33))]
1806 "TARGET_64BIT"
1807 "*
1808 {
1809 switch (which_alternative)
1810 {
1811 case 0:
1812 return \"xc\\t%O0(%b1+1,%R0),%0\";
1813
1814 case 1:
1815 output_asm_insn (\"bras\\t%2,.+10\", operands);
1816 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1817 return \"ex\\t%1,0(%2)\";
1818
1819 default:
1820 abort ();
1821 }
1822 }"
1823 [(set_attr "op_type" "SS,NN")
1824 (set_attr "type" "cs,cs")
1825 (set_attr "atype" "*,agen")
1826 (set_attr "length" "*,14")])
1827
1828 (define_insn "clrstr_short_31"
1829 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1830 (const_int 0))
1831 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1832 (clobber (match_scratch:SI 2 "=X,&a"))
1833 (clobber (reg:CC 33))]
1834 "!TARGET_64BIT"
1835 "*
1836 {
1837 switch (which_alternative)
1838 {
1839 case 0:
1840 return \"xc\\t%O0(%b1+1,%R0),%0\";
1841
1842 case 1:
1843 output_asm_insn (\"bras\\t%2,.+10\", operands);
1844 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1845 return \"ex\\t%1,0(%2)\";
1846
1847 default:
1848 abort ();
1849 }
1850 }"
1851 [(set_attr "op_type" "SS,NN")
1852 (set_attr "type" "cs,cs")
1853 (set_attr "atype" "*,agen")
1854 (set_attr "length" "*,14")])
1855
1856 ; Clear a block of arbitrary length.
1857
1858 (define_insn "clrstr_long_64"
1859 [(set (match_operand:TI 0 "register_operand" "=d")
1860 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1861 (lshiftrt:TI (match_dup 2) (const_int 64)))
1862 (const_int 64)))
1863 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1864 (const_int 0))
1865 (use (match_operand:TI 1 "register_operand" "d"))
1866 (clobber (reg:CC 33))]
1867 "TARGET_64BIT"
1868 "mvcle\\t%0,%1,0\;jo\\t.-4"
1869 [(set_attr "op_type" "NN")
1870 (set_attr "type" "vs")
1871 (set_attr "length" "8")])
1872
1873 (define_insn "clrstr_long_31"
1874 [(set (match_operand:DI 0 "register_operand" "=d")
1875 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1876 (lshiftrt:DI (match_dup 2) (const_int 32)))
1877 (const_int 32)))
1878 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1879 (const_int 0))
1880 (use (match_operand:DI 1 "register_operand" "d"))
1881 (clobber (reg:CC 33))]
1882 "!TARGET_64BIT"
1883 "mvcle\\t%0,%1,0\;jo\\t.-4"
1884 [(set_attr "op_type" "NN")
1885 (set_attr "type" "vs")
1886 (set_attr "length" "8")])
1887
1888 ;
1889 ; cmpstrM instruction pattern(s).
1890 ;
1891
1892 (define_expand "cmpstrdi"
1893 [(set (match_operand:DI 0 "register_operand" "")
1894 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1895 (match_operand:BLK 2 "memory_operand" "") ) )
1896 (use (match_operand:DI 3 "general_operand" ""))
1897 (use (match_operand:DI 4 "" ""))]
1898 "TARGET_64BIT"
1899 "s390_expand_cmpstr (operands[0], operands[1],
1900 operands[2], operands[3]); DONE;")
1901
1902 (define_expand "cmpstrsi"
1903 [(set (match_operand:SI 0 "register_operand" "")
1904 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1905 (match_operand:BLK 2 "memory_operand" "") ) )
1906 (use (match_operand:SI 3 "general_operand" ""))
1907 (use (match_operand:SI 4 "" ""))]
1908 ""
1909 "s390_expand_cmpstr (operands[0], operands[1],
1910 operands[2], operands[3]); DONE;")
1911
1912 ; Compare a block that is up to 256 bytes in length.
1913 ; The block length is taken as (operands[2] % 256) + 1.
1914
1915 (define_insn "cmpstr_short_64"
1916 [(set (reg:CCS 33)
1917 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1918 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1919 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1920 (clobber (match_scratch:DI 3 "=X,&a"))]
1921 "TARGET_64BIT"
1922 "*
1923 {
1924 switch (which_alternative)
1925 {
1926 case 0:
1927 return \"clc\\t%O0(%b2+1,%R0),%1\";
1928
1929 case 1:
1930 output_asm_insn (\"bras\\t%3,.+10\", operands);
1931 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1932 return \"ex\\t%2,0(%3)\";
1933
1934 default:
1935 abort ();
1936 }
1937 }"
1938 [(set_attr "op_type" "SS,NN")
1939 (set_attr "type" "cs,cs")
1940 (set_attr "atype" "*,agen")
1941 (set_attr "length" "*,14")])
1942
1943 (define_insn "cmpstr_short_31"
1944 [(set (reg:CCS 33)
1945 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1946 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1947 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1948 (clobber (match_scratch:SI 3 "=X,&a"))]
1949 "!TARGET_64BIT"
1950 "*
1951 {
1952 switch (which_alternative)
1953 {
1954 case 0:
1955 return \"clc\\t%O0(%b2+1,%R0),%1\";
1956
1957 case 1:
1958 output_asm_insn (\"bras\\t%3,.+10\", operands);
1959 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1960 return \"ex\\t%2,0(%3)\";
1961
1962 default:
1963 abort ();
1964 }
1965 }"
1966 [(set_attr "op_type" "SS,NN")
1967 (set_attr "type" "cs,cs")
1968 (set_attr "atype" "*,agen")
1969 (set_attr "length" "*,14")])
1970
1971 ; Compare a block of arbitrary length.
1972
1973 (define_insn "cmpstr_long_64"
1974 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1975 (clobber (match_operand:TI 1 "register_operand" "=d"))
1976 (set (reg:CCS 33)
1977 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1978 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1979 (use (match_dup 2))
1980 (use (match_dup 3))]
1981 "TARGET_64BIT"
1982 "clcl\\t%0,%1"
1983 [(set_attr "op_type" "RR")
1984 (set_attr "type" "vs")])
1985
1986 (define_insn "cmpstr_long_31"
1987 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1988 (clobber (match_operand:DI 1 "register_operand" "=d"))
1989 (set (reg:CCS 33)
1990 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1991 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1992 (use (match_dup 2))
1993 (use (match_dup 3))]
1994 "!TARGET_64BIT"
1995 "clcl\\t%0,%1"
1996 [(set_attr "op_type" "RR")
1997 (set_attr "type" "vs")])
1998
1999 ; Convert condition code to integer in range (-1, 0, 1)
2000
2001 (define_insn "cmpint_si"
2002 [(set (match_operand:SI 0 "register_operand" "=d")
2003 (compare:SI (reg:CCS 33) (const_int 0)))]
2004 ""
2005 "*
2006 {
2007 output_asm_insn (\"lhi\\t%0,1\", operands);
2008 output_asm_insn (\"jh\\t.+12\", operands);
2009 output_asm_insn (\"jl\\t.+6\", operands);
2010 output_asm_insn (\"sr\\t%0,%0\", operands);
2011 return \"lcr\\t%0,%0\";
2012 }"
2013 [(set_attr "op_type" "NN")
2014 (set_attr "length" "16")
2015 (set_attr "type" "other")])
2016
2017 (define_insn "cmpint_di"
2018 [(set (match_operand:DI 0 "register_operand" "=d")
2019 (compare:DI (reg:CCS 33) (const_int 0)))]
2020 "TARGET_64BIT"
2021 "*
2022 {
2023 output_asm_insn (\"lghi\\t%0,1\", operands);
2024 output_asm_insn (\"jh\\t.+12\", operands);
2025 output_asm_insn (\"jl\\t.+6\", operands);
2026 output_asm_insn (\"sgr\\t%0,%0\", operands);
2027 return \"lcgr\\t%0,%0\";
2028 }"
2029 [(set_attr "op_type" "NN")
2030 (set_attr "length" "22")
2031 (set_attr "type" "other")])
2032
2033
2034 ;;
2035 ;;- Conversion instructions.
2036 ;;
2037
2038 (define_insn "*sethighqisi"
2039 [(set (match_operand:SI 0 "register_operand" "=d")
2040 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
2041 (clobber (reg:CC 33))]
2042 ""
2043 "icm\\t%0,8,%1"
2044 [(set_attr "op_type" "RS")])
2045
2046 (define_insn "*sethighhisi"
2047 [(set (match_operand:SI 0 "register_operand" "=d")
2048 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
2049 (clobber (reg:CC 33))]
2050 ""
2051 "icm\\t%0,12,%1"
2052 [(set_attr "op_type" "RS")])
2053
2054 (define_insn "*sethighqidi_64"
2055 [(set (match_operand:DI 0 "register_operand" "=d")
2056 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2057 (clobber (reg:CC 33))]
2058 "TARGET_64BIT"
2059 "icmh\\t%0,8,%1"
2060 [(set_attr "op_type" "RSE")])
2061
2062 (define_insn "*sethighqidi_31"
2063 [(set (match_operand:DI 0 "register_operand" "=d")
2064 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2065 (clobber (reg:CC 33))]
2066 "!TARGET_64BIT"
2067 "icm\\t%0,8,%1"
2068 [(set_attr "op_type" "RS")])
2069
2070 (define_insn_and_split "*extractqi"
2071 [(set (match_operand:SI 0 "register_operand" "=d")
2072 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2073 (match_operand 2 "const_int_operand" "n")
2074 (const_int 0)))
2075 (clobber (reg:CC 33))]
2076 "!TARGET_64BIT
2077 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2078 "#"
2079 "&& reload_completed"
2080 [(parallel
2081 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2082 (clobber (reg:CC 33))])
2083 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2084 "
2085 {
2086 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2087 operands[1] = change_address (operands[1], QImode, 0);
2088 }"
2089 [(set_attr "atype" "agen")])
2090
2091 (define_insn_and_split "*extracthi"
2092 [(set (match_operand:SI 0 "register_operand" "=d")
2093 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2094 (match_operand 2 "const_int_operand" "n")
2095 (const_int 0)))
2096 (clobber (reg:CC 33))]
2097 "!TARGET_64BIT
2098 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2099 "#"
2100 "&& reload_completed"
2101 [(parallel
2102 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2103 (clobber (reg:CC 33))])
2104 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2105 "
2106 {
2107 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2108 operands[1] = change_address (operands[1], HImode, 0);
2109 }"
2110 [(set_attr "atype" "agen")])
2111
2112 ;
2113 ; extendsidi2 instruction pattern(s).
2114 ;
2115
2116 (define_expand "extendsidi2"
2117 [(set (match_operand:DI 0 "register_operand" "")
2118 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2119 ""
2120 "
2121 {
2122 if (!TARGET_64BIT)
2123 {
2124 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2125 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2126 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2127 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2128 DONE;
2129 }
2130 }
2131 ")
2132
2133 (define_insn "*extendsidi2"
2134 [(set (match_operand:DI 0 "register_operand" "=d,d")
2135 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2136 "TARGET_64BIT"
2137 "@
2138 lgfr\\t%0,%1
2139 lgf\\t%0,%1"
2140 [(set_attr "op_type" "RRE,RXE")])
2141
2142 ;
2143 ; extendhidi2 instruction pattern(s).
2144 ;
2145
2146 (define_expand "extendhidi2"
2147 [(set (match_operand:DI 0 "register_operand" "")
2148 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2149 ""
2150 "
2151 {
2152 if (!TARGET_64BIT)
2153 {
2154 rtx tmp = gen_reg_rtx (SImode);
2155 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2156 emit_insn (gen_extendsidi2 (operands[0], tmp));
2157 DONE;
2158 }
2159 else
2160 {
2161 operands[1] = gen_lowpart (DImode, operands[1]);
2162 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2163 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2164 DONE;
2165 }
2166 }
2167 ")
2168
2169 (define_insn "*extendhidi2"
2170 [(set (match_operand:DI 0 "register_operand" "=d")
2171 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2172 "TARGET_64BIT"
2173 "lgh\\t%0,%1"
2174 [(set_attr "op_type" "RXE")])
2175
2176 ;
2177 ; extendqidi2 instruction pattern(s).
2178 ;
2179
2180 (define_expand "extendqidi2"
2181 [(set (match_operand:DI 0 "register_operand" "")
2182 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2183 ""
2184 "
2185 {
2186 if (!TARGET_64BIT)
2187 {
2188 rtx tmp = gen_reg_rtx (SImode);
2189 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2190 emit_insn (gen_extendsidi2 (operands[0], tmp));
2191 DONE;
2192 }
2193 else
2194 {
2195 operands[1] = gen_lowpart (DImode, operands[1]);
2196 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2197 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2198 DONE;
2199 }
2200 }
2201 ")
2202
2203 (define_split
2204 [(set (match_operand:DI 0 "register_operand" "")
2205 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2206 "TARGET_64BIT && !reload_completed"
2207 [(parallel
2208 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2209 (clobber (reg:CC 33))])
2210 (parallel
2211 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2212 (clobber (reg:CC 33))])]
2213 "")
2214
2215 ;
2216 ; extendhisi2 instruction pattern(s).
2217 ;
2218
2219 (define_expand "extendhisi2"
2220 [(set (match_operand:SI 0 "register_operand" "")
2221 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2222 ""
2223 "
2224 {
2225 operands[1] = gen_lowpart (SImode, operands[1]);
2226 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2227 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2228 DONE;
2229 }
2230 ")
2231
2232 (define_insn "*extendhisi2"
2233 [(set (match_operand:SI 0 "register_operand" "=d")
2234 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2235 ""
2236 "lh\\t%0,%1"
2237 [(set_attr "op_type" "RX")])
2238
2239 ;
2240 ; extendqisi2 instruction pattern(s).
2241 ;
2242
2243 (define_expand "extendqisi2"
2244 [(set (match_operand:SI 0 "register_operand" "")
2245 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2246 ""
2247 "
2248 {
2249 operands[1] = gen_lowpart (SImode, operands[1]);
2250 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2251 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2252 DONE;
2253 }
2254 ")
2255
2256 (define_split
2257 [(set (match_operand:SI 0 "register_operand" "")
2258 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2259 "!reload_completed"
2260 [(parallel
2261 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2262 (clobber (reg:CC 33))])
2263 (parallel
2264 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2265 (clobber (reg:CC 33))])]
2266 "")
2267
2268 ;
2269 ; extendqihi2 instruction pattern(s).
2270 ;
2271
2272
2273 ;
2274 ; zero_extendsidi2 instruction pattern(s).
2275 ;
2276
2277 (define_expand "zero_extendsidi2"
2278 [(set (match_operand:DI 0 "register_operand" "")
2279 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2280 ""
2281 "
2282 {
2283 if (!TARGET_64BIT)
2284 {
2285 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2286 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2287 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2288 DONE;
2289 }
2290 }
2291 ")
2292
2293 (define_insn "*zero_extendsidi2"
2294 [(set (match_operand:DI 0 "register_operand" "=d,d")
2295 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2296 "TARGET_64BIT"
2297 "@
2298 llgfr\\t%0,%1
2299 llgf\\t%0,%1"
2300 [(set_attr "op_type" "RRE,RXE")])
2301
2302 ;
2303 ; zero_extendhidi2 instruction pattern(s).
2304 ;
2305
2306 (define_expand "zero_extendhidi2"
2307 [(set (match_operand:DI 0 "register_operand" "")
2308 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2309 ""
2310 "
2311 {
2312 if (!TARGET_64BIT)
2313 {
2314 rtx tmp = gen_reg_rtx (SImode);
2315 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2316 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2317 DONE;
2318 }
2319 else
2320 {
2321 operands[1] = gen_lowpart (DImode, operands[1]);
2322 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2323 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2324 DONE;
2325 }
2326 }
2327 ")
2328
2329 (define_insn "*zero_extendhidi2"
2330 [(set (match_operand:DI 0 "register_operand" "=d")
2331 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2332 "TARGET_64BIT"
2333 "llgh\\t%0,%1"
2334 [(set_attr "op_type" "RXE")])
2335
2336 ;
2337 ; zero_extendqidi2 instruction pattern(s)
2338 ;
2339
2340 (define_expand "zero_extendqidi2"
2341 [(set (match_operand:DI 0 "register_operand" "")
2342 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2343 ""
2344 "
2345 {
2346 if (!TARGET_64BIT)
2347 {
2348 rtx tmp = gen_reg_rtx (SImode);
2349 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2350 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2351 DONE;
2352 }
2353 else
2354 {
2355 operands[1] = gen_lowpart (DImode, operands[1]);
2356 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2357 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2358 DONE;
2359 }
2360 }
2361 ")
2362
2363 (define_insn "*zero_extendqidi2"
2364 [(set (match_operand:DI 0 "register_operand" "=d")
2365 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2366 "TARGET_64BIT"
2367 "llgc\\t%0,%1"
2368 [(set_attr "op_type" "RXE")])
2369
2370 ;
2371 ; zero_extendhisi2 instruction pattern(s).
2372 ;
2373
2374 (define_expand "zero_extendhisi2"
2375 [(set (match_operand:SI 0 "register_operand" "")
2376 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2377 ""
2378 "
2379 {
2380 operands[1] = gen_lowpart (SImode, operands[1]);
2381 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2382 DONE;
2383 }
2384 ")
2385
2386 (define_insn "*zero_extendhisi2_64"
2387 [(set (match_operand:SI 0 "register_operand" "=d")
2388 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2389 "TARGET_64BIT"
2390 "llgh\\t%0,%1"
2391 [(set_attr "op_type" "RXE")])
2392
2393 (define_insn_and_split "*zero_extendhisi2_31"
2394 [(set (match_operand:SI 0 "register_operand" "=&d")
2395 (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
2396 (clobber (reg:CC 33))]
2397 "!TARGET_64BIT"
2398 "#"
2399 "&& reload_completed"
2400 [(set (match_dup 0) (const_int 0))
2401 (parallel
2402 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2403 (clobber (reg:CC 33))])]
2404 "operands[2] = gen_lowpart (HImode, operands[0]);"
2405 [(set_attr "atype" "agen")])
2406
2407 ;
2408 ; zero_extendqisi2 instruction pattern(s).
2409 ;
2410
2411 (define_expand "zero_extendqisi2"
2412 [(set (match_operand:SI 0 "register_operand" "")
2413 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2414 ""
2415 "
2416 {
2417 operands[1] = gen_lowpart (SImode, operands[1]);
2418 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2419 DONE;
2420 }
2421 ")
2422
2423 (define_insn "*zero_extendqisi2_64"
2424 [(set (match_operand:SI 0 "register_operand" "=d")
2425 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2426 "TARGET_64BIT"
2427 "llgc\\t%0,%1"
2428 [(set_attr "op_type" "RXE")])
2429
2430 (define_insn_and_split "*zero_extendqisi2_31"
2431 [(set (match_operand:SI 0 "register_operand" "=&d")
2432 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2433 "!TARGET_64BIT"
2434 "#"
2435 "&& reload_completed"
2436 [(set (match_dup 0) (const_int 0))
2437 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2438 "operands[2] = gen_lowpart (QImode, operands[0]);"
2439 [(set_attr "atype" "agen")])
2440
2441 ;
2442 ; zero_extendqihi2 instruction pattern(s).
2443 ;
2444
2445 (define_expand "zero_extendqihi2"
2446 [(set (match_operand:HI 0 "register_operand" "")
2447 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2448 "TARGET_64BIT"
2449 "
2450 {
2451 operands[1] = gen_lowpart (HImode, operands[1]);
2452 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2453 DONE;
2454 }
2455 ")
2456
2457 (define_insn "*zero_extendqihi2_64"
2458 [(set (match_operand:HI 0 "register_operand" "=d")
2459 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2460 "TARGET_64BIT"
2461 "llgc\\t%0,%1"
2462 [(set_attr "op_type" "RXE")])
2463
2464 (define_insn_and_split "*zero_extendqihi2_31"
2465 [(set (match_operand:HI 0 "register_operand" "=&d")
2466 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2467 "!TARGET_64BIT"
2468 "#"
2469 "&& reload_completed"
2470 [(set (match_dup 0) (const_int 0))
2471 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2472 "operands[2] = gen_lowpart (QImode, operands[0]);"
2473 [(set_attr "atype" "agen")])
2474
2475
2476 ;
2477 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2478 ;
2479
2480 (define_expand "fixuns_truncdfdi2"
2481 [(set (match_operand:DI 0 "register_operand" "")
2482 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2483 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2484 "
2485 {
2486 rtx label1 = gen_label_rtx ();
2487 rtx label2 = gen_label_rtx ();
2488 rtx temp = gen_reg_rtx (DFmode);
2489 operands[1] = force_reg (DFmode, operands[1]);
2490
2491 emit_insn (gen_cmpdf (operands[1],
2492 CONST_DOUBLE_FROM_REAL_VALUE (
2493 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2494 emit_jump_insn (gen_blt (label1));
2495 emit_insn (gen_subdf3 (temp, operands[1],
2496 CONST_DOUBLE_FROM_REAL_VALUE (
2497 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2498 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2499 emit_jump (label2);
2500
2501 emit_label (label1);
2502 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2503 emit_label (label2);
2504 DONE;
2505 }")
2506
2507 (define_expand "fix_truncdfdi2"
2508 [(set (match_operand:DI 0 "register_operand" "")
2509 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2510 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2511 "
2512 {
2513 operands[1] = force_reg (DFmode, operands[1]);
2514 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2515 DONE;
2516 }")
2517
2518 (define_insn "fix_truncdfdi2_ieee"
2519 [(set (match_operand:DI 0 "register_operand" "=d")
2520 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2521 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2522 (clobber (reg:CC 33))]
2523 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2524 "cgdbr\\t%0,%h2,%1"
2525 [(set_attr "op_type" "RRE")
2526 (set_attr "type" "ftoi")])
2527
2528 ;
2529 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2530 ;
2531
2532 (define_expand "fixuns_truncdfsi2"
2533 [(set (match_operand:SI 0 "register_operand" "")
2534 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2535 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2536 "
2537 {
2538 rtx label1 = gen_label_rtx ();
2539 rtx label2 = gen_label_rtx ();
2540 rtx temp = gen_reg_rtx (DFmode);
2541
2542 operands[1] = force_reg (DFmode,operands[1]);
2543 emit_insn (gen_cmpdf (operands[1],
2544 CONST_DOUBLE_FROM_REAL_VALUE (
2545 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2546 emit_jump_insn (gen_blt (label1));
2547 emit_insn (gen_subdf3 (temp, operands[1],
2548 CONST_DOUBLE_FROM_REAL_VALUE (
2549 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2550 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2551 emit_jump (label2);
2552
2553 emit_label (label1);
2554 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2555 emit_label (label2);
2556 DONE;
2557 }")
2558
2559 (define_expand "fix_truncdfsi2"
2560 [(set (match_operand:SI 0 "register_operand" "")
2561 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2562 "TARGET_HARD_FLOAT"
2563 "
2564 {
2565 if (TARGET_IBM_FLOAT)
2566 {
2567 /* This is the algorithm from POP chapter A.5.7.2. */
2568
2569 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2570 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2571 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2572
2573 operands[1] = force_reg (DFmode, operands[1]);
2574 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2575 two31r, two32, temp));
2576 }
2577 else
2578 {
2579 operands[1] = force_reg (DFmode, operands[1]);
2580 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2581 }
2582
2583 DONE;
2584 }")
2585
2586 (define_insn "fix_truncdfsi2_ieee"
2587 [(set (match_operand:SI 0 "register_operand" "=d")
2588 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2589 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2590 (clobber (reg:CC 33))]
2591 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2592 "cfdbr\\t%0,%h2,%1"
2593 [(set_attr "op_type" "RRE")
2594 (set_attr "type" "other" )])
2595
2596 (define_insn "fix_truncdfsi2_ibm"
2597 [(set (match_operand:SI 0 "register_operand" "=d")
2598 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2599 (use (match_operand:DI 2 "immediate_operand" "m"))
2600 (use (match_operand:DI 3 "immediate_operand" "m"))
2601 (use (match_operand:BLK 4 "memory_operand" "m"))
2602 (clobber (reg:CC 33))]
2603 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2604 "*
2605 {
2606 output_asm_insn (\"sd\\t%1,%2\", operands);
2607 output_asm_insn (\"aw\\t%1,%3\", operands);
2608 output_asm_insn (\"std\\t%1,%4\", operands);
2609 output_asm_insn (\"xi\\t%N4,128\", operands);
2610 return \"l\\t%0,%N4\";
2611 }"
2612 [(set_attr "op_type" "NN")
2613 (set_attr "type" "ftoi")
2614 (set_attr "atype" "agen")
2615 (set_attr "length" "20")])
2616
2617 ;
2618 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2619 ;
2620
2621 (define_expand "fixuns_truncsfdi2"
2622 [(set (match_operand:DI 0 "register_operand" "")
2623 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2624 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2625 "
2626 {
2627 rtx label1 = gen_label_rtx ();
2628 rtx label2 = gen_label_rtx ();
2629 rtx temp = gen_reg_rtx (SFmode);
2630
2631 operands[1] = force_reg (SFmode, operands[1]);
2632 emit_insn (gen_cmpsf (operands[1],
2633 CONST_DOUBLE_FROM_REAL_VALUE (
2634 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2635 emit_jump_insn (gen_blt (label1));
2636
2637 emit_insn (gen_subsf3 (temp, operands[1],
2638 CONST_DOUBLE_FROM_REAL_VALUE (
2639 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2640 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2641 emit_jump (label2);
2642
2643 emit_label (label1);
2644 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2645 emit_label (label2);
2646 DONE;
2647 }")
2648
2649 (define_expand "fix_truncsfdi2"
2650 [(set (match_operand:DI 0 "register_operand" "")
2651 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2652 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2653 "
2654 {
2655 operands[1] = force_reg (SFmode, operands[1]);
2656 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2657 DONE;
2658 }")
2659
2660 (define_insn "fix_truncsfdi2_ieee"
2661 [(set (match_operand:DI 0 "register_operand" "=d")
2662 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2663 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2664 (clobber (reg:CC 33))]
2665 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2666 "cgebr\\t%0,%h2,%1"
2667 [(set_attr "op_type" "RRE")
2668 (set_attr "type" "ftoi")])
2669
2670 ;
2671 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2672 ;
2673
2674 (define_expand "fixuns_truncsfsi2"
2675 [(set (match_operand:SI 0 "register_operand" "")
2676 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2677 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2678 "
2679 {
2680 rtx label1 = gen_label_rtx ();
2681 rtx label2 = gen_label_rtx ();
2682 rtx temp = gen_reg_rtx (SFmode);
2683
2684 operands[1] = force_reg (SFmode, operands[1]);
2685 emit_insn (gen_cmpsf (operands[1],
2686 CONST_DOUBLE_FROM_REAL_VALUE (
2687 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2688 emit_jump_insn (gen_blt (label1));
2689 emit_insn (gen_subsf3 (temp, operands[1],
2690 CONST_DOUBLE_FROM_REAL_VALUE (
2691 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2692 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2693 emit_jump (label2);
2694
2695 emit_label (label1);
2696 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2697 emit_label (label2);
2698 DONE;
2699 }")
2700
2701 (define_expand "fix_truncsfsi2"
2702 [(set (match_operand:SI 0 "register_operand" "")
2703 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2704 "TARGET_HARD_FLOAT"
2705 "
2706 {
2707 if (TARGET_IBM_FLOAT)
2708 {
2709 /* Convert to DFmode and then use the POP algorithm. */
2710 rtx temp = gen_reg_rtx (DFmode);
2711 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2712 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2713 }
2714 else
2715 {
2716 operands[1] = force_reg (SFmode, operands[1]);
2717 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2718 }
2719
2720 DONE;
2721 }")
2722
2723 (define_insn "fix_truncsfsi2_ieee"
2724 [(set (match_operand:SI 0 "register_operand" "=d")
2725 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2726 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2727 (clobber (reg:CC 33))]
2728 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2729 "cfebr\\t%0,%h2,%1"
2730 [(set_attr "op_type" "RRE")
2731 (set_attr "type" "ftoi")])
2732
2733 ;
2734 ; floatdidf2 instruction pattern(s).
2735 ;
2736
2737 (define_insn "floatdidf2"
2738 [(set (match_operand:DF 0 "register_operand" "=f")
2739 (float:DF (match_operand:DI 1 "register_operand" "d")))
2740 (clobber (reg:CC 33))]
2741 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2742 "cdgbr\\t%0,%1"
2743 [(set_attr "op_type" "RRE")
2744 (set_attr "type" "itof" )])
2745
2746 ;
2747 ; floatdisf2 instruction pattern(s).
2748 ;
2749
2750 (define_insn "floatdisf2"
2751 [(set (match_operand:SF 0 "register_operand" "=f")
2752 (float:SF (match_operand:DI 1 "register_operand" "d")))
2753 (clobber (reg:CC 33))]
2754 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2755 "cegbr\\t%0,%1"
2756 [(set_attr "op_type" "RRE")
2757 (set_attr "type" "itof" )])
2758
2759 ;
2760 ; floatsidf2 instruction pattern(s).
2761 ;
2762
2763 (define_expand "floatsidf2"
2764 [(parallel
2765 [(set (match_operand:DF 0 "register_operand" "")
2766 (float:DF (match_operand:SI 1 "register_operand" "")))
2767 (clobber (reg:CC 33))])]
2768 "TARGET_HARD_FLOAT"
2769 "
2770 {
2771 if (TARGET_IBM_FLOAT)
2772 {
2773 /* This is the algorithm from POP chapter A.5.7.1. */
2774
2775 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2776 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2777
2778 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2779 DONE;
2780 }
2781 }")
2782
2783 (define_insn "floatsidf2_ieee"
2784 [(set (match_operand:DF 0 "register_operand" "=f")
2785 (float:DF (match_operand:SI 1 "register_operand" "d")))
2786 (clobber (reg:CC 33))]
2787 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2788 "cdfbr\\t%0,%1"
2789 [(set_attr "op_type" "RRE")
2790 (set_attr "type" "itof" )])
2791
2792 (define_insn "floatsidf2_ibm"
2793 [(set (match_operand:DF 0 "register_operand" "=f")
2794 (float:DF (match_operand:SI 1 "register_operand" "d")))
2795 (use (match_operand:DI 2 "immediate_operand" "m"))
2796 (use (match_operand:BLK 3 "memory_operand" "m"))
2797 (clobber (reg:CC 33))]
2798 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2799 "*
2800 {
2801 output_asm_insn (\"st\\t%1,%N3\", operands);
2802 output_asm_insn (\"xi\\t%N3,128\", operands);
2803 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2804 output_asm_insn (\"ld\\t%0,%3\", operands);
2805 return \"sd\\t%0,%2\";
2806 }"
2807 [(set_attr "op_type" "NN")
2808 (set_attr "type" "other" )
2809 (set_attr "atype" "agen")
2810 (set_attr "length" "20")])
2811
2812 ;
2813 ; floatsisf2 instruction pattern(s).
2814 ;
2815
2816 (define_expand "floatsisf2"
2817 [(parallel
2818 [(set (match_operand:SF 0 "register_operand" "")
2819 (float:SF (match_operand:SI 1 "register_operand" "")))
2820 (clobber (reg:CC 33))])]
2821 "TARGET_HARD_FLOAT"
2822 "
2823 {
2824 if (TARGET_IBM_FLOAT)
2825 {
2826 /* Use the POP algorithm to convert to DFmode and then truncate. */
2827 rtx temp = gen_reg_rtx (DFmode);
2828 emit_insn (gen_floatsidf2 (temp, operands[1]));
2829 emit_insn (gen_truncdfsf2 (operands[0], temp));
2830 DONE;
2831 }
2832 }")
2833
2834 (define_insn "floatsisf2_ieee"
2835 [(set (match_operand:SF 0 "register_operand" "=f")
2836 (float:SF (match_operand:SI 1 "register_operand" "d")))
2837 (clobber (reg:CC 33))]
2838 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2839 "cefbr\\t%0,%1"
2840 [(set_attr "op_type" "RRE")
2841 (set_attr "type" "itof" )])
2842
2843 ;
2844 ; truncdfsf2 instruction pattern(s).
2845 ;
2846
2847 (define_expand "truncdfsf2"
2848 [(set (match_operand:SF 0 "register_operand" "")
2849 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2850 "TARGET_HARD_FLOAT"
2851 "")
2852
2853 (define_insn "truncdfsf2_ieee"
2854 [(set (match_operand:SF 0 "register_operand" "=f")
2855 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2856 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2857 "ledbr\\t%0,%1"
2858 [(set_attr "op_type" "RRE")])
2859
2860 (define_insn "truncdfsf2_ibm"
2861 [(set (match_operand:SF 0 "register_operand" "=f,f")
2862 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2863 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2864 "@
2865 lrer\\t%0,%1
2866 le\\t%0,%1"
2867 [(set_attr "op_type" "RR,RX")
2868 (set_attr "type" "floads,floads")])
2869
2870 ;
2871 ; extendsfdf2 instruction pattern(s).
2872 ;
2873
2874 (define_expand "extendsfdf2"
2875 [(set (match_operand:DF 0 "register_operand" "")
2876 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2877 "TARGET_HARD_FLOAT"
2878 "
2879 {
2880 if (TARGET_IBM_FLOAT)
2881 {
2882 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2883 DONE;
2884 }
2885 }")
2886
2887 (define_insn "extendsfdf2_ieee"
2888 [(set (match_operand:DF 0 "register_operand" "=f,f")
2889 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2890 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2891 "@
2892 ldebr\\t%0,%1
2893 ldeb\\t%0,%1"
2894 [(set_attr "op_type" "RRE,RXE")
2895 (set_attr "type" "floads,floads")])
2896
2897 (define_insn "extendsfdf2_ibm"
2898 [(set (match_operand:DF 0 "register_operand" "=f,f")
2899 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2900 (clobber (reg:CC 33))]
2901 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2902 "@
2903 sdr\\t%0,%0\;ler\\t%0,%1
2904 sdr\\t%0,%0\;le\\t%0,%1"
2905 [(set_attr "op_type" "NN,NN")
2906 (set_attr "atype" "reg,agen")
2907 (set_attr "length" "4,6")
2908 (set_attr "type" "o2,o2")])
2909
2910
2911 ;;
2912 ;; ARITHMETRIC OPERATIONS
2913 ;;
2914 ; arithmetric operations set the ConditionCode,
2915 ; because of unpredictable Bits in Register for Halfword and Byte
2916 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2917
2918 ;;
2919 ;;- Add instructions.
2920 ;;
2921
2922 ;
2923 ; adddi3 instruction pattern(s).
2924 ;
2925
2926 (define_insn "*adddi3_sign"
2927 [(set (match_operand:DI 0 "register_operand" "=d,d")
2928 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2929 (match_operand:DI 1 "register_operand" "0,0")))
2930 (clobber (reg:CC 33))]
2931 "TARGET_64BIT"
2932 "@
2933 agfr\\t%0,%2
2934 agf\\t%0,%2"
2935 [(set_attr "op_type" "RRE,RXE")])
2936
2937 (define_insn "*adddi3_zero_cc"
2938 [(set (reg 33)
2939 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2940 (match_operand:DI 1 "register_operand" "0,0"))
2941 (const_int 0)))
2942 (set (match_operand:DI 0 "register_operand" "=d,d")
2943 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2944 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2945 "@
2946 algfr\\t%0,%2
2947 algf\\t%0,%2"
2948 [(set_attr "op_type" "RRE,RXE")])
2949
2950 (define_insn "*adddi3_zero_cconly"
2951 [(set (reg 33)
2952 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2953 (match_operand:DI 1 "register_operand" "0,0"))
2954 (const_int 0)))
2955 (clobber (match_scratch:DI 0 "=d,d"))]
2956 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2957 "@
2958 algfr\\t%0,%2
2959 algf\\t%0,%2"
2960 [(set_attr "op_type" "RRE,RXE")])
2961
2962 (define_insn "*adddi3_zero"
2963 [(set (match_operand:DI 0 "register_operand" "=d,d")
2964 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2965 (match_operand:DI 1 "register_operand" "0,0")))
2966 (clobber (reg:CC 33))]
2967 "TARGET_64BIT"
2968 "@
2969 algfr\\t%0,%2
2970 algf\\t%0,%2"
2971 [(set_attr "op_type" "RRE,RXE")])
2972
2973 (define_insn "*adddi3_imm_cc"
2974 [(set (reg 33)
2975 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2976 (match_operand:DI 2 "const_int_operand" "K"))
2977 (const_int 0)))
2978 (set (match_operand:DI 0 "register_operand" "=d")
2979 (plus:DI (match_dup 1) (match_dup 2)))]
2980 "TARGET_64BIT
2981 && s390_match_ccmode (insn, CCAmode)
2982 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2983 "aghi\\t%0,%h2"
2984 [(set_attr "op_type" "RI")])
2985
2986 (define_insn "*adddi3_cc"
2987 [(set (reg 33)
2988 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2989 (match_operand:DI 2 "general_operand" "d,m"))
2990 (const_int 0)))
2991 (set (match_operand:DI 0 "register_operand" "=d,d")
2992 (plus:DI (match_dup 1) (match_dup 2)))]
2993 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2994 "@
2995 algr\\t%0,%2
2996 alg\\t%0,%2"
2997 [(set_attr "op_type" "RRE,RXE")])
2998
2999 (define_insn "*adddi3_cconly"
3000 [(set (reg 33)
3001 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3002 (match_operand:DI 2 "general_operand" "d,m"))
3003 (const_int 0)))
3004 (clobber (match_scratch:DI 0 "=d,d"))]
3005 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3006 "@
3007 algr\\t%0,%2
3008 alg\\t%0,%2"
3009 [(set_attr "op_type" "RRE,RXE")])
3010
3011 (define_insn "*adddi3_cconly2"
3012 [(set (reg 33)
3013 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3014 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3015 (clobber (match_scratch:DI 0 "=d,d"))]
3016 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3017 "@
3018 algr\\t%0,%2
3019 alg\\t%0,%2"
3020 [(set_attr "op_type" "RRE,RXE")])
3021
3022 (define_insn "*adddi3_64"
3023 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3024 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3025 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3026 (clobber (reg:CC 33))]
3027 "TARGET_64BIT"
3028 "@
3029 agr\\t%0,%2
3030 aghi\\t%0,%h2
3031 ag\\t%0,%2"
3032 [(set_attr "op_type" "RRE,RI,RXE")])
3033
3034 (define_insn_and_split "*adddi3_31"
3035 [(set (match_operand:DI 0 "register_operand" "=&d")
3036 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3037 (match_operand:DI 2 "general_operand" "do") ) )
3038 (clobber (reg:CC 33))]
3039 "!TARGET_64BIT"
3040 "#"
3041 "&& reload_completed"
3042 [(parallel
3043 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3044 (clobber (reg:CC 33))])
3045 (parallel
3046 [(set (reg:CCL1 33)
3047 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3048 (match_dup 7)))
3049 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3050 (set (pc)
3051 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3052 (pc)
3053 (label_ref (match_dup 9))))
3054 (parallel
3055 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3056 (clobber (reg:CC 33))])
3057 (match_dup 9)]
3058 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3059 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3060 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3061 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3062 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3063 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3064 operands[9] = gen_label_rtx ();"
3065 [(set_attr "op_type" "NN")])
3066
3067 (define_expand "adddi3"
3068 [(parallel
3069 [(set (match_operand:DI 0 "register_operand" "")
3070 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3071 (match_operand:DI 2 "general_operand" "")))
3072 (clobber (reg:CC 33))])]
3073 ""
3074 "")
3075
3076 (define_insn "*la_64"
3077 [(set (match_operand:DI 0 "register_operand" "=d")
3078 (match_operand:QI 1 "address_operand" "p"))]
3079 "TARGET_64BIT"
3080 "la\\t%0,%a1"
3081 [(set_attr "op_type" "RX")
3082 (set_attr "type" "la")])
3083
3084 (define_peephole2
3085 [(parallel
3086 [(set (match_operand:DI 0 "register_operand" "")
3087 (match_operand:QI 1 "address_operand" ""))
3088 (clobber (reg:CC 33))])]
3089 "TARGET_64BIT
3090 && strict_memory_address_p (VOIDmode, operands[1])
3091 && preferred_la_operand_p (operands[1])"
3092 [(set (match_dup 0) (match_dup 1))]
3093 "")
3094
3095 (define_peephole2
3096 [(set (match_operand:DI 0 "register_operand" "")
3097 (match_operand:DI 1 "register_operand" ""))
3098 (parallel
3099 [(set (match_dup 0)
3100 (plus:DI (match_dup 0)
3101 (match_operand:DI 2 "nonmemory_operand" "")))
3102 (clobber (reg:CC 33))])]
3103 "TARGET_64BIT
3104 && !reg_overlap_mentioned_p (operands[0], operands[2])
3105 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2]))
3106 && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))"
3107 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3108 "")
3109
3110 (define_expand "reload_indi"
3111 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3112 (match_operand:DI 1 "s390_plus_operand" "")
3113 (match_operand:DI 2 "register_operand" "=&a")])]
3114 "TARGET_64BIT"
3115 "
3116 {
3117 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3118 DONE;
3119 }")
3120
3121
3122 ;
3123 ; addsi3 instruction pattern(s).
3124 ;
3125
3126 (define_insn "*addsi3_imm_cc"
3127 [(set (reg 33)
3128 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3129 (match_operand:SI 2 "const_int_operand" "K"))
3130 (const_int 0)))
3131 (set (match_operand:SI 0 "register_operand" "=d")
3132 (plus:SI (match_dup 1) (match_dup 2)))]
3133 "s390_match_ccmode (insn, CCAmode)
3134 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3135 "ahi\\t%0,%h2"
3136 [(set_attr "op_type" "RI")])
3137
3138 (define_insn "*addsi3_carry1_cc"
3139 [(set (reg 33)
3140 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3141 (match_operand:SI 2 "general_operand" "d,m"))
3142 (match_dup 1)))
3143 (set (match_operand:SI 0 "register_operand" "=d,d")
3144 (plus:SI (match_dup 1) (match_dup 2)))]
3145 "s390_match_ccmode (insn, CCL1mode)"
3146 "@
3147 alr\\t%0,%2
3148 al\\t%0,%2"
3149 [(set_attr "op_type" "RR,RX")])
3150
3151 (define_insn "*addsi3_carry1_cconly"
3152 [(set (reg 33)
3153 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3154 (match_operand:SI 2 "general_operand" "d,m"))
3155 (match_dup 1)))
3156 (clobber (match_scratch:SI 0 "=d,d"))]
3157 "s390_match_ccmode (insn, CCL1mode)"
3158 "@
3159 alr\\t%0,%2
3160 al\\t%0,%2"
3161 [(set_attr "op_type" "RR,RX")])
3162
3163 (define_insn "*addsi3_carry2_cc"
3164 [(set (reg 33)
3165 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3166 (match_operand:SI 2 "general_operand" "d,m"))
3167 (match_dup 2)))
3168 (set (match_operand:SI 0 "register_operand" "=d,d")
3169 (plus:SI (match_dup 1) (match_dup 2)))]
3170 "s390_match_ccmode (insn, CCL1mode)"
3171 "@
3172 alr\\t%0,%2
3173 al\\t%0,%2"
3174 [(set_attr "op_type" "RR,RX")])
3175
3176 (define_insn "*addsi3_carry2_cconly"
3177 [(set (reg 33)
3178 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3179 (match_operand:SI 2 "general_operand" "d,m"))
3180 (match_dup 2)))
3181 (clobber (match_scratch:SI 0 "=d,d"))]
3182 "s390_match_ccmode (insn, CCL1mode)"
3183 "@
3184 alr\\t%0,%2
3185 al\\t%0,%2"
3186 [(set_attr "op_type" "RR,RX")])
3187
3188 (define_insn "*addsi3_cc"
3189 [(set (reg 33)
3190 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3191 (match_operand:SI 2 "general_operand" "d,m"))
3192 (const_int 0)))
3193 (set (match_operand:SI 0 "register_operand" "=d,d")
3194 (plus:SI (match_dup 1) (match_dup 2)))]
3195 "s390_match_ccmode (insn, CCLmode)"
3196 "@
3197 alr\\t%0,%2
3198 al\\t%0,%2"
3199 [(set_attr "op_type" "RR,RX")])
3200
3201 (define_insn "*addsi3_cconly"
3202 [(set (reg 33)
3203 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3204 (match_operand:SI 2 "general_operand" "d,m"))
3205 (const_int 0)))
3206 (clobber (match_scratch:SI 0 "=d,d"))]
3207 "s390_match_ccmode (insn, CCLmode)"
3208 "@
3209 alr\\t%0,%2
3210 al\\t%0,%2"
3211 [(set_attr "op_type" "RR,RX")])
3212
3213 (define_insn "*addsi3_cconly2"
3214 [(set (reg 33)
3215 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3216 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3217 (clobber (match_scratch:SI 0 "=d,d"))]
3218 "s390_match_ccmode(insn, CCLmode)"
3219 "@
3220 alr\\t%0,%2
3221 al\\t%0,%2"
3222 [(set_attr "op_type" "RR,RX")])
3223
3224 (define_insn "*addsi3_sign"
3225 [(set (match_operand:SI 0 "register_operand" "=d")
3226 (plus:SI (match_operand:SI 1 "register_operand" "0")
3227 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3228 (clobber (reg:CC 33))]
3229 ""
3230 "ah\\t%0,%2"
3231 [(set_attr "op_type" "RX")])
3232
3233 (define_insn "*addsi3_sub"
3234 [(set (match_operand:SI 0 "register_operand" "=d")
3235 (plus:SI (match_operand:SI 1 "register_operand" "0")
3236 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3237 (clobber (reg:CC 33))]
3238 ""
3239 "ah\\t%0,%2"
3240 [(set_attr "op_type" "RX")])
3241
3242 (define_insn "addsi3"
3243 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3244 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3245 (match_operand:SI 2 "general_operand" "d,K,m")))
3246 (clobber (reg:CC 33))]
3247 ""
3248 "@
3249 ar\\t%0,%2
3250 ahi\\t%0,%h2
3251 a\\t%0,%2"
3252 [(set_attr "op_type" "RR,RI,RX")])
3253
3254 (define_insn "*la_31"
3255 [(set (match_operand:SI 0 "register_operand" "=d")
3256 (match_operand:QI 1 "address_operand" "p"))]
3257 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3258 "la\\t%0,%a1"
3259 [(set_attr "op_type" "RX")
3260 (set_attr "type" "la")])
3261
3262 (define_peephole2
3263 [(parallel
3264 [(set (match_operand:SI 0 "register_operand" "")
3265 (match_operand:QI 1 "address_operand" ""))
3266 (clobber (reg:CC 33))])]
3267 "!TARGET_64BIT
3268 && strict_memory_address_p (VOIDmode, operands[1])
3269 && preferred_la_operand_p (operands[1])"
3270 [(set (match_dup 0) (match_dup 1))]
3271 "")
3272
3273 (define_peephole2
3274 [(set (match_operand:SI 0 "register_operand" "")
3275 (match_operand:SI 1 "register_operand" ""))
3276 (parallel
3277 [(set (match_dup 0)
3278 (plus:SI (match_dup 0)
3279 (match_operand:SI 2 "nonmemory_operand" "")))
3280 (clobber (reg:CC 33))])]
3281 "!TARGET_64BIT
3282 && !reg_overlap_mentioned_p (operands[0], operands[2])
3283 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2]))
3284 && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))"
3285 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3286 "")
3287
3288 (define_insn "*la_31_and"
3289 [(set (match_operand:SI 0 "register_operand" "=d")
3290 (and:SI (match_operand:QI 1 "address_operand" "p")
3291 (const_int 2147483647)))]
3292 "!TARGET_64BIT"
3293 "la\\t%0,%a1"
3294 [(set_attr "op_type" "RX")
3295 (set_attr "type" "la")])
3296
3297 (define_insn_and_split "*la_31_and_cc"
3298 [(set (match_operand:SI 0 "register_operand" "=d")
3299 (and:SI (match_operand:QI 1 "address_operand" "p")
3300 (const_int 2147483647)))
3301 (clobber (reg:CC 33))]
3302 "!TARGET_64BIT"
3303 "#"
3304 "&& reload_completed"
3305 [(set (match_dup 0)
3306 (and:SI (match_dup 1) (const_int 2147483647)))]
3307 ""
3308 [(set_attr "op_type" "RX")
3309 (set_attr "type" "la")])
3310
3311 (define_insn "force_la_31"
3312 [(set (match_operand:SI 0 "register_operand" "=d")
3313 (match_operand:QI 1 "address_operand" "p"))
3314 (use (const_int 0))]
3315 "!TARGET_64BIT"
3316 "la\\t%0,%a1"
3317 [(set_attr "op_type" "RX")
3318 (set_attr "type" "la")])
3319
3320 (define_expand "reload_insi"
3321 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3322 (match_operand:SI 1 "s390_plus_operand" "")
3323 (match_operand:SI 2 "register_operand" "=&a")])]
3324 "!TARGET_64BIT"
3325 "
3326 {
3327 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3328 DONE;
3329 }")
3330
3331
3332 ;
3333 ; adddf3 instruction pattern(s).
3334 ;
3335
3336 (define_expand "adddf3"
3337 [(parallel
3338 [(set (match_operand:DF 0 "register_operand" "=f,f")
3339 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3340 (match_operand:DF 2 "general_operand" "f,m")))
3341 (clobber (reg:CC 33))])]
3342 "TARGET_HARD_FLOAT"
3343 "")
3344
3345 (define_insn "*adddf3"
3346 [(set (match_operand:DF 0 "register_operand" "=f,f")
3347 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3348 (match_operand:DF 2 "general_operand" "f,m")))
3349 (clobber (reg:CC 33))]
3350 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3351 "@
3352 adbr\\t%0,%2
3353 adb\\t%0,%2"
3354 [(set_attr "op_type" "RRE,RXE")
3355 (set_attr "type" "fsimpd,fsimpd")])
3356
3357 (define_insn "*adddf3_ibm"
3358 [(set (match_operand:DF 0 "register_operand" "=f,f")
3359 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3360 (match_operand:DF 2 "general_operand" "f,m")))
3361 (clobber (reg:CC 33))]
3362 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3363 "@
3364 adr\\t%0,%2
3365 ad\\t%0,%2"
3366 [(set_attr "op_type" "RR,RX")
3367 (set_attr "type" "fsimpd,fsimpd")])
3368
3369 ;
3370 ; addsf3 instruction pattern(s).
3371 ;
3372
3373 (define_expand "addsf3"
3374 [(parallel
3375 [(set (match_operand:SF 0 "register_operand" "=f,f")
3376 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3377 (match_operand:SF 2 "general_operand" "f,m")))
3378 (clobber (reg:CC 33))])]
3379 "TARGET_HARD_FLOAT"
3380 "")
3381
3382 (define_insn "*addsf3"
3383 [(set (match_operand:SF 0 "register_operand" "=f,f")
3384 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3385 (match_operand:SF 2 "general_operand" "f,m")))
3386 (clobber (reg:CC 33))]
3387 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3388 "@
3389 aebr\\t%0,%2
3390 aeb\\t%0,%2"
3391 [(set_attr "op_type" "RRE,RXE")
3392 (set_attr "type" "fsimps,fsimps")])
3393
3394 (define_insn "*addsf3"
3395 [(set (match_operand:SF 0 "register_operand" "=f,f")
3396 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3397 (match_operand:SF 2 "general_operand" "f,m")))
3398 (clobber (reg:CC 33))]
3399 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3400 "@
3401 aer\\t%0,%2
3402 ae\\t%0,%2"
3403 [(set_attr "op_type" "RR,RX")
3404 (set_attr "type" "fsimps,fsimps")])
3405
3406
3407 ;;
3408 ;;- Subtract instructions.
3409 ;;
3410
3411 ;
3412 ; subdi3 instruction pattern(s).
3413 ;
3414
3415 (define_insn "*subdi3_sign"
3416 [(set (match_operand:DI 0 "register_operand" "=d,d")
3417 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3418 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3419 (clobber (reg:CC 33))]
3420 "TARGET_64BIT"
3421 "@
3422 sgfr\\t%0,%2
3423 sgf\\t%0,%2"
3424 [(set_attr "op_type" "RRE,RXE")])
3425
3426 (define_insn "*subdi3_zero_cc"
3427 [(set (reg 33)
3428 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3429 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3430 (const_int 0)))
3431 (set (match_operand:DI 0 "register_operand" "=d,d")
3432 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3433 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3434 "@
3435 slgfr\\t%0,%2
3436 slgf\\t%0,%2"
3437 [(set_attr "op_type" "RRE,RXE")])
3438
3439 (define_insn "*subdi3_zero_cconly"
3440 [(set (reg 33)
3441 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3442 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3443 (const_int 0)))
3444 (clobber (match_scratch:DI 0 "=d,d"))]
3445 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3446 "@
3447 slgfr\\t%0,%2
3448 slgf\\t%0,%2"
3449 [(set_attr "op_type" "RRE,RXE")])
3450
3451 (define_insn "*subdi3_zero"
3452 [(set (match_operand:DI 0 "register_operand" "=d,d")
3453 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3454 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3455 (clobber (reg:CC 33))]
3456 "TARGET_64BIT"
3457 "@
3458 slgfr\\t%0,%2
3459 slgf\\t%0,%2"
3460 [(set_attr "op_type" "RRE,RXE")])
3461
3462 (define_insn "*subdi3_cc"
3463 [(set (reg 33)
3464 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3465 (match_operand:DI 2 "general_operand" "d,m"))
3466 (const_int 0)))
3467 (set (match_operand:DI 0 "register_operand" "=d,d")
3468 (minus:DI (match_dup 1) (match_dup 2)))]
3469 "s390_match_ccmode (insn, CCLmode)"
3470 "@
3471 slgr\\t%0,%2
3472 slg\\t%0,%2"
3473 [(set_attr "op_type" "RRE,RXE")])
3474
3475 (define_insn "*subdi3_cconly"
3476 [(set (reg 33)
3477 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3478 (match_operand:DI 2 "general_operand" "d,m"))
3479 (const_int 0)))
3480 (clobber (match_scratch:DI 0 "=d,d"))]
3481 "s390_match_ccmode (insn, CCLmode)"
3482 "@
3483 slgr\\t%0,%2
3484 slg\\t%0,%2"
3485 [(set_attr "op_type" "RRE,RXE")])
3486
3487 (define_insn "*subdi3_64"
3488 [(set (match_operand:DI 0 "register_operand" "=d,d")
3489 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3490 (match_operand:DI 2 "general_operand" "d,m") ) )
3491 (clobber (reg:CC 33))]
3492 "TARGET_64BIT"
3493 "@
3494 sgr\\t%0,%2
3495 sg\\t%0,%2"
3496 [(set_attr "op_type" "RRE,RRE")])
3497
3498 (define_insn_and_split "*subdi3_31"
3499 [(set (match_operand:DI 0 "register_operand" "=&d")
3500 (minus:DI (match_operand:DI 1 "register_operand" "0")
3501 (match_operand:DI 2 "general_operand" "do") ) )
3502 (clobber (reg:CC 33))]
3503 "!TARGET_64BIT"
3504 "#"
3505 "&& reload_completed"
3506 [(parallel
3507 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3508 (clobber (reg:CC 33))])
3509 (parallel
3510 [(set (reg:CCL2 33)
3511 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3512 (match_dup 7)))
3513 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3514 (set (pc)
3515 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3516 (pc)
3517 (label_ref (match_dup 9))))
3518 (parallel
3519 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3520 (clobber (reg:CC 33))])
3521 (match_dup 9)]
3522 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3523 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3524 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3525 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3526 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3527 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3528 operands[9] = gen_label_rtx ();"
3529 [(set_attr "op_type" "NN")])
3530
3531 (define_expand "subdi3"
3532 [(parallel
3533 [(set (match_operand:DI 0 "register_operand" "")
3534 (minus:DI (match_operand:DI 1 "register_operand" "")
3535 (match_operand:DI 2 "general_operand" "")))
3536 (clobber (reg:CC 33))])]
3537 ""
3538 "")
3539
3540 ;
3541 ; subsi3 instruction pattern(s).
3542 ;
3543
3544 (define_insn "*subsi3_borrow_cc"
3545 [(set (reg 33)
3546 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3547 (match_operand:SI 2 "general_operand" "d,m"))
3548 (match_dup 1)))
3549 (set (match_operand:SI 0 "register_operand" "=d,d")
3550 (minus:SI (match_dup 1) (match_dup 2)))]
3551 "s390_match_ccmode(insn, CCL2mode)"
3552 "@
3553 slr\\t%0,%2
3554 sl\\t%0,%2"
3555 [(set_attr "op_type" "RR,RX")])
3556
3557 (define_insn "*subsi3_borrow_cconly"
3558 [(set (reg 33)
3559 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3560 (match_operand:SI 2 "general_operand" "d,m"))
3561 (match_dup 1)))
3562 (clobber (match_scratch:SI 0 "=d,d"))]
3563 "s390_match_ccmode(insn, CCL2mode)"
3564 "@
3565 slr\\t%0,%2
3566 sl\\t%0,%2"
3567 [(set_attr "op_type" "RR,RX")])
3568
3569 (define_insn "*subsi3_cc"
3570 [(set (reg 33)
3571 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3572 (match_operand:SI 2 "general_operand" "d,m"))
3573 (const_int 0)))
3574 (set (match_operand:SI 0 "register_operand" "=d,d")
3575 (minus:SI (match_dup 1) (match_dup 2)))]
3576 "s390_match_ccmode(insn, CCLmode)"
3577 "@
3578 slr\\t%0,%2
3579 sl\\t%0,%2"
3580 [(set_attr "op_type" "RR,RX")])
3581
3582 (define_insn "*subsi3_cconly"
3583 [(set (reg 33)
3584 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3585 (match_operand:SI 2 "general_operand" "d,m"))
3586 (const_int 0)))
3587 (clobber (match_scratch:SI 0 "=d,d"))]
3588 "s390_match_ccmode(insn, CCLmode)"
3589 "@
3590 slr\\t%0,%2
3591 sl\\t%0,%2"
3592 [(set_attr "op_type" "RR,RX")])
3593
3594 (define_insn "*subsi3_sign"
3595 [(set (match_operand:SI 0 "register_operand" "=d")
3596 (minus:SI (match_operand:SI 1 "register_operand" "0")
3597 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3598 (clobber (reg:CC 33))]
3599 ""
3600 "sh\\t%0,%2"
3601 [(set_attr "op_type" "RX")])
3602
3603 (define_insn "*subsi3_sub"
3604 [(set (match_operand:SI 0 "register_operand" "=d")
3605 (minus:SI (match_operand:SI 1 "register_operand" "0")
3606 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3607 (clobber (reg:CC 33))]
3608 ""
3609 "sh\\t%0,%2"
3610 [(set_attr "op_type" "RX")])
3611
3612 (define_insn "subsi3"
3613 [(set (match_operand:SI 0 "register_operand" "=d,d")
3614 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3615 (match_operand:SI 2 "general_operand" "d,m")))
3616 (clobber (reg:CC 33))]
3617 ""
3618 "@
3619 sr\\t%0,%2
3620 s\\t%0,%2"
3621 [(set_attr "op_type" "RR,RX")])
3622
3623
3624 ;
3625 ; subdf3 instruction pattern(s).
3626 ;
3627
3628 (define_expand "subdf3"
3629 [(parallel
3630 [(set (match_operand:DF 0 "register_operand" "=f,f")
3631 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3632 (match_operand:DF 2 "general_operand" "f,m")))
3633 (clobber (reg:CC 33))])]
3634 "TARGET_HARD_FLOAT"
3635 "")
3636
3637 (define_insn "*subdf3"
3638 [(set (match_operand:DF 0 "register_operand" "=f,f")
3639 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3640 (match_operand:DF 2 "general_operand" "f,m")))
3641 (clobber (reg:CC 33))]
3642 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3643 "@
3644 sdbr\\t%0,%2
3645 sdb\\t%0,%2"
3646 [(set_attr "op_type" "RRE,RXE")
3647 (set_attr "type" "fsimpd,fsimpd")])
3648
3649 (define_insn "*subdf3_ibm"
3650 [(set (match_operand:DF 0 "register_operand" "=f,f")
3651 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3652 (match_operand:DF 2 "general_operand" "f,m")))
3653 (clobber (reg:CC 33))]
3654 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3655 "@
3656 sdr\\t%0,%2
3657 sd\\t%0,%2"
3658 [(set_attr "op_type" "RR,RX")
3659 (set_attr "type" "fsimpd,fsimpd")])
3660
3661 ;
3662 ; subsf3 instruction pattern(s).
3663 ;
3664
3665 (define_expand "subsf3"
3666 [(parallel
3667 [(set (match_operand:SF 0 "register_operand" "=f,f")
3668 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3669 (match_operand:SF 2 "general_operand" "f,m")))
3670 (clobber (reg:CC 33))])]
3671 "TARGET_HARD_FLOAT"
3672 "")
3673
3674 (define_insn "*subsf3"
3675 [(set (match_operand:SF 0 "register_operand" "=f,f")
3676 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3677 (match_operand:SF 2 "general_operand" "f,m")))
3678 (clobber (reg:CC 33))]
3679 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3680 "@
3681 sebr\\t%0,%2
3682 seb\\t%0,%2"
3683 [(set_attr "op_type" "RRE,RXE")
3684 (set_attr "type" "fsimps,fsimps")])
3685
3686 (define_insn "*subsf3_ibm"
3687 [(set (match_operand:SF 0 "register_operand" "=f,f")
3688 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3689 (match_operand:SF 2 "general_operand" "f,m")))
3690 (clobber (reg:CC 33))]
3691 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3692 "@
3693 ser\\t%0,%2
3694 se\\t%0,%2"
3695 [(set_attr "op_type" "RR,RX")
3696 (set_attr "type" "fsimps,fsimps")])
3697
3698
3699 ;;
3700 ;;- Multiply instructions.
3701 ;;
3702
3703 ;
3704 ; muldi3 instruction pattern(s).
3705 ;
3706
3707 (define_insn "*muldi3_sign"
3708 [(set (match_operand:DI 0 "register_operand" "=d,d")
3709 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3710 (match_operand:DI 1 "register_operand" "0,0")))]
3711 "TARGET_64BIT"
3712 "@
3713 msgfr\\t%0,%2
3714 msgf\\t%0,%2"
3715 [(set_attr "op_type" "RRE,RXE")
3716 (set_attr "type" "imul")])
3717
3718
3719 (define_insn "muldi3"
3720 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3721 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3722 (match_operand:DI 2 "general_operand" "d,K,m")))]
3723 "TARGET_64BIT"
3724 "@
3725 msgr\\t%0,%2
3726 mghi\\t%0,%h2
3727 msg\\t%0,%2"
3728 [(set_attr "op_type" "RRE,RI,RXE")
3729 (set_attr "type" "imul")])
3730
3731 ;
3732 ; mulsi3 instruction pattern(s).
3733 ;
3734
3735 (define_insn "mulsi3"
3736 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3737 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3738 (match_operand:SI 2 "general_operand" "d,K,m")))]
3739 ""
3740 "@
3741 msr\\t%0,%2
3742 mhi\\t%0,%h2
3743 ms\\t%0,%2"
3744 [(set_attr "op_type" "RRE,RI,RX")
3745 (set_attr "type" "imul")])
3746
3747 ;
3748 ; mulsidi3 instruction pattern(s).
3749 ;
3750
3751 (define_expand "mulsidi3"
3752 [(set (match_operand:DI 0 "register_operand" "")
3753 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3754 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3755 "!TARGET_64BIT"
3756 "
3757 {
3758 rtx insn;
3759
3760 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3761 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3762
3763 REG_NOTES (insn) =
3764 gen_rtx_EXPR_LIST (REG_EQUAL,
3765 gen_rtx_MULT (DImode,
3766 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3767 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3768 REG_NOTES (insn));
3769 DONE;
3770 }")
3771
3772 (define_insn "mulsi_6432"
3773 [(set (match_operand:DI 0 "register_operand" "=d,d")
3774 (mult:DI (sign_extend:DI
3775 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3776 (sign_extend:DI
3777 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3778 "!TARGET_64BIT"
3779 "@
3780 mr\\t%0,%2
3781 m\\t%0,%2"
3782 [(set_attr "op_type" "RR,RX")
3783 (set_attr "type" "imul")])
3784
3785 ;
3786 ; muldf3 instruction pattern(s).
3787 ;
3788
3789 (define_expand "muldf3"
3790 [(parallel
3791 [(set (match_operand:DF 0 "register_operand" "=f,f")
3792 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3793 (match_operand:DF 2 "general_operand" "f,m")))
3794 (clobber (reg:CC 33))])]
3795 "TARGET_HARD_FLOAT"
3796 "")
3797
3798 (define_insn "*muldf3"
3799 [(set (match_operand:DF 0 "register_operand" "=f,f")
3800 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3801 (match_operand:DF 2 "general_operand" "f,m")))
3802 (clobber (reg:CC 33))]
3803 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3804 "@
3805 mdbr\\t%0,%2
3806 mdb\\t%0,%2"
3807 [(set_attr "op_type" "RRE,RXE")
3808 (set_attr "type" "fmuld")])
3809
3810 (define_insn "*muldf3_ibm"
3811 [(set (match_operand:DF 0 "register_operand" "=f,f")
3812 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3813 (match_operand:DF 2 "general_operand" "f,m")))
3814 (clobber (reg:CC 33))]
3815 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3816 "@
3817 mdr\\t%0,%2
3818 md\\t%0,%2"
3819 [(set_attr "op_type" "RR,RX")
3820 (set_attr "type" "fmuld")])
3821
3822 ;
3823 ; mulsf3 instruction pattern(s).
3824 ;
3825
3826 (define_expand "mulsf3"
3827 [(parallel
3828 [(set (match_operand:SF 0 "register_operand" "=f,f")
3829 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3830 (match_operand:SF 2 "general_operand" "f,m")))
3831 (clobber (reg:CC 33))])]
3832 "TARGET_HARD_FLOAT"
3833 "")
3834
3835 (define_insn "*mulsf3"
3836 [(set (match_operand:SF 0 "register_operand" "=f,f")
3837 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3838 (match_operand:SF 2 "general_operand" "f,m")))
3839 (clobber (reg:CC 33))]
3840 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3841 "@
3842 meebr\\t%0,%2
3843 meeb\\t%0,%2"
3844 [(set_attr "op_type" "RRE,RXE")
3845 (set_attr "type" "fmuls")])
3846
3847 (define_insn "*mulsf3_ibm"
3848 [(set (match_operand:SF 0 "register_operand" "=f,f")
3849 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3850 (match_operand:SF 2 "general_operand" "f,m")))
3851 (clobber (reg:CC 33))]
3852 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3853 "@
3854 mer\\t%0,%2
3855 me\\t%0,%2"
3856 [(set_attr "op_type" "RR,RX")
3857 (set_attr "type" "fmuls")])
3858
3859
3860 ;;
3861 ;;- Divide and modulo instructions.
3862 ;;
3863
3864 ;
3865 ; divmoddi4 instruction pattern(s).
3866 ;
3867
3868 (define_expand "divmoddi4"
3869 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3870 (div:DI (match_operand:DI 1 "general_operand" "")
3871 (match_operand:DI 2 "general_operand" "")))
3872 (set (match_operand:DI 3 "general_operand" "")
3873 (mod:DI (match_dup 1) (match_dup 2)))])
3874 (clobber (match_dup 4))]
3875 "TARGET_64BIT"
3876 "
3877 {
3878 rtx insn, div_equal, mod_equal, equal;
3879
3880 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3881 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3882 equal = gen_rtx_IOR (TImode,
3883 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3884 gen_rtx_ASHIFT (TImode,
3885 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3886 GEN_INT (64)));
3887
3888 operands[4] = gen_reg_rtx(TImode);
3889 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3890 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3891 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3892 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3893 REG_NOTES (insn) =
3894 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3895
3896 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3897 REG_NOTES (insn) =
3898 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3899
3900 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3901 REG_NOTES (insn) =
3902 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3903
3904 DONE;
3905 }")
3906
3907 (define_insn "divmodtidi3"
3908 [(set (match_operand:TI 0 "register_operand" "=d,d")
3909 (ior:TI
3910 (zero_extend:TI
3911 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3912 (match_operand:DI 2 "general_operand" "d,m")))
3913 (ashift:TI
3914 (zero_extend:TI
3915 (mod:DI (truncate:DI (match_dup 1))
3916 (match_dup 2)))
3917 (const_int 64))))]
3918 "TARGET_64BIT"
3919 "@
3920 dsgr\\t%0,%2
3921 dsg\\t%0,%2"
3922 [(set_attr "op_type" "RRE,RXE")
3923 (set_attr "type" "idiv")])
3924
3925 (define_insn "divmodtisi3"
3926 [(set (match_operand:TI 0 "register_operand" "=d,d")
3927 (ior:TI
3928 (zero_extend:TI
3929 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3930 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3931 (ashift:TI
3932 (zero_extend:TI
3933 (mod:DI (truncate:DI (match_dup 1))
3934 (sign_extend:DI (match_dup 2))))
3935 (const_int 64))))]
3936 "TARGET_64BIT"
3937 "@
3938 dsgfr\\t%0,%2
3939 dsgf\\t%0,%2"
3940 [(set_attr "op_type" "RRE,RXE")
3941 (set_attr "type" "idiv")])
3942
3943 ;
3944 ; udivmoddi4 instruction pattern(s).
3945 ;
3946
3947 (define_expand "udivmoddi4"
3948 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3949 (udiv:DI (match_operand:DI 1 "general_operand" "")
3950 (match_operand:DI 2 "nonimmediate_operand" "")))
3951 (set (match_operand:DI 3 "general_operand" "")
3952 (umod:DI (match_dup 1) (match_dup 2)))])
3953 (clobber (match_dup 4))]
3954 "TARGET_64BIT"
3955 "
3956 {
3957 rtx insn, div_equal, mod_equal, equal;
3958
3959 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3960 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3961 equal = gen_rtx_IOR (TImode,
3962 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3963 gen_rtx_ASHIFT (TImode,
3964 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3965 GEN_INT (64)));
3966
3967 operands[4] = gen_reg_rtx(TImode);
3968 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3969 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3970 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3971 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3972 REG_NOTES (insn) =
3973 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3974
3975 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3976 REG_NOTES (insn) =
3977 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3978
3979 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3980 REG_NOTES (insn) =
3981 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3982
3983 DONE;
3984 }")
3985
3986 (define_insn "udivmodtidi3"
3987 [(set (match_operand:TI 0 "register_operand" "=d,d")
3988 (ior:TI (zero_extend:TI
3989 (truncate:DI
3990 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3991 (zero_extend:TI
3992 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3993 (ashift:TI
3994 (zero_extend:TI
3995 (truncate:DI
3996 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3997 (const_int 64))))]
3998 "TARGET_64BIT"
3999 "@
4000 dlgr\\t%0,%2
4001 dlg\\t%0,%2"
4002 [(set_attr "op_type" "RRE,RXE")
4003 (set_attr "type" "idiv")])
4004
4005 ;
4006 ; divmodsi4 instruction pattern(s).
4007 ;
4008
4009 (define_expand "divmodsi4"
4010 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4011 (div:SI (match_operand:SI 1 "general_operand" "")
4012 (match_operand:SI 2 "nonimmediate_operand" "")))
4013 (set (match_operand:SI 3 "general_operand" "")
4014 (mod:SI (match_dup 1) (match_dup 2)))])
4015 (clobber (match_dup 4))]
4016 "!TARGET_64BIT"
4017 "
4018 {
4019 rtx insn, div_equal, mod_equal, equal;
4020
4021 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4022 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4023 equal = gen_rtx_IOR (DImode,
4024 gen_rtx_ZERO_EXTEND (DImode, div_equal),
4025 gen_rtx_ASHIFT (DImode,
4026 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4027 GEN_INT (32)));
4028
4029 operands[4] = gen_reg_rtx(DImode);
4030 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4031 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4032 REG_NOTES (insn) =
4033 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4034
4035 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4036 REG_NOTES (insn) =
4037 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4038
4039 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4040 REG_NOTES (insn) =
4041 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4042
4043 DONE;
4044 }")
4045
4046 (define_insn "divmoddisi3"
4047 [(set (match_operand:DI 0 "register_operand" "=d,d")
4048 (ior:DI (zero_extend:DI
4049 (truncate:SI
4050 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4051 (sign_extend:DI
4052 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4053 (ashift:DI
4054 (zero_extend:DI
4055 (truncate:SI
4056 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4057 (const_int 32))))]
4058 "!TARGET_64BIT"
4059 "@
4060 dr\\t%0,%2
4061 d\\t%0,%2"
4062 [(set_attr "op_type" "RR,RX")
4063 (set_attr "type" "idiv")])
4064
4065 ;
4066 ; udivsi3 and umodsi3 instruction pattern(s).
4067 ;
4068
4069
4070 (define_expand "udivsi3"
4071 [(set (match_operand:SI 0 "register_operand" "=d")
4072 (udiv:SI (match_operand:SI 1 "general_operand" "")
4073 (match_operand:SI 2 "general_operand" "")))
4074 (clobber (match_dup 3))]
4075 "!TARGET_64BIT"
4076 "
4077 {
4078 rtx insn, udiv_equal, umod_equal, equal;
4079
4080 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4081 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4082 equal = gen_rtx_IOR (DImode,
4083 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4084 gen_rtx_ASHIFT (DImode,
4085 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4086 GEN_INT (32)));
4087
4088 operands[3] = gen_reg_rtx (DImode);
4089
4090 if (CONSTANT_P (operands[2]))
4091 {
4092 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4093 {
4094 rtx label1 = gen_label_rtx ();
4095
4096 operands[1] = make_safe_from (operands[1], operands[0]);
4097 emit_move_insn (operands[0], const0_rtx);
4098 emit_insn (gen_cmpsi (operands[1], operands[2]));
4099 emit_jump_insn (gen_bltu (label1));
4100 emit_move_insn (operands[0], const1_rtx);
4101 emit_label (label1);
4102 }
4103 else
4104 {
4105 operands[2] = force_reg (SImode, operands[2]);
4106 operands[2] = make_safe_from (operands[2], operands[0]);
4107
4108 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4109 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4110 operands[2]));
4111 REG_NOTES (insn) =
4112 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4113
4114 insn = emit_move_insn (operands[0],
4115 gen_lowpart (SImode, operands[3]));
4116 REG_NOTES (insn) =
4117 gen_rtx_EXPR_LIST (REG_EQUAL,
4118 udiv_equal, REG_NOTES (insn));
4119 }
4120 }
4121 else
4122 {
4123 rtx label1 = gen_label_rtx ();
4124 rtx label2 = gen_label_rtx ();
4125 rtx label3 = gen_label_rtx ();
4126
4127 operands[1] = force_reg (SImode, operands[1]);
4128 operands[1] = make_safe_from (operands[1], operands[0]);
4129 operands[2] = force_reg (SImode, operands[2]);
4130 operands[2] = make_safe_from (operands[2], operands[0]);
4131
4132 emit_move_insn (operands[0], const0_rtx);
4133 emit_insn (gen_cmpsi (operands[2], operands[1]));
4134 emit_jump_insn (gen_bgtu (label3));
4135 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4136 emit_jump_insn (gen_blt (label2));
4137 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4138 emit_jump_insn (gen_beq (label1));
4139 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4140 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4141 operands[2]));
4142 REG_NOTES (insn) =
4143 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4144
4145 insn = emit_move_insn (operands[0],
4146 gen_lowpart (SImode, operands[3]));
4147 REG_NOTES (insn) =
4148 gen_rtx_EXPR_LIST (REG_EQUAL,
4149 udiv_equal, REG_NOTES (insn));
4150 emit_jump (label3);
4151 emit_label (label1);
4152 emit_move_insn (operands[0], operands[1]);
4153 emit_jump (label3);
4154 emit_label (label2);
4155 emit_move_insn (operands[0], const1_rtx);
4156 emit_label (label3);
4157 }
4158 emit_move_insn (operands[0], operands[0]);
4159 DONE;
4160 }")
4161
4162 (define_expand "umodsi3"
4163 [(set (match_operand:SI 0 "register_operand" "=d")
4164 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4165 (match_operand:SI 2 "nonimmediate_operand" "")))
4166 (clobber (match_dup 3))]
4167 "!TARGET_64BIT"
4168 "
4169 {
4170 rtx insn, udiv_equal, umod_equal, equal;
4171
4172 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4173 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4174 equal = gen_rtx_IOR (DImode,
4175 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4176 gen_rtx_ASHIFT (DImode,
4177 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4178 GEN_INT (32)));
4179
4180 operands[3] = gen_reg_rtx (DImode);
4181
4182 if (CONSTANT_P (operands[2]))
4183 {
4184 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4185 {
4186 rtx label1 = gen_label_rtx ();
4187
4188 operands[1] = make_safe_from (operands[1], operands[0]);
4189 emit_move_insn (operands[0], operands[1]);
4190 emit_insn (gen_cmpsi (operands[0], operands[2]));
4191 emit_jump_insn (gen_bltu (label1));
4192 emit_insn (gen_abssi2 (operands[0], operands[2]));
4193 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4194 emit_label (label1);
4195 }
4196 else
4197 {
4198 operands[2] = force_reg (SImode, operands[2]);
4199 operands[2] = make_safe_from (operands[2], operands[0]);
4200
4201 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4202 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4203 operands[2]));
4204 REG_NOTES (insn) =
4205 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4206
4207 insn = emit_move_insn (operands[0],
4208 gen_highpart (SImode, operands[3]));
4209 REG_NOTES (insn) =
4210 gen_rtx_EXPR_LIST (REG_EQUAL,
4211 umod_equal, REG_NOTES (insn));
4212 }
4213 }
4214 else
4215 {
4216 rtx label1 = gen_label_rtx ();
4217 rtx label2 = gen_label_rtx ();
4218 rtx label3 = gen_label_rtx ();
4219
4220 operands[1] = force_reg (SImode, operands[1]);
4221 operands[1] = make_safe_from (operands[1], operands[0]);
4222 operands[2] = force_reg (SImode, operands[2]);
4223 operands[2] = make_safe_from (operands[2], operands[0]);
4224
4225 emit_move_insn(operands[0], operands[1]);
4226 emit_insn (gen_cmpsi (operands[2], operands[1]));
4227 emit_jump_insn (gen_bgtu (label3));
4228 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4229 emit_jump_insn (gen_blt (label2));
4230 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4231 emit_jump_insn (gen_beq (label1));
4232 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4233 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4234 operands[2]));
4235 REG_NOTES (insn) =
4236 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4237
4238 insn = emit_move_insn (operands[0],
4239 gen_highpart (SImode, operands[3]));
4240 REG_NOTES (insn) =
4241 gen_rtx_EXPR_LIST (REG_EQUAL,
4242 umod_equal, REG_NOTES (insn));
4243 emit_jump (label3);
4244 emit_label (label1);
4245 emit_move_insn (operands[0], const0_rtx);
4246 emit_jump (label3);
4247 emit_label (label2);
4248 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4249 emit_label (label3);
4250 }
4251 DONE;
4252 }")
4253
4254 ;
4255 ; divdf3 instruction pattern(s).
4256 ;
4257
4258 (define_expand "divdf3"
4259 [(parallel
4260 [(set (match_operand:DF 0 "register_operand" "=f,f")
4261 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4262 (match_operand:DF 2 "general_operand" "f,m")))
4263 (clobber (reg:CC 33))])]
4264 "TARGET_HARD_FLOAT"
4265 "")
4266
4267 (define_insn "*divdf3"
4268 [(set (match_operand:DF 0 "register_operand" "=f,f")
4269 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4270 (match_operand:DF 2 "general_operand" "f,m")))
4271 (clobber (reg:CC 33))]
4272 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4273 "@
4274 ddbr\\t%0,%2
4275 ddb\\t%0,%2"
4276 [(set_attr "op_type" "RRE,RXE")
4277 (set_attr "type" "fdivd")])
4278
4279 (define_insn "*divdf3_ibm"
4280 [(set (match_operand:DF 0 "register_operand" "=f,f")
4281 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4282 (match_operand:DF 2 "general_operand" "f,m")))
4283 (clobber (reg:CC 33))]
4284 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4285 "@
4286 ddr\\t%0,%2
4287 dd\\t%0,%2"
4288 [(set_attr "op_type" "RR,RX")
4289 (set_attr "type" "fdivd")])
4290
4291 ;
4292 ; divsf3 instruction pattern(s).
4293 ;
4294
4295 (define_expand "divsf3"
4296 [(parallel
4297 [(set (match_operand:SF 0 "register_operand" "=f,f")
4298 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4299 (match_operand:SF 2 "general_operand" "f,m")))
4300 (clobber (reg:CC 33))])]
4301 "TARGET_HARD_FLOAT"
4302 "")
4303
4304 (define_insn "*divsf3"
4305 [(set (match_operand:SF 0 "register_operand" "=f,f")
4306 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4307 (match_operand:SF 2 "general_operand" "f,m")))
4308 (clobber (reg:CC 33))]
4309 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4310 "@
4311 debr\\t%0,%2
4312 deb\\t%0,%2"
4313 [(set_attr "op_type" "RRE,RXE")
4314 (set_attr "type" "fdivs")])
4315
4316 (define_insn "*divsf3"
4317 [(set (match_operand:SF 0 "register_operand" "=f,f")
4318 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4319 (match_operand:SF 2 "general_operand" "f,m")))
4320 (clobber (reg:CC 33))]
4321 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4322 "@
4323 der\\t%0,%2
4324 de\\t%0,%2"
4325 [(set_attr "op_type" "RR,RX")
4326 (set_attr "type" "fdivs")])
4327
4328
4329 ;;
4330 ;;- And instructions.
4331 ;;
4332
4333 ;
4334 ; anddi3 instruction pattern(s).
4335 ;
4336
4337 (define_insn "*anddi3_cc"
4338 [(set (reg 33)
4339 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4340 (match_operand:DI 2 "general_operand" "d,m"))
4341 (const_int 0)))
4342 (set (match_operand:DI 0 "register_operand" "=d,d")
4343 (and:DI (match_dup 1) (match_dup 2)))]
4344 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4345 "@
4346 ngr\\t%0,%2
4347 ng\\t%0,%2"
4348 [(set_attr "op_type" "RRE,RXE")])
4349
4350 (define_insn "*anddi3_cconly"
4351 [(set (reg 33)
4352 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4353 (match_operand:DI 2 "general_operand" "d,m"))
4354 (const_int 0)))
4355 (clobber (match_scratch:DI 0 "=d,d"))]
4356 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4357 "@
4358 ngr\\t%0,%2
4359 ng\\t%0,%2"
4360 [(set_attr "op_type" "RRE,RXE")])
4361
4362 (define_insn "*anddi3_ni"
4363 [(set (match_operand:DI 0 "register_operand" "=d")
4364 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4365 (match_operand:DI 2 "immediate_operand" "n")))
4366 (clobber (reg:CC 33))]
4367 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4368 "*
4369 {
4370 int part = s390_single_hi (operands[2], DImode, -1);
4371 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4372
4373 switch (part)
4374 {
4375 case 0: return \"nihh\\t%0,%x2\";
4376 case 1: return \"nihl\\t%0,%x2\";
4377 case 2: return \"nilh\\t%0,%x2\";
4378 case 3: return \"nill\\t%0,%x2\";
4379 default: abort ();
4380 }
4381 }"
4382 [(set_attr "op_type" "RI")])
4383
4384 (define_insn "anddi3"
4385 [(set (match_operand:DI 0 "register_operand" "=d,d")
4386 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4387 (match_operand:DI 2 "general_operand" "d,m")))
4388 (clobber (reg:CC 33))]
4389 "TARGET_64BIT"
4390 "@
4391 ngr\\t%0,%2
4392 ng\\t%0,%2"
4393 [(set_attr "op_type" "RRE,RXE")])
4394
4395 (define_insn "*anddi3_ss"
4396 [(set (match_operand:DI 0 "s_operand" "=Q")
4397 (and:DI (match_dup 0)
4398 (match_operand:DI 1 "s_imm_operand" "Q")))
4399 (clobber (reg:CC 33))]
4400 ""
4401 "nc\\t%O0(8,%R0),%1"
4402 [(set_attr "op_type" "SS")])
4403
4404 (define_insn "*anddi3_ss_inv"
4405 [(set (match_operand:DI 0 "s_operand" "=Q")
4406 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4407 (match_dup 0)))
4408 (clobber (reg:CC 33))]
4409 ""
4410 "nc\\t%O0(8,%R0),%1"
4411 [(set_attr "op_type" "SS")])
4412
4413 ;
4414 ; andsi3 instruction pattern(s).
4415 ;
4416
4417 (define_insn "*andsi3_cc"
4418 [(set (reg 33)
4419 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4420 (match_operand:SI 2 "general_operand" "d,m"))
4421 (const_int 0)))
4422 (set (match_operand:SI 0 "register_operand" "=d,d")
4423 (and:SI (match_dup 1) (match_dup 2)))]
4424 "s390_match_ccmode(insn, CCTmode)"
4425 "@
4426 nr\\t%0,%2
4427 n\\t%0,%2"
4428 [(set_attr "op_type" "RR,RX")])
4429
4430 (define_insn "*andsi3_cconly"
4431 [(set (reg 33)
4432 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4433 (match_operand:SI 2 "general_operand" "d,m"))
4434 (const_int 0)))
4435 (clobber (match_scratch:SI 0 "=d,d"))]
4436 "s390_match_ccmode(insn, CCTmode)"
4437 "@
4438 nr\\t%0,%2
4439 n\\t%0,%2"
4440 [(set_attr "op_type" "RR,RX")])
4441
4442 (define_insn "*andsi3_ni"
4443 [(set (match_operand:SI 0 "register_operand" "=d")
4444 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4445 (match_operand:SI 2 "immediate_operand" "n")))
4446 (clobber (reg:CC 33))]
4447 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4448 "*
4449 {
4450 int part = s390_single_hi (operands[2], SImode, -1);
4451 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4452
4453 switch (part)
4454 {
4455 case 0: return \"nilh\\t%0,%x2\";
4456 case 1: return \"nill\\t%0,%x2\";
4457 default: abort ();
4458 }
4459 }"
4460 [(set_attr "op_type" "RI")])
4461
4462 (define_insn "andsi3"
4463 [(set (match_operand:SI 0 "register_operand" "=d,d")
4464 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4465 (match_operand:SI 2 "general_operand" "d,m")))
4466 (clobber (reg:CC 33))]
4467 ""
4468 "@
4469 nr\\t%0,%2
4470 n\\t%0,%2"
4471 [(set_attr "op_type" "RR,RX")])
4472
4473 (define_insn "*andsi3_ss"
4474 [(set (match_operand:SI 0 "s_operand" "=Q")
4475 (and:SI (match_dup 0)
4476 (match_operand:SI 1 "s_imm_operand" "Q")))
4477 (clobber (reg:CC 33))]
4478 ""
4479 "nc\\t%O0(4,%R0),%1"
4480 [(set_attr "op_type" "SS")])
4481
4482 (define_insn "*andsi3_ss_inv"
4483 [(set (match_operand:SI 0 "s_operand" "=Q")
4484 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4485 (match_dup 0)))
4486 (clobber (reg:CC 33))]
4487 ""
4488 "nc\\t%O0(4,%R0),%1"
4489 [(set_attr "op_type" "SS")])
4490
4491 ;
4492 ; andhi3 instruction pattern(s).
4493 ;
4494
4495 (define_insn "*andhi3_ni"
4496 [(set (match_operand:HI 0 "register_operand" "=d,d")
4497 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4498 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4499 (clobber (reg:CC 33))]
4500 "TARGET_64BIT"
4501 "@
4502 nr\\t%0,%2
4503 nill\\t%0,%x2"
4504 [(set_attr "op_type" "RR,RI")])
4505
4506 (define_insn "andhi3"
4507 [(set (match_operand:HI 0 "register_operand" "=d")
4508 (and:HI (match_operand:HI 1 "register_operand" "%0")
4509 (match_operand:HI 2 "nonmemory_operand" "d")))
4510 (clobber (reg:CC 33))]
4511 ""
4512 "nr\\t%0,%2"
4513 [(set_attr "op_type" "RR")])
4514
4515 (define_insn "*andhi3_ss"
4516 [(set (match_operand:HI 0 "s_operand" "=Q")
4517 (and:HI (match_dup 0)
4518 (match_operand:HI 1 "s_imm_operand" "Q")))
4519 (clobber (reg:CC 33))]
4520 ""
4521 "nc\\t%O0(2,%R0),%1"
4522 [(set_attr "op_type" "SS")])
4523
4524 (define_insn "*andhi3_ss_inv"
4525 [(set (match_operand:HI 0 "s_operand" "=Q")
4526 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4527 (match_dup 0)))
4528 (clobber (reg:CC 33))]
4529 ""
4530 "nc\\t%O0(2,%R0),%1"
4531 [(set_attr "op_type" "SS")])
4532
4533 ;
4534 ; andqi3 instruction pattern(s).
4535 ;
4536
4537 (define_insn "*andqi3_ni"
4538 [(set (match_operand:QI 0 "register_operand" "=d,d")
4539 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4540 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4541 (clobber (reg:CC 33))]
4542 "TARGET_64BIT"
4543 "@
4544 nr\\t%0,%2
4545 nill\\t%0,%b2"
4546 [(set_attr "op_type" "RR,RI")])
4547
4548 (define_insn "andqi3"
4549 [(set (match_operand:QI 0 "register_operand" "=d")
4550 (and:QI (match_operand:QI 1 "register_operand" "%0")
4551 (match_operand:QI 2 "nonmemory_operand" "d")))
4552 (clobber (reg:CC 33))]
4553 ""
4554 "nr\\t%0,%2"
4555 [(set_attr "op_type" "RR")])
4556
4557 (define_insn "*andqi3_ss"
4558 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4559 (and:QI (match_dup 0)
4560 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4561 (clobber (reg:CC 33))]
4562 ""
4563 "@
4564 ni\\t%0,%b1
4565 nc\\t%O0(1,%R0),%1"
4566 [(set_attr "op_type" "SI,SS")])
4567
4568 (define_insn "*andqi3_ss_inv"
4569 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4570 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4571 (match_dup 0)))
4572 (clobber (reg:CC 33))]
4573 ""
4574 "@
4575 ni\\t%0,%b1
4576 nc\\t%O0(1,%R0),%1"
4577 [(set_attr "op_type" "SI,SS")])
4578
4579
4580 ;;
4581 ;;- Bit set (inclusive or) instructions.
4582 ;;
4583
4584 ;
4585 ; iordi3 instruction pattern(s).
4586 ;
4587
4588 (define_insn "*iordi3_cc"
4589 [(set (reg 33)
4590 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4591 (match_operand:DI 2 "general_operand" "d,m"))
4592 (const_int 0)))
4593 (set (match_operand:DI 0 "register_operand" "=d,d")
4594 (ior:DI (match_dup 1) (match_dup 2)))]
4595 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4596 "@
4597 ogr\\t%0,%2
4598 og\\t%0,%2"
4599 [(set_attr "op_type" "RRE,RXE")])
4600
4601 (define_insn "*iordi3_cconly"
4602 [(set (reg 33)
4603 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4604 (match_operand:DI 2 "general_operand" "d,m"))
4605 (const_int 0)))
4606 (clobber (match_scratch:DI 0 "=d,d"))]
4607 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4608 "@
4609 ogr\\t%0,%2
4610 og\\t%0,%2"
4611 [(set_attr "op_type" "RRE,RXE")])
4612
4613 (define_insn "*iordi3_oi"
4614 [(set (match_operand:DI 0 "register_operand" "=d")
4615 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4616 (match_operand:DI 2 "immediate_operand" "n")))
4617 (clobber (reg:CC 33))]
4618 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4619 "*
4620 {
4621 int part = s390_single_hi (operands[2], DImode, 0);
4622 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4623
4624 switch (part)
4625 {
4626 case 0: return \"oihh\\t%0,%x2\";
4627 case 1: return \"oihl\\t%0,%x2\";
4628 case 2: return \"oilh\\t%0,%x2\";
4629 case 3: return \"oill\\t%0,%x2\";
4630 default: abort ();
4631 }
4632 }"
4633 [(set_attr "op_type" "RI")])
4634
4635 (define_insn "iordi3"
4636 [(set (match_operand:DI 0 "register_operand" "=d,d")
4637 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4638 (match_operand:DI 2 "general_operand" "d,m")))
4639 (clobber (reg:CC 33))]
4640 "TARGET_64BIT"
4641 "@
4642 ogr\\t%0,%2
4643 og\\t%0,%2"
4644 [(set_attr "op_type" "RRE,RXE")])
4645
4646 (define_insn "*iordi3_ss"
4647 [(set (match_operand:DI 0 "s_operand" "=Q")
4648 (ior:DI (match_dup 0)
4649 (match_operand:DI 1 "s_imm_operand" "Q")))
4650 (clobber (reg:CC 33))]
4651 ""
4652 "oc\\t%O0(8,%R0),%1"
4653 [(set_attr "op_type" "SS")])
4654
4655 (define_insn "*iordi3_ss_inv"
4656 [(set (match_operand:DI 0 "s_operand" "=Q")
4657 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4658 (match_dup 0)))
4659 (clobber (reg:CC 33))]
4660 ""
4661 "oc\\t%O0(8,%R0),%1"
4662 [(set_attr "op_type" "SS")])
4663
4664 ;
4665 ; iorsi3 instruction pattern(s).
4666 ;
4667
4668 (define_insn "*iorsi3_cc"
4669 [(set (reg 33)
4670 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4671 (match_operand:SI 2 "general_operand" "d,m"))
4672 (const_int 0)))
4673 (set (match_operand:SI 0 "register_operand" "=d,d")
4674 (ior:SI (match_dup 1) (match_dup 2)))]
4675 "s390_match_ccmode(insn, CCTmode)"
4676 "@
4677 or\\t%0,%2
4678 o\\t%0,%2"
4679 [(set_attr "op_type" "RR,RX")])
4680
4681 (define_insn "*iorsi3_cconly"
4682 [(set (reg 33)
4683 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4684 (match_operand:SI 2 "general_operand" "d,m"))
4685 (const_int 0)))
4686 (clobber (match_scratch:SI 0 "=d,d"))]
4687 "s390_match_ccmode(insn, CCTmode)"
4688 "@
4689 or\\t%0,%2
4690 o\\t%0,%2"
4691 [(set_attr "op_type" "RR,RX")])
4692
4693 (define_insn "*iorsi3_oi"
4694 [(set (match_operand:SI 0 "register_operand" "=d")
4695 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4696 (match_operand:SI 2 "immediate_operand" "n")))
4697 (clobber (reg:CC 33))]
4698 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4699 "*
4700 {
4701 int part = s390_single_hi (operands[2], SImode, 0);
4702 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4703
4704 switch (part)
4705 {
4706 case 0: return \"oilh\\t%0,%x2\";
4707 case 1: return \"oill\\t%0,%x2\";
4708 default: abort ();
4709 }
4710 }"
4711 [(set_attr "op_type" "RI")])
4712
4713 (define_insn "iorsi3"
4714 [(set (match_operand:SI 0 "register_operand" "=d,d")
4715 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4716 (match_operand:SI 2 "general_operand" "d,m")))
4717 (clobber (reg:CC 33))]
4718 ""
4719 "@
4720 or\\t%0,%2
4721 o\\t%0,%2"
4722 [(set_attr "op_type" "RR,RX")])
4723
4724 (define_insn "*iorsi3_ss"
4725 [(set (match_operand:SI 0 "s_operand" "=Q")
4726 (ior:SI (match_dup 0)
4727 (match_operand:SI 1 "s_imm_operand" "Q")))
4728 (clobber (reg:CC 33))]
4729 ""
4730 "oc\\t%O0(4,%R0),%1"
4731 [(set_attr "op_type" "SS")])
4732
4733 (define_insn "*iorsi3_ss_inv"
4734 [(set (match_operand:SI 0 "s_operand" "=Q")
4735 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4736 (match_dup 0)))
4737 (clobber (reg:CC 33))]
4738 ""
4739 "oc\\t%O0(4,%R0),%1"
4740 [(set_attr "op_type" "SS")])
4741
4742 ;
4743 ; iorhi3 instruction pattern(s).
4744 ;
4745
4746 (define_insn "*iorhi3_oi"
4747 [(set (match_operand:HI 0 "register_operand" "=d,d")
4748 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4749 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4750 (clobber (reg:CC 33))]
4751 "TARGET_64BIT"
4752 "@
4753 or\\t%0,%2
4754 oill\\t%0,%x2"
4755 [(set_attr "op_type" "RR,RI")])
4756
4757 (define_insn "iorhi3"
4758 [(set (match_operand:HI 0 "register_operand" "=d")
4759 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4760 (match_operand:HI 2 "nonmemory_operand" "d")))
4761 (clobber (reg:CC 33))]
4762 ""
4763 "or\\t%0,%2"
4764 [(set_attr "op_type" "RR")])
4765
4766 (define_insn "*iorhi3_ss"
4767 [(set (match_operand:HI 0 "s_operand" "=Q")
4768 (ior:HI (match_dup 0)
4769 (match_operand:HI 1 "s_imm_operand" "Q")))
4770 (clobber (reg:CC 33))]
4771 ""
4772 "oc\\t%O0(2,%R0),%1"
4773 [(set_attr "op_type" "SS")])
4774
4775 (define_insn "*iorhi3_ss_inv"
4776 [(set (match_operand:HI 0 "s_operand" "=Q")
4777 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4778 (match_dup 0)))
4779 (clobber (reg:CC 33))]
4780 ""
4781 "oc\\t%O0(2,%R0),%1"
4782 [(set_attr "op_type" "SS")])
4783
4784 ;
4785 ; iorqi3 instruction pattern(s).
4786 ;
4787
4788 (define_insn "*iorqi3_oi"
4789 [(set (match_operand:QI 0 "register_operand" "=d,d")
4790 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4791 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4792 (clobber (reg:CC 33))]
4793 "TARGET_64BIT"
4794 "@
4795 or\\t%0,%2
4796 oill\\t%0,%b2"
4797 [(set_attr "op_type" "RR,RI")])
4798
4799 (define_insn "iorqi3"
4800 [(set (match_operand:QI 0 "register_operand" "=d")
4801 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4802 (match_operand:QI 2 "nonmemory_operand" "d")))
4803 (clobber (reg:CC 33))]
4804 ""
4805 "or\\t%0,%2"
4806 [(set_attr "op_type" "RR")])
4807
4808 (define_insn "*iorqi3_ss"
4809 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4810 (ior:QI (match_dup 0)
4811 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4812 (clobber (reg:CC 33))]
4813 ""
4814 "@
4815 oi\\t%0,%b1
4816 oc\\t%O0(1,%R0),%1"
4817 [(set_attr "op_type" "SI,SS")])
4818
4819 (define_insn "*iorqi3_ss_inv"
4820 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4821 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4822 (match_dup 0)))
4823 (clobber (reg:CC 33))]
4824 ""
4825 "@
4826 oi\\t%0,%b1
4827 oc\\t%O0(1,%R0),%1"
4828 [(set_attr "op_type" "SI,SS")])
4829
4830
4831 ;;
4832 ;;- Xor instructions.
4833 ;;
4834
4835 ;
4836 ; xordi3 instruction pattern(s).
4837 ;
4838
4839 (define_insn "*xordi3_cc"
4840 [(set (reg 33)
4841 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4842 (match_operand:DI 2 "general_operand" "d,m"))
4843 (const_int 0)))
4844 (set (match_operand:DI 0 "register_operand" "=d,d")
4845 (xor:DI (match_dup 1) (match_dup 2)))]
4846 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4847 "@
4848 xgr\\t%0,%2
4849 xg\\t%0,%2"
4850 [(set_attr "op_type" "RRE,RXE")])
4851
4852 (define_insn "*xordi3_cconly"
4853 [(set (reg 33)
4854 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4855 (match_operand:DI 2 "general_operand" "d,m"))
4856 (const_int 0)))
4857 (clobber (match_scratch:DI 0 "=d,d"))]
4858 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4859 "@
4860 xgr\\t%0,%2
4861 xr\\t%0,%2"
4862 [(set_attr "op_type" "RRE,RXE")])
4863
4864 (define_insn "xordi3"
4865 [(set (match_operand:DI 0 "register_operand" "=d,d")
4866 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4867 (match_operand:DI 2 "general_operand" "d,m")))
4868 (clobber (reg:CC 33))]
4869 "TARGET_64BIT"
4870 "@
4871 xgr\\t%0,%2
4872 xg\\t%0,%2"
4873 [(set_attr "op_type" "RRE,RXE")])
4874
4875 (define_insn "*xordi3_ss"
4876 [(set (match_operand:DI 0 "s_operand" "=Q")
4877 (xor:DI (match_dup 0)
4878 (match_operand:DI 1 "s_imm_operand" "Q")))
4879 (clobber (reg:CC 33))]
4880 ""
4881 "xc\\t%O0(8,%R0),%1"
4882 [(set_attr "op_type" "SS")])
4883
4884 (define_insn "*xordi3_ss_inv"
4885 [(set (match_operand:DI 0 "s_operand" "=Q")
4886 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4887 (match_dup 0)))
4888 (clobber (reg:CC 33))]
4889 ""
4890 "xc\\t%O0(8,%R0),%1"
4891 [(set_attr "op_type" "SS")])
4892
4893 ;
4894 ; xorsi3 instruction pattern(s).
4895 ;
4896
4897 (define_insn "*xorsi3_cc"
4898 [(set (reg 33)
4899 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4900 (match_operand:SI 2 "general_operand" "d,m"))
4901 (const_int 0)))
4902 (set (match_operand:SI 0 "register_operand" "=d,d")
4903 (xor:SI (match_dup 1) (match_dup 2)))]
4904 "s390_match_ccmode(insn, CCTmode)"
4905 "@
4906 xr\\t%0,%2
4907 x\\t%0,%2"
4908 [(set_attr "op_type" "RR,RX")])
4909
4910 (define_insn "*xorsi3_cconly"
4911 [(set (reg 33)
4912 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4913 (match_operand:SI 2 "general_operand" "d,m"))
4914 (const_int 0)))
4915 (clobber (match_scratch:SI 0 "=d,d"))]
4916 "s390_match_ccmode(insn, CCTmode)"
4917 "@
4918 xr\\t%0,%2
4919 x\\t%0,%2"
4920 [(set_attr "op_type" "RR,RX")])
4921
4922 (define_insn "xorsi3"
4923 [(set (match_operand:SI 0 "register_operand" "=d,d")
4924 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4925 (match_operand:SI 2 "general_operand" "d,m")))
4926 (clobber (reg:CC 33))]
4927 ""
4928 "@
4929 xr\\t%0,%2
4930 x\\t%0,%2"
4931 [(set_attr "op_type" "RR,RX")])
4932
4933 (define_insn "*xorsi3_ss"
4934 [(set (match_operand:SI 0 "s_operand" "=Q")
4935 (xor:SI (match_dup 0)
4936 (match_operand:SI 1 "s_imm_operand" "Q")))
4937 (clobber (reg:CC 33))]
4938 ""
4939 "xc\\t%O0(4,%R0),%1"
4940 [(set_attr "op_type" "SS")])
4941
4942 (define_insn "*xorsi3_ss_inv"
4943 [(set (match_operand:SI 0 "s_operand" "=Q")
4944 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4945 (match_dup 0)))
4946 (clobber (reg:CC 33))]
4947 ""
4948 "xc\\t%O0(4,%R0),%1"
4949 [(set_attr "op_type" "SS")])
4950
4951 ;
4952 ; xorhi3 instruction pattern(s).
4953 ;
4954
4955 (define_insn "xorhi3"
4956 [(set (match_operand:HI 0 "register_operand" "=d")
4957 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4958 (match_operand:HI 2 "nonmemory_operand" "d")))
4959 (clobber (reg:CC 33))]
4960 ""
4961 "xr\\t%0,%2"
4962 [(set_attr "op_type" "RR")
4963 (set_attr "atype" "reg")])
4964
4965 (define_insn "*xorhi3_ss"
4966 [(set (match_operand:HI 0 "s_operand" "=Q")
4967 (xor:HI (match_dup 0)
4968 (match_operand:HI 1 "s_imm_operand" "Q")))
4969 (clobber (reg:CC 33))]
4970 ""
4971 "xc\\t%O0(2,%R0),%1"
4972 [(set_attr "op_type" "SS")])
4973
4974 (define_insn "*xorhi3_ss_inv"
4975 [(set (match_operand:HI 0 "s_operand" "=Q")
4976 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4977 (match_dup 0)))
4978 (clobber (reg:CC 33))]
4979 ""
4980 "xc\\t%O0(2,%R0),%1"
4981 [(set_attr "op_type" "SS")])
4982
4983 ;
4984 ; xorqi3 instruction pattern(s).
4985 ;
4986
4987 (define_insn "xorqi3"
4988 [(set (match_operand:QI 0 "register_operand" "=d")
4989 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4990 (match_operand:QI 2 "nonmemory_operand" "d")))
4991 (clobber (reg:CC 33))]
4992 ""
4993 "xr\\t%0,%2"
4994 [(set_attr "op_type" "RR")])
4995
4996 (define_insn "*xorqi3_ss"
4997 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4998 (xor:QI (match_dup 0)
4999 (match_operand:QI 1 "s_imm_operand" "n,Q")))
5000 (clobber (reg:CC 33))]
5001 ""
5002 "@
5003 xi\\t%0,%b1
5004 xc\\t%O0(1,%R0),%1"
5005 [(set_attr "op_type" "SI,SS")])
5006
5007 (define_insn "*xorqi3_ss_inv"
5008 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5009 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
5010 (match_dup 0)))
5011 (clobber (reg:CC 33))]
5012 ""
5013 "@
5014 xi\\t%0,%b1
5015 xc\\t%O0(1,%R0),%1"
5016 [(set_attr "op_type" "SI,SS")])
5017
5018
5019 ;;
5020 ;;- Negate instructions.
5021 ;;
5022
5023 ;
5024 ; negdi2 instruction pattern(s).
5025 ;
5026
5027 (define_expand "negdi2"
5028 [(parallel
5029 [(set (match_operand:DI 0 "register_operand" "=d")
5030 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5031 (clobber (reg:CC 33))])]
5032 ""
5033 "")
5034
5035 (define_insn "*negdi2_64"
5036 [(set (match_operand:DI 0 "register_operand" "=d")
5037 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5038 (clobber (reg:CC 33))]
5039 "TARGET_64BIT"
5040 "lcgr\\t%0,%1"
5041 [(set_attr "op_type" "RR")])
5042
5043 (define_insn "*negdi2_31"
5044 [(set (match_operand:DI 0 "register_operand" "=d")
5045 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5046 (clobber (reg:CC 33))]
5047 "!TARGET_64BIT"
5048 "*
5049 {
5050 rtx xop[1];
5051 xop[0] = gen_label_rtx ();
5052 output_asm_insn (\"lcr\\t%0,%1\", operands);
5053 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5054 output_asm_insn (\"je\\t%l0\", xop);
5055 output_asm_insn (\"bctr\\t%0,0\", operands);
5056 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5057 CODE_LABEL_NUMBER (xop[0]));
5058 return \"\";
5059 }"
5060 [(set_attr "op_type" "NN")
5061 (set_attr "type" "other")
5062 (set_attr "length" "10")])
5063
5064 ;
5065 ; negsi2 instruction pattern(s).
5066 ;
5067
5068 (define_insn "negsi2"
5069 [(set (match_operand:SI 0 "register_operand" "=d")
5070 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5071 (clobber (reg:CC 33))]
5072 ""
5073 "lcr\\t%0,%1"
5074 [(set_attr "op_type" "RR")])
5075
5076 ;
5077 ; negdf2 instruction pattern(s).
5078 ;
5079
5080 (define_expand "negdf2"
5081 [(parallel
5082 [(set (match_operand:DF 0 "register_operand" "=f")
5083 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5084 (clobber (reg:CC 33))])]
5085 "TARGET_HARD_FLOAT"
5086 "")
5087
5088 (define_insn "*negdf2"
5089 [(set (match_operand:DF 0 "register_operand" "=f")
5090 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5091 (clobber (reg:CC 33))]
5092 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5093 "lcdbr\\t%0,%1"
5094 [(set_attr "op_type" "RRE")
5095 (set_attr "type" "fsimpd")])
5096
5097 (define_insn "*negdf2_ibm"
5098 [(set (match_operand:DF 0 "register_operand" "=f")
5099 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5100 (clobber (reg:CC 33))]
5101 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5102 "lcdr\\t%0,%1"
5103 [(set_attr "op_type" "RR")
5104 (set_attr "type" "fsimpd")])
5105
5106 ;
5107 ; negsf2 instruction pattern(s).
5108 ;
5109
5110 (define_expand "negsf2"
5111 [(parallel
5112 [(set (match_operand:SF 0 "register_operand" "=f")
5113 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5114 (clobber (reg:CC 33))])]
5115 "TARGET_HARD_FLOAT"
5116 "")
5117
5118 (define_insn "*negsf2"
5119 [(set (match_operand:SF 0 "register_operand" "=f")
5120 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5121 (clobber (reg:CC 33))]
5122 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5123 "lcebr\\t%0,%1"
5124 [(set_attr "op_type" "RRE")
5125 (set_attr "type" "fsimps")])
5126
5127 (define_insn "*negsf2"
5128 [(set (match_operand:SF 0 "register_operand" "=f")
5129 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5130 (clobber (reg:CC 33))]
5131 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5132 "lcer\\t%0,%1"
5133 [(set_attr "op_type" "RR")
5134 (set_attr "type" "fsimps")])
5135
5136
5137 ;;
5138 ;;- Absolute value instructions.
5139 ;;
5140
5141 ;
5142 ; absdi2 instruction pattern(s).
5143 ;
5144
5145 (define_insn "absdi2"
5146 [(set (match_operand:DI 0 "register_operand" "=d")
5147 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5148 (clobber (reg:CC 33))]
5149 "TARGET_64BIT"
5150 "lpgr\\t%0,%1"
5151 [(set_attr "op_type" "RRE")])
5152
5153 ;
5154 ; abssi2 instruction pattern(s).
5155 ;
5156
5157 (define_insn "abssi2"
5158 [(set (match_operand:SI 0 "register_operand" "=d")
5159 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5160 (clobber (reg:CC 33))]
5161 ""
5162 "lpr\\t%0,%1"
5163 [(set_attr "op_type" "RR")])
5164
5165 ;
5166 ; absdf2 instruction pattern(s).
5167 ;
5168
5169 (define_expand "absdf2"
5170 [(parallel
5171 [(set (match_operand:DF 0 "register_operand" "=f")
5172 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5173 (clobber (reg:CC 33))])]
5174 "TARGET_HARD_FLOAT"
5175 "")
5176
5177 (define_insn "*absdf2"
5178 [(set (match_operand:DF 0 "register_operand" "=f")
5179 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5180 (clobber (reg:CC 33))]
5181 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5182 "lpdbr\\t%0,%1"
5183 [(set_attr "op_type" "RRE")
5184 (set_attr "type" "fsimpd")])
5185
5186 (define_insn "*absdf2_ibm"
5187 [(set (match_operand:DF 0 "register_operand" "=f")
5188 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5189 (clobber (reg:CC 33))]
5190 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5191 "lpdr\\t%0,%1"
5192 [(set_attr "op_type" "RR")
5193 (set_attr "type" "fsimpd")])
5194
5195 ;
5196 ; abssf2 instruction pattern(s).
5197 ;
5198
5199 (define_expand "abssf2"
5200 [(parallel
5201 [(set (match_operand:SF 0 "register_operand" "=f")
5202 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5203 (clobber (reg:CC 33))])]
5204 "TARGET_HARD_FLOAT"
5205 "")
5206
5207 (define_insn "*abssf2"
5208 [(set (match_operand:SF 0 "register_operand" "=f")
5209 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5210 (clobber (reg:CC 33))]
5211 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5212 "lpebr\\t%0,%1"
5213 [(set_attr "op_type" "RRE")
5214 (set_attr "type" "fsimps")])
5215
5216 (define_insn "*abssf2_ibm"
5217 [(set (match_operand:SF 0 "register_operand" "=f")
5218 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5219 (clobber (reg:CC 33))]
5220 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5221 "lper\\t%0,%1"
5222 [(set_attr "op_type" "RR")
5223 (set_attr "type" "fsimps")])
5224
5225 ;;
5226 ;;- Square root instructions.
5227 ;;
5228
5229 ;
5230 ; sqrtdf2 instruction pattern(s).
5231 ;
5232
5233 (define_insn "sqrtdf2"
5234 [(set (match_operand:DF 0 "register_operand" "=f,f")
5235 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5236 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5237 "@
5238 sqdbr\\t%0,%1
5239 sqdb\\t%0,%1"
5240 [(set_attr "op_type" "RRE,RSE")
5241 (set_attr "type" "fsqrtd")])
5242
5243 ;
5244 ; sqrtsf2 instruction pattern(s).
5245 ;
5246
5247 (define_insn "sqrtsf2"
5248 [(set (match_operand:SF 0 "register_operand" "=f,f")
5249 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5250 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5251 "@
5252 sqebr\\t%0,%1
5253 sqeb\\t%0,%1"
5254 [(set_attr "op_type" "RRE,RSE")
5255 (set_attr "type" "fsqrts")])
5256
5257 ;;
5258 ;;- One complement instructions.
5259 ;;
5260
5261 ;
5262 ; one_cmpldi2 instruction pattern(s).
5263 ;
5264
5265 (define_expand "one_cmpldi2"
5266 [(parallel
5267 [(set (match_operand:DI 0 "register_operand" "")
5268 (xor:DI (match_operand:DI 1 "register_operand" "")
5269 (const_int -1)))
5270 (clobber (reg:CC 33))])]
5271 "TARGET_64BIT"
5272 "")
5273
5274 ;
5275 ; one_cmplsi2 instruction pattern(s).
5276 ;
5277
5278 (define_expand "one_cmplsi2"
5279 [(parallel
5280 [(set (match_operand:SI 0 "register_operand" "")
5281 (xor:SI (match_operand:SI 1 "register_operand" "")
5282 (const_int -1)))
5283 (clobber (reg:CC 33))])]
5284 ""
5285 "")
5286
5287 ;
5288 ; one_cmplhi2 instruction pattern(s).
5289 ;
5290
5291 (define_expand "one_cmplhi2"
5292 [(parallel
5293 [(set (match_operand:HI 0 "register_operand" "")
5294 (xor:HI (match_operand:HI 1 "register_operand" "")
5295 (const_int -1)))
5296 (clobber (reg:CC 33))])]
5297 ""
5298 "")
5299
5300 ;
5301 ; one_cmplqi2 instruction pattern(s).
5302 ;
5303
5304 (define_expand "one_cmplqi2"
5305 [(parallel
5306 [(set (match_operand:QI 0 "register_operand" "")
5307 (xor:QI (match_operand:QI 1 "register_operand" "")
5308 (const_int -1)))
5309 (clobber (reg:CC 33))])]
5310 ""
5311 "")
5312
5313
5314 ;;
5315 ;;- Rotate instructions.
5316 ;;
5317
5318 ;
5319 ; rotldi3 instruction pattern(s).
5320 ;
5321
5322 (define_insn "rotldi3"
5323 [(set (match_operand:DI 0 "register_operand" "=d,d")
5324 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5325 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5326 "TARGET_64BIT"
5327 "@
5328 rllg\\t%0,%1,%c2
5329 rllg\\t%0,%1,0(%2)"
5330 [(set_attr "op_type" "RSE")
5331 (set_attr "atype" "reg")])
5332
5333 ;
5334 ; rotlsi3 instruction pattern(s).
5335 ;
5336
5337 (define_insn "rotlsi3"
5338 [(set (match_operand:SI 0 "register_operand" "=d,d")
5339 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5340 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5341 "TARGET_64BIT"
5342 "@
5343 rll\\t%0,%1,%c2
5344 rll\\t%0,%1,0(%2)"
5345 [(set_attr "op_type" "RSE")
5346 (set_attr "atype" "reg")])
5347
5348
5349 ;;
5350 ;;- Arithmetic shift instructions.
5351 ;;
5352
5353 ;
5354 ; ashldi3 instruction pattern(s).
5355 ;
5356
5357 (define_expand "ashldi3"
5358 [(set (match_operand:DI 0 "register_operand" "")
5359 (ashift:DI (match_operand:DI 1 "register_operand" "")
5360 (match_operand:SI 2 "nonmemory_operand" "")))]
5361 ""
5362 "")
5363
5364 (define_insn "*ashldi3_31"
5365 [(set (match_operand:DI 0 "register_operand" "=d,d")
5366 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5367 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5368 "!TARGET_64BIT"
5369 "@
5370 sldl\\t%0,%c2
5371 sldl\\t%0,0(%2)"
5372 [(set_attr "op_type" "RS")
5373 (set_attr "atype" "reg")])
5374
5375 (define_insn "*ashldi3_64"
5376 [(set (match_operand:DI 0 "register_operand" "=d,d")
5377 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5378 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5379 "TARGET_64BIT"
5380 "@
5381 sllg\\t%0,%1,%2
5382 sllg\\t%0,%1,0(%2)"
5383 [(set_attr "op_type" "RSE")
5384 (set_attr "atype" "reg")])
5385
5386 ;
5387 ; ashrdi3 instruction pattern(s).
5388 ;
5389
5390 (define_expand "ashrdi3"
5391 [(parallel
5392 [(set (match_operand:DI 0 "register_operand" "")
5393 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5394 (match_operand:SI 2 "nonmemory_operand" "")))
5395 (clobber (reg:CC 33))])]
5396 ""
5397 "")
5398
5399 (define_insn "*ashrdi3_cc_31"
5400 [(set (reg 33)
5401 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5402 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5403 (const_int 0)))
5404 (set (match_operand:DI 0 "register_operand" "=d,d")
5405 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5406 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5407 "@
5408 srda\\t%0,%c2
5409 srda\\t%0,0(%2)"
5410 [(set_attr "op_type" "RS")
5411 (set_attr "atype" "reg")])
5412
5413 (define_insn "*ashrdi3_cconly_31"
5414 [(set (reg 33)
5415 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5416 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5417 (const_int 0)))
5418 (clobber (match_scratch:DI 0 "=d,d"))]
5419 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5420 "@
5421 srda\\t%0,%c2
5422 srda\\t%0,0(%2)"
5423 [(set_attr "op_type" "RS")
5424 (set_attr "atype" "reg")])
5425
5426 (define_insn "*ashrdi3_31"
5427 [(set (match_operand:DI 0 "register_operand" "=d,d")
5428 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5429 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5430 (clobber (reg:CC 33))]
5431 "!TARGET_64BIT"
5432 "@
5433 srda\\t%0,%c2
5434 srda\\t%0,0(%2)"
5435 [(set_attr "op_type" "RS")
5436 (set_attr "atype" "reg")])
5437
5438 (define_insn "*ashrdi3_cc_64"
5439 [(set (reg 33)
5440 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5441 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5442 (const_int 0)))
5443 (set (match_operand:DI 0 "register_operand" "=d,d")
5444 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5445 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5446 "@
5447 srag\\t%0,%1,%c2
5448 srag\\t%0,%1,0(%2)"
5449 [(set_attr "op_type" "RSE")
5450 (set_attr "atype" "reg")])
5451
5452 (define_insn "*ashrdi3_cconly_64"
5453 [(set (reg 33)
5454 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5455 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5456 (const_int 0)))
5457 (clobber (match_scratch:DI 0 "=d,d"))]
5458 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5459 "@
5460 srag\\t%0,%1,%c2
5461 srag\\t%0,%1,0(%2)"
5462 [(set_attr "op_type" "RSE")
5463 (set_attr "atype" "reg")])
5464
5465 (define_insn "*ashrdi3_64"
5466 [(set (match_operand:DI 0 "register_operand" "=d,d")
5467 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5468 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5469 (clobber (reg:CC 33))]
5470 "TARGET_64BIT"
5471 "@
5472 srag\\t%0,%1,%c2
5473 srag\\t%0,%1,0(%2)"
5474 [(set_attr "op_type" "RSE")
5475 (set_attr "atype" "reg")])
5476
5477
5478 ;
5479 ; ashlsi3 instruction pattern(s).
5480 ;
5481
5482 (define_insn "ashlsi3"
5483 [(set (match_operand:SI 0 "register_operand" "=d,d")
5484 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5485 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5486 ""
5487 "@
5488 sll\\t%0,%c2
5489 sll\\t%0,0(%2)"
5490 [(set_attr "op_type" "RS")
5491 (set_attr "atype" "reg")])
5492
5493 ;
5494 ; ashrsi3 instruction pattern(s).
5495 ;
5496
5497 (define_insn "*ashrsi3_cc"
5498 [(set (reg 33)
5499 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5500 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5501 (const_int 0)))
5502 (set (match_operand:SI 0 "register_operand" "=d,d")
5503 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5504 "s390_match_ccmode(insn, CCSmode)"
5505 "@
5506 sra\\t%0,%c2
5507 sra\\t%0,0(%2)"
5508 [(set_attr "op_type" "RS")
5509 (set_attr "atype" "reg")])
5510
5511
5512 (define_insn "*ashrsi3_cconly"
5513 [(set (reg 33)
5514 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5515 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5516 (const_int 0)))
5517 (clobber (match_scratch:SI 0 "=d,d"))]
5518 "s390_match_ccmode(insn, CCSmode)"
5519 "@
5520 sra\\t%0,%c2
5521 sra\\t%0,0(%2)"
5522 [(set_attr "op_type" "RS")
5523 (set_attr "atype" "reg")])
5524
5525 (define_insn "ashrsi3"
5526 [(set (match_operand:SI 0 "register_operand" "=d,d")
5527 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5528 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5529 (clobber (reg:CC 33))]
5530 ""
5531 "@
5532 sra\\t%0,%c2
5533 sra\\t%0,0(%2)"
5534 [(set_attr "op_type" "RS")
5535 (set_attr "atype" "reg")])
5536
5537
5538 ;;
5539 ;;- logical shift instructions.
5540 ;;
5541
5542 ;
5543 ; lshrdi3 instruction pattern(s).
5544 ;
5545
5546 (define_expand "lshrdi3"
5547 [(set (match_operand:DI 0 "register_operand" "")
5548 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5549 (match_operand:SI 2 "nonmemory_operand" "")))]
5550 ""
5551 "")
5552
5553 (define_insn "*lshrdi3_31"
5554 [(set (match_operand:DI 0 "register_operand" "=d,d")
5555 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5556 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5557 "!TARGET_64BIT"
5558 "@
5559 srdl\\t%0,%c2
5560 srdl\\t%0,0(%2)"
5561 [(set_attr "op_type" "RS,RS")
5562 (set_attr "atype" "reg")])
5563
5564 (define_insn "*lshrdi3_64"
5565 [(set (match_operand:DI 0 "register_operand" "=d,d")
5566 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5567 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5568 "TARGET_64BIT"
5569 "@
5570 srlg\\t%0,%1,%c2
5571 srlg\\t%0,%1,0(%2)"
5572 [(set_attr "op_type" "RSE,RSE")
5573 (set_attr "atype" "reg")])
5574
5575 ;
5576 ; lshrsi3 instruction pattern(s).
5577 ;
5578
5579 (define_insn "lshrsi3"
5580 [(set (match_operand:SI 0 "register_operand" "=d,d")
5581 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5582 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5583 ""
5584 "@
5585 srl\\t%0,%c2
5586 srl\\t%0,0(%2)"
5587 [(set_attr "op_type" "RS")
5588 (set_attr "atype" "reg")])
5589
5590
5591 ;;
5592 ;; Branch instruction patterns.
5593 ;;
5594
5595 (define_expand "beq"
5596 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5597 (set (pc)
5598 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5599 (label_ref (match_operand 0 "" ""))
5600 (pc)))]
5601 ""
5602 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5603
5604 (define_expand "bne"
5605 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5606 (set (pc)
5607 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5608 (label_ref (match_operand 0 "" ""))
5609 (pc)))]
5610 ""
5611 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5612
5613 (define_expand "bgt"
5614 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5615 (set (pc)
5616 (if_then_else (gt (reg:CCS 33) (const_int 0))
5617 (label_ref (match_operand 0 "" ""))
5618 (pc)))]
5619 ""
5620 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5621
5622 (define_expand "bgtu"
5623 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5624 (set (pc)
5625 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5626 (label_ref (match_operand 0 "" ""))
5627 (pc)))]
5628 ""
5629 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5630
5631 (define_expand "blt"
5632 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5633 (set (pc)
5634 (if_then_else (lt (reg:CCS 33) (const_int 0))
5635 (label_ref (match_operand 0 "" ""))
5636 (pc)))]
5637 ""
5638 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5639
5640 (define_expand "bltu"
5641 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5642 (set (pc)
5643 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5644 (label_ref (match_operand 0 "" ""))
5645 (pc)))]
5646 ""
5647 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5648
5649 (define_expand "bge"
5650 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5651 (set (pc)
5652 (if_then_else (ge (reg:CCS 33) (const_int 0))
5653 (label_ref (match_operand 0 "" ""))
5654 (pc)))]
5655 ""
5656 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5657
5658 (define_expand "bgeu"
5659 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5660 (set (pc)
5661 (if_then_else (geu (reg:CCU 33) (const_int 0))
5662 (label_ref (match_operand 0 "" ""))
5663 (pc)))]
5664 ""
5665 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5666
5667 (define_expand "ble"
5668 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5669 (set (pc)
5670 (if_then_else (le (reg:CCS 33) (const_int 0))
5671 (label_ref (match_operand 0 "" ""))
5672 (pc)))]
5673 ""
5674 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5675
5676 (define_expand "bleu"
5677 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5678 (set (pc)
5679 (if_then_else (leu (reg:CCU 33) (const_int 0))
5680 (label_ref (match_operand 0 "" ""))
5681 (pc)))]
5682 ""
5683 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5684
5685 (define_expand "bunordered"
5686 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5687 (set (pc)
5688 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5689 (label_ref (match_operand 0 "" ""))
5690 (pc)))]
5691 ""
5692 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5693
5694 (define_expand "bordered"
5695 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5696 (set (pc)
5697 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5698 (label_ref (match_operand 0 "" ""))
5699 (pc)))]
5700 ""
5701 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5702
5703 (define_expand "buneq"
5704 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5705 (set (pc)
5706 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5707 (label_ref (match_operand 0 "" ""))
5708 (pc)))]
5709 ""
5710 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5711
5712 (define_expand "bungt"
5713 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5714 (set (pc)
5715 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5716 (label_ref (match_operand 0 "" ""))
5717 (pc)))]
5718 ""
5719 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5720
5721 (define_expand "bunlt"
5722 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5723 (set (pc)
5724 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5725 (label_ref (match_operand 0 "" ""))
5726 (pc)))]
5727 ""
5728 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5729
5730 (define_expand "bunge"
5731 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5732 (set (pc)
5733 (if_then_else (unge (reg:CCS 33) (const_int 0))
5734 (label_ref (match_operand 0 "" ""))
5735 (pc)))]
5736 ""
5737 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5738
5739 (define_expand "bunle"
5740 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5741 (set (pc)
5742 (if_then_else (unle (reg:CCS 33) (const_int 0))
5743 (label_ref (match_operand 0 "" ""))
5744 (pc)))]
5745 ""
5746 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5747
5748 (define_expand "bltgt"
5749 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5750 (set (pc)
5751 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5752 (label_ref (match_operand 0 "" ""))
5753 (pc)))]
5754 ""
5755 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5756
5757
5758 ;;
5759 ;;- Conditional jump instructions.
5760 ;;
5761
5762 (define_insn "cjump"
5763 [(set (pc)
5764 (if_then_else
5765 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5766 (label_ref (match_operand 0 "" ""))
5767 (pc)))]
5768 ""
5769 "*
5770 {
5771 if (get_attr_length (insn) == 4)
5772 return \"j%C1\\t%l0\";
5773 else if (TARGET_64BIT)
5774 return \"jg%C1\\t%l0\";
5775 else
5776 abort ();
5777 }"
5778 [(set_attr "op_type" "RI")
5779 (set_attr "type" "branch")
5780 (set (attr "length")
5781 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5782 (const_int 4)
5783 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5784 (const_int 6)
5785 (eq (symbol_ref "flag_pic") (const_int 0))
5786 (const_int 6)] (const_int 8)))])
5787
5788 (define_insn "*cjump_long"
5789 [(set (pc)
5790 (if_then_else
5791 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5792 (match_operand 0 "address_operand" "p")
5793 (pc)))]
5794 ""
5795 "*
5796 {
5797 if (get_attr_op_type (insn) == OP_TYPE_RR)
5798 return \"b%C1r\\t%0\";
5799 else
5800 return \"b%C1\\t%a0\";
5801 }"
5802 [(set (attr "op_type")
5803 (if_then_else (match_operand 0 "register_operand" "")
5804 (const_string "RR") (const_string "RX")))
5805 (set_attr "type" "branch")
5806 (set_attr "atype" "agen")])
5807
5808
5809 ;;
5810 ;;- Negated conditional jump instructions.
5811 ;;
5812
5813 (define_insn "icjump"
5814 [(set (pc)
5815 (if_then_else
5816 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5817 (pc)
5818 (label_ref (match_operand 0 "" ""))))]
5819 ""
5820 "*
5821 {
5822 if (get_attr_length (insn) == 4)
5823 return \"j%D1\\t%l0\";
5824 else if (TARGET_64BIT)
5825 return \"jg%D1\\t%l0\";
5826 else
5827 abort ();
5828 }"
5829 [(set_attr "op_type" "RI")
5830 (set_attr "type" "branch")
5831 (set (attr "length")
5832 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5833 (const_int 4)
5834 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5835 (const_int 6)
5836 (eq (symbol_ref "flag_pic") (const_int 0))
5837 (const_int 6)] (const_int 8)))])
5838
5839 (define_insn "*icjump_long"
5840 [(set (pc)
5841 (if_then_else
5842 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5843 (pc)
5844 (match_operand 0 "address_operand" "p")))]
5845 ""
5846 "*
5847 {
5848 if (get_attr_op_type (insn) == OP_TYPE_RR)
5849 return \"b%D1r\\t%0\";
5850 else
5851 return \"b%D1\\t%a0\";
5852 }"
5853 [(set (attr "op_type")
5854 (if_then_else (match_operand 0 "register_operand" "")
5855 (const_string "RR") (const_string "RX")))
5856 (set_attr "type" "branch")
5857 (set_attr "atype" "agen")])
5858
5859 ;;
5860 ;;- Trap instructions.
5861 ;;
5862
5863 (define_insn "trap"
5864 [(trap_if (const_int 1) (const_int 0))]
5865 ""
5866 "j\\t.+2"
5867 [(set_attr "op_type" "RX")
5868 (set_attr "type" "branch")])
5869
5870 (define_expand "conditional_trap"
5871 [(set (match_dup 2) (match_dup 3))
5872 (trap_if (match_operator 0 "comparison_operator"
5873 [(match_dup 2) (const_int 0)])
5874 (match_operand:SI 1 "general_operand" ""))]
5875 ""
5876 "
5877 {
5878 enum machine_mode ccmode;
5879
5880 if (operands[1] != const0_rtx) FAIL;
5881
5882 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5883 s390_compare_op0, s390_compare_op1);
5884 operands[2] = gen_rtx_REG (ccmode, 33);
5885 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5886 }")
5887
5888 (define_insn "*trap"
5889 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5890 (const_int 0))]
5891 ""
5892 "j%C0\\t.+2";
5893 [(set_attr "op_type" "RI")
5894 (set_attr "type" "branch")])
5895
5896 ;;
5897 ;;- Loop instructions.
5898 ;;
5899 ;; This is all complicated by the fact that since this is a jump insn
5900 ;; we must handle our own output reloads.
5901
5902 (define_expand "doloop_end"
5903 [(use (match_operand 0 "" "")) ; loop pseudo
5904 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5905 (use (match_operand 2 "" "")) ; max iterations
5906 (use (match_operand 3 "" "")) ; loop level
5907 (use (match_operand 4 "" ""))] ; label
5908 ""
5909 "
5910 {
5911 if (GET_MODE (operands[0]) == SImode)
5912 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5913 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5914 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5915 else
5916 FAIL;
5917
5918 DONE;
5919 }")
5920
5921 (define_insn "doloop_si"
5922 [(set (pc)
5923 (if_then_else
5924 (ne (match_operand:SI 1 "register_operand" "d,d")
5925 (const_int 1))
5926 (label_ref (match_operand 0 "" ""))
5927 (pc)))
5928 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5929 (plus:SI (match_dup 1) (const_int -1)))
5930 (clobber (match_scratch:SI 3 "=X,&d"))
5931 (clobber (reg:CC 33))]
5932 ""
5933 "*
5934 {
5935 if (which_alternative != 0)
5936 return \"#\";
5937 else if (get_attr_length (insn) == 4)
5938 return \"brct\\t%1,%l0\";
5939 else
5940 abort ();
5941 }"
5942 [(set_attr "op_type" "RI")
5943 (set_attr "type" "branch")
5944 (set (attr "length")
5945 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5946 (const_int 4)
5947 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5948 (const_int 10)
5949 (eq (symbol_ref "flag_pic") (const_int 0))
5950 (const_int 6)] (const_int 8)))])
5951
5952 (define_insn "*doloop_si_long"
5953 [(set (pc)
5954 (if_then_else
5955 (ne (match_operand:SI 1 "register_operand" "d,d")
5956 (const_int 1))
5957 (match_operand 0 "address_operand" "p,p")
5958 (pc)))
5959 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5960 (plus:SI (match_dup 1) (const_int -1)))
5961 (clobber (match_scratch:SI 3 "=X,&d"))
5962 (clobber (reg:CC 33))]
5963 ""
5964 "*
5965 {
5966 if (get_attr_op_type (insn) == OP_TYPE_RR)
5967 return \"bctr\\t%1,%0\";
5968 else
5969 return \"bct\\t%1,%a0\";
5970 }"
5971 [(set (attr "op_type")
5972 (if_then_else (match_operand 0 "register_operand" "")
5973 (const_string "RR") (const_string "RX")))
5974 (set_attr "type" "branch")
5975 (set_attr "atype" "agen")])
5976
5977 (define_split
5978 [(set (pc)
5979 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5980 (const_int 1))
5981 (match_operand 0 "" "")
5982 (pc)))
5983 (set (match_operand:SI 2 "nonimmediate_operand" "")
5984 (plus:SI (match_dup 1) (const_int -1)))
5985 (clobber (match_scratch:SI 3 ""))
5986 (clobber (reg:CC 33))]
5987 "reload_completed
5988 && (! REG_P (operands[2])
5989 || ! rtx_equal_p (operands[1], operands[2]))"
5990 [(set (match_dup 3) (match_dup 1))
5991 (parallel [(set (reg:CCAN 33)
5992 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
5993 (const_int 0)))
5994 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
5995 (set (match_dup 2) (match_dup 3))
5996 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5997 (match_dup 0)
5998 (pc)))]
5999 "")
6000
6001 (define_insn "doloop_di"
6002 [(set (pc)
6003 (if_then_else
6004 (ne (match_operand:DI 1 "register_operand" "d,d")
6005 (const_int 1))
6006 (label_ref (match_operand 0 "" ""))
6007 (pc)))
6008 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
6009 (plus:DI (match_dup 1) (const_int -1)))
6010 (clobber (match_scratch:DI 3 "=X,&d"))
6011 (clobber (reg:CC 33))]
6012 "TARGET_64BIT"
6013 "*
6014 {
6015 if (which_alternative != 0)
6016 return \"#\";
6017 else if (get_attr_length (insn) == 4)
6018 return \"brctg\\t%1,%l0\";
6019 else
6020 abort ();
6021 }"
6022 [(set_attr "op_type" "RI")
6023 (set_attr "type" "branch")
6024 (set (attr "length")
6025 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6026 (const_int 4) (const_int 12)))])
6027
6028 (define_insn "*doloop_di_long"
6029 [(set (pc)
6030 (if_then_else
6031 (ne (match_operand:DI 1 "register_operand" "d,d")
6032 (const_int 1))
6033 (match_operand 0 "address_operand" "p,p")
6034 (pc)))
6035 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
6036 (plus:DI (match_dup 1) (const_int -1)))
6037 (clobber (match_scratch:DI 3 "=X,&d"))
6038 (clobber (reg:CC 33))]
6039 ""
6040 "*
6041 {
6042 if (get_attr_op_type (insn) == OP_TYPE_RRE)
6043 return \"bctgr\\t%1,%0\";
6044 else
6045 return \"bctg\\t%1,%a0\";
6046 }"
6047 [(set (attr "op_type")
6048 (if_then_else (match_operand 0 "register_operand" "")
6049 (const_string "RRE") (const_string "RXE")))
6050 (set_attr "type" "branch")
6051 (set_attr "atype" "agen")])
6052
6053 (define_split
6054 [(set (pc)
6055 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
6056 (const_int 1))
6057 (match_operand 0 "" "")
6058 (pc)))
6059 (set (match_operand:DI 2 "nonimmediate_operand" "")
6060 (plus:DI (match_dup 1) (const_int -1)))
6061 (clobber (match_scratch:DI 3 ""))
6062 (clobber (reg:CC 33))]
6063 "reload_completed
6064 && (! REG_P (operands[2])
6065 || ! rtx_equal_p (operands[1], operands[2]))"
6066 [(set (match_dup 3) (match_dup 1))
6067 (parallel [(set (reg:CCAN 33)
6068 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6069 (const_int 0)))
6070 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6071 (set (match_dup 2) (match_dup 3))
6072 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6073 (match_dup 0)
6074 (pc)))]
6075 "")
6076
6077 ;;
6078 ;;- Unconditional jump instructions.
6079 ;;
6080
6081 ;
6082 ; jump instruction pattern(s).
6083 ;
6084
6085 (define_insn "jump"
6086 [(set (pc) (label_ref (match_operand 0 "" "")))]
6087 ""
6088 "*
6089 {
6090 if (get_attr_length (insn) == 4)
6091 return \"j\\t%l0\";
6092 else if (TARGET_64BIT)
6093 return \"jg\\t%l0\";
6094 else
6095 abort ();
6096 }"
6097 [(set_attr "op_type" "RI")
6098 (set_attr "type" "branch")
6099 (set (attr "length")
6100 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6101 (const_int 4)
6102 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6103 (const_int 6)
6104 (eq (symbol_ref "flag_pic") (const_int 0))
6105 (const_int 6)] (const_int 8)))])
6106
6107 ;
6108 ; indirect-jump instruction pattern(s).
6109 ;
6110
6111 (define_insn "indirect_jump"
6112 [(set (pc) (match_operand 0 "address_operand" "p"))]
6113 ""
6114 "*
6115 {
6116 if (get_attr_op_type (insn) == OP_TYPE_RR)
6117 return \"br\\t%0\";
6118 else
6119 return \"b\\t%a0\";
6120 }"
6121 [(set (attr "op_type")
6122 (if_then_else (match_operand 0 "register_operand" "")
6123 (const_string "RR") (const_string "RX")))
6124 (set_attr "type" "branch")
6125 (set_attr "atype" "agen")])
6126
6127 ;
6128 ; casesi instruction pattern(s).
6129 ;
6130
6131 (define_insn "casesi_jump"
6132 [(set (pc) (match_operand 0 "address_operand" "p"))
6133 (use (label_ref (match_operand 1 "" "")))]
6134 ""
6135 "*
6136 {
6137 if (get_attr_op_type (insn) == OP_TYPE_RR)
6138 return \"br\\t%0\";
6139 else
6140 return \"b\\t%a0\";
6141 }"
6142 [(set (attr "op_type")
6143 (if_then_else (match_operand 0 "register_operand" "")
6144 (const_string "RR") (const_string "RX")))
6145 (set_attr "type" "branch")
6146 (set_attr "atype" "agen")])
6147
6148 (define_expand "casesi"
6149 [(match_operand:SI 0 "general_operand" "")
6150 (match_operand:SI 1 "general_operand" "")
6151 (match_operand:SI 2 "general_operand" "")
6152 (label_ref (match_operand 3 "" ""))
6153 (label_ref (match_operand 4 "" ""))]
6154 ""
6155 "
6156 {
6157 rtx index = gen_reg_rtx (SImode);
6158 rtx base = gen_reg_rtx (Pmode);
6159 rtx target = gen_reg_rtx (Pmode);
6160
6161 emit_move_insn (index, operands[0]);
6162 emit_insn (gen_subsi3 (index, index, operands[1]));
6163 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6164 operands[4]);
6165
6166 if (Pmode != SImode)
6167 index = convert_to_mode (Pmode, index, 1);
6168 if (GET_CODE (index) != REG)
6169 index = copy_to_mode_reg (Pmode, index);
6170
6171 if (TARGET_64BIT)
6172 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6173 else
6174 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6175
6176 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6177
6178 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6179 emit_move_insn (target, index);
6180
6181 if (flag_pic)
6182 target = gen_rtx_PLUS (Pmode, base, target);
6183 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6184
6185 DONE;
6186 }")
6187
6188
6189 ;;
6190 ;;- Jump to subroutine.
6191 ;;
6192 ;;
6193
6194 ;
6195 ; untyped call instruction pattern(s).
6196 ;
6197
6198 ;; Call subroutine returning any type.
6199 (define_expand "untyped_call"
6200 [(parallel [(call (match_operand 0 "" "")
6201 (const_int 0))
6202 (match_operand 1 "" "")
6203 (match_operand 2 "" "")])]
6204 ""
6205 "
6206 {
6207 int i;
6208
6209 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6210
6211 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6212 {
6213 rtx set = XVECEXP (operands[2], 0, i);
6214 emit_move_insn (SET_DEST (set), SET_SRC (set));
6215 }
6216
6217 /* The optimizer does not know that the call sets the function value
6218 registers we stored in the result block. We avoid problems by
6219 claiming that all hard registers are used and clobbered at this
6220 point. */
6221 emit_insn (gen_blockage ());
6222
6223 DONE;
6224 }")
6225
6226 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6227 ;; all of memory. This blocks insns from being moved across this point.
6228
6229 (define_insn "blockage"
6230 [(unspec_volatile [(const_int 0)] 0)]
6231 ""
6232 ""
6233 [(set_attr "type" "none")
6234 (set_attr "length" "0")])
6235
6236
6237
6238 ;
6239 ; call instruction pattern(s).
6240 ;
6241
6242 (define_expand "call"
6243 [(call (match_operand 0 "" "")
6244 (match_operand 1 "" ""))
6245 (use (match_operand 2 "" ""))]
6246 ""
6247 "
6248 {
6249 int plt_call = 0;
6250 rtx insn;
6251
6252 /* Direct function calls need special treatment. */
6253 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6254 {
6255 rtx sym = XEXP (operands[0], 0);
6256
6257 /* When calling a global routine in PIC mode, we must
6258 replace the symbol itself with the PLT stub. */
6259 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6260 {
6261 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6262 sym = gen_rtx_CONST (Pmode, sym);
6263
6264 plt_call = 1;
6265 }
6266
6267 /* Unless we can use the bras(l) insn, force the
6268 routine address into a register. */
6269 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6270 {
6271 rtx target = gen_reg_rtx (Pmode);
6272 emit_move_insn (target, sym);
6273 sym = target;
6274 }
6275
6276 operands[0] = gen_rtx_MEM (QImode, sym);
6277 }
6278
6279 /* Emit insn. */
6280 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6281 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6282
6283 /* In 31-bit, we must load the GOT register even if the
6284 compiler doesn't know about it, because the PLT glue
6285 code uses it. In 64-bit, this is not necessary. */
6286 if (plt_call && !TARGET_64BIT)
6287 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6288
6289 DONE;
6290 }")
6291
6292 (define_expand "call_exp"
6293 [(parallel [(call (match_operand 0 "" "")
6294 (match_operand 1 "" ""))
6295 (clobber (match_operand 2 "" ""))])]
6296 ""
6297 "")
6298
6299 (define_insn "brasl"
6300 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6301 (match_operand:SI 1 "const_int_operand" "n"))
6302 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6303 "TARGET_64BIT"
6304 "brasl\\t%2,%0"
6305 [(set_attr "op_type" "RIL")
6306 (set_attr "type" "jsr")])
6307
6308 (define_insn "bras"
6309 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6310 (match_operand:SI 1 "const_int_operand" "n"))
6311 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6312 "TARGET_SMALL_EXEC"
6313 "bras\\t%2,%0"
6314 [(set_attr "op_type" "RI")
6315 (set_attr "type" "jsr")])
6316
6317 (define_insn "basr_64"
6318 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6319 (match_operand:SI 1 "const_int_operand" "n"))
6320 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6321 "TARGET_64BIT"
6322 "basr\\t%2,%0"
6323 [(set_attr "op_type" "RR")
6324 (set_attr "type" "jsr")
6325 (set_attr "atype" "agen")])
6326
6327 (define_insn "basr_31"
6328 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6329 (match_operand:SI 1 "const_int_operand" "n"))
6330 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6331 "!TARGET_64BIT"
6332 "basr\\t%2,%0"
6333 [(set_attr "op_type" "RR")
6334 (set_attr "type" "jsr")
6335 (set_attr "atype" "agen")])
6336
6337 (define_insn "bas_64"
6338 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6339 (match_operand:SI 1 "const_int_operand" "n"))
6340 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6341 "TARGET_64BIT"
6342 "bas\\t%2,%a0"
6343 [(set_attr "op_type" "RX")
6344 (set_attr "type" "jsr")])
6345
6346 (define_insn "bas_31"
6347 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6348 (match_operand:SI 1 "const_int_operand" "n"))
6349 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6350 "!TARGET_64BIT"
6351 "bas\\t%2,%a0"
6352 [(set_attr "op_type" "RX")
6353 (set_attr "type" "jsr")])
6354
6355
6356 ;
6357 ; call_value instruction pattern(s).
6358 ;
6359
6360 (define_expand "call_value"
6361 [(set (match_operand 0 "" "")
6362 (call (match_operand 1 "" "")
6363 (match_operand 2 "" "")))
6364 (use (match_operand 3 "" ""))]
6365 ""
6366 "
6367 {
6368 int plt_call = 0;
6369 rtx insn;
6370
6371 /* Direct function calls need special treatment. */
6372 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6373 {
6374 rtx sym = XEXP (operands[1], 0);
6375
6376 /* When calling a global routine in PIC mode, we must
6377 replace the symbol itself with the PLT stub. */
6378 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6379 {
6380 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6381 sym = gen_rtx_CONST (Pmode, sym);
6382
6383 plt_call = 1;
6384 }
6385
6386 /* Unless we can use the bras(l) insn, force the
6387 routine address into a register. */
6388 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6389 {
6390 rtx target = gen_reg_rtx (Pmode);
6391 emit_move_insn (target, sym);
6392 sym = target;
6393 }
6394
6395 operands[1] = gen_rtx_MEM (QImode, sym);
6396 }
6397
6398 /* Emit insn. */
6399 insn = emit_call_insn (
6400 gen_call_value_exp (operands[0], operands[1], operands[2],
6401 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6402
6403 /* In 31-bit, we must load the GOT register even if the
6404 compiler doesn't know about it, because the PLT glue
6405 code uses it. In 64-bit, this is not necessary. */
6406 if (plt_call && !TARGET_64BIT)
6407 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6408
6409 DONE;
6410 }")
6411
6412 (define_expand "call_value_exp"
6413 [(parallel [(set (match_operand 0 "" "")
6414 (call (match_operand 1 "" "")
6415 (match_operand 2 "" "")))
6416 (clobber (match_operand 3 "" ""))])]
6417 ""
6418 "")
6419
6420 (define_insn "brasl_r"
6421 [(set (match_operand 0 "register_operand" "=df")
6422 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6423 (match_operand:SI 2 "const_int_operand" "n")))
6424 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6425 "TARGET_64BIT"
6426 "brasl\\t%3,%1"
6427 [(set_attr "op_type" "RIL")
6428 (set_attr "type" "jsr")])
6429
6430 (define_insn "bras_r"
6431 [(set (match_operand 0 "register_operand" "=df")
6432 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6433 (match_operand:SI 2 "const_int_operand" "n")))
6434 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6435 "TARGET_SMALL_EXEC"
6436 "bras\\t%3,%1"
6437 [(set_attr "op_type" "RI")
6438 (set_attr "type" "jsr")])
6439
6440 (define_insn "basr_r_64"
6441 [(set (match_operand 0 "register_operand" "=df")
6442 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6443 (match_operand:SI 2 "const_int_operand" "n")))
6444 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6445 "TARGET_64BIT"
6446 "basr\\t%3,%1"
6447 [(set_attr "op_type" "RR")
6448 (set_attr "type" "jsr")
6449 (set_attr "atype" "agen")])
6450
6451 (define_insn "basr_r_31"
6452 [(set (match_operand 0 "register_operand" "=df")
6453 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6454 (match_operand:SI 2 "const_int_operand" "n")))
6455 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6456 "!TARGET_64BIT"
6457 "basr\\t%3,%1"
6458 [(set_attr "op_type" "RR")
6459 (set_attr "type" "jsr")
6460 (set_attr "atype" "agen")])
6461
6462 (define_insn "bas_r_64"
6463 [(set (match_operand 0 "register_operand" "=df")
6464 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6465 (match_operand:SI 2 "const_int_operand" "n")))
6466 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6467 "TARGET_64BIT"
6468 "bas\\t%3,%a1"
6469 [(set_attr "op_type" "RX")
6470 (set_attr "type" "jsr")])
6471
6472 (define_insn "bas_r_31"
6473 [(set (match_operand 0 "register_operand" "=df")
6474 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6475 (match_operand:SI 2 "const_int_operand" "n")))
6476 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6477 "!TARGET_64BIT"
6478 "bas\\t%3,%a1"
6479 [(set_attr "op_type" "RX")
6480 (set_attr "type" "jsr")])
6481
6482
6483 ;;
6484 ;;- Thread-local storage support.
6485 ;;
6486
6487 (define_insn "get_tp_64"
6488 [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q")
6489 (unspec:DI [(const_int 0)] UNSPEC_TP))]
6490 "TARGET_64BIT"
6491 "@
6492 ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1
6493 stam\\t%%a0,%%a1,%0"
6494 [(set_attr "op_type" "NN,RS")
6495 (set_attr "atype" "reg,*")
6496 (set_attr "type" "o3,*")
6497 (set_attr "length" "14,*")])
6498
6499 (define_insn "get_tp_31"
6500 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q")
6501 (unspec:SI [(const_int 0)] UNSPEC_TP))]
6502 "!TARGET_64BIT"
6503 "@
6504 ear\\t%0,%%a0
6505 stam\\t%%a0,%%a0,%0"
6506 [(set_attr "op_type" "RRE,RS")])
6507
6508 (define_insn "set_tp_64"
6509 [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP)
6510 (clobber (match_scratch:SI 1 "=d,X"))]
6511 "TARGET_64BIT"
6512 "@
6513 sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1
6514 lam\\t%%a0,%%a1,%0"
6515 [(set_attr "op_type" "NN,RS")
6516 (set_attr "atype" "reg,*")
6517 (set_attr "type" "o3,*")
6518 (set_attr "length" "14,*")])
6519
6520 (define_insn "set_tp_31"
6521 [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)]
6522 "!TARGET_64BIT"
6523 "@
6524 sar\\t%%a0,%0
6525 lam\\t%%a0,%%a0,%0"
6526 [(set_attr "op_type" "RRE,RS")])
6527
6528 (define_insn "*tls_load_64"
6529 [(set (match_operand:DI 0 "register_operand" "=d")
6530 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6531 (match_operand:DI 2 "" "")]
6532 UNSPEC_TLS_LOAD))]
6533 "TARGET_64BIT"
6534 "lg\\t%0,%1%J2"
6535 [(set_attr "op_type" "RXE")])
6536
6537 (define_insn "*tls_load_31"
6538 [(set (match_operand:SI 0 "register_operand" "=d")
6539 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
6540 (match_operand:SI 2 "" "")]
6541 UNSPEC_TLS_LOAD))]
6542 "!TARGET_64BIT"
6543 "l\\t%0,%1%J2"
6544 [(set_attr "op_type" "RX")])
6545
6546 (define_expand "call_value_tls"
6547 [(set (match_operand 0 "" "")
6548 (call (const_int 0) (const_int 0)))
6549 (use (match_operand 1 "" ""))]
6550 ""
6551 "
6552 {
6553 rtx insn, sym;
6554
6555 if (!flag_pic)
6556 abort ();
6557
6558 sym = s390_tls_get_offset ();
6559 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6560 sym = gen_rtx_CONST (Pmode, sym);
6561
6562 /* Unless we can use the bras(l) insn, force the
6563 routine address into a register. */
6564 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6565 {
6566 rtx target = gen_reg_rtx (Pmode);
6567 emit_move_insn (target, sym);
6568 sym = target;
6569 }
6570
6571 sym = gen_rtx_MEM (QImode, sym);
6572
6573 /* Emit insn. */
6574 insn = emit_call_insn (
6575 gen_call_value_tls_exp (operands[0], sym, const0_rtx,
6576 gen_rtx_REG (Pmode, RETURN_REGNUM),
6577 operands[1]));
6578
6579 /* The calling convention of __tls_get_offset uses the
6580 GOT register implicitly. */
6581 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6582 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]);
6583 CONST_OR_PURE_CALL_P (insn) = 1;
6584
6585 DONE;
6586 }")
6587
6588 (define_expand "call_value_tls_exp"
6589 [(parallel [(set (match_operand 0 "" "")
6590 (call (match_operand 1 "" "")
6591 (match_operand 2 "" "")))
6592 (clobber (match_operand 3 "" ""))
6593 (use (match_operand 4 "" ""))])]
6594 ""
6595 "")
6596
6597 (define_insn "brasl_tls"
6598 [(set (match_operand 0 "register_operand" "=df")
6599 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6600 (match_operand:SI 2 "const_int_operand" "n")))
6601 (clobber (match_operand:DI 3 "register_operand" "=r"))
6602 (use (match_operand:DI 4 "" ""))]
6603 "TARGET_64BIT"
6604 "brasl\\t%3,%1%J4"
6605 [(set_attr "op_type" "RIL")
6606 (set_attr "type" "jsr")])
6607
6608 (define_insn "bras_tls"
6609 [(set (match_operand 0 "register_operand" "=df")
6610 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6611 (match_operand:SI 2 "const_int_operand" "n")))
6612 (clobber (match_operand:SI 3 "register_operand" "=r"))
6613 (use (match_operand:SI 4 "" ""))]
6614 "TARGET_SMALL_EXEC"
6615 "bras\\t%3,%1%J4"
6616 [(set_attr "op_type" "RI")
6617 (set_attr "type" "jsr")])
6618
6619 (define_insn "basr_tls_64"
6620 [(set (match_operand 0 "register_operand" "=df")
6621 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6622 (match_operand:SI 2 "const_int_operand" "n")))
6623 (clobber (match_operand:DI 3 "register_operand" "=r"))
6624 (use (match_operand:DI 4 "" ""))]
6625 "TARGET_64BIT"
6626 "basr\\t%3,%1%J4"
6627 [(set_attr "op_type" "RR")
6628 (set_attr "type" "jsr")])
6629
6630 (define_insn "basr_tls_31"
6631 [(set (match_operand 0 "register_operand" "=df")
6632 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6633 (match_operand:SI 2 "const_int_operand" "n")))
6634 (clobber (match_operand:SI 3 "register_operand" "=r"))
6635 (use (match_operand:SI 4 "" ""))]
6636 "!TARGET_64BIT"
6637 "basr\\t%3,%1%J4"
6638 [(set_attr "op_type" "RR")
6639 (set_attr "type" "jsr")
6640 (set_attr "atype" "agen")])
6641
6642 (define_insn "bas_tls_64"
6643 [(set (match_operand 0 "register_operand" "=df")
6644 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6645 (match_operand:SI 2 "const_int_operand" "n")))
6646 (clobber (match_operand:DI 3 "register_operand" "=r"))
6647 (use (match_operand:DI 4 "" ""))]
6648 "TARGET_64BIT"
6649 "bas\\t%3,%a1%J4"
6650 [(set_attr "op_type" "RX")
6651 (set_attr "type" "jsr")
6652 (set_attr "atype" "agen")])
6653
6654 (define_insn "bas_tls_31"
6655 [(set (match_operand 0 "register_operand" "=df")
6656 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6657 (match_operand:SI 2 "const_int_operand" "n")))
6658 (clobber (match_operand:SI 3 "register_operand" "=r"))
6659 (use (match_operand:SI 4 "" ""))]
6660 "!TARGET_64BIT"
6661 "bas\\t%3,%a1%J4"
6662 [(set_attr "op_type" "RX")
6663 (set_attr "type" "jsr")
6664 (set_attr "atype" "agen")])
6665
6666 ;;
6667 ;;- Miscellaneous instructions.
6668 ;;
6669
6670 ;
6671 ; allocate stack instruction pattern(s).
6672 ;
6673
6674 (define_expand "allocate_stack"
6675 [(set (reg 15)
6676 (plus (reg 15) (match_operand 1 "general_operand" "")))
6677 (set (match_operand 0 "general_operand" "")
6678 (reg 15))]
6679 ""
6680 "
6681 {
6682 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6683 rtx chain = gen_rtx (MEM, Pmode, stack);
6684 rtx temp = gen_reg_rtx (Pmode);
6685
6686 emit_move_insn (temp, chain);
6687
6688 if (TARGET_64BIT)
6689 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6690 else
6691 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6692
6693 emit_move_insn (chain, temp);
6694
6695 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6696 DONE;
6697 }")
6698
6699
6700 ;
6701 ; setjmp/longjmp instruction pattern(s).
6702 ;
6703
6704 (define_expand "builtin_setjmp_setup"
6705 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6706 ""
6707 "
6708 {
6709 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6710 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6711
6712 emit_move_insn (base, basereg);
6713 DONE;
6714 }")
6715
6716 (define_expand "builtin_setjmp_receiver"
6717 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6718 "flag_pic"
6719 "
6720 {
6721 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6722 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6723 SYMBOL_REF_FLAG (got) = 1;
6724
6725 emit_move_insn (gotreg, got);
6726 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6727 DONE;
6728 }")
6729
6730 (define_expand "builtin_longjmp"
6731 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6732 ""
6733 "
6734 {
6735 /* The elements of the buffer are, in order: */
6736 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6737 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6738 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6739 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6740 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6741 rtx jmp = gen_rtx_REG (Pmode, 14);
6742
6743 emit_move_insn (jmp, lab);
6744 emit_move_insn (basereg, base);
6745 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6746 emit_move_insn (hard_frame_pointer_rtx, fp);
6747
6748 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6749 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6750 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6751 emit_indirect_jump (jmp);
6752 DONE;
6753 }")
6754
6755
6756 ;; These patterns say how to save and restore the stack pointer. We need not
6757 ;; save the stack pointer at function level since we are careful to
6758 ;; preserve the backchain. At block level, we have to restore the backchain
6759 ;; when we restore the stack pointer.
6760 ;;
6761 ;; For nonlocal gotos, we must save both the stack pointer and its
6762 ;; backchain and restore both. Note that in the nonlocal case, the
6763 ;; save area is a memory location.
6764
6765 (define_expand "save_stack_function"
6766 [(match_operand 0 "general_operand" "")
6767 (match_operand 1 "general_operand" "")]
6768 ""
6769 "DONE;")
6770
6771 (define_expand "restore_stack_function"
6772 [(match_operand 0 "general_operand" "")
6773 (match_operand 1 "general_operand" "")]
6774 ""
6775 "DONE;")
6776
6777 (define_expand "restore_stack_block"
6778 [(use (match_operand 0 "register_operand" ""))
6779 (set (match_dup 2) (match_dup 3))
6780 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6781 (set (match_dup 3) (match_dup 2))]
6782 ""
6783 "
6784 {
6785 operands[2] = gen_reg_rtx (Pmode);
6786 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6787 }")
6788
6789 (define_expand "save_stack_nonlocal"
6790 [(match_operand 0 "memory_operand" "")
6791 (match_operand 1 "register_operand" "")]
6792 ""
6793 "
6794 {
6795 rtx temp = gen_reg_rtx (Pmode);
6796
6797 /* Copy the backchain to the first word, sp to the second. */
6798 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6799 emit_move_insn (operand_subword (operands[0], 0, 0,
6800 TARGET_64BIT ? TImode : DImode),
6801 temp);
6802 emit_move_insn (operand_subword (operands[0], 1, 0,
6803 TARGET_64BIT ? TImode : DImode),
6804 operands[1]);
6805 DONE;
6806 }")
6807
6808 (define_expand "restore_stack_nonlocal"
6809 [(match_operand 0 "register_operand" "")
6810 (match_operand 1 "memory_operand" "")]
6811 ""
6812 "
6813 {
6814 rtx temp = gen_reg_rtx (Pmode);
6815
6816 /* Restore the backchain from the first word, sp from the second. */
6817 emit_move_insn (temp,
6818 operand_subword (operands[1], 0, 0,
6819 TARGET_64BIT ? TImode : DImode));
6820 emit_move_insn (operands[0],
6821 operand_subword (operands[1], 1, 0,
6822 TARGET_64BIT ? TImode : DImode));
6823 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6824 DONE;
6825 }")
6826
6827
6828 ;
6829 ; nop instruction pattern(s).
6830 ;
6831
6832 (define_insn "nop"
6833 [(const_int 0)]
6834 ""
6835 "lr\\t0,0"
6836 [(set_attr "op_type" "RR")])
6837
6838
6839 ;
6840 ; Special literal pool access instruction pattern(s).
6841 ;
6842
6843 (define_insn "consttable_qi"
6844 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6845 ""
6846 "*
6847 {
6848 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6849 return \"\";
6850 }"
6851 [(set_attr "op_type" "NN")
6852 (set_attr "length" "1")])
6853
6854 (define_insn "consttable_hi"
6855 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6856 ""
6857 "*
6858 {
6859 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6860 return \"\";
6861 }"
6862 [(set_attr "op_type" "NN")
6863 (set_attr "length" "2")])
6864
6865 (define_insn "consttable_si"
6866 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6867 ""
6868 "*
6869 {
6870 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6871 return \".long\\t%0\";
6872
6873 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6874 return \"\";
6875 }"
6876 [(set_attr "op_type" "NN")
6877 (set_attr "length" "4")])
6878
6879 (define_insn "consttable_di"
6880 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6881 ""
6882 "*
6883 {
6884 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6885 return \"\";
6886 }"
6887 [(set_attr "op_type" "NN")
6888 (set_attr "length" "8")])
6889
6890 (define_insn "consttable_sf"
6891 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6892 ""
6893 "*
6894 {
6895 REAL_VALUE_TYPE r;
6896
6897 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6898 abort ();
6899
6900 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6901 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6902 return \"\";
6903 }"
6904 [(set_attr "op_type" "NN")
6905 (set_attr "length" "4")])
6906
6907 (define_insn "consttable_df"
6908 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6909 ""
6910 "*
6911 {
6912 REAL_VALUE_TYPE r;
6913
6914 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6915 abort ();
6916
6917 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6918 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6919 return \"\";
6920 }"
6921 [(set_attr "op_type" "NN")
6922 (set_attr "length" "8")])
6923
6924 (define_insn "pool_start_31"
6925 [(unspec_volatile [(const_int 0)] 206)]
6926 "!TARGET_64BIT"
6927 ".align\\t4"
6928 [(set_attr "op_type" "NN")
6929 (set_attr "length" "2")])
6930
6931 (define_insn "pool_end_31"
6932 [(unspec_volatile [(const_int 0)] 207)]
6933 "!TARGET_64BIT"
6934 ".align\\t2"
6935 [(set_attr "op_type" "NN")
6936 (set_attr "length" "2")])
6937
6938 (define_insn "pool_start_64"
6939 [(unspec_volatile [(const_int 0)] 206)]
6940 "TARGET_64BIT"
6941 ".section\\t.rodata\;.align\\t8"
6942 [(set_attr "op_type" "NN")
6943 (set_attr "length" "0")])
6944
6945 (define_insn "pool_end_64"
6946 [(unspec_volatile [(const_int 0)] 207)]
6947 "TARGET_64BIT"
6948 ".previous"
6949 [(set_attr "op_type" "NN")
6950 (set_attr "length" "0")])
6951
6952 (define_insn "reload_base_31"
6953 [(set (match_operand:SI 0 "register_operand" "=a")
6954 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6955 "!TARGET_64BIT"
6956 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6957 [(set_attr "op_type" "NN")
6958 (set_attr "type" "la")
6959 (set_attr "length" "6")])
6960
6961 (define_insn "reload_base_64"
6962 [(set (match_operand:DI 0 "register_operand" "=a")
6963 (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))]
6964 "TARGET_64BIT"
6965 "larl\\t%0,%1"
6966 [(set_attr "op_type" "RIL")
6967 (set_attr "type" "larl")])
6968
6969 (define_insn "reload_anchor"
6970 [(set (match_operand:SI 0 "register_operand" "=a")
6971 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))]
6972 "!TARGET_64BIT"
6973 "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
6974 [(set_attr "op_type" "NN")
6975 (set_attr "type" "la")
6976 (set_attr "atype" "agen")
6977 (set_attr "length" "8")])
6978
6979 (define_insn "pool"
6980 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)]
6981 ""
6982 "* abort ();"
6983 [(set_attr "op_type" "NN")
6984 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6985
6986 ;;
6987 ;; Insns related to generating the function prologue and epilogue.
6988 ;;
6989
6990
6991 (define_expand "prologue"
6992 [(use (const_int 0))]
6993 ""
6994 "
6995 {
6996 s390_emit_prologue ();
6997 DONE;
6998 }")
6999
7000 (define_expand "epilogue"
7001 [(use (const_int 1))]
7002 ""
7003 "
7004 {
7005 s390_emit_epilogue ();
7006 DONE;
7007 }")
7008
7009
7010 (define_insn "*return_si"
7011 [(return)
7012 (use (match_operand:SI 0 "register_operand" "a"))]
7013 "!TARGET_64BIT"
7014 "br\\t%0"
7015 [(set_attr "op_type" "RR")
7016 (set_attr "type" "jsr")
7017 (set_attr "atype" "agen")])
7018
7019 (define_insn "*return_di"
7020 [(return)
7021 (use (match_operand:DI 0 "register_operand" "a"))]
7022 "TARGET_64BIT"
7023 "br\\t%0"
7024 [(set_attr "op_type" "RR")
7025 (set_attr "type" "jsr")
7026 (set_attr "atype" "agen")])
7027
7028 (define_insn "literal_pool_31"
7029 [(unspec_volatile [(const_int 0)] 300)
7030 (set (match_operand:SI 0 "register_operand" "=a")
7031 (label_ref (match_operand 1 "" "")))
7032 (use (label_ref (match_operand 2 "" "")))]
7033 ""
7034 "*
7035 {
7036 if (s390_nr_constants) {
7037 output_asm_insn (\"bras\\t%0,%2\", operands);
7038 s390_output_constant_pool (operands[1], operands[2]);
7039 }
7040 return \"\";
7041 }"
7042 [(set_attr "op_type" "NN")
7043 (set_attr "type" "larl")])
7044
7045 (define_insn "literal_pool_64"
7046 [(unspec_volatile [(const_int 0)] 300)
7047 (set (match_operand:DI 0 "register_operand" "=a")
7048 (label_ref (match_operand 1 "" "")))
7049 (use (label_ref (match_operand 2 "" "")))]
7050 ""
7051 "*
7052 {
7053 if (s390_nr_constants) {
7054 output_asm_insn (\"larl\\t%0,%1\", operands);
7055 s390_output_constant_pool (operands[1], operands[2]);
7056 }
7057 return \"\";
7058 }"
7059 [(set_attr "op_type" "NN")
7060 (set_attr "type" "larl")])