1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
60 (define_c_enum "unspec" [
68 ; GOT/PLT and lt-relative accesses
89 ; TLS relocation specifiers
105 ; Stack Smashing Protector
109 ; Test Data Class (TDC)
118 ;; UNSPEC_VOLATILE usage
121 (define_c_enum "unspecv" [
148 ; Registers with special meaning
152 ; Sibling call register.
154 ; Literal pool base register.
156 ; Return address register.
158 ; Condition code register.
160 ; Thread local storage pointer register.
164 ; Hardware register names
168 ; General purpose registers
170 ; Floating point registers.
176 ;; PFPO GPR0 argument format
181 ; PFPO operation type
182 (PFPO_CONVERT 0x1000000)
184 (PFPO_OP_TYPE_SF 0x5)
185 (PFPO_OP_TYPE_DF 0x6)
186 (PFPO_OP_TYPE_TF 0x7)
187 (PFPO_OP_TYPE_SD 0x8)
188 (PFPO_OP_TYPE_DD 0x9)
189 (PFPO_OP_TYPE_TD 0xa)
190 ; Bitposition of operand types
191 (PFPO_OP0_TYPE_SHIFT 16)
192 (PFPO_OP1_TYPE_SHIFT 8)
196 ;; Instruction operand type as used in the Principles of Operation.
197 ;; Used to determine defaults for length and other attribute values.
199 (define_attr "op_type"
200 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
203 ;; Instruction type attribute used for scheduling.
205 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
206 cs,vs,store,sem,idiv,
207 imulhi,imulsi,imuldi,
208 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
209 floadtf,floaddf,floadsf,fstoredf,fstoresf,
210 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
211 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
213 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
214 itoftf, itofdf, itofsf, itofdd, itoftd,
215 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
216 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
218 (cond [(eq_attr "op_type" "NN") (const_string "other")
219 (eq_attr "op_type" "SS") (const_string "cs")]
220 (const_string "integer")))
222 ;; Another attribute used for scheduling purposes:
223 ;; agen: Instruction uses the address generation unit
224 ;; reg: Instruction does not use the agen unit
226 (define_attr "atype" "agen,reg"
227 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
229 (const_string "agen")))
231 ;; Properties concerning Z10 execution grouping and value forwarding.
232 ;; z10_super: instruction is superscalar.
233 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
234 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
235 ;; target register. It can forward this value to a second instruction that reads
236 ;; the same register if that second instruction is issued in the same group.
237 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
238 ;; instruction in the S pipe writes to the register, then the T instruction
239 ;; can immediately read the new value.
240 ;; z10_fr: union of Z10_fwd and z10_rec.
241 ;; z10_c: second operand of instruction is a register and read with complemented bits.
243 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
246 (define_attr "z10prop" "none,
247 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
248 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
250 z10_fr, z10_fr_A3, z10_fr_E1,
252 (const_string "none"))
254 ;; Properties concerning Z196 decoding
255 ;; z196_alone: must group alone
256 ;; z196_end: ends a group
257 ;; z196_cracked: instruction is cracked or expanded
258 (define_attr "z196prop" "none,
259 z196_alone, z196_ends,
261 (const_string "none"))
263 (define_attr "mnemonic" "unknown" (const_string "unknown"))
267 (define_attr "length" ""
268 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
269 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
273 ;; Processor type. This attribute must exactly match the processor_type
274 ;; enumeration in s390.h. The current machine description does not
275 ;; distinguish between g5 and g6, but there are differences between the two
276 ;; CPUs could in theory be modeled.
278 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
279 (const (symbol_ref "s390_tune_attr")))
281 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196,zEC12"
282 (const_string "standard"))
284 (define_attr "enabled" ""
285 (cond [(eq_attr "cpu_facility" "standard")
288 (and (eq_attr "cpu_facility" "ieee")
289 (match_test "TARGET_CPU_IEEE_FLOAT"))
292 (and (eq_attr "cpu_facility" "zarch")
293 (match_test "TARGET_ZARCH"))
296 (and (eq_attr "cpu_facility" "longdisp")
297 (match_test "TARGET_LONG_DISPLACEMENT"))
300 (and (eq_attr "cpu_facility" "extimm")
301 (match_test "TARGET_EXTIMM"))
304 (and (eq_attr "cpu_facility" "dfp")
305 (match_test "TARGET_DFP"))
308 (and (eq_attr "cpu_facility" "z10")
309 (match_test "TARGET_Z10"))
312 (and (eq_attr "cpu_facility" "z196")
313 (match_test "TARGET_Z196"))
316 (and (eq_attr "cpu_facility" "zEC12")
317 (match_test "TARGET_ZEC12"))
321 ;; Pipeline description for z900. For lack of anything better,
322 ;; this description is also used for the g5 and g6.
325 ;; Pipeline description for z990, z9-109 and z9-ec.
328 ;; Pipeline description for z10
331 ;; Pipeline description for z196
334 ;; Pipeline description for zEC12
338 (include "predicates.md")
340 ;; Constraint definitions
341 (include "constraints.md")
348 ;; These mode iterators allow floating point patterns to be generated from the
350 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
351 (SD "TARGET_HARD_DFP")])
352 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
353 (define_mode_iterator FPALL [TF DF SF TD DD SD])
354 (define_mode_iterator BFP [TF DF SF])
355 (define_mode_iterator DFP [TD DD])
356 (define_mode_iterator DFP_ALL [TD DD SD])
357 (define_mode_iterator DSF [DF SF])
358 (define_mode_iterator SD_SF [SF SD])
359 (define_mode_iterator DD_DF [DF DD])
360 (define_mode_iterator TD_TF [TF TD])
362 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
363 ;; from the same template.
364 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
365 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
366 (define_mode_iterator DSI [DI SI])
367 (define_mode_iterator TDI [TI DI])
369 ;; These mode iterators allow :P to be used for patterns that operate on
370 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
371 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
373 ;; These macros refer to the actual word_mode of the configuration.
374 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
375 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
376 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
378 ;; Used by the umul pattern to express modes having half the size.
379 (define_mode_attr DWH [(TI "DI") (DI "SI")])
380 (define_mode_attr dwh [(TI "di") (DI "si")])
382 ;; This mode iterator allows the QI and HI patterns to be defined from
383 ;; the same template.
384 (define_mode_iterator HQI [HI QI])
386 ;; This mode iterator allows the integer patterns to be defined from the
388 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
389 (define_mode_iterator INTALL [TI DI SI HI QI])
390 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
392 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
393 ;; the same template.
394 (define_code_iterator SHIFT [ashift lshiftrt])
396 ;; This iterator and attribute allow to combine most atomic operations.
397 (define_code_iterator ATOMIC [and ior xor plus minus mult])
398 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
399 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
400 (plus "add") (minus "sub") (mult "nand")])
401 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
403 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
404 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
405 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
407 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
408 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
410 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
412 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
413 ;; Likewise for "<RXe>".
414 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
415 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
417 ;; The decimal floating point variants of add, sub, div and mul support 3
418 ;; fp register operands. The following attributes allow to merge the bfp and
419 ;; dfp variants in a single insn definition.
421 ;; This attribute is used to set op_type accordingly.
422 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
423 (DD "RRR") (SD "RRR")])
425 ;; This attribute is used in the operand constraint list in order to have the
426 ;; first and the second operand match for bfp modes.
427 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
429 ;; This attribute is used in the operand list of the instruction to have an
430 ;; additional operand for the dfp instructions.
431 (define_mode_attr op1 [(TF "") (DF "") (SF "")
432 (TD "%1,") (DD "%1,") (SD "%1,")])
435 ;; This attribute is used in the operand constraint list
436 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
437 ;; TFmode values are represented by a fp register pair. Since the
438 ;; sign bit instructions only handle single source and target fp registers
439 ;; these instructions can only be used for TFmode values if the source and
440 ;; target operand uses the same fp register.
441 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
443 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
444 ;; This is used to disable the memory alternative in TFmode patterns.
445 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
447 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
448 ;; within instruction mnemonics.
449 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
451 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
452 ;; modes and to an empty string for bfp modes.
453 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
455 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
456 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
457 ;; version only operates on one register.
458 (define_mode_attr d0 [(DI "d") (SI "0")])
460 ;; In combination with d0 this allows to combine instructions of which the 31bit
461 ;; version only operates on one register. The DImode version needs an additional
462 ;; register for the assembler output.
463 (define_mode_attr 1 [(DI "%1,") (SI "")])
465 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
466 ;; 'ashift' and "srdl" in 'lshiftrt'.
467 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
469 ;; In SHIFT templates, this attribute holds the correct standard name for the
470 ;; pattern itself and the corresponding function calls.
471 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
473 ;; This attribute handles differences in the instruction 'type' and will result
474 ;; in "RRE" for DImode and "RR" for SImode.
475 (define_mode_attr E [(DI "E") (SI "")])
477 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
478 ;; to result in "RXY" for DImode and "RX" for SImode.
479 (define_mode_attr Y [(DI "Y") (SI "")])
481 ;; This attribute handles differences in the instruction 'type' and will result
482 ;; in "RSE" for TImode and "RS" for DImode.
483 (define_mode_attr TE [(TI "E") (DI "")])
485 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
486 ;; and "lcr" in SImode.
487 (define_mode_attr g [(DI "g") (SI "")])
489 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
490 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
491 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
492 ;; variant for long displacements.
493 (define_mode_attr y [(DI "g") (SI "y")])
495 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
496 ;; and "cds" in DImode.
497 (define_mode_attr tg [(TI "g") (DI "")])
499 ;; In TDI templates, a string like "c<d>sg".
500 (define_mode_attr td [(TI "d") (DI "")])
502 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
503 ;; and "cfdbr" in SImode.
504 (define_mode_attr gf [(DI "g") (SI "f")])
506 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
507 ;; and sllk for SI. This way it is possible to merge the new z196 SI
508 ;; 3 operands shift instructions into the existing patterns.
509 (define_mode_attr gk [(DI "g") (SI "k")])
511 ;; ICM mask required to load MODE value into the lowest subreg
512 ;; of a SImode register.
513 (define_mode_attr icm_lo [(HI "3") (QI "1")])
515 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
516 ;; HImode and "llgc" in QImode.
517 (define_mode_attr hc [(HI "h") (QI "c")])
519 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
521 (define_mode_attr DBL [(DI "TI") (SI "DI")])
523 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
524 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
525 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
527 ;; Maximum unsigned integer that fits in MODE.
528 (define_mode_attr max_uint [(HI "65535") (QI "255")])
530 ;; Start and end field computations for RISBG et al.
531 (define_mode_attr bfstart [(DI "s") (SI "t")])
532 (define_mode_attr bfend [(DI "e") (SI "f")])
535 ;;- Compare instructions.
538 ; Test-under-Mask instructions
540 (define_insn "*tmqi_mem"
541 [(set (reg CC_REGNUM)
542 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
543 (match_operand:QI 1 "immediate_operand" "n,n"))
544 (match_operand:QI 2 "immediate_operand" "n,n")))]
545 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
549 [(set_attr "op_type" "SI,SIY")
550 (set_attr "z10prop" "z10_super,z10_super")])
552 (define_insn "*tmdi_reg"
553 [(set (reg CC_REGNUM)
554 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
555 (match_operand:DI 1 "immediate_operand"
556 "N0HD0,N1HD0,N2HD0,N3HD0"))
557 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
559 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
560 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
566 [(set_attr "op_type" "RI")
567 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
569 (define_insn "*tmsi_reg"
570 [(set (reg CC_REGNUM)
571 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
572 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
573 (match_operand:SI 2 "immediate_operand" "n,n")))]
574 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
575 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
579 [(set_attr "op_type" "RI")
580 (set_attr "z10prop" "z10_super,z10_super")])
582 (define_insn "*tm<mode>_full"
583 [(set (reg CC_REGNUM)
584 (compare (match_operand:HQI 0 "register_operand" "d")
585 (match_operand:HQI 1 "immediate_operand" "n")))]
586 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
588 [(set_attr "op_type" "RI")
589 (set_attr "z10prop" "z10_super")])
593 ; Load-and-Test instructions
596 ; tst(di|si) instruction pattern(s).
598 (define_insn "*tstdi_sign"
599 [(set (reg CC_REGNUM)
603 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
604 (const_int 32)) (const_int 32))
605 (match_operand:DI 1 "const0_operand" "")))
606 (set (match_operand:DI 2 "register_operand" "=d,d")
607 (sign_extend:DI (match_dup 0)))]
608 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
611 [(set_attr "op_type" "RRE,RXY")
612 (set_attr "cpu_facility" "*,z10")
613 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
616 (define_insn "*tst<mode>_extimm"
617 [(set (reg CC_REGNUM)
618 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
619 (match_operand:GPR 1 "const0_operand" "")))
620 (set (match_operand:GPR 2 "register_operand" "=d,d")
622 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
626 [(set_attr "op_type" "RR<E>,RXY")
627 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
630 (define_insn "*tst<mode>_cconly_extimm"
631 [(set (reg CC_REGNUM)
632 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
633 (match_operand:GPR 1 "const0_operand" "")))
634 (clobber (match_scratch:GPR 2 "=X,d"))]
635 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
639 [(set_attr "op_type" "RR<E>,RXY")
640 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
642 (define_insn "*tstdi"
643 [(set (reg CC_REGNUM)
644 (compare (match_operand:DI 0 "register_operand" "d")
645 (match_operand:DI 1 "const0_operand" "")))
646 (set (match_operand:DI 2 "register_operand" "=d")
648 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
650 [(set_attr "op_type" "RRE")
651 (set_attr "z10prop" "z10_fr_E1")])
653 (define_insn "*tstsi"
654 [(set (reg CC_REGNUM)
655 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
656 (match_operand:SI 1 "const0_operand" "")))
657 (set (match_operand:SI 2 "register_operand" "=d,d,d")
659 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
664 [(set_attr "op_type" "RR,RS,RSY")
665 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
667 (define_insn "*tstsi_cconly"
668 [(set (reg CC_REGNUM)
669 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
670 (match_operand:SI 1 "const0_operand" "")))
671 (clobber (match_scratch:SI 2 "=X,d,d"))]
672 "s390_match_ccmode(insn, CCSmode)"
677 [(set_attr "op_type" "RR,RS,RSY")
678 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
680 (define_insn "*tstdi_cconly_31"
681 [(set (reg CC_REGNUM)
682 (compare (match_operand:DI 0 "register_operand" "d")
683 (match_operand:DI 1 "const0_operand" "")))]
684 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
686 [(set_attr "op_type" "RS")
687 (set_attr "atype" "reg")])
690 (define_insn "*tst<mode>_cconly2"
691 [(set (reg CC_REGNUM)
692 (compare (match_operand:GPR 0 "register_operand" "d")
693 (match_operand:GPR 1 "const0_operand" "")))]
694 "s390_match_ccmode(insn, CCSmode)"
696 [(set_attr "op_type" "RR<E>")
697 (set_attr "z10prop" "z10_fr_E1")])
699 ; tst(hi|qi) instruction pattern(s).
701 (define_insn "*tst<mode>CCT"
702 [(set (reg CC_REGNUM)
703 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
704 (match_operand:HQI 1 "const0_operand" "")))
705 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
707 "s390_match_ccmode(insn, CCTmode)"
710 icmy\t%2,<icm_lo>,%S0
712 [(set_attr "op_type" "RS,RSY,RI")
713 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
715 (define_insn "*tsthiCCT_cconly"
716 [(set (reg CC_REGNUM)
717 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
718 (match_operand:HI 1 "const0_operand" "")))
719 (clobber (match_scratch:HI 2 "=d,d,X"))]
720 "s390_match_ccmode(insn, CCTmode)"
725 [(set_attr "op_type" "RS,RSY,RI")
726 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
728 (define_insn "*tstqiCCT_cconly"
729 [(set (reg CC_REGNUM)
730 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
731 (match_operand:QI 1 "const0_operand" "")))]
732 "s390_match_ccmode(insn, CCTmode)"
737 [(set_attr "op_type" "SI,SIY,RI")
738 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
740 (define_insn "*tst<mode>"
741 [(set (reg CC_REGNUM)
742 (compare (match_operand:HQI 0 "s_operand" "Q,S")
743 (match_operand:HQI 1 "const0_operand" "")))
744 (set (match_operand:HQI 2 "register_operand" "=d,d")
746 "s390_match_ccmode(insn, CCSmode)"
749 icmy\t%2,<icm_lo>,%S0"
750 [(set_attr "op_type" "RS,RSY")
751 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
753 (define_insn "*tst<mode>_cconly"
754 [(set (reg CC_REGNUM)
755 (compare (match_operand:HQI 0 "s_operand" "Q,S")
756 (match_operand:HQI 1 "const0_operand" "")))
757 (clobber (match_scratch:HQI 2 "=d,d"))]
758 "s390_match_ccmode(insn, CCSmode)"
761 icmy\t%2,<icm_lo>,%S0"
762 [(set_attr "op_type" "RS,RSY")
763 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
766 ; Compare (equality) instructions
768 (define_insn "*cmpdi_cct"
769 [(set (reg CC_REGNUM)
770 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
771 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
772 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
779 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
780 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
782 (define_insn "*cmpsi_cct"
783 [(set (reg CC_REGNUM)
784 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
785 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
786 "s390_match_ccmode (insn, CCTmode)"
794 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
795 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
797 ; Compare (signed) instructions
799 (define_insn "*cmpdi_ccs_sign"
800 [(set (reg CC_REGNUM)
801 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
803 (match_operand:DI 0 "register_operand" "d, d,d")))]
804 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
809 [(set_attr "op_type" "RRE,RXY,RIL")
810 (set_attr "z10prop" "z10_c,*,*")
811 (set_attr "type" "*,*,larl")])
815 (define_insn "*cmpsi_ccs_sign"
816 [(set (reg CC_REGNUM)
817 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
818 (match_operand:SI 0 "register_operand" "d,d,d")))]
819 "s390_match_ccmode(insn, CCSRmode)"
824 [(set_attr "op_type" "RX,RXY,RIL")
825 (set_attr "cpu_facility" "*,*,z10")
826 (set_attr "type" "*,*,larl")
827 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
829 (define_insn "*cmphi_ccs_z10"
830 [(set (reg CC_REGNUM)
831 (compare (match_operand:HI 0 "s_operand" "Q")
832 (match_operand:HI 1 "immediate_operand" "K")))]
833 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
835 [(set_attr "op_type" "SIL")
836 (set_attr "z196prop" "z196_cracked")])
838 (define_insn "*cmpdi_ccs_signhi_rl"
839 [(set (reg CC_REGNUM)
840 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
841 (match_operand:GPR 0 "register_operand" "d,d")))]
842 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
846 [(set_attr "op_type" "RXY,RIL")
847 (set_attr "type" "*,larl")])
849 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
850 (define_insn "*cmp<mode>_ccs"
851 [(set (reg CC_REGNUM)
852 (compare (match_operand:GPR 0 "nonimmediate_operand"
854 (match_operand:GPR 1 "general_operand"
856 "s390_match_ccmode(insn, CCSmode)"
865 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
866 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
867 (set_attr "type" "*,*,*,*,*,*,larl")
868 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
871 ; Compare (unsigned) instructions
873 (define_insn "*cmpsi_ccu_zerohi_rlsi"
874 [(set (reg CC_REGNUM)
875 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
876 "larl_operand" "X")))
877 (match_operand:SI 0 "register_operand" "d")))]
878 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
880 [(set_attr "op_type" "RIL")
881 (set_attr "type" "larl")
882 (set_attr "z10prop" "z10_super")])
885 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
886 [(set (reg CC_REGNUM)
887 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
888 "larl_operand" "X")))
889 (match_operand:GPR 0 "register_operand" "d")))]
890 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
892 [(set_attr "op_type" "RIL")
893 (set_attr "type" "larl")
894 (set_attr "z10prop" "z10_super")])
896 (define_insn "*cmpdi_ccu_zero"
897 [(set (reg CC_REGNUM)
898 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
900 (match_operand:DI 0 "register_operand" "d, d,d")))]
901 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
906 [(set_attr "op_type" "RRE,RXY,RIL")
907 (set_attr "cpu_facility" "*,*,z10")
908 (set_attr "type" "*,*,larl")
909 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
911 (define_insn "*cmpdi_ccu"
912 [(set (reg CC_REGNUM)
913 (compare (match_operand:DI 0 "nonimmediate_operand"
915 (match_operand:DI 1 "general_operand"
916 "d,Op,b,D,RT,BQ,Q")))]
917 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
926 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
927 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
928 (set_attr "type" "*,*,larl,*,*,*,*")
929 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
931 (define_insn "*cmpsi_ccu"
932 [(set (reg CC_REGNUM)
933 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
934 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
935 "s390_match_ccmode (insn, CCUmode)"
945 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
946 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
947 (set_attr "type" "*,*,larl,*,*,*,*,*")
948 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
950 (define_insn "*cmphi_ccu"
951 [(set (reg CC_REGNUM)
952 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
953 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
954 "s390_match_ccmode (insn, CCUmode)
955 && !register_operand (operands[1], HImode)"
962 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
963 (set_attr "cpu_facility" "*,*,z10,*,*")
964 (set_attr "z10prop" "*,*,z10_super,*,*")])
966 (define_insn "*cmpqi_ccu"
967 [(set (reg CC_REGNUM)
968 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
969 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
970 "s390_match_ccmode (insn, CCUmode)
971 && !register_operand (operands[1], QImode)"
979 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
980 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
983 ; Block compare (CLC) instruction patterns.
986 [(set (reg CC_REGNUM)
987 (compare (match_operand:BLK 0 "memory_operand" "Q")
988 (match_operand:BLK 1 "memory_operand" "Q")))
989 (use (match_operand 2 "const_int_operand" "n"))]
990 "s390_match_ccmode (insn, CCUmode)
991 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
992 "clc\t%O0(%2,%R0),%S1"
993 [(set_attr "op_type" "SS")])
996 [(set (reg CC_REGNUM)
997 (compare (match_operand 0 "memory_operand" "")
998 (match_operand 1 "memory_operand" "")))]
1000 && s390_match_ccmode (insn, CCUmode)
1001 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1002 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1004 [(set (match_dup 0) (match_dup 1))
1005 (use (match_dup 2))])]
1007 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1008 operands[0] = adjust_address (operands[0], BLKmode, 0);
1009 operands[1] = adjust_address (operands[1], BLKmode, 0);
1011 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1012 operands[0], operands[1]);
1013 operands[0] = SET_DEST (PATTERN (curr_insn));
1017 ; (TF|DF|SF|TD|DD|SD) instructions
1019 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1020 (define_insn "*cmp<mode>_ccs_0"
1021 [(set (reg CC_REGNUM)
1022 (compare (match_operand:FP 0 "register_operand" "f")
1023 (match_operand:FP 1 "const0_operand" "")))]
1024 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1025 "lt<xde><bt>r\t%0,%0"
1026 [(set_attr "op_type" "RRE")
1027 (set_attr "type" "fsimp<mode>")])
1029 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1030 (define_insn "*cmp<mode>_ccs"
1031 [(set (reg CC_REGNUM)
1032 (compare (match_operand:FP 0 "register_operand" "f,f")
1033 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1034 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1038 [(set_attr "op_type" "RRE,RXE")
1039 (set_attr "type" "fsimp<mode>")])
1042 ; Compare and Branch instructions
1044 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1045 ; The following instructions do a complementary access of their second
1046 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1047 (define_insn "*cmp_and_br_signed_<mode>"
1049 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1050 [(match_operand:GPR 1 "register_operand" "d,d")
1051 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1052 (label_ref (match_operand 3 "" ""))
1054 (clobber (reg:CC CC_REGNUM))]
1055 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1057 if (get_attr_length (insn) == 6)
1058 return which_alternative ?
1059 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1061 return which_alternative ?
1062 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1064 [(set_attr "op_type" "RIE")
1065 (set_attr "type" "branch")
1066 (set_attr "z10prop" "z10_super_c,z10_super")
1067 (set (attr "length")
1068 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1069 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1070 ; 10 byte for cgr/jg
1072 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1073 ; The following instructions do a complementary access of their second
1074 ; operand (z10 only): clrj, clgrj, clr, clgr
1075 (define_insn "*cmp_and_br_unsigned_<mode>"
1077 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1078 [(match_operand:GPR 1 "register_operand" "d,d")
1079 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1080 (label_ref (match_operand 3 "" ""))
1082 (clobber (reg:CC CC_REGNUM))]
1083 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1085 if (get_attr_length (insn) == 6)
1086 return which_alternative ?
1087 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1089 return which_alternative ?
1090 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1092 [(set_attr "op_type" "RIE")
1093 (set_attr "type" "branch")
1094 (set_attr "z10prop" "z10_super_c,z10_super")
1095 (set (attr "length")
1096 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1097 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1098 ; 10 byte for clgr/jg
1100 ; And now the same two patterns as above but with a negated CC mask.
1102 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1103 ; The following instructions do a complementary access of their second
1104 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1105 (define_insn "*icmp_and_br_signed_<mode>"
1107 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1108 [(match_operand:GPR 1 "register_operand" "d,d")
1109 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1111 (label_ref (match_operand 3 "" ""))))
1112 (clobber (reg:CC CC_REGNUM))]
1113 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1115 if (get_attr_length (insn) == 6)
1116 return which_alternative ?
1117 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1119 return which_alternative ?
1120 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1122 [(set_attr "op_type" "RIE")
1123 (set_attr "type" "branch")
1124 (set_attr "z10prop" "z10_super_c,z10_super")
1125 (set (attr "length")
1126 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1127 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1128 ; 10 byte for cgr/jg
1130 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1131 ; The following instructions do a complementary access of their second
1132 ; operand (z10 only): clrj, clgrj, clr, clgr
1133 (define_insn "*icmp_and_br_unsigned_<mode>"
1135 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1136 [(match_operand:GPR 1 "register_operand" "d,d")
1137 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1139 (label_ref (match_operand 3 "" ""))))
1140 (clobber (reg:CC CC_REGNUM))]
1141 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1143 if (get_attr_length (insn) == 6)
1144 return which_alternative ?
1145 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1147 return which_alternative ?
1148 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1150 [(set_attr "op_type" "RIE")
1151 (set_attr "type" "branch")
1152 (set_attr "z10prop" "z10_super_c,z10_super")
1153 (set (attr "length")
1154 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1155 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1156 ; 10 byte for clgr/jg
1159 ;;- Move instructions.
1163 ; movti instruction pattern(s).
1166 (define_insn "movti"
1167 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1168 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1175 [(set_attr "op_type" "RSY,RSY,*,*")
1176 (set_attr "type" "lm,stm,*,*")])
1179 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1180 (match_operand:TI 1 "general_operand" ""))]
1181 "TARGET_ZARCH && reload_completed
1182 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1183 [(set (match_dup 2) (match_dup 4))
1184 (set (match_dup 3) (match_dup 5))]
1186 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1187 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1188 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1189 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1193 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1194 (match_operand:TI 1 "general_operand" ""))]
1195 "TARGET_ZARCH && reload_completed
1196 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1197 [(set (match_dup 2) (match_dup 4))
1198 (set (match_dup 3) (match_dup 5))]
1200 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1201 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1202 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1203 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1207 [(set (match_operand:TI 0 "register_operand" "")
1208 (match_operand:TI 1 "memory_operand" ""))]
1209 "TARGET_ZARCH && reload_completed
1210 && !s_operand (operands[1], VOIDmode)"
1211 [(set (match_dup 0) (match_dup 1))]
1213 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1214 addr = gen_lowpart (Pmode, addr);
1215 s390_load_address (addr, XEXP (operands[1], 0));
1216 operands[1] = replace_equiv_address (operands[1], addr);
1221 ; Patterns used for secondary reloads
1224 ; z10 provides move instructions accepting larl memory operands.
1225 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1226 ; These patterns are also used for unaligned SI and DI accesses.
1228 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1229 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1230 (match_operand:INTALL 1 "register_operand" "=d")
1231 (match_operand:P 2 "register_operand" "=&a")])]
1234 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1238 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1239 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1240 (match_operand:INTALL 1 "memory_operand" "")
1241 (match_operand:P 2 "register_operand" "=a")])]
1244 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1248 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1249 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1250 (match_operand:FPALL 1 "register_operand" "=d")
1251 (match_operand:P 2 "register_operand" "=&a")])]
1254 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1258 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1259 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1260 (match_operand:FPALL 1 "memory_operand" "")
1261 (match_operand:P 2 "register_operand" "=a")])]
1264 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1268 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1269 [(parallel [(match_operand:P 0 "register_operand" "=d")
1270 (match_operand:P 1 "larl_operand" "")
1271 (match_operand:P 2 "register_operand" "=a")])]
1274 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1278 ; Handles loading a PLUS (load address) expression
1280 (define_expand "reload<mode>_plus"
1281 [(parallel [(match_operand:P 0 "register_operand" "=a")
1282 (match_operand:P 1 "s390_plus_operand" "")
1283 (match_operand:P 2 "register_operand" "=&a")])]
1286 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1290 ; Handles assessing a non-offsetable memory address
1292 (define_expand "reload<mode>_nonoffmem_in"
1293 [(parallel [(match_operand 0 "register_operand" "")
1294 (match_operand 1 "" "")
1295 (match_operand:P 2 "register_operand" "=&a")])]
1298 gcc_assert (MEM_P (operands[1]));
1299 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1300 operands[1] = replace_equiv_address (operands[1], operands[2]);
1301 emit_move_insn (operands[0], operands[1]);
1305 (define_expand "reload<mode>_nonoffmem_out"
1306 [(parallel [(match_operand 0 "" "")
1307 (match_operand 1 "register_operand" "")
1308 (match_operand:P 2 "register_operand" "=&a")])]
1311 gcc_assert (MEM_P (operands[0]));
1312 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1313 operands[0] = replace_equiv_address (operands[0], operands[2]);
1314 emit_move_insn (operands[0], operands[1]);
1318 (define_expand "reload<mode>_PIC_addr"
1319 [(parallel [(match_operand 0 "register_operand" "=d")
1320 (match_operand 1 "larl_operand" "")
1321 (match_operand:P 2 "register_operand" "=a")])]
1324 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1325 emit_move_insn (operands[0], new_rtx);
1329 ; movdi instruction pattern(s).
1332 (define_expand "movdi"
1333 [(set (match_operand:DI 0 "general_operand" "")
1334 (match_operand:DI 1 "general_operand" ""))]
1337 /* Handle symbolic constants. */
1339 && (SYMBOLIC_CONST (operands[1])
1340 || (GET_CODE (operands[1]) == PLUS
1341 && XEXP (operands[1], 0) == pic_offset_table_rtx
1342 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1343 emit_symbolic_move (operands);
1346 (define_insn "*movdi_larl"
1347 [(set (match_operand:DI 0 "register_operand" "=d")
1348 (match_operand:DI 1 "larl_operand" "X"))]
1350 && !FP_REG_P (operands[0])"
1352 [(set_attr "op_type" "RIL")
1353 (set_attr "type" "larl")
1354 (set_attr "z10prop" "z10_super_A1")])
1356 (define_insn "*movdi_64"
1357 [(set (match_operand:DI 0 "nonimmediate_operand"
1358 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1359 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1360 (match_operand:DI 1 "general_operand"
1361 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1362 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1391 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1392 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1393 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1394 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1396 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1397 z10,*,*,*,*,*,longdisp,*,longdisp,
1399 (set_attr "z10prop" "z10_fwd_A1,
1428 [(set (match_operand:DI 0 "register_operand" "")
1429 (match_operand:DI 1 "register_operand" ""))]
1430 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1431 [(set (match_dup 2) (match_dup 3))
1432 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1433 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1434 "operands[2] = gen_lowpart (SImode, operands[0]);
1435 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1438 [(set (match_operand:DI 0 "register_operand" "")
1439 (match_operand:DI 1 "register_operand" ""))]
1440 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1441 && dead_or_set_p (insn, operands[1])"
1442 [(set (match_dup 3) (match_dup 2))
1443 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1444 (set (match_dup 4) (match_dup 2))]
1445 "operands[2] = gen_lowpart (SImode, operands[1]);
1446 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1449 [(set (match_operand:DI 0 "register_operand" "")
1450 (match_operand:DI 1 "register_operand" ""))]
1451 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1452 && !dead_or_set_p (insn, operands[1])"
1453 [(set (match_dup 3) (match_dup 2))
1454 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1455 (set (match_dup 4) (match_dup 2))
1456 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1457 "operands[2] = gen_lowpart (SImode, operands[1]);
1458 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1460 (define_insn "*movdi_31"
1461 [(set (match_operand:DI 0 "nonimmediate_operand"
1462 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1463 (match_operand:DI 1 "general_operand"
1464 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1479 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1480 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1481 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1483 ; For a load from a symbol ref we can use one of the target registers
1484 ; together with larl to load the address.
1486 [(set (match_operand:DI 0 "register_operand" "")
1487 (match_operand:DI 1 "memory_operand" ""))]
1488 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1489 && larl_operand (XEXP (operands[1], 0), SImode)"
1490 [(set (match_dup 2) (match_dup 3))
1491 (set (match_dup 0) (match_dup 1))]
1493 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1494 operands[3] = XEXP (operands[1], 0);
1495 operands[1] = replace_equiv_address (operands[1], operands[2]);
1499 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1500 (match_operand:DI 1 "general_operand" ""))]
1501 "!TARGET_ZARCH && reload_completed
1502 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1503 [(set (match_dup 2) (match_dup 4))
1504 (set (match_dup 3) (match_dup 5))]
1506 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1507 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1508 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1509 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1513 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1514 (match_operand:DI 1 "general_operand" ""))]
1515 "!TARGET_ZARCH && reload_completed
1516 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1517 [(set (match_dup 2) (match_dup 4))
1518 (set (match_dup 3) (match_dup 5))]
1520 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1521 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1522 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1523 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1527 [(set (match_operand:DI 0 "register_operand" "")
1528 (match_operand:DI 1 "memory_operand" ""))]
1529 "!TARGET_ZARCH && reload_completed
1530 && !FP_REG_P (operands[0])
1531 && !s_operand (operands[1], VOIDmode)"
1532 [(set (match_dup 0) (match_dup 1))]
1534 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1535 s390_load_address (addr, XEXP (operands[1], 0));
1536 operands[1] = replace_equiv_address (operands[1], addr);
1540 [(set (match_operand:DI 0 "register_operand" "")
1541 (mem:DI (match_operand 1 "address_operand" "")))]
1543 && !FP_REG_P (operands[0])
1544 && GET_CODE (operands[1]) == SYMBOL_REF
1545 && CONSTANT_POOL_ADDRESS_P (operands[1])
1546 && get_pool_mode (operands[1]) == DImode
1547 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1548 [(set (match_dup 0) (match_dup 2))]
1549 "operands[2] = get_pool_constant (operands[1]);")
1551 (define_insn "*la_64"
1552 [(set (match_operand:DI 0 "register_operand" "=d,d")
1553 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1558 [(set_attr "op_type" "RX,RXY")
1559 (set_attr "type" "la")
1560 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1564 [(set (match_operand:DI 0 "register_operand" "")
1565 (match_operand:QI 1 "address_operand" ""))
1566 (clobber (reg:CC CC_REGNUM))])]
1568 && preferred_la_operand_p (operands[1], const0_rtx)"
1569 [(set (match_dup 0) (match_dup 1))]
1573 [(set (match_operand:DI 0 "register_operand" "")
1574 (match_operand:DI 1 "register_operand" ""))
1577 (plus:DI (match_dup 0)
1578 (match_operand:DI 2 "nonmemory_operand" "")))
1579 (clobber (reg:CC CC_REGNUM))])]
1581 && !reg_overlap_mentioned_p (operands[0], operands[2])
1582 && preferred_la_operand_p (operands[1], operands[2])"
1583 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1587 ; movsi instruction pattern(s).
1590 (define_expand "movsi"
1591 [(set (match_operand:SI 0 "general_operand" "")
1592 (match_operand:SI 1 "general_operand" ""))]
1595 /* Handle symbolic constants. */
1597 && (SYMBOLIC_CONST (operands[1])
1598 || (GET_CODE (operands[1]) == PLUS
1599 && XEXP (operands[1], 0) == pic_offset_table_rtx
1600 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1601 emit_symbolic_move (operands);
1604 (define_insn "*movsi_larl"
1605 [(set (match_operand:SI 0 "register_operand" "=d")
1606 (match_operand:SI 1 "larl_operand" "X"))]
1607 "!TARGET_64BIT && TARGET_CPU_ZARCH
1608 && !FP_REG_P (operands[0])"
1610 [(set_attr "op_type" "RIL")
1611 (set_attr "type" "larl")
1612 (set_attr "z10prop" "z10_fwd_A1")])
1614 (define_insn "*movsi_zarch"
1615 [(set (match_operand:SI 0 "nonimmediate_operand"
1616 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1617 (match_operand:SI 1 "general_operand"
1618 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1643 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1644 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1645 (set_attr "type" "*,
1667 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1668 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1669 (set_attr "z10prop" "z10_fwd_A1,
1692 (define_insn "*movsi_esa"
1693 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1694 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1708 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1709 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1710 (set_attr "z10prop" "z10_fwd_A1,
1724 [(set (match_operand:SI 0 "register_operand" "")
1725 (mem:SI (match_operand 1 "address_operand" "")))]
1726 "!FP_REG_P (operands[0])
1727 && GET_CODE (operands[1]) == SYMBOL_REF
1728 && CONSTANT_POOL_ADDRESS_P (operands[1])
1729 && get_pool_mode (operands[1]) == SImode
1730 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1731 [(set (match_dup 0) (match_dup 2))]
1732 "operands[2] = get_pool_constant (operands[1]);")
1734 (define_insn "*la_31"
1735 [(set (match_operand:SI 0 "register_operand" "=d,d")
1736 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1737 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1741 [(set_attr "op_type" "RX,RXY")
1742 (set_attr "type" "la")
1743 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1747 [(set (match_operand:SI 0 "register_operand" "")
1748 (match_operand:QI 1 "address_operand" ""))
1749 (clobber (reg:CC CC_REGNUM))])]
1751 && preferred_la_operand_p (operands[1], const0_rtx)"
1752 [(set (match_dup 0) (match_dup 1))]
1756 [(set (match_operand:SI 0 "register_operand" "")
1757 (match_operand:SI 1 "register_operand" ""))
1760 (plus:SI (match_dup 0)
1761 (match_operand:SI 2 "nonmemory_operand" "")))
1762 (clobber (reg:CC CC_REGNUM))])]
1764 && !reg_overlap_mentioned_p (operands[0], operands[2])
1765 && preferred_la_operand_p (operands[1], operands[2])"
1766 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1769 (define_insn "*la_31_and"
1770 [(set (match_operand:SI 0 "register_operand" "=d,d")
1771 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1772 (const_int 2147483647)))]
1777 [(set_attr "op_type" "RX,RXY")
1778 (set_attr "type" "la")
1779 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1781 (define_insn_and_split "*la_31_and_cc"
1782 [(set (match_operand:SI 0 "register_operand" "=d")
1783 (and:SI (match_operand:QI 1 "address_operand" "p")
1784 (const_int 2147483647)))
1785 (clobber (reg:CC CC_REGNUM))]
1788 "&& reload_completed"
1790 (and:SI (match_dup 1) (const_int 2147483647)))]
1792 [(set_attr "op_type" "RX")
1793 (set_attr "type" "la")])
1795 (define_insn "force_la_31"
1796 [(set (match_operand:SI 0 "register_operand" "=d,d")
1797 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1798 (use (const_int 0))]
1803 [(set_attr "op_type" "RX")
1804 (set_attr "type" "la")
1805 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1808 ; movhi instruction pattern(s).
1811 (define_expand "movhi"
1812 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1813 (match_operand:HI 1 "general_operand" ""))]
1816 /* Make it explicit that loading a register from memory
1817 always sign-extends (at least) to SImode. */
1818 if (optimize && can_create_pseudo_p ()
1819 && register_operand (operands[0], VOIDmode)
1820 && GET_CODE (operands[1]) == MEM)
1822 rtx tmp = gen_reg_rtx (SImode);
1823 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1824 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1825 operands[1] = gen_lowpart (HImode, tmp);
1829 (define_insn "*movhi"
1830 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1831 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1843 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1844 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1845 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1846 (set_attr "z10prop" "z10_fr_E1,
1857 [(set (match_operand:HI 0 "register_operand" "")
1858 (mem:HI (match_operand 1 "address_operand" "")))]
1859 "GET_CODE (operands[1]) == SYMBOL_REF
1860 && CONSTANT_POOL_ADDRESS_P (operands[1])
1861 && get_pool_mode (operands[1]) == HImode
1862 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1863 [(set (match_dup 0) (match_dup 2))]
1864 "operands[2] = get_pool_constant (operands[1]);")
1867 ; movqi instruction pattern(s).
1870 (define_expand "movqi"
1871 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1872 (match_operand:QI 1 "general_operand" ""))]
1875 /* On z/Architecture, zero-extending from memory to register
1876 is just as fast as a QImode load. */
1877 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1878 && register_operand (operands[0], VOIDmode)
1879 && GET_CODE (operands[1]) == MEM)
1881 rtx tmp = gen_reg_rtx (DImode);
1882 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1883 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1884 operands[1] = gen_lowpart (QImode, tmp);
1888 (define_insn "*movqi"
1889 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1890 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1902 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1903 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1904 (set_attr "z10prop" "z10_fr_E1,
1915 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1916 (mem:QI (match_operand 1 "address_operand" "")))]
1917 "GET_CODE (operands[1]) == SYMBOL_REF
1918 && CONSTANT_POOL_ADDRESS_P (operands[1])
1919 && get_pool_mode (operands[1]) == QImode
1920 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1921 [(set (match_dup 0) (match_dup 2))]
1922 "operands[2] = get_pool_constant (operands[1]);")
1925 ; movstrictqi instruction pattern(s).
1928 (define_insn "*movstrictqi"
1929 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1930 (match_operand:QI 1 "memory_operand" "R,T"))]
1935 [(set_attr "op_type" "RX,RXY")
1936 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1939 ; movstricthi instruction pattern(s).
1942 (define_insn "*movstricthi"
1943 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1944 (match_operand:HI 1 "memory_operand" "Q,S"))
1945 (clobber (reg:CC CC_REGNUM))]
1950 [(set_attr "op_type" "RS,RSY")
1951 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1954 ; movstrictsi instruction pattern(s).
1957 (define_insn "movstrictsi"
1958 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1959 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1966 [(set_attr "op_type" "RR,RX,RXY,RRE")
1967 (set_attr "type" "lr,load,load,*")
1968 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1971 ; mov(tf|td) instruction pattern(s).
1974 (define_expand "mov<mode>"
1975 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1976 (match_operand:TD_TF 1 "general_operand" ""))]
1980 (define_insn "*mov<mode>_64"
1981 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1982 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1993 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1994 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
1995 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
1997 (define_insn "*mov<mode>_31"
1998 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1999 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2006 [(set_attr "op_type" "RRE,RRE,*,*")
2007 (set_attr "type" "fsimptf,fsimptf,*,*")
2008 (set_attr "cpu_facility" "z196,*,*,*")])
2010 ; TFmode in GPRs splitters
2013 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2014 (match_operand:TD_TF 1 "general_operand" ""))]
2015 "TARGET_ZARCH && reload_completed
2016 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2017 [(set (match_dup 2) (match_dup 4))
2018 (set (match_dup 3) (match_dup 5))]
2020 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2021 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2022 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2023 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2027 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2028 (match_operand:TD_TF 1 "general_operand" ""))]
2029 "TARGET_ZARCH && reload_completed
2030 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2031 [(set (match_dup 2) (match_dup 4))
2032 (set (match_dup 3) (match_dup 5))]
2034 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2035 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2036 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2037 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2041 [(set (match_operand:TD_TF 0 "register_operand" "")
2042 (match_operand:TD_TF 1 "memory_operand" ""))]
2043 "TARGET_ZARCH && reload_completed
2044 && !FP_REG_P (operands[0])
2045 && !s_operand (operands[1], VOIDmode)"
2046 [(set (match_dup 0) (match_dup 1))]
2048 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2049 addr = gen_lowpart (Pmode, addr);
2050 s390_load_address (addr, XEXP (operands[1], 0));
2051 operands[1] = replace_equiv_address (operands[1], addr);
2054 ; TFmode in BFPs splitters
2057 [(set (match_operand:TD_TF 0 "register_operand" "")
2058 (match_operand:TD_TF 1 "memory_operand" ""))]
2059 "reload_completed && offsettable_memref_p (operands[1])
2060 && FP_REG_P (operands[0])"
2061 [(set (match_dup 2) (match_dup 4))
2062 (set (match_dup 3) (match_dup 5))]
2064 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2066 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2068 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2069 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2073 [(set (match_operand:TD_TF 0 "memory_operand" "")
2074 (match_operand:TD_TF 1 "register_operand" ""))]
2075 "reload_completed && offsettable_memref_p (operands[0])
2076 && FP_REG_P (operands[1])"
2077 [(set (match_dup 2) (match_dup 4))
2078 (set (match_dup 3) (match_dup 5))]
2080 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2081 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2082 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2084 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2089 ; mov(df|dd) instruction pattern(s).
2092 (define_expand "mov<mode>"
2093 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2094 (match_operand:DD_DF 1 "general_operand" ""))]
2098 (define_insn "*mov<mode>_64dfp"
2099 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2100 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2101 (match_operand:DD_DF 1 "general_operand"
2102 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2117 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2118 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2119 fstoredf,fstoredf,*,lr,load,store")
2120 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2121 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2123 (define_insn "*mov<mode>_64"
2124 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2125 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2138 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2139 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2140 fstore<mode>,fstore<mode>,*,lr,load,store")
2141 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2142 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2144 (define_insn "*mov<mode>_31"
2145 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2146 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2147 (match_operand:DD_DF 1 "general_operand"
2148 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2163 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2164 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2165 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2166 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2169 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2170 (match_operand:DD_DF 1 "general_operand" ""))]
2171 "!TARGET_ZARCH && reload_completed
2172 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2173 [(set (match_dup 2) (match_dup 4))
2174 (set (match_dup 3) (match_dup 5))]
2176 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2177 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2178 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2179 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2183 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2184 (match_operand:DD_DF 1 "general_operand" ""))]
2185 "!TARGET_ZARCH && reload_completed
2186 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2187 [(set (match_dup 2) (match_dup 4))
2188 (set (match_dup 3) (match_dup 5))]
2190 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2191 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2192 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2193 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2197 [(set (match_operand:DD_DF 0 "register_operand" "")
2198 (match_operand:DD_DF 1 "memory_operand" ""))]
2199 "!TARGET_ZARCH && reload_completed
2200 && !FP_REG_P (operands[0])
2201 && !s_operand (operands[1], VOIDmode)"
2202 [(set (match_dup 0) (match_dup 1))]
2204 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2205 s390_load_address (addr, XEXP (operands[1], 0));
2206 operands[1] = replace_equiv_address (operands[1], addr);
2210 ; mov(sf|sd) instruction pattern(s).
2213 (define_insn "mov<mode>"
2214 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2215 "=f,f,f,f,R,T,d,d,d,d,R,T")
2216 (match_operand:SD_SF 1 "general_operand"
2217 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2232 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2233 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2234 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2235 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2236 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2239 ; movcc instruction pattern
2242 (define_insn "movcc"
2243 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2244 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2254 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2255 (set_attr "type" "lr,*,*,store,store,load,load")
2256 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2257 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2260 ; Block move (MVC) patterns.
2264 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2265 (match_operand:BLK 1 "memory_operand" "Q"))
2266 (use (match_operand 2 "const_int_operand" "n"))]
2267 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2268 "mvc\t%O0(%2,%R0),%S1"
2269 [(set_attr "op_type" "SS")])
2271 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2272 ; order to have it implemented with mvc.
2275 [(set (match_operand:QI 0 "memory_operand" "")
2276 (match_operand:QI 1 "memory_operand" ""))]
2279 [(set (match_dup 0) (match_dup 1))
2280 (use (const_int 1))])]
2282 operands[0] = adjust_address (operands[0], BLKmode, 0);
2283 operands[1] = adjust_address (operands[1], BLKmode, 0);
2289 [(set (match_operand:BLK 0 "memory_operand" "")
2290 (match_operand:BLK 1 "memory_operand" ""))
2291 (use (match_operand 2 "const_int_operand" ""))])
2293 [(set (match_operand:BLK 3 "memory_operand" "")
2294 (match_operand:BLK 4 "memory_operand" ""))
2295 (use (match_operand 5 "const_int_operand" ""))])]
2296 "s390_offset_p (operands[0], operands[3], operands[2])
2297 && s390_offset_p (operands[1], operands[4], operands[2])
2298 && !s390_overlap_p (operands[0], operands[1],
2299 INTVAL (operands[2]) + INTVAL (operands[5]))
2300 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2302 [(set (match_dup 6) (match_dup 7))
2303 (use (match_dup 8))])]
2304 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2305 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2306 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2310 ; load_multiple pattern(s).
2312 ; ??? Due to reload problems with replacing registers inside match_parallel
2313 ; we currently support load_multiple/store_multiple only after reload.
2316 (define_expand "load_multiple"
2317 [(match_par_dup 3 [(set (match_operand 0 "" "")
2318 (match_operand 1 "" ""))
2319 (use (match_operand 2 "" ""))])]
2322 enum machine_mode mode;
2328 /* Support only loading a constant number of fixed-point registers from
2329 memory and only bother with this if more than two */
2330 if (GET_CODE (operands[2]) != CONST_INT
2331 || INTVAL (operands[2]) < 2
2332 || INTVAL (operands[2]) > 16
2333 || GET_CODE (operands[1]) != MEM
2334 || GET_CODE (operands[0]) != REG
2335 || REGNO (operands[0]) >= 16)
2338 count = INTVAL (operands[2]);
2339 regno = REGNO (operands[0]);
2340 mode = GET_MODE (operands[0]);
2341 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2344 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2345 if (!can_create_pseudo_p ())
2347 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2349 from = XEXP (operands[1], 0);
2352 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2353 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2354 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2356 from = XEXP (XEXP (operands[1], 0), 0);
2357 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2364 from = force_reg (Pmode, XEXP (operands[1], 0));
2368 for (i = 0; i < count; i++)
2369 XVECEXP (operands[3], 0, i)
2370 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2371 change_address (operands[1], mode,
2372 plus_constant (Pmode, from,
2373 off + i * GET_MODE_SIZE (mode))));
2376 (define_insn "*load_multiple_di"
2377 [(match_parallel 0 "load_multiple_operation"
2378 [(set (match_operand:DI 1 "register_operand" "=r")
2379 (match_operand:DI 2 "s_operand" "QS"))])]
2380 "reload_completed && TARGET_ZARCH"
2382 int words = XVECLEN (operands[0], 0);
2383 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2384 return "lmg\t%1,%0,%S2";
2386 [(set_attr "op_type" "RSY")
2387 (set_attr "type" "lm")])
2389 (define_insn "*load_multiple_si"
2390 [(match_parallel 0 "load_multiple_operation"
2391 [(set (match_operand:SI 1 "register_operand" "=r,r")
2392 (match_operand:SI 2 "s_operand" "Q,S"))])]
2395 int words = XVECLEN (operands[0], 0);
2396 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2397 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2399 [(set_attr "op_type" "RS,RSY")
2400 (set_attr "type" "lm")])
2403 ; store multiple pattern(s).
2406 (define_expand "store_multiple"
2407 [(match_par_dup 3 [(set (match_operand 0 "" "")
2408 (match_operand 1 "" ""))
2409 (use (match_operand 2 "" ""))])]
2412 enum machine_mode mode;
2418 /* Support only storing a constant number of fixed-point registers to
2419 memory and only bother with this if more than two. */
2420 if (GET_CODE (operands[2]) != CONST_INT
2421 || INTVAL (operands[2]) < 2
2422 || INTVAL (operands[2]) > 16
2423 || GET_CODE (operands[0]) != MEM
2424 || GET_CODE (operands[1]) != REG
2425 || REGNO (operands[1]) >= 16)
2428 count = INTVAL (operands[2]);
2429 regno = REGNO (operands[1]);
2430 mode = GET_MODE (operands[1]);
2431 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2434 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2436 if (!can_create_pseudo_p ())
2438 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2440 to = XEXP (operands[0], 0);
2443 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2444 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2445 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2447 to = XEXP (XEXP (operands[0], 0), 0);
2448 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2455 to = force_reg (Pmode, XEXP (operands[0], 0));
2459 for (i = 0; i < count; i++)
2460 XVECEXP (operands[3], 0, i)
2461 = gen_rtx_SET (VOIDmode,
2462 change_address (operands[0], mode,
2463 plus_constant (Pmode, to,
2464 off + i * GET_MODE_SIZE (mode))),
2465 gen_rtx_REG (mode, regno + i));
2468 (define_insn "*store_multiple_di"
2469 [(match_parallel 0 "store_multiple_operation"
2470 [(set (match_operand:DI 1 "s_operand" "=QS")
2471 (match_operand:DI 2 "register_operand" "r"))])]
2472 "reload_completed && TARGET_ZARCH"
2474 int words = XVECLEN (operands[0], 0);
2475 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2476 return "stmg\t%2,%0,%S1";
2478 [(set_attr "op_type" "RSY")
2479 (set_attr "type" "stm")])
2482 (define_insn "*store_multiple_si"
2483 [(match_parallel 0 "store_multiple_operation"
2484 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2485 (match_operand:SI 2 "register_operand" "r,r"))])]
2488 int words = XVECLEN (operands[0], 0);
2489 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2490 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2492 [(set_attr "op_type" "RS,RSY")
2493 (set_attr "type" "stm")])
2496 ;; String instructions.
2499 (define_insn "*execute_rl"
2500 [(match_parallel 0 "execute_operation"
2501 [(unspec [(match_operand 1 "register_operand" "a")
2502 (match_operand 2 "" "")
2503 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2504 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2505 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2507 [(set_attr "op_type" "RIL")
2508 (set_attr "type" "cs")])
2510 (define_insn "*execute"
2511 [(match_parallel 0 "execute_operation"
2512 [(unspec [(match_operand 1 "register_operand" "a")
2513 (match_operand:BLK 2 "memory_operand" "R")
2514 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2515 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2516 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2518 [(set_attr "op_type" "RX")
2519 (set_attr "type" "cs")])
2523 ; strlenM instruction pattern(s).
2526 (define_expand "strlen<mode>"
2527 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2530 (unspec:P [(const_int 0)
2531 (match_operand:BLK 1 "memory_operand" "")
2533 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2534 (clobber (scratch:P))
2535 (clobber (reg:CC CC_REGNUM))])
2537 [(set (match_operand:P 0 "register_operand" "")
2538 (minus:P (match_dup 4) (match_dup 5)))
2539 (clobber (reg:CC CC_REGNUM))])]
2542 operands[4] = gen_reg_rtx (Pmode);
2543 operands[5] = gen_reg_rtx (Pmode);
2544 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2545 operands[1] = replace_equiv_address (operands[1], operands[5]);
2548 (define_insn "*strlen<mode>"
2549 [(set (match_operand:P 0 "register_operand" "=a")
2550 (unspec:P [(match_operand:P 2 "general_operand" "0")
2551 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2553 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2554 (clobber (match_scratch:P 1 "=a"))
2555 (clobber (reg:CC CC_REGNUM))]
2557 "srst\t%0,%1\;jo\t.-4"
2558 [(set_attr "length" "8")
2559 (set_attr "type" "vs")])
2562 ; cmpstrM instruction pattern(s).
2565 (define_expand "cmpstrsi"
2566 [(set (reg:SI 0) (const_int 0))
2568 [(clobber (match_operand 3 "" ""))
2569 (clobber (match_dup 4))
2570 (set (reg:CCU CC_REGNUM)
2571 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2572 (match_operand:BLK 2 "memory_operand" "")))
2575 [(set (match_operand:SI 0 "register_operand" "=d")
2576 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2577 (clobber (reg:CC CC_REGNUM))])]
2580 /* As the result of CMPINT is inverted compared to what we need,
2581 we have to swap the operands. */
2582 rtx op1 = operands[2];
2583 rtx op2 = operands[1];
2584 rtx addr1 = gen_reg_rtx (Pmode);
2585 rtx addr2 = gen_reg_rtx (Pmode);
2587 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2588 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2589 operands[1] = replace_equiv_address_nv (op1, addr1);
2590 operands[2] = replace_equiv_address_nv (op2, addr2);
2591 operands[3] = addr1;
2592 operands[4] = addr2;
2595 (define_insn "*cmpstr<mode>"
2596 [(clobber (match_operand:P 0 "register_operand" "=d"))
2597 (clobber (match_operand:P 1 "register_operand" "=d"))
2598 (set (reg:CCU CC_REGNUM)
2599 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2600 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2603 "clst\t%0,%1\;jo\t.-4"
2604 [(set_attr "length" "8")
2605 (set_attr "type" "vs")])
2608 ; movstr instruction pattern.
2611 (define_expand "movstr"
2612 [(set (reg:SI 0) (const_int 0))
2614 [(clobber (match_dup 3))
2615 (set (match_operand:BLK 1 "memory_operand" "")
2616 (match_operand:BLK 2 "memory_operand" ""))
2617 (set (match_operand 0 "register_operand" "")
2618 (unspec [(match_dup 1)
2620 (reg:SI 0)] UNSPEC_MVST))
2621 (clobber (reg:CC CC_REGNUM))])]
2624 rtx addr1 = gen_reg_rtx (Pmode);
2625 rtx addr2 = gen_reg_rtx (Pmode);
2627 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2628 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2629 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2630 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2631 operands[3] = addr2;
2634 (define_insn "*movstr"
2635 [(clobber (match_operand:P 2 "register_operand" "=d"))
2636 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2637 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2638 (set (match_operand:P 0 "register_operand" "=d")
2639 (unspec [(mem:BLK (match_dup 1))
2640 (mem:BLK (match_dup 3))
2641 (reg:SI 0)] UNSPEC_MVST))
2642 (clobber (reg:CC CC_REGNUM))]
2644 "mvst\t%1,%2\;jo\t.-4"
2645 [(set_attr "length" "8")
2646 (set_attr "type" "vs")])
2650 ; movmemM instruction pattern(s).
2653 (define_expand "movmem<mode>"
2654 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2655 (match_operand:BLK 1 "memory_operand" "")) ; source
2656 (use (match_operand:GPR 2 "general_operand" "")) ; count
2657 (match_operand 3 "" "")]
2660 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2666 ; Move a block that is up to 256 bytes in length.
2667 ; The block length is taken as (operands[2] % 256) + 1.
2669 (define_expand "movmem_short"
2671 [(set (match_operand:BLK 0 "memory_operand" "")
2672 (match_operand:BLK 1 "memory_operand" ""))
2673 (use (match_operand 2 "nonmemory_operand" ""))
2674 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2675 (clobber (match_dup 3))])]
2677 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2679 (define_insn "*movmem_short"
2680 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2681 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2682 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2683 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2684 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2685 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2687 [(set_attr "type" "cs")
2688 (set_attr "cpu_facility" "*,*,z10,*")])
2691 [(set (match_operand:BLK 0 "memory_operand" "")
2692 (match_operand:BLK 1 "memory_operand" ""))
2693 (use (match_operand 2 "const_int_operand" ""))
2694 (use (match_operand 3 "immediate_operand" ""))
2695 (clobber (scratch))]
2698 [(set (match_dup 0) (match_dup 1))
2699 (use (match_dup 2))])]
2700 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2703 [(set (match_operand:BLK 0 "memory_operand" "")
2704 (match_operand:BLK 1 "memory_operand" ""))
2705 (use (match_operand 2 "register_operand" ""))
2706 (use (match_operand 3 "memory_operand" ""))
2707 (clobber (scratch))]
2710 [(unspec [(match_dup 2) (match_dup 3)
2711 (const_int 0)] UNSPEC_EXECUTE)
2712 (set (match_dup 0) (match_dup 1))
2713 (use (const_int 1))])]
2717 [(set (match_operand:BLK 0 "memory_operand" "")
2718 (match_operand:BLK 1 "memory_operand" ""))
2719 (use (match_operand 2 "register_operand" ""))
2720 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2721 (clobber (scratch))]
2722 "TARGET_Z10 && reload_completed"
2724 [(unspec [(match_dup 2) (const_int 0)
2725 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2726 (set (match_dup 0) (match_dup 1))
2727 (use (const_int 1))])]
2728 "operands[3] = gen_label_rtx ();")
2731 [(set (match_operand:BLK 0 "memory_operand" "")
2732 (match_operand:BLK 1 "memory_operand" ""))
2733 (use (match_operand 2 "register_operand" ""))
2734 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2735 (clobber (match_operand 3 "register_operand" ""))]
2736 "reload_completed && TARGET_CPU_ZARCH"
2737 [(set (match_dup 3) (label_ref (match_dup 4)))
2739 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2740 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2741 (set (match_dup 0) (match_dup 1))
2742 (use (const_int 1))])]
2743 "operands[4] = gen_label_rtx ();")
2745 ; Move a block of arbitrary length.
2747 (define_expand "movmem_long"
2749 [(clobber (match_dup 2))
2750 (clobber (match_dup 3))
2751 (set (match_operand:BLK 0 "memory_operand" "")
2752 (match_operand:BLK 1 "memory_operand" ""))
2753 (use (match_operand 2 "general_operand" ""))
2755 (clobber (reg:CC CC_REGNUM))])]
2758 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2759 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2760 rtx reg0 = gen_reg_rtx (dreg_mode);
2761 rtx reg1 = gen_reg_rtx (dreg_mode);
2762 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2763 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2764 rtx len0 = gen_lowpart (Pmode, reg0);
2765 rtx len1 = gen_lowpart (Pmode, reg1);
2767 emit_clobber (reg0);
2768 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2769 emit_move_insn (len0, operands[2]);
2771 emit_clobber (reg1);
2772 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2773 emit_move_insn (len1, operands[2]);
2775 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2776 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2781 (define_insn "*movmem_long"
2782 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2783 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2784 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2785 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2788 (clobber (reg:CC CC_REGNUM))]
2789 "TARGET_64BIT || !TARGET_ZARCH"
2790 "mvcle\t%0,%1,0\;jo\t.-4"
2791 [(set_attr "length" "8")
2792 (set_attr "type" "vs")])
2794 (define_insn "*movmem_long_31z"
2795 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2796 (clobber (match_operand:TI 1 "register_operand" "=d"))
2797 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2798 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2801 (clobber (reg:CC CC_REGNUM))]
2802 "!TARGET_64BIT && TARGET_ZARCH"
2803 "mvcle\t%0,%1,0\;jo\t.-4"
2804 [(set_attr "length" "8")
2805 (set_attr "type" "vs")])
2812 (define_expand "signbit<mode>2"
2813 [(set (reg:CCZ CC_REGNUM)
2814 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2817 (set (match_operand:SI 0 "register_operand" "=d")
2818 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2821 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2824 (define_expand "isinf<mode>2"
2825 [(set (reg:CCZ CC_REGNUM)
2826 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2829 (set (match_operand:SI 0 "register_operand" "=d")
2830 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2833 operands[2] = GEN_INT (S390_TDC_INFINITY);
2836 ; This insn is used to generate all variants of the Test Data Class
2837 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2838 ; is the register to be tested and the second one is the bit mask
2839 ; specifying the required test(s).
2841 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2842 (define_insn "*TDC_insn_<mode>"
2843 [(set (reg:CCZ CC_REGNUM)
2844 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2845 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2847 "t<_d>c<xde><bt>\t%0,%1"
2848 [(set_attr "op_type" "RXE")
2849 (set_attr "type" "fsimp<mode>")])
2851 (define_insn_and_split "*ccz_to_int"
2852 [(set (match_operand:SI 0 "register_operand" "=d")
2853 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2854 UNSPEC_CCZ_TO_INT))]
2858 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2862 ; setmemM instruction pattern(s).
2865 (define_expand "setmem<mode>"
2866 [(set (match_operand:BLK 0 "memory_operand" "")
2867 (match_operand:QI 2 "general_operand" ""))
2868 (use (match_operand:GPR 1 "general_operand" ""))
2869 (match_operand 3 "" "")]
2871 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2873 ; Clear a block that is up to 256 bytes in length.
2874 ; The block length is taken as (operands[1] % 256) + 1.
2876 (define_expand "clrmem_short"
2878 [(set (match_operand:BLK 0 "memory_operand" "")
2880 (use (match_operand 1 "nonmemory_operand" ""))
2881 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2882 (clobber (match_dup 2))
2883 (clobber (reg:CC CC_REGNUM))])]
2885 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2887 (define_insn "*clrmem_short"
2888 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2890 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2891 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2892 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2893 (clobber (reg:CC CC_REGNUM))]
2894 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2896 [(set_attr "type" "cs")
2897 (set_attr "cpu_facility" "*,*,z10,*")])
2900 [(set (match_operand:BLK 0 "memory_operand" "")
2902 (use (match_operand 1 "const_int_operand" ""))
2903 (use (match_operand 2 "immediate_operand" ""))
2905 (clobber (reg:CC CC_REGNUM))]
2908 [(set (match_dup 0) (const_int 0))
2910 (clobber (reg:CC CC_REGNUM))])]
2911 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2914 [(set (match_operand:BLK 0 "memory_operand" "")
2916 (use (match_operand 1 "register_operand" ""))
2917 (use (match_operand 2 "memory_operand" ""))
2919 (clobber (reg:CC CC_REGNUM))]
2922 [(unspec [(match_dup 1) (match_dup 2)
2923 (const_int 0)] UNSPEC_EXECUTE)
2924 (set (match_dup 0) (const_int 0))
2926 (clobber (reg:CC CC_REGNUM))])]
2930 [(set (match_operand:BLK 0 "memory_operand" "")
2932 (use (match_operand 1 "register_operand" ""))
2933 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2935 (clobber (reg:CC CC_REGNUM))]
2936 "TARGET_Z10 && reload_completed"
2938 [(unspec [(match_dup 1) (const_int 0)
2939 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2940 (set (match_dup 0) (const_int 0))
2942 (clobber (reg:CC CC_REGNUM))])]
2943 "operands[3] = gen_label_rtx ();")
2946 [(set (match_operand:BLK 0 "memory_operand" "")
2948 (use (match_operand 1 "register_operand" ""))
2949 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2950 (clobber (match_operand 2 "register_operand" ""))
2951 (clobber (reg:CC CC_REGNUM))]
2952 "reload_completed && TARGET_CPU_ZARCH"
2953 [(set (match_dup 2) (label_ref (match_dup 3)))
2955 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2956 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2957 (set (match_dup 0) (const_int 0))
2959 (clobber (reg:CC CC_REGNUM))])]
2960 "operands[3] = gen_label_rtx ();")
2962 ; Initialize a block of arbitrary length with (operands[2] % 256).
2964 (define_expand "setmem_long"
2966 [(clobber (match_dup 1))
2967 (set (match_operand:BLK 0 "memory_operand" "")
2968 (match_operand 2 "shift_count_or_setmem_operand" ""))
2969 (use (match_operand 1 "general_operand" ""))
2971 (clobber (reg:CC CC_REGNUM))])]
2974 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2975 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2976 rtx reg0 = gen_reg_rtx (dreg_mode);
2977 rtx reg1 = gen_reg_rtx (dreg_mode);
2978 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2979 rtx len0 = gen_lowpart (Pmode, reg0);
2981 emit_clobber (reg0);
2982 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2983 emit_move_insn (len0, operands[1]);
2985 emit_move_insn (reg1, const0_rtx);
2987 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2992 (define_insn "*setmem_long"
2993 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2994 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2995 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2997 (use (match_operand:<DBL> 1 "register_operand" "d"))
2998 (clobber (reg:CC CC_REGNUM))]
2999 "TARGET_64BIT || !TARGET_ZARCH"
3000 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3001 [(set_attr "length" "8")
3002 (set_attr "type" "vs")])
3004 (define_insn "*setmem_long_and"
3005 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3006 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3007 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3008 (match_operand 4 "const_int_operand" "n")))
3010 (use (match_operand:<DBL> 1 "register_operand" "d"))
3011 (clobber (reg:CC CC_REGNUM))]
3012 "(TARGET_64BIT || !TARGET_ZARCH) &&
3013 (INTVAL (operands[4]) & 255) == 255"
3014 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3015 [(set_attr "length" "8")
3016 (set_attr "type" "vs")])
3018 (define_insn "*setmem_long_31z"
3019 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3020 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3021 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3023 (use (match_operand:TI 1 "register_operand" "d"))
3024 (clobber (reg:CC CC_REGNUM))]
3025 "!TARGET_64BIT && TARGET_ZARCH"
3026 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3027 [(set_attr "length" "8")
3028 (set_attr "type" "vs")])
3031 ; cmpmemM instruction pattern(s).
3034 (define_expand "cmpmemsi"
3035 [(set (match_operand:SI 0 "register_operand" "")
3036 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3037 (match_operand:BLK 2 "memory_operand" "") ) )
3038 (use (match_operand:SI 3 "general_operand" ""))
3039 (use (match_operand:SI 4 "" ""))]
3042 if (s390_expand_cmpmem (operands[0], operands[1],
3043 operands[2], operands[3]))
3049 ; Compare a block that is up to 256 bytes in length.
3050 ; The block length is taken as (operands[2] % 256) + 1.
3052 (define_expand "cmpmem_short"
3054 [(set (reg:CCU CC_REGNUM)
3055 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3056 (match_operand:BLK 1 "memory_operand" "")))
3057 (use (match_operand 2 "nonmemory_operand" ""))
3058 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3059 (clobber (match_dup 3))])]
3061 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3063 (define_insn "*cmpmem_short"
3064 [(set (reg:CCU CC_REGNUM)
3065 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3066 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3067 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3068 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3069 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3070 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3072 [(set_attr "type" "cs")
3073 (set_attr "cpu_facility" "*,*,z10,*")])
3076 [(set (reg:CCU CC_REGNUM)
3077 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3078 (match_operand:BLK 1 "memory_operand" "")))
3079 (use (match_operand 2 "const_int_operand" ""))
3080 (use (match_operand 3 "immediate_operand" ""))
3081 (clobber (scratch))]
3084 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3085 (use (match_dup 2))])]
3086 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3089 [(set (reg:CCU CC_REGNUM)
3090 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3091 (match_operand:BLK 1 "memory_operand" "")))
3092 (use (match_operand 2 "register_operand" ""))
3093 (use (match_operand 3 "memory_operand" ""))
3094 (clobber (scratch))]
3097 [(unspec [(match_dup 2) (match_dup 3)
3098 (const_int 0)] UNSPEC_EXECUTE)
3099 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3100 (use (const_int 1))])]
3104 [(set (reg:CCU CC_REGNUM)
3105 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3106 (match_operand:BLK 1 "memory_operand" "")))
3107 (use (match_operand 2 "register_operand" ""))
3108 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3109 (clobber (scratch))]
3110 "TARGET_Z10 && reload_completed"
3112 [(unspec [(match_dup 2) (const_int 0)
3113 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3114 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3115 (use (const_int 1))])]
3116 "operands[4] = gen_label_rtx ();")
3119 [(set (reg:CCU CC_REGNUM)
3120 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3121 (match_operand:BLK 1 "memory_operand" "")))
3122 (use (match_operand 2 "register_operand" ""))
3123 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3124 (clobber (match_operand 3 "register_operand" ""))]
3125 "reload_completed && TARGET_CPU_ZARCH"
3126 [(set (match_dup 3) (label_ref (match_dup 4)))
3128 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3129 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3130 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3131 (use (const_int 1))])]
3132 "operands[4] = gen_label_rtx ();")
3134 ; Compare a block of arbitrary length.
3136 (define_expand "cmpmem_long"
3138 [(clobber (match_dup 2))
3139 (clobber (match_dup 3))
3140 (set (reg:CCU CC_REGNUM)
3141 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3142 (match_operand:BLK 1 "memory_operand" "")))
3143 (use (match_operand 2 "general_operand" ""))
3144 (use (match_dup 3))])]
3147 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3148 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3149 rtx reg0 = gen_reg_rtx (dreg_mode);
3150 rtx reg1 = gen_reg_rtx (dreg_mode);
3151 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3152 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3153 rtx len0 = gen_lowpart (Pmode, reg0);
3154 rtx len1 = gen_lowpart (Pmode, reg1);
3156 emit_clobber (reg0);
3157 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3158 emit_move_insn (len0, operands[2]);
3160 emit_clobber (reg1);
3161 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3162 emit_move_insn (len1, operands[2]);
3164 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3165 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3170 (define_insn "*cmpmem_long"
3171 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3172 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3173 (set (reg:CCU CC_REGNUM)
3174 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3175 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3177 (use (match_dup 3))]
3178 "TARGET_64BIT || !TARGET_ZARCH"
3179 "clcle\t%0,%1,0\;jo\t.-4"
3180 [(set_attr "length" "8")
3181 (set_attr "type" "vs")])
3183 (define_insn "*cmpmem_long_31z"
3184 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3185 (clobber (match_operand:TI 1 "register_operand" "=d"))
3186 (set (reg:CCU CC_REGNUM)
3187 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3188 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3190 (use (match_dup 3))]
3191 "!TARGET_64BIT && TARGET_ZARCH"
3192 "clcle\t%0,%1,0\;jo\t.-4"
3193 [(set_attr "op_type" "NN")
3194 (set_attr "type" "vs")
3195 (set_attr "length" "8")])
3197 ; Convert CCUmode condition code to integer.
3198 ; Result is zero if EQ, positive if LTU, negative if GTU.
3200 (define_insn_and_split "cmpint"
3201 [(set (match_operand:SI 0 "register_operand" "=d")
3202 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3204 (clobber (reg:CC CC_REGNUM))]
3208 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3210 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3211 (clobber (reg:CC CC_REGNUM))])])
3213 (define_insn_and_split "*cmpint_cc"
3214 [(set (reg CC_REGNUM)
3215 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3218 (set (match_operand:SI 0 "register_operand" "=d")
3219 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3220 "s390_match_ccmode (insn, CCSmode)"
3222 "&& reload_completed"
3223 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3225 [(set (match_dup 2) (match_dup 3))
3226 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3228 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3229 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3230 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3233 (define_insn_and_split "*cmpint_sign"
3234 [(set (match_operand:DI 0 "register_operand" "=d")
3235 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3236 UNSPEC_CCU_TO_INT)))
3237 (clobber (reg:CC CC_REGNUM))]
3240 "&& reload_completed"
3241 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3243 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3244 (clobber (reg:CC CC_REGNUM))])])
3246 (define_insn_and_split "*cmpint_sign_cc"
3247 [(set (reg CC_REGNUM)
3248 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3249 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3250 UNSPEC_CCU_TO_INT) 0)
3251 (const_int 32)) (const_int 32))
3253 (set (match_operand:DI 0 "register_operand" "=d")
3254 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3255 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3257 "&& reload_completed"
3258 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3260 [(set (match_dup 2) (match_dup 3))
3261 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3263 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3264 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3265 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3270 ;;- Conversion instructions.
3273 (define_insn "*sethighpartsi"
3274 [(set (match_operand:SI 0 "register_operand" "=d,d")
3275 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3276 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3277 (clobber (reg:CC CC_REGNUM))]
3282 [(set_attr "op_type" "RS,RSY")
3283 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3285 (define_insn "*sethighpartdi_64"
3286 [(set (match_operand:DI 0 "register_operand" "=d")
3287 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3288 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3289 (clobber (reg:CC CC_REGNUM))]
3292 [(set_attr "op_type" "RSY")
3293 (set_attr "z10prop" "z10_super")])
3295 (define_insn "*sethighpartdi_31"
3296 [(set (match_operand:DI 0 "register_operand" "=d,d")
3297 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3298 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3299 (clobber (reg:CC CC_REGNUM))]
3304 [(set_attr "op_type" "RS,RSY")
3305 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3308 (define_insn_and_split "*extzv<mode>"
3309 [(set (match_operand:GPR 0 "register_operand" "=d")
3310 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3311 (match_operand 2 "const_int_operand" "n")
3313 (clobber (reg:CC CC_REGNUM))]
3314 "INTVAL (operands[2]) > 0
3315 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3317 "&& reload_completed"
3319 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3320 (clobber (reg:CC CC_REGNUM))])
3321 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3323 int bitsize = INTVAL (operands[2]);
3324 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3325 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3327 operands[1] = adjust_address (operands[1], BLKmode, 0);
3328 set_mem_size (operands[1], size);
3329 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3330 operands[3] = GEN_INT (mask);
3333 (define_insn_and_split "*extv<mode>"
3334 [(set (match_operand:GPR 0 "register_operand" "=d")
3335 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3336 (match_operand 2 "const_int_operand" "n")
3338 (clobber (reg:CC CC_REGNUM))]
3339 "INTVAL (operands[2]) > 0
3340 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3342 "&& reload_completed"
3344 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3345 (clobber (reg:CC CC_REGNUM))])
3347 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3348 (clobber (reg:CC CC_REGNUM))])]
3350 int bitsize = INTVAL (operands[2]);
3351 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3352 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3354 operands[1] = adjust_address (operands[1], BLKmode, 0);
3355 set_mem_size (operands[1], size);
3356 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3357 operands[3] = GEN_INT (mask);
3361 ; insv instruction patterns
3364 (define_expand "insv"
3365 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3366 (match_operand 1 "const_int_operand" "")
3367 (match_operand 2 "const_int_operand" ""))
3368 (match_operand 3 "general_operand" ""))]
3371 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3376 (define_insn "*insv<mode>_zEC12"
3377 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3378 (match_operand 1 "const_int_operand" "I")
3379 (match_operand 2 "const_int_operand" "I"))
3380 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3382 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3383 GET_MODE_BITSIZE (<MODE>mode)"
3385 int start = INTVAL (operands[2]);
3386 int size = INTVAL (operands[1]);
3387 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3389 operands[2] = GEN_INT (offset + start); /* start bit position */
3390 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3391 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3392 start - size); /* left shift count */
3394 return "risbgn\t%0,%3,%b2,%b1,%b4";
3396 [(set_attr "op_type" "RIE")])
3398 (define_insn "*insv<mode>_z10"
3399 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3400 (match_operand 1 "const_int_operand" "I")
3401 (match_operand 2 "const_int_operand" "I"))
3402 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3403 (clobber (reg:CC CC_REGNUM))]
3405 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3406 GET_MODE_BITSIZE (<MODE>mode)"
3408 int start = INTVAL (operands[2]);
3409 int size = INTVAL (operands[1]);
3410 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3412 operands[2] = GEN_INT (offset + start); /* start bit position */
3413 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3414 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3415 start - size); /* left shift count */
3417 return "risbg\t%0,%3,%b2,%b1,%b4";
3419 [(set_attr "op_type" "RIE")
3420 (set_attr "z10prop" "z10_super_E1")])
3422 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3423 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3424 (define_insn "*insv<mode>_zEC12_noshift"
3425 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3426 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3427 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3428 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3429 (match_operand:GPR 4 "const_int_operand" ""))))]
3430 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3431 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3432 [(set_attr "op_type" "RIE")])
3434 (define_insn "*insv<mode>_z10_noshift"
3435 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3436 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3437 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3438 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3439 (match_operand:GPR 4 "const_int_operand" ""))))
3440 (clobber (reg:CC CC_REGNUM))]
3441 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3442 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3443 [(set_attr "op_type" "RIE")
3444 (set_attr "z10prop" "z10_super_E1")])
3446 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3447 (define_insn "*insv<mode>_or_z10_noshift"
3448 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3449 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3450 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3451 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3452 (clobber (reg:CC CC_REGNUM))]
3454 "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3455 [(set_attr "op_type" "RIE")])
3457 (define_insn "*insv<mode>_mem_reg"
3458 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3459 (match_operand 1 "const_int_operand" "n,n")
3461 (match_operand:W 2 "register_operand" "d,d"))]
3462 "INTVAL (operands[1]) > 0
3463 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3464 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3466 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3468 operands[1] = GEN_INT ((1ul << size) - 1);
3469 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3470 : "stcmy\t%2,%1,%S0";
3472 [(set_attr "op_type" "RS,RSY")
3473 (set_attr "z10prop" "z10_super,z10_super")])
3475 (define_insn "*insvdi_mem_reghigh"
3476 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3477 (match_operand 1 "const_int_operand" "n")
3479 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3482 && INTVAL (operands[1]) > 0
3483 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3484 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3486 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3488 operands[1] = GEN_INT ((1ul << size) - 1);
3489 return "stcmh\t%2,%1,%S0";
3491 [(set_attr "op_type" "RSY")
3492 (set_attr "z10prop" "z10_super")])
3494 (define_insn "*insvdi_reg_imm"
3495 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3497 (match_operand 1 "const_int_operand" "n"))
3498 (match_operand:DI 2 "const_int_operand" "n"))]
3500 && INTVAL (operands[1]) >= 0
3501 && INTVAL (operands[1]) < BITS_PER_WORD
3502 && INTVAL (operands[1]) % 16 == 0"
3504 switch (BITS_PER_WORD - INTVAL (operands[1]))
3506 case 64: return "iihh\t%0,%x2"; break;
3507 case 48: return "iihl\t%0,%x2"; break;
3508 case 32: return "iilh\t%0,%x2"; break;
3509 case 16: return "iill\t%0,%x2"; break;
3510 default: gcc_unreachable();
3513 [(set_attr "op_type" "RI")
3514 (set_attr "z10prop" "z10_super_E1")])
3516 ; Update the left-most 32 bit of a DI.
3517 (define_insn "*insv_h_di_reg_extimm"
3518 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3521 (match_operand:DI 1 "const_int_operand" "n"))]
3524 [(set_attr "op_type" "RIL")
3525 (set_attr "z10prop" "z10_fwd_E1")])
3527 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3528 (define_insn "*insv_l<mode>_reg_extimm"
3529 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3531 (match_operand 1 "const_int_operand" "n"))
3532 (match_operand:P 2 "const_int_operand" "n"))]
3534 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3536 [(set_attr "op_type" "RIL")
3537 (set_attr "z10prop" "z10_fwd_A1")])
3540 ; extendsidi2 instruction pattern(s).
3543 (define_expand "extendsidi2"
3544 [(set (match_operand:DI 0 "register_operand" "")
3545 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3550 emit_clobber (operands[0]);
3551 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3552 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3553 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3558 (define_insn "*extendsidi2"
3559 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3560 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3566 [(set_attr "op_type" "RRE,RXY,RIL")
3567 (set_attr "type" "*,*,larl")
3568 (set_attr "cpu_facility" "*,*,z10")
3569 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3572 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3575 (define_expand "extend<HQI:mode><DSI:mode>2"
3576 [(set (match_operand:DSI 0 "register_operand" "")
3577 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3580 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3582 rtx tmp = gen_reg_rtx (SImode);
3583 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3584 emit_insn (gen_extendsidi2 (operands[0], tmp));
3587 else if (!TARGET_EXTIMM)
3589 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3590 GET_MODE_BITSIZE (<HQI:MODE>mode));
3592 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3593 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3594 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3600 ; extendhidi2 instruction pattern(s).
3603 (define_insn "*extendhidi2_extimm"
3604 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3605 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3606 "TARGET_ZARCH && TARGET_EXTIMM"
3611 [(set_attr "op_type" "RRE,RXY,RIL")
3612 (set_attr "type" "*,*,larl")
3613 (set_attr "cpu_facility" "extimm,extimm,z10")
3614 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3616 (define_insn "*extendhidi2"
3617 [(set (match_operand:DI 0 "register_operand" "=d")
3618 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3621 [(set_attr "op_type" "RXY")
3622 (set_attr "z10prop" "z10_super_E1")])
3625 ; extendhisi2 instruction pattern(s).
3628 (define_insn "*extendhisi2_extimm"
3629 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3630 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3637 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3638 (set_attr "type" "*,*,*,larl")
3639 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3640 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3642 (define_insn "*extendhisi2"
3643 [(set (match_operand:SI 0 "register_operand" "=d,d")
3644 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3649 [(set_attr "op_type" "RX,RXY")
3650 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3653 ; extendqi(si|di)2 instruction pattern(s).
3656 ; lbr, lgbr, lb, lgb
3657 (define_insn "*extendqi<mode>2_extimm"
3658 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3659 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3664 [(set_attr "op_type" "RRE,RXY")
3665 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3668 (define_insn "*extendqi<mode>2"
3669 [(set (match_operand:GPR 0 "register_operand" "=d")
3670 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3671 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3673 [(set_attr "op_type" "RXY")
3674 (set_attr "z10prop" "z10_super_E1")])
3676 (define_insn_and_split "*extendqi<mode>2_short_displ"
3677 [(set (match_operand:GPR 0 "register_operand" "=d")
3678 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3679 (clobber (reg:CC CC_REGNUM))]
3680 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3682 "&& reload_completed"
3684 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3685 (clobber (reg:CC CC_REGNUM))])
3687 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3688 (clobber (reg:CC CC_REGNUM))])]
3690 operands[1] = adjust_address (operands[1], BLKmode, 0);
3691 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3692 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3693 - GET_MODE_BITSIZE (QImode));
3697 ; zero_extendsidi2 instruction pattern(s).
3700 (define_expand "zero_extendsidi2"
3701 [(set (match_operand:DI 0 "register_operand" "")
3702 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3707 emit_clobber (operands[0]);
3708 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3709 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3714 (define_insn "*zero_extendsidi2"
3715 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3716 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3722 [(set_attr "op_type" "RRE,RXY,RIL")
3723 (set_attr "type" "*,*,larl")
3724 (set_attr "cpu_facility" "*,*,z10")
3725 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3728 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3731 (define_insn "*llgt_sidi"
3732 [(set (match_operand:DI 0 "register_operand" "=d")
3733 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3734 (const_int 2147483647)))]
3737 [(set_attr "op_type" "RXE")
3738 (set_attr "z10prop" "z10_super_E1")])
3740 (define_insn_and_split "*llgt_sidi_split"
3741 [(set (match_operand:DI 0 "register_operand" "=d")
3742 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3743 (const_int 2147483647)))
3744 (clobber (reg:CC CC_REGNUM))]
3747 "&& reload_completed"
3749 (and:DI (subreg:DI (match_dup 1) 0)
3750 (const_int 2147483647)))]
3753 (define_insn "*llgt_sisi"
3754 [(set (match_operand:SI 0 "register_operand" "=d,d")
3755 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3756 (const_int 2147483647)))]
3761 [(set_attr "op_type" "RRE,RXE")
3762 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3764 (define_insn "*llgt_didi"
3765 [(set (match_operand:DI 0 "register_operand" "=d,d")
3766 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3767 (const_int 2147483647)))]
3772 [(set_attr "op_type" "RRE,RXE")
3773 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3776 [(set (match_operand:DSI 0 "register_operand" "")
3777 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3778 (const_int 2147483647)))
3779 (clobber (reg:CC CC_REGNUM))]
3780 "TARGET_ZARCH && reload_completed"
3782 (and:DSI (match_dup 1)
3783 (const_int 2147483647)))]
3787 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3790 (define_expand "zero_extend<mode>di2"
3791 [(set (match_operand:DI 0 "register_operand" "")
3792 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3797 rtx tmp = gen_reg_rtx (SImode);
3798 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3799 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3802 else if (!TARGET_EXTIMM)
3804 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3805 GET_MODE_BITSIZE(<MODE>mode));
3806 operands[1] = gen_lowpart (DImode, operands[1]);
3807 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3808 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3813 (define_expand "zero_extend<mode>si2"
3814 [(set (match_operand:SI 0 "register_operand" "")
3815 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3820 operands[1] = gen_lowpart (SImode, operands[1]);
3821 emit_insn (gen_andsi3 (operands[0], operands[1],
3822 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3828 (define_insn "*zero_extendhi<mode>2_z10"
3829 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3830 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3836 [(set_attr "op_type" "RXY,RRE,RIL")
3837 (set_attr "type" "*,*,larl")
3838 (set_attr "cpu_facility" "*,*,z10")
3839 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3841 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3842 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3843 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3844 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3849 [(set_attr "op_type" "RRE,RXY")
3850 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3853 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3854 [(set (match_operand:GPR 0 "register_operand" "=d")
3855 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3856 "TARGET_ZARCH && !TARGET_EXTIMM"
3858 [(set_attr "op_type" "RXY")
3859 (set_attr "z10prop" "z10_fwd_A3")])
3861 (define_insn_and_split "*zero_extendhisi2_31"
3862 [(set (match_operand:SI 0 "register_operand" "=&d")
3863 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3864 (clobber (reg:CC CC_REGNUM))]
3867 "&& reload_completed"
3868 [(set (match_dup 0) (const_int 0))
3870 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3871 (clobber (reg:CC CC_REGNUM))])]
3872 "operands[2] = gen_lowpart (HImode, operands[0]);")
3874 (define_insn_and_split "*zero_extendqisi2_31"
3875 [(set (match_operand:SI 0 "register_operand" "=&d")
3876 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3879 "&& reload_completed"
3880 [(set (match_dup 0) (const_int 0))
3881 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3882 "operands[2] = gen_lowpart (QImode, operands[0]);")
3885 ; zero_extendqihi2 instruction pattern(s).
3888 (define_expand "zero_extendqihi2"
3889 [(set (match_operand:HI 0 "register_operand" "")
3890 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3891 "TARGET_ZARCH && !TARGET_EXTIMM"
3893 operands[1] = gen_lowpart (HImode, operands[1]);
3894 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3898 (define_insn "*zero_extendqihi2_64"
3899 [(set (match_operand:HI 0 "register_operand" "=d")
3900 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3901 "TARGET_ZARCH && !TARGET_EXTIMM"
3903 [(set_attr "op_type" "RXY")
3904 (set_attr "z10prop" "z10_fwd_A3")])
3906 (define_insn_and_split "*zero_extendqihi2_31"
3907 [(set (match_operand:HI 0 "register_operand" "=&d")
3908 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3911 "&& reload_completed"
3912 [(set (match_dup 0) (const_int 0))
3913 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3914 "operands[2] = gen_lowpart (QImode, operands[0]);")
3917 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3920 (define_expand "fixuns_truncdddi2"
3922 [(set (match_operand:DI 0 "register_operand" "")
3923 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3924 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3925 (clobber (reg:CC CC_REGNUM))])]
3931 rtx label1 = gen_label_rtx ();
3932 rtx label2 = gen_label_rtx ();
3933 rtx temp = gen_reg_rtx (TDmode);
3934 REAL_VALUE_TYPE cmp, sub;
3936 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3937 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3939 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3940 solution is doing the check and the subtraction in TD mode and using a
3941 TD -> DI convert afterwards. */
3942 emit_insn (gen_extendddtd2 (temp, operands[1]));
3943 temp = force_reg (TDmode, temp);
3944 emit_cmp_and_jump_insns (temp,
3945 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3946 LT, NULL_RTX, VOIDmode, 0, label1);
3947 emit_insn (gen_subtd3 (temp, temp,
3948 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3949 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3952 emit_label (label1);
3953 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3954 emit_label (label2);
3959 (define_expand "fixuns_trunctddi2"
3961 [(set (match_operand:DI 0 "register_operand" "")
3962 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
3963 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3964 (clobber (reg:CC CC_REGNUM))])]
3970 rtx label1 = gen_label_rtx ();
3971 rtx label2 = gen_label_rtx ();
3972 rtx temp = gen_reg_rtx (TDmode);
3973 REAL_VALUE_TYPE cmp, sub;
3975 operands[1] = force_reg (TDmode, operands[1]);
3976 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3977 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3979 emit_cmp_and_jump_insns (operands[1],
3980 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3981 LT, NULL_RTX, VOIDmode, 0, label1);
3982 emit_insn (gen_subtd3 (temp, operands[1],
3983 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3984 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3987 emit_label (label1);
3988 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3989 emit_label (label2);
3995 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
3996 ; instruction pattern(s).
3999 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4001 [(set (match_operand:GPR 0 "register_operand" "")
4002 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4003 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4004 (clobber (reg:CC CC_REGNUM))])]
4009 rtx label1 = gen_label_rtx ();
4010 rtx label2 = gen_label_rtx ();
4011 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4012 REAL_VALUE_TYPE cmp, sub;
4014 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4015 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
4016 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
4018 emit_cmp_and_jump_insns (operands[1],
4019 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4020 LT, NULL_RTX, VOIDmode, 0, label1);
4021 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4022 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4023 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4027 emit_label (label1);
4028 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4029 operands[1], GEN_INT (5)));
4030 emit_label (label2);
4035 ; fixuns_trunc(td|dd)si2 expander
4036 (define_expand "fixuns_trunc<mode>si2"
4038 [(set (match_operand:SI 0 "register_operand" "")
4039 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4040 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4041 (clobber (reg:CC CC_REGNUM))])]
4042 "TARGET_Z196 && TARGET_HARD_DFP"
4045 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4047 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4048 ; clfdtr, clfxtr, clgdtr, clgxtr
4049 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4050 [(set (match_operand:GPR 0 "register_operand" "=r")
4051 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4052 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4053 (clobber (reg:CC CC_REGNUM))]
4055 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4056 [(set_attr "op_type" "RRF")
4057 (set_attr "type" "ftoi")])
4059 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4060 [(set (match_operand:GPR 0 "register_operand" "")
4061 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4064 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4069 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4070 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4071 [(set (match_operand:GPR 0 "register_operand" "=d")
4072 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4073 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4074 (clobber (reg:CC CC_REGNUM))]
4076 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4077 [(set_attr "op_type" "RRE")
4078 (set_attr "type" "ftoi")])
4082 ; fix_trunc(td|dd)di2 instruction pattern(s).
4085 (define_expand "fix_trunc<mode>di2"
4086 [(set (match_operand:DI 0 "register_operand" "")
4087 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4088 "TARGET_ZARCH && TARGET_HARD_DFP"
4090 operands[1] = force_reg (<MODE>mode, operands[1]);
4091 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4097 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4098 [(set (match_operand:DI 0 "register_operand" "=d")
4099 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4100 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4101 (clobber (reg:CC CC_REGNUM))]
4102 "TARGET_ZARCH && TARGET_HARD_DFP"
4103 "cg<DFP:xde>tr\t%0,%h2,%1"
4104 [(set_attr "op_type" "RRF")
4105 (set_attr "type" "ftoidfp")])
4109 ; fix_trunctf(si|di)2 instruction pattern(s).
4112 (define_expand "fix_trunctf<mode>2"
4113 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4114 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4115 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4116 (clobber (reg:CC CC_REGNUM))])]
4122 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4125 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4126 (define_insn "floatdi<mode>2"
4127 [(set (match_operand:FP 0 "register_operand" "=f")
4128 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4129 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4130 "c<xde>g<bt>r\t%0,%1"
4131 [(set_attr "op_type" "RRE")
4132 (set_attr "type" "itof<mode>" )])
4134 ; cxfbr, cdfbr, cefbr
4135 (define_insn "floatsi<mode>2"
4136 [(set (match_operand:BFP 0 "register_operand" "=f")
4137 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4140 [(set_attr "op_type" "RRE")
4141 (set_attr "type" "itof<mode>" )])
4144 (define_insn "floatsi<mode>2"
4145 [(set (match_operand:DFP 0 "register_operand" "=f")
4146 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4147 "TARGET_Z196 && TARGET_HARD_FLOAT"
4148 "c<xde>ftr\t%0,0,%1,0"
4149 [(set_attr "op_type" "RRE")
4150 (set_attr "type" "itof<mode>" )])
4153 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4156 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4157 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4158 (define_insn "floatuns<GPR:mode><FP:mode>2"
4159 [(set (match_operand:FP 0 "register_operand" "=f")
4160 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4161 "TARGET_Z196 && TARGET_HARD_FLOAT"
4162 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4163 [(set_attr "op_type" "RRE")
4164 (set_attr "type" "itof<FP:mode>" )])
4167 ; truncdfsf2 instruction pattern(s).
4170 (define_insn "truncdfsf2"
4171 [(set (match_operand:SF 0 "register_operand" "=f")
4172 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4175 [(set_attr "op_type" "RRE")
4176 (set_attr "type" "ftruncdf")])
4179 ; trunctf(df|sf)2 instruction pattern(s).
4183 (define_insn "trunctf<mode>2"
4184 [(set (match_operand:DSF 0 "register_operand" "=f")
4185 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4186 (clobber (match_scratch:TF 2 "=f"))]
4188 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4189 [(set_attr "length" "6")
4190 (set_attr "type" "ftrunctf")])
4193 ; trunctddd2 and truncddsd2 instruction pattern(s).
4196 (define_insn "trunctddd2"
4197 [(set (match_operand:DD 0 "register_operand" "=f")
4198 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4199 (clobber (match_scratch:TD 2 "=f"))]
4201 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4202 [(set_attr "length" "6")
4203 (set_attr "type" "ftruncdd")])
4205 (define_insn "truncddsd2"
4206 [(set (match_operand:SD 0 "register_operand" "=f")
4207 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4210 [(set_attr "op_type" "RRF")
4211 (set_attr "type" "ftruncsd")])
4214 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4217 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4218 (define_insn "extend<DSF:mode><BFP:mode>2"
4219 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4220 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4222 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4224 l<BFP:xde><DSF:xde>br\t%0,%1
4225 l<BFP:xde><DSF:xde>b\t%0,%1"
4226 [(set_attr "op_type" "RRE,RXE")
4227 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4230 ; extendddtd2 and extendsddd2 instruction pattern(s).
4233 (define_insn "extendddtd2"
4234 [(set (match_operand:TD 0 "register_operand" "=f")
4235 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4238 [(set_attr "op_type" "RRF")
4239 (set_attr "type" "fsimptf")])
4241 (define_insn "extendsddd2"
4242 [(set (match_operand:DD 0 "register_operand" "=f")
4243 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4246 [(set_attr "op_type" "RRF")
4247 (set_attr "type" "fsimptf")])
4249 ; Binary <-> Decimal floating point trunc patterns
4252 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4253 [(set (reg:DFP_ALL FPR0_REGNUM)
4254 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4255 (use (reg:SI GPR0_REGNUM))
4256 (clobber (reg:CC CC_REGNUM))]
4260 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4261 [(set (reg:BFP FPR0_REGNUM)
4262 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4263 (use (reg:SI GPR0_REGNUM))
4264 (clobber (reg:CC CC_REGNUM))]
4268 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4269 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4270 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4272 [(set (reg:DFP_ALL FPR0_REGNUM)
4273 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4274 (use (reg:SI GPR0_REGNUM))
4275 (clobber (reg:CC CC_REGNUM))])
4276 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4277 (reg:DFP_ALL FPR0_REGNUM))]
4279 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4281 HOST_WIDE_INT flags;
4283 flags = (PFPO_CONVERT |
4284 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4285 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4287 operands[2] = GEN_INT (flags);
4290 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4291 [(set (reg:DFP_ALL FPR2_REGNUM)
4292 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4293 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4295 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4296 (use (reg:SI GPR0_REGNUM))
4297 (clobber (reg:CC CC_REGNUM))])
4298 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4300 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4302 HOST_WIDE_INT flags;
4304 flags = (PFPO_CONVERT |
4305 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4306 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4308 operands[2] = GEN_INT (flags);
4312 ; Binary <-> Decimal floating point extend patterns
4315 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4316 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4317 (use (reg:SI GPR0_REGNUM))
4318 (clobber (reg:CC CC_REGNUM))]
4322 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4323 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4324 (use (reg:SI GPR0_REGNUM))
4325 (clobber (reg:CC CC_REGNUM))]
4329 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4330 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4331 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4333 [(set (reg:DFP_ALL FPR0_REGNUM)
4334 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4335 (use (reg:SI GPR0_REGNUM))
4336 (clobber (reg:CC CC_REGNUM))])
4337 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4338 (reg:DFP_ALL FPR0_REGNUM))]
4340 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4342 HOST_WIDE_INT flags;
4344 flags = (PFPO_CONVERT |
4345 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4346 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4348 operands[2] = GEN_INT (flags);
4351 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4352 [(set (reg:DFP_ALL FPR2_REGNUM)
4353 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4354 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4356 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4357 (use (reg:SI GPR0_REGNUM))
4358 (clobber (reg:CC CC_REGNUM))])
4359 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4361 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4363 HOST_WIDE_INT flags;
4365 flags = (PFPO_CONVERT |
4366 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4367 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4369 operands[2] = GEN_INT (flags);
4374 ;; ARITHMETIC OPERATIONS
4376 ; arithmetic operations set the ConditionCode,
4377 ; because of unpredictable Bits in Register for Halfword and Byte
4378 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4381 ;;- Add instructions.
4385 ; addti3 instruction pattern(s).
4388 (define_insn_and_split "addti3"
4389 [(set (match_operand:TI 0 "register_operand" "=&d")
4390 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4391 (match_operand:TI 2 "general_operand" "do") ) )
4392 (clobber (reg:CC CC_REGNUM))]
4395 "&& reload_completed"
4397 [(set (reg:CCL1 CC_REGNUM)
4398 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4400 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4402 [(set (match_dup 3) (plus:DI
4403 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4404 (match_dup 4)) (match_dup 5)))
4405 (clobber (reg:CC CC_REGNUM))])]
4406 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4407 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4408 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4409 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4410 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4411 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4414 ; adddi3 instruction pattern(s).
4417 (define_expand "adddi3"
4419 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4420 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4421 (match_operand:DI 2 "general_operand" "")))
4422 (clobber (reg:CC CC_REGNUM))])]
4426 (define_insn "*adddi3_sign"
4427 [(set (match_operand:DI 0 "register_operand" "=d,d")
4428 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4429 (match_operand:DI 1 "register_operand" "0,0")))
4430 (clobber (reg:CC CC_REGNUM))]
4435 [(set_attr "op_type" "RRE,RXY")
4436 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4438 (define_insn "*adddi3_zero_cc"
4439 [(set (reg CC_REGNUM)
4440 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4441 (match_operand:DI 1 "register_operand" "0,0"))
4443 (set (match_operand:DI 0 "register_operand" "=d,d")
4444 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4445 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4449 [(set_attr "op_type" "RRE,RXY")
4450 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4452 (define_insn "*adddi3_zero_cconly"
4453 [(set (reg CC_REGNUM)
4454 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4455 (match_operand:DI 1 "register_operand" "0,0"))
4457 (clobber (match_scratch:DI 0 "=d,d"))]
4458 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4462 [(set_attr "op_type" "RRE,RXY")
4463 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4465 (define_insn "*adddi3_zero"
4466 [(set (match_operand:DI 0 "register_operand" "=d,d")
4467 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4468 (match_operand:DI 1 "register_operand" "0,0")))
4469 (clobber (reg:CC CC_REGNUM))]
4474 [(set_attr "op_type" "RRE,RXY")
4475 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4477 (define_insn_and_split "*adddi3_31z"
4478 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4479 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4480 (match_operand:DI 2 "general_operand" "do") ) )
4481 (clobber (reg:CC CC_REGNUM))]
4482 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4484 "&& reload_completed"
4486 [(set (reg:CCL1 CC_REGNUM)
4487 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4489 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4491 [(set (match_dup 3) (plus:SI
4492 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4493 (match_dup 4)) (match_dup 5)))
4494 (clobber (reg:CC CC_REGNUM))])]
4495 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4496 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4497 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4498 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4499 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4500 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4502 (define_insn_and_split "*adddi3_31"
4503 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4504 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4505 (match_operand:DI 2 "general_operand" "do") ) )
4506 (clobber (reg:CC CC_REGNUM))]
4509 "&& reload_completed"
4511 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4512 (clobber (reg:CC CC_REGNUM))])
4514 [(set (reg:CCL1 CC_REGNUM)
4515 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4517 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4519 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4521 (label_ref (match_dup 9))))
4523 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4524 (clobber (reg:CC CC_REGNUM))])
4526 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4527 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4528 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4529 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4530 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4531 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4532 operands[9] = gen_label_rtx ();")
4535 ; addsi3 instruction pattern(s).
4538 (define_expand "addsi3"
4540 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4541 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4542 (match_operand:SI 2 "general_operand" "")))
4543 (clobber (reg:CC CC_REGNUM))])]
4547 (define_insn "*addsi3_sign"
4548 [(set (match_operand:SI 0 "register_operand" "=d,d")
4549 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4550 (match_operand:SI 1 "register_operand" "0,0")))
4551 (clobber (reg:CC CC_REGNUM))]
4556 [(set_attr "op_type" "RX,RXY")
4557 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4560 ; add(di|si)3 instruction pattern(s).
4563 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4564 (define_insn "*add<mode>3"
4565 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4566 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4567 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4568 (clobber (reg:CC CC_REGNUM))]
4580 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4581 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4582 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4583 z10_super_E1,z10_super_E1,z10_super_E1")])
4585 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4586 (define_insn "*add<mode>3_carry1_cc"
4587 [(set (reg CC_REGNUM)
4588 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4589 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4591 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4592 (plus:GPR (match_dup 1) (match_dup 2)))]
4593 "s390_match_ccmode (insn, CCL1mode)"
4599 al<g>hsik\t%0,%1,%h2
4603 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4604 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4605 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4606 z10_super_E1,z10_super_E1,z10_super_E1")])
4608 ; alr, al, aly, algr, alg, alrk, algrk
4609 (define_insn "*add<mode>3_carry1_cconly"
4610 [(set (reg CC_REGNUM)
4611 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4612 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4614 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4615 "s390_match_ccmode (insn, CCL1mode)"
4621 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4622 (set_attr "cpu_facility" "*,z196,*,*")
4623 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4625 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4626 (define_insn "*add<mode>3_carry2_cc"
4627 [(set (reg CC_REGNUM)
4628 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4629 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4631 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4632 (plus:GPR (match_dup 1) (match_dup 2)))]
4633 "s390_match_ccmode (insn, CCL1mode)"
4639 al<g>hsik\t%0,%1,%h2
4643 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4644 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4645 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4646 z10_super_E1,z10_super_E1,z10_super_E1")])
4648 ; alr, al, aly, algr, alg, alrk, algrk
4649 (define_insn "*add<mode>3_carry2_cconly"
4650 [(set (reg CC_REGNUM)
4651 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4652 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4654 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4655 "s390_match_ccmode (insn, CCL1mode)"
4661 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4662 (set_attr "cpu_facility" "*,z196,*,*")
4663 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4665 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4666 (define_insn "*add<mode>3_cc"
4667 [(set (reg CC_REGNUM)
4668 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4669 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4671 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4672 (plus:GPR (match_dup 1) (match_dup 2)))]
4673 "s390_match_ccmode (insn, CCLmode)"
4679 al<g>hsik\t%0,%1,%h2
4683 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4684 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4685 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4686 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4688 ; alr, al, aly, algr, alg, alrk, algrk
4689 (define_insn "*add<mode>3_cconly"
4690 [(set (reg CC_REGNUM)
4691 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4692 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4694 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4695 "s390_match_ccmode (insn, CCLmode)"
4701 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4702 (set_attr "cpu_facility" "*,z196,*,*")
4703 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4705 ; alr, al, aly, algr, alg, alrk, algrk
4706 (define_insn "*add<mode>3_cconly2"
4707 [(set (reg CC_REGNUM)
4708 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4709 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4710 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4711 "s390_match_ccmode(insn, CCLmode)"
4717 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4718 (set_attr "cpu_facility" "*,z196,*,*")
4719 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4721 ; ahi, afi, aghi, agfi, asi, agsi
4722 (define_insn "*add<mode>3_imm_cc"
4723 [(set (reg CC_REGNUM)
4724 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4725 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4727 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4728 (plus:GPR (match_dup 1) (match_dup 2)))]
4729 "s390_match_ccmode (insn, CCAmode)
4730 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4731 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4732 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4733 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4739 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4740 (set_attr "cpu_facility" "*,z196,extimm,z10")
4741 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4744 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4747 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4748 (define_insn "add<mode>3"
4749 [(set (match_operand:FP 0 "register_operand" "=f, f")
4750 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4751 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4752 (clobber (reg:CC CC_REGNUM))]
4755 a<xde><bt>r\t%0,<op1>%2
4757 [(set_attr "op_type" "<RRer>,RXE")
4758 (set_attr "type" "fsimp<mode>")])
4760 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4761 (define_insn "*add<mode>3_cc"
4762 [(set (reg CC_REGNUM)
4763 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4764 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4765 (match_operand:FP 3 "const0_operand" "")))
4766 (set (match_operand:FP 0 "register_operand" "=f,f")
4767 (plus:FP (match_dup 1) (match_dup 2)))]
4768 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4770 a<xde><bt>r\t%0,<op1>%2
4772 [(set_attr "op_type" "<RRer>,RXE")
4773 (set_attr "type" "fsimp<mode>")])
4775 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4776 (define_insn "*add<mode>3_cconly"
4777 [(set (reg CC_REGNUM)
4778 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4779 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4780 (match_operand:FP 3 "const0_operand" "")))
4781 (clobber (match_scratch:FP 0 "=f,f"))]
4782 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4784 a<xde><bt>r\t%0,<op1>%2
4786 [(set_attr "op_type" "<RRer>,RXE")
4787 (set_attr "type" "fsimp<mode>")])
4791 ;;- Subtract instructions.
4795 ; subti3 instruction pattern(s).
4798 (define_insn_and_split "subti3"
4799 [(set (match_operand:TI 0 "register_operand" "=&d")
4800 (minus:TI (match_operand:TI 1 "register_operand" "0")
4801 (match_operand:TI 2 "general_operand" "do") ) )
4802 (clobber (reg:CC CC_REGNUM))]
4805 "&& reload_completed"
4807 [(set (reg:CCL2 CC_REGNUM)
4808 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4810 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4812 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4813 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4814 (clobber (reg:CC CC_REGNUM))])]
4815 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4816 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4817 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4818 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4819 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4820 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4823 ; subdi3 instruction pattern(s).
4826 (define_expand "subdi3"
4828 [(set (match_operand:DI 0 "register_operand" "")
4829 (minus:DI (match_operand:DI 1 "register_operand" "")
4830 (match_operand:DI 2 "general_operand" "")))
4831 (clobber (reg:CC CC_REGNUM))])]
4835 (define_insn "*subdi3_sign"
4836 [(set (match_operand:DI 0 "register_operand" "=d,d")
4837 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4838 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4839 (clobber (reg:CC CC_REGNUM))]
4844 [(set_attr "op_type" "RRE,RXY")
4845 (set_attr "z10prop" "z10_c,*")
4846 (set_attr "z196prop" "z196_cracked")])
4848 (define_insn "*subdi3_zero_cc"
4849 [(set (reg CC_REGNUM)
4850 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4851 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4853 (set (match_operand:DI 0 "register_operand" "=d,d")
4854 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4855 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4859 [(set_attr "op_type" "RRE,RXY")
4860 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4862 (define_insn "*subdi3_zero_cconly"
4863 [(set (reg CC_REGNUM)
4864 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4865 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4867 (clobber (match_scratch:DI 0 "=d,d"))]
4868 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4872 [(set_attr "op_type" "RRE,RXY")
4873 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4875 (define_insn "*subdi3_zero"
4876 [(set (match_operand:DI 0 "register_operand" "=d,d")
4877 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4878 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4879 (clobber (reg:CC CC_REGNUM))]
4884 [(set_attr "op_type" "RRE,RXY")
4885 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4887 (define_insn_and_split "*subdi3_31z"
4888 [(set (match_operand:DI 0 "register_operand" "=&d")
4889 (minus:DI (match_operand:DI 1 "register_operand" "0")
4890 (match_operand:DI 2 "general_operand" "do") ) )
4891 (clobber (reg:CC CC_REGNUM))]
4892 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4894 "&& reload_completed"
4896 [(set (reg:CCL2 CC_REGNUM)
4897 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4899 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4901 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4902 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4903 (clobber (reg:CC CC_REGNUM))])]
4904 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4905 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4906 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4907 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4908 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4909 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4911 (define_insn_and_split "*subdi3_31"
4912 [(set (match_operand:DI 0 "register_operand" "=&d")
4913 (minus:DI (match_operand:DI 1 "register_operand" "0")
4914 (match_operand:DI 2 "general_operand" "do") ) )
4915 (clobber (reg:CC CC_REGNUM))]
4918 "&& reload_completed"
4920 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4921 (clobber (reg:CC CC_REGNUM))])
4923 [(set (reg:CCL2 CC_REGNUM)
4924 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4926 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4928 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4930 (label_ref (match_dup 9))))
4932 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4933 (clobber (reg:CC CC_REGNUM))])
4935 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4936 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4937 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4938 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4939 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4940 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4941 operands[9] = gen_label_rtx ();")
4944 ; subsi3 instruction pattern(s).
4947 (define_expand "subsi3"
4949 [(set (match_operand:SI 0 "register_operand" "")
4950 (minus:SI (match_operand:SI 1 "register_operand" "")
4951 (match_operand:SI 2 "general_operand" "")))
4952 (clobber (reg:CC CC_REGNUM))])]
4956 (define_insn "*subsi3_sign"
4957 [(set (match_operand:SI 0 "register_operand" "=d,d")
4958 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4959 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4960 (clobber (reg:CC CC_REGNUM))]
4965 [(set_attr "op_type" "RX,RXY")
4966 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4969 ; sub(di|si)3 instruction pattern(s).
4972 ; sr, s, sy, sgr, sg, srk, sgrk
4973 (define_insn "*sub<mode>3"
4974 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4975 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4976 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
4977 (clobber (reg:CC CC_REGNUM))]
4984 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4985 (set_attr "cpu_facility" "*,z196,*,*")
4986 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
4988 ; slr, sl, sly, slgr, slg, slrk, slgrk
4989 (define_insn "*sub<mode>3_borrow_cc"
4990 [(set (reg CC_REGNUM)
4991 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4992 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4994 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4995 (minus:GPR (match_dup 1) (match_dup 2)))]
4996 "s390_match_ccmode (insn, CCL2mode)"
5002 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5003 (set_attr "cpu_facility" "*,z196,*,*")
5004 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5006 ; slr, sl, sly, slgr, slg, slrk, slgrk
5007 (define_insn "*sub<mode>3_borrow_cconly"
5008 [(set (reg CC_REGNUM)
5009 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5010 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5012 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5013 "s390_match_ccmode (insn, CCL2mode)"
5019 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5020 (set_attr "cpu_facility" "*,z196,*,*")
5021 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5023 ; slr, sl, sly, slgr, slg, slrk, slgrk
5024 (define_insn "*sub<mode>3_cc"
5025 [(set (reg CC_REGNUM)
5026 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5027 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5029 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5030 (minus:GPR (match_dup 1) (match_dup 2)))]
5031 "s390_match_ccmode (insn, CCLmode)"
5037 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5038 (set_attr "cpu_facility" "*,z196,*,*")
5039 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5041 ; slr, sl, sly, slgr, slg, slrk, slgrk
5042 (define_insn "*sub<mode>3_cc2"
5043 [(set (reg CC_REGNUM)
5044 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5045 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5046 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5047 (minus:GPR (match_dup 1) (match_dup 2)))]
5048 "s390_match_ccmode (insn, CCL3mode)"
5054 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5055 (set_attr "cpu_facility" "*,z196,*,*")
5056 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5058 ; slr, sl, sly, slgr, slg, slrk, slgrk
5059 (define_insn "*sub<mode>3_cconly"
5060 [(set (reg CC_REGNUM)
5061 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5062 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5064 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5065 "s390_match_ccmode (insn, CCLmode)"
5071 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5072 (set_attr "cpu_facility" "*,z196,*,*")
5073 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5076 ; slr, sl, sly, slgr, slg, slrk, slgrk
5077 (define_insn "*sub<mode>3_cconly2"
5078 [(set (reg CC_REGNUM)
5079 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5080 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5081 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5082 "s390_match_ccmode (insn, CCL3mode)"
5088 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5089 (set_attr "cpu_facility" "*,z196,*,*")
5090 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5094 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5097 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5098 (define_insn "sub<mode>3"
5099 [(set (match_operand:FP 0 "register_operand" "=f, f")
5100 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5101 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5102 (clobber (reg:CC CC_REGNUM))]
5105 s<xde><bt>r\t%0,<op1>%2
5107 [(set_attr "op_type" "<RRer>,RXE")
5108 (set_attr "type" "fsimp<mode>")])
5110 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5111 (define_insn "*sub<mode>3_cc"
5112 [(set (reg CC_REGNUM)
5113 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5114 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5115 (match_operand:FP 3 "const0_operand" "")))
5116 (set (match_operand:FP 0 "register_operand" "=f,f")
5117 (minus:FP (match_dup 1) (match_dup 2)))]
5118 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5120 s<xde><bt>r\t%0,<op1>%2
5122 [(set_attr "op_type" "<RRer>,RXE")
5123 (set_attr "type" "fsimp<mode>")])
5125 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5126 (define_insn "*sub<mode>3_cconly"
5127 [(set (reg CC_REGNUM)
5128 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5129 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5130 (match_operand:FP 3 "const0_operand" "")))
5131 (clobber (match_scratch:FP 0 "=f,f"))]
5132 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5134 s<xde><bt>r\t%0,<op1>%2
5136 [(set_attr "op_type" "<RRer>,RXE")
5137 (set_attr "type" "fsimp<mode>")])
5141 ;;- Conditional add/subtract instructions.
5145 ; add(di|si)cc instruction pattern(s).
5148 ; the following 4 patterns are used when the result of an add with
5149 ; carry is checked for an overflow condition
5151 ; op1 + op2 + c < op1
5153 ; alcr, alc, alcgr, alcg
5154 (define_insn "*add<mode>3_alc_carry1_cc"
5155 [(set (reg CC_REGNUM)
5157 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5158 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5159 (match_operand:GPR 2 "general_operand" "d,RT"))
5161 (set (match_operand:GPR 0 "register_operand" "=d,d")
5162 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5163 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5167 [(set_attr "op_type" "RRE,RXY")
5168 (set_attr "z196prop" "z196_alone,z196_alone")])
5170 ; alcr, alc, alcgr, alcg
5171 (define_insn "*add<mode>3_alc_carry1_cconly"
5172 [(set (reg CC_REGNUM)
5174 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5175 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5176 (match_operand:GPR 2 "general_operand" "d,RT"))
5178 (clobber (match_scratch:GPR 0 "=d,d"))]
5179 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5183 [(set_attr "op_type" "RRE,RXY")
5184 (set_attr "z196prop" "z196_alone,z196_alone")])
5186 ; op1 + op2 + c < op2
5188 ; alcr, alc, alcgr, alcg
5189 (define_insn "*add<mode>3_alc_carry2_cc"
5190 [(set (reg CC_REGNUM)
5192 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5193 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5194 (match_operand:GPR 2 "general_operand" "d,RT"))
5196 (set (match_operand:GPR 0 "register_operand" "=d,d")
5197 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5198 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5202 [(set_attr "op_type" "RRE,RXY")])
5204 ; alcr, alc, alcgr, alcg
5205 (define_insn "*add<mode>3_alc_carry2_cconly"
5206 [(set (reg CC_REGNUM)
5208 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5209 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5210 (match_operand:GPR 2 "general_operand" "d,RT"))
5212 (clobber (match_scratch:GPR 0 "=d,d"))]
5213 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5217 [(set_attr "op_type" "RRE,RXY")])
5219 ; alcr, alc, alcgr, alcg
5220 (define_insn "*add<mode>3_alc_cc"
5221 [(set (reg CC_REGNUM)
5223 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5224 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5225 (match_operand:GPR 2 "general_operand" "d,RT"))
5227 (set (match_operand:GPR 0 "register_operand" "=d,d")
5228 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5229 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5233 [(set_attr "op_type" "RRE,RXY")])
5235 ; alcr, alc, alcgr, alcg
5236 (define_insn "*add<mode>3_alc"
5237 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5238 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5239 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5240 (match_operand:GPR 2 "general_operand" "d,RT")))
5241 (clobber (reg:CC CC_REGNUM))]
5246 [(set_attr "op_type" "RRE,RXY")])
5248 ; slbr, slb, slbgr, slbg
5249 (define_insn "*sub<mode>3_slb_cc"
5250 [(set (reg CC_REGNUM)
5252 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5253 (match_operand:GPR 2 "general_operand" "d,RT"))
5254 (match_operand:GPR 3 "s390_slb_comparison" ""))
5256 (set (match_operand:GPR 0 "register_operand" "=d,d")
5257 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5258 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5262 [(set_attr "op_type" "RRE,RXY")
5263 (set_attr "z10prop" "z10_c,*")])
5265 ; slbr, slb, slbgr, slbg
5266 (define_insn "*sub<mode>3_slb"
5267 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5268 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5269 (match_operand:GPR 2 "general_operand" "d,RT"))
5270 (match_operand:GPR 3 "s390_slb_comparison" "")))
5271 (clobber (reg:CC CC_REGNUM))]
5276 [(set_attr "op_type" "RRE,RXY")
5277 (set_attr "z10prop" "z10_c,*")])
5279 (define_expand "add<mode>cc"
5280 [(match_operand:GPR 0 "register_operand" "")
5281 (match_operand 1 "comparison_operator" "")
5282 (match_operand:GPR 2 "register_operand" "")
5283 (match_operand:GPR 3 "const_int_operand" "")]
5285 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5286 XEXP (operands[1], 0), XEXP (operands[1], 1),
5287 operands[0], operands[2],
5288 operands[3])) FAIL; DONE;")
5291 ; scond instruction pattern(s).
5294 (define_insn_and_split "*scond<mode>"
5295 [(set (match_operand:GPR 0 "register_operand" "=&d")
5296 (match_operand:GPR 1 "s390_alc_comparison" ""))
5297 (clobber (reg:CC CC_REGNUM))]
5300 "&& reload_completed"
5301 [(set (match_dup 0) (const_int 0))
5303 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5305 (clobber (reg:CC CC_REGNUM))])]
5308 (define_insn_and_split "*scond<mode>_neg"
5309 [(set (match_operand:GPR 0 "register_operand" "=&d")
5310 (match_operand:GPR 1 "s390_slb_comparison" ""))
5311 (clobber (reg:CC CC_REGNUM))]
5314 "&& reload_completed"
5315 [(set (match_dup 0) (const_int 0))
5317 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5319 (clobber (reg:CC CC_REGNUM))])
5321 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5322 (clobber (reg:CC CC_REGNUM))])]
5326 (define_expand "cstore<mode>4"
5327 [(set (match_operand:SI 0 "register_operand" "")
5328 (match_operator:SI 1 "s390_scond_operator"
5329 [(match_operand:GPR 2 "register_operand" "")
5330 (match_operand:GPR 3 "general_operand" "")]))]
5332 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5333 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5335 (define_expand "cstorecc4"
5337 [(set (match_operand:SI 0 "register_operand" "")
5338 (match_operator:SI 1 "s390_eqne_operator"
5339 [(match_operand:CCZ1 2 "register_operand")
5340 (match_operand 3 "const0_operand")]))
5341 (clobber (reg:CC CC_REGNUM))])]
5343 "emit_insn (gen_sne (operands[0], operands[2]));
5344 if (GET_CODE (operands[1]) == EQ)
5345 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5348 (define_insn_and_split "sne"
5349 [(set (match_operand:SI 0 "register_operand" "=d")
5350 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5352 (clobber (reg:CC CC_REGNUM))]
5357 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5358 (clobber (reg:CC CC_REGNUM))])])
5362 ;; - Conditional move instructions (introduced with z196)
5365 (define_expand "mov<mode>cc"
5366 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5367 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5368 (match_operand:GPR 2 "nonimmediate_operand" "")
5369 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5371 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5372 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5374 ; locr, loc, stoc, locgr, locg, stocg
5375 (define_insn_and_split "*mov<mode>cc"
5376 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5378 (match_operator 1 "s390_comparison"
5379 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5381 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5382 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5392 "&& reload_completed
5393 && MEM_P (operands[3]) && MEM_P (operands[4])"
5396 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5401 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5405 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5408 ;;- Multiply instructions.
5412 ; muldi3 instruction pattern(s).
5415 (define_insn "*muldi3_sign"
5416 [(set (match_operand:DI 0 "register_operand" "=d,d")
5417 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5418 (match_operand:DI 1 "register_operand" "0,0")))]
5423 [(set_attr "op_type" "RRE,RXY")
5424 (set_attr "type" "imuldi")])
5426 (define_insn "muldi3"
5427 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5428 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5429 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5436 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5437 (set_attr "type" "imuldi")
5438 (set_attr "cpu_facility" "*,*,*,z10")])
5441 ; mulsi3 instruction pattern(s).
5444 (define_insn "*mulsi3_sign"
5445 [(set (match_operand:SI 0 "register_operand" "=d,d")
5446 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5447 (match_operand:SI 1 "register_operand" "0,0")))]
5452 [(set_attr "op_type" "RX,RXY")
5453 (set_attr "type" "imulhi")
5454 (set_attr "cpu_facility" "*,z10")])
5456 (define_insn "mulsi3"
5457 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5458 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5459 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5467 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5468 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5469 (set_attr "cpu_facility" "*,*,*,*,z10")])
5472 ; mulsidi3 instruction pattern(s).
5475 (define_insn "mulsidi3"
5476 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5477 (mult:DI (sign_extend:DI
5478 (match_operand:SI 1 "register_operand" "%0,0,0"))
5480 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5486 [(set_attr "op_type" "RR,RX,RXY")
5487 (set_attr "type" "imulsi")
5488 (set_attr "cpu_facility" "*,*,z10")])
5491 ; umul instruction pattern(s).
5494 ; mlr, ml, mlgr, mlg
5495 (define_insn "umul<dwh><mode>3"
5496 [(set (match_operand:DW 0 "register_operand" "=d, d")
5497 (mult:DW (zero_extend:DW
5498 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5500 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5505 [(set_attr "op_type" "RRE,RXY")
5506 (set_attr "type" "imul<dwh>")])
5509 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5512 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5513 (define_insn "mul<mode>3"
5514 [(set (match_operand:FP 0 "register_operand" "=f,f")
5515 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5516 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5519 m<xdee><bt>r\t%0,<op1>%2
5521 [(set_attr "op_type" "<RRer>,RXE")
5522 (set_attr "type" "fmul<mode>")])
5524 ; madbr, maebr, maxb, madb, maeb
5525 (define_insn "fma<mode>4"
5526 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5527 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5528 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5529 (match_operand:DSF 3 "register_operand" "0,0")))]
5534 [(set_attr "op_type" "RRE,RXE")
5535 (set_attr "type" "fmadd<mode>")])
5537 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5538 (define_insn "fms<mode>4"
5539 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5540 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5541 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5542 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5547 [(set_attr "op_type" "RRE,RXE")
5548 (set_attr "type" "fmadd<mode>")])
5551 ;;- Divide and modulo instructions.
5555 ; divmoddi4 instruction pattern(s).
5558 (define_expand "divmoddi4"
5559 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5560 (div:DI (match_operand:DI 1 "register_operand" "")
5561 (match_operand:DI 2 "general_operand" "")))
5562 (set (match_operand:DI 3 "general_operand" "")
5563 (mod:DI (match_dup 1) (match_dup 2)))])
5564 (clobber (match_dup 4))]
5567 rtx insn, div_equal, mod_equal;
5569 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5570 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5572 operands[4] = gen_reg_rtx(TImode);
5573 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5575 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5576 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5578 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5579 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5584 (define_insn "divmodtidi3"
5585 [(set (match_operand:TI 0 "register_operand" "=d,d")
5589 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5590 (match_operand:DI 2 "general_operand" "d,RT")))
5592 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5597 [(set_attr "op_type" "RRE,RXY")
5598 (set_attr "type" "idiv")])
5600 (define_insn "divmodtisi3"
5601 [(set (match_operand:TI 0 "register_operand" "=d,d")
5605 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5607 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5610 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5615 [(set_attr "op_type" "RRE,RXY")
5616 (set_attr "type" "idiv")])
5619 ; udivmoddi4 instruction pattern(s).
5622 (define_expand "udivmoddi4"
5623 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5624 (udiv:DI (match_operand:DI 1 "general_operand" "")
5625 (match_operand:DI 2 "nonimmediate_operand" "")))
5626 (set (match_operand:DI 3 "general_operand" "")
5627 (umod:DI (match_dup 1) (match_dup 2)))])
5628 (clobber (match_dup 4))]
5631 rtx insn, div_equal, mod_equal, equal;
5633 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5634 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5635 equal = gen_rtx_IOR (TImode,
5636 gen_rtx_ASHIFT (TImode,
5637 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5639 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5641 operands[4] = gen_reg_rtx(TImode);
5642 emit_clobber (operands[4]);
5643 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5644 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5646 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5647 set_unique_reg_note (insn, REG_EQUAL, equal);
5649 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5650 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5652 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5653 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5658 (define_insn "udivmodtidi3"
5659 [(set (match_operand:TI 0 "register_operand" "=d,d")
5664 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5666 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5670 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5675 [(set_attr "op_type" "RRE,RXY")
5676 (set_attr "type" "idiv")])
5679 ; divmodsi4 instruction pattern(s).
5682 (define_expand "divmodsi4"
5683 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5684 (div:SI (match_operand:SI 1 "general_operand" "")
5685 (match_operand:SI 2 "nonimmediate_operand" "")))
5686 (set (match_operand:SI 3 "general_operand" "")
5687 (mod:SI (match_dup 1) (match_dup 2)))])
5688 (clobber (match_dup 4))]
5691 rtx insn, div_equal, mod_equal, equal;
5693 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5694 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5695 equal = gen_rtx_IOR (DImode,
5696 gen_rtx_ASHIFT (DImode,
5697 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5699 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5701 operands[4] = gen_reg_rtx(DImode);
5702 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5704 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5705 set_unique_reg_note (insn, REG_EQUAL, equal);
5707 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5708 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5710 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5711 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5716 (define_insn "divmoddisi3"
5717 [(set (match_operand:DI 0 "register_operand" "=d,d")
5722 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5724 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5728 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5733 [(set_attr "op_type" "RR,RX")
5734 (set_attr "type" "idiv")])
5737 ; udivsi3 and umodsi3 instruction pattern(s).
5740 (define_expand "udivmodsi4"
5741 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5742 (udiv:SI (match_operand:SI 1 "general_operand" "")
5743 (match_operand:SI 2 "nonimmediate_operand" "")))
5744 (set (match_operand:SI 3 "general_operand" "")
5745 (umod:SI (match_dup 1) (match_dup 2)))])
5746 (clobber (match_dup 4))]
5747 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5749 rtx insn, div_equal, mod_equal, equal;
5751 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5752 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5753 equal = gen_rtx_IOR (DImode,
5754 gen_rtx_ASHIFT (DImode,
5755 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5757 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5759 operands[4] = gen_reg_rtx(DImode);
5760 emit_clobber (operands[4]);
5761 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5762 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5764 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5765 set_unique_reg_note (insn, REG_EQUAL, equal);
5767 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5768 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5770 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5771 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5776 (define_insn "udivmoddisi3"
5777 [(set (match_operand:DI 0 "register_operand" "=d,d")
5782 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5784 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5788 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5789 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5793 [(set_attr "op_type" "RRE,RXY")
5794 (set_attr "type" "idiv")])
5796 (define_expand "udivsi3"
5797 [(set (match_operand:SI 0 "register_operand" "=d")
5798 (udiv:SI (match_operand:SI 1 "general_operand" "")
5799 (match_operand:SI 2 "general_operand" "")))
5800 (clobber (match_dup 3))]
5801 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5803 rtx insn, udiv_equal, umod_equal, equal;
5805 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5806 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5807 equal = gen_rtx_IOR (DImode,
5808 gen_rtx_ASHIFT (DImode,
5809 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5811 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5813 operands[3] = gen_reg_rtx (DImode);
5815 if (CONSTANT_P (operands[2]))
5817 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5819 rtx label1 = gen_label_rtx ();
5821 operands[1] = make_safe_from (operands[1], operands[0]);
5822 emit_move_insn (operands[0], const0_rtx);
5823 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5825 emit_move_insn (operands[0], const1_rtx);
5826 emit_label (label1);
5830 operands[2] = force_reg (SImode, operands[2]);
5831 operands[2] = make_safe_from (operands[2], operands[0]);
5833 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5834 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5836 set_unique_reg_note (insn, REG_EQUAL, equal);
5838 insn = emit_move_insn (operands[0],
5839 gen_lowpart (SImode, operands[3]));
5840 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5845 rtx label1 = gen_label_rtx ();
5846 rtx label2 = gen_label_rtx ();
5847 rtx label3 = gen_label_rtx ();
5849 operands[1] = force_reg (SImode, operands[1]);
5850 operands[1] = make_safe_from (operands[1], operands[0]);
5851 operands[2] = force_reg (SImode, operands[2]);
5852 operands[2] = make_safe_from (operands[2], operands[0]);
5854 emit_move_insn (operands[0], const0_rtx);
5855 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5857 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5859 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5861 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5862 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5864 set_unique_reg_note (insn, REG_EQUAL, equal);
5866 insn = emit_move_insn (operands[0],
5867 gen_lowpart (SImode, operands[3]));
5868 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5871 emit_label (label1);
5872 emit_move_insn (operands[0], operands[1]);
5874 emit_label (label2);
5875 emit_move_insn (operands[0], const1_rtx);
5876 emit_label (label3);
5878 emit_move_insn (operands[0], operands[0]);
5882 (define_expand "umodsi3"
5883 [(set (match_operand:SI 0 "register_operand" "=d")
5884 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5885 (match_operand:SI 2 "nonimmediate_operand" "")))
5886 (clobber (match_dup 3))]
5887 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5889 rtx insn, udiv_equal, umod_equal, equal;
5891 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5892 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5893 equal = gen_rtx_IOR (DImode,
5894 gen_rtx_ASHIFT (DImode,
5895 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5897 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5899 operands[3] = gen_reg_rtx (DImode);
5901 if (CONSTANT_P (operands[2]))
5903 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5905 rtx label1 = gen_label_rtx ();
5907 operands[1] = make_safe_from (operands[1], operands[0]);
5908 emit_move_insn (operands[0], operands[1]);
5909 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5911 emit_insn (gen_abssi2 (operands[0], operands[2]));
5912 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5913 emit_label (label1);
5917 operands[2] = force_reg (SImode, operands[2]);
5918 operands[2] = make_safe_from (operands[2], operands[0]);
5920 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5921 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5923 set_unique_reg_note (insn, REG_EQUAL, equal);
5925 insn = emit_move_insn (operands[0],
5926 gen_highpart (SImode, operands[3]));
5927 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5932 rtx label1 = gen_label_rtx ();
5933 rtx label2 = gen_label_rtx ();
5934 rtx label3 = gen_label_rtx ();
5936 operands[1] = force_reg (SImode, operands[1]);
5937 operands[1] = make_safe_from (operands[1], operands[0]);
5938 operands[2] = force_reg (SImode, operands[2]);
5939 operands[2] = make_safe_from (operands[2], operands[0]);
5941 emit_move_insn(operands[0], operands[1]);
5942 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5944 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5946 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5948 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5949 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5951 set_unique_reg_note (insn, REG_EQUAL, equal);
5953 insn = emit_move_insn (operands[0],
5954 gen_highpart (SImode, operands[3]));
5955 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5958 emit_label (label1);
5959 emit_move_insn (operands[0], const0_rtx);
5961 emit_label (label2);
5962 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5963 emit_label (label3);
5969 ; div(df|sf)3 instruction pattern(s).
5972 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5973 (define_insn "div<mode>3"
5974 [(set (match_operand:FP 0 "register_operand" "=f,f")
5975 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5976 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5979 d<xde><bt>r\t%0,<op1>%2
5981 [(set_attr "op_type" "<RRer>,RXE")
5982 (set_attr "type" "fdiv<mode>")])
5986 ;;- And instructions.
5989 (define_expand "and<mode>3"
5990 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5991 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5992 (match_operand:INT 2 "general_operand" "")))
5993 (clobber (reg:CC CC_REGNUM))]
5995 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5998 ; anddi3 instruction pattern(s).
6001 (define_insn "*anddi3_cc"
6002 [(set (reg CC_REGNUM)
6003 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6004 (match_operand:DI 2 "general_operand" " d,d,RT"))
6006 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6007 (and:DI (match_dup 1) (match_dup 2)))]
6008 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6013 [(set_attr "op_type" "RRE,RRF,RXY")
6014 (set_attr "cpu_facility" "*,z196,*")
6015 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6017 (define_insn "*anddi3_cconly"
6018 [(set (reg CC_REGNUM)
6019 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6020 (match_operand:DI 2 "general_operand" " d,d,RT"))
6022 (clobber (match_scratch:DI 0 "=d,d, d"))]
6023 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
6024 /* Do not steal TM patterns. */
6025 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6030 [(set_attr "op_type" "RRE,RRF,RXY")
6031 (set_attr "cpu_facility" "*,z196,*")
6032 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6034 (define_insn "*anddi3"
6035 [(set (match_operand:DI 0 "nonimmediate_operand"
6036 "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
6037 (and:DI (match_operand:DI 1 "nonimmediate_operand"
6038 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6039 (match_operand:DI 2 "general_operand"
6040 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
6041 (clobber (reg:CC CC_REGNUM))]
6042 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6057 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6058 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
6059 (set_attr "z10prop" "*,
6074 [(set (match_operand:DI 0 "s_operand" "")
6075 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6076 (clobber (reg:CC CC_REGNUM))]
6079 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6080 (clobber (reg:CC CC_REGNUM))])]
6081 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6085 ; andsi3 instruction pattern(s).
6088 (define_insn "*andsi3_cc"
6089 [(set (reg CC_REGNUM)
6090 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6091 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6093 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6094 (and:SI (match_dup 1) (match_dup 2)))]
6095 "s390_match_ccmode(insn, CCTmode)"
6102 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6103 (set_attr "cpu_facility" "*,*,z196,*,*")
6104 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6106 (define_insn "*andsi3_cconly"
6107 [(set (reg CC_REGNUM)
6108 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6109 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6111 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6112 "s390_match_ccmode(insn, CCTmode)
6113 /* Do not steal TM patterns. */
6114 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6121 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6122 (set_attr "cpu_facility" "*,*,z196,*,*")
6123 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6124 z10_super_E1,z10_super_E1")])
6126 (define_insn "*andsi3_zarch"
6127 [(set (match_operand:SI 0 "nonimmediate_operand"
6128 "=d,d, d, d, d,d,d,d,d, AQ,Q")
6129 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6130 "%d,o, 0, 0, 0,0,d,0,0, 0,0")
6131 (match_operand:SI 2 "general_operand"
6132 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
6133 (clobber (reg:CC CC_REGNUM))]
6134 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6147 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6148 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
6149 (set_attr "z10prop" "*,
6161 (define_insn "*andsi3_esa"
6162 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6163 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6164 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6165 (clobber (reg:CC CC_REGNUM))]
6166 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6172 [(set_attr "op_type" "RR,RX,SI,SS")
6173 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6177 [(set (match_operand:SI 0 "s_operand" "")
6178 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6179 (clobber (reg:CC CC_REGNUM))]
6182 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6183 (clobber (reg:CC CC_REGNUM))])]
6184 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6187 ; andhi3 instruction pattern(s).
6190 (define_insn "*andhi3_zarch"
6191 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6192 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6193 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6194 (clobber (reg:CC CC_REGNUM))]
6195 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6202 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6203 (set_attr "cpu_facility" "*,z196,*,*,*")
6204 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6207 (define_insn "*andhi3_esa"
6208 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6209 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6210 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6211 (clobber (reg:CC CC_REGNUM))]
6212 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6217 [(set_attr "op_type" "RR,SI,SS")
6218 (set_attr "z10prop" "z10_super_E1,*,*")
6222 [(set (match_operand:HI 0 "s_operand" "")
6223 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6224 (clobber (reg:CC CC_REGNUM))]
6227 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6228 (clobber (reg:CC CC_REGNUM))])]
6229 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6232 ; andqi3 instruction pattern(s).
6235 (define_insn "*andqi3_zarch"
6236 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6237 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6238 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6239 (clobber (reg:CC CC_REGNUM))]
6240 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6248 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6249 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6250 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6252 (define_insn "*andqi3_esa"
6253 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6254 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6255 (match_operand:QI 2 "general_operand" "d,n,Q")))
6256 (clobber (reg:CC CC_REGNUM))]
6257 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6262 [(set_attr "op_type" "RR,SI,SS")
6263 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6266 ; Block and (NC) patterns.
6270 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6271 (and:BLK (match_dup 0)
6272 (match_operand:BLK 1 "memory_operand" "Q")))
6273 (use (match_operand 2 "const_int_operand" "n"))
6274 (clobber (reg:CC CC_REGNUM))]
6275 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6276 "nc\t%O0(%2,%R0),%S1"
6277 [(set_attr "op_type" "SS")
6278 (set_attr "z196prop" "z196_cracked")])
6281 [(set (match_operand 0 "memory_operand" "")
6283 (match_operand 1 "memory_operand" "")))
6284 (clobber (reg:CC CC_REGNUM))]
6286 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6287 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6289 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6291 (clobber (reg:CC CC_REGNUM))])]
6293 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6294 operands[0] = adjust_address (operands[0], BLKmode, 0);
6295 operands[1] = adjust_address (operands[1], BLKmode, 0);
6300 [(set (match_operand:BLK 0 "memory_operand" "")
6301 (and:BLK (match_dup 0)
6302 (match_operand:BLK 1 "memory_operand" "")))
6303 (use (match_operand 2 "const_int_operand" ""))
6304 (clobber (reg:CC CC_REGNUM))])
6306 [(set (match_operand:BLK 3 "memory_operand" "")
6307 (and:BLK (match_dup 3)
6308 (match_operand:BLK 4 "memory_operand" "")))
6309 (use (match_operand 5 "const_int_operand" ""))
6310 (clobber (reg:CC CC_REGNUM))])]
6311 "s390_offset_p (operands[0], operands[3], operands[2])
6312 && s390_offset_p (operands[1], operands[4], operands[2])
6313 && !s390_overlap_p (operands[0], operands[1],
6314 INTVAL (operands[2]) + INTVAL (operands[5]))
6315 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6317 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6319 (clobber (reg:CC CC_REGNUM))])]
6320 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6321 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6322 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6326 ;;- Bit set (inclusive or) instructions.
6329 (define_expand "ior<mode>3"
6330 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6331 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6332 (match_operand:INT 2 "general_operand" "")))
6333 (clobber (reg:CC CC_REGNUM))]
6335 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6338 ; iordi3 instruction pattern(s).
6341 (define_insn "*iordi3_cc"
6342 [(set (reg CC_REGNUM)
6343 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6344 (match_operand:DI 2 "general_operand" " d,d,RT"))
6346 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6347 (ior:DI (match_dup 1) (match_dup 2)))]
6348 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6353 [(set_attr "op_type" "RRE,RRF,RXY")
6354 (set_attr "cpu_facility" "*,z196,*")
6355 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6357 (define_insn "*iordi3_cconly"
6358 [(set (reg CC_REGNUM)
6359 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6360 (match_operand:DI 2 "general_operand" " d,d,RT"))
6362 (clobber (match_scratch:DI 0 "=d,d,d"))]
6363 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6368 [(set_attr "op_type" "RRE,RRF,RXY")
6369 (set_attr "cpu_facility" "*,z196,*")
6370 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6372 (define_insn "*iordi3"
6373 [(set (match_operand:DI 0 "nonimmediate_operand"
6374 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6375 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6376 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6377 (match_operand:DI 2 "general_operand"
6378 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6379 (clobber (reg:CC CC_REGNUM))]
6380 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6393 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6394 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6395 (set_attr "z10prop" "z10_super_E1,
6408 [(set (match_operand:DI 0 "s_operand" "")
6409 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6410 (clobber (reg:CC CC_REGNUM))]
6413 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6414 (clobber (reg:CC CC_REGNUM))])]
6415 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6418 ; iorsi3 instruction pattern(s).
6421 (define_insn "*iorsi3_cc"
6422 [(set (reg CC_REGNUM)
6423 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6424 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6426 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6427 (ior:SI (match_dup 1) (match_dup 2)))]
6428 "s390_match_ccmode(insn, CCTmode)"
6435 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6436 (set_attr "cpu_facility" "*,*,z196,*,*")
6437 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6439 (define_insn "*iorsi3_cconly"
6440 [(set (reg CC_REGNUM)
6441 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6442 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6444 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6445 "s390_match_ccmode(insn, CCTmode)"
6452 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6453 (set_attr "cpu_facility" "*,*,z196,*,*")
6454 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6456 (define_insn "*iorsi3_zarch"
6457 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6458 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6459 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6460 (clobber (reg:CC CC_REGNUM))]
6461 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6472 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6473 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6474 (set_attr "z10prop" "z10_super_E1,
6484 (define_insn "*iorsi3_esa"
6485 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6486 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6487 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6488 (clobber (reg:CC CC_REGNUM))]
6489 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6495 [(set_attr "op_type" "RR,RX,SI,SS")
6496 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6499 [(set (match_operand:SI 0 "s_operand" "")
6500 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6501 (clobber (reg:CC CC_REGNUM))]
6504 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6505 (clobber (reg:CC CC_REGNUM))])]
6506 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6509 ; iorhi3 instruction pattern(s).
6512 (define_insn "*iorhi3_zarch"
6513 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6514 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6515 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6516 (clobber (reg:CC CC_REGNUM))]
6517 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6524 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6525 (set_attr "cpu_facility" "*,z196,*,*,*")
6526 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6528 (define_insn "*iorhi3_esa"
6529 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6530 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6531 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6532 (clobber (reg:CC CC_REGNUM))]
6533 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6538 [(set_attr "op_type" "RR,SI,SS")
6539 (set_attr "z10prop" "z10_super_E1,*,*")])
6542 [(set (match_operand:HI 0 "s_operand" "")
6543 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6544 (clobber (reg:CC CC_REGNUM))]
6547 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6548 (clobber (reg:CC CC_REGNUM))])]
6549 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6552 ; iorqi3 instruction pattern(s).
6555 (define_insn "*iorqi3_zarch"
6556 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6557 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6558 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6559 (clobber (reg:CC CC_REGNUM))]
6560 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6568 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6569 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6570 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6571 z10_super,z10_super,*")])
6573 (define_insn "*iorqi3_esa"
6574 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6575 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6576 (match_operand:QI 2 "general_operand" "d,n,Q")))
6577 (clobber (reg:CC CC_REGNUM))]
6578 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6583 [(set_attr "op_type" "RR,SI,SS")
6584 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6587 ; Block inclusive or (OC) patterns.
6591 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6592 (ior:BLK (match_dup 0)
6593 (match_operand:BLK 1 "memory_operand" "Q")))
6594 (use (match_operand 2 "const_int_operand" "n"))
6595 (clobber (reg:CC CC_REGNUM))]
6596 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6597 "oc\t%O0(%2,%R0),%S1"
6598 [(set_attr "op_type" "SS")
6599 (set_attr "z196prop" "z196_cracked")])
6602 [(set (match_operand 0 "memory_operand" "")
6604 (match_operand 1 "memory_operand" "")))
6605 (clobber (reg:CC CC_REGNUM))]
6607 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6608 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6610 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6612 (clobber (reg:CC CC_REGNUM))])]
6614 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6615 operands[0] = adjust_address (operands[0], BLKmode, 0);
6616 operands[1] = adjust_address (operands[1], BLKmode, 0);
6621 [(set (match_operand:BLK 0 "memory_operand" "")
6622 (ior:BLK (match_dup 0)
6623 (match_operand:BLK 1 "memory_operand" "")))
6624 (use (match_operand 2 "const_int_operand" ""))
6625 (clobber (reg:CC CC_REGNUM))])
6627 [(set (match_operand:BLK 3 "memory_operand" "")
6628 (ior:BLK (match_dup 3)
6629 (match_operand:BLK 4 "memory_operand" "")))
6630 (use (match_operand 5 "const_int_operand" ""))
6631 (clobber (reg:CC CC_REGNUM))])]
6632 "s390_offset_p (operands[0], operands[3], operands[2])
6633 && s390_offset_p (operands[1], operands[4], operands[2])
6634 && !s390_overlap_p (operands[0], operands[1],
6635 INTVAL (operands[2]) + INTVAL (operands[5]))
6636 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6638 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6640 (clobber (reg:CC CC_REGNUM))])]
6641 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6642 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6643 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6647 ;;- Xor instructions.
6650 (define_expand "xor<mode>3"
6651 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6652 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6653 (match_operand:INT 2 "general_operand" "")))
6654 (clobber (reg:CC CC_REGNUM))]
6656 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6659 ; xordi3 instruction pattern(s).
6662 (define_insn "*xordi3_cc"
6663 [(set (reg CC_REGNUM)
6664 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6665 (match_operand:DI 2 "general_operand" " d,d,RT"))
6667 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6668 (xor:DI (match_dup 1) (match_dup 2)))]
6669 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6674 [(set_attr "op_type" "RRE,RRF,RXY")
6675 (set_attr "cpu_facility" "*,z196,*")
6676 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6678 (define_insn "*xordi3_cconly"
6679 [(set (reg CC_REGNUM)
6680 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6681 (match_operand:DI 2 "general_operand" " d,d,RT"))
6683 (clobber (match_scratch:DI 0 "=d,d, d"))]
6684 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6689 [(set_attr "op_type" "RRE,RRF,RXY")
6690 (set_attr "cpu_facility" "*,z196,*")
6691 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6693 (define_insn "*xordi3"
6694 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6695 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6696 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6697 (clobber (reg:CC CC_REGNUM))]
6698 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6707 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6708 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6709 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6710 *,z10_super_E1,*,*")])
6713 [(set (match_operand:DI 0 "s_operand" "")
6714 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6715 (clobber (reg:CC CC_REGNUM))]
6718 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6719 (clobber (reg:CC CC_REGNUM))])]
6720 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6723 ; xorsi3 instruction pattern(s).
6726 (define_insn "*xorsi3_cc"
6727 [(set (reg CC_REGNUM)
6728 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6729 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6731 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6732 (xor:SI (match_dup 1) (match_dup 2)))]
6733 "s390_match_ccmode(insn, CCTmode)"
6740 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6741 (set_attr "cpu_facility" "*,*,z196,*,*")
6742 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6743 z10_super_E1,z10_super_E1")])
6745 (define_insn "*xorsi3_cconly"
6746 [(set (reg CC_REGNUM)
6747 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6748 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6750 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6751 "s390_match_ccmode(insn, CCTmode)"
6758 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6759 (set_attr "cpu_facility" "*,*,z196,*,*")
6760 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6761 z10_super_E1,z10_super_E1")])
6763 (define_insn "*xorsi3"
6764 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6765 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6766 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6767 (clobber (reg:CC CC_REGNUM))]
6768 "s390_logical_operator_ok_p (operands)"
6777 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6778 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6779 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6780 z10_super_E1,z10_super_E1,*,*")])
6783 [(set (match_operand:SI 0 "s_operand" "")
6784 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6785 (clobber (reg:CC CC_REGNUM))]
6788 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6789 (clobber (reg:CC CC_REGNUM))])]
6790 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6793 ; xorhi3 instruction pattern(s).
6796 (define_insn "*xorhi3"
6797 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6798 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6799 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6800 (clobber (reg:CC CC_REGNUM))]
6801 "s390_logical_operator_ok_p (operands)"
6808 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6809 (set_attr "cpu_facility" "*,*,z196,*,*")
6810 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6813 [(set (match_operand:HI 0 "s_operand" "")
6814 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6815 (clobber (reg:CC CC_REGNUM))]
6818 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6819 (clobber (reg:CC CC_REGNUM))])]
6820 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6823 ; xorqi3 instruction pattern(s).
6826 (define_insn "*xorqi3"
6827 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6828 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
6829 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
6830 (clobber (reg:CC CC_REGNUM))]
6831 "s390_logical_operator_ok_p (operands)"
6839 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
6840 (set_attr "cpu_facility" "*,*,z196,*,*,*")
6841 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
6845 ; Block exclusive or (XC) patterns.
6849 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6850 (xor:BLK (match_dup 0)
6851 (match_operand:BLK 1 "memory_operand" "Q")))
6852 (use (match_operand 2 "const_int_operand" "n"))
6853 (clobber (reg:CC CC_REGNUM))]
6854 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6855 "xc\t%O0(%2,%R0),%S1"
6856 [(set_attr "op_type" "SS")])
6859 [(set (match_operand 0 "memory_operand" "")
6861 (match_operand 1 "memory_operand" "")))
6862 (clobber (reg:CC CC_REGNUM))]
6864 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6865 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6867 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6869 (clobber (reg:CC CC_REGNUM))])]
6871 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6872 operands[0] = adjust_address (operands[0], BLKmode, 0);
6873 operands[1] = adjust_address (operands[1], BLKmode, 0);
6878 [(set (match_operand:BLK 0 "memory_operand" "")
6879 (xor:BLK (match_dup 0)
6880 (match_operand:BLK 1 "memory_operand" "")))
6881 (use (match_operand 2 "const_int_operand" ""))
6882 (clobber (reg:CC CC_REGNUM))])
6884 [(set (match_operand:BLK 3 "memory_operand" "")
6885 (xor:BLK (match_dup 3)
6886 (match_operand:BLK 4 "memory_operand" "")))
6887 (use (match_operand 5 "const_int_operand" ""))
6888 (clobber (reg:CC CC_REGNUM))])]
6889 "s390_offset_p (operands[0], operands[3], operands[2])
6890 && s390_offset_p (operands[1], operands[4], operands[2])
6891 && !s390_overlap_p (operands[0], operands[1],
6892 INTVAL (operands[2]) + INTVAL (operands[5]))
6893 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6895 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6897 (clobber (reg:CC CC_REGNUM))])]
6898 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6899 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6900 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6903 ; Block xor (XC) patterns with src == dest.
6906 (define_insn "*xc_zero"
6907 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6909 (use (match_operand 1 "const_int_operand" "n"))
6910 (clobber (reg:CC CC_REGNUM))]
6911 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6912 "xc\t%O0(%1,%R0),%S0"
6913 [(set_attr "op_type" "SS")
6914 (set_attr "z196prop" "z196_cracked")])
6918 [(set (match_operand:BLK 0 "memory_operand" "")
6920 (use (match_operand 1 "const_int_operand" ""))
6921 (clobber (reg:CC CC_REGNUM))])
6923 [(set (match_operand:BLK 2 "memory_operand" "")
6925 (use (match_operand 3 "const_int_operand" ""))
6926 (clobber (reg:CC CC_REGNUM))])]
6927 "s390_offset_p (operands[0], operands[2], operands[1])
6928 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6930 [(set (match_dup 4) (const_int 0))
6932 (clobber (reg:CC CC_REGNUM))])]
6933 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6934 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6938 ;;- Negate instructions.
6942 ; neg(di|si)2 instruction pattern(s).
6945 (define_expand "neg<mode>2"
6947 [(set (match_operand:DSI 0 "register_operand" "=d")
6948 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6949 (clobber (reg:CC CC_REGNUM))])]
6953 (define_insn "*negdi2_sign_cc"
6954 [(set (reg CC_REGNUM)
6955 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6956 (match_operand:SI 1 "register_operand" "d") 0)
6957 (const_int 32)) (const_int 32)))
6959 (set (match_operand:DI 0 "register_operand" "=d")
6960 (neg:DI (sign_extend:DI (match_dup 1))))]
6961 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6963 [(set_attr "op_type" "RRE")
6964 (set_attr "z10prop" "z10_c")])
6966 (define_insn "*negdi2_sign"
6967 [(set (match_operand:DI 0 "register_operand" "=d")
6968 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6969 (clobber (reg:CC CC_REGNUM))]
6972 [(set_attr "op_type" "RRE")
6973 (set_attr "z10prop" "z10_c")])
6976 (define_insn "*neg<mode>2_cc"
6977 [(set (reg CC_REGNUM)
6978 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6980 (set (match_operand:GPR 0 "register_operand" "=d")
6981 (neg:GPR (match_dup 1)))]
6982 "s390_match_ccmode (insn, CCAmode)"
6984 [(set_attr "op_type" "RR<E>")
6985 (set_attr "z10prop" "z10_super_c_E1")])
6988 (define_insn "*neg<mode>2_cconly"
6989 [(set (reg CC_REGNUM)
6990 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6992 (clobber (match_scratch:GPR 0 "=d"))]
6993 "s390_match_ccmode (insn, CCAmode)"
6995 [(set_attr "op_type" "RR<E>")
6996 (set_attr "z10prop" "z10_super_c_E1")])
6999 (define_insn "*neg<mode>2"
7000 [(set (match_operand:GPR 0 "register_operand" "=d")
7001 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7002 (clobber (reg:CC CC_REGNUM))]
7005 [(set_attr "op_type" "RR<E>")
7006 (set_attr "z10prop" "z10_super_c_E1")])
7008 (define_insn_and_split "*negdi2_31"
7009 [(set (match_operand:DI 0 "register_operand" "=d")
7010 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7011 (clobber (reg:CC CC_REGNUM))]
7014 "&& reload_completed"
7016 [(set (match_dup 2) (neg:SI (match_dup 3)))
7017 (clobber (reg:CC CC_REGNUM))])
7019 [(set (reg:CCAP CC_REGNUM)
7020 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7021 (set (match_dup 4) (neg:SI (match_dup 5)))])
7023 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7025 (label_ref (match_dup 6))))
7027 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7028 (clobber (reg:CC CC_REGNUM))])
7030 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7031 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7032 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7033 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7034 operands[6] = gen_label_rtx ();")
7037 ; neg(df|sf)2 instruction pattern(s).
7040 (define_expand "neg<mode>2"
7042 [(set (match_operand:BFP 0 "register_operand" "=f")
7043 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7044 (clobber (reg:CC CC_REGNUM))])]
7048 ; lcxbr, lcdbr, lcebr
7049 (define_insn "*neg<mode>2_cc"
7050 [(set (reg CC_REGNUM)
7051 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7052 (match_operand:BFP 2 "const0_operand" "")))
7053 (set (match_operand:BFP 0 "register_operand" "=f")
7054 (neg:BFP (match_dup 1)))]
7055 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7057 [(set_attr "op_type" "RRE")
7058 (set_attr "type" "fsimp<mode>")])
7060 ; lcxbr, lcdbr, lcebr
7061 (define_insn "*neg<mode>2_cconly"
7062 [(set (reg CC_REGNUM)
7063 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7064 (match_operand:BFP 2 "const0_operand" "")))
7065 (clobber (match_scratch:BFP 0 "=f"))]
7066 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7068 [(set_attr "op_type" "RRE")
7069 (set_attr "type" "fsimp<mode>")])
7072 (define_insn "*neg<mode>2_nocc"
7073 [(set (match_operand:FP 0 "register_operand" "=f")
7074 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7077 [(set_attr "op_type" "RRE")
7078 (set_attr "type" "fsimp<mode>")])
7080 ; lcxbr, lcdbr, lcebr
7081 (define_insn "*neg<mode>2"
7082 [(set (match_operand:BFP 0 "register_operand" "=f")
7083 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7084 (clobber (reg:CC CC_REGNUM))]
7087 [(set_attr "op_type" "RRE")
7088 (set_attr "type" "fsimp<mode>")])
7092 ;;- Absolute value instructions.
7096 ; abs(di|si)2 instruction pattern(s).
7099 (define_insn "*absdi2_sign_cc"
7100 [(set (reg CC_REGNUM)
7101 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7102 (match_operand:SI 1 "register_operand" "d") 0)
7103 (const_int 32)) (const_int 32)))
7105 (set (match_operand:DI 0 "register_operand" "=d")
7106 (abs:DI (sign_extend:DI (match_dup 1))))]
7107 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7109 [(set_attr "op_type" "RRE")
7110 (set_attr "z10prop" "z10_c")])
7112 (define_insn "*absdi2_sign"
7113 [(set (match_operand:DI 0 "register_operand" "=d")
7114 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7115 (clobber (reg:CC CC_REGNUM))]
7118 [(set_attr "op_type" "RRE")
7119 (set_attr "z10prop" "z10_c")])
7122 (define_insn "*abs<mode>2_cc"
7123 [(set (reg CC_REGNUM)
7124 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7126 (set (match_operand:GPR 0 "register_operand" "=d")
7127 (abs:GPR (match_dup 1)))]
7128 "s390_match_ccmode (insn, CCAmode)"
7130 [(set_attr "op_type" "RR<E>")
7131 (set_attr "z10prop" "z10_c")])
7134 (define_insn "*abs<mode>2_cconly"
7135 [(set (reg CC_REGNUM)
7136 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7138 (clobber (match_scratch:GPR 0 "=d"))]
7139 "s390_match_ccmode (insn, CCAmode)"
7141 [(set_attr "op_type" "RR<E>")
7142 (set_attr "z10prop" "z10_c")])
7145 (define_insn "abs<mode>2"
7146 [(set (match_operand:GPR 0 "register_operand" "=d")
7147 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7148 (clobber (reg:CC CC_REGNUM))]
7151 [(set_attr "op_type" "RR<E>")
7152 (set_attr "z10prop" "z10_c")])
7155 ; abs(df|sf)2 instruction pattern(s).
7158 (define_expand "abs<mode>2"
7160 [(set (match_operand:BFP 0 "register_operand" "=f")
7161 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7162 (clobber (reg:CC CC_REGNUM))])]
7166 ; lpxbr, lpdbr, lpebr
7167 (define_insn "*abs<mode>2_cc"
7168 [(set (reg CC_REGNUM)
7169 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7170 (match_operand:BFP 2 "const0_operand" "")))
7171 (set (match_operand:BFP 0 "register_operand" "=f")
7172 (abs:BFP (match_dup 1)))]
7173 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7175 [(set_attr "op_type" "RRE")
7176 (set_attr "type" "fsimp<mode>")])
7178 ; lpxbr, lpdbr, lpebr
7179 (define_insn "*abs<mode>2_cconly"
7180 [(set (reg CC_REGNUM)
7181 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7182 (match_operand:BFP 2 "const0_operand" "")))
7183 (clobber (match_scratch:BFP 0 "=f"))]
7184 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7186 [(set_attr "op_type" "RRE")
7187 (set_attr "type" "fsimp<mode>")])
7190 (define_insn "*abs<mode>2_nocc"
7191 [(set (match_operand:FP 0 "register_operand" "=f")
7192 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7195 [(set_attr "op_type" "RRE")
7196 (set_attr "type" "fsimp<mode>")])
7198 ; lpxbr, lpdbr, lpebr
7199 (define_insn "*abs<mode>2"
7200 [(set (match_operand:BFP 0 "register_operand" "=f")
7201 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7202 (clobber (reg:CC CC_REGNUM))]
7205 [(set_attr "op_type" "RRE")
7206 (set_attr "type" "fsimp<mode>")])
7210 ;;- Negated absolute value instructions
7217 (define_insn "*negabsdi2_sign_cc"
7218 [(set (reg CC_REGNUM)
7219 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7220 (match_operand:SI 1 "register_operand" "d") 0)
7221 (const_int 32)) (const_int 32))))
7223 (set (match_operand:DI 0 "register_operand" "=d")
7224 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7225 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7227 [(set_attr "op_type" "RRE")
7228 (set_attr "z10prop" "z10_c")])
7230 (define_insn "*negabsdi2_sign"
7231 [(set (match_operand:DI 0 "register_operand" "=d")
7232 (neg:DI (abs:DI (sign_extend:DI
7233 (match_operand:SI 1 "register_operand" "d")))))
7234 (clobber (reg:CC CC_REGNUM))]
7237 [(set_attr "op_type" "RRE")
7238 (set_attr "z10prop" "z10_c")])
7241 (define_insn "*negabs<mode>2_cc"
7242 [(set (reg CC_REGNUM)
7243 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7245 (set (match_operand:GPR 0 "register_operand" "=d")
7246 (neg:GPR (abs:GPR (match_dup 1))))]
7247 "s390_match_ccmode (insn, CCAmode)"
7249 [(set_attr "op_type" "RR<E>")
7250 (set_attr "z10prop" "z10_c")])
7253 (define_insn "*negabs<mode>2_cconly"
7254 [(set (reg CC_REGNUM)
7255 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7257 (clobber (match_scratch:GPR 0 "=d"))]
7258 "s390_match_ccmode (insn, CCAmode)"
7260 [(set_attr "op_type" "RR<E>")
7261 (set_attr "z10prop" "z10_c")])
7264 (define_insn "*negabs<mode>2"
7265 [(set (match_operand:GPR 0 "register_operand" "=d")
7266 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7267 (clobber (reg:CC CC_REGNUM))]
7270 [(set_attr "op_type" "RR<E>")
7271 (set_attr "z10prop" "z10_c")])
7277 ; lnxbr, lndbr, lnebr
7278 (define_insn "*negabs<mode>2_cc"
7279 [(set (reg CC_REGNUM)
7280 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7281 (match_operand:BFP 2 "const0_operand" "")))
7282 (set (match_operand:BFP 0 "register_operand" "=f")
7283 (neg:BFP (abs:BFP (match_dup 1))))]
7284 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7286 [(set_attr "op_type" "RRE")
7287 (set_attr "type" "fsimp<mode>")])
7289 ; lnxbr, lndbr, lnebr
7290 (define_insn "*negabs<mode>2_cconly"
7291 [(set (reg CC_REGNUM)
7292 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7293 (match_operand:BFP 2 "const0_operand" "")))
7294 (clobber (match_scratch:BFP 0 "=f"))]
7295 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7297 [(set_attr "op_type" "RRE")
7298 (set_attr "type" "fsimp<mode>")])
7301 (define_insn "*negabs<mode>2_nocc"
7302 [(set (match_operand:FP 0 "register_operand" "=f")
7303 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7306 [(set_attr "op_type" "RRE")
7307 (set_attr "type" "fsimp<mode>")])
7309 ; lnxbr, lndbr, lnebr
7310 (define_insn "*negabs<mode>2"
7311 [(set (match_operand:BFP 0 "register_operand" "=f")
7312 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7313 (clobber (reg:CC CC_REGNUM))]
7316 [(set_attr "op_type" "RRE")
7317 (set_attr "type" "fsimp<mode>")])
7320 ;;- Square root instructions.
7324 ; sqrt(df|sf)2 instruction pattern(s).
7327 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7328 (define_insn "sqrt<mode>2"
7329 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7330 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7335 [(set_attr "op_type" "RRE,RXE")
7336 (set_attr "type" "fsqrt<mode>")])
7340 ;;- One complement instructions.
7344 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7347 (define_expand "one_cmpl<mode>2"
7349 [(set (match_operand:INT 0 "register_operand" "")
7350 (xor:INT (match_operand:INT 1 "register_operand" "")
7352 (clobber (reg:CC CC_REGNUM))])]
7358 ;; Find leftmost bit instructions.
7361 (define_expand "clzdi2"
7362 [(set (match_operand:DI 0 "register_operand" "=d")
7363 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7364 "TARGET_EXTIMM && TARGET_ZARCH"
7366 rtx insn, clz_equal;
7367 rtx wide_reg = gen_reg_rtx (TImode);
7368 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7370 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7372 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7374 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7375 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7380 (define_insn "clztidi2"
7381 [(set (match_operand:TI 0 "register_operand" "=d")
7385 (xor:DI (match_operand:DI 1 "register_operand" "d")
7386 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7387 (subreg:SI (clz:DI (match_dup 1)) 4))))
7390 (zero_extend:TI (clz:DI (match_dup 1)))))
7391 (clobber (reg:CC CC_REGNUM))]
7392 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7393 == (unsigned HOST_WIDE_INT) 1 << 63
7394 && TARGET_EXTIMM && TARGET_ZARCH"
7396 [(set_attr "op_type" "RRE")])
7400 ;;- Rotate instructions.
7404 ; rotl(di|si)3 instruction pattern(s).
7408 (define_insn "rotl<mode>3"
7409 [(set (match_operand:GPR 0 "register_operand" "=d")
7410 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7411 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7414 [(set_attr "op_type" "RSE")
7415 (set_attr "atype" "reg")
7416 (set_attr "z10prop" "z10_super_E1")])
7419 (define_insn "*rotl<mode>3_and"
7420 [(set (match_operand:GPR 0 "register_operand" "=d")
7421 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7422 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7423 (match_operand:SI 3 "const_int_operand" "n"))))]
7424 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7426 [(set_attr "op_type" "RSE")
7427 (set_attr "atype" "reg")
7428 (set_attr "z10prop" "z10_super_E1")])
7432 ;;- Shift instructions.
7436 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7437 ; Left shifts and logical right shifts
7439 (define_expand "<shift><mode>3"
7440 [(set (match_operand:DSI 0 "register_operand" "")
7441 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7442 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7447 (define_insn "*<shift>di3_31"
7448 [(set (match_operand:DI 0 "register_operand" "=d")
7449 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7450 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7453 [(set_attr "op_type" "RS")
7454 (set_attr "atype" "reg")
7455 (set_attr "z196prop" "z196_cracked")])
7457 ; sll, srl, sllg, srlg, sllk, srlk
7458 (define_insn "*<shift><mode>3"
7459 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7460 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7461 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7464 s<lr>l<g>\t%0,<1>%Y2
7465 s<lr>l<gk>\t%0,%1,%Y2"
7466 [(set_attr "op_type" "RS<E>,RSY")
7467 (set_attr "atype" "reg,reg")
7468 (set_attr "cpu_facility" "*,z196")
7469 (set_attr "z10prop" "z10_super_E1,*")])
7472 (define_insn "*<shift>di3_31_and"
7473 [(set (match_operand:DI 0 "register_operand" "=d")
7474 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7475 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7476 (match_operand:SI 3 "const_int_operand" "n"))))]
7477 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7479 [(set_attr "op_type" "RS")
7480 (set_attr "atype" "reg")])
7482 ; sll, srl, sllg, srlg, sllk, srlk
7483 (define_insn "*<shift><mode>3_and"
7484 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7485 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7486 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7487 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7488 "(INTVAL (operands[3]) & 63) == 63"
7490 s<lr>l<g>\t%0,<1>%Y2
7491 s<lr>l<gk>\t%0,%1,%Y2"
7492 [(set_attr "op_type" "RS<E>,RSY")
7493 (set_attr "atype" "reg,reg")
7494 (set_attr "cpu_facility" "*,z196")
7495 (set_attr "z10prop" "z10_super_E1,*")])
7498 ; ashr(di|si)3 instruction pattern(s).
7499 ; Arithmetic right shifts
7501 (define_expand "ashr<mode>3"
7503 [(set (match_operand:DSI 0 "register_operand" "")
7504 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7505 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7506 (clobber (reg:CC CC_REGNUM))])]
7510 (define_insn "*ashrdi3_cc_31"
7511 [(set (reg CC_REGNUM)
7512 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7513 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7515 (set (match_operand:DI 0 "register_operand" "=d")
7516 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7517 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7519 [(set_attr "op_type" "RS")
7520 (set_attr "atype" "reg")])
7522 (define_insn "*ashrdi3_cconly_31"
7523 [(set (reg CC_REGNUM)
7524 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7525 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7527 (clobber (match_scratch:DI 0 "=d"))]
7528 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7530 [(set_attr "op_type" "RS")
7531 (set_attr "atype" "reg")])
7533 (define_insn "*ashrdi3_31"
7534 [(set (match_operand:DI 0 "register_operand" "=d")
7535 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7536 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7537 (clobber (reg:CC CC_REGNUM))]
7540 [(set_attr "op_type" "RS")
7541 (set_attr "atype" "reg")])
7544 (define_insn "*ashr<mode>3_cc"
7545 [(set (reg CC_REGNUM)
7546 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7547 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7549 (set (match_operand:GPR 0 "register_operand" "=d,d")
7550 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7551 "s390_match_ccmode(insn, CCSmode)"
7555 [(set_attr "op_type" "RS<E>,RSY")
7556 (set_attr "atype" "reg,reg")
7557 (set_attr "cpu_facility" "*,z196")
7558 (set_attr "z10prop" "z10_super_E1,*")])
7561 (define_insn "*ashr<mode>3_cconly"
7562 [(set (reg CC_REGNUM)
7563 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7564 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7566 (clobber (match_scratch:GPR 0 "=d,d"))]
7567 "s390_match_ccmode(insn, CCSmode)"
7571 [(set_attr "op_type" "RS<E>,RSY")
7572 (set_attr "atype" "reg,reg")
7573 (set_attr "cpu_facility" "*,z196")
7574 (set_attr "z10prop" "z10_super_E1,*")])
7577 (define_insn "*ashr<mode>3"
7578 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7579 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7580 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7581 (clobber (reg:CC CC_REGNUM))]
7586 [(set_attr "op_type" "RS<E>,RSY")
7587 (set_attr "atype" "reg,reg")
7588 (set_attr "cpu_facility" "*,z196")
7589 (set_attr "z10prop" "z10_super_E1,*")])
7592 ; shift pattern with implicit ANDs
7594 (define_insn "*ashrdi3_cc_31_and"
7595 [(set (reg CC_REGNUM)
7596 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7597 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7598 (match_operand:SI 3 "const_int_operand" "n")))
7600 (set (match_operand:DI 0 "register_operand" "=d")
7601 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7602 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7603 && (INTVAL (operands[3]) & 63) == 63"
7605 [(set_attr "op_type" "RS")
7606 (set_attr "atype" "reg")])
7608 (define_insn "*ashrdi3_cconly_31_and"
7609 [(set (reg CC_REGNUM)
7610 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7611 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7612 (match_operand:SI 3 "const_int_operand" "n")))
7614 (clobber (match_scratch:DI 0 "=d"))]
7615 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7616 && (INTVAL (operands[3]) & 63) == 63"
7618 [(set_attr "op_type" "RS")
7619 (set_attr "atype" "reg")])
7621 (define_insn "*ashrdi3_31_and"
7622 [(set (match_operand:DI 0 "register_operand" "=d")
7623 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7624 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7625 (match_operand:SI 3 "const_int_operand" "n"))))
7626 (clobber (reg:CC CC_REGNUM))]
7627 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7629 [(set_attr "op_type" "RS")
7630 (set_attr "atype" "reg")])
7633 (define_insn "*ashr<mode>3_cc_and"
7634 [(set (reg CC_REGNUM)
7635 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7636 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7637 (match_operand:SI 3 "const_int_operand" "n,n")))
7639 (set (match_operand:GPR 0 "register_operand" "=d,d")
7640 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7641 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7645 [(set_attr "op_type" "RS<E>,RSY")
7646 (set_attr "atype" "reg,reg")
7647 (set_attr "cpu_facility" "*,z196")
7648 (set_attr "z10prop" "z10_super_E1,*")])
7651 (define_insn "*ashr<mode>3_cconly_and"
7652 [(set (reg CC_REGNUM)
7653 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7654 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7655 (match_operand:SI 3 "const_int_operand" "n,n")))
7657 (clobber (match_scratch:GPR 0 "=d,d"))]
7658 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7662 [(set_attr "op_type" "RS<E>,RSY")
7663 (set_attr "atype" "reg,reg")
7664 (set_attr "cpu_facility" "*,z196")
7665 (set_attr "z10prop" "z10_super_E1,*")])
7668 (define_insn "*ashr<mode>3_and"
7669 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7670 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7671 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7672 (match_operand:SI 3 "const_int_operand" "n,n"))))
7673 (clobber (reg:CC CC_REGNUM))]
7674 "(INTVAL (operands[3]) & 63) == 63"
7678 [(set_attr "op_type" "RS<E>,RSY")
7679 (set_attr "atype" "reg,reg")
7680 (set_attr "cpu_facility" "*,z196")
7681 (set_attr "z10prop" "z10_super_E1,*")])
7685 ;; Branch instruction patterns.
7688 (define_expand "cbranch<mode>4"
7690 (if_then_else (match_operator 0 "comparison_operator"
7691 [(match_operand:GPR 1 "register_operand" "")
7692 (match_operand:GPR 2 "general_operand" "")])
7693 (label_ref (match_operand 3 "" ""))
7696 "s390_emit_jump (operands[3],
7697 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7700 (define_expand "cbranch<mode>4"
7702 (if_then_else (match_operator 0 "comparison_operator"
7703 [(match_operand:FP 1 "register_operand" "")
7704 (match_operand:FP 2 "general_operand" "")])
7705 (label_ref (match_operand 3 "" ""))
7708 "s390_emit_jump (operands[3],
7709 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7712 (define_expand "cbranchcc4"
7714 (if_then_else (match_operator 0 "s390_eqne_operator"
7715 [(match_operand 1 "cc_reg_operand" "")
7716 (match_operand 2 "const0_operand" "")])
7717 (label_ref (match_operand 3 "" ""))
7720 "s390_emit_jump (operands[3],
7721 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7727 ;;- Conditional jump instructions.
7730 (define_insn "*cjump_64"
7733 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7734 (label_ref (match_operand 0 "" ""))
7738 if (get_attr_length (insn) == 4)
7741 return "jg%C1\t%l0";
7743 [(set_attr "op_type" "RI")
7744 (set_attr "type" "branch")
7745 (set (attr "length")
7746 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7747 (const_int 4) (const_int 6)))])
7749 (define_insn "*cjump_31"
7752 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7753 (label_ref (match_operand 0 "" ""))
7757 gcc_assert (get_attr_length (insn) == 4);
7760 [(set_attr "op_type" "RI")
7761 (set_attr "type" "branch")
7762 (set (attr "length")
7763 (if_then_else (not (match_test "flag_pic"))
7764 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7765 (const_int 4) (const_int 6))
7766 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7767 (const_int 4) (const_int 8))))])
7769 (define_insn "*cjump_long"
7772 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7773 (match_operand 0 "address_operand" "ZQZR")
7777 if (get_attr_op_type (insn) == OP_TYPE_RR)
7782 [(set (attr "op_type")
7783 (if_then_else (match_operand 0 "register_operand" "")
7784 (const_string "RR") (const_string "RX")))
7785 (set_attr "type" "branch")
7786 (set_attr "atype" "agen")])
7790 ;;- Negated conditional jump instructions.
7793 (define_insn "*icjump_64"
7796 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7798 (label_ref (match_operand 0 "" ""))))]
7801 if (get_attr_length (insn) == 4)
7804 return "jg%D1\t%l0";
7806 [(set_attr "op_type" "RI")
7807 (set_attr "type" "branch")
7808 (set (attr "length")
7809 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7810 (const_int 4) (const_int 6)))])
7812 (define_insn "*icjump_31"
7815 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7817 (label_ref (match_operand 0 "" ""))))]
7820 gcc_assert (get_attr_length (insn) == 4);
7823 [(set_attr "op_type" "RI")
7824 (set_attr "type" "branch")
7825 (set (attr "length")
7826 (if_then_else (not (match_test "flag_pic"))
7827 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7828 (const_int 4) (const_int 6))
7829 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7830 (const_int 4) (const_int 8))))])
7832 (define_insn "*icjump_long"
7835 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7837 (match_operand 0 "address_operand" "ZQZR")))]
7840 if (get_attr_op_type (insn) == OP_TYPE_RR)
7845 [(set (attr "op_type")
7846 (if_then_else (match_operand 0 "register_operand" "")
7847 (const_string "RR") (const_string "RX")))
7848 (set_attr "type" "branch")
7849 (set_attr "atype" "agen")])
7852 ;;- Trap instructions.
7856 [(trap_if (const_int 1) (const_int 0))]
7859 [(set_attr "op_type" "RI")
7860 (set_attr "type" "branch")])
7862 (define_expand "ctrap<mode>4"
7863 [(trap_if (match_operator 0 "comparison_operator"
7864 [(match_operand:GPR 1 "register_operand" "")
7865 (match_operand:GPR 2 "general_operand" "")])
7866 (match_operand 3 "const0_operand" ""))]
7869 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7870 operands[1], operands[2]);
7871 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7875 (define_expand "ctrap<mode>4"
7876 [(trap_if (match_operator 0 "comparison_operator"
7877 [(match_operand:FP 1 "register_operand" "")
7878 (match_operand:FP 2 "general_operand" "")])
7879 (match_operand 3 "const0_operand" ""))]
7882 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7883 operands[1], operands[2]);
7884 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7888 (define_insn "condtrap"
7889 [(trap_if (match_operator 0 "s390_comparison"
7890 [(match_operand 1 "cc_reg_operand" "c")
7895 [(set_attr "op_type" "RI")
7896 (set_attr "type" "branch")])
7898 ; crt, cgrt, cit, cgit
7899 (define_insn "*cmp_and_trap_signed_int<mode>"
7900 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7901 [(match_operand:GPR 1 "register_operand" "d,d")
7902 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7908 [(set_attr "op_type" "RRF,RIE")
7909 (set_attr "type" "branch")
7910 (set_attr "z10prop" "z10_super_c,z10_super")])
7912 ; clrt, clgrt, clfit, clgit, clt, clgt
7913 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7914 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7915 [(match_operand:GPR 1 "register_operand" "d,d, d")
7916 (match_operand:GPR 2 "general_operand" "d,D,RT")])
7923 [(set_attr "op_type" "RRF,RIE,RSY")
7924 (set_attr "type" "branch")
7925 (set_attr "z10prop" "z10_super_c,z10_super,*")
7926 (set_attr "cpu_facility" "z10,z10,zEC12")])
7929 (define_insn "*load_and_trap<mode>"
7930 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
7933 (set (match_operand:GPR 1 "register_operand" "=d")
7937 [(set_attr "op_type" "RXY")])
7941 ;;- Loop instructions.
7943 ;; This is all complicated by the fact that since this is a jump insn
7944 ;; we must handle our own output reloads.
7948 ; This splitter will be matched by combine and has to add the 2 moves
7949 ; necessary to load the compare and the increment values into a
7950 ; register pair as needed by brxle.
7952 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7955 (match_operator 6 "s390_brx_operator"
7956 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
7957 (match_operand:GPR 2 "general_operand" ""))
7958 (match_operand:GPR 3 "register_operand" "")])
7959 (label_ref (match_operand 0 "" ""))
7961 (set (match_operand:GPR 4 "nonimmediate_operand" "")
7962 (plus:GPR (match_dup 1) (match_dup 2)))
7963 (clobber (match_scratch:GPR 5 ""))]
7966 "!reload_completed && !reload_in_progress"
7967 [(set (match_dup 7) (match_dup 2)) ; the increment
7968 (set (match_dup 8) (match_dup 3)) ; the comparison value
7969 (parallel [(set (pc)
7972 [(plus:GPR (match_dup 1) (match_dup 7))
7974 (label_ref (match_dup 0))
7977 (plus:GPR (match_dup 1) (match_dup 7)))
7978 (clobber (match_dup 5))
7979 (clobber (reg:CC CC_REGNUM))])]
7981 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
7982 operands[7] = gen_lowpart (<GPR:MODE>mode,
7983 gen_highpart (word_mode, dreg));
7984 operands[8] = gen_lowpart (<GPR:MODE>mode,
7985 gen_lowpart (word_mode, dreg));
7990 (define_insn_and_split "*brxg_64bit"
7993 (match_operator 5 "s390_brx_operator"
7994 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
7995 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
7996 (subreg:DI (match_dup 2) 8)])
7997 (label_ref (match_operand 0 "" ""))
7999 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8000 (plus:DI (match_dup 1)
8001 (subreg:DI (match_dup 2) 0)))
8002 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8003 (clobber (reg:CC CC_REGNUM))]
8006 if (which_alternative != 0)
8008 else if (get_attr_length (insn) == 6)
8009 return "brx%E5g\t%1,%2,%l0";
8011 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8013 "&& reload_completed
8014 && (!REG_P (operands[3])
8015 || !rtx_equal_p (operands[1], operands[3]))"
8016 [(set (match_dup 4) (match_dup 1))
8017 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8018 (clobber (reg:CC CC_REGNUM))])
8019 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8020 (set (match_dup 3) (match_dup 4))
8021 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8022 (label_ref (match_dup 0))
8025 [(set_attr "op_type" "RIE")
8026 (set_attr "type" "branch")
8027 (set (attr "length")
8028 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8029 (const_int 6) (const_int 16)))])
8033 (define_insn_and_split "*brx_64bit"
8036 (match_operator 5 "s390_brx_operator"
8037 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8038 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8039 (subreg:SI (match_dup 2) 12)])
8040 (label_ref (match_operand 0 "" ""))
8042 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8043 (plus:SI (match_dup 1)
8044 (subreg:SI (match_dup 2) 4)))
8045 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8046 (clobber (reg:CC CC_REGNUM))]
8049 if (which_alternative != 0)
8051 else if (get_attr_length (insn) == 6)
8052 return "brx%C5\t%1,%2,%l0";
8054 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8056 "&& reload_completed
8057 && (!REG_P (operands[3])
8058 || !rtx_equal_p (operands[1], operands[3]))"
8059 [(set (match_dup 4) (match_dup 1))
8060 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8061 (clobber (reg:CC CC_REGNUM))])
8062 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8063 (set (match_dup 3) (match_dup 4))
8064 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8065 (label_ref (match_dup 0))
8068 [(set_attr "op_type" "RSI")
8069 (set_attr "type" "branch")
8070 (set (attr "length")
8071 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8072 (const_int 6) (const_int 14)))])
8076 (define_insn_and_split "*brx_31bit"
8079 (match_operator 5 "s390_brx_operator"
8080 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8081 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8082 (subreg:SI (match_dup 2) 4)])
8083 (label_ref (match_operand 0 "" ""))
8085 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8086 (plus:SI (match_dup 1)
8087 (subreg:SI (match_dup 2) 0)))
8088 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8089 (clobber (reg:CC CC_REGNUM))]
8090 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8092 if (which_alternative != 0)
8094 else if (get_attr_length (insn) == 6)
8095 return "brx%C5\t%1,%2,%l0";
8097 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8099 "&& reload_completed
8100 && (!REG_P (operands[3])
8101 || !rtx_equal_p (operands[1], operands[3]))"
8102 [(set (match_dup 4) (match_dup 1))
8103 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8104 (clobber (reg:CC CC_REGNUM))])
8105 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8106 (set (match_dup 3) (match_dup 4))
8107 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8108 (label_ref (match_dup 0))
8111 [(set_attr "op_type" "RSI")
8112 (set_attr "type" "branch")
8113 (set (attr "length")
8114 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8115 (const_int 6) (const_int 14)))])
8120 (define_expand "doloop_end"
8121 [(use (match_operand 0 "" "")) ; loop pseudo
8122 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8123 (use (match_operand 2 "" "")) ; max iterations
8124 (use (match_operand 3 "" "")) ; loop level
8125 (use (match_operand 4 "" "")) ; label
8126 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
8129 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8130 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8131 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8132 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8133 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8134 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8141 (define_insn_and_split "doloop_si64"
8144 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8146 (label_ref (match_operand 0 "" ""))
8148 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8149 (plus:SI (match_dup 1) (const_int -1)))
8150 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8151 (clobber (reg:CC CC_REGNUM))]
8154 if (which_alternative != 0)
8156 else if (get_attr_length (insn) == 4)
8157 return "brct\t%1,%l0";
8159 return "ahi\t%1,-1\;jgne\t%l0";
8161 "&& reload_completed
8162 && (! REG_P (operands[2])
8163 || ! rtx_equal_p (operands[1], operands[2]))"
8164 [(set (match_dup 3) (match_dup 1))
8165 (parallel [(set (reg:CCAN CC_REGNUM)
8166 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8168 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8169 (set (match_dup 2) (match_dup 3))
8170 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8171 (label_ref (match_dup 0))
8174 [(set_attr "op_type" "RI")
8175 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8176 ; hurt us in the (rare) case of ahi.
8177 (set_attr "z10prop" "z10_super_E1")
8178 (set_attr "type" "branch")
8179 (set (attr "length")
8180 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8181 (const_int 4) (const_int 10)))])
8183 (define_insn_and_split "doloop_si31"
8186 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8188 (label_ref (match_operand 0 "" ""))
8190 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8191 (plus:SI (match_dup 1) (const_int -1)))
8192 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8193 (clobber (reg:CC CC_REGNUM))]
8196 if (which_alternative != 0)
8198 else if (get_attr_length (insn) == 4)
8199 return "brct\t%1,%l0";
8203 "&& reload_completed
8204 && (! REG_P (operands[2])
8205 || ! rtx_equal_p (operands[1], operands[2]))"
8206 [(set (match_dup 3) (match_dup 1))
8207 (parallel [(set (reg:CCAN CC_REGNUM)
8208 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8210 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8211 (set (match_dup 2) (match_dup 3))
8212 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8213 (label_ref (match_dup 0))
8216 [(set_attr "op_type" "RI")
8217 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8218 ; hurt us in the (rare) case of ahi.
8219 (set_attr "z10prop" "z10_super_E1")
8220 (set_attr "type" "branch")
8221 (set (attr "length")
8222 (if_then_else (not (match_test "flag_pic"))
8223 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8224 (const_int 4) (const_int 6))
8225 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8226 (const_int 4) (const_int 8))))])
8228 (define_insn "*doloop_si_long"
8231 (ne (match_operand:SI 1 "register_operand" "d")
8233 (match_operand 0 "address_operand" "ZQZR")
8235 (set (match_operand:SI 2 "register_operand" "=1")
8236 (plus:SI (match_dup 1) (const_int -1)))
8237 (clobber (match_scratch:SI 3 "=X"))
8238 (clobber (reg:CC CC_REGNUM))]
8241 if (get_attr_op_type (insn) == OP_TYPE_RR)
8242 return "bctr\t%1,%0";
8244 return "bct\t%1,%a0";
8246 [(set (attr "op_type")
8247 (if_then_else (match_operand 0 "register_operand" "")
8248 (const_string "RR") (const_string "RX")))
8249 (set_attr "type" "branch")
8250 (set_attr "atype" "agen")
8251 (set_attr "z10prop" "z10_c")
8252 (set_attr "z196prop" "z196_cracked")])
8254 (define_insn_and_split "doloop_di"
8257 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8259 (label_ref (match_operand 0 "" ""))
8261 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8262 (plus:DI (match_dup 1) (const_int -1)))
8263 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8264 (clobber (reg:CC CC_REGNUM))]
8267 if (which_alternative != 0)
8269 else if (get_attr_length (insn) == 4)
8270 return "brctg\t%1,%l0";
8272 return "aghi\t%1,-1\;jgne\t%l0";
8274 "&& reload_completed
8275 && (! REG_P (operands[2])
8276 || ! rtx_equal_p (operands[1], operands[2]))"
8277 [(set (match_dup 3) (match_dup 1))
8278 (parallel [(set (reg:CCAN CC_REGNUM)
8279 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8281 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8282 (set (match_dup 2) (match_dup 3))
8283 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8284 (label_ref (match_dup 0))
8287 [(set_attr "op_type" "RI")
8288 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8289 ; hurt us in the (rare) case of ahi.
8290 (set_attr "z10prop" "z10_super_E1")
8291 (set_attr "type" "branch")
8292 (set (attr "length")
8293 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8294 (const_int 4) (const_int 10)))])
8297 ;;- Unconditional jump instructions.
8301 ; jump instruction pattern(s).
8304 (define_expand "jump"
8305 [(match_operand 0 "" "")]
8307 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8309 (define_insn "*jump64"
8310 [(set (pc) (label_ref (match_operand 0 "" "")))]
8313 if (get_attr_length (insn) == 4)
8318 [(set_attr "op_type" "RI")
8319 (set_attr "type" "branch")
8320 (set (attr "length")
8321 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8322 (const_int 4) (const_int 6)))])
8324 (define_insn "*jump31"
8325 [(set (pc) (label_ref (match_operand 0 "" "")))]
8328 gcc_assert (get_attr_length (insn) == 4);
8331 [(set_attr "op_type" "RI")
8332 (set_attr "type" "branch")
8333 (set (attr "length")
8334 (if_then_else (not (match_test "flag_pic"))
8335 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8336 (const_int 4) (const_int 6))
8337 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8338 (const_int 4) (const_int 8))))])
8341 ; indirect-jump instruction pattern(s).
8344 (define_insn "indirect_jump"
8345 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8348 if (get_attr_op_type (insn) == OP_TYPE_RR)
8353 [(set (attr "op_type")
8354 (if_then_else (match_operand 0 "register_operand" "")
8355 (const_string "RR") (const_string "RX")))
8356 (set_attr "type" "branch")
8357 (set_attr "atype" "agen")])
8360 ; casesi instruction pattern(s).
8363 (define_insn "casesi_jump"
8364 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8365 (use (label_ref (match_operand 1 "" "")))]
8368 if (get_attr_op_type (insn) == OP_TYPE_RR)
8373 [(set (attr "op_type")
8374 (if_then_else (match_operand 0 "register_operand" "")
8375 (const_string "RR") (const_string "RX")))
8376 (set_attr "type" "branch")
8377 (set_attr "atype" "agen")])
8379 (define_expand "casesi"
8380 [(match_operand:SI 0 "general_operand" "")
8381 (match_operand:SI 1 "general_operand" "")
8382 (match_operand:SI 2 "general_operand" "")
8383 (label_ref (match_operand 3 "" ""))
8384 (label_ref (match_operand 4 "" ""))]
8387 rtx index = gen_reg_rtx (SImode);
8388 rtx base = gen_reg_rtx (Pmode);
8389 rtx target = gen_reg_rtx (Pmode);
8391 emit_move_insn (index, operands[0]);
8392 emit_insn (gen_subsi3 (index, index, operands[1]));
8393 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8396 if (Pmode != SImode)
8397 index = convert_to_mode (Pmode, index, 1);
8398 if (GET_CODE (index) != REG)
8399 index = copy_to_mode_reg (Pmode, index);
8402 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8404 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8406 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8408 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8409 emit_move_insn (target, index);
8412 target = gen_rtx_PLUS (Pmode, base, target);
8413 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8420 ;;- Jump to subroutine.
8425 ; untyped call instruction pattern(s).
8428 ;; Call subroutine returning any type.
8429 (define_expand "untyped_call"
8430 [(parallel [(call (match_operand 0 "" "")
8432 (match_operand 1 "" "")
8433 (match_operand 2 "" "")])]
8438 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8440 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8442 rtx set = XVECEXP (operands[2], 0, i);
8443 emit_move_insn (SET_DEST (set), SET_SRC (set));
8446 /* The optimizer does not know that the call sets the function value
8447 registers we stored in the result block. We avoid problems by
8448 claiming that all hard registers are used and clobbered at this
8450 emit_insn (gen_blockage ());
8455 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8456 ;; all of memory. This blocks insns from being moved across this point.
8458 (define_insn "blockage"
8459 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8462 [(set_attr "type" "none")
8463 (set_attr "length" "0")])
8469 (define_expand "sibcall"
8470 [(call (match_operand 0 "" "")
8471 (match_operand 1 "" ""))]
8474 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8478 (define_insn "*sibcall_br"
8479 [(call (mem:QI (reg SIBCALL_REGNUM))
8480 (match_operand 0 "const_int_operand" "n"))]
8481 "SIBLING_CALL_P (insn)
8482 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8484 [(set_attr "op_type" "RR")
8485 (set_attr "type" "branch")
8486 (set_attr "atype" "agen")])
8488 (define_insn "*sibcall_brc"
8489 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8490 (match_operand 1 "const_int_operand" "n"))]
8491 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8493 [(set_attr "op_type" "RI")
8494 (set_attr "type" "branch")])
8496 (define_insn "*sibcall_brcl"
8497 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8498 (match_operand 1 "const_int_operand" "n"))]
8499 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8501 [(set_attr "op_type" "RIL")
8502 (set_attr "type" "branch")])
8505 ; sibcall_value patterns
8508 (define_expand "sibcall_value"
8509 [(set (match_operand 0 "" "")
8510 (call (match_operand 1 "" "")
8511 (match_operand 2 "" "")))]
8514 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8518 (define_insn "*sibcall_value_br"
8519 [(set (match_operand 0 "" "")
8520 (call (mem:QI (reg SIBCALL_REGNUM))
8521 (match_operand 1 "const_int_operand" "n")))]
8522 "SIBLING_CALL_P (insn)
8523 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8525 [(set_attr "op_type" "RR")
8526 (set_attr "type" "branch")
8527 (set_attr "atype" "agen")])
8529 (define_insn "*sibcall_value_brc"
8530 [(set (match_operand 0 "" "")
8531 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8532 (match_operand 2 "const_int_operand" "n")))]
8533 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8535 [(set_attr "op_type" "RI")
8536 (set_attr "type" "branch")])
8538 (define_insn "*sibcall_value_brcl"
8539 [(set (match_operand 0 "" "")
8540 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8541 (match_operand 2 "const_int_operand" "n")))]
8542 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8544 [(set_attr "op_type" "RIL")
8545 (set_attr "type" "branch")])
8549 ; call instruction pattern(s).
8552 (define_expand "call"
8553 [(call (match_operand 0 "" "")
8554 (match_operand 1 "" ""))
8555 (use (match_operand 2 "" ""))]
8558 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8559 gen_rtx_REG (Pmode, RETURN_REGNUM));
8563 (define_insn "*bras"
8564 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8565 (match_operand 1 "const_int_operand" "n"))
8566 (clobber (match_operand 2 "register_operand" "=r"))]
8567 "!SIBLING_CALL_P (insn)
8568 && TARGET_SMALL_EXEC
8569 && GET_MODE (operands[2]) == Pmode"
8571 [(set_attr "op_type" "RI")
8572 (set_attr "type" "jsr")
8573 (set_attr "z196prop" "z196_cracked")])
8575 (define_insn "*brasl"
8576 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8577 (match_operand 1 "const_int_operand" "n"))
8578 (clobber (match_operand 2 "register_operand" "=r"))]
8579 "!SIBLING_CALL_P (insn)
8581 && GET_MODE (operands[2]) == Pmode"
8583 [(set_attr "op_type" "RIL")
8584 (set_attr "type" "jsr")
8585 (set_attr "z196prop" "z196_cracked")])
8587 (define_insn "*basr"
8588 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8589 (match_operand 1 "const_int_operand" "n"))
8590 (clobber (match_operand 2 "register_operand" "=r"))]
8591 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8593 if (get_attr_op_type (insn) == OP_TYPE_RR)
8594 return "basr\t%2,%0";
8596 return "bas\t%2,%a0";
8598 [(set (attr "op_type")
8599 (if_then_else (match_operand 0 "register_operand" "")
8600 (const_string "RR") (const_string "RX")))
8601 (set_attr "type" "jsr")
8602 (set_attr "atype" "agen")
8603 (set_attr "z196prop" "z196_cracked")])
8606 ; call_value instruction pattern(s).
8609 (define_expand "call_value"
8610 [(set (match_operand 0 "" "")
8611 (call (match_operand 1 "" "")
8612 (match_operand 2 "" "")))
8613 (use (match_operand 3 "" ""))]
8616 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8617 gen_rtx_REG (Pmode, RETURN_REGNUM));
8621 (define_insn "*bras_r"
8622 [(set (match_operand 0 "" "")
8623 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8624 (match_operand:SI 2 "const_int_operand" "n")))
8625 (clobber (match_operand 3 "register_operand" "=r"))]
8626 "!SIBLING_CALL_P (insn)
8627 && TARGET_SMALL_EXEC
8628 && GET_MODE (operands[3]) == Pmode"
8630 [(set_attr "op_type" "RI")
8631 (set_attr "type" "jsr")
8632 (set_attr "z196prop" "z196_cracked")])
8634 (define_insn "*brasl_r"
8635 [(set (match_operand 0 "" "")
8636 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8637 (match_operand 2 "const_int_operand" "n")))
8638 (clobber (match_operand 3 "register_operand" "=r"))]
8639 "!SIBLING_CALL_P (insn)
8641 && GET_MODE (operands[3]) == Pmode"
8643 [(set_attr "op_type" "RIL")
8644 (set_attr "type" "jsr")
8645 (set_attr "z196prop" "z196_cracked")])
8647 (define_insn "*basr_r"
8648 [(set (match_operand 0 "" "")
8649 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8650 (match_operand 2 "const_int_operand" "n")))
8651 (clobber (match_operand 3 "register_operand" "=r"))]
8652 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8654 if (get_attr_op_type (insn) == OP_TYPE_RR)
8655 return "basr\t%3,%1";
8657 return "bas\t%3,%a1";
8659 [(set (attr "op_type")
8660 (if_then_else (match_operand 1 "register_operand" "")
8661 (const_string "RR") (const_string "RX")))
8662 (set_attr "type" "jsr")
8663 (set_attr "atype" "agen")
8664 (set_attr "z196prop" "z196_cracked")])
8667 ;;- Thread-local storage support.
8670 (define_expand "get_thread_pointer<mode>"
8671 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8675 (define_expand "set_thread_pointer<mode>"
8676 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8677 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8681 (define_insn "*set_tp"
8682 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8685 [(set_attr "type" "none")
8686 (set_attr "length" "0")])
8688 (define_insn "*tls_load_64"
8689 [(set (match_operand:DI 0 "register_operand" "=d")
8690 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8691 (match_operand:DI 2 "" "")]
8695 [(set_attr "op_type" "RXE")
8696 (set_attr "z10prop" "z10_fwd_A3")])
8698 (define_insn "*tls_load_31"
8699 [(set (match_operand:SI 0 "register_operand" "=d,d")
8700 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8701 (match_operand:SI 2 "" "")]
8707 [(set_attr "op_type" "RX,RXY")
8708 (set_attr "type" "load")
8709 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8711 (define_insn "*bras_tls"
8712 [(set (match_operand 0 "" "")
8713 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8714 (match_operand 2 "const_int_operand" "n")))
8715 (clobber (match_operand 3 "register_operand" "=r"))
8716 (use (match_operand 4 "" ""))]
8717 "!SIBLING_CALL_P (insn)
8718 && TARGET_SMALL_EXEC
8719 && GET_MODE (operands[3]) == Pmode"
8721 [(set_attr "op_type" "RI")
8722 (set_attr "type" "jsr")
8723 (set_attr "z196prop" "z196_cracked")])
8725 (define_insn "*brasl_tls"
8726 [(set (match_operand 0 "" "")
8727 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8728 (match_operand 2 "const_int_operand" "n")))
8729 (clobber (match_operand 3 "register_operand" "=r"))
8730 (use (match_operand 4 "" ""))]
8731 "!SIBLING_CALL_P (insn)
8733 && GET_MODE (operands[3]) == Pmode"
8735 [(set_attr "op_type" "RIL")
8736 (set_attr "type" "jsr")
8737 (set_attr "z196prop" "z196_cracked")])
8739 (define_insn "*basr_tls"
8740 [(set (match_operand 0 "" "")
8741 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8742 (match_operand 2 "const_int_operand" "n")))
8743 (clobber (match_operand 3 "register_operand" "=r"))
8744 (use (match_operand 4 "" ""))]
8745 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8747 if (get_attr_op_type (insn) == OP_TYPE_RR)
8748 return "basr\t%3,%1%J4";
8750 return "bas\t%3,%a1%J4";
8752 [(set (attr "op_type")
8753 (if_then_else (match_operand 1 "register_operand" "")
8754 (const_string "RR") (const_string "RX")))
8755 (set_attr "type" "jsr")
8756 (set_attr "atype" "agen")
8757 (set_attr "z196prop" "z196_cracked")])
8760 ;;- Atomic operations
8764 ; memory barrier patterns.
8767 (define_expand "mem_signal_fence"
8768 [(match_operand:SI 0 "const_int_operand")] ;; model
8771 /* The s390 memory model is strong enough not to require any
8772 barrier in order to synchronize a thread with itself. */
8776 (define_expand "mem_thread_fence"
8777 [(match_operand:SI 0 "const_int_operand")] ;; model
8780 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8781 enough not to require barriers of any kind. */
8782 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
8784 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8785 MEM_VOLATILE_P (mem) = 1;
8786 emit_insn (gen_mem_thread_fence_1 (mem));
8791 ; Although bcr is superscalar on Z10, this variant will never
8792 ; become part of an execution group.
8793 (define_insn "mem_thread_fence_1"
8794 [(set (match_operand:BLK 0 "" "")
8795 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8798 [(set_attr "op_type" "RR")])
8801 ; atomic load/store operations
8804 ; Atomic loads need not examine the memory model at all.
8805 (define_expand "atomic_load<mode>"
8806 [(match_operand:DINT 0 "register_operand") ;; output
8807 (match_operand:DINT 1 "memory_operand") ;; memory
8808 (match_operand:SI 2 "const_int_operand")] ;; model
8811 if (<MODE>mode == TImode)
8812 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
8813 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8814 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
8816 emit_move_insn (operands[0], operands[1]);
8820 ; Different from movdi_31 in that we want no splitters.
8821 (define_insn "atomic_loaddi_1"
8822 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
8823 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
8831 [(set_attr "op_type" "RS,RSY,RS,RSY")
8832 (set_attr "type" "lm,lm,floaddf,floaddf")])
8834 (define_insn "atomic_loadti_1"
8835 [(set (match_operand:TI 0 "register_operand" "=r")
8836 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
8840 [(set_attr "op_type" "RXY")
8841 (set_attr "type" "other")])
8843 ; Atomic stores must(?) enforce sequential consistency.
8844 (define_expand "atomic_store<mode>"
8845 [(match_operand:DINT 0 "memory_operand") ;; memory
8846 (match_operand:DINT 1 "register_operand") ;; input
8847 (match_operand:SI 2 "const_int_operand")] ;; model
8850 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
8852 if (<MODE>mode == TImode)
8853 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
8854 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8855 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
8857 emit_move_insn (operands[0], operands[1]);
8858 if (model == MEMMODEL_SEQ_CST)
8859 emit_insn (gen_mem_thread_fence (operands[2]));
8863 ; Different from movdi_31 in that we want no splitters.
8864 (define_insn "atomic_storedi_1"
8865 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
8866 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
8874 [(set_attr "op_type" "RS,RSY,RS,RSY")
8875 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
8877 (define_insn "atomic_storeti_1"
8878 [(set (match_operand:TI 0 "memory_operand" "=RT")
8879 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
8883 [(set_attr "op_type" "RXY")
8884 (set_attr "type" "other")])
8887 ; compare and swap patterns.
8890 (define_expand "atomic_compare_and_swap<mode>"
8891 [(match_operand:SI 0 "register_operand") ;; bool success output
8892 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
8893 (match_operand:DGPR 2 "memory_operand") ;; memory
8894 (match_operand:DGPR 3 "register_operand") ;; expected intput
8895 (match_operand:DGPR 4 "register_operand") ;; newval intput
8896 (match_operand:SI 5 "const_int_operand") ;; is_weak
8897 (match_operand:SI 6 "const_int_operand") ;; success model
8898 (match_operand:SI 7 "const_int_operand")] ;; failure model
8901 rtx cc, cmp, output = operands[1];
8903 if (!register_operand (output, <MODE>mode))
8904 output = gen_reg_rtx (<MODE>mode);
8906 emit_insn (gen_atomic_compare_and_swap<mode>_internal
8907 (output, operands[2], operands[3], operands[4]));
8909 /* We deliberately accept non-register operands in the predicate
8910 to ensure the write back to the output operand happens *before*
8911 the store-flags code below. This makes it easier for combine
8912 to merge the store-flags code with a potential test-and-branch
8913 pattern following (immediately!) afterwards. */
8914 if (output != operands[1])
8915 emit_move_insn (operands[1], output);
8917 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
8918 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
8919 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
8923 (define_expand "atomic_compare_and_swap<mode>"
8924 [(match_operand:SI 0 "register_operand") ;; bool success output
8925 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
8926 (match_operand:HQI 2 "memory_operand") ;; memory
8927 (match_operand:HQI 3 "general_operand") ;; expected intput
8928 (match_operand:HQI 4 "general_operand") ;; newval intput
8929 (match_operand:SI 5 "const_int_operand") ;; is_weak
8930 (match_operand:SI 6 "const_int_operand") ;; success model
8931 (match_operand:SI 7 "const_int_operand")] ;; failure model
8934 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
8935 operands[3], operands[4], INTVAL (operands[5]));
8939 (define_expand "atomic_compare_and_swap<mode>_internal"
8941 [(set (match_operand:DGPR 0 "register_operand")
8942 (match_operand:DGPR 1 "memory_operand"))
8944 (unspec_volatile:DGPR
8946 (match_operand:DGPR 2 "register_operand")
8947 (match_operand:DGPR 3 "register_operand")]
8949 (set (reg:CCZ1 CC_REGNUM)
8950 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8954 (define_insn "*atomic_compare_and_swap<mode>_1"
8955 [(set (match_operand:TDI 0 "register_operand" "=r")
8956 (match_operand:TDI 1 "memory_operand" "+QS"))
8958 (unspec_volatile:TDI
8960 (match_operand:TDI 2 "register_operand" "0")
8961 (match_operand:TDI 3 "register_operand" "r")]
8963 (set (reg:CCZ1 CC_REGNUM)
8964 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8966 "c<td>sg\t%0,%3,%S1"
8967 [(set_attr "op_type" "RSY")
8968 (set_attr "type" "sem")])
8971 (define_insn "*atomic_compare_and_swapdi_2"
8972 [(set (match_operand:DI 0 "register_operand" "=r,r")
8973 (match_operand:DI 1 "memory_operand" "+Q,S"))
8977 (match_operand:DI 2 "register_operand" "0,0")
8978 (match_operand:DI 3 "register_operand" "r,r")]
8980 (set (reg:CCZ1 CC_REGNUM)
8981 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8986 [(set_attr "op_type" "RS,RSY")
8987 (set_attr "type" "sem")])
8990 (define_insn "*atomic_compare_and_swapsi_3"
8991 [(set (match_operand:SI 0 "register_operand" "=r,r")
8992 (match_operand:SI 1 "memory_operand" "+Q,S"))
8996 (match_operand:SI 2 "register_operand" "0,0")
8997 (match_operand:SI 3 "register_operand" "r,r")]
8999 (set (reg:CCZ1 CC_REGNUM)
9000 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9005 [(set_attr "op_type" "RS,RSY")
9006 (set_attr "type" "sem")])
9009 ; Other atomic instruction patterns.
9012 ; z196 load and add, xor, or and and instructions
9014 (define_expand "atomic_fetch_<atomic><mode>"
9015 [(match_operand:GPR 0 "register_operand") ;; val out
9017 (match_operand:GPR 1 "memory_operand") ;; memory
9018 (match_operand:GPR 2 "register_operand")) ;; val in
9019 (match_operand:SI 3 "const_int_operand")] ;; model
9022 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9023 (operands[0], operands[1], operands[2]));
9027 ; lan, lang, lao, laog, lax, laxg, laa, laag
9028 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9029 [(set (match_operand:GPR 0 "register_operand" "=d")
9030 (match_operand:GPR 1 "memory_operand" "+QS"))
9032 (unspec_volatile:GPR
9033 [(ATOMIC_Z196:GPR (match_dup 1)
9034 (match_operand:GPR 2 "general_operand" "d"))]
9036 (clobber (reg:CC CC_REGNUM))]
9038 "la<noxa><g>\t%0,%2,%1"
9039 [(set_attr "op_type" "RSY")
9040 (set_attr "type" "sem")])
9042 ;; For SImode and larger, the optabs.c code will do just fine in
9043 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9044 ;; better by expanding our own loop.
9046 (define_expand "atomic_<atomic><mode>"
9048 (match_operand:HQI 0 "memory_operand") ;; memory
9049 (match_operand:HQI 1 "general_operand")) ;; val in
9050 (match_operand:SI 2 "const_int_operand")] ;; model
9053 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9054 operands[1], false);
9058 (define_expand "atomic_fetch_<atomic><mode>"
9059 [(match_operand:HQI 0 "register_operand") ;; val out
9061 (match_operand:HQI 1 "memory_operand") ;; memory
9062 (match_operand:HQI 2 "general_operand")) ;; val in
9063 (match_operand:SI 3 "const_int_operand")] ;; model
9066 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9067 operands[2], false);
9071 (define_expand "atomic_<atomic>_fetch<mode>"
9072 [(match_operand:HQI 0 "register_operand") ;; val out
9074 (match_operand:HQI 1 "memory_operand") ;; memory
9075 (match_operand:HQI 2 "general_operand")) ;; val in
9076 (match_operand:SI 3 "const_int_operand")] ;; model
9079 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9084 (define_expand "atomic_exchange<mode>"
9085 [(match_operand:HQI 0 "register_operand") ;; val out
9086 (match_operand:HQI 1 "memory_operand") ;; memory
9087 (match_operand:HQI 2 "general_operand") ;; val in
9088 (match_operand:SI 3 "const_int_operand")] ;; model
9091 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9092 operands[2], false);
9097 ;;- Miscellaneous instructions.
9101 ; allocate stack instruction pattern(s).
9104 (define_expand "allocate_stack"
9105 [(match_operand 0 "general_operand" "")
9106 (match_operand 1 "general_operand" "")]
9109 rtx temp = gen_reg_rtx (Pmode);
9111 emit_move_insn (temp, s390_back_chain_rtx ());
9112 anti_adjust_stack (operands[1]);
9113 emit_move_insn (s390_back_chain_rtx (), temp);
9115 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9121 ; setjmp instruction pattern.
9124 (define_expand "builtin_setjmp_receiver"
9125 [(match_operand 0 "" "")]
9128 emit_insn (s390_load_got ());
9129 emit_use (pic_offset_table_rtx);
9133 ;; These patterns say how to save and restore the stack pointer. We need not
9134 ;; save the stack pointer at function level since we are careful to
9135 ;; preserve the backchain. At block level, we have to restore the backchain
9136 ;; when we restore the stack pointer.
9138 ;; For nonlocal gotos, we must save both the stack pointer and its
9139 ;; backchain and restore both. Note that in the nonlocal case, the
9140 ;; save area is a memory location.
9142 (define_expand "save_stack_function"
9143 [(match_operand 0 "general_operand" "")
9144 (match_operand 1 "general_operand" "")]
9148 (define_expand "restore_stack_function"
9149 [(match_operand 0 "general_operand" "")
9150 (match_operand 1 "general_operand" "")]
9154 (define_expand "restore_stack_block"
9155 [(match_operand 0 "register_operand" "")
9156 (match_operand 1 "register_operand" "")]
9159 rtx temp = gen_reg_rtx (Pmode);
9161 emit_move_insn (temp, s390_back_chain_rtx ());
9162 emit_move_insn (operands[0], operands[1]);
9163 emit_move_insn (s390_back_chain_rtx (), temp);
9168 (define_expand "save_stack_nonlocal"
9169 [(match_operand 0 "memory_operand" "")
9170 (match_operand 1 "register_operand" "")]
9173 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9175 /* Copy the backchain to the first word, sp to the second and the
9176 literal pool base to the third. */
9178 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9179 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9180 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9182 if (TARGET_BACKCHAIN)
9183 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9185 emit_move_insn (save_sp, operands[1]);
9186 emit_move_insn (save_bp, base);
9191 (define_expand "restore_stack_nonlocal"
9192 [(match_operand 0 "register_operand" "")
9193 (match_operand 1 "memory_operand" "")]
9196 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9197 rtx temp = NULL_RTX;
9199 /* Restore the backchain from the first word, sp from the second and the
9200 literal pool base from the third. */
9202 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9203 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9204 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9206 if (TARGET_BACKCHAIN)
9207 temp = force_reg (Pmode, save_bc);
9209 emit_move_insn (base, save_bp);
9210 emit_move_insn (operands[0], save_sp);
9213 emit_move_insn (s390_back_chain_rtx (), temp);
9219 (define_expand "exception_receiver"
9223 s390_set_has_landing_pad_p (true);
9228 ; nop instruction pattern(s).
9235 [(set_attr "op_type" "RR")
9236 (set_attr "z10prop" "z10_fr_E1")])
9242 [(set_attr "op_type" "RR")])
9246 ; Special literal pool access instruction pattern(s).
9249 (define_insn "*pool_entry"
9250 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9251 UNSPECV_POOL_ENTRY)]
9254 enum machine_mode mode = GET_MODE (PATTERN (insn));
9255 unsigned int align = GET_MODE_BITSIZE (mode);
9256 s390_output_pool_entry (operands[0], mode, align);
9259 [(set (attr "length")
9260 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9262 (define_insn "pool_align"
9263 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9264 UNSPECV_POOL_ALIGN)]
9267 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9269 (define_insn "pool_section_start"
9270 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9273 [(set_attr "length" "0")])
9275 (define_insn "pool_section_end"
9276 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9279 [(set_attr "length" "0")])
9281 (define_insn "main_base_31_small"
9282 [(set (match_operand 0 "register_operand" "=a")
9283 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9284 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9286 [(set_attr "op_type" "RR")
9287 (set_attr "type" "la")
9288 (set_attr "z196prop" "z196_cracked")])
9290 (define_insn "main_base_31_large"
9291 [(set (match_operand 0 "register_operand" "=a")
9292 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9293 (set (pc) (label_ref (match_operand 2 "" "")))]
9294 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9296 [(set_attr "op_type" "RI")
9297 (set_attr "z196prop" "z196_cracked")])
9299 (define_insn "main_base_64"
9300 [(set (match_operand 0 "register_operand" "=a")
9301 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9302 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9304 [(set_attr "op_type" "RIL")
9305 (set_attr "type" "larl")
9306 (set_attr "z10prop" "z10_fwd_A1")])
9308 (define_insn "main_pool"
9309 [(set (match_operand 0 "register_operand" "=a")
9310 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9311 "GET_MODE (operands[0]) == Pmode"
9316 (if_then_else (match_test "TARGET_CPU_ZARCH")
9317 (const_string "larl") (const_string "la")))])
9319 (define_insn "reload_base_31"
9320 [(set (match_operand 0 "register_operand" "=a")
9321 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9322 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9323 "basr\t%0,0\;la\t%0,%1-.(%0)"
9324 [(set_attr "length" "6")
9325 (set_attr "type" "la")
9326 (set_attr "z196prop" "z196_cracked")])
9328 (define_insn "reload_base_64"
9329 [(set (match_operand 0 "register_operand" "=a")
9330 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9331 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9333 [(set_attr "op_type" "RIL")
9334 (set_attr "type" "larl")
9335 (set_attr "z10prop" "z10_fwd_A1")])
9338 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9343 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9346 ;; Insns related to generating the function prologue and epilogue.
9350 (define_expand "prologue"
9351 [(use (const_int 0))]
9353 "s390_emit_prologue (); DONE;")
9355 (define_expand "epilogue"
9356 [(use (const_int 1))]
9358 "s390_emit_epilogue (false); DONE;")
9360 (define_expand "sibcall_epilogue"
9361 [(use (const_int 0))]
9363 "s390_emit_epilogue (true); DONE;")
9365 (define_insn "*return"
9367 (use (match_operand 0 "register_operand" "a"))]
9368 "GET_MODE (operands[0]) == Pmode"
9370 [(set_attr "op_type" "RR")
9371 (set_attr "type" "jsr")
9372 (set_attr "atype" "agen")])
9375 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9376 ;; pointer. This is used for compatibility.
9378 (define_expand "ptr_extend"
9379 [(set (match_operand:DI 0 "register_operand" "=r")
9380 (match_operand:SI 1 "register_operand" "r"))]
9383 emit_insn (gen_anddi3 (operands[0],
9384 gen_lowpart (DImode, operands[1]),
9385 GEN_INT (0x7fffffff)));
9389 ;; Instruction definition to expand eh_return macro to support
9390 ;; swapping in special linkage return addresses.
9392 (define_expand "eh_return"
9393 [(use (match_operand 0 "register_operand" ""))]
9396 s390_emit_tpf_eh_return (operands[0]);
9401 ; Stack Protector Patterns
9404 (define_expand "stack_protect_set"
9405 [(set (match_operand 0 "memory_operand" "")
9406 (match_operand 1 "memory_operand" ""))]
9409 #ifdef TARGET_THREAD_SSP_OFFSET
9411 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9412 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9415 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9417 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9422 (define_insn "stack_protect_set<mode>"
9423 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9424 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9426 "mvc\t%O0(%G0,%R0),%S1"
9427 [(set_attr "op_type" "SS")])
9429 (define_expand "stack_protect_test"
9430 [(set (reg:CC CC_REGNUM)
9431 (compare (match_operand 0 "memory_operand" "")
9432 (match_operand 1 "memory_operand" "")))
9433 (match_operand 2 "" "")]
9437 #ifdef TARGET_THREAD_SSP_OFFSET
9439 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9440 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9443 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9445 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9447 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9448 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9449 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9453 (define_insn "stack_protect_test<mode>"
9454 [(set (reg:CCZ CC_REGNUM)
9455 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9456 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9458 "clc\t%O0(%G0,%R0),%S1"
9459 [(set_attr "op_type" "SS")])
9461 ; This is used in s390_emit_prologue in order to prevent insns
9462 ; adjusting the stack pointer to be moved over insns writing stack
9463 ; slots using a copy of the stack pointer in a different register.
9464 (define_insn "stack_tie"
9465 [(set (match_operand:BLK 0 "memory_operand" "+m")
9466 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9469 [(set_attr "length" "0")])
9473 ; Data prefetch patterns
9476 (define_insn "prefetch"
9477 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9478 (match_operand:SI 1 "const_int_operand" " n,n")
9479 (match_operand:SI 2 "const_int_operand" " n,n"))]
9482 switch (which_alternative)
9485 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9487 if (larl_operand (operands[0], Pmode))
9488 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9491 /* This might be reached for symbolic operands with an odd
9492 addend. We simply omit the prefetch for such rare cases. */
9497 [(set_attr "type" "load,larl")
9498 (set_attr "op_type" "RXY,RIL")
9499 (set_attr "z10prop" "z10_super")
9500 (set_attr "z196prop" "z196_alone")])
9504 ; Byte swap instructions
9507 (define_insn "bswap<mode>2"
9508 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9509 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9514 [(set_attr "type" "*,load")
9515 (set_attr "op_type" "RRE,RXY")
9516 (set_attr "z10prop" "z10_super")])
9520 ; Population count instruction
9523 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9524 ; portions and stores the result in the corresponding bytes in op0.
9525 (define_insn "*popcount<mode>"
9526 [(set (match_operand:INT 0 "register_operand" "=d")
9527 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9528 (clobber (reg:CC CC_REGNUM))]
9531 [(set_attr "op_type" "RRE")])
9533 (define_expand "popcountdi2"
9535 (parallel [(set (match_operand:DI 0 "register_operand" "")
9536 (unspec:DI [(match_operand:DI 1 "register_operand")]
9538 (clobber (reg:CC CC_REGNUM))])
9540 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9542 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9543 (clobber (reg:CC CC_REGNUM))])
9546 (ashift:DI (match_dup 0) (const_int 16)))
9548 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9549 (clobber (reg:CC CC_REGNUM))])
9551 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9553 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9554 (clobber (reg:CC CC_REGNUM))])
9556 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9557 "TARGET_Z196 && TARGET_64BIT"
9558 "operands[2] = gen_reg_rtx (DImode);")
9560 (define_expand "popcountsi2"
9562 (parallel [(set (match_operand:SI 0 "register_operand" "")
9563 (unspec:SI [(match_operand:SI 1 "register_operand")]
9565 (clobber (reg:CC CC_REGNUM))])
9568 (ashift:SI (match_dup 0) (const_int 16)))
9570 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9571 (clobber (reg:CC CC_REGNUM))])
9573 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9575 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9576 (clobber (reg:CC CC_REGNUM))])
9578 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9580 "operands[2] = gen_reg_rtx (SImode);")
9582 (define_expand "popcounthi2"
9584 (parallel [(set (match_operand:HI 0 "register_operand" "")
9585 (unspec:HI [(match_operand:HI 1 "register_operand")]
9587 (clobber (reg:CC CC_REGNUM))])
9590 (ashift:SI (match_dup 0) (const_int 8)))
9592 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9593 (clobber (reg:CC CC_REGNUM))])
9595 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9597 "operands[2] = gen_reg_rtx (SImode);")
9599 (define_expand "popcountqi2"
9601 (parallel [(set (match_operand:QI 0 "register_operand" "")
9602 (unspec:QI [(match_operand:QI 1 "register_operand")]
9604 (clobber (reg:CC CC_REGNUM))])]
9609 ;;- Copy sign instructions
9612 (define_insn "copysign<mode>3"
9613 [(set (match_operand:FP 0 "register_operand" "=f")
9614 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9615 (match_operand:FP 2 "register_operand" "f")]
9619 [(set_attr "op_type" "RRF")
9620 (set_attr "type" "fsimp<mode>")])