1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
48 ;; Define an insn type attribute. This is used in function unit delay
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
58 (define_attr "atype" "reg,mem"
61 ;; Generic pipeline function unit.
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
117 ;; Operand type. Used to default length attribute values
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
143 ;; Define attributes for `asm' insns.
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
159 ; CCZ1 -> CCA/CCU/CCS/CCT
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
167 ;;- Compare instructions.
170 (define_expand "cmpdi"
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
182 (define_expand "cmpsi"
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
194 (define_expand "cmpdf"
196 (compare:CC (match_operand:DF 0 "register_operand" "")
197 (match_operand:DF 1 "general_operand" "")))]
201 s390_compare_op0 = operands[0];
202 s390_compare_op1 = operands[1];
206 (define_expand "cmpsf"
208 (compare:CC (match_operand:SF 0 "register_operand" "")
209 (match_operand:SF 1 "general_operand" "")))]
213 s390_compare_op0 = operands[0];
214 s390_compare_op1 = operands[1];
219 ; Test-under-Mask (zero_extract) instructions
221 (define_insn "*tmdi_ext"
223 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
224 (match_operand:DI 1 "const_int_operand" "n")
225 (match_operand:DI 2 "const_int_operand" "n"))
227 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
228 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
229 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
230 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
231 == INTVAL (operands[2]) >> 4"
234 int part = INTVAL (operands[2]) >> 4;
235 int block = (1 << INTVAL (operands[1])) - 1;
236 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
238 operands[2] = GEN_INT (block << shift);
242 case 0: return \"tmhh\\t%0,%x2\";
243 case 1: return \"tmhl\\t%0,%x2\";
244 case 2: return \"tmlh\\t%0,%x2\";
245 case 3: return \"tmll\\t%0,%x2\";
249 [(set_attr "op_type" "RI")])
251 (define_insn "*tmsi_ext"
253 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
254 (match_operand:SI 1 "const_int_operand" "n")
255 (match_operand:SI 2 "const_int_operand" "n"))
257 "s390_match_ccmode(insn, CCTmode)
258 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
259 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
260 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
261 == INTVAL (operands[2]) >> 4"
264 int part = INTVAL (operands[2]) >> 4;
265 int block = (1 << INTVAL (operands[1])) - 1;
266 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
268 operands[2] = GEN_INT (block << shift);
272 case 0: return \"tmh\\t%0,%x2\";
273 case 1: return \"tml\\t%0,%x2\";
277 [(set_attr "op_type" "RI")])
279 (define_insn "*tmqi_ext"
281 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
282 (match_operand:SI 1 "const_int_operand" "n")
283 (match_operand:SI 2 "const_int_operand" "n"))
285 "s390_match_ccmode(insn, CCTmode)
286 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
287 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
290 int block = (1 << INTVAL (operands[1])) - 1;
291 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
293 operands[2] = GEN_INT (block << shift);
294 return \"tm\\t%0,%b2\";
296 [(set_attr "op_type" "SI")
297 (set_attr "atype" "mem")])
299 ; Test-under-Mask instructions
301 (define_insn "*tmdi_mem"
303 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
304 (match_operand:DI 1 "immediate_operand" "n"))
305 (match_operand:DI 2 "immediate_operand" "n")))]
307 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
308 && s390_single_qi (operands[1], DImode, 0) >= 0"
311 int part = s390_single_qi (operands[1], DImode, 0);
312 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
314 operands[0] = gen_rtx_MEM (QImode,
315 plus_constant (XEXP (operands[0], 0), part));
316 return \"tm\\t%0,%b1\";
318 [(set_attr "op_type" "SI")
319 (set_attr "atype" "mem")])
321 (define_insn "*tmsi_mem"
323 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
324 (match_operand:SI 1 "immediate_operand" "n"))
325 (match_operand:SI 2 "immediate_operand" "n")))]
326 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
327 && s390_single_qi (operands[1], SImode, 0) >= 0"
330 int part = s390_single_qi (operands[1], SImode, 0);
331 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
333 operands[0] = gen_rtx_MEM (QImode,
334 plus_constant (XEXP (operands[0], 0), part));
335 return \"tm\\t%0,%b1\";
337 [(set_attr "op_type" "SI")
338 (set_attr "atype" "mem")])
340 (define_insn "*tmhi_mem"
342 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
343 (match_operand:SI 1 "immediate_operand" "n"))
344 (match_operand:SI 2 "immediate_operand" "n")))]
345 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
346 && s390_single_qi (operands[1], HImode, 0) >= 0"
349 int part = s390_single_qi (operands[1], HImode, 0);
350 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
352 operands[0] = gen_rtx_MEM (QImode,
353 plus_constant (XEXP (operands[0], 0), part));
354 return \"tm\\t%0,%b1\";
356 [(set_attr "op_type" "SI")
357 (set_attr "atype" "mem")])
359 (define_insn "*tmqi_mem"
361 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
362 (match_operand:SI 1 "immediate_operand" "n"))
363 (match_operand:SI 2 "immediate_operand" "n")))]
364 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
366 [(set_attr "op_type" "SI")
367 (set_attr "atype" "mem")])
369 (define_insn "*tmdi_reg"
371 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
372 (match_operand:DI 1 "immediate_operand" "n"))
373 (match_operand:DI 2 "immediate_operand" "n")))]
375 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
376 && s390_single_hi (operands[1], DImode, 0) >= 0"
379 int part = s390_single_hi (operands[1], DImode, 0);
380 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
384 case 0: return \"tmhh\\t%0,%x1\";
385 case 1: return \"tmhl\\t%0,%x1\";
386 case 2: return \"tmlh\\t%0,%x1\";
387 case 3: return \"tmll\\t%0,%x1\";
391 [(set_attr "op_type" "RI")])
393 (define_insn "*tmsi_reg"
395 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
396 (match_operand:SI 1 "immediate_operand" "n"))
397 (match_operand:SI 2 "immediate_operand" "n")))]
398 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
399 && s390_single_hi (operands[1], SImode, 0) >= 0"
402 int part = s390_single_hi (operands[1], SImode, 0);
403 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
407 case 0: return \"tmh\\t%0,%x1\";
408 case 1: return \"tml\\t%0,%x1\";
412 [(set_attr "op_type" "RI")])
414 (define_insn "*tmhi_full"
416 (compare (match_operand:HI 0 "register_operand" "d")
417 (match_operand:HI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
420 [(set_attr "op_type" "RX")])
422 (define_insn "*tmqi_full"
424 (compare (match_operand:QI 0 "register_operand" "d")
425 (match_operand:QI 1 "immediate_operand" "n")))]
426 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
428 [(set_attr "op_type" "RI")])
431 ; Load-and-Test instructions
433 (define_insn "*tstdi_sign"
435 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
436 (const_int 32)) (const_int 32))
437 (match_operand:DI 1 "const0_operand" "")))
438 (set (match_operand:DI 2 "register_operand" "=d")
439 (sign_extend:DI (match_dup 0)))]
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
442 [(set_attr "op_type" "RRE")])
444 (define_insn "*tstdi"
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))
448 (set (match_operand:DI 2 "register_operand" "=d")
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
452 [(set_attr "op_type" "RRE")])
454 (define_insn "*tstdi_cconly"
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
460 [(set_attr "op_type" "RRE")])
462 (define_insn "*tstdi_cconly_31"
464 (compare (match_operand:DI 0 "register_operand" "d")
465 (match_operand:DI 1 "const0_operand" "")))]
466 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
468 [(set_attr "op_type" "RS")])
470 (define_insn "*tstsi"
472 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
473 (match_operand:SI 1 "const0_operand" "")))
474 (set (match_operand:SI 2 "register_operand" "=d,d")
476 "s390_match_ccmode(insn, CCSmode)"
480 [(set_attr "op_type" "RR,RS")
481 (set_attr "atype" "reg,mem")])
483 (define_insn "*tstsi_cconly"
485 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
486 (match_operand:SI 1 "const0_operand" "")))
487 (clobber (match_scratch:SI 2 "=X,d"))]
488 "s390_match_ccmode(insn, CCSmode)"
492 [(set_attr "op_type" "RR,RS")
493 (set_attr "atype" "reg,mem")])
495 (define_insn "*tstsi_cconly2"
497 (compare (match_operand:SI 0 "register_operand" "d")
498 (match_operand:SI 1 "const0_operand" "")))]
499 "s390_match_ccmode(insn, CCSmode)"
501 [(set_attr "op_type" "RR")])
503 (define_insn "*tsthi"
505 (compare (match_operand:HI 0 "s_operand" "Q")
506 (match_operand:HI 1 "const0_operand" "")))
507 (set (match_operand:HI 2 "register_operand" "=d")
509 "s390_match_ccmode(insn, CCSmode)"
511 [(set_attr "op_type" "RS")
512 (set_attr "atype" "mem")])
514 (define_insn "*tsthi_cconly"
516 (compare (match_operand:HI 0 "s_operand" "Q")
517 (match_operand:HI 1 "const0_operand" "")))
518 (clobber (match_scratch:HI 2 "=d"))]
519 "s390_match_ccmode(insn, CCSmode)"
521 [(set_attr "op_type" "RS")
522 (set_attr "atype" "mem")])
524 (define_insn "*tstqi"
526 (compare (match_operand:QI 0 "s_operand" "Q")
527 (match_operand:QI 1 "const0_operand" "")))
528 (set (match_operand:QI 2 "register_operand" "=d")
530 "s390_match_ccmode(insn, CCSmode)"
532 [(set_attr "op_type" "RS")
533 (set_attr "atype" "mem")])
535 (define_insn "*tstqi_cconly"
537 (compare (match_operand:QI 0 "s_operand" "Q")
538 (match_operand:QI 1 "const0_operand" "")))
539 (clobber (match_scratch:QI 2 "=d"))]
540 "s390_match_ccmode(insn, CCSmode)"
542 [(set_attr "op_type" "RS")
543 (set_attr "atype" "mem")])
546 ; Compare (signed) instructions
548 (define_insn "*cmpdi_ccs_sign"
550 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
551 (match_operand:DI 0 "register_operand" "d,d")))]
552 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
556 [(set_attr "op_type" "RRE,RXE")
557 (set_attr "atype" "reg,mem")])
559 (define_insn "*cmpdi_ccs"
561 (compare (match_operand:DI 0 "register_operand" "d,d,d")
562 (match_operand:DI 1 "general_operand" "d,K,m")))]
563 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
568 [(set_attr "op_type" "RRE,RI,RXE")
569 (set_attr "atype" "reg,reg,mem")])
571 (define_insn "*cmpsi_ccs_sign"
573 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
574 (match_operand:SI 0 "register_operand" "d")))]
575 "s390_match_ccmode(insn, CCSRmode)"
577 [(set_attr "op_type" "RX")
578 (set_attr "atype" "mem")])
580 (define_insn "*cmpsi_ccs"
582 (compare (match_operand:SI 0 "register_operand" "d,d,d")
583 (match_operand:SI 1 "general_operand" "d,K,m")))]
584 "s390_match_ccmode(insn, CCSmode)"
589 [(set_attr "op_type" "RR,RI,RX")
590 (set_attr "atype" "reg,reg,mem")])
593 ; Compare (unsigned) instructions
595 (define_insn "*cmpdi_ccu_zero"
597 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
598 (match_operand:DI 0 "register_operand" "d,d")))]
599 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
603 [(set_attr "op_type" "RRE,RXE")
604 (set_attr "atype" "reg,mem")])
606 (define_insn "*cmpdi_ccu"
608 (compare (match_operand:DI 0 "register_operand" "d,d")
609 (match_operand:DI 1 "general_operand" "d,m")))]
610 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
614 [(set_attr "op_type" "RRE,RXE")
615 (set_attr "atype" "reg,mem")])
617 (define_insn "*cmpsi_ccu"
619 (compare (match_operand:SI 0 "register_operand" "d,d")
620 (match_operand:SI 1 "general_operand" "d,m")))]
621 "s390_match_ccmode(insn, CCUmode)"
625 [(set_attr "op_type" "RR,RX")
626 (set_attr "atype" "reg,mem")])
628 (define_insn "*cmphi_ccu"
630 (compare (match_operand:HI 0 "register_operand" "d")
631 (match_operand:HI 1 "s_imm_operand" "Q")))]
632 "s390_match_ccmode(insn, CCUmode)"
634 [(set_attr "op_type" "RS")
635 (set_attr "atype" "mem")])
637 (define_insn "*cmpqi_ccu"
639 (compare (match_operand:QI 0 "register_operand" "d")
640 (match_operand:QI 1 "s_imm_operand" "Q")))]
641 "s390_match_ccmode(insn, CCUmode)"
643 [(set_attr "op_type" "RS")
644 (set_attr "atype" "mem")])
648 (compare (match_operand:QI 0 "memory_operand" "Q")
649 (match_operand:QI 1 "immediate_operand" "n")))]
650 "s390_match_ccmode (insn, CCUmode)"
652 [(set_attr "op_type" "SI")
653 (set_attr "atype" "mem")])
655 (define_insn "*cmpdi_ccu_mem"
657 (compare (match_operand:DI 0 "s_operand" "Q")
658 (match_operand:DI 1 "s_imm_operand" "Q")))]
659 "s390_match_ccmode(insn, CCUmode)"
660 "clc\\t%O0(8,%R0),%1"
661 [(set_attr "op_type" "SS")
662 (set_attr "atype" "mem")])
664 (define_insn "*cmpsi_ccu_mem"
666 (compare (match_operand:SI 0 "s_operand" "Q")
667 (match_operand:SI 1 "s_imm_operand" "Q")))]
668 "s390_match_ccmode(insn, CCUmode)"
669 "clc\\t%O0(4,%R0),%1"
670 [(set_attr "op_type" "SS")
671 (set_attr "atype" "mem")])
673 (define_insn "*cmphi_ccu_mem"
675 (compare (match_operand:HI 0 "s_operand" "Q")
676 (match_operand:HI 1 "s_imm_operand" "Q")))]
677 "s390_match_ccmode(insn, CCUmode)"
678 "clc\\t%O0(2,%R0),%1"
679 [(set_attr "op_type" "SS")
680 (set_attr "atype" "mem")])
682 (define_insn "*cmpqi_ccu_mem"
684 (compare (match_operand:QI 0 "s_operand" "Q")
685 (match_operand:QI 1 "s_imm_operand" "Q")))]
686 "s390_match_ccmode(insn, CCUmode)"
687 "clc\\t%O0(1,%R0),%1"
688 [(set_attr "op_type" "SS")
689 (set_attr "atype" "mem")])
694 (define_insn "*cmpdf_ccs_0"
696 (compare (match_operand:DF 0 "register_operand" "f")
697 (match_operand:DF 1 "const0_operand" "")))]
698 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
700 [(set_attr "op_type" "RRE")])
702 (define_insn "*cmpdf_ccs_0_ibm"
704 (compare (match_operand:DF 0 "register_operand" "f")
705 (match_operand:DF 1 "const0_operand" "")))]
706 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
708 [(set_attr "op_type" "RR")])
710 (define_insn "*cmpdf_ccs"
712 (compare (match_operand:DF 0 "register_operand" "f,f")
713 (match_operand:DF 1 "general_operand" "f,m")))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
718 [(set_attr "op_type" "RRE,RXE")
719 (set_attr "atype" "reg,mem")])
721 (define_insn "*cmpdf_ccs_ibm"
723 (compare (match_operand:DF 0 "register_operand" "f,f")
724 (match_operand:DF 1 "general_operand" "f,m")))]
725 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
729 [(set_attr "op_type" "RR,RX")
730 (set_attr "atype" "reg,mem")])
735 (define_insn "*cmpsf_ccs_0"
737 (compare (match_operand:SF 0 "register_operand" "f")
738 (match_operand:SF 1 "const0_operand" "")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
741 [(set_attr "op_type" "RRE")])
743 (define_insn "*cmpsf_ccs_0_ibm"
745 (compare (match_operand:SF 0 "register_operand" "f")
746 (match_operand:SF 1 "const0_operand" "")))]
747 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
749 [(set_attr "op_type" "RR")])
751 (define_insn "*cmpsf_ccs"
753 (compare (match_operand:SF 0 "register_operand" "f,f")
754 (match_operand:SF 1 "general_operand" "f,m")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
759 [(set_attr "op_type" "RRE,RXE")
760 (set_attr "atype" "reg,mem")])
762 (define_insn "*cmpsf_ccs"
764 (compare (match_operand:SF 0 "register_operand" "f,f")
765 (match_operand:SF 1 "general_operand" "f,m")))]
766 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
770 [(set_attr "op_type" "RR,RX")
771 (set_attr "atype" "reg,mem")])
775 ;;- Move instructions.
779 ; movti instruction pattern(s).
783 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
784 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
791 mvc\\t%O0(16,%R0),%1"
792 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
793 (set_attr "atype" "mem")])
796 [(set (match_operand:TI 0 "nonimmediate_operand" "")
797 (match_operand:TI 1 "general_operand" ""))]
798 "TARGET_64BIT && reload_completed
799 && !s_operand (operands[0], VOIDmode)
800 && !s_operand (operands[1], VOIDmode)
801 && (register_operand (operands[0], VOIDmode)
802 || register_operand (operands[1], VOIDmode))
803 && (!register_operand (operands[0], VOIDmode)
804 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
806 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
808 [(set (match_dup 2) (match_dup 4))
809 (set (match_dup 3) (match_dup 5))]
812 if (!register_operand (operands[0], VOIDmode)
813 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
816 operands[2] = operand_subword (operands[0], 0, 0, TImode);
817 operands[3] = operand_subword (operands[0], 1, 0, TImode);
818 operands[4] = operand_subword (operands[1], 0, 0, TImode);
819 operands[5] = operand_subword (operands[1], 1, 0, TImode);
823 operands[2] = operand_subword (operands[0], 1, 0, TImode);
824 operands[3] = operand_subword (operands[0], 0, 0, TImode);
825 operands[4] = operand_subword (operands[1], 1, 0, TImode);
826 operands[5] = operand_subword (operands[1], 0, 0, TImode);
831 [(set (match_operand:TI 0 "register_operand" "")
832 (match_operand:TI 1 "memory_operand" ""))]
833 "TARGET_64BIT && reload_completed
834 && !s_operand (operands[1], VOIDmode)"
835 [(set (match_dup 2) (match_dup 3))
836 (set (match_dup 0) (mem:TI (match_dup 2)))]
837 "operands[2] = operand_subword (operands[0], 1, 0, TImode);
838 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
841 ; movdi instruction pattern(s).
844 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
845 ;; move to get the address of the symbolic object from the GOT.
847 (define_expand "movdi"
848 [(set (match_operand:DI 0 "general_operand" "")
849 (match_operand:DI 1 "general_operand" ""))]
853 /* Handle PIC symbolic constants. */
854 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
855 emit_pic_move (operands, DImode);
857 /* During and after reload, we need to force constants
858 to the literal pool ourselves, if necessary. */
859 if ((reload_in_progress || reload_completed)
860 && CONSTANT_P (operands[1])
861 && (!legitimate_reload_constant_p (operands[1])
862 || fp_operand (operands[0], VOIDmode)))
863 operands[1] = force_const_mem (DImode, operands[1]);
866 (define_insn "*movdi_lhi"
867 [(set (match_operand:DI 0 "register_operand" "=d")
868 (match_operand:DI 1 "immediate_operand" "K"))]
870 && GET_CODE (operands[1]) == CONST_INT
871 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
872 && !fp_operand (operands[0], VOIDmode)"
874 [(set_attr "op_type" "RI")
875 (set_attr "atype" "reg")])
877 (define_insn "*movdi_lli"
878 [(set (match_operand:DI 0 "register_operand" "=d")
879 (match_operand:DI 1 "immediate_operand" "n"))]
880 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
881 && !fp_operand (operands[0], VOIDmode)"
884 int part = s390_single_hi (operands[1], DImode, 0);
885 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
889 case 0: return \"llihh\\t%0,%x1\";
890 case 1: return \"llihl\\t%0,%x1\";
891 case 2: return \"llilh\\t%0,%x1\";
892 case 3: return \"llill\\t%0,%x1\";
896 [(set_attr "op_type" "RI")
897 (set_attr "atype" "reg")])
899 (define_insn "*movdi_larl"
900 [(set (match_operand:DI 0 "register_operand" "=d")
901 (match_operand:DI 1 "larl_operand" "X"))]
903 && !fp_operand (operands[0], VOIDmode)"
905 [(set_attr "op_type" "RIL")
906 (set_attr "atype" "reg")
907 (set_attr "type" "la")])
909 (define_insn "*movdi_64"
910 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
911 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
921 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX,SS")
922 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
924 (define_insn "*movdi_31"
925 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
926 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
937 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
938 (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
941 [(set (match_operand:DI 0 "nonimmediate_operand" "")
942 (match_operand:DI 1 "general_operand" ""))]
943 "!TARGET_64BIT && reload_completed
944 && !fp_operand (operands[0], VOIDmode)
945 && !fp_operand (operands[1], VOIDmode)
946 && !s_operand (operands[0], VOIDmode)
947 && !s_operand (operands[1], VOIDmode)
948 && (register_operand (operands[0], VOIDmode)
949 || register_operand (operands[1], VOIDmode))
950 && (!register_operand (operands[0], VOIDmode)
951 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
953 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
955 [(set (match_dup 2) (match_dup 4))
956 (set (match_dup 3) (match_dup 5))]
959 if (!register_operand (operands[0], VOIDmode)
960 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
963 operands[2] = operand_subword (operands[0], 0, 0, DImode);
964 operands[3] = operand_subword (operands[0], 1, 0, DImode);
965 operands[4] = operand_subword (operands[1], 0, 0, DImode);
966 operands[5] = operand_subword (operands[1], 1, 0, DImode);
970 operands[2] = operand_subword (operands[0], 1, 0, DImode);
971 operands[3] = operand_subword (operands[0], 0, 0, DImode);
972 operands[4] = operand_subword (operands[1], 1, 0, DImode);
973 operands[5] = operand_subword (operands[1], 0, 0, DImode);
978 [(set (match_operand:DI 0 "register_operand" "")
979 (match_operand:DI 1 "memory_operand" ""))]
980 "!TARGET_64BIT && reload_completed
981 && !fp_operand (operands[0], VOIDmode)
982 && !fp_operand (operands[1], VOIDmode)
983 && !s_operand (operands[1], VOIDmode)"
984 [(set (match_dup 2) (match_dup 3))
985 (set (match_dup 0) (mem:DI (match_dup 2)))]
986 "operands[2] = operand_subword (operands[0], 1, 0, DImode);
987 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
990 ; movsi instruction pattern(s).
993 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
994 ;; move to get the address of the symbolic object from the GOT.
996 (define_expand "movsi"
997 [(set (match_operand:SI 0 "general_operand" "")
998 (match_operand:SI 1 "general_operand" ""))]
1002 /* Handle PIC symbolic constants. */
1003 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1004 emit_pic_move (operands, SImode);
1006 /* expr.c tries to load an effective address using
1007 force_reg. This fails because we don't have a
1008 generic load_address pattern. Convert the move
1009 to a proper arithmetic operation instead, unless
1010 it is guaranteed to be OK. */
1011 if (GET_CODE (operands[1]) == PLUS
1012 && !legitimate_la_operand_p (operands[1]))
1014 operands[1] = force_operand (operands[1], operands[0]);
1015 if (operands[1] == operands[0])
1019 /* During and after reload, we need to force constants
1020 to the literal pool ourselves, if necessary. */
1021 if ((reload_in_progress || reload_completed)
1022 && CONSTANT_P (operands[1])
1023 && (!legitimate_reload_constant_p (operands[1])
1024 || fp_operand (operands[0], VOIDmode)))
1025 operands[1] = force_const_mem (SImode, operands[1]);
1028 (define_insn "*movsi_lhi"
1029 [(set (match_operand:SI 0 "register_operand" "=d")
1030 (match_operand:SI 1 "immediate_operand" "K"))]
1031 "GET_CODE (operands[1]) == CONST_INT
1032 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1033 && !fp_operand (operands[0], VOIDmode)"
1035 [(set_attr "op_type" "RI")])
1037 (define_insn "*movsi_lli"
1038 [(set (match_operand:SI 0 "register_operand" "=d")
1039 (match_operand:SI 1 "immediate_operand" "n"))]
1040 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1041 && !fp_operand (operands[0], VOIDmode)"
1044 int part = s390_single_hi (operands[1], SImode, 0);
1045 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1049 case 0: return \"llilh\\t%0,%x1\";
1050 case 1: return \"llill\\t%0,%x1\";
1054 [(set_attr "op_type" "RI")])
1056 (define_insn "*movsi"
1057 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1058 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1067 mvc\\t%O0(4,%R0),%1"
1068 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1069 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1073 ; movhi instruction pattern(s).
1076 (define_insn "movhi"
1077 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1078 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1085 mvc\\t%O0(2,%R0),%1"
1086 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1087 (set_attr "atype" "reg,reg,mem,mem,mem")])
1091 ; movqi instruction pattern(s).
1094 (define_insn "movqi_64"
1095 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1096 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1104 mvc\\t%O0(1,%R0),%1"
1105 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1106 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1109 (define_insn "movqi"
1110 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1111 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1119 mvc\\t%O0(1,%R0),%1"
1120 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1121 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1125 ; movstrictqi instruction pattern(s).
1128 (define_insn "*movstrictqi"
1129 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1130 (match_operand:QI 1 "memory_operand" "m"))]
1133 [(set_attr "op_type" "RX")
1134 (set_attr "atype" "mem")])
1137 ; movstricthi instruction pattern(s).
1140 (define_insn "*movstricthi"
1141 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1142 (match_operand:HI 1 "s_imm_operand" "Q"))
1143 (clobber (reg:CC 33))]
1146 [(set_attr "op_type" "RS")
1147 (set_attr "atype" "mem")])
1151 ; movstrictsi instruction pattern(s).
1154 (define_insn "movstrictsi"
1155 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1156 (match_operand:SI 1 "general_operand" "d,m"))]
1161 [(set_attr "op_type" "RR,RS")
1162 (set_attr "atype" "reg,mem")])
1166 ; movdf instruction pattern(s).
1169 (define_expand "movdf"
1170 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1171 (match_operand:DF 1 "general_operand" ""))]
1175 /* During and after reload, we need to force constants
1176 to the literal pool ourselves, if necessary. */
1177 if ((reload_in_progress || reload_completed)
1178 && CONSTANT_P (operands[1]))
1179 operands[1] = force_const_mem (DFmode, operands[1]);
1182 (define_insn "*movdf_64"
1183 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1184 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1193 mvc\\t%O0(8,%R0),%1"
1194 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE,SS")
1195 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1197 (define_insn "*movdf_31"
1198 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1199 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1209 mvc\\t%O0(8,%R0),%1"
1210 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1211 (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
1214 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1215 (match_operand:DF 1 "general_operand" ""))]
1216 "!TARGET_64BIT && reload_completed
1217 && !fp_operand (operands[0], VOIDmode)
1218 && !fp_operand (operands[1], VOIDmode)
1219 && !s_operand (operands[0], VOIDmode)
1220 && !s_operand (operands[1], VOIDmode)
1221 && (register_operand (operands[0], VOIDmode)
1222 || register_operand (operands[1], VOIDmode))
1223 && (!register_operand (operands[0], VOIDmode)
1224 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1226 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1228 [(set (match_dup 2) (match_dup 4))
1229 (set (match_dup 3) (match_dup 5))]
1232 if (!register_operand (operands[0], VOIDmode)
1233 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1236 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1237 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1238 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1239 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1243 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1244 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1245 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1246 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1251 [(set (match_operand:DF 0 "register_operand" "")
1252 (match_operand:DF 1 "memory_operand" ""))]
1253 "!TARGET_64BIT && reload_completed
1254 && !fp_operand (operands[0], VOIDmode)
1255 && !fp_operand (operands[1], VOIDmode)
1256 && !s_operand (operands[1], VOIDmode)"
1257 [(set (match_dup 2) (match_dup 3))
1258 (set (match_dup 0) (mem:DI (match_dup 2)))]
1259 "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1260 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1263 ; movsf instruction pattern(s).
1266 (define_expand "movsf"
1267 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1268 (match_operand:SF 1 "general_operand" ""))]
1272 /* During and after reload, we need to force constants
1273 to the literal pool ourselves, if necessary. */
1274 if ((reload_in_progress || reload_completed)
1275 && CONSTANT_P (operands[1]))
1276 operands[1] = force_const_mem (SFmode, operands[1]);
1279 (define_insn "*movsf"
1280 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1281 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1290 mvc\\t%O0(4,%R0),%1"
1291 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1292 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1295 ; load_multiple pattern(s).
1298 (define_expand "load_multiple"
1299 [(match_par_dup 3 [(set (match_operand 0 "" "")
1300 (match_operand 1 "" ""))
1301 (use (match_operand 2 "" ""))])]
1310 /* Support only loading a constant number of fixed-point registers from
1311 memory and only bother with this if more than two */
1312 if (GET_CODE (operands[2]) != CONST_INT
1313 || INTVAL (operands[2]) < 2
1314 || INTVAL (operands[2]) > 16
1315 || GET_CODE (operands[1]) != MEM
1316 || GET_CODE (operands[0]) != REG
1317 || REGNO (operands[0]) >= 16)
1320 count = INTVAL (operands[2]);
1321 regno = REGNO (operands[0]);
1323 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1326 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1328 from = XEXP (operands[1], 0);
1331 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1332 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1333 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1335 from = XEXP (XEXP (operands[1], 0), 0);
1336 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1341 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1346 from = force_reg (Pmode, XEXP (operands[1], 0));
1350 for (i = 0; i < count; i++)
1351 XVECEXP (operands[3], 0, i)
1352 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1353 change_address (operands[1], Pmode,
1354 plus_constant (from,
1355 off + i * UNITS_PER_WORD)));
1358 (define_insn "*load_multiple_di"
1359 [(match_parallel 0 "load_multiple_operation"
1360 [(set (match_operand:DI 1 "register_operand" "=r")
1361 (match_operand:DI 2 "s_operand" "Q"))])]
1365 int words = XVECLEN (operands[0], 0);
1367 if (XVECLEN (operands[0], 0) == 1)
1368 return \"lg\\t%1,0(%2)\";
1370 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1371 return \"lmg\\t%1,%0,%2\";
1373 [(set_attr "op_type" "RXE")
1374 (set_attr "atype" "mem")
1375 (set_attr "type" "lm")])
1377 (define_insn "*load_multiple_si"
1378 [(match_parallel 0 "load_multiple_operation"
1379 [(set (match_operand:SI 1 "register_operand" "=r")
1380 (match_operand:SI 2 "s_operand" "Q"))])]
1384 int words = XVECLEN (operands[0], 0);
1386 if (XVECLEN (operands[0], 0) == 1)
1387 return \"l\\t%1,0(%2)\";
1389 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1390 return \"lm\\t%1,%0,%2\";
1392 [(set_attr "op_type" "RXE")
1393 (set_attr "atype" "mem")
1394 (set_attr "type" "lm")])
1397 ; store multiple pattern(s).
1400 (define_expand "store_multiple"
1401 [(match_par_dup 3 [(set (match_operand 0 "" "")
1402 (match_operand 1 "" ""))
1403 (use (match_operand 2 "" ""))])]
1412 /* Support only storing a constant number of fixed-point registers to
1413 memory and only bother with this if more than two. */
1414 if (GET_CODE (operands[2]) != CONST_INT
1415 || INTVAL (operands[2]) < 2
1416 || INTVAL (operands[2]) > 16
1417 || GET_CODE (operands[0]) != MEM
1418 || GET_CODE (operands[1]) != REG
1419 || REGNO (operands[1]) >= 16)
1422 count = INTVAL (operands[2]);
1423 regno = REGNO (operands[1]);
1425 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1429 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1431 to = XEXP (operands[0], 0);
1434 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1435 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1436 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1438 to = XEXP (XEXP (operands[0], 0), 0);
1439 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1444 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1449 to = force_reg (Pmode, XEXP (operands[0], 0));
1453 for (i = 0; i < count; i++)
1454 XVECEXP (operands[3], 0, i)
1455 = gen_rtx_SET (VOIDmode,
1456 change_address (operands[0], Pmode,
1458 off + i * UNITS_PER_WORD)),
1459 gen_rtx_REG (Pmode, regno + i));
1462 (define_insn "*store_multiple_di"
1463 [(match_parallel 0 "store_multiple_operation"
1464 [(set (match_operand:DI 1 "s_operand" "=Q")
1465 (match_operand:DI 2 "register_operand" "r"))])]
1469 int words = XVECLEN (operands[0], 0);
1471 if (XVECLEN (operands[0], 0) == 1)
1472 return \"stg\\t%1,0(%2)\";
1474 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1475 return \"stmg\\t%2,%0,%1\";
1477 [(set_attr "op_type" "RXE")
1478 (set_attr "atype" "mem")
1479 (set_attr "type" "stm")])
1482 (define_insn "*store_multiple_si"
1483 [(match_parallel 0 "store_multiple_operation"
1484 [(set (match_operand:SI 1 "s_operand" "=Q")
1485 (match_operand:SI 2 "register_operand" "r"))])]
1489 int words = XVECLEN (operands[0], 0);
1491 if (XVECLEN (operands[0], 0) == 1)
1492 return \"st\\t%1,0(%2)\";
1494 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1495 return \"stm\\t%2,%0,%1\";
1497 [(set_attr "op_type" "RXE")
1498 (set_attr "atype" "mem")
1499 (set_attr "type" "stm")])
1502 ;; String instructions.
1506 ; movstrdi instruction pattern(s).
1509 (define_expand "movstrdi"
1510 [(set (match_operand:BLK 0 "general_operand" "")
1511 (match_operand:BLK 1 "general_operand" ""))
1512 (use (match_operand:DI 2 "general_operand" ""))
1513 (match_operand 3 "" "")]
1519 addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1520 addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1522 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1524 operands[0] = change_address (operands[0], VOIDmode, addr0);
1525 operands[1] = change_address (operands[1], VOIDmode, addr1);
1526 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1528 emit_insn (gen_movstrdi_short (operands[0], operands[1], operands[2]));
1535 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1536 rtx reg0 = gen_reg_rtx (TImode);
1537 rtx reg1 = gen_reg_rtx (TImode);
1538 rtx len = operands[2];
1540 if (! CONSTANT_P (len))
1541 len = force_reg (DImode, len);
1543 /* Load up the address+length pairs. */
1545 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1546 emit_move_insn (gen_lowpart (DImode, reg0), len);
1548 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1549 emit_move_insn (gen_lowpart (DImode, reg1), len);
1552 emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
1557 rtx label1 = gen_label_rtx ();
1558 rtx label2 = gen_label_rtx ();
1559 rtx reg0, reg1, len, blocks;
1561 reg0 = gen_reg_rtx (DImode);
1562 reg1 = gen_reg_rtx (DImode);
1563 len = gen_reg_rtx (DImode);
1564 blocks = gen_reg_rtx (DImode);
1566 emit_move_insn (len, operands[2]);
1567 emit_insn (gen_cmpdi (len, const0_rtx));
1568 emit_jump_insn (gen_beq (label1));
1569 emit_move_insn (reg0, addr0);
1570 emit_move_insn (reg1, addr1);
1571 emit_insn (gen_adddi3 (len, len, constm1_rtx));
1572 emit_insn (gen_ashrdi3 (blocks, len, GEN_INT (8)));
1573 emit_insn (gen_cmpdi (blocks, const0_rtx));
1574 emit_jump_insn (gen_beq (label2));
1575 emit_insn (gen_movstrdi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1576 emit_label (label2);
1577 operands[0] = change_address (operands[0], VOIDmode, reg0);
1578 operands[1] = change_address (operands[1], VOIDmode, reg1);
1579 emit_insn (gen_movstrdi_short (operands[0], operands[1], len));
1580 emit_label (label1);
1587 ; movstrsi instruction pattern(s).
1590 (define_expand "movstrsi"
1591 [(set (match_operand:BLK 0 "general_operand" "")
1592 (match_operand:BLK 1 "general_operand" ""))
1593 (use (match_operand:SI 2 "general_operand" ""))
1594 (match_operand 3 "" "")]
1598 rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1599 rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1601 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1603 operands[0] = change_address (operands[0], VOIDmode, addr0);
1604 operands[1] = change_address (operands[1], VOIDmode, addr1);
1605 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1607 emit_insn (gen_movstrsi_short (operands[0], operands[1], operands[2]));
1614 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1615 rtx reg0 = gen_reg_rtx (DImode);
1616 rtx reg1 = gen_reg_rtx (DImode);
1617 rtx len = operands[2];
1620 if (! CONSTANT_P (len))
1621 len = force_reg (SImode, len);
1623 /* Load up the address+length pairs. */
1625 emit_move_insn (gen_highpart (SImode, reg0), addr0);
1626 emit_move_insn (gen_lowpart (SImode, reg0), len);
1628 emit_move_insn (gen_highpart (SImode, reg1), addr1);
1629 emit_move_insn (gen_lowpart (SImode, reg1), len);
1632 emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
1637 rtx label1 = gen_label_rtx ();
1638 rtx label2 = gen_label_rtx ();
1639 rtx reg0, reg1, len, blocks;
1641 reg0 = gen_reg_rtx (SImode);
1642 reg1 = gen_reg_rtx (SImode);
1643 len = gen_reg_rtx (SImode);
1644 blocks = gen_reg_rtx (SImode);
1646 emit_move_insn (len, operands[2]);
1647 emit_insn (gen_cmpsi (len, const0_rtx));
1648 emit_jump_insn (gen_beq (label1));
1649 emit_move_insn (reg0, addr0);
1650 emit_move_insn (reg1, addr1);
1651 emit_insn (gen_addsi3 (len, len, constm1_rtx));
1652 emit_insn (gen_ashrsi3 (blocks, len, GEN_INT (8)));
1653 emit_insn (gen_cmpsi (blocks, const0_rtx));
1654 emit_jump_insn (gen_beq (label2));
1655 emit_insn (gen_movstrsi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1656 emit_label (label2);
1657 operands[0] = change_address (operands[0], VOIDmode, reg0);
1658 operands[1] = change_address (operands[1], VOIDmode, reg1);
1659 emit_insn (gen_movstrsi_short (operands[0], operands[1], len));
1660 emit_label (label1);
1666 ; Move a block that is up to 256 bytes in length.
1667 ; The block length is taken as (operands[2] % 256) + 1.
1669 (define_insn "movstrdi_short"
1670 [(set (match_operand:BLK 0 "s_operand" "=Q,Q")
1671 (match_operand:BLK 1 "s_operand" "Q,Q"))
1672 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1673 (clobber (match_scratch:DI 3 "=X,&a"))]
1677 switch (which_alternative)
1680 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1683 output_asm_insn (\"bras\\t%3,.+10\", operands);
1684 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1685 return \"ex\\t%2,0(%3)\";
1691 [(set_attr "op_type" "SS,NN")
1692 (set_attr "atype" "mem,mem")
1693 (set_attr "length" "*,14")])
1695 (define_insn "movstrsi_short"
1696 [(set (match_operand:BLK 0 "s_operand" "=Q,Q")
1697 (match_operand:BLK 1 "s_operand" "Q,Q"))
1698 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1699 (clobber (match_scratch:SI 3 "=X,&a"))]
1703 switch (which_alternative)
1706 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1709 output_asm_insn (\"bras\\t%3,.+10\", operands);
1710 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1711 return \"ex\\t%2,0(%3)\";
1717 [(set_attr "op_type" "SS,NN")
1718 (set_attr "atype" "mem,mem")
1719 (set_attr "length" "*,14")])
1721 ; Move a block that is a multiple of 256 bytes in length
1723 (define_insn "movstrdi_long"
1724 [(set (match_operand:DI 4 "register_operand" "=d")
1726 (set (match_operand:DI 0 "register_operand" "=a")
1727 (plus:DI (match_operand:DI 2 "register_operand" "0")
1728 (ashift:DI (match_operand:DI 5 "register_operand" "4")
1730 (set (match_operand:DI 1 "register_operand" "=a")
1731 (plus:DI (match_operand:DI 3 "register_operand" "1")
1732 (ashift:DI (match_dup 5) (const_int 8))))
1733 (set (mem:BLK (match_dup 2))
1734 (mem:BLK (match_dup 3)))
1735 (use (match_dup 5))]
1739 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1740 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1741 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1742 return \"brct\\t%4,.-14\";
1744 [(set_attr "op_type" "NN")
1745 (set_attr "atype" "mem")
1746 (set_attr "length" "18")])
1748 (define_insn "movstrsi_long"
1749 [(set (match_operand:SI 4 "register_operand" "=d")
1751 (set (match_operand:SI 0 "register_operand" "=a")
1752 (plus:SI (match_operand:SI 2 "register_operand" "0")
1753 (ashift:SI (match_operand:SI 5 "register_operand" "4")
1755 (set (match_operand:SI 1 "register_operand" "=a")
1756 (plus:SI (match_operand:SI 3 "register_operand" "1")
1757 (ashift:SI (match_dup 5) (const_int 8))))
1758 (set (mem:BLK (match_dup 2))
1759 (mem:BLK (match_dup 3)))
1760 (use (match_dup 5))]
1764 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1765 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1766 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1767 return \"brct\\t%4,.-14\";
1769 [(set_attr "op_type" "NN")
1770 (set_attr "atype" "mem")
1771 (set_attr "length" "18")])
1773 ; Move a block that is larger than 255 bytes in length.
1775 (define_insn "movstrdi_64"
1776 [(set (match_operand:TI 0 "register_operand" "=d")
1777 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1778 (lshiftrt:TI (match_dup 2) (const_int 64)))
1780 (set (match_operand:TI 1 "register_operand" "=d")
1781 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1782 (lshiftrt:TI (match_dup 3) (const_int 64)))
1784 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1785 (mem:BLK (subreg:DI (match_dup 3) 0)))
1786 (clobber (reg:CC 33))]
1788 "mvcle\\t%0,%1,0\;jo\\t.-4"
1789 [(set_attr "op_type" "NN")
1790 (set_attr "atype" "mem")
1791 (set_attr "length" "8")])
1793 (define_insn "movstrsi_31"
1794 [(set (match_operand:DI 0 "register_operand" "=d")
1795 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1796 (lshiftrt:DI (match_dup 2) (const_int 32)))
1798 (set (match_operand:DI 1 "register_operand" "=d")
1799 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1800 (lshiftrt:DI (match_dup 3) (const_int 32)))
1802 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1803 (mem:BLK (subreg:SI (match_dup 3) 0)))
1804 (clobber (reg:CC 33))]
1806 "mvcle\\t%0,%1,0\;jo\\t.-4"
1807 [(set_attr "op_type" "NN")
1808 (set_attr "atype" "mem")
1809 (set_attr "length" "8")])
1812 ; clrstrdi instruction pattern(s).
1815 (define_expand "clrstrdi"
1816 [(set (match_operand:BLK 0 "general_operand" "")
1818 (use (match_operand:DI 1 "general_operand" ""))
1819 (match_operand 2 "" "")]
1823 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1825 operands[0] = change_address (operands[0], VOIDmode, addr);
1827 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1829 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1834 rtx reg0 = gen_reg_rtx (TImode);
1835 rtx reg1 = gen_reg_rtx (TImode);
1836 rtx len = operands[1];
1838 if (! CONSTANT_P (len))
1839 len = force_reg (DImode, len);
1841 /* Load up the address+length pairs. */
1843 emit_move_insn (gen_highpart (DImode, reg0), addr);
1844 emit_move_insn (gen_lowpart (DImode, reg0), len);
1846 emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
1849 emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0));
1855 ; clrstrsi instruction pattern(s).
1858 (define_expand "clrstrsi"
1859 [(set (match_operand:BLK 0 "general_operand" "")
1861 (use (match_operand:SI 1 "general_operand" ""))
1862 (match_operand 2 "" "")]
1866 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1868 operands[0] = change_address (operands[0], VOIDmode, addr);
1870 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1872 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1877 rtx reg0 = gen_reg_rtx (DImode);
1878 rtx reg1 = gen_reg_rtx (DImode);
1879 rtx len = operands[1];
1881 if (! CONSTANT_P (len))
1882 len = force_reg (SImode, len);
1884 /* Load up the address+length pairs. */
1886 emit_move_insn (gen_highpart (SImode, reg0), addr);
1887 emit_move_insn (gen_lowpart (SImode, reg0), len);
1889 emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
1892 emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0));
1897 ; Clear memory with length less than 256 bytes
1899 (define_insn "clrstrsico"
1900 [(set (match_operand:BLK 0 "s_operand" "=Q")
1902 (use (match_operand 1 "immediate_operand" "I"))
1903 (clobber (reg:CC 33))]
1905 "xc\\t%O0(%1,%R0),%0"
1906 [(set_attr "op_type" "RS")
1907 (set_attr "type" "cs")
1908 (set_attr "atype" "mem")])
1910 ; Clear memory with length greater 256 bytes or lenght not constant
1912 (define_insn "clrstrsi_64"
1913 [(set (match_operand:TI 0 "register_operand" "=d")
1914 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1915 (lshiftrt:TI (match_dup 2) (const_int 64)))
1917 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1919 (use (match_operand:TI 1 "register_operand" "d"))
1920 (clobber (reg:CC 33))]
1922 "mvcle\\t%0,%1,0\;jo\\t.-4"
1923 [(set_attr "op_type" "NN")
1924 (set_attr "atype" "mem")
1925 (set_attr "type" "vs")
1926 (set_attr "length" "8")])
1928 (define_insn "clrstrsi_31"
1929 [(set (match_operand:DI 0 "register_operand" "=d")
1930 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1931 (lshiftrt:DI (match_dup 2) (const_int 32)))
1933 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1935 (use (match_operand:DI 1 "register_operand" "d"))
1936 (clobber (reg:CC 33))]
1938 "mvcle\\t%0,%1,0\;jo\\t.-4"
1939 [(set_attr "op_type" "NN")
1940 (set_attr "atype" "mem")
1941 (set_attr "type" "vs")
1942 (set_attr "length" "8")])
1945 ; cmpstrdi instruction pattern(s).
1948 (define_expand "cmpstrdi"
1949 [(set (match_operand:DI 0 "register_operand" "")
1950 (compare:DI (match_operand:BLK 1 "general_operand" "")
1951 (match_operand:BLK 2 "general_operand" "") ) )
1952 (use (match_operand:DI 3 "general_operand" ""))
1953 (use (match_operand:DI 4 "" ""))]
1959 /* for pre/post increment */
1960 operands[1] = protect_from_queue (operands[1], 0);
1961 operands[2] = protect_from_queue (operands[2], 0);
1962 operands[3] = protect_from_queue (operands[3], 0);
1964 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1965 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1967 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1969 if (INTVAL (operands[3]) == 0) {
1970 emit_move_insn (operands[0], operands[3]);
1974 operands[1] = change_address (operands[1], VOIDmode, addr0);
1975 operands[2] = change_address (operands[2], VOIDmode, addr1);
1977 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1978 emit_insn (gen_cmpint_di (operands[0]));
1983 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1984 rtx reg0 = gen_reg_rtx (TImode);
1985 rtx reg1 = gen_reg_rtx (TImode);
1986 rtx len = operands[3];
1988 if (! CONSTANT_P (len))
1989 len = force_reg (DImode, len);
1991 /* Load up the address+length pairs. */
1992 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1993 emit_move_insn (gen_lowpart (DImode, reg0), len);
1995 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1996 emit_move_insn (gen_lowpart (DImode, reg1), len);
1999 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2000 emit_insn (gen_cmpint_di (operands[0]));
2006 ; cmpstrsi instruction pattern(s).
2009 (define_expand "cmpstrsi"
2010 [(set (match_operand:SI 0 "register_operand" "")
2011 (compare:SI (match_operand:BLK 1 "general_operand" "")
2012 (match_operand:BLK 2 "general_operand" "") ) )
2013 (use (match_operand:SI 3 "general_operand" ""))
2014 (use (match_operand:SI 4 "" ""))]
2020 /* for pre/post increment */
2021 operands[1] = protect_from_queue (operands[1], 0);
2022 operands[2] = protect_from_queue (operands[2], 0);
2023 operands[3] = protect_from_queue (operands[3], 0);
2025 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2026 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2028 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2030 if (INTVAL (operands[3]) == 0) {
2031 emit_move_insn (operands[0], operands[3]);
2035 operands[1] = change_address (operands[1], VOIDmode, addr0);
2036 operands[2] = change_address (operands[2], VOIDmode, addr1);
2038 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2039 emit_insn (gen_cmpint_si (operands[0]));
2044 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2046 rtx len = operands[3];
2050 reg0 = gen_reg_rtx (TImode);
2051 reg1 = gen_reg_rtx (TImode);
2055 reg0 = gen_reg_rtx (DImode);
2056 reg1 = gen_reg_rtx (DImode);
2059 if (! CONSTANT_P (len))
2060 len = force_reg (Pmode, len);
2062 /* Load up the address+length pairs. */
2063 emit_move_insn (gen_highpart (Pmode, reg0), addr0);
2064 emit_move_insn (gen_lowpart (Pmode, reg0), len);
2066 emit_move_insn (gen_highpart (Pmode, reg1), addr1);
2067 emit_move_insn (gen_lowpart (Pmode, reg1), len);
2071 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2073 emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
2075 emit_insn (gen_cmpint_si (operands[0]));
2080 ; Compare a block that is less than 256 bytes in length.
2082 (define_insn "cmpstr_const"
2084 (compare:CCS (match_operand:BLK 0 "s_operand" "Q")
2085 (match_operand:BLK 1 "s_operand" "Q")))
2086 (use (match_operand 2 "immediate_operand" "I"))]
2087 "(unsigned) INTVAL (operands[2]) < 256"
2088 "clc\\t%O0(%c2,%R0),%1"
2089 [(set_attr "op_type" "SS")
2090 (set_attr "atype" "mem")
2091 (set_attr "type" "cs")])
2093 ; Compare a block that is larger than 255 bytes in length.
2095 (define_insn "cmpstr_64"
2096 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2097 (clobber (match_operand:TI 1 "register_operand" "=d"))
2099 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2100 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2102 (use (match_dup 3))]
2105 [(set_attr "op_type" "RR")
2106 (set_attr "atype" "mem")
2107 (set_attr "type" "vs")])
2109 (define_insn "cmpstr_31"
2110 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2111 (clobber (match_operand:DI 1 "register_operand" "=d"))
2113 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2114 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2116 (use (match_dup 3))]
2119 [(set_attr "op_type" "RR")
2120 (set_attr "atype" "mem")
2121 (set_attr "type" "vs")])
2123 ; Convert condition code to integer in range (-1, 0, 1)
2125 (define_insn "cmpint_si"
2126 [(set (match_operand:SI 0 "register_operand" "=d")
2127 (compare:SI (reg:CCS 33) (const_int 0)))]
2131 output_asm_insn (\"lhi\\t%0,1\", operands);
2132 output_asm_insn (\"jh\\t.+12\", operands);
2133 output_asm_insn (\"jl\\t.+6\", operands);
2134 output_asm_insn (\"sr\\t%0,%0\", operands);
2135 return \"lcr\\t%0,%0\";
2137 [(set_attr "op_type" "NN")
2138 (set_attr "length" "16")
2139 (set_attr "atype" "reg")
2140 (set_attr "type" "other")])
2142 (define_insn "cmpint_di"
2143 [(set (match_operand:DI 0 "register_operand" "=d")
2144 (compare:DI (reg:CCS 33) (const_int 0)))]
2148 output_asm_insn (\"lghi\\t%0,1\", operands);
2149 output_asm_insn (\"jh\\t.+12\", operands);
2150 output_asm_insn (\"jl\\t.+6\", operands);
2151 output_asm_insn (\"sgr\\t%0,%0\", operands);
2152 return \"lcgr\\t%0,%0\";
2154 [(set_attr "op_type" "NN")
2155 (set_attr "length" "22")
2156 (set_attr "atype" "reg")
2157 (set_attr "type" "other")])
2161 ;;- Conversion instructions.
2164 (define_insn "*sethighqisi"
2165 [(set (match_operand:SI 0 "register_operand" "=d")
2166 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
2167 (clobber (reg:CC 33))]
2170 [(set_attr "op_type" "RS")
2171 (set_attr "atype" "mem")])
2173 (define_insn "*sethighhisi"
2174 [(set (match_operand:SI 0 "register_operand" "=d")
2175 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
2176 (clobber (reg:CC 33))]
2179 [(set_attr "op_type" "RS")
2180 (set_attr "atype" "mem")])
2182 (define_insn "*sethighqidi_64"
2183 [(set (match_operand:DI 0 "register_operand" "=d")
2184 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2185 (clobber (reg:CC 33))]
2188 [(set_attr "op_type" "RSE")
2189 (set_attr "atype" "mem")])
2191 (define_insn "*sethighqidi_31"
2192 [(set (match_operand:DI 0 "register_operand" "=d")
2193 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2194 (clobber (reg:CC 33))]
2197 [(set_attr "op_type" "RS")
2198 (set_attr "atype" "mem")])
2201 [(set (match_operand:SI 0 "register_operand" "")
2202 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2203 (match_operand 2 "const_int_operand" "")
2205 "!TARGET_64BIT && !reload_completed
2206 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2208 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2209 (clobber (reg:CC 33))])
2210 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2213 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2214 operands[1] = change_address (operands[1], QImode, 0);
2218 [(set (match_operand:SI 0 "register_operand" "")
2219 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2220 (match_operand 2 "const_int_operand" "")
2222 "!TARGET_64BIT && !reload_completed
2223 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2225 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2226 (clobber (reg:CC 33))])
2227 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2230 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2231 operands[1] = change_address (operands[1], HImode, 0);
2235 ; extendsidi2 instruction pattern(s).
2238 (define_expand "extendsidi2"
2239 [(set (match_operand:DI 0 "register_operand" "")
2240 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2246 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2247 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2248 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2249 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2255 (define_insn "*extendsidi2"
2256 [(set (match_operand:DI 0 "register_operand" "=d,d")
2257 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2262 [(set_attr "op_type" "RRE,RXE")
2263 (set_attr "atype" "reg,mem")])
2266 ; extendhidi2 instruction pattern(s).
2269 (define_expand "extendhidi2"
2270 [(set (match_operand:DI 0 "register_operand" "")
2271 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2277 rtx tmp = gen_reg_rtx (SImode);
2278 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2279 emit_insn (gen_extendsidi2 (operands[0], tmp));
2284 operands[1] = gen_lowpart (DImode, operands[1]);
2285 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2286 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2292 (define_insn "*extendhidi2"
2293 [(set (match_operand:DI 0 "register_operand" "=d")
2294 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2297 [(set_attr "op_type" "RXE")
2298 (set_attr "atype" "mem")])
2301 ; extendqidi2 instruction pattern(s).
2304 (define_expand "extendqidi2"
2305 [(set (match_operand:DI 0 "register_operand" "")
2306 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2312 rtx tmp = gen_reg_rtx (SImode);
2313 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2314 emit_insn (gen_extendsidi2 (operands[0], tmp));
2319 operands[1] = gen_lowpart (DImode, operands[1]);
2320 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2321 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2328 [(set (match_operand:DI 0 "register_operand" "")
2329 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2330 "TARGET_64BIT && !reload_completed"
2332 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2333 (clobber (reg:CC 33))])
2335 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2336 (clobber (reg:CC 33))])]
2340 ; extendhisi2 instruction pattern(s).
2343 (define_expand "extendhisi2"
2344 [(set (match_operand:SI 0 "register_operand" "")
2345 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2349 operands[1] = gen_lowpart (SImode, operands[1]);
2350 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2351 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2356 (define_insn "*extendhisi2"
2357 [(set (match_operand:SI 0 "register_operand" "=d")
2358 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2361 [(set_attr "op_type" "RX")
2362 (set_attr "atype" "mem")])
2365 ; extendqisi2 instruction pattern(s).
2368 (define_expand "extendqisi2"
2369 [(set (match_operand:SI 0 "register_operand" "")
2370 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2374 operands[1] = gen_lowpart (SImode, operands[1]);
2375 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2376 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2382 [(set (match_operand:SI 0 "register_operand" "")
2383 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2386 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2387 (clobber (reg:CC 33))])
2389 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2390 (clobber (reg:CC 33))])]
2394 ; extendqihi2 instruction pattern(s).
2399 ; zero_extendsidi2 instruction pattern(s).
2402 (define_expand "zero_extendsidi2"
2403 [(set (match_operand:DI 0 "register_operand" "")
2404 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2410 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2411 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2412 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2418 (define_insn "*zero_extendsidi2"
2419 [(set (match_operand:DI 0 "register_operand" "=d,d")
2420 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2425 [(set_attr "op_type" "RRE,RXE")
2426 (set_attr "atype" "reg,mem")])
2429 ; zero_extendhidi2 instruction pattern(s).
2432 (define_expand "zero_extendhidi2"
2433 [(set (match_operand:DI 0 "register_operand" "")
2434 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2440 rtx tmp = gen_reg_rtx (SImode);
2441 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2442 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2447 operands[1] = gen_lowpart (DImode, operands[1]);
2448 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2449 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2455 (define_insn "*zero_extendhidi2"
2456 [(set (match_operand:DI 0 "register_operand" "=d")
2457 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2460 [(set_attr "op_type" "RXE")
2461 (set_attr "atype" "mem")])
2464 ; zero_extendqidi2 instruction pattern(s)
2467 (define_expand "zero_extendqidi2"
2468 [(set (match_operand:DI 0 "register_operand" "")
2469 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2475 rtx tmp = gen_reg_rtx (SImode);
2476 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2477 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2482 operands[1] = gen_lowpart (DImode, operands[1]);
2483 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2484 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2490 (define_insn "*zero_extendqidi2"
2491 [(set (match_operand:DI 0 "register_operand" "=d")
2492 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2495 [(set_attr "op_type" "RXE")
2496 (set_attr "atype" "mem")])
2499 ; zero_extendhisi2 instruction pattern(s).
2502 (define_expand "zero_extendhisi2"
2503 [(set (match_operand:SI 0 "register_operand" "")
2504 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2508 operands[1] = gen_lowpart (SImode, operands[1]);
2509 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2514 (define_insn "*zero_extendhisi2_64"
2515 [(set (match_operand:SI 0 "register_operand" "=d")
2516 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2519 [(set_attr "op_type" "RXE")
2520 (set_attr "atype" "mem")])
2523 ; zero_extendqisi2 instruction pattern(s).
2526 (define_expand "zero_extendqisi2"
2527 [(set (match_operand:SI 0 "register_operand" "")
2528 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2532 operands[1] = gen_lowpart (SImode, operands[1]);
2533 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2538 (define_insn "*zero_extendqisi2_64"
2539 [(set (match_operand:SI 0 "register_operand" "=d")
2540 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2543 [(set_attr "op_type" "RXE")
2544 (set_attr "atype" "mem")])
2547 ; zero_extendqihi2 instruction pattern(s).
2550 (define_expand "zero_extendqihi2"
2551 [(set (match_operand:HI 0 "register_operand" "")
2552 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2556 operands[1] = gen_lowpart (HImode, operands[1]);
2557 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2562 (define_insn "*zero_extendqihi2_64"
2563 [(set (match_operand:HI 0 "register_operand" "=d")
2564 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2565 (clobber (reg:CC 33))]
2568 [(set_attr "op_type" "RXE")
2569 (set_attr "atype" "mem")])
2572 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2575 (define_expand "fixuns_truncdfdi2"
2576 [(set (match_operand:DI 0 "register_operand" "")
2577 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2578 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2581 rtx label1 = gen_label_rtx ();
2582 rtx label2 = gen_label_rtx ();
2583 rtx temp = gen_reg_rtx (DFmode);
2584 operands[1] = force_reg (DFmode, operands[1]);
2586 emit_insn (gen_cmpdf (operands[1],
2587 CONST_DOUBLE_FROM_REAL_VALUE (
2588 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2589 emit_jump_insn (gen_blt (label1));
2590 emit_insn (gen_subdf3 (temp, operands[1],
2591 CONST_DOUBLE_FROM_REAL_VALUE (
2592 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2593 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2596 emit_label (label1);
2597 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2598 emit_label (label2);
2602 (define_expand "fix_truncdfdi2"
2603 [(set (match_operand:DI 0 "register_operand" "")
2604 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2605 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2608 operands[1] = force_reg (DFmode, operands[1]);
2609 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2613 (define_insn "fix_truncdfdi2_ieee"
2614 [(set (match_operand:DI 0 "register_operand" "=d")
2615 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2616 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2617 (clobber (reg:CC 33))]
2618 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2620 [(set_attr "op_type" "RRE")
2621 (set_attr "type" "other")])
2624 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2627 (define_expand "fixuns_truncdfsi2"
2628 [(set (match_operand:SI 0 "register_operand" "")
2629 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2630 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2633 rtx label1 = gen_label_rtx ();
2634 rtx label2 = gen_label_rtx ();
2635 rtx temp = gen_reg_rtx (DFmode);
2637 operands[1] = force_reg (DFmode,operands[1]);
2638 emit_insn (gen_cmpdf (operands[1],
2639 CONST_DOUBLE_FROM_REAL_VALUE (
2640 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2641 emit_jump_insn (gen_blt (label1));
2642 emit_insn (gen_subdf3 (temp, operands[1],
2643 CONST_DOUBLE_FROM_REAL_VALUE (
2644 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2645 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2648 emit_label (label1);
2649 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2650 emit_label (label2);
2654 (define_expand "fix_truncdfsi2"
2655 [(set (match_operand:SI 0 "register_operand" "")
2656 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2660 if (TARGET_IBM_FLOAT)
2662 /* This is the algorithm from POP chapter A.5.7.2. */
2664 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2665 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2666 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2668 operands[1] = force_reg (DFmode, operands[1]);
2669 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2670 two31r, two32, temp));
2674 operands[1] = force_reg (DFmode, operands[1]);
2675 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2681 (define_insn "fix_truncdfsi2_ieee"
2682 [(set (match_operand:SI 0 "register_operand" "=d")
2683 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2684 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2685 (clobber (reg:CC 33))]
2686 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2688 [(set_attr "op_type" "RRE")
2689 (set_attr "type" "other" )])
2691 (define_insn "fix_truncdfsi2_ibm"
2692 [(set (match_operand:SI 0 "register_operand" "=d")
2693 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2694 (use (match_operand:DI 2 "immediate_operand" "m"))
2695 (use (match_operand:DI 3 "immediate_operand" "m"))
2696 (use (match_operand:BLK 4 "memory_operand" "m"))
2697 (clobber (reg:CC 33))]
2698 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2701 output_asm_insn (\"sd\\t%1,%2\", operands);
2702 output_asm_insn (\"aw\\t%1,%3\", operands);
2703 output_asm_insn (\"std\\t%1,%4\", operands);
2704 output_asm_insn (\"xi\\t%N4,128\", operands);
2705 return \"l\\t%0,%N4\";
2707 [(set_attr "op_type" "NN")
2708 (set_attr "type" "other")
2709 (set_attr "length" "20")])
2712 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2715 (define_expand "fixuns_truncsfdi2"
2716 [(set (match_operand:DI 0 "register_operand" "")
2717 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2718 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2721 rtx label1 = gen_label_rtx ();
2722 rtx label2 = gen_label_rtx ();
2723 rtx temp = gen_reg_rtx (SFmode);
2725 operands[1] = force_reg (SFmode, operands[1]);
2726 emit_insn (gen_cmpsf (operands[1],
2727 CONST_DOUBLE_FROM_REAL_VALUE (
2728 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2729 emit_jump_insn (gen_blt (label1));
2731 emit_insn (gen_subsf3 (temp, operands[1],
2732 CONST_DOUBLE_FROM_REAL_VALUE (
2733 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2734 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2737 emit_label (label1);
2738 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2739 emit_label (label2);
2743 (define_expand "fix_truncsfdi2"
2744 [(set (match_operand:DI 0 "register_operand" "")
2745 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2746 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2749 operands[1] = force_reg (SFmode, operands[1]);
2750 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2754 (define_insn "fix_truncsfdi2_ieee"
2755 [(set (match_operand:DI 0 "register_operand" "=d")
2756 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2757 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2758 (clobber (reg:CC 33))]
2759 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2761 [(set_attr "op_type" "RRE")
2762 (set_attr "type" "other")])
2765 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2768 (define_expand "fixuns_truncsfsi2"
2769 [(set (match_operand:SI 0 "register_operand" "")
2770 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2771 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2774 rtx label1 = gen_label_rtx ();
2775 rtx label2 = gen_label_rtx ();
2776 rtx temp = gen_reg_rtx (SFmode);
2778 operands[1] = force_reg (SFmode, operands[1]);
2779 emit_insn (gen_cmpsf (operands[1],
2780 CONST_DOUBLE_FROM_REAL_VALUE (
2781 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2782 emit_jump_insn (gen_blt (label1));
2783 emit_insn (gen_subsf3 (temp, operands[1],
2784 CONST_DOUBLE_FROM_REAL_VALUE (
2785 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2786 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2789 emit_label (label1);
2790 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2791 emit_label (label2);
2795 (define_expand "fix_truncsfsi2"
2796 [(set (match_operand:SI 0 "register_operand" "")
2797 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2801 if (TARGET_IBM_FLOAT)
2803 /* Convert to DFmode and then use the POP algorithm. */
2804 rtx temp = gen_reg_rtx (DFmode);
2805 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2806 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2810 operands[1] = force_reg (SFmode, operands[1]);
2811 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2817 (define_insn "fix_truncsfsi2_ieee"
2818 [(set (match_operand:SI 0 "register_operand" "=d")
2819 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2820 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2821 (clobber (reg:CC 33))]
2822 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2824 [(set_attr "op_type" "RRE")
2825 (set_attr "type" "other")])
2828 ; floatdidf2 instruction pattern(s).
2831 (define_insn "floatdidf2"
2832 [(set (match_operand:DF 0 "register_operand" "=f")
2833 (float:DF (match_operand:DI 1 "register_operand" "d")))
2834 (clobber (reg:CC 33))]
2835 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2837 [(set_attr "op_type" "RRE")
2838 (set_attr "type" "other" )])
2841 ; floatdisf2 instruction pattern(s).
2844 (define_insn "floatdisf2"
2845 [(set (match_operand:SF 0 "register_operand" "=f")
2846 (float:SF (match_operand:DI 1 "register_operand" "d")))
2847 (clobber (reg:CC 33))]
2848 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2850 [(set_attr "op_type" "RRE")
2851 (set_attr "type" "other" )])
2854 ; floatsidf2 instruction pattern(s).
2857 (define_expand "floatsidf2"
2859 [(set (match_operand:DF 0 "register_operand" "")
2860 (float:DF (match_operand:SI 1 "register_operand" "")))
2861 (clobber (reg:CC 33))])]
2865 if (TARGET_IBM_FLOAT)
2867 /* This is the algorithm from POP chapter A.5.7.1. */
2869 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2870 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2872 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2877 (define_insn "floatsidf2_ieee"
2878 [(set (match_operand:DF 0 "register_operand" "=f")
2879 (float:DF (match_operand:SI 1 "register_operand" "d")))
2880 (clobber (reg:CC 33))]
2881 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2883 [(set_attr "op_type" "RRE")
2884 (set_attr "type" "other" )])
2886 (define_insn "floatsidf2_ibm"
2887 [(set (match_operand:DF 0 "register_operand" "=f")
2888 (float:DF (match_operand:SI 1 "register_operand" "d")))
2889 (use (match_operand:DI 2 "immediate_operand" "m"))
2890 (use (match_operand:BLK 3 "memory_operand" "m"))
2891 (clobber (reg:CC 33))]
2892 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2895 output_asm_insn (\"st\\t%1,%N3\", operands);
2896 output_asm_insn (\"xi\\t%N3,128\", operands);
2897 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2898 output_asm_insn (\"ld\\t%0,%3\", operands);
2899 return \"sd\\t%0,%2\";
2901 [(set_attr "op_type" "NN")
2902 (set_attr "type" "other" )
2903 (set_attr "length" "20")])
2906 ; floatsisf2 instruction pattern(s).
2909 (define_expand "floatsisf2"
2911 [(set (match_operand:SF 0 "register_operand" "")
2912 (float:SF (match_operand:SI 1 "register_operand" "")))
2913 (clobber (reg:CC 33))])]
2917 if (TARGET_IBM_FLOAT)
2919 /* Use the POP algorithm to convert to DFmode and then truncate. */
2920 rtx temp = gen_reg_rtx (DFmode);
2921 emit_insn (gen_floatsidf2 (temp, operands[1]));
2922 emit_insn (gen_truncdfsf2 (operands[0], temp));
2927 (define_insn "floatsisf2_ieee"
2928 [(set (match_operand:SF 0 "register_operand" "=f")
2929 (float:SF (match_operand:SI 1 "register_operand" "d")))
2930 (clobber (reg:CC 33))]
2931 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2933 [(set_attr "op_type" "RRE")
2934 (set_attr "type" "other" )])
2937 ; truncdfsf2 instruction pattern(s).
2940 (define_expand "truncdfsf2"
2941 [(set (match_operand:SF 0 "register_operand" "")
2942 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2946 (define_insn "truncdfsf2_ieee"
2947 [(set (match_operand:SF 0 "register_operand" "=f")
2948 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2949 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2951 [(set_attr "op_type" "RRE")])
2953 (define_insn "truncdfsf2_ibm"
2954 [(set (match_operand:SF 0 "register_operand" "=f,f")
2955 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2956 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2960 [(set_attr "op_type" "RR,RX")
2961 (set_attr "atype" "reg,mem")])
2964 ; extendsfdf2 instruction pattern(s).
2967 (define_expand "extendsfdf2"
2968 [(set (match_operand:DF 0 "register_operand" "")
2969 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2973 if (TARGET_IBM_FLOAT)
2975 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2980 (define_insn "extendsfdf2_ieee"
2981 [(set (match_operand:DF 0 "register_operand" "=f,f")
2982 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2983 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2987 [(set_attr "op_type" "RRE,RXE")])
2989 (define_insn "extendsfdf2_ibm"
2990 [(set (match_operand:DF 0 "register_operand" "=f,f")
2991 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2992 (clobber (reg:CC 33))]
2993 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2995 sdr\\t%0,%0\;ler\\t%0,%1
2996 sdr\\t%0,%0\;le\\t%0,%1"
2997 [(set_attr "op_type" "RRE,RXE")
2998 (set_attr "atype" "reg,mem")
2999 (set_attr "type" "o2,o2")])
3003 ;; ARITHMETRIC OPERATIONS
3005 ; arithmetric operations set the ConditionCode,
3006 ; because of unpredictable Bits in Register for Halfword and Byte
3007 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3010 ;;- Add instructions.
3014 ; adddi3 instruction pattern(s).
3017 (define_insn "addaddr_esame"
3018 [(set (match_operand:DI 0 "register_operand" "=a,a")
3019 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
3020 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
3021 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3022 (REGNO (operands[1]) == BASE_REGISTER)) &&
3023 (GET_CODE (operands[2]) == REG ||
3024 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3028 [(set_attr "op_type" "RX")
3029 (set_attr "atype" "mem")
3030 (set_attr "type" "la")])
3032 (define_insn "*adddi3_sign"
3033 [(set (match_operand:DI 0 "register_operand" "=d,d")
3034 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3035 (match_operand:DI 1 "register_operand" "0,0")))
3036 (clobber (reg:CC 33))]
3041 [(set_attr "op_type" "RRE,RXE")
3042 (set_attr "atype" "reg,mem")])
3044 (define_insn "*adddi3_zero_cc"
3046 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3047 (match_operand:DI 1 "register_operand" "0,0"))
3049 (set (match_operand:DI 0 "register_operand" "=d,d")
3050 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3051 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3055 [(set_attr "op_type" "RRE,RXE")
3056 (set_attr "atype" "reg,mem")])
3058 (define_insn "*adddi3_zero_cconly"
3060 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3061 (match_operand:DI 1 "register_operand" "0,0"))
3063 (clobber (match_scratch:DI 0 "=d,d"))]
3064 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3068 [(set_attr "op_type" "RRE,RXE")
3069 (set_attr "atype" "reg,mem")])
3071 (define_insn "*adddi3_zero"
3072 [(set (match_operand:DI 0 "register_operand" "=d,d")
3073 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3074 (match_operand:DI 1 "register_operand" "0,0")))
3075 (clobber (reg:CC 33))]
3080 [(set_attr "op_type" "RRE,RXE")
3081 (set_attr "atype" "reg,mem")])
3083 (define_insn "*adddi3_cc"
3085 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3086 (match_operand:DI 2 "general_operand" "d,m"))
3088 (set (match_operand:DI 0 "register_operand" "=d,d")
3089 (plus:DI (match_dup 1) (match_dup 2)))]
3090 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3094 [(set_attr "op_type" "RRE,RXE")
3095 (set_attr "atype" "reg,mem")])
3097 (define_insn "*adddi3_cconly"
3099 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3100 (match_operand:DI 2 "general_operand" "d,m"))
3102 (clobber (match_scratch:DI 0 "=d,d"))]
3103 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3107 [(set_attr "op_type" "RRE,RXE")
3108 (set_attr "atype" "reg,mem")])
3110 (define_insn "*adddi3_cconly2"
3112 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3113 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3114 (clobber (match_scratch:DI 0 "=d,d"))]
3115 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3119 [(set_attr "op_type" "RRE,RXE")
3120 (set_attr "atype" "reg,mem")])
3122 (define_insn "*adddi3_64"
3123 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3124 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3125 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3126 (clobber (reg:CC 33))]
3132 [(set_attr "op_type" "RRE,RI,RXE")
3133 (set_attr "atype" "reg,reg,mem")])
3135 (define_insn_and_split "*adddi3_31"
3136 [(set (match_operand:DI 0 "register_operand" "=&d")
3137 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3138 (match_operand:DI 2 "general_operand" "dm") ) )
3139 (clobber (reg:CC 33))]
3142 "&& reload_completed"
3144 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3145 (clobber (reg:CC 33))])
3148 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3150 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3152 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3154 (label_ref (match_dup 9))))
3156 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3157 (clobber (reg:CC 33))])
3159 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3160 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3161 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3162 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3163 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3164 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3165 operands[9] = gen_label_rtx ();"
3166 [(set_attr "op_type" "NN")
3167 (set_attr "type" "o3")])
3169 (define_expand "adddi3"
3171 [(set (match_operand:DI 0 "register_operand" "")
3172 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3173 (match_operand:DI 2 "general_operand" "")))
3174 (clobber (reg:CC 33))])]
3178 (define_insn "*la_64"
3179 [(set (match_operand:DI 0 "register_operand" "=d")
3180 (match_operand:QI 1 "address_operand" "p"))]
3183 [(set_attr "op_type" "RX")
3184 (set_attr "atype" "mem")
3185 (set_attr "type" "la")])
3187 (define_expand "reload_indi"
3188 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3189 (match_operand:DI 1 "s390_plus_operand" "")
3190 (match_operand:DI 2 "register_operand" "=&a")])]
3194 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3200 ; addsi3 instruction pattern(s).
3203 (define_insn "*la_ccclobber"
3204 [(set (match_operand:SI 0 "register_operand" "=d")
3205 (match_operand:QI 1 "address_operand" "p"))
3206 (clobber (reg:CC 33))]
3207 "legitimate_la_operand_p (operands[1])"
3209 [(set_attr "op_type" "RX")
3210 (set_attr "atype" "mem")
3211 (set_attr "type" "la")])
3213 (define_insn "*addsi3_carry1_cc"
3215 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3216 (match_operand:SI 2 "general_operand" "d,m"))
3218 (set (match_operand:SI 0 "register_operand" "=d,d")
3219 (plus:SI (match_dup 1) (match_dup 2)))]
3220 "s390_match_ccmode (insn, CCL1mode)"
3224 [(set_attr "op_type" "RR,RX")
3225 (set_attr "atype" "reg,mem")])
3227 (define_insn "*addsi3_carry1_cconly"
3229 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3230 (match_operand:SI 2 "general_operand" "d,m"))
3232 (clobber (match_scratch:SI 0 "=d,d"))]
3233 "s390_match_ccmode (insn, CCL1mode)"
3237 [(set_attr "op_type" "RR,RX")
3238 (set_attr "atype" "reg,mem")])
3240 (define_insn "*addsi3_carry2_cc"
3242 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3243 (match_operand:SI 2 "general_operand" "d,m"))
3245 (set (match_operand:SI 0 "register_operand" "=d,d")
3246 (plus:SI (match_dup 1) (match_dup 2)))]
3247 "s390_match_ccmode (insn, CCL1mode)"
3251 [(set_attr "op_type" "RR,RX")
3252 (set_attr "atype" "reg,mem")])
3254 (define_insn "*addsi3_carry2_cconly"
3256 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3257 (match_operand:SI 2 "general_operand" "d,m"))
3259 (clobber (match_scratch:SI 0 "=d,d"))]
3260 "s390_match_ccmode (insn, CCL1mode)"
3264 [(set_attr "op_type" "RR,RX")
3265 (set_attr "atype" "reg,mem")])
3267 (define_insn "*addsi3_cc"
3269 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3270 (match_operand:SI 2 "general_operand" "d,m"))
3272 (set (match_operand:SI 0 "register_operand" "=d,d")
3273 (plus:SI (match_dup 1) (match_dup 2)))]
3274 "s390_match_ccmode (insn, CCLmode)"
3278 [(set_attr "op_type" "RR,RX")
3279 (set_attr "atype" "reg,mem")])
3281 (define_insn "*addsi3_cconly"
3283 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3284 (match_operand:SI 2 "general_operand" "d,m"))
3286 (clobber (match_scratch:SI 0 "=d,d"))]
3287 "s390_match_ccmode (insn, CCLmode)"
3291 [(set_attr "op_type" "RR,RX")
3292 (set_attr "atype" "reg,mem")])
3294 (define_insn "*addsi3_cconly2"
3296 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3297 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3298 (clobber (match_scratch:SI 0 "=d,d"))]
3299 "s390_match_ccmode(insn, CCLmode)"
3303 [(set_attr "op_type" "RR,RX")
3304 (set_attr "atype" "reg,mem")])
3306 (define_insn "*addsi3_sign"
3307 [(set (match_operand:SI 0 "register_operand" "=d")
3308 (plus:SI (match_operand:SI 1 "register_operand" "0")
3309 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3310 (clobber (reg:CC 33))]
3313 [(set_attr "op_type" "RX")
3314 (set_attr "atype" "mem")])
3316 (define_insn "*addsi3_sub"
3317 [(set (match_operand:SI 0 "register_operand" "=d")
3318 (plus:SI (match_operand:SI 1 "register_operand" "0")
3319 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3320 (clobber (reg:CC 33))]
3323 [(set_attr "op_type" "RX")
3324 (set_attr "atype" "mem")])
3326 (define_insn "addsi3"
3327 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3328 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3329 (match_operand:SI 2 "general_operand" "d,K,m")))
3330 (clobber (reg:CC 33))]
3336 [(set_attr "op_type" "RR,RI,RX")
3337 (set_attr "atype" "reg,reg,mem")])
3339 (define_insn "*la_31"
3340 [(set (match_operand:SI 0 "register_operand" "=d")
3341 (match_operand:QI 1 "address_operand" "p"))]
3342 "legitimate_la_operand_p (operands[1])"
3344 [(set_attr "op_type" "RX")
3345 (set_attr "atype" "mem")
3346 (set_attr "type" "la")])
3348 (define_expand "reload_insi"
3349 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3350 (match_operand:SI 1 "s390_plus_operand" "")
3351 (match_operand:SI 2 "register_operand" "=&a")])]
3355 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3361 ; adddf3 instruction pattern(s).
3364 (define_expand "adddf3"
3366 [(set (match_operand:DF 0 "register_operand" "=f,f")
3367 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3368 (match_operand:DF 2 "general_operand" "f,m")))
3369 (clobber (reg:CC 33))])]
3373 (define_insn "*adddf3"
3374 [(set (match_operand:DF 0 "register_operand" "=f,f")
3375 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3376 (match_operand:DF 2 "general_operand" "f,m")))
3377 (clobber (reg:CC 33))]
3378 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3382 [(set_attr "op_type" "RRE,RXE")
3383 (set_attr "atype" "reg,mem")])
3385 (define_insn "*adddf3_ibm"
3386 [(set (match_operand:DF 0 "register_operand" "=f,f")
3387 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3388 (match_operand:DF 2 "general_operand" "f,m")))
3389 (clobber (reg:CC 33))]
3390 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3394 [(set_attr "op_type" "RR,RX")
3395 (set_attr "atype" "reg,mem")])
3398 ; addsf3 instruction pattern(s).
3401 (define_expand "addsf3"
3403 [(set (match_operand:SF 0 "register_operand" "=f,f")
3404 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3405 (match_operand:SF 2 "general_operand" "f,m")))
3406 (clobber (reg:CC 33))])]
3410 (define_insn "*addsf3"
3411 [(set (match_operand:SF 0 "register_operand" "=f,f")
3412 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3413 (match_operand:SF 2 "general_operand" "f,m")))
3414 (clobber (reg:CC 33))]
3415 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3419 [(set_attr "op_type" "RRE,RXE")
3420 (set_attr "atype" "reg,mem")])
3422 (define_insn "*addsf3"
3423 [(set (match_operand:SF 0 "register_operand" "=f,f")
3424 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3425 (match_operand:SF 2 "general_operand" "f,m")))
3426 (clobber (reg:CC 33))]
3427 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3431 [(set_attr "op_type" "RR,RX")
3432 (set_attr "atype" "reg,mem")])
3436 ;;- Subtract instructions.
3440 ; subdi3 instruction pattern(s).
3443 (define_insn "*subdi3_sign"
3444 [(set (match_operand:DI 0 "register_operand" "=d,d")
3445 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3446 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3447 (clobber (reg:CC 33))]
3452 [(set_attr "op_type" "RRE,RXE")
3453 (set_attr "atype" "reg,mem")])
3455 (define_insn "*subdi3_zero_cc"
3457 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3458 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3460 (set (match_operand:DI 0 "register_operand" "=d,d")
3461 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3462 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3466 [(set_attr "op_type" "RRE,RXE")
3467 (set_attr "atype" "reg,mem")])
3469 (define_insn "*subdi3_zero_cconly"
3471 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3472 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3474 (clobber (match_scratch:DI 0 "=d,d"))]
3475 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3479 [(set_attr "op_type" "RRE,RXE")
3480 (set_attr "atype" "reg,mem")])
3482 (define_insn "*subdi3_zero"
3483 [(set (match_operand:DI 0 "register_operand" "=d,d")
3484 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3485 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3486 (clobber (reg:CC 33))]
3491 [(set_attr "op_type" "RRE,RXE")
3492 (set_attr "atype" "reg,mem")])
3494 (define_insn "*subdi3_cc"
3496 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3497 (match_operand:DI 2 "general_operand" "d,m"))
3499 (set (match_operand:DI 0 "register_operand" "=d,d")
3500 (minus:DI (match_dup 1) (match_dup 2)))]
3501 "s390_match_ccmode (insn, CCLmode)"
3505 [(set_attr "op_type" "RRE,RXE")
3506 (set_attr "atype" "reg,mem")])
3508 (define_insn "*subdi3_cconly"
3510 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3511 (match_operand:DI 2 "general_operand" "d,m"))
3513 (clobber (match_scratch:DI 0 "=d,d"))]
3514 "s390_match_ccmode (insn, CCLmode)"
3518 [(set_attr "op_type" "RRE,RXE")
3519 (set_attr "atype" "reg,mem")])
3521 (define_insn "*subdi3_64"
3522 [(set (match_operand:DI 0 "register_operand" "=d,d")
3523 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3524 (match_operand:DI 2 "general_operand" "d,m") ) )
3525 (clobber (reg:CC 33))]
3530 [(set_attr "op_type" "RRE,RRE")
3531 (set_attr "atype" "reg,mem")])
3533 (define_insn_and_split "*subdi3_31"
3534 [(set (match_operand:DI 0 "register_operand" "=&d")
3535 (minus:DI (match_operand:DI 1 "register_operand" "0")
3536 (match_operand:DI 2 "general_operand" "dm") ) )
3537 (clobber (reg:CC 33))]
3540 "&& reload_completed"
3542 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3543 (clobber (reg:CC 33))])
3546 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3548 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3550 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3552 (label_ref (match_dup 9))))
3554 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3555 (clobber (reg:CC 33))])
3557 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3558 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3559 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3560 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3561 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3562 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3563 operands[9] = gen_label_rtx ();"
3564 [(set_attr "op_type" "NN")
3565 (set_attr "type" "o3")])
3567 (define_expand "subdi3"
3569 [(set (match_operand:DI 0 "register_operand" "")
3570 (minus:DI (match_operand:DI 1 "register_operand" "")
3571 (match_operand:DI 2 "general_operand" "")))
3572 (clobber (reg:CC 33))])]
3577 ; subsi3 instruction pattern(s).
3580 (define_insn "*subsi3_borrow_cc"
3582 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3583 (match_operand:SI 2 "general_operand" "d,m"))
3585 (set (match_operand:SI 0 "register_operand" "=d,d")
3586 (minus:SI (match_dup 1) (match_dup 2)))]
3587 "s390_match_ccmode(insn, CCL2mode)"
3591 [(set_attr "op_type" "RR,RX")
3592 (set_attr "atype" "reg,mem")])
3594 (define_insn "*subsi3_borrow_cconly"
3596 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3597 (match_operand:SI 2 "general_operand" "d,m"))
3599 (clobber (match_scratch:SI 0 "=d,d"))]
3600 "s390_match_ccmode(insn, CCL2mode)"
3604 [(set_attr "op_type" "RR,RX")
3605 (set_attr "atype" "reg,mem")])
3607 (define_insn "*subsi3_cc"
3609 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3610 (match_operand:SI 2 "general_operand" "d,m"))
3612 (set (match_operand:SI 0 "register_operand" "=d,d")
3613 (minus:SI (match_dup 1) (match_dup 2)))]
3614 "s390_match_ccmode(insn, CCLmode)"
3618 [(set_attr "op_type" "RR,RX")
3619 (set_attr "atype" "reg,mem")])
3621 (define_insn "*subsi3_cconly"
3623 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3624 (match_operand:SI 2 "general_operand" "d,m"))
3626 (clobber (match_scratch:SI 0 "=d,d"))]
3627 "s390_match_ccmode(insn, CCLmode)"
3631 [(set_attr "op_type" "RR,RX")
3632 (set_attr "atype" "reg,mem")])
3634 (define_insn "*subsi3_sign"
3635 [(set (match_operand:SI 0 "register_operand" "=d")
3636 (minus:SI (match_operand:SI 1 "register_operand" "0")
3637 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3638 (clobber (reg:CC 33))]
3641 [(set_attr "op_type" "RX")
3642 (set_attr "atype" "mem")])
3644 (define_insn "*subsi3_sub"
3645 [(set (match_operand:SI 0 "register_operand" "=d")
3646 (minus:SI (match_operand:SI 1 "register_operand" "0")
3647 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3648 (clobber (reg:CC 33))]
3651 [(set_attr "op_type" "RX")
3652 (set_attr "atype" "mem")])
3654 (define_insn "subsi3"
3655 [(set (match_operand:SI 0 "register_operand" "=d,d")
3656 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3657 (match_operand:SI 2 "general_operand" "d,m")))
3658 (clobber (reg:CC 33))]
3663 [(set_attr "op_type" "RR,RX")
3664 (set_attr "atype" "reg,mem")])
3668 ; subdf3 instruction pattern(s).
3671 (define_expand "subdf3"
3673 [(set (match_operand:DF 0 "register_operand" "=f,f")
3674 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3675 (match_operand:DF 2 "general_operand" "f,m")))
3676 (clobber (reg:CC 33))])]
3680 (define_insn "*subdf3"
3681 [(set (match_operand:DF 0 "register_operand" "=f,f")
3682 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3683 (match_operand:DF 2 "general_operand" "f,m")))
3684 (clobber (reg:CC 33))]
3685 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3689 [(set_attr "op_type" "RRE,RXE")
3690 (set_attr "atype" "reg,mem")])
3692 (define_insn "*subdf3_ibm"
3693 [(set (match_operand:DF 0 "register_operand" "=f,f")
3694 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3695 (match_operand:DF 2 "general_operand" "f,m")))
3696 (clobber (reg:CC 33))]
3697 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3701 [(set_attr "op_type" "RR,RX")
3702 (set_attr "atype" "reg,mem")])
3705 ; subsf3 instruction pattern(s).
3708 (define_expand "subsf3"
3710 [(set (match_operand:SF 0 "register_operand" "=f,f")
3711 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3712 (match_operand:SF 2 "general_operand" "f,m")))
3713 (clobber (reg:CC 33))])]
3717 (define_insn "*subsf3"
3718 [(set (match_operand:SF 0 "register_operand" "=f,f")
3719 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3720 (match_operand:SF 2 "general_operand" "f,m")))
3721 (clobber (reg:CC 33))]
3722 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3726 [(set_attr "op_type" "RRE,RXE")
3727 (set_attr "atype" "reg,mem")])
3729 (define_insn "*subsf3_ibm"
3730 [(set (match_operand:SF 0 "register_operand" "=f,f")
3731 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3732 (match_operand:SF 2 "general_operand" "f,m")))
3733 (clobber (reg:CC 33))]
3734 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3738 [(set_attr "op_type" "RR,RX")
3739 (set_attr "atype" "reg,mem")])
3743 ;;- Multiply instructions.
3747 ; muldi3 instruction pattern(s).
3750 (define_insn "*muldi3_sign"
3751 [(set (match_operand:DI 0 "register_operand" "=d,d")
3752 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3753 (match_operand:DI 1 "register_operand" "0,0")))]
3758 [(set_attr "op_type" "RRE,RXE")
3759 (set_attr "atype" "reg,mem")
3760 (set_attr "type" "imul")])
3763 (define_insn "muldi3"
3764 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3765 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3766 (match_operand:DI 2 "general_operand" "d,K,m")))]
3772 [(set_attr "op_type" "RRE,RI,RXE")
3773 (set_attr "atype" "reg,reg,mem")
3774 (set_attr "type" "imul")])
3777 ; mulsi3 instruction pattern(s).
3780 (define_insn "mulsi3"
3781 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3782 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3783 (match_operand:SI 2 "general_operand" "d,K,m")))]
3789 [(set_attr "op_type" "RRE,RI,RX")
3790 (set_attr "atype" "reg,reg,mem")
3791 (set_attr "type" "imul")])
3794 ; mulsidi3 instruction pattern(s).
3797 (define_expand "mulsidi3"
3798 [(set (match_operand:DI 0 "register_operand" "")
3799 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3800 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3806 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3807 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3810 gen_rtx_EXPR_LIST (REG_EQUAL,
3811 gen_rtx_MULT (DImode,
3812 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3813 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3818 (define_insn "mulsi_6432"
3819 [(set (match_operand:DI 0 "register_operand" "=d,d")
3820 (mult:DI (sign_extend:DI
3821 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3823 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3828 [(set_attr "op_type" "RR,RX")
3829 (set_attr "atype" "reg,mem")
3830 (set_attr "type" "imul")])
3833 ; muldf3 instruction pattern(s).
3836 (define_expand "muldf3"
3838 [(set (match_operand:DF 0 "register_operand" "=f,f")
3839 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3840 (match_operand:DF 2 "general_operand" "f,m")))
3841 (clobber (reg:CC 33))])]
3845 (define_insn "*muldf3"
3846 [(set (match_operand:DF 0 "register_operand" "=f,f")
3847 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3848 (match_operand:DF 2 "general_operand" "f,m")))
3849 (clobber (reg:CC 33))]
3850 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3854 [(set_attr "op_type" "RRE,RXE")
3855 (set_attr "type" "fmul")
3856 (set_attr "atype" "reg,mem")])
3858 (define_insn "*muldf3_ibm"
3859 [(set (match_operand:DF 0 "register_operand" "=f,f")
3860 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3861 (match_operand:DF 2 "general_operand" "f,m")))
3862 (clobber (reg:CC 33))]
3863 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3867 [(set_attr "op_type" "RR,RX")
3868 (set_attr "type" "fmul")
3869 (set_attr "atype" "reg,mem")])
3872 ; mulsf3 instruction pattern(s).
3875 (define_expand "mulsf3"
3877 [(set (match_operand:SF 0 "register_operand" "=f,f")
3878 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3879 (match_operand:SF 2 "general_operand" "f,m")))
3880 (clobber (reg:CC 33))])]
3884 (define_insn "*mulsf3"
3885 [(set (match_operand:SF 0 "register_operand" "=f,f")
3886 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3887 (match_operand:SF 2 "general_operand" "f,m")))
3888 (clobber (reg:CC 33))]
3889 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3893 [(set_attr "op_type" "RRE,RXE")
3894 (set_attr "type" "fmul")
3895 (set_attr "atype" "reg,mem")])
3897 (define_insn "*mulsf3_ibm"
3898 [(set (match_operand:SF 0 "register_operand" "=f,f")
3899 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3900 (match_operand:SF 2 "general_operand" "f,m")))
3901 (clobber (reg:CC 33))]
3902 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3906 [(set_attr "op_type" "RR,RX")
3907 (set_attr "type" "fmul")
3908 (set_attr "atype" "reg,mem")])
3912 ;;- Divide and modulo instructions.
3916 ; divmoddi4 instruction pattern(s).
3919 (define_expand "divmoddi4"
3920 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3921 (div:DI (match_operand:DI 1 "general_operand" "")
3922 (match_operand:DI 2 "general_operand" "")))
3923 (set (match_operand:DI 3 "general_operand" "")
3924 (mod:DI (match_dup 1) (match_dup 2)))])
3925 (clobber (match_dup 4))]
3929 rtx insn, div_equal, mod_equal, equal;
3931 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3932 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3933 equal = gen_rtx_IOR (TImode,
3934 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3935 gen_rtx_ASHIFT (TImode,
3936 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3939 operands[4] = gen_reg_rtx(TImode);
3940 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3941 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3942 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3943 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3945 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3947 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3949 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3951 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3953 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3958 (define_insn "divmodtidi3"
3959 [(set (match_operand:TI 0 "register_operand" "=d,d")
3962 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3963 (match_operand:DI 2 "general_operand" "d,m")))
3966 (mod:DI (truncate:DI (match_dup 1))
3973 [(set_attr "op_type" "RRE,RXE")
3974 (set_attr "type" "idiv")
3975 (set_attr "atype" "reg,mem")])
3977 (define_insn "divmodtisi3"
3978 [(set (match_operand:TI 0 "register_operand" "=d,d")
3981 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3982 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3985 (mod:DI (truncate:DI (match_dup 1))
3986 (sign_extend:DI (match_dup 2))))
3992 [(set_attr "op_type" "RRE,RXE")
3993 (set_attr "type" "idiv")
3994 (set_attr "atype" "reg,mem")])
3997 ; udivmoddi4 instruction pattern(s).
4000 (define_expand "udivmoddi4"
4001 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4002 (udiv:DI (match_operand:DI 1 "general_operand" "")
4003 (match_operand:DI 2 "nonimmediate_operand" "")))
4004 (set (match_operand:DI 3 "general_operand" "")
4005 (umod:DI (match_dup 1) (match_dup 2)))])
4006 (clobber (match_dup 4))]
4010 rtx insn, div_equal, mod_equal, equal;
4012 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4013 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4014 equal = gen_rtx_IOR (TImode,
4015 gen_rtx_ZERO_EXTEND (TImode, div_equal),
4016 gen_rtx_ASHIFT (TImode,
4017 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4020 operands[4] = gen_reg_rtx(TImode);
4021 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4022 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4023 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4024 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4026 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4028 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4030 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4032 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4034 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4039 (define_insn "udivmodtidi3"
4040 [(set (match_operand:TI 0 "register_operand" "=d,d")
4041 (ior:TI (zero_extend:TI
4043 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
4045 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4049 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
4055 [(set_attr "op_type" "RRE,RXE")
4056 (set_attr "type" "idiv")
4057 (set_attr "atype" "reg,mem")])
4060 ; divmodsi4 instruction pattern(s).
4063 (define_expand "divmodsi4"
4064 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4065 (div:SI (match_operand:SI 1 "general_operand" "")
4066 (match_operand:SI 2 "nonimmediate_operand" "")))
4067 (set (match_operand:SI 3 "general_operand" "")
4068 (mod:SI (match_dup 1) (match_dup 2)))])
4069 (clobber (match_dup 4))]
4073 rtx insn, div_equal, mod_equal, equal;
4075 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4076 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4077 equal = gen_rtx_IOR (DImode,
4078 gen_rtx_ZERO_EXTEND (DImode, div_equal),
4079 gen_rtx_ASHIFT (DImode,
4080 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4083 operands[4] = gen_reg_rtx(DImode);
4084 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4085 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4087 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4089 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4091 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4093 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4095 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4100 (define_insn "divmoddisi3"
4101 [(set (match_operand:DI 0 "register_operand" "=d,d")
4102 (ior:DI (zero_extend:DI
4104 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4106 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4110 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4116 [(set_attr "op_type" "RR,RX")
4117 (set_attr "type" "idiv")
4118 (set_attr "atype" "reg,mem")])
4121 ; udivsi3 and umodsi3 instruction pattern(s).
4125 (define_expand "udivsi3"
4126 [(set (match_operand:SI 0 "register_operand" "=d")
4127 (udiv:SI (match_operand:SI 1 "general_operand" "")
4128 (match_operand:SI 2 "general_operand" "")))
4129 (clobber (match_dup 3))]
4133 rtx insn, udiv_equal, umod_equal, equal;
4135 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4136 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4137 equal = gen_rtx_IOR (DImode,
4138 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4139 gen_rtx_ASHIFT (DImode,
4140 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4143 operands[3] = gen_reg_rtx (DImode);
4145 if (CONSTANT_P (operands[2]))
4147 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4149 rtx label1 = gen_label_rtx ();
4151 operands[1] = make_safe_from (operands[1], operands[0]);
4152 emit_move_insn (operands[0], const0_rtx);
4153 emit_insn (gen_cmpsi (operands[1], operands[2]));
4154 emit_jump_insn (gen_bltu (label1));
4155 emit_move_insn (operands[0], const1_rtx);
4156 emit_label (label1);
4160 operands[2] = force_reg (SImode, operands[2]);
4161 operands[2] = make_safe_from (operands[2], operands[0]);
4163 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4164 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4167 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4169 insn = emit_move_insn (operands[0],
4170 gen_lowpart (SImode, operands[3]));
4172 gen_rtx_EXPR_LIST (REG_EQUAL,
4173 udiv_equal, REG_NOTES (insn));
4178 rtx label1 = gen_label_rtx ();
4179 rtx label2 = gen_label_rtx ();
4180 rtx label3 = gen_label_rtx ();
4182 operands[1] = force_reg (SImode, operands[1]);
4183 operands[1] = make_safe_from (operands[1], operands[0]);
4184 operands[2] = force_reg (SImode, operands[2]);
4185 operands[2] = make_safe_from (operands[2], operands[0]);
4187 emit_move_insn (operands[0], const0_rtx);
4188 emit_insn (gen_cmpsi (operands[2], operands[1]));
4189 emit_jump_insn (gen_bgtu (label3));
4190 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4191 emit_jump_insn (gen_blt (label2));
4192 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4193 emit_jump_insn (gen_beq (label1));
4194 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4195 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4198 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4200 insn = emit_move_insn (operands[0],
4201 gen_lowpart (SImode, operands[3]));
4203 gen_rtx_EXPR_LIST (REG_EQUAL,
4204 udiv_equal, REG_NOTES (insn));
4206 emit_label (label1);
4207 emit_move_insn (operands[0], operands[1]);
4209 emit_label (label2);
4210 emit_move_insn (operands[0], const1_rtx);
4211 emit_label (label3);
4213 emit_move_insn (operands[0], operands[0]);
4217 (define_expand "umodsi3"
4218 [(set (match_operand:SI 0 "register_operand" "=d")
4219 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4220 (match_operand:SI 2 "nonimmediate_operand" "")))
4221 (clobber (match_dup 3))]
4225 rtx insn, udiv_equal, umod_equal, equal;
4227 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4228 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4229 equal = gen_rtx_IOR (DImode,
4230 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4231 gen_rtx_ASHIFT (DImode,
4232 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4235 operands[3] = gen_reg_rtx (DImode);
4237 if (CONSTANT_P (operands[2]))
4239 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4241 rtx label1 = gen_label_rtx ();
4243 operands[1] = make_safe_from (operands[1], operands[0]);
4244 emit_move_insn (operands[0], operands[1]);
4245 emit_insn (gen_cmpsi (operands[0], operands[2]));
4246 emit_jump_insn (gen_bltu (label1));
4247 emit_insn (gen_abssi2 (operands[0], operands[2]));
4248 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4249 emit_label (label1);
4253 operands[2] = force_reg (SImode, operands[2]);
4254 operands[2] = make_safe_from (operands[2], operands[0]);
4256 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4257 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4260 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4262 insn = emit_move_insn (operands[0],
4263 gen_highpart (SImode, operands[3]));
4265 gen_rtx_EXPR_LIST (REG_EQUAL,
4266 umod_equal, REG_NOTES (insn));
4271 rtx label1 = gen_label_rtx ();
4272 rtx label2 = gen_label_rtx ();
4273 rtx label3 = gen_label_rtx ();
4275 operands[1] = force_reg (SImode, operands[1]);
4276 operands[1] = make_safe_from (operands[1], operands[0]);
4277 operands[2] = force_reg (SImode, operands[2]);
4278 operands[2] = make_safe_from (operands[2], operands[0]);
4280 emit_move_insn(operands[0], operands[1]);
4281 emit_insn (gen_cmpsi (operands[2], operands[1]));
4282 emit_jump_insn (gen_bgtu (label3));
4283 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4284 emit_jump_insn (gen_blt (label2));
4285 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4286 emit_jump_insn (gen_beq (label1));
4287 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4288 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4291 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4293 insn = emit_move_insn (operands[0],
4294 gen_highpart (SImode, operands[3]));
4296 gen_rtx_EXPR_LIST (REG_EQUAL,
4297 umod_equal, REG_NOTES (insn));
4299 emit_label (label1);
4300 emit_move_insn (operands[0], const0_rtx);
4302 emit_label (label2);
4303 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4304 emit_label (label3);
4310 ; divdf3 instruction pattern(s).
4313 (define_expand "divdf3"
4315 [(set (match_operand:DF 0 "register_operand" "=f,f")
4316 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4317 (match_operand:DF 2 "general_operand" "f,m")))
4318 (clobber (reg:CC 33))])]
4322 (define_insn "*divdf3"
4323 [(set (match_operand:DF 0 "register_operand" "=f,f")
4324 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4325 (match_operand:DF 2 "general_operand" "f,m")))
4326 (clobber (reg:CC 33))]
4327 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4331 [(set_attr "op_type" "RRE,RXE")
4332 (set_attr "type" "fdiv")
4333 (set_attr "atype" "reg,mem")])
4335 (define_insn "*divdf3_ibm"
4336 [(set (match_operand:DF 0 "register_operand" "=f,f")
4337 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4338 (match_operand:DF 2 "general_operand" "f,m")))
4339 (clobber (reg:CC 33))]
4340 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4344 [(set_attr "op_type" "RR,RX")
4345 (set_attr "type" "fdiv")
4346 (set_attr "atype" "reg,mem")])
4349 ; divsf3 instruction pattern(s).
4352 (define_expand "divsf3"
4354 [(set (match_operand:SF 0 "register_operand" "=f,f")
4355 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4356 (match_operand:SF 2 "general_operand" "f,m")))
4357 (clobber (reg:CC 33))])]
4361 (define_insn "*divsf3"
4362 [(set (match_operand:SF 0 "register_operand" "=f,f")
4363 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4364 (match_operand:SF 2 "general_operand" "f,m")))
4365 (clobber (reg:CC 33))]
4366 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4370 [(set_attr "op_type" "RRE,RXE")
4371 (set_attr "type" "fdiv")
4372 (set_attr "atype" "reg,mem")])
4374 (define_insn "*divsf3"
4375 [(set (match_operand:SF 0 "register_operand" "=f,f")
4376 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4377 (match_operand:SF 2 "general_operand" "f,m")))
4378 (clobber (reg:CC 33))]
4379 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4383 [(set_attr "op_type" "RR,RX")
4384 (set_attr "type" "fdiv")
4385 (set_attr "atype" "reg,mem")])
4389 ;;- And instructions.
4393 ; anddi3 instruction pattern(s).
4396 (define_insn "*anddi3_cc"
4398 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4399 (match_operand:DI 2 "general_operand" "d,m"))
4401 (set (match_operand:DI 0 "register_operand" "=d,d")
4402 (and:DI (match_dup 1) (match_dup 2)))]
4403 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4407 [(set_attr "op_type" "RRE,RXE")
4408 (set_attr "atype" "reg,mem")])
4410 (define_insn "*anddi3_cconly"
4412 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4413 (match_operand:DI 2 "general_operand" "d,m"))
4415 (clobber (match_scratch:DI 0 "=d,d"))]
4416 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4420 [(set_attr "op_type" "RRE,RXE")
4421 (set_attr "atype" "reg,mem")])
4423 (define_insn "*anddi3_ni"
4424 [(set (match_operand:DI 0 "register_operand" "=d")
4425 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4426 (match_operand:DI 2 "immediate_operand" "n")))
4427 (clobber (reg:CC 33))]
4428 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4431 int part = s390_single_hi (operands[2], DImode, -1);
4432 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4436 case 0: return \"nihh\\t%0,%x2\";
4437 case 1: return \"nihl\\t%0,%x2\";
4438 case 2: return \"nilh\\t%0,%x2\";
4439 case 3: return \"nill\\t%0,%x2\";
4443 [(set_attr "op_type" "RI")
4444 (set_attr "atype" "reg")])
4446 (define_insn "anddi3"
4447 [(set (match_operand:DI 0 "register_operand" "=d,d")
4448 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4449 (match_operand:DI 2 "general_operand" "d,m")))
4450 (clobber (reg:CC 33))]
4455 [(set_attr "op_type" "RRE,RXE")
4456 (set_attr "atype" "reg,mem")])
4458 (define_insn "*anddi3_ss"
4459 [(set (match_operand:DI 0 "s_operand" "=Q")
4460 (and:DI (match_dup 0)
4461 (match_operand:DI 1 "s_imm_operand" "Q")))
4462 (clobber (reg:CC 33))]
4464 "nc\\t%O0(8,%R0),%1"
4465 [(set_attr "op_type" "SS")
4466 (set_attr "atype" "mem")])
4468 (define_insn "*anddi3_ss_inv"
4469 [(set (match_operand:DI 0 "s_operand" "=Q")
4470 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4472 (clobber (reg:CC 33))]
4474 "nc\\t%O0(8,%R0),%1"
4475 [(set_attr "op_type" "SS")
4476 (set_attr "atype" "mem")])
4479 ; andsi3 instruction pattern(s).
4482 (define_insn "*andsi3_cc"
4484 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4485 (match_operand:SI 2 "general_operand" "d,m"))
4487 (set (match_operand:SI 0 "register_operand" "=d,d")
4488 (and:SI (match_dup 1) (match_dup 2)))]
4489 "s390_match_ccmode(insn, CCTmode)"
4493 [(set_attr "op_type" "RR,RX")
4494 (set_attr "atype" "reg,mem")])
4496 (define_insn "*andsi3_cconly"
4498 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4499 (match_operand:SI 2 "general_operand" "d,m"))
4501 (clobber (match_scratch:SI 0 "=d,d"))]
4502 "s390_match_ccmode(insn, CCTmode)"
4506 [(set_attr "op_type" "RR,RX")
4507 (set_attr "atype" "reg,mem")])
4509 (define_insn "*andsi3_ni"
4510 [(set (match_operand:SI 0 "register_operand" "=d")
4511 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4512 (match_operand:SI 2 "immediate_operand" "n")))
4513 (clobber (reg:CC 33))]
4514 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4517 int part = s390_single_hi (operands[2], SImode, -1);
4518 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4522 case 0: return \"nilh\\t%0,%x2\";
4523 case 1: return \"nill\\t%0,%x2\";
4527 [(set_attr "op_type" "RI")
4528 (set_attr "atype" "reg")])
4530 (define_insn "andsi3"
4531 [(set (match_operand:SI 0 "register_operand" "=d,d")
4532 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4533 (match_operand:SI 2 "general_operand" "d,m")))
4534 (clobber (reg:CC 33))]
4539 [(set_attr "op_type" "RR,RX")
4540 (set_attr "atype" "reg,mem")])
4542 (define_insn "*andsi3_ss"
4543 [(set (match_operand:SI 0 "s_operand" "=Q")
4544 (and:SI (match_dup 0)
4545 (match_operand:SI 1 "s_imm_operand" "Q")))
4546 (clobber (reg:CC 33))]
4548 "nc\\t%O0(4,%R0),%1"
4549 [(set_attr "op_type" "SS")
4550 (set_attr "atype" "mem")])
4552 (define_insn "*andsi3_ss_inv"
4553 [(set (match_operand:SI 0 "s_operand" "=Q")
4554 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4556 (clobber (reg:CC 33))]
4558 "nc\\t%O0(4,%R0),%1"
4559 [(set_attr "op_type" "SS")
4560 (set_attr "atype" "mem")])
4563 ; andhi3 instruction pattern(s).
4566 (define_insn "*andhi3_ni"
4567 [(set (match_operand:HI 0 "register_operand" "=d,d")
4568 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4569 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4570 (clobber (reg:CC 33))]
4575 [(set_attr "op_type" "RR,RI")
4576 (set_attr "atype" "reg")])
4578 (define_insn "andhi3"
4579 [(set (match_operand:HI 0 "register_operand" "=d")
4580 (and:HI (match_operand:HI 1 "register_operand" "%0")
4581 (match_operand:HI 2 "nonmemory_operand" "d")))
4582 (clobber (reg:CC 33))]
4585 [(set_attr "op_type" "RR")
4586 (set_attr "atype" "reg")])
4588 (define_insn "*andhi3_ss"
4589 [(set (match_operand:HI 0 "s_operand" "=Q")
4590 (and:HI (match_dup 0)
4591 (match_operand:HI 1 "s_imm_operand" "Q")))
4592 (clobber (reg:CC 33))]
4594 "nc\\t%O0(2,%R0),%1"
4595 [(set_attr "op_type" "SS")
4596 (set_attr "atype" "mem")])
4598 (define_insn "*andhi3_ss_inv"
4599 [(set (match_operand:HI 0 "s_operand" "=Q")
4600 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4602 (clobber (reg:CC 33))]
4604 "nc\\t%O0(2,%R0),%1"
4605 [(set_attr "op_type" "SS")
4606 (set_attr "atype" "mem")])
4609 ; andqi3 instruction pattern(s).
4612 (define_insn "*andqi3_ni"
4613 [(set (match_operand:QI 0 "register_operand" "=d,d")
4614 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4615 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4616 (clobber (reg:CC 33))]
4621 [(set_attr "op_type" "RR,RI")
4622 (set_attr "atype" "reg")])
4624 (define_insn "andqi3"
4625 [(set (match_operand:QI 0 "register_operand" "=d")
4626 (and:QI (match_operand:QI 1 "register_operand" "%0")
4627 (match_operand:QI 2 "nonmemory_operand" "d")))
4628 (clobber (reg:CC 33))]
4631 [(set_attr "op_type" "RR")
4632 (set_attr "atype" "reg")])
4634 (define_insn "*andqi3_ss"
4635 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4636 (and:QI (match_dup 0)
4637 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4638 (clobber (reg:CC 33))]
4643 [(set_attr "op_type" "SI,SS")
4644 (set_attr "atype" "mem")])
4646 (define_insn "*andqi3_ss_inv"
4647 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4648 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4650 (clobber (reg:CC 33))]
4655 [(set_attr "op_type" "SI,SS")
4656 (set_attr "atype" "mem")])
4660 ;;- Bit set (inclusive or) instructions.
4664 ; iordi3 instruction pattern(s).
4667 (define_insn "*iordi3_cc"
4669 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4670 (match_operand:DI 2 "general_operand" "d,m"))
4672 (set (match_operand:DI 0 "register_operand" "=d,d")
4673 (ior:DI (match_dup 1) (match_dup 2)))]
4674 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4678 [(set_attr "op_type" "RRE,RXE")
4679 (set_attr "atype" "reg,mem")])
4681 (define_insn "*iordi3_cconly"
4683 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4684 (match_operand:DI 2 "general_operand" "d,m"))
4686 (clobber (match_scratch:DI 0 "=d,d"))]
4687 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4691 [(set_attr "op_type" "RRE,RXE")
4692 (set_attr "atype" "reg,mem")])
4694 (define_insn "*iordi3_oi"
4695 [(set (match_operand:DI 0 "register_operand" "=d")
4696 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4697 (match_operand:DI 2 "immediate_operand" "n")))
4698 (clobber (reg:CC 33))]
4699 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4702 int part = s390_single_hi (operands[2], DImode, 0);
4703 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4707 case 0: return \"oihh\\t%0,%x2\";
4708 case 1: return \"oihl\\t%0,%x2\";
4709 case 2: return \"oilh\\t%0,%x2\";
4710 case 3: return \"oill\\t%0,%x2\";
4714 [(set_attr "op_type" "RI")
4715 (set_attr "atype" "reg")])
4717 (define_insn "iordi3"
4718 [(set (match_operand:DI 0 "register_operand" "=d,d")
4719 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4720 (match_operand:DI 2 "general_operand" "d,m")))
4721 (clobber (reg:CC 33))]
4726 [(set_attr "op_type" "RRE,RXE")
4727 (set_attr "atype" "reg,mem")])
4729 (define_insn "*iordi3_ss"
4730 [(set (match_operand:DI 0 "s_operand" "=Q")
4731 (ior:DI (match_dup 0)
4732 (match_operand:DI 1 "s_imm_operand" "Q")))
4733 (clobber (reg:CC 33))]
4735 "oc\\t%O0(8,%R0),%1"
4736 [(set_attr "op_type" "SS")
4737 (set_attr "atype" "mem")])
4739 (define_insn "*iordi3_ss_inv"
4740 [(set (match_operand:DI 0 "s_operand" "=Q")
4741 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4743 (clobber (reg:CC 33))]
4745 "oc\\t%O0(8,%R0),%1"
4746 [(set_attr "op_type" "SS")
4747 (set_attr "atype" "mem")])
4750 ; iorsi3 instruction pattern(s).
4753 (define_insn "*iorsi3_cc"
4755 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4756 (match_operand:SI 2 "general_operand" "d,m"))
4758 (set (match_operand:SI 0 "register_operand" "=d,d")
4759 (ior:SI (match_dup 1) (match_dup 2)))]
4760 "s390_match_ccmode(insn, CCTmode)"
4764 [(set_attr "op_type" "RR,RX")
4765 (set_attr "atype" "reg,mem")])
4767 (define_insn "*iorsi3_cconly"
4769 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4770 (match_operand:SI 2 "general_operand" "d,m"))
4772 (clobber (match_scratch:SI 0 "=d,d"))]
4773 "s390_match_ccmode(insn, CCTmode)"
4777 [(set_attr "op_type" "RR,RX")
4778 (set_attr "atype" "reg,mem")])
4780 (define_insn "*iorsi3_oi"
4781 [(set (match_operand:SI 0 "register_operand" "=d")
4782 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4783 (match_operand:SI 2 "immediate_operand" "n")))
4784 (clobber (reg:CC 33))]
4785 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4788 int part = s390_single_hi (operands[2], SImode, 0);
4789 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4793 case 0: return \"oilh\\t%0,%x2\";
4794 case 1: return \"oill\\t%0,%x2\";
4798 [(set_attr "op_type" "RI")
4799 (set_attr "atype" "reg")])
4801 (define_insn "iorsi3"
4802 [(set (match_operand:SI 0 "register_operand" "=d,d")
4803 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4804 (match_operand:SI 2 "general_operand" "d,m")))
4805 (clobber (reg:CC 33))]
4810 [(set_attr "op_type" "RR,RX")
4811 (set_attr "atype" "reg,mem")])
4813 (define_insn "*iorsi3_ss"
4814 [(set (match_operand:SI 0 "s_operand" "=Q")
4815 (ior:SI (match_dup 0)
4816 (match_operand:SI 1 "s_imm_operand" "Q")))
4817 (clobber (reg:CC 33))]
4819 "oc\\t%O0(4,%R0),%1"
4820 [(set_attr "op_type" "SS")
4821 (set_attr "atype" "mem")])
4823 (define_insn "*iorsi3_ss_inv"
4824 [(set (match_operand:SI 0 "s_operand" "=Q")
4825 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4827 (clobber (reg:CC 33))]
4829 "oc\\t%O0(4,%R0),%1"
4830 [(set_attr "op_type" "SS")
4831 (set_attr "atype" "mem")])
4834 ; iorhi3 instruction pattern(s).
4837 (define_insn "*iorhi3_oi"
4838 [(set (match_operand:HI 0 "register_operand" "=d,d")
4839 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4840 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4841 (clobber (reg:CC 33))]
4846 [(set_attr "op_type" "RR,RI")
4847 (set_attr "atype" "reg")])
4849 (define_insn "iorhi3"
4850 [(set (match_operand:HI 0 "register_operand" "=d")
4851 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4852 (match_operand:HI 2 "nonmemory_operand" "d")))
4853 (clobber (reg:CC 33))]
4856 [(set_attr "op_type" "RR")
4857 (set_attr "atype" "reg")])
4859 (define_insn "*iorhi3_ss"
4860 [(set (match_operand:HI 0 "s_operand" "=Q")
4861 (ior:HI (match_dup 0)
4862 (match_operand:HI 1 "s_imm_operand" "Q")))
4863 (clobber (reg:CC 33))]
4865 "oc\\t%O0(2,%R0),%1"
4866 [(set_attr "op_type" "SS")
4867 (set_attr "atype" "mem")])
4869 (define_insn "*iorhi3_ss_inv"
4870 [(set (match_operand:HI 0 "s_operand" "=Q")
4871 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4873 (clobber (reg:CC 33))]
4875 "oc\\t%O0(2,%R0),%1"
4876 [(set_attr "op_type" "SS")
4877 (set_attr "atype" "mem")])
4880 ; iorqi3 instruction pattern(s).
4883 (define_insn "*iorqi3_oi"
4884 [(set (match_operand:QI 0 "register_operand" "=d,d")
4885 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4886 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4887 (clobber (reg:CC 33))]
4892 [(set_attr "op_type" "RR,RI")
4893 (set_attr "atype" "reg")])
4895 (define_insn "iorqi3"
4896 [(set (match_operand:QI 0 "register_operand" "=d")
4897 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4898 (match_operand:QI 2 "nonmemory_operand" "d")))
4899 (clobber (reg:CC 33))]
4902 [(set_attr "op_type" "RR")
4903 (set_attr "atype" "reg")])
4905 (define_insn "*iorqi3_ss"
4906 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4907 (ior:QI (match_dup 0)
4908 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4909 (clobber (reg:CC 33))]
4914 [(set_attr "op_type" "SI,SS")
4915 (set_attr "atype" "reg,mem")])
4917 (define_insn "*iorqi3_ss_inv"
4918 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4919 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4921 (clobber (reg:CC 33))]
4926 [(set_attr "op_type" "SI,SS")
4927 (set_attr "atype" "reg,mem")])
4931 ;;- Xor instructions.
4935 ; xordi3 instruction pattern(s).
4938 (define_insn "*xordi3_cc"
4940 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4941 (match_operand:DI 2 "general_operand" "d,m"))
4943 (set (match_operand:DI 0 "register_operand" "=d,d")
4944 (xor:DI (match_dup 1) (match_dup 2)))]
4945 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4949 [(set_attr "op_type" "RRE,RXE")
4950 (set_attr "atype" "reg,mem")])
4952 (define_insn "*xordi3_cconly"
4954 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4955 (match_operand:DI 2 "general_operand" "d,m"))
4957 (clobber (match_scratch:DI 0 "=d,d"))]
4958 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4962 [(set_attr "op_type" "RRE,RXE")
4963 (set_attr "atype" "reg,mem")])
4965 (define_insn "xordi3"
4966 [(set (match_operand:DI 0 "register_operand" "=d,d")
4967 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4968 (match_operand:DI 2 "general_operand" "d,m")))
4969 (clobber (reg:CC 33))]
4974 [(set_attr "op_type" "RRE,RXE")
4975 (set_attr "atype" "reg,mem")])
4977 (define_insn "*xordi3_ss"
4978 [(set (match_operand:DI 0 "s_operand" "=Q")
4979 (xor:DI (match_dup 0)
4980 (match_operand:DI 1 "s_imm_operand" "Q")))
4981 (clobber (reg:CC 33))]
4983 "xc\\t%O0(8,%R0),%1"
4984 [(set_attr "op_type" "SS")
4985 (set_attr "atype" "mem")])
4987 (define_insn "*xordi3_ss_inv"
4988 [(set (match_operand:DI 0 "s_operand" "=Q")
4989 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4991 (clobber (reg:CC 33))]
4993 "xc\\t%O0(8,%R0),%1"
4994 [(set_attr "op_type" "SS")
4995 (set_attr "atype" "mem")])
4998 ; xorsi3 instruction pattern(s).
5001 (define_insn "*xorsi3_cc"
5003 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5004 (match_operand:SI 2 "general_operand" "d,m"))
5006 (set (match_operand:SI 0 "register_operand" "=d,d")
5007 (xor:SI (match_dup 1) (match_dup 2)))]
5008 "s390_match_ccmode(insn, CCTmode)"
5012 [(set_attr "op_type" "RR,RX")
5013 (set_attr "atype" "reg,mem")])
5015 (define_insn "*xorsi3_cconly"
5017 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5018 (match_operand:SI 2 "general_operand" "d,m"))
5020 (clobber (match_scratch:SI 0 "=d,d"))]
5021 "s390_match_ccmode(insn, CCTmode)"
5025 [(set_attr "op_type" "RR,RX")
5026 (set_attr "atype" "reg,mem")])
5028 (define_insn "xorsi3"
5029 [(set (match_operand:SI 0 "register_operand" "=d,d")
5030 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5031 (match_operand:SI 2 "general_operand" "d,m")))
5032 (clobber (reg:CC 33))]
5037 [(set_attr "op_type" "RR,RX")
5038 (set_attr "atype" "reg,mem")])
5040 (define_insn "*xorsi3_ss"
5041 [(set (match_operand:SI 0 "s_operand" "=Q")
5042 (xor:SI (match_dup 0)
5043 (match_operand:SI 1 "s_imm_operand" "Q")))
5044 (clobber (reg:CC 33))]
5046 "xc\\t%O0(4,%R0),%1"
5047 [(set_attr "op_type" "SS")
5048 (set_attr "atype" "mem")])
5050 (define_insn "*xorsi3_ss_inv"
5051 [(set (match_operand:SI 0 "s_operand" "=Q")
5052 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
5054 (clobber (reg:CC 33))]
5056 "xc\\t%O0(4,%R0),%1"
5057 [(set_attr "op_type" "SS")
5058 (set_attr "atype" "mem")])
5061 ; xorhi3 instruction pattern(s).
5064 (define_insn "xorhi3"
5065 [(set (match_operand:HI 0 "register_operand" "=d")
5066 (xor:HI (match_operand:HI 1 "register_operand" "%0")
5067 (match_operand:HI 2 "nonmemory_operand" "d")))
5068 (clobber (reg:CC 33))]
5071 [(set_attr "op_type" "RR")
5072 (set_attr "atype" "reg")])
5074 (define_insn "*xorhi3_ss"
5075 [(set (match_operand:HI 0 "s_operand" "=Q")
5076 (xor:HI (match_dup 0)
5077 (match_operand:HI 1 "s_imm_operand" "Q")))
5078 (clobber (reg:CC 33))]
5080 "xc\\t%O0(2,%R0),%1"
5081 [(set_attr "op_type" "SS")
5082 (set_attr "atype" "mem")])
5084 (define_insn "*xorhi3_ss_inv"
5085 [(set (match_operand:HI 0 "s_operand" "=Q")
5086 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
5088 (clobber (reg:CC 33))]
5090 "xc\\t%O0(2,%R0),%1"
5091 [(set_attr "op_type" "SS")
5092 (set_attr "atype" "mem")])
5095 ; xorqi3 instruction pattern(s).
5098 (define_insn "xorqi3"
5099 [(set (match_operand:QI 0 "register_operand" "=d")
5100 (xor:QI (match_operand:QI 1 "register_operand" "%0")
5101 (match_operand:QI 2 "nonmemory_operand" "d")))
5102 (clobber (reg:CC 33))]
5105 [(set_attr "op_type" "RR")
5106 (set_attr "atype" "reg")])
5108 (define_insn "*xorqi3_ss"
5109 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5110 (xor:QI (match_dup 0)
5111 (match_operand:QI 1 "s_imm_operand" "n,Q")))
5112 (clobber (reg:CC 33))]
5117 [(set_attr "op_type" "SI,SS")
5118 (set_attr "atype" "mem")])
5120 (define_insn "*xorqi3_ss_inv"
5121 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5122 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
5124 (clobber (reg:CC 33))]
5129 [(set_attr "op_type" "SI,SS")
5130 (set_attr "atype" "mem")])
5134 ;;- Negate instructions.
5138 ; negdi2 instruction pattern(s).
5141 (define_expand "negdi2"
5143 [(set (match_operand:DI 0 "register_operand" "=d")
5144 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5145 (clobber (reg:CC 33))])]
5149 (define_insn "*negdi2_64"
5150 [(set (match_operand:DI 0 "register_operand" "=d")
5151 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5152 (clobber (reg:CC 33))]
5155 [(set_attr "op_type" "RR")])
5157 (define_insn "*negdi2_31"
5158 [(set (match_operand:DI 0 "register_operand" "=d")
5159 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5160 (clobber (reg:CC 33))]
5165 xop[0] = gen_label_rtx ();
5166 output_asm_insn (\"lcr\\t%0,%1\", operands);
5167 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5168 output_asm_insn (\"je\\t%l0\", xop);
5169 output_asm_insn (\"bctr\\t%0,0\", operands);
5170 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5171 CODE_LABEL_NUMBER (xop[0]));
5174 [(set_attr "op_type" "NN")
5175 (set_attr "type" "other")
5176 (set_attr "length" "10")])
5179 ; negsi2 instruction pattern(s).
5182 (define_insn "negsi2"
5183 [(set (match_operand:SI 0 "register_operand" "=d")
5184 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5185 (clobber (reg:CC 33))]
5188 [(set_attr "op_type" "RR")])
5191 ; negdf2 instruction pattern(s).
5194 (define_expand "negdf2"
5196 [(set (match_operand:DF 0 "register_operand" "=f")
5197 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5198 (clobber (reg:CC 33))])]
5202 (define_insn "*negdf2"
5203 [(set (match_operand:DF 0 "register_operand" "=f")
5204 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5205 (clobber (reg:CC 33))]
5206 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5208 [(set_attr "op_type" "RRE")])
5210 (define_insn "*negdf2_ibm"
5211 [(set (match_operand:DF 0 "register_operand" "=f")
5212 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5213 (clobber (reg:CC 33))]
5214 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5216 [(set_attr "op_type" "RR")])
5219 ; negsf2 instruction pattern(s).
5222 (define_expand "negsf2"
5224 [(set (match_operand:SF 0 "register_operand" "=f")
5225 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5226 (clobber (reg:CC 33))])]
5230 (define_insn "*negsf2"
5231 [(set (match_operand:SF 0 "register_operand" "=f")
5232 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5233 (clobber (reg:CC 33))]
5234 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5236 [(set_attr "op_type" "RRE")])
5238 (define_insn "*negsf2"
5239 [(set (match_operand:SF 0 "register_operand" "=f")
5240 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5241 (clobber (reg:CC 33))]
5242 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5244 [(set_attr "op_type" "RR")])
5248 ;;- Absolute value instructions.
5252 ; absdi2 instruction pattern(s).
5255 (define_insn "absdi2"
5256 [(set (match_operand:DI 0 "register_operand" "=d")
5257 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5258 (clobber (reg:CC 33))]
5261 [(set_attr "op_type" "RRE")])
5264 ; abssi2 instruction pattern(s).
5267 (define_insn "abssi2"
5268 [(set (match_operand:SI 0 "register_operand" "=d")
5269 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5270 (clobber (reg:CC 33))]
5273 [(set_attr "op_type" "RR")])
5276 ; absdf2 instruction pattern(s).
5279 (define_expand "absdf2"
5281 [(set (match_operand:DF 0 "register_operand" "=f")
5282 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5283 (clobber (reg:CC 33))])]
5287 (define_insn "*absdf2"
5288 [(set (match_operand:DF 0 "register_operand" "=f")
5289 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5290 (clobber (reg:CC 33))]
5291 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5293 [(set_attr "op_type" "RRE")])
5295 (define_insn "*absdf2_ibm"
5296 [(set (match_operand:DF 0 "register_operand" "=f")
5297 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5298 (clobber (reg:CC 33))]
5299 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5301 [(set_attr "op_type" "RR")])
5304 ; abssf2 instruction pattern(s).
5307 (define_expand "abssf2"
5309 [(set (match_operand:SF 0 "register_operand" "=f")
5310 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5311 (clobber (reg:CC 33))])]
5315 (define_insn "*abssf2"
5316 [(set (match_operand:SF 0 "register_operand" "=f")
5317 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5318 (clobber (reg:CC 33))]
5319 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5321 [(set_attr "op_type" "RRE")])
5323 (define_insn "*abssf2_ibm"
5324 [(set (match_operand:SF 0 "register_operand" "=f")
5325 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5326 (clobber (reg:CC 33))]
5327 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5329 [(set_attr "op_type" "RR")])
5332 ;;- Square root instructions.
5336 ; sqrtdf2 instruction pattern(s).
5339 (define_insn "sqrtdf2"
5340 [(set (match_operand:DF 0 "register_operand" "=f,f")
5341 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5342 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5346 [(set_attr "op_type" "RRE,RSE")])
5349 ; sqrtsf2 instruction pattern(s).
5352 (define_insn "sqrtsf2"
5353 [(set (match_operand:SF 0 "register_operand" "=f,f")
5354 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5355 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5359 [(set_attr "op_type" "RRE,RSE")])
5362 ;;- One complement instructions.
5366 ; one_cmpldi2 instruction pattern(s).
5369 (define_expand "one_cmpldi2"
5371 [(set (match_operand:DI 0 "register_operand" "")
5372 (xor:DI (match_operand:DI 1 "register_operand" "")
5374 (clobber (reg:CC 33))])]
5379 ; one_cmplsi2 instruction pattern(s).
5382 (define_expand "one_cmplsi2"
5384 [(set (match_operand:SI 0 "register_operand" "")
5385 (xor:SI (match_operand:SI 1 "register_operand" "")
5387 (clobber (reg:CC 33))])]
5392 ; one_cmplhi2 instruction pattern(s).
5395 (define_expand "one_cmplhi2"
5397 [(set (match_operand:HI 0 "register_operand" "")
5398 (xor:HI (match_operand:HI 1 "register_operand" "")
5400 (clobber (reg:CC 33))])]
5405 ; one_cmplqi2 instruction pattern(s).
5408 (define_expand "one_cmplqi2"
5410 [(set (match_operand:QI 0 "register_operand" "")
5411 (xor:QI (match_operand:QI 1 "register_operand" "")
5413 (clobber (reg:CC 33))])]
5419 ;;- Rotate instructions.
5423 ; rotldi3 instruction pattern(s).
5426 (define_insn "rotldi3"
5427 [(set (match_operand:DI 0 "register_operand" "=d,d")
5428 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5429 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5434 [(set_attr "op_type" "RSE")])
5437 ; rotlsi3 instruction pattern(s).
5440 (define_insn "rotlsi3"
5441 [(set (match_operand:SI 0 "register_operand" "=d,d")
5442 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5443 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5448 [(set_attr "op_type" "RSE")])
5452 ;;- Arithmetic shift instructions.
5456 ; ashldi3 instruction pattern(s).
5459 (define_expand "ashldi3"
5460 [(set (match_operand:DI 0 "register_operand" "")
5461 (ashift:DI (match_operand:DI 1 "register_operand" "")
5462 (match_operand:SI 2 "nonmemory_operand" "")))]
5466 (define_insn "*ashldi3_31"
5467 [(set (match_operand:DI 0 "register_operand" "=d,d")
5468 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5469 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5474 [(set_attr "op_type" "RS")])
5476 (define_insn "*ashldi3_64"
5477 [(set (match_operand:DI 0 "register_operand" "=d,d")
5478 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5479 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5484 [(set_attr "op_type" "RSE")])
5487 ; ashrdi3 instruction pattern(s).
5490 (define_expand "ashrdi3"
5492 [(set (match_operand:DI 0 "register_operand" "")
5493 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5494 (match_operand:SI 2 "nonmemory_operand" "")))
5495 (clobber (reg:CC 33))])]
5499 (define_insn "*ashrdi3_cc_31"
5501 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5502 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5504 (set (match_operand:DI 0 "register_operand" "=d,d")
5505 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5506 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5510 [(set_attr "op_type" "RS")])
5512 (define_insn "*ashrdi3_cconly_31"
5514 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5515 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5517 (clobber (match_scratch:DI 0 "=d,d"))]
5518 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5522 [(set_attr "op_type" "RS")])
5524 (define_insn "*ashrdi3_31"
5525 [(set (match_operand:DI 0 "register_operand" "=d,d")
5526 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5527 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5528 (clobber (reg:CC 33))]
5533 [(set_attr "op_type" "RS")])
5535 (define_insn "*ashrdi3_cc_64"
5537 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5538 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5540 (set (match_operand:DI 0 "register_operand" "=d,d")
5541 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5542 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5546 [(set_attr "op_type" "RSE")])
5548 (define_insn "*ashrdi3_cconly_64"
5550 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5551 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5553 (clobber (match_scratch:DI 0 "=d,d"))]
5554 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5558 [(set_attr "op_type" "RSE")])
5560 (define_insn "*ashrdi3_64"
5561 [(set (match_operand:DI 0 "register_operand" "=d,d")
5562 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5563 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5564 (clobber (reg:CC 33))]
5569 [(set_attr "op_type" "RSE")])
5572 ; ashlsi3 instruction pattern(s).
5575 (define_insn "ashlsi3"
5576 [(set (match_operand:SI 0 "register_operand" "=d,d")
5577 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5578 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5583 [(set_attr "op_type" "RS")])
5586 ; ashrsi3 instruction pattern(s).
5589 (define_insn "*ashrsi3_cc"
5591 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5592 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5594 (set (match_operand:SI 0 "register_operand" "=d,d")
5595 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5596 "s390_match_ccmode(insn, CCSmode)"
5600 [(set_attr "op_type" "RS")])
5602 (define_insn "*ashrsi3_cconly"
5604 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5605 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5607 (clobber (match_scratch:SI 0 "=d,d"))]
5608 "s390_match_ccmode(insn, CCSmode)"
5612 [(set_attr "op_type" "RS")])
5614 (define_insn "ashrsi3"
5615 [(set (match_operand:SI 0 "register_operand" "=d,d")
5616 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5617 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5618 (clobber (reg:CC 33))]
5623 [(set_attr "op_type" "RS")])
5627 ;;- logical shift instructions.
5631 ; lshrdi3 instruction pattern(s).
5634 (define_expand "lshrdi3"
5635 [(set (match_operand:DI 0 "register_operand" "")
5636 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5637 (match_operand:SI 2 "nonmemory_operand" "")))]
5641 (define_insn "*lshrdi3_31"
5642 [(set (match_operand:DI 0 "register_operand" "=d,d")
5643 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5644 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5649 [(set_attr "op_type" "RS,RS")])
5651 (define_insn "*lshrdi3_64"
5652 [(set (match_operand:DI 0 "register_operand" "=d,d")
5653 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5654 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5659 [(set_attr "op_type" "RS,RS")])
5662 ; lshrsi3 instruction pattern(s).
5665 (define_insn "lshrsi3"
5666 [(set (match_operand:SI 0 "register_operand" "=d,d")
5667 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5668 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5673 [(set_attr "op_type" "RS")])
5677 ;; Branch instruction patterns.
5680 (define_expand "beq"
5681 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5683 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5684 (label_ref (match_operand 0 "" ""))
5687 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5689 (define_expand "bne"
5690 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5692 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5693 (label_ref (match_operand 0 "" ""))
5696 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5698 (define_expand "bgt"
5699 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5701 (if_then_else (gt (reg:CCS 33) (const_int 0))
5702 (label_ref (match_operand 0 "" ""))
5705 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5707 (define_expand "bgtu"
5708 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5710 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5711 (label_ref (match_operand 0 "" ""))
5714 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5716 (define_expand "blt"
5717 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5719 (if_then_else (lt (reg:CCS 33) (const_int 0))
5720 (label_ref (match_operand 0 "" ""))
5723 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5725 (define_expand "bltu"
5726 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5728 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5729 (label_ref (match_operand 0 "" ""))
5732 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5734 (define_expand "bge"
5735 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5737 (if_then_else (ge (reg:CCS 33) (const_int 0))
5738 (label_ref (match_operand 0 "" ""))
5741 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5743 (define_expand "bgeu"
5744 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5746 (if_then_else (geu (reg:CCU 33) (const_int 0))
5747 (label_ref (match_operand 0 "" ""))
5750 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5752 (define_expand "ble"
5753 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5755 (if_then_else (le (reg:CCS 33) (const_int 0))
5756 (label_ref (match_operand 0 "" ""))
5759 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5761 (define_expand "bleu"
5762 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5764 (if_then_else (leu (reg:CCU 33) (const_int 0))
5765 (label_ref (match_operand 0 "" ""))
5768 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5770 (define_expand "bunordered"
5771 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5773 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5774 (label_ref (match_operand 0 "" ""))
5777 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5779 (define_expand "bordered"
5780 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5782 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5783 (label_ref (match_operand 0 "" ""))
5786 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5788 (define_expand "buneq"
5789 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5791 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5792 (label_ref (match_operand 0 "" ""))
5795 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5797 (define_expand "bungt"
5798 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5800 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5801 (label_ref (match_operand 0 "" ""))
5804 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5806 (define_expand "bunlt"
5807 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5809 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5810 (label_ref (match_operand 0 "" ""))
5813 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5815 (define_expand "bunge"
5816 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5818 (if_then_else (unge (reg:CCS 33) (const_int 0))
5819 (label_ref (match_operand 0 "" ""))
5822 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5824 (define_expand "bunle"
5825 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5827 (if_then_else (unle (reg:CCS 33) (const_int 0))
5828 (label_ref (match_operand 0 "" ""))
5831 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5833 (define_expand "bltgt"
5834 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5836 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5837 (label_ref (match_operand 0 "" ""))
5840 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5844 ;;- Conditional jump instructions.
5847 (define_insn "cjump"
5850 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5851 (label_ref (match_operand 0 "" ""))
5856 if (get_attr_length (insn) == 4)
5857 return \"j%C1\\t%l0\";
5858 else if (TARGET_64BIT)
5859 return \"jg%C1\\t%l0\";
5863 [(set_attr "op_type" "RI")
5864 (set (attr "length")
5865 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5867 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5869 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5870 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5871 (const_int 12) (const_int 14))
5872 (eq (symbol_ref "flag_pic") (const_int 0))
5873 (const_int 6)] (const_int 8)))])
5875 (define_insn "*cjump_long"
5878 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5879 (match_operand 0 "address_operand" "p")
5884 if (get_attr_op_type (insn) == OP_TYPE_RR)
5885 return \"b%C1r\\t%0\";
5887 return \"b%C1\\t%a0\";
5889 [(set (attr "op_type")
5890 (if_then_else (match_operand 0 "register_operand" "")
5891 (const_string "RR") (const_string "RX")))
5892 (set_attr "atype" "mem")])
5896 ;;- Negated conditional jump instructions.
5899 (define_insn "icjump"
5902 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5904 (label_ref (match_operand 0 "" ""))))]
5908 if (get_attr_length (insn) == 4)
5909 return \"j%D1\\t%l0\";
5910 else if (TARGET_64BIT)
5911 return \"jg%D1\\t%l0\";
5915 [(set_attr "op_type" "RI")
5916 (set (attr "length")
5917 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5919 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5921 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5922 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5923 (const_int 12) (const_int 14))
5924 (eq (symbol_ref "flag_pic") (const_int 0))
5925 (const_int 6)] (const_int 8)))])
5927 (define_insn "*icjump_long"
5930 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5932 (match_operand 0 "address_operand" "p")))]
5936 if (get_attr_op_type (insn) == OP_TYPE_RR)
5937 return \"b%D1r\\t%0\";
5939 return \"b%D1\\t%a0\";
5941 [(set (attr "op_type")
5942 (if_then_else (match_operand 0 "register_operand" "")
5943 (const_string "RR") (const_string "RX")))
5944 (set_attr "atype" "mem")])
5948 ;;- Subtract one and jump if not zero.
5951 ;(define_expand "decrement_and_branch_on_count"
5952 ; [(use (match_operand 0 "register_operand" ""))
5953 ; (use (label_ref (match_operand 1 "" "")))]
5957 ;/* if (TARGET_64BIT)
5958 ; emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5960 ; emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5964 ;(define_insn "brctsi"
5967 ; (ne (match_operand:SI 0 "register_operand" "+a")
5969 ; (label_ref (match_operand 1 "" ""))
5971 ; (set (match_dup 0)
5972 ; (plus:SI (match_dup 0) (const_int -1)))]
5975 ; [(set_attr "op_type" "RI")
5976 ; (set_attr "type" "branch")]
5979 ;(define_insn "ibrctsi"
5982 ; (eq (match_operand:SI 0 "register_operand" "+a")
5985 ; (label_ref (match_operand 1 "" ""))))
5986 ; (set (match_dup 0)
5987 ; (plus:SI (match_dup 0) (const_int -1)))]
5990 ; [(set_attr "op_type" "RI")
5991 ; (set_attr "type" "branch")]
5996 ;;- Unconditional jump instructions.
6000 ; jump instruction pattern(s).
6004 [(set (pc) (label_ref (match_operand 0 "" "")))]
6008 if (get_attr_length (insn) == 4)
6010 else if (TARGET_64BIT)
6011 return \"jg\\t%l0\";
6015 [(set_attr "op_type" "RI")
6016 (set (attr "length")
6017 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6019 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6021 (eq (symbol_ref "flag_pic") (const_int 0))
6022 (const_int 6)] (const_int 8)))])
6025 ; indirect-jump instruction pattern(s).
6028 (define_insn "indirect_jump"
6029 [(set (pc) (match_operand 0 "address_operand" "p"))]
6033 if (get_attr_op_type (insn) == OP_TYPE_RR)
6038 [(set (attr "op_type")
6039 (if_then_else (match_operand 0 "register_operand" "")
6040 (const_string "RR") (const_string "RX")))
6041 (set_attr "atype" "mem")])
6044 ; casesi instruction pattern(s).
6047 (define_insn "casesi_jump"
6048 [(set (pc) (match_operand 0 "address_operand" "p"))
6049 (use (label_ref (match_operand 1 "" "")))]
6053 if (get_attr_op_type (insn) == OP_TYPE_RR)
6058 [(set (attr "op_type")
6059 (if_then_else (match_operand 0 "register_operand" "")
6060 (const_string "RR") (const_string "RX")))
6061 (set_attr "atype" "mem")])
6063 (define_expand "casesi"
6064 [(match_operand:SI 0 "general_operand" "")
6065 (match_operand:SI 1 "general_operand" "")
6066 (match_operand:SI 2 "general_operand" "")
6067 (label_ref (match_operand 3 "" ""))
6068 (label_ref (match_operand 4 "" ""))]
6072 rtx index = gen_reg_rtx (SImode);
6073 rtx base = gen_reg_rtx (Pmode);
6074 rtx target = gen_reg_rtx (Pmode);
6076 emit_move_insn (index, operands[0]);
6077 emit_insn (gen_subsi3 (index, index, operands[1]));
6078 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6081 if (Pmode != SImode)
6082 index = convert_to_mode (Pmode, index, 1);
6083 if (GET_CODE (index) != REG)
6084 index = copy_to_mode_reg (Pmode, index);
6087 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6089 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6091 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6093 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6094 emit_move_insn (target, index);
6097 target = gen_rtx_PLUS (Pmode, base, target);
6098 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6105 ;;- Jump to subroutine.
6110 ; untyped call instruction pattern(s).
6113 ;; Call subroutine returning any type.
6114 (define_expand "untyped_call"
6115 [(parallel [(call (match_operand 0 "" "")
6117 (match_operand 1 "" "")
6118 (match_operand 2 "" "")])]
6124 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6126 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6128 rtx set = XVECEXP (operands[2], 0, i);
6129 emit_move_insn (SET_DEST (set), SET_SRC (set));
6132 /* The optimizer does not know that the call sets the function value
6133 registers we stored in the result block. We avoid problems by
6134 claiming that all hard registers are used and clobbered at this
6136 emit_insn (gen_blockage ());
6141 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6142 ;; all of memory. This blocks insns from being moved across this point.
6144 (define_insn "blockage"
6145 [(unspec_volatile [(const_int 0)] 0)]
6148 [(set_attr "type" "none")])
6153 ; call instruction pattern(s).
6156 (define_expand "call"
6157 [(call (match_operand 0 "" "")
6158 (match_operand 1 "" ""))
6159 (use (match_operand 2 "" ""))]
6166 /* Direct function calls need special treatment. */
6167 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6169 rtx sym = XEXP (operands[0], 0);
6171 /* When calling a global routine in PIC mode, we must
6172 replace the symbol itself with the PLT stub. */
6173 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6175 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6176 sym = gen_rtx_CONST (Pmode, sym);
6181 /* Unless we can use the bras(l) insn, force the
6182 routine address into a register. */
6183 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6185 rtx target = gen_reg_rtx (Pmode);
6186 emit_move_insn (target, sym);
6190 operands[0] = gen_rtx_MEM (QImode, sym);
6194 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6195 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6197 /* In 31-bit, we must load the GOT register even if the
6198 compiler doesn't know about it, because the PLT glue
6199 code uses it. In 64-bit, this is not necessary. */
6200 if (plt_call && !TARGET_64BIT)
6201 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6206 (define_expand "call_exp"
6207 [(parallel [(call (match_operand 0 "" "")
6208 (match_operand 1 "" ""))
6209 (clobber (match_operand 2 "" ""))])]
6213 (define_insn "brasl"
6214 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6215 (match_operand:SI 1 "const_int_operand" "n"))
6216 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6219 [(set_attr "op_type" "RIL")
6220 (set_attr "type" "jsr")])
6223 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6224 (match_operand:SI 1 "const_int_operand" "n"))
6225 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6228 [(set_attr "op_type" "RI")
6229 (set_attr "type" "jsr")])
6231 (define_insn "basr_64"
6232 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6233 (match_operand:SI 1 "const_int_operand" "n"))
6234 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6237 [(set_attr "op_type" "RR")
6238 (set_attr "type" "jsr")
6239 (set_attr "atype" "mem")])
6241 (define_insn "basr_31"
6242 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6243 (match_operand:SI 1 "const_int_operand" "n"))
6244 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6247 [(set_attr "op_type" "RR")
6248 (set_attr "type" "jsr")
6249 (set_attr "atype" "mem")])
6251 (define_insn "bas_64"
6252 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6253 (match_operand:SI 1 "const_int_operand" "n"))
6254 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6257 [(set_attr "op_type" "RX")
6258 (set_attr "type" "jsr")
6259 (set_attr "atype" "mem")])
6261 (define_insn "bas_31"
6262 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6263 (match_operand:SI 1 "const_int_operand" "n"))
6264 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6267 [(set_attr "op_type" "RX")
6268 (set_attr "type" "jsr")
6269 (set_attr "atype" "mem")])
6273 ; call_value instruction pattern(s).
6276 (define_expand "call_value"
6277 [(set (match_operand 0 "" "")
6278 (call (match_operand 1 "" "")
6279 (match_operand 2 "" "")))
6280 (use (match_operand 3 "" ""))]
6287 /* Direct function calls need special treatment. */
6288 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6290 rtx sym = XEXP (operands[1], 0);
6292 /* When calling a global routine in PIC mode, we must
6293 replace the symbol itself with the PLT stub. */
6294 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6296 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6297 sym = gen_rtx_CONST (Pmode, sym);
6302 /* Unless we can use the bras(l) insn, force the
6303 routine address into a register. */
6304 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6306 rtx target = gen_reg_rtx (Pmode);
6307 emit_move_insn (target, sym);
6311 operands[1] = gen_rtx_MEM (QImode, sym);
6315 insn = emit_call_insn (
6316 gen_call_value_exp (operands[0], operands[1], operands[2],
6317 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6319 /* In 31-bit, we must load the GOT register even if the
6320 compiler doesn't know about it, because the PLT glue
6321 code uses it. In 64-bit, this is not necessary. */
6322 if (plt_call && !TARGET_64BIT)
6323 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6328 (define_expand "call_value_exp"
6329 [(parallel [(set (match_operand 0 "" "")
6330 (call (match_operand 1 "" "")
6331 (match_operand 2 "" "")))
6332 (clobber (match_operand 3 "" ""))])]
6336 (define_insn "brasl_r"
6337 [(set (match_operand 0 "register_operand" "=df")
6338 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6339 (match_operand:SI 2 "const_int_operand" "n")))
6340 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6343 [(set_attr "op_type" "RIL")
6344 (set_attr "type" "jsr")])
6346 (define_insn "bras_r"
6347 [(set (match_operand 0 "register_operand" "=df")
6348 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6349 (match_operand:SI 2 "const_int_operand" "n")))
6350 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6353 [(set_attr "op_type" "RI")
6354 (set_attr "type" "jsr")])
6356 (define_insn "basr_r_64"
6357 [(set (match_operand 0 "register_operand" "=df")
6358 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6359 (match_operand:SI 2 "const_int_operand" "n")))
6360 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6363 [(set_attr "op_type" "RR")
6364 (set_attr "type" "jsr")])
6366 (define_insn "basr_r_31"
6367 [(set (match_operand 0 "register_operand" "=df")
6368 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6369 (match_operand:SI 2 "const_int_operand" "n")))
6370 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6373 [(set_attr "op_type" "RR")
6374 (set_attr "type" "jsr")
6375 (set_attr "atype" "mem")])
6377 (define_insn "bas_r_64"
6378 [(set (match_operand 0 "register_operand" "=df")
6379 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6380 (match_operand:SI 2 "const_int_operand" "n")))
6381 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6384 [(set_attr "op_type" "RX")
6385 (set_attr "type" "jsr")
6386 (set_attr "atype" "mem")])
6388 (define_insn "bas_r_31"
6389 [(set (match_operand 0 "register_operand" "=df")
6390 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6391 (match_operand:SI 2 "const_int_operand" "n")))
6392 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6395 [(set_attr "op_type" "RX")
6396 (set_attr "type" "jsr")
6397 (set_attr "atype" "mem")])
6401 ;;- Miscellaneous instructions.
6405 ; allocate stack instruction pattern(s).
6408 (define_expand "allocate_stack"
6410 (plus (reg 15) (match_operand 1 "general_operand" "")))
6411 (set (match_operand 0 "general_operand" "")
6416 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6417 rtx chain = gen_rtx (MEM, Pmode, stack);
6418 rtx temp = gen_reg_rtx (Pmode);
6420 emit_move_insn (temp, chain);
6423 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6425 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6427 emit_move_insn (chain, temp);
6429 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6435 ; setjmp/longjmp instruction pattern(s).
6438 (define_expand "builtin_setjmp_setup"
6439 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6443 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6444 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6446 emit_move_insn (base, basereg);
6450 (define_expand "builtin_setjmp_receiver"
6451 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6455 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6456 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6457 SYMBOL_REF_FLAG (got) = 1;
6459 emit_move_insn (gotreg, got);
6460 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6464 (define_expand "builtin_longjmp"
6465 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6469 /* The elements of the buffer are, in order: */
6470 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6471 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6472 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6473 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6474 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6475 rtx jmp = gen_rtx_REG (Pmode, 14);
6477 emit_move_insn (jmp, lab);
6478 emit_move_insn (basereg, base);
6479 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6480 emit_move_insn (hard_frame_pointer_rtx, fp);
6482 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6483 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6484 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6485 emit_indirect_jump (jmp);
6490 ;; These patterns say how to save and restore the stack pointer. We need not
6491 ;; save the stack pointer at function level since we are careful to
6492 ;; preserve the backchain. At block level, we have to restore the backchain
6493 ;; when we restore the stack pointer.
6495 ;; For nonlocal gotos, we must save both the stack pointer and its
6496 ;; backchain and restore both. Note that in the nonlocal case, the
6497 ;; save area is a memory location.
6499 (define_expand "save_stack_function"
6500 [(match_operand 0 "general_operand" "")
6501 (match_operand 1 "general_operand" "")]
6505 (define_expand "restore_stack_function"
6506 [(match_operand 0 "general_operand" "")
6507 (match_operand 1 "general_operand" "")]
6511 (define_expand "restore_stack_block"
6512 [(use (match_operand 0 "register_operand" ""))
6513 (set (match_dup 2) (match_dup 3))
6514 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6515 (set (match_dup 3) (match_dup 2))]
6519 operands[2] = gen_reg_rtx (Pmode);
6520 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6523 (define_expand "save_stack_nonlocal"
6524 [(match_operand 0 "memory_operand" "")
6525 (match_operand 1 "register_operand" "")]
6529 rtx temp = gen_reg_rtx (Pmode);
6531 /* Copy the backchain to the first word, sp to the second. */
6532 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6533 emit_move_insn (operand_subword (operands[0], 0, 0,
6534 TARGET_64BIT ? TImode : DImode),
6536 emit_move_insn (operand_subword (operands[0], 1, 0,
6537 TARGET_64BIT ? TImode : DImode),
6542 (define_expand "restore_stack_nonlocal"
6543 [(match_operand 0 "register_operand" "")
6544 (match_operand 1 "memory_operand" "")]
6548 rtx temp = gen_reg_rtx (Pmode);
6550 /* Restore the backchain from the first word, sp from the second. */
6551 emit_move_insn (temp,
6552 operand_subword (operands[1], 0, 0,
6553 TARGET_64BIT ? TImode : DImode));
6554 emit_move_insn (operands[0],
6555 operand_subword (operands[1], 1, 0,
6556 TARGET_64BIT ? TImode : DImode));
6557 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6563 ; nop instruction pattern(s).
6570 [(set_attr "op_type" "RR")])
6574 ; Special literal pool access instruction pattern(s).
6577 (define_insn "consttable_qi"
6578 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6582 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6585 [(set_attr "op_type" "NN")
6586 (set_attr "length" "1")])
6588 (define_insn "consttable_hi"
6589 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6593 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6596 [(set_attr "op_type" "NN")
6597 (set_attr "length" "2")])
6599 (define_insn "consttable_si"
6600 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6604 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6605 return \".long\\t%0\";
6607 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6610 [(set_attr "op_type" "NN")
6611 (set_attr "length" "4")])
6613 (define_insn "consttable_di"
6614 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6618 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6621 [(set_attr "op_type" "NN")
6622 (set_attr "length" "8")])
6624 (define_insn "consttable_sf"
6625 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6631 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6634 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6635 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6638 [(set_attr "op_type" "NN")
6639 (set_attr "length" "4")])
6641 (define_insn "consttable_df"
6642 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6648 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6651 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6652 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6655 [(set_attr "op_type" "NN")
6656 (set_attr "length" "8")])
6658 (define_insn "pool_start_31"
6659 [(unspec_volatile [(const_int 0)] 206)]
6662 [(set_attr "op_type" "NN")
6663 (set_attr "length" "2")])
6665 (define_insn "pool_end_31"
6666 [(unspec_volatile [(const_int 0)] 207)]
6669 [(set_attr "op_type" "NN")
6670 (set_attr "length" "2")])
6672 (define_insn "pool_start_64"
6673 [(unspec_volatile [(const_int 0)] 206)]
6675 ".section\\t.rodata\;.align\\t8"
6676 [(set_attr "op_type" "NN")
6677 (set_attr "length" "0")])
6679 (define_insn "pool_end_64"
6680 [(unspec_volatile [(const_int 0)] 207)]
6683 [(set_attr "op_type" "NN")
6684 (set_attr "length" "0")])
6686 (define_insn "reload_base"
6687 [(set (match_operand:SI 0 "register_operand" "=a")
6688 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6690 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6691 [(set_attr "op_type" "NN")
6692 (set_attr "type" "la")
6693 (set_attr "length" "6")])
6695 (define_insn "reload_base2"
6696 [(set (match_operand:SI 0 "register_operand" "=a")
6697 (unspec:SI [(label_ref (match_operand 1 "" ""))] 211))]
6700 [(set_attr "op_type" "NN")
6701 (set_attr "type" "la")
6702 (set_attr "length" "4")])
6706 ;; Insns related to generating the function prologue and epilogue.
6710 (define_expand "prologue"
6711 [(use (const_int 0))]
6715 s390_emit_prologue ();
6719 (define_expand "epilogue"
6720 [(use (const_int 1))]
6724 s390_emit_epilogue ();
6729 (define_insn "*return_si"
6731 (use (match_operand:SI 0 "register_operand" "a"))]
6734 [(set_attr "op_type" "RR")
6735 (set_attr "type" "jsr")
6736 (set_attr "atype" "mem")])
6738 (define_insn "*return_di"
6740 (use (match_operand:DI 0 "register_operand" "a"))]
6743 [(set_attr "op_type" "RR")
6744 (set_attr "type" "jsr")
6745 (set_attr "atype" "mem")])
6749 [(set (reg 13) (pc))
6750 (unspec_volatile [(const_int 0)] 200)]
6754 s390_output_constant_pool (asm_out_file);
6757 [(set_attr "op_type" "NN")
6758 (set_attr "type" "integer")])
6762 ;; Peephole optimization patterns.
6766 [(set (match_operand:SI 0 "memory_operand" "m")
6767 (match_operand:SI 1 "register_operand" "d"))
6774 [(set (match_operand:SI 0 "memory_operand" "m")
6775 (match_operand:SI 1 "register_operand" "d"))
6782 [(set (match_operand:SI 0 "register_operand" "")
6783 (match_operand:SI 1 "register_operand" ""))
6786 (plus:SI (match_dup 0)
6787 (match_operand:SI 2 "immediate_operand" "")))
6788 (clobber (reg:CC 33))])]
6789 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6790 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6791 REGNO (operands[0]) == BASE_REGISTER ||
6792 REGNO (operands[1]) == BASE_REGISTER) &&
6793 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6797 ; peepholes for fast char instructions
6801 ; [(set (match_operand:QI 0 "register_operand" "d")
6802 ; (match_operand:QI 1 "s_operand" "Q"))
6803 ; (set (match_operand:SI 2 "register_operand" "0")
6804 ; (zero_extend:SI (match_dup 0)))]
6805 ; "REGNO(operands[0]) == REGNO(operands[2])"
6806 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6809 ; [(set (match_operand:QI 0 "register_operand" "d")
6810 ; (match_operand:QI 1 "s_operand" "Q"))
6811 ; (set (match_operand:SI 2 "register_operand" "0")
6812 ; (sign_extend:SI (match_dup 0)))]
6813 ; "REGNO(operands[0]) == REGNO(operands[2])"
6814 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6817 [(set (match_operand:QI 0 "register_operand" "d")
6818 (match_operand:QI 1 "immediate_operand" "J"))
6819 (set (match_operand:SI 2 "register_operand" "0" )
6820 (sign_extend:SI (match_dup 0) ) )]
6821 "REGNO(operands[0]) == REGNO(operands[2])"
6825 ; peepholes for fast short instructions
6829 ; [(set (match_operand:HI 0 "register_operand" "d")
6830 ; (match_operand:HI 1 "s_operand" "Q"))
6831 ; (set (match_operand:SI 2 "register_operand" "0" )
6832 ; (zero_extend:SI (match_dup 0)))]
6833 ; "REGNO(operands[0]) == REGNO(operands[2])"
6834 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6837 [(set (match_operand:HI 0 "register_operand" "d")
6838 (match_operand:HI 1 "memory_operand" "m"))
6839 (set (match_operand:SI 2 "register_operand" "0" )
6840 (sign_extend:SI (match_dup 0)))]
6841 "REGNO(operands[0]) == REGNO(operands[2])"
6845 [(set (match_operand:HI 0 "register_operand" "d")
6846 (match_operand:HI 1 "immediate_operand" "K"))
6847 (set (match_operand:SI 2 "register_operand" "0" )
6848 (sign_extend:SI (match_dup 0) ) )]
6849 "REGNO(operands[0]) == REGNO(operands[2])"
6853 ; peepholes for divide instructions
6857 [(set (match_operand:DI 0 "register_operand" "d")
6858 (match_operand:DI 1 "memory_operand" "m"))
6860 (lshiftrt:DI (match_dup 0)
6861 (match_operand:SI 2 "immediate_operand" "J")))
6863 (div:SI (match_dup 0)
6864 (match_operand:SI 3 "nonimmediate_operand" "g")))
6870 output_asm_insn (\"l\\t%0,%1\", operands);
6871 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6873 if (REG_P (operands[3]))
6874 output_asm_insn (\"dr\\t%0,%3\", operands);
6876 output_asm_insn (\"d\\t%0,%3\", operands);
6878 return \"st\\t%N0,%N1\";
6882 [(set (match_operand:DI 0 "register_operand" "d")
6883 (match_operand:DI 1 "memory_operand" "m"))
6885 (lshiftrt:DI (match_dup 0)
6886 (match_operand:SI 2 "immediate_operand" "J")))
6888 (mod:SI (match_dup 0)
6889 (match_operand:SI 3 "nonimmediate_operand" "g")))
6895 output_asm_insn (\"l\\t%0,%1\", operands);
6896 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6898 if (REG_P (operands[3]))
6899 output_asm_insn (\"dr\\t%0,%3\", operands);
6901 output_asm_insn (\"d\\t%0,%3\", operands);
6903 return \"st\\t%0,%1\";