1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; GOT/PLT and lt-relative accesses
94 ; TLS relocation specifiers
110 ; Stack Smashing Protector
114 ; Test Data Class (TDC)
126 UNSPEC_FPINT_NEARBYINT
134 UNSPEC_VEC_GENBYTEMASK
137 UNSPEC_VEC_SMULT_EVEN
138 UNSPEC_VEC_UMULT_EVEN
147 ;; UNSPEC_VOLATILE usage
150 (define_c_enum "unspecv" [
172 ; Hotpatching (unremovable NOPs)
177 ; Transactional Execution support
187 ; Set and get floating point control register
196 ; Registers with special meaning
200 ; Sibling call register.
202 ; Literal pool base register.
204 ; Return address register.
206 ; Condition code register.
208 ; Thread local storage pointer register.
212 ; Hardware register names
216 ; General purpose registers
218 ; Floating point registers.
243 ;; PFPO GPR0 argument format
248 ; PFPO operation type
249 (PFPO_CONVERT 0x1000000)
251 (PFPO_OP_TYPE_SF 0x5)
252 (PFPO_OP_TYPE_DF 0x6)
253 (PFPO_OP_TYPE_TF 0x7)
254 (PFPO_OP_TYPE_SD 0x8)
255 (PFPO_OP_TYPE_DD 0x9)
256 (PFPO_OP_TYPE_TD 0xa)
257 ; Bitposition of operand types
258 (PFPO_OP0_TYPE_SHIFT 16)
259 (PFPO_OP1_TYPE_SHIFT 8)
262 ; Immediate operands for tbegin and tbeginc
263 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
264 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
266 ;; Instruction operand type as used in the Principles of Operation.
267 ;; Used to determine defaults for length and other attribute values.
269 (define_attr "op_type"
270 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
273 ;; Instruction type attribute used for scheduling.
275 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
276 cs,vs,store,sem,idiv,
277 imulhi,imulsi,imuldi,
278 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
279 floadtf,floaddf,floadsf,fstoredf,fstoresf,
280 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
281 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
283 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
284 itoftf, itofdf, itofsf, itofdd, itoftd,
285 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
286 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
288 (cond [(eq_attr "op_type" "NN") (const_string "other")
289 (eq_attr "op_type" "SS") (const_string "cs")]
290 (const_string "integer")))
292 ;; Another attribute used for scheduling purposes:
293 ;; agen: Instruction uses the address generation unit
294 ;; reg: Instruction does not use the agen unit
296 (define_attr "atype" "agen,reg"
297 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
299 (const_string "agen")))
301 ;; Properties concerning Z10 execution grouping and value forwarding.
302 ;; z10_super: instruction is superscalar.
303 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
304 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
305 ;; target register. It can forward this value to a second instruction that reads
306 ;; the same register if that second instruction is issued in the same group.
307 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
308 ;; instruction in the S pipe writes to the register, then the T instruction
309 ;; can immediately read the new value.
310 ;; z10_fr: union of Z10_fwd and z10_rec.
311 ;; z10_c: second operand of instruction is a register and read with complemented bits.
313 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
316 (define_attr "z10prop" "none,
317 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
318 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
320 z10_fr, z10_fr_A3, z10_fr_E1,
322 (const_string "none"))
324 ;; Properties concerning Z196 decoding
325 ;; z196_alone: must group alone
326 ;; z196_end: ends a group
327 ;; z196_cracked: instruction is cracked or expanded
328 (define_attr "z196prop" "none,
329 z196_alone, z196_ends,
331 (const_string "none"))
333 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
337 (define_attr "length" ""
338 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
339 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
343 ;; Processor type. This attribute must exactly match the processor_type
344 ;; enumeration in s390.h. The current machine description does not
345 ;; distinguish between g5 and g6, but there are differences between the two
346 ;; CPUs could in theory be modeled.
348 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
349 (const (symbol_ref "s390_tune_attr")))
351 (define_attr "cpu_facility"
352 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
353 (const_string "standard"))
355 (define_attr "enabled" ""
356 (cond [(eq_attr "cpu_facility" "standard")
359 (and (eq_attr "cpu_facility" "ieee")
360 (match_test "TARGET_CPU_IEEE_FLOAT"))
363 (and (eq_attr "cpu_facility" "zarch")
364 (match_test "TARGET_ZARCH"))
367 (and (eq_attr "cpu_facility" "longdisp")
368 (match_test "TARGET_LONG_DISPLACEMENT"))
371 (and (eq_attr "cpu_facility" "extimm")
372 (match_test "TARGET_EXTIMM"))
375 (and (eq_attr "cpu_facility" "dfp")
376 (match_test "TARGET_DFP"))
379 (and (eq_attr "cpu_facility" "cpu_zarch")
380 (match_test "TARGET_CPU_ZARCH"))
383 (and (eq_attr "cpu_facility" "z10")
384 (match_test "TARGET_Z10"))
387 (and (eq_attr "cpu_facility" "z196")
388 (match_test "TARGET_Z196"))
391 (and (eq_attr "cpu_facility" "zEC12")
392 (match_test "TARGET_ZEC12"))
395 (and (eq_attr "cpu_facility" "vec")
396 (match_test "TARGET_VX"))
400 ;; Pipeline description for z900. For lack of anything better,
401 ;; this description is also used for the g5 and g6.
404 ;; Pipeline description for z990, z9-109 and z9-ec.
407 ;; Pipeline description for z10
410 ;; Pipeline description for z196
413 ;; Pipeline description for zEC12
417 (include "predicates.md")
419 ;; Constraint definitions
420 (include "constraints.md")
427 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
429 ;; These mode iterators allow floating point patterns to be generated from the
431 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
432 (SD "TARGET_HARD_DFP")])
433 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
434 (define_mode_iterator BFP [TF DF SF])
435 (define_mode_iterator DFP [TD DD])
436 (define_mode_iterator DFP_ALL [TD DD SD])
437 (define_mode_iterator DSF [DF SF])
438 (define_mode_iterator SD_SF [SF SD])
439 (define_mode_iterator DD_DF [DF DD])
440 (define_mode_iterator TD_TF [TF TD])
442 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
443 ;; from the same template.
444 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
445 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
446 (define_mode_iterator DSI [DI SI])
447 (define_mode_iterator TDI [TI DI])
449 ;; These mode iterators allow :P to be used for patterns that operate on
450 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
451 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
453 ;; These macros refer to the actual word_mode of the configuration.
454 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
455 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
456 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
458 ;; Used by the umul pattern to express modes having half the size.
459 (define_mode_attr DWH [(TI "DI") (DI "SI")])
460 (define_mode_attr dwh [(TI "di") (DI "si")])
462 ;; This mode iterator allows the QI and HI patterns to be defined from
463 ;; the same template.
464 (define_mode_iterator HQI [HI QI])
466 ;; This mode iterator allows the integer patterns to be defined from the
468 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
469 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
471 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
472 ;; the same template.
473 (define_code_iterator SHIFT [ashift lshiftrt])
475 ;; This iterator allows r[ox]sbg to be defined with the same template
476 (define_code_iterator IXOR [ior xor])
478 ;; This iterator is used to expand the patterns for the nearest
479 ;; integer functions.
480 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
481 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
482 UNSPEC_FPINT_NEARBYINT])
483 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
484 (UNSPEC_FPINT_BTRUNC "btrunc")
485 (UNSPEC_FPINT_ROUND "round")
486 (UNSPEC_FPINT_CEIL "ceil")
487 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
488 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
489 (UNSPEC_FPINT_BTRUNC "5")
490 (UNSPEC_FPINT_ROUND "1")
491 (UNSPEC_FPINT_CEIL "6")
492 (UNSPEC_FPINT_NEARBYINT "0")])
494 ;; This iterator and attribute allow to combine most atomic operations.
495 (define_code_iterator ATOMIC [and ior xor plus minus mult])
496 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
497 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
498 (plus "add") (minus "sub") (mult "nand")])
499 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
501 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
502 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
503 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
505 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
506 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
508 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
510 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
511 ;; Likewise for "<RXe>".
512 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
513 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
515 ;; The decimal floating point variants of add, sub, div and mul support 3
516 ;; fp register operands. The following attributes allow to merge the bfp and
517 ;; dfp variants in a single insn definition.
519 ;; This attribute is used to set op_type accordingly.
520 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
521 (DD "RRR") (SD "RRR")])
523 ;; This attribute is used in the operand constraint list in order to have the
524 ;; first and the second operand match for bfp modes.
525 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
527 ;; This attribute is used in the operand list of the instruction to have an
528 ;; additional operand for the dfp instructions.
529 (define_mode_attr op1 [(TF "") (DF "") (SF "")
530 (TD "%1,") (DD "%1,") (SD "%1,")])
533 ;; This attribute is used in the operand constraint list
534 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
535 ;; TFmode values are represented by a fp register pair. Since the
536 ;; sign bit instructions only handle single source and target fp registers
537 ;; these instructions can only be used for TFmode values if the source and
538 ;; target operand uses the same fp register.
539 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
541 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
542 ;; This is used to disable the memory alternative in TFmode patterns.
543 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
545 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
546 ;; within instruction mnemonics.
547 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
549 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
550 ;; modes and to an empty string for bfp modes.
551 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
553 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
554 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
555 ;; version only operates on one register.
556 (define_mode_attr d0 [(DI "d") (SI "0")])
558 ;; In combination with d0 this allows to combine instructions of which the 31bit
559 ;; version only operates on one register. The DImode version needs an additional
560 ;; register for the assembler output.
561 (define_mode_attr 1 [(DI "%1,") (SI "")])
563 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
564 ;; 'ashift' and "srdl" in 'lshiftrt'.
565 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
567 ;; In SHIFT templates, this attribute holds the correct standard name for the
568 ;; pattern itself and the corresponding function calls.
569 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
571 ;; This attribute handles differences in the instruction 'type' and will result
572 ;; in "RRE" for DImode and "RR" for SImode.
573 (define_mode_attr E [(DI "E") (SI "")])
575 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
576 ;; to result in "RXY" for DImode and "RX" for SImode.
577 (define_mode_attr Y [(DI "Y") (SI "")])
579 ;; This attribute handles differences in the instruction 'type' and will result
580 ;; in "RSE" for TImode and "RS" for DImode.
581 (define_mode_attr TE [(TI "E") (DI "")])
583 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
584 ;; and "lcr" in SImode.
585 (define_mode_attr g [(DI "g") (SI "")])
587 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
588 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
589 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
590 ;; variant for long displacements.
591 (define_mode_attr y [(DI "g") (SI "y")])
593 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
594 ;; and "cds" in DImode.
595 (define_mode_attr tg [(TI "g") (DI "")])
597 ;; In TDI templates, a string like "c<d>sg".
598 (define_mode_attr td [(TI "d") (DI "")])
600 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
601 ;; and "cfdbr" in SImode.
602 (define_mode_attr gf [(DI "g") (SI "f")])
604 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
605 ;; and sllk for SI. This way it is possible to merge the new z196 SI
606 ;; 3 operands shift instructions into the existing patterns.
607 (define_mode_attr gk [(DI "g") (SI "k")])
609 ;; ICM mask required to load MODE value into the lowest subreg
610 ;; of a SImode register.
611 (define_mode_attr icm_lo [(HI "3") (QI "1")])
613 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
614 ;; HImode and "llgc" in QImode.
615 (define_mode_attr hc [(HI "h") (QI "c")])
617 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
619 (define_mode_attr DBL [(DI "TI") (SI "DI")])
621 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
622 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
623 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
625 ;; Maximum unsigned integer that fits in MODE.
626 (define_mode_attr max_uint [(HI "65535") (QI "255")])
628 ;; Start and end field computations for RISBG et al.
629 (define_mode_attr bfstart [(DI "s") (SI "t")])
630 (define_mode_attr bfend [(DI "e") (SI "f")])
632 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
633 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
635 ;; Allow return and simple_return to be defined from a single template.
636 (define_code_iterator ANY_RETURN [return simple_return])
638 (include "vector.md")
641 ;;- Compare instructions.
644 ; Test-under-Mask instructions
646 (define_insn "*tmqi_mem"
647 [(set (reg CC_REGNUM)
648 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
649 (match_operand:QI 1 "immediate_operand" "n,n"))
650 (match_operand:QI 2 "immediate_operand" "n,n")))]
651 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
655 [(set_attr "op_type" "SI,SIY")
656 (set_attr "z10prop" "z10_super,z10_super")])
658 (define_insn "*tmdi_reg"
659 [(set (reg CC_REGNUM)
660 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
661 (match_operand:DI 1 "immediate_operand"
662 "N0HD0,N1HD0,N2HD0,N3HD0"))
663 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
665 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
666 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
672 [(set_attr "op_type" "RI")
673 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
675 (define_insn "*tmsi_reg"
676 [(set (reg CC_REGNUM)
677 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
678 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
679 (match_operand:SI 2 "immediate_operand" "n,n")))]
680 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
681 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
685 [(set_attr "op_type" "RI")
686 (set_attr "z10prop" "z10_super,z10_super")])
688 (define_insn "*tm<mode>_full"
689 [(set (reg CC_REGNUM)
690 (compare (match_operand:HQI 0 "register_operand" "d")
691 (match_operand:HQI 1 "immediate_operand" "n")))]
692 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
694 [(set_attr "op_type" "RI")
695 (set_attr "z10prop" "z10_super")])
699 ; Load-and-Test instructions
702 ; tst(di|si) instruction pattern(s).
704 (define_insn "*tstdi_sign"
705 [(set (reg CC_REGNUM)
709 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
710 (const_int 32)) (const_int 32))
711 (match_operand:DI 1 "const0_operand" "")))
712 (set (match_operand:DI 2 "register_operand" "=d,d")
713 (sign_extend:DI (match_dup 0)))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
717 [(set_attr "op_type" "RRE,RXY")
718 (set_attr "cpu_facility" "*,z10")
719 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
722 (define_insn "*tst<mode>_extimm"
723 [(set (reg CC_REGNUM)
724 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
725 (match_operand:GPR 1 "const0_operand" "")))
726 (set (match_operand:GPR 2 "register_operand" "=d,d")
728 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
732 [(set_attr "op_type" "RR<E>,RXY")
733 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
736 (define_insn "*tst<mode>_cconly_extimm"
737 [(set (reg CC_REGNUM)
738 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
739 (match_operand:GPR 1 "const0_operand" "")))
740 (clobber (match_scratch:GPR 2 "=X,d"))]
741 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
745 [(set_attr "op_type" "RR<E>,RXY")
746 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
748 (define_insn "*tstdi"
749 [(set (reg CC_REGNUM)
750 (compare (match_operand:DI 0 "register_operand" "d")
751 (match_operand:DI 1 "const0_operand" "")))
752 (set (match_operand:DI 2 "register_operand" "=d")
754 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
756 [(set_attr "op_type" "RRE")
757 (set_attr "z10prop" "z10_fr_E1")])
759 (define_insn "*tstsi"
760 [(set (reg CC_REGNUM)
761 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
762 (match_operand:SI 1 "const0_operand" "")))
763 (set (match_operand:SI 2 "register_operand" "=d,d,d")
765 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
770 [(set_attr "op_type" "RR,RS,RSY")
771 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
773 (define_insn "*tstsi_cconly"
774 [(set (reg CC_REGNUM)
775 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
776 (match_operand:SI 1 "const0_operand" "")))
777 (clobber (match_scratch:SI 2 "=X,d,d"))]
778 "s390_match_ccmode(insn, CCSmode)"
783 [(set_attr "op_type" "RR,RS,RSY")
784 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
786 (define_insn "*tstdi_cconly_31"
787 [(set (reg CC_REGNUM)
788 (compare (match_operand:DI 0 "register_operand" "d")
789 (match_operand:DI 1 "const0_operand" "")))]
790 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
792 [(set_attr "op_type" "RS")
793 (set_attr "atype" "reg")])
796 (define_insn "*tst<mode>_cconly2"
797 [(set (reg CC_REGNUM)
798 (compare (match_operand:GPR 0 "register_operand" "d")
799 (match_operand:GPR 1 "const0_operand" "")))]
800 "s390_match_ccmode(insn, CCSmode)"
802 [(set_attr "op_type" "RR<E>")
803 (set_attr "z10prop" "z10_fr_E1")])
805 ; tst(hi|qi) instruction pattern(s).
807 (define_insn "*tst<mode>CCT"
808 [(set (reg CC_REGNUM)
809 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
810 (match_operand:HQI 1 "const0_operand" "")))
811 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
813 "s390_match_ccmode(insn, CCTmode)"
816 icmy\t%2,<icm_lo>,%S0
818 [(set_attr "op_type" "RS,RSY,RI")
819 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
821 (define_insn "*tsthiCCT_cconly"
822 [(set (reg CC_REGNUM)
823 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
824 (match_operand:HI 1 "const0_operand" "")))
825 (clobber (match_scratch:HI 2 "=d,d,X"))]
826 "s390_match_ccmode(insn, CCTmode)"
831 [(set_attr "op_type" "RS,RSY,RI")
832 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
834 (define_insn "*tstqiCCT_cconly"
835 [(set (reg CC_REGNUM)
836 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
837 (match_operand:QI 1 "const0_operand" "")))]
838 "s390_match_ccmode(insn, CCTmode)"
843 [(set_attr "op_type" "SI,SIY,RI")
844 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
846 (define_insn "*tst<mode>"
847 [(set (reg CC_REGNUM)
848 (compare (match_operand:HQI 0 "s_operand" "Q,S")
849 (match_operand:HQI 1 "const0_operand" "")))
850 (set (match_operand:HQI 2 "register_operand" "=d,d")
852 "s390_match_ccmode(insn, CCSmode)"
855 icmy\t%2,<icm_lo>,%S0"
856 [(set_attr "op_type" "RS,RSY")
857 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
859 (define_insn "*tst<mode>_cconly"
860 [(set (reg CC_REGNUM)
861 (compare (match_operand:HQI 0 "s_operand" "Q,S")
862 (match_operand:HQI 1 "const0_operand" "")))
863 (clobber (match_scratch:HQI 2 "=d,d"))]
864 "s390_match_ccmode(insn, CCSmode)"
867 icmy\t%2,<icm_lo>,%S0"
868 [(set_attr "op_type" "RS,RSY")
869 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
872 ; Compare (equality) instructions
874 (define_insn "*cmpdi_cct"
875 [(set (reg CC_REGNUM)
876 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
877 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
878 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
885 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
886 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
888 (define_insn "*cmpsi_cct"
889 [(set (reg CC_REGNUM)
890 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
891 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
892 "s390_match_ccmode (insn, CCTmode)"
900 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
901 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
903 ; Compare (signed) instructions
905 (define_insn "*cmpdi_ccs_sign"
906 [(set (reg CC_REGNUM)
907 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
909 (match_operand:DI 0 "register_operand" "d, d,d")))]
910 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
915 [(set_attr "op_type" "RRE,RXY,RIL")
916 (set_attr "z10prop" "z10_c,*,*")
917 (set_attr "type" "*,*,larl")])
921 (define_insn "*cmpsi_ccs_sign"
922 [(set (reg CC_REGNUM)
923 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
924 (match_operand:SI 0 "register_operand" "d,d,d")))]
925 "s390_match_ccmode(insn, CCSRmode)"
930 [(set_attr "op_type" "RX,RXY,RIL")
931 (set_attr "cpu_facility" "*,*,z10")
932 (set_attr "type" "*,*,larl")
933 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
935 (define_insn "*cmphi_ccs_z10"
936 [(set (reg CC_REGNUM)
937 (compare (match_operand:HI 0 "s_operand" "Q")
938 (match_operand:HI 1 "immediate_operand" "K")))]
939 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
941 [(set_attr "op_type" "SIL")
942 (set_attr "z196prop" "z196_cracked")])
944 (define_insn "*cmpdi_ccs_signhi_rl"
945 [(set (reg CC_REGNUM)
946 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
947 (match_operand:GPR 0 "register_operand" "d,d")))]
948 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
952 [(set_attr "op_type" "RXY,RIL")
953 (set_attr "type" "*,larl")])
955 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
956 (define_insn "*cmp<mode>_ccs"
957 [(set (reg CC_REGNUM)
958 (compare (match_operand:GPR 0 "nonimmediate_operand"
960 (match_operand:GPR 1 "general_operand"
962 "s390_match_ccmode(insn, CCSmode)"
971 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
972 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
973 (set_attr "type" "*,*,*,*,*,*,larl")
974 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
977 ; Compare (unsigned) instructions
979 (define_insn "*cmpsi_ccu_zerohi_rlsi"
980 [(set (reg CC_REGNUM)
981 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
982 "larl_operand" "X")))
983 (match_operand:SI 0 "register_operand" "d")))]
984 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
986 [(set_attr "op_type" "RIL")
987 (set_attr "type" "larl")
988 (set_attr "z10prop" "z10_super")])
991 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
992 [(set (reg CC_REGNUM)
993 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
994 "larl_operand" "X")))
995 (match_operand:GPR 0 "register_operand" "d")))]
996 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
998 [(set_attr "op_type" "RIL")
999 (set_attr "type" "larl")
1000 (set_attr "z10prop" "z10_super")])
1002 (define_insn "*cmpdi_ccu_zero"
1003 [(set (reg CC_REGNUM)
1004 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1006 (match_operand:DI 0 "register_operand" "d, d,d")))]
1007 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1012 [(set_attr "op_type" "RRE,RXY,RIL")
1013 (set_attr "cpu_facility" "*,*,z10")
1014 (set_attr "type" "*,*,larl")
1015 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1017 (define_insn "*cmpdi_ccu"
1018 [(set (reg CC_REGNUM)
1019 (compare (match_operand:DI 0 "nonimmediate_operand"
1020 "d, d,d,Q, d, Q,BQ")
1021 (match_operand:DI 1 "general_operand"
1022 "d,Op,b,D,RT,BQ,Q")))]
1023 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1032 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1033 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1034 (set_attr "type" "*,*,larl,*,*,*,*")
1035 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1037 (define_insn "*cmpsi_ccu"
1038 [(set (reg CC_REGNUM)
1039 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1040 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1041 "s390_match_ccmode (insn, CCUmode)"
1051 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1052 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1053 (set_attr "type" "*,*,larl,*,*,*,*,*")
1054 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1056 (define_insn "*cmphi_ccu"
1057 [(set (reg CC_REGNUM)
1058 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1059 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1060 "s390_match_ccmode (insn, CCUmode)
1061 && !register_operand (operands[1], HImode)"
1068 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1069 (set_attr "cpu_facility" "*,*,z10,*,*")
1070 (set_attr "z10prop" "*,*,z10_super,*,*")])
1072 (define_insn "*cmpqi_ccu"
1073 [(set (reg CC_REGNUM)
1074 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1075 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1076 "s390_match_ccmode (insn, CCUmode)
1077 && !register_operand (operands[1], QImode)"
1085 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1086 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1089 ; Block compare (CLC) instruction patterns.
1092 [(set (reg CC_REGNUM)
1093 (compare (match_operand:BLK 0 "memory_operand" "Q")
1094 (match_operand:BLK 1 "memory_operand" "Q")))
1095 (use (match_operand 2 "const_int_operand" "n"))]
1096 "s390_match_ccmode (insn, CCUmode)
1097 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1098 "clc\t%O0(%2,%R0),%S1"
1099 [(set_attr "op_type" "SS")])
1102 [(set (reg CC_REGNUM)
1103 (compare (match_operand 0 "memory_operand" "")
1104 (match_operand 1 "memory_operand" "")))]
1106 && s390_match_ccmode (insn, CCUmode)
1107 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1108 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1110 [(set (match_dup 0) (match_dup 1))
1111 (use (match_dup 2))])]
1113 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1114 operands[0] = adjust_address (operands[0], BLKmode, 0);
1115 operands[1] = adjust_address (operands[1], BLKmode, 0);
1117 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1118 operands[0], operands[1]);
1119 operands[0] = SET_DEST (PATTERN (curr_insn));
1123 ; (TF|DF|SF|TD|DD|SD) instructions
1125 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1126 (define_insn "*cmp<mode>_ccs_0"
1127 [(set (reg CC_REGNUM)
1128 (compare (match_operand:FP 0 "register_operand" "f")
1129 (match_operand:FP 1 "const0_operand" "")))]
1130 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1131 "lt<xde><bt>r\t%0,%0"
1132 [(set_attr "op_type" "RRE")
1133 (set_attr "type" "fsimp<mode>")])
1135 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1136 (define_insn "*cmp<mode>_ccs"
1137 [(set (reg CC_REGNUM)
1138 (compare (match_operand:FP 0 "register_operand" "f,f")
1139 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1140 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1144 [(set_attr "op_type" "RRE,RXE")
1145 (set_attr "type" "fsimp<mode>")])
1148 ; Compare and Branch instructions
1150 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1151 ; The following instructions do a complementary access of their second
1152 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1153 (define_insn "*cmp_and_br_signed_<mode>"
1155 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1156 [(match_operand:GPR 1 "register_operand" "d,d")
1157 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1158 (label_ref (match_operand 3 "" ""))
1160 (clobber (reg:CC CC_REGNUM))]
1161 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1163 if (get_attr_length (insn) == 6)
1164 return which_alternative ?
1165 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1167 return which_alternative ?
1168 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1170 [(set_attr "op_type" "RIE")
1171 (set_attr "type" "branch")
1172 (set_attr "z10prop" "z10_super_c,z10_super")
1173 (set (attr "length")
1174 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1175 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1176 ; 10 byte for cgr/jg
1178 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1179 ; The following instructions do a complementary access of their second
1180 ; operand (z10 only): clrj, clgrj, clr, clgr
1181 (define_insn "*cmp_and_br_unsigned_<mode>"
1183 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1184 [(match_operand:GPR 1 "register_operand" "d,d")
1185 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1186 (label_ref (match_operand 3 "" ""))
1188 (clobber (reg:CC CC_REGNUM))]
1189 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1191 if (get_attr_length (insn) == 6)
1192 return which_alternative ?
1193 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1195 return which_alternative ?
1196 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1198 [(set_attr "op_type" "RIE")
1199 (set_attr "type" "branch")
1200 (set_attr "z10prop" "z10_super_c,z10_super")
1201 (set (attr "length")
1202 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1203 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1204 ; 10 byte for clgr/jg
1206 ; And now the same two patterns as above but with a negated CC mask.
1208 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1209 ; The following instructions do a complementary access of their second
1210 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1211 (define_insn "*icmp_and_br_signed_<mode>"
1213 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1214 [(match_operand:GPR 1 "register_operand" "d,d")
1215 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1217 (label_ref (match_operand 3 "" ""))))
1218 (clobber (reg:CC CC_REGNUM))]
1219 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1221 if (get_attr_length (insn) == 6)
1222 return which_alternative ?
1223 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1225 return which_alternative ?
1226 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1228 [(set_attr "op_type" "RIE")
1229 (set_attr "type" "branch")
1230 (set_attr "z10prop" "z10_super_c,z10_super")
1231 (set (attr "length")
1232 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1233 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1234 ; 10 byte for cgr/jg
1236 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1237 ; The following instructions do a complementary access of their second
1238 ; operand (z10 only): clrj, clgrj, clr, clgr
1239 (define_insn "*icmp_and_br_unsigned_<mode>"
1241 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1242 [(match_operand:GPR 1 "register_operand" "d,d")
1243 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1245 (label_ref (match_operand 3 "" ""))))
1246 (clobber (reg:CC CC_REGNUM))]
1247 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1249 if (get_attr_length (insn) == 6)
1250 return which_alternative ?
1251 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1253 return which_alternative ?
1254 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1256 [(set_attr "op_type" "RIE")
1257 (set_attr "type" "branch")
1258 (set_attr "z10prop" "z10_super_c,z10_super")
1259 (set (attr "length")
1260 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1261 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1262 ; 10 byte for clgr/jg
1265 ;;- Move instructions.
1269 ; movti instruction pattern(s).
1272 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1273 ; for TImode (use double-int for the calculations)
1274 (define_insn "movti"
1275 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o")
1276 (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
1290 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1291 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1292 (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1295 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1296 (match_operand:TI 1 "general_operand" ""))]
1297 "TARGET_ZARCH && reload_completed
1298 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1299 [(set (match_dup 2) (match_dup 4))
1300 (set (match_dup 3) (match_dup 5))]
1302 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1303 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1304 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1305 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1309 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1310 (match_operand:TI 1 "general_operand" ""))]
1311 "TARGET_ZARCH && reload_completed
1312 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1313 [(set (match_dup 2) (match_dup 4))
1314 (set (match_dup 3) (match_dup 5))]
1316 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1317 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1318 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1319 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1322 ; Use part of the TImode target reg to perform the address
1323 ; calculation. If the TImode value is supposed to be copied into a VR
1324 ; this splitter is not necessary.
1326 [(set (match_operand:TI 0 "register_operand" "")
1327 (match_operand:TI 1 "memory_operand" ""))]
1328 "TARGET_ZARCH && reload_completed
1329 && !VECTOR_REG_P (operands[0])
1330 && !s_operand (operands[1], VOIDmode)"
1331 [(set (match_dup 0) (match_dup 1))]
1333 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1334 addr = gen_lowpart (Pmode, addr);
1335 s390_load_address (addr, XEXP (operands[1], 0));
1336 operands[1] = replace_equiv_address (operands[1], addr);
1340 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1341 ; For the higher order bits we do simply a DImode move while the
1342 ; second part is done via vec extract. Both will end up as vlgvg.
1344 [(set (match_operand:TI 0 "register_operand" "")
1345 (match_operand:TI 1 "register_operand" ""))]
1346 "TARGET_VX && reload_completed
1347 && GENERAL_REG_P (operands[0])
1348 && VECTOR_REG_P (operands[1])"
1349 [(set (match_dup 2) (match_dup 4))
1350 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1351 UNSPEC_VEC_EXTRACT))]
1353 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1354 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1355 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1356 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1360 ; Patterns used for secondary reloads
1363 ; z10 provides move instructions accepting larl memory operands.
1364 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1365 ; These patterns are also used for unaligned SI and DI accesses.
1367 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1368 [(parallel [(match_operand:ALL 0 "memory_operand" "")
1369 (match_operand:ALL 1 "register_operand" "=d")
1370 (match_operand:P 2 "register_operand" "=&a")])]
1373 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1377 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1378 [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1379 (match_operand:ALL 1 "memory_operand" "")
1380 (match_operand:P 2 "register_operand" "=a")])]
1383 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1387 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1388 [(parallel [(match_operand:P 0 "register_operand" "=d")
1389 (match_operand:P 1 "larl_operand" "")
1390 (match_operand:P 2 "register_operand" "=a")])]
1393 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1397 ; Handles loading a PLUS (load address) expression
1399 (define_expand "reload<mode>_plus"
1400 [(parallel [(match_operand:P 0 "register_operand" "=a")
1401 (match_operand:P 1 "s390_plus_operand" "")
1402 (match_operand:P 2 "register_operand" "=&a")])]
1405 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1409 ; Not all the indirect memory access instructions support the full
1410 ; format (long disp + index + base). So whenever a move from/to such
1411 ; an address is required and the instruction cannot deal with it we do
1412 ; a load address into a scratch register first and use this as the new
1414 ; This in particular is used for:
1415 ; - non-offsetable memory accesses for multiword moves
1416 ; - full vector reg moves with long displacements
1418 (define_expand "reload<mode>_la_in"
1419 [(parallel [(match_operand 0 "register_operand" "")
1420 (match_operand 1 "" "")
1421 (match_operand:P 2 "register_operand" "=&a")])]
1424 gcc_assert (MEM_P (operands[1]));
1425 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1426 operands[1] = replace_equiv_address (operands[1], operands[2]);
1427 emit_move_insn (operands[0], operands[1]);
1431 (define_expand "reload<mode>_la_out"
1432 [(parallel [(match_operand 0 "" "")
1433 (match_operand 1 "register_operand" "")
1434 (match_operand:P 2 "register_operand" "=&a")])]
1437 gcc_assert (MEM_P (operands[0]));
1438 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1439 operands[0] = replace_equiv_address (operands[0], operands[2]);
1440 emit_move_insn (operands[0], operands[1]);
1444 (define_expand "reload<mode>_PIC_addr"
1445 [(parallel [(match_operand 0 "register_operand" "=d")
1446 (match_operand 1 "larl_operand" "")
1447 (match_operand:P 2 "register_operand" "=a")])]
1450 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1451 emit_move_insn (operands[0], new_rtx);
1455 ; movdi instruction pattern(s).
1458 (define_expand "movdi"
1459 [(set (match_operand:DI 0 "general_operand" "")
1460 (match_operand:DI 1 "general_operand" ""))]
1463 /* Handle symbolic constants. */
1465 && (SYMBOLIC_CONST (operands[1])
1466 || (GET_CODE (operands[1]) == PLUS
1467 && XEXP (operands[1], 0) == pic_offset_table_rtx
1468 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1469 emit_symbolic_move (operands);
1472 (define_insn "*movdi_larl"
1473 [(set (match_operand:DI 0 "register_operand" "=d")
1474 (match_operand:DI 1 "larl_operand" "X"))]
1476 && !FP_REG_P (operands[0])"
1478 [(set_attr "op_type" "RIL")
1479 (set_attr "type" "larl")
1480 (set_attr "z10prop" "z10_super_A1")])
1482 (define_insn "*movdi_64"
1483 [(set (match_operand:DI 0 "nonimmediate_operand"
1484 "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
1485 (match_operand:DI 1 "general_operand"
1486 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
1521 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1522 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1523 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1524 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1526 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1527 z10,*,*,*,*,*,longdisp,*,longdisp,
1528 z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1529 (set_attr "z10prop" "z10_fwd_A1,
1558 [(set (match_operand:DI 0 "register_operand" "")
1559 (match_operand:DI 1 "register_operand" ""))]
1560 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1561 [(set (match_dup 2) (match_dup 3))
1562 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1563 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1564 "operands[2] = gen_lowpart (SImode, operands[0]);
1565 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1568 [(set (match_operand:DI 0 "register_operand" "")
1569 (match_operand:DI 1 "register_operand" ""))]
1570 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1571 && dead_or_set_p (insn, operands[1])"
1572 [(set (match_dup 3) (match_dup 2))
1573 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1574 (set (match_dup 4) (match_dup 2))]
1575 "operands[2] = gen_lowpart (SImode, operands[1]);
1576 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1579 [(set (match_operand:DI 0 "register_operand" "")
1580 (match_operand:DI 1 "register_operand" ""))]
1581 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1582 && !dead_or_set_p (insn, operands[1])"
1583 [(set (match_dup 3) (match_dup 2))
1584 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1585 (set (match_dup 4) (match_dup 2))
1586 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1587 "operands[2] = gen_lowpart (SImode, operands[1]);
1588 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1590 (define_insn "*movdi_31"
1591 [(set (match_operand:DI 0 "nonimmediate_operand"
1592 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1593 (match_operand:DI 1 "general_operand"
1594 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1609 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1610 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1611 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1613 ; For a load from a symbol ref we can use one of the target registers
1614 ; together with larl to load the address.
1616 [(set (match_operand:DI 0 "register_operand" "")
1617 (match_operand:DI 1 "memory_operand" ""))]
1618 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1619 && larl_operand (XEXP (operands[1], 0), SImode)"
1620 [(set (match_dup 2) (match_dup 3))
1621 (set (match_dup 0) (match_dup 1))]
1623 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1624 operands[3] = XEXP (operands[1], 0);
1625 operands[1] = replace_equiv_address (operands[1], operands[2]);
1629 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1630 (match_operand:DI 1 "general_operand" ""))]
1631 "!TARGET_ZARCH && reload_completed
1632 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1633 [(set (match_dup 2) (match_dup 4))
1634 (set (match_dup 3) (match_dup 5))]
1636 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1637 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1638 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1639 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1643 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1644 (match_operand:DI 1 "general_operand" ""))]
1645 "!TARGET_ZARCH && reload_completed
1646 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1647 [(set (match_dup 2) (match_dup 4))
1648 (set (match_dup 3) (match_dup 5))]
1650 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1651 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1652 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1653 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1657 [(set (match_operand:DI 0 "register_operand" "")
1658 (match_operand:DI 1 "memory_operand" ""))]
1659 "!TARGET_ZARCH && reload_completed
1660 && !FP_REG_P (operands[0])
1661 && !s_operand (operands[1], VOIDmode)"
1662 [(set (match_dup 0) (match_dup 1))]
1664 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1665 s390_load_address (addr, XEXP (operands[1], 0));
1666 operands[1] = replace_equiv_address (operands[1], addr);
1670 [(set (match_operand:DI 0 "register_operand" "")
1671 (mem:DI (match_operand 1 "address_operand" "")))]
1673 && !FP_REG_P (operands[0])
1674 && GET_CODE (operands[1]) == SYMBOL_REF
1675 && CONSTANT_POOL_ADDRESS_P (operands[1])
1676 && get_pool_mode (operands[1]) == DImode
1677 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1678 [(set (match_dup 0) (match_dup 2))]
1679 "operands[2] = get_pool_constant (operands[1]);")
1681 (define_insn "*la_64"
1682 [(set (match_operand:DI 0 "register_operand" "=d,d")
1683 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1688 [(set_attr "op_type" "RX,RXY")
1689 (set_attr "type" "la")
1690 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1694 [(set (match_operand:DI 0 "register_operand" "")
1695 (match_operand:QI 1 "address_operand" ""))
1696 (clobber (reg:CC CC_REGNUM))])]
1698 && preferred_la_operand_p (operands[1], const0_rtx)"
1699 [(set (match_dup 0) (match_dup 1))]
1703 [(set (match_operand:DI 0 "register_operand" "")
1704 (match_operand:DI 1 "register_operand" ""))
1707 (plus:DI (match_dup 0)
1708 (match_operand:DI 2 "nonmemory_operand" "")))
1709 (clobber (reg:CC CC_REGNUM))])]
1711 && !reg_overlap_mentioned_p (operands[0], operands[2])
1712 && preferred_la_operand_p (operands[1], operands[2])"
1713 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1717 ; movsi instruction pattern(s).
1720 (define_expand "movsi"
1721 [(set (match_operand:SI 0 "general_operand" "")
1722 (match_operand:SI 1 "general_operand" ""))]
1725 /* Handle symbolic constants. */
1727 && (SYMBOLIC_CONST (operands[1])
1728 || (GET_CODE (operands[1]) == PLUS
1729 && XEXP (operands[1], 0) == pic_offset_table_rtx
1730 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1731 emit_symbolic_move (operands);
1734 (define_insn "*movsi_larl"
1735 [(set (match_operand:SI 0 "register_operand" "=d")
1736 (match_operand:SI 1 "larl_operand" "X"))]
1737 "!TARGET_64BIT && TARGET_CPU_ZARCH
1738 && !FP_REG_P (operands[0])"
1740 [(set_attr "op_type" "RIL")
1741 (set_attr "type" "larl")
1742 (set_attr "z10prop" "z10_fwd_A1")])
1744 (define_insn "*movsi_zarch"
1745 [(set (match_operand:SI 0 "nonimmediate_operand"
1746 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
1747 (match_operand:SI 1 "general_operand"
1748 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
1781 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1782 RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1783 (set_attr "type" "*,
1807 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1808 vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1809 (set_attr "z10prop" "z10_fwd_A1,
1834 (define_insn "*movsi_esa"
1835 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
1836 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
1852 [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
1853 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
1854 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
1856 (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
1860 [(set (match_operand:SI 0 "register_operand" "")
1861 (mem:SI (match_operand 1 "address_operand" "")))]
1862 "!FP_REG_P (operands[0])
1863 && GET_CODE (operands[1]) == SYMBOL_REF
1864 && CONSTANT_POOL_ADDRESS_P (operands[1])
1865 && get_pool_mode (operands[1]) == SImode
1866 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1867 [(set (match_dup 0) (match_dup 2))]
1868 "operands[2] = get_pool_constant (operands[1]);")
1870 (define_insn "*la_31"
1871 [(set (match_operand:SI 0 "register_operand" "=d,d")
1872 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1873 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1877 [(set_attr "op_type" "RX,RXY")
1878 (set_attr "type" "la")
1879 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1883 [(set (match_operand:SI 0 "register_operand" "")
1884 (match_operand:QI 1 "address_operand" ""))
1885 (clobber (reg:CC CC_REGNUM))])]
1887 && preferred_la_operand_p (operands[1], const0_rtx)"
1888 [(set (match_dup 0) (match_dup 1))]
1892 [(set (match_operand:SI 0 "register_operand" "")
1893 (match_operand:SI 1 "register_operand" ""))
1896 (plus:SI (match_dup 0)
1897 (match_operand:SI 2 "nonmemory_operand" "")))
1898 (clobber (reg:CC CC_REGNUM))])]
1900 && !reg_overlap_mentioned_p (operands[0], operands[2])
1901 && preferred_la_operand_p (operands[1], operands[2])"
1902 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1905 (define_insn "*la_31_and"
1906 [(set (match_operand:SI 0 "register_operand" "=d,d")
1907 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1908 (const_int 2147483647)))]
1913 [(set_attr "op_type" "RX,RXY")
1914 (set_attr "type" "la")
1915 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1917 (define_insn_and_split "*la_31_and_cc"
1918 [(set (match_operand:SI 0 "register_operand" "=d")
1919 (and:SI (match_operand:QI 1 "address_operand" "p")
1920 (const_int 2147483647)))
1921 (clobber (reg:CC CC_REGNUM))]
1924 "&& reload_completed"
1926 (and:SI (match_dup 1) (const_int 2147483647)))]
1928 [(set_attr "op_type" "RX")
1929 (set_attr "type" "la")])
1931 (define_insn "force_la_31"
1932 [(set (match_operand:SI 0 "register_operand" "=d,d")
1933 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1934 (use (const_int 0))]
1939 [(set_attr "op_type" "RX")
1940 (set_attr "type" "la")
1941 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1944 ; movhi instruction pattern(s).
1947 (define_expand "movhi"
1948 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1949 (match_operand:HI 1 "general_operand" ""))]
1952 /* Make it explicit that loading a register from memory
1953 always sign-extends (at least) to SImode. */
1954 if (optimize && can_create_pseudo_p ()
1955 && register_operand (operands[0], VOIDmode)
1956 && GET_CODE (operands[1]) == MEM)
1958 rtx tmp = gen_reg_rtx (SImode);
1959 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1960 emit_insn (gen_rtx_SET (tmp, ext));
1961 operands[1] = gen_lowpart (HImode, tmp);
1965 (define_insn "*movhi"
1966 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
1967 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
1985 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
1986 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
1987 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
1988 (set_attr "z10prop" "z10_fr_E1,
1996 z10_super,*,*,*,*,*,*")])
1999 [(set (match_operand:HI 0 "register_operand" "")
2000 (mem:HI (match_operand 1 "address_operand" "")))]
2001 "GET_CODE (operands[1]) == SYMBOL_REF
2002 && CONSTANT_POOL_ADDRESS_P (operands[1])
2003 && get_pool_mode (operands[1]) == HImode
2004 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2005 [(set (match_dup 0) (match_dup 2))]
2006 "operands[2] = get_pool_constant (operands[1]);")
2009 ; movqi instruction pattern(s).
2012 (define_expand "movqi"
2013 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2014 (match_operand:QI 1 "general_operand" ""))]
2017 /* On z/Architecture, zero-extending from memory to register
2018 is just as fast as a QImode load. */
2019 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2020 && register_operand (operands[0], VOIDmode)
2021 && GET_CODE (operands[1]) == MEM)
2023 rtx tmp = gen_reg_rtx (DImode);
2024 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2025 emit_insn (gen_rtx_SET (tmp, ext));
2026 operands[1] = gen_lowpart (QImode, tmp);
2030 (define_insn "*movqi"
2031 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
2032 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
2050 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2051 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2052 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
2053 (set_attr "z10prop" "z10_fr_E1,
2064 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2065 (mem:QI (match_operand 1 "address_operand" "")))]
2066 "GET_CODE (operands[1]) == SYMBOL_REF
2067 && CONSTANT_POOL_ADDRESS_P (operands[1])
2068 && get_pool_mode (operands[1]) == QImode
2069 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2070 [(set (match_dup 0) (match_dup 2))]
2071 "operands[2] = get_pool_constant (operands[1]);")
2074 ; movstrictqi instruction pattern(s).
2077 (define_insn "*movstrictqi"
2078 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2079 (match_operand:QI 1 "memory_operand" "R,T"))]
2084 [(set_attr "op_type" "RX,RXY")
2085 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2088 ; movstricthi instruction pattern(s).
2091 (define_insn "*movstricthi"
2092 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2093 (match_operand:HI 1 "memory_operand" "Q,S"))
2094 (clobber (reg:CC CC_REGNUM))]
2099 [(set_attr "op_type" "RS,RSY")
2100 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2103 ; movstrictsi instruction pattern(s).
2106 (define_insn "movstrictsi"
2107 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2108 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2115 [(set_attr "op_type" "RR,RX,RXY,RRE")
2116 (set_attr "type" "lr,load,load,*")
2117 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2120 ; mov(tf|td) instruction pattern(s).
2123 (define_expand "mov<mode>"
2124 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2125 (match_operand:TD_TF 1 "general_operand" ""))]
2129 (define_insn "*mov<mode>_64"
2130 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2131 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2142 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2143 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2144 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2146 (define_insn "*mov<mode>_31"
2147 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2148 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2155 [(set_attr "op_type" "RRE,RRE,*,*")
2156 (set_attr "type" "fsimptf,fsimptf,*,*")
2157 (set_attr "cpu_facility" "z196,*,*,*")])
2159 ; TFmode in GPRs splitters
2162 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2163 (match_operand:TD_TF 1 "general_operand" ""))]
2164 "TARGET_ZARCH && reload_completed
2165 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2166 [(set (match_dup 2) (match_dup 4))
2167 (set (match_dup 3) (match_dup 5))]
2169 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2170 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2171 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2172 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2176 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2177 (match_operand:TD_TF 1 "general_operand" ""))]
2178 "TARGET_ZARCH && reload_completed
2179 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2180 [(set (match_dup 2) (match_dup 4))
2181 (set (match_dup 3) (match_dup 5))]
2183 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2184 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2185 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2186 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2190 [(set (match_operand:TD_TF 0 "register_operand" "")
2191 (match_operand:TD_TF 1 "memory_operand" ""))]
2192 "TARGET_ZARCH && reload_completed
2193 && GENERAL_REG_P (operands[0])
2194 && !s_operand (operands[1], VOIDmode)"
2195 [(set (match_dup 0) (match_dup 1))]
2197 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2198 addr = gen_lowpart (Pmode, addr);
2199 s390_load_address (addr, XEXP (operands[1], 0));
2200 operands[1] = replace_equiv_address (operands[1], addr);
2203 ; TFmode in BFPs splitters
2206 [(set (match_operand:TD_TF 0 "register_operand" "")
2207 (match_operand:TD_TF 1 "memory_operand" ""))]
2208 "reload_completed && offsettable_memref_p (operands[1])
2209 && FP_REG_P (operands[0])"
2210 [(set (match_dup 2) (match_dup 4))
2211 (set (match_dup 3) (match_dup 5))]
2213 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2215 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2217 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2218 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2222 [(set (match_operand:TD_TF 0 "memory_operand" "")
2223 (match_operand:TD_TF 1 "register_operand" ""))]
2224 "reload_completed && offsettable_memref_p (operands[0])
2225 && FP_REG_P (operands[1])"
2226 [(set (match_dup 2) (match_dup 4))
2227 (set (match_dup 3) (match_dup 5))]
2229 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2230 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2231 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2233 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2238 ; mov(df|dd) instruction pattern(s).
2241 (define_expand "mov<mode>"
2242 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2243 (match_operand:DD_DF 1 "general_operand" ""))]
2247 (define_insn "*mov<mode>_64dfp"
2248 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2249 "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
2250 (match_operand:DD_DF 1 "general_operand"
2251 " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
2273 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2274 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2275 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2276 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2277 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2279 (define_insn "*mov<mode>_64"
2280 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
2281 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
2299 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2300 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2301 fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2302 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2303 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
2305 (define_insn "*mov<mode>_31"
2306 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2307 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2308 (match_operand:DD_DF 1 "general_operand"
2309 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2324 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2325 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2326 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2327 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2330 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2331 (match_operand:DD_DF 1 "general_operand" ""))]
2332 "!TARGET_ZARCH && reload_completed
2333 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2334 [(set (match_dup 2) (match_dup 4))
2335 (set (match_dup 3) (match_dup 5))]
2337 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2338 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2339 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2340 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2344 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2345 (match_operand:DD_DF 1 "general_operand" ""))]
2346 "!TARGET_ZARCH && reload_completed
2347 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2348 [(set (match_dup 2) (match_dup 4))
2349 (set (match_dup 3) (match_dup 5))]
2351 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2352 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2353 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2354 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2358 [(set (match_operand:DD_DF 0 "register_operand" "")
2359 (match_operand:DD_DF 1 "memory_operand" ""))]
2360 "!TARGET_ZARCH && reload_completed
2361 && !FP_REG_P (operands[0])
2362 && !s_operand (operands[1], VOIDmode)"
2363 [(set (match_dup 0) (match_dup 1))]
2365 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2366 s390_load_address (addr, XEXP (operands[1], 0));
2367 operands[1] = replace_equiv_address (operands[1], addr);
2371 ; mov(sf|sd) instruction pattern(s).
2374 (define_insn "mov<mode>"
2375 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2376 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
2377 (match_operand:SD_SF 1 "general_operand"
2378 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
2403 [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2404 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2405 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2406 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2407 (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
2410 ; movcc instruction pattern
2413 (define_insn "movcc"
2414 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2415 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2425 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2426 (set_attr "type" "lr,*,*,load,load,store,store")
2427 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2428 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2431 ; Block move (MVC) patterns.
2435 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2436 (match_operand:BLK 1 "memory_operand" "Q"))
2437 (use (match_operand 2 "const_int_operand" "n"))]
2438 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2439 "mvc\t%O0(%2,%R0),%S1"
2440 [(set_attr "op_type" "SS")])
2442 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2443 ; order to have it implemented with mvc.
2446 [(set (match_operand:QI 0 "memory_operand" "")
2447 (match_operand:QI 1 "memory_operand" ""))]
2450 [(set (match_dup 0) (match_dup 1))
2451 (use (const_int 1))])]
2453 operands[0] = adjust_address (operands[0], BLKmode, 0);
2454 operands[1] = adjust_address (operands[1], BLKmode, 0);
2460 [(set (match_operand:BLK 0 "memory_operand" "")
2461 (match_operand:BLK 1 "memory_operand" ""))
2462 (use (match_operand 2 "const_int_operand" ""))])
2464 [(set (match_operand:BLK 3 "memory_operand" "")
2465 (match_operand:BLK 4 "memory_operand" ""))
2466 (use (match_operand 5 "const_int_operand" ""))])]
2467 "s390_offset_p (operands[0], operands[3], operands[2])
2468 && s390_offset_p (operands[1], operands[4], operands[2])
2469 && !s390_overlap_p (operands[0], operands[1],
2470 INTVAL (operands[2]) + INTVAL (operands[5]))
2471 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2473 [(set (match_dup 6) (match_dup 7))
2474 (use (match_dup 8))])]
2475 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2476 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2477 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2481 ; load_multiple pattern(s).
2483 ; ??? Due to reload problems with replacing registers inside match_parallel
2484 ; we currently support load_multiple/store_multiple only after reload.
2487 (define_expand "load_multiple"
2488 [(match_par_dup 3 [(set (match_operand 0 "" "")
2489 (match_operand 1 "" ""))
2490 (use (match_operand 2 "" ""))])]
2499 /* Support only loading a constant number of fixed-point registers from
2500 memory and only bother with this if more than two */
2501 if (GET_CODE (operands[2]) != CONST_INT
2502 || INTVAL (operands[2]) < 2
2503 || INTVAL (operands[2]) > 16
2504 || GET_CODE (operands[1]) != MEM
2505 || GET_CODE (operands[0]) != REG
2506 || REGNO (operands[0]) >= 16)
2509 count = INTVAL (operands[2]);
2510 regno = REGNO (operands[0]);
2511 mode = GET_MODE (operands[0]);
2512 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2515 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2516 if (!can_create_pseudo_p ())
2518 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2520 from = XEXP (operands[1], 0);
2523 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2524 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2525 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2527 from = XEXP (XEXP (operands[1], 0), 0);
2528 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2535 from = force_reg (Pmode, XEXP (operands[1], 0));
2539 for (i = 0; i < count; i++)
2540 XVECEXP (operands[3], 0, i)
2541 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2542 change_address (operands[1], mode,
2543 plus_constant (Pmode, from,
2544 off + i * GET_MODE_SIZE (mode))));
2547 (define_insn "*load_multiple_di"
2548 [(match_parallel 0 "load_multiple_operation"
2549 [(set (match_operand:DI 1 "register_operand" "=r")
2550 (match_operand:DI 2 "s_operand" "QS"))])]
2551 "reload_completed && TARGET_ZARCH"
2553 int words = XVECLEN (operands[0], 0);
2554 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2555 return "lmg\t%1,%0,%S2";
2557 [(set_attr "op_type" "RSY")
2558 (set_attr "type" "lm")])
2560 (define_insn "*load_multiple_si"
2561 [(match_parallel 0 "load_multiple_operation"
2562 [(set (match_operand:SI 1 "register_operand" "=r,r")
2563 (match_operand:SI 2 "s_operand" "Q,S"))])]
2566 int words = XVECLEN (operands[0], 0);
2567 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2568 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2570 [(set_attr "op_type" "RS,RSY")
2571 (set_attr "type" "lm")])
2574 ; store multiple pattern(s).
2577 (define_expand "store_multiple"
2578 [(match_par_dup 3 [(set (match_operand 0 "" "")
2579 (match_operand 1 "" ""))
2580 (use (match_operand 2 "" ""))])]
2589 /* Support only storing a constant number of fixed-point registers to
2590 memory and only bother with this if more than two. */
2591 if (GET_CODE (operands[2]) != CONST_INT
2592 || INTVAL (operands[2]) < 2
2593 || INTVAL (operands[2]) > 16
2594 || GET_CODE (operands[0]) != MEM
2595 || GET_CODE (operands[1]) != REG
2596 || REGNO (operands[1]) >= 16)
2599 count = INTVAL (operands[2]);
2600 regno = REGNO (operands[1]);
2601 mode = GET_MODE (operands[1]);
2602 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2605 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2607 if (!can_create_pseudo_p ())
2609 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2611 to = XEXP (operands[0], 0);
2614 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2615 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2616 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2618 to = XEXP (XEXP (operands[0], 0), 0);
2619 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2626 to = force_reg (Pmode, XEXP (operands[0], 0));
2630 for (i = 0; i < count; i++)
2631 XVECEXP (operands[3], 0, i)
2632 = gen_rtx_SET (change_address (operands[0], mode,
2633 plus_constant (Pmode, to,
2634 off + i * GET_MODE_SIZE (mode))),
2635 gen_rtx_REG (mode, regno + i));
2638 (define_insn "*store_multiple_di"
2639 [(match_parallel 0 "store_multiple_operation"
2640 [(set (match_operand:DI 1 "s_operand" "=QS")
2641 (match_operand:DI 2 "register_operand" "r"))])]
2642 "reload_completed && TARGET_ZARCH"
2644 int words = XVECLEN (operands[0], 0);
2645 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2646 return "stmg\t%2,%0,%S1";
2648 [(set_attr "op_type" "RSY")
2649 (set_attr "type" "stm")])
2652 (define_insn "*store_multiple_si"
2653 [(match_parallel 0 "store_multiple_operation"
2654 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2655 (match_operand:SI 2 "register_operand" "r,r"))])]
2658 int words = XVECLEN (operands[0], 0);
2659 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2660 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2662 [(set_attr "op_type" "RS,RSY")
2663 (set_attr "type" "stm")])
2666 ;; String instructions.
2669 (define_insn "*execute_rl"
2670 [(match_parallel 0 "execute_operation"
2671 [(unspec [(match_operand 1 "register_operand" "a")
2672 (match_operand 2 "" "")
2673 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2674 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2675 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2677 [(set_attr "op_type" "RIL")
2678 (set_attr "type" "cs")])
2680 (define_insn "*execute"
2681 [(match_parallel 0 "execute_operation"
2682 [(unspec [(match_operand 1 "register_operand" "a")
2683 (match_operand:BLK 2 "memory_operand" "R")
2684 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2685 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2686 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2688 [(set_attr "op_type" "RX")
2689 (set_attr "type" "cs")])
2693 ; strlenM instruction pattern(s).
2696 (define_expand "strlen<mode>"
2697 [(match_operand:P 0 "register_operand" "") ; result
2698 (match_operand:BLK 1 "memory_operand" "") ; input string
2699 (match_operand:SI 2 "immediate_operand" "") ; search character
2700 (match_operand:SI 3 "immediate_operand" "")] ; known alignment
2703 if (!TARGET_VX || operands[2] != const0_rtx)
2704 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2705 operands[2], operands[3]));
2707 s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2712 (define_expand "strlen_srst<mode>"
2713 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2716 (unspec:P [(const_int 0)
2717 (match_operand:BLK 1 "memory_operand" "")
2719 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2720 (clobber (scratch:P))
2721 (clobber (reg:CC CC_REGNUM))])
2723 [(set (match_operand:P 0 "register_operand" "")
2724 (minus:P (match_dup 4) (match_dup 5)))
2725 (clobber (reg:CC CC_REGNUM))])]
2728 operands[4] = gen_reg_rtx (Pmode);
2729 operands[5] = gen_reg_rtx (Pmode);
2730 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2731 operands[1] = replace_equiv_address (operands[1], operands[5]);
2734 (define_insn "*strlen<mode>"
2735 [(set (match_operand:P 0 "register_operand" "=a")
2736 (unspec:P [(match_operand:P 2 "general_operand" "0")
2737 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2739 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2740 (clobber (match_scratch:P 1 "=a"))
2741 (clobber (reg:CC CC_REGNUM))]
2743 "srst\t%0,%1\;jo\t.-4"
2744 [(set_attr "length" "8")
2745 (set_attr "type" "vs")])
2748 ; cmpstrM instruction pattern(s).
2751 (define_expand "cmpstrsi"
2752 [(set (reg:SI 0) (const_int 0))
2754 [(clobber (match_operand 3 "" ""))
2755 (clobber (match_dup 4))
2756 (set (reg:CCU CC_REGNUM)
2757 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2758 (match_operand:BLK 2 "memory_operand" "")))
2761 [(set (match_operand:SI 0 "register_operand" "=d")
2762 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2763 (clobber (reg:CC CC_REGNUM))])]
2766 /* As the result of CMPINT is inverted compared to what we need,
2767 we have to swap the operands. */
2768 rtx op1 = operands[2];
2769 rtx op2 = operands[1];
2770 rtx addr1 = gen_reg_rtx (Pmode);
2771 rtx addr2 = gen_reg_rtx (Pmode);
2773 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2774 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2775 operands[1] = replace_equiv_address_nv (op1, addr1);
2776 operands[2] = replace_equiv_address_nv (op2, addr2);
2777 operands[3] = addr1;
2778 operands[4] = addr2;
2781 (define_insn "*cmpstr<mode>"
2782 [(clobber (match_operand:P 0 "register_operand" "=d"))
2783 (clobber (match_operand:P 1 "register_operand" "=d"))
2784 (set (reg:CCU CC_REGNUM)
2785 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2786 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2789 "clst\t%0,%1\;jo\t.-4"
2790 [(set_attr "length" "8")
2791 (set_attr "type" "vs")])
2794 ; movstr instruction pattern.
2797 (define_expand "movstr"
2798 [(set (reg:SI 0) (const_int 0))
2800 [(clobber (match_dup 3))
2801 (set (match_operand:BLK 1 "memory_operand" "")
2802 (match_operand:BLK 2 "memory_operand" ""))
2803 (set (match_operand 0 "register_operand" "")
2804 (unspec [(match_dup 1)
2806 (reg:SI 0)] UNSPEC_MVST))
2807 (clobber (reg:CC CC_REGNUM))])]
2810 rtx addr1 = gen_reg_rtx (Pmode);
2811 rtx addr2 = gen_reg_rtx (Pmode);
2813 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2814 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2815 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2816 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2817 operands[3] = addr2;
2820 (define_insn "*movstr"
2821 [(clobber (match_operand:P 2 "register_operand" "=d"))
2822 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2823 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2824 (set (match_operand:P 0 "register_operand" "=d")
2825 (unspec [(mem:BLK (match_dup 1))
2826 (mem:BLK (match_dup 3))
2827 (reg:SI 0)] UNSPEC_MVST))
2828 (clobber (reg:CC CC_REGNUM))]
2830 "mvst\t%1,%2\;jo\t.-4"
2831 [(set_attr "length" "8")
2832 (set_attr "type" "vs")])
2836 ; movmemM instruction pattern(s).
2839 (define_expand "movmem<mode>"
2840 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2841 (match_operand:BLK 1 "memory_operand" "")) ; source
2842 (use (match_operand:GPR 2 "general_operand" "")) ; count
2843 (match_operand 3 "" "")]
2846 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2852 ; Move a block that is up to 256 bytes in length.
2853 ; The block length is taken as (operands[2] % 256) + 1.
2855 (define_expand "movmem_short"
2857 [(set (match_operand:BLK 0 "memory_operand" "")
2858 (match_operand:BLK 1 "memory_operand" ""))
2859 (use (match_operand 2 "nonmemory_operand" ""))
2860 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2861 (clobber (match_dup 3))])]
2863 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2865 (define_insn "*movmem_short"
2866 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2867 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2868 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2869 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2870 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2871 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2873 [(set_attr "type" "cs")
2874 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2877 [(set (match_operand:BLK 0 "memory_operand" "")
2878 (match_operand:BLK 1 "memory_operand" ""))
2879 (use (match_operand 2 "const_int_operand" ""))
2880 (use (match_operand 3 "immediate_operand" ""))
2881 (clobber (scratch))]
2884 [(set (match_dup 0) (match_dup 1))
2885 (use (match_dup 2))])]
2886 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2889 [(set (match_operand:BLK 0 "memory_operand" "")
2890 (match_operand:BLK 1 "memory_operand" ""))
2891 (use (match_operand 2 "register_operand" ""))
2892 (use (match_operand 3 "memory_operand" ""))
2893 (clobber (scratch))]
2896 [(unspec [(match_dup 2) (match_dup 3)
2897 (const_int 0)] UNSPEC_EXECUTE)
2898 (set (match_dup 0) (match_dup 1))
2899 (use (const_int 1))])]
2903 [(set (match_operand:BLK 0 "memory_operand" "")
2904 (match_operand:BLK 1 "memory_operand" ""))
2905 (use (match_operand 2 "register_operand" ""))
2906 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2907 (clobber (scratch))]
2908 "TARGET_Z10 && reload_completed"
2910 [(unspec [(match_dup 2) (const_int 0)
2911 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2912 (set (match_dup 0) (match_dup 1))
2913 (use (const_int 1))])]
2914 "operands[3] = gen_label_rtx ();")
2917 [(set (match_operand:BLK 0 "memory_operand" "")
2918 (match_operand:BLK 1 "memory_operand" ""))
2919 (use (match_operand 2 "register_operand" ""))
2920 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2921 (clobber (match_operand 3 "register_operand" ""))]
2922 "reload_completed && TARGET_CPU_ZARCH"
2923 [(set (match_dup 3) (label_ref (match_dup 4)))
2925 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2926 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2927 (set (match_dup 0) (match_dup 1))
2928 (use (const_int 1))])]
2929 "operands[4] = gen_label_rtx ();")
2931 ; Move a block of arbitrary length.
2933 (define_expand "movmem_long"
2935 [(clobber (match_dup 2))
2936 (clobber (match_dup 3))
2937 (set (match_operand:BLK 0 "memory_operand" "")
2938 (match_operand:BLK 1 "memory_operand" ""))
2939 (use (match_operand 2 "general_operand" ""))
2941 (clobber (reg:CC CC_REGNUM))])]
2944 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2945 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2946 rtx reg0 = gen_reg_rtx (dreg_mode);
2947 rtx reg1 = gen_reg_rtx (dreg_mode);
2948 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2949 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2950 rtx len0 = gen_lowpart (Pmode, reg0);
2951 rtx len1 = gen_lowpart (Pmode, reg1);
2953 emit_clobber (reg0);
2954 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2955 emit_move_insn (len0, operands[2]);
2957 emit_clobber (reg1);
2958 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2959 emit_move_insn (len1, operands[2]);
2961 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2962 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2967 (define_insn "*movmem_long"
2968 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2969 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2970 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2971 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2974 (clobber (reg:CC CC_REGNUM))]
2975 "TARGET_64BIT || !TARGET_ZARCH"
2976 "mvcle\t%0,%1,0\;jo\t.-4"
2977 [(set_attr "length" "8")
2978 (set_attr "type" "vs")])
2980 (define_insn "*movmem_long_31z"
2981 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2982 (clobber (match_operand:TI 1 "register_operand" "=d"))
2983 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2984 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2987 (clobber (reg:CC CC_REGNUM))]
2988 "!TARGET_64BIT && TARGET_ZARCH"
2989 "mvcle\t%0,%1,0\;jo\t.-4"
2990 [(set_attr "length" "8")
2991 (set_attr "type" "vs")])
2998 (define_expand "signbit<mode>2"
2999 [(set (reg:CCZ CC_REGNUM)
3000 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3003 (set (match_operand:SI 0 "register_operand" "=d")
3004 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3007 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3010 (define_expand "isinf<mode>2"
3011 [(set (reg:CCZ CC_REGNUM)
3012 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3015 (set (match_operand:SI 0 "register_operand" "=d")
3016 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3019 operands[2] = GEN_INT (S390_TDC_INFINITY);
3022 ; This extracts CC into a GPR properly shifted. The actual IPM
3023 ; instruction will be issued by reload. The constraint of operand 1
3024 ; forces reload to use a GPR. So reload will issue a movcc insn for
3025 ; copying CC into a GPR first.
3026 (define_insn_and_split "*cc_to_int"
3027 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3028 (unspec:SI [(match_operand 1 "register_operand" "0")]
3033 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3035 ; This insn is used to generate all variants of the Test Data Class
3036 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
3037 ; is the register to be tested and the second one is the bit mask
3038 ; specifying the required test(s).
3040 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3041 (define_insn "*TDC_insn_<mode>"
3042 [(set (reg:CCZ CC_REGNUM)
3043 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3044 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3046 "t<_d>c<xde><bt>\t%0,%1"
3047 [(set_attr "op_type" "RXE")
3048 (set_attr "type" "fsimp<mode>")])
3053 ; setmemM instruction pattern(s).
3056 (define_expand "setmem<mode>"
3057 [(set (match_operand:BLK 0 "memory_operand" "")
3058 (match_operand:QI 2 "general_operand" ""))
3059 (use (match_operand:GPR 1 "general_operand" ""))
3060 (match_operand 3 "" "")]
3062 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3064 ; Clear a block that is up to 256 bytes in length.
3065 ; The block length is taken as (operands[1] % 256) + 1.
3067 (define_expand "clrmem_short"
3069 [(set (match_operand:BLK 0 "memory_operand" "")
3071 (use (match_operand 1 "nonmemory_operand" ""))
3072 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3073 (clobber (match_dup 2))
3074 (clobber (reg:CC CC_REGNUM))])]
3076 "operands[2] = gen_rtx_SCRATCH (Pmode);")
3078 (define_insn "*clrmem_short"
3079 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3081 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3082 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3083 (clobber (match_scratch:P 3 "=X,X,X,&a"))
3084 (clobber (reg:CC CC_REGNUM))]
3085 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3087 [(set_attr "type" "cs")
3088 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3091 [(set (match_operand:BLK 0 "memory_operand" "")
3093 (use (match_operand 1 "const_int_operand" ""))
3094 (use (match_operand 2 "immediate_operand" ""))
3096 (clobber (reg:CC CC_REGNUM))]
3099 [(set (match_dup 0) (const_int 0))
3101 (clobber (reg:CC CC_REGNUM))])]
3102 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3105 [(set (match_operand:BLK 0 "memory_operand" "")
3107 (use (match_operand 1 "register_operand" ""))
3108 (use (match_operand 2 "memory_operand" ""))
3110 (clobber (reg:CC CC_REGNUM))]
3113 [(unspec [(match_dup 1) (match_dup 2)
3114 (const_int 0)] UNSPEC_EXECUTE)
3115 (set (match_dup 0) (const_int 0))
3117 (clobber (reg:CC CC_REGNUM))])]
3121 [(set (match_operand:BLK 0 "memory_operand" "")
3123 (use (match_operand 1 "register_operand" ""))
3124 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3126 (clobber (reg:CC CC_REGNUM))]
3127 "TARGET_Z10 && reload_completed"
3129 [(unspec [(match_dup 1) (const_int 0)
3130 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3131 (set (match_dup 0) (const_int 0))
3133 (clobber (reg:CC CC_REGNUM))])]
3134 "operands[3] = gen_label_rtx ();")
3137 [(set (match_operand:BLK 0 "memory_operand" "")
3139 (use (match_operand 1 "register_operand" ""))
3140 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3141 (clobber (match_operand 2 "register_operand" ""))
3142 (clobber (reg:CC CC_REGNUM))]
3143 "reload_completed && TARGET_CPU_ZARCH"
3144 [(set (match_dup 2) (label_ref (match_dup 3)))
3146 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3147 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3148 (set (match_dup 0) (const_int 0))
3150 (clobber (reg:CC CC_REGNUM))])]
3151 "operands[3] = gen_label_rtx ();")
3153 ; Initialize a block of arbitrary length with (operands[2] % 256).
3155 (define_expand "setmem_long"
3157 [(clobber (match_dup 1))
3158 (set (match_operand:BLK 0 "memory_operand" "")
3159 (match_operand 2 "shift_count_or_setmem_operand" ""))
3160 (use (match_operand 1 "general_operand" ""))
3162 (clobber (reg:CC CC_REGNUM))])]
3165 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3166 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3167 rtx reg0 = gen_reg_rtx (dreg_mode);
3168 rtx reg1 = gen_reg_rtx (dreg_mode);
3169 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3170 rtx len0 = gen_lowpart (Pmode, reg0);
3172 emit_clobber (reg0);
3173 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3174 emit_move_insn (len0, operands[1]);
3176 emit_move_insn (reg1, const0_rtx);
3178 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3183 (define_insn "*setmem_long"
3184 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3185 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3186 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3188 (use (match_operand:<DBL> 1 "register_operand" "d"))
3189 (clobber (reg:CC CC_REGNUM))]
3190 "TARGET_64BIT || !TARGET_ZARCH"
3191 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3192 [(set_attr "length" "8")
3193 (set_attr "type" "vs")])
3195 (define_insn "*setmem_long_and"
3196 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3197 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3198 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3199 (match_operand 4 "const_int_operand" "n")))
3201 (use (match_operand:<DBL> 1 "register_operand" "d"))
3202 (clobber (reg:CC CC_REGNUM))]
3203 "(TARGET_64BIT || !TARGET_ZARCH) &&
3204 (INTVAL (operands[4]) & 255) == 255"
3205 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3206 [(set_attr "length" "8")
3207 (set_attr "type" "vs")])
3209 (define_insn "*setmem_long_31z"
3210 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3211 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3212 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3214 (use (match_operand:TI 1 "register_operand" "d"))
3215 (clobber (reg:CC CC_REGNUM))]
3216 "!TARGET_64BIT && TARGET_ZARCH"
3217 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3218 [(set_attr "length" "8")
3219 (set_attr "type" "vs")])
3222 ; cmpmemM instruction pattern(s).
3225 (define_expand "cmpmemsi"
3226 [(set (match_operand:SI 0 "register_operand" "")
3227 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3228 (match_operand:BLK 2 "memory_operand" "") ) )
3229 (use (match_operand:SI 3 "general_operand" ""))
3230 (use (match_operand:SI 4 "" ""))]
3233 if (s390_expand_cmpmem (operands[0], operands[1],
3234 operands[2], operands[3]))
3240 ; Compare a block that is up to 256 bytes in length.
3241 ; The block length is taken as (operands[2] % 256) + 1.
3243 (define_expand "cmpmem_short"
3245 [(set (reg:CCU CC_REGNUM)
3246 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3247 (match_operand:BLK 1 "memory_operand" "")))
3248 (use (match_operand 2 "nonmemory_operand" ""))
3249 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3250 (clobber (match_dup 3))])]
3252 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3254 (define_insn "*cmpmem_short"
3255 [(set (reg:CCU CC_REGNUM)
3256 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3257 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3258 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3259 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3260 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3261 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3263 [(set_attr "type" "cs")
3264 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3267 [(set (reg:CCU CC_REGNUM)
3268 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3269 (match_operand:BLK 1 "memory_operand" "")))
3270 (use (match_operand 2 "const_int_operand" ""))
3271 (use (match_operand 3 "immediate_operand" ""))
3272 (clobber (scratch))]
3275 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3276 (use (match_dup 2))])]
3277 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3280 [(set (reg:CCU CC_REGNUM)
3281 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3282 (match_operand:BLK 1 "memory_operand" "")))
3283 (use (match_operand 2 "register_operand" ""))
3284 (use (match_operand 3 "memory_operand" ""))
3285 (clobber (scratch))]
3288 [(unspec [(match_dup 2) (match_dup 3)
3289 (const_int 0)] UNSPEC_EXECUTE)
3290 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3291 (use (const_int 1))])]
3295 [(set (reg:CCU CC_REGNUM)
3296 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3297 (match_operand:BLK 1 "memory_operand" "")))
3298 (use (match_operand 2 "register_operand" ""))
3299 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3300 (clobber (scratch))]
3301 "TARGET_Z10 && reload_completed"
3303 [(unspec [(match_dup 2) (const_int 0)
3304 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3305 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3306 (use (const_int 1))])]
3307 "operands[4] = gen_label_rtx ();")
3310 [(set (reg:CCU CC_REGNUM)
3311 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3312 (match_operand:BLK 1 "memory_operand" "")))
3313 (use (match_operand 2 "register_operand" ""))
3314 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3315 (clobber (match_operand 3 "register_operand" ""))]
3316 "reload_completed && TARGET_CPU_ZARCH"
3317 [(set (match_dup 3) (label_ref (match_dup 4)))
3319 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3320 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3321 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3322 (use (const_int 1))])]
3323 "operands[4] = gen_label_rtx ();")
3325 ; Compare a block of arbitrary length.
3327 (define_expand "cmpmem_long"
3329 [(clobber (match_dup 2))
3330 (clobber (match_dup 3))
3331 (set (reg:CCU CC_REGNUM)
3332 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3333 (match_operand:BLK 1 "memory_operand" "")))
3334 (use (match_operand 2 "general_operand" ""))
3335 (use (match_dup 3))])]
3338 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3339 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3340 rtx reg0 = gen_reg_rtx (dreg_mode);
3341 rtx reg1 = gen_reg_rtx (dreg_mode);
3342 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3343 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3344 rtx len0 = gen_lowpart (Pmode, reg0);
3345 rtx len1 = gen_lowpart (Pmode, reg1);
3347 emit_clobber (reg0);
3348 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3349 emit_move_insn (len0, operands[2]);
3351 emit_clobber (reg1);
3352 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3353 emit_move_insn (len1, operands[2]);
3355 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3356 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3361 (define_insn "*cmpmem_long"
3362 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3363 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3364 (set (reg:CCU CC_REGNUM)
3365 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3366 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3368 (use (match_dup 3))]
3369 "TARGET_64BIT || !TARGET_ZARCH"
3370 "clcle\t%0,%1,0\;jo\t.-4"
3371 [(set_attr "length" "8")
3372 (set_attr "type" "vs")])
3374 (define_insn "*cmpmem_long_31z"
3375 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3376 (clobber (match_operand:TI 1 "register_operand" "=d"))
3377 (set (reg:CCU CC_REGNUM)
3378 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3379 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3381 (use (match_dup 3))]
3382 "!TARGET_64BIT && TARGET_ZARCH"
3383 "clcle\t%0,%1,0\;jo\t.-4"
3384 [(set_attr "op_type" "NN")
3385 (set_attr "type" "vs")
3386 (set_attr "length" "8")])
3388 ; Convert CCUmode condition code to integer.
3389 ; Result is zero if EQ, positive if LTU, negative if GTU.
3391 (define_insn_and_split "cmpint"
3392 [(set (match_operand:SI 0 "register_operand" "=d")
3393 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3394 UNSPEC_STRCMPCC_TO_INT))
3395 (clobber (reg:CC CC_REGNUM))]
3399 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3401 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3402 (clobber (reg:CC CC_REGNUM))])])
3404 (define_insn_and_split "*cmpint_cc"
3405 [(set (reg CC_REGNUM)
3406 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3407 UNSPEC_STRCMPCC_TO_INT)
3409 (set (match_operand:SI 0 "register_operand" "=d")
3410 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3411 "s390_match_ccmode (insn, CCSmode)"
3413 "&& reload_completed"
3414 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3416 [(set (match_dup 2) (match_dup 3))
3417 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3419 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3420 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3421 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3424 (define_insn_and_split "*cmpint_sign"
3425 [(set (match_operand:DI 0 "register_operand" "=d")
3426 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3427 UNSPEC_STRCMPCC_TO_INT)))
3428 (clobber (reg:CC CC_REGNUM))]
3431 "&& reload_completed"
3432 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3434 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3435 (clobber (reg:CC CC_REGNUM))])])
3437 (define_insn_and_split "*cmpint_sign_cc"
3438 [(set (reg CC_REGNUM)
3439 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3440 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3441 UNSPEC_STRCMPCC_TO_INT) 0)
3442 (const_int 32)) (const_int 32))
3444 (set (match_operand:DI 0 "register_operand" "=d")
3445 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3446 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3448 "&& reload_completed"
3449 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3451 [(set (match_dup 2) (match_dup 3))
3452 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3454 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3455 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3456 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3461 ;;- Conversion instructions.
3464 (define_insn "*sethighpartsi"
3465 [(set (match_operand:SI 0 "register_operand" "=d,d")
3466 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3467 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3468 (clobber (reg:CC CC_REGNUM))]
3473 [(set_attr "op_type" "RS,RSY")
3474 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3476 (define_insn "*sethighpartdi_64"
3477 [(set (match_operand:DI 0 "register_operand" "=d")
3478 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3479 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3480 (clobber (reg:CC CC_REGNUM))]
3483 [(set_attr "op_type" "RSY")
3484 (set_attr "z10prop" "z10_super")])
3486 (define_insn "*sethighpartdi_31"
3487 [(set (match_operand:DI 0 "register_operand" "=d,d")
3488 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3489 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3490 (clobber (reg:CC CC_REGNUM))]
3495 [(set_attr "op_type" "RS,RSY")
3496 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3499 ; extv instruction patterns
3502 ; FIXME: This expander needs to be converted from DI to GPR as well
3503 ; after resolving some issues with it.
3505 (define_expand "extzv"
3507 [(set (match_operand:DI 0 "register_operand" "=d")
3509 (match_operand:DI 1 "register_operand" "d")
3510 (match_operand 2 "const_int_operand" "") ; size
3511 (match_operand 3 "const_int_operand" ""))) ; start
3512 (clobber (reg:CC CC_REGNUM))])]
3515 /* Starting with zEC12 there is risbgn not clobbering CC. */
3518 emit_move_insn (operands[0],
3519 gen_rtx_ZERO_EXTRACT (DImode,
3527 (define_insn "*extzv<mode>_zEC12"
3528 [(set (match_operand:GPR 0 "register_operand" "=d")
3530 (match_operand:GPR 1 "register_operand" "d")
3531 (match_operand 2 "const_int_operand" "") ; size
3532 (match_operand 3 "const_int_operand" "")))] ; start]
3534 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3535 [(set_attr "op_type" "RIE")])
3537 (define_insn "*extzv<mode>_z10"
3538 [(set (match_operand:GPR 0 "register_operand" "=d")
3540 (match_operand:GPR 1 "register_operand" "d")
3541 (match_operand 2 "const_int_operand" "") ; size
3542 (match_operand 3 "const_int_operand" ""))) ; start
3543 (clobber (reg:CC CC_REGNUM))]
3545 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3546 [(set_attr "op_type" "RIE")
3547 (set_attr "z10prop" "z10_super_E1")])
3549 (define_insn_and_split "*pre_z10_extzv<mode>"
3550 [(set (match_operand:GPR 0 "register_operand" "=d")
3551 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3552 (match_operand 2 "nonzero_shift_count_operand" "")
3554 (clobber (reg:CC CC_REGNUM))]
3557 "&& reload_completed"
3559 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3560 (clobber (reg:CC CC_REGNUM))])
3561 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3563 int bitsize = INTVAL (operands[2]);
3564 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3565 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3567 operands[1] = adjust_address (operands[1], BLKmode, 0);
3568 set_mem_size (operands[1], size);
3569 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3570 operands[3] = GEN_INT (mask);
3573 (define_insn_and_split "*pre_z10_extv<mode>"
3574 [(set (match_operand:GPR 0 "register_operand" "=d")
3575 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3576 (match_operand 2 "nonzero_shift_count_operand" "")
3578 (clobber (reg:CC CC_REGNUM))]
3581 "&& reload_completed"
3583 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3584 (clobber (reg:CC CC_REGNUM))])
3586 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3587 (clobber (reg:CC CC_REGNUM))])]
3589 int bitsize = INTVAL (operands[2]);
3590 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3591 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3593 operands[1] = adjust_address (operands[1], BLKmode, 0);
3594 set_mem_size (operands[1], size);
3595 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3596 operands[3] = GEN_INT (mask);
3600 ; insv instruction patterns
3603 (define_expand "insv"
3604 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3605 (match_operand 1 "const_int_operand" "")
3606 (match_operand 2 "const_int_operand" ""))
3607 (match_operand 3 "general_operand" ""))]
3610 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3616 ; The normal RTL expansion will never generate a zero_extract where
3617 ; the location operand isn't word mode. However, we do this in the
3618 ; back-end when generating atomic operations. See s390_two_part_insv.
3619 (define_insn "*insv<mode>_zEC12"
3620 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3621 (match_operand 1 "const_int_operand" "I") ; size
3622 (match_operand 2 "const_int_operand" "I")) ; pos
3623 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3625 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3626 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3627 [(set_attr "op_type" "RIE")])
3629 (define_insn "*insv<mode>_z10"
3630 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3631 (match_operand 1 "const_int_operand" "I") ; size
3632 (match_operand 2 "const_int_operand" "I")) ; pos
3633 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3634 (clobber (reg:CC CC_REGNUM))]
3636 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3637 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3638 [(set_attr "op_type" "RIE")
3639 (set_attr "z10prop" "z10_super_E1")])
3641 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3642 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3643 (define_insn "*insv<mode>_zEC12_noshift"
3644 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3645 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3646 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3647 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3648 (match_operand:GPR 4 "const_int_operand" ""))))]
3649 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3650 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3651 [(set_attr "op_type" "RIE")])
3653 (define_insn "*insv<mode>_z10_noshift"
3654 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3655 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3656 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3657 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3658 (match_operand:GPR 4 "const_int_operand" ""))))
3659 (clobber (reg:CC CC_REGNUM))]
3660 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3661 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3662 [(set_attr "op_type" "RIE")
3663 (set_attr "z10prop" "z10_super_E1")])
3665 (define_insn "*r<noxa>sbg_<mode>_noshift"
3666 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3668 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3669 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3670 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3671 (clobber (reg:CC CC_REGNUM))]
3673 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3674 [(set_attr "op_type" "RIE")])
3676 (define_insn "*r<noxa>sbg_di_rotl"
3677 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3681 (match_operand:DI 1 "nonimmediate_operand" "d")
3682 (match_operand:DI 3 "const_int_operand" ""))
3683 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3684 (match_operand:DI 4 "nonimmediate_operand" "0")))
3685 (clobber (reg:CC CC_REGNUM))]
3687 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3688 [(set_attr "op_type" "RIE")])
3690 (define_insn "*r<noxa>sbg_<mode>_srl"
3691 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3695 (match_operand:GPR 1 "nonimmediate_operand" "d")
3696 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3697 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3698 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3699 (clobber (reg:CC CC_REGNUM))]
3701 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3702 INTVAL (operands[2]))"
3703 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3704 [(set_attr "op_type" "RIE")])
3706 (define_insn "*r<noxa>sbg_<mode>_sll"
3707 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3711 (match_operand:GPR 1 "nonimmediate_operand" "d")
3712 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3713 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3714 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3715 (clobber (reg:CC CC_REGNUM))]
3717 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3718 INTVAL (operands[2]))"
3719 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3720 [(set_attr "op_type" "RIE")])
3722 ;; These two are generated by combine for s.bf &= val.
3723 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3724 ;; shifts and ands, which results in some truly awful patterns
3725 ;; including subregs of operations. Rather unnecessisarily, IMO.
3728 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3729 ;; (const_int 24 [0x18])
3730 ;; (const_int 0 [0]))
3731 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3732 ;; (const_int 40 [0x28])) 4)
3733 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3735 ;; we should instead generate
3737 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3738 ;; (const_int 24 [0x18])
3739 ;; (const_int 0 [0]))
3740 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3741 ;; (const_int 40 [0x28]))
3742 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3744 ;; by noticing that we can push down the outer paradoxical subreg
3745 ;; into the operation.
3747 (define_insn "*insv_rnsbg_noshift"
3748 [(set (zero_extract:DI
3749 (match_operand:DI 0 "nonimmediate_operand" "+d")
3750 (match_operand 1 "const_int_operand" "")
3751 (match_operand 2 "const_int_operand" ""))
3754 (match_operand:DI 3 "nonimmediate_operand" "d")))
3755 (clobber (reg:CC CC_REGNUM))]
3757 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3758 "rnsbg\t%0,%3,%2,63,0"
3759 [(set_attr "op_type" "RIE")])
3761 (define_insn "*insv_rnsbg_srl"
3762 [(set (zero_extract:DI
3763 (match_operand:DI 0 "nonimmediate_operand" "+d")
3764 (match_operand 1 "const_int_operand" "")
3765 (match_operand 2 "const_int_operand" ""))
3769 (match_operand 3 "const_int_operand" ""))
3770 (match_operand:DI 4 "nonimmediate_operand" "d")))
3771 (clobber (reg:CC CC_REGNUM))]
3773 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3774 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3775 [(set_attr "op_type" "RIE")])
3777 (define_insn "*insv<mode>_mem_reg"
3778 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3779 (match_operand 1 "const_int_operand" "n,n")
3781 (match_operand:W 2 "register_operand" "d,d"))]
3782 "INTVAL (operands[1]) > 0
3783 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3784 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3786 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3788 operands[1] = GEN_INT ((1ul << size) - 1);
3789 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3790 : "stcmy\t%2,%1,%S0";
3792 [(set_attr "op_type" "RS,RSY")
3793 (set_attr "z10prop" "z10_super,z10_super")])
3795 (define_insn "*insvdi_mem_reghigh"
3796 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3797 (match_operand 1 "const_int_operand" "n")
3799 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3802 && INTVAL (operands[1]) > 0
3803 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3804 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3806 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3808 operands[1] = GEN_INT ((1ul << size) - 1);
3809 return "stcmh\t%2,%1,%S0";
3811 [(set_attr "op_type" "RSY")
3812 (set_attr "z10prop" "z10_super")])
3814 (define_insn "*insvdi_reg_imm"
3815 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3817 (match_operand 1 "const_int_operand" "n"))
3818 (match_operand:DI 2 "const_int_operand" "n"))]
3820 && INTVAL (operands[1]) >= 0
3821 && INTVAL (operands[1]) < BITS_PER_WORD
3822 && INTVAL (operands[1]) % 16 == 0"
3824 switch (BITS_PER_WORD - INTVAL (operands[1]))
3826 case 64: return "iihh\t%0,%x2"; break;
3827 case 48: return "iihl\t%0,%x2"; break;
3828 case 32: return "iilh\t%0,%x2"; break;
3829 case 16: return "iill\t%0,%x2"; break;
3830 default: gcc_unreachable();
3833 [(set_attr "op_type" "RI")
3834 (set_attr "z10prop" "z10_super_E1")])
3836 ; Update the left-most 32 bit of a DI.
3837 (define_insn "*insv_h_di_reg_extimm"
3838 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3841 (match_operand:DI 1 "const_int_operand" "n"))]
3844 [(set_attr "op_type" "RIL")
3845 (set_attr "z10prop" "z10_fwd_E1")])
3847 ; Update the right-most 32 bit of a DI.
3848 (define_insn "*insv_l_di_reg_extimm"
3849 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3852 (match_operand:DI 1 "const_int_operand" "n"))]
3855 [(set_attr "op_type" "RIL")
3856 (set_attr "z10prop" "z10_fwd_A1")])
3859 ; extendsidi2 instruction pattern(s).
3862 (define_expand "extendsidi2"
3863 [(set (match_operand:DI 0 "register_operand" "")
3864 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3869 emit_clobber (operands[0]);
3870 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3871 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3872 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3877 (define_insn "*extendsidi2"
3878 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3879 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3885 [(set_attr "op_type" "RRE,RXY,RIL")
3886 (set_attr "type" "*,*,larl")
3887 (set_attr "cpu_facility" "*,*,z10")
3888 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3891 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3894 (define_expand "extend<HQI:mode><DSI:mode>2"
3895 [(set (match_operand:DSI 0 "register_operand" "")
3896 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3899 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3901 rtx tmp = gen_reg_rtx (SImode);
3902 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3903 emit_insn (gen_extendsidi2 (operands[0], tmp));
3906 else if (!TARGET_EXTIMM)
3908 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3910 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3911 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3912 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3918 ; extendhidi2 instruction pattern(s).
3921 (define_insn "*extendhidi2_extimm"
3922 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3923 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3924 "TARGET_ZARCH && TARGET_EXTIMM"
3929 [(set_attr "op_type" "RRE,RXY,RIL")
3930 (set_attr "type" "*,*,larl")
3931 (set_attr "cpu_facility" "extimm,extimm,z10")
3932 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3934 (define_insn "*extendhidi2"
3935 [(set (match_operand:DI 0 "register_operand" "=d")
3936 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3939 [(set_attr "op_type" "RXY")
3940 (set_attr "z10prop" "z10_super_E1")])
3943 ; extendhisi2 instruction pattern(s).
3946 (define_insn "*extendhisi2_extimm"
3947 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3948 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3955 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3956 (set_attr "type" "*,*,*,larl")
3957 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3958 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3960 (define_insn "*extendhisi2"
3961 [(set (match_operand:SI 0 "register_operand" "=d,d")
3962 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3967 [(set_attr "op_type" "RX,RXY")
3968 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3971 ; extendqi(si|di)2 instruction pattern(s).
3974 ; lbr, lgbr, lb, lgb
3975 (define_insn "*extendqi<mode>2_extimm"
3976 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3977 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3982 [(set_attr "op_type" "RRE,RXY")
3983 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3986 (define_insn "*extendqi<mode>2"
3987 [(set (match_operand:GPR 0 "register_operand" "=d")
3988 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3989 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3991 [(set_attr "op_type" "RXY")
3992 (set_attr "z10prop" "z10_super_E1")])
3994 (define_insn_and_split "*extendqi<mode>2_short_displ"
3995 [(set (match_operand:GPR 0 "register_operand" "=d")
3996 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3997 (clobber (reg:CC CC_REGNUM))]
3998 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4000 "&& reload_completed"
4002 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4003 (clobber (reg:CC CC_REGNUM))])
4005 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4006 (clobber (reg:CC CC_REGNUM))])]
4008 operands[1] = adjust_address (operands[1], BLKmode, 0);
4009 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4010 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4014 ; zero_extendsidi2 instruction pattern(s).
4017 (define_expand "zero_extendsidi2"
4018 [(set (match_operand:DI 0 "register_operand" "")
4019 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4024 emit_clobber (operands[0]);
4025 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4026 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4031 (define_insn "*zero_extendsidi2"
4032 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4033 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4039 [(set_attr "op_type" "RRE,RXY,RIL")
4040 (set_attr "type" "*,*,larl")
4041 (set_attr "cpu_facility" "*,*,z10")
4042 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4045 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4048 (define_insn "*llgt_sidi"
4049 [(set (match_operand:DI 0 "register_operand" "=d")
4050 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4051 (const_int 2147483647)))]
4054 [(set_attr "op_type" "RXE")
4055 (set_attr "z10prop" "z10_super_E1")])
4057 (define_insn_and_split "*llgt_sidi_split"
4058 [(set (match_operand:DI 0 "register_operand" "=d")
4059 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4060 (const_int 2147483647)))
4061 (clobber (reg:CC CC_REGNUM))]
4064 "&& reload_completed"
4066 (and:DI (subreg:DI (match_dup 1) 0)
4067 (const_int 2147483647)))]
4070 (define_insn "*llgt_sisi"
4071 [(set (match_operand:SI 0 "register_operand" "=d,d")
4072 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
4073 (const_int 2147483647)))]
4078 [(set_attr "op_type" "RRE,RXE")
4079 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4081 (define_insn "*llgt_didi"
4082 [(set (match_operand:DI 0 "register_operand" "=d,d")
4083 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4084 (const_int 2147483647)))]
4089 [(set_attr "op_type" "RRE,RXE")
4090 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4093 [(set (match_operand:DSI 0 "register_operand" "")
4094 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4095 (const_int 2147483647)))
4096 (clobber (reg:CC CC_REGNUM))]
4097 "TARGET_ZARCH && reload_completed"
4099 (and:DSI (match_dup 1)
4100 (const_int 2147483647)))]
4104 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4107 (define_expand "zero_extend<mode>di2"
4108 [(set (match_operand:DI 0 "register_operand" "")
4109 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4114 rtx tmp = gen_reg_rtx (SImode);
4115 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4116 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4119 else if (!TARGET_EXTIMM)
4121 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4122 operands[1] = gen_lowpart (DImode, operands[1]);
4123 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4124 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4129 (define_expand "zero_extend<mode>si2"
4130 [(set (match_operand:SI 0 "register_operand" "")
4131 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4136 operands[1] = gen_lowpart (SImode, operands[1]);
4137 emit_insn (gen_andsi3 (operands[0], operands[1],
4138 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4144 (define_insn "*zero_extendhi<mode>2_z10"
4145 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4146 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4152 [(set_attr "op_type" "RXY,RRE,RIL")
4153 (set_attr "type" "*,*,larl")
4154 (set_attr "cpu_facility" "*,*,z10")
4155 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4157 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4158 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4159 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4160 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4165 [(set_attr "op_type" "RRE,RXY")
4166 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4169 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4170 [(set (match_operand:GPR 0 "register_operand" "=d")
4171 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4172 "TARGET_ZARCH && !TARGET_EXTIMM"
4174 [(set_attr "op_type" "RXY")
4175 (set_attr "z10prop" "z10_fwd_A3")])
4177 (define_insn_and_split "*zero_extendhisi2_31"
4178 [(set (match_operand:SI 0 "register_operand" "=&d")
4179 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4180 (clobber (reg:CC CC_REGNUM))]
4183 "&& reload_completed"
4184 [(set (match_dup 0) (const_int 0))
4186 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4187 (clobber (reg:CC CC_REGNUM))])]
4188 "operands[2] = gen_lowpart (HImode, operands[0]);")
4190 (define_insn_and_split "*zero_extendqisi2_31"
4191 [(set (match_operand:SI 0 "register_operand" "=&d")
4192 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4195 "&& reload_completed"
4196 [(set (match_dup 0) (const_int 0))
4197 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4198 "operands[2] = gen_lowpart (QImode, operands[0]);")
4201 ; zero_extendqihi2 instruction pattern(s).
4204 (define_expand "zero_extendqihi2"
4205 [(set (match_operand:HI 0 "register_operand" "")
4206 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4207 "TARGET_ZARCH && !TARGET_EXTIMM"
4209 operands[1] = gen_lowpart (HImode, operands[1]);
4210 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4214 (define_insn "*zero_extendqihi2_64"
4215 [(set (match_operand:HI 0 "register_operand" "=d")
4216 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4217 "TARGET_ZARCH && !TARGET_EXTIMM"
4219 [(set_attr "op_type" "RXY")
4220 (set_attr "z10prop" "z10_fwd_A3")])
4222 (define_insn_and_split "*zero_extendqihi2_31"
4223 [(set (match_operand:HI 0 "register_operand" "=&d")
4224 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4227 "&& reload_completed"
4228 [(set (match_dup 0) (const_int 0))
4229 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4230 "operands[2] = gen_lowpart (QImode, operands[0]);")
4233 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4236 (define_expand "fixuns_truncdddi2"
4238 [(set (match_operand:DI 0 "register_operand" "")
4239 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4240 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4241 (clobber (reg:CC CC_REGNUM))])]
4247 rtx_code_label *label1 = gen_label_rtx ();
4248 rtx_code_label *label2 = gen_label_rtx ();
4249 rtx temp = gen_reg_rtx (TDmode);
4250 REAL_VALUE_TYPE cmp, sub;
4252 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4253 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4255 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4256 solution is doing the check and the subtraction in TD mode and using a
4257 TD -> DI convert afterwards. */
4258 emit_insn (gen_extendddtd2 (temp, operands[1]));
4259 temp = force_reg (TDmode, temp);
4260 emit_cmp_and_jump_insns (temp,
4261 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4262 LT, NULL_RTX, VOIDmode, 0, label1);
4263 emit_insn (gen_subtd3 (temp, temp,
4264 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4265 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4268 emit_label (label1);
4269 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4270 emit_label (label2);
4275 (define_expand "fixuns_trunctddi2"
4277 [(set (match_operand:DI 0 "register_operand" "")
4278 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4279 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4280 (clobber (reg:CC CC_REGNUM))])]
4286 rtx_code_label *label1 = gen_label_rtx ();
4287 rtx_code_label *label2 = gen_label_rtx ();
4288 rtx temp = gen_reg_rtx (TDmode);
4289 REAL_VALUE_TYPE cmp, sub;
4291 operands[1] = force_reg (TDmode, operands[1]);
4292 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4293 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4295 emit_cmp_and_jump_insns (operands[1],
4296 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4297 LT, NULL_RTX, VOIDmode, 0, label1);
4298 emit_insn (gen_subtd3 (temp, operands[1],
4299 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4300 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4303 emit_label (label1);
4304 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4305 emit_label (label2);
4311 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4312 ; instruction pattern(s).
4315 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4317 [(set (match_operand:GPR 0 "register_operand" "")
4318 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4319 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4320 (clobber (reg:CC CC_REGNUM))])]
4325 rtx_code_label *label1 = gen_label_rtx ();
4326 rtx_code_label *label2 = gen_label_rtx ();
4327 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4328 REAL_VALUE_TYPE cmp, sub;
4330 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4331 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4332 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4334 emit_cmp_and_jump_insns (operands[1],
4335 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4336 LT, NULL_RTX, VOIDmode, 0, label1);
4337 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4338 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4339 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4343 emit_label (label1);
4344 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4345 operands[1], GEN_INT (5)));
4346 emit_label (label2);
4351 ; fixuns_trunc(td|dd)si2 expander
4352 (define_expand "fixuns_trunc<mode>si2"
4354 [(set (match_operand:SI 0 "register_operand" "")
4355 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4356 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4357 (clobber (reg:CC CC_REGNUM))])]
4358 "TARGET_Z196 && TARGET_HARD_DFP"
4361 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4363 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4364 ; clfdtr, clfxtr, clgdtr, clgxtr
4365 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4366 [(set (match_operand:GPR 0 "register_operand" "=r")
4367 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4368 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4369 (clobber (reg:CC CC_REGNUM))]
4371 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4372 [(set_attr "op_type" "RRF")
4373 (set_attr "type" "ftoi")])
4375 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4376 [(set (match_operand:GPR 0 "register_operand" "")
4377 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4380 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4385 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4386 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4387 [(set (match_operand:GPR 0 "register_operand" "=d")
4388 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4389 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4390 (clobber (reg:CC CC_REGNUM))]
4392 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4393 [(set_attr "op_type" "RRE")
4394 (set_attr "type" "ftoi")])
4398 ; fix_trunc(td|dd)di2 instruction pattern(s).
4401 (define_expand "fix_trunc<mode>di2"
4402 [(set (match_operand:DI 0 "register_operand" "")
4403 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4404 "TARGET_ZARCH && TARGET_HARD_DFP"
4406 operands[1] = force_reg (<MODE>mode, operands[1]);
4407 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4413 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4414 [(set (match_operand:DI 0 "register_operand" "=d")
4415 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4416 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4417 (clobber (reg:CC CC_REGNUM))]
4418 "TARGET_ZARCH && TARGET_HARD_DFP"
4419 "cg<DFP:xde>tr\t%0,%h2,%1"
4420 [(set_attr "op_type" "RRF")
4421 (set_attr "type" "ftoidfp")])
4425 ; fix_trunctf(si|di)2 instruction pattern(s).
4428 (define_expand "fix_trunctf<mode>2"
4429 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4430 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4431 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4432 (clobber (reg:CC CC_REGNUM))])]
4438 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4441 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4442 (define_insn "floatdi<mode>2"
4443 [(set (match_operand:FP 0 "register_operand" "=f")
4444 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4445 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4446 "c<xde>g<bt>r\t%0,%1"
4447 [(set_attr "op_type" "RRE")
4448 (set_attr "type" "itof<mode>" )])
4450 ; cxfbr, cdfbr, cefbr
4451 (define_insn "floatsi<mode>2"
4452 [(set (match_operand:BFP 0 "register_operand" "=f")
4453 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4456 [(set_attr "op_type" "RRE")
4457 (set_attr "type" "itof<mode>" )])
4460 (define_insn "floatsi<mode>2"
4461 [(set (match_operand:DFP 0 "register_operand" "=f")
4462 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4463 "TARGET_Z196 && TARGET_HARD_FLOAT"
4464 "c<xde>ftr\t%0,0,%1,0"
4465 [(set_attr "op_type" "RRE")
4466 (set_attr "type" "itof<mode>" )])
4469 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4472 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4473 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4474 (define_insn "floatuns<GPR:mode><FP:mode>2"
4475 [(set (match_operand:FP 0 "register_operand" "=f")
4476 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4477 "TARGET_Z196 && TARGET_HARD_FLOAT"
4478 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4479 [(set_attr "op_type" "RRE")
4480 (set_attr "type" "itof<FP:mode>" )])
4483 ; truncdfsf2 instruction pattern(s).
4486 (define_insn "truncdfsf2"
4487 [(set (match_operand:SF 0 "register_operand" "=f")
4488 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4491 [(set_attr "op_type" "RRE")
4492 (set_attr "type" "ftruncdf")])
4495 ; trunctf(df|sf)2 instruction pattern(s).
4499 (define_insn "trunctf<mode>2"
4500 [(set (match_operand:DSF 0 "register_operand" "=f")
4501 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4502 (clobber (match_scratch:TF 2 "=f"))]
4504 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4505 [(set_attr "length" "6")
4506 (set_attr "type" "ftrunctf")])
4509 ; trunctddd2 and truncddsd2 instruction pattern(s).
4512 (define_insn "trunctddd2"
4513 [(set (match_operand:DD 0 "register_operand" "=f")
4514 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4515 (clobber (match_scratch:TD 2 "=f"))]
4517 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4518 [(set_attr "length" "6")
4519 (set_attr "type" "ftruncdd")])
4521 (define_insn "truncddsd2"
4522 [(set (match_operand:SD 0 "register_operand" "=f")
4523 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4526 [(set_attr "op_type" "RRF")
4527 (set_attr "type" "ftruncsd")])
4529 (define_expand "trunctdsd2"
4532 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4533 (clobber (match_scratch:TD 2 ""))])
4534 (set (match_operand:SD 0 "register_operand" "")
4535 (float_truncate:SD (match_dup 3)))]
4538 operands[3] = gen_reg_rtx (DDmode);
4542 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4545 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4546 (define_insn "extend<DSF:mode><BFP:mode>2"
4547 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4548 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4550 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4552 l<BFP:xde><DSF:xde>br\t%0,%1
4553 l<BFP:xde><DSF:xde>b\t%0,%1"
4554 [(set_attr "op_type" "RRE,RXE")
4555 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4558 ; extendddtd2 and extendsddd2 instruction pattern(s).
4561 (define_insn "extendddtd2"
4562 [(set (match_operand:TD 0 "register_operand" "=f")
4563 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4566 [(set_attr "op_type" "RRF")
4567 (set_attr "type" "fsimptf")])
4569 (define_insn "extendsddd2"
4570 [(set (match_operand:DD 0 "register_operand" "=f")
4571 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4574 [(set_attr "op_type" "RRF")
4575 (set_attr "type" "fsimptf")])
4577 (define_expand "extendsdtd2"
4579 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4580 (set (match_operand:TD 0 "register_operand" "")
4581 (float_extend:TD (match_dup 2)))]
4584 operands[2] = gen_reg_rtx (DDmode);
4587 ; Binary Floating Point - load fp integer
4589 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4590 ; For all of them the inexact exceptions are suppressed.
4592 ; fiebra, fidbra, fixbra
4593 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4594 [(set (match_operand:BFP 0 "register_operand" "=f")
4595 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4598 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4599 [(set_attr "op_type" "RRF")
4600 (set_attr "type" "fsimp<BFP:mode>")])
4602 ; rint is supposed to raise an inexact exception so we can use the
4603 ; older instructions.
4605 ; fiebr, fidbr, fixbr
4606 (define_insn "rint<BFP:mode>2"
4607 [(set (match_operand:BFP 0 "register_operand" "=f")
4608 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4609 UNSPEC_FPINT_RINT))]
4611 "fi<BFP:xde>br\t%0,0,%1"
4612 [(set_attr "op_type" "RRF")
4613 (set_attr "type" "fsimp<BFP:mode>")])
4616 ; Decimal Floating Point - load fp integer
4619 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4620 [(set (match_operand:DFP 0 "register_operand" "=f")
4621 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4624 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4625 [(set_attr "op_type" "RRF")
4626 (set_attr "type" "fsimp<DFP:mode>")])
4629 (define_insn "rint<DFP:mode>2"
4630 [(set (match_operand:DFP 0 "register_operand" "=f")
4631 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4632 UNSPEC_FPINT_RINT))]
4634 "fi<DFP:xde>tr\t%0,0,%1,0"
4635 [(set_attr "op_type" "RRF")
4636 (set_attr "type" "fsimp<DFP:mode>")])
4639 ; Binary <-> Decimal floating point trunc patterns
4642 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4643 [(set (reg:DFP_ALL FPR0_REGNUM)
4644 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4645 (use (reg:SI GPR0_REGNUM))
4646 (clobber (reg:CC CC_REGNUM))]
4650 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4651 [(set (reg:BFP FPR0_REGNUM)
4652 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4653 (use (reg:SI GPR0_REGNUM))
4654 (clobber (reg:CC CC_REGNUM))]
4658 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4659 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4660 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4662 [(set (reg:DFP_ALL FPR0_REGNUM)
4663 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4664 (use (reg:SI GPR0_REGNUM))
4665 (clobber (reg:CC CC_REGNUM))])
4666 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4667 (reg:DFP_ALL FPR0_REGNUM))]
4669 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4671 HOST_WIDE_INT flags;
4673 flags = (PFPO_CONVERT |
4674 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4675 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4677 operands[2] = GEN_INT (flags);
4680 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4681 [(set (reg:DFP_ALL FPR4_REGNUM)
4682 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4683 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4685 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4686 (use (reg:SI GPR0_REGNUM))
4687 (clobber (reg:CC CC_REGNUM))])
4688 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4690 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4692 HOST_WIDE_INT flags;
4694 flags = (PFPO_CONVERT |
4695 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4696 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4698 operands[2] = GEN_INT (flags);
4702 ; Binary <-> Decimal floating point extend patterns
4705 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4706 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4707 (use (reg:SI GPR0_REGNUM))
4708 (clobber (reg:CC CC_REGNUM))]
4712 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4713 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4714 (use (reg:SI GPR0_REGNUM))
4715 (clobber (reg:CC CC_REGNUM))]
4719 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4720 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4721 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4723 [(set (reg:DFP_ALL FPR0_REGNUM)
4724 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4725 (use (reg:SI GPR0_REGNUM))
4726 (clobber (reg:CC CC_REGNUM))])
4727 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4728 (reg:DFP_ALL FPR0_REGNUM))]
4730 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4732 HOST_WIDE_INT flags;
4734 flags = (PFPO_CONVERT |
4735 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4736 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4738 operands[2] = GEN_INT (flags);
4741 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4742 [(set (reg:DFP_ALL FPR4_REGNUM)
4743 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4744 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4746 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4747 (use (reg:SI GPR0_REGNUM))
4748 (clobber (reg:CC CC_REGNUM))])
4749 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4751 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4753 HOST_WIDE_INT flags;
4755 flags = (PFPO_CONVERT |
4756 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4757 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4759 operands[2] = GEN_INT (flags);
4764 ;; ARITHMETIC OPERATIONS
4766 ; arithmetic operations set the ConditionCode,
4767 ; because of unpredictable Bits in Register for Halfword and Byte
4768 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4771 ;;- Add instructions.
4775 ; addti3 instruction pattern(s).
4778 (define_expand "addti3"
4780 [(set (match_operand:TI 0 "register_operand" "")
4781 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
4782 (match_operand:TI 2 "general_operand" "") ) )
4783 (clobber (reg:CC CC_REGNUM))])]
4786 /* For z13 we have vaq which doesn't set CC. */
4789 emit_insn (gen_rtx_SET (operands[0],
4790 gen_rtx_PLUS (TImode,
4791 copy_to_mode_reg (TImode, operands[1]),
4792 copy_to_mode_reg (TImode, operands[2]))));
4797 (define_insn_and_split "*addti3"
4798 [(set (match_operand:TI 0 "register_operand" "=&d")
4799 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4800 (match_operand:TI 2 "general_operand" "do") ) )
4801 (clobber (reg:CC CC_REGNUM))]
4804 "&& reload_completed"
4806 [(set (reg:CCL1 CC_REGNUM)
4807 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4809 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4811 [(set (match_dup 3) (plus:DI
4812 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4813 (match_dup 4)) (match_dup 5)))
4814 (clobber (reg:CC CC_REGNUM))])]
4815 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4816 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4817 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4818 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4819 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4820 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
4821 [(set_attr "op_type" "*")
4822 (set_attr "cpu_facility" "*")])
4825 ; adddi3 instruction pattern(s).
4828 (define_expand "adddi3"
4830 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4831 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4832 (match_operand:DI 2 "general_operand" "")))
4833 (clobber (reg:CC CC_REGNUM))])]
4837 (define_insn "*adddi3_sign"
4838 [(set (match_operand:DI 0 "register_operand" "=d,d")
4839 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4840 (match_operand:DI 1 "register_operand" "0,0")))
4841 (clobber (reg:CC CC_REGNUM))]
4846 [(set_attr "op_type" "RRE,RXY")
4847 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4849 (define_insn "*adddi3_zero_cc"
4850 [(set (reg CC_REGNUM)
4851 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4852 (match_operand:DI 1 "register_operand" "0,0"))
4854 (set (match_operand:DI 0 "register_operand" "=d,d")
4855 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4856 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4860 [(set_attr "op_type" "RRE,RXY")
4861 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4863 (define_insn "*adddi3_zero_cconly"
4864 [(set (reg CC_REGNUM)
4865 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4866 (match_operand:DI 1 "register_operand" "0,0"))
4868 (clobber (match_scratch:DI 0 "=d,d"))]
4869 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4873 [(set_attr "op_type" "RRE,RXY")
4874 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4876 (define_insn "*adddi3_zero"
4877 [(set (match_operand:DI 0 "register_operand" "=d,d")
4878 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4879 (match_operand:DI 1 "register_operand" "0,0")))
4880 (clobber (reg:CC CC_REGNUM))]
4885 [(set_attr "op_type" "RRE,RXY")
4886 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4888 (define_insn_and_split "*adddi3_31z"
4889 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4890 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4891 (match_operand:DI 2 "general_operand" "do") ) )
4892 (clobber (reg:CC CC_REGNUM))]
4893 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4895 "&& reload_completed"
4897 [(set (reg:CCL1 CC_REGNUM)
4898 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4900 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4902 [(set (match_dup 3) (plus:SI
4903 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4904 (match_dup 4)) (match_dup 5)))
4905 (clobber (reg:CC CC_REGNUM))])]
4906 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4907 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4908 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4909 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4910 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4911 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4913 (define_insn_and_split "*adddi3_31"
4914 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4915 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4916 (match_operand:DI 2 "general_operand" "do") ) )
4917 (clobber (reg:CC CC_REGNUM))]
4920 "&& reload_completed"
4922 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4923 (clobber (reg:CC CC_REGNUM))])
4925 [(set (reg:CCL1 CC_REGNUM)
4926 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4928 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4930 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4932 (label_ref (match_dup 9))))
4934 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4935 (clobber (reg:CC CC_REGNUM))])
4937 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4938 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4939 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4940 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4941 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4942 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4943 operands[9] = gen_label_rtx ();")
4946 ; addsi3 instruction pattern(s).
4949 (define_expand "addsi3"
4951 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4952 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4953 (match_operand:SI 2 "general_operand" "")))
4954 (clobber (reg:CC CC_REGNUM))])]
4958 (define_insn "*addsi3_sign"
4959 [(set (match_operand:SI 0 "register_operand" "=d,d")
4960 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4961 (match_operand:SI 1 "register_operand" "0,0")))
4962 (clobber (reg:CC CC_REGNUM))]
4967 [(set_attr "op_type" "RX,RXY")
4968 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4971 ; add(di|si)3 instruction pattern(s).
4974 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4975 (define_insn "*add<mode>3"
4976 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4977 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4978 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4979 (clobber (reg:CC CC_REGNUM))]
4991 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4992 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4993 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4994 z10_super_E1,z10_super_E1,z10_super_E1")])
4996 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4997 (define_insn "*add<mode>3_carry1_cc"
4998 [(set (reg CC_REGNUM)
4999 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5000 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5002 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
5003 (plus:GPR (match_dup 1) (match_dup 2)))]
5004 "s390_match_ccmode (insn, CCL1mode)"
5010 al<g>hsik\t%0,%1,%h2
5014 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5015 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5016 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5017 z10_super_E1,z10_super_E1,z10_super_E1")])
5019 ; alr, al, aly, algr, alg, alrk, algrk
5020 (define_insn "*add<mode>3_carry1_cconly"
5021 [(set (reg CC_REGNUM)
5022 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5023 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5025 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5026 "s390_match_ccmode (insn, CCL1mode)"
5032 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5033 (set_attr "cpu_facility" "*,z196,*,*")
5034 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5036 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5037 (define_insn "*add<mode>3_carry2_cc"
5038 [(set (reg CC_REGNUM)
5039 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5040 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
5042 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
5043 (plus:GPR (match_dup 1) (match_dup 2)))]
5044 "s390_match_ccmode (insn, CCL1mode)"
5050 al<g>hsik\t%0,%1,%h2
5054 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5055 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5056 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5057 z10_super_E1,z10_super_E1,z10_super_E1")])
5059 ; alr, al, aly, algr, alg, alrk, algrk
5060 (define_insn "*add<mode>3_carry2_cconly"
5061 [(set (reg CC_REGNUM)
5062 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5063 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5065 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5066 "s390_match_ccmode (insn, CCL1mode)"
5072 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5073 (set_attr "cpu_facility" "*,z196,*,*")
5074 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5076 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5077 (define_insn "*add<mode>3_cc"
5078 [(set (reg CC_REGNUM)
5079 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5080 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
5082 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
5083 (plus:GPR (match_dup 1) (match_dup 2)))]
5084 "s390_match_ccmode (insn, CCLmode)"
5090 al<g>hsik\t%0,%1,%h2
5094 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5095 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5096 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5097 *,z10_super_E1,z10_super_E1,z10_super_E1")])
5099 ; alr, al, aly, algr, alg, alrk, algrk
5100 (define_insn "*add<mode>3_cconly"
5101 [(set (reg CC_REGNUM)
5102 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5103 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5105 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5106 "s390_match_ccmode (insn, CCLmode)"
5112 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5113 (set_attr "cpu_facility" "*,z196,*,*")
5114 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5116 ; alr, al, aly, algr, alg, alrk, algrk
5117 (define_insn "*add<mode>3_cconly2"
5118 [(set (reg CC_REGNUM)
5119 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5120 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5121 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5122 "s390_match_ccmode(insn, CCLmode)"
5128 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5129 (set_attr "cpu_facility" "*,z196,*,*")
5130 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5132 ; ahi, afi, aghi, agfi, asi, agsi
5133 (define_insn "*add<mode>3_imm_cc"
5134 [(set (reg CC_REGNUM)
5135 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5136 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
5138 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
5139 (plus:GPR (match_dup 1) (match_dup 2)))]
5140 "s390_match_ccmode (insn, CCAmode)
5141 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5142 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5143 /* Avoid INT32_MIN on 32 bit. */
5144 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5150 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5151 (set_attr "cpu_facility" "*,z196,extimm,z10")
5152 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5155 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5158 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5159 (define_insn "add<mode>3"
5160 [(set (match_operand:FP 0 "register_operand" "=f, f")
5161 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5162 (match_operand:FP 2 "general_operand" " f,<Rf>")))
5163 (clobber (reg:CC CC_REGNUM))]
5166 a<xde><bt>r\t%0,<op1>%2
5168 [(set_attr "op_type" "<RRer>,RXE")
5169 (set_attr "type" "fsimp<mode>")])
5171 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5172 (define_insn "*add<mode>3_cc"
5173 [(set (reg CC_REGNUM)
5174 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5175 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5176 (match_operand:FP 3 "const0_operand" "")))
5177 (set (match_operand:FP 0 "register_operand" "=f,f")
5178 (plus:FP (match_dup 1) (match_dup 2)))]
5179 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5181 a<xde><bt>r\t%0,<op1>%2
5183 [(set_attr "op_type" "<RRer>,RXE")
5184 (set_attr "type" "fsimp<mode>")])
5186 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5187 (define_insn "*add<mode>3_cconly"
5188 [(set (reg CC_REGNUM)
5189 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5190 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5191 (match_operand:FP 3 "const0_operand" "")))
5192 (clobber (match_scratch:FP 0 "=f,f"))]
5193 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5195 a<xde><bt>r\t%0,<op1>%2
5197 [(set_attr "op_type" "<RRer>,RXE")
5198 (set_attr "type" "fsimp<mode>")])
5201 ; Pointer add instruction patterns
5204 ; This will match "*la_64"
5205 (define_expand "addptrdi3"
5206 [(set (match_operand:DI 0 "register_operand" "")
5207 (plus:DI (match_operand:DI 1 "register_operand" "")
5208 (match_operand:DI 2 "nonmemory_operand" "")))]
5211 if (GET_CODE (operands[2]) == CONST_INT)
5213 HOST_WIDE_INT c = INTVAL (operands[2]);
5215 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5216 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5218 operands[2] = force_const_mem (DImode, operands[2]);
5219 operands[2] = force_reg (DImode, operands[2]);
5221 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5222 operands[2] = force_reg (DImode, operands[2]);
5226 ; For 31 bit we have to prevent the generated pattern from matching
5227 ; normal ADDs since la only does a 31 bit add. This is supposed to
5228 ; match "force_la_31".
5229 (define_expand "addptrsi3"
5231 [(set (match_operand:SI 0 "register_operand" "")
5232 (plus:SI (match_operand:SI 1 "register_operand" "")
5233 (match_operand:SI 2 "nonmemory_operand" "")))
5234 (use (const_int 0))])]
5237 if (GET_CODE (operands[2]) == CONST_INT)
5239 HOST_WIDE_INT c = INTVAL (operands[2]);
5241 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5242 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5244 operands[2] = force_const_mem (SImode, operands[2]);
5245 operands[2] = force_reg (SImode, operands[2]);
5247 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5248 operands[2] = force_reg (SImode, operands[2]);
5253 ;;- Subtract instructions.
5257 ; subti3 instruction pattern(s).
5260 (define_expand "subti3"
5262 [(set (match_operand:TI 0 "register_operand" "")
5263 (minus:TI (match_operand:TI 1 "register_operand" "")
5264 (match_operand:TI 2 "general_operand" "") ) )
5265 (clobber (reg:CC CC_REGNUM))])]
5268 /* For z13 we have vaq which doesn't set CC. */
5271 emit_insn (gen_rtx_SET (operands[0],
5272 gen_rtx_MINUS (TImode,
5274 copy_to_mode_reg (TImode, operands[2]))));
5279 (define_insn_and_split "*subti3"
5280 [(set (match_operand:TI 0 "register_operand" "=&d")
5281 (minus:TI (match_operand:TI 1 "register_operand" "0")
5282 (match_operand:TI 2 "general_operand" "do") ) )
5283 (clobber (reg:CC CC_REGNUM))]
5286 "&& reload_completed"
5288 [(set (reg:CCL2 CC_REGNUM)
5289 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5291 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5293 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5294 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5295 (clobber (reg:CC CC_REGNUM))])]
5296 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5297 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5298 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5299 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5300 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5301 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5302 [(set_attr "op_type" "*")
5303 (set_attr "cpu_facility" "*")])
5306 ; subdi3 instruction pattern(s).
5309 (define_expand "subdi3"
5311 [(set (match_operand:DI 0 "register_operand" "")
5312 (minus:DI (match_operand:DI 1 "register_operand" "")
5313 (match_operand:DI 2 "general_operand" "")))
5314 (clobber (reg:CC CC_REGNUM))])]
5318 (define_insn "*subdi3_sign"
5319 [(set (match_operand:DI 0 "register_operand" "=d,d")
5320 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5321 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5322 (clobber (reg:CC CC_REGNUM))]
5327 [(set_attr "op_type" "RRE,RXY")
5328 (set_attr "z10prop" "z10_c,*")
5329 (set_attr "z196prop" "z196_cracked")])
5331 (define_insn "*subdi3_zero_cc"
5332 [(set (reg CC_REGNUM)
5333 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5334 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5336 (set (match_operand:DI 0 "register_operand" "=d,d")
5337 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5338 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5342 [(set_attr "op_type" "RRE,RXY")
5343 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5345 (define_insn "*subdi3_zero_cconly"
5346 [(set (reg CC_REGNUM)
5347 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5348 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5350 (clobber (match_scratch:DI 0 "=d,d"))]
5351 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5355 [(set_attr "op_type" "RRE,RXY")
5356 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5358 (define_insn "*subdi3_zero"
5359 [(set (match_operand:DI 0 "register_operand" "=d,d")
5360 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5361 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5362 (clobber (reg:CC CC_REGNUM))]
5367 [(set_attr "op_type" "RRE,RXY")
5368 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5370 (define_insn_and_split "*subdi3_31z"
5371 [(set (match_operand:DI 0 "register_operand" "=&d")
5372 (minus:DI (match_operand:DI 1 "register_operand" "0")
5373 (match_operand:DI 2 "general_operand" "do") ) )
5374 (clobber (reg:CC CC_REGNUM))]
5375 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5377 "&& reload_completed"
5379 [(set (reg:CCL2 CC_REGNUM)
5380 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5382 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5384 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5385 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5386 (clobber (reg:CC CC_REGNUM))])]
5387 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5388 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5389 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5390 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5391 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5392 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5394 (define_insn_and_split "*subdi3_31"
5395 [(set (match_operand:DI 0 "register_operand" "=&d")
5396 (minus:DI (match_operand:DI 1 "register_operand" "0")
5397 (match_operand:DI 2 "general_operand" "do") ) )
5398 (clobber (reg:CC CC_REGNUM))]
5401 "&& reload_completed"
5403 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5404 (clobber (reg:CC CC_REGNUM))])
5406 [(set (reg:CCL2 CC_REGNUM)
5407 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5409 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5411 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5413 (label_ref (match_dup 9))))
5415 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5416 (clobber (reg:CC CC_REGNUM))])
5418 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5419 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5420 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5421 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5422 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5423 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5424 operands[9] = gen_label_rtx ();")
5427 ; subsi3 instruction pattern(s).
5430 (define_expand "subsi3"
5432 [(set (match_operand:SI 0 "register_operand" "")
5433 (minus:SI (match_operand:SI 1 "register_operand" "")
5434 (match_operand:SI 2 "general_operand" "")))
5435 (clobber (reg:CC CC_REGNUM))])]
5439 (define_insn "*subsi3_sign"
5440 [(set (match_operand:SI 0 "register_operand" "=d,d")
5441 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5442 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5443 (clobber (reg:CC CC_REGNUM))]
5448 [(set_attr "op_type" "RX,RXY")
5449 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5452 ; sub(di|si)3 instruction pattern(s).
5455 ; sr, s, sy, sgr, sg, srk, sgrk
5456 (define_insn "*sub<mode>3"
5457 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5458 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5459 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5460 (clobber (reg:CC CC_REGNUM))]
5467 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5468 (set_attr "cpu_facility" "*,z196,*,*")
5469 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5471 ; slr, sl, sly, slgr, slg, slrk, slgrk
5472 (define_insn "*sub<mode>3_borrow_cc"
5473 [(set (reg CC_REGNUM)
5474 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5475 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5477 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5478 (minus:GPR (match_dup 1) (match_dup 2)))]
5479 "s390_match_ccmode (insn, CCL2mode)"
5485 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5486 (set_attr "cpu_facility" "*,z196,*,*")
5487 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5489 ; slr, sl, sly, slgr, slg, slrk, slgrk
5490 (define_insn "*sub<mode>3_borrow_cconly"
5491 [(set (reg CC_REGNUM)
5492 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5493 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5495 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5496 "s390_match_ccmode (insn, CCL2mode)"
5502 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5503 (set_attr "cpu_facility" "*,z196,*,*")
5504 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5506 ; slr, sl, sly, slgr, slg, slrk, slgrk
5507 (define_insn "*sub<mode>3_cc"
5508 [(set (reg CC_REGNUM)
5509 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5510 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5512 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5513 (minus:GPR (match_dup 1) (match_dup 2)))]
5514 "s390_match_ccmode (insn, CCLmode)"
5520 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5521 (set_attr "cpu_facility" "*,z196,*,*")
5522 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5524 ; slr, sl, sly, slgr, slg, slrk, slgrk
5525 (define_insn "*sub<mode>3_cc2"
5526 [(set (reg CC_REGNUM)
5527 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5528 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5529 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5530 (minus:GPR (match_dup 1) (match_dup 2)))]
5531 "s390_match_ccmode (insn, CCL3mode)"
5537 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5538 (set_attr "cpu_facility" "*,z196,*,*")
5539 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5541 ; slr, sl, sly, slgr, slg, slrk, slgrk
5542 (define_insn "*sub<mode>3_cconly"
5543 [(set (reg CC_REGNUM)
5544 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5545 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5547 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5548 "s390_match_ccmode (insn, CCLmode)"
5554 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5555 (set_attr "cpu_facility" "*,z196,*,*")
5556 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5559 ; slr, sl, sly, slgr, slg, slrk, slgrk
5560 (define_insn "*sub<mode>3_cconly2"
5561 [(set (reg CC_REGNUM)
5562 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5563 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5564 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5565 "s390_match_ccmode (insn, CCL3mode)"
5571 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5572 (set_attr "cpu_facility" "*,z196,*,*")
5573 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5577 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5580 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5581 (define_insn "sub<mode>3"
5582 [(set (match_operand:FP 0 "register_operand" "=f, f")
5583 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5584 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5585 (clobber (reg:CC CC_REGNUM))]
5588 s<xde><bt>r\t%0,<op1>%2
5590 [(set_attr "op_type" "<RRer>,RXE")
5591 (set_attr "type" "fsimp<mode>")])
5593 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5594 (define_insn "*sub<mode>3_cc"
5595 [(set (reg CC_REGNUM)
5596 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5597 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5598 (match_operand:FP 3 "const0_operand" "")))
5599 (set (match_operand:FP 0 "register_operand" "=f,f")
5600 (minus:FP (match_dup 1) (match_dup 2)))]
5601 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5603 s<xde><bt>r\t%0,<op1>%2
5605 [(set_attr "op_type" "<RRer>,RXE")
5606 (set_attr "type" "fsimp<mode>")])
5608 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5609 (define_insn "*sub<mode>3_cconly"
5610 [(set (reg CC_REGNUM)
5611 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5612 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5613 (match_operand:FP 3 "const0_operand" "")))
5614 (clobber (match_scratch:FP 0 "=f,f"))]
5615 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5617 s<xde><bt>r\t%0,<op1>%2
5619 [(set_attr "op_type" "<RRer>,RXE")
5620 (set_attr "type" "fsimp<mode>")])
5624 ;;- Conditional add/subtract instructions.
5628 ; add(di|si)cc instruction pattern(s).
5631 ; the following 4 patterns are used when the result of an add with
5632 ; carry is checked for an overflow condition
5634 ; op1 + op2 + c < op1
5636 ; alcr, alc, alcgr, alcg
5637 (define_insn "*add<mode>3_alc_carry1_cc"
5638 [(set (reg CC_REGNUM)
5640 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5641 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5642 (match_operand:GPR 2 "general_operand" "d,RT"))
5644 (set (match_operand:GPR 0 "register_operand" "=d,d")
5645 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5646 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5650 [(set_attr "op_type" "RRE,RXY")
5651 (set_attr "z196prop" "z196_alone,z196_alone")])
5653 ; alcr, alc, alcgr, alcg
5654 (define_insn "*add<mode>3_alc_carry1_cconly"
5655 [(set (reg CC_REGNUM)
5657 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5658 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5659 (match_operand:GPR 2 "general_operand" "d,RT"))
5661 (clobber (match_scratch:GPR 0 "=d,d"))]
5662 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5666 [(set_attr "op_type" "RRE,RXY")
5667 (set_attr "z196prop" "z196_alone,z196_alone")])
5669 ; op1 + op2 + c < op2
5671 ; alcr, alc, alcgr, alcg
5672 (define_insn "*add<mode>3_alc_carry2_cc"
5673 [(set (reg CC_REGNUM)
5675 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5676 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5677 (match_operand:GPR 2 "general_operand" "d,RT"))
5679 (set (match_operand:GPR 0 "register_operand" "=d,d")
5680 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5681 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5685 [(set_attr "op_type" "RRE,RXY")])
5687 ; alcr, alc, alcgr, alcg
5688 (define_insn "*add<mode>3_alc_carry2_cconly"
5689 [(set (reg CC_REGNUM)
5691 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5692 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5693 (match_operand:GPR 2 "general_operand" "d,RT"))
5695 (clobber (match_scratch:GPR 0 "=d,d"))]
5696 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5700 [(set_attr "op_type" "RRE,RXY")])
5702 ; alcr, alc, alcgr, alcg
5703 (define_insn "*add<mode>3_alc_cc"
5704 [(set (reg CC_REGNUM)
5706 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5707 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5708 (match_operand:GPR 2 "general_operand" "d,RT"))
5710 (set (match_operand:GPR 0 "register_operand" "=d,d")
5711 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5712 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5716 [(set_attr "op_type" "RRE,RXY")])
5718 ; alcr, alc, alcgr, alcg
5719 (define_insn "*add<mode>3_alc"
5720 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5721 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5722 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5723 (match_operand:GPR 2 "general_operand" "d,RT")))
5724 (clobber (reg:CC CC_REGNUM))]
5729 [(set_attr "op_type" "RRE,RXY")])
5731 ; slbr, slb, slbgr, slbg
5732 (define_insn "*sub<mode>3_slb_cc"
5733 [(set (reg CC_REGNUM)
5735 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5736 (match_operand:GPR 2 "general_operand" "d,RT"))
5737 (match_operand:GPR 3 "s390_slb_comparison" ""))
5739 (set (match_operand:GPR 0 "register_operand" "=d,d")
5740 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5741 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5745 [(set_attr "op_type" "RRE,RXY")
5746 (set_attr "z10prop" "z10_c,*")])
5748 ; slbr, slb, slbgr, slbg
5749 (define_insn "*sub<mode>3_slb"
5750 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5751 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5752 (match_operand:GPR 2 "general_operand" "d,RT"))
5753 (match_operand:GPR 3 "s390_slb_comparison" "")))
5754 (clobber (reg:CC CC_REGNUM))]
5759 [(set_attr "op_type" "RRE,RXY")
5760 (set_attr "z10prop" "z10_c,*")])
5762 (define_expand "add<mode>cc"
5763 [(match_operand:GPR 0 "register_operand" "")
5764 (match_operand 1 "comparison_operator" "")
5765 (match_operand:GPR 2 "register_operand" "")
5766 (match_operand:GPR 3 "const_int_operand" "")]
5768 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5769 XEXP (operands[1], 0), XEXP (operands[1], 1),
5770 operands[0], operands[2],
5771 operands[3])) FAIL; DONE;")
5774 ; scond instruction pattern(s).
5777 (define_insn_and_split "*scond<mode>"
5778 [(set (match_operand:GPR 0 "register_operand" "=&d")
5779 (match_operand:GPR 1 "s390_alc_comparison" ""))
5780 (clobber (reg:CC CC_REGNUM))]
5783 "&& reload_completed"
5784 [(set (match_dup 0) (const_int 0))
5786 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5788 (clobber (reg:CC CC_REGNUM))])]
5791 (define_insn_and_split "*scond<mode>_neg"
5792 [(set (match_operand:GPR 0 "register_operand" "=&d")
5793 (match_operand:GPR 1 "s390_slb_comparison" ""))
5794 (clobber (reg:CC CC_REGNUM))]
5797 "&& reload_completed"
5798 [(set (match_dup 0) (const_int 0))
5800 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5802 (clobber (reg:CC CC_REGNUM))])
5804 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5805 (clobber (reg:CC CC_REGNUM))])]
5809 (define_expand "cstore<mode>4"
5810 [(set (match_operand:SI 0 "register_operand" "")
5811 (match_operator:SI 1 "s390_scond_operator"
5812 [(match_operand:GPR 2 "register_operand" "")
5813 (match_operand:GPR 3 "general_operand" "")]))]
5815 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5816 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5818 (define_expand "cstorecc4"
5820 [(set (match_operand:SI 0 "register_operand" "")
5821 (match_operator:SI 1 "s390_eqne_operator"
5822 [(match_operand:CCZ1 2 "register_operand")
5823 (match_operand 3 "const0_operand")]))
5824 (clobber (reg:CC CC_REGNUM))])]
5826 "emit_insn (gen_sne (operands[0], operands[2]));
5827 if (GET_CODE (operands[1]) == EQ)
5828 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5831 (define_insn_and_split "sne"
5832 [(set (match_operand:SI 0 "register_operand" "=d")
5833 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5835 (clobber (reg:CC CC_REGNUM))]
5840 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5841 (clobber (reg:CC CC_REGNUM))])])
5845 ;; - Conditional move instructions (introduced with z196)
5848 (define_expand "mov<mode>cc"
5849 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5850 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5851 (match_operand:GPR 2 "nonimmediate_operand" "")
5852 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5854 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5855 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5857 ; locr, loc, stoc, locgr, locg, stocg
5858 (define_insn_and_split "*mov<mode>cc"
5859 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5861 (match_operator 1 "s390_comparison"
5862 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5863 (match_operand 5 "const_int_operand" "")])
5864 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5865 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5875 "&& reload_completed
5876 && MEM_P (operands[3]) && MEM_P (operands[4])"
5879 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5884 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5888 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5891 ;;- Multiply instructions.
5895 ; muldi3 instruction pattern(s).
5898 (define_insn "*muldi3_sign"
5899 [(set (match_operand:DI 0 "register_operand" "=d,d")
5900 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5901 (match_operand:DI 1 "register_operand" "0,0")))]
5906 [(set_attr "op_type" "RRE,RXY")
5907 (set_attr "type" "imuldi")])
5909 (define_insn "muldi3"
5910 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5911 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5912 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5919 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5920 (set_attr "type" "imuldi")
5921 (set_attr "cpu_facility" "*,*,*,z10")])
5924 ; mulsi3 instruction pattern(s).
5927 (define_insn "*mulsi3_sign"
5928 [(set (match_operand:SI 0 "register_operand" "=d,d")
5929 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5930 (match_operand:SI 1 "register_operand" "0,0")))]
5935 [(set_attr "op_type" "RX,RXY")
5936 (set_attr "type" "imulhi")
5937 (set_attr "cpu_facility" "*,z10")])
5939 (define_insn "mulsi3"
5940 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5941 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5942 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5950 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5951 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5952 (set_attr "cpu_facility" "*,*,*,*,z10")])
5955 ; mulsidi3 instruction pattern(s).
5958 (define_insn "mulsidi3"
5959 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5960 (mult:DI (sign_extend:DI
5961 (match_operand:SI 1 "register_operand" "%0,0,0"))
5963 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5969 [(set_attr "op_type" "RR,RX,RXY")
5970 (set_attr "type" "imulsi")
5971 (set_attr "cpu_facility" "*,*,z10")])
5974 ; umul instruction pattern(s).
5977 ; mlr, ml, mlgr, mlg
5978 (define_insn "umul<dwh><mode>3"
5979 [(set (match_operand:DW 0 "register_operand" "=d, d")
5980 (mult:DW (zero_extend:DW
5981 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5983 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5988 [(set_attr "op_type" "RRE,RXY")
5989 (set_attr "type" "imul<dwh>")])
5992 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5995 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5996 (define_insn "mul<mode>3"
5997 [(set (match_operand:FP 0 "register_operand" "=f,f")
5998 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5999 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6002 m<xdee><bt>r\t%0,<op1>%2
6004 [(set_attr "op_type" "<RRer>,RXE")
6005 (set_attr "type" "fmul<mode>")])
6007 ; madbr, maebr, maxb, madb, maeb
6008 (define_insn "fma<mode>4"
6009 [(set (match_operand:DSF 0 "register_operand" "=f,f")
6010 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
6011 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
6012 (match_operand:DSF 3 "register_operand" "0,0")))]
6017 [(set_attr "op_type" "RRE,RXE")
6018 (set_attr "type" "fmadd<mode>")])
6020 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6021 (define_insn "fms<mode>4"
6022 [(set (match_operand:DSF 0 "register_operand" "=f,f")
6023 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
6024 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
6025 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
6030 [(set_attr "op_type" "RRE,RXE")
6031 (set_attr "type" "fmadd<mode>")])
6034 ;;- Divide and modulo instructions.
6038 ; divmoddi4 instruction pattern(s).
6041 (define_expand "divmoddi4"
6042 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6043 (div:DI (match_operand:DI 1 "register_operand" "")
6044 (match_operand:DI 2 "general_operand" "")))
6045 (set (match_operand:DI 3 "general_operand" "")
6046 (mod:DI (match_dup 1) (match_dup 2)))])
6047 (clobber (match_dup 4))]
6050 rtx insn, div_equal, mod_equal;
6052 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6053 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6055 operands[4] = gen_reg_rtx(TImode);
6056 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6058 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6059 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6061 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6062 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6067 (define_insn "divmodtidi3"
6068 [(set (match_operand:TI 0 "register_operand" "=d,d")
6072 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6073 (match_operand:DI 2 "general_operand" "d,RT")))
6075 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6080 [(set_attr "op_type" "RRE,RXY")
6081 (set_attr "type" "idiv")])
6083 (define_insn "divmodtisi3"
6084 [(set (match_operand:TI 0 "register_operand" "=d,d")
6088 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6090 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
6093 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6098 [(set_attr "op_type" "RRE,RXY")
6099 (set_attr "type" "idiv")])
6102 ; udivmoddi4 instruction pattern(s).
6105 (define_expand "udivmoddi4"
6106 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6107 (udiv:DI (match_operand:DI 1 "general_operand" "")
6108 (match_operand:DI 2 "nonimmediate_operand" "")))
6109 (set (match_operand:DI 3 "general_operand" "")
6110 (umod:DI (match_dup 1) (match_dup 2)))])
6111 (clobber (match_dup 4))]
6114 rtx insn, div_equal, mod_equal, equal;
6116 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6117 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6118 equal = gen_rtx_IOR (TImode,
6119 gen_rtx_ASHIFT (TImode,
6120 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6122 gen_rtx_ZERO_EXTEND (TImode, div_equal));
6124 operands[4] = gen_reg_rtx(TImode);
6125 emit_clobber (operands[4]);
6126 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6127 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6129 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6130 set_unique_reg_note (insn, REG_EQUAL, equal);
6132 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6133 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6135 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6136 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6141 (define_insn "udivmodtidi3"
6142 [(set (match_operand:TI 0 "register_operand" "=d,d")
6147 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6149 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6153 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6158 [(set_attr "op_type" "RRE,RXY")
6159 (set_attr "type" "idiv")])
6162 ; divmodsi4 instruction pattern(s).
6165 (define_expand "divmodsi4"
6166 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6167 (div:SI (match_operand:SI 1 "general_operand" "")
6168 (match_operand:SI 2 "nonimmediate_operand" "")))
6169 (set (match_operand:SI 3 "general_operand" "")
6170 (mod:SI (match_dup 1) (match_dup 2)))])
6171 (clobber (match_dup 4))]
6174 rtx insn, div_equal, mod_equal, equal;
6176 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6177 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6178 equal = gen_rtx_IOR (DImode,
6179 gen_rtx_ASHIFT (DImode,
6180 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6182 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6184 operands[4] = gen_reg_rtx(DImode);
6185 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6187 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6188 set_unique_reg_note (insn, REG_EQUAL, equal);
6190 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6191 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6193 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6194 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6199 (define_insn "divmoddisi3"
6200 [(set (match_operand:DI 0 "register_operand" "=d,d")
6205 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6207 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6211 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6216 [(set_attr "op_type" "RR,RX")
6217 (set_attr "type" "idiv")])
6220 ; udivsi3 and umodsi3 instruction pattern(s).
6223 (define_expand "udivmodsi4"
6224 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6225 (udiv:SI (match_operand:SI 1 "general_operand" "")
6226 (match_operand:SI 2 "nonimmediate_operand" "")))
6227 (set (match_operand:SI 3 "general_operand" "")
6228 (umod:SI (match_dup 1) (match_dup 2)))])
6229 (clobber (match_dup 4))]
6230 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6232 rtx insn, div_equal, mod_equal, equal;
6234 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6235 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6236 equal = gen_rtx_IOR (DImode,
6237 gen_rtx_ASHIFT (DImode,
6238 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6240 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6242 operands[4] = gen_reg_rtx(DImode);
6243 emit_clobber (operands[4]);
6244 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6245 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6247 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6248 set_unique_reg_note (insn, REG_EQUAL, equal);
6250 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6251 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6253 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6254 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6259 (define_insn "udivmoddisi3"
6260 [(set (match_operand:DI 0 "register_operand" "=d,d")
6265 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6267 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6271 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6272 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6276 [(set_attr "op_type" "RRE,RXY")
6277 (set_attr "type" "idiv")])
6279 (define_expand "udivsi3"
6280 [(set (match_operand:SI 0 "register_operand" "=d")
6281 (udiv:SI (match_operand:SI 1 "general_operand" "")
6282 (match_operand:SI 2 "general_operand" "")))
6283 (clobber (match_dup 3))]
6284 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6286 rtx insn, udiv_equal, umod_equal, equal;
6288 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6289 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6290 equal = gen_rtx_IOR (DImode,
6291 gen_rtx_ASHIFT (DImode,
6292 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6294 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6296 operands[3] = gen_reg_rtx (DImode);
6298 if (CONSTANT_P (operands[2]))
6300 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6302 rtx_code_label *label1 = gen_label_rtx ();
6304 operands[1] = make_safe_from (operands[1], operands[0]);
6305 emit_move_insn (operands[0], const0_rtx);
6306 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6308 emit_move_insn (operands[0], const1_rtx);
6309 emit_label (label1);
6313 operands[2] = force_reg (SImode, operands[2]);
6314 operands[2] = make_safe_from (operands[2], operands[0]);
6316 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6317 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6319 set_unique_reg_note (insn, REG_EQUAL, equal);
6321 insn = emit_move_insn (operands[0],
6322 gen_lowpart (SImode, operands[3]));
6323 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6328 rtx_code_label *label1 = gen_label_rtx ();
6329 rtx_code_label *label2 = gen_label_rtx ();
6330 rtx_code_label *label3 = gen_label_rtx ();
6332 operands[1] = force_reg (SImode, operands[1]);
6333 operands[1] = make_safe_from (operands[1], operands[0]);
6334 operands[2] = force_reg (SImode, operands[2]);
6335 operands[2] = make_safe_from (operands[2], operands[0]);
6337 emit_move_insn (operands[0], const0_rtx);
6338 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6340 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6342 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6344 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6345 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6347 set_unique_reg_note (insn, REG_EQUAL, equal);
6349 insn = emit_move_insn (operands[0],
6350 gen_lowpart (SImode, operands[3]));
6351 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6354 emit_label (label1);
6355 emit_move_insn (operands[0], operands[1]);
6357 emit_label (label2);
6358 emit_move_insn (operands[0], const1_rtx);
6359 emit_label (label3);
6361 emit_move_insn (operands[0], operands[0]);
6365 (define_expand "umodsi3"
6366 [(set (match_operand:SI 0 "register_operand" "=d")
6367 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6368 (match_operand:SI 2 "nonimmediate_operand" "")))
6369 (clobber (match_dup 3))]
6370 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6372 rtx insn, udiv_equal, umod_equal, equal;
6374 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6375 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6376 equal = gen_rtx_IOR (DImode,
6377 gen_rtx_ASHIFT (DImode,
6378 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6380 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6382 operands[3] = gen_reg_rtx (DImode);
6384 if (CONSTANT_P (operands[2]))
6386 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6388 rtx_code_label *label1 = gen_label_rtx ();
6390 operands[1] = make_safe_from (operands[1], operands[0]);
6391 emit_move_insn (operands[0], operands[1]);
6392 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6394 emit_insn (gen_abssi2 (operands[0], operands[2]));
6395 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6396 emit_label (label1);
6400 operands[2] = force_reg (SImode, operands[2]);
6401 operands[2] = make_safe_from (operands[2], operands[0]);
6403 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6404 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6406 set_unique_reg_note (insn, REG_EQUAL, equal);
6408 insn = emit_move_insn (operands[0],
6409 gen_highpart (SImode, operands[3]));
6410 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6415 rtx_code_label *label1 = gen_label_rtx ();
6416 rtx_code_label *label2 = gen_label_rtx ();
6417 rtx_code_label *label3 = gen_label_rtx ();
6419 operands[1] = force_reg (SImode, operands[1]);
6420 operands[1] = make_safe_from (operands[1], operands[0]);
6421 operands[2] = force_reg (SImode, operands[2]);
6422 operands[2] = make_safe_from (operands[2], operands[0]);
6424 emit_move_insn(operands[0], operands[1]);
6425 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6427 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6429 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6431 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6432 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6434 set_unique_reg_note (insn, REG_EQUAL, equal);
6436 insn = emit_move_insn (operands[0],
6437 gen_highpart (SImode, operands[3]));
6438 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6441 emit_label (label1);
6442 emit_move_insn (operands[0], const0_rtx);
6444 emit_label (label2);
6445 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6446 emit_label (label3);
6452 ; div(df|sf)3 instruction pattern(s).
6455 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6456 (define_insn "div<mode>3"
6457 [(set (match_operand:FP 0 "register_operand" "=f,f")
6458 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6459 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6462 d<xde><bt>r\t%0,<op1>%2
6464 [(set_attr "op_type" "<RRer>,RXE")
6465 (set_attr "type" "fdiv<mode>")])
6469 ;;- And instructions.
6472 (define_expand "and<mode>3"
6473 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6474 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6475 (match_operand:INT 2 "general_operand" "")))
6476 (clobber (reg:CC CC_REGNUM))]
6478 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6481 ; anddi3 instruction pattern(s).
6484 (define_insn "*anddi3_cc"
6485 [(set (reg CC_REGNUM)
6487 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6488 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6490 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6491 (and:DI (match_dup 1) (match_dup 2)))]
6492 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6497 risbg\t%0,%1,%s2,128+%e2,0"
6498 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6499 (set_attr "cpu_facility" "*,z196,*,z10")
6500 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6502 (define_insn "*anddi3_cconly"
6503 [(set (reg CC_REGNUM)
6505 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6506 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6508 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6510 && s390_match_ccmode(insn, CCTmode)
6511 /* Do not steal TM patterns. */
6512 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6517 risbg\t%0,%1,%s2,128+%e2,0"
6518 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6519 (set_attr "cpu_facility" "*,z196,*,z10")
6520 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6522 (define_insn "*anddi3"
6523 [(set (match_operand:DI 0 "nonimmediate_operand"
6524 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6526 (match_operand:DI 1 "nonimmediate_operand"
6527 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6528 (match_operand:DI 2 "general_operand"
6529 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6530 (clobber (reg:CC CC_REGNUM))]
6531 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6544 risbg\t%0,%1,%s2,128+%e2,0
6547 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6548 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6549 (set_attr "z10prop" "*,
6565 [(set (match_operand:DI 0 "s_operand" "")
6566 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6567 (clobber (reg:CC CC_REGNUM))]
6570 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6571 (clobber (reg:CC CC_REGNUM))])]
6572 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6574 ;; These two are what combine generates for (ashift (zero_extract)).
6575 (define_insn "*extzv_<mode>_srl"
6576 [(set (match_operand:GPR 0 "register_operand" "=d")
6577 (and:GPR (lshiftrt:GPR
6578 (match_operand:GPR 1 "register_operand" "d")
6579 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6580 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6581 (clobber (reg:CC CC_REGNUM))]
6583 /* Note that even for the SImode pattern, the rotate is always DImode. */
6584 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6585 INTVAL (operands[3]))"
6586 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6587 [(set_attr "op_type" "RIE")
6588 (set_attr "z10prop" "z10_super_E1")])
6590 (define_insn "*extzv_<mode>_sll"
6591 [(set (match_operand:GPR 0 "register_operand" "=d")
6592 (and:GPR (ashift:GPR
6593 (match_operand:GPR 1 "register_operand" "d")
6594 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6595 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6596 (clobber (reg:CC CC_REGNUM))]
6598 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6599 INTVAL (operands[3]))"
6600 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6601 [(set_attr "op_type" "RIE")
6602 (set_attr "z10prop" "z10_super_E1")])
6606 ; andsi3 instruction pattern(s).
6609 (define_insn "*andsi3_cc"
6610 [(set (reg CC_REGNUM)
6613 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6614 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6616 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6617 (and:SI (match_dup 1) (match_dup 2)))]
6618 "s390_match_ccmode(insn, CCTmode)"
6625 risbg\t%0,%1,%t2,128+%f2,0"
6626 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6627 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6628 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6629 z10_super_E1,z10_super_E1,z10_super_E1")])
6631 (define_insn "*andsi3_cconly"
6632 [(set (reg CC_REGNUM)
6635 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6636 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6638 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6639 "s390_match_ccmode(insn, CCTmode)
6640 /* Do not steal TM patterns. */
6641 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6648 risbg\t%0,%1,%t2,128+%f2,0"
6649 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6650 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6651 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6652 z10_super_E1,z10_super_E1,z10_super_E1")])
6654 (define_insn "*andsi3_zarch"
6655 [(set (match_operand:SI 0 "nonimmediate_operand"
6656 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6657 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6658 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6659 (match_operand:SI 2 "general_operand"
6660 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6661 (clobber (reg:CC CC_REGNUM))]
6662 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6673 risbg\t%0,%1,%t2,128+%f2,0
6676 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6677 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6678 (set_attr "z10prop" "*,
6691 (define_insn "*andsi3_esa"
6692 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6693 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6694 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6695 (clobber (reg:CC CC_REGNUM))]
6696 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6702 [(set_attr "op_type" "RR,RX,SI,SS")
6703 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6707 [(set (match_operand:SI 0 "s_operand" "")
6708 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6709 (clobber (reg:CC CC_REGNUM))]
6712 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6713 (clobber (reg:CC CC_REGNUM))])]
6714 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6717 ; andhi3 instruction pattern(s).
6720 (define_insn "*andhi3_zarch"
6721 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6722 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6723 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6724 (clobber (reg:CC CC_REGNUM))]
6725 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6732 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6733 (set_attr "cpu_facility" "*,z196,*,*,*")
6734 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6737 (define_insn "*andhi3_esa"
6738 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6739 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6740 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6741 (clobber (reg:CC CC_REGNUM))]
6742 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6747 [(set_attr "op_type" "RR,SI,SS")
6748 (set_attr "z10prop" "z10_super_E1,*,*")
6752 [(set (match_operand:HI 0 "s_operand" "")
6753 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6754 (clobber (reg:CC CC_REGNUM))]
6757 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6758 (clobber (reg:CC CC_REGNUM))])]
6759 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6762 ; andqi3 instruction pattern(s).
6765 (define_insn "*andqi3_zarch"
6766 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6767 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6768 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6769 (clobber (reg:CC CC_REGNUM))]
6770 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6778 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6779 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6780 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6782 (define_insn "*andqi3_esa"
6783 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6784 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6785 (match_operand:QI 2 "general_operand" "d,n,Q")))
6786 (clobber (reg:CC CC_REGNUM))]
6787 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6792 [(set_attr "op_type" "RR,SI,SS")
6793 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6796 ; Block and (NC) patterns.
6800 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6801 (and:BLK (match_dup 0)
6802 (match_operand:BLK 1 "memory_operand" "Q")))
6803 (use (match_operand 2 "const_int_operand" "n"))
6804 (clobber (reg:CC CC_REGNUM))]
6805 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6806 "nc\t%O0(%2,%R0),%S1"
6807 [(set_attr "op_type" "SS")
6808 (set_attr "z196prop" "z196_cracked")])
6811 [(set (match_operand 0 "memory_operand" "")
6813 (match_operand 1 "memory_operand" "")))
6814 (clobber (reg:CC CC_REGNUM))]
6816 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6817 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6819 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6821 (clobber (reg:CC CC_REGNUM))])]
6823 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6824 operands[0] = adjust_address (operands[0], BLKmode, 0);
6825 operands[1] = adjust_address (operands[1], BLKmode, 0);
6830 [(set (match_operand:BLK 0 "memory_operand" "")
6831 (and:BLK (match_dup 0)
6832 (match_operand:BLK 1 "memory_operand" "")))
6833 (use (match_operand 2 "const_int_operand" ""))
6834 (clobber (reg:CC CC_REGNUM))])
6836 [(set (match_operand:BLK 3 "memory_operand" "")
6837 (and:BLK (match_dup 3)
6838 (match_operand:BLK 4 "memory_operand" "")))
6839 (use (match_operand 5 "const_int_operand" ""))
6840 (clobber (reg:CC CC_REGNUM))])]
6841 "s390_offset_p (operands[0], operands[3], operands[2])
6842 && s390_offset_p (operands[1], operands[4], operands[2])
6843 && !s390_overlap_p (operands[0], operands[1],
6844 INTVAL (operands[2]) + INTVAL (operands[5]))
6845 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6847 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6849 (clobber (reg:CC CC_REGNUM))])]
6850 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6851 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6852 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6856 ;;- Bit set (inclusive or) instructions.
6859 (define_expand "ior<mode>3"
6860 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6861 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6862 (match_operand:INT 2 "general_operand" "")))
6863 (clobber (reg:CC CC_REGNUM))]
6865 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6868 ; iordi3 instruction pattern(s).
6871 (define_insn "*iordi3_cc"
6872 [(set (reg CC_REGNUM)
6873 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6874 (match_operand:DI 2 "general_operand" " d,d,RT"))
6876 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6877 (ior:DI (match_dup 1) (match_dup 2)))]
6878 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6883 [(set_attr "op_type" "RRE,RRF,RXY")
6884 (set_attr "cpu_facility" "*,z196,*")
6885 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6887 (define_insn "*iordi3_cconly"
6888 [(set (reg CC_REGNUM)
6889 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6890 (match_operand:DI 2 "general_operand" " d,d,RT"))
6892 (clobber (match_scratch:DI 0 "=d,d,d"))]
6893 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6898 [(set_attr "op_type" "RRE,RRF,RXY")
6899 (set_attr "cpu_facility" "*,z196,*")
6900 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6902 (define_insn "*iordi3"
6903 [(set (match_operand:DI 0 "nonimmediate_operand"
6904 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6905 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6906 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6907 (match_operand:DI 2 "general_operand"
6908 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6909 (clobber (reg:CC CC_REGNUM))]
6910 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6923 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6924 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6925 (set_attr "z10prop" "z10_super_E1,
6938 [(set (match_operand:DI 0 "s_operand" "")
6939 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6940 (clobber (reg:CC CC_REGNUM))]
6943 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6944 (clobber (reg:CC CC_REGNUM))])]
6945 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6948 ; iorsi3 instruction pattern(s).
6951 (define_insn "*iorsi3_cc"
6952 [(set (reg CC_REGNUM)
6953 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6954 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6956 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6957 (ior:SI (match_dup 1) (match_dup 2)))]
6958 "s390_match_ccmode(insn, CCTmode)"
6965 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6966 (set_attr "cpu_facility" "*,*,z196,*,*")
6967 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6969 (define_insn "*iorsi3_cconly"
6970 [(set (reg CC_REGNUM)
6971 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6972 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6974 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6975 "s390_match_ccmode(insn, CCTmode)"
6982 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6983 (set_attr "cpu_facility" "*,*,z196,*,*")
6984 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6986 (define_insn "*iorsi3_zarch"
6987 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6988 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6989 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6990 (clobber (reg:CC CC_REGNUM))]
6991 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7002 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7003 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
7004 (set_attr "z10prop" "z10_super_E1,
7014 (define_insn "*iorsi3_esa"
7015 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7016 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7017 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7018 (clobber (reg:CC CC_REGNUM))]
7019 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7025 [(set_attr "op_type" "RR,RX,SI,SS")
7026 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7029 [(set (match_operand:SI 0 "s_operand" "")
7030 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7031 (clobber (reg:CC CC_REGNUM))]
7034 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7035 (clobber (reg:CC CC_REGNUM))])]
7036 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7039 ; iorhi3 instruction pattern(s).
7042 (define_insn "*iorhi3_zarch"
7043 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7044 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7045 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
7046 (clobber (reg:CC CC_REGNUM))]
7047 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7054 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7055 (set_attr "cpu_facility" "*,z196,*,*,*")
7056 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7058 (define_insn "*iorhi3_esa"
7059 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7060 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7061 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7062 (clobber (reg:CC CC_REGNUM))]
7063 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7068 [(set_attr "op_type" "RR,SI,SS")
7069 (set_attr "z10prop" "z10_super_E1,*,*")])
7072 [(set (match_operand:HI 0 "s_operand" "")
7073 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7074 (clobber (reg:CC CC_REGNUM))]
7077 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7078 (clobber (reg:CC CC_REGNUM))])]
7079 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7082 ; iorqi3 instruction pattern(s).
7085 (define_insn "*iorqi3_zarch"
7086 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7087 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7088 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7089 (clobber (reg:CC CC_REGNUM))]
7090 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7098 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7099 (set_attr "cpu_facility" "*,z196,*,*,*,*")
7100 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7101 z10_super,z10_super,*")])
7103 (define_insn "*iorqi3_esa"
7104 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7105 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7106 (match_operand:QI 2 "general_operand" "d,n,Q")))
7107 (clobber (reg:CC CC_REGNUM))]
7108 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7113 [(set_attr "op_type" "RR,SI,SS")
7114 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7117 ; Block inclusive or (OC) patterns.
7121 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7122 (ior:BLK (match_dup 0)
7123 (match_operand:BLK 1 "memory_operand" "Q")))
7124 (use (match_operand 2 "const_int_operand" "n"))
7125 (clobber (reg:CC CC_REGNUM))]
7126 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7127 "oc\t%O0(%2,%R0),%S1"
7128 [(set_attr "op_type" "SS")
7129 (set_attr "z196prop" "z196_cracked")])
7132 [(set (match_operand 0 "memory_operand" "")
7134 (match_operand 1 "memory_operand" "")))
7135 (clobber (reg:CC CC_REGNUM))]
7137 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7138 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7140 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7142 (clobber (reg:CC CC_REGNUM))])]
7144 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7145 operands[0] = adjust_address (operands[0], BLKmode, 0);
7146 operands[1] = adjust_address (operands[1], BLKmode, 0);
7151 [(set (match_operand:BLK 0 "memory_operand" "")
7152 (ior:BLK (match_dup 0)
7153 (match_operand:BLK 1 "memory_operand" "")))
7154 (use (match_operand 2 "const_int_operand" ""))
7155 (clobber (reg:CC CC_REGNUM))])
7157 [(set (match_operand:BLK 3 "memory_operand" "")
7158 (ior:BLK (match_dup 3)
7159 (match_operand:BLK 4 "memory_operand" "")))
7160 (use (match_operand 5 "const_int_operand" ""))
7161 (clobber (reg:CC CC_REGNUM))])]
7162 "s390_offset_p (operands[0], operands[3], operands[2])
7163 && s390_offset_p (operands[1], operands[4], operands[2])
7164 && !s390_overlap_p (operands[0], operands[1],
7165 INTVAL (operands[2]) + INTVAL (operands[5]))
7166 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7168 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7170 (clobber (reg:CC CC_REGNUM))])]
7171 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7172 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7173 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7177 ;;- Xor instructions.
7180 (define_expand "xor<mode>3"
7181 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7182 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7183 (match_operand:INT 2 "general_operand" "")))
7184 (clobber (reg:CC CC_REGNUM))]
7186 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7188 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7189 ; simplifications. So its better to have something matching.
7191 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7192 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7195 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7196 (clobber (reg:CC CC_REGNUM))])]
7198 operands[2] = constm1_rtx;
7199 if (!s390_logical_operator_ok_p (operands))
7204 ; xordi3 instruction pattern(s).
7207 (define_insn "*xordi3_cc"
7208 [(set (reg CC_REGNUM)
7209 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7210 (match_operand:DI 2 "general_operand" " d,d,RT"))
7212 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7213 (xor:DI (match_dup 1) (match_dup 2)))]
7214 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7219 [(set_attr "op_type" "RRE,RRF,RXY")
7220 (set_attr "cpu_facility" "*,z196,*")
7221 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7223 (define_insn "*xordi3_cconly"
7224 [(set (reg CC_REGNUM)
7225 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7226 (match_operand:DI 2 "general_operand" " d,d,RT"))
7228 (clobber (match_scratch:DI 0 "=d,d, d"))]
7229 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7234 [(set_attr "op_type" "RRE,RRF,RXY")
7235 (set_attr "cpu_facility" "*,z196,*")
7236 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7238 (define_insn "*xordi3"
7239 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
7240 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
7241 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7242 (clobber (reg:CC CC_REGNUM))]
7243 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7252 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7253 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7254 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7255 *,z10_super_E1,*,*")])
7258 [(set (match_operand:DI 0 "s_operand" "")
7259 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7260 (clobber (reg:CC CC_REGNUM))]
7263 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7264 (clobber (reg:CC CC_REGNUM))])]
7265 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7268 ; xorsi3 instruction pattern(s).
7271 (define_insn "*xorsi3_cc"
7272 [(set (reg CC_REGNUM)
7273 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7274 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7276 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7277 (xor:SI (match_dup 1) (match_dup 2)))]
7278 "s390_match_ccmode(insn, CCTmode)"
7285 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7286 (set_attr "cpu_facility" "*,*,z196,*,*")
7287 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7288 z10_super_E1,z10_super_E1")])
7290 (define_insn "*xorsi3_cconly"
7291 [(set (reg CC_REGNUM)
7292 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7293 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7295 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7296 "s390_match_ccmode(insn, CCTmode)"
7303 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7304 (set_attr "cpu_facility" "*,*,z196,*,*")
7305 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7306 z10_super_E1,z10_super_E1")])
7308 (define_insn "*xorsi3"
7309 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7310 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7311 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7312 (clobber (reg:CC CC_REGNUM))]
7313 "s390_logical_operator_ok_p (operands)"
7322 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7323 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7324 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7325 z10_super_E1,z10_super_E1,*,*")])
7328 [(set (match_operand:SI 0 "s_operand" "")
7329 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7330 (clobber (reg:CC CC_REGNUM))]
7333 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7334 (clobber (reg:CC CC_REGNUM))])]
7335 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7338 ; xorhi3 instruction pattern(s).
7341 (define_insn "*xorhi3"
7342 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7343 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7344 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7345 (clobber (reg:CC CC_REGNUM))]
7346 "s390_logical_operator_ok_p (operands)"
7353 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7354 (set_attr "cpu_facility" "*,*,z196,*,*")
7355 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7358 [(set (match_operand:HI 0 "s_operand" "")
7359 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7360 (clobber (reg:CC CC_REGNUM))]
7363 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7364 (clobber (reg:CC CC_REGNUM))])]
7365 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7368 ; xorqi3 instruction pattern(s).
7371 (define_insn "*xorqi3"
7372 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7373 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7374 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7375 (clobber (reg:CC CC_REGNUM))]
7376 "s390_logical_operator_ok_p (operands)"
7384 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7385 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7386 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7390 ; Block exclusive or (XC) patterns.
7394 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7395 (xor:BLK (match_dup 0)
7396 (match_operand:BLK 1 "memory_operand" "Q")))
7397 (use (match_operand 2 "const_int_operand" "n"))
7398 (clobber (reg:CC CC_REGNUM))]
7399 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7400 "xc\t%O0(%2,%R0),%S1"
7401 [(set_attr "op_type" "SS")])
7404 [(set (match_operand 0 "memory_operand" "")
7406 (match_operand 1 "memory_operand" "")))
7407 (clobber (reg:CC CC_REGNUM))]
7409 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7410 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7412 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7414 (clobber (reg:CC CC_REGNUM))])]
7416 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7417 operands[0] = adjust_address (operands[0], BLKmode, 0);
7418 operands[1] = adjust_address (operands[1], BLKmode, 0);
7423 [(set (match_operand:BLK 0 "memory_operand" "")
7424 (xor:BLK (match_dup 0)
7425 (match_operand:BLK 1 "memory_operand" "")))
7426 (use (match_operand 2 "const_int_operand" ""))
7427 (clobber (reg:CC CC_REGNUM))])
7429 [(set (match_operand:BLK 3 "memory_operand" "")
7430 (xor:BLK (match_dup 3)
7431 (match_operand:BLK 4 "memory_operand" "")))
7432 (use (match_operand 5 "const_int_operand" ""))
7433 (clobber (reg:CC CC_REGNUM))])]
7434 "s390_offset_p (operands[0], operands[3], operands[2])
7435 && s390_offset_p (operands[1], operands[4], operands[2])
7436 && !s390_overlap_p (operands[0], operands[1],
7437 INTVAL (operands[2]) + INTVAL (operands[5]))
7438 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7440 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7442 (clobber (reg:CC CC_REGNUM))])]
7443 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7444 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7445 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7448 ; Block xor (XC) patterns with src == dest.
7451 (define_insn "*xc_zero"
7452 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7454 (use (match_operand 1 "const_int_operand" "n"))
7455 (clobber (reg:CC CC_REGNUM))]
7456 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7457 "xc\t%O0(%1,%R0),%S0"
7458 [(set_attr "op_type" "SS")
7459 (set_attr "z196prop" "z196_cracked")])
7463 [(set (match_operand:BLK 0 "memory_operand" "")
7465 (use (match_operand 1 "const_int_operand" ""))
7466 (clobber (reg:CC CC_REGNUM))])
7468 [(set (match_operand:BLK 2 "memory_operand" "")
7470 (use (match_operand 3 "const_int_operand" ""))
7471 (clobber (reg:CC CC_REGNUM))])]
7472 "s390_offset_p (operands[0], operands[2], operands[1])
7473 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7475 [(set (match_dup 4) (const_int 0))
7477 (clobber (reg:CC CC_REGNUM))])]
7478 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7479 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7483 ;;- Negate instructions.
7487 ; neg(di|si)2 instruction pattern(s).
7490 (define_expand "neg<mode>2"
7492 [(set (match_operand:DSI 0 "register_operand" "=d")
7493 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7494 (clobber (reg:CC CC_REGNUM))])]
7498 (define_insn "*negdi2_sign_cc"
7499 [(set (reg CC_REGNUM)
7500 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7501 (match_operand:SI 1 "register_operand" "d") 0)
7502 (const_int 32)) (const_int 32)))
7504 (set (match_operand:DI 0 "register_operand" "=d")
7505 (neg:DI (sign_extend:DI (match_dup 1))))]
7506 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7508 [(set_attr "op_type" "RRE")
7509 (set_attr "z10prop" "z10_c")])
7511 (define_insn "*negdi2_sign"
7512 [(set (match_operand:DI 0 "register_operand" "=d")
7513 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7514 (clobber (reg:CC CC_REGNUM))]
7517 [(set_attr "op_type" "RRE")
7518 (set_attr "z10prop" "z10_c")])
7521 (define_insn "*neg<mode>2_cc"
7522 [(set (reg CC_REGNUM)
7523 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7525 (set (match_operand:GPR 0 "register_operand" "=d")
7526 (neg:GPR (match_dup 1)))]
7527 "s390_match_ccmode (insn, CCAmode)"
7529 [(set_attr "op_type" "RR<E>")
7530 (set_attr "z10prop" "z10_super_c_E1")])
7533 (define_insn "*neg<mode>2_cconly"
7534 [(set (reg CC_REGNUM)
7535 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7537 (clobber (match_scratch:GPR 0 "=d"))]
7538 "s390_match_ccmode (insn, CCAmode)"
7540 [(set_attr "op_type" "RR<E>")
7541 (set_attr "z10prop" "z10_super_c_E1")])
7544 (define_insn "*neg<mode>2"
7545 [(set (match_operand:GPR 0 "register_operand" "=d")
7546 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7547 (clobber (reg:CC CC_REGNUM))]
7550 [(set_attr "op_type" "RR<E>")
7551 (set_attr "z10prop" "z10_super_c_E1")])
7553 (define_insn "*negdi2_31"
7554 [(set (match_operand:DI 0 "register_operand" "=d")
7555 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7556 (clobber (reg:CC CC_REGNUM))]
7560 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7562 ; Doing the twos complement separately on the SImode parts does an
7563 ; unwanted +1 on the high part which needs to be subtracted afterwards
7564 ; ... unless the +1 on the low part created an overflow.
7567 [(set (match_operand:DI 0 "register_operand" "")
7568 (neg:DI (match_operand:DI 1 "register_operand" "")))
7569 (clobber (reg:CC CC_REGNUM))]
7571 && (REGNO (operands[0]) == REGNO (operands[1])
7572 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7573 && reload_completed"
7575 [(set (match_dup 2) (neg:SI (match_dup 3)))
7576 (clobber (reg:CC CC_REGNUM))])
7578 [(set (reg:CCAP CC_REGNUM)
7579 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7580 (set (match_dup 4) (neg:SI (match_dup 5)))])
7582 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7584 (label_ref (match_dup 6))))
7586 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7587 (clobber (reg:CC CC_REGNUM))])
7589 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7590 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7591 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7592 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7593 operands[6] = gen_label_rtx ();")
7595 ; Like above but first make a copy of the low part of the src operand
7596 ; since it might overlap with the high part of the destination.
7599 [(set (match_operand:DI 0 "register_operand" "")
7600 (neg:DI (match_operand:DI 1 "register_operand" "")))
7601 (clobber (reg:CC CC_REGNUM))]
7603 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7604 && reload_completed"
7605 [; Make a backup of op5 first
7606 (set (match_dup 4) (match_dup 5))
7607 ; Setting op2 here might clobber op5
7609 [(set (match_dup 2) (neg:SI (match_dup 3)))
7610 (clobber (reg:CC CC_REGNUM))])
7612 [(set (reg:CCAP CC_REGNUM)
7613 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7614 (set (match_dup 4) (neg:SI (match_dup 4)))])
7616 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7618 (label_ref (match_dup 6))))
7620 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7621 (clobber (reg:CC CC_REGNUM))])
7623 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7624 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7625 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7626 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7627 operands[6] = gen_label_rtx ();")
7630 ; neg(df|sf)2 instruction pattern(s).
7633 (define_expand "neg<mode>2"
7635 [(set (match_operand:BFP 0 "register_operand" "=f")
7636 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7637 (clobber (reg:CC CC_REGNUM))])]
7641 ; lcxbr, lcdbr, lcebr
7642 (define_insn "*neg<mode>2_cc"
7643 [(set (reg CC_REGNUM)
7644 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7645 (match_operand:BFP 2 "const0_operand" "")))
7646 (set (match_operand:BFP 0 "register_operand" "=f")
7647 (neg:BFP (match_dup 1)))]
7648 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7650 [(set_attr "op_type" "RRE")
7651 (set_attr "type" "fsimp<mode>")])
7653 ; lcxbr, lcdbr, lcebr
7654 (define_insn "*neg<mode>2_cconly"
7655 [(set (reg CC_REGNUM)
7656 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7657 (match_operand:BFP 2 "const0_operand" "")))
7658 (clobber (match_scratch:BFP 0 "=f"))]
7659 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7661 [(set_attr "op_type" "RRE")
7662 (set_attr "type" "fsimp<mode>")])
7665 (define_insn "*neg<mode>2_nocc"
7666 [(set (match_operand:FP 0 "register_operand" "=f")
7667 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7670 [(set_attr "op_type" "RRE")
7671 (set_attr "type" "fsimp<mode>")])
7673 ; lcxbr, lcdbr, lcebr
7674 (define_insn "*neg<mode>2"
7675 [(set (match_operand:BFP 0 "register_operand" "=f")
7676 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7677 (clobber (reg:CC CC_REGNUM))]
7680 [(set_attr "op_type" "RRE")
7681 (set_attr "type" "fsimp<mode>")])
7685 ;;- Absolute value instructions.
7689 ; abs(di|si)2 instruction pattern(s).
7692 (define_insn "*absdi2_sign_cc"
7693 [(set (reg CC_REGNUM)
7694 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7695 (match_operand:SI 1 "register_operand" "d") 0)
7696 (const_int 32)) (const_int 32)))
7698 (set (match_operand:DI 0 "register_operand" "=d")
7699 (abs:DI (sign_extend:DI (match_dup 1))))]
7700 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7702 [(set_attr "op_type" "RRE")
7703 (set_attr "z10prop" "z10_c")])
7705 (define_insn "*absdi2_sign"
7706 [(set (match_operand:DI 0 "register_operand" "=d")
7707 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7708 (clobber (reg:CC CC_REGNUM))]
7711 [(set_attr "op_type" "RRE")
7712 (set_attr "z10prop" "z10_c")])
7715 (define_insn "*abs<mode>2_cc"
7716 [(set (reg CC_REGNUM)
7717 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7719 (set (match_operand:GPR 0 "register_operand" "=d")
7720 (abs:GPR (match_dup 1)))]
7721 "s390_match_ccmode (insn, CCAmode)"
7723 [(set_attr "op_type" "RR<E>")
7724 (set_attr "z10prop" "z10_c")])
7727 (define_insn "*abs<mode>2_cconly"
7728 [(set (reg CC_REGNUM)
7729 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7731 (clobber (match_scratch:GPR 0 "=d"))]
7732 "s390_match_ccmode (insn, CCAmode)"
7734 [(set_attr "op_type" "RR<E>")
7735 (set_attr "z10prop" "z10_c")])
7738 (define_insn "abs<mode>2"
7739 [(set (match_operand:GPR 0 "register_operand" "=d")
7740 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7741 (clobber (reg:CC CC_REGNUM))]
7744 [(set_attr "op_type" "RR<E>")
7745 (set_attr "z10prop" "z10_c")])
7748 ; abs(df|sf)2 instruction pattern(s).
7751 (define_expand "abs<mode>2"
7753 [(set (match_operand:BFP 0 "register_operand" "=f")
7754 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7755 (clobber (reg:CC CC_REGNUM))])]
7759 ; lpxbr, lpdbr, lpebr
7760 (define_insn "*abs<mode>2_cc"
7761 [(set (reg CC_REGNUM)
7762 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7763 (match_operand:BFP 2 "const0_operand" "")))
7764 (set (match_operand:BFP 0 "register_operand" "=f")
7765 (abs:BFP (match_dup 1)))]
7766 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7768 [(set_attr "op_type" "RRE")
7769 (set_attr "type" "fsimp<mode>")])
7771 ; lpxbr, lpdbr, lpebr
7772 (define_insn "*abs<mode>2_cconly"
7773 [(set (reg CC_REGNUM)
7774 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7775 (match_operand:BFP 2 "const0_operand" "")))
7776 (clobber (match_scratch:BFP 0 "=f"))]
7777 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7779 [(set_attr "op_type" "RRE")
7780 (set_attr "type" "fsimp<mode>")])
7783 (define_insn "*abs<mode>2_nocc"
7784 [(set (match_operand:FP 0 "register_operand" "=f")
7785 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7788 [(set_attr "op_type" "RRE")
7789 (set_attr "type" "fsimp<mode>")])
7791 ; lpxbr, lpdbr, lpebr
7792 (define_insn "*abs<mode>2"
7793 [(set (match_operand:BFP 0 "register_operand" "=f")
7794 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7795 (clobber (reg:CC CC_REGNUM))]
7798 [(set_attr "op_type" "RRE")
7799 (set_attr "type" "fsimp<mode>")])
7803 ;;- Negated absolute value instructions
7810 (define_insn "*negabsdi2_sign_cc"
7811 [(set (reg CC_REGNUM)
7812 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7813 (match_operand:SI 1 "register_operand" "d") 0)
7814 (const_int 32)) (const_int 32))))
7816 (set (match_operand:DI 0 "register_operand" "=d")
7817 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7818 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7820 [(set_attr "op_type" "RRE")
7821 (set_attr "z10prop" "z10_c")])
7823 (define_insn "*negabsdi2_sign"
7824 [(set (match_operand:DI 0 "register_operand" "=d")
7825 (neg:DI (abs:DI (sign_extend:DI
7826 (match_operand:SI 1 "register_operand" "d")))))
7827 (clobber (reg:CC CC_REGNUM))]
7830 [(set_attr "op_type" "RRE")
7831 (set_attr "z10prop" "z10_c")])
7834 (define_insn "*negabs<mode>2_cc"
7835 [(set (reg CC_REGNUM)
7836 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7838 (set (match_operand:GPR 0 "register_operand" "=d")
7839 (neg:GPR (abs:GPR (match_dup 1))))]
7840 "s390_match_ccmode (insn, CCAmode)"
7842 [(set_attr "op_type" "RR<E>")
7843 (set_attr "z10prop" "z10_c")])
7846 (define_insn "*negabs<mode>2_cconly"
7847 [(set (reg CC_REGNUM)
7848 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7850 (clobber (match_scratch:GPR 0 "=d"))]
7851 "s390_match_ccmode (insn, CCAmode)"
7853 [(set_attr "op_type" "RR<E>")
7854 (set_attr "z10prop" "z10_c")])
7857 (define_insn "*negabs<mode>2"
7858 [(set (match_operand:GPR 0 "register_operand" "=d")
7859 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7860 (clobber (reg:CC CC_REGNUM))]
7863 [(set_attr "op_type" "RR<E>")
7864 (set_attr "z10prop" "z10_c")])
7870 ; lnxbr, lndbr, lnebr
7871 (define_insn "*negabs<mode>2_cc"
7872 [(set (reg CC_REGNUM)
7873 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7874 (match_operand:BFP 2 "const0_operand" "")))
7875 (set (match_operand:BFP 0 "register_operand" "=f")
7876 (neg:BFP (abs:BFP (match_dup 1))))]
7877 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7879 [(set_attr "op_type" "RRE")
7880 (set_attr "type" "fsimp<mode>")])
7882 ; lnxbr, lndbr, lnebr
7883 (define_insn "*negabs<mode>2_cconly"
7884 [(set (reg CC_REGNUM)
7885 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7886 (match_operand:BFP 2 "const0_operand" "")))
7887 (clobber (match_scratch:BFP 0 "=f"))]
7888 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7890 [(set_attr "op_type" "RRE")
7891 (set_attr "type" "fsimp<mode>")])
7894 (define_insn "*negabs<mode>2_nocc"
7895 [(set (match_operand:FP 0 "register_operand" "=f")
7896 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7899 [(set_attr "op_type" "RRE")
7900 (set_attr "type" "fsimp<mode>")])
7902 ; lnxbr, lndbr, lnebr
7903 (define_insn "*negabs<mode>2"
7904 [(set (match_operand:BFP 0 "register_operand" "=f")
7905 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7906 (clobber (reg:CC CC_REGNUM))]
7909 [(set_attr "op_type" "RRE")
7910 (set_attr "type" "fsimp<mode>")])
7913 ;;- Square root instructions.
7917 ; sqrt(df|sf)2 instruction pattern(s).
7920 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7921 (define_insn "sqrt<mode>2"
7922 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7923 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7928 [(set_attr "op_type" "RRE,RXE")
7929 (set_attr "type" "fsqrt<mode>")])
7933 ;;- One complement instructions.
7937 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7940 (define_expand "one_cmpl<mode>2"
7942 [(set (match_operand:INT 0 "register_operand" "")
7943 (xor:INT (match_operand:INT 1 "register_operand" "")
7945 (clobber (reg:CC CC_REGNUM))])]
7951 ;; Find leftmost bit instructions.
7954 (define_expand "clzdi2"
7955 [(set (match_operand:DI 0 "register_operand" "=d")
7956 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7957 "TARGET_EXTIMM && TARGET_ZARCH"
7959 rtx insn, clz_equal;
7960 rtx wide_reg = gen_reg_rtx (TImode);
7961 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7963 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7965 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7967 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7968 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7973 (define_insn "clztidi2"
7974 [(set (match_operand:TI 0 "register_operand" "=d")
7978 (xor:DI (match_operand:DI 1 "register_operand" "d")
7979 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7980 (subreg:SI (clz:DI (match_dup 1)) 4))))
7983 (zero_extend:TI (clz:DI (match_dup 1)))))
7984 (clobber (reg:CC CC_REGNUM))]
7985 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7986 == (unsigned HOST_WIDE_INT) 1 << 63
7987 && TARGET_EXTIMM && TARGET_ZARCH"
7989 [(set_attr "op_type" "RRE")])
7993 ;;- Rotate instructions.
7997 ; rotl(di|si)3 instruction pattern(s).
8001 (define_insn "rotl<mode>3"
8002 [(set (match_operand:GPR 0 "register_operand" "=d")
8003 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8004 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8007 [(set_attr "op_type" "RSE")
8008 (set_attr "atype" "reg")
8009 (set_attr "z10prop" "z10_super_E1")])
8012 (define_insn "*rotl<mode>3_and"
8013 [(set (match_operand:GPR 0 "register_operand" "=d")
8014 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8015 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8016 (match_operand:SI 3 "const_int_operand" "n"))))]
8017 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8019 [(set_attr "op_type" "RSE")
8020 (set_attr "atype" "reg")
8021 (set_attr "z10prop" "z10_super_E1")])
8025 ;;- Shift instructions.
8029 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8030 ; Left shifts and logical right shifts
8032 (define_expand "<shift><mode>3"
8033 [(set (match_operand:DSI 0 "register_operand" "")
8034 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8035 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
8040 (define_insn "*<shift>di3_31"
8041 [(set (match_operand:DI 0 "register_operand" "=d")
8042 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8043 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8046 [(set_attr "op_type" "RS")
8047 (set_attr "atype" "reg")
8048 (set_attr "z196prop" "z196_cracked")])
8050 ; sll, srl, sllg, srlg, sllk, srlk
8051 (define_insn "*<shift><mode>3"
8052 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8053 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8054 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
8057 s<lr>l<g>\t%0,<1>%Y2
8058 s<lr>l<gk>\t%0,%1,%Y2"
8059 [(set_attr "op_type" "RS<E>,RSY")
8060 (set_attr "atype" "reg,reg")
8061 (set_attr "cpu_facility" "*,z196")
8062 (set_attr "z10prop" "z10_super_E1,*")])
8065 (define_insn "*<shift>di3_31_and"
8066 [(set (match_operand:DI 0 "register_operand" "=d")
8067 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8068 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8069 (match_operand:SI 3 "const_int_operand" "n"))))]
8070 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8072 [(set_attr "op_type" "RS")
8073 (set_attr "atype" "reg")])
8075 ; sll, srl, sllg, srlg, sllk, srlk
8076 (define_insn "*<shift><mode>3_and"
8077 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8078 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8079 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8080 (match_operand:SI 3 "const_int_operand" "n,n"))))]
8081 "(INTVAL (operands[3]) & 63) == 63"
8083 s<lr>l<g>\t%0,<1>%Y2
8084 s<lr>l<gk>\t%0,%1,%Y2"
8085 [(set_attr "op_type" "RS<E>,RSY")
8086 (set_attr "atype" "reg,reg")
8087 (set_attr "cpu_facility" "*,z196")
8088 (set_attr "z10prop" "z10_super_E1,*")])
8091 ; ashr(di|si)3 instruction pattern(s).
8092 ; Arithmetic right shifts
8094 (define_expand "ashr<mode>3"
8096 [(set (match_operand:DSI 0 "register_operand" "")
8097 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8098 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
8099 (clobber (reg:CC CC_REGNUM))])]
8103 (define_insn "*ashrdi3_cc_31"
8104 [(set (reg CC_REGNUM)
8105 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8106 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8108 (set (match_operand:DI 0 "register_operand" "=d")
8109 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8110 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8112 [(set_attr "op_type" "RS")
8113 (set_attr "atype" "reg")])
8115 (define_insn "*ashrdi3_cconly_31"
8116 [(set (reg CC_REGNUM)
8117 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8118 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8120 (clobber (match_scratch:DI 0 "=d"))]
8121 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8123 [(set_attr "op_type" "RS")
8124 (set_attr "atype" "reg")])
8126 (define_insn "*ashrdi3_31"
8127 [(set (match_operand:DI 0 "register_operand" "=d")
8128 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8129 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
8130 (clobber (reg:CC CC_REGNUM))]
8133 [(set_attr "op_type" "RS")
8134 (set_attr "atype" "reg")])
8137 (define_insn "*ashr<mode>3_cc"
8138 [(set (reg CC_REGNUM)
8139 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8140 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8142 (set (match_operand:GPR 0 "register_operand" "=d,d")
8143 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
8144 "s390_match_ccmode(insn, CCSmode)"
8148 [(set_attr "op_type" "RS<E>,RSY")
8149 (set_attr "atype" "reg,reg")
8150 (set_attr "cpu_facility" "*,z196")
8151 (set_attr "z10prop" "z10_super_E1,*")])
8154 (define_insn "*ashr<mode>3_cconly"
8155 [(set (reg CC_REGNUM)
8156 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8157 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8159 (clobber (match_scratch:GPR 0 "=d,d"))]
8160 "s390_match_ccmode(insn, CCSmode)"
8164 [(set_attr "op_type" "RS<E>,RSY")
8165 (set_attr "atype" "reg,reg")
8166 (set_attr "cpu_facility" "*,z196")
8167 (set_attr "z10prop" "z10_super_E1,*")])
8170 (define_insn "*ashr<mode>3"
8171 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8172 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8173 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8174 (clobber (reg:CC CC_REGNUM))]
8179 [(set_attr "op_type" "RS<E>,RSY")
8180 (set_attr "atype" "reg,reg")
8181 (set_attr "cpu_facility" "*,z196")
8182 (set_attr "z10prop" "z10_super_E1,*")])
8185 ; shift pattern with implicit ANDs
8187 (define_insn "*ashrdi3_cc_31_and"
8188 [(set (reg CC_REGNUM)
8189 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8190 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8191 (match_operand:SI 3 "const_int_operand" "n")))
8193 (set (match_operand:DI 0 "register_operand" "=d")
8194 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8195 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8196 && (INTVAL (operands[3]) & 63) == 63"
8198 [(set_attr "op_type" "RS")
8199 (set_attr "atype" "reg")])
8201 (define_insn "*ashrdi3_cconly_31_and"
8202 [(set (reg CC_REGNUM)
8203 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8204 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8205 (match_operand:SI 3 "const_int_operand" "n")))
8207 (clobber (match_scratch:DI 0 "=d"))]
8208 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8209 && (INTVAL (operands[3]) & 63) == 63"
8211 [(set_attr "op_type" "RS")
8212 (set_attr "atype" "reg")])
8214 (define_insn "*ashrdi3_31_and"
8215 [(set (match_operand:DI 0 "register_operand" "=d")
8216 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8217 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8218 (match_operand:SI 3 "const_int_operand" "n"))))
8219 (clobber (reg:CC CC_REGNUM))]
8220 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8222 [(set_attr "op_type" "RS")
8223 (set_attr "atype" "reg")])
8226 (define_insn "*ashr<mode>3_cc_and"
8227 [(set (reg CC_REGNUM)
8228 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8229 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8230 (match_operand:SI 3 "const_int_operand" "n,n")))
8232 (set (match_operand:GPR 0 "register_operand" "=d,d")
8233 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8234 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8238 [(set_attr "op_type" "RS<E>,RSY")
8239 (set_attr "atype" "reg,reg")
8240 (set_attr "cpu_facility" "*,z196")
8241 (set_attr "z10prop" "z10_super_E1,*")])
8244 (define_insn "*ashr<mode>3_cconly_and"
8245 [(set (reg CC_REGNUM)
8246 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8247 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8248 (match_operand:SI 3 "const_int_operand" "n,n")))
8250 (clobber (match_scratch:GPR 0 "=d,d"))]
8251 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8255 [(set_attr "op_type" "RS<E>,RSY")
8256 (set_attr "atype" "reg,reg")
8257 (set_attr "cpu_facility" "*,z196")
8258 (set_attr "z10prop" "z10_super_E1,*")])
8261 (define_insn "*ashr<mode>3_and"
8262 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8263 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8264 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8265 (match_operand:SI 3 "const_int_operand" "n,n"))))
8266 (clobber (reg:CC CC_REGNUM))]
8267 "(INTVAL (operands[3]) & 63) == 63"
8271 [(set_attr "op_type" "RS<E>,RSY")
8272 (set_attr "atype" "reg,reg")
8273 (set_attr "cpu_facility" "*,z196")
8274 (set_attr "z10prop" "z10_super_E1,*")])
8278 ;; Branch instruction patterns.
8281 (define_expand "cbranch<mode>4"
8283 (if_then_else (match_operator 0 "comparison_operator"
8284 [(match_operand:GPR 1 "register_operand" "")
8285 (match_operand:GPR 2 "general_operand" "")])
8286 (label_ref (match_operand 3 "" ""))
8289 "s390_emit_jump (operands[3],
8290 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8293 (define_expand "cbranch<mode>4"
8295 (if_then_else (match_operator 0 "comparison_operator"
8296 [(match_operand:FP 1 "register_operand" "")
8297 (match_operand:FP 2 "general_operand" "")])
8298 (label_ref (match_operand 3 "" ""))
8301 "s390_emit_jump (operands[3],
8302 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8305 (define_expand "cbranchcc4"
8307 (if_then_else (match_operator 0 "s390_comparison"
8308 [(match_operand 1 "cc_reg_operand" "")
8309 (match_operand 2 "const_int_operand" "")])
8310 (label_ref (match_operand 3 "" ""))
8317 ;;- Conditional jump instructions.
8320 (define_insn "*cjump_64"
8323 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8324 (match_operand 2 "const_int_operand" "")])
8325 (label_ref (match_operand 0 "" ""))
8329 if (get_attr_length (insn) == 4)
8332 return "jg%C1\t%l0";
8334 [(set_attr "op_type" "RI")
8335 (set_attr "type" "branch")
8336 (set (attr "length")
8337 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8338 (const_int 4) (const_int 6)))])
8340 (define_insn "*cjump_31"
8343 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8344 (match_operand 2 "const_int_operand" "")])
8345 (label_ref (match_operand 0 "" ""))
8349 gcc_assert (get_attr_length (insn) == 4);
8352 [(set_attr "op_type" "RI")
8353 (set_attr "type" "branch")
8354 (set (attr "length")
8355 (if_then_else (not (match_test "flag_pic"))
8356 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8357 (const_int 4) (const_int 6))
8358 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8359 (const_int 4) (const_int 8))))])
8361 (define_insn "*cjump_long"
8364 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8365 (match_operand 0 "address_operand" "ZQZR")
8369 if (get_attr_op_type (insn) == OP_TYPE_RR)
8374 [(set (attr "op_type")
8375 (if_then_else (match_operand 0 "register_operand" "")
8376 (const_string "RR") (const_string "RX")))
8377 (set_attr "type" "branch")
8378 (set_attr "atype" "agen")])
8380 ;; A conditional return instruction.
8381 (define_insn "*c<code>"
8384 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8387 "s390_can_use_<code>_insn ()"
8389 [(set_attr "op_type" "RR")
8390 (set_attr "type" "jsr")
8391 (set_attr "atype" "agen")])
8394 ;;- Negated conditional jump instructions.
8397 (define_insn "*icjump_64"
8400 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8402 (label_ref (match_operand 0 "" ""))))]
8405 if (get_attr_length (insn) == 4)
8408 return "jg%D1\t%l0";
8410 [(set_attr "op_type" "RI")
8411 (set_attr "type" "branch")
8412 (set (attr "length")
8413 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8414 (const_int 4) (const_int 6)))])
8416 (define_insn "*icjump_31"
8419 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8421 (label_ref (match_operand 0 "" ""))))]
8424 gcc_assert (get_attr_length (insn) == 4);
8427 [(set_attr "op_type" "RI")
8428 (set_attr "type" "branch")
8429 (set (attr "length")
8430 (if_then_else (not (match_test "flag_pic"))
8431 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8432 (const_int 4) (const_int 6))
8433 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8434 (const_int 4) (const_int 8))))])
8436 (define_insn "*icjump_long"
8439 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8441 (match_operand 0 "address_operand" "ZQZR")))]
8444 if (get_attr_op_type (insn) == OP_TYPE_RR)
8449 [(set (attr "op_type")
8450 (if_then_else (match_operand 0 "register_operand" "")
8451 (const_string "RR") (const_string "RX")))
8452 (set_attr "type" "branch")
8453 (set_attr "atype" "agen")])
8456 ;;- Trap instructions.
8460 [(trap_if (const_int 1) (const_int 0))]
8463 [(set_attr "op_type" "RI")
8464 (set_attr "type" "branch")])
8466 (define_expand "ctrap<mode>4"
8467 [(trap_if (match_operator 0 "comparison_operator"
8468 [(match_operand:GPR 1 "register_operand" "")
8469 (match_operand:GPR 2 "general_operand" "")])
8470 (match_operand 3 "const0_operand" ""))]
8473 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8474 operands[1], operands[2]);
8475 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8479 (define_expand "ctrap<mode>4"
8480 [(trap_if (match_operator 0 "comparison_operator"
8481 [(match_operand:FP 1 "register_operand" "")
8482 (match_operand:FP 2 "general_operand" "")])
8483 (match_operand 3 "const0_operand" ""))]
8486 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8487 operands[1], operands[2]);
8488 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8492 (define_insn "condtrap"
8493 [(trap_if (match_operator 0 "s390_comparison"
8494 [(match_operand 1 "cc_reg_operand" "c")
8499 [(set_attr "op_type" "RI")
8500 (set_attr "type" "branch")])
8502 ; crt, cgrt, cit, cgit
8503 (define_insn "*cmp_and_trap_signed_int<mode>"
8504 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8505 [(match_operand:GPR 1 "register_operand" "d,d")
8506 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8512 [(set_attr "op_type" "RRF,RIE")
8513 (set_attr "type" "branch")
8514 (set_attr "z10prop" "z10_super_c,z10_super")])
8516 ; clrt, clgrt, clfit, clgit, clt, clgt
8517 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8518 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8519 [(match_operand:GPR 1 "register_operand" "d,d, d")
8520 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8527 [(set_attr "op_type" "RRF,RIE,RSY")
8528 (set_attr "type" "branch")
8529 (set_attr "z10prop" "z10_super_c,z10_super,*")
8530 (set_attr "cpu_facility" "z10,z10,zEC12")])
8533 (define_insn "*load_and_trap<mode>"
8534 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8537 (set (match_operand:GPR 1 "register_operand" "=d")
8541 [(set_attr "op_type" "RXY")])
8545 ;;- Loop instructions.
8547 ;; This is all complicated by the fact that since this is a jump insn
8548 ;; we must handle our own output reloads.
8552 ; This splitter will be matched by combine and has to add the 2 moves
8553 ; necessary to load the compare and the increment values into a
8554 ; register pair as needed by brxle.
8556 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8559 (match_operator 6 "s390_brx_operator"
8560 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8561 (match_operand:GPR 2 "general_operand" ""))
8562 (match_operand:GPR 3 "register_operand" "")])
8563 (label_ref (match_operand 0 "" ""))
8565 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8566 (plus:GPR (match_dup 1) (match_dup 2)))
8567 (clobber (match_scratch:GPR 5 ""))]
8570 "!reload_completed && !reload_in_progress"
8571 [(set (match_dup 7) (match_dup 2)) ; the increment
8572 (set (match_dup 8) (match_dup 3)) ; the comparison value
8573 (parallel [(set (pc)
8576 [(plus:GPR (match_dup 1) (match_dup 7))
8578 (label_ref (match_dup 0))
8581 (plus:GPR (match_dup 1) (match_dup 7)))
8582 (clobber (match_dup 5))
8583 (clobber (reg:CC CC_REGNUM))])]
8585 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8586 operands[7] = gen_lowpart (<GPR:MODE>mode,
8587 gen_highpart (word_mode, dreg));
8588 operands[8] = gen_lowpart (<GPR:MODE>mode,
8589 gen_lowpart (word_mode, dreg));
8594 (define_insn_and_split "*brxg_64bit"
8597 (match_operator 5 "s390_brx_operator"
8598 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8599 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8600 (subreg:DI (match_dup 2) 8)])
8601 (label_ref (match_operand 0 "" ""))
8603 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8604 (plus:DI (match_dup 1)
8605 (subreg:DI (match_dup 2) 0)))
8606 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8607 (clobber (reg:CC CC_REGNUM))]
8610 if (which_alternative != 0)
8612 else if (get_attr_length (insn) == 6)
8613 return "brx%E5g\t%1,%2,%l0";
8615 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8617 "&& reload_completed
8618 && (!REG_P (operands[3])
8619 || !rtx_equal_p (operands[1], operands[3]))"
8620 [(set (match_dup 4) (match_dup 1))
8621 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8622 (clobber (reg:CC CC_REGNUM))])
8623 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8624 (set (match_dup 3) (match_dup 4))
8625 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8626 (label_ref (match_dup 0))
8629 [(set_attr "op_type" "RIE")
8630 (set_attr "type" "branch")
8631 (set (attr "length")
8632 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8633 (const_int 6) (const_int 16)))])
8637 (define_insn_and_split "*brx_64bit"
8640 (match_operator 5 "s390_brx_operator"
8641 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8642 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8643 (subreg:SI (match_dup 2) 12)])
8644 (label_ref (match_operand 0 "" ""))
8646 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8647 (plus:SI (match_dup 1)
8648 (subreg:SI (match_dup 2) 4)))
8649 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8650 (clobber (reg:CC CC_REGNUM))]
8653 if (which_alternative != 0)
8655 else if (get_attr_length (insn) == 6)
8656 return "brx%C5\t%1,%2,%l0";
8658 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8660 "&& reload_completed
8661 && (!REG_P (operands[3])
8662 || !rtx_equal_p (operands[1], operands[3]))"
8663 [(set (match_dup 4) (match_dup 1))
8664 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8665 (clobber (reg:CC CC_REGNUM))])
8666 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8667 (set (match_dup 3) (match_dup 4))
8668 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8669 (label_ref (match_dup 0))
8672 [(set_attr "op_type" "RSI")
8673 (set_attr "type" "branch")
8674 (set (attr "length")
8675 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8676 (const_int 6) (const_int 14)))])
8680 (define_insn_and_split "*brx_31bit"
8683 (match_operator 5 "s390_brx_operator"
8684 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8685 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8686 (subreg:SI (match_dup 2) 4)])
8687 (label_ref (match_operand 0 "" ""))
8689 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8690 (plus:SI (match_dup 1)
8691 (subreg:SI (match_dup 2) 0)))
8692 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8693 (clobber (reg:CC CC_REGNUM))]
8694 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8696 if (which_alternative != 0)
8698 else if (get_attr_length (insn) == 6)
8699 return "brx%C5\t%1,%2,%l0";
8701 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8703 "&& reload_completed
8704 && (!REG_P (operands[3])
8705 || !rtx_equal_p (operands[1], operands[3]))"
8706 [(set (match_dup 4) (match_dup 1))
8707 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8708 (clobber (reg:CC CC_REGNUM))])
8709 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8710 (set (match_dup 3) (match_dup 4))
8711 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8712 (label_ref (match_dup 0))
8715 [(set_attr "op_type" "RSI")
8716 (set_attr "type" "branch")
8717 (set (attr "length")
8718 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8719 (const_int 6) (const_int 14)))])
8724 (define_expand "doloop_end"
8725 [(use (match_operand 0 "" "")) ; loop pseudo
8726 (use (match_operand 1 "" ""))] ; label
8729 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8730 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8731 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8732 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8733 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8734 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8741 (define_insn_and_split "doloop_si64"
8744 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8746 (label_ref (match_operand 0 "" ""))
8748 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8749 (plus:SI (match_dup 1) (const_int -1)))
8750 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8751 (clobber (reg:CC CC_REGNUM))]
8754 if (which_alternative != 0)
8756 else if (get_attr_length (insn) == 4)
8757 return "brct\t%1,%l0";
8759 return "ahi\t%1,-1\;jgne\t%l0";
8761 "&& reload_completed
8762 && (! REG_P (operands[2])
8763 || ! rtx_equal_p (operands[1], operands[2]))"
8764 [(set (match_dup 3) (match_dup 1))
8765 (parallel [(set (reg:CCAN CC_REGNUM)
8766 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8768 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8769 (set (match_dup 2) (match_dup 3))
8770 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8771 (label_ref (match_dup 0))
8774 [(set_attr "op_type" "RI")
8775 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8776 ; hurt us in the (rare) case of ahi.
8777 (set_attr "z10prop" "z10_super_E1")
8778 (set_attr "type" "branch")
8779 (set (attr "length")
8780 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8781 (const_int 4) (const_int 10)))])
8783 (define_insn_and_split "doloop_si31"
8786 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8788 (label_ref (match_operand 0 "" ""))
8790 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8791 (plus:SI (match_dup 1) (const_int -1)))
8792 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8793 (clobber (reg:CC CC_REGNUM))]
8796 if (which_alternative != 0)
8798 else if (get_attr_length (insn) == 4)
8799 return "brct\t%1,%l0";
8803 "&& reload_completed
8804 && (! REG_P (operands[2])
8805 || ! rtx_equal_p (operands[1], operands[2]))"
8806 [(set (match_dup 3) (match_dup 1))
8807 (parallel [(set (reg:CCAN CC_REGNUM)
8808 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8810 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8811 (set (match_dup 2) (match_dup 3))
8812 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8813 (label_ref (match_dup 0))
8816 [(set_attr "op_type" "RI")
8817 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8818 ; hurt us in the (rare) case of ahi.
8819 (set_attr "z10prop" "z10_super_E1")
8820 (set_attr "type" "branch")
8821 (set (attr "length")
8822 (if_then_else (not (match_test "flag_pic"))
8823 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8824 (const_int 4) (const_int 6))
8825 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8826 (const_int 4) (const_int 8))))])
8828 (define_insn "*doloop_si_long"
8831 (ne (match_operand:SI 1 "register_operand" "d")
8833 (match_operand 0 "address_operand" "ZQZR")
8835 (set (match_operand:SI 2 "register_operand" "=1")
8836 (plus:SI (match_dup 1) (const_int -1)))
8837 (clobber (match_scratch:SI 3 "=X"))
8838 (clobber (reg:CC CC_REGNUM))]
8841 if (get_attr_op_type (insn) == OP_TYPE_RR)
8842 return "bctr\t%1,%0";
8844 return "bct\t%1,%a0";
8846 [(set (attr "op_type")
8847 (if_then_else (match_operand 0 "register_operand" "")
8848 (const_string "RR") (const_string "RX")))
8849 (set_attr "type" "branch")
8850 (set_attr "atype" "agen")
8851 (set_attr "z10prop" "z10_c")
8852 (set_attr "z196prop" "z196_cracked")])
8854 (define_insn_and_split "doloop_di"
8857 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8859 (label_ref (match_operand 0 "" ""))
8861 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8862 (plus:DI (match_dup 1) (const_int -1)))
8863 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8864 (clobber (reg:CC CC_REGNUM))]
8867 if (which_alternative != 0)
8869 else if (get_attr_length (insn) == 4)
8870 return "brctg\t%1,%l0";
8872 return "aghi\t%1,-1\;jgne\t%l0";
8874 "&& reload_completed
8875 && (! REG_P (operands[2])
8876 || ! rtx_equal_p (operands[1], operands[2]))"
8877 [(set (match_dup 3) (match_dup 1))
8878 (parallel [(set (reg:CCAN CC_REGNUM)
8879 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8881 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8882 (set (match_dup 2) (match_dup 3))
8883 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8884 (label_ref (match_dup 0))
8887 [(set_attr "op_type" "RI")
8888 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8889 ; hurt us in the (rare) case of ahi.
8890 (set_attr "z10prop" "z10_super_E1")
8891 (set_attr "type" "branch")
8892 (set (attr "length")
8893 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8894 (const_int 4) (const_int 10)))])
8897 ;;- Unconditional jump instructions.
8901 ; jump instruction pattern(s).
8904 (define_expand "jump"
8905 [(match_operand 0 "" "")]
8907 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8909 (define_insn "*jump64"
8910 [(set (pc) (label_ref (match_operand 0 "" "")))]
8913 if (get_attr_length (insn) == 4)
8918 [(set_attr "op_type" "RI")
8919 (set_attr "type" "branch")
8920 (set (attr "length")
8921 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8922 (const_int 4) (const_int 6)))])
8924 (define_insn "*jump31"
8925 [(set (pc) (label_ref (match_operand 0 "" "")))]
8928 gcc_assert (get_attr_length (insn) == 4);
8931 [(set_attr "op_type" "RI")
8932 (set_attr "type" "branch")
8933 (set (attr "length")
8934 (if_then_else (not (match_test "flag_pic"))
8935 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8936 (const_int 4) (const_int 6))
8937 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8938 (const_int 4) (const_int 8))))])
8941 ; indirect-jump instruction pattern(s).
8944 (define_insn "indirect_jump"
8945 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8948 if (get_attr_op_type (insn) == OP_TYPE_RR)
8953 [(set (attr "op_type")
8954 (if_then_else (match_operand 0 "register_operand" "")
8955 (const_string "RR") (const_string "RX")))
8956 (set_attr "type" "branch")
8957 (set_attr "atype" "agen")])
8960 ; casesi instruction pattern(s).
8963 (define_insn "casesi_jump"
8964 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8965 (use (label_ref (match_operand 1 "" "")))]
8968 if (get_attr_op_type (insn) == OP_TYPE_RR)
8973 [(set (attr "op_type")
8974 (if_then_else (match_operand 0 "register_operand" "")
8975 (const_string "RR") (const_string "RX")))
8976 (set_attr "type" "branch")
8977 (set_attr "atype" "agen")])
8979 (define_expand "casesi"
8980 [(match_operand:SI 0 "general_operand" "")
8981 (match_operand:SI 1 "general_operand" "")
8982 (match_operand:SI 2 "general_operand" "")
8983 (label_ref (match_operand 3 "" ""))
8984 (label_ref (match_operand 4 "" ""))]
8987 rtx index = gen_reg_rtx (SImode);
8988 rtx base = gen_reg_rtx (Pmode);
8989 rtx target = gen_reg_rtx (Pmode);
8991 emit_move_insn (index, operands[0]);
8992 emit_insn (gen_subsi3 (index, index, operands[1]));
8993 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8996 if (Pmode != SImode)
8997 index = convert_to_mode (Pmode, index, 1);
8998 if (GET_CODE (index) != REG)
8999 index = copy_to_mode_reg (Pmode, index);
9002 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9004 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9006 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9008 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9009 emit_move_insn (target, index);
9012 target = gen_rtx_PLUS (Pmode, base, target);
9013 emit_jump_insn (gen_casesi_jump (target, operands[3]));
9020 ;;- Jump to subroutine.
9025 ; untyped call instruction pattern(s).
9028 ;; Call subroutine returning any type.
9029 (define_expand "untyped_call"
9030 [(parallel [(call (match_operand 0 "" "")
9032 (match_operand 1 "" "")
9033 (match_operand 2 "" "")])]
9038 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9040 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9042 rtx set = XVECEXP (operands[2], 0, i);
9043 emit_move_insn (SET_DEST (set), SET_SRC (set));
9046 /* The optimizer does not know that the call sets the function value
9047 registers we stored in the result block. We avoid problems by
9048 claiming that all hard registers are used and clobbered at this
9050 emit_insn (gen_blockage ());
9055 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9056 ;; all of memory. This blocks insns from being moved across this point.
9058 (define_insn "blockage"
9059 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9062 [(set_attr "type" "none")
9063 (set_attr "length" "0")])
9069 (define_expand "sibcall"
9070 [(call (match_operand 0 "" "")
9071 (match_operand 1 "" ""))]
9074 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9078 (define_insn "*sibcall_br"
9079 [(call (mem:QI (reg SIBCALL_REGNUM))
9080 (match_operand 0 "const_int_operand" "n"))]
9081 "SIBLING_CALL_P (insn)
9082 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9084 [(set_attr "op_type" "RR")
9085 (set_attr "type" "branch")
9086 (set_attr "atype" "agen")])
9088 (define_insn "*sibcall_brc"
9089 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9090 (match_operand 1 "const_int_operand" "n"))]
9091 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9093 [(set_attr "op_type" "RI")
9094 (set_attr "type" "branch")])
9096 (define_insn "*sibcall_brcl"
9097 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9098 (match_operand 1 "const_int_operand" "n"))]
9099 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9101 [(set_attr "op_type" "RIL")
9102 (set_attr "type" "branch")])
9105 ; sibcall_value patterns
9108 (define_expand "sibcall_value"
9109 [(set (match_operand 0 "" "")
9110 (call (match_operand 1 "" "")
9111 (match_operand 2 "" "")))]
9114 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9118 (define_insn "*sibcall_value_br"
9119 [(set (match_operand 0 "" "")
9120 (call (mem:QI (reg SIBCALL_REGNUM))
9121 (match_operand 1 "const_int_operand" "n")))]
9122 "SIBLING_CALL_P (insn)
9123 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9125 [(set_attr "op_type" "RR")
9126 (set_attr "type" "branch")
9127 (set_attr "atype" "agen")])
9129 (define_insn "*sibcall_value_brc"
9130 [(set (match_operand 0 "" "")
9131 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9132 (match_operand 2 "const_int_operand" "n")))]
9133 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9135 [(set_attr "op_type" "RI")
9136 (set_attr "type" "branch")])
9138 (define_insn "*sibcall_value_brcl"
9139 [(set (match_operand 0 "" "")
9140 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9141 (match_operand 2 "const_int_operand" "n")))]
9142 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9144 [(set_attr "op_type" "RIL")
9145 (set_attr "type" "branch")])
9149 ; call instruction pattern(s).
9152 (define_expand "call"
9153 [(call (match_operand 0 "" "")
9154 (match_operand 1 "" ""))
9155 (use (match_operand 2 "" ""))]
9158 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9159 gen_rtx_REG (Pmode, RETURN_REGNUM));
9163 (define_insn "*bras"
9164 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9165 (match_operand 1 "const_int_operand" "n"))
9166 (clobber (match_operand 2 "register_operand" "=r"))]
9167 "!SIBLING_CALL_P (insn)
9168 && TARGET_SMALL_EXEC
9169 && GET_MODE (operands[2]) == Pmode"
9171 [(set_attr "op_type" "RI")
9172 (set_attr "type" "jsr")
9173 (set_attr "z196prop" "z196_cracked")])
9175 (define_insn "*brasl"
9176 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9177 (match_operand 1 "const_int_operand" "n"))
9178 (clobber (match_operand 2 "register_operand" "=r"))]
9179 "!SIBLING_CALL_P (insn)
9181 && GET_MODE (operands[2]) == Pmode"
9183 [(set_attr "op_type" "RIL")
9184 (set_attr "type" "jsr")
9185 (set_attr "z196prop" "z196_cracked")])
9187 (define_insn "*basr"
9188 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9189 (match_operand 1 "const_int_operand" "n"))
9190 (clobber (match_operand 2 "register_operand" "=r"))]
9191 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9193 if (get_attr_op_type (insn) == OP_TYPE_RR)
9194 return "basr\t%2,%0";
9196 return "bas\t%2,%a0";
9198 [(set (attr "op_type")
9199 (if_then_else (match_operand 0 "register_operand" "")
9200 (const_string "RR") (const_string "RX")))
9201 (set_attr "type" "jsr")
9202 (set_attr "atype" "agen")
9203 (set_attr "z196prop" "z196_cracked")])
9206 ; call_value instruction pattern(s).
9209 (define_expand "call_value"
9210 [(set (match_operand 0 "" "")
9211 (call (match_operand 1 "" "")
9212 (match_operand 2 "" "")))
9213 (use (match_operand 3 "" ""))]
9216 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9217 gen_rtx_REG (Pmode, RETURN_REGNUM));
9221 (define_insn "*bras_r"
9222 [(set (match_operand 0 "" "")
9223 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9224 (match_operand:SI 2 "const_int_operand" "n")))
9225 (clobber (match_operand 3 "register_operand" "=r"))]
9226 "!SIBLING_CALL_P (insn)
9227 && TARGET_SMALL_EXEC
9228 && GET_MODE (operands[3]) == Pmode"
9230 [(set_attr "op_type" "RI")
9231 (set_attr "type" "jsr")
9232 (set_attr "z196prop" "z196_cracked")])
9234 (define_insn "*brasl_r"
9235 [(set (match_operand 0 "" "")
9236 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9237 (match_operand 2 "const_int_operand" "n")))
9238 (clobber (match_operand 3 "register_operand" "=r"))]
9239 "!SIBLING_CALL_P (insn)
9241 && GET_MODE (operands[3]) == Pmode"
9243 [(set_attr "op_type" "RIL")
9244 (set_attr "type" "jsr")
9245 (set_attr "z196prop" "z196_cracked")])
9247 (define_insn "*basr_r"
9248 [(set (match_operand 0 "" "")
9249 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9250 (match_operand 2 "const_int_operand" "n")))
9251 (clobber (match_operand 3 "register_operand" "=r"))]
9252 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9254 if (get_attr_op_type (insn) == OP_TYPE_RR)
9255 return "basr\t%3,%1";
9257 return "bas\t%3,%a1";
9259 [(set (attr "op_type")
9260 (if_then_else (match_operand 1 "register_operand" "")
9261 (const_string "RR") (const_string "RX")))
9262 (set_attr "type" "jsr")
9263 (set_attr "atype" "agen")
9264 (set_attr "z196prop" "z196_cracked")])
9267 ;;- Thread-local storage support.
9270 (define_expand "get_thread_pointer<mode>"
9271 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9275 (define_expand "set_thread_pointer<mode>"
9276 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9277 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9281 (define_insn "*set_tp"
9282 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9285 [(set_attr "type" "none")
9286 (set_attr "length" "0")])
9288 (define_insn "*tls_load_64"
9289 [(set (match_operand:DI 0 "register_operand" "=d")
9290 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9291 (match_operand:DI 2 "" "")]
9295 [(set_attr "op_type" "RXE")
9296 (set_attr "z10prop" "z10_fwd_A3")])
9298 (define_insn "*tls_load_31"
9299 [(set (match_operand:SI 0 "register_operand" "=d,d")
9300 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9301 (match_operand:SI 2 "" "")]
9307 [(set_attr "op_type" "RX,RXY")
9308 (set_attr "type" "load")
9309 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9311 (define_insn "*bras_tls"
9312 [(set (match_operand 0 "" "")
9313 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9314 (match_operand 2 "const_int_operand" "n")))
9315 (clobber (match_operand 3 "register_operand" "=r"))
9316 (use (match_operand 4 "" ""))]
9317 "!SIBLING_CALL_P (insn)
9318 && TARGET_SMALL_EXEC
9319 && GET_MODE (operands[3]) == Pmode"
9321 [(set_attr "op_type" "RI")
9322 (set_attr "type" "jsr")
9323 (set_attr "z196prop" "z196_cracked")])
9325 (define_insn "*brasl_tls"
9326 [(set (match_operand 0 "" "")
9327 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9328 (match_operand 2 "const_int_operand" "n")))
9329 (clobber (match_operand 3 "register_operand" "=r"))
9330 (use (match_operand 4 "" ""))]
9331 "!SIBLING_CALL_P (insn)
9333 && GET_MODE (operands[3]) == Pmode"
9335 [(set_attr "op_type" "RIL")
9336 (set_attr "type" "jsr")
9337 (set_attr "z196prop" "z196_cracked")])
9339 (define_insn "*basr_tls"
9340 [(set (match_operand 0 "" "")
9341 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9342 (match_operand 2 "const_int_operand" "n")))
9343 (clobber (match_operand 3 "register_operand" "=r"))
9344 (use (match_operand 4 "" ""))]
9345 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9347 if (get_attr_op_type (insn) == OP_TYPE_RR)
9348 return "basr\t%3,%1%J4";
9350 return "bas\t%3,%a1%J4";
9352 [(set (attr "op_type")
9353 (if_then_else (match_operand 1 "register_operand" "")
9354 (const_string "RR") (const_string "RX")))
9355 (set_attr "type" "jsr")
9356 (set_attr "atype" "agen")
9357 (set_attr "z196prop" "z196_cracked")])
9360 ;;- Atomic operations
9364 ; memory barrier patterns.
9367 (define_expand "mem_signal_fence"
9368 [(match_operand:SI 0 "const_int_operand")] ;; model
9371 /* The s390 memory model is strong enough not to require any
9372 barrier in order to synchronize a thread with itself. */
9376 (define_expand "mem_thread_fence"
9377 [(match_operand:SI 0 "const_int_operand")] ;; model
9380 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9381 enough not to require barriers of any kind. */
9382 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9384 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9385 MEM_VOLATILE_P (mem) = 1;
9386 emit_insn (gen_mem_thread_fence_1 (mem));
9391 ; Although bcr is superscalar on Z10, this variant will never
9392 ; become part of an execution group.
9393 ; With z196 we can make use of the fast-BCR-serialization facility.
9394 ; This allows for a slightly faster sync which is sufficient for our
9396 (define_insn "mem_thread_fence_1"
9397 [(set (match_operand:BLK 0 "" "")
9398 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9406 [(set_attr "op_type" "RR")
9407 (set_attr "mnemonic" "bcr_flush")
9408 (set_attr "z196prop" "z196_alone")])
9411 ; atomic load/store operations
9414 ; Atomic loads need not examine the memory model at all.
9415 (define_expand "atomic_load<mode>"
9416 [(match_operand:DINT 0 "register_operand") ;; output
9417 (match_operand:DINT 1 "memory_operand") ;; memory
9418 (match_operand:SI 2 "const_int_operand")] ;; model
9421 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9424 if (<MODE>mode == TImode)
9425 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9426 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9427 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9429 emit_move_insn (operands[0], operands[1]);
9433 ; Different from movdi_31 in that we want no splitters.
9434 (define_insn "atomic_loaddi_1"
9435 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9436 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9444 [(set_attr "op_type" "RS,RSY,RS,RSY")
9445 (set_attr "type" "lm,lm,floaddf,floaddf")])
9447 (define_insn "atomic_loadti_1"
9448 [(set (match_operand:TI 0 "register_operand" "=r")
9449 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9453 [(set_attr "op_type" "RXY")
9454 (set_attr "type" "other")])
9456 ; Atomic stores must(?) enforce sequential consistency.
9457 (define_expand "atomic_store<mode>"
9458 [(match_operand:DINT 0 "memory_operand") ;; memory
9459 (match_operand:DINT 1 "register_operand") ;; input
9460 (match_operand:SI 2 "const_int_operand")] ;; model
9463 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9465 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9468 if (<MODE>mode == TImode)
9469 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9470 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9471 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9473 emit_move_insn (operands[0], operands[1]);
9474 if (is_mm_seq_cst (model))
9475 emit_insn (gen_mem_thread_fence (operands[2]));
9479 ; Different from movdi_31 in that we want no splitters.
9480 (define_insn "atomic_storedi_1"
9481 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9482 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9490 [(set_attr "op_type" "RS,RSY,RS,RSY")
9491 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9493 (define_insn "atomic_storeti_1"
9494 [(set (match_operand:TI 0 "memory_operand" "=RT")
9495 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9499 [(set_attr "op_type" "RXY")
9500 (set_attr "type" "other")])
9503 ; compare and swap patterns.
9506 (define_expand "atomic_compare_and_swap<mode>"
9507 [(match_operand:SI 0 "register_operand") ;; bool success output
9508 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9509 (match_operand:DGPR 2 "memory_operand") ;; memory
9510 (match_operand:DGPR 3 "register_operand") ;; expected intput
9511 (match_operand:DGPR 4 "register_operand") ;; newval intput
9512 (match_operand:SI 5 "const_int_operand") ;; is_weak
9513 (match_operand:SI 6 "const_int_operand") ;; success model
9514 (match_operand:SI 7 "const_int_operand")] ;; failure model
9517 rtx cc, cmp, output = operands[1];
9519 if (!register_operand (output, <MODE>mode))
9520 output = gen_reg_rtx (<MODE>mode);
9522 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9525 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9526 (output, operands[2], operands[3], operands[4]));
9528 /* We deliberately accept non-register operands in the predicate
9529 to ensure the write back to the output operand happens *before*
9530 the store-flags code below. This makes it easier for combine
9531 to merge the store-flags code with a potential test-and-branch
9532 pattern following (immediately!) afterwards. */
9533 if (output != operands[1])
9534 emit_move_insn (operands[1], output);
9536 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9537 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9538 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9542 (define_expand "atomic_compare_and_swap<mode>"
9543 [(match_operand:SI 0 "register_operand") ;; bool success output
9544 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9545 (match_operand:HQI 2 "memory_operand") ;; memory
9546 (match_operand:HQI 3 "general_operand") ;; expected intput
9547 (match_operand:HQI 4 "general_operand") ;; newval intput
9548 (match_operand:SI 5 "const_int_operand") ;; is_weak
9549 (match_operand:SI 6 "const_int_operand") ;; success model
9550 (match_operand:SI 7 "const_int_operand")] ;; failure model
9553 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9554 operands[3], operands[4], INTVAL (operands[5]));
9558 (define_expand "atomic_compare_and_swap<mode>_internal"
9560 [(set (match_operand:DGPR 0 "register_operand")
9561 (match_operand:DGPR 1 "memory_operand"))
9563 (unspec_volatile:DGPR
9565 (match_operand:DGPR 2 "register_operand")
9566 (match_operand:DGPR 3 "register_operand")]
9568 (set (reg:CCZ1 CC_REGNUM)
9569 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9573 (define_insn "*atomic_compare_and_swap<mode>_1"
9574 [(set (match_operand:TDI 0 "register_operand" "=r")
9575 (match_operand:TDI 1 "memory_operand" "+QS"))
9577 (unspec_volatile:TDI
9579 (match_operand:TDI 2 "register_operand" "0")
9580 (match_operand:TDI 3 "register_operand" "r")]
9582 (set (reg:CCZ1 CC_REGNUM)
9583 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9585 "c<td>sg\t%0,%3,%S1"
9586 [(set_attr "op_type" "RSY")
9587 (set_attr "type" "sem")])
9590 (define_insn "*atomic_compare_and_swapdi_2"
9591 [(set (match_operand:DI 0 "register_operand" "=r,r")
9592 (match_operand:DI 1 "memory_operand" "+Q,S"))
9596 (match_operand:DI 2 "register_operand" "0,0")
9597 (match_operand:DI 3 "register_operand" "r,r")]
9599 (set (reg:CCZ1 CC_REGNUM)
9600 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9605 [(set_attr "op_type" "RS,RSY")
9606 (set_attr "type" "sem")])
9609 (define_insn "*atomic_compare_and_swapsi_3"
9610 [(set (match_operand:SI 0 "register_operand" "=r,r")
9611 (match_operand:SI 1 "memory_operand" "+Q,S"))
9615 (match_operand:SI 2 "register_operand" "0,0")
9616 (match_operand:SI 3 "register_operand" "r,r")]
9618 (set (reg:CCZ1 CC_REGNUM)
9619 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9624 [(set_attr "op_type" "RS,RSY")
9625 (set_attr "type" "sem")])
9628 ; Other atomic instruction patterns.
9631 ; z196 load and add, xor, or and and instructions
9633 (define_expand "atomic_fetch_<atomic><mode>"
9634 [(match_operand:GPR 0 "register_operand") ;; val out
9636 (match_operand:GPR 1 "memory_operand") ;; memory
9637 (match_operand:GPR 2 "register_operand")) ;; val in
9638 (match_operand:SI 3 "const_int_operand")] ;; model
9641 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9644 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9645 (operands[0], operands[1], operands[2]));
9649 ; lan, lang, lao, laog, lax, laxg, laa, laag
9650 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9651 [(set (match_operand:GPR 0 "register_operand" "=d")
9652 (match_operand:GPR 1 "memory_operand" "+QS"))
9654 (unspec_volatile:GPR
9655 [(ATOMIC_Z196:GPR (match_dup 1)
9656 (match_operand:GPR 2 "general_operand" "d"))]
9658 (clobber (reg:CC CC_REGNUM))]
9660 "la<noxa><g>\t%0,%2,%1"
9661 [(set_attr "op_type" "RSY")
9662 (set_attr "type" "sem")])
9664 ;; For SImode and larger, the optabs.c code will do just fine in
9665 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9666 ;; better by expanding our own loop.
9668 (define_expand "atomic_<atomic><mode>"
9670 (match_operand:HQI 0 "memory_operand") ;; memory
9671 (match_operand:HQI 1 "general_operand")) ;; val in
9672 (match_operand:SI 2 "const_int_operand")] ;; model
9675 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9676 operands[1], false);
9680 (define_expand "atomic_fetch_<atomic><mode>"
9681 [(match_operand:HQI 0 "register_operand") ;; val out
9683 (match_operand:HQI 1 "memory_operand") ;; memory
9684 (match_operand:HQI 2 "general_operand")) ;; val in
9685 (match_operand:SI 3 "const_int_operand")] ;; model
9688 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9689 operands[2], false);
9693 (define_expand "atomic_<atomic>_fetch<mode>"
9694 [(match_operand:HQI 0 "register_operand") ;; val out
9696 (match_operand:HQI 1 "memory_operand") ;; memory
9697 (match_operand:HQI 2 "general_operand")) ;; val in
9698 (match_operand:SI 3 "const_int_operand")] ;; model
9701 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9706 (define_expand "atomic_exchange<mode>"
9707 [(match_operand:HQI 0 "register_operand") ;; val out
9708 (match_operand:HQI 1 "memory_operand") ;; memory
9709 (match_operand:HQI 2 "general_operand") ;; val in
9710 (match_operand:SI 3 "const_int_operand")] ;; model
9713 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9714 operands[2], false);
9719 ;;- Miscellaneous instructions.
9723 ; allocate stack instruction pattern(s).
9726 (define_expand "allocate_stack"
9727 [(match_operand 0 "general_operand" "")
9728 (match_operand 1 "general_operand" "")]
9731 rtx temp = gen_reg_rtx (Pmode);
9733 emit_move_insn (temp, s390_back_chain_rtx ());
9734 anti_adjust_stack (operands[1]);
9735 emit_move_insn (s390_back_chain_rtx (), temp);
9737 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9743 ; setjmp instruction pattern.
9746 (define_expand "builtin_setjmp_receiver"
9747 [(match_operand 0 "" "")]
9750 emit_insn (s390_load_got ());
9751 emit_use (pic_offset_table_rtx);
9755 ;; These patterns say how to save and restore the stack pointer. We need not
9756 ;; save the stack pointer at function level since we are careful to
9757 ;; preserve the backchain. At block level, we have to restore the backchain
9758 ;; when we restore the stack pointer.
9760 ;; For nonlocal gotos, we must save both the stack pointer and its
9761 ;; backchain and restore both. Note that in the nonlocal case, the
9762 ;; save area is a memory location.
9764 (define_expand "save_stack_function"
9765 [(match_operand 0 "general_operand" "")
9766 (match_operand 1 "general_operand" "")]
9770 (define_expand "restore_stack_function"
9771 [(match_operand 0 "general_operand" "")
9772 (match_operand 1 "general_operand" "")]
9776 (define_expand "restore_stack_block"
9777 [(match_operand 0 "register_operand" "")
9778 (match_operand 1 "register_operand" "")]
9781 rtx temp = gen_reg_rtx (Pmode);
9783 emit_move_insn (temp, s390_back_chain_rtx ());
9784 emit_move_insn (operands[0], operands[1]);
9785 emit_move_insn (s390_back_chain_rtx (), temp);
9790 (define_expand "save_stack_nonlocal"
9791 [(match_operand 0 "memory_operand" "")
9792 (match_operand 1 "register_operand" "")]
9795 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9797 /* Copy the backchain to the first word, sp to the second and the
9798 literal pool base to the third. */
9800 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9801 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9802 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9804 if (TARGET_BACKCHAIN)
9805 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9807 emit_move_insn (save_sp, operands[1]);
9808 emit_move_insn (save_bp, base);
9813 (define_expand "restore_stack_nonlocal"
9814 [(match_operand 0 "register_operand" "")
9815 (match_operand 1 "memory_operand" "")]
9818 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9819 rtx temp = NULL_RTX;
9821 /* Restore the backchain from the first word, sp from the second and the
9822 literal pool base from the third. */
9824 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9825 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9826 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9828 if (TARGET_BACKCHAIN)
9829 temp = force_reg (Pmode, save_bc);
9831 emit_move_insn (base, save_bp);
9832 emit_move_insn (operands[0], save_sp);
9835 emit_move_insn (s390_back_chain_rtx (), temp);
9841 (define_expand "exception_receiver"
9845 s390_set_has_landing_pad_p (true);
9850 ; nop instruction pattern(s).
9857 [(set_attr "op_type" "RR")
9858 (set_attr "z10prop" "z10_fr_E1")])
9864 [(set_attr "op_type" "RR")])
9866 ;;- Undeletable nops (used for hotpatching)
9868 (define_insn "nop_2_byte"
9869 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
9872 [(set_attr "op_type" "RR")])
9874 (define_insn "nop_4_byte"
9875 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
9878 [(set_attr "op_type" "RX")])
9880 (define_insn "nop_6_byte"
9881 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
9884 [(set_attr "op_type" "RIL")])
9888 ; Special literal pool access instruction pattern(s).
9891 (define_insn "*pool_entry"
9892 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9893 UNSPECV_POOL_ENTRY)]
9896 machine_mode mode = GET_MODE (PATTERN (insn));
9897 unsigned int align = GET_MODE_BITSIZE (mode);
9898 s390_output_pool_entry (operands[0], mode, align);
9901 [(set (attr "length")
9902 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9904 (define_insn "pool_align"
9905 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9906 UNSPECV_POOL_ALIGN)]
9909 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9911 (define_insn "pool_section_start"
9912 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9915 [(set_attr "length" "0")])
9917 (define_insn "pool_section_end"
9918 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9921 [(set_attr "length" "0")])
9923 (define_insn "main_base_31_small"
9924 [(set (match_operand 0 "register_operand" "=a")
9925 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9926 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9928 [(set_attr "op_type" "RR")
9929 (set_attr "type" "la")
9930 (set_attr "z196prop" "z196_cracked")])
9932 (define_insn "main_base_31_large"
9933 [(set (match_operand 0 "register_operand" "=a")
9934 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9935 (set (pc) (label_ref (match_operand 2 "" "")))]
9936 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9938 [(set_attr "op_type" "RI")
9939 (set_attr "z196prop" "z196_cracked")])
9941 (define_insn "main_base_64"
9942 [(set (match_operand 0 "register_operand" "=a")
9943 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9944 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9946 [(set_attr "op_type" "RIL")
9947 (set_attr "type" "larl")
9948 (set_attr "z10prop" "z10_fwd_A1")])
9950 (define_insn "main_pool"
9951 [(set (match_operand 0 "register_operand" "=a")
9952 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9953 "GET_MODE (operands[0]) == Pmode"
9958 (if_then_else (match_test "TARGET_CPU_ZARCH")
9959 (const_string "larl") (const_string "la")))])
9961 (define_insn "reload_base_31"
9962 [(set (match_operand 0 "register_operand" "=a")
9963 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9964 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9965 "basr\t%0,0\;la\t%0,%1-.(%0)"
9966 [(set_attr "length" "6")
9967 (set_attr "type" "la")
9968 (set_attr "z196prop" "z196_cracked")])
9970 (define_insn "reload_base_64"
9971 [(set (match_operand 0 "register_operand" "=a")
9972 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9973 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9975 [(set_attr "op_type" "RIL")
9976 (set_attr "type" "larl")
9977 (set_attr "z10prop" "z10_fwd_A1")])
9980 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9985 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9988 ;; Insns related to generating the function prologue and epilogue.
9992 (define_expand "prologue"
9993 [(use (const_int 0))]
9995 "s390_emit_prologue (); DONE;")
9997 (define_expand "epilogue"
9998 [(use (const_int 1))]
10000 "s390_emit_epilogue (false); DONE;")
10002 (define_expand "sibcall_epilogue"
10003 [(use (const_int 0))]
10005 "s390_emit_epilogue (true); DONE;")
10007 ;; A direct return instruction, without using an epilogue.
10008 (define_insn "<code>"
10010 "s390_can_use_<code>_insn ()"
10012 [(set_attr "op_type" "RR")
10013 (set_attr "type" "jsr")
10014 (set_attr "atype" "agen")])
10016 (define_insn "*return"
10018 (use (match_operand 0 "register_operand" "a"))]
10019 "GET_MODE (operands[0]) == Pmode"
10021 [(set_attr "op_type" "RR")
10022 (set_attr "type" "jsr")
10023 (set_attr "atype" "agen")])
10026 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10027 ;; pointer. This is used for compatibility.
10029 (define_expand "ptr_extend"
10030 [(set (match_operand:DI 0 "register_operand" "=r")
10031 (match_operand:SI 1 "register_operand" "r"))]
10034 emit_insn (gen_anddi3 (operands[0],
10035 gen_lowpart (DImode, operands[1]),
10036 GEN_INT (0x7fffffff)));
10040 ;; Instruction definition to expand eh_return macro to support
10041 ;; swapping in special linkage return addresses.
10043 (define_expand "eh_return"
10044 [(use (match_operand 0 "register_operand" ""))]
10047 s390_emit_tpf_eh_return (operands[0]);
10052 ; Stack Protector Patterns
10055 (define_expand "stack_protect_set"
10056 [(set (match_operand 0 "memory_operand" "")
10057 (match_operand 1 "memory_operand" ""))]
10060 #ifdef TARGET_THREAD_SSP_OFFSET
10062 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10063 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10066 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10068 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10073 (define_insn "stack_protect_set<mode>"
10074 [(set (match_operand:DSI 0 "memory_operand" "=Q")
10075 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10077 "mvc\t%O0(%G0,%R0),%S1"
10078 [(set_attr "op_type" "SS")])
10080 (define_expand "stack_protect_test"
10081 [(set (reg:CC CC_REGNUM)
10082 (compare (match_operand 0 "memory_operand" "")
10083 (match_operand 1 "memory_operand" "")))
10084 (match_operand 2 "" "")]
10088 #ifdef TARGET_THREAD_SSP_OFFSET
10090 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10091 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10094 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10096 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10098 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10099 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10100 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10104 (define_insn "stack_protect_test<mode>"
10105 [(set (reg:CCZ CC_REGNUM)
10106 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10107 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10109 "clc\t%O0(%G0,%R0),%S1"
10110 [(set_attr "op_type" "SS")])
10112 ; This is used in s390_emit_prologue in order to prevent insns
10113 ; adjusting the stack pointer to be moved over insns writing stack
10114 ; slots using a copy of the stack pointer in a different register.
10115 (define_insn "stack_tie"
10116 [(set (match_operand:BLK 0 "memory_operand" "+m")
10117 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10120 [(set_attr "length" "0")])
10124 ; Data prefetch patterns
10127 (define_insn "prefetch"
10128 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
10129 (match_operand:SI 1 "const_int_operand" " n,n")
10130 (match_operand:SI 2 "const_int_operand" " n,n"))]
10133 switch (which_alternative)
10136 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10138 if (larl_operand (operands[0], Pmode))
10139 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10142 /* This might be reached for symbolic operands with an odd
10143 addend. We simply omit the prefetch for such rare cases. */
10148 [(set_attr "type" "load,larl")
10149 (set_attr "op_type" "RXY,RIL")
10150 (set_attr "z10prop" "z10_super")
10151 (set_attr "z196prop" "z196_alone")])
10155 ; Byte swap instructions
10158 (define_insn "bswap<mode>2"
10159 [(set (match_operand:GPR 0 "register_operand" "=d, d")
10160 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
10165 [(set_attr "type" "*,load")
10166 (set_attr "op_type" "RRE,RXY")
10167 (set_attr "z10prop" "z10_super")])
10171 ; Population count instruction
10174 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10175 ; portions and stores the result in the corresponding bytes in op0.
10176 (define_insn "*popcount<mode>"
10177 [(set (match_operand:INT 0 "register_operand" "=d")
10178 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10179 (clobber (reg:CC CC_REGNUM))]
10182 [(set_attr "op_type" "RRE")])
10184 (define_expand "popcountdi2"
10186 (parallel [(set (match_operand:DI 0 "register_operand" "")
10187 (unspec:DI [(match_operand:DI 1 "register_operand")]
10189 (clobber (reg:CC CC_REGNUM))])
10190 ; sllg op2, op0, 32
10191 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10193 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10194 (clobber (reg:CC CC_REGNUM))])
10195 ; sllg op2, op0, 16
10197 (ashift:DI (match_dup 0) (const_int 16)))
10199 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10200 (clobber (reg:CC CC_REGNUM))])
10202 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10204 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10205 (clobber (reg:CC CC_REGNUM))])
10206 ; srlg op0, op0, 56
10207 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10208 "TARGET_Z196 && TARGET_64BIT"
10209 "operands[2] = gen_reg_rtx (DImode);")
10211 (define_expand "popcountsi2"
10213 (parallel [(set (match_operand:SI 0 "register_operand" "")
10214 (unspec:SI [(match_operand:SI 1 "register_operand")]
10216 (clobber (reg:CC CC_REGNUM))])
10217 ; sllk op2, op0, 16
10219 (ashift:SI (match_dup 0) (const_int 16)))
10221 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10222 (clobber (reg:CC CC_REGNUM))])
10224 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10226 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10227 (clobber (reg:CC CC_REGNUM))])
10229 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10231 "operands[2] = gen_reg_rtx (SImode);")
10233 (define_expand "popcounthi2"
10235 (parallel [(set (match_operand:HI 0 "register_operand" "")
10236 (unspec:HI [(match_operand:HI 1 "register_operand")]
10238 (clobber (reg:CC CC_REGNUM))])
10241 (ashift:SI (match_dup 0) (const_int 8)))
10243 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10244 (clobber (reg:CC CC_REGNUM))])
10246 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10248 "operands[2] = gen_reg_rtx (SImode);")
10250 (define_expand "popcountqi2"
10252 (parallel [(set (match_operand:QI 0 "register_operand" "")
10253 (unspec:QI [(match_operand:QI 1 "register_operand")]
10255 (clobber (reg:CC CC_REGNUM))])]
10260 ;;- Copy sign instructions
10263 (define_insn "copysign<mode>3"
10264 [(set (match_operand:FP 0 "register_operand" "=f")
10265 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10266 (match_operand:FP 2 "register_operand" "f")]
10270 [(set_attr "op_type" "RRF")
10271 (set_attr "type" "fsimp<mode>")])
10275 ;;- Transactional execution instructions
10278 ; This splitter helps combine to make use of CC directly when
10279 ; comparing the integer result of a tbegin builtin with a constant.
10280 ; The unspec is already removed by canonicalize_comparison. So this
10281 ; splitters only job is to turn the PARALLEL into separate insns
10282 ; again. Unfortunately this only works with the very first cc/int
10283 ; compare since combine is not able to deal with data flow across
10284 ; basic block boundaries.
10286 ; It needs to be an insn pattern as well since combine does not apply
10287 ; the splitter directly. Combine would only use it if it actually
10288 ; would reduce the number of instructions.
10289 (define_insn_and_split "*ccraw_to_int"
10292 (match_operator 0 "s390_eqne_operator"
10293 [(reg:CCRAW CC_REGNUM)
10294 (match_operand 1 "const_int_operand" "")])
10295 (label_ref (match_operand 2 "" ""))
10297 (set (match_operand:SI 3 "register_operand" "=d")
10298 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10302 [(set (match_dup 3)
10303 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10305 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10306 (label_ref (match_dup 2))
10310 ; Non-constrained transaction begin
10312 (define_expand "tbegin"
10313 [(match_operand:SI 0 "register_operand" "")
10314 (match_operand:BLK 1 "memory_operand" "")]
10317 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10321 (define_expand "tbegin_nofloat"
10322 [(match_operand:SI 0 "register_operand" "")
10323 (match_operand:BLK 1 "memory_operand" "")]
10326 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10330 (define_expand "tbegin_retry"
10331 [(match_operand:SI 0 "register_operand" "")
10332 (match_operand:BLK 1 "memory_operand" "")
10333 (match_operand:SI 2 "general_operand" "")]
10336 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10340 (define_expand "tbegin_retry_nofloat"
10341 [(match_operand:SI 0 "register_operand" "")
10342 (match_operand:BLK 1 "memory_operand" "")
10343 (match_operand:SI 2 "general_operand" "")]
10346 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10350 (define_insn "tbegin_1"
10351 [(set (reg:CCRAW CC_REGNUM)
10352 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10354 (set (match_operand:BLK 1 "memory_operand" "=Q")
10355 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10356 (clobber (reg:DF 16))
10357 (clobber (reg:DF 17))
10358 (clobber (reg:DF 18))
10359 (clobber (reg:DF 19))
10360 (clobber (reg:DF 20))
10361 (clobber (reg:DF 21))
10362 (clobber (reg:DF 22))
10363 (clobber (reg:DF 23))
10364 (clobber (reg:DF 24))
10365 (clobber (reg:DF 25))
10366 (clobber (reg:DF 26))
10367 (clobber (reg:DF 27))
10368 (clobber (reg:DF 28))
10369 (clobber (reg:DF 29))
10370 (clobber (reg:DF 30))
10371 (clobber (reg:DF 31))]
10372 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10373 ; not supposed to be used for immediates (see genpreds.c).
10374 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10376 [(set_attr "op_type" "SIL")])
10378 ; Same as above but without the FPR clobbers
10379 (define_insn "tbegin_nofloat_1"
10380 [(set (reg:CCRAW CC_REGNUM)
10381 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10383 (set (match_operand:BLK 1 "memory_operand" "=Q")
10384 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10385 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10387 [(set_attr "op_type" "SIL")])
10390 ; Constrained transaction begin
10392 (define_expand "tbeginc"
10393 [(set (reg:CCRAW CC_REGNUM)
10394 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10399 (define_insn "*tbeginc_1"
10400 [(set (reg:CCRAW CC_REGNUM)
10401 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10403 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10405 [(set_attr "op_type" "SIL")])
10409 (define_expand "tend"
10410 [(set (reg:CCRAW CC_REGNUM)
10411 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10412 (set (match_operand:SI 0 "register_operand" "")
10413 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10417 (define_insn "*tend_1"
10418 [(set (reg:CCRAW CC_REGNUM)
10419 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10422 [(set_attr "op_type" "S")])
10424 ; Transaction abort
10426 (define_expand "tabort"
10427 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10429 "TARGET_HTM && operands != NULL"
10431 if (CONST_INT_P (operands[0])
10432 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10434 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10435 ". Values in range 0 through 255 are reserved.",
10436 INTVAL (operands[0]));
10441 (define_insn "*tabort_1"
10442 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10444 "TARGET_HTM && operands != NULL"
10446 [(set_attr "op_type" "S")])
10448 ; Transaction extract nesting depth
10450 (define_insn "etnd"
10451 [(set (match_operand:SI 0 "register_operand" "=d")
10452 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10455 [(set_attr "op_type" "RRE")])
10457 ; Non-transactional store
10459 (define_insn "ntstg"
10460 [(set (match_operand:DI 0 "memory_operand" "=RT")
10461 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10465 [(set_attr "op_type" "RXY")])
10467 ; Transaction perform processor assist
10469 (define_expand "tx_assist"
10470 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10471 (reg:SI GPR0_REGNUM)
10477 (define_insn "*ppa"
10478 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10479 (match_operand:SI 1 "register_operand" "d")
10480 (match_operand 2 "const_int_operand" "I")]
10482 "TARGET_HTM && INTVAL (operands[2]) < 16"
10484 [(set_attr "op_type" "RRF")])
10487 ; Set and get floating point control register
10489 (define_insn "s390_sfpc"
10490 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10492 "TARGET_HARD_FLOAT"
10495 (define_insn "s390_efpc"
10496 [(set (match_operand:SI 0 "register_operand" "=d")
10497 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10498 "TARGET_HARD_FLOAT"