gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com).
   5 ;; This file is part of GNU CC.
   6
   7 ;; GNU CC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11
  12 ;; GNU CC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GNU CC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22 ;;
  23 ;; Special constraints for s/390 machine description:
  24 ;;
  25 ;;    a -- Any address register from 1 to 15.
  26 ;;    d -- Any register from 0 to 15.
  27 ;;    I -- An 8-bit constant (0..255).
  28 ;;    J -- A 12-bit constant (0..4095).
  29 ;;    K -- A 16-bit constant (-32768..32767).
  30 ;;    Q -- A memory reference without index-register.
  31 ;;    S -- Valid operand for the LARL instruction.
  32 ;;
  33 ;; Special formats used for outputting 390 instructions.
  34 ;;
  35 ;;   %b -- Print a constant byte integer.               xy
  36 ;;   %h -- Print a signed 16-bit.                       wxyz
  37 ;;   %N -- Print next register (second word of a DImode reg) or next word.
  38 ;;   %M -- Print next register (second word of a TImode reg) or next word.
  39 ;;   %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
  40 ;;   %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
  41 ;;
  42 ;; We have a special constraint for pattern matching.
  43 ;;
  44 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  45 ;;
  46
  47
  48 ;; Define an insn type attribute.  This is used in function unit delay
  49 ;; computations.
  50
  51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
  52   (const_string "integer"))
  53
  54 ;; Insn are devide in two classes:
  55 ;;   mem: Insn accessing memory
  56 ;;   reg: Insn operands all in registers
  57
  58 (define_attr "atype" "reg,mem"
  59   (const_string "reg"))
  60
  61 ;; Generic pipeline function unit.
  62
  63 (define_function_unit "integer" 1 0
  64   (eq_attr "type" "none") 0 0)
  65
  66 (define_function_unit "integer" 1 0
  67   (eq_attr "type" "integer") 1 1)
  68
  69 (define_function_unit "integer" 1 0
  70   (eq_attr "type" "load") 1 1)
  71
  72 (define_function_unit "integer" 1 0
  73   (eq_attr "type" "la") 1 1)
  74
  75 (define_function_unit "integer" 1 0
  76   (eq_attr "type" "lr") 1 1)
  77
  78 (define_function_unit "integer" 1 0
  79   (eq_attr "type" "store") 1 1)
  80
  81 (define_function_unit "integer" 1 0
  82   (eq_attr "type" "lm") 2 2)
  83
  84 (define_function_unit "integer" 1 0
  85   (eq_attr "type" "stm") 2 2)
  86
  87 (define_function_unit "integer" 1 0
  88   (eq_attr "type" "cs") 5 5)
  89
  90 (define_function_unit "integer" 1 0
  91   (eq_attr "type" "vs") 30 30)
  92
  93 (define_function_unit "integer" 1 0
  94   (eq_attr "type" "jsr") 5 5)
  95
  96 (define_function_unit "integer" 1 0
  97   (eq_attr "type" "imul") 7 7)
  98
  99 (define_function_unit "integer" 1 0
 100   (eq_attr "type" "fmul") 6 6)
 101
 102 (define_function_unit "integer" 1 0
 103   (eq_attr "type" "idiv") 33 33)
 104
 105 (define_function_unit "integer" 1 0
 106   (eq_attr "type" "fdiv") 33 33)
 107
 108 (define_function_unit "integer" 1 0
 109   (eq_attr "type" "o2") 2 2)
 110
 111 (define_function_unit "integer" 1 0
 112   (eq_attr "type" "o3") 3 3)
 113
 114 (define_function_unit "integer" 1 0
 115   (eq_attr "type" "other") 5 5)
 116
 117 ;; Operand type. Used to default length attribute values
 118
 119 (define_attr "op_type"
 120   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
 121   (const_string "RX"))
 122
 123 ;; Length in bytes.
 124
 125 (define_attr "length" ""
 126 (cond [ (eq_attr "op_type" "E")    (const_int 2)
 127          (eq_attr "op_type" "RR")  (const_int 2)
 128          (eq_attr "op_type" "RX")  (const_int 4)
 129          (eq_attr "op_type" "RI")  (const_int 4)
 130          (eq_attr "op_type" "RRE") (const_int 4)
 131          (eq_attr "op_type" "RS")  (const_int 4)
 132          (eq_attr "op_type" "RSI") (const_int 4)
 133          (eq_attr "op_type" "RX")  (const_int 4)
 134          (eq_attr "op_type" "S")   (const_int 4)
 135          (eq_attr "op_type" "SI")  (const_int 4)
 136          (eq_attr "op_type" "SS")  (const_int 6)
 137          (eq_attr "op_type" "SSE") (const_int 6)
 138          (eq_attr "op_type" "RXE") (const_int 6)
 139          (eq_attr "op_type" "RSE") (const_int 6)
 140          (eq_attr "op_type" "RIL") (const_int 6)]
 141          (const_int 4)))
 142
 143 ;; Define attributes for `asm' insns.
 144
 145 (define_asm_attributes [(set_attr "type" "other")
 146                         (set_attr "op_type" "NN")])
 147
 148 ;;
 149 ;;  Condition Codes
 150 ;;
 151 ;
 152 ;   CCL:  Zero     Nonzero   Zero      Nonzero      (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
 153 ;   CCA:  Zero     <Zero     >Zero     Overflow     (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
 154 ;   CCU:  Equal    ULess     UGreater  --           (CL, CLR, CLI, CLM)
 155 ;   CCS:  Equal    SLess     SGreater  --           (C, CR, CH, CHI, ICM)
 156 ;   CCT:  Zero     Mixed     Mixed     Ones         (TM, TMH, TML)
 157
 158 ;   CCZ  -> CCL / CCZ1
 159 ;   CCZ1 -> CCA/CCU/CCS/CCT
 160 ;   CCS  -> CCA
 161
 162 ;   String:    CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
 163 ;   Clobber:   CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
 164
 165
 166 ;;
 167 ;;- Compare instructions.
 168 ;;
 169
 170 (define_expand "cmpdi"
 171   [(set (reg:CC 33)
 172         (compare:CC (match_operand:DI 0 "register_operand" "")
 173                     (match_operand:DI 1 "general_operand" "")))]
 174   "TARGET_64BIT"
 175   "
 176 {
 177   s390_compare_op0 = operands[0];
 178   s390_compare_op1 = operands[1];
 179   DONE;
 180 }")
 181
 182 (define_expand "cmpsi"
 183   [(set (reg:CC 33)
 184         (compare:CC (match_operand:SI 0 "register_operand" "")
 185                     (match_operand:SI 1 "general_operand" "")))]
 186   ""
 187   "
 188 {
 189   s390_compare_op0 = operands[0];
 190   s390_compare_op1 = operands[1];
 191   DONE;
 192 }")
 193
 194 (define_expand "cmpdf"
 195   [(set (reg:CC 33)
 196         (compare:CC (match_operand:DF 0 "register_operand" "")
 197                     (match_operand:DF 1 "general_operand" "")))]
 198   "TARGET_HARD_FLOAT"
 199   "
 200 {
 201   s390_compare_op0 = operands[0];
 202   s390_compare_op1 = operands[1];
 203   DONE;
 204 }")
 205
 206 (define_expand "cmpsf"
 207   [(set (reg:CC 33)
 208         (compare:CC (match_operand:SF 0 "register_operand" "")
 209                     (match_operand:SF 1 "general_operand" "")))]
 210   "TARGET_HARD_FLOAT"
 211   "
 212 {
 213   s390_compare_op0 = operands[0];
 214   s390_compare_op1 = operands[1];
 215   DONE;
 216 }")
 217
 218
 219 ; Test-under-Mask (zero_extract) instructions
 220
 221 (define_insn "*tmdi_ext"
 222   [(set (reg 33)
 223         (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
 224                                   (match_operand:DI 1 "const_int_operand" "n")
 225                                   (match_operand:DI 2 "const_int_operand" "n"))
 226                  (const_int 0)))]
 227   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
 228    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 229    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
 230    && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
 231       == INTVAL (operands[2]) >> 4"
 232   "*
 233 {
 234   int part = INTVAL (operands[2]) >> 4;
 235   int block = (1 << INTVAL (operands[1])) - 1;
 236   int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
 237
 238   operands[2] = GEN_INT (block << shift);
 239
 240   switch (part)
 241     {
 242       case 0: return \"tmhh\\t%0,%x2\";
 243       case 1: return \"tmhl\\t%0,%x2\";
 244       case 2: return \"tmlh\\t%0,%x2\";
 245       case 3: return \"tmll\\t%0,%x2\";
 246       default: abort ();
 247     }
 248 }"
 249   [(set_attr "op_type" "RI")])
 250
 251 (define_insn "*tmsi_ext"
 252   [(set (reg 33)
 253         (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
 254                                   (match_operand:SI 1 "const_int_operand" "n")
 255                                   (match_operand:SI 2 "const_int_operand" "n"))
 256                  (const_int 0)))]
 257   "s390_match_ccmode(insn, CCTmode)
 258    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 259    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
 260    && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
 261       == INTVAL (operands[2]) >> 4"
 262   "*
 263 {
 264   int part = INTVAL (operands[2]) >> 4;
 265   int block = (1 << INTVAL (operands[1])) - 1;
 266   int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
 267
 268   operands[2] = GEN_INT (block << shift);
 269
 270   switch (part)
 271     {
 272       case 0: return \"tmh\\t%0,%x2\";
 273       case 1: return \"tml\\t%0,%x2\";
 274       default: abort ();
 275     }
 276 }"
 277   [(set_attr "op_type" "RI")])
 278
 279 (define_insn "*tmqi_ext"
 280   [(set (reg 33)
 281         (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
 282                                   (match_operand:SI 1 "const_int_operand" "n")
 283                                   (match_operand:SI 2 "const_int_operand" "n"))
 284                  (const_int 0)))]
 285   "s390_match_ccmode(insn, CCTmode)
 286    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 287    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
 288   "*
 289 {
 290   int block = (1 << INTVAL (operands[1])) - 1;
 291   int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
 292
 293   operands[2] = GEN_INT (block << shift);
 294   return \"tm\\t%0,%b2\";
 295 }"
 296   [(set_attr "op_type" "SI")
 297    (set_attr "atype"   "mem")])
 298
 299 ; Test-under-Mask instructions
 300
 301 (define_insn "*tmdi_mem"
 302   [(set (reg 33)
 303         (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
 304                          (match_operand:DI 1 "immediate_operand" "n"))
 305                  (match_operand:DI 2 "immediate_operand" "n")))]
 306   "TARGET_64BIT
 307    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
 308    && s390_single_qi (operands[1], DImode, 0) >= 0"
 309   "*
 310 {
 311   int part = s390_single_qi (operands[1], DImode, 0);
 312   operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
 313
 314   operands[0] = gen_rtx_MEM (QImode,
 315                              plus_constant (XEXP (operands[0], 0), part));
 316   return \"tm\\t%0,%b1\";
 317 }"
 318   [(set_attr "op_type" "SI")
 319    (set_attr "atype"   "mem")])
 320
 321 (define_insn "*tmsi_mem"
 322   [(set (reg 33)
 323         (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
 324                          (match_operand:SI 1 "immediate_operand" "n"))
 325                  (match_operand:SI 2 "immediate_operand" "n")))]
 326   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
 327    && s390_single_qi (operands[1], SImode, 0) >= 0"
 328   "*
 329 {
 330   int part = s390_single_qi (operands[1], SImode, 0);
 331   operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
 332
 333   operands[0] = gen_rtx_MEM (QImode,
 334                              plus_constant (XEXP (operands[0], 0), part));
 335   return \"tm\\t%0,%b1\";
 336 }"
 337   [(set_attr "op_type" "SI")
 338    (set_attr "atype"   "mem")])
 339
 340 (define_insn "*tmhi_mem"
 341   [(set (reg 33)
 342         (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
 343                          (match_operand:SI 1 "immediate_operand" "n"))
 344                  (match_operand:SI 2 "immediate_operand" "n")))]
 345   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
 346    && s390_single_qi (operands[1], HImode, 0) >= 0"
 347   "*
 348 {
 349   int part = s390_single_qi (operands[1], HImode, 0);
 350   operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
 351
 352   operands[0] = gen_rtx_MEM (QImode,
 353                              plus_constant (XEXP (operands[0], 0), part));
 354   return \"tm\\t%0,%b1\";
 355 }"
 356   [(set_attr "op_type" "SI")
 357    (set_attr "atype"   "mem")])
 358
 359 (define_insn "*tmqi_mem"
 360   [(set (reg 33)
 361         (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
 362                          (match_operand:SI 1 "immediate_operand" "n"))
 363                  (match_operand:SI 2 "immediate_operand" "n")))]
 364   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
 365   "tm\\t%0,%b1"
 366   [(set_attr "op_type" "SI")
 367    (set_attr "atype"   "mem")])
 368
 369 (define_insn "*tmdi_reg"
 370   [(set (reg 33)
 371         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
 372                          (match_operand:DI 1 "immediate_operand" "n"))
 373                  (match_operand:DI 2 "immediate_operand" "n")))]
 374   "TARGET_64BIT
 375    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
 376    && s390_single_hi (operands[1], DImode, 0) >= 0"
 377   "*
 378 {
 379   int part = s390_single_hi (operands[1], DImode, 0);
 380   operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
 381
 382   switch (part)
 383     {
 384       case 0: return \"tmhh\\t%0,%x1\";
 385       case 1: return \"tmhl\\t%0,%x1\";
 386       case 2: return \"tmlh\\t%0,%x1\";
 387       case 3: return \"tmll\\t%0,%x1\";
 388       default: abort ();
 389     }
 390 }"
 391   [(set_attr "op_type" "RI")])
 392
 393 (define_insn "*tmsi_reg"
 394   [(set (reg 33)
 395         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
 396                          (match_operand:SI 1 "immediate_operand" "n"))
 397                  (match_operand:SI 2 "immediate_operand" "n")))]
 398   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
 399    && s390_single_hi (operands[1], SImode, 0) >= 0"
 400   "*
 401 {
 402   int part = s390_single_hi (operands[1], SImode, 0);
 403   operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
 404
 405   switch (part)
 406     {
 407       case 0: return \"tmh\\t%0,%x1\";
 408       case 1: return \"tml\\t%0,%x1\";
 409       default: abort ();
 410     }
 411 }"
 412   [(set_attr "op_type" "RI")])
 413
 414 (define_insn "*tmhi_full"
 415   [(set (reg 33)
 416         (compare (match_operand:HI 0 "register_operand" "d")
 417                  (match_operand:HI 1 "immediate_operand" "n")))]
 418   "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
 419   "tml\\t%0,65535"
 420   [(set_attr "op_type" "RX")])
 421
 422 (define_insn "*tmqi_full"
 423   [(set (reg 33)
 424         (compare (match_operand:QI 0 "register_operand" "d")
 425                  (match_operand:QI 1 "immediate_operand" "n")))]
 426   "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
 427   "tml\\t%0,255"
 428   [(set_attr "op_type" "RI")])
 429
 430
 431 ; Load-and-Test instructions
 432
 433 (define_insn "*tstdi_sign"
 434   [(set (reg 33)
 435         (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
 436                                          (const_int 32)) (const_int 32))
 437                  (match_operand:DI 1 "const0_operand" "")))
 438    (set (match_operand:DI 2 "register_operand" "=d")
 439         (sign_extend:DI (match_dup 0)))]
 440   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 441   "ltgfr\\t%2,%0"
 442   [(set_attr "op_type" "RRE")])
 443
 444 (define_insn "*tstdi"
 445   [(set (reg 33)
 446         (compare (match_operand:DI 0 "register_operand" "d")
 447                  (match_operand:DI 1 "const0_operand" "")))
 448    (set (match_operand:DI 2 "register_operand" "=d")
 449         (match_dup 0))]
 450   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 451   "ltgr\\t%2,%0"
 452   [(set_attr "op_type" "RRE")])
 453
 454 (define_insn "*tstdi_cconly"
 455   [(set (reg 33)
 456         (compare (match_operand:DI 0 "register_operand" "d")
 457                  (match_operand:DI 1 "const0_operand" "")))]
 458   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 459   "ltgr\\t%0,%0"
 460   [(set_attr "op_type" "RRE")])
 461
 462 (define_insn "*tstdi_cconly_31"
 463   [(set (reg 33)
 464         (compare (match_operand:DI 0 "register_operand" "d")
 465                  (match_operand:DI 1 "const0_operand" "")))]
 466   "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
 467   "srda\\t%0,0"
 468   [(set_attr "op_type" "RS")])
 469
 470 (define_insn "*tstsi"
 471   [(set (reg 33)
 472         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
 473                  (match_operand:SI 1 "const0_operand" "")))
 474    (set (match_operand:SI 2 "register_operand" "=d,d")
 475         (match_dup 0))]
 476   "s390_match_ccmode(insn, CCSmode)"
 477   "@
 478    ltr\\t%2,%0
 479    icm\\t%2,15,%0"
 480   [(set_attr "op_type" "RR,RS")
 481    (set_attr "atype"   "reg,mem")])
 482
 483 (define_insn "*tstsi_cconly"
 484   [(set (reg 33)
 485         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
 486                  (match_operand:SI 1 "const0_operand" "")))
 487    (clobber (match_scratch:SI 2 "=X,d"))]
 488   "s390_match_ccmode(insn, CCSmode)"
 489   "@
 490    ltr\\t%0,%0
 491    icm\\t%2,15,%0"
 492   [(set_attr "op_type" "RR,RS")
 493    (set_attr "atype"   "reg,mem")])
 494
 495 (define_insn "*tstsi_cconly2"
 496   [(set (reg 33)
 497         (compare (match_operand:SI 0 "register_operand" "d")
 498                  (match_operand:SI 1 "const0_operand" "")))]
 499   "s390_match_ccmode(insn, CCSmode)"
 500   "ltr\\t%0,%0"
 501   [(set_attr "op_type" "RR")])
 502
 503 (define_insn "*tsthi"
 504   [(set (reg 33)
 505         (compare (match_operand:HI 0 "s_operand" "Q")
 506                  (match_operand:HI 1 "const0_operand" "")))
 507    (set (match_operand:HI 2 "register_operand" "=d")
 508         (match_dup 0))]
 509   "s390_match_ccmode(insn, CCSmode)"
 510   "icm\\t%2,3,%0"
 511   [(set_attr "op_type" "RS")
 512    (set_attr "atype"   "mem")])
 513
 514 (define_insn "*tsthi_cconly"
 515   [(set (reg 33)
 516         (compare (match_operand:HI 0 "s_operand" "Q")
 517                  (match_operand:HI 1 "const0_operand" "")))
 518    (clobber (match_scratch:HI 2 "=d"))]
 519   "s390_match_ccmode(insn, CCSmode)"
 520   "icm\\t%2,3,%0"
 521   [(set_attr "op_type" "RS")
 522    (set_attr "atype"   "mem")])
 523
 524 (define_insn "*tstqi"
 525   [(set (reg 33)
 526         (compare (match_operand:QI 0 "s_operand" "Q")
 527                  (match_operand:QI 1 "const0_operand" "")))
 528    (set (match_operand:QI 2 "register_operand" "=d")
 529         (match_dup 0))]
 530   "s390_match_ccmode(insn, CCSmode)"
 531   "icm\\t%2,1,%0"
 532   [(set_attr "op_type" "RS")
 533    (set_attr "atype"   "mem")])
 534
 535 (define_insn "*tstqi_cconly"
 536   [(set (reg 33)
 537         (compare (match_operand:QI 0 "s_operand" "Q")
 538                  (match_operand:QI 1 "const0_operand" "")))
 539    (clobber (match_scratch:QI 2 "=d"))]
 540   "s390_match_ccmode(insn, CCSmode)"
 541   "icm\\t%2,1,%0"
 542   [(set_attr "op_type" "RS")
 543    (set_attr "atype"   "mem")])
 544
 545
 546 ; Compare (signed) instructions
 547
 548 (define_insn "*cmpdi_ccs_sign"
 549   [(set (reg 33)
 550         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
 551                  (match_operand:DI 0 "register_operand" "d,d")))]
 552   "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
 553   "@
 554    cgfr\\t%0,%1
 555    cgf\\t%0,%1"
 556   [(set_attr "op_type" "RRE,RXE")
 557    (set_attr "atype"   "reg,mem")])
 558
 559 (define_insn "*cmpdi_ccs"
 560   [(set (reg 33)
 561         (compare (match_operand:DI 0 "register_operand" "d,d,d")
 562                  (match_operand:DI 1 "general_operand" "d,K,m")))]
 563   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 564   "@
 565    cgr\\t%0,%1
 566    cghi\\t%0,%c1
 567    cg\\t%0,%1"
 568   [(set_attr "op_type" "RRE,RI,RXE")
 569    (set_attr "atype"    "reg,reg,mem")])
 570
 571 (define_insn "*cmpsi_ccs_sign"
 572   [(set (reg 33)
 573         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
 574                  (match_operand:SI 0 "register_operand" "d")))]
 575   "s390_match_ccmode(insn, CCSRmode)"
 576   "ch\\t%0,%1"
 577   [(set_attr "op_type" "RX")
 578    (set_attr "atype"   "mem")])
 579
 580 (define_insn "*cmpsi_ccs"
 581   [(set (reg 33)
 582         (compare (match_operand:SI 0 "register_operand" "d,d,d")
 583                  (match_operand:SI 1 "general_operand" "d,K,m")))]
 584   "s390_match_ccmode(insn, CCSmode)"
 585   "@
 586    cr\\t%0,%1
 587    chi\\t%0,%c1
 588    c\\t%0,%1"
 589   [(set_attr "op_type" "RR,RI,RX")
 590    (set_attr "atype"   "reg,reg,mem")])
 591
 592
 593 ; Compare (unsigned) instructions
 594
 595 (define_insn "*cmpdi_ccu_zero"
 596   [(set (reg 33)
 597         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
 598                  (match_operand:DI 0 "register_operand" "d,d")))]
 599   "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
 600   "@
 601    clgfr\\t%0,%1
 602    clgf\\t%0,%1"
 603   [(set_attr "op_type" "RRE,RXE")
 604    (set_attr "atype"   "reg,mem")])
 605
 606 (define_insn "*cmpdi_ccu"
 607   [(set (reg 33)
 608         (compare (match_operand:DI 0 "register_operand" "d,d")
 609                  (match_operand:DI 1 "general_operand" "d,m")))]
 610   "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
 611   "@
 612    clgr\\t%0,%1
 613    clg\\t%0,%1"
 614   [(set_attr "op_type" "RRE,RXE")
 615    (set_attr "atype"   "reg,mem")])
 616
 617 (define_insn "*cmpsi_ccu"
 618   [(set (reg 33)
 619         (compare (match_operand:SI 0 "register_operand" "d,d")
 620                  (match_operand:SI 1 "general_operand" "d,m")))]
 621   "s390_match_ccmode(insn, CCUmode)"
 622   "@
 623    clr\\t%0,%1
 624    cl\\t%0,%1"
 625   [(set_attr "op_type" "RR,RX")
 626    (set_attr "atype"   "reg,mem")])
 627
 628 (define_insn "*cmphi_ccu"
 629   [(set (reg 33)
 630         (compare (match_operand:HI 0 "register_operand" "d")
 631                  (match_operand:HI 1 "s_imm_operand" "Q")))]
 632   "s390_match_ccmode(insn, CCUmode)"
 633   "clm\\t%0,3,%1"
 634   [(set_attr "op_type" "RS")
 635    (set_attr "atype"   "mem")])
 636
 637 (define_insn "*cmpqi_ccu"
 638   [(set (reg 33)
 639         (compare (match_operand:QI 0 "register_operand" "d")
 640                  (match_operand:QI 1 "s_imm_operand" "Q")))]
 641   "s390_match_ccmode(insn, CCUmode)"
 642   "clm\\t%0,1,%1"
 643   [(set_attr "op_type" "RS")
 644    (set_attr "atype"   "mem")])
 645
 646 (define_insn "*cli"
 647   [(set (reg 33)
 648         (compare (match_operand:QI 0 "memory_operand" "Q")
 649                  (match_operand:QI 1 "immediate_operand" "n")))]
 650   "s390_match_ccmode (insn, CCUmode)"
 651   "cli\\t%0,%b1"
 652   [(set_attr "op_type" "SI")
 653    (set_attr "atype"   "mem")])
 654
 655 (define_insn "*cmpdi_ccu_mem"
 656   [(set (reg 33)
 657         (compare (match_operand:DI 0 "s_operand" "Q")
 658                  (match_operand:DI 1 "s_imm_operand" "Q")))]
 659   "s390_match_ccmode(insn, CCUmode)"
 660   "clc\\t%O0(8,%R0),%1"
 661   [(set_attr "op_type" "SS")
 662    (set_attr "atype"   "mem")])
 663
 664 (define_insn "*cmpsi_ccu_mem"
 665   [(set (reg 33)
 666         (compare (match_operand:SI 0 "s_operand" "Q")
 667                  (match_operand:SI 1 "s_imm_operand" "Q")))]
 668   "s390_match_ccmode(insn, CCUmode)"
 669   "clc\\t%O0(4,%R0),%1"
 670    [(set_attr "op_type" "SS")
 671     (set_attr "atype"   "mem")])
 672
 673 (define_insn "*cmphi_ccu_mem"
 674   [(set (reg 33)
 675         (compare (match_operand:HI 0 "s_operand" "Q")
 676                  (match_operand:HI 1 "s_imm_operand" "Q")))]
 677   "s390_match_ccmode(insn, CCUmode)"
 678   "clc\\t%O0(2,%R0),%1"
 679   [(set_attr "op_type" "SS")
 680    (set_attr "atype"   "mem")])
 681
 682 (define_insn "*cmpqi_ccu_mem"
 683   [(set (reg 33)
 684         (compare (match_operand:QI 0 "s_operand" "Q")
 685                  (match_operand:QI 1 "s_imm_operand" "Q")))]
 686   "s390_match_ccmode(insn, CCUmode)"
 687   "clc\\t%O0(1,%R0),%1"
 688   [(set_attr "op_type" "SS")
 689    (set_attr "atype"   "mem")])
 690
 691
 692 ; DF instructions
 693
 694 (define_insn "*cmpdf_ccs_0"
 695   [(set (reg 33)
 696         (compare (match_operand:DF 0 "register_operand" "f")
 697                  (match_operand:DF 1 "const0_operand" "")))]
 698   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 699   "ltdbr\\t%0,%0"
 700    [(set_attr "op_type" "RRE")])
 701
 702 (define_insn "*cmpdf_ccs_0_ibm"
 703   [(set (reg 33)
 704         (compare (match_operand:DF 0 "register_operand" "f")
 705                  (match_operand:DF 1 "const0_operand" "")))]
 706   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 707   "ltdr\\t%0,%0"
 708    [(set_attr "op_type" "RR")])
 709
 710 (define_insn "*cmpdf_ccs"
 711   [(set (reg 33)
 712         (compare (match_operand:DF 0 "register_operand" "f,f")
 713                  (match_operand:DF 1 "general_operand" "f,m")))]
 714   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 715   "@
 716    cdbr\\t%0,%1
 717    cdb\\t%0,%1"
 718    [(set_attr "op_type" "RRE,RXE")
 719     (set_attr "atype"   "reg,mem")])
 720
 721 (define_insn "*cmpdf_ccs_ibm"
 722   [(set (reg 33)
 723         (compare (match_operand:DF 0 "register_operand" "f,f")
 724                  (match_operand:DF 1 "general_operand" "f,m")))]
 725   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 726   "@
 727    cdr\\t%0,%1
 728    cd\\t%0,%1"
 729    [(set_attr "op_type" "RR,RX")
 730     (set_attr "atype"   "reg,mem")])
 731
 732
 733 ; SF instructions
 734
 735 (define_insn "*cmpsf_ccs_0"
 736   [(set (reg 33)
 737         (compare (match_operand:SF 0 "register_operand" "f")
 738                  (match_operand:SF 1 "const0_operand" "")))]
 739   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 740   "ltebr\\t%0,%0"
 741    [(set_attr "op_type" "RRE")])
 742
 743 (define_insn "*cmpsf_ccs_0_ibm"
 744   [(set (reg 33)
 745         (compare (match_operand:SF 0 "register_operand" "f")
 746                  (match_operand:SF 1 "const0_operand" "")))]
 747   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 748   "lter\\t%0,%0"
 749    [(set_attr "op_type" "RR")])
 750
 751 (define_insn "*cmpsf_ccs"
 752   [(set (reg 33)
 753         (compare (match_operand:SF 0 "register_operand" "f,f")
 754                  (match_operand:SF 1 "general_operand" "f,m")))]
 755   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 756   "@
 757    cebr\\t%0,%1
 758    ceb\\t%0,%1"
 759   [(set_attr "op_type" "RRE,RXE")
 760    (set_attr "atype"   "reg,mem")])
 761
 762 (define_insn "*cmpsf_ccs"
 763   [(set (reg 33)
 764         (compare (match_operand:SF 0 "register_operand" "f,f")
 765                  (match_operand:SF 1 "general_operand" "f,m")))]
 766   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 767   "@
 768    cer\\t%0,%1
 769    ce\\t%0,%1"
 770   [(set_attr "op_type" "RR,RX")
 771    (set_attr "atype"   "reg,mem")])
 772
 773
 774 ;;
 775 ;;- Move instructions.
 776 ;;
 777
 778 ;
 779 ; movti instruction pattern(s).
 780 ;
 781
 782 (define_insn "movti"
 783   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
 784         (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
 785   "TARGET_64BIT"
 786   "@
 787    lmg\\t%0,%N0,%1
 788    stmg\\t%1,%N1,%0
 789    #
 790    #
 791    mvc\\t%O0(16,%R0),%1"
 792   [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
 793    (set_attr "atype"   "mem")])
 794
 795 (define_split
 796   [(set (match_operand:TI 0 "nonimmediate_operand" "")
 797         (match_operand:TI 1 "general_operand" ""))]
 798   "TARGET_64BIT && reload_completed
 799    && !s_operand (operands[0], VOIDmode)
 800    && !s_operand (operands[1], VOIDmode)
 801    && (register_operand (operands[0], VOIDmode)
 802        || register_operand (operands[1], VOIDmode))
 803    && (!register_operand (operands[0], VOIDmode)
 804        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
 805                                     operands[1])
 806        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
 807                                     operands[1]))"
 808   [(set (match_dup 2) (match_dup 4))
 809    (set (match_dup 3) (match_dup 5))]
 810   "
 811 {
 812   if (!register_operand (operands[0], VOIDmode)
 813       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
 814                                    operands[1]))
 815     {
 816       operands[2] = operand_subword (operands[0], 0, 0, TImode);
 817       operands[3] = operand_subword (operands[0], 1, 0, TImode);
 818       operands[4] = operand_subword (operands[1], 0, 0, TImode);
 819       operands[5] = operand_subword (operands[1], 1, 0, TImode);
 820     }
 821   else
 822     {
 823       operands[2] = operand_subword (operands[0], 1, 0, TImode);
 824       operands[3] = operand_subword (operands[0], 0, 0, TImode);
 825       operands[4] = operand_subword (operands[1], 1, 0, TImode);
 826       operands[5] = operand_subword (operands[1], 0, 0, TImode);
 827     }
 828 }")
 829
 830 (define_split
 831   [(set (match_operand:TI 0 "register_operand" "")
 832         (match_operand:TI 1 "memory_operand" ""))]
 833   "TARGET_64BIT && reload_completed
 834    && !s_operand (operands[1], VOIDmode)"
 835   [(set (match_dup 2) (match_dup 3))
 836    (set (match_dup 0) (mem:TI (match_dup 2)))]
 837   "operands[2] = operand_subword (operands[0], 1, 0, TImode);
 838    operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
 839
 840 ;
 841 ; movdi instruction pattern(s).
 842 ;
 843
 844 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
 845 ;; move to get the address of the symbolic object from the GOT.
 846
 847 (define_expand "movdi"
 848   [(set (match_operand:DI 0 "general_operand" "")
 849         (match_operand:DI 1 "general_operand" ""))]
 850   ""
 851   "
 852 {
 853   /* Handle PIC symbolic constants.  */
 854   if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
 855     emit_pic_move (operands, DImode);
 856
 857   /* During and after reload, we need to force constants
 858      to the literal pool ourselves, if necessary.  */
 859   if ((reload_in_progress || reload_completed)
 860       && CONSTANT_P (operands[1])
 861       && (!legitimate_reload_constant_p (operands[1])
 862           || fp_operand (operands[0], VOIDmode)))
 863     operands[1] = force_const_mem (DImode, operands[1]);
 864 }")
 865
 866 (define_insn "*movdi_lhi"
 867   [(set (match_operand:DI 0 "register_operand" "=d")
 868         (match_operand:DI 1 "immediate_operand" "K"))]
 869   "TARGET_64BIT
 870    && GET_CODE (operands[1]) == CONST_INT
 871    && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
 872    && !fp_operand (operands[0], VOIDmode)"
 873   "lghi\\t%0,%h1"
 874   [(set_attr "op_type" "RI")
 875    (set_attr "atype"   "reg")])
 876
 877 (define_insn "*movdi_lli"
 878   [(set (match_operand:DI 0 "register_operand" "=d")
 879         (match_operand:DI 1 "immediate_operand" "n"))]
 880   "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
 881    && !fp_operand (operands[0], VOIDmode)"
 882   "*
 883 {
 884   int part = s390_single_hi (operands[1], DImode, 0);
 885   operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
 886
 887   switch (part)
 888     {
 889       case 0: return \"llihh\\t%0,%x1\";
 890       case 1: return \"llihl\\t%0,%x1\";
 891       case 2: return \"llilh\\t%0,%x1\";
 892       case 3: return \"llill\\t%0,%x1\";
 893       default: abort ();
 894     }
 895 }"
 896   [(set_attr "op_type" "RI")
 897    (set_attr "atype"   "reg")])
 898
 899 (define_insn "*movdi_larl"
 900   [(set (match_operand:DI 0 "register_operand" "=d")
 901         (match_operand:DI 1 "larl_operand" "X"))]
 902   "TARGET_64BIT
 903    && !fp_operand (operands[0], VOIDmode)"
 904   "larl\\t%0,%1"
 905    [(set_attr "op_type" "RIL")
 906     (set_attr "atype"   "reg")
 907     (set_attr "type"    "la")])
 908
 909 (define_insn "*movdi_64"
 910   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
 911         (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
 912   "TARGET_64BIT"
 913   "@
 914    lgr\\t%0,%1
 915    lg\\t%0,%1
 916    stg\\t%1,%0
 917    ldr\\t%0,%1
 918    ld\\t%0,%1
 919    std\\t%1,%0
 920    mvc\\t%O0(8,%R0),%1"
 921   [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX,SS")
 922    (set_attr "atype"   "reg,mem,mem,reg,mem,mem,mem")])
 923
 924 (define_insn "*movdi_31"
 925   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
 926         (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
 927   "!TARGET_64BIT"
 928   "@
 929    lm\\t%0,%N0,%1
 930    stm\\t%1,%N1,%0
 931    #
 932    #
 933    ldr\\t%0,%1
 934    ld\\t%0,%1
 935    std\\t%1,%0
 936    mvc\\t%O0(8,%R0),%1"
 937   [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
 938    (set_attr "atype"   "mem,mem,*,*,reg,mem,mem,mem")])
 939
 940 (define_split
 941   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 942         (match_operand:DI 1 "general_operand" ""))]
 943   "!TARGET_64BIT && reload_completed
 944    && !fp_operand (operands[0], VOIDmode)
 945    && !fp_operand (operands[1], VOIDmode)
 946    && !s_operand (operands[0], VOIDmode)
 947    && !s_operand (operands[1], VOIDmode)
 948    && (register_operand (operands[0], VOIDmode)
 949        || register_operand (operands[1], VOIDmode))
 950    && (!register_operand (operands[0], VOIDmode)
 951        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
 952                                     operands[1])
 953        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
 954                                     operands[1]))"
 955   [(set (match_dup 2) (match_dup 4))
 956    (set (match_dup 3) (match_dup 5))]
 957   "
 958 {
 959   if (!register_operand (operands[0], VOIDmode)
 960       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
 961                                    operands[1]))
 962     {
 963       operands[2] = operand_subword (operands[0], 0, 0, DImode);
 964       operands[3] = operand_subword (operands[0], 1, 0, DImode);
 965       operands[4] = operand_subword (operands[1], 0, 0, DImode);
 966       operands[5] = operand_subword (operands[1], 1, 0, DImode);
 967     }
 968   else
 969     {
 970       operands[2] = operand_subword (operands[0], 1, 0, DImode);
 971       operands[3] = operand_subword (operands[0], 0, 0, DImode);
 972       operands[4] = operand_subword (operands[1], 1, 0, DImode);
 973       operands[5] = operand_subword (operands[1], 0, 0, DImode);
 974     }
 975 }")
 976
 977 (define_split
 978   [(set (match_operand:DI 0 "register_operand" "")
 979         (match_operand:DI 1 "memory_operand" ""))]
 980   "!TARGET_64BIT && reload_completed
 981    && !fp_operand (operands[0], VOIDmode)
 982    && !fp_operand (operands[1], VOIDmode)
 983    && !s_operand (operands[1], VOIDmode)"
 984   [(set (match_dup 2) (match_dup 3))
 985    (set (match_dup 0) (mem:DI (match_dup 2)))]
 986   "operands[2] = operand_subword (operands[0], 1, 0, DImode);
 987    operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
 988
 989 ;
 990 ; movsi instruction pattern(s).
 991 ;
 992
 993 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
 994 ;; move to get the address of the symbolic object from the GOT.
 995
 996 (define_expand "movsi"
 997   [(set (match_operand:SI 0 "general_operand" "")
 998         (match_operand:SI 1 "general_operand" ""))]
 999   ""
1000   "
1001 {
1002   /* Handle PIC symbolic constants.  */
1003   if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1004     emit_pic_move (operands, SImode);
1005
1006   /* expr.c tries to load an effective address using
1007      force_reg.  This fails because we don't have a
1008      generic load_address pattern.  Convert the move
1009      to a proper arithmetic operation instead, unless
1010      it is guaranteed to be OK.  */
1011   if (GET_CODE (operands[1]) == PLUS
1012       && !legitimate_la_operand_p (operands[1]))
1013     {
1014       operands[1] = force_operand (operands[1], operands[0]);
1015       if (operands[1] == operands[0])
1016         DONE;
1017     }
1018
1019   /* During and after reload, we need to force constants
1020      to the literal pool ourselves, if necessary.  */
1021   if ((reload_in_progress || reload_completed)
1022       && CONSTANT_P (operands[1])
1023       && (!legitimate_reload_constant_p (operands[1])
1024           || fp_operand (operands[0], VOIDmode)))
1025     operands[1] = force_const_mem (SImode, operands[1]);
1026 }")
1027
1028 (define_insn "*movsi_lhi"
1029   [(set (match_operand:SI 0 "register_operand" "=d")
1030         (match_operand:SI 1 "immediate_operand" "K"))]
1031   "GET_CODE (operands[1]) == CONST_INT
1032    && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1033    && !fp_operand (operands[0], VOIDmode)"
1034   "lhi\\t%0,%h1"
1035   [(set_attr "op_type" "RI")])
1036
1037 (define_insn "*movsi_lli"
1038   [(set (match_operand:SI 0 "register_operand" "=d")
1039         (match_operand:SI 1 "immediate_operand" "n"))]
1040   "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1041    && !fp_operand (operands[0], VOIDmode)"
1042   "*
1043 {
1044   int part = s390_single_hi (operands[1], SImode, 0);
1045   operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1046
1047   switch (part)
1048     {
1049       case 0: return \"llilh\\t%0,%x1\";
1050       case 1: return \"llill\\t%0,%x1\";
1051       default: abort ();
1052     }
1053 }"
1054   [(set_attr "op_type" "RI")])
1055
1056 (define_insn "*movsi"
1057   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1058         (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1059   ""
1060   "@
1061    lr\\t%0,%1
1062    l\\t%0,%1
1063    st\\t%1,%0
1064    ler\\t%0,%1
1065    le\\t%0,%1
1066    ste\\t%1,%0
1067    mvc\\t%O0(4,%R0),%1"
1068   [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1069    (set_attr "atype"   "reg,mem,mem,reg,mem,mem,mem")])
1070
1071
1072 ;
1073 ; movhi instruction pattern(s).
1074 ;
1075
1076 (define_insn "movhi"
1077   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1078         (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1079   ""
1080   "@
1081    lr\\t%0,%1
1082    lhi\\t%0,%h1
1083    lh\\t%0,%1
1084    sth\\t%1,%0
1085    mvc\\t%O0(2,%R0),%1"
1086   [(set_attr "op_type" "RR,RI,RX,RX,SS")
1087    (set_attr "atype"   "reg,reg,mem,mem,mem")])
1088
1089
1090 ;
1091 ; movqi instruction pattern(s).
1092 ;
1093
1094 (define_insn "movqi_64"
1095   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1096         (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1097   "TARGET_64BIT"
1098   "@
1099    lr\\t%0,%1
1100    lhi\\t%0,%b1
1101    llgc\\t%0,%1
1102    stc\\t%1,%0
1103    mvi\\t%0,%b1
1104    mvc\\t%O0(1,%R0),%1"
1105   [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1106    (set_attr "atype"   "reg,reg,mem,mem,mem,mem")])
1107
1108
1109 (define_insn "movqi"
1110   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1111         (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1112   ""
1113   "@
1114    lr\\t%0,%1
1115    lhi\\t%0,%b1
1116    ic\\t%0,%1
1117    stc\\t%1,%0
1118    mvi\\t%0,%b1
1119    mvc\\t%O0(1,%R0),%1"
1120   [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1121    (set_attr "atype"   "reg,reg,mem,mem,mem,mem")])
1122
1123
1124 ;
1125 ; movstrictqi instruction pattern(s).
1126 ;
1127
1128 (define_insn "*movstrictqi"
1129   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1130                          (match_operand:QI 1 "memory_operand" "m"))]
1131   ""
1132   "ic\\t%0,%1"
1133   [(set_attr "op_type"  "RX")
1134    (set_attr "atype"    "mem")])
1135
1136 ;
1137 ; movstricthi instruction pattern(s).
1138 ;
1139
1140 (define_insn "*movstricthi"
1141   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1142                          (match_operand:HI 1 "s_imm_operand" "Q"))
1143    (clobber (reg:CC 33))]
1144   ""
1145   "icm\\t%0,3,%1"
1146   [(set_attr "op_type" "RS")
1147    (set_attr "atype"   "mem")])
1148
1149
1150 ;
1151 ; movstrictsi instruction pattern(s).
1152 ;
1153
1154 (define_insn "movstrictsi"
1155   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1156                          (match_operand:SI 1 "general_operand" "d,m"))]
1157   "TARGET_64BIT"
1158   "@
1159    lr\\t%0,%1
1160    l\\t%0,%1"
1161   [(set_attr "op_type" "RR,RS")
1162    (set_attr "atype"   "reg,mem")])
1163
1164
1165 ;
1166 ; movdf instruction pattern(s).
1167 ;
1168
1169 (define_expand "movdf"
1170   [(set (match_operand:DF 0 "nonimmediate_operand" "")
1171         (match_operand:DF 1 "general_operand"  ""))]
1172   ""
1173   "
1174 {
1175   /* During and after reload, we need to force constants
1176      to the literal pool ourselves, if necessary.  */
1177   if ((reload_in_progress || reload_completed)
1178       && CONSTANT_P (operands[1]))
1179     operands[1] = force_const_mem (DFmode, operands[1]);
1180 }")
1181
1182 (define_insn "*movdf_64"
1183   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1184         (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1185   "TARGET_64BIT"
1186   "@
1187    ldr\\t%0,%1
1188    ld\\t%0,%1
1189    std\\t%1,%0
1190    lgr\\t%0,%1
1191    lg\\t%0,%1
1192    stg\\t%1,%0
1193    mvc\\t%O0(8,%R0),%1"
1194   [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE,SS")
1195    (set_attr "atype"   "reg,mem,mem,reg,mem,mem,mem")])
1196
1197 (define_insn "*movdf_31"
1198   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1199         (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1200   "!TARGET_64BIT"
1201   "@
1202    ldr\\t%0,%1
1203    ld\\t%0,%1
1204    std\\t%1,%0
1205    lm\\t%0,%N0,%1
1206    stm\\t%1,%N1,%0
1207    #
1208    #
1209    mvc\\t%O0(8,%R0),%1"
1210   [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1211    (set_attr "atype"   "reg,mem,mem,mem,mem,*,*,mem")])
1212
1213 (define_split
1214   [(set (match_operand:DF 0 "nonimmediate_operand" "")
1215         (match_operand:DF 1 "general_operand" ""))]
1216   "!TARGET_64BIT && reload_completed
1217    && !fp_operand (operands[0], VOIDmode)
1218    && !fp_operand (operands[1], VOIDmode)
1219    && !s_operand (operands[0], VOIDmode)
1220    && !s_operand (operands[1], VOIDmode)
1221    && (register_operand (operands[0], VOIDmode)
1222        || register_operand (operands[1], VOIDmode))
1223    && (!register_operand (operands[0], VOIDmode)
1224        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1225                                     operands[1])
1226        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1227                                     operands[1]))"
1228   [(set (match_dup 2) (match_dup 4))
1229    (set (match_dup 3) (match_dup 5))]
1230   "
1231 {
1232   if (!register_operand (operands[0], VOIDmode)
1233       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1234                                    operands[1]))
1235     {
1236       operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1237       operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1238       operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1239       operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1240     }
1241   else
1242     {
1243       operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1244       operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1245       operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1246       operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1247     }
1248 }")
1249
1250 (define_split
1251   [(set (match_operand:DF 0 "register_operand" "")
1252         (match_operand:DF 1 "memory_operand" ""))]
1253   "!TARGET_64BIT && reload_completed
1254    && !fp_operand (operands[0], VOIDmode)
1255    && !fp_operand (operands[1], VOIDmode)
1256    && !s_operand (operands[1], VOIDmode)"
1257   [(set (match_dup 2) (match_dup 3))
1258    (set (match_dup 0) (mem:DI (match_dup 2)))]
1259   "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1260    operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1261
1262 ;
1263 ; movsf instruction pattern(s).
1264 ;
1265
1266 (define_expand "movsf"
1267   [(set (match_operand:SF 0 "nonimmediate_operand" "")
1268         (match_operand:SF 1 "general_operand"  ""))]
1269   ""
1270   "
1271 {
1272   /* During and after reload, we need to force constants
1273      to the literal pool ourselves, if necessary.  */
1274   if ((reload_in_progress || reload_completed)
1275       && CONSTANT_P (operands[1]))
1276     operands[1] = force_const_mem (SFmode, operands[1]);
1277 }")
1278
1279 (define_insn "*movsf"
1280   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1281         (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1282   ""
1283   "@
1284    ler\\t%0,%1
1285    le\\t%0,%1
1286    ste\\t%1,%0
1287    lr\\t%0,%1
1288    l\\t%0,%1
1289    st\\t%1,%0
1290    mvc\\t%O0(4,%R0),%1"
1291   [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1292    (set_attr "atype"   "reg,mem,mem,reg,mem,mem,mem")])
1293
1294 ;
1295 ; load_multiple pattern(s).
1296 ;
1297
1298 (define_expand "load_multiple"
1299   [(match_par_dup 3 [(set (match_operand 0 "" "")
1300                           (match_operand 1 "" ""))
1301                      (use (match_operand 2 "" ""))])]
1302   ""
1303   "
1304 {
1305   int regno;
1306   int count;
1307   rtx from;
1308   int i, off;
1309
1310   /* Support only loading a constant number of fixed-point registers from
1311      memory and only bother with this if more than two */
1312   if (GET_CODE (operands[2]) != CONST_INT
1313       || INTVAL (operands[2]) < 2
1314       || INTVAL (operands[2]) > 16
1315       || GET_CODE (operands[1]) != MEM
1316       || GET_CODE (operands[0]) != REG
1317       || REGNO (operands[0]) >= 16)
1318     FAIL;
1319
1320   count = INTVAL (operands[2]);
1321   regno = REGNO (operands[0]);
1322
1323   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1324   if (no_new_pseudos)
1325     {
1326       if (GET_CODE (XEXP (operands[1], 0)) == REG)
1327         {
1328           from = XEXP (operands[1], 0);
1329           off = 0;
1330         }
1331       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1332                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1333                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1334         {
1335           from = XEXP (XEXP (operands[1], 0), 0);
1336           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1337         }
1338       else
1339         FAIL;
1340
1341       if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1342         FAIL;
1343     }
1344   else
1345     {
1346       from = force_reg (Pmode, XEXP (operands[1], 0));
1347       off = 0;
1348     }
1349
1350   for (i = 0; i < count; i++)
1351     XVECEXP (operands[3], 0, i)
1352       = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1353                      change_address (operands[1], Pmode,
1354                                      plus_constant (from,
1355                                                     off + i * UNITS_PER_WORD)));
1356 }")
1357
1358 (define_insn "*load_multiple_di"
1359   [(match_parallel 0 "load_multiple_operation"
1360                    [(set (match_operand:DI 1 "register_operand" "=r")
1361                          (match_operand:DI 2 "s_operand" "Q"))])]
1362   ""
1363   "*
1364 {
1365   int words = XVECLEN (operands[0], 0);
1366
1367   if (XVECLEN (operands[0], 0) == 1)
1368     return \"lg\\t%1,0(%2)\";
1369
1370   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1371     return \"lmg\\t%1,%0,%2\";
1372 }"
1373    [(set_attr "op_type" "RXE")
1374     (set_attr "atype"   "mem")
1375     (set_attr "type"    "lm")])
1376
1377 (define_insn "*load_multiple_si"
1378   [(match_parallel 0 "load_multiple_operation"
1379                    [(set (match_operand:SI 1 "register_operand" "=r")
1380                          (match_operand:SI 2 "s_operand" "Q"))])]
1381   ""
1382   "*
1383 {
1384   int words = XVECLEN (operands[0], 0);
1385
1386   if (XVECLEN (operands[0], 0) == 1)
1387     return \"l\\t%1,0(%2)\";
1388
1389   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1390     return \"lm\\t%1,%0,%2\";
1391 }"
1392    [(set_attr "op_type" "RXE")
1393     (set_attr "atype"   "mem")
1394     (set_attr "type"    "lm")])
1395
1396 ;
1397 ; store multiple pattern(s).
1398 ;
1399
1400 (define_expand "store_multiple"
1401   [(match_par_dup 3 [(set (match_operand 0 "" "")
1402                           (match_operand 1 "" ""))
1403                      (use (match_operand 2 "" ""))])]
1404   ""
1405   "
1406 {
1407   int regno;
1408   int count;
1409   rtx to;
1410   int i, off;
1411
1412   /* Support only storing a constant number of fixed-point registers to
1413      memory and only bother with this if more than two.  */
1414   if (GET_CODE (operands[2]) != CONST_INT
1415       || INTVAL (operands[2]) < 2
1416       || INTVAL (operands[2]) > 16
1417       || GET_CODE (operands[0]) != MEM
1418       || GET_CODE (operands[1]) != REG
1419       || REGNO (operands[1]) >= 16)
1420     FAIL;
1421
1422   count = INTVAL (operands[2]);
1423   regno = REGNO (operands[1]);
1424
1425   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1426
1427   if (no_new_pseudos)
1428     {
1429       if (GET_CODE (XEXP (operands[0], 0)) == REG)
1430         {
1431           to = XEXP (operands[0], 0);
1432           off = 0;
1433         }
1434       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1435                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1436                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1437         {
1438           to = XEXP (XEXP (operands[0], 0), 0);
1439           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1440         }
1441       else
1442         FAIL;
1443
1444       if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1445         FAIL;
1446     }
1447   else
1448     {
1449       to = force_reg (Pmode, XEXP (operands[0], 0));
1450       off = 0;
1451     }
1452
1453   for (i = 0; i < count; i++)
1454     XVECEXP (operands[3], 0, i)
1455       = gen_rtx_SET (VOIDmode,
1456                      change_address (operands[0], Pmode,
1457                                      plus_constant (to,
1458                                                     off + i * UNITS_PER_WORD)),
1459                      gen_rtx_REG (Pmode, regno + i));
1460 }")
1461
1462 (define_insn "*store_multiple_di"
1463   [(match_parallel 0 "store_multiple_operation"
1464                    [(set (match_operand:DI 1 "s_operand" "=Q")
1465                          (match_operand:DI 2 "register_operand" "r"))])]
1466   ""
1467   "*
1468 {
1469   int words = XVECLEN (operands[0], 0);
1470
1471   if (XVECLEN (operands[0], 0) == 1)
1472     return \"stg\\t%1,0(%2)\";
1473
1474   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1475     return \"stmg\\t%2,%0,%1\";
1476 }"
1477    [(set_attr "op_type" "RXE")
1478     (set_attr "atype"   "mem")
1479     (set_attr "type"    "stm")])
1480
1481
1482 (define_insn "*store_multiple_si"
1483   [(match_parallel 0 "store_multiple_operation"
1484                    [(set (match_operand:SI 1 "s_operand" "=Q")
1485                          (match_operand:SI 2 "register_operand" "r"))])]
1486   ""
1487   "*
1488 {
1489   int words = XVECLEN (operands[0], 0);
1490
1491   if (XVECLEN (operands[0], 0) == 1)
1492     return \"st\\t%1,0(%2)\";
1493
1494   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1495     return \"stm\\t%2,%0,%1\";
1496 }"
1497    [(set_attr "op_type" "RXE")
1498     (set_attr "atype"   "mem")
1499     (set_attr "type"    "stm")])
1500
1501 ;;
1502 ;; String instructions.
1503 ;;
1504
1505 ;
1506 ; movstrdi instruction pattern(s).
1507 ;
1508
1509 (define_expand "movstrdi"
1510    [(set (match_operand:BLK 0 "general_operand" "")
1511          (match_operand:BLK 1 "general_operand" ""))
1512     (use (match_operand:DI 2 "general_operand" ""))
1513     (match_operand 3 "" "")]
1514     "TARGET_64BIT"
1515     "
1516 {
1517   rtx addr0, addr1;
1518
1519   addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1520   addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1521
1522   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1523     {
1524       operands[0] = change_address (operands[0], VOIDmode, addr0);
1525       operands[1] = change_address (operands[1], VOIDmode, addr1);
1526       operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1527
1528       emit_insn (gen_movstrdi_short (operands[0], operands[1], operands[2]));
1529       DONE;
1530     }
1531   else
1532     {
1533       if (TARGET_MVCLE)
1534         {
1535           /* implementation suggested by  Richard Henderson <rth@cygnus.com> */
1536           rtx reg0 = gen_reg_rtx (TImode);
1537           rtx reg1 = gen_reg_rtx (TImode);
1538           rtx len = operands[2];
1539
1540           if (! CONSTANT_P (len))
1541             len = force_reg (DImode, len);
1542
1543           /* Load up the address+length pairs.  */
1544
1545           emit_move_insn (gen_highpart (DImode, reg0), addr0);
1546           emit_move_insn (gen_lowpart (DImode, reg0), len);
1547
1548           emit_move_insn (gen_highpart (DImode, reg1), addr1);
1549           emit_move_insn (gen_lowpart (DImode, reg1), len);
1550
1551           /* MOVE */
1552           emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
1553           DONE;
1554         }
1555       else
1556         {
1557           rtx label1 = gen_label_rtx ();
1558           rtx label2 = gen_label_rtx ();
1559           rtx reg0, reg1, len, blocks;
1560
1561           reg0 = gen_reg_rtx (DImode);
1562           reg1 = gen_reg_rtx (DImode);
1563           len = gen_reg_rtx (DImode);
1564           blocks = gen_reg_rtx (DImode);
1565
1566           emit_move_insn (len, operands[2]);
1567           emit_insn (gen_cmpdi (len, const0_rtx));
1568           emit_jump_insn (gen_beq (label1));
1569           emit_move_insn (reg0, addr0);
1570           emit_move_insn (reg1, addr1);
1571           emit_insn (gen_adddi3 (len, len, constm1_rtx));
1572           emit_insn (gen_ashrdi3 (blocks, len, GEN_INT (8)));
1573           emit_insn (gen_cmpdi (blocks, const0_rtx));
1574           emit_jump_insn (gen_beq (label2));
1575           emit_insn (gen_movstrdi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1576           emit_label (label2);
1577           operands[0] = change_address (operands[0], VOIDmode, reg0);
1578           operands[1] = change_address (operands[1], VOIDmode, reg1);
1579           emit_insn (gen_movstrdi_short (operands[0], operands[1], len));
1580           emit_label (label1);
1581           DONE;
1582        }
1583     }
1584 }")
1585
1586 ;
1587 ; movstrsi instruction pattern(s).
1588 ;
1589
1590 (define_expand "movstrsi"
1591    [(set (match_operand:BLK 0 "general_operand" "")
1592          (match_operand:BLK 1 "general_operand" ""))
1593     (use (match_operand:SI 2 "general_operand" ""))
1594     (match_operand 3 "" "")]
1595     "!TARGET_64BIT"
1596     "
1597 {
1598   rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1599   rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1600
1601   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1602     {
1603       operands[0] = change_address (operands[0], VOIDmode, addr0);
1604       operands[1] = change_address (operands[1], VOIDmode, addr1);
1605       operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1606
1607       emit_insn (gen_movstrsi_short (operands[0], operands[1], operands[2]));
1608       DONE;
1609     }
1610   else
1611     {
1612       if (TARGET_MVCLE)
1613         {
1614           /* implementation suggested by  Richard Henderson <rth@cygnus.com> */
1615           rtx reg0 = gen_reg_rtx (DImode);
1616           rtx reg1 = gen_reg_rtx (DImode);
1617           rtx len = operands[2];
1618
1619
1620           if (! CONSTANT_P (len))
1621             len = force_reg (SImode, len);
1622
1623           /* Load up the address+length pairs.  */
1624
1625           emit_move_insn (gen_highpart (SImode, reg0), addr0);
1626           emit_move_insn (gen_lowpart (SImode, reg0), len);
1627
1628           emit_move_insn (gen_highpart (SImode, reg1), addr1);
1629           emit_move_insn (gen_lowpart (SImode, reg1), len);
1630
1631           /* MOVE */
1632           emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
1633           DONE;
1634         }
1635       else
1636         {
1637           rtx label1 = gen_label_rtx ();
1638           rtx label2 = gen_label_rtx ();
1639           rtx reg0, reg1, len, blocks;
1640
1641           reg0 = gen_reg_rtx (SImode);
1642           reg1 = gen_reg_rtx (SImode);
1643           len = gen_reg_rtx (SImode);
1644           blocks = gen_reg_rtx (SImode);
1645
1646           emit_move_insn (len, operands[2]);
1647           emit_insn (gen_cmpsi (len, const0_rtx));
1648           emit_jump_insn (gen_beq (label1));
1649           emit_move_insn (reg0, addr0);
1650           emit_move_insn (reg1, addr1);
1651           emit_insn (gen_addsi3 (len, len, constm1_rtx));
1652           emit_insn (gen_ashrsi3 (blocks, len, GEN_INT (8)));
1653           emit_insn (gen_cmpsi (blocks, const0_rtx));
1654           emit_jump_insn (gen_beq (label2));
1655           emit_insn (gen_movstrsi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1656           emit_label (label2);
1657           operands[0] = change_address (operands[0], VOIDmode, reg0);
1658           operands[1] = change_address (operands[1], VOIDmode, reg1);
1659           emit_insn (gen_movstrsi_short (operands[0], operands[1], len));
1660           emit_label (label1);
1661           DONE;
1662        }
1663     }
1664 }")
1665
1666 ; Move a block that is up to 256 bytes in length.
1667 ; The block length is taken as (operands[2] % 256) + 1.
1668
1669 (define_insn "movstrdi_short"
1670   [(set (match_operand:BLK 0 "s_operand" "=Q,Q")
1671         (match_operand:BLK 1 "s_operand" "Q,Q"))
1672    (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1673    (clobber (match_scratch:DI 3 "=X,&a"))]
1674   "TARGET_64BIT"
1675   "*
1676 {
1677   switch (which_alternative)
1678     {
1679       case 0:
1680         return \"mvc\\t%O0(%b2+1,%R0),%1\";
1681
1682       case 1:
1683         output_asm_insn (\"bras\\t%3,.+10\", operands);
1684         output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1685         return \"ex\\t%2,0(%3)\";
1686
1687       default:
1688         abort ();
1689     }
1690 }"
1691   [(set_attr "op_type" "SS,NN")
1692    (set_attr "atype"   "mem,mem")
1693    (set_attr "length"  "*,14")])
1694
1695 (define_insn "movstrsi_short"
1696   [(set (match_operand:BLK 0 "s_operand" "=Q,Q")
1697         (match_operand:BLK 1 "s_operand" "Q,Q"))
1698    (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1699    (clobber (match_scratch:SI 3 "=X,&a"))]
1700   "!TARGET_64BIT"
1701   "*
1702 {
1703   switch (which_alternative)
1704     {
1705       case 0:
1706         return \"mvc\\t%O0(%b2+1,%R0),%1\";
1707
1708       case 1:
1709         output_asm_insn (\"bras\\t%3,.+10\", operands);
1710         output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1711         return \"ex\\t%2,0(%3)\";
1712
1713       default:
1714         abort ();
1715     }
1716 }"
1717   [(set_attr "op_type" "SS,NN")
1718    (set_attr "atype"   "mem,mem")
1719    (set_attr "length"  "*,14")])
1720
1721 ; Move a block that is a multiple of 256 bytes in length
1722
1723 (define_insn "movstrdi_long"
1724   [(set (match_operand:DI 4 "register_operand" "=d")
1725         (const_int 0))
1726    (set (match_operand:DI 0 "register_operand" "=a")
1727         (plus:DI (match_operand:DI 2 "register_operand" "0")
1728                  (ashift:DI (match_operand:DI 5 "register_operand" "4")
1729                             (const_int 8))))
1730    (set (match_operand:DI 1 "register_operand" "=a")
1731         (plus:DI (match_operand:DI 3 "register_operand" "1")
1732                  (ashift:DI (match_dup 5) (const_int 8))))
1733    (set (mem:BLK (match_dup 2))
1734         (mem:BLK (match_dup 3)))
1735    (use (match_dup 5))]
1736   "TARGET_64BIT"
1737   "*
1738 {
1739   output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1740   output_asm_insn (\"la\\t%0,256(%0)\", operands);
1741   output_asm_insn (\"la\\t%1,256(%1)\", operands);
1742   return \"brct\\t%4,.-14\";
1743 }"
1744   [(set_attr "op_type" "NN")
1745    (set_attr "atype"   "mem")
1746    (set_attr "length"  "18")])
1747
1748 (define_insn "movstrsi_long"
1749   [(set (match_operand:SI 4 "register_operand" "=d")
1750         (const_int 0))
1751    (set (match_operand:SI 0 "register_operand" "=a")
1752         (plus:SI (match_operand:SI 2 "register_operand" "0")
1753                  (ashift:SI (match_operand:SI 5 "register_operand" "4")
1754                             (const_int 8))))
1755    (set (match_operand:SI 1 "register_operand" "=a")
1756         (plus:SI (match_operand:SI 3 "register_operand" "1")
1757                  (ashift:SI (match_dup 5) (const_int 8))))
1758    (set (mem:BLK (match_dup 2))
1759         (mem:BLK (match_dup 3)))
1760    (use (match_dup 5))]
1761   "!TARGET_64BIT"
1762   "*
1763 {
1764   output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1765   output_asm_insn (\"la\\t%0,256(%0)\", operands);
1766   output_asm_insn (\"la\\t%1,256(%1)\", operands);
1767   return \"brct\\t%4,.-14\";
1768 }"
1769   [(set_attr "op_type" "NN")
1770    (set_attr "atype"   "mem")
1771    (set_attr "length"  "18")])
1772
1773 ; Move a block that is larger than 255 bytes in length.
1774
1775 (define_insn "movstrdi_64"
1776   [(set (match_operand:TI 0 "register_operand" "=d")
1777         (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1778                             (lshiftrt:TI (match_dup 2) (const_int 64)))
1779                    (const_int 64)))
1780    (set (match_operand:TI 1 "register_operand" "=d")
1781         (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1782                             (lshiftrt:TI (match_dup 3) (const_int 64)))
1783                    (const_int 64)))
1784    (set (mem:BLK (subreg:DI (match_dup 2) 0))
1785         (mem:BLK (subreg:DI (match_dup 3) 0)))
1786    (clobber (reg:CC 33))]
1787   "TARGET_64BIT"
1788   "mvcle\\t%0,%1,0\;jo\\t.-4"
1789   [(set_attr "op_type" "NN")
1790    (set_attr "atype"   "mem")
1791    (set_attr "length"  "8")])
1792
1793 (define_insn "movstrsi_31"
1794   [(set (match_operand:DI 0 "register_operand" "=d")
1795         (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1796                             (lshiftrt:DI (match_dup 2) (const_int 32)))
1797                    (const_int 32)))
1798    (set (match_operand:DI 1 "register_operand" "=d")
1799         (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1800                             (lshiftrt:DI (match_dup 3) (const_int 32)))
1801                    (const_int 32)))
1802    (set (mem:BLK (subreg:SI (match_dup 2) 0))
1803         (mem:BLK (subreg:SI (match_dup 3) 0)))
1804    (clobber (reg:CC 33))]
1805   "!TARGET_64BIT"
1806   "mvcle\\t%0,%1,0\;jo\\t.-4"
1807    [(set_attr "op_type" "NN")
1808     (set_attr "atype" "mem")
1809     (set_attr "length"  "8")])
1810
1811 ;
1812 ; clrstrdi instruction pattern(s).
1813 ;
1814
1815 (define_expand "clrstrdi"
1816   [(set (match_operand:BLK 0 "general_operand" "")
1817         (const_int 0))
1818    (use (match_operand:DI 1 "general_operand" ""))
1819    (match_operand 2 "" "")]
1820   "TARGET_64BIT"
1821   "
1822 {
1823    rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1824
1825    operands[0] = change_address (operands[0], VOIDmode, addr);
1826
1827    if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1828      {
1829         emit_insn (gen_clrstrsico (operands[0], operands[1]));
1830         DONE;
1831      }
1832    else
1833      {
1834       rtx reg0 = gen_reg_rtx (TImode);
1835       rtx reg1 = gen_reg_rtx (TImode);
1836       rtx len = operands[1];
1837
1838       if (! CONSTANT_P (len))
1839           len = force_reg (DImode, len);
1840
1841       /* Load up the address+length pairs.  */
1842
1843       emit_move_insn (gen_highpart (DImode, reg0), addr);
1844       emit_move_insn (gen_lowpart (DImode, reg0), len);
1845
1846       emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
1847
1848       /* Clear! */
1849       emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0));
1850       DONE;
1851      }
1852 }")
1853
1854 ;
1855 ; clrstrsi instruction pattern(s).
1856 ;
1857
1858 (define_expand "clrstrsi"
1859   [(set (match_operand:BLK 0 "general_operand" "")
1860         (const_int 0))
1861    (use (match_operand:SI 1 "general_operand" ""))
1862    (match_operand 2 "" "")]
1863    "!TARGET_64BIT"
1864    "
1865 {
1866    rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1867
1868    operands[0] = change_address (operands[0], VOIDmode, addr);
1869
1870    if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1871      {
1872         emit_insn (gen_clrstrsico (operands[0], operands[1]));
1873         DONE;
1874      }
1875    else
1876      {
1877       rtx reg0 = gen_reg_rtx (DImode);
1878       rtx reg1 = gen_reg_rtx (DImode);
1879       rtx len = operands[1];
1880
1881       if (! CONSTANT_P (len))
1882           len = force_reg (SImode, len);
1883
1884       /* Load up the address+length pairs.  */
1885
1886       emit_move_insn (gen_highpart (SImode, reg0), addr);
1887       emit_move_insn (gen_lowpart (SImode, reg0), len);
1888
1889       emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
1890
1891       /* CLear! */
1892       emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0));
1893       DONE;
1894      }
1895 }")
1896
1897 ; Clear memory with length less than 256 bytes
1898
1899 (define_insn "clrstrsico"
1900   [(set (match_operand:BLK 0 "s_operand" "=Q")
1901         (const_int 0))
1902    (use (match_operand 1 "immediate_operand" "I"))
1903    (clobber (reg:CC 33))]
1904   ""
1905   "xc\\t%O0(%1,%R0),%0"
1906   [(set_attr "op_type" "RS")
1907    (set_attr "type"    "cs")
1908    (set_attr "atype"   "mem")])
1909
1910 ; Clear memory with length greater 256 bytes or lenght not constant
1911
1912 (define_insn "clrstrsi_64"
1913   [(set (match_operand:TI 0 "register_operand" "=d")
1914         (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1915                             (lshiftrt:TI (match_dup 2) (const_int 64)))
1916                    (const_int 64)))
1917    (set (mem:BLK (subreg:DI (match_dup 2) 0))
1918         (const_int 0))
1919    (use (match_operand:TI 1 "register_operand" "d"))
1920    (clobber (reg:CC 33))]
1921   "TARGET_64BIT"
1922   "mvcle\\t%0,%1,0\;jo\\t.-4"
1923   [(set_attr "op_type" "NN")
1924    (set_attr "atype"   "mem")
1925    (set_attr "type"    "vs")
1926    (set_attr "length"  "8")])
1927
1928 (define_insn "clrstrsi_31"
1929   [(set (match_operand:DI 0 "register_operand" "=d")
1930         (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1931                             (lshiftrt:DI (match_dup 2) (const_int 32)))
1932                    (const_int 32)))
1933    (set (mem:BLK (subreg:SI (match_dup 2) 0))
1934         (const_int 0))
1935    (use (match_operand:DI 1 "register_operand" "d"))
1936    (clobber (reg:CC 33))]
1937   "!TARGET_64BIT"
1938   "mvcle\\t%0,%1,0\;jo\\t.-4"
1939   [(set_attr "op_type" "NN")
1940    (set_attr "atype"   "mem")
1941    (set_attr "type"    "vs")
1942    (set_attr "length"  "8")])
1943
1944 ;
1945 ; cmpstrdi instruction pattern(s).
1946 ;
1947
1948 (define_expand "cmpstrdi"
1949    [(set (match_operand:DI 0 "register_operand" "")
1950          (compare:DI (match_operand:BLK 1 "general_operand" "")
1951                   (match_operand:BLK 2 "general_operand" "") ) )
1952              (use (match_operand:DI 3  "general_operand" ""))
1953              (use (match_operand:DI 4  "" ""))]
1954    "TARGET_64BIT"
1955    "
1956 {
1957   rtx addr0, addr1;
1958
1959   /* for pre/post increment */
1960   operands[1] = protect_from_queue (operands[1], 0);
1961   operands[2] = protect_from_queue (operands[2], 0);
1962   operands[3] = protect_from_queue (operands[3], 0);
1963
1964   addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1965   addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1966
1967   if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1968     {
1969       if (INTVAL (operands[3]) == 0) {
1970         emit_move_insn (operands[0], operands[3]);
1971         DONE;
1972       }
1973
1974       operands[1] = change_address (operands[1], VOIDmode, addr0);
1975       operands[2] = change_address (operands[2], VOIDmode, addr1);
1976
1977       emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1978       emit_insn (gen_cmpint_di (operands[0]));
1979       DONE;
1980     }
1981   else
1982     {
1983       /* implementation suggested by  Richard Henderson <rth@cygnus.com> */
1984       rtx reg0 = gen_reg_rtx (TImode);
1985       rtx reg1 = gen_reg_rtx (TImode);
1986       rtx len = operands[3];
1987
1988       if (! CONSTANT_P (len))
1989           len = force_reg (DImode, len);
1990
1991       /* Load up the address+length pairs.  */
1992       emit_move_insn (gen_highpart (DImode, reg0), addr0);
1993       emit_move_insn (gen_lowpart (DImode, reg0), len);
1994
1995       emit_move_insn (gen_highpart (DImode, reg1), addr1);
1996       emit_move_insn (gen_lowpart (DImode, reg1), len);
1997
1998       /* Compare! */
1999       emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2000       emit_insn (gen_cmpint_di (operands[0]));
2001       DONE;
2002     }
2003 }")
2004
2005 ;
2006 ; cmpstrsi instruction pattern(s).
2007 ;
2008
2009 (define_expand "cmpstrsi"
2010    [(set (match_operand:SI 0 "register_operand" "")
2011          (compare:SI (match_operand:BLK 1 "general_operand" "")
2012                   (match_operand:BLK 2 "general_operand" "") ) )
2013              (use (match_operand:SI 3  "general_operand" ""))
2014              (use (match_operand:SI 4  "" ""))]
2015    ""
2016    "
2017 {
2018   rtx addr0, addr1;
2019
2020   /* for pre/post increment */
2021   operands[1] = protect_from_queue (operands[1], 0);
2022   operands[2] = protect_from_queue (operands[2], 0);
2023   operands[3] = protect_from_queue (operands[3], 0);
2024
2025   addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2026   addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2027
2028   if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2029     {
2030       if (INTVAL (operands[3]) == 0) {
2031         emit_move_insn (operands[0], operands[3]);
2032         DONE;
2033       }
2034
2035       operands[1] = change_address (operands[1], VOIDmode, addr0);
2036       operands[2] = change_address (operands[2], VOIDmode, addr1);
2037
2038       emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2039       emit_insn (gen_cmpint_si (operands[0]));
2040       DONE;
2041     }
2042   else
2043     {
2044       /* implementation suggested by  Richard Henderson <rth@cygnus.com> */
2045       rtx reg0, reg1;
2046       rtx len = operands[3];
2047
2048       if (TARGET_64BIT)
2049         {
2050           reg0 = gen_reg_rtx (TImode);
2051           reg1 = gen_reg_rtx (TImode);
2052         }
2053       else
2054         {
2055           reg0 = gen_reg_rtx (DImode);
2056           reg1 = gen_reg_rtx (DImode);
2057         }
2058
2059       if (! CONSTANT_P (len))
2060           len = force_reg (Pmode, len);
2061
2062       /* Load up the address+length pairs.  */
2063       emit_move_insn (gen_highpart (Pmode, reg0), addr0);
2064       emit_move_insn (gen_lowpart (Pmode, reg0), len);
2065
2066       emit_move_insn (gen_highpart (Pmode, reg1), addr1);
2067       emit_move_insn (gen_lowpart (Pmode, reg1), len);
2068
2069       /* Compare! */
2070       if (TARGET_64BIT)
2071           emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2072       else
2073           emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
2074
2075       emit_insn (gen_cmpint_si (operands[0]));
2076       DONE;
2077     }
2078 }")
2079
2080 ; Compare a block that is less than 256 bytes in length.
2081
2082 (define_insn "cmpstr_const"
2083   [(set (reg:CCS 33)
2084         (compare:CCS (match_operand:BLK 0 "s_operand" "Q")
2085                      (match_operand:BLK 1 "s_operand" "Q")))
2086    (use (match_operand 2 "immediate_operand" "I"))]
2087   "(unsigned) INTVAL (operands[2]) < 256"
2088   "clc\\t%O0(%c2,%R0),%1"
2089   [(set_attr "op_type" "SS")
2090    (set_attr "atype"   "mem")
2091    (set_attr "type"    "cs")])
2092
2093 ; Compare a block that is larger than 255 bytes in length.
2094
2095 (define_insn "cmpstr_64"
2096   [(clobber (match_operand:TI 0 "register_operand" "=d"))
2097    (clobber (match_operand:TI 1 "register_operand" "=d"))
2098    (set (reg:CCS 33)
2099         (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2100                      (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2101    (use (match_dup 2))
2102    (use (match_dup 3))]
2103   "TARGET_64BIT"
2104   "clcl\\t%0,%1"
2105   [(set_attr "op_type" "RR")
2106    (set_attr "atype"   "mem")
2107    (set_attr "type"    "vs")])
2108
2109 (define_insn "cmpstr_31"
2110   [(clobber (match_operand:DI 0 "register_operand" "=d"))
2111    (clobber (match_operand:DI 1 "register_operand" "=d"))
2112    (set (reg:CCS 33)
2113         (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2114                      (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2115    (use (match_dup 2))
2116    (use (match_dup 3))]
2117   "!TARGET_64BIT"
2118   "clcl\\t%0,%1"
2119   [(set_attr "op_type" "RR")
2120    (set_attr "atype"   "mem")
2121    (set_attr "type"    "vs")])
2122
2123 ; Convert condition code to integer in range (-1, 0, 1)
2124
2125 (define_insn "cmpint_si"
2126   [(set (match_operand:SI 0 "register_operand" "=d")
2127         (compare:SI (reg:CCS 33) (const_int 0)))]
2128   ""
2129   "*
2130 {
2131    output_asm_insn (\"lhi\\t%0,1\", operands);
2132    output_asm_insn (\"jh\\t.+12\", operands);
2133    output_asm_insn (\"jl\\t.+6\", operands);
2134    output_asm_insn (\"sr\\t%0,%0\", operands);
2135    return \"lcr\\t%0,%0\";
2136 }"
2137   [(set_attr "op_type" "NN")
2138    (set_attr "length"  "16")
2139    (set_attr "atype"   "reg")
2140    (set_attr "type"    "other")])
2141
2142 (define_insn "cmpint_di"
2143   [(set (match_operand:DI 0 "register_operand" "=d")
2144         (compare:DI (reg:CCS 33) (const_int 0)))]
2145   "TARGET_64BIT"
2146   "*
2147 {
2148    output_asm_insn (\"lghi\\t%0,1\", operands);
2149    output_asm_insn (\"jh\\t.+12\", operands);
2150    output_asm_insn (\"jl\\t.+6\", operands);
2151    output_asm_insn (\"sgr\\t%0,%0\", operands);
2152    return \"lcgr\\t%0,%0\";
2153 }"
2154   [(set_attr "op_type" "NN")
2155    (set_attr "length"  "22")
2156    (set_attr "atype"   "reg")
2157    (set_attr "type"    "other")])
2158
2159
2160 ;;
2161 ;;- Conversion instructions.
2162 ;;
2163
2164 (define_insn "*sethighqisi"
2165   [(set (match_operand:SI 0 "register_operand" "=d")
2166         (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
2167    (clobber (reg:CC 33))]
2168   ""
2169   "icm\\t%0,8,%1"
2170   [(set_attr "op_type" "RS")
2171    (set_attr "atype"   "mem")])
2172
2173 (define_insn "*sethighhisi"
2174   [(set (match_operand:SI 0 "register_operand" "=d")
2175         (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
2176    (clobber (reg:CC 33))]
2177   ""
2178   "icm\\t%0,12,%1"
2179   [(set_attr "op_type" "RS")
2180    (set_attr "atype"   "mem")])
2181
2182 (define_insn "*sethighqidi_64"
2183   [(set (match_operand:DI 0 "register_operand" "=d")
2184         (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2185    (clobber (reg:CC 33))]
2186   "TARGET_64BIT"
2187   "icmh\\t%0,8,%1"
2188   [(set_attr "op_type" "RSE")
2189    (set_attr "atype"   "mem")])
2190
2191 (define_insn "*sethighqidi_31"
2192   [(set (match_operand:DI 0 "register_operand" "=d")
2193         (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2194    (clobber (reg:CC 33))]
2195   "!TARGET_64BIT"
2196   "icm\\t%0,8,%1"
2197   [(set_attr "op_type" "RS")
2198    (set_attr "atype"   "mem")])
2199
2200 (define_split
2201   [(set (match_operand:SI 0 "register_operand" "")
2202         (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2203                          (match_operand 2 "const_int_operand" "")
2204                          (const_int 0)))]
2205   "!TARGET_64BIT && !reload_completed
2206    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2207   [(parallel
2208     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2209      (clobber (reg:CC 33))])
2210     (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2211   "
2212 {
2213   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2214   operands[1] = change_address (operands[1], QImode, 0);
2215 }")
2216
2217 (define_split
2218   [(set (match_operand:SI 0 "register_operand" "")
2219         (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2220                          (match_operand 2 "const_int_operand" "")
2221                          (const_int 0)))]
2222   "!TARGET_64BIT && !reload_completed
2223    && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2224   [(parallel
2225     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2226      (clobber (reg:CC 33))])
2227     (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2228   "
2229 {
2230   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2231   operands[1] = change_address (operands[1], HImode, 0);
2232 }")
2233
2234 ;
2235 ; extendsidi2 instruction pattern(s).
2236 ;
2237
2238 (define_expand "extendsidi2"
2239   [(set (match_operand:DI 0 "register_operand" "")
2240         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2241   ""
2242   "
2243 {
2244   if (!TARGET_64BIT)
2245     {
2246       emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2247       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2248       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2249       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2250       DONE;
2251     }
2252 }
2253 ")
2254
2255 (define_insn "*extendsidi2"
2256   [(set (match_operand:DI 0 "register_operand" "=d,d")
2257         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2258   "TARGET_64BIT"
2259   "@
2260    lgfr\\t%0,%1
2261    lgf\\t%0,%1"
2262   [(set_attr "op_type" "RRE,RXE")
2263    (set_attr "atype"   "reg,mem")])
2264
2265 ;
2266 ; extendhidi2 instruction pattern(s).
2267 ;
2268
2269 (define_expand "extendhidi2"
2270   [(set (match_operand:DI 0 "register_operand" "")
2271         (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2272   ""
2273   "
2274 {
2275   if (!TARGET_64BIT)
2276     {
2277       rtx tmp = gen_reg_rtx (SImode);
2278       emit_insn (gen_extendhisi2 (tmp, operands[1]));
2279       emit_insn (gen_extendsidi2 (operands[0], tmp));
2280       DONE;
2281     }
2282   else
2283     {
2284       operands[1] = gen_lowpart (DImode, operands[1]);
2285       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2286       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2287       DONE;
2288     }
2289 }
2290 ")
2291
2292 (define_insn "*extendhidi2"
2293   [(set (match_operand:DI 0 "register_operand" "=d")
2294         (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2295   "TARGET_64BIT"
2296   "lgh\\t%0,%1"
2297   [(set_attr "op_type" "RXE")
2298    (set_attr "atype"   "mem")])
2299
2300 ;
2301 ; extendqidi2 instruction pattern(s).
2302 ;
2303
2304 (define_expand "extendqidi2"
2305   [(set (match_operand:DI 0 "register_operand" "")
2306         (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2307   ""
2308   "
2309 {
2310   if (!TARGET_64BIT)
2311     {
2312       rtx tmp = gen_reg_rtx (SImode);
2313       emit_insn (gen_extendqisi2 (tmp, operands[1]));
2314       emit_insn (gen_extendsidi2 (operands[0], tmp));
2315       DONE;
2316     }
2317   else
2318     {
2319       operands[1] = gen_lowpart (DImode, operands[1]);
2320       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2321       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2322       DONE;
2323     }
2324 }
2325 ")
2326
2327 (define_split
2328   [(set (match_operand:DI 0 "register_operand" "")
2329         (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2330   "TARGET_64BIT && !reload_completed"
2331   [(parallel
2332     [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2333      (clobber (reg:CC 33))])
2334    (parallel
2335     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2336      (clobber (reg:CC 33))])]
2337   "")
2338
2339 ;
2340 ; extendhisi2 instruction pattern(s).
2341 ;
2342
2343 (define_expand "extendhisi2"
2344   [(set (match_operand:SI 0 "register_operand" "")
2345         (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2346   ""
2347   "
2348 {
2349   operands[1] = gen_lowpart (SImode, operands[1]);
2350   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2351   emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2352   DONE;
2353 }
2354 ")
2355
2356 (define_insn "*extendhisi2"
2357   [(set (match_operand:SI 0 "register_operand" "=d")
2358         (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2359   ""
2360   "lh\\t%0,%1"
2361   [(set_attr "op_type" "RX")
2362    (set_attr "atype"   "mem")])
2363
2364 ;
2365 ; extendqisi2 instruction pattern(s).
2366 ;
2367
2368 (define_expand "extendqisi2"
2369   [(set (match_operand:SI 0 "register_operand" "")
2370         (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2371   ""
2372   "
2373 {
2374   operands[1] = gen_lowpart (SImode, operands[1]);
2375   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2376   emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2377   DONE;
2378 }
2379 ")
2380
2381 (define_split
2382   [(set (match_operand:SI 0 "register_operand" "")
2383         (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2384   "!reload_completed"
2385   [(parallel
2386     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2387      (clobber (reg:CC 33))])
2388    (parallel
2389     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2390      (clobber (reg:CC 33))])]
2391   "")
2392
2393 ;
2394 ; extendqihi2 instruction pattern(s).
2395 ;
2396
2397
2398 ;
2399 ; zero_extendsidi2 instruction pattern(s).
2400 ;
2401
2402 (define_expand "zero_extendsidi2"
2403   [(set (match_operand:DI 0 "register_operand" "")
2404         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2405   ""
2406   "
2407 {
2408   if (!TARGET_64BIT)
2409     {
2410       emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2411       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2412       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2413       DONE;
2414     }
2415 }
2416 ")
2417
2418 (define_insn "*zero_extendsidi2"
2419   [(set (match_operand:DI 0 "register_operand" "=d,d")
2420         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2421   "TARGET_64BIT"
2422   "@
2423    llgfr\\t%0,%1
2424    llgf\\t%0,%1"
2425   [(set_attr "op_type" "RRE,RXE")
2426    (set_attr "atype"   "reg,mem")])
2427
2428 ;
2429 ; zero_extendhidi2 instruction pattern(s).
2430 ;
2431
2432 (define_expand "zero_extendhidi2"
2433   [(set (match_operand:DI 0 "register_operand" "")
2434         (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2435   ""
2436   "
2437 {
2438   if (!TARGET_64BIT)
2439     {
2440       rtx tmp = gen_reg_rtx (SImode);
2441       emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2442       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2443       DONE;
2444     }
2445   else
2446     {
2447       operands[1] = gen_lowpart (DImode, operands[1]);
2448       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2449       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2450       DONE;
2451     }
2452 }
2453 ")
2454
2455 (define_insn "*zero_extendhidi2"
2456   [(set (match_operand:DI 0 "register_operand" "=d")
2457         (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2458   "TARGET_64BIT"
2459   "llgh\\t%0,%1"
2460   [(set_attr "op_type" "RXE")
2461    (set_attr "atype"   "mem")])
2462
2463 ;
2464 ; zero_extendqidi2 instruction pattern(s)
2465 ;
2466
2467 (define_expand "zero_extendqidi2"
2468   [(set (match_operand:DI 0 "register_operand" "")
2469         (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2470   ""
2471   "
2472 {
2473   if (!TARGET_64BIT)
2474     {
2475       rtx tmp = gen_reg_rtx (SImode);
2476       emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2477       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2478       DONE;
2479     }
2480   else
2481     {
2482       operands[1] = gen_lowpart (DImode, operands[1]);
2483       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2484       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2485       DONE;
2486     }
2487 }
2488 ")
2489
2490 (define_insn "*zero_extendqidi2"
2491   [(set (match_operand:DI 0 "register_operand" "=d")
2492         (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2493   "TARGET_64BIT"
2494   "llgc\\t%0,%1"
2495   [(set_attr "op_type" "RXE")
2496    (set_attr "atype"   "mem")])
2497
2498 ;
2499 ; zero_extendhisi2 instruction pattern(s).
2500 ;
2501
2502 (define_expand "zero_extendhisi2"
2503   [(set (match_operand:SI 0 "register_operand" "")
2504         (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2505   ""
2506   "
2507 {
2508   operands[1] = gen_lowpart (SImode, operands[1]);
2509   emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2510   DONE;
2511 }
2512 ")
2513
2514 (define_insn "*zero_extendhisi2_64"
2515   [(set (match_operand:SI 0 "register_operand" "=d")
2516         (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2517   "TARGET_64BIT"
2518   "llgh\\t%0,%1"
2519   [(set_attr "op_type" "RXE")
2520    (set_attr "atype"   "mem")])
2521
2522 ;
2523 ; zero_extendqisi2 instruction pattern(s).
2524 ;
2525
2526 (define_expand "zero_extendqisi2"
2527   [(set (match_operand:SI 0 "register_operand" "")
2528         (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2529   ""
2530   "
2531 {
2532   operands[1] = gen_lowpart (SImode, operands[1]);
2533   emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2534   DONE;
2535 }
2536 ")
2537
2538 (define_insn "*zero_extendqisi2_64"
2539   [(set (match_operand:SI 0 "register_operand" "=d")
2540         (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2541   "TARGET_64BIT"
2542   "llgc\\t%0,%1"
2543   [(set_attr "op_type" "RXE")
2544    (set_attr "atype"   "mem")])
2545
2546 ;
2547 ; zero_extendqihi2 instruction pattern(s).
2548 ;
2549
2550 (define_expand "zero_extendqihi2"
2551   [(set (match_operand:HI 0 "register_operand" "")
2552         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2553   "TARGET_64BIT"
2554   "
2555 {
2556   operands[1] = gen_lowpart (HImode, operands[1]);
2557   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2558   DONE;
2559 }
2560 ")
2561
2562 (define_insn "*zero_extendqihi2_64"
2563   [(set (match_operand:HI 0 "register_operand" "=d")
2564         (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2565    (clobber (reg:CC 33))]
2566   "TARGET_64BIT"
2567   "llgc\\t%0,%1"
2568   [(set_attr "op_type" "RXE")
2569    (set_attr "atype"   "mem")])
2570
2571 ;
2572 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2573 ;
2574
2575 (define_expand "fixuns_truncdfdi2"
2576   [(set (match_operand:DI 0 "register_operand" "")
2577         (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2578   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2579   "
2580 {
2581   rtx label1 = gen_label_rtx ();
2582   rtx label2 = gen_label_rtx ();
2583   rtx temp = gen_reg_rtx (DFmode);
2584   operands[1] = force_reg (DFmode, operands[1]);
2585
2586   emit_insn (gen_cmpdf (operands[1],
2587         CONST_DOUBLE_FROM_REAL_VALUE (
2588           REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2589   emit_jump_insn (gen_blt (label1));
2590   emit_insn (gen_subdf3 (temp, operands[1],
2591         CONST_DOUBLE_FROM_REAL_VALUE (
2592           REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2593   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2594   emit_jump (label2);
2595
2596   emit_label (label1);
2597   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2598   emit_label (label2);
2599   DONE;
2600 }")
2601
2602 (define_expand "fix_truncdfdi2"
2603   [(set (match_operand:DI 0 "register_operand" "")
2604         (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2605   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2606   "
2607 {
2608   operands[1] = force_reg (DFmode, operands[1]);
2609   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2610   DONE;
2611 }")
2612
2613 (define_insn "fix_truncdfdi2_ieee"
2614   [(set (match_operand:DI 0 "register_operand" "=d")
2615         (fix:DI (match_operand:DF 1 "register_operand" "f")))
2616    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2617    (clobber (reg:CC 33))]
2618   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2619   "cgdbr\\t%0,%h2,%1"
2620   [(set_attr "op_type" "RRE")
2621    (set_attr "type"    "other")])
2622
2623 ;
2624 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2625 ;
2626
2627 (define_expand "fixuns_truncdfsi2"
2628   [(set (match_operand:SI 0 "register_operand" "")
2629         (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2630   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2631   "
2632 {
2633   rtx label1 = gen_label_rtx ();
2634   rtx label2 = gen_label_rtx ();
2635   rtx temp = gen_reg_rtx (DFmode);
2636
2637   operands[1] = force_reg (DFmode,operands[1]);
2638   emit_insn (gen_cmpdf (operands[1],
2639         CONST_DOUBLE_FROM_REAL_VALUE (
2640           REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2641   emit_jump_insn (gen_blt (label1));
2642   emit_insn (gen_subdf3 (temp, operands[1],
2643         CONST_DOUBLE_FROM_REAL_VALUE (
2644           REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2645   emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2646   emit_jump (label2);
2647
2648   emit_label (label1);
2649   emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2650   emit_label (label2);
2651   DONE;
2652 }")
2653
2654 (define_expand "fix_truncdfsi2"
2655   [(set (match_operand:SI 0 "register_operand" "")
2656         (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2657   "TARGET_HARD_FLOAT"
2658   "
2659 {
2660   if (TARGET_IBM_FLOAT)
2661     {
2662       /* This is the algorithm from POP chapter A.5.7.2.  */
2663
2664       rtx temp   = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2665       rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2666       rtx two32  = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2667
2668       operands[1] = force_reg (DFmode, operands[1]);
2669       emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2670                                          two31r, two32, temp));
2671     }
2672   else
2673     {
2674       operands[1] = force_reg (DFmode, operands[1]);
2675       emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2676     }
2677
2678   DONE;
2679 }")
2680
2681 (define_insn "fix_truncdfsi2_ieee"
2682   [(set (match_operand:SI 0 "register_operand" "=d")
2683         (fix:SI (match_operand:DF 1 "register_operand" "f")))
2684     (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2685     (clobber (reg:CC 33))]
2686   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2687   "cfdbr\\t%0,%h2,%1"
2688    [(set_attr "op_type" "RRE")
2689     (set_attr "type"    "other" )])
2690
2691 (define_insn "fix_truncdfsi2_ibm"
2692   [(set (match_operand:SI 0 "register_operand" "=d")
2693         (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2694    (use (match_operand:DI 2 "immediate_operand" "m"))
2695    (use (match_operand:DI 3 "immediate_operand" "m"))
2696    (use (match_operand:BLK 4 "memory_operand" "m"))
2697    (clobber (reg:CC 33))]
2698   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2699   "*
2700 {
2701    output_asm_insn (\"sd\\t%1,%2\", operands);
2702    output_asm_insn (\"aw\\t%1,%3\", operands);
2703    output_asm_insn (\"std\\t%1,%4\", operands);
2704    output_asm_insn (\"xi\\t%N4,128\", operands);
2705    return \"l\\t%0,%N4\";
2706 }"
2707   [(set_attr "op_type" "NN")
2708    (set_attr "type"    "other")
2709    (set_attr "length"  "20")])
2710
2711 ;
2712 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2713 ;
2714
2715 (define_expand "fixuns_truncsfdi2"
2716   [(set (match_operand:DI 0 "register_operand" "")
2717         (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2718   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2719   "
2720 {
2721   rtx label1 = gen_label_rtx ();
2722   rtx label2 = gen_label_rtx ();
2723   rtx temp = gen_reg_rtx (SFmode);
2724
2725   operands[1] = force_reg (SFmode, operands[1]);
2726   emit_insn (gen_cmpsf (operands[1],
2727         CONST_DOUBLE_FROM_REAL_VALUE (
2728           REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2729   emit_jump_insn (gen_blt (label1));
2730
2731   emit_insn (gen_subsf3 (temp, operands[1],
2732         CONST_DOUBLE_FROM_REAL_VALUE (
2733           REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2734   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2735   emit_jump (label2);
2736
2737   emit_label (label1);
2738   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2739   emit_label (label2);
2740   DONE;
2741 }")
2742
2743 (define_expand "fix_truncsfdi2"
2744   [(set (match_operand:DI 0 "register_operand" "")
2745         (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2746   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2747   "
2748 {
2749   operands[1] = force_reg (SFmode, operands[1]);
2750   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2751   DONE;
2752 }")
2753
2754 (define_insn "fix_truncsfdi2_ieee"
2755   [(set (match_operand:DI 0 "register_operand" "=d")
2756         (fix:DI (match_operand:SF 1 "register_operand"  "f")))
2757    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2758    (clobber (reg:CC 33))]
2759   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2760   "cgebr\\t%0,%h2,%1"
2761   [(set_attr "op_type" "RRE")
2762    (set_attr "type"    "other")])
2763
2764 ;
2765 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2766 ;
2767
2768 (define_expand "fixuns_truncsfsi2"
2769   [(set (match_operand:SI 0 "register_operand" "")
2770         (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2771   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2772   "
2773 {
2774   rtx label1 = gen_label_rtx ();
2775   rtx label2 = gen_label_rtx ();
2776   rtx temp = gen_reg_rtx (SFmode);
2777
2778   operands[1] = force_reg (SFmode, operands[1]);
2779   emit_insn (gen_cmpsf (operands[1],
2780         CONST_DOUBLE_FROM_REAL_VALUE (
2781           REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2782   emit_jump_insn (gen_blt (label1));
2783   emit_insn (gen_subsf3 (temp, operands[1],
2784         CONST_DOUBLE_FROM_REAL_VALUE (
2785           REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2786   emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2787   emit_jump (label2);
2788
2789   emit_label (label1);
2790   emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2791   emit_label (label2);
2792   DONE;
2793 }")
2794
2795 (define_expand "fix_truncsfsi2"
2796   [(set (match_operand:SI 0 "register_operand" "")
2797         (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2798   "TARGET_HARD_FLOAT"
2799   "
2800 {
2801   if (TARGET_IBM_FLOAT)
2802     {
2803       /* Convert to DFmode and then use the POP algorithm.  */
2804       rtx temp = gen_reg_rtx (DFmode);
2805       emit_insn (gen_extendsfdf2 (temp, operands[1]));
2806       emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2807     }
2808   else
2809     {
2810       operands[1] = force_reg (SFmode, operands[1]);
2811       emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2812     }
2813
2814   DONE;
2815 }")
2816
2817 (define_insn "fix_truncsfsi2_ieee"
2818   [(set (match_operand:SI 0 "register_operand" "=d")
2819         (fix:SI (match_operand:SF 1 "register_operand" "f")))
2820     (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2821     (clobber (reg:CC 33))]
2822   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2823   "cfebr\\t%0,%h2,%1"
2824   [(set_attr "op_type" "RRE")
2825    (set_attr "type"    "other")])
2826
2827 ;
2828 ; floatdidf2 instruction pattern(s).
2829 ;
2830
2831 (define_insn "floatdidf2"
2832   [(set (match_operand:DF 0 "register_operand" "=f")
2833         (float:DF (match_operand:DI 1 "register_operand" "d")))
2834    (clobber (reg:CC 33))]
2835   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2836   "cdgbr\\t%0,%1"
2837   [(set_attr "op_type" "RRE")
2838    (set_attr "type"    "other" )])
2839
2840 ;
2841 ; floatdisf2 instruction pattern(s).
2842 ;
2843
2844 (define_insn "floatdisf2"
2845   [(set (match_operand:SF 0 "register_operand" "=f")
2846         (float:SF (match_operand:DI 1 "register_operand" "d")))
2847    (clobber (reg:CC 33))]
2848   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2849   "cegbr\\t%0,%1"
2850   [(set_attr "op_type" "RRE")
2851    (set_attr "type"    "other" )])
2852
2853 ;
2854 ; floatsidf2 instruction pattern(s).
2855 ;
2856
2857 (define_expand "floatsidf2"
2858   [(parallel
2859     [(set (match_operand:DF 0 "register_operand" "")
2860           (float:DF (match_operand:SI 1 "register_operand" "")))
2861      (clobber (reg:CC 33))])]
2862   "TARGET_HARD_FLOAT"
2863   "
2864 {
2865   if (TARGET_IBM_FLOAT)
2866     {
2867       /* This is the algorithm from POP chapter A.5.7.1.  */
2868
2869       rtx temp  = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2870       rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2871
2872       emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2873       DONE;
2874     }
2875 }")
2876
2877 (define_insn "floatsidf2_ieee"
2878   [(set (match_operand:DF 0 "register_operand" "=f")
2879         (float:DF (match_operand:SI 1 "register_operand"  "d")))
2880    (clobber (reg:CC 33))]
2881   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2882   "cdfbr\\t%0,%1"
2883   [(set_attr "op_type" "RRE")
2884    (set_attr "type"   "other" )])
2885
2886 (define_insn "floatsidf2_ibm"
2887   [(set (match_operand:DF 0 "register_operand" "=f")
2888         (float:DF (match_operand:SI 1 "register_operand" "d")))
2889    (use (match_operand:DI 2 "immediate_operand" "m"))
2890    (use (match_operand:BLK 3 "memory_operand" "m"))
2891    (clobber (reg:CC 33))]
2892   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2893   "*
2894 {
2895    output_asm_insn (\"st\\t%1,%N3\", operands);
2896    output_asm_insn (\"xi\\t%N3,128\", operands);
2897    output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2898    output_asm_insn (\"ld\\t%0,%3\", operands);
2899    return \"sd\\t%0,%2\";
2900 }"
2901   [(set_attr "op_type" "NN")
2902    (set_attr "type"    "other" )
2903    (set_attr "length"  "20")])
2904
2905 ;
2906 ; floatsisf2 instruction pattern(s).
2907 ;
2908
2909 (define_expand "floatsisf2"
2910   [(parallel
2911     [(set (match_operand:SF 0 "register_operand" "")
2912           (float:SF (match_operand:SI 1 "register_operand" "")))
2913      (clobber (reg:CC 33))])]
2914   "TARGET_HARD_FLOAT"
2915   "
2916 {
2917   if (TARGET_IBM_FLOAT)
2918     {
2919       /* Use the POP algorithm to convert to DFmode and then truncate.  */
2920       rtx temp = gen_reg_rtx (DFmode);
2921       emit_insn (gen_floatsidf2 (temp, operands[1]));
2922       emit_insn (gen_truncdfsf2 (operands[0], temp));
2923       DONE;
2924     }
2925 }")
2926
2927 (define_insn "floatsisf2_ieee"
2928   [(set (match_operand:SF 0 "register_operand" "=f")
2929         (float:SF (match_operand:SI 1 "register_operand" "d")))
2930    (clobber (reg:CC 33))]
2931   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2932   "cefbr\\t%0,%1"
2933   [(set_attr "op_type" "RRE")
2934    (set_attr "type"    "other" )])
2935
2936 ;
2937 ; truncdfsf2 instruction pattern(s).
2938 ;
2939
2940 (define_expand "truncdfsf2"
2941   [(set (match_operand:SF 0 "register_operand" "")
2942         (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2943   "TARGET_HARD_FLOAT"
2944   "")
2945
2946 (define_insn "truncdfsf2_ieee"
2947   [(set (match_operand:SF 0 "register_operand" "=f")
2948         (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2949   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2950   "ledbr\\t%0,%1"
2951   [(set_attr "op_type"  "RRE")])
2952
2953 (define_insn "truncdfsf2_ibm"
2954   [(set (match_operand:SF 0 "register_operand" "=f,f")
2955         (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2956   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2957   "@
2958    lrer\\t%0,%1
2959    le\\t%0,%1"
2960   [(set_attr "op_type"  "RR,RX")
2961    (set_attr "atype"    "reg,mem")])
2962
2963 ;
2964 ; extendsfdf2 instruction pattern(s).
2965 ;
2966
2967 (define_expand "extendsfdf2"
2968   [(set (match_operand:DF 0 "register_operand" "")
2969         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2970   "TARGET_HARD_FLOAT"
2971   "
2972 {
2973   if (TARGET_IBM_FLOAT)
2974     {
2975       emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2976       DONE;
2977     }
2978 }")
2979
2980 (define_insn "extendsfdf2_ieee"
2981   [(set (match_operand:DF 0 "register_operand" "=f,f")
2982         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,m")))]
2983   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2984   "@
2985    ldebr\\t%0,%1
2986    ldeb\\t%0,%1"
2987   [(set_attr "op_type"  "RRE,RXE")])
2988
2989 (define_insn "extendsfdf2_ibm"
2990   [(set (match_operand:DF 0 "register_operand" "=f,f")
2991         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2992    (clobber (reg:CC 33))]
2993   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2994   "@
2995    sdr\\t%0,%0\;ler\\t%0,%1
2996    sdr\\t%0,%0\;le\\t%0,%1"
2997   [(set_attr "op_type"  "RRE,RXE")
2998    (set_attr "atype"    "reg,mem")
2999    (set_attr "type"     "o2,o2")])
3000
3001
3002 ;;
3003 ;; ARITHMETRIC OPERATIONS
3004 ;;
3005 ;  arithmetric operations set the ConditionCode,
3006 ;  because of unpredictable Bits in Register for Halfword and Byte
3007 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
3008
3009 ;;
3010 ;;- Add instructions.
3011 ;;
3012
3013 ;
3014 ; adddi3 instruction pattern(s).
3015 ;
3016
3017 (define_insn "addaddr_esame"
3018   [(set (match_operand:DI 0 "register_operand" "=a,a")
3019         (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
3020                  (match_operand:DI 2 "nonmemory_operand" "J,a")))]
3021   "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3022      (REGNO (operands[1]) == BASE_REGISTER)) &&
3023         (GET_CODE (operands[2]) == REG ||
3024          CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3025   "@
3026    la\\t%0,%c2(,%1)
3027    la\\t%0,0(%1,%2)"
3028   [(set_attr "op_type" "RX")
3029    (set_attr "atype"   "mem")
3030    (set_attr "type"    "la")])
3031
3032 (define_insn "*adddi3_sign"
3033   [(set (match_operand:DI 0 "register_operand" "=d,d")
3034         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3035                  (match_operand:DI 1 "register_operand" "0,0")))
3036    (clobber (reg:CC 33))]
3037   "TARGET_64BIT"
3038   "@
3039    agfr\\t%0,%2
3040    agf\\t%0,%2"
3041   [(set_attr "op_type"  "RRE,RXE")
3042    (set_attr "atype"    "reg,mem")])
3043
3044 (define_insn "*adddi3_zero_cc"
3045   [(set (reg 33)
3046         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3047                           (match_operand:DI 1 "register_operand" "0,0"))
3048                  (const_int 0)))
3049    (set (match_operand:DI 0 "register_operand" "=d,d")
3050         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3051   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3052   "@
3053    algfr\\t%0,%2
3054    algf\\t%0,%2"
3055   [(set_attr "op_type"  "RRE,RXE")
3056    (set_attr "atype"    "reg,mem")])
3057
3058 (define_insn "*adddi3_zero_cconly"
3059   [(set (reg 33)
3060         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3061                           (match_operand:DI 1 "register_operand" "0,0"))
3062                  (const_int 0)))
3063    (clobber (match_scratch:DI 0 "=d,d"))]
3064   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3065   "@
3066    algfr\\t%0,%2
3067    algf\\t%0,%2"
3068   [(set_attr "op_type"  "RRE,RXE")
3069    (set_attr "atype"    "reg,mem")])
3070
3071 (define_insn "*adddi3_zero"
3072   [(set (match_operand:DI 0 "register_operand" "=d,d")
3073         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3074                  (match_operand:DI 1 "register_operand" "0,0")))
3075    (clobber (reg:CC 33))]
3076   "TARGET_64BIT"
3077   "@
3078    algfr\\t%0,%2
3079    algf\\t%0,%2"
3080   [(set_attr "op_type"  "RRE,RXE")
3081    (set_attr "atype"    "reg,mem")])
3082
3083 (define_insn "*adddi3_imm_cc"
3084   [(set (reg 33)
3085         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3086                           (match_operand:DI 2 "const_int_operand" "K"))
3087                  (const_int 0)))
3088    (set (match_operand:DI 0 "register_operand" "=d")
3089         (plus:DI (match_dup 1) (match_dup 2)))]
3090   "TARGET_64BIT
3091    && s390_match_ccmode (insn, CCAmode)
3092    && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3093   "aghi\\t%0,%h2"
3094   [(set_attr "op_type"  "RI")
3095    (set_attr "atype"    "reg")])
3096
3097 (define_insn "*adddi3_cc"
3098   [(set (reg 33)
3099         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3100                           (match_operand:DI 2 "general_operand" "d,m"))
3101                  (const_int 0)))
3102    (set (match_operand:DI 0 "register_operand" "=d,d")
3103         (plus:DI (match_dup 1) (match_dup 2)))]
3104   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3105   "@
3106    algr\\t%0,%2
3107    alg\\t%0,%2"
3108   [(set_attr "op_type"  "RRE,RXE")
3109    (set_attr "atype"    "reg,mem")])
3110
3111 (define_insn "*adddi3_cconly"
3112   [(set (reg 33)
3113         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3114                           (match_operand:DI 2 "general_operand" "d,m"))
3115                  (const_int 0)))
3116    (clobber (match_scratch:DI 0 "=d,d"))]
3117   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3118   "@
3119    algr\\t%0,%2
3120    alg\\t%0,%2"
3121   [(set_attr "op_type"  "RRE,RXE")
3122    (set_attr "atype"    "reg,mem")])
3123
3124 (define_insn "*adddi3_cconly2"
3125   [(set (reg 33)
3126         (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3127                  (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3128    (clobber (match_scratch:DI 0 "=d,d"))]
3129   "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3130   "@
3131    algr\\t%0,%2
3132    alg\\t%0,%2"
3133   [(set_attr "op_type"  "RRE,RXE")
3134    (set_attr "atype"    "reg,mem")])
3135
3136 (define_insn "*adddi3_64"
3137   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3138         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3139                  (match_operand:DI 2 "general_operand" "d,K,m") ) )
3140    (clobber (reg:CC 33))]
3141   "TARGET_64BIT"
3142   "@
3143    agr\\t%0,%2
3144    aghi\\t%0,%h2
3145    ag\\t%0,%2"
3146   [(set_attr "op_type"  "RRE,RI,RXE")
3147    (set_attr "atype"    "reg,reg,mem")])
3148
3149 (define_insn_and_split "*adddi3_31"
3150   [(set (match_operand:DI 0 "register_operand" "=&d")
3151         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3152                  (match_operand:DI 2 "general_operand" "dm") ) )
3153    (clobber (reg:CC 33))]
3154   "!TARGET_64BIT"
3155   "#"
3156   "&& reload_completed"
3157   [(parallel
3158     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3159      (clobber (reg:CC 33))])
3160    (parallel
3161     [(set (reg:CCL1 33)
3162           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3163                         (match_dup 7)))
3164      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3165    (set (pc)
3166         (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3167                       (pc)
3168                       (label_ref (match_dup 9))))
3169    (parallel
3170     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3171      (clobber (reg:CC 33))])
3172    (match_dup 9)]
3173   "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3174    operands[4] = operand_subword (operands[1], 0, 1, DImode);
3175    operands[5] = operand_subword (operands[2], 0, 1, DImode);
3176    operands[6] = operand_subword (operands[0], 1, 1, DImode);
3177    operands[7] = operand_subword (operands[1], 1, 1, DImode);
3178    operands[8] = operand_subword (operands[2], 1, 1, DImode);
3179    operands[9] = gen_label_rtx ();"
3180   [(set_attr "op_type"  "NN")
3181    (set_attr "type"     "o3")])
3182
3183 (define_expand "adddi3"
3184   [(parallel
3185     [(set (match_operand:DI 0 "register_operand" "")
3186           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3187                    (match_operand:DI 2 "general_operand" "")))
3188      (clobber (reg:CC 33))])]
3189   ""
3190   "")
3191
3192 (define_insn "*la_64"
3193   [(set (match_operand:DI 0 "register_operand" "=d")
3194         (match_operand:QI 1 "address_operand" "p"))]
3195   "TARGET_64BIT"
3196   "la\\t%0,%a1"
3197   [(set_attr "op_type" "RX")
3198    (set_attr "atype"   "mem")
3199    (set_attr "type"    "la")])
3200
3201 (define_expand "reload_indi"
3202   [(parallel [(match_operand:DI 0 "register_operand" "=a")
3203               (match_operand:DI 1 "s390_plus_operand" "")
3204               (match_operand:DI 2 "register_operand" "=&a")])]
3205   "TARGET_64BIT"
3206   "
3207 {
3208   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3209   DONE;
3210 }")
3211
3212
3213 ;
3214 ; addsi3 instruction pattern(s).
3215 ;
3216
3217 (define_insn "*la_ccclobber"
3218   [(set (match_operand:SI 0 "register_operand" "=d")
3219         (match_operand:QI 1 "address_operand"  "p"))
3220    (clobber (reg:CC 33))]
3221   "legitimate_la_operand_p (operands[1])"
3222   "la\\t%0,%a1"
3223    [(set_attr "op_type"  "RX")
3224     (set_attr "atype"    "mem")
3225     (set_attr "type"     "la")])
3226
3227 (define_insn "*addsi3_imm_cc"
3228   [(set (reg 33)
3229         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3230                           (match_operand:SI 2 "const_int_operand" "K"))
3231                  (const_int 0)))
3232    (set (match_operand:SI 0 "register_operand" "=d")
3233         (plus:SI (match_dup 1) (match_dup 2)))]
3234   "s390_match_ccmode (insn, CCAmode)
3235    && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3236   "ahi\\t%0,%h2"
3237   [(set_attr "op_type"  "RI")
3238    (set_attr "atype"    "reg")])
3239
3240 (define_insn "*addsi3_carry1_cc"
3241   [(set (reg 33)
3242         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3243                           (match_operand:SI 2 "general_operand" "d,m"))
3244                  (match_dup 1)))
3245    (set (match_operand:SI 0 "register_operand" "=d,d")
3246         (plus:SI (match_dup 1) (match_dup 2)))]
3247   "s390_match_ccmode (insn, CCL1mode)"
3248   "@
3249    alr\\t%0,%2
3250    al\\t%0,%2"
3251   [(set_attr "op_type"  "RR,RX")
3252    (set_attr "atype"    "reg,mem")])
3253
3254 (define_insn "*addsi3_carry1_cconly"
3255   [(set (reg 33)
3256         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3257                           (match_operand:SI 2 "general_operand" "d,m"))
3258                  (match_dup 1)))
3259    (clobber (match_scratch:SI 0 "=d,d"))]
3260   "s390_match_ccmode (insn, CCL1mode)"
3261   "@
3262    alr\\t%0,%2
3263    al\\t%0,%2"
3264   [(set_attr "op_type"  "RR,RX")
3265    (set_attr "atype"    "reg,mem")])
3266
3267 (define_insn "*addsi3_carry2_cc"
3268   [(set (reg 33)
3269         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3270                           (match_operand:SI 2 "general_operand" "d,m"))
3271                  (match_dup 2)))
3272    (set (match_operand:SI 0 "register_operand" "=d,d")
3273         (plus:SI (match_dup 1) (match_dup 2)))]
3274   "s390_match_ccmode (insn, CCL1mode)"
3275   "@
3276    alr\\t%0,%2
3277    al\\t%0,%2"
3278   [(set_attr "op_type"  "RR,RX")
3279    (set_attr "atype"    "reg,mem")])
3280
3281 (define_insn "*addsi3_carry2_cconly"
3282   [(set (reg 33)
3283         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3284                           (match_operand:SI 2 "general_operand" "d,m"))
3285                  (match_dup 2)))
3286    (clobber (match_scratch:SI 0 "=d,d"))]
3287   "s390_match_ccmode (insn, CCL1mode)"
3288   "@
3289    alr\\t%0,%2
3290    al\\t%0,%2"
3291   [(set_attr "op_type"  "RR,RX")
3292    (set_attr "atype"    "reg,mem")])
3293
3294 (define_insn "*addsi3_cc"
3295   [(set (reg 33)
3296         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3297                           (match_operand:SI 2 "general_operand" "d,m"))
3298                  (const_int 0)))
3299    (set (match_operand:SI 0 "register_operand" "=d,d")
3300         (plus:SI (match_dup 1) (match_dup 2)))]
3301   "s390_match_ccmode (insn, CCLmode)"
3302   "@
3303    alr\\t%0,%2
3304    al\\t%0,%2"
3305   [(set_attr "op_type"  "RR,RX")
3306    (set_attr "atype"    "reg,mem")])
3307
3308 (define_insn "*addsi3_cconly"
3309   [(set (reg 33)
3310         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3311                           (match_operand:SI 2 "general_operand" "d,m"))
3312                  (const_int 0)))
3313    (clobber (match_scratch:SI 0 "=d,d"))]
3314   "s390_match_ccmode (insn, CCLmode)"
3315   "@
3316    alr\\t%0,%2
3317    al\\t%0,%2"
3318   [(set_attr "op_type"  "RR,RX")
3319    (set_attr "atype"    "reg,mem")])
3320
3321 (define_insn "*addsi3_cconly2"
3322   [(set (reg 33)
3323         (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3324                  (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3325    (clobber (match_scratch:SI 0 "=d,d"))]
3326   "s390_match_ccmode(insn, CCLmode)"
3327   "@
3328    alr\\t%0,%2
3329    al\\t%0,%2"
3330   [(set_attr "op_type"  "RR,RX")
3331    (set_attr "atype"    "reg,mem")])
3332
3333 (define_insn "*addsi3_sign"
3334   [(set (match_operand:SI 0 "register_operand" "=d")
3335         (plus:SI (match_operand:SI 1 "register_operand" "0")
3336                  (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3337    (clobber (reg:CC 33))]
3338   ""
3339   "ah\\t%0,%2"
3340   [(set_attr "op_type"  "RX")
3341    (set_attr "atype"    "mem")])
3342
3343 (define_insn "*addsi3_sub"
3344   [(set (match_operand:SI 0 "register_operand" "=d")
3345         (plus:SI (match_operand:SI 1 "register_operand" "0")
3346                  (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3347    (clobber (reg:CC 33))]
3348   ""
3349   "ah\\t%0,%2"
3350   [(set_attr "op_type"  "RX")
3351    (set_attr "atype"    "mem")])
3352
3353 (define_insn "addsi3"
3354   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3355         (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3356                  (match_operand:SI 2 "general_operand" "d,K,m")))
3357    (clobber (reg:CC 33))]
3358   ""
3359   "@
3360    ar\\t%0,%2
3361    ahi\\t%0,%h2
3362    a\\t%0,%2"
3363   [(set_attr "op_type"  "RR,RI,RX")
3364    (set_attr "atype"    "reg,reg,mem")])
3365
3366 (define_insn "*la_31"
3367   [(set (match_operand:SI 0 "register_operand" "=d")
3368         (match_operand:QI 1 "address_operand" "p"))]
3369   "legitimate_la_operand_p (operands[1])"
3370   "la\\t%0,%a1"
3371   [(set_attr "op_type"  "RX")
3372    (set_attr "atype"    "mem")
3373    (set_attr "type"     "la")])
3374
3375 (define_expand "reload_insi"
3376   [(parallel [(match_operand:SI 0 "register_operand" "=a")
3377               (match_operand:SI 1 "s390_plus_operand" "")
3378               (match_operand:SI 2 "register_operand" "=&a")])]
3379   "!TARGET_64BIT"
3380   "
3381 {
3382   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3383   DONE;
3384 }")
3385
3386
3387 ;
3388 ; adddf3 instruction pattern(s).
3389 ;
3390
3391 (define_expand "adddf3"
3392   [(parallel
3393     [(set (match_operand:DF 0 "register_operand" "=f,f")
3394           (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3395                    (match_operand:DF 2 "general_operand" "f,m")))
3396      (clobber (reg:CC 33))])]
3397   "TARGET_HARD_FLOAT"
3398   "")
3399
3400 (define_insn "*adddf3"
3401   [(set (match_operand:DF 0 "register_operand" "=f,f")
3402         (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3403                  (match_operand:DF 2 "general_operand" "f,m")))
3404    (clobber (reg:CC 33))]
3405   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3406   "@
3407    adbr\\t%0,%2
3408    adb\\t%0,%2"
3409   [(set_attr "op_type"  "RRE,RXE")
3410    (set_attr "atype"    "reg,mem")])
3411
3412 (define_insn "*adddf3_ibm"
3413   [(set (match_operand:DF 0 "register_operand" "=f,f")
3414         (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3415                  (match_operand:DF 2 "general_operand" "f,m")))
3416    (clobber (reg:CC 33))]
3417   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3418   "@
3419    adr\\t%0,%2
3420    ad\\t%0,%2"
3421   [(set_attr "op_type"  "RR,RX")
3422    (set_attr "atype"    "reg,mem")])
3423
3424 ;
3425 ; addsf3 instruction pattern(s).
3426 ;
3427
3428 (define_expand "addsf3"
3429   [(parallel
3430     [(set (match_operand:SF 0 "register_operand" "=f,f")
3431           (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3432                    (match_operand:SF 2 "general_operand" "f,m")))
3433      (clobber (reg:CC 33))])]
3434   "TARGET_HARD_FLOAT"
3435   "")
3436
3437 (define_insn "*addsf3"
3438   [(set (match_operand:SF 0 "register_operand" "=f,f")
3439         (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3440                  (match_operand:SF 2 "general_operand" "f,m")))
3441    (clobber (reg:CC 33))]
3442   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3443   "@
3444    aebr\\t%0,%2
3445    aeb\\t%0,%2"
3446   [(set_attr "op_type"  "RRE,RXE")
3447    (set_attr "atype"    "reg,mem")])
3448
3449 (define_insn "*addsf3"
3450   [(set (match_operand:SF 0 "register_operand" "=f,f")
3451         (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3452                  (match_operand:SF 2 "general_operand" "f,m")))
3453    (clobber (reg:CC 33))]
3454   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3455   "@
3456    aer\\t%0,%2
3457    ae\\t%0,%2"
3458   [(set_attr "op_type"  "RR,RX")
3459    (set_attr "atype"    "reg,mem")])
3460
3461
3462 ;;
3463 ;;- Subtract instructions.
3464 ;;
3465
3466 ;
3467 ; subdi3 instruction pattern(s).
3468 ;
3469
3470 (define_insn "*subdi3_sign"
3471   [(set (match_operand:DI 0 "register_operand" "=d,d")
3472         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3473                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3474    (clobber (reg:CC 33))]
3475   "TARGET_64BIT"
3476   "@
3477    sgfr\\t%0,%2
3478    sgf\\t%0,%2"
3479   [(set_attr "op_type"  "RRE,RXE")
3480    (set_attr "atype"    "reg,mem")])
3481
3482 (define_insn "*subdi3_zero_cc"
3483   [(set (reg 33)
3484         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3485                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3486                  (const_int 0)))
3487    (set (match_operand:DI 0 "register_operand" "=d,d")
3488         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3489   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3490   "@
3491    slgfr\\t%0,%2
3492    slgf\\t%0,%2"
3493   [(set_attr "op_type"  "RRE,RXE")
3494    (set_attr "atype"    "reg,mem")])
3495
3496 (define_insn "*subdi3_zero_cconly"
3497   [(set (reg 33)
3498         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3499                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3500                  (const_int 0)))
3501    (clobber (match_scratch:DI 0 "=d,d"))]
3502   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3503   "@
3504    slgfr\\t%0,%2
3505    slgf\\t%0,%2"
3506   [(set_attr "op_type"  "RRE,RXE")
3507    (set_attr "atype"    "reg,mem")])
3508
3509 (define_insn "*subdi3_zero"
3510   [(set (match_operand:DI 0 "register_operand" "=d,d")
3511         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3512                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3513    (clobber (reg:CC 33))]
3514   "TARGET_64BIT"
3515   "@
3516    slgfr\\t%0,%2
3517    slgf\\t%0,%2"
3518   [(set_attr "op_type"  "RRE,RXE")
3519    (set_attr "atype"    "reg,mem")])
3520
3521 (define_insn "*subdi3_cc"
3522   [(set (reg 33)
3523         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3524                            (match_operand:DI 2 "general_operand" "d,m"))
3525                  (const_int 0)))
3526    (set (match_operand:DI 0 "register_operand" "=d,d")
3527         (minus:DI (match_dup 1) (match_dup 2)))]
3528   "s390_match_ccmode (insn, CCLmode)"
3529   "@
3530    slgr\\t%0,%2
3531    slg\\t%0,%2"
3532   [(set_attr "op_type"  "RRE,RXE")
3533    (set_attr "atype"    "reg,mem")])
3534
3535 (define_insn "*subdi3_cconly"
3536   [(set (reg 33)
3537         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3538                            (match_operand:DI 2 "general_operand" "d,m"))
3539                  (const_int 0)))
3540    (clobber (match_scratch:DI 0 "=d,d"))]
3541   "s390_match_ccmode (insn, CCLmode)"
3542   "@
3543    slgr\\t%0,%2
3544    slg\\t%0,%2"
3545   [(set_attr "op_type"  "RRE,RXE")
3546    (set_attr "atype"    "reg,mem")])
3547
3548 (define_insn "*subdi3_64"
3549   [(set (match_operand:DI 0 "register_operand" "=d,d")
3550         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3551                   (match_operand:DI 2 "general_operand" "d,m") ) )
3552    (clobber (reg:CC 33))]
3553   "TARGET_64BIT"
3554   "@
3555    sgr\\t%0,%2
3556    sg\\t%0,%2"
3557   [(set_attr "op_type"  "RRE,RRE")
3558    (set_attr "atype"    "reg,mem")])
3559
3560 (define_insn_and_split "*subdi3_31"
3561   [(set (match_operand:DI 0 "register_operand" "=&d")
3562         (minus:DI (match_operand:DI 1 "register_operand" "0")
3563                   (match_operand:DI 2 "general_operand" "dm") ) )
3564    (clobber (reg:CC 33))]
3565   "!TARGET_64BIT"
3566   "#"
3567   "&& reload_completed"
3568   [(parallel
3569     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3570      (clobber (reg:CC 33))])
3571    (parallel
3572     [(set (reg:CCL2 33)
3573           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3574                         (match_dup 7)))
3575      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3576    (set (pc)
3577         (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3578                       (pc)
3579                       (label_ref (match_dup 9))))
3580    (parallel
3581     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3582      (clobber (reg:CC 33))])
3583    (match_dup 9)]
3584   "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3585    operands[4] = operand_subword (operands[1], 0, 1, DImode);
3586    operands[5] = operand_subword (operands[2], 0, 1, DImode);
3587    operands[6] = operand_subword (operands[0], 1, 1, DImode);
3588    operands[7] = operand_subword (operands[1], 1, 1, DImode);
3589    operands[8] = operand_subword (operands[2], 1, 1, DImode);
3590    operands[9] = gen_label_rtx ();"
3591   [(set_attr "op_type"  "NN")
3592    (set_attr "type"     "o3")])
3593
3594 (define_expand "subdi3"
3595   [(parallel
3596     [(set (match_operand:DI 0 "register_operand" "")
3597           (minus:DI (match_operand:DI 1 "register_operand" "")
3598                     (match_operand:DI 2 "general_operand" "")))
3599      (clobber (reg:CC 33))])]
3600   ""
3601   "")
3602
3603 ;
3604 ; subsi3 instruction pattern(s).
3605 ;
3606
3607 (define_insn "*subsi3_borrow_cc"
3608   [(set (reg 33)
3609         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3610                            (match_operand:SI 2 "general_operand" "d,m"))
3611                  (match_dup 1)))
3612    (set (match_operand:SI 0 "register_operand" "=d,d")
3613         (minus:SI (match_dup 1) (match_dup 2)))]
3614   "s390_match_ccmode(insn, CCL2mode)"
3615   "@
3616    slr\\t%0,%2
3617    sl\\t%0,%2"
3618   [(set_attr "op_type"  "RR,RX")
3619    (set_attr "atype"    "reg,mem")])
3620
3621 (define_insn "*subsi3_borrow_cconly"
3622   [(set (reg 33)
3623         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3624                            (match_operand:SI 2 "general_operand" "d,m"))
3625                  (match_dup 1)))
3626    (clobber (match_scratch:SI 0 "=d,d"))]
3627   "s390_match_ccmode(insn, CCL2mode)"
3628   "@
3629    slr\\t%0,%2
3630    sl\\t%0,%2"
3631   [(set_attr "op_type"  "RR,RX")
3632    (set_attr "atype"    "reg,mem")])
3633
3634 (define_insn "*subsi3_cc"
3635   [(set (reg 33)
3636         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3637                            (match_operand:SI 2 "general_operand" "d,m"))
3638                  (const_int 0)))
3639    (set (match_operand:SI 0 "register_operand" "=d,d")
3640         (minus:SI (match_dup 1) (match_dup 2)))]
3641   "s390_match_ccmode(insn, CCLmode)"
3642   "@
3643    slr\\t%0,%2
3644    sl\\t%0,%2"
3645   [(set_attr "op_type"  "RR,RX")
3646    (set_attr "atype"    "reg,mem")])
3647
3648 (define_insn "*subsi3_cconly"
3649   [(set (reg 33)
3650         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3651                            (match_operand:SI 2 "general_operand" "d,m"))
3652                  (const_int 0)))
3653    (clobber (match_scratch:SI 0 "=d,d"))]
3654   "s390_match_ccmode(insn, CCLmode)"
3655   "@
3656    slr\\t%0,%2
3657    sl\\t%0,%2"
3658   [(set_attr "op_type"  "RR,RX")
3659    (set_attr "atype"    "reg,mem")])
3660
3661 (define_insn "*subsi3_sign"
3662   [(set (match_operand:SI 0 "register_operand" "=d")
3663         (minus:SI (match_operand:SI 1 "register_operand" "0")
3664                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3665    (clobber (reg:CC 33))]
3666   ""
3667   "sh\\t%0,%2"
3668   [(set_attr "op_type"  "RX")
3669    (set_attr "atype"    "mem")])
3670
3671 (define_insn "*subsi3_sub"
3672   [(set (match_operand:SI 0 "register_operand" "=d")
3673         (minus:SI (match_operand:SI 1 "register_operand" "0")
3674                   (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3675    (clobber (reg:CC 33))]
3676   ""
3677   "sh\\t%0,%2"
3678   [(set_attr "op_type"  "RX")
3679    (set_attr "atype"    "mem")])
3680
3681 (define_insn "subsi3"
3682   [(set (match_operand:SI 0 "register_operand" "=d,d")
3683         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3684                   (match_operand:SI 2 "general_operand" "d,m")))
3685    (clobber (reg:CC 33))]
3686   ""
3687   "@
3688    sr\\t%0,%2
3689    s\\t%0,%2"
3690   [(set_attr "op_type"  "RR,RX")
3691    (set_attr "atype"    "reg,mem")])
3692
3693
3694 ;
3695 ; subdf3 instruction pattern(s).
3696 ;
3697
3698 (define_expand "subdf3"
3699   [(parallel
3700     [(set (match_operand:DF 0 "register_operand" "=f,f")
3701           (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3702                     (match_operand:DF 2 "general_operand" "f,m")))
3703      (clobber (reg:CC 33))])]
3704   "TARGET_HARD_FLOAT"
3705   "")
3706
3707 (define_insn "*subdf3"
3708   [(set (match_operand:DF 0 "register_operand" "=f,f")
3709         (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3710                   (match_operand:DF 2 "general_operand" "f,m")))
3711    (clobber (reg:CC 33))]
3712   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3713   "@
3714    sdbr\\t%0,%2
3715    sdb\\t%0,%2"
3716   [(set_attr "op_type"  "RRE,RXE")
3717    (set_attr "atype"    "reg,mem")])
3718
3719 (define_insn "*subdf3_ibm"
3720   [(set (match_operand:DF 0 "register_operand" "=f,f")
3721         (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3722                   (match_operand:DF 2 "general_operand" "f,m")))
3723    (clobber (reg:CC 33))]
3724   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3725   "@
3726    sdr\\t%0,%2
3727    sd\\t%0,%2"
3728   [(set_attr "op_type"  "RR,RX")
3729    (set_attr "atype"    "reg,mem")])
3730
3731 ;
3732 ; subsf3 instruction pattern(s).
3733 ;
3734
3735 (define_expand "subsf3"
3736   [(parallel
3737     [(set (match_operand:SF 0 "register_operand" "=f,f")
3738           (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3739                     (match_operand:SF 2 "general_operand" "f,m")))
3740      (clobber (reg:CC 33))])]
3741   "TARGET_HARD_FLOAT"
3742   "")
3743
3744 (define_insn "*subsf3"
3745   [(set (match_operand:SF 0 "register_operand" "=f,f")
3746         (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3747                   (match_operand:SF 2 "general_operand" "f,m")))
3748    (clobber (reg:CC 33))]
3749   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3750   "@
3751    sebr\\t%0,%2
3752    seb\\t%0,%2"
3753   [(set_attr "op_type"  "RRE,RXE")
3754    (set_attr "atype"    "reg,mem")])
3755
3756 (define_insn "*subsf3_ibm"
3757   [(set (match_operand:SF 0 "register_operand" "=f,f")
3758         (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3759                   (match_operand:SF 2 "general_operand" "f,m")))
3760    (clobber (reg:CC 33))]
3761   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3762   "@
3763    ser\\t%0,%2
3764    se\\t%0,%2"
3765   [(set_attr "op_type"  "RR,RX")
3766    (set_attr "atype"    "reg,mem")])
3767
3768
3769 ;;
3770 ;;- Multiply instructions.
3771 ;;
3772
3773 ;
3774 ; muldi3 instruction pattern(s).
3775 ;
3776
3777 (define_insn "*muldi3_sign"
3778   [(set (match_operand:DI 0 "register_operand" "=d,d")
3779         (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3780                  (match_operand:DI 1 "register_operand" "0,0")))]
3781   "TARGET_64BIT"
3782   "@
3783    msgfr\\t%0,%2
3784    msgf\\t%0,%2"
3785   [(set_attr "op_type"  "RRE,RXE")
3786    (set_attr "atype"    "reg,mem")
3787    (set_attr "type"     "imul")])
3788
3789
3790 (define_insn "muldi3"
3791   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3792         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3793                  (match_operand:DI 2 "general_operand" "d,K,m")))]
3794   "TARGET_64BIT"
3795   "@
3796    msgr\\t%0,%2
3797    mghi\\t%0,%h2
3798    msg\\t%0,%2"
3799   [(set_attr "op_type"  "RRE,RI,RXE")
3800    (set_attr "atype"    "reg,reg,mem")
3801    (set_attr "type"     "imul")])
3802
3803 ;
3804 ; mulsi3 instruction pattern(s).
3805 ;
3806
3807 (define_insn "mulsi3"
3808   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3809         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3810                   (match_operand:SI 2 "general_operand" "d,K,m")))]
3811   ""
3812   "@
3813    msr\\t%0,%2
3814    mhi\\t%0,%h2
3815    ms\\t%0,%2"
3816   [(set_attr "op_type"  "RRE,RI,RX")
3817    (set_attr "atype"    "reg,reg,mem")
3818    (set_attr "type"     "imul")])
3819
3820 ;
3821 ; mulsidi3 instruction pattern(s).
3822 ;
3823
3824 (define_expand "mulsidi3"
3825   [(set (match_operand:DI 0 "register_operand" "")
3826         (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3827                  (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3828   "!TARGET_64BIT"
3829   "
3830 {
3831   rtx insn;
3832
3833   emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3834   insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3835
3836   REG_NOTES (insn) =
3837         gen_rtx_EXPR_LIST (REG_EQUAL,
3838                            gen_rtx_MULT (DImode,
3839                                 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3840                                 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3841                            REG_NOTES (insn));
3842   DONE;
3843 }")
3844
3845 (define_insn "mulsi_6432"
3846    [(set (match_operand:DI 0 "register_operand" "=d,d")
3847          (mult:DI (sign_extend:DI
3848                     (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3849                   (sign_extend:DI
3850                     (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3851    "!TARGET_64BIT"
3852    "@
3853     mr\\t%0,%2
3854     m\\t%0,%2"
3855   [(set_attr "op_type"  "RR,RX")
3856    (set_attr "atype"    "reg,mem")
3857    (set_attr "type"     "imul")])
3858
3859 ;
3860 ; muldf3 instruction pattern(s).
3861 ;
3862
3863 (define_expand "muldf3"
3864   [(parallel
3865     [(set (match_operand:DF 0 "register_operand" "=f,f")
3866           (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3867                    (match_operand:DF 2 "general_operand" "f,m")))
3868      (clobber (reg:CC 33))])]
3869   "TARGET_HARD_FLOAT"
3870   "")
3871
3872 (define_insn "*muldf3"
3873   [(set (match_operand:DF 0 "register_operand" "=f,f")
3874         (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3875                  (match_operand:DF 2 "general_operand" "f,m")))
3876    (clobber (reg:CC 33))]
3877   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3878   "@
3879    mdbr\\t%0,%2
3880    mdb\\t%0,%2"
3881   [(set_attr "op_type"  "RRE,RXE")
3882    (set_attr "type"     "fmul")
3883    (set_attr "atype"    "reg,mem")])
3884
3885 (define_insn "*muldf3_ibm"
3886   [(set (match_operand:DF 0 "register_operand" "=f,f")
3887         (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3888                  (match_operand:DF 2 "general_operand" "f,m")))
3889    (clobber (reg:CC 33))]
3890   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3891   "@
3892    mdr\\t%0,%2
3893    md\\t%0,%2"
3894   [(set_attr "op_type"  "RR,RX")
3895    (set_attr "type"    "fmul")
3896    (set_attr "atype"    "reg,mem")])
3897
3898 ;
3899 ; mulsf3 instruction pattern(s).
3900 ;
3901
3902 (define_expand "mulsf3"
3903   [(parallel
3904     [(set (match_operand:SF 0 "register_operand" "=f,f")
3905           (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3906                    (match_operand:SF 2 "general_operand" "f,m")))
3907      (clobber (reg:CC 33))])]
3908   "TARGET_HARD_FLOAT"
3909   "")
3910
3911 (define_insn "*mulsf3"
3912   [(set (match_operand:SF 0 "register_operand" "=f,f")
3913         (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3914                  (match_operand:SF 2 "general_operand" "f,m")))
3915    (clobber (reg:CC 33))]
3916   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3917   "@
3918    meebr\\t%0,%2
3919    meeb\\t%0,%2"
3920   [(set_attr "op_type"  "RRE,RXE")
3921    (set_attr "type"     "fmul")
3922    (set_attr "atype"    "reg,mem")])
3923
3924 (define_insn "*mulsf3_ibm"
3925   [(set (match_operand:SF 0 "register_operand" "=f,f")
3926         (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3927                  (match_operand:SF 2 "general_operand" "f,m")))
3928    (clobber (reg:CC 33))]
3929   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3930   "@
3931    mer\\t%0,%2
3932    me\\t%0,%2"
3933   [(set_attr "op_type"  "RR,RX")
3934    (set_attr "type"     "fmul")
3935    (set_attr "atype"    "reg,mem")])
3936
3937
3938 ;;
3939 ;;- Divide and modulo instructions.
3940 ;;
3941
3942 ;
3943 ; divmoddi4 instruction pattern(s).
3944 ;
3945
3946 (define_expand "divmoddi4"
3947   [(parallel [(set (match_operand:DI 0 "general_operand" "")
3948                    (div:DI (match_operand:DI 1 "general_operand" "")
3949                            (match_operand:DI 2 "general_operand" "")))
3950               (set (match_operand:DI 3 "general_operand" "")
3951                    (mod:DI (match_dup 1) (match_dup 2)))])
3952    (clobber (match_dup 4))]
3953   "TARGET_64BIT"
3954   "
3955 {
3956   rtx insn, div_equal, mod_equal, equal;
3957
3958   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3959   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3960   equal = gen_rtx_IOR (TImode,
3961                        gen_rtx_ZERO_EXTEND (TImode, div_equal),
3962                        gen_rtx_ASHIFT (TImode,
3963                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3964                                        GEN_INT (64)));
3965
3966   operands[4] = gen_reg_rtx(TImode);
3967   emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3968   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3969   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3970   insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3971   REG_NOTES (insn) =
3972         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3973
3974   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3975   REG_NOTES (insn) =
3976         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3977
3978   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3979   REG_NOTES (insn) =
3980         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3981
3982   DONE;
3983 }")
3984
3985 (define_insn "divmodtidi3"
3986   [(set (match_operand:TI 0 "register_operand" "=d,d")
3987         (ior:TI
3988           (zero_extend:TI
3989             (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3990                     (match_operand:DI 2 "general_operand" "d,m")))
3991           (ashift:TI
3992             (zero_extend:TI
3993               (mod:DI (truncate:DI (match_dup 1))
3994                       (match_dup 2)))
3995             (const_int 64))))]
3996   "TARGET_64BIT"
3997   "@
3998    dsgr\\t%0,%2
3999    dsg\\t%0,%2"
4000   [(set_attr "op_type"  "RRE,RXE")
4001    (set_attr "type"     "idiv")
4002    (set_attr "atype"    "reg,mem")])
4003
4004 (define_insn "divmodtisi3"
4005   [(set (match_operand:TI 0 "register_operand" "=d,d")
4006         (ior:TI
4007           (zero_extend:TI
4008             (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
4009                     (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4010           (ashift:TI
4011             (zero_extend:TI
4012               (mod:DI (truncate:DI (match_dup 1))
4013                       (sign_extend:DI (match_dup 2))))
4014             (const_int 64))))]
4015   "TARGET_64BIT"
4016   "@
4017    dsgfr\\t%0,%2
4018    dsgf\\t%0,%2"
4019   [(set_attr "op_type"  "RRE,RXE")
4020    (set_attr "type"     "idiv")
4021    (set_attr "atype"    "reg,mem")])
4022
4023 ;
4024 ; udivmoddi4 instruction pattern(s).
4025 ;
4026
4027 (define_expand "udivmoddi4"
4028   [(parallel [(set (match_operand:DI 0 "general_operand" "")
4029                    (udiv:DI (match_operand:DI 1 "general_operand" "")
4030                             (match_operand:DI 2 "nonimmediate_operand" "")))
4031               (set (match_operand:DI 3 "general_operand" "")
4032                    (umod:DI (match_dup 1) (match_dup 2)))])
4033    (clobber (match_dup 4))]
4034   "TARGET_64BIT"
4035   "
4036 {
4037   rtx insn, div_equal, mod_equal, equal;
4038
4039   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4040   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4041   equal = gen_rtx_IOR (TImode,
4042                        gen_rtx_ZERO_EXTEND (TImode, div_equal),
4043                        gen_rtx_ASHIFT (TImode,
4044                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4045                                        GEN_INT (64)));
4046
4047   operands[4] = gen_reg_rtx(TImode);
4048   emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4049   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4050   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4051   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4052   REG_NOTES (insn) =
4053         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4054
4055   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4056   REG_NOTES (insn) =
4057         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4058
4059   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4060   REG_NOTES (insn) =
4061         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4062
4063   DONE;
4064 }")
4065
4066 (define_insn "udivmodtidi3"
4067   [(set (match_operand:TI 0 "register_operand" "=d,d")
4068         (ior:TI (zero_extend:TI
4069                   (truncate:DI
4070                     (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
4071                              (zero_extend:TI
4072                                (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4073                 (ashift:TI
4074                   (zero_extend:TI
4075                     (truncate:DI
4076                       (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
4077                   (const_int 64))))]
4078   "TARGET_64BIT"
4079   "@
4080    dlgr\\t%0,%2
4081    dlg\\t%0,%2"
4082   [(set_attr "op_type"  "RRE,RXE")
4083    (set_attr "type"     "idiv")
4084    (set_attr "atype"    "reg,mem")])
4085
4086 ;
4087 ; divmodsi4 instruction pattern(s).
4088 ;
4089
4090 (define_expand "divmodsi4"
4091   [(parallel [(set (match_operand:SI 0 "general_operand" "")
4092                    (div:SI (match_operand:SI 1 "general_operand" "")
4093                            (match_operand:SI 2 "nonimmediate_operand" "")))
4094               (set (match_operand:SI 3 "general_operand" "")
4095                    (mod:SI (match_dup 1) (match_dup 2)))])
4096    (clobber (match_dup 4))]
4097   "!TARGET_64BIT"
4098   "
4099 {
4100   rtx insn, div_equal, mod_equal, equal;
4101
4102   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4103   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4104   equal = gen_rtx_IOR (DImode,
4105                        gen_rtx_ZERO_EXTEND (DImode, div_equal),
4106                        gen_rtx_ASHIFT (DImode,
4107                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4108                                        GEN_INT (32)));
4109
4110   operands[4] = gen_reg_rtx(DImode);
4111   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4112   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4113   REG_NOTES (insn) =
4114         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4115
4116   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4117   REG_NOTES (insn) =
4118         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4119
4120   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4121   REG_NOTES (insn) =
4122         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4123
4124   DONE;
4125 }")
4126
4127 (define_insn "divmoddisi3"
4128   [(set (match_operand:DI 0 "register_operand" "=d,d")
4129         (ior:DI (zero_extend:DI
4130                   (truncate:SI
4131                     (div:DI (match_operand:DI 1 "register_operand" "0,0")
4132                             (sign_extend:DI
4133                               (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4134                 (ashift:DI
4135                   (zero_extend:DI
4136                     (truncate:SI
4137                       (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4138                   (const_int 32))))]
4139   "!TARGET_64BIT"
4140   "@
4141    dr\\t%0,%2
4142    d\\t%0,%2"
4143   [(set_attr "op_type"  "RR,RX")
4144    (set_attr "type"     "idiv")
4145    (set_attr "atype"    "reg,mem")])
4146
4147 ;
4148 ; udivsi3 and umodsi3 instruction pattern(s).
4149 ;
4150
4151
4152 (define_expand "udivsi3"
4153   [(set (match_operand:SI 0 "register_operand" "=d")
4154         (udiv:SI (match_operand:SI 1 "general_operand" "")
4155                  (match_operand:SI 2 "general_operand" "")))
4156    (clobber (match_dup 3))]
4157   "!TARGET_64BIT"
4158   "
4159 {
4160   rtx insn, udiv_equal, umod_equal, equal;
4161
4162   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4163   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4164   equal = gen_rtx_IOR (DImode,
4165                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4166                        gen_rtx_ASHIFT (DImode,
4167                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4168                                        GEN_INT (32)));
4169
4170   operands[3] = gen_reg_rtx (DImode);
4171
4172   if (CONSTANT_P (operands[2]))
4173     {
4174       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4175         {
4176           rtx label1 = gen_label_rtx ();
4177
4178           operands[1] = make_safe_from (operands[1], operands[0]);
4179           emit_move_insn (operands[0], const0_rtx);
4180           emit_insn (gen_cmpsi (operands[1], operands[2]));
4181           emit_jump_insn (gen_bltu (label1));
4182           emit_move_insn (operands[0], const1_rtx);
4183           emit_label (label1);
4184         }
4185       else
4186         {
4187           operands[2] = force_reg (SImode, operands[2]);
4188           operands[2] = make_safe_from (operands[2], operands[0]);
4189
4190           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4191           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4192                                              operands[2]));
4193           REG_NOTES (insn) =
4194             gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4195
4196           insn = emit_move_insn (operands[0],
4197                                  gen_lowpart (SImode, operands[3]));
4198           REG_NOTES (insn) =
4199             gen_rtx_EXPR_LIST (REG_EQUAL,
4200                                udiv_equal, REG_NOTES (insn));
4201         }
4202     }
4203   else
4204     {
4205       rtx label1 = gen_label_rtx ();
4206       rtx label2 = gen_label_rtx ();
4207       rtx label3 = gen_label_rtx ();
4208
4209       operands[1] = force_reg (SImode, operands[1]);
4210       operands[1] = make_safe_from (operands[1], operands[0]);
4211       operands[2] = force_reg (SImode, operands[2]);
4212       operands[2] = make_safe_from (operands[2], operands[0]);
4213
4214       emit_move_insn (operands[0], const0_rtx);
4215       emit_insn (gen_cmpsi (operands[2], operands[1]));
4216       emit_jump_insn (gen_bgtu (label3));
4217       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4218       emit_jump_insn (gen_blt (label2));
4219       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4220       emit_jump_insn (gen_beq (label1));
4221       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4222       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4223                                          operands[2]));
4224       REG_NOTES (insn) =
4225       gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4226
4227       insn = emit_move_insn (operands[0],
4228                              gen_lowpart (SImode, operands[3]));
4229       REG_NOTES (insn) =
4230       gen_rtx_EXPR_LIST (REG_EQUAL,
4231                                udiv_equal, REG_NOTES (insn));
4232       emit_jump (label3);
4233       emit_label (label1);
4234       emit_move_insn (operands[0], operands[1]);
4235       emit_jump (label3);
4236       emit_label (label2);
4237       emit_move_insn (operands[0], const1_rtx);
4238       emit_label (label3);
4239     }
4240   emit_move_insn (operands[0], operands[0]);
4241   DONE;
4242 }")
4243
4244 (define_expand "umodsi3"
4245   [(set (match_operand:SI 0 "register_operand" "=d")
4246         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4247                  (match_operand:SI 2 "nonimmediate_operand" "")))
4248    (clobber (match_dup 3))]
4249   "!TARGET_64BIT"
4250   "
4251 {
4252   rtx insn, udiv_equal, umod_equal, equal;
4253
4254   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4255   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4256   equal = gen_rtx_IOR (DImode,
4257                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4258                        gen_rtx_ASHIFT (DImode,
4259                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4260                                        GEN_INT (32)));
4261
4262   operands[3] = gen_reg_rtx (DImode);
4263
4264   if (CONSTANT_P (operands[2]))
4265     {
4266       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4267         {
4268           rtx label1 = gen_label_rtx ();
4269
4270           operands[1] = make_safe_from (operands[1], operands[0]);
4271           emit_move_insn (operands[0], operands[1]);
4272           emit_insn (gen_cmpsi (operands[0], operands[2]));
4273           emit_jump_insn (gen_bltu (label1));
4274           emit_insn (gen_abssi2 (operands[0], operands[2]));
4275           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4276           emit_label (label1);
4277         }
4278       else
4279         {
4280           operands[2] = force_reg (SImode, operands[2]);
4281           operands[2] = make_safe_from (operands[2], operands[0]);
4282
4283           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4284           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4285                                              operands[2]));
4286           REG_NOTES (insn) =
4287             gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4288
4289           insn = emit_move_insn (operands[0],
4290                                  gen_highpart (SImode, operands[3]));
4291           REG_NOTES (insn) =
4292             gen_rtx_EXPR_LIST (REG_EQUAL,
4293                                umod_equal, REG_NOTES (insn));
4294         }
4295     }
4296   else
4297     {
4298       rtx label1 = gen_label_rtx ();
4299       rtx label2 = gen_label_rtx ();
4300       rtx label3 = gen_label_rtx ();
4301
4302       operands[1] = force_reg (SImode, operands[1]);
4303       operands[1] = make_safe_from (operands[1], operands[0]);
4304       operands[2] = force_reg (SImode, operands[2]);
4305       operands[2] = make_safe_from (operands[2], operands[0]);
4306
4307       emit_move_insn(operands[0], operands[1]);
4308       emit_insn (gen_cmpsi (operands[2], operands[1]));
4309       emit_jump_insn (gen_bgtu (label3));
4310       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4311       emit_jump_insn (gen_blt (label2));
4312       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4313       emit_jump_insn (gen_beq (label1));
4314       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4315       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4316                                          operands[2]));
4317       REG_NOTES (insn) =
4318       gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4319
4320       insn = emit_move_insn (operands[0],
4321                              gen_highpart (SImode, operands[3]));
4322       REG_NOTES (insn) =
4323       gen_rtx_EXPR_LIST (REG_EQUAL,
4324                          umod_equal, REG_NOTES (insn));
4325       emit_jump (label3);
4326       emit_label (label1);
4327       emit_move_insn (operands[0], const0_rtx);
4328       emit_jump (label3);
4329       emit_label (label2);
4330       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4331       emit_label (label3);
4332     }
4333   DONE;
4334 }")
4335
4336 ;
4337 ; divdf3 instruction pattern(s).
4338 ;
4339
4340 (define_expand "divdf3"
4341   [(parallel
4342     [(set (match_operand:DF 0 "register_operand" "=f,f")
4343           (div:DF (match_operand:DF 1 "register_operand" "0,0")
4344                   (match_operand:DF 2 "general_operand" "f,m")))
4345      (clobber (reg:CC 33))])]
4346   "TARGET_HARD_FLOAT"
4347   "")
4348
4349 (define_insn "*divdf3"
4350   [(set (match_operand:DF 0 "register_operand" "=f,f")
4351         (div:DF (match_operand:DF 1 "register_operand" "0,0")
4352                 (match_operand:DF 2 "general_operand" "f,m")))
4353    (clobber (reg:CC 33))]
4354   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4355   "@
4356    ddbr\\t%0,%2
4357    ddb\\t%0,%2"
4358   [(set_attr "op_type"  "RRE,RXE")
4359    (set_attr "type"     "fdiv")
4360    (set_attr "atype"    "reg,mem")])
4361
4362 (define_insn "*divdf3_ibm"
4363   [(set (match_operand:DF 0 "register_operand" "=f,f")
4364         (div:DF (match_operand:DF 1 "register_operand" "0,0")
4365                 (match_operand:DF 2 "general_operand" "f,m")))
4366    (clobber (reg:CC 33))]
4367   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4368   "@
4369    ddr\\t%0,%2
4370    dd\\t%0,%2"
4371   [(set_attr "op_type"  "RR,RX")
4372    (set_attr "type"     "fdiv")
4373    (set_attr "atype"    "reg,mem")])
4374
4375 ;
4376 ; divsf3 instruction pattern(s).
4377 ;
4378
4379 (define_expand "divsf3"
4380   [(parallel
4381     [(set (match_operand:SF 0 "register_operand" "=f,f")
4382           (div:SF (match_operand:SF 1 "register_operand" "0,0")
4383                   (match_operand:SF 2 "general_operand" "f,m")))
4384      (clobber (reg:CC 33))])]
4385   "TARGET_HARD_FLOAT"
4386   "")
4387
4388 (define_insn "*divsf3"
4389   [(set (match_operand:SF 0 "register_operand" "=f,f")
4390         (div:SF (match_operand:SF 1 "register_operand" "0,0")
4391                 (match_operand:SF 2 "general_operand" "f,m")))
4392    (clobber (reg:CC 33))]
4393   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4394   "@
4395    debr\\t%0,%2
4396    deb\\t%0,%2"
4397   [(set_attr "op_type"  "RRE,RXE")
4398    (set_attr "type"     "fdiv")
4399    (set_attr "atype"    "reg,mem")])
4400
4401 (define_insn "*divsf3"
4402   [(set (match_operand:SF 0 "register_operand" "=f,f")
4403         (div:SF (match_operand:SF 1 "register_operand" "0,0")
4404                 (match_operand:SF 2 "general_operand" "f,m")))
4405    (clobber (reg:CC 33))]
4406   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4407   "@
4408    der\\t%0,%2
4409    de\\t%0,%2"
4410   [(set_attr "op_type"  "RR,RX")
4411    (set_attr "type"     "fdiv")
4412    (set_attr "atype"    "reg,mem")])
4413
4414
4415 ;;
4416 ;;- And instructions.
4417 ;;
4418
4419 ;
4420 ; anddi3 instruction pattern(s).
4421 ;
4422
4423 (define_insn "*anddi3_cc"
4424   [(set (reg 33)
4425         (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4426                          (match_operand:DI 2 "general_operand" "d,m"))
4427                  (const_int 0)))
4428    (set (match_operand:DI 0 "register_operand" "=d,d")
4429         (and:DI (match_dup 1) (match_dup 2)))]
4430   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4431   "@
4432    ngr\\t%0,%2
4433    ng\\t%0,%2"
4434   [(set_attr "op_type"  "RRE,RXE")
4435    (set_attr "atype"    "reg,mem")])
4436
4437 (define_insn "*anddi3_cconly"
4438   [(set (reg 33)
4439         (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4440                          (match_operand:DI 2 "general_operand" "d,m"))
4441                  (const_int 0)))
4442    (clobber (match_scratch:DI 0 "=d,d"))]
4443   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4444   "@
4445    ngr\\t%0,%2
4446    ng\\t%0,%2"
4447   [(set_attr "op_type"  "RRE,RXE")
4448    (set_attr "atype"    "reg,mem")])
4449
4450 (define_insn "*anddi3_ni"
4451   [(set (match_operand:DI 0 "register_operand" "=d")
4452         (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4453                 (match_operand:DI 2 "immediate_operand" "n")))
4454    (clobber (reg:CC 33))]
4455   "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4456   "*
4457 {
4458   int part = s390_single_hi (operands[2], DImode, -1);
4459   operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4460
4461   switch (part)
4462     {
4463       case 0: return \"nihh\\t%0,%x2\";
4464       case 1: return \"nihl\\t%0,%x2\";
4465       case 2: return \"nilh\\t%0,%x2\";
4466       case 3: return \"nill\\t%0,%x2\";
4467       default: abort ();
4468     }
4469 }"
4470   [(set_attr "op_type"  "RI")
4471    (set_attr "atype"    "reg")])
4472
4473 (define_insn "anddi3"
4474   [(set (match_operand:DI 0 "register_operand" "=d,d")
4475         (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4476                 (match_operand:DI 2 "general_operand" "d,m")))
4477    (clobber (reg:CC 33))]
4478   "TARGET_64BIT"
4479   "@
4480    ngr\\t%0,%2
4481    ng\\t%0,%2"
4482   [(set_attr "op_type"  "RRE,RXE")
4483    (set_attr "atype"    "reg,mem")])
4484
4485 (define_insn "*anddi3_ss"
4486   [(set (match_operand:DI 0 "s_operand" "=Q")
4487         (and:DI (match_dup 0)
4488                 (match_operand:DI 1 "s_imm_operand" "Q")))
4489    (clobber (reg:CC 33))]
4490   ""
4491   "nc\\t%O0(8,%R0),%1"
4492   [(set_attr "op_type"  "SS")
4493    (set_attr "atype"    "mem")])
4494
4495 (define_insn "*anddi3_ss_inv"
4496   [(set (match_operand:DI 0 "s_operand" "=Q")
4497         (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4498                 (match_dup 0)))
4499    (clobber (reg:CC 33))]
4500   ""
4501   "nc\\t%O0(8,%R0),%1"
4502   [(set_attr "op_type"  "SS")
4503    (set_attr "atype"    "mem")])
4504
4505 ;
4506 ; andsi3 instruction pattern(s).
4507 ;
4508
4509 (define_insn "*andsi3_cc"
4510   [(set (reg 33)
4511         (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4512                          (match_operand:SI 2 "general_operand" "d,m"))
4513                  (const_int 0)))
4514    (set (match_operand:SI 0 "register_operand" "=d,d")
4515         (and:SI (match_dup 1) (match_dup 2)))]
4516   "s390_match_ccmode(insn, CCTmode)"
4517   "@
4518    nr\\t%0,%2
4519    n\\t%0,%2"
4520   [(set_attr "op_type"  "RR,RX")
4521    (set_attr "atype"    "reg,mem")])
4522
4523 (define_insn "*andsi3_cconly"
4524   [(set (reg 33)
4525         (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4526                          (match_operand:SI 2 "general_operand" "d,m"))
4527                  (const_int 0)))
4528    (clobber (match_scratch:SI 0 "=d,d"))]
4529   "s390_match_ccmode(insn, CCTmode)"
4530   "@
4531    nr\\t%0,%2
4532    n\\t%0,%2"
4533   [(set_attr "op_type"  "RR,RX")
4534    (set_attr "atype"    "reg,mem")])
4535
4536 (define_insn "*andsi3_ni"
4537   [(set (match_operand:SI 0 "register_operand" "=d")
4538         (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4539                 (match_operand:SI 2 "immediate_operand" "n")))
4540    (clobber (reg:CC 33))]
4541   "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4542   "*
4543 {
4544   int part = s390_single_hi (operands[2], SImode, -1);
4545   operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4546
4547   switch (part)
4548     {
4549       case 0: return \"nilh\\t%0,%x2\";
4550       case 1: return \"nill\\t%0,%x2\";
4551       default: abort ();
4552     }
4553 }"
4554   [(set_attr "op_type"  "RI")
4555    (set_attr "atype"    "reg")])
4556
4557 (define_insn "andsi3"
4558   [(set (match_operand:SI 0 "register_operand" "=d,d")
4559         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4560                 (match_operand:SI 2 "general_operand" "d,m")))
4561    (clobber (reg:CC 33))]
4562   ""
4563   "@
4564    nr\\t%0,%2
4565    n\\t%0,%2"
4566   [(set_attr "op_type"  "RR,RX")
4567    (set_attr "atype"    "reg,mem")])
4568
4569 (define_insn "*andsi3_ss"
4570   [(set (match_operand:SI 0 "s_operand" "=Q")
4571         (and:SI (match_dup 0)
4572                 (match_operand:SI 1 "s_imm_operand" "Q")))
4573    (clobber (reg:CC 33))]
4574   ""
4575   "nc\\t%O0(4,%R0),%1"
4576   [(set_attr "op_type"  "SS")
4577    (set_attr "atype"    "mem")])
4578
4579 (define_insn "*andsi3_ss_inv"
4580   [(set (match_operand:SI 0 "s_operand" "=Q")
4581         (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4582                 (match_dup 0)))
4583    (clobber (reg:CC 33))]
4584   ""
4585   "nc\\t%O0(4,%R0),%1"
4586   [(set_attr "op_type"  "SS")
4587    (set_attr "atype"    "mem")])
4588
4589 ;
4590 ; andhi3 instruction pattern(s).
4591 ;
4592
4593 (define_insn "*andhi3_ni"
4594   [(set (match_operand:HI 0 "register_operand" "=d,d")
4595         (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4596                 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4597    (clobber (reg:CC 33))]
4598   "TARGET_64BIT"
4599   "@
4600    nr\\t%0,%2
4601    nill\\t%0,%x2"
4602   [(set_attr "op_type"  "RR,RI")
4603    (set_attr "atype"    "reg")])
4604
4605 (define_insn "andhi3"
4606   [(set (match_operand:HI 0 "register_operand" "=d")
4607         (and:HI (match_operand:HI 1 "register_operand" "%0")
4608                 (match_operand:HI 2 "nonmemory_operand" "d")))
4609    (clobber (reg:CC 33))]
4610   ""
4611   "nr\\t%0,%2"
4612   [(set_attr "op_type"  "RR")
4613    (set_attr "atype"    "reg")])
4614
4615 (define_insn "*andhi3_ss"
4616   [(set (match_operand:HI 0 "s_operand" "=Q")
4617         (and:HI (match_dup 0)
4618                 (match_operand:HI 1 "s_imm_operand" "Q")))
4619    (clobber (reg:CC 33))]
4620   ""
4621   "nc\\t%O0(2,%R0),%1"
4622   [(set_attr "op_type"  "SS")
4623    (set_attr "atype"    "mem")])
4624
4625 (define_insn "*andhi3_ss_inv"
4626   [(set (match_operand:HI 0 "s_operand" "=Q")
4627         (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4628                 (match_dup 0)))
4629    (clobber (reg:CC 33))]
4630   ""
4631   "nc\\t%O0(2,%R0),%1"
4632   [(set_attr "op_type"  "SS")
4633    (set_attr "atype"    "mem")])
4634
4635 ;
4636 ; andqi3 instruction pattern(s).
4637 ;
4638
4639 (define_insn "*andqi3_ni"
4640   [(set (match_operand:QI 0 "register_operand" "=d,d")
4641         (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4642                 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4643    (clobber (reg:CC 33))]
4644   "TARGET_64BIT"
4645   "@
4646    nr\\t%0,%2
4647    nill\\t%0,%b2"
4648   [(set_attr "op_type"  "RR,RI")
4649    (set_attr "atype"    "reg")])
4650
4651 (define_insn "andqi3"
4652   [(set (match_operand:QI 0 "register_operand" "=d")
4653         (and:QI (match_operand:QI 1 "register_operand" "%0")
4654                 (match_operand:QI 2 "nonmemory_operand" "d")))
4655    (clobber (reg:CC 33))]
4656   ""
4657   "nr\\t%0,%2"
4658   [(set_attr "op_type"  "RR")
4659    (set_attr "atype"    "reg")])
4660
4661 (define_insn "*andqi3_ss"
4662   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4663         (and:QI (match_dup 0)
4664                 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4665    (clobber (reg:CC 33))]
4666   ""
4667   "@
4668    ni\\t%0,%b1
4669    nc\\t%O0(1,%R0),%1"
4670   [(set_attr "op_type"  "SI,SS")
4671    (set_attr "atype"    "mem")])
4672
4673 (define_insn "*andqi3_ss_inv"
4674   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4675         (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4676                 (match_dup 0)))
4677    (clobber (reg:CC 33))]
4678   ""
4679   "@
4680    ni\\t%0,%b1
4681    nc\\t%O0(1,%R0),%1"
4682   [(set_attr "op_type"  "SI,SS")
4683    (set_attr "atype"    "mem")])
4684
4685
4686 ;;
4687 ;;- Bit set (inclusive or) instructions.
4688 ;;
4689
4690 ;
4691 ; iordi3 instruction pattern(s).
4692 ;
4693
4694 (define_insn "*iordi3_cc"
4695   [(set (reg 33)
4696         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4697                          (match_operand:DI 2 "general_operand" "d,m"))
4698                  (const_int 0)))
4699    (set (match_operand:DI 0 "register_operand" "=d,d")
4700         (ior:DI (match_dup 1) (match_dup 2)))]
4701   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4702   "@
4703    ogr\\t%0,%2
4704    og\\t%0,%2"
4705   [(set_attr "op_type"  "RRE,RXE")
4706    (set_attr "atype"    "reg,mem")])
4707
4708 (define_insn "*iordi3_cconly"
4709   [(set (reg 33)
4710         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4711                          (match_operand:DI 2 "general_operand" "d,m"))
4712                  (const_int 0)))
4713    (clobber (match_scratch:DI 0 "=d,d"))]
4714   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4715   "@
4716    ogr\\t%0,%2
4717    og\\t%0,%2"
4718   [(set_attr "op_type"  "RRE,RXE")
4719    (set_attr "atype"    "reg,mem")])
4720
4721 (define_insn "*iordi3_oi"
4722   [(set (match_operand:DI 0 "register_operand" "=d")
4723         (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4724                 (match_operand:DI 2 "immediate_operand" "n")))
4725    (clobber (reg:CC 33))]
4726   "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4727   "*
4728 {
4729   int part = s390_single_hi (operands[2], DImode, 0);
4730   operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4731
4732   switch (part)
4733     {
4734       case 0: return \"oihh\\t%0,%x2\";
4735       case 1: return \"oihl\\t%0,%x2\";
4736       case 2: return \"oilh\\t%0,%x2\";
4737       case 3: return \"oill\\t%0,%x2\";
4738       default: abort ();
4739     }
4740 }"
4741   [(set_attr "op_type"  "RI")
4742    (set_attr "atype"    "reg")])
4743
4744 (define_insn "iordi3"
4745   [(set (match_operand:DI 0 "register_operand" "=d,d")
4746         (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4747                 (match_operand:DI 2 "general_operand" "d,m")))
4748    (clobber (reg:CC 33))]
4749   "TARGET_64BIT"
4750   "@
4751    ogr\\t%0,%2
4752    og\\t%0,%2"
4753   [(set_attr "op_type"  "RRE,RXE")
4754    (set_attr "atype"    "reg,mem")])
4755
4756 (define_insn "*iordi3_ss"
4757   [(set (match_operand:DI 0 "s_operand" "=Q")
4758         (ior:DI (match_dup 0)
4759                 (match_operand:DI 1 "s_imm_operand" "Q")))
4760    (clobber (reg:CC 33))]
4761   ""
4762   "oc\\t%O0(8,%R0),%1"
4763   [(set_attr "op_type"  "SS")
4764    (set_attr "atype"    "mem")])
4765
4766 (define_insn "*iordi3_ss_inv"
4767   [(set (match_operand:DI 0 "s_operand" "=Q")
4768         (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4769                 (match_dup 0)))
4770    (clobber (reg:CC 33))]
4771   ""
4772   "oc\\t%O0(8,%R0),%1"
4773   [(set_attr "op_type"  "SS")
4774    (set_attr "atype"    "mem")])
4775
4776 ;
4777 ; iorsi3 instruction pattern(s).
4778 ;
4779
4780 (define_insn "*iorsi3_cc"
4781   [(set (reg 33)
4782         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4783                          (match_operand:SI 2 "general_operand" "d,m"))
4784                  (const_int 0)))
4785    (set (match_operand:SI 0 "register_operand" "=d,d")
4786         (ior:SI (match_dup 1) (match_dup 2)))]
4787   "s390_match_ccmode(insn, CCTmode)"
4788   "@
4789    or\\t%0,%2
4790    o\\t%0,%2"
4791   [(set_attr "op_type"  "RR,RX")
4792    (set_attr "atype"    "reg,mem")])
4793
4794 (define_insn "*iorsi3_cconly"
4795   [(set (reg 33)
4796         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4797                          (match_operand:SI 2 "general_operand" "d,m"))
4798                  (const_int 0)))
4799    (clobber (match_scratch:SI 0 "=d,d"))]
4800   "s390_match_ccmode(insn, CCTmode)"
4801   "@
4802    or\\t%0,%2
4803    o\\t%0,%2"
4804   [(set_attr "op_type"  "RR,RX")
4805    (set_attr "atype"    "reg,mem")])
4806
4807 (define_insn "*iorsi3_oi"
4808   [(set (match_operand:SI 0 "register_operand" "=d")
4809         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4810                 (match_operand:SI 2 "immediate_operand" "n")))
4811    (clobber (reg:CC 33))]
4812   "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4813   "*
4814 {
4815   int part = s390_single_hi (operands[2], SImode, 0);
4816   operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4817
4818   switch (part)
4819     {
4820       case 0: return \"oilh\\t%0,%x2\";
4821       case 1: return \"oill\\t%0,%x2\";
4822       default: abort ();
4823     }
4824 }"
4825   [(set_attr "op_type"  "RI")
4826    (set_attr "atype"    "reg")])
4827
4828 (define_insn "iorsi3"
4829   [(set (match_operand:SI 0 "register_operand" "=d,d")
4830         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4831                 (match_operand:SI 2 "general_operand" "d,m")))
4832    (clobber (reg:CC 33))]
4833   ""
4834   "@
4835    or\\t%0,%2
4836    o\\t%0,%2"
4837   [(set_attr "op_type"  "RR,RX")
4838    (set_attr "atype"    "reg,mem")])
4839
4840 (define_insn "*iorsi3_ss"
4841   [(set (match_operand:SI 0 "s_operand" "=Q")
4842         (ior:SI (match_dup 0)
4843                 (match_operand:SI 1 "s_imm_operand" "Q")))
4844    (clobber (reg:CC 33))]
4845   ""
4846   "oc\\t%O0(4,%R0),%1"
4847   [(set_attr "op_type"  "SS")
4848    (set_attr "atype"    "mem")])
4849
4850 (define_insn "*iorsi3_ss_inv"
4851   [(set (match_operand:SI 0 "s_operand" "=Q")
4852         (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4853                 (match_dup 0)))
4854    (clobber (reg:CC 33))]
4855   ""
4856   "oc\\t%O0(4,%R0),%1"
4857   [(set_attr "op_type"  "SS")
4858    (set_attr "atype"    "mem")])
4859
4860 ;
4861 ; iorhi3 instruction pattern(s).
4862 ;
4863
4864 (define_insn "*iorhi3_oi"
4865   [(set (match_operand:HI 0 "register_operand" "=d,d")
4866         (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4867                 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4868    (clobber (reg:CC 33))]
4869   "TARGET_64BIT"
4870   "@
4871    or\\t%0,%2
4872    oill\\t%0,%x2"
4873   [(set_attr "op_type"  "RR,RI")
4874    (set_attr "atype"    "reg")])
4875
4876 (define_insn "iorhi3"
4877   [(set (match_operand:HI 0 "register_operand" "=d")
4878         (ior:HI (match_operand:HI 1 "register_operand" "%0")
4879                 (match_operand:HI 2 "nonmemory_operand" "d")))
4880    (clobber (reg:CC 33))]
4881   ""
4882   "or\\t%0,%2"
4883   [(set_attr "op_type"  "RR")
4884    (set_attr "atype"    "reg")])
4885
4886 (define_insn "*iorhi3_ss"
4887   [(set (match_operand:HI 0 "s_operand" "=Q")
4888         (ior:HI (match_dup 0)
4889                 (match_operand:HI 1 "s_imm_operand" "Q")))
4890    (clobber (reg:CC 33))]
4891   ""
4892   "oc\\t%O0(2,%R0),%1"
4893   [(set_attr "op_type"  "SS")
4894    (set_attr "atype"    "mem")])
4895
4896 (define_insn "*iorhi3_ss_inv"
4897   [(set (match_operand:HI 0 "s_operand" "=Q")
4898         (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4899                 (match_dup 0)))
4900    (clobber (reg:CC 33))]
4901   ""
4902   "oc\\t%O0(2,%R0),%1"
4903   [(set_attr "op_type"  "SS")
4904    (set_attr "atype"    "mem")])
4905
4906 ;
4907 ; iorqi3 instruction pattern(s).
4908 ;
4909
4910 (define_insn "*iorqi3_oi"
4911   [(set (match_operand:QI 0 "register_operand" "=d,d")
4912         (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4913                 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4914    (clobber (reg:CC 33))]
4915   "TARGET_64BIT"
4916   "@
4917    or\\t%0,%2
4918    oill\\t%0,%b2"
4919   [(set_attr "op_type"  "RR,RI")
4920    (set_attr "atype"    "reg")])
4921
4922 (define_insn "iorqi3"
4923   [(set (match_operand:QI 0 "register_operand" "=d")
4924         (ior:QI (match_operand:QI 1 "register_operand" "%0")
4925                 (match_operand:QI 2 "nonmemory_operand" "d")))
4926    (clobber (reg:CC 33))]
4927   ""
4928   "or\\t%0,%2"
4929   [(set_attr "op_type"  "RR")
4930    (set_attr "atype"    "reg")])
4931
4932 (define_insn "*iorqi3_ss"
4933   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4934         (ior:QI (match_dup 0)
4935                 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4936    (clobber (reg:CC 33))]
4937   ""
4938   "@
4939    oi\\t%0,%b1
4940    oc\\t%O0(1,%R0),%1"
4941   [(set_attr "op_type"  "SI,SS")
4942    (set_attr "atype"    "reg,mem")])
4943
4944 (define_insn "*iorqi3_ss_inv"
4945   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4946         (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4947                 (match_dup 0)))
4948    (clobber (reg:CC 33))]
4949   ""
4950   "@
4951    oi\\t%0,%b1
4952    oc\\t%O0(1,%R0),%1"
4953   [(set_attr "op_type"  "SI,SS")
4954    (set_attr "atype"    "reg,mem")])
4955
4956
4957 ;;
4958 ;;- Xor instructions.
4959 ;;
4960
4961 ;
4962 ; xordi3 instruction pattern(s).
4963 ;
4964
4965 (define_insn "*xordi3_cc"
4966   [(set (reg 33)
4967         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4968                          (match_operand:DI 2 "general_operand" "d,m"))
4969                  (const_int 0)))
4970    (set (match_operand:DI 0 "register_operand" "=d,d")
4971         (xor:DI (match_dup 1) (match_dup 2)))]
4972   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4973   "@
4974    xgr\\t%0,%2
4975    xg\\t%0,%2"
4976   [(set_attr "op_type"  "RRE,RXE")
4977    (set_attr "atype"    "reg,mem")])
4978
4979 (define_insn "*xordi3_cconly"
4980   [(set (reg 33)
4981         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4982                          (match_operand:DI 2 "general_operand" "d,m"))
4983                  (const_int 0)))
4984    (clobber (match_scratch:DI 0 "=d,d"))]
4985   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4986   "@
4987    xgr\\t%0,%2
4988    xr\\t%0,%2"
4989   [(set_attr "op_type"  "RRE,RXE")
4990    (set_attr "atype"    "reg,mem")])
4991
4992 (define_insn "xordi3"
4993   [(set (match_operand:DI 0 "register_operand" "=d,d")
4994         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4995                 (match_operand:DI 2 "general_operand" "d,m")))
4996    (clobber (reg:CC 33))]
4997   "TARGET_64BIT"
4998   "@
4999    xgr\\t%0,%2
5000    xg\\t%0,%2"
5001   [(set_attr "op_type"  "RRE,RXE")
5002    (set_attr "atype"    "reg,mem")])
5003
5004 (define_insn "*xordi3_ss"
5005   [(set (match_operand:DI 0 "s_operand" "=Q")
5006         (xor:DI (match_dup 0)
5007                 (match_operand:DI 1 "s_imm_operand" "Q")))
5008    (clobber (reg:CC 33))]
5009   ""
5010   "xc\\t%O0(8,%R0),%1"
5011   [(set_attr "op_type"  "SS")
5012    (set_attr "atype"    "mem")])
5013
5014 (define_insn "*xordi3_ss_inv"
5015   [(set (match_operand:DI 0 "s_operand" "=Q")
5016         (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
5017                 (match_dup 0)))
5018    (clobber (reg:CC 33))]
5019   ""
5020   "xc\\t%O0(8,%R0),%1"
5021   [(set_attr "op_type"  "SS")
5022    (set_attr "atype"    "mem")])
5023
5024 ;
5025 ; xorsi3 instruction pattern(s).
5026 ;
5027
5028 (define_insn "*xorsi3_cc"
5029   [(set (reg 33)
5030         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5031                          (match_operand:SI 2 "general_operand" "d,m"))
5032                  (const_int 0)))
5033    (set (match_operand:SI 0 "register_operand" "=d,d")
5034         (xor:SI (match_dup 1) (match_dup 2)))]
5035   "s390_match_ccmode(insn, CCTmode)"
5036   "@
5037    xr\\t%0,%2
5038    x\\t%0,%2"
5039   [(set_attr "op_type"  "RR,RX")
5040    (set_attr "atype"    "reg,mem")])
5041
5042 (define_insn "*xorsi3_cconly"
5043   [(set (reg 33)
5044         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5045                          (match_operand:SI 2 "general_operand" "d,m"))
5046                  (const_int 0)))
5047    (clobber (match_scratch:SI 0 "=d,d"))]
5048   "s390_match_ccmode(insn, CCTmode)"
5049   "@
5050    xr\\t%0,%2
5051    x\\t%0,%2"
5052   [(set_attr "op_type"  "RR,RX")
5053    (set_attr "atype"    "reg,mem")])
5054
5055 (define_insn "xorsi3"
5056   [(set (match_operand:SI 0 "register_operand" "=d,d")
5057         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5058                 (match_operand:SI 2 "general_operand" "d,m")))
5059    (clobber (reg:CC 33))]
5060   ""
5061   "@
5062    xr\\t%0,%2
5063    x\\t%0,%2"
5064   [(set_attr "op_type"  "RR,RX")
5065    (set_attr "atype"    "reg,mem")])
5066
5067 (define_insn "*xorsi3_ss"
5068   [(set (match_operand:SI 0 "s_operand" "=Q")
5069         (xor:SI (match_dup 0)
5070                 (match_operand:SI 1 "s_imm_operand" "Q")))
5071    (clobber (reg:CC 33))]
5072   ""
5073   "xc\\t%O0(4,%R0),%1"
5074   [(set_attr "op_type"  "SS")
5075    (set_attr "atype"    "mem")])
5076
5077 (define_insn "*xorsi3_ss_inv"
5078   [(set (match_operand:SI 0 "s_operand" "=Q")
5079         (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
5080                 (match_dup 0)))
5081    (clobber (reg:CC 33))]
5082   ""
5083   "xc\\t%O0(4,%R0),%1"
5084   [(set_attr "op_type"  "SS")
5085    (set_attr "atype"    "mem")])
5086
5087 ;
5088 ; xorhi3 instruction pattern(s).
5089 ;
5090
5091 (define_insn "xorhi3"
5092   [(set (match_operand:HI 0 "register_operand" "=d")
5093         (xor:HI (match_operand:HI 1 "register_operand" "%0")
5094                 (match_operand:HI 2 "nonmemory_operand" "d")))
5095    (clobber (reg:CC 33))]
5096   ""
5097   "xr\\t%0,%2"
5098   [(set_attr "op_type"  "RR")
5099    (set_attr "atype"    "reg")])
5100
5101 (define_insn "*xorhi3_ss"
5102   [(set (match_operand:HI 0 "s_operand" "=Q")
5103         (xor:HI (match_dup 0)
5104                 (match_operand:HI 1 "s_imm_operand" "Q")))
5105    (clobber (reg:CC 33))]
5106   ""
5107   "xc\\t%O0(2,%R0),%1"
5108   [(set_attr "op_type"  "SS")
5109    (set_attr "atype"    "mem")])
5110
5111 (define_insn "*xorhi3_ss_inv"
5112   [(set (match_operand:HI 0 "s_operand" "=Q")
5113         (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
5114                 (match_dup 0)))
5115    (clobber (reg:CC 33))]
5116   ""
5117   "xc\\t%O0(2,%R0),%1"
5118   [(set_attr "op_type"  "SS")
5119    (set_attr "atype"    "mem")])
5120
5121 ;
5122 ; xorqi3 instruction pattern(s).
5123 ;
5124
5125 (define_insn "xorqi3"
5126   [(set (match_operand:QI 0 "register_operand" "=d")
5127         (xor:QI (match_operand:QI 1 "register_operand" "%0")
5128                 (match_operand:QI 2 "nonmemory_operand" "d")))
5129    (clobber (reg:CC 33))]
5130   ""
5131   "xr\\t%0,%2"
5132   [(set_attr "op_type"  "RR")
5133    (set_attr "atype"    "reg")])
5134
5135 (define_insn "*xorqi3_ss"
5136   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5137         (xor:QI (match_dup 0)
5138                 (match_operand:QI 1 "s_imm_operand" "n,Q")))
5139    (clobber (reg:CC 33))]
5140   ""
5141   "@
5142    xi\\t%0,%b1
5143    xc\\t%O0(1,%R0),%1"
5144   [(set_attr "op_type"  "SI,SS")
5145    (set_attr "atype"    "mem")])
5146
5147 (define_insn "*xorqi3_ss_inv"
5148   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5149         (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
5150                 (match_dup 0)))
5151    (clobber (reg:CC 33))]
5152   ""
5153   "@
5154    xi\\t%0,%b1
5155    xc\\t%O0(1,%R0),%1"
5156   [(set_attr "op_type"  "SI,SS")
5157    (set_attr "atype"    "mem")])
5158
5159
5160 ;;
5161 ;;- Negate instructions.
5162 ;;
5163
5164 ;
5165 ; negdi2 instruction pattern(s).
5166 ;
5167
5168 (define_expand "negdi2"
5169   [(parallel
5170     [(set (match_operand:DI 0 "register_operand" "=d")
5171           (neg:DI (match_operand:DI 1 "register_operand" "d")))
5172      (clobber (reg:CC 33))])]
5173   ""
5174   "")
5175
5176 (define_insn "*negdi2_64"
5177   [(set (match_operand:DI 0 "register_operand" "=d")
5178         (neg:DI (match_operand:DI 1 "register_operand" "d")))
5179    (clobber (reg:CC 33))]
5180   "TARGET_64BIT"
5181   "lcgr\\t%0,%1"
5182   [(set_attr "op_type"  "RR")])
5183
5184 (define_insn "*negdi2_31"
5185   [(set (match_operand:DI 0 "register_operand" "=d")
5186         (neg:DI (match_operand:DI 1 "register_operand" "d")))
5187    (clobber (reg:CC 33))]
5188   "!TARGET_64BIT"
5189   "*
5190 {
5191   rtx xop[1];
5192   xop[0] = gen_label_rtx ();
5193   output_asm_insn (\"lcr\\t%0,%1\", operands);
5194   output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5195   output_asm_insn (\"je\\t%l0\", xop);
5196   output_asm_insn (\"bctr\\t%0,0\", operands);
5197   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5198                              CODE_LABEL_NUMBER (xop[0]));
5199   return \"\";
5200 }"
5201   [(set_attr "op_type"  "NN")
5202    (set_attr "type"     "other")
5203    (set_attr "length"   "10")])
5204
5205 ;
5206 ; negsi2 instruction pattern(s).
5207 ;
5208
5209 (define_insn "negsi2"
5210   [(set (match_operand:SI 0 "register_operand" "=d")
5211         (neg:SI (match_operand:SI 1 "register_operand" "d")))
5212    (clobber (reg:CC 33))]
5213   ""
5214   "lcr\\t%0,%1"
5215   [(set_attr "op_type"  "RR")])
5216
5217 ;
5218 ; negdf2 instruction pattern(s).
5219 ;
5220
5221 (define_expand "negdf2"
5222   [(parallel
5223     [(set (match_operand:DF 0 "register_operand" "=f")
5224           (neg:DF (match_operand:DF 1 "register_operand" "f")))
5225      (clobber (reg:CC 33))])]
5226   "TARGET_HARD_FLOAT"
5227   "")
5228
5229 (define_insn "*negdf2"
5230   [(set (match_operand:DF 0 "register_operand" "=f")
5231         (neg:DF (match_operand:DF 1 "register_operand" "f")))
5232    (clobber (reg:CC 33))]
5233   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5234   "lcdbr\\t%0,%1"
5235   [(set_attr "op_type"  "RRE")])
5236
5237 (define_insn "*negdf2_ibm"
5238   [(set (match_operand:DF 0 "register_operand" "=f")
5239         (neg:DF (match_operand:DF 1 "register_operand" "f")))
5240    (clobber (reg:CC 33))]
5241   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5242   "lcdr\\t%0,%1"
5243   [(set_attr "op_type"  "RR")])
5244
5245 ;
5246 ; negsf2 instruction pattern(s).
5247 ;
5248
5249 (define_expand "negsf2"
5250   [(parallel
5251     [(set (match_operand:SF 0 "register_operand" "=f")
5252           (neg:SF (match_operand:SF 1 "register_operand" "f")))
5253      (clobber (reg:CC 33))])]
5254   "TARGET_HARD_FLOAT"
5255   "")
5256
5257 (define_insn "*negsf2"
5258   [(set (match_operand:SF 0 "register_operand" "=f")
5259         (neg:SF (match_operand:SF 1 "register_operand" "f")))
5260    (clobber (reg:CC 33))]
5261   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5262   "lcebr\\t%0,%1"
5263   [(set_attr "op_type"  "RRE")])
5264
5265 (define_insn "*negsf2"
5266   [(set (match_operand:SF 0 "register_operand" "=f")
5267         (neg:SF (match_operand:SF 1 "register_operand" "f")))
5268    (clobber (reg:CC 33))]
5269   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5270   "lcer\\t%0,%1"
5271   [(set_attr "op_type"  "RR")])
5272
5273
5274 ;;
5275 ;;- Absolute value instructions.
5276 ;;
5277
5278 ;
5279 ; absdi2 instruction pattern(s).
5280 ;
5281
5282 (define_insn "absdi2"
5283   [(set (match_operand:DI 0 "register_operand" "=d")
5284         (abs:DI (match_operand:DI 1 "register_operand" "d")))
5285    (clobber (reg:CC 33))]
5286   "TARGET_64BIT"
5287   "lpgr\\t%0,%1"
5288   [(set_attr "op_type"  "RRE")])
5289
5290 ;
5291 ; abssi2 instruction pattern(s).
5292 ;
5293
5294 (define_insn "abssi2"
5295   [(set (match_operand:SI 0 "register_operand" "=d")
5296         (abs:SI (match_operand:SI 1 "register_operand" "d")))
5297    (clobber (reg:CC 33))]
5298   ""
5299   "lpr\\t%0,%1"
5300   [(set_attr "op_type"  "RR")])
5301
5302 ;
5303 ; absdf2 instruction pattern(s).
5304 ;
5305
5306 (define_expand "absdf2"
5307   [(parallel
5308     [(set (match_operand:DF 0 "register_operand" "=f")
5309           (abs:DF (match_operand:DF 1 "register_operand" "f")))
5310      (clobber (reg:CC 33))])]
5311   "TARGET_HARD_FLOAT"
5312   "")
5313
5314 (define_insn "*absdf2"
5315   [(set (match_operand:DF 0 "register_operand" "=f")
5316         (abs:DF (match_operand:DF 1 "register_operand" "f")))
5317    (clobber (reg:CC 33))]
5318   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5319   "lpdbr\\t%0,%1"
5320   [(set_attr "op_type"  "RRE")])
5321
5322 (define_insn "*absdf2_ibm"
5323   [(set (match_operand:DF 0 "register_operand" "=f")
5324         (abs:DF (match_operand:DF 1 "register_operand" "f")))
5325    (clobber (reg:CC 33))]
5326   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5327   "lpdr\\t%0,%1"
5328   [(set_attr "op_type"  "RR")])
5329
5330 ;
5331 ; abssf2 instruction pattern(s).
5332 ;
5333
5334 (define_expand "abssf2"
5335   [(parallel
5336     [(set (match_operand:SF 0 "register_operand" "=f")
5337           (abs:SF (match_operand:SF 1 "register_operand" "f")))
5338      (clobber (reg:CC 33))])]
5339   "TARGET_HARD_FLOAT"
5340   "")
5341
5342 (define_insn "*abssf2"
5343   [(set (match_operand:SF 0 "register_operand" "=f")
5344         (abs:SF (match_operand:SF 1 "register_operand" "f")))
5345    (clobber (reg:CC 33))]
5346   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5347   "lpebr\\t%0,%1"
5348   [(set_attr "op_type"  "RRE")])
5349
5350 (define_insn "*abssf2_ibm"
5351   [(set (match_operand:SF 0 "register_operand" "=f")
5352         (abs:SF (match_operand:SF 1 "register_operand" "f")))
5353    (clobber (reg:CC 33))]
5354   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5355   "lper\\t%0,%1"
5356   [(set_attr "op_type"  "RR")])
5357
5358 ;;
5359 ;;- Square root instructions.
5360 ;;
5361
5362 ;
5363 ; sqrtdf2 instruction pattern(s).
5364 ;
5365
5366 (define_insn "sqrtdf2"
5367   [(set (match_operand:DF 0 "register_operand" "=f,f")
5368         (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5369   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5370   "@
5371    sqdbr\\t%0,%1
5372    sqdb\\t%0,%1"
5373   [(set_attr "op_type"  "RRE,RSE")])
5374
5375 ;
5376 ; sqrtsf2 instruction pattern(s).
5377 ;
5378
5379 (define_insn "sqrtsf2"
5380   [(set (match_operand:SF 0 "register_operand" "=f,f")
5381         (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5382   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5383   "@
5384    sqebr\\t%0,%1
5385    sqeb\\t%0,%1"
5386   [(set_attr "op_type"  "RRE,RSE")])
5387
5388 ;;
5389 ;;- One complement instructions.
5390 ;;
5391
5392 ;
5393 ; one_cmpldi2 instruction pattern(s).
5394 ;
5395
5396 (define_expand "one_cmpldi2"
5397   [(parallel
5398     [(set (match_operand:DI 0 "register_operand" "")
5399           (xor:DI (match_operand:DI 1 "register_operand" "")
5400                   (const_int -1)))
5401      (clobber (reg:CC 33))])]
5402   "TARGET_64BIT"
5403   "")
5404
5405 ;
5406 ; one_cmplsi2 instruction pattern(s).
5407 ;
5408
5409 (define_expand "one_cmplsi2"
5410   [(parallel
5411     [(set (match_operand:SI 0 "register_operand" "")
5412           (xor:SI (match_operand:SI 1 "register_operand" "")
5413                   (const_int -1)))
5414      (clobber (reg:CC 33))])]
5415   ""
5416   "")
5417
5418 ;
5419 ; one_cmplhi2 instruction pattern(s).
5420 ;
5421
5422 (define_expand "one_cmplhi2"
5423   [(parallel
5424     [(set (match_operand:HI 0 "register_operand" "")
5425           (xor:HI (match_operand:HI 1 "register_operand" "")
5426                   (const_int -1)))
5427      (clobber (reg:CC 33))])]
5428   ""
5429   "")
5430
5431 ;
5432 ; one_cmplqi2 instruction pattern(s).
5433 ;
5434
5435 (define_expand "one_cmplqi2"
5436   [(parallel
5437     [(set (match_operand:QI 0 "register_operand" "")
5438           (xor:QI (match_operand:QI 1 "register_operand" "")
5439                   (const_int -1)))
5440      (clobber (reg:CC 33))])]
5441   ""
5442   "")
5443
5444
5445 ;;
5446 ;;- Rotate instructions.
5447 ;;
5448
5449 ;
5450 ; rotldi3 instruction pattern(s).
5451 ;
5452
5453 (define_insn "rotldi3"
5454   [(set (match_operand:DI 0 "register_operand" "=d,d")
5455         (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5456                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5457   "TARGET_64BIT"
5458   "@
5459    rllg\\t%0,%1,%c2
5460    rllg\\t%0,%1,0(%2)"
5461   [(set_attr "op_type"  "RSE")])
5462
5463 ;
5464 ; rotlsi3 instruction pattern(s).
5465 ;
5466
5467 (define_insn "rotlsi3"
5468   [(set (match_operand:SI 0 "register_operand" "=d,d")
5469         (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5470                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5471   "TARGET_64BIT"
5472   "@
5473    rll\\t%0,%1,%c2
5474    rll\\t%0,%1,0(%2)"
5475   [(set_attr "op_type"  "RSE")])
5476
5477
5478 ;;
5479 ;;- Arithmetic shift instructions.
5480 ;;
5481
5482 ;
5483 ; ashldi3 instruction pattern(s).
5484 ;
5485
5486 (define_expand "ashldi3"
5487   [(set (match_operand:DI 0 "register_operand" "")
5488         (ashift:DI (match_operand:DI 1 "register_operand" "")
5489                    (match_operand:SI 2 "nonmemory_operand" "")))]
5490   ""
5491   "")
5492
5493 (define_insn "*ashldi3_31"
5494   [(set (match_operand:DI 0 "register_operand" "=d,d")
5495         (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5496                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5497   "!TARGET_64BIT"
5498   "@
5499    sldl\\t%0,%c2
5500    sldl\\t%0,0(%2)"
5501   [(set_attr "op_type"  "RS")])
5502
5503 (define_insn "*ashldi3_64"
5504   [(set (match_operand:DI 0 "register_operand" "=d,d")
5505         (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5506                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5507   "TARGET_64BIT"
5508   "@
5509    sllg\\t%0,%1,%2
5510    sllg\\t%0,%1,0(%2)"
5511   [(set_attr "op_type"  "RSE")])
5512
5513 ;
5514 ; ashrdi3 instruction pattern(s).
5515 ;
5516
5517 (define_expand "ashrdi3"
5518   [(parallel
5519     [(set (match_operand:DI 0 "register_operand" "")
5520           (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5521                        (match_operand:SI 2 "nonmemory_operand" "")))
5522      (clobber (reg:CC 33))])]
5523   ""
5524   "")
5525
5526 (define_insn "*ashrdi3_cc_31"
5527   [(set (reg 33)
5528         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5529                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5530                  (const_int 0)))
5531    (set (match_operand:DI 0 "register_operand" "=d,d")
5532         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5533   "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5534   "@
5535    srda\\t%0,%c2
5536    srda\\t%0,0(%2)"
5537   [(set_attr "op_type"  "RS")])
5538
5539 (define_insn "*ashrdi3_cconly_31"
5540   [(set (reg 33)
5541         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5542                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5543                  (const_int 0)))
5544    (clobber (match_scratch:DI 0 "=d,d"))]
5545   "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5546   "@
5547    srda\\t%0,%c2
5548    srda\\t%0,0(%2)"
5549   [(set_attr "op_type"  "RS")])
5550
5551 (define_insn "*ashrdi3_31"
5552   [(set (match_operand:DI 0 "register_operand" "=d,d")
5553         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5554                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5555    (clobber (reg:CC 33))]
5556   "!TARGET_64BIT"
5557   "@
5558    srda\\t%0,%c2
5559    srda\\t%0,0(%2)"
5560   [(set_attr "op_type"  "RS")])
5561
5562 (define_insn "*ashrdi3_cc_64"
5563   [(set (reg 33)
5564         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5565                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5566                  (const_int 0)))
5567    (set (match_operand:DI 0 "register_operand" "=d,d")
5568         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5569   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5570   "@
5571    srag\\t%0,%1,%c2
5572    srag\\t%0,%1,0(%2)"
5573   [(set_attr "op_type"  "RSE")])
5574
5575 (define_insn "*ashrdi3_cconly_64"
5576   [(set (reg 33)
5577         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5578                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5579                  (const_int 0)))
5580    (clobber (match_scratch:DI 0 "=d,d"))]
5581   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5582   "@
5583    srag\\t%0,%1,%c2
5584    srag\\t%0,%1,0(%2)"
5585   [(set_attr "op_type"  "RSE")])
5586
5587 (define_insn "*ashrdi3_64"
5588   [(set (match_operand:DI 0 "register_operand" "=d,d")
5589         (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5590                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5591    (clobber (reg:CC 33))]
5592   "TARGET_64BIT"
5593   "@
5594    srag\\t%0,%1,%c2
5595    srag\\t%0,%1,0(%2)"
5596   [(set_attr "op_type"  "RSE")])
5597
5598 ;
5599 ; ashlsi3 instruction pattern(s).
5600 ;
5601
5602 (define_insn "ashlsi3"
5603   [(set (match_operand:SI 0 "register_operand" "=d,d")
5604         (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5605                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5606   ""
5607   "@
5608    sll\\t%0,%c2
5609    sll\\t%0,0(%2)"
5610   [(set_attr "op_type"  "RS")])
5611
5612 ;
5613 ; ashrsi3 instruction pattern(s).
5614 ;
5615
5616 (define_insn "*ashrsi3_cc"
5617   [(set (reg 33)
5618         (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5619                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5620                  (const_int 0)))
5621    (set (match_operand:SI 0 "register_operand" "=d,d")
5622         (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5623   "s390_match_ccmode(insn, CCSmode)"
5624   "@
5625    sra\\t%0,%c2
5626    sra\\t%0,0(%2)"
5627   [(set_attr "op_type"  "RS")])
5628
5629 (define_insn "*ashrsi3_cconly"
5630   [(set (reg 33)
5631         (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5632                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5633                  (const_int 0)))
5634    (clobber (match_scratch:SI 0 "=d,d"))]
5635   "s390_match_ccmode(insn, CCSmode)"
5636   "@
5637    sra\\t%0,%c2
5638    sra\\t%0,0(%2)"
5639   [(set_attr "op_type"  "RS")])
5640
5641 (define_insn "ashrsi3"
5642   [(set (match_operand:SI 0 "register_operand" "=d,d")
5643         (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5644                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5645    (clobber (reg:CC 33))]
5646   ""
5647   "@
5648    sra\\t%0,%c2
5649    sra\\t%0,0(%2)"
5650   [(set_attr "op_type"  "RS")])
5651
5652
5653 ;;
5654 ;;- logical shift instructions.
5655 ;;
5656
5657 ;
5658 ; lshrdi3 instruction pattern(s).
5659 ;
5660
5661 (define_expand "lshrdi3"
5662   [(set (match_operand:DI 0 "register_operand" "")
5663         (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5664                      (match_operand:SI 2 "nonmemory_operand" "")))]
5665   ""
5666   "")
5667
5668 (define_insn "*lshrdi3_31"
5669   [(set (match_operand:DI 0 "register_operand" "=d,d")
5670         (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5671                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5672   "!TARGET_64BIT"
5673   "@
5674    srdl\\t%0,%c2
5675    srdl\\t%0,0(%2)"
5676    [(set_attr "op_type"  "RS,RS")])
5677
5678 (define_insn "*lshrdi3_64"
5679   [(set (match_operand:DI 0 "register_operand" "=d,d")
5680         (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5681                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5682   "TARGET_64BIT"
5683   "@
5684    srlg\\t%0,%1,%c2
5685    srlg\\t%0,%1,0(%2)"
5686   [(set_attr "op_type"  "RS,RS")])
5687
5688 ;
5689 ; lshrsi3 instruction pattern(s).
5690 ;
5691
5692 (define_insn "lshrsi3"
5693   [(set (match_operand:SI 0 "register_operand" "=d,d")
5694         (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5695                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5696   ""
5697   "@
5698    srl\\t%0,%c2
5699    srl\\t%0,0(%2)"
5700   [(set_attr "op_type"  "RS")])
5701
5702
5703 ;;
5704 ;; Branch instruction patterns.
5705 ;;
5706
5707 (define_expand "beq"
5708   [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5709    (set (pc)
5710         (if_then_else (eq (reg:CCZ 33) (const_int 0))
5711                       (label_ref (match_operand 0 "" ""))
5712                       (pc)))]
5713   ""
5714   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5715
5716 (define_expand "bne"
5717   [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5718    (set (pc)
5719         (if_then_else (ne (reg:CCZ 33) (const_int 0))
5720                       (label_ref (match_operand 0 "" ""))
5721                       (pc)))]
5722   ""
5723   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5724
5725 (define_expand "bgt"
5726   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5727    (set (pc)
5728         (if_then_else (gt (reg:CCS 33) (const_int 0))
5729                       (label_ref (match_operand 0 "" ""))
5730                       (pc)))]
5731   ""
5732   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5733
5734 (define_expand "bgtu"
5735   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5736    (set (pc)
5737         (if_then_else (gtu (reg:CCU 33) (const_int 0))
5738                       (label_ref (match_operand 0 "" ""))
5739                       (pc)))]
5740   ""
5741   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5742
5743 (define_expand "blt"
5744   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5745    (set (pc)
5746         (if_then_else (lt (reg:CCS 33) (const_int 0))
5747                       (label_ref (match_operand 0 "" ""))
5748                       (pc)))]
5749   ""
5750   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5751
5752 (define_expand "bltu"
5753   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5754    (set (pc)
5755         (if_then_else (ltu (reg:CCU 33) (const_int 0))
5756                       (label_ref (match_operand 0 "" ""))
5757                       (pc)))]
5758   ""
5759   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5760
5761 (define_expand "bge"
5762   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5763    (set (pc)
5764         (if_then_else (ge (reg:CCS 33) (const_int 0))
5765                       (label_ref (match_operand 0 "" ""))
5766                       (pc)))]
5767   ""
5768   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5769
5770 (define_expand "bgeu"
5771   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5772    (set (pc)
5773         (if_then_else (geu (reg:CCU 33) (const_int 0))
5774                       (label_ref (match_operand 0 "" ""))
5775                       (pc)))]
5776   ""
5777   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5778
5779 (define_expand "ble"
5780   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5781    (set (pc)
5782         (if_then_else (le (reg:CCS 33) (const_int 0))
5783                       (label_ref (match_operand 0 "" ""))
5784                       (pc)))]
5785   ""
5786   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5787
5788 (define_expand "bleu"
5789   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5790    (set (pc)
5791         (if_then_else (leu (reg:CCU 33) (const_int 0))
5792                       (label_ref (match_operand 0 "" ""))
5793                       (pc)))]
5794   ""
5795   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5796
5797 (define_expand "bunordered"
5798   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5799    (set (pc)
5800         (if_then_else (unordered (reg:CCS 33) (const_int 0))
5801                       (label_ref (match_operand 0 "" ""))
5802                       (pc)))]
5803   ""
5804   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5805
5806 (define_expand "bordered"
5807   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5808    (set (pc)
5809         (if_then_else (ordered (reg:CCS 33) (const_int 0))
5810                       (label_ref (match_operand 0 "" ""))
5811                       (pc)))]
5812   ""
5813   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5814
5815 (define_expand "buneq"
5816   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5817    (set (pc)
5818         (if_then_else (uneq (reg:CCS 33) (const_int 0))
5819                       (label_ref (match_operand 0 "" ""))
5820                       (pc)))]
5821   ""
5822   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5823
5824 (define_expand "bungt"
5825   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5826    (set (pc)
5827         (if_then_else (ungt (reg:CCS 33) (const_int 0))
5828                       (label_ref (match_operand 0 "" ""))
5829                       (pc)))]
5830   ""
5831   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5832
5833 (define_expand "bunlt"
5834   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5835    (set (pc)
5836         (if_then_else (unlt (reg:CCS 33) (const_int 0))
5837                       (label_ref (match_operand 0 "" ""))
5838                       (pc)))]
5839   ""
5840   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5841
5842 (define_expand "bunge"
5843   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5844    (set (pc)
5845         (if_then_else (unge (reg:CCS 33) (const_int 0))
5846                       (label_ref (match_operand 0 "" ""))
5847                       (pc)))]
5848   ""
5849   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5850
5851 (define_expand "bunle"
5852   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5853    (set (pc)
5854         (if_then_else (unle (reg:CCS 33) (const_int 0))
5855                       (label_ref (match_operand 0 "" ""))
5856                       (pc)))]
5857   ""
5858   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5859
5860 (define_expand "bltgt"
5861   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5862    (set (pc)
5863         (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5864                       (label_ref (match_operand 0 "" ""))
5865                       (pc)))]
5866   ""
5867   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5868
5869
5870 ;;
5871 ;;- Conditional jump instructions.
5872 ;;
5873
5874 (define_insn "cjump"
5875  [(set (pc)
5876        (if_then_else
5877          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5878          (label_ref (match_operand 0 "" ""))
5879          (pc)))]
5880   ""
5881   "*
5882 {
5883   if (get_attr_length (insn) == 4)
5884     return \"j%C1\\t%l0\";
5885   else if (TARGET_64BIT)
5886     return \"jg%C1\\t%l0\";
5887   else
5888     abort ();
5889 }"
5890   [(set_attr "op_type" "RI")
5891    (set (attr "length")
5892         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5893                 (const_int 4)
5894                (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5895                  (const_int 6)
5896                (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5897                  (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5898                                (const_int 12) (const_int 14))
5899                (eq (symbol_ref "flag_pic") (const_int 0))
5900                  (const_int 6)] (const_int 8)))])
5901
5902 (define_insn "*cjump_long"
5903  [(set (pc)
5904        (if_then_else
5905          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5906          (match_operand 0 "address_operand" "p")
5907          (pc)))]
5908   ""
5909   "*
5910 {
5911   if (get_attr_op_type (insn) == OP_TYPE_RR)
5912     return \"b%C1r\\t%0\";
5913   else
5914     return \"b%C1\\t%a0\";
5915 }"
5916   [(set (attr "op_type")
5917         (if_then_else (match_operand 0 "register_operand" "")
5918                       (const_string "RR") (const_string "RX")))
5919    (set_attr "atype" "mem")])
5920
5921
5922 ;;
5923 ;;- Negated conditional jump instructions.
5924 ;;
5925
5926 (define_insn "icjump"
5927  [(set (pc)
5928        (if_then_else
5929          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5930          (pc)
5931          (label_ref (match_operand 0 "" ""))))]
5932   ""
5933   "*
5934 {
5935   if (get_attr_length (insn) == 4)
5936     return \"j%D1\\t%l0\";
5937   else if (TARGET_64BIT)
5938     return \"jg%D1\\t%l0\";
5939   else
5940     abort ();
5941 }"
5942   [(set_attr "op_type" "RI")
5943    (set (attr "length")
5944         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5945                 (const_int 4)
5946                (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5947                  (const_int 6)
5948                (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5949                  (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5950                                (const_int 12) (const_int 14))
5951                (eq (symbol_ref "flag_pic") (const_int 0))
5952                  (const_int 6)] (const_int 8)))])
5953
5954 (define_insn "*icjump_long"
5955  [(set (pc)
5956        (if_then_else
5957          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5958          (pc)
5959          (match_operand 0 "address_operand" "p")))]
5960   ""
5961   "*
5962 {
5963   if (get_attr_op_type (insn) == OP_TYPE_RR)
5964     return \"b%D1r\\t%0\";
5965   else
5966     return \"b%D1\\t%a0\";
5967 }"
5968   [(set (attr "op_type")
5969         (if_then_else (match_operand 0 "register_operand" "")
5970                       (const_string "RR") (const_string "RX")))
5971    (set_attr "atype" "mem")])
5972
5973
5974 ;;
5975 ;;- Loop instructions.
5976 ;;
5977 ;;  This is all complicated by the fact that since this is a jump insn
5978 ;;  we must handle our own output reloads.
5979
5980 (define_expand "doloop_end"
5981   [(use (match_operand 0 "" ""))        ; loop pseudo
5982    (use (match_operand 1 "" ""))        ; iterations; zero if unknown
5983    (use (match_operand 2 "" ""))        ; max iterations
5984    (use (match_operand 3 "" ""))        ; loop level
5985    (use (match_operand 4 "" ""))]       ; label
5986   ""
5987   "
5988 {
5989   if (GET_MODE (operands[0]) == SImode)
5990     emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5991   else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5992     emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5993   else
5994     FAIL;
5995
5996   DONE;
5997 }")
5998
5999 (define_insn "doloop_si"
6000   [(set (pc)
6001         (if_then_else
6002           (ne (match_operand:SI 1 "register_operand" "d,d")
6003               (const_int 1))
6004           (label_ref (match_operand 0 "" ""))
6005           (pc)))
6006    (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6007         (plus:SI (match_dup 1) (const_int -1)))
6008    (clobber (match_scratch:SI 3 "=X,&d"))
6009    (clobber (reg:CC 33))]
6010   ""
6011   "*
6012 {
6013   if (which_alternative != 0)
6014     return \"#\";
6015   else if (get_attr_length (insn) == 4)
6016     return \"brct\\t%1,%l0\";
6017   else
6018     abort ();
6019 }"
6020   [(set_attr "op_type"  "RI")
6021    (set (attr "length")
6022         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6023                 (const_int 4)
6024                (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6025                  (const_int 10)
6026                (ne (symbol_ref "s390_pool_overflow") (const_int 0))
6027                  (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6028                                (const_int 12) (const_int 14))
6029                (eq (symbol_ref "flag_pic") (const_int 0))
6030                  (const_int 6)] (const_int 8)))])
6031
6032 (define_insn "*doloop_si_long"
6033   [(set (pc)
6034         (if_then_else
6035           (ne (match_operand:SI 1 "register_operand" "d,d")
6036               (const_int 1))
6037           (match_operand 0 "address_operand" "p,p")
6038           (pc)))
6039    (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6040         (plus:SI (match_dup 1) (const_int -1)))
6041    (clobber (match_scratch:SI 3 "=X,&d"))
6042    (clobber (reg:CC 33))]
6043   ""
6044   "*
6045 {
6046   if (get_attr_op_type (insn) == OP_TYPE_RR)
6047     return \"bctr\\t%0\";
6048   else
6049     return \"bct\\t%a0\";
6050 }"
6051   [(set (attr "op_type")
6052         (if_then_else (match_operand 0 "register_operand" "")
6053                       (const_string "RR") (const_string "RX")))
6054    (set_attr "atype" "mem")])
6055
6056 (define_split
6057   [(set (pc)
6058         (if_then_else (ne (match_operand:SI 1 "register_operand" "")
6059                           (const_int 1))
6060                       (match_operand 0 "" "")
6061                       (pc)))
6062    (set (match_operand:SI 2 "nonimmediate_operand" "")
6063         (plus:SI (match_dup 1) (const_int -1)))
6064    (clobber (match_scratch:SI 3 ""))
6065    (clobber (reg:CC 33))]
6066   "reload_completed
6067    && (! REG_P (operands[2])
6068        || ! rtx_equal_p (operands[1], operands[2]))"
6069   [(set (match_dup 3) (match_dup 1))
6070    (parallel [(set (reg:CCAN 33)
6071                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6072                                  (const_int 0)))
6073               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6074    (set (match_dup 2) (match_dup 3))
6075    (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6076                            (match_dup 0)
6077                            (pc)))]
6078   "")
6079
6080 (define_insn "doloop_di"
6081   [(set (pc)
6082         (if_then_else
6083           (ne (match_operand:DI 1 "register_operand" "d,d")
6084               (const_int 1))
6085           (label_ref (match_operand 0 "" ""))
6086           (pc)))
6087    (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
6088         (plus:DI (match_dup 1) (const_int -1)))
6089    (clobber (match_scratch:DI 3 "=X,&d"))
6090    (clobber (reg:CC 33))]
6091   "TARGET_64BIT"
6092   "*
6093 {
6094   if (which_alternative != 0)
6095     return \"#\";
6096   else if (get_attr_length (insn) == 4)
6097     return \"brctg\\t%1,%l0\";
6098   else
6099     abort ();
6100 }"
6101   [(set_attr "op_type"  "RI")
6102    (set (attr "length")
6103         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6104                       (const_int 4) (const_int 12)))])
6105
6106 (define_insn "*doloop_di_long"
6107   [(set (pc)
6108         (if_then_else
6109           (ne (match_operand:DI 1 "register_operand" "d,d")
6110               (const_int 1))
6111           (match_operand 0 "address_operand" "p,p")
6112           (pc)))
6113    (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
6114         (plus:DI (match_dup 1) (const_int -1)))
6115    (clobber (match_scratch:DI 3 "=X,&d"))
6116    (clobber (reg:CC 33))]
6117   ""
6118   "*
6119 {
6120   if (get_attr_op_type (insn) == OP_TYPE_RRE)
6121     return \"bctgr\\t%0\";
6122   else
6123     return \"bctg\\t%a0\";
6124 }"
6125   [(set (attr "op_type")
6126         (if_then_else (match_operand 0 "register_operand" "")
6127                       (const_string "RRE") (const_string "RXE")))
6128    (set_attr "atype" "mem")])
6129
6130 (define_split
6131   [(set (pc)
6132         (if_then_else (ne (match_operand:DI 1 "register_operand" "")
6133                           (const_int 1))
6134                       (match_operand 0 "" "")
6135                       (pc)))
6136    (set (match_operand:DI 2 "nonimmediate_operand" "")
6137         (plus:DI (match_dup 1) (const_int -1)))
6138    (clobber (match_scratch:DI 3 ""))
6139    (clobber (reg:CC 33))]
6140   "reload_completed
6141    && (! REG_P (operands[2])
6142        || ! rtx_equal_p (operands[1], operands[2]))"
6143   [(set (match_dup 3) (match_dup 1))
6144    (parallel [(set (reg:CCAN 33)
6145                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6146                                  (const_int 0)))
6147               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6148    (set (match_dup 2) (match_dup 3))
6149    (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6150                            (match_dup 0)
6151                            (pc)))]
6152   "")
6153
6154 ;;
6155 ;;- Unconditional jump instructions.
6156 ;;
6157
6158 ;
6159 ; jump instruction pattern(s).
6160 ;
6161
6162 (define_insn "jump"
6163   [(set (pc) (label_ref (match_operand 0 "" "")))]
6164   ""
6165   "*
6166 {
6167   if (get_attr_length (insn) == 4)
6168     return \"j\\t%l0\";
6169   else if (TARGET_64BIT)
6170     return \"jg\\t%l0\";
6171   else
6172     abort ();
6173 }"
6174   [(set_attr "op_type" "RI")
6175    (set (attr "length")
6176         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6177                 (const_int 4)
6178                (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6179                  (const_int 6)
6180                (eq (symbol_ref "flag_pic") (const_int 0))
6181                  (const_int 6)] (const_int 8)))])
6182
6183 ;
6184 ; indirect-jump instruction pattern(s).
6185 ;
6186
6187 (define_insn "indirect_jump"
6188  [(set (pc) (match_operand 0 "address_operand" "p"))]
6189   ""
6190   "*
6191 {
6192   if (get_attr_op_type (insn) == OP_TYPE_RR)
6193     return \"br\\t%0\";
6194   else
6195     return \"b\\t%a0\";
6196 }"
6197   [(set (attr "op_type")
6198         (if_then_else (match_operand 0 "register_operand" "")
6199                       (const_string "RR") (const_string "RX")))
6200    (set_attr "atype" "mem")])
6201
6202 ;
6203 ; casesi instruction pattern(s).
6204 ;
6205
6206 (define_insn "casesi_jump"
6207  [(set (pc) (match_operand 0 "address_operand" "p"))
6208    (use (label_ref (match_operand 1 "" "")))]
6209   ""
6210   "*
6211 {
6212   if (get_attr_op_type (insn) == OP_TYPE_RR)
6213     return \"br\\t%0\";
6214   else
6215     return \"b\\t%a0\";
6216 }"
6217   [(set (attr "op_type")
6218         (if_then_else (match_operand 0 "register_operand" "")
6219                       (const_string "RR") (const_string "RX")))
6220    (set_attr "atype" "mem")])
6221
6222 (define_expand "casesi"
6223   [(match_operand:SI 0 "general_operand" "")
6224    (match_operand:SI 1 "general_operand" "")
6225    (match_operand:SI 2 "general_operand" "")
6226    (label_ref (match_operand 3 "" ""))
6227    (label_ref (match_operand 4 "" ""))]
6228   ""
6229   "
6230 {
6231    rtx index  = gen_reg_rtx (SImode);
6232    rtx base   = gen_reg_rtx (Pmode);
6233    rtx target = gen_reg_rtx (Pmode);
6234
6235    emit_move_insn (index, operands[0]);
6236    emit_insn (gen_subsi3 (index, index, operands[1]));
6237    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6238                             operands[4]);
6239
6240    if (Pmode != SImode)
6241      index = convert_to_mode (Pmode, index, 1);
6242    if (GET_CODE (index) != REG)
6243      index = copy_to_mode_reg (Pmode, index);
6244
6245    if (TARGET_64BIT)
6246        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6247    else
6248        emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6249
6250    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6251
6252    index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6253    emit_move_insn (target, index);
6254
6255    if (flag_pic)
6256      target = gen_rtx_PLUS (Pmode, base, target);
6257    emit_jump_insn (gen_casesi_jump (target, operands[3]));
6258
6259    DONE;
6260 }")
6261
6262
6263 ;;
6264 ;;- Jump to subroutine.
6265 ;;
6266 ;;
6267
6268 ;
6269 ; untyped call instruction pattern(s).
6270 ;
6271
6272 ;; Call subroutine returning any type.
6273 (define_expand "untyped_call"
6274   [(parallel [(call (match_operand 0 "" "")
6275                     (const_int 0))
6276               (match_operand 1 "" "")
6277               (match_operand 2 "" "")])]
6278   ""
6279   "
6280 {
6281   int i;
6282
6283   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6284
6285   for (i = 0; i < XVECLEN (operands[2], 0); i++)
6286     {
6287       rtx set = XVECEXP (operands[2], 0, i);
6288       emit_move_insn (SET_DEST (set), SET_SRC (set));
6289     }
6290
6291   /* The optimizer does not know that the call sets the function value
6292      registers we stored in the result block.  We avoid problems by
6293      claiming that all hard registers are used and clobbered at this
6294      point.  */
6295   emit_insn (gen_blockage ());
6296
6297   DONE;
6298 }")
6299
6300 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6301 ;; all of memory.  This blocks insns from being moved across this point.
6302
6303 (define_insn "blockage"
6304   [(unspec_volatile [(const_int 0)] 0)]
6305   ""
6306   ""
6307   [(set_attr "type"    "none")])
6308
6309
6310
6311 ;
6312 ; call instruction pattern(s).
6313 ;
6314
6315 (define_expand "call"
6316   [(call (match_operand 0 "" "")
6317          (match_operand 1 "" ""))
6318    (use (match_operand 2 "" ""))]
6319   ""
6320   "
6321 {
6322   int plt_call = 0;
6323   rtx insn;
6324
6325   /* Direct function calls need special treatment.  */
6326   if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6327     {
6328       rtx sym = XEXP (operands[0], 0);
6329
6330       /* When calling a global routine in PIC mode, we must
6331          replace the symbol itself with the PLT stub.  */
6332       if (flag_pic && !SYMBOL_REF_FLAG (sym))
6333         {
6334           sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6335           sym = gen_rtx_CONST (Pmode, sym);
6336
6337           plt_call = 1;
6338         }
6339
6340       /* Unless we can use the bras(l) insn, force the
6341          routine address into a register.  */
6342       if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6343         {
6344           rtx target = gen_reg_rtx (Pmode);
6345           emit_move_insn (target, sym);
6346           sym = target;
6347         }
6348
6349       operands[0] = gen_rtx_MEM (QImode, sym);
6350     }
6351
6352   /* Emit insn.  */
6353   insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6354                                        gen_rtx_REG (Pmode, RETURN_REGNUM)));
6355
6356   /* In 31-bit, we must load the GOT register even if the
6357      compiler doesn't know about it, because the PLT glue
6358      code uses it.  In 64-bit, this is not necessary.  */
6359   if (plt_call && !TARGET_64BIT)
6360     use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6361
6362   DONE;
6363 }")
6364
6365 (define_expand "call_exp"
6366   [(parallel [(call (match_operand 0 "" "")
6367                     (match_operand 1 "" ""))
6368               (clobber (match_operand 2 "" ""))])]
6369   ""
6370   "")
6371
6372 (define_insn "brasl"
6373   [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6374          (match_operand:SI 1 "const_int_operand" "n"))
6375    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6376   "TARGET_64BIT"
6377   "brasl\\t%2,%0"
6378   [(set_attr "op_type" "RIL")
6379    (set_attr "type"    "jsr")])
6380
6381 (define_insn "bras"
6382   [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6383          (match_operand:SI 1 "const_int_operand" "n"))
6384    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6385   "TARGET_SMALL_EXEC"
6386   "bras\\t%2,%0"
6387   [(set_attr "op_type" "RI")
6388    (set_attr "type"    "jsr")])
6389
6390 (define_insn "basr_64"
6391   [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6392          (match_operand:SI 1 "const_int_operand" "n"))
6393    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6394   "TARGET_64BIT"
6395   "basr\\t%2,%0"
6396   [(set_attr "op_type" "RR")
6397    (set_attr "type"    "jsr")
6398    (set_attr "atype"   "mem")])
6399
6400 (define_insn "basr_31"
6401   [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6402          (match_operand:SI 1 "const_int_operand" "n"))
6403    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6404   "!TARGET_64BIT"
6405   "basr\\t%2,%0"
6406   [(set_attr "op_type" "RR")
6407    (set_attr "type"    "jsr")
6408    (set_attr "atype"    "mem")])
6409
6410 (define_insn "bas_64"
6411   [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6412          (match_operand:SI 1 "const_int_operand" "n"))
6413    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6414   "TARGET_64BIT"
6415   "bas\\t%2,%a0"
6416   [(set_attr "op_type" "RX")
6417    (set_attr "type"    "jsr")
6418    (set_attr "atype"   "mem")])
6419
6420 (define_insn "bas_31"
6421   [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6422          (match_operand:SI 1 "const_int_operand" "n"))
6423    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6424   "!TARGET_64BIT"
6425   "bas\\t%2,%a0"
6426   [(set_attr "op_type" "RX")
6427    (set_attr "type"    "jsr")
6428    (set_attr "atype"   "mem")])
6429
6430
6431 ;
6432 ; call_value instruction pattern(s).
6433 ;
6434
6435 (define_expand "call_value"
6436   [(set (match_operand 0 "" "")
6437         (call (match_operand 1 "" "")
6438               (match_operand 2 "" "")))
6439    (use (match_operand 3 "" ""))]
6440   ""
6441   "
6442 {
6443   int plt_call = 0;
6444   rtx insn;
6445
6446   /* Direct function calls need special treatment.  */
6447   if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6448     {
6449       rtx sym = XEXP (operands[1], 0);
6450
6451       /* When calling a global routine in PIC mode, we must
6452          replace the symbol itself with the PLT stub.  */
6453       if (flag_pic && !SYMBOL_REF_FLAG (sym))
6454         {
6455           sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6456           sym = gen_rtx_CONST (Pmode, sym);
6457
6458           plt_call = 1;
6459         }
6460
6461       /* Unless we can use the bras(l) insn, force the
6462          routine address into a register.  */
6463       if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6464         {
6465           rtx target = gen_reg_rtx (Pmode);
6466           emit_move_insn (target, sym);
6467           sym = target;
6468         }
6469
6470       operands[1] = gen_rtx_MEM (QImode, sym);
6471     }
6472
6473   /* Emit insn.  */
6474   insn = emit_call_insn (
6475             gen_call_value_exp (operands[0], operands[1], operands[2],
6476                                 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6477
6478   /* In 31-bit, we must load the GOT register even if the
6479      compiler doesn't know about it, because the PLT glue
6480      code uses it.  In 64-bit, this is not necessary.  */
6481   if (plt_call && !TARGET_64BIT)
6482     use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6483
6484   DONE;
6485 }")
6486
6487 (define_expand "call_value_exp"
6488   [(parallel [(set (match_operand 0 "" "")
6489                    (call (match_operand 1 "" "")
6490                          (match_operand 2 "" "")))
6491               (clobber (match_operand 3 "" ""))])]
6492   ""
6493   "")
6494
6495 (define_insn "brasl_r"
6496   [(set (match_operand 0 "register_operand" "=df")
6497         (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6498               (match_operand:SI 2 "const_int_operand" "n")))
6499    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6500   "TARGET_64BIT"
6501   "brasl\\t%3,%1"
6502   [(set_attr "op_type" "RIL")
6503    (set_attr "type"    "jsr")])
6504
6505 (define_insn "bras_r"
6506   [(set (match_operand 0 "register_operand" "=df")
6507         (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6508               (match_operand:SI 2 "const_int_operand" "n")))
6509    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6510   "TARGET_SMALL_EXEC"
6511   "bras\\t%3,%1"
6512   [(set_attr "op_type" "RI")
6513    (set_attr "type"    "jsr")])
6514
6515 (define_insn "basr_r_64"
6516   [(set (match_operand 0 "register_operand" "=df")
6517         (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6518               (match_operand:SI 2 "const_int_operand" "n")))
6519    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6520   "TARGET_64BIT"
6521   "basr\\t%3,%1"
6522   [(set_attr "op_type" "RR")
6523    (set_attr "type"    "jsr")])
6524
6525 (define_insn "basr_r_31"
6526   [(set (match_operand 0 "register_operand" "=df")
6527         (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6528               (match_operand:SI 2 "const_int_operand" "n")))
6529    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6530   "!TARGET_64BIT"
6531   "basr\\t%3,%1"
6532   [(set_attr "op_type" "RR")
6533    (set_attr "type"    "jsr")
6534    (set_attr "atype"   "mem")])
6535
6536 (define_insn "bas_r_64"
6537   [(set (match_operand 0 "register_operand" "=df")
6538         (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6539               (match_operand:SI 2 "const_int_operand" "n")))
6540    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6541   "TARGET_64BIT"
6542   "bas\\t%3,%a1"
6543   [(set_attr "op_type" "RX")
6544    (set_attr "type"    "jsr")
6545    (set_attr "atype"   "mem")])
6546
6547 (define_insn "bas_r_31"
6548   [(set (match_operand 0 "register_operand" "=df")
6549         (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6550               (match_operand:SI 2 "const_int_operand" "n")))
6551    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6552   "!TARGET_64BIT"
6553   "bas\\t%3,%a1"
6554    [(set_attr "op_type" "RX")
6555     (set_attr "type"    "jsr")
6556     (set_attr "atype"   "mem")])
6557
6558
6559 ;;
6560 ;;- Miscellaneous instructions.
6561 ;;
6562
6563 ;
6564 ; allocate stack instruction pattern(s).
6565 ;
6566
6567 (define_expand "allocate_stack"
6568   [(set (reg 15)
6569         (plus (reg 15) (match_operand 1 "general_operand" "")))
6570    (set (match_operand 0 "general_operand" "")
6571         (reg 15))]
6572  ""
6573  "
6574 {
6575     rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6576     rtx chain = gen_rtx (MEM, Pmode, stack);
6577     rtx temp = gen_reg_rtx (Pmode);
6578
6579     emit_move_insn (temp, chain);
6580
6581     if (TARGET_64BIT)
6582       emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6583     else
6584       emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6585
6586     emit_move_insn (chain, temp);
6587
6588     emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6589     DONE;
6590 }")
6591
6592
6593 ;
6594 ; setjmp/longjmp instruction pattern(s).
6595 ;
6596
6597 (define_expand "builtin_setjmp_setup"
6598   [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6599   ""
6600   "
6601 {
6602   rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6603   rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6604
6605   emit_move_insn (base, basereg);
6606   DONE;
6607 }")
6608
6609 (define_expand "builtin_setjmp_receiver"
6610   [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6611   "flag_pic"
6612   "
6613 {
6614   rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6615   rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6616   SYMBOL_REF_FLAG (got) = 1;
6617
6618   emit_move_insn (gotreg, got);
6619   emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6620   DONE;
6621 }")
6622
6623 (define_expand "builtin_longjmp"
6624   [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6625   ""
6626   "
6627 {
6628   /* The elements of the buffer are, in order:  */
6629   rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6630   rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6631   rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6632   rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6633   rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6634   rtx jmp = gen_rtx_REG (Pmode, 14);
6635
6636   emit_move_insn (jmp, lab);
6637   emit_move_insn (basereg, base);
6638   emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6639   emit_move_insn (hard_frame_pointer_rtx, fp);
6640
6641   emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6642   emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6643   emit_insn (gen_rtx_USE (VOIDmode, basereg));
6644   emit_indirect_jump (jmp);
6645   DONE;
6646 }")
6647
6648
6649 ;; These patterns say how to save and restore the stack pointer.  We need not
6650 ;; save the stack pointer at function level since we are careful to
6651 ;; preserve the backchain.  At block level, we have to restore the backchain
6652 ;; when we restore the stack pointer.
6653 ;;
6654 ;; For nonlocal gotos, we must save both the stack pointer and its
6655 ;; backchain and restore both.  Note that in the nonlocal case, the
6656 ;; save area is a memory location.
6657
6658 (define_expand "save_stack_function"
6659   [(match_operand 0 "general_operand" "")
6660    (match_operand 1 "general_operand" "")]
6661   ""
6662   "DONE;")
6663
6664 (define_expand "restore_stack_function"
6665   [(match_operand 0 "general_operand" "")
6666    (match_operand 1 "general_operand" "")]
6667   ""
6668   "DONE;")
6669
6670 (define_expand "restore_stack_block"
6671   [(use (match_operand 0 "register_operand" ""))
6672    (set (match_dup 2) (match_dup 3))
6673    (set (match_dup 0) (match_operand 1 "register_operand" ""))
6674    (set (match_dup 3) (match_dup 2))]
6675   ""
6676   "
6677 {
6678   operands[2] = gen_reg_rtx (Pmode);
6679   operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6680 }")
6681
6682 (define_expand "save_stack_nonlocal"
6683   [(match_operand 0 "memory_operand" "")
6684    (match_operand 1 "register_operand" "")]
6685   ""
6686   "
6687 {
6688   rtx temp = gen_reg_rtx (Pmode);
6689
6690   /* Copy the backchain to the first word, sp to the second.  */
6691   emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6692   emit_move_insn (operand_subword (operands[0], 0, 0,
6693                  TARGET_64BIT ? TImode : DImode),
6694                  temp);
6695   emit_move_insn (operand_subword (operands[0], 1, 0,
6696                  TARGET_64BIT ? TImode : DImode),
6697                  operands[1]);
6698   DONE;
6699 }")
6700
6701 (define_expand "restore_stack_nonlocal"
6702   [(match_operand 0 "register_operand" "")
6703    (match_operand 1 "memory_operand" "")]
6704   ""
6705   "
6706 {
6707   rtx temp = gen_reg_rtx (Pmode);
6708
6709   /* Restore the backchain from the first word, sp from the second.  */
6710   emit_move_insn (temp,
6711                  operand_subword (operands[1], 0, 0,
6712                  TARGET_64BIT ? TImode : DImode));
6713   emit_move_insn (operands[0],
6714                  operand_subword (operands[1], 1, 0,
6715                  TARGET_64BIT ? TImode : DImode));
6716   emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6717   DONE;
6718 }")
6719
6720
6721 ;
6722 ; nop instruction pattern(s).
6723 ;
6724
6725 (define_insn "nop"
6726   [(const_int 0)]
6727   ""
6728   "lr\\t0,0"
6729   [(set_attr "op_type" "RR")])
6730
6731
6732 ;
6733 ; Special literal pool access instruction pattern(s).
6734 ;
6735
6736 (define_insn "consttable_qi"
6737   [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6738   ""
6739   "*
6740 {
6741   assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6742   return \"\";
6743 }"
6744   [(set_attr "op_type"  "NN")
6745    (set_attr "length"   "1")])
6746
6747 (define_insn "consttable_hi"
6748   [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6749   ""
6750   "*
6751 {
6752   assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6753   return \"\";
6754 }"
6755   [(set_attr "op_type"  "NN")
6756    (set_attr "length"   "2")])
6757
6758 (define_insn "consttable_si"
6759   [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6760   ""
6761   "*
6762 {
6763   if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6764     return \".long\\t%0\";
6765
6766   assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6767   return \"\";
6768 }"
6769   [(set_attr "op_type"  "NN")
6770    (set_attr "length"   "4")])
6771
6772 (define_insn "consttable_di"
6773   [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6774   ""
6775   "*
6776 {
6777   assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6778   return \"\";
6779 }"
6780   [(set_attr "op_type"  "NN")
6781    (set_attr "length"   "8")])
6782
6783 (define_insn "consttable_sf"
6784   [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6785   ""
6786   "*
6787 {
6788   REAL_VALUE_TYPE r;
6789
6790   if (GET_CODE (operands[0]) != CONST_DOUBLE)
6791     abort ();
6792
6793   REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6794   assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6795   return \"\";
6796 }"
6797   [(set_attr "op_type"  "NN")
6798    (set_attr "length"   "4")])
6799
6800 (define_insn "consttable_df"
6801   [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6802   ""
6803   "*
6804 {
6805   REAL_VALUE_TYPE r;
6806
6807   if (GET_CODE (operands[0]) != CONST_DOUBLE)
6808     abort ();
6809
6810   REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6811   assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6812   return \"\";
6813 }"
6814   [(set_attr "op_type"  "NN")
6815    (set_attr "length"   "8")])
6816
6817 (define_insn "pool_start_31"
6818   [(unspec_volatile [(const_int 0)] 206)]
6819   "!TARGET_64BIT"
6820   ".align\\t4"
6821   [(set_attr "op_type"  "NN")
6822    (set_attr "length"   "2")])
6823
6824 (define_insn "pool_end_31"
6825   [(unspec_volatile [(const_int 0)] 207)]
6826   "!TARGET_64BIT"
6827   ".align\\t2"
6828   [(set_attr "op_type"  "NN")
6829    (set_attr "length"   "2")])
6830
6831 (define_insn "pool_start_64"
6832   [(unspec_volatile [(const_int 0)] 206)]
6833   "TARGET_64BIT"
6834   ".section\\t.rodata\;.align\\t8"
6835   [(set_attr "op_type"  "NN")
6836    (set_attr "length"   "0")])
6837
6838 (define_insn "pool_end_64"
6839   [(unspec_volatile [(const_int 0)] 207)]
6840   "TARGET_64BIT"
6841   ".previous"
6842   [(set_attr "op_type"  "NN")
6843    (set_attr "length"   "0")])
6844
6845 (define_insn "reload_base"
6846   [(set (match_operand:SI 0 "register_operand" "=a")
6847         (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6848   "!TARGET_64BIT"
6849   "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6850   [(set_attr "op_type" "NN")
6851    (set_attr "type"    "la")
6852    (set_attr "length"  "6")])
6853
6854 (define_insn "reload_base2"
6855   [(set (match_operand:SI 0 "register_operand" "=a")
6856         (unspec:SI [(label_ref (match_operand 1 "" ""))] 211))]
6857   "!TARGET_64BIT"
6858   "la\\t%0,%1-.(%0)"
6859   [(set_attr "op_type" "NN")
6860    (set_attr "type"    "la")
6861    (set_attr "length"  "4")])
6862
6863
6864 ;;
6865 ;; Insns related to generating the function prologue and epilogue.
6866 ;;
6867
6868
6869 (define_expand "prologue"
6870   [(use (const_int 0))]
6871   ""
6872   "
6873 {
6874       s390_emit_prologue ();
6875       DONE;
6876 }")
6877
6878 (define_expand "epilogue"
6879   [(use (const_int 1))]
6880   ""
6881   "
6882 {
6883       s390_emit_epilogue ();
6884       DONE;
6885 }")
6886
6887
6888 (define_insn "*return_si"
6889   [(return)
6890    (use (match_operand:SI 0 "register_operand" "a"))]
6891   "!TARGET_64BIT"
6892   "br\\t%0"
6893   [(set_attr "op_type" "RR")
6894    (set_attr "type"    "jsr")
6895    (set_attr "atype"   "mem")])
6896
6897 (define_insn "*return_di"
6898   [(return)
6899    (use (match_operand:DI 0 "register_operand" "a"))]
6900   "TARGET_64BIT"
6901   "br\\t%0"
6902   [(set_attr "op_type" "RR")
6903    (set_attr "type"    "jsr")
6904    (set_attr "atype"   "mem")])
6905
6906
6907 (define_insn "lit"
6908   [(set (reg 13) (pc))
6909    (unspec_volatile [(const_int 0)] 200)]
6910   ""
6911   "*
6912 {
6913    s390_output_constant_pool (asm_out_file);
6914    return \"\";
6915 }"
6916   [(set_attr "op_type" "NN")
6917    (set_attr "type"    "integer")])
6918
6919
6920 ;;
6921 ;; Peephole optimization patterns.
6922 ;;
6923
6924 (define_peephole
6925   [(set (match_operand:SI 0 "memory_operand" "m")
6926         (match_operand:SI 1 "register_operand" "d"))
6927    (set (match_dup 1)
6928         (match_dup 0))]
6929  ""
6930  "st\\t%1,%0")
6931
6932 (define_peephole
6933   [(set (match_operand:SI 0 "memory_operand" "m")
6934         (match_operand:SI 1 "register_operand" "d"))
6935    (set (match_dup 0)
6936         (match_dup 1))]
6937  ""
6938  "st\\t%1,%0")
6939
6940 (define_peephole
6941   [(set (match_operand:SI 0 "register_operand" "")
6942         (match_operand:SI 1 "register_operand" ""))
6943    (parallel
6944     [(set (match_dup 0)
6945           (plus:SI (match_dup 0)
6946                    (match_operand:SI 2 "immediate_operand" "")))
6947      (clobber (reg:CC 33))])]
6948  "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6949    REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6950    REGNO (operands[0]) == BASE_REGISTER ||
6951    REGNO (operands[1]) == BASE_REGISTER) &&
6952   INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6953  "la\\t%0,%c2(%1)")
6954
6955 ;
6956 ; peepholes for fast char instructions
6957 ;
6958
6959 ;(define_peephole
6960 ;  [(set (match_operand:QI 0 "register_operand" "d")
6961 ;        (match_operand:QI 1 "s_operand" "Q"))
6962 ;  (set  (match_operand:SI 2 "register_operand" "0")
6963 ;        (zero_extend:SI (match_dup 0)))]
6964 ; "REGNO(operands[0]) == REGNO(operands[2])"
6965 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6966
6967 ;(define_peephole
6968 ;  [(set (match_operand:QI 0 "register_operand" "d")
6969 ;        (match_operand:QI 1 "s_operand" "Q"))
6970 ;   (set (match_operand:SI 2 "register_operand" "0")
6971 ;        (sign_extend:SI (match_dup 0)))]
6972 ; "REGNO(operands[0]) == REGNO(operands[2])"
6973 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6974
6975 (define_peephole
6976   [(set (match_operand:QI 0 "register_operand" "d")
6977         (match_operand:QI 1 "immediate_operand" "J"))
6978    (set (match_operand:SI 2 "register_operand" "0" )
6979         (sign_extend:SI (match_dup 0) ) )]
6980  "REGNO(operands[0]) == REGNO(operands[2])"
6981  "lhi\\t%0,%h1")
6982
6983 ;
6984 ; peepholes for fast short instructions
6985 ;
6986
6987 ;(define_peephole
6988 ;  [(set (match_operand:HI 0 "register_operand" "d")
6989 ;        (match_operand:HI 1 "s_operand" "Q"))
6990 ;   (set (match_operand:SI 2 "register_operand" "0" )
6991 ;        (zero_extend:SI (match_dup 0)))]
6992 ; "REGNO(operands[0]) == REGNO(operands[2])"
6993 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6994
6995 (define_peephole
6996   [(set (match_operand:HI 0 "register_operand" "d")
6997         (match_operand:HI 1 "memory_operand" "m"))
6998    (set (match_operand:SI 2 "register_operand" "0" )
6999         (sign_extend:SI (match_dup 0)))]
7000  "REGNO(operands[0]) == REGNO(operands[2])"
7001  "lh\\t%0,%1")
7002
7003 (define_peephole
7004   [(set (match_operand:HI 0 "register_operand" "d")
7005         (match_operand:HI 1 "immediate_operand" "K"))
7006    (set (match_operand:SI 2 "register_operand" "0" )
7007         (sign_extend:SI (match_dup 0) ) )]
7008  "REGNO(operands[0]) == REGNO(operands[2])"
7009  "lhi\\t%0,%h1")
7010
7011 ;
7012 ; peepholes for divide instructions
7013 ;
7014
7015 (define_peephole
7016   [(set (match_operand:DI 0 "register_operand" "d")
7017         (match_operand:DI 1 "memory_operand" "m"))
7018    (set (match_dup 0)
7019         (lshiftrt:DI (match_dup 0)
7020         (match_operand:SI 2 "immediate_operand" "J")))
7021    (set (match_dup 0)
7022         (div:SI (match_dup 0)
7023         (match_operand:SI 3 "nonimmediate_operand" "g")))
7024    (set (match_dup 1)
7025         (match_dup 0))]
7026   ""
7027   "*
7028 {
7029    output_asm_insn (\"l\\t%0,%1\", operands);
7030    output_asm_insn (\"srdl\\t%0,%b2\", operands);
7031
7032    if (REG_P (operands[3]))
7033      output_asm_insn (\"dr\\t%0,%3\", operands);
7034    else
7035      output_asm_insn (\"d\\t%0,%3\", operands);
7036
7037    return \"st\\t%N0,%N1\";
7038 }")
7039
7040 (define_peephole
7041   [(set (match_operand:DI 0 "register_operand" "d")
7042         (match_operand:DI 1 "memory_operand" "m"))
7043    (set (match_dup 0)
7044         (lshiftrt:DI (match_dup 0)
7045         (match_operand:SI 2 "immediate_operand" "J")))
7046    (set (match_dup 0)
7047         (mod:SI (match_dup 0)
7048         (match_operand:SI 3 "nonimmediate_operand" "g")))
7049    (set (match_dup 1)
7050         (match_dup 0))]
7051   ""
7052   "*
7053 {
7054    output_asm_insn (\"l\\t%0,%1\", operands);
7055    output_asm_insn (\"srdl\\t%0,%b2\", operands);
7056
7057    if (REG_P (operands[3]))
7058      output_asm_insn (\"dr\\t%0,%3\", operands);
7059    else
7060      output_asm_insn (\"d\\t%0,%3\", operands);
7061
7062    return \"st\\t%0,%1\";
7063 }")
7064