1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
48 ;; Define an insn type attribute. This is used in function unit delay
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
58 (define_attr "atype" "reg,mem"
61 ;; Generic pipeline function unit.
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
117 ;; Operand type. Used to default length attribute values
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
143 ;; Define attributes for `asm' insns.
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
159 ; CCZ1 -> CCA/CCU/CCS/CCT
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
167 ;;- Compare instructions.
170 (define_expand "cmpdi"
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
182 (define_expand "cmpsi"
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
194 ;(define_expand "cmphi"
196 ; (compare:CC (match_operand:HI 0 "register_operand" "")
197 ; (match_operand:HI 1 "general_operand" "")))]
201 ; s390_compare_op0 = operands[0];
202 ; s390_compare_op1 = operands[1];
206 ;(define_expand "cmpqi"
208 ; (compare:CC (match_operand:QI 0 "register_operand" "")
209 ; (match_operand:QI 1 "general_operand" "")))]
213 ; s390_compare_op0 = operands[0];
214 ; s390_compare_op1 = operands[1];
218 (define_expand "cmpdf"
220 (compare:CC (match_operand:DF 0 "register_operand" "")
221 (match_operand:DF 1 "general_operand" "")))]
225 s390_compare_op0 = operands[0];
226 s390_compare_op1 = operands[1];
230 (define_expand "cmpsf"
232 (compare:CC (match_operand:SF 0 "register_operand" "")
233 (match_operand:SF 1 "general_operand" "")))]
237 s390_compare_op0 = operands[0];
238 s390_compare_op1 = operands[1];
245 (define_insn "*cmpdi_tm2"
247 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
248 (match_operand:DI 1 "const_int_operand" "n")
249 (match_operand:DI 2 "const_int_operand" "n"))
251 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
252 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
253 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
254 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
255 == INTVAL (operands[2]) >> 4"
258 int part = INTVAL (operands[2]) >> 4;
259 int block = (1 << INTVAL (operands[1])) - 1;
260 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
262 operands[2] = GEN_INT (block << shift);
266 case 0: return \"tmhh\\t%0,%x2\";
267 case 1: return \"tmhl\\t%0,%x2\";
268 case 2: return \"tmlh\\t%0,%x2\";
269 case 3: return \"tmll\\t%0,%x2\";
273 [(set_attr "op_type" "RI")])
275 (define_insn "*cmpdi_tm_reg"
277 (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
278 (match_operand:DI 1 "immediate_operand" "n"))
280 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
281 && s390_single_hi (operands[1], DImode, 0) >= 0"
284 int part = s390_single_hi (operands[1], DImode, 0);
285 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
289 case 0: return \"tmhh\\t%0,%x1\";
290 case 1: return \"tmhl\\t%0,%x1\";
291 case 2: return \"tmlh\\t%0,%x1\";
292 case 3: return \"tmll\\t%0,%x1\";
296 [(set_attr "op_type" "RI")])
298 (define_insn "*cmpdi_tm_mem"
300 (compare (and:DI (match_operand:DI 0 "s_operand" "%Qo")
301 (match_operand:DI 1 "immediate_operand" "n"))
303 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
304 && s390_single_qi (operands[1], DImode, 0) >= 0"
307 int part = s390_single_qi (operands[1], DImode, 0);
308 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
310 operands[0] = gen_rtx_MEM (QImode,
311 plus_constant (XEXP (operands[0], 0), part));
312 return \"tm\\t%0,%b1\";
314 [(set_attr "op_type" "SI")
315 (set_attr "atype" "mem")])
319 (compare (match_operand:DI 0 "register_operand" "d")
320 (match_operand:DI 1 "const0_operand" "")))
321 (set (match_operand:DI 2 "register_operand" "=d")
323 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
325 [(set_attr "op_type" "RRE")])
327 (define_insn "*cmpdi_ccs_0_64"
329 (compare (match_operand:DI 0 "register_operand" "d")
330 (match_operand:DI 1 "const0_operand" "")))]
331 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
333 [(set_attr "op_type" "RRE")])
335 (define_insn "*cmpdi_ccs_0_31"
337 (compare (match_operand:DI 0 "register_operand" "d")
338 (match_operand:DI 1 "const0_operand" "")))]
339 "s390_match_ccmode(insn, CCSmode)"
341 [(set_attr "op_type" "RS")])
343 (define_insn "*cmpdi_ccs"
345 (compare (match_operand:DI 0 "register_operand" "d,d,d")
346 (match_operand:DI 1 "general_operand" "d,K,m")))]
347 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
352 [(set_attr "op_type" "RRE,RI,RXE")
353 (set_attr "atype" "reg,reg,mem")])
355 (define_insn "*cmpdi_ccu"
357 (compare (match_operand:DI 0 "register_operand" "d,d")
358 (match_operand:DI 1 "general_operand" "d,m")))]
359 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
363 [(set_attr "op_type" "RRE,RXE")
364 (set_attr "atype" "reg,mem")])
366 (define_insn "*cmpdi_ccu_mem"
368 (compare (match_operand:DI 0 "s_operand" "oQ")
369 (match_operand:DI 1 "s_imm_operand" "oQ")))]
370 "s390_match_ccmode(insn, CCUmode)"
371 "clc\\t%O0(8,%R0),%1"
372 [(set_attr "op_type" "SS")
373 (set_attr "atype" "mem")])
377 (define_insn "*cmpsi_tm2"
379 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
380 (match_operand:SI 1 "const_int_operand" "n")
381 (match_operand:SI 2 "const_int_operand" "n"))
383 "s390_match_ccmode(insn, CCTmode)
384 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
385 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
386 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
387 == INTVAL (operands[2]) >> 4"
390 int part = INTVAL (operands[2]) >> 4;
391 int block = (1 << INTVAL (operands[1])) - 1;
392 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
394 operands[2] = GEN_INT (block << shift);
398 case 0: return \"tmh\\t%0,%x2\";
399 case 1: return \"tml\\t%0,%x2\";
403 [(set_attr "op_type" "RI")])
405 (define_insn "*cmpsi_tm_reg"
407 (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
408 (match_operand:SI 1 "immediate_operand" "n"))
410 "s390_match_ccmode(insn, CCTmode)
411 && s390_single_hi (operands[1], SImode, 0) >= 0"
414 int part = s390_single_hi (operands[1], SImode, 0);
415 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
419 case 0: return \"tmh\\t%0,%x1\";
420 case 1: return \"tml\\t%0,%x1\";
424 [(set_attr "op_type" "RI")])
426 (define_insn "*cmpsi_tm_mem"
428 (compare (and:SI (match_operand:SI 0 "s_operand" "%Qo")
429 (match_operand:SI 1 "immediate_operand" "n"))
431 "s390_match_ccmode(insn, CCTmode)
432 && s390_single_qi (operands[1], SImode, 0) >= 0"
435 int part = s390_single_qi (operands[1], SImode, 0);
436 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
438 operands[0] = gen_rtx_MEM (QImode,
439 plus_constant (XEXP (operands[0], 0), part));
440 return \"tm\\t%0,%b1\";
442 [(set_attr "op_type" "SI")
443 (set_attr "atype" "mem")])
447 (compare (match_operand:SI 0 "register_operand" "d")
448 (match_operand:SI 1 "const0_operand" "")))
449 (set (match_operand:SI 2 "register_operand" "=d")
451 "s390_match_ccmode(insn, CCSmode)"
453 [(set_attr "op_type" "RR")])
455 (define_insn "*icm15"
457 (compare (match_operand:SI 0 "s_operand" "Qo")
458 (match_operand:SI 1 "const0_operand" "")))
459 (set (match_operand:SI 2 "register_operand" "=d")
461 "s390_match_ccmode(insn, CCSmode)"
463 [(set_attr "op_type" "RS")
464 (set_attr "atype" "mem")])
466 (define_insn "*icm15_cconly"
468 (compare (match_operand:SI 0 "s_operand" "Qo")
469 (match_operand:SI 1 "const0_operand" "")))
470 (clobber (match_scratch:SI 2 "=d"))]
471 "s390_match_ccmode(insn, CCSmode)"
473 [(set_attr "op_type" "RS")
474 (set_attr "atype" "mem")])
476 (define_insn "*cmpsi_ccs_0"
478 (compare (match_operand:SI 0 "register_operand" "d")
479 (match_operand:SI 1 "const0_operand" "")))]
480 "s390_match_ccmode(insn, CCSmode)"
482 [(set_attr "op_type" "RR")])
484 (define_insn "*cmpsidi_ccs"
486 (compare (match_operand:SI 0 "register_operand" "d")
487 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
488 "s390_match_ccmode(insn, CCSmode)"
490 [(set_attr "op_type" "RR")
491 (set_attr "atype" "mem")])
493 (define_insn "*cmpsi_ccs"
495 (compare (match_operand:SI 0 "register_operand" "d,d,d")
496 (match_operand:SI 1 "general_operand" "d,K,m")))]
497 "s390_match_ccmode(insn, CCSmode)"
502 [(set_attr "op_type" "RR,RI,RX")
503 (set_attr "atype" "reg,reg,mem")])
505 (define_insn "*cmpsi_ccu"
507 (compare (match_operand:SI 0 "register_operand" "d,d")
508 (match_operand:SI 1 "general_operand" "d,m")))]
509 "s390_match_ccmode(insn, CCUmode)"
513 [(set_attr "op_type" "RR,RX")
514 (set_attr "atype" "reg,mem")])
516 (define_insn "*cmpsi_ccu_mem"
518 (compare (match_operand:SI 0 "s_operand" "oQ")
519 (match_operand:SI 1 "s_imm_operand" "oQ")))]
520 "s390_match_ccmode(insn, CCUmode)"
521 "clc\\t%O0(4,%R0),%1"
522 [(set_attr "op_type" "SS")
523 (set_attr "atype" "mem")])
528 (define_insn "*cmphi_tm_sub"
530 (compare (and:SI (subreg:SI (match_operand:HI 0 "s_operand" "%Qo") 0)
531 (match_operand:SI 1 "immediate_operand" "n"))
533 "s390_match_ccmode(insn, CCTmode)
534 && s390_single_qi (operands[1], HImode, 0) >= 0"
537 int part = s390_single_qi (operands[1], HImode, 0);
538 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
540 operands[0] = gen_rtx_MEM (QImode,
541 plus_constant (XEXP (operands[0], 0), part));
542 return \"tm\\t%0,%b1\";
544 [(set_attr "op_type" "SI")
545 (set_attr "atype" "mem")])
549 (compare (match_operand:HI 0 "s_operand" "Qo")
550 (match_operand:HI 1 "const0_operand" "")))
551 (set (match_operand:HI 2 "register_operand" "=d")
553 "s390_match_ccmode(insn, CCSmode)"
555 [(set_attr "op_type" "RS")
556 (set_attr "atype" "mem")])
558 (define_insn "*cmphi_cct_0"
560 (compare (match_operand:HI 0 "register_operand" "d")
561 (match_operand:HI 1 "const0_operand" "")))]
562 "s390_match_ccmode(insn, CCTmode)"
564 [(set_attr "op_type" "RX")])
566 (define_insn "*cmphi_ccs_0"
568 (compare (match_operand:HI 0 "s_operand" "Qo")
569 (match_operand:HI 1 "const0_operand" "")))
570 (clobber (match_scratch:HI 2 "=d"))]
571 "s390_match_ccmode(insn, CCSmode)"
573 [(set_attr "op_type" "RS")
574 (set_attr "atype" "mem")])
576 (define_insn "*cmphi_ccu"
578 (compare (match_operand:HI 0 "register_operand" "d")
579 (match_operand:HI 1 "s_imm_operand" "Qo")))]
580 "s390_match_ccmode(insn, CCUmode)"
582 [(set_attr "op_type" "RS")
583 (set_attr "atype" "mem")])
585 (define_insn "*cmphi_ccu_mem"
587 (compare (match_operand:HI 0 "s_operand" "oQ")
588 (match_operand:HI 1 "s_imm_operand" "oQ")))]
589 "s390_match_ccmode(insn, CCUmode)"
590 "clc\\t%O0(2,%R0),%1"
591 [(set_attr "op_type" "SS")
592 (set_attr "atype" "mem")])
597 (define_insn "*cmpqi_tm2"
599 (compare (zero_extract:SI (match_operand:QI 0 "s_operand" "Qo")
600 (match_operand:SI 1 "const_int_operand" "n")
601 (match_operand:SI 2 "const_int_operand" "n"))
603 "s390_match_ccmode(insn, CCTmode)
604 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
605 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
608 int block = (1 << INTVAL (operands[1])) - 1;
609 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
611 operands[2] = GEN_INT (block << shift);
612 return \"tm\\t%0,%b2\";
614 [(set_attr "op_type" "SI")
615 (set_attr "atype" "mem")])
617 (define_insn "*cmpqi_tm"
619 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,Q")
620 (match_operand:QI 1 "immediate_operand" "n,n"))
622 "s390_match_ccmode(insn, CCTmode)"
626 [(set_attr "op_type" "RI,SI")
627 (set_attr "atype" "reg,mem")])
629 (define_insn "*cmpqi_tm_sub"
631 (compare (and:SI (subreg:SI (match_operand:QI 0 "s_operand" "%Qo") 0)
632 (match_operand:SI 1 "immediate_operand" "n"))
634 "s390_match_ccmode(insn, CCTmode)"
636 [(set_attr "op_type" "SI")
637 (set_attr "atype" "mem")])
641 (compare (match_operand:QI 0 "s_operand" "Qo")
642 (match_operand:QI 1 "const0_operand" "")))
643 (set (match_operand:QI 2 "register_operand" "=d")
645 "s390_match_ccmode(insn, CCSmode)"
647 [(set_attr "op_type" "RS")
648 (set_attr "atype" "mem")])
652 (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
653 (match_operand:QI 1 "immediate_operand" "")))
655 "s390_match_ccmode(insn, CCTmode) &&
656 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
658 [(set_attr "op_type" "RI")
659 (set_attr "atype" "mem")])
661 (define_insn "*cmpqi_cct_0"
663 (compare (match_operand:QI 0 "register_operand" "d")
664 (match_operand:QI 1 "const0_operand" "")))]
665 "s390_match_ccmode(insn, CCTmode)"
667 [(set_attr "op_type" "RI")])
669 (define_insn "*cmpqi_ccs_0"
671 (compare (match_operand:QI 0 "s_operand" "Qo")
672 (match_operand:QI 1 "const0_operand" "")))
673 (clobber (match_scratch:QI 2 "=d"))]
674 "s390_match_ccmode(insn, CCSmode)"
676 [(set_attr "op_type" "RS")
677 (set_attr "atype" "mem")])
679 (define_insn "*cmpqi_ccu_0"
681 (compare (match_operand:QI 0 "s_operand" "Qo")
682 (match_operand:QI 1 "const0_operand" "")))]
683 "s390_match_ccmode(insn, CCUmode)"
685 [(set_attr "op_type" "SI")
686 (set_attr "atype" "mem")])
688 (define_insn "*cmpqi_ccu"
690 (compare (match_operand:QI 0 "register_operand" "d")
691 (match_operand:QI 1 "s_imm_operand" "Qo")))]
692 "s390_match_ccmode(insn, CCUmode)"
694 [(set_attr "op_type" "RS")
695 (set_attr "atype" "mem")])
697 (define_insn "*cmpqi_ccu_immed"
699 (compare (match_operand:QI 0 "s_operand" "Qo")
700 (match_operand:QI 1 "const_int_operand" "n")))]
701 "s390_match_ccmode(insn, CCUmode) &&
702 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
704 [(set_attr "op_type" "SI")
705 (set_attr "atype" "mem")])
707 (define_insn "*cmpqi_ccu_mem"
709 (compare (match_operand:QI 0 "s_operand" "oQ")
710 (match_operand:QI 1 "s_imm_operand" "oQ")))]
711 "s390_match_ccmode(insn, CCUmode)"
712 "clc\\t%O0(1,%R0),%1"
713 [(set_attr "op_type" "SS")
714 (set_attr "atype" "mem")])
719 (define_insn "*cmpdf_ccs_0"
721 (compare (match_operand:DF 0 "register_operand" "f")
722 (match_operand:DF 1 "const0_operand" "")))]
723 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
725 [(set_attr "op_type" "RRE")])
727 (define_insn "*cmpdf_ccs_0_ibm"
729 (compare (match_operand:DF 0 "register_operand" "f")
730 (match_operand:DF 1 "const0_operand" "")))]
731 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
733 [(set_attr "op_type" "RR")])
735 (define_insn "*cmpdf_ccs"
737 (compare (match_operand:DF 0 "register_operand" "f,f")
738 (match_operand:DF 1 "general_operand" "f,m")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
743 [(set_attr "op_type" "RRE,RXE")
744 (set_attr "atype" "reg,mem")])
746 (define_insn "*cmpdf_ccs_ibm"
748 (compare (match_operand:DF 0 "register_operand" "f,f")
749 (match_operand:DF 1 "general_operand" "f,m")))]
750 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
754 [(set_attr "op_type" "RR,RX")
755 (set_attr "atype" "reg,mem")])
760 (define_insn "*cmpsf_ccs_0"
762 (compare (match_operand:SF 0 "register_operand" "f")
763 (match_operand:SF 1 "const0_operand" "")))]
764 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
766 [(set_attr "op_type" "RRE")])
768 (define_insn "*cmpsf_ccs_0_ibm"
770 (compare (match_operand:SF 0 "register_operand" "f")
771 (match_operand:SF 1 "const0_operand" "")))]
772 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
774 [(set_attr "op_type" "RR")])
776 (define_insn "*cmpsf_ccs"
778 (compare (match_operand:SF 0 "register_operand" "f,f")
779 (match_operand:SF 1 "general_operand" "f,m")))]
780 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
784 [(set_attr "op_type" "RRE,RXE")
785 (set_attr "atype" "reg,mem")])
787 (define_insn "*cmpsf_ccs"
789 (compare (match_operand:SF 0 "register_operand" "f,f")
790 (match_operand:SF 1 "general_operand" "f,m")))]
791 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
795 [(set_attr "op_type" "RR,RX")
796 (set_attr "atype" "reg,mem")])
800 ;;- Move instructions.
804 ; movti instruction pattern(s).
807 (define_insn "*movti_ss"
808 [(set (match_operand:TI 0 "s_operand" "=Qo")
809 (match_operand:TI 1 "s_imm_operand" "Qo"))]
811 "mvc\\t%O0(16,%R0),%1"
812 [(set_attr "op_type" "SS")
813 (set_attr "atype" "mem")])
816 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m")
817 (match_operand:TI 1 "general_operand" "Q,d,dKm,d"))]
824 [(set_attr "op_type" "RSE,RSE,NN,NN")
825 (set_attr "atype" "mem")])
828 [(set (match_operand:TI 0 "nonimmediate_operand" "")
829 (match_operand:TI 1 "general_operand" ""))]
830 "TARGET_64BIT && reload_completed
831 && !s_operand (operands[0], VOIDmode)
832 && !s_operand (operands[1], VOIDmode)
833 && (register_operand (operands[0], VOIDmode)
834 || register_operand (operands[1], VOIDmode))
835 && (!register_operand (operands[0], VOIDmode)
836 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
838 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
840 [(set (match_dup 2) (match_dup 4))
841 (set (match_dup 3) (match_dup 5))]
844 if (!register_operand (operands[0], VOIDmode)
845 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
848 operands[2] = operand_subword (operands[0], 0, 0, TImode);
849 operands[3] = operand_subword (operands[0], 1, 0, TImode);
850 operands[4] = operand_subword (operands[1], 0, 0, TImode);
851 operands[5] = operand_subword (operands[1], 1, 0, TImode);
855 operands[2] = operand_subword (operands[0], 1, 0, TImode);
856 operands[3] = operand_subword (operands[0], 0, 0, TImode);
857 operands[4] = operand_subword (operands[1], 1, 0, TImode);
858 operands[5] = operand_subword (operands[1], 0, 0, TImode);
863 [(set (match_operand:TI 0 "register_operand" "")
864 (match_operand:TI 1 "memory_operand" ""))]
865 "TARGET_64BIT && reload_completed
866 && !s_operand (operands[1], VOIDmode)"
867 [(set (match_dup 2) (match_dup 3))
868 (set (match_dup 0) (mem:TI (match_dup 2)))]
869 "operands[2] = operand_subword (operands[0], 1, 0, TImode);
870 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
873 ; movdi instruction pattern(s).
876 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
877 ;; move to get the address of the symbolic object from the GOT.
879 (define_expand "movdi"
880 [(set (match_operand:DI 0 "general_operand" "")
881 (match_operand:DI 1 "general_operand" ""))]
885 /* Handle PIC symbolic constants. */
886 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
887 emit_pic_move (operands, DImode);
889 /* During and after reload, we need to force constants
890 to the literal pool ourselves, if necessary. */
891 if ((reload_in_progress || reload_completed)
892 && CONSTANT_P (operands[1])
893 && (!legitimate_reload_constant_p (operands[1])
894 || fp_operand (operands[0], VOIDmode)))
895 operands[1] = force_const_mem (DImode, operands[1]);
898 (define_insn "*movdi_lhi"
899 [(set (match_operand:DI 0 "register_operand" "=d")
900 (match_operand:DI 1 "immediate_operand" "K"))]
902 && GET_CODE (operands[1]) == CONST_INT
903 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
904 && !fp_operand (operands[0], VOIDmode)"
906 [(set_attr "op_type" "RI")
907 (set_attr "atype" "reg")])
909 (define_insn "*movdi_lli"
910 [(set (match_operand:DI 0 "register_operand" "=d")
911 (match_operand:DI 1 "immediate_operand" "n"))]
912 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
913 && !fp_operand (operands[0], VOIDmode)"
916 int part = s390_single_hi (operands[1], DImode, 0);
917 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
921 case 0: return \"llihh\\t%0,%x1\";
922 case 1: return \"llihl\\t%0,%x1\";
923 case 2: return \"llilh\\t%0,%x1\";
924 case 3: return \"llill\\t%0,%x1\";
928 [(set_attr "op_type" "RI")
929 (set_attr "atype" "reg")])
931 (define_insn "*movdi_larl"
932 [(set (match_operand:DI 0 "register_operand" "=d")
933 (match_operand:DI 1 "larl_operand" "X"))]
935 && !fp_operand (operands[0], VOIDmode)"
937 [(set_attr "op_type" "RIL")
938 (set_attr "atype" "reg")
939 (set_attr "type" "la")])
941 (define_insn "*movdi_ss"
942 [(set (match_operand:DI 0 "s_operand" "=Qo")
943 (match_operand:DI 1 "s_imm_operand" "Qo"))]
945 "mvc\\t%O0(8,%R0),%1"
946 [(set_attr "op_type" "SS")
947 (set_attr "atype" "mem")])
949 (define_insn "*movdi_64"
950 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,f,f,m")
951 (match_operand:DI 1 "general_operand" "d,m,d,f,m,f"))]
960 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX")
961 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
963 (define_insn "*movdi_31"
964 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,f,f,m")
965 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,f,m,f"))]
975 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX")
976 (set_attr "atype" "mem,mem,*,*,reg,mem,mem")])
979 [(set (match_operand:DI 0 "nonimmediate_operand" "")
980 (match_operand:DI 1 "general_operand" ""))]
981 "!TARGET_64BIT && reload_completed
982 && !fp_operand (operands[0], VOIDmode)
983 && !fp_operand (operands[1], VOIDmode)
984 && !s_operand (operands[0], VOIDmode)
985 && !s_operand (operands[1], VOIDmode)
986 && (register_operand (operands[0], VOIDmode)
987 || register_operand (operands[1], VOIDmode))
988 && (!register_operand (operands[0], VOIDmode)
989 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
991 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
993 [(set (match_dup 2) (match_dup 4))
994 (set (match_dup 3) (match_dup 5))]
997 if (!register_operand (operands[0], VOIDmode)
998 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1001 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1002 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1003 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1004 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1008 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1009 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1010 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1011 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1016 [(set (match_operand:DI 0 "register_operand" "")
1017 (match_operand:DI 1 "memory_operand" ""))]
1018 "!TARGET_64BIT && reload_completed
1019 && !fp_operand (operands[0], VOIDmode)
1020 && !fp_operand (operands[1], VOIDmode)
1021 && !s_operand (operands[1], VOIDmode)"
1022 [(set (match_dup 2) (match_dup 3))
1023 (set (match_dup 0) (mem:DI (match_dup 2)))]
1024 "operands[2] = operand_subword (operands[0], 1, 0, DImode);
1025 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1028 ; movsi instruction pattern(s).
1031 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1032 ;; move to get the address of the symbolic object from the GOT.
1034 (define_expand "movsi"
1035 [(set (match_operand:SI 0 "general_operand" "")
1036 (match_operand:SI 1 "general_operand" ""))]
1040 /* Handle PIC symbolic constants. */
1041 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1042 emit_pic_move (operands, SImode);
1044 /* expr.c tries to load an effective address using
1045 force_reg. This fails because we don't have a
1046 generic load_address pattern. Convert the move
1047 to a proper arithmetic operation instead, unless
1048 it is guaranteed to be OK. */
1049 if (GET_CODE (operands[1]) == PLUS
1050 && !legitimate_la_operand_p (operands[1]))
1052 operands[1] = force_operand (operands[1], operands[0]);
1053 if (operands[1] == operands[0])
1057 /* During and after reload, we need to force constants
1058 to the literal pool ourselves, if necessary. */
1059 if ((reload_in_progress || reload_completed)
1060 && CONSTANT_P (operands[1])
1061 && (!legitimate_reload_constant_p (operands[1])
1062 || fp_operand (operands[0], VOIDmode)))
1063 operands[1] = force_const_mem (SImode, operands[1]);
1066 (define_insn "*movsi_lhi"
1067 [(set (match_operand:SI 0 "register_operand" "=d")
1068 (match_operand:SI 1 "immediate_operand" "K"))]
1069 "GET_CODE (operands[1]) == CONST_INT
1070 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1071 && !fp_operand (operands[0], VOIDmode)"
1073 [(set_attr "op_type" "RI")])
1075 (define_insn "*movsi_lli"
1076 [(set (match_operand:SI 0 "register_operand" "=d")
1077 (match_operand:SI 1 "immediate_operand" "n"))]
1078 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1079 && !fp_operand (operands[0], VOIDmode)"
1082 int part = s390_single_hi (operands[1], SImode, 0);
1083 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1087 case 0: return \"llilh\\t%0,%x1\";
1088 case 1: return \"llill\\t%0,%x1\";
1092 [(set_attr "op_type" "RI")])
1094 (define_insn "*movsi_ss"
1095 [(set (match_operand:SI 0 "s_operand" "=Qo")
1096 (match_operand:SI 1 "s_imm_operand" "Qo"))]
1098 "mvc\\t%O0(4,%R0),%1"
1099 [(set_attr "op_type" "SS")
1100 (set_attr "atype" "mem")])
1102 (define_insn "*movsi"
1103 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,f,f,m")
1104 (match_operand:SI 1 "general_operand" "d,m,d,f,m,f"))]
1113 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1114 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1118 ; movhi instruction pattern(s).
1121 (define_insn "movhi"
1122 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m")
1123 (match_operand:HI 1 "general_operand" "d,n,m,d"))]
1130 [(set_attr "op_type" "RR,RI,RX,RX")
1131 (set_attr "atype" "reg,reg,mem,mem")])
1135 ; movqi instruction pattern(s).
1138 (define_insn "movqi_64"
1139 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1140 (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1148 [(set_attr "op_type" "RR,RI,RXE,RX,SI")
1149 (set_attr "atype" "reg,reg,mem,mem,mem")])
1152 (define_insn "movqi"
1153 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1154 (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1162 [(set_attr "op_type" "RR,RI,RX,RX,SI")
1163 (set_attr "atype" "reg,reg,mem,mem,mem")])
1167 ; moveqstrictqi instruction pattern(s).
1170 (define_insn "*movstrictqi"
1171 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1172 (match_operand:QI 1 "memory_operand" "m"))]
1175 [(set_attr "op_type" "RX")
1176 (set_attr "atype" "mem")])
1179 ; movstricthi instruction pattern(s).
1182 (define_insn "*movstricthi"
1183 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1184 (match_operand:HI 1 "s_imm_operand" "Qo"))
1185 (clobber (reg:CC 33))]
1188 [(set_attr "op_type" "RS")
1189 (set_attr "atype" "mem")])
1193 ; movstrictsi instruction pattern(s).
1196 (define_insn "movestrictsi"
1197 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1198 (match_operand:SI 1 "general_operand" "d,m"))]
1203 [(set_attr "op_type" "RR,RS")
1204 (set_attr "atype" "reg,mem")])
1208 ; movdf instruction pattern(s).
1211 (define_expand "movdf"
1212 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1213 (match_operand:DF 1 "general_operand" ""))]
1217 /* During and after reload, we need to force constants
1218 to the literal pool ourselves, if necessary. */
1219 if ((reload_in_progress || reload_completed)
1220 && CONSTANT_P (operands[1]))
1221 operands[1] = force_const_mem (DFmode, operands[1]);
1224 (define_insn "*movdf_ss"
1225 [(set (match_operand:DF 0 "s_operand" "=Qo")
1226 (match_operand:DF 1 "s_imm_operand" "Qo"))]
1228 "mvc\\t%O0(8,%R0),%1"
1229 [(set_attr "op_type" "SS")
1230 (set_attr "atype" "mem")])
1232 (define_insn "*movdf_64"
1233 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1234 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d"))]
1243 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE")
1244 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1246 (define_insn "*movdf_31"
1247 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m")
1248 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d"))]
1258 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN")
1259 (set_attr "atype" "reg,mem,mem,mem,mem,*,*")])
1262 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1263 (match_operand:DF 1 "general_operand" ""))]
1264 "!TARGET_64BIT && reload_completed
1265 && !fp_operand (operands[0], VOIDmode)
1266 && !fp_operand (operands[1], VOIDmode)
1267 && !s_operand (operands[0], VOIDmode)
1268 && !s_operand (operands[1], VOIDmode)
1269 && (register_operand (operands[0], VOIDmode)
1270 || register_operand (operands[1], VOIDmode))
1271 && (!register_operand (operands[0], VOIDmode)
1272 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1274 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1276 [(set (match_dup 2) (match_dup 4))
1277 (set (match_dup 3) (match_dup 5))]
1280 if (!register_operand (operands[0], VOIDmode)
1281 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1284 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1285 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1286 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1287 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1291 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1292 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1293 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1294 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1299 [(set (match_operand:DF 0 "register_operand" "")
1300 (match_operand:DF 1 "memory_operand" ""))]
1301 "!TARGET_64BIT && reload_completed
1302 && !fp_operand (operands[0], VOIDmode)
1303 && !fp_operand (operands[1], VOIDmode)
1304 && !s_operand (operands[1], VOIDmode)"
1305 [(set (match_dup 2) (match_dup 3))
1306 (set (match_dup 0) (mem:DI (match_dup 2)))]
1307 "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1308 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1311 ; movsf instruction pattern(s).
1314 (define_expand "movsf"
1315 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1316 (match_operand:SF 1 "general_operand" ""))]
1320 /* During and after reload, we need to force constants
1321 to the literal pool ourselves, if necessary. */
1322 if ((reload_in_progress || reload_completed)
1323 && CONSTANT_P (operands[1]))
1324 operands[1] = force_const_mem (SFmode, operands[1]);
1327 (define_insn "*movsf_ss"
1328 [(set (match_operand:SF 0 "s_operand" "=Qo")
1329 (match_operand:SF 1 "s_imm_operand" "Qo"))]
1331 "mvc\\t%O0(4,%R0),%1"
1332 [(set_attr "op_type" "SS")
1333 (set_attr "atype" "mem")])
1335 (define_insn "*movsf"
1336 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1337 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d"))]
1346 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1347 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1350 ; load_multiple pattern(s).
1353 (define_expand "load_multiple"
1354 [(match_par_dup 3 [(set (match_operand 0 "" "")
1355 (match_operand 1 "" ""))
1356 (use (match_operand 2 "" ""))])]
1365 /* Support only loading a constant number of fixed-point registers from
1366 memory and only bother with this if more than two */
1367 if (GET_CODE (operands[2]) != CONST_INT
1368 || INTVAL (operands[2]) < 2
1369 || INTVAL (operands[2]) > 16
1370 || GET_CODE (operands[1]) != MEM
1371 || GET_CODE (operands[0]) != REG
1372 || REGNO (operands[0]) >= 16)
1375 count = INTVAL (operands[2]);
1376 regno = REGNO (operands[0]);
1378 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1381 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1383 from = XEXP (operands[1], 0);
1386 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1387 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1388 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1390 from = XEXP (XEXP (operands[1], 0), 0);
1391 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1396 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1401 from = force_reg (Pmode, XEXP (operands[1], 0));
1405 for (i = 0; i < count; i++)
1406 XVECEXP (operands[3], 0, i)
1407 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1408 change_address (operands[1], Pmode,
1409 plus_constant (from,
1410 off + i * UNITS_PER_WORD)));
1413 (define_insn "*load_multiple_di"
1414 [(match_parallel 0 "load_multiple_operation"
1415 [(set (match_operand:DI 1 "register_operand" "=r")
1416 (match_operand:DI 2 "s_operand" "oQ"))])]
1420 int words = XVECLEN (operands[0], 0);
1422 if (XVECLEN (operands[0], 0) == 1)
1423 return \"lg\\t%1,0(%2)\";
1425 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1426 return \"lmg\\t%1,%0,%2\";
1428 [(set_attr "op_type" "RXE")
1429 (set_attr "atype" "mem")
1430 (set_attr "type" "lm")])
1432 (define_insn "*load_multiple_si"
1433 [(match_parallel 0 "load_multiple_operation"
1434 [(set (match_operand:SI 1 "register_operand" "=r")
1435 (match_operand:SI 2 "s_operand" "oQ"))])]
1439 int words = XVECLEN (operands[0], 0);
1441 if (XVECLEN (operands[0], 0) == 1)
1442 return \"l\\t%1,0(%2)\";
1444 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1445 return \"lm\\t%1,%0,%2\";
1447 [(set_attr "op_type" "RXE")
1448 (set_attr "atype" "mem")
1449 (set_attr "type" "lm")])
1452 ; store multiple pattern(s).
1455 (define_expand "store_multiple"
1456 [(match_par_dup 3 [(set (match_operand 0 "" "")
1457 (match_operand 1 "" ""))
1458 (use (match_operand 2 "" ""))])]
1467 /* Support only storing a constant number of fixed-point registers to
1468 memory and only bother with this if more than two. */
1469 if (GET_CODE (operands[2]) != CONST_INT
1470 || INTVAL (operands[2]) < 2
1471 || INTVAL (operands[2]) > 16
1472 || GET_CODE (operands[0]) != MEM
1473 || GET_CODE (operands[1]) != REG
1474 || REGNO (operands[1]) >= 16)
1477 count = INTVAL (operands[2]);
1478 regno = REGNO (operands[1]);
1480 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1484 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1486 to = XEXP (operands[0], 0);
1489 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1490 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1491 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1493 to = XEXP (XEXP (operands[0], 0), 0);
1494 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1499 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1504 to = force_reg (Pmode, XEXP (operands[0], 0));
1508 for (i = 0; i < count; i++)
1509 XVECEXP (operands[3], 0, i)
1510 = gen_rtx_SET (VOIDmode,
1511 change_address (operands[0], Pmode,
1513 off + i * UNITS_PER_WORD)),
1514 gen_rtx_REG (Pmode, regno + i));
1517 (define_insn "*store_multiple_di"
1518 [(match_parallel 0 "store_multiple_operation"
1519 [(set (match_operand:DI 1 "s_operand" "=oQ")
1520 (match_operand:DI 2 "register_operand" "r"))])]
1524 int words = XVECLEN (operands[0], 0);
1526 if (XVECLEN (operands[0], 0) == 1)
1527 return \"stg\\t%1,0(%2)\";
1529 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1530 return \"stmg\\t%2,%0,%1\";
1532 [(set_attr "op_type" "RXE")
1533 (set_attr "atype" "mem")
1534 (set_attr "type" "stm")])
1537 (define_insn "*store_multiple_si"
1538 [(match_parallel 0 "store_multiple_operation"
1539 [(set (match_operand:SI 1 "s_operand" "=oQ")
1540 (match_operand:SI 2 "register_operand" "r"))])]
1544 int words = XVECLEN (operands[0], 0);
1546 if (XVECLEN (operands[0], 0) == 1)
1547 return \"st\\t%1,0(%2)\";
1549 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1550 return \"stm\\t%2,%0,%1\";
1552 [(set_attr "op_type" "RXE")
1553 (set_attr "atype" "mem")
1554 (set_attr "type" "stm")])
1557 ;; String instructions.
1561 ; movstrdi instruction pattern(s).
1564 (define_expand "movstrdi"
1565 [(set (match_operand:BLK 0 "general_operand" "")
1566 (match_operand:BLK 1 "general_operand" ""))
1567 (use (match_operand:DI 2 "general_operand" ""))
1568 (match_operand 3 "" "")]
1574 addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1575 addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1577 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1579 operands[0] = change_address (operands[0], VOIDmode, addr0);
1580 operands[1] = change_address (operands[1], VOIDmode, addr1);
1581 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1583 emit_insn (gen_movstrdi_short (operands[0], operands[1], operands[2]));
1590 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1591 rtx reg0 = gen_reg_rtx (TImode);
1592 rtx reg1 = gen_reg_rtx (TImode);
1593 rtx len = operands[2];
1595 if (! CONSTANT_P (len))
1596 len = force_reg (DImode, len);
1598 /* Load up the address+length pairs. */
1600 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1601 emit_move_insn (gen_lowpart (DImode, reg0), len);
1603 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1604 emit_move_insn (gen_lowpart (DImode, reg1), len);
1607 emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
1612 rtx label1 = gen_label_rtx ();
1613 rtx label2 = gen_label_rtx ();
1614 rtx reg0, reg1, len, blocks;
1616 reg0 = gen_reg_rtx (DImode);
1617 reg1 = gen_reg_rtx (DImode);
1618 len = gen_reg_rtx (DImode);
1619 blocks = gen_reg_rtx (DImode);
1621 emit_move_insn (len, operands[2]);
1622 emit_insn (gen_cmpdi (len, const0_rtx));
1623 emit_jump_insn (gen_beq (label1));
1624 emit_move_insn (reg0, addr0);
1625 emit_move_insn (reg1, addr1);
1626 emit_insn (gen_adddi3 (len, len, constm1_rtx));
1627 emit_insn (gen_ashrdi3 (blocks, len, GEN_INT (8)));
1628 emit_insn (gen_cmpdi (blocks, const0_rtx));
1629 emit_jump_insn (gen_beq (label2));
1630 emit_insn (gen_movstrdi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1631 emit_label (label2);
1632 operands[0] = change_address (operands[0], VOIDmode, reg0);
1633 operands[1] = change_address (operands[1], VOIDmode, reg1);
1634 emit_insn (gen_movstrdi_short (operands[0], operands[1], len));
1635 emit_label (label1);
1642 ; movstrsi instruction pattern(s).
1645 (define_expand "movstrsi"
1646 [(set (match_operand:BLK 0 "general_operand" "")
1647 (match_operand:BLK 1 "general_operand" ""))
1648 (use (match_operand:SI 2 "general_operand" ""))
1649 (match_operand 3 "" "")]
1653 rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1654 rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1656 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1658 operands[0] = change_address (operands[0], VOIDmode, addr0);
1659 operands[1] = change_address (operands[1], VOIDmode, addr1);
1660 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1662 emit_insn (gen_movstrsi_short (operands[0], operands[1], operands[2]));
1669 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1670 rtx reg0 = gen_reg_rtx (DImode);
1671 rtx reg1 = gen_reg_rtx (DImode);
1672 rtx len = operands[2];
1675 if (! CONSTANT_P (len))
1676 len = force_reg (SImode, len);
1678 /* Load up the address+length pairs. */
1680 emit_move_insn (gen_highpart (SImode, reg0), addr0);
1681 emit_move_insn (gen_lowpart (SImode, reg0), len);
1683 emit_move_insn (gen_highpart (SImode, reg1), addr1);
1684 emit_move_insn (gen_lowpart (SImode, reg1), len);
1687 emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
1692 rtx label1 = gen_label_rtx ();
1693 rtx label2 = gen_label_rtx ();
1694 rtx reg0, reg1, len, blocks;
1696 reg0 = gen_reg_rtx (SImode);
1697 reg1 = gen_reg_rtx (SImode);
1698 len = gen_reg_rtx (SImode);
1699 blocks = gen_reg_rtx (SImode);
1701 emit_move_insn (len, operands[2]);
1702 emit_insn (gen_cmpsi (len, const0_rtx));
1703 emit_jump_insn (gen_beq (label1));
1704 emit_move_insn (reg0, addr0);
1705 emit_move_insn (reg1, addr1);
1706 emit_insn (gen_addsi3 (len, len, constm1_rtx));
1707 emit_insn (gen_ashrsi3 (blocks, len, GEN_INT (8)));
1708 emit_insn (gen_cmpsi (blocks, const0_rtx));
1709 emit_jump_insn (gen_beq (label2));
1710 emit_insn (gen_movstrsi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1711 emit_label (label2);
1712 operands[0] = change_address (operands[0], VOIDmode, reg0);
1713 operands[1] = change_address (operands[1], VOIDmode, reg1);
1714 emit_insn (gen_movstrsi_short (operands[0], operands[1], len));
1715 emit_label (label1);
1721 ; Move a block that is up to 256 bytes in length.
1722 ; The block length is taken as (operands[2] % 256) + 1.
1724 (define_insn "movstrdi_short"
1725 [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ")
1726 (match_operand:BLK 1 "s_operand" "oQ,oQ"))
1727 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1728 (clobber (match_scratch:DI 3 "=X,&a"))]
1732 switch (which_alternative)
1735 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1738 output_asm_insn (\"bras\\t%3,.+10\", operands);
1739 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1740 return \"ex\\t%2,0(%3)\";
1746 [(set_attr "op_type" "SS,NN")
1747 (set_attr "atype" "mem,mem")
1748 (set_attr "length" "*,14")])
1750 (define_insn "movstrsi_short"
1751 [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ")
1752 (match_operand:BLK 1 "s_operand" "oQ,oQ"))
1753 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1754 (clobber (match_scratch:SI 3 "=X,&a"))]
1758 switch (which_alternative)
1761 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1764 output_asm_insn (\"bras\\t%3,.+10\", operands);
1765 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1766 return \"ex\\t%2,0(%3)\";
1772 [(set_attr "op_type" "SS,NN")
1773 (set_attr "atype" "mem,mem")
1774 (set_attr "length" "*,14")])
1776 ; Move a block that is a multiple of 256 bytes in length
1778 (define_insn "movstrdi_long"
1779 [(set (match_operand:DI 4 "register_operand" "=d")
1781 (set (match_operand:DI 0 "register_operand" "=a")
1782 (plus:DI (match_operand:DI 2 "register_operand" "0")
1783 (ashift:DI (match_operand:DI 5 "register_operand" "4")
1785 (set (match_operand:DI 1 "register_operand" "=a")
1786 (plus:DI (match_operand:DI 3 "register_operand" "1")
1787 (ashift:DI (match_dup 5) (const_int 8))))
1788 (set (mem:BLK (match_dup 2))
1789 (mem:BLK (match_dup 3)))
1790 (use (match_dup 5))]
1794 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1795 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1796 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1797 return \"brct\\t%4,.-14\";
1799 [(set_attr "op_type" "NN")
1800 (set_attr "atype" "mem")
1801 (set_attr "length" "18")])
1803 (define_insn "movstrsi_long"
1804 [(set (match_operand:SI 4 "register_operand" "=d")
1806 (set (match_operand:SI 0 "register_operand" "=a")
1807 (plus:SI (match_operand:SI 2 "register_operand" "0")
1808 (ashift:SI (match_operand:SI 5 "register_operand" "4")
1810 (set (match_operand:SI 1 "register_operand" "=a")
1811 (plus:SI (match_operand:SI 3 "register_operand" "1")
1812 (ashift:SI (match_dup 5) (const_int 8))))
1813 (set (mem:BLK (match_dup 2))
1814 (mem:BLK (match_dup 3)))
1815 (use (match_dup 5))]
1819 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1820 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1821 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1822 return \"brct\\t%4,.-14\";
1824 [(set_attr "op_type" "NN")
1825 (set_attr "atype" "mem")
1826 (set_attr "length" "18")])
1828 ; Move a block that is larger than 255 bytes in length.
1830 (define_insn "movstrdi_64"
1831 [(set (match_operand:TI 0 "register_operand" "=d")
1832 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1833 (lshiftrt:TI (match_dup 2) (const_int 64)))
1835 (set (match_operand:TI 1 "register_operand" "=d")
1836 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1837 (lshiftrt:TI (match_dup 3) (const_int 64)))
1839 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1840 (mem:BLK (subreg:DI (match_dup 3) 0)))
1841 (clobber (reg:CC 33))]
1843 "mvcle\\t%0,%1,0\;jo\\t.-4"
1844 [(set_attr "op_type" "NN")
1845 (set_attr "atype" "mem")
1846 (set_attr "length" "8")])
1848 (define_insn "movstrsi_31"
1849 [(set (match_operand:DI 0 "register_operand" "=d")
1850 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1851 (lshiftrt:DI (match_dup 2) (const_int 32)))
1853 (set (match_operand:DI 1 "register_operand" "=d")
1854 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1855 (lshiftrt:DI (match_dup 3) (const_int 32)))
1857 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1858 (mem:BLK (subreg:SI (match_dup 3) 0)))
1859 (clobber (reg:CC 33))]
1861 "mvcle\\t%0,%1,0\;jo\\t.-4"
1862 [(set_attr "op_type" "NN")
1863 (set_attr "atype" "mem")
1864 (set_attr "length" "8")])
1867 ; clrstrdi instruction pattern(s).
1870 (define_expand "clrstrdi"
1871 [(set (match_operand:BLK 0 "general_operand" "")
1873 (use (match_operand:DI 1 "general_operand" ""))
1874 (match_operand 2 "" "")]
1878 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1880 operands[0] = change_address (operands[0], VOIDmode, addr);
1882 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1884 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1889 rtx reg0 = gen_reg_rtx (TImode);
1890 rtx reg1 = gen_reg_rtx (TImode);
1891 rtx len = operands[1];
1893 if (! CONSTANT_P (len))
1894 len = force_reg (DImode, len);
1896 /* Load up the address+length pairs. */
1898 emit_move_insn (gen_highpart (DImode, reg0), addr);
1899 emit_move_insn (gen_lowpart (DImode, reg0), len);
1901 emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
1904 emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0));
1910 ; clrstrsi instruction pattern(s).
1913 (define_expand "clrstrsi"
1914 [(set (match_operand:BLK 0 "general_operand" "")
1916 (use (match_operand:SI 1 "general_operand" ""))
1917 (match_operand 2 "" "")]
1921 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1923 operands[0] = change_address (operands[0], VOIDmode, addr);
1925 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1927 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1932 rtx reg0 = gen_reg_rtx (DImode);
1933 rtx reg1 = gen_reg_rtx (DImode);
1934 rtx len = operands[1];
1936 if (! CONSTANT_P (len))
1937 len = force_reg (SImode, len);
1939 /* Load up the address+length pairs. */
1941 emit_move_insn (gen_highpart (SImode, reg0), addr);
1942 emit_move_insn (gen_lowpart (SImode, reg0), len);
1944 emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
1947 emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0));
1952 ; Clear memory with length less than 256 bytes
1954 (define_insn "clrstrsico"
1955 [(set (match_operand:BLK 0 "s_operand" "=Qo")
1957 (use (match_operand 1 "immediate_operand" "I"))
1958 (clobber (reg:CC 33))]
1960 "xc\\t%O0(%1,%R0),%0"
1961 [(set_attr "op_type" "RS")
1962 (set_attr "type" "cs")
1963 (set_attr "atype" "mem")])
1965 ; Clear memory with length greater 256 bytes or lenght not constant
1967 (define_insn "clrstrsi_64"
1968 [(set (match_operand:TI 0 "register_operand" "=d")
1969 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1970 (lshiftrt:TI (match_dup 2) (const_int 64)))
1972 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1974 (use (match_operand:TI 1 "register_operand" "d"))
1975 (clobber (reg:CC 33))]
1977 "mvcle\\t%0,%1,0\;jo\\t.-4"
1978 [(set_attr "op_type" "NN")
1979 (set_attr "atype" "mem")
1980 (set_attr "type" "vs")
1981 (set_attr "length" "8")])
1983 (define_insn "clrstrsi_31"
1984 [(set (match_operand:DI 0 "register_operand" "=d")
1985 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1986 (lshiftrt:DI (match_dup 2) (const_int 32)))
1988 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1990 (use (match_operand:DI 1 "register_operand" "d"))
1991 (clobber (reg:CC 33))]
1993 "mvcle\\t%0,%1,0\;jo\\t.-4"
1994 [(set_attr "op_type" "NN")
1995 (set_attr "atype" "mem")
1996 (set_attr "type" "vs")
1997 (set_attr "length" "8")])
2000 ; cmpstrdi instruction pattern(s).
2003 (define_expand "cmpstrdi"
2004 [(set (match_operand:DI 0 "register_operand" "")
2005 (compare:DI (match_operand:BLK 1 "s_operand" "")
2006 (match_operand:BLK 2 "s_operand" "") ) )
2007 (use (match_operand:DI 3 "general_operand" ""))
2008 (use (match_operand:DI 4 "" ""))]
2014 /* for pre/post increment */
2015 operands[1] = protect_from_queue (operands[1], 0);
2016 operands[2] = protect_from_queue (operands[2], 0);
2017 operands[3] = protect_from_queue (operands[3], 0);
2019 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2020 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2022 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2024 if (INTVAL (operands[3]) == 0) {
2025 emit_move_insn (operands[0], operands[3]);
2029 operands[1] = change_address (operands[1], VOIDmode, addr0);
2030 operands[2] = change_address (operands[2], VOIDmode, addr1);
2032 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2033 emit_insn (gen_cmpint_di (operands[0]));
2038 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2039 rtx reg0 = gen_reg_rtx (TImode);
2040 rtx reg1 = gen_reg_rtx (TImode);
2041 rtx len = operands[3];
2043 if (! CONSTANT_P (len))
2044 len = force_reg (DImode, len);
2046 /* Load up the address+length pairs. */
2047 emit_move_insn (gen_highpart (DImode, reg0), addr0);
2048 emit_move_insn (gen_lowpart (DImode, reg0), len);
2050 emit_move_insn (gen_highpart (DImode, reg1), addr1);
2051 emit_move_insn (gen_lowpart (DImode, reg1), len);
2054 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2055 emit_insn (gen_cmpint_di (operands[0]));
2061 ; cmpstrsi instruction pattern(s).
2064 (define_expand "cmpstrsi"
2065 [(set (match_operand:SI 0 "register_operand" "")
2066 (compare:SI (match_operand:BLK 1 "s_operand" "")
2067 (match_operand:BLK 2 "s_operand" "") ) )
2068 (use (match_operand:SI 3 "general_operand" ""))
2069 (use (match_operand:SI 4 "" ""))]
2075 /* for pre/post increment */
2076 operands[1] = protect_from_queue (operands[1], 0);
2077 operands[2] = protect_from_queue (operands[2], 0);
2078 operands[3] = protect_from_queue (operands[3], 0);
2080 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2081 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2083 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2085 if (INTVAL (operands[3]) == 0) {
2086 emit_move_insn (operands[0], operands[3]);
2090 operands[1] = change_address (operands[1], VOIDmode, addr0);
2091 operands[2] = change_address (operands[2], VOIDmode, addr1);
2093 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2094 emit_insn (gen_cmpint_si (operands[0]));
2099 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2101 rtx len = operands[3];
2105 reg0 = gen_reg_rtx (TImode);
2106 reg1 = gen_reg_rtx (TImode);
2110 reg0 = gen_reg_rtx (DImode);
2111 reg1 = gen_reg_rtx (DImode);
2114 if (! CONSTANT_P (len))
2115 len = force_reg (Pmode, len);
2117 /* Load up the address+length pairs. */
2118 emit_move_insn (gen_highpart (Pmode, reg0), addr0);
2119 emit_move_insn (gen_lowpart (Pmode, reg0), len);
2121 emit_move_insn (gen_highpart (Pmode, reg1), addr1);
2122 emit_move_insn (gen_lowpart (Pmode, reg1), len);
2126 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2128 emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
2130 emit_insn (gen_cmpint_si (operands[0]));
2135 ; Compare a block that is less than 256 bytes in length.
2137 (define_insn "cmpstr_const"
2139 (compare:CCS (match_operand:BLK 0 "s_operand" "oQ")
2140 (match_operand:BLK 1 "s_operand" "oQ")))
2141 (use (match_operand 2 "immediate_operand" "I"))]
2142 "(unsigned) INTVAL (operands[2]) < 256"
2143 "clc\\t%O0(%c2,%R0),%1"
2144 [(set_attr "op_type" "SS")
2145 (set_attr "atype" "mem")
2146 (set_attr "type" "cs")])
2148 ; Compare a block that is larger than 255 bytes in length.
2150 (define_insn "cmpstr_64"
2151 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2152 (clobber (match_operand:TI 1 "register_operand" "=d"))
2154 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2155 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))]
2158 [(set_attr "op_type" "RR")
2159 (set_attr "atype" "mem")
2160 (set_attr "type" "vs")])
2162 (define_insn "cmpstr_31"
2163 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2164 (clobber (match_operand:DI 1 "register_operand" "=d"))
2166 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2167 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))]
2170 [(set_attr "op_type" "RR")
2171 (set_attr "atype" "mem")
2172 (set_attr "type" "vs")])
2174 ; Convert condition code to integer in range (-1, 0, 1)
2176 (define_insn "cmpint_si"
2177 [(set (match_operand:SI 0 "register_operand" "=d")
2178 (compare:SI (reg:CCS 33) (const_int 0)))]
2182 output_asm_insn (\"lhi\\t%0,1\", operands);
2183 output_asm_insn (\"jh\\t.+12\", operands);
2184 output_asm_insn (\"jl\\t.+6\", operands);
2185 output_asm_insn (\"sr\\t%0,%0\", operands);
2186 return \"lcr\\t%0,%0\";
2188 [(set_attr "op_type" "NN")
2189 (set_attr "length" "16")
2190 (set_attr "atype" "reg")
2191 (set_attr "type" "other")])
2193 (define_insn "cmpint_di"
2194 [(set (match_operand:DI 0 "register_operand" "=d")
2195 (compare:DI (reg:CCS 33) (const_int 0)))]
2199 output_asm_insn (\"lghi\\t%0,1\", operands);
2200 output_asm_insn (\"jh\\t.+12\", operands);
2201 output_asm_insn (\"jl\\t.+6\", operands);
2202 output_asm_insn (\"sgr\\t%0,%0\", operands);
2203 return \"lcgr\\t%0,%0\";
2205 [(set_attr "op_type" "NN")
2206 (set_attr "length" "22")
2207 (set_attr "atype" "reg")
2208 (set_attr "type" "other")])
2212 ;;- Conversion instructions.
2215 (define_insn "*sethighqisi"
2216 [(set (match_operand:SI 0 "register_operand" "=d")
2217 (unspec:SI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2218 (clobber (reg:CC 33))]
2221 [(set_attr "op_type" "RS")
2222 (set_attr "atype" "mem")])
2224 (define_insn "*sethighhisi"
2225 [(set (match_operand:SI 0 "register_operand" "=d")
2226 (unspec:SI [(match_operand:HI 1 "s_operand" "Qo")] 10))
2227 (clobber (reg:CC 33))]
2230 [(set_attr "op_type" "RS")
2231 (set_attr "atype" "mem")])
2233 (define_insn "*sethighqidi_64"
2234 [(set (match_operand:DI 0 "register_operand" "=d")
2235 (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2236 (clobber (reg:CC 33))]
2239 [(set_attr "op_type" "RSE")
2240 (set_attr "atype" "mem")])
2242 (define_insn "*sethighqidi_31"
2243 [(set (match_operand:DI 0 "register_operand" "=d")
2244 (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2245 (clobber (reg:CC 33))]
2248 [(set_attr "op_type" "RS")
2249 (set_attr "atype" "mem")])
2252 [(set (match_operand:SI 0 "register_operand" "")
2253 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2254 (match_operand 2 "const_int_operand" "")
2256 "!TARGET_64BIT && !reload_completed
2257 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2259 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2260 (clobber (reg:CC 33))])
2261 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2264 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2265 operands[1] = change_address (operands[1], QImode, 0);
2269 [(set (match_operand:SI 0 "register_operand" "")
2270 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2271 (match_operand 2 "const_int_operand" "")
2273 "!TARGET_64BIT && !reload_completed
2274 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2276 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2277 (clobber (reg:CC 33))])
2278 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2281 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2282 operands[1] = change_address (operands[1], HImode, 0);
2286 ; extendsidi2 instruction pattern(s).
2289 (define_expand "extendsidi2"
2290 [(set (match_operand:DI 0 "register_operand" "")
2291 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2297 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2298 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2299 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2300 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2306 (define_insn "*extendsidi2"
2307 [(set (match_operand:DI 0 "register_operand" "=d,d")
2308 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2313 [(set_attr "op_type" "RRE,RXE")
2314 (set_attr "atype" "reg,mem")])
2317 ; extendhidi2 instruction pattern(s).
2320 (define_expand "extendhidi2"
2321 [(set (match_operand:DI 0 "register_operand" "")
2322 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2328 rtx tmp = gen_reg_rtx (SImode);
2329 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2330 emit_insn (gen_extendsidi2 (operands[0], tmp));
2335 operands[1] = gen_lowpart (DImode, operands[1]);
2336 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2337 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2343 (define_insn "*extendhidi2"
2344 [(set (match_operand:DI 0 "register_operand" "=d")
2345 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2348 [(set_attr "op_type" "RXE")
2349 (set_attr "atype" "mem")])
2352 ; extendqidi2 instruction pattern(s).
2355 (define_expand "extendqidi2"
2356 [(set (match_operand:DI 0 "register_operand" "")
2357 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2363 rtx tmp = gen_reg_rtx (SImode);
2364 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2365 emit_insn (gen_extendsidi2 (operands[0], tmp));
2370 operands[1] = gen_lowpart (DImode, operands[1]);
2371 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2372 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2379 [(set (match_operand:DI 0 "register_operand" "")
2380 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2381 "TARGET_64BIT && !reload_completed"
2383 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2384 (clobber (reg:CC 33))])
2386 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2387 (clobber (reg:CC 33))])]
2391 ; extendhisi2 instruction pattern(s).
2394 (define_expand "extendhisi2"
2395 [(set (match_operand:SI 0 "register_operand" "")
2396 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2400 operands[1] = gen_lowpart (SImode, operands[1]);
2401 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2402 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2407 (define_insn "*extendhisi2"
2408 [(set (match_operand:SI 0 "register_operand" "=d")
2409 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2412 [(set_attr "op_type" "RX")
2413 (set_attr "atype" "mem")])
2416 ; extendqisi2 instruction pattern(s).
2419 (define_expand "extendqisi2"
2420 [(set (match_operand:SI 0 "register_operand" "")
2421 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2425 operands[1] = gen_lowpart (SImode, operands[1]);
2426 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2427 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2433 [(set (match_operand:SI 0 "register_operand" "")
2434 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2437 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2438 (clobber (reg:CC 33))])
2440 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2441 (clobber (reg:CC 33))])]
2445 ; extendqihi2 instruction pattern(s).
2450 ; zero_extendsidi2 instruction pattern(s).
2453 (define_expand "zero_extendsidi2"
2454 [(set (match_operand:DI 0 "register_operand" "")
2455 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2461 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2462 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2463 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2469 (define_insn "*zero_extendsidi2"
2470 [(set (match_operand:DI 0 "register_operand" "=d,d")
2471 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2476 [(set_attr "op_type" "RRE,RXE")
2477 (set_attr "atype" "reg,mem")])
2480 ; zero_extendhidi2 instruction pattern(s).
2483 (define_expand "zero_extendhidi2"
2484 [(set (match_operand:DI 0 "register_operand" "")
2485 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2491 rtx tmp = gen_reg_rtx (SImode);
2492 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2493 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2498 operands[1] = gen_lowpart (DImode, operands[1]);
2499 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2500 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2506 (define_insn "*zero_extendhidi2"
2507 [(set (match_operand:DI 0 "register_operand" "=d")
2508 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2511 [(set_attr "op_type" "RXE")
2512 (set_attr "atype" "mem")])
2515 ; zero_extendqidi2 instruction pattern(s)
2518 (define_expand "zero_extendqidi2"
2519 [(set (match_operand:DI 0 "register_operand" "")
2520 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2526 rtx tmp = gen_reg_rtx (SImode);
2527 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2528 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2533 operands[1] = gen_lowpart (DImode, operands[1]);
2534 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2535 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2541 (define_insn "*zero_extendqidi2"
2542 [(set (match_operand:DI 0 "register_operand" "=d")
2543 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2546 [(set_attr "op_type" "RXE")
2547 (set_attr "atype" "mem")])
2550 ; zero_extendhisi2 instruction pattern(s).
2553 (define_expand "zero_extendhisi2"
2554 [(set (match_operand:SI 0 "register_operand" "")
2555 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2559 operands[1] = gen_lowpart (SImode, operands[1]);
2560 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2565 (define_insn "*zero_extendhisi2_64"
2566 [(set (match_operand:SI 0 "register_operand" "=d")
2567 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2570 [(set_attr "op_type" "RXE")
2571 (set_attr "atype" "mem")])
2574 ; zero_extendqisi2 instruction pattern(s).
2577 (define_expand "zero_extendqisi2"
2578 [(set (match_operand:SI 0 "register_operand" "")
2579 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2583 operands[1] = gen_lowpart (SImode, operands[1]);
2584 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2589 (define_insn "*zero_extendqisi2_64"
2590 [(set (match_operand:SI 0 "register_operand" "=d")
2591 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2594 [(set_attr "op_type" "RXE")
2595 (set_attr "atype" "mem")])
2598 ; zero_extendqihi2 instruction pattern(s).
2601 (define_expand "zero_extendqihi2"
2602 [(set (match_operand:HI 0 "register_operand" "")
2603 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2607 operands[1] = gen_lowpart (HImode, operands[1]);
2608 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2613 (define_insn "*zero_extendqihi2_64"
2614 [(set (match_operand:HI 0 "register_operand" "=d")
2615 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2616 (clobber (reg:CC 33))]
2619 [(set_attr "op_type" "RXE")
2620 (set_attr "atype" "mem")])
2623 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2626 (define_expand "fixuns_truncdfdi2"
2627 [(set (match_operand:DI 0 "register_operand" "")
2628 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2629 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2632 rtx label1 = gen_label_rtx ();
2633 rtx label2 = gen_label_rtx ();
2634 rtx temp = gen_reg_rtx (DFmode);
2635 operands[1] = force_reg (DFmode, operands[1]);
2637 emit_insn (gen_cmpdf (operands[1],
2638 CONST_DOUBLE_FROM_REAL_VALUE (
2639 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2640 emit_jump_insn (gen_blt (label1));
2641 emit_insn (gen_subdf3 (temp, operands[1],
2642 CONST_DOUBLE_FROM_REAL_VALUE (
2643 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2644 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2647 emit_label (label1);
2648 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2649 emit_label (label2);
2653 (define_expand "fix_truncdfdi2"
2654 [(set (match_operand:DI 0 "register_operand" "")
2655 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2656 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2659 operands[1] = force_reg (DFmode, operands[1]);
2660 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2664 (define_insn "fix_truncdfdi2_ieee"
2665 [(set (match_operand:DI 0 "register_operand" "=d")
2666 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2667 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2668 (clobber (reg:CC 33))]
2669 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2671 [(set_attr "op_type" "RRE")
2672 (set_attr "type" "other")])
2675 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2678 (define_expand "fixuns_truncdfsi2"
2679 [(set (match_operand:SI 0 "register_operand" "")
2680 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2681 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2684 rtx label1 = gen_label_rtx ();
2685 rtx label2 = gen_label_rtx ();
2686 rtx temp = gen_reg_rtx (DFmode);
2688 operands[1] = force_reg (DFmode,operands[1]);
2689 emit_insn (gen_cmpdf (operands[1],
2690 CONST_DOUBLE_FROM_REAL_VALUE (
2691 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2692 emit_jump_insn (gen_blt (label1));
2693 emit_insn (gen_subdf3 (temp, operands[1],
2694 CONST_DOUBLE_FROM_REAL_VALUE (
2695 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2696 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2699 emit_label (label1);
2700 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2701 emit_label (label2);
2705 (define_expand "fix_truncdfsi2"
2706 [(set (match_operand:SI 0 "register_operand" "")
2707 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2711 if (TARGET_IBM_FLOAT)
2713 /* This is the algorithm from POP chapter A.5.7.2. */
2715 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2716 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2717 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2719 operands[1] = force_reg (DFmode, operands[1]);
2720 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2721 two31r, two32, temp));
2725 operands[1] = force_reg (DFmode, operands[1]);
2726 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2732 (define_insn "fix_truncdfsi2_ieee"
2733 [(set (match_operand:SI 0 "register_operand" "=d")
2734 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2735 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2736 (clobber (reg:CC 33))]
2737 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2739 [(set_attr "op_type" "RRE")
2740 (set_attr "type" "other" )])
2742 (define_insn "fix_truncdfsi2_ibm"
2743 [(set (match_operand:SI 0 "register_operand" "=d")
2744 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2745 (use (match_operand:DI 2 "immediate_operand" "m"))
2746 (use (match_operand:DI 3 "immediate_operand" "m"))
2747 (use (match_operand:BLK 4 "memory_operand" "m"))
2748 (clobber (reg:CC 33))]
2749 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2752 output_asm_insn (\"sd\\t%1,%2\", operands);
2753 output_asm_insn (\"aw\\t%1,%3\", operands);
2754 output_asm_insn (\"std\\t%1,%4\", operands);
2755 output_asm_insn (\"xi\\t%N4,128\", operands);
2756 return \"l\\t%0,%N4\";
2758 [(set_attr "op_type" "NN")
2759 (set_attr "type" "other")
2760 (set_attr "length" "20")])
2763 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2766 (define_expand "fixuns_truncsfdi2"
2767 [(set (match_operand:DI 0 "register_operand" "")
2768 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2769 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2772 rtx label1 = gen_label_rtx ();
2773 rtx label2 = gen_label_rtx ();
2774 rtx temp = gen_reg_rtx (SFmode);
2776 operands[1] = force_reg (SFmode, operands[1]);
2777 emit_insn (gen_cmpsf (operands[1],
2778 CONST_DOUBLE_FROM_REAL_VALUE (
2779 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2780 emit_jump_insn (gen_blt (label1));
2782 emit_insn (gen_subsf3 (temp, operands[1],
2783 CONST_DOUBLE_FROM_REAL_VALUE (
2784 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2785 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2788 emit_label (label1);
2789 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2790 emit_label (label2);
2794 (define_expand "fix_truncsfdi2"
2795 [(set (match_operand:DI 0 "register_operand" "")
2796 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2797 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2800 operands[1] = force_reg (SFmode, operands[1]);
2801 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2805 (define_insn "fix_truncsfdi2_ieee"
2806 [(set (match_operand:DI 0 "register_operand" "=d")
2807 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2808 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2809 (clobber (reg:CC 33))]
2810 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2812 [(set_attr "op_type" "RRE")
2813 (set_attr "type" "other")])
2816 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2819 (define_expand "fixuns_truncsfsi2"
2820 [(set (match_operand:SI 0 "register_operand" "")
2821 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2822 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2825 rtx label1 = gen_label_rtx ();
2826 rtx label2 = gen_label_rtx ();
2827 rtx temp = gen_reg_rtx (SFmode);
2829 operands[1] = force_reg (SFmode, operands[1]);
2830 emit_insn (gen_cmpsf (operands[1],
2831 CONST_DOUBLE_FROM_REAL_VALUE (
2832 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2833 emit_jump_insn (gen_blt (label1));
2834 emit_insn (gen_subsf3 (temp, operands[1],
2835 CONST_DOUBLE_FROM_REAL_VALUE (
2836 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2837 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2840 emit_label (label1);
2841 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2842 emit_label (label2);
2846 (define_expand "fix_truncsfsi2"
2847 [(set (match_operand:SI 0 "register_operand" "")
2848 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2852 if (TARGET_IBM_FLOAT)
2854 /* Convert to DFmode and then use the POP algorithm. */
2855 rtx temp = gen_reg_rtx (DFmode);
2856 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2857 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2861 operands[1] = force_reg (SFmode, operands[1]);
2862 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2868 (define_insn "fix_truncsfsi2_ieee"
2869 [(set (match_operand:SI 0 "register_operand" "=d")
2870 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2871 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2872 (clobber (reg:CC 33))]
2873 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2875 [(set_attr "op_type" "RRE")
2876 (set_attr "type" "other")])
2879 ; floatdidf2 instruction pattern(s).
2882 (define_insn "floatdidf2"
2883 [(set (match_operand:DF 0 "register_operand" "=f")
2884 (float:DF (match_operand:DI 1 "register_operand" "d")))
2885 (clobber (reg:CC 33))]
2886 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2888 [(set_attr "op_type" "RRE")
2889 (set_attr "type" "other" )])
2892 ; floatdisf2 instruction pattern(s).
2895 (define_insn "floatdisf2"
2896 [(set (match_operand:SF 0 "register_operand" "=f")
2897 (float:SF (match_operand:DI 1 "register_operand" "d")))
2898 (clobber (reg:CC 33))]
2899 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2901 [(set_attr "op_type" "RRE")
2902 (set_attr "type" "other" )])
2905 ; floatsidf2 instruction pattern(s).
2908 (define_expand "floatsidf2"
2910 [(set (match_operand:DF 0 "register_operand" "")
2911 (float:DF (match_operand:SI 1 "register_operand" "")))
2912 (clobber (reg:CC 33))])]
2916 if (TARGET_IBM_FLOAT)
2918 /* This is the algorithm from POP chapter A.5.7.1. */
2920 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2921 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2923 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2928 (define_insn "floatsidf2_ieee"
2929 [(set (match_operand:DF 0 "register_operand" "=f")
2930 (float:DF (match_operand:SI 1 "register_operand" "d")))
2931 (clobber (reg:CC 33))]
2932 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2934 [(set_attr "op_type" "RRE")
2935 (set_attr "type" "other" )])
2937 (define_insn "floatsidf2_ibm"
2938 [(set (match_operand:DF 0 "register_operand" "=f")
2939 (float:DF (match_operand:SI 1 "register_operand" "d")))
2940 (use (match_operand:DI 2 "immediate_operand" "m"))
2941 (use (match_operand:BLK 3 "memory_operand" "m"))
2942 (clobber (reg:CC 33))]
2943 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2946 output_asm_insn (\"st\\t%1,%N3\", operands);
2947 output_asm_insn (\"xi\\t%N3,128\", operands);
2948 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2949 output_asm_insn (\"ld\\t%0,%3\", operands);
2950 return \"sd\\t%0,%2\";
2952 [(set_attr "op_type" "NN")
2953 (set_attr "type" "other" )
2954 (set_attr "length" "20")])
2957 ; floatsisf2 instruction pattern(s).
2960 (define_expand "floatsisf2"
2962 [(set (match_operand:SF 0 "register_operand" "")
2963 (float:SF (match_operand:SI 1 "register_operand" "")))
2964 (clobber (reg:CC 33))])]
2968 if (TARGET_IBM_FLOAT)
2970 /* Use the POP algorithm to convert to DFmode and then truncate. */
2971 rtx temp = gen_reg_rtx (DFmode);
2972 emit_insn (gen_floatsidf2 (temp, operands[1]));
2973 emit_insn (gen_truncdfsf2 (operands[0], temp));
2978 (define_insn "floatsisf2_ieee"
2979 [(set (match_operand:SF 0 "register_operand" "=f")
2980 (float:SF (match_operand:SI 1 "register_operand" "d")))
2981 (clobber (reg:CC 33))]
2982 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2984 [(set_attr "op_type" "RRE")
2985 (set_attr "type" "other" )])
2988 ; truncdfsf2 instruction pattern(s).
2991 (define_expand "truncdfsf2"
2992 [(set (match_operand:SF 0 "register_operand" "")
2993 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2997 (define_insn "truncdfsf2_ieee"
2998 [(set (match_operand:SF 0 "register_operand" "=f")
2999 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
3000 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3002 [(set_attr "op_type" "RRE")])
3004 (define_insn "truncdfsf2_ibm"
3005 [(set (match_operand:SF 0 "register_operand" "=f,f")
3006 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
3007 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3011 [(set_attr "op_type" "RR,RX")
3012 (set_attr "atype" "reg,mem")])
3015 ; extendsfdf2 instruction pattern(s).
3018 (define_expand "extendsfdf2"
3019 [(set (match_operand:DF 0 "register_operand" "")
3020 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3024 if (TARGET_IBM_FLOAT)
3026 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3031 (define_insn "extendsfdf2_ieee"
3032 [(set (match_operand:DF 0 "register_operand" "=f,f")
3033 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
3034 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3038 [(set_attr "op_type" "RRE,RXE")])
3040 (define_insn "extendsfdf2_ibm"
3041 [(set (match_operand:DF 0 "register_operand" "=f,f")
3042 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
3043 (clobber (reg:CC 33))]
3044 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3046 sdr\\t%0,%0\;ler\\t%0,%1
3047 sdr\\t%0,%0\;le\\t%0,%1"
3048 [(set_attr "op_type" "RRE,RXE")
3049 (set_attr "atype" "reg,mem")
3050 (set_attr "type" "o2,o2")])
3054 ;; ARITHMETRIC OPERATIONS
3056 ; arithmetric operations set the ConditionCode,
3057 ; because of unpredictable Bits in Register for Halfword and Byte
3058 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3061 ;;- Add instructions.
3065 ; adddi3 instruction pattern(s).
3068 (define_insn "addaddr_esame"
3069 [(set (match_operand:DI 0 "register_operand" "=a,a")
3070 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
3071 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
3072 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3073 (REGNO (operands[1]) == BASE_REGISTER)) &&
3074 (GET_CODE (operands[2]) == REG ||
3075 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3079 [(set_attr "op_type" "RX")
3080 (set_attr "atype" "mem")
3081 (set_attr "type" "la")])
3083 (define_insn "adddi3_64"
3084 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3085 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3086 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3087 (clobber (reg:CC 33))]
3093 [(set_attr "op_type" "RRE,RI,RXE")
3094 (set_attr "atype" "reg,reg,mem")])
3096 (define_insn "adddi3_31"
3097 [(set (match_operand:DI 0 "register_operand" "=d,d")
3098 (plus:DI (match_operand:DI 1 "register_operand" "0,0")
3099 (match_operand:DI 2 "general_operand" "d,m") ) )
3100 (clobber (reg:CC 33))]
3104 switch (which_alternative)
3106 case 0: /* d <- d */
3107 output_asm_insn (\"ar\\t%0,%2\", operands);
3108 output_asm_insn (\"alr\\t%N0,%N2\", operands);
3111 case 1: /* d <- m */
3112 output_asm_insn (\"a\\t%0,%2\", operands);
3113 output_asm_insn (\"al\\t%N0,%N2\", operands);
3120 output_asm_insn (\"brc\\t12,.+8\", operands);
3121 return \"ahi\\t%0,1\";
3123 [(set_attr "op_type" "NN,NN")
3124 (set_attr "atype" "reg,mem")
3125 (set_attr "type" "o2,o2")
3126 (set_attr "length" "12,16")])
3128 (define_expand "adddi3"
3129 [(set (match_operand:DI 0 "register_operand" "")
3130 (plus:DI (match_operand:DI 1 "register_operand" "")
3131 (match_operand:DI 2 "general_operand" "")))]
3136 emit_insn(gen_adddi3_64 (operands[0],operands[1],operands[2]));
3138 emit_insn(gen_adddi3_31 (operands[0],operands[1],operands[2]));
3142 (define_insn "*la_64"
3143 [(set (match_operand:DI 0 "register_operand" "=d")
3144 (match_operand:QI 1 "address_operand" "p"))]
3147 [(set_attr "op_type" "RX")
3148 (set_attr "atype" "mem")
3149 (set_attr "type" "la")])
3151 (define_expand "reload_indi"
3152 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3153 (match_operand:DI 1 "s390_plus_operand" "")
3154 (match_operand:DI 2 "register_operand" "=&a")])]
3158 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3164 ; addsi3 instruction pattern(s).
3167 (define_insn "*la_ccclobber"
3168 [(set (match_operand:SI 0 "register_operand" "=d")
3169 (match_operand:QI 1 "address_operand" "p"))
3170 (clobber (reg:CC 33))]
3171 "legitimate_la_operand_p (operands[1])"
3173 [(set_attr "op_type" "RX")
3174 (set_attr "atype" "mem")
3175 (set_attr "type" "la")])
3177 (define_insn "*addsi3_cc"
3179 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3180 (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3182 (set (match_operand:SI 0 "register_operand" "=d,d")
3183 (plus:SI (match_dup 1) (match_dup 2)))]
3184 "s390_match_ccmode(insn, CCLmode)"
3188 [(set_attr "op_type" "RR,RX")
3189 (set_attr "atype" "reg,mem")])
3191 (define_insn "*addsi3_cconly"
3193 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3194 (match_operand:SI 2 "general_operand" "d,m"))
3196 (clobber (match_scratch:SI 0 "=d,d"))]
3197 "s390_match_ccmode(insn, CCLmode)"
3201 [(set_attr "op_type" "RR,RX")
3202 (set_attr "atype" "reg,mem")])
3204 (define_insn "*addsi3_cconly2"
3206 (compare (match_operand:SI 1 "register_operand" "%0,0")
3207 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3208 (clobber (match_scratch:SI 0 "=d,d"))]
3209 "s390_match_ccmode(insn, CCLmode)"
3213 [(set_attr "op_type" "RR,RX")
3214 (set_attr "atype" "reg,mem")])
3216 (define_insn "addsi3"
3217 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3218 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3219 (match_operand:SI 2 "general_operand" "d,K,m")))
3220 (clobber (reg:CC 33))]
3226 [(set_attr "op_type" "RR,RI,RX")
3227 (set_attr "atype" "reg,reg,mem")])
3229 (define_insn "*la_31"
3230 [(set (match_operand:SI 0 "register_operand" "=d")
3231 (match_operand:QI 1 "address_operand" "p"))]
3232 "legitimate_la_operand_p (operands[1])"
3234 [(set_attr "op_type" "RX")
3235 (set_attr "atype" "mem")
3236 (set_attr "type" "la")])
3238 (define_expand "reload_insi"
3239 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3240 (match_operand:SI 1 "s390_plus_operand" "")
3241 (match_operand:SI 2 "register_operand" "=&a")])]
3245 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3251 ; addhi3 instruction pattern(s).
3254 (define_insn "addhi3"
3255 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3256 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
3257 (match_operand:HI 2 "general_operand" "d,K,m")))
3258 (clobber (reg:CC 33))]
3264 [(set_attr "op_type" "RR,RI,RX")
3265 (set_attr "atype" "reg,reg,mem")])
3269 ; addqi3 instruction pattern(s).
3272 (define_insn "addqi3"
3273 [(set (match_operand:QI 0 "register_operand" "=d,d")
3274 (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
3275 (match_operand:QI 2 "general_operand" "a,n")))
3276 (clobber (reg:CC 33))]
3281 [(set_attr "op_type" "RX,RX")
3282 (set_attr "atype" "reg,mem")])
3286 ; adddf3 instruction pattern(s).
3289 (define_expand "adddf3"
3291 [(set (match_operand:DF 0 "register_operand" "=f,f")
3292 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3293 (match_operand:DF 2 "general_operand" "f,m")))
3294 (clobber (reg:CC 33))])]
3298 (define_insn "*adddf3"
3299 [(set (match_operand:DF 0 "register_operand" "=f,f")
3300 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3301 (match_operand:DF 2 "general_operand" "f,m")))
3302 (clobber (reg:CC 33))]
3303 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3307 [(set_attr "op_type" "RRE,RXE")
3308 (set_attr "atype" "reg,mem")])
3310 (define_insn "*adddf3_ibm"
3311 [(set (match_operand:DF 0 "register_operand" "=f,f")
3312 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3313 (match_operand:DF 2 "general_operand" "f,m")))
3314 (clobber (reg:CC 33))]
3315 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3319 [(set_attr "op_type" "RR,RX")
3320 (set_attr "atype" "reg,mem")])
3323 ; addsf3 instruction pattern(s).
3326 (define_expand "addsf3"
3328 [(set (match_operand:SF 0 "register_operand" "=f,f")
3329 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3330 (match_operand:SF 2 "general_operand" "f,m")))
3331 (clobber (reg:CC 33))])]
3335 (define_insn "*addsf3"
3336 [(set (match_operand:SF 0 "register_operand" "=f,f")
3337 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3338 (match_operand:SF 2 "general_operand" "f,m")))
3339 (clobber (reg:CC 33))]
3340 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3344 [(set_attr "op_type" "RRE,RXE")
3345 (set_attr "atype" "reg,mem")])
3347 (define_insn "*addsf3"
3348 [(set (match_operand:SF 0 "register_operand" "=f,f")
3349 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3350 (match_operand:SF 2 "general_operand" "f,m")))
3351 (clobber (reg:CC 33))]
3352 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3356 [(set_attr "op_type" "RR,RX")
3357 (set_attr "atype" "reg,mem")])
3361 ;;- Subtract instructions.
3365 ; subdi3 instruction pattern(s).
3368 (define_insn "*subdi3_64"
3369 [(set (match_operand:DI 0 "register_operand" "=d,d")
3370 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3371 (match_operand:DI 2 "general_operand" "d,m") ) )
3372 (clobber (reg:CC 33))]
3377 [(set_attr "op_type" "RRE,RRE")
3378 (set_attr "atype" "reg,mem")])
3380 (define_insn "subdi3"
3381 [(set (match_operand:DI 0 "register_operand" "=d,d")
3382 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3383 (match_operand:DI 2 "general_operand" "d,m")))
3384 (clobber (reg:CC 33))]
3388 switch (which_alternative)
3390 case 0: /* d <- d */
3391 output_asm_insn (\"sr\\t%0,%2\", operands);
3392 output_asm_insn (\"slr\\t%N0,%N2\", operands);
3394 case 1: /* d <- m */
3395 output_asm_insn (\"s\\t%0,%2\", operands);
3396 output_asm_insn (\"sl\\t%N0,%N2\", operands);
3403 output_asm_insn (\"brc\\t11,.+8\", operands);
3404 return \"ahi\\t%0,-1\";
3406 [(set_attr "op_type" "NN,NN")
3407 (set_attr "atype" "reg,mem")
3408 (set_attr "type" "other,other")
3409 (set_attr "length" "12,16")])
3412 ; subsi3 instruction pattern(s).
3415 (define_insn "*subsi3_cc"
3417 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3418 (match_operand:SI 2 "general_operand" "d,m"))
3420 (set (match_operand:SI 0 "register_operand" "=d,d")
3421 (minus:SI (match_dup 1) (match_dup 2)))]
3422 "s390_match_ccmode(insn, CCLmode)"
3426 [(set_attr "op_type" "RR,RX")
3427 (set_attr "atype" "reg,mem")])
3429 (define_insn "*subsi3_cconly"
3431 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3432 (match_operand:SI 2 "general_operand" "d,m"))
3434 (clobber (match_scratch:SI 0 "=d,d"))]
3435 "s390_match_ccmode(insn, CCLmode)"
3439 [(set_attr "op_type" "RR,RX")
3440 (set_attr "atype" "reg,mem")])
3442 (define_insn "subsi3"
3443 [(set (match_operand:SI 0 "register_operand" "=d,d")
3444 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3445 (match_operand:SI 2 "general_operand" "d,m")))
3446 (clobber (reg:CC 33))]
3451 [(set_attr "op_type" "RR,RX")
3452 (set_attr "atype" "reg,mem")])
3455 ; subhi3 instruction pattern(s).
3458 (define_insn "subhi3"
3459 [(set (match_operand:HI 0 "register_operand" "=d,d")
3460 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
3461 (match_operand:HI 2 "general_operand" "d,m")))
3462 (clobber (reg:CC 33))]
3467 [(set_attr "op_type" "RR,RX")
3468 (set_attr "atype" "reg,mem")])
3471 ; subqi3 instruction pattern(s).
3474 (define_insn "subqi3"
3475 [(set (match_operand:QI 0 "register_operand" "=d")
3476 (minus:QI (match_operand:QI 1 "register_operand" "0")
3477 (match_operand:QI 2 "register_operand" "d")))
3478 (clobber (reg:CC 33))]
3481 [(set_attr "op_type" "RR")])
3484 ; subdf3 instruction pattern(s).
3487 (define_expand "subdf3"
3489 [(set (match_operand:DF 0 "register_operand" "=f,f")
3490 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3491 (match_operand:DF 2 "general_operand" "f,m")))
3492 (clobber (reg:CC 33))])]
3496 (define_insn "*subdf3"
3497 [(set (match_operand:DF 0 "register_operand" "=f,f")
3498 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3499 (match_operand:DF 2 "general_operand" "f,m")))
3500 (clobber (reg:CC 33))]
3501 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3505 [(set_attr "op_type" "RRE,RXE")
3506 (set_attr "atype" "reg,mem")])
3508 (define_insn "*subdf3_ibm"
3509 [(set (match_operand:DF 0 "register_operand" "=f,f")
3510 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3511 (match_operand:DF 2 "general_operand" "f,m")))
3512 (clobber (reg:CC 33))]
3513 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3517 [(set_attr "op_type" "RR,RX")
3518 (set_attr "atype" "reg,mem")])
3521 ; subsf3 instruction pattern(s).
3524 (define_expand "subsf3"
3526 [(set (match_operand:SF 0 "register_operand" "=f,f")
3527 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3528 (match_operand:SF 2 "general_operand" "f,m")))
3529 (clobber (reg:CC 33))])]
3533 (define_insn "*subsf3"
3534 [(set (match_operand:SF 0 "register_operand" "=f,f")
3535 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3536 (match_operand:SF 2 "general_operand" "f,m")))
3537 (clobber (reg:CC 33))]
3538 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3542 [(set_attr "op_type" "RRE,RXE")
3543 (set_attr "atype" "reg,mem")])
3545 (define_insn "*subsf3_ibm"
3546 [(set (match_operand:SF 0 "register_operand" "=f,f")
3547 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3548 (match_operand:SF 2 "general_operand" "f,m")))
3549 (clobber (reg:CC 33))]
3550 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3554 [(set_attr "op_type" "RR,RX")
3555 (set_attr "atype" "reg,mem")])
3559 ;;- Multiply instructions.
3563 ; muldi3 instruction pattern(s).
3566 (define_insn "muldi3"
3567 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3568 (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3569 (match_operand:DI 2 "general_operand" "d,K,m")))
3570 (clobber (reg:CC 33))]
3576 [(set_attr "op_type" "RRE,RI,RX")
3577 (set_attr "atype" "reg,reg,mem")
3578 (set_attr "type" "imul")])
3581 ; mulsi3 instruction pattern(s).
3584 (define_insn "mulsi3"
3585 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3586 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3587 (match_operand:SI 2 "general_operand" "d,K,m")))
3588 (clobber (reg:CC 33))]
3594 [(set_attr "op_type" "RRE,RI,RX")
3595 (set_attr "atype" "reg,reg,mem")
3596 (set_attr "type" "imul")])
3599 ; mulsidi3 instruction pattern(s).
3602 (define_expand "mulsidi3"
3603 [(set (match_operand:DI 0 "register_operand" "")
3604 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3605 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3611 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
3612 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3613 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3616 gen_rtx_EXPR_LIST (REG_EQUAL,
3617 gen_rtx_MULT (DImode,
3618 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3619 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3624 (define_insn "mulsi_6432"
3625 [(set (match_operand:DI 0 "register_operand" "=d,d")
3626 (mult:DI (sign_extend:DI
3627 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3629 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3630 (clobber (reg:CC 33))]
3635 [(set_attr "op_type" "RR,RX")
3636 (set_attr "atype" "reg,mem")
3637 (set_attr "type" "imul")])
3640 ; muldf3 instruction pattern(s).
3643 (define_expand "muldf3"
3645 [(set (match_operand:DF 0 "register_operand" "=f,f")
3646 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3647 (match_operand:DF 2 "general_operand" "f,m")))
3648 (clobber (reg:CC 33))])]
3652 (define_insn "*muldf3"
3653 [(set (match_operand:DF 0 "register_operand" "=f,f")
3654 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3655 (match_operand:DF 2 "general_operand" "f,m")))
3656 (clobber (reg:CC 33))]
3657 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3661 [(set_attr "op_type" "RRE,RXE")
3662 (set_attr "type" "fmul")
3663 (set_attr "atype" "reg,mem")])
3665 (define_insn "*muldf3_ibm"
3666 [(set (match_operand:DF 0 "register_operand" "=f,f")
3667 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3668 (match_operand:DF 2 "general_operand" "f,m")))
3669 (clobber (reg:CC 33))]
3670 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3674 [(set_attr "op_type" "RR,RX")
3675 (set_attr "type" "fmul")
3676 (set_attr "atype" "reg,mem")])
3679 ; mulsf3 instruction pattern(s).
3682 (define_expand "mulsf3"
3684 [(set (match_operand:SF 0 "register_operand" "=f,f")
3685 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3686 (match_operand:SF 2 "general_operand" "f,m")))
3687 (clobber (reg:CC 33))])]
3691 (define_insn "*mulsf3"
3692 [(set (match_operand:SF 0 "register_operand" "=f,f")
3693 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3694 (match_operand:SF 2 "general_operand" "f,m")))
3695 (clobber (reg:CC 33))]
3696 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3700 [(set_attr "op_type" "RRE,RXE")
3701 (set_attr "type" "fmul")
3702 (set_attr "atype" "reg,mem")])
3704 (define_insn "*mulsf3_ibm"
3705 [(set (match_operand:SF 0 "register_operand" "=f,f")
3706 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3707 (match_operand:SF 2 "general_operand" "f,m")))
3708 (clobber (reg:CC 33))]
3709 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3713 [(set_attr "op_type" "RR,RX")
3714 (set_attr "type" "fmul")
3715 (set_attr "atype" "reg,mem")])
3719 ;;- Divide and modulo instructions.
3723 ; divmoddi4 instruction pattern(s).
3726 (define_expand "divmoddi4"
3727 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3728 (div:DI (match_operand:DI 1 "general_operand" "")
3729 (match_operand:DI 2 "general_operand" "")))
3730 (set (match_operand:DI 3 "general_operand" "")
3731 (mod:DI (match_dup 1) (match_dup 2)))])
3732 (clobber (match_dup 4))]
3736 rtx insn, div_equal, mod_equal, equal;
3738 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3739 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3740 equal = gen_rtx_IOR (TImode,
3741 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3742 gen_rtx_ASHIFT (TImode,
3743 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3746 operands[4] = gen_reg_rtx(TImode);
3747 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3748 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3749 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3750 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3752 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3754 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3756 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3758 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3760 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3765 (define_insn "divmodtidi3"
3766 [(set (match_operand:TI 0 "register_operand" "=d,d")
3769 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3770 (match_operand:DI 2 "general_operand" "d,m")))
3773 (mod:DI (truncate:DI (match_dup 1))
3780 [(set_attr "op_type" "RRE,RXE")
3781 (set_attr "type" "idiv")
3782 (set_attr "atype" "reg,mem")])
3784 (define_insn "divmodtisi3"
3785 [(set (match_operand:TI 0 "register_operand" "=d,d")
3788 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3789 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3792 (mod:DI (truncate:DI (match_dup 1))
3793 (sign_extend:DI (match_dup 2))))
3799 [(set_attr "op_type" "RRE,RXE")
3800 (set_attr "type" "idiv")
3801 (set_attr "atype" "reg,mem")])
3804 ; udivmoddi4 instruction pattern(s).
3807 (define_expand "udivmoddi4"
3808 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3809 (udiv:DI (match_operand:DI 1 "general_operand" "")
3810 (match_operand:DI 2 "nonimmediate_operand" "")))
3811 (set (match_operand:DI 3 "general_operand" "")
3812 (umod:DI (match_dup 1) (match_dup 2)))])
3813 (clobber (match_dup 4))]
3817 rtx insn, div_equal, mod_equal, equal;
3819 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3820 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3821 equal = gen_rtx_IOR (TImode,
3822 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3823 gen_rtx_ASHIFT (TImode,
3824 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3827 operands[4] = gen_reg_rtx(TImode);
3828 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3829 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3830 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3831 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3833 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3835 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3837 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3839 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3841 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3846 (define_insn "udivmodtidi3"
3847 [(set (match_operand:TI 0 "register_operand" "=d,d")
3848 (ior:TI (zero_extend:TI
3850 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3852 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3856 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3862 [(set_attr "op_type" "RRE,RXE")
3863 (set_attr "type" "idiv")
3864 (set_attr "atype" "reg,mem")])
3867 ; divmodsi4 instruction pattern(s).
3870 (define_expand "divmodsi4"
3871 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3872 (div:SI (match_operand:SI 1 "general_operand" "")
3873 (match_operand:SI 2 "nonimmediate_operand" "")))
3874 (set (match_operand:SI 3 "general_operand" "")
3875 (mod:SI (match_dup 1) (match_dup 2)))])
3876 (clobber (match_dup 4))]
3880 rtx insn, div_equal, mod_equal, equal;
3882 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3883 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3884 equal = gen_rtx_IOR (DImode,
3885 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3886 gen_rtx_ASHIFT (DImode,
3887 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3890 operands[4] = gen_reg_rtx(DImode);
3891 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3892 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3894 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3896 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3898 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3900 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3902 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3907 (define_insn "divmoddisi3"
3908 [(set (match_operand:DI 0 "register_operand" "=d,d")
3909 (ior:DI (zero_extend:DI
3911 (div:DI (match_operand:DI 1 "register_operand" "0,0")
3913 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3917 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
3923 [(set_attr "op_type" "RR,RX")
3924 (set_attr "type" "idiv")
3925 (set_attr "atype" "reg,mem")])
3928 ; udivsi3 and umodsi3 instruction pattern(s).
3932 (define_expand "udivsi3"
3933 [(set (match_operand:SI 0 "register_operand" "=d")
3934 (udiv:SI (match_operand:SI 1 "general_operand" "")
3935 (match_operand:SI 2 "general_operand" "")))
3936 (clobber (match_dup 3))]
3940 rtx insn, udiv_equal, umod_equal, equal;
3942 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3943 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
3944 equal = gen_rtx_IOR (DImode,
3945 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
3946 gen_rtx_ASHIFT (DImode,
3947 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
3950 operands[3] = gen_reg_rtx (DImode);
3952 if (CONSTANT_P (operands[2]))
3954 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3956 rtx label1 = gen_label_rtx ();
3958 operands[1] = make_safe_from (operands[1], operands[0]);
3959 emit_move_insn (operands[0], const0_rtx);
3960 emit_insn (gen_cmpsi (operands[1], operands[2]));
3961 emit_jump_insn (gen_bltu (label1));
3962 emit_move_insn (operands[0], const1_rtx);
3963 emit_label (label1);
3967 operands[2] = force_reg (SImode, operands[2]);
3968 operands[2] = make_safe_from (operands[2], operands[0]);
3970 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
3971 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
3974 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3976 insn = emit_move_insn (operands[0],
3977 gen_lowpart (SImode, operands[3]));
3979 gen_rtx_EXPR_LIST (REG_EQUAL,
3980 udiv_equal, REG_NOTES (insn));
3985 rtx label1 = gen_label_rtx ();
3986 rtx label2 = gen_label_rtx ();
3987 rtx label3 = gen_label_rtx ();
3989 operands[1] = force_reg (SImode, operands[1]);
3990 operands[1] = make_safe_from (operands[1], operands[0]);
3991 operands[2] = force_reg (SImode, operands[2]);
3992 operands[2] = make_safe_from (operands[2], operands[0]);
3994 emit_move_insn (operands[0], const0_rtx);
3995 emit_insn (gen_cmpsi (operands[2], operands[1]));
3996 emit_jump_insn (gen_bgtu (label3));
3997 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3998 emit_jump_insn (gen_blt (label2));
3999 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4000 emit_jump_insn (gen_beq (label1));
4001 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4002 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4005 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4007 insn = emit_move_insn (operands[0],
4008 gen_lowpart (SImode, operands[3]));
4010 gen_rtx_EXPR_LIST (REG_EQUAL,
4011 udiv_equal, REG_NOTES (insn));
4013 emit_label (label1);
4014 emit_move_insn (operands[0], operands[1]);
4016 emit_label (label2);
4017 emit_move_insn (operands[0], const1_rtx);
4018 emit_label (label3);
4020 emit_move_insn (operands[0], operands[0]);
4024 (define_expand "umodsi3"
4025 [(set (match_operand:SI 0 "register_operand" "=d")
4026 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4027 (match_operand:SI 2 "nonimmediate_operand" "")))
4028 (clobber (match_dup 3))]
4032 rtx insn, udiv_equal, umod_equal, equal;
4034 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4035 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4036 equal = gen_rtx_IOR (DImode,
4037 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4038 gen_rtx_ASHIFT (DImode,
4039 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4042 operands[3] = gen_reg_rtx (DImode);
4044 if (CONSTANT_P (operands[2]))
4046 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4048 rtx label1 = gen_label_rtx ();
4050 operands[1] = make_safe_from (operands[1], operands[0]);
4051 emit_move_insn (operands[0], operands[1]);
4052 emit_insn (gen_cmpsi (operands[0], operands[2]));
4053 emit_jump_insn (gen_bltu (label1));
4054 emit_insn (gen_abssi2 (operands[0], operands[2]));
4055 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4056 emit_label (label1);
4060 operands[2] = force_reg (SImode, operands[2]);
4061 operands[2] = make_safe_from (operands[2], operands[0]);
4063 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4064 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4067 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4069 insn = emit_move_insn (operands[0],
4070 gen_highpart (SImode, operands[3]));
4072 gen_rtx_EXPR_LIST (REG_EQUAL,
4073 umod_equal, REG_NOTES (insn));
4078 rtx label1 = gen_label_rtx ();
4079 rtx label2 = gen_label_rtx ();
4080 rtx label3 = gen_label_rtx ();
4082 operands[1] = force_reg (SImode, operands[1]);
4083 operands[1] = make_safe_from (operands[1], operands[0]);
4084 operands[2] = force_reg (SImode, operands[2]);
4085 operands[2] = make_safe_from (operands[2], operands[0]);
4087 emit_move_insn(operands[0], operands[1]);
4088 emit_insn (gen_cmpsi (operands[2], operands[1]));
4089 emit_jump_insn (gen_bgtu (label3));
4090 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4091 emit_jump_insn (gen_blt (label2));
4092 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4093 emit_jump_insn (gen_beq (label1));
4094 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4095 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4098 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4100 insn = emit_move_insn (operands[0],
4101 gen_highpart (SImode, operands[3]));
4103 gen_rtx_EXPR_LIST (REG_EQUAL,
4104 umod_equal, REG_NOTES (insn));
4106 emit_label (label1);
4107 emit_move_insn (operands[0], const0_rtx);
4109 emit_label (label2);
4110 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4111 emit_label (label3);
4117 ; divdf3 instruction pattern(s).
4120 (define_expand "divdf3"
4122 [(set (match_operand:DF 0 "register_operand" "=f,f")
4123 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4124 (match_operand:DF 2 "general_operand" "f,m")))
4125 (clobber (reg:CC 33))])]
4129 (define_insn "*divdf3"
4130 [(set (match_operand:DF 0 "register_operand" "=f,f")
4131 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4132 (match_operand:DF 2 "general_operand" "f,m")))
4133 (clobber (reg:CC 33))]
4134 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4138 [(set_attr "op_type" "RRE,RXE")
4139 (set_attr "type" "fdiv")
4140 (set_attr "atype" "reg,mem")])
4142 (define_insn "*divdf3_ibm"
4143 [(set (match_operand:DF 0 "register_operand" "=f,f")
4144 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4145 (match_operand:DF 2 "general_operand" "f,m")))
4146 (clobber (reg:CC 33))]
4147 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4151 [(set_attr "op_type" "RR,RX")
4152 (set_attr "type" "fdiv")
4153 (set_attr "atype" "reg,mem")])
4156 ; divsf3 instruction pattern(s).
4159 (define_expand "divsf3"
4161 [(set (match_operand:SF 0 "register_operand" "=f,f")
4162 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4163 (match_operand:SF 2 "general_operand" "f,m")))
4164 (clobber (reg:CC 33))])]
4168 (define_insn "*divsf3"
4169 [(set (match_operand:SF 0 "register_operand" "=f,f")
4170 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4171 (match_operand:SF 2 "general_operand" "f,m")))
4172 (clobber (reg:CC 33))]
4173 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4177 [(set_attr "op_type" "RRE,RXE")
4178 (set_attr "type" "fdiv")
4179 (set_attr "atype" "reg,mem")])
4181 (define_insn "*divsf3"
4182 [(set (match_operand:SF 0 "register_operand" "=f,f")
4183 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4184 (match_operand:SF 2 "general_operand" "f,m")))
4185 (clobber (reg:CC 33))]
4186 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4190 [(set_attr "op_type" "RR,RX")
4191 (set_attr "type" "fdiv")
4192 (set_attr "atype" "reg,mem")])
4196 ;;- And instructions.
4200 ; anddi3 instruction pattern(s).
4203 (define_insn "*anddi3_cc"
4205 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4206 (match_operand:DI 2 "general_operand" "d,m"))
4208 (set (match_operand:DI 0 "register_operand" "=d,d")
4209 (and:DI (match_dup 1) (match_dup 2)))]
4210 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4214 [(set_attr "op_type" "RRE,RXE")
4215 (set_attr "atype" "reg,mem")])
4217 (define_insn "*anddi3_cconly"
4219 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4220 (match_operand:DI 2 "general_operand" "d,m"))
4222 (clobber (match_scratch:DI 0 "=d,d"))]
4223 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4227 [(set_attr "op_type" "RRE,RXE")
4228 (set_attr "atype" "reg,mem")])
4230 (define_insn "*anddi3_ni"
4231 [(set (match_operand:DI 0 "register_operand" "=d")
4232 (and:DI (match_operand:DI 1 "register_operand" "%0")
4233 (match_operand:DI 2 "immediate_operand" "n")))
4234 (clobber (reg:CC 33))]
4235 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4238 int part = s390_single_hi (operands[2], DImode, -1);
4239 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4243 case 0: return \"nihh\\t%0,%x2\";
4244 case 1: return \"nihl\\t%0,%x2\";
4245 case 2: return \"nilh\\t%0,%x2\";
4246 case 3: return \"nill\\t%0,%x2\";
4250 [(set_attr "op_type" "RI")
4251 (set_attr "atype" "reg")])
4253 (define_insn "anddi3"
4254 [(set (match_operand:DI 0 "register_operand" "=d,d")
4255 (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4256 (match_operand:DI 2 "general_operand" "d,m")))
4257 (clobber (reg:CC 33))]
4262 [(set_attr "op_type" "RRE,RXE")
4263 (set_attr "atype" "reg,mem")])
4265 (define_insn "*anddi3_ss"
4266 [(set (match_operand:DI 0 "s_operand" "=Qo")
4267 (and:DI (match_dup 0)
4268 (match_operand:DI 1 "s_imm_operand" "Qo")))
4269 (clobber (reg:CC 33))]
4271 "nc\\t%O0(8,%R0),%1"
4272 [(set_attr "op_type" "SS")
4273 (set_attr "atype" "mem")])
4275 (define_insn "*anddi3_ss_inv"
4276 [(set (match_operand:DI 0 "s_operand" "=Qo")
4277 (and:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4279 (clobber (reg:CC 33))]
4281 "nc\\t%O0(8,%R0),%1"
4282 [(set_attr "op_type" "SS")
4283 (set_attr "atype" "mem")])
4286 ; andsi3 instruction pattern(s).
4289 (define_insn "*andsi3_cc"
4291 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4292 (match_operand:SI 2 "general_operand" "d,m"))
4294 (set (match_operand:SI 0 "register_operand" "=d,d")
4295 (and:SI (match_dup 1) (match_dup 2)))]
4296 "s390_match_ccmode(insn, CCTmode)"
4300 [(set_attr "op_type" "RR,RX")
4301 (set_attr "atype" "reg,mem")])
4303 (define_insn "*andsi3_cconly"
4305 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4306 (match_operand:SI 2 "general_operand" "d,m"))
4308 (clobber (match_scratch:SI 0 "=d,d"))]
4309 "s390_match_ccmode(insn, CCTmode)"
4313 [(set_attr "op_type" "RR,RX")
4314 (set_attr "atype" "reg,mem")])
4316 (define_insn "*andsi3_ni"
4317 [(set (match_operand:SI 0 "register_operand" "=d")
4318 (and:SI (match_operand:SI 1 "register_operand" "%0")
4319 (match_operand:SI 2 "immediate_operand" "n")))
4320 (clobber (reg:CC 33))]
4321 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4324 int part = s390_single_hi (operands[2], SImode, -1);
4325 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4329 case 0: return \"nilh\\t%0,%x2\";
4330 case 1: return \"nill\\t%0,%x2\";
4334 [(set_attr "op_type" "RI")
4335 (set_attr "atype" "reg")])
4337 (define_insn "andsi3"
4338 [(set (match_operand:SI 0 "register_operand" "=d,d")
4339 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4340 (match_operand:SI 2 "general_operand" "d,m")))
4341 (clobber (reg:CC 33))]
4346 [(set_attr "op_type" "RR,RX")
4347 (set_attr "atype" "reg,mem")])
4349 (define_insn "*andsi3_ss"
4350 [(set (match_operand:SI 0 "s_operand" "=Qo")
4351 (and:SI (match_dup 0)
4352 (match_operand:SI 1 "s_imm_operand" "Qo")))
4353 (clobber (reg:CC 33))]
4355 "nc\\t%O0(4,%R0),%1"
4356 [(set_attr "op_type" "SS")
4357 (set_attr "atype" "mem")])
4359 (define_insn "*andsi3_ss_inv"
4360 [(set (match_operand:SI 0 "s_operand" "=Qo")
4361 (and:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4363 (clobber (reg:CC 33))]
4365 "nc\\t%O0(4,%R0),%1"
4366 [(set_attr "op_type" "SS")
4367 (set_attr "atype" "mem")])
4370 ; andhi3 instruction pattern(s).
4373 (define_insn "*andhi3_ni"
4374 [(set (match_operand:HI 0 "register_operand" "=d,d")
4375 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4376 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4377 (clobber (reg:CC 33))]
4382 [(set_attr "op_type" "RR,RI")
4383 (set_attr "atype" "reg")])
4385 (define_insn "andhi3"
4386 [(set (match_operand:HI 0 "register_operand" "=d")
4387 (and:HI (match_operand:HI 1 "register_operand" "%0")
4388 (match_operand:HI 2 "nonmemory_operand" "d")))
4389 (clobber (reg:CC 33))]
4392 [(set_attr "op_type" "RR")
4393 (set_attr "atype" "reg")])
4395 (define_insn "*andhi3_ss"
4396 [(set (match_operand:HI 0 "s_operand" "=Qo")
4397 (and:HI (match_dup 0)
4398 (match_operand:HI 1 "s_imm_operand" "Qo")))
4399 (clobber (reg:CC 33))]
4401 "nc\\t%O0(2,%R0),%1"
4402 [(set_attr "op_type" "SS")
4403 (set_attr "atype" "mem")])
4405 (define_insn "*andhi3_ss_inv"
4406 [(set (match_operand:HI 0 "s_operand" "=Qo")
4407 (and:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4409 (clobber (reg:CC 33))]
4411 "nc\\t%O0(2,%R0),%1"
4412 [(set_attr "op_type" "SS")
4413 (set_attr "atype" "mem")])
4416 ; andqi3 instruction pattern(s).
4419 (define_insn "*andqi3_ni"
4420 [(set (match_operand:QI 0 "register_operand" "=d,d")
4421 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4422 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4423 (clobber (reg:CC 33))]
4428 [(set_attr "op_type" "RR,RI")
4429 (set_attr "atype" "reg")])
4431 (define_insn "andqi3"
4432 [(set (match_operand:QI 0 "register_operand" "=d")
4433 (and:QI (match_operand:QI 1 "register_operand" "%0")
4434 (match_operand:QI 2 "nonmemory_operand" "d")))
4435 (clobber (reg:CC 33))]
4438 [(set_attr "op_type" "RR")
4439 (set_attr "atype" "reg")])
4441 (define_insn "*andqi3_ss"
4442 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4443 (and:QI (match_dup 0)
4444 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4445 (clobber (reg:CC 33))]
4450 [(set_attr "op_type" "SI,SS")
4451 (set_attr "atype" "mem")])
4453 (define_insn "*andqi3_ss_inv"
4454 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4455 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4457 (clobber (reg:CC 33))]
4462 [(set_attr "op_type" "SI,SS")
4463 (set_attr "atype" "mem")])
4467 ;;- Bit set (inclusive or) instructions.
4471 ; iordi3 instruction pattern(s).
4474 (define_insn "*iordi3_cc"
4476 (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4477 (match_operand:DI 2 "general_operand" "d,m"))
4479 (set (match_operand:DI 0 "register_operand" "=d,d")
4480 (ior:DI (match_dup 1) (match_dup 2)))]
4481 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4485 [(set_attr "op_type" "RRE,RXE")
4486 (set_attr "atype" "reg,mem")])
4488 (define_insn "*iordi3_cconly"
4490 (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4491 (match_operand:DI 2 "general_operand" "d,m"))
4493 (clobber (match_scratch:DI 0 "=d,d"))]
4494 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4498 [(set_attr "op_type" "RRE,RXE")
4499 (set_attr "atype" "reg,mem")])
4501 (define_insn "*iordi3_oi"
4502 [(set (match_operand:DI 0 "register_operand" "=d")
4503 (ior:DI (match_operand:DI 1 "register_operand" "%0")
4504 (match_operand:DI 2 "immediate_operand" "n")))
4505 (clobber (reg:CC 33))]
4506 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4509 int part = s390_single_hi (operands[2], DImode, 0);
4510 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4514 case 0: return \"oihh\\t%0,%x2\";
4515 case 1: return \"oihl\\t%0,%x2\";
4516 case 2: return \"oilh\\t%0,%x2\";
4517 case 3: return \"oill\\t%0,%x2\";
4521 [(set_attr "op_type" "RI")
4522 (set_attr "atype" "reg")])
4524 (define_insn "iordi3"
4525 [(set (match_operand:DI 0 "register_operand" "=d,d")
4526 (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4527 (match_operand:DI 2 "general_operand" "d,m")))
4528 (clobber (reg:CC 33))]
4533 [(set_attr "op_type" "RRE,RXE")
4534 (set_attr "atype" "reg,mem")])
4536 (define_insn "*iordi3_ss"
4537 [(set (match_operand:DI 0 "s_operand" "=Qo")
4538 (ior:DI (match_dup 0)
4539 (match_operand:DI 1 "s_imm_operand" "Qo")))
4540 (clobber (reg:CC 33))]
4542 "oc\\t%O0(8,%R0),%1"
4543 [(set_attr "op_type" "SS")
4544 (set_attr "atype" "mem")])
4546 (define_insn "*iordi3_ss_inv"
4547 [(set (match_operand:DI 0 "s_operand" "=Qo")
4548 (ior:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4550 (clobber (reg:CC 33))]
4552 "oc\\t%O0(8,%R0),%1"
4553 [(set_attr "op_type" "SS")
4554 (set_attr "atype" "mem")])
4557 ; iorsi3 instruction pattern(s).
4560 (define_insn "*iorsi3_cc"
4562 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4563 (match_operand:SI 2 "general_operand" "d,m"))
4565 (set (match_operand:SI 0 "register_operand" "=d,d")
4566 (ior:SI (match_dup 1) (match_dup 2)))]
4567 "s390_match_ccmode(insn, CCTmode)"
4571 [(set_attr "op_type" "RR,RX")
4572 (set_attr "atype" "reg,mem")])
4574 (define_insn "*iorsi3_cconly"
4576 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4577 (match_operand:SI 2 "general_operand" "d,m"))
4579 (clobber (match_scratch:SI 0 "=d,d"))]
4580 "s390_match_ccmode(insn, CCTmode)"
4584 [(set_attr "op_type" "RR,RX")
4585 (set_attr "atype" "reg,mem")])
4587 (define_insn "*iorsi3_oi"
4588 [(set (match_operand:SI 0 "register_operand" "=d")
4589 (ior:SI (match_operand:SI 1 "register_operand" "%0")
4590 (match_operand:SI 2 "immediate_operand" "n")))
4591 (clobber (reg:CC 33))]
4592 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4595 int part = s390_single_hi (operands[2], SImode, 0);
4596 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4600 case 0: return \"oilh\\t%0,%x2\";
4601 case 1: return \"oill\\t%0,%x2\";
4605 [(set_attr "op_type" "RI")
4606 (set_attr "atype" "reg")])
4608 (define_insn "iorsi3"
4609 [(set (match_operand:SI 0 "register_operand" "=d,d")
4610 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4611 (match_operand:SI 2 "general_operand" "d,m")))
4612 (clobber (reg:CC 33))]
4617 [(set_attr "op_type" "RR,RX")
4618 (set_attr "atype" "reg,mem")])
4620 (define_insn "*iorsi3_ss"
4621 [(set (match_operand:SI 0 "s_operand" "=Qo")
4622 (ior:SI (match_dup 0)
4623 (match_operand:SI 1 "s_imm_operand" "Qo")))
4624 (clobber (reg:CC 33))]
4626 "oc\\t%O0(4,%R0),%1"
4627 [(set_attr "op_type" "SS")
4628 (set_attr "atype" "mem")])
4630 (define_insn "*iorsi3_ss_inv"
4631 [(set (match_operand:SI 0 "s_operand" "=Qo")
4632 (ior:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4634 (clobber (reg:CC 33))]
4636 "oc\\t%O0(4,%R0),%1"
4637 [(set_attr "op_type" "SS")
4638 (set_attr "atype" "mem")])
4641 ; iorhi3 instruction pattern(s).
4644 (define_insn "*iorhi3_oi"
4645 [(set (match_operand:HI 0 "register_operand" "=d,d")
4646 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4647 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4648 (clobber (reg:CC 33))]
4653 [(set_attr "op_type" "RR,RI")
4654 (set_attr "atype" "reg")])
4656 (define_insn "iorhi3"
4657 [(set (match_operand:HI 0 "register_operand" "=d")
4658 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4659 (match_operand:HI 2 "nonmemory_operand" "d")))
4660 (clobber (reg:CC 33))]
4663 [(set_attr "op_type" "RR")
4664 (set_attr "atype" "reg")])
4666 (define_insn "*iorhi3_ss"
4667 [(set (match_operand:HI 0 "s_operand" "=Qo")
4668 (ior:HI (match_dup 0)
4669 (match_operand:HI 1 "s_imm_operand" "Qo")))
4670 (clobber (reg:CC 33))]
4672 "oc\\t%O0(2,%R0),%1"
4673 [(set_attr "op_type" "SS")
4674 (set_attr "atype" "mem")])
4676 (define_insn "*iorhi3_ss_inv"
4677 [(set (match_operand:HI 0 "s_operand" "=Qo")
4678 (ior:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4680 (clobber (reg:CC 33))]
4682 "oc\\t%O0(2,%R0),%1"
4683 [(set_attr "op_type" "SS")
4684 (set_attr "atype" "mem")])
4687 ; iorqi3 instruction pattern(s).
4690 (define_insn "*iorqi3_oi"
4691 [(set (match_operand:QI 0 "register_operand" "=d,d")
4692 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4693 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4694 (clobber (reg:CC 33))]
4699 [(set_attr "op_type" "RR,RI")
4700 (set_attr "atype" "reg")])
4702 (define_insn "iorqi3"
4703 [(set (match_operand:QI 0 "register_operand" "=d")
4704 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4705 (match_operand:QI 2 "nonmemory_operand" "d")))
4706 (clobber (reg:CC 33))]
4709 [(set_attr "op_type" "RR")
4710 (set_attr "atype" "reg")])
4712 (define_insn "*iorqi3_ss"
4713 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4714 (ior:QI (match_dup 0)
4715 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4716 (clobber (reg:CC 33))]
4721 [(set_attr "op_type" "SI,SS")
4722 (set_attr "atype" "reg,mem")])
4724 (define_insn "*iorqi3_ss_inv"
4725 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4726 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4728 (clobber (reg:CC 33))]
4733 [(set_attr "op_type" "SI,SS")
4734 (set_attr "atype" "reg,mem")])
4738 ;;- Xor instructions.
4742 ; xordi3 instruction pattern(s).
4745 (define_insn "*xordi3_cc"
4747 (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4748 (match_operand:DI 2 "general_operand" "d,m"))
4750 (set (match_operand:DI 0 "register_operand" "=d,d")
4751 (xor:DI (match_dup 1) (match_dup 2)))]
4752 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4756 [(set_attr "op_type" "RRE,RXE")
4757 (set_attr "atype" "reg,mem")])
4759 (define_insn "*xordi3_cconly"
4761 (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4762 (match_operand:DI 2 "general_operand" "d,m"))
4764 (clobber (match_scratch:DI 0 "=d,d"))]
4765 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4769 [(set_attr "op_type" "RRE,RXE")
4770 (set_attr "atype" "reg,mem")])
4772 (define_insn "xordi3"
4773 [(set (match_operand:DI 0 "register_operand" "=d,d")
4774 (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4775 (match_operand:DI 2 "general_operand" "d,m")))
4776 (clobber (reg:CC 33))]
4781 [(set_attr "op_type" "RRE,RXE")
4782 (set_attr "atype" "reg,mem")])
4784 (define_insn "*xordi3_ss"
4785 [(set (match_operand:DI 0 "s_operand" "=Qo")
4786 (xor:DI (match_dup 0)
4787 (match_operand:DI 1 "s_imm_operand" "Qo")))
4788 (clobber (reg:CC 33))]
4790 "xc\\t%O0(8,%R0),%1"
4791 [(set_attr "op_type" "SS")
4792 (set_attr "atype" "mem")])
4794 (define_insn "*xordi3_ss_inv"
4795 [(set (match_operand:DI 0 "s_operand" "=Qo")
4796 (xor:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4798 (clobber (reg:CC 33))]
4800 "xc\\t%O0(8,%R0),%1"
4801 [(set_attr "op_type" "SS")
4802 (set_attr "atype" "mem")])
4805 ; xorsi3 instruction pattern(s).
4808 (define_insn "*xorsi3_cc"
4810 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4811 (match_operand:SI 2 "general_operand" "d,m"))
4813 (set (match_operand:SI 0 "register_operand" "=d,d")
4814 (xor:SI (match_dup 1) (match_dup 2)))]
4815 "s390_match_ccmode(insn, CCTmode)"
4819 [(set_attr "op_type" "RR,RX")
4820 (set_attr "atype" "reg,mem")])
4822 (define_insn "*xorsi3_cconly"
4824 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4825 (match_operand:SI 2 "general_operand" "d,m"))
4827 (clobber (match_scratch:SI 0 "=d,d"))]
4828 "s390_match_ccmode(insn, CCTmode)"
4832 [(set_attr "op_type" "RR,RX")
4833 (set_attr "atype" "reg,mem")])
4835 (define_insn "xorsi3"
4836 [(set (match_operand:SI 0 "register_operand" "=d,d")
4837 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4838 (match_operand:SI 2 "general_operand" "d,m")))
4839 (clobber (reg:CC 33))]
4844 [(set_attr "op_type" "RR,RX")
4845 (set_attr "atype" "reg,mem")])
4847 (define_insn "*xorsi3_ss"
4848 [(set (match_operand:SI 0 "s_operand" "=Qo")
4849 (xor:SI (match_dup 0)
4850 (match_operand:SI 1 "s_imm_operand" "Qo")))
4851 (clobber (reg:CC 33))]
4853 "xc\\t%O0(4,%R0),%1"
4854 [(set_attr "op_type" "SS")
4855 (set_attr "atype" "mem")])
4857 (define_insn "*xorsi3_ss_inv"
4858 [(set (match_operand:SI 0 "s_operand" "=Qo")
4859 (xor:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4861 (clobber (reg:CC 33))]
4863 "xc\\t%O0(4,%R0),%1"
4864 [(set_attr "op_type" "SS")
4865 (set_attr "atype" "mem")])
4868 ; xorhi3 instruction pattern(s).
4871 (define_insn "xorhi3"
4872 [(set (match_operand:HI 0 "register_operand" "=d")
4873 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4874 (match_operand:HI 2 "nonmemory_operand" "d")))
4875 (clobber (reg:CC 33))]
4878 [(set_attr "op_type" "RR")
4879 (set_attr "atype" "reg")])
4881 (define_insn "*xorhi3_ss"
4882 [(set (match_operand:HI 0 "s_operand" "=Qo")
4883 (xor:HI (match_dup 0)
4884 (match_operand:HI 1 "s_imm_operand" "Qo")))
4885 (clobber (reg:CC 33))]
4887 "xc\\t%O0(2,%R0),%1"
4888 [(set_attr "op_type" "SS")
4889 (set_attr "atype" "mem")])
4891 (define_insn "*xorhi3_ss_inv"
4892 [(set (match_operand:HI 0 "s_operand" "=Qo")
4893 (xor:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4895 (clobber (reg:CC 33))]
4897 "xc\\t%O0(2,%R0),%1"
4898 [(set_attr "op_type" "SS")
4899 (set_attr "atype" "mem")])
4902 ; xorqi3 instruction pattern(s).
4905 (define_insn "xorqi3"
4906 [(set (match_operand:QI 0 "register_operand" "=d")
4907 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4908 (match_operand:QI 2 "nonmemory_operand" "d")))
4909 (clobber (reg:CC 33))]
4912 [(set_attr "op_type" "RR")
4913 (set_attr "atype" "reg")])
4915 (define_insn "*xorqi3_ss"
4916 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4917 (xor:QI (match_dup 0)
4918 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4919 (clobber (reg:CC 33))]
4924 [(set_attr "op_type" "SI,SS")
4925 (set_attr "atype" "mem")])
4927 (define_insn "*xorqi3_ss_inv"
4928 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4929 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4931 (clobber (reg:CC 33))]
4936 [(set_attr "op_type" "SI,SS")
4937 (set_attr "atype" "mem")])
4941 ;;- Negate instructions.
4945 ; negdi2 instruction pattern(s).
4948 (define_expand "negdi2"
4950 [(set (match_operand:DI 0 "register_operand" "=d")
4951 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4952 (clobber (reg:CC 33))])]
4956 (define_insn "*negdi2_64"
4957 [(set (match_operand:DI 0 "register_operand" "=d")
4958 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4959 (clobber (reg:CC 33))]
4962 [(set_attr "op_type" "RR")])
4964 (define_insn "*negdi2_31"
4965 [(set (match_operand:DI 0 "register_operand" "=d")
4966 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4967 (clobber (reg:CC 33))]
4972 xop[0] = gen_label_rtx ();
4973 output_asm_insn (\"lcr\\t%0,%1\", operands);
4974 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
4975 output_asm_insn (\"je\\t%l0\", xop);
4976 output_asm_insn (\"bctr\\t%0,0\", operands);
4977 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4978 CODE_LABEL_NUMBER (xop[0]));
4981 [(set_attr "op_type" "NN")
4982 (set_attr "type" "other")
4983 (set_attr "length" "10")])
4986 ; negsi2 instruction pattern(s).
4989 (define_insn "negsi2"
4990 [(set (match_operand:SI 0 "register_operand" "=d")
4991 (neg:SI (match_operand:SI 1 "register_operand" "d")))
4992 (clobber (reg:CC 33))]
4995 [(set_attr "op_type" "RR")])
4998 ; negdf2 instruction pattern(s).
5001 (define_expand "negdf2"
5003 [(set (match_operand:DF 0 "register_operand" "=f")
5004 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5005 (clobber (reg:CC 33))])]
5009 (define_insn "*negdf2"
5010 [(set (match_operand:DF 0 "register_operand" "=f")
5011 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5012 (clobber (reg:CC 33))]
5013 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5015 [(set_attr "op_type" "RRE")])
5017 (define_insn "*negdf2_ibm"
5018 [(set (match_operand:DF 0 "register_operand" "=f")
5019 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5020 (clobber (reg:CC 33))]
5021 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5023 [(set_attr "op_type" "RR")])
5026 ; negsf2 instruction pattern(s).
5029 (define_expand "negsf2"
5031 [(set (match_operand:SF 0 "register_operand" "=f")
5032 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5033 (clobber (reg:CC 33))])]
5037 (define_insn "*negsf2"
5038 [(set (match_operand:SF 0 "register_operand" "=f")
5039 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5040 (clobber (reg:CC 33))]
5041 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5043 [(set_attr "op_type" "RRE")])
5045 (define_insn "*negsf2"
5046 [(set (match_operand:SF 0 "register_operand" "=f")
5047 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5048 (clobber (reg:CC 33))]
5049 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5051 [(set_attr "op_type" "RR")])
5055 ;;- Absolute value instructions.
5059 ; absdi2 instruction pattern(s).
5062 (define_insn "absdi2"
5063 [(set (match_operand:DI 0 "register_operand" "=d")
5064 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5065 (clobber (reg:CC 33))]
5068 [(set_attr "op_type" "RRE")])
5071 ; abssi2 instruction pattern(s).
5074 (define_insn "abssi2"
5075 [(set (match_operand:SI 0 "register_operand" "=d")
5076 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5077 (clobber (reg:CC 33))]
5080 [(set_attr "op_type" "RR")])
5083 ; absdf2 instruction pattern(s).
5086 (define_expand "absdf2"
5088 [(set (match_operand:DF 0 "register_operand" "=f")
5089 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5090 (clobber (reg:CC 33))])]
5094 (define_insn "*absdf2"
5095 [(set (match_operand:DF 0 "register_operand" "=f")
5096 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5097 (clobber (reg:CC 33))]
5098 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5100 [(set_attr "op_type" "RRE")])
5102 (define_insn "*absdf2_ibm"
5103 [(set (match_operand:DF 0 "register_operand" "=f")
5104 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5105 (clobber (reg:CC 33))]
5106 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5108 [(set_attr "op_type" "RR")])
5111 ; abssf2 instruction pattern(s).
5114 (define_expand "abssf2"
5116 [(set (match_operand:SF 0 "register_operand" "=f")
5117 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5118 (clobber (reg:CC 33))])]
5122 (define_insn "*abssf2"
5123 [(set (match_operand:SF 0 "register_operand" "=f")
5124 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5125 (clobber (reg:CC 33))]
5126 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5128 [(set_attr "op_type" "RRE")])
5130 (define_insn "*abssf2_ibm"
5131 [(set (match_operand:SF 0 "register_operand" "=f")
5132 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5133 (clobber (reg:CC 33))]
5134 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5136 [(set_attr "op_type" "RR")])
5139 ;;- Square root instructions.
5143 ; sqrtdf2 instruction pattern(s).
5146 (define_insn "sqrtdf2"
5147 [(set (match_operand:DF 0 "register_operand" "=f,f")
5148 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5149 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5153 [(set_attr "op_type" "RRE,RSE")])
5156 ; sqrtsf2 instruction pattern(s).
5159 (define_insn "sqrtsf2"
5160 [(set (match_operand:SF 0 "register_operand" "=f,f")
5161 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5162 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5166 [(set_attr "op_type" "RRE,RSE")])
5169 ;;- One complement instructions.
5173 ; one_cmpldi2 instruction pattern(s).
5176 (define_expand "one_cmpldi2"
5178 [(set (match_operand:DI 0 "register_operand" "")
5179 (xor:DI (match_operand:DI 1 "register_operand" "")
5181 (clobber (reg:CC 33))])]
5186 ; one_cmplsi2 instruction pattern(s).
5189 (define_expand "one_cmplsi2"
5191 [(set (match_operand:SI 0 "register_operand" "")
5192 (xor:SI (match_operand:SI 1 "register_operand" "")
5194 (clobber (reg:CC 33))])]
5199 ; one_cmplhi2 instruction pattern(s).
5202 (define_expand "one_cmplhi2"
5204 [(set (match_operand:HI 0 "register_operand" "")
5205 (xor:HI (match_operand:HI 1 "register_operand" "")
5207 (clobber (reg:CC 33))])]
5212 ; one_cmplqi2 instruction pattern(s).
5215 (define_expand "one_cmplqi2"
5217 [(set (match_operand:QI 0 "register_operand" "")
5218 (xor:QI (match_operand:QI 1 "register_operand" "")
5220 (clobber (reg:CC 33))])]
5226 ;;- Rotate instructions.
5230 ; rotldi3 instruction pattern(s).
5233 (define_insn "rotldi3"
5234 [(set (match_operand:DI 0 "register_operand" "=d,d")
5235 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5236 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5241 [(set_attr "op_type" "RSE")])
5244 ; rotlsi3 instruction pattern(s).
5247 (define_insn "rotlsi3"
5248 [(set (match_operand:SI 0 "register_operand" "=d,d")
5249 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5250 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5255 [(set_attr "op_type" "RSE")])
5259 ;;- Arithmetic shift instructions.
5263 ; ashldi3 instruction pattern(s).
5266 (define_expand "ashldi3"
5267 [(set (match_operand:DI 0 "register_operand" "")
5268 (ashift:DI (match_operand:DI 1 "register_operand" "")
5269 (match_operand:SI 2 "nonmemory_operand" "")))]
5273 (define_insn "*ashldi3_31"
5274 [(set (match_operand:DI 0 "register_operand" "=d,d")
5275 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5276 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5281 [(set_attr "op_type" "RS")])
5283 (define_insn "*ashldi3_64"
5284 [(set (match_operand:DI 0 "register_operand" "=d,d")
5285 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5286 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5291 [(set_attr "op_type" "RSE")])
5294 ; ashrdi3 instruction pattern(s).
5297 (define_expand "ashrdi3"
5299 [(set (match_operand:DI 0 "register_operand" "")
5300 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5301 (match_operand:SI 2 "nonmemory_operand" "")))
5302 (clobber (reg:CC 33))])]
5306 (define_insn "*ashrdi3_cc_31"
5308 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5309 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5311 (set (match_operand:DI 0 "register_operand" "=d,d")
5312 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5313 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5317 [(set_attr "op_type" "RS")])
5319 (define_insn "*ashrdi3_cconly_31"
5321 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5322 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5324 (clobber (match_scratch:DI 0 "=d,d"))]
5325 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5329 [(set_attr "op_type" "RS")])
5331 (define_insn "*ashrdi3_31"
5332 [(set (match_operand:DI 0 "register_operand" "=d,d")
5333 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5334 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5335 (clobber (reg:CC 33))]
5340 [(set_attr "op_type" "RS")])
5342 (define_insn "*ashrdi3_cc_64"
5344 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5345 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5347 (set (match_operand:DI 0 "register_operand" "=d,d")
5348 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5349 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5353 [(set_attr "op_type" "RSE")])
5355 (define_insn "*ashrdi3_cconly_64"
5357 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5358 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5360 (clobber (match_scratch:DI 0 "=d,d"))]
5361 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5365 [(set_attr "op_type" "RSE")])
5367 (define_insn "*ashrdi3_64"
5368 [(set (match_operand:DI 0 "register_operand" "=d,d")
5369 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5370 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5371 (clobber (reg:CC 33))]
5376 [(set_attr "op_type" "RSE")])
5379 ; ashlsi3 instruction pattern(s).
5382 (define_insn "ashlsi3"
5383 [(set (match_operand:SI 0 "register_operand" "=d,d")
5384 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5385 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5390 [(set_attr "op_type" "RS")])
5393 ; ashrsi3 instruction pattern(s).
5396 (define_insn "*ashrsi3_cc"
5398 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5399 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5401 (set (match_operand:SI 0 "register_operand" "=d,d")
5402 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5403 "s390_match_ccmode(insn, CCSmode)"
5407 [(set_attr "op_type" "RS")])
5409 (define_insn "*ashrsi3_cconly"
5411 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5412 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5414 (clobber (match_scratch:SI 0 "=d,d"))]
5415 "s390_match_ccmode(insn, CCSmode)"
5419 [(set_attr "op_type" "RS")])
5421 (define_insn "ashrsi3"
5422 [(set (match_operand:SI 0 "register_operand" "=d,d")
5423 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5424 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5425 (clobber (reg:CC 33))]
5430 [(set_attr "op_type" "RS")])
5434 ;;- logical shift instructions.
5438 ; lshrdi3 instruction pattern(s).
5441 (define_expand "lshrdi3"
5442 [(set (match_operand:DI 0 "register_operand" "")
5443 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5444 (match_operand:SI 2 "nonmemory_operand" "")))]
5448 (define_insn "*lshrdi3_31"
5449 [(set (match_operand:DI 0 "register_operand" "=d,d")
5450 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5451 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5456 [(set_attr "op_type" "RS,RS")])
5458 (define_insn "*lshrdi3_64"
5459 [(set (match_operand:DI 0 "register_operand" "=d,d")
5460 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5461 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5466 [(set_attr "op_type" "RS,RS")])
5469 ; lshrsi3 instruction pattern(s).
5472 (define_insn "lshrsi3"
5473 [(set (match_operand:SI 0 "register_operand" "=d,d")
5474 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5475 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5480 [(set_attr "op_type" "RS")])
5484 ;; Branch instruction patterns.
5487 (define_expand "beq"
5488 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5490 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5491 (label_ref (match_operand 0 "" ""))
5494 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5496 (define_expand "bne"
5497 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5499 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5500 (label_ref (match_operand 0 "" ""))
5503 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5505 (define_expand "bgt"
5506 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5508 (if_then_else (gt (reg:CCS 33) (const_int 0))
5509 (label_ref (match_operand 0 "" ""))
5512 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5514 (define_expand "bgtu"
5515 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5517 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5518 (label_ref (match_operand 0 "" ""))
5521 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5523 (define_expand "blt"
5524 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5526 (if_then_else (lt (reg:CCS 33) (const_int 0))
5527 (label_ref (match_operand 0 "" ""))
5530 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5532 (define_expand "bltu"
5533 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5535 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5536 (label_ref (match_operand 0 "" ""))
5539 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5541 (define_expand "bge"
5542 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5544 (if_then_else (ge (reg:CCS 33) (const_int 0))
5545 (label_ref (match_operand 0 "" ""))
5548 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5550 (define_expand "bgeu"
5551 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5553 (if_then_else (geu (reg:CCU 33) (const_int 0))
5554 (label_ref (match_operand 0 "" ""))
5557 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5559 (define_expand "ble"
5560 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5562 (if_then_else (le (reg:CCS 33) (const_int 0))
5563 (label_ref (match_operand 0 "" ""))
5566 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5568 (define_expand "bleu"
5569 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5571 (if_then_else (leu (reg:CCU 33) (const_int 0))
5572 (label_ref (match_operand 0 "" ""))
5575 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5577 (define_expand "bunordered"
5578 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5580 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5581 (label_ref (match_operand 0 "" ""))
5584 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5586 (define_expand "bordered"
5587 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5589 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5590 (label_ref (match_operand 0 "" ""))
5593 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5595 (define_expand "buneq"
5596 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5598 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5599 (label_ref (match_operand 0 "" ""))
5602 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5604 (define_expand "bungt"
5605 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5607 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5608 (label_ref (match_operand 0 "" ""))
5611 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5613 (define_expand "bunlt"
5614 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5616 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5617 (label_ref (match_operand 0 "" ""))
5620 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5622 (define_expand "bunge"
5623 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5625 (if_then_else (unge (reg:CCS 33) (const_int 0))
5626 (label_ref (match_operand 0 "" ""))
5629 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5631 (define_expand "bunle"
5632 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5634 (if_then_else (unle (reg:CCS 33) (const_int 0))
5635 (label_ref (match_operand 0 "" ""))
5638 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5640 (define_expand "bltgt"
5641 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5643 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5644 (label_ref (match_operand 0 "" ""))
5647 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5651 ;;- Conditional jump instructions.
5654 (define_insn "cjump"
5657 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5658 (label_ref (match_operand 0 "" ""))
5663 if (get_attr_length (insn) == 4)
5664 return \"j%C1\\t%l0\";
5665 else if (TARGET_64BIT)
5666 return \"jg%C1\\t%l0\";
5670 [(set_attr "op_type" "RI")
5671 (set (attr "length")
5672 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5674 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5676 (eq (symbol_ref "flag_pic") (const_int 0))
5677 (const_int 6)] (const_int 8)))])
5679 (define_insn "*cjump_long"
5682 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5683 (match_operand 0 "address_operand" "p")
5688 if (get_attr_op_type (insn) == OP_TYPE_RR)
5689 return \"b%C1r\\t%0\";
5691 return \"b%C1\\t%a0\";
5693 [(set (attr "op_type")
5694 (if_then_else (match_operand 0 "register_operand" "")
5695 (const_string "RR") (const_string "RX")))
5696 (set_attr "atype" "mem")])
5700 ;;- Negated conditional jump instructions.
5703 (define_insn "icjump"
5706 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5708 (label_ref (match_operand 0 "" ""))))]
5712 if (get_attr_length (insn) == 4)
5713 return \"j%D1\\t%l0\";
5714 else if (TARGET_64BIT)
5715 return \"jg%D1\\t%l0\";
5719 [(set_attr "op_type" "RI")
5720 (set (attr "length")
5721 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5723 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5725 (eq (symbol_ref "flag_pic") (const_int 0))
5726 (const_int 6)] (const_int 8)))])
5728 (define_insn "*icjump_long"
5731 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5733 (match_operand 0 "address_operand" "p")))]
5737 if (get_attr_op_type (insn) == OP_TYPE_RR)
5738 return \"b%D1r\\t%0\";
5740 return \"b%D1\\t%a0\";
5742 [(set (attr "op_type")
5743 (if_then_else (match_operand 0 "register_operand" "")
5744 (const_string "RR") (const_string "RX")))
5745 (set_attr "atype" "mem")])
5749 ;;- Subtract one and jump if not zero.
5752 ;(define_expand "decrement_and_branch_on_count"
5753 ; [(use (match_operand 0 "register_operand" ""))
5754 ; (use (label_ref (match_operand 1 "" "")))]
5758 ;/* if (TARGET_64BIT)
5759 ; emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5761 ; emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5765 ;(define_insn "brctsi"
5768 ; (ne (match_operand:SI 0 "register_operand" "+a")
5770 ; (label_ref (match_operand 1 "" ""))
5772 ; (set (match_dup 0)
5773 ; (plus:SI (match_dup 0) (const_int -1)))]
5776 ; [(set_attr "op_type" "RI")
5777 ; (set_attr "type" "branch")]
5780 ;(define_insn "ibrctsi"
5783 ; (eq (match_operand:SI 0 "register_operand" "+a")
5786 ; (label_ref (match_operand 1 "" ""))))
5787 ; (set (match_dup 0)
5788 ; (plus:SI (match_dup 0) (const_int -1)))]
5791 ; [(set_attr "op_type" "RI")
5792 ; (set_attr "type" "branch")]
5797 ;;- Unconditional jump instructions.
5801 ; jump instruction pattern(s).
5805 [(set (pc) (label_ref (match_operand 0 "" "")))]
5809 if (get_attr_length (insn) == 4)
5811 else if (TARGET_64BIT)
5812 return \"jg\\t%l0\";
5816 [(set_attr "op_type" "RI")
5817 (set (attr "length")
5818 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5820 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5822 (eq (symbol_ref "flag_pic") (const_int 0))
5823 (const_int 6)] (const_int 8)))])
5826 ; indirect-jump instruction pattern(s).
5829 (define_insn "indirect_jump"
5830 [(set (pc) (match_operand 0 "address_operand" "p"))]
5834 if (get_attr_op_type (insn) == OP_TYPE_RR)
5839 [(set (attr "op_type")
5840 (if_then_else (match_operand 0 "register_operand" "")
5841 (const_string "RR") (const_string "RX")))
5842 (set_attr "atype" "mem")])
5845 ; casesi instruction pattern(s).
5848 (define_insn "casesi_jump"
5849 [(set (pc) (match_operand 0 "address_operand" "p"))
5850 (use (label_ref (match_operand 1 "" "")))]
5854 if (get_attr_op_type (insn) == OP_TYPE_RR)
5859 [(set (attr "op_type")
5860 (if_then_else (match_operand 0 "register_operand" "")
5861 (const_string "RR") (const_string "RX")))
5862 (set_attr "atype" "mem")])
5864 (define_expand "casesi"
5865 [(match_operand:SI 0 "general_operand" "")
5866 (match_operand:SI 1 "general_operand" "")
5867 (match_operand:SI 2 "general_operand" "")
5868 (label_ref (match_operand 3 "" ""))
5869 (label_ref (match_operand 4 "" ""))]
5873 rtx index = gen_reg_rtx (SImode);
5874 rtx base = gen_reg_rtx (Pmode);
5875 rtx target = gen_reg_rtx (Pmode);
5877 emit_move_insn (index, operands[0]);
5878 emit_insn (gen_subsi3 (index, index, operands[1]));
5879 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
5882 if (Pmode != SImode)
5883 index = convert_to_mode (Pmode, index, 1);
5884 if (GET_CODE (index) != REG)
5885 index = copy_to_mode_reg (Pmode, index);
5888 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
5890 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
5892 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
5894 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
5895 emit_move_insn (target, index);
5898 target = gen_rtx_PLUS (Pmode, base, target);
5899 emit_jump_insn (gen_casesi_jump (target, operands[3]));
5906 ;;- Jump to subroutine.
5911 ; untyped call instruction pattern(s).
5914 ;; Call subroutine returning any type.
5915 (define_expand "untyped_call"
5916 [(parallel [(call (match_operand 0 "" "")
5918 (match_operand 1 "" "")
5919 (match_operand 2 "" "")])]
5925 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
5927 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5929 rtx set = XVECEXP (operands[2], 0, i);
5930 emit_move_insn (SET_DEST (set), SET_SRC (set));
5933 /* The optimizer does not know that the call sets the function value
5934 registers we stored in the result block. We avoid problems by
5935 claiming that all hard registers are used and clobbered at this
5937 emit_insn (gen_blockage ());
5942 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5943 ;; all of memory. This blocks insns from being moved across this point.
5945 (define_insn "blockage"
5946 [(unspec_volatile [(const_int 0)] 0)]
5949 [(set_attr "type" "none")])
5954 ; call instruction pattern(s).
5957 (define_expand "call"
5958 [(call (match_operand 0 "" "")
5959 (match_operand 1 "" ""))
5960 (use (match_operand 2 "" ""))]
5967 /* Direct function calls need special treatment. */
5968 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5970 rtx sym = XEXP (operands[0], 0);
5972 /* When calling a global routine in PIC mode, we must
5973 replace the symbol itself with the PLT stub. */
5974 if (flag_pic && !SYMBOL_REF_FLAG (sym))
5976 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5977 sym = gen_rtx_CONST (Pmode, sym);
5982 /* Unless we can use the bras(l) insn, force the
5983 routine address into a register. */
5984 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
5986 rtx target = gen_reg_rtx (Pmode);
5987 emit_move_insn (target, sym);
5991 operands[0] = gen_rtx_MEM (QImode, sym);
5995 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
5996 gen_rtx_REG (Pmode, RETURN_REGNUM)));
5998 /* In 31-bit, we must load the GOT register even if the
5999 compiler doesn't know about it, because the PLT glue
6000 code uses it. In 64-bit, this is not necessary. */
6001 if (plt_call && !TARGET_64BIT)
6003 current_function_uses_pic_offset_table = 1;
6004 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6010 (define_expand "call_exp"
6011 [(parallel [(call (match_operand 0 "" "")
6012 (match_operand 1 "" ""))
6013 (clobber (match_operand 2 "" ""))])]
6017 (define_insn "brasl"
6018 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6019 (match_operand:SI 1 "const_int_operand" "n"))
6020 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6023 [(set_attr "op_type" "RIL")
6024 (set_attr "type" "jsr")])
6027 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6028 (match_operand:SI 1 "const_int_operand" "n"))
6029 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6032 [(set_attr "op_type" "RI")
6033 (set_attr "type" "jsr")])
6035 (define_insn "basr_64"
6036 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6037 (match_operand:SI 1 "const_int_operand" "n"))
6038 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6041 [(set_attr "op_type" "RR")
6042 (set_attr "type" "jsr")
6043 (set_attr "atype" "mem")])
6045 (define_insn "basr_31"
6046 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6047 (match_operand:SI 1 "const_int_operand" "n"))
6048 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6051 [(set_attr "op_type" "RR")
6052 (set_attr "type" "jsr")
6053 (set_attr "atype" "mem")])
6055 (define_insn "bas_64"
6056 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6057 (match_operand:SI 1 "const_int_operand" "n"))
6058 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6061 [(set_attr "op_type" "RX")
6062 (set_attr "type" "jsr")
6063 (set_attr "atype" "mem")])
6065 (define_insn "bas_31"
6066 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6067 (match_operand:SI 1 "const_int_operand" "n"))
6068 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6071 [(set_attr "op_type" "RX")
6072 (set_attr "type" "jsr")
6073 (set_attr "atype" "mem")])
6077 ; call_value instruction pattern(s).
6080 (define_expand "call_value"
6081 [(set (match_operand 0 "" "")
6082 (call (match_operand 1 "" "")
6083 (match_operand 2 "" "")))
6084 (use (match_operand 3 "" ""))]
6091 /* Direct function calls need special treatment. */
6092 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6094 rtx sym = XEXP (operands[1], 0);
6096 /* When calling a global routine in PIC mode, we must
6097 replace the symbol itself with the PLT stub. */
6098 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6100 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6101 sym = gen_rtx_CONST (Pmode, sym);
6106 /* Unless we can use the bras(l) insn, force the
6107 routine address into a register. */
6108 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6110 rtx target = gen_reg_rtx (Pmode);
6111 emit_move_insn (target, sym);
6115 operands[1] = gen_rtx_MEM (QImode, sym);
6119 insn = emit_call_insn (
6120 gen_call_value_exp (operands[0], operands[1], operands[2],
6121 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6123 /* In 31-bit, we must load the GOT register even if the
6124 compiler doesn't know about it, because the PLT glue
6125 code uses it. In 64-bit, this is not necessary. */
6126 if (plt_call && !TARGET_64BIT)
6128 current_function_uses_pic_offset_table = 1;
6129 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6135 (define_expand "call_value_exp"
6136 [(parallel [(set (match_operand 0 "" "")
6137 (call (match_operand 1 "" "")
6138 (match_operand 2 "" "")))
6139 (clobber (match_operand 3 "" ""))])]
6143 (define_insn "brasl_r"
6144 [(set (match_operand 0 "register_operand" "=df")
6145 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6146 (match_operand:SI 2 "const_int_operand" "n")))
6147 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6150 [(set_attr "op_type" "RIL")
6151 (set_attr "type" "jsr")])
6153 (define_insn "bras_r"
6154 [(set (match_operand 0 "register_operand" "=df")
6155 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6156 (match_operand:SI 2 "const_int_operand" "n")))
6157 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6160 [(set_attr "op_type" "RI")
6161 (set_attr "type" "jsr")])
6163 (define_insn "basr_r_64"
6164 [(set (match_operand 0 "register_operand" "=df")
6165 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6166 (match_operand:SI 2 "const_int_operand" "n")))
6167 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6170 [(set_attr "op_type" "RR")
6171 (set_attr "type" "jsr")])
6173 (define_insn "basr_r_31"
6174 [(set (match_operand 0 "register_operand" "=df")
6175 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6176 (match_operand:SI 2 "const_int_operand" "n")))
6177 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6180 [(set_attr "op_type" "RR")
6181 (set_attr "type" "jsr")
6182 (set_attr "atype" "mem")])
6184 (define_insn "bas_r_64"
6185 [(set (match_operand 0 "register_operand" "=df")
6186 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6187 (match_operand:SI 2 "const_int_operand" "n")))
6188 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6191 [(set_attr "op_type" "RX")
6192 (set_attr "type" "jsr")
6193 (set_attr "atype" "mem")])
6195 (define_insn "bas_r_31"
6196 [(set (match_operand 0 "register_operand" "=df")
6197 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6198 (match_operand:SI 2 "const_int_operand" "n")))
6199 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6202 [(set_attr "op_type" "RX")
6203 (set_attr "type" "jsr")
6204 (set_attr "atype" "mem")])
6208 ;;- Miscellaneous instructions.
6212 ; allocate stack instruction pattern(s).
6215 (define_expand "allocate_stack"
6217 (plus (reg 15) (match_operand 1 "general_operand" "")))
6218 (set (match_operand 0 "general_operand" "")
6223 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6224 rtx chain = gen_rtx (MEM, Pmode, stack);
6225 rtx temp = gen_reg_rtx (Pmode);
6227 emit_move_insn (temp, chain);
6230 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6232 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6234 emit_move_insn (chain, temp);
6236 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6242 ; setjmp/longjmp instruction pattern(s).
6245 (define_expand "builtin_setjmp_setup"
6246 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6250 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6251 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6253 emit_move_insn (base, basereg);
6257 (define_expand "builtin_setjmp_receiver"
6258 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6262 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6263 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6264 SYMBOL_REF_FLAG (got) = 1;
6266 emit_move_insn (gotreg, got);
6267 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6271 (define_expand "builtin_longjmp"
6272 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6276 /* The elements of the buffer are, in order: */
6277 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6278 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6279 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6280 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6281 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6282 rtx jmp = gen_rtx_REG (Pmode, 14);
6284 emit_move_insn (jmp, lab);
6285 emit_move_insn (basereg, base);
6286 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6287 emit_move_insn (hard_frame_pointer_rtx, fp);
6289 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6290 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6291 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6292 emit_indirect_jump (jmp);
6297 ;; These patterns say how to save and restore the stack pointer. We need not
6298 ;; save the stack pointer at function level since we are careful to
6299 ;; preserve the backchain. At block level, we have to restore the backchain
6300 ;; when we restore the stack pointer.
6302 ;; For nonlocal gotos, we must save both the stack pointer and its
6303 ;; backchain and restore both. Note that in the nonlocal case, the
6304 ;; save area is a memory location.
6306 (define_expand "save_stack_function"
6307 [(match_operand 0 "general_operand" "")
6308 (match_operand 1 "general_operand" "")]
6312 (define_expand "restore_stack_function"
6313 [(match_operand 0 "general_operand" "")
6314 (match_operand 1 "general_operand" "")]
6318 (define_expand "restore_stack_block"
6319 [(use (match_operand 0 "register_operand" ""))
6320 (set (match_dup 2) (match_dup 3))
6321 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6322 (set (match_dup 3) (match_dup 2))]
6326 operands[2] = gen_reg_rtx (Pmode);
6327 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6330 (define_expand "save_stack_nonlocal"
6331 [(match_operand 0 "memory_operand" "")
6332 (match_operand 1 "register_operand" "")]
6336 rtx temp = gen_reg_rtx (Pmode);
6338 /* Copy the backchain to the first word, sp to the second. */
6339 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6340 emit_move_insn (operand_subword (operands[0], 0, 0,
6341 TARGET_64BIT ? TImode : DImode),
6343 emit_move_insn (operand_subword (operands[0], 1, 0,
6344 TARGET_64BIT ? TImode : DImode),
6349 (define_expand "restore_stack_nonlocal"
6350 [(match_operand 0 "register_operand" "")
6351 (match_operand 1 "memory_operand" "")]
6355 rtx temp = gen_reg_rtx (Pmode);
6357 /* Restore the backchain from the first word, sp from the second. */
6358 emit_move_insn (temp,
6359 operand_subword (operands[1], 0, 0,
6360 TARGET_64BIT ? TImode : DImode));
6361 emit_move_insn (operands[0],
6362 operand_subword (operands[1], 1, 0,
6363 TARGET_64BIT ? TImode : DImode));
6364 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6370 ; nop instruction pattern(s).
6377 [(set_attr "op_type" "RR")])
6381 ; Special literal pool access instruction pattern(s).
6384 (define_insn "reload_base"
6385 [(parallel [(set (reg 13) (pc))
6386 (use (label_ref (match_operand 0 "" "")))])]
6391 return \"larl\\t13,%y0\";
6393 return \"basr\\t13,0\;ahi\\t13,%Y0\";
6395 [(set_attr "op_type" "NN")
6396 (set_attr "type" "la")
6397 (set_attr "length" "8")])
6399 (define_insn "ltorg"
6400 [(parallel [(set (reg 13) (pc))
6401 (use (match_operand:SI 0 "const_int_operand" ""))])]
6405 s390_dump_literal_pool (insn, operands[0]);
6408 [(set_attr "op_type" "NN")
6409 (set_attr "type" "other")
6410 (set_attr "length" "4096")])
6413 ;; Insns related to generating the function prologue and epilogue.
6417 (define_expand "prologue"
6418 [(use (const_int 0))]
6422 s390_emit_prologue ();
6426 (define_expand "epilogue"
6427 [(use (const_int 1))]
6431 s390_emit_epilogue ();
6436 (define_insn "*return_si"
6438 (use (match_operand:SI 0 "register_operand" "a"))]
6441 [(set_attr "op_type" "RR")
6442 (set_attr "type" "jsr")
6443 (set_attr "atype" "mem")])
6445 (define_insn "*return_di"
6447 (use (match_operand:DI 0 "register_operand" "a"))]
6450 [(set_attr "op_type" "RR")
6451 (set_attr "type" "jsr")
6452 (set_attr "atype" "mem")])
6456 [(set (reg 13) (pc))
6457 (unspec_volatile [(const_int 0)] 200)]
6461 s390_output_constant_pool (asm_out_file);
6464 [(set_attr "op_type" "NN")
6465 (set_attr "type" "integer")])
6469 ;; Peephole optimization patterns.
6473 [(set (match_operand:SI 0 "memory_operand" "m")
6474 (match_operand:SI 1 "register_operand" "d"))
6481 [(set (match_operand:SI 0 "memory_operand" "m")
6482 (match_operand:SI 1 "register_operand" "d"))
6489 [(set (match_operand:SI 0 "register_operand" "")
6490 (match_operand:SI 1 "register_operand" ""))
6493 (plus:SI (match_dup 0)
6494 (match_operand:SI 2 "immediate_operand" "")))
6495 (clobber (reg:CC 33))])]
6496 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6497 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6498 REGNO (operands[0]) == BASE_REGISTER ||
6499 REGNO (operands[1]) == BASE_REGISTER) &&
6500 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6504 ; peepholes for fast char instructions
6508 ; [(set (match_operand:QI 0 "register_operand" "d")
6509 ; (match_operand:QI 1 "s_operand" "Q"))
6510 ; (set (match_operand:SI 2 "register_operand" "0")
6511 ; (zero_extend:SI (match_dup 0)))]
6512 ; "REGNO(operands[0]) == REGNO(operands[2])"
6513 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6516 ; [(set (match_operand:QI 0 "register_operand" "d")
6517 ; (match_operand:QI 1 "s_operand" "Q"))
6518 ; (set (match_operand:SI 2 "register_operand" "0")
6519 ; (sign_extend:SI (match_dup 0)))]
6520 ; "REGNO(operands[0]) == REGNO(operands[2])"
6521 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6524 [(set (match_operand:QI 0 "register_operand" "d")
6525 (match_operand:QI 1 "immediate_operand" "J"))
6526 (set (match_operand:SI 2 "register_operand" "0" )
6527 (sign_extend:SI (match_dup 0) ) )]
6528 "REGNO(operands[0]) == REGNO(operands[2])"
6532 ; peepholes for fast short instructions
6536 ; [(set (match_operand:HI 0 "register_operand" "d")
6537 ; (match_operand:HI 1 "s_operand" "Q"))
6538 ; (set (match_operand:SI 2 "register_operand" "0" )
6539 ; (zero_extend:SI (match_dup 0)))]
6540 ; "REGNO(operands[0]) == REGNO(operands[2])"
6541 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6544 [(set (match_operand:HI 0 "register_operand" "d")
6545 (match_operand:HI 1 "memory_operand" "m"))
6546 (set (match_operand:SI 2 "register_operand" "0" )
6547 (sign_extend:SI (match_dup 0)))]
6548 "REGNO(operands[0]) == REGNO(operands[2])"
6552 [(set (match_operand:HI 0 "register_operand" "d")
6553 (match_operand:HI 1 "immediate_operand" "K"))
6554 (set (match_operand:SI 2 "register_operand" "0" )
6555 (sign_extend:SI (match_dup 0) ) )]
6556 "REGNO(operands[0]) == REGNO(operands[2])"
6560 ; peepholes for divide instructions
6564 [(set (match_operand:DI 0 "register_operand" "d")
6565 (match_operand:DI 1 "memory_operand" "m"))
6567 (lshiftrt:DI (match_dup 0)
6568 (match_operand:SI 2 "immediate_operand" "J")))
6570 (div:SI (match_dup 0)
6571 (match_operand:SI 3 "nonimmediate_operand" "g")))
6577 output_asm_insn (\"l\\t%0,%1\", operands);
6578 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6580 if (REG_P (operands[3]))
6581 output_asm_insn (\"dr\\t%0,%3\", operands);
6583 output_asm_insn (\"d\\t%0,%3\", operands);
6585 return \"st\\t%N0,%N1\";
6589 [(set (match_operand:DI 0 "register_operand" "d")
6590 (match_operand:DI 1 "memory_operand" "m"))
6592 (lshiftrt:DI (match_dup 0)
6593 (match_operand:SI 2 "immediate_operand" "J")))
6595 (mod:SI (match_dup 0)
6596 (match_operand:SI 3 "nonimmediate_operand" "g")))
6602 output_asm_insn (\"l\\t%0,%1\", operands);
6603 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6605 if (REG_P (operands[3]))
6606 output_asm_insn (\"dr\\t%0,%3\", operands);
6608 output_asm_insn (\"d\\t%0,%3\", operands);
6610 return \"st\\t%0,%1\";