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s390.c (s390_preferred_reload_class): Never return ADDR_REGS if it isn't a subset...
[gcc.git] / gcc / config / s390 / s390.md
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
21
22 ;;
23 ;; Special constraints for s/390 machine description:
24 ;;
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
32 ;;
33 ;; Special formats used for outputting 390 instructions.
34 ;;
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
41 ;;
42 ;; We have a special constraint for pattern matching.
43 ;;
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
45 ;;
46
47
48 ;; Define an insn type attribute. This is used in function unit delay
49 ;; computations.
50
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
53
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
57
58 (define_attr "atype" "reg,mem"
59 (const_string "reg"))
60
61 ;; Generic pipeline function unit.
62
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
65
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
68
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
71
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
74
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
77
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
80
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
83
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
86
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
89
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
92
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
95
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
98
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
101
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
104
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
107
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
110
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
113
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
116
117 ;; Operand type. Used to default length attribute values
118
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
121 (const_string "RX"))
122
123 ;; Length in bytes.
124
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
141 (const_int 4)))
142
143 ;; Define attributes for `asm' insns.
144
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
147
148 ;;
149 ;; Condition Codes
150 ;;
151 ;
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
157
158 ; CCZ -> CCL / CCZ1
159 ; CCZ1 -> CCA/CCU/CCS/CCT
160 ; CCS -> CCA
161
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
164
165
166 ;;
167 ;;- Compare instructions.
168 ;;
169
170 (define_expand "cmpdi"
171 [(set (reg:CC 33)
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
174 "TARGET_64BIT"
175 "
176 {
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
179 DONE;
180 }")
181
182 (define_expand "cmpsi"
183 [(set (reg:CC 33)
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
186 ""
187 "
188 {
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
191 DONE;
192 }")
193
194 ;(define_expand "cmphi"
195 ; [(set (reg:CC 33)
196 ; (compare:CC (match_operand:HI 0 "register_operand" "")
197 ; (match_operand:HI 1 "general_operand" "")))]
198 ; ""
199 ; "
200 ;{
201 ; s390_compare_op0 = operands[0];
202 ; s390_compare_op1 = operands[1];
203 ; DONE;
204 ;}")
205
206 ;(define_expand "cmpqi"
207 ; [(set (reg:CC 33)
208 ; (compare:CC (match_operand:QI 0 "register_operand" "")
209 ; (match_operand:QI 1 "general_operand" "")))]
210 ; ""
211 ; "
212 ;{
213 ; s390_compare_op0 = operands[0];
214 ; s390_compare_op1 = operands[1];
215 ; DONE;
216 ;}")
217
218 (define_expand "cmpdf"
219 [(set (reg:CC 33)
220 (compare:CC (match_operand:DF 0 "register_operand" "")
221 (match_operand:DF 1 "general_operand" "")))]
222 "TARGET_HARD_FLOAT"
223 "
224 {
225 s390_compare_op0 = operands[0];
226 s390_compare_op1 = operands[1];
227 DONE;
228 }")
229
230 (define_expand "cmpsf"
231 [(set (reg:CC 33)
232 (compare:CC (match_operand:SF 0 "register_operand" "")
233 (match_operand:SF 1 "general_operand" "")))]
234 "TARGET_HARD_FLOAT"
235 "
236 {
237 s390_compare_op0 = operands[0];
238 s390_compare_op1 = operands[1];
239 DONE;
240 }")
241
242
243 ; DI instructions
244
245 (define_insn "*cmpdi_tm2"
246 [(set (reg 33)
247 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
248 (match_operand:DI 1 "const_int_operand" "n")
249 (match_operand:DI 2 "const_int_operand" "n"))
250 (const_int 0)))]
251 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
252 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
253 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
254 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
255 == INTVAL (operands[2]) >> 4"
256 "*
257 {
258 int part = INTVAL (operands[2]) >> 4;
259 int block = (1 << INTVAL (operands[1])) - 1;
260 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
261
262 operands[2] = GEN_INT (block << shift);
263
264 switch (part)
265 {
266 case 0: return \"tmhh\\t%0,%x2\";
267 case 1: return \"tmhl\\t%0,%x2\";
268 case 2: return \"tmlh\\t%0,%x2\";
269 case 3: return \"tmll\\t%0,%x2\";
270 default: abort ();
271 }
272 }"
273 [(set_attr "op_type" "RI")])
274
275 (define_insn "*cmpdi_tm_reg"
276 [(set (reg 33)
277 (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
278 (match_operand:DI 1 "immediate_operand" "n"))
279 (const_int 0)))]
280 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
281 && s390_single_hi (operands[1], DImode, 0) >= 0"
282 "*
283 {
284 int part = s390_single_hi (operands[1], DImode, 0);
285 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
286
287 switch (part)
288 {
289 case 0: return \"tmhh\\t%0,%x1\";
290 case 1: return \"tmhl\\t%0,%x1\";
291 case 2: return \"tmlh\\t%0,%x1\";
292 case 3: return \"tmll\\t%0,%x1\";
293 default: abort ();
294 }
295 }"
296 [(set_attr "op_type" "RI")])
297
298 (define_insn "*cmpdi_tm_mem"
299 [(set (reg 33)
300 (compare (and:DI (match_operand:DI 0 "s_operand" "%Qo")
301 (match_operand:DI 1 "immediate_operand" "n"))
302 (const_int 0)))]
303 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
304 && s390_single_qi (operands[1], DImode, 0) >= 0"
305 "*
306 {
307 int part = s390_single_qi (operands[1], DImode, 0);
308 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
309
310 operands[0] = gen_rtx_MEM (QImode,
311 plus_constant (XEXP (operands[0], 0), part));
312 return \"tm\\t%0,%b1\";
313 }"
314 [(set_attr "op_type" "SI")
315 (set_attr "atype" "mem")])
316
317 (define_insn "*ltgr"
318 [(set (reg 33)
319 (compare (match_operand:DI 0 "register_operand" "d")
320 (match_operand:DI 1 "const0_operand" "")))
321 (set (match_operand:DI 2 "register_operand" "=d")
322 (match_dup 0))]
323 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
324 "ltgr\\t%2,%0"
325 [(set_attr "op_type" "RRE")])
326
327 (define_insn "*cmpdi_ccs_0_64"
328 [(set (reg 33)
329 (compare (match_operand:DI 0 "register_operand" "d")
330 (match_operand:DI 1 "const0_operand" "")))]
331 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
332 "ltgr\\t%0,%0"
333 [(set_attr "op_type" "RRE")])
334
335 (define_insn "*cmpdi_ccs_0_31"
336 [(set (reg 33)
337 (compare (match_operand:DI 0 "register_operand" "d")
338 (match_operand:DI 1 "const0_operand" "")))]
339 "s390_match_ccmode(insn, CCSmode)"
340 "srda\\t%0,0"
341 [(set_attr "op_type" "RS")])
342
343 (define_insn "*cmpdi_ccs"
344 [(set (reg 33)
345 (compare (match_operand:DI 0 "register_operand" "d,d,d")
346 (match_operand:DI 1 "general_operand" "d,K,m")))]
347 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
348 "@
349 cgr\\t%0,%1
350 cghi\\t%0,%c1
351 cg\\t%0,%1"
352 [(set_attr "op_type" "RRE,RI,RXE")
353 (set_attr "atype" "reg,reg,mem")])
354
355 (define_insn "*cmpdi_ccu"
356 [(set (reg 33)
357 (compare (match_operand:DI 0 "register_operand" "d,d")
358 (match_operand:DI 1 "general_operand" "d,m")))]
359 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
360 "@
361 clgr\\t%0,%1
362 clg\\t%0,%1"
363 [(set_attr "op_type" "RRE,RXE")
364 (set_attr "atype" "reg,mem")])
365
366 (define_insn "*cmpdi_ccu_mem"
367 [(set (reg 33)
368 (compare (match_operand:DI 0 "s_operand" "oQ")
369 (match_operand:DI 1 "s_imm_operand" "oQ")))]
370 "s390_match_ccmode(insn, CCUmode)"
371 "clc\\t%O0(8,%R0),%1"
372 [(set_attr "op_type" "SS")
373 (set_attr "atype" "mem")])
374
375 ; SI instructions
376
377 (define_insn "*cmpsi_tm2"
378 [(set (reg 33)
379 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
380 (match_operand:SI 1 "const_int_operand" "n")
381 (match_operand:SI 2 "const_int_operand" "n"))
382 (const_int 0)))]
383 "s390_match_ccmode(insn, CCTmode)
384 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
385 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
386 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
387 == INTVAL (operands[2]) >> 4"
388 "*
389 {
390 int part = INTVAL (operands[2]) >> 4;
391 int block = (1 << INTVAL (operands[1])) - 1;
392 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
393
394 operands[2] = GEN_INT (block << shift);
395
396 switch (part)
397 {
398 case 0: return \"tmh\\t%0,%x2\";
399 case 1: return \"tml\\t%0,%x2\";
400 default: abort ();
401 }
402 }"
403 [(set_attr "op_type" "RI")])
404
405 (define_insn "*cmpsi_tm_reg"
406 [(set (reg 33)
407 (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
408 (match_operand:SI 1 "immediate_operand" "n"))
409 (const_int 0)))]
410 "s390_match_ccmode(insn, CCTmode)
411 && s390_single_hi (operands[1], SImode, 0) >= 0"
412 "*
413 {
414 int part = s390_single_hi (operands[1], SImode, 0);
415 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
416
417 switch (part)
418 {
419 case 0: return \"tmh\\t%0,%x1\";
420 case 1: return \"tml\\t%0,%x1\";
421 default: abort ();
422 }
423 }"
424 [(set_attr "op_type" "RI")])
425
426 (define_insn "*cmpsi_tm_mem"
427 [(set (reg 33)
428 (compare (and:SI (match_operand:SI 0 "s_operand" "%Qo")
429 (match_operand:SI 1 "immediate_operand" "n"))
430 (const_int 0)))]
431 "s390_match_ccmode(insn, CCTmode)
432 && s390_single_qi (operands[1], SImode, 0) >= 0"
433 "*
434 {
435 int part = s390_single_qi (operands[1], SImode, 0);
436 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
437
438 operands[0] = gen_rtx_MEM (QImode,
439 plus_constant (XEXP (operands[0], 0), part));
440 return \"tm\\t%0,%b1\";
441 }"
442 [(set_attr "op_type" "SI")
443 (set_attr "atype" "mem")])
444
445 (define_insn "*ltr"
446 [(set (reg 33)
447 (compare (match_operand:SI 0 "register_operand" "d")
448 (match_operand:SI 1 "const0_operand" "")))
449 (set (match_operand:SI 2 "register_operand" "=d")
450 (match_dup 0))]
451 "s390_match_ccmode(insn, CCSmode)"
452 "ltr\\t%2,%0"
453 [(set_attr "op_type" "RR")])
454
455 (define_insn "*icm15"
456 [(set (reg 33)
457 (compare (match_operand:SI 0 "s_operand" "Qo")
458 (match_operand:SI 1 "const0_operand" "")))
459 (set (match_operand:SI 2 "register_operand" "=d")
460 (match_dup 0))]
461 "s390_match_ccmode(insn, CCSmode)"
462 "icm\\t%2,15,%0"
463 [(set_attr "op_type" "RS")
464 (set_attr "atype" "mem")])
465
466 (define_insn "*icm15_cconly"
467 [(set (reg 33)
468 (compare (match_operand:SI 0 "s_operand" "Qo")
469 (match_operand:SI 1 "const0_operand" "")))
470 (clobber (match_scratch:SI 2 "=d"))]
471 "s390_match_ccmode(insn, CCSmode)"
472 "icm\\t%2,15,%0"
473 [(set_attr "op_type" "RS")
474 (set_attr "atype" "mem")])
475
476 (define_insn "*cmpsi_ccs_0"
477 [(set (reg 33)
478 (compare (match_operand:SI 0 "register_operand" "d")
479 (match_operand:SI 1 "const0_operand" "")))]
480 "s390_match_ccmode(insn, CCSmode)"
481 "ltr\\t%0,%0"
482 [(set_attr "op_type" "RR")])
483
484 (define_insn "*cmpsidi_ccs"
485 [(set (reg 33)
486 (compare (match_operand:SI 0 "register_operand" "d")
487 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
488 "s390_match_ccmode(insn, CCSmode)"
489 "ch\\t%0,%1"
490 [(set_attr "op_type" "RR")
491 (set_attr "atype" "mem")])
492
493 (define_insn "*cmpsi_ccs"
494 [(set (reg 33)
495 (compare (match_operand:SI 0 "register_operand" "d,d,d")
496 (match_operand:SI 1 "general_operand" "d,K,m")))]
497 "s390_match_ccmode(insn, CCSmode)"
498 "@
499 cr\\t%0,%1
500 chi\\t%0,%c1
501 c\\t%0,%1"
502 [(set_attr "op_type" "RR,RI,RX")
503 (set_attr "atype" "reg,reg,mem")])
504
505 (define_insn "*cmpsi_ccu"
506 [(set (reg 33)
507 (compare (match_operand:SI 0 "register_operand" "d,d")
508 (match_operand:SI 1 "general_operand" "d,m")))]
509 "s390_match_ccmode(insn, CCUmode)"
510 "@
511 clr\\t%0,%1
512 cl\\t%0,%1"
513 [(set_attr "op_type" "RR,RX")
514 (set_attr "atype" "reg,mem")])
515
516 (define_insn "*cmpsi_ccu_mem"
517 [(set (reg 33)
518 (compare (match_operand:SI 0 "s_operand" "oQ")
519 (match_operand:SI 1 "s_imm_operand" "oQ")))]
520 "s390_match_ccmode(insn, CCUmode)"
521 "clc\\t%O0(4,%R0),%1"
522 [(set_attr "op_type" "SS")
523 (set_attr "atype" "mem")])
524
525
526 ; HI instructions
527
528 (define_insn "*cmphi_tm_sub"
529 [(set (reg 33)
530 (compare (and:SI (subreg:SI (match_operand:HI 0 "s_operand" "%Qo") 0)
531 (match_operand:SI 1 "immediate_operand" "n"))
532 (const_int 0)))]
533 "s390_match_ccmode(insn, CCTmode)
534 && s390_single_qi (operands[1], HImode, 0) >= 0"
535 "*
536 {
537 int part = s390_single_qi (operands[1], HImode, 0);
538 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
539
540 operands[0] = gen_rtx_MEM (QImode,
541 plus_constant (XEXP (operands[0], 0), part));
542 return \"tm\\t%0,%b1\";
543 }"
544 [(set_attr "op_type" "SI")
545 (set_attr "atype" "mem")])
546
547 (define_insn "*icm3"
548 [(set (reg 33)
549 (compare (match_operand:HI 0 "s_operand" "Qo")
550 (match_operand:HI 1 "const0_operand" "")))
551 (set (match_operand:HI 2 "register_operand" "=d")
552 (match_dup 0))]
553 "s390_match_ccmode(insn, CCSmode)"
554 "icm\\t%2,3,%0"
555 [(set_attr "op_type" "RS")
556 (set_attr "atype" "mem")])
557
558 (define_insn "*cmphi_cct_0"
559 [(set (reg 33)
560 (compare (match_operand:HI 0 "register_operand" "d")
561 (match_operand:HI 1 "const0_operand" "")))]
562 "s390_match_ccmode(insn, CCTmode)"
563 "tml\\t%0,65535"
564 [(set_attr "op_type" "RX")])
565
566 (define_insn "*cmphi_ccs_0"
567 [(set (reg 33)
568 (compare (match_operand:HI 0 "s_operand" "Qo")
569 (match_operand:HI 1 "const0_operand" "")))
570 (clobber (match_scratch:HI 2 "=d"))]
571 "s390_match_ccmode(insn, CCSmode)"
572 "icm\\t%2,3,%0"
573 [(set_attr "op_type" "RS")
574 (set_attr "atype" "mem")])
575
576 (define_insn "*cmphi_ccu"
577 [(set (reg 33)
578 (compare (match_operand:HI 0 "register_operand" "d")
579 (match_operand:HI 1 "s_imm_operand" "Qo")))]
580 "s390_match_ccmode(insn, CCUmode)"
581 "clm\\t%0,3,%1"
582 [(set_attr "op_type" "RS")
583 (set_attr "atype" "mem")])
584
585 (define_insn "*cmphi_ccu_mem"
586 [(set (reg 33)
587 (compare (match_operand:HI 0 "s_operand" "oQ")
588 (match_operand:HI 1 "s_imm_operand" "oQ")))]
589 "s390_match_ccmode(insn, CCUmode)"
590 "clc\\t%O0(2,%R0),%1"
591 [(set_attr "op_type" "SS")
592 (set_attr "atype" "mem")])
593
594
595 ; QI instructions
596
597 (define_insn "*cmpqi_tm2"
598 [(set (reg 33)
599 (compare (zero_extract:SI (match_operand:QI 0 "s_operand" "Qo")
600 (match_operand:SI 1 "const_int_operand" "n")
601 (match_operand:SI 2 "const_int_operand" "n"))
602 (const_int 0)))]
603 "s390_match_ccmode(insn, CCTmode)
604 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
605 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
606 "*
607 {
608 int block = (1 << INTVAL (operands[1])) - 1;
609 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
610
611 operands[2] = GEN_INT (block << shift);
612 return \"tm\\t%0,%b2\";
613 }"
614 [(set_attr "op_type" "SI")
615 (set_attr "atype" "mem")])
616
617 (define_insn "*cmpqi_tm"
618 [(set (reg 33)
619 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,Q")
620 (match_operand:QI 1 "immediate_operand" "n,n"))
621 (const_int 0)))]
622 "s390_match_ccmode(insn, CCTmode)"
623 "@
624 tml\\t%0,%b1
625 tm\\t%0,%b1"
626 [(set_attr "op_type" "RI,SI")
627 (set_attr "atype" "reg,mem")])
628
629 (define_insn "*cmpqi_tm_sub"
630 [(set (reg 33)
631 (compare (and:SI (subreg:SI (match_operand:QI 0 "s_operand" "%Qo") 0)
632 (match_operand:SI 1 "immediate_operand" "n"))
633 (const_int 0)))]
634 "s390_match_ccmode(insn, CCTmode)"
635 "tm\\t%0,%b1"
636 [(set_attr "op_type" "SI")
637 (set_attr "atype" "mem")])
638
639 (define_insn "*icm1"
640 [(set (reg 33)
641 (compare (match_operand:QI 0 "s_operand" "Qo")
642 (match_operand:QI 1 "const0_operand" "")))
643 (set (match_operand:QI 2 "register_operand" "=d")
644 (match_dup 0))]
645 "s390_match_ccmode(insn, CCSmode)"
646 "icm\\t%2,1,%0"
647 [(set_attr "op_type" "RS")
648 (set_attr "atype" "mem")])
649
650 (define_insn "*tm_0"
651 [(set (reg 33)
652 (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
653 (match_operand:QI 1 "immediate_operand" "")))
654 (const_int 0)))]
655 "s390_match_ccmode(insn, CCTmode) &&
656 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
657 "tm\\t%0,%1"
658 [(set_attr "op_type" "RI")
659 (set_attr "atype" "mem")])
660
661 (define_insn "*cmpqi_cct_0"
662 [(set (reg 33)
663 (compare (match_operand:QI 0 "register_operand" "d")
664 (match_operand:QI 1 "const0_operand" "")))]
665 "s390_match_ccmode(insn, CCTmode)"
666 "tml\\t%0,255"
667 [(set_attr "op_type" "RI")])
668
669 (define_insn "*cmpqi_ccs_0"
670 [(set (reg 33)
671 (compare (match_operand:QI 0 "s_operand" "Qo")
672 (match_operand:QI 1 "const0_operand" "")))
673 (clobber (match_scratch:QI 2 "=d"))]
674 "s390_match_ccmode(insn, CCSmode)"
675 "icm\\t%2,1,%0"
676 [(set_attr "op_type" "RS")
677 (set_attr "atype" "mem")])
678
679 (define_insn "*cmpqi_ccu_0"
680 [(set (reg 33)
681 (compare (match_operand:QI 0 "s_operand" "Qo")
682 (match_operand:QI 1 "const0_operand" "")))]
683 "s390_match_ccmode(insn, CCUmode)"
684 "cli\\t%0,0"
685 [(set_attr "op_type" "SI")
686 (set_attr "atype" "mem")])
687
688 (define_insn "*cmpqi_ccu"
689 [(set (reg 33)
690 (compare (match_operand:QI 0 "register_operand" "d")
691 (match_operand:QI 1 "s_imm_operand" "Qo")))]
692 "s390_match_ccmode(insn, CCUmode)"
693 "clm\\t%0,1,%1"
694 [(set_attr "op_type" "RS")
695 (set_attr "atype" "mem")])
696
697 (define_insn "*cmpqi_ccu_immed"
698 [(set (reg 33)
699 (compare (match_operand:QI 0 "s_operand" "Qo")
700 (match_operand:QI 1 "const_int_operand" "n")))]
701 "s390_match_ccmode(insn, CCUmode) &&
702 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
703 "cli\\t%0,%1"
704 [(set_attr "op_type" "SI")
705 (set_attr "atype" "mem")])
706
707 (define_insn "*cmpqi_ccu_mem"
708 [(set (reg 33)
709 (compare (match_operand:QI 0 "s_operand" "oQ")
710 (match_operand:QI 1 "s_imm_operand" "oQ")))]
711 "s390_match_ccmode(insn, CCUmode)"
712 "clc\\t%O0(1,%R0),%1"
713 [(set_attr "op_type" "SS")
714 (set_attr "atype" "mem")])
715
716
717 ; DF instructions
718
719 (define_insn "*cmpdf_ccs_0"
720 [(set (reg 33)
721 (compare (match_operand:DF 0 "register_operand" "f")
722 (match_operand:DF 1 "const0_operand" "")))]
723 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
724 "ltdbr\\t%0,%0"
725 [(set_attr "op_type" "RR")])
726
727 (define_insn "*cmpdf_ccs_0_ibm"
728 [(set (reg 33)
729 (compare (match_operand:DF 0 "register_operand" "f")
730 (match_operand:DF 1 "const0_operand" "")))]
731 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
732 "ltdr\\t%0,%0"
733 [(set_attr "op_type" "RR")])
734
735 (define_insn "*cmpdf_ccs"
736 [(set (reg 33)
737 (compare (match_operand:DF 0 "register_operand" "f,f")
738 (match_operand:DF 1 "general_operand" "f,m")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
740 "@
741 cdbr\\t%0,%1
742 cdb\\t%0,%1"
743 [(set_attr "op_type" "RR,RX")
744 (set_attr "atype" "reg,mem")])
745
746 (define_insn "*cmpdf_ccs_ibm"
747 [(set (reg 33)
748 (compare (match_operand:DF 0 "register_operand" "f,f")
749 (match_operand:DF 1 "general_operand" "f,m")))]
750 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
751 "@
752 cdr\\t%0,%1
753 cd\\t%0,%1"
754 [(set_attr "op_type" "RR,RX")
755 (set_attr "atype" "reg,mem")])
756
757
758 ; SF instructions
759
760 (define_insn "*cmpsf_ccs_0"
761 [(set (reg 33)
762 (compare (match_operand:SF 0 "register_operand" "f")
763 (match_operand:SF 1 "const0_operand" "")))]
764 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
765 "ltebr\\t%0,%0"
766 [(set_attr "op_type" "RR")])
767
768 (define_insn "*cmpsf_ccs_0_ibm"
769 [(set (reg 33)
770 (compare (match_operand:SF 0 "register_operand" "f")
771 (match_operand:SF 1 "const0_operand" "")))]
772 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
773 "lter\\t%0,%0"
774 [(set_attr "op_type" "RR")])
775
776 (define_insn "*cmpsf_ccs"
777 [(set (reg 33)
778 (compare (match_operand:SF 0 "register_operand" "f,f")
779 (match_operand:SF 1 "general_operand" "f,m")))]
780 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
781 "@
782 cebr\\t%0,%1
783 ceb\\t%0,%1"
784 [(set_attr "op_type" "RR,RX")
785 (set_attr "atype" "reg,mem")])
786
787 (define_insn "*cmpsf_ccs"
788 [(set (reg 33)
789 (compare (match_operand:SF 0 "register_operand" "f,f")
790 (match_operand:SF 1 "general_operand" "f,m")))]
791 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
792 "@
793 cer\\t%0,%1
794 ce\\t%0,%1"
795 [(set_attr "op_type" "RR,RX")
796 (set_attr "atype" "reg,mem")])
797
798
799 ;;
800 ;;- Move instructions.
801 ;;
802
803 ;
804 ; movti instruction pattern(s).
805 ;
806
807 (define_insn "*movti_ss"
808 [(set (match_operand:TI 0 "s_operand" "=Qo")
809 (match_operand:TI 1 "s_imm_operand" "Qo"))]
810 ""
811 "mvc\\t%O0(16,%R0),%1"
812 [(set_attr "op_type" "SS")
813 (set_attr "atype" "mem")])
814
815 (define_insn "movti"
816 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m")
817 (match_operand:TI 1 "general_operand" "Q,d,dKm,d"))]
818 "TARGET_64BIT"
819 "@
820 lmg\\t%0,%N0,%1
821 stmg\\t%1,%N1,%0
822 #
823 #"
824 [(set_attr "op_type" "RSE,RSE,NN,NN")
825 (set_attr "atype" "mem")])
826
827 (define_split
828 [(set (match_operand:TI 0 "nonimmediate_operand" "")
829 (match_operand:TI 1 "general_operand" ""))]
830 "TARGET_64BIT && reload_completed
831 && !s_operand (operands[0], VOIDmode)
832 && !s_operand (operands[1], VOIDmode)
833 && (register_operand (operands[0], VOIDmode)
834 || register_operand (operands[1], VOIDmode))
835 && (!register_operand (operands[0], VOIDmode)
836 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
837 operands[1])
838 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
839 operands[1]))"
840 [(set (match_dup 2) (match_dup 4))
841 (set (match_dup 3) (match_dup 5))]
842 "
843 {
844 if (!register_operand (operands[0], VOIDmode)
845 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
846 operands[1]))
847 {
848 operands[2] = operand_subword (operands[0], 0, 0, TImode);
849 operands[3] = operand_subword (operands[0], 1, 0, TImode);
850 operands[4] = operand_subword (operands[1], 0, 0, TImode);
851 operands[5] = operand_subword (operands[1], 1, 0, TImode);
852 }
853 else
854 {
855 operands[2] = operand_subword (operands[0], 1, 0, TImode);
856 operands[3] = operand_subword (operands[0], 0, 0, TImode);
857 operands[4] = operand_subword (operands[1], 1, 0, TImode);
858 operands[5] = operand_subword (operands[1], 0, 0, TImode);
859 }
860 }")
861
862 (define_split
863 [(set (match_operand:TI 0 "register_operand" "")
864 (match_operand:TI 1 "memory_operand" ""))]
865 "TARGET_64BIT && reload_completed
866 && !s_operand (operands[1], VOIDmode)"
867 [(set (match_dup 2) (match_dup 3))
868 (set (match_dup 0) (mem:TI (match_dup 2)))]
869 "operands[2] = operand_subword (operands[0], 0, 0, TImode);
870 operands[3] = XEXP (operands[1], 0);")
871
872 ;
873 ; movdi instruction pattern(s).
874 ;
875
876 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
877 ;; move to get the address of the symbolic object from the GOT.
878
879 (define_expand "movdi"
880 [(set (match_operand:DI 0 "general_operand" "")
881 (match_operand:DI 1 "general_operand" ""))]
882 ""
883 "
884 {
885 /* Handle PIC symbolic constants. */
886 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
887 emit_pic_move (operands, DImode);
888
889 /* During and after reload, we need to force constants
890 to the literal pool ourselves, if necessary. */
891 if ((reload_in_progress || reload_completed)
892 && CONSTANT_P (operands[1])
893 && (!legitimate_reload_constant_p (operands[1])
894 || fp_operand (operands[0], VOIDmode)))
895 operands[1] = force_const_mem (DImode, operands[1]);
896 }")
897
898 (define_insn "*movdi_lhi"
899 [(set (match_operand:DI 0 "register_operand" "=d")
900 (match_operand:DI 1 "immediate_operand" "K"))]
901 "TARGET_64BIT
902 && GET_CODE (operands[1]) == CONST_INT
903 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
904 && !fp_operand (operands[0], VOIDmode)"
905 "lghi\\t%0,%h1"
906 [(set_attr "op_type" "RI")
907 (set_attr "atype" "reg")])
908
909 (define_insn "*movdi_lli"
910 [(set (match_operand:DI 0 "register_operand" "=d")
911 (match_operand:DI 1 "immediate_operand" "n"))]
912 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
913 && !fp_operand (operands[0], VOIDmode)"
914 "*
915 {
916 int part = s390_single_hi (operands[1], DImode, 0);
917 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
918
919 switch (part)
920 {
921 case 0: return \"llihh\\t%0,%x1\";
922 case 1: return \"llihl\\t%0,%x1\";
923 case 2: return \"llilh\\t%0,%x1\";
924 case 3: return \"llill\\t%0,%x1\";
925 default: abort ();
926 }
927 }"
928 [(set_attr "op_type" "RI")
929 (set_attr "atype" "reg")])
930
931 (define_insn "*movdi_larl"
932 [(set (match_operand:DI 0 "register_operand" "=d")
933 (match_operand:DI 1 "larl_operand" "X"))]
934 "TARGET_64BIT
935 && !fp_operand (operands[0], VOIDmode)"
936 "larl\\t%0,%1"
937 [(set_attr "op_type" "RIL")
938 (set_attr "atype" "reg")
939 (set_attr "type" "la")])
940
941 (define_insn "*movdi_ss"
942 [(set (match_operand:DI 0 "s_operand" "=Qo")
943 (match_operand:DI 1 "s_imm_operand" "Qo"))]
944 ""
945 "mvc\\t%O0(8,%R0),%1"
946 [(set_attr "op_type" "SS")
947 (set_attr "atype" "mem")])
948
949 (define_insn "*movdi_64"
950 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,f,f,m")
951 (match_operand:DI 1 "general_operand" "d,m,d,f,m,f"))]
952 "TARGET_64BIT"
953 "@
954 lgr\\t%0,%1
955 lg\\t%0,%1
956 stg\\t%1,%0
957 ldr\\t%0,%1
958 ld\\t%0,%1
959 std\\t%1,%0"
960 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX")
961 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
962
963 (define_insn "*movdi_31"
964 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,f,f,m")
965 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,f,m,f"))]
966 "!TARGET_64BIT"
967 "@
968 lm\\t%0,%N0,%1
969 stm\\t%1,%N1,%0
970 #
971 #
972 ldr\\t%0,%1
973 ld\\t%0,%1
974 std\\t%1,%0"
975 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX")
976 (set_attr "atype" "mem,mem,*,*,reg,mem,mem")])
977
978 (define_split
979 [(set (match_operand:DI 0 "nonimmediate_operand" "")
980 (match_operand:DI 1 "general_operand" ""))]
981 "!TARGET_64BIT && reload_completed
982 && !fp_operand (operands[0], VOIDmode)
983 && !fp_operand (operands[1], VOIDmode)
984 && !s_operand (operands[0], VOIDmode)
985 && !s_operand (operands[1], VOIDmode)
986 && (register_operand (operands[0], VOIDmode)
987 || register_operand (operands[1], VOIDmode))
988 && (!register_operand (operands[0], VOIDmode)
989 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
990 operands[1])
991 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
992 operands[1]))"
993 [(set (match_dup 2) (match_dup 4))
994 (set (match_dup 3) (match_dup 5))]
995 "
996 {
997 if (!register_operand (operands[0], VOIDmode)
998 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
999 operands[1]))
1000 {
1001 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1002 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1003 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1004 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1005 }
1006 else
1007 {
1008 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1009 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1010 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1011 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1012 }
1013 }")
1014
1015 (define_split
1016 [(set (match_operand:DI 0 "register_operand" "")
1017 (match_operand:DI 1 "memory_operand" ""))]
1018 "!TARGET_64BIT && reload_completed
1019 && !fp_operand (operands[0], VOIDmode)
1020 && !fp_operand (operands[1], VOIDmode)
1021 && !s_operand (operands[1], VOIDmode)"
1022 [(set (match_dup 2) (match_dup 3))
1023 (set (match_dup 0) (mem:DI (match_dup 2)))]
1024 "operands[2] = operand_subword (operands[0], 1, 0, DImode);
1025 operands[3] = XEXP (operands[1], 0);")
1026
1027 ;
1028 ; movsi instruction pattern(s).
1029 ;
1030
1031 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1032 ;; move to get the address of the symbolic object from the GOT.
1033
1034 (define_expand "movsi"
1035 [(set (match_operand:SI 0 "general_operand" "")
1036 (match_operand:SI 1 "general_operand" ""))]
1037 ""
1038 "
1039 {
1040 /* Handle PIC symbolic constants. */
1041 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1042 emit_pic_move (operands, SImode);
1043
1044 /* expr.c tries to load an effective address using
1045 force_reg. This fails because we don't have a
1046 generic load_address pattern. Convert the move
1047 to a proper arithmetic operation instead, unless
1048 it is guaranteed to be OK. */
1049 if (GET_CODE (operands[1]) == PLUS
1050 && !legitimate_la_operand_p (operands[1]))
1051 {
1052 operands[1] = force_operand (operands[1], operands[0]);
1053 if (operands[1] == operands[0])
1054 DONE;
1055 }
1056
1057 /* During and after reload, we need to force constants
1058 to the literal pool ourselves, if necessary. */
1059 if ((reload_in_progress || reload_completed)
1060 && CONSTANT_P (operands[1])
1061 && (!legitimate_reload_constant_p (operands[1])
1062 || fp_operand (operands[0], VOIDmode)))
1063 operands[1] = force_const_mem (SImode, operands[1]);
1064 }")
1065
1066 (define_insn "*movsi_lhi"
1067 [(set (match_operand:SI 0 "register_operand" "=d")
1068 (match_operand:SI 1 "immediate_operand" "K"))]
1069 "GET_CODE (operands[1]) == CONST_INT
1070 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1071 && !fp_operand (operands[0], VOIDmode)"
1072 "lhi\\t%0,%h1"
1073 [(set_attr "op_type" "RI")])
1074
1075 (define_insn "*movsi_lli"
1076 [(set (match_operand:SI 0 "register_operand" "=d")
1077 (match_operand:SI 1 "immediate_operand" "n"))]
1078 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1079 && !fp_operand (operands[0], VOIDmode)"
1080 "*
1081 {
1082 int part = s390_single_hi (operands[1], SImode, 0);
1083 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1084
1085 switch (part)
1086 {
1087 case 0: return \"llilh\\t%0,%x1\";
1088 case 1: return \"llill\\t%0,%x1\";
1089 default: abort ();
1090 }
1091 }"
1092 [(set_attr "op_type" "RI")])
1093
1094 (define_insn "*movsi_ss"
1095 [(set (match_operand:SI 0 "s_operand" "=Qo")
1096 (match_operand:SI 1 "s_imm_operand" "Qo"))]
1097 ""
1098 "mvc\\t%O0(4,%R0),%1"
1099 [(set_attr "op_type" "SS")
1100 (set_attr "atype" "mem")])
1101
1102 (define_insn "*movsi"
1103 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,f,f,m")
1104 (match_operand:SI 1 "general_operand" "d,m,d,f,m,f"))]
1105 ""
1106 "@
1107 lr\\t%0,%1
1108 l\\t%0,%1
1109 st\\t%1,%0
1110 ler\\t%0,%1
1111 le\\t%0,%1
1112 ste\\t%1,%0"
1113 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1114 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1115
1116
1117 ;
1118 ; movhi instruction pattern(s).
1119 ;
1120
1121 (define_insn "movhi"
1122 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m")
1123 (match_operand:HI 1 "general_operand" "d,n,m,d"))]
1124 ""
1125 "@
1126 lr\\t%0,%1
1127 lhi\\t%0,%h1
1128 lh\\t%0,%1
1129 sth\\t%1,%0"
1130 [(set_attr "op_type" "RR,RI,RX,RX")
1131 (set_attr "atype" "reg,reg,mem,mem")])
1132
1133
1134 ;
1135 ; movqi instruction pattern(s).
1136 ;
1137
1138 (define_insn "movqi_64"
1139 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1140 (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1141 "TARGET_64BIT"
1142 "@
1143 lr\\t%0,%1
1144 lhi\\t%0,%b1
1145 llgc\\t%0,%1
1146 stc\\t%1,%0
1147 mvi\\t%0,%b1"
1148 [(set_attr "op_type" "RR,RI,RXE,RX,SI")
1149 (set_attr "atype" "reg,reg,mem,mem,mem")])
1150
1151
1152 (define_insn "movqi"
1153 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1154 (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1155 ""
1156 "@
1157 lr\\t%0,%1
1158 lhi\\t%0,%b1
1159 ic\\t%0,%1
1160 stc\\t%1,%0
1161 mvi\\t%0,%b1"
1162 [(set_attr "op_type" "RR,RI,RX,RX,SI")
1163 (set_attr "atype" "reg,reg,mem,mem,mem")])
1164
1165
1166 ;
1167 ; moveqstrictqi instruction pattern(s).
1168 ;
1169
1170 (define_insn "*movstrictqi"
1171 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1172 (match_operand:QI 1 "memory_operand" "m"))]
1173 ""
1174 "ic\\t%0,%1"
1175 [(set_attr "op_type" "RX")
1176 (set_attr "atype" "mem")])
1177
1178 ;
1179 ; movstricthi instruction pattern(s).
1180 ;
1181
1182 (define_insn "*movstricthi"
1183 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1184 (match_operand:HI 1 "s_imm_operand" "Qo"))
1185 (clobber (reg:CC 33))]
1186 ""
1187 "icm\\t%0,3,%1"
1188 [(set_attr "op_type" "RS")
1189 (set_attr "atype" "mem")])
1190
1191
1192 ;
1193 ; movstrictsi instruction pattern(s).
1194 ;
1195
1196 (define_insn "movestrictsi"
1197 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1198 (match_operand:SI 1 "general_operand" "d,m"))]
1199 "TARGET_64BIT"
1200 "@
1201 lr\\t%0,%1
1202 l\\t%0,%1"
1203 [(set_attr "op_type" "RR,RS")
1204 (set_attr "atype" "reg,mem")])
1205
1206
1207 ;
1208 ; movdf instruction pattern(s).
1209 ;
1210
1211 (define_expand "movdf"
1212 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1213 (match_operand:DF 1 "general_operand" ""))]
1214 ""
1215 "
1216 {
1217 /* During and after reload, we need to force constants
1218 to the literal pool ourselves, if necessary. */
1219 if ((reload_in_progress || reload_completed)
1220 && CONSTANT_P (operands[1]))
1221 operands[1] = force_const_mem (DFmode, operands[1]);
1222 }")
1223
1224 (define_insn "*movdf_ss"
1225 [(set (match_operand:DF 0 "s_operand" "=Qo")
1226 (match_operand:DF 1 "s_imm_operand" "Qo"))]
1227 ""
1228 "mvc\\t%O0(8,%R0),%1"
1229 [(set_attr "op_type" "SS")
1230 (set_attr "atype" "mem")])
1231
1232 (define_insn "*movdf_64"
1233 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1234 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d"))]
1235 "TARGET_64BIT"
1236 "@
1237 ldr\\t%0,%1
1238 ld\\t%0,%1
1239 std\\t%1,%0
1240 lgr\\t%0,%1
1241 lg\\t%0,%1
1242 stg\\t%1,%0"
1243 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE")
1244 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1245
1246 (define_insn "*movdf_31"
1247 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m")
1248 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d"))]
1249 "!TARGET_64BIT"
1250 "@
1251 ldr\\t%0,%1
1252 ld\\t%0,%1
1253 std\\t%1,%0
1254 lm\\t%0,%N0,%1
1255 stm\\t%1,%N1,%0
1256 #
1257 #"
1258 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN")
1259 (set_attr "atype" "reg,mem,mem,mem,mem,*,*")])
1260
1261 (define_split
1262 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1263 (match_operand:DF 1 "general_operand" ""))]
1264 "!TARGET_64BIT && reload_completed
1265 && !fp_operand (operands[0], VOIDmode)
1266 && !fp_operand (operands[1], VOIDmode)
1267 && !s_operand (operands[0], VOIDmode)
1268 && !s_operand (operands[1], VOIDmode)
1269 && (register_operand (operands[0], VOIDmode)
1270 || register_operand (operands[1], VOIDmode))
1271 && (!register_operand (operands[0], VOIDmode)
1272 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1273 operands[1])
1274 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1275 operands[1]))"
1276 [(set (match_dup 2) (match_dup 4))
1277 (set (match_dup 3) (match_dup 5))]
1278 "
1279 {
1280 if (!register_operand (operands[0], VOIDmode)
1281 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1282 operands[1]))
1283 {
1284 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1285 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1286 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1287 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1288 }
1289 else
1290 {
1291 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1292 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1293 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1294 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1295 }
1296 }")
1297
1298 (define_split
1299 [(set (match_operand:DF 0 "register_operand" "")
1300 (match_operand:DF 1 "memory_operand" ""))]
1301 "!TARGET_64BIT && reload_completed
1302 && !fp_operand (operands[0], VOIDmode)
1303 && !fp_operand (operands[1], VOIDmode)
1304 && !s_operand (operands[1], VOIDmode)"
1305 [(set (match_dup 2) (match_dup 3))
1306 (set (match_dup 0) (mem:DI (match_dup 2)))]
1307 "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1308 operands[3] = XEXP (operands[1], 0);")
1309
1310 ;
1311 ; movsf instruction pattern(s).
1312 ;
1313
1314 (define_expand "movsf"
1315 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1316 (match_operand:SF 1 "general_operand" ""))]
1317 ""
1318 "
1319 {
1320 /* During and after reload, we need to force constants
1321 to the literal pool ourselves, if necessary. */
1322 if ((reload_in_progress || reload_completed)
1323 && CONSTANT_P (operands[1]))
1324 operands[1] = force_const_mem (SFmode, operands[1]);
1325 }")
1326
1327 (define_insn "*movsf_ss"
1328 [(set (match_operand:SF 0 "s_operand" "=Qo")
1329 (match_operand:SF 1 "s_imm_operand" "Qo"))]
1330 ""
1331 "mvc\\t%O0(4,%R0),%1"
1332 [(set_attr "op_type" "SS")
1333 (set_attr "atype" "mem")])
1334
1335 (define_insn "*movsf"
1336 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1337 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d"))]
1338 ""
1339 "@
1340 ler\\t%0,%1
1341 le\\t%0,%1
1342 ste\\t%1,%0
1343 lr\\t%0,%1
1344 l\\t%0,%1
1345 st\\t%1,%0"
1346 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1347 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1348
1349 ;
1350 ; load_multiple pattern(s).
1351 ;
1352
1353 (define_expand "load_multiple"
1354 [(match_par_dup 3 [(set (match_operand 0 "" "")
1355 (match_operand 1 "" ""))
1356 (use (match_operand 2 "" ""))])]
1357 ""
1358 "
1359 {
1360 int regno;
1361 int count;
1362 rtx from;
1363 int i, off;
1364
1365 /* Support only loading a constant number of fixed-point registers from
1366 memory and only bother with this if more than two */
1367 if (GET_CODE (operands[2]) != CONST_INT
1368 || INTVAL (operands[2]) < 2
1369 || INTVAL (operands[2]) > 16
1370 || GET_CODE (operands[1]) != MEM
1371 || GET_CODE (operands[0]) != REG
1372 || REGNO (operands[0]) >= 16)
1373 FAIL;
1374
1375 count = INTVAL (operands[2]);
1376 regno = REGNO (operands[0]);
1377
1378 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1379 if (no_new_pseudos)
1380 {
1381 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1382 {
1383 from = XEXP (operands[1], 0);
1384 off = 0;
1385 }
1386 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1387 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1388 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1389 {
1390 from = XEXP (XEXP (operands[1], 0), 0);
1391 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1392 }
1393 else
1394 FAIL;
1395
1396 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1397 FAIL;
1398 }
1399 else
1400 {
1401 from = force_reg (Pmode, XEXP (operands[1], 0));
1402 off = 0;
1403 }
1404
1405 for (i = 0; i < count; i++)
1406 XVECEXP (operands[3], 0, i)
1407 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1408 change_address (operands[1], Pmode,
1409 plus_constant (from,
1410 off + i * UNITS_PER_WORD)));
1411 }")
1412
1413 (define_insn "*load_multiple_di"
1414 [(match_parallel 0 "load_multiple_operation"
1415 [(set (match_operand:DI 1 "register_operand" "=r")
1416 (match_operand:DI 2 "s_operand" "oQ"))])]
1417 ""
1418 "*
1419 {
1420 int words = XVECLEN (operands[0], 0);
1421
1422 if (XVECLEN (operands[0], 0) == 1)
1423 return \"lg\\t%1,0(%2)\";
1424
1425 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1426 return \"lmg\\t%1,%0,%2\";
1427 }"
1428 [(set_attr "op_type" "RXE")
1429 (set_attr "atype" "mem")
1430 (set_attr "type" "lm")])
1431
1432 (define_insn "*load_multiple_si"
1433 [(match_parallel 0 "load_multiple_operation"
1434 [(set (match_operand:SI 1 "register_operand" "=r")
1435 (match_operand:SI 2 "s_operand" "oQ"))])]
1436 ""
1437 "*
1438 {
1439 int words = XVECLEN (operands[0], 0);
1440
1441 if (XVECLEN (operands[0], 0) == 1)
1442 return \"l\\t%1,0(%2)\";
1443
1444 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1445 return \"lm\\t%1,%0,%2\";
1446 }"
1447 [(set_attr "op_type" "RXE")
1448 (set_attr "atype" "mem")
1449 (set_attr "type" "lm")])
1450
1451 ;
1452 ; store multiple pattern(s).
1453 ;
1454
1455 (define_expand "store_multiple"
1456 [(match_par_dup 3 [(set (match_operand 0 "" "")
1457 (match_operand 1 "" ""))
1458 (use (match_operand 2 "" ""))])]
1459 ""
1460 "
1461 {
1462 int regno;
1463 int count;
1464 rtx to;
1465 int i, off;
1466
1467 /* Support only storing a constant number of fixed-point registers to
1468 memory and only bother with this if more than two. */
1469 if (GET_CODE (operands[2]) != CONST_INT
1470 || INTVAL (operands[2]) < 2
1471 || INTVAL (operands[2]) > 16
1472 || GET_CODE (operands[0]) != MEM
1473 || GET_CODE (operands[1]) != REG
1474 || REGNO (operands[1]) >= 16)
1475 FAIL;
1476
1477 count = INTVAL (operands[2]);
1478 regno = REGNO (operands[1]);
1479
1480 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1481
1482 if (no_new_pseudos)
1483 {
1484 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1485 {
1486 to = XEXP (operands[0], 0);
1487 off = 0;
1488 }
1489 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1490 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1491 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1492 {
1493 to = XEXP (XEXP (operands[0], 0), 0);
1494 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1495 }
1496 else
1497 FAIL;
1498
1499 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1500 FAIL;
1501 }
1502 else
1503 {
1504 to = force_reg (Pmode, XEXP (operands[0], 0));
1505 off = 0;
1506 }
1507
1508 for (i = 0; i < count; i++)
1509 XVECEXP (operands[3], 0, i)
1510 = gen_rtx_SET (VOIDmode,
1511 change_address (operands[0], Pmode,
1512 plus_constant (to,
1513 off + i * UNITS_PER_WORD)),
1514 gen_rtx_REG (Pmode, regno + i));
1515 }")
1516
1517 (define_insn "*store_multiple_di"
1518 [(match_parallel 0 "store_multiple_operation"
1519 [(set (match_operand:DI 1 "s_operand" "=oQ")
1520 (match_operand:DI 2 "register_operand" "r"))])]
1521 ""
1522 "*
1523 {
1524 int words = XVECLEN (operands[0], 0);
1525
1526 if (XVECLEN (operands[0], 0) == 1)
1527 return \"stg\\t%1,0(%2)\";
1528
1529 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1530 return \"stmg\\t%2,%0,%1\";
1531 }"
1532 [(set_attr "op_type" "RXE")
1533 (set_attr "atype" "mem")
1534 (set_attr "type" "stm")])
1535
1536
1537 (define_insn "*store_multiple_si"
1538 [(match_parallel 0 "store_multiple_operation"
1539 [(set (match_operand:SI 1 "s_operand" "=oQ")
1540 (match_operand:SI 2 "register_operand" "r"))])]
1541 ""
1542 "*
1543 {
1544 int words = XVECLEN (operands[0], 0);
1545
1546 if (XVECLEN (operands[0], 0) == 1)
1547 return \"st\\t%1,0(%2)\";
1548
1549 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1550 return \"stm\\t%2,%0,%1\";
1551 }"
1552 [(set_attr "op_type" "RXE")
1553 (set_attr "atype" "mem")
1554 (set_attr "type" "stm")])
1555
1556 ;;
1557 ;; String instructions.
1558 ;;
1559
1560 ;
1561 ; movstrdi instruction pattern(s).
1562 ;
1563
1564 (define_expand "movstrdi"
1565 [(set (match_operand:BLK 0 "general_operand" "")
1566 (match_operand:BLK 1 "general_operand" ""))
1567 (use (match_operand:DI 2 "general_operand" ""))
1568 (match_operand 3 "" "")]
1569 "TARGET_64BIT"
1570 "
1571 {
1572 rtx addr0, addr1;
1573
1574 addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1575 addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1576
1577 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1578 {
1579 operands[0] = change_address (operands[0], VOIDmode, addr0);
1580 operands[1] = change_address (operands[1], VOIDmode, addr1);
1581 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1582
1583 emit_insn (gen_movstrsico (operands[0], operands[1], operands[2]));
1584 DONE;
1585 }
1586 else
1587 {
1588 if (TARGET_MVCLE)
1589 {
1590 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1591 rtx reg0 = gen_reg_rtx (TImode);
1592 rtx reg1 = gen_reg_rtx (TImode);
1593 rtx len = operands[2];
1594
1595 if (! CONSTANT_P (len))
1596 len = force_reg (DImode, len);
1597
1598 /* Load up the address+length pairs. */
1599
1600 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1601 emit_move_insn (gen_lowpart (DImode, reg0), len);
1602
1603 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1604 emit_move_insn (gen_lowpart (DImode, reg1), len);
1605
1606 /* MOVE */
1607 emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
1608 DONE;
1609 }
1610 else
1611 {
1612 rtx label = gen_label_rtx ();
1613 rtx reg0, reg1, len;
1614
1615 reg0 = gen_reg_rtx (DImode);
1616 reg1 = gen_reg_rtx (DImode);
1617 len = gen_reg_rtx (DImode);
1618
1619 emit_move_insn (len, operands[2]);
1620 emit_insn (gen_cmpdi (len, const0_rtx));
1621 emit_jump_insn (gen_beq (label));
1622 emit_move_insn (reg0, addr0);
1623 emit_move_insn (reg1, addr1);
1624 emit_insn (gen_adddi3 (len, len, constm1_rtx));
1625 emit_insn (gen_movstrdix_64 (reg0, reg1, reg0, reg1, len));
1626 emit_label (label);
1627 DONE;
1628 }
1629 }
1630 }")
1631
1632 ;
1633 ; movstrsi instruction pattern(s).
1634 ;
1635
1636 (define_expand "movstrsi"
1637 [(set (match_operand:BLK 0 "general_operand" "")
1638 (match_operand:BLK 1 "general_operand" ""))
1639 (use (match_operand:SI 2 "general_operand" ""))
1640 (match_operand 3 "" "")]
1641 ""
1642 "
1643 {
1644 rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1645 rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1646
1647 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1648 {
1649 operands[0] = change_address (operands[0], VOIDmode, addr0);
1650 operands[1] = change_address (operands[1], VOIDmode, addr1);
1651 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1652
1653 emit_insn (gen_movstrsico (operands[0], operands[1], operands[2]));
1654 DONE;
1655 }
1656 else
1657 {
1658 if (TARGET_64BIT)
1659 FAIL;
1660
1661 if (TARGET_MVCLE)
1662 {
1663 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1664 rtx reg0 = gen_reg_rtx (DImode);
1665 rtx reg1 = gen_reg_rtx (DImode);
1666 rtx len = operands[2];
1667
1668
1669 if (! CONSTANT_P (len))
1670 len = force_reg (SImode, len);
1671
1672 /* Load up the address+length pairs. */
1673
1674 emit_move_insn (gen_highpart (SImode, reg0), addr0);
1675 emit_move_insn (gen_lowpart (SImode, reg0), len);
1676
1677 emit_move_insn (gen_highpart (SImode, reg1), addr1);
1678 emit_move_insn (gen_lowpart (SImode, reg1), len);
1679
1680 /* MOVE */
1681 emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
1682 DONE;
1683 }
1684 else
1685 {
1686 rtx label = gen_label_rtx ();
1687 rtx reg0, reg1, len;
1688
1689 reg0 = gen_reg_rtx (SImode);
1690 reg1 = gen_reg_rtx (SImode);
1691 len = gen_reg_rtx (SImode);
1692
1693 emit_move_insn (len, operands[2]);
1694 emit_insn (gen_cmpsi (len, const0_rtx));
1695 emit_jump_insn (gen_beq (label));
1696 emit_move_insn (reg0, addr0);
1697 emit_move_insn (reg1, addr1);
1698 emit_insn (gen_addsi3 (len, len, constm1_rtx));
1699 emit_insn (gen_movstrsix_31 (reg0, reg1, reg0, reg1, len));
1700 emit_label (label);
1701 DONE;
1702 }
1703 }
1704 }")
1705
1706 ; Move a block that is less than 256 bytes in length.
1707
1708 (define_insn "movstrsico"
1709 [(set (match_operand:BLK 0 "s_operand" "=oQ")
1710 (match_operand:BLK 1 "s_operand" "oQ"))
1711 (use (match_operand 2 "const_int_operand" "I"))]
1712 "((unsigned) INTVAL (operands[2]) < 256)"
1713 "mvc\\t%O0(%c2+1,%R0),%1"
1714 [(set_attr "op_type" "SS")
1715 (set_attr "atype" "mem")])
1716
1717 ; Move a block that is more than 256 bytes in lenght or length in register
1718
1719 (define_insn "movstrdix_64"
1720 [(clobber (match_operand:DI 0 "register_operand" "=a"))
1721 (clobber (match_operand:DI 1 "register_operand" "=a"))
1722 (set (mem:BLK (match_operand:DI 2 "register_operand" "0"))
1723 (mem:BLK (match_operand:DI 3 "register_operand" "1")))
1724 (use (match_operand:DI 4 "register_operand" "a"))
1725 (clobber (match_scratch:DI 5 "=&a"))
1726 (clobber (reg:CC 33))]
1727 ""
1728 "*
1729 {
1730 rtx xop[4];
1731 xop[0] = gen_label_rtx ();
1732 xop[1] = gen_label_rtx ();
1733 xop[2] = gen_label_rtx ();
1734 xop[3] = operands[5];
1735 output_asm_insn (\"srag\\t%5,%4,8\", operands);
1736 output_asm_insn (\"jz\\t%l1\", xop);
1737 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1738 CODE_LABEL_NUMBER (xop[0]));
1739 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1740 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1741 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1742 output_asm_insn (\"brct\\t%3,%l0\", xop);
1743 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1744 CODE_LABEL_NUMBER (xop[1]));
1745 output_asm_insn (\"bras\\t%3,%l2\", xop);
1746 output_asm_insn (\"mvc\\t0(1,%0),0(%1)\", operands);
1747 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1748 CODE_LABEL_NUMBER (xop[2]));
1749 return \"ex\\t%4,0(%5)\";
1750 }"
1751 [(set_attr "op_type" "NN")
1752 (set_attr "atype" "mem")
1753 (set_attr "length" "44")])
1754
1755 (define_insn "movstrsix_31"
1756 [(clobber (match_operand:SI 0 "register_operand" "=a"))
1757 (clobber (match_operand:SI 1 "register_operand" "=a"))
1758 (set (mem:BLK (match_operand:SI 2 "register_operand" "0"))
1759 (mem:BLK (match_operand:SI 3 "register_operand" "1")))
1760 (use (match_operand:SI 4 "register_operand" "a"))
1761 (clobber (match_scratch:SI 5 "=&a"))
1762 (clobber (reg:CC 33))]
1763 ""
1764 "*
1765 {
1766 rtx xop[4];
1767 xop[0] = gen_label_rtx ();
1768 xop[1] = gen_label_rtx ();
1769 xop[2] = gen_label_rtx ();
1770 xop[3] = operands[5];
1771 output_asm_insn (\"lr\\t%5,%4\", operands);
1772 output_asm_insn (\"sra\\t%5,8\", operands);
1773 output_asm_insn (\"jz\\t%l1\", xop);
1774 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1775 CODE_LABEL_NUMBER (xop[0]));
1776 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1777 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1778 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1779 output_asm_insn (\"brct\\t%3,%l0\", xop);
1780 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1781 CODE_LABEL_NUMBER (xop[1]));
1782 output_asm_insn (\"bras\\t%3,%l2\", xop);
1783 output_asm_insn (\"mvc\\t0(1,%0),0(%1)\", operands);
1784 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1785 CODE_LABEL_NUMBER (xop[2]));
1786 return \"ex\\t%4,0(%5)\";
1787 }"
1788 [(set_attr "op_type" "NN")
1789 (set_attr "length" "42")
1790 (set_attr "atype" "mem")])
1791
1792 ; Move a block that is larger than 255 bytes in length.
1793
1794 (define_insn "movstrdi_64"
1795 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1796 (clobber (match_operand:TI 1 "register_operand" "=d"))
1797 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1798 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1799 (clobber (reg:CC 33))]
1800 ""
1801 "mvcle\\t%0,%1,0\;jo\\t.-4"
1802 [(set_attr "op_type" "NN")
1803 (set_attr "atype" "mem")
1804 (set_attr "length" "8")])
1805
1806 (define_insn "movstrsi_31"
1807 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1808 (clobber (match_operand:DI 1 "register_operand" "=d"))
1809 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1810 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1811 (clobber (reg:CC 33))]
1812 ""
1813 "mvcle\\t%0,%1,0\;jo\\t.-4"
1814 [(set_attr "op_type" "NN")
1815 (set_attr "atype" "mem")
1816 (set_attr "length" "8")])
1817
1818 ;
1819 ; clrstrdi instruction pattern(s).
1820 ;
1821
1822 (define_expand "clrstrdi"
1823 [(set (match_operand:BLK 0 "general_operand" "")
1824 (const_int 0))
1825 (use (match_operand:DI 1 "general_operand" ""))
1826 (match_operand 2 "" "")]
1827 "TARGET_64BIT"
1828 "
1829 {
1830 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1831
1832 operands[0] = change_address (operands[0], VOIDmode, addr);
1833
1834 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1835 {
1836 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1837 DONE;
1838 }
1839 else
1840 {
1841 rtx reg0 = gen_reg_rtx (TImode);
1842 rtx reg1 = gen_reg_rtx (TImode);
1843 rtx len = operands[1];
1844
1845 if (! CONSTANT_P (len))
1846 len = force_reg (DImode, len);
1847
1848 /* Load up the address+length pairs. */
1849
1850 emit_move_insn (gen_highpart (DImode, reg0), addr);
1851 emit_move_insn (gen_lowpart (DImode, reg0), len);
1852
1853 emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
1854
1855 /* Clear! */
1856 emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0, reg1));
1857 DONE;
1858 }
1859 }")
1860
1861 ;
1862 ; clrstrsi instruction pattern(s).
1863 ;
1864
1865 (define_expand "clrstrsi"
1866 [(set (match_operand:BLK 0 "general_operand" "")
1867 (const_int 0))
1868 (use (match_operand:SI 1 "general_operand" ""))
1869 (match_operand 2 "" "")]
1870 "!TARGET_64BIT"
1871 "
1872 {
1873 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1874
1875 operands[0] = change_address (operands[0], VOIDmode, addr);
1876
1877 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1878 {
1879 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1880 DONE;
1881 }
1882 else
1883 {
1884 rtx reg0 = gen_reg_rtx (DImode);
1885 rtx reg1 = gen_reg_rtx (DImode);
1886 rtx len = operands[1];
1887
1888 if (! CONSTANT_P (len))
1889 len = force_reg (SImode, len);
1890
1891 /* Load up the address+length pairs. */
1892
1893 emit_move_insn (gen_highpart (SImode, reg0), addr);
1894 emit_move_insn (gen_lowpart (SImode, reg0), len);
1895
1896 emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
1897
1898 /* CLear! */
1899 emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0, reg1));
1900 DONE;
1901 }
1902 }")
1903
1904 ; Clear memory with length less than 256 bytes
1905
1906 (define_insn "clrstrsico"
1907 [(set (match_operand:BLK 0 "s_operand" "=Qo")
1908 (const_int 0))
1909 (use (match_operand 1 "immediate_operand" "I"))
1910 (clobber (reg:CC 33))]
1911 ""
1912 "xc\\t%O0(%1,%R0),%0"
1913 [(set_attr "op_type" "RS")
1914 (set_attr "type" "cs")
1915 (set_attr "atype" "mem")])
1916
1917 ; Clear memory with length greater 256 bytes or lenght not constant
1918
1919 (define_insn "clrstrsi_64"
1920 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1921 (clobber (match_operand:TI 1 "register_operand" "=d"))
1922 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1923 (const_int 0))
1924 (use (match_operand:TI 3 "register_operand" "1"))
1925 (clobber (reg:CC 33))]
1926 "TARGET_64BIT"
1927 "mvcle\\t%0,%1,0\;jo\\t.-4"
1928 [(set_attr "op_type" "NN")
1929 (set_attr "atype" "mem")
1930 (set_attr "type" "vs")
1931 (set_attr "length" "8")])
1932
1933 (define_insn "clrstrsi_31"
1934 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1935 (clobber (match_operand:DI 1 "register_operand" "=d"))
1936 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1937 (const_int 0))
1938 (use (match_operand:DI 3 "register_operand" "1"))
1939 (clobber (reg:CC 33))]
1940 "!TARGET_64BIT"
1941 "mvcle\\t%0,%1,0\;jo\\t.-4"
1942 [(set_attr "op_type" "NN")
1943 (set_attr "atype" "mem")
1944 (set_attr "type" "vs")
1945 (set_attr "length" "8")])
1946
1947 ;
1948 ; cmpstrdi instruction pattern(s).
1949 ;
1950
1951 (define_expand "cmpstrdi"
1952 [(set (match_operand:DI 0 "register_operand" "")
1953 (compare:DI (match_operand:BLK 1 "s_operand" "")
1954 (match_operand:BLK 2 "s_operand" "") ) )
1955 (use (match_operand:DI 3 "general_operand" ""))
1956 (use (match_operand:DI 4 "" ""))]
1957 "TARGET_64BIT"
1958 "
1959 {
1960 rtx addr0, addr1;
1961
1962 /* for pre/post increment */
1963 operands[1] = protect_from_queue (operands[1], 0);
1964 operands[2] = protect_from_queue (operands[2], 0);
1965 operands[3] = protect_from_queue (operands[3], 0);
1966
1967 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1968 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1969
1970 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1971 {
1972 if (INTVAL (operands[3]) == 0) {
1973 emit_move_insn (operands[0], operands[3]);
1974 DONE;
1975 }
1976
1977 operands[1] = change_address (operands[1], VOIDmode, addr0);
1978 operands[2] = change_address (operands[2], VOIDmode, addr1);
1979
1980 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1981 emit_insn (gen_cmpint_di (operands[0]));
1982 DONE;
1983 }
1984 else
1985 {
1986 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1987 rtx reg0 = gen_reg_rtx (TImode);
1988 rtx reg1 = gen_reg_rtx (TImode);
1989 rtx len = operands[3];
1990
1991 if (! CONSTANT_P (len))
1992 len = force_reg (DImode, len);
1993
1994 /* Load up the address+length pairs. */
1995 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1996 emit_move_insn (gen_lowpart (DImode, reg0), len);
1997
1998 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1999 emit_move_insn (gen_lowpart (DImode, reg1), len);
2000
2001 /* Compare! */
2002 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2003 emit_insn (gen_cmpint_di (operands[0]));
2004 DONE;
2005 }
2006 }")
2007
2008 ;
2009 ; cmpstrsi instruction pattern(s).
2010 ;
2011
2012 (define_expand "cmpstrsi"
2013 [(set (match_operand:SI 0 "register_operand" "")
2014 (compare:SI (match_operand:BLK 1 "s_operand" "")
2015 (match_operand:BLK 2 "s_operand" "") ) )
2016 (use (match_operand:SI 3 "general_operand" ""))
2017 (use (match_operand:SI 4 "" ""))]
2018 ""
2019 "
2020 {
2021 rtx addr0, addr1;
2022
2023 /* for pre/post increment */
2024 operands[1] = protect_from_queue (operands[1], 0);
2025 operands[2] = protect_from_queue (operands[2], 0);
2026 operands[3] = protect_from_queue (operands[3], 0);
2027
2028 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2029 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2030
2031 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2032 {
2033 if (INTVAL (operands[3]) == 0) {
2034 emit_move_insn (operands[0], operands[3]);
2035 DONE;
2036 }
2037
2038 operands[1] = change_address (operands[1], VOIDmode, addr0);
2039 operands[2] = change_address (operands[2], VOIDmode, addr1);
2040
2041 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2042 emit_insn (gen_cmpint_si (operands[0]));
2043 DONE;
2044 }
2045 else
2046 {
2047 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2048 rtx reg0, reg1;
2049 rtx len = operands[3];
2050
2051 if (TARGET_64BIT)
2052 {
2053 reg0 = gen_reg_rtx (TImode);
2054 reg1 = gen_reg_rtx (TImode);
2055 }
2056 else
2057 {
2058 reg0 = gen_reg_rtx (DImode);
2059 reg1 = gen_reg_rtx (DImode);
2060 }
2061
2062 if (! CONSTANT_P (len))
2063 len = force_reg (Pmode, len);
2064
2065 /* Load up the address+length pairs. */
2066 emit_move_insn (gen_highpart (Pmode, reg0), addr0);
2067 emit_move_insn (gen_lowpart (Pmode, reg0), len);
2068
2069 emit_move_insn (gen_highpart (Pmode, reg1), addr1);
2070 emit_move_insn (gen_lowpart (Pmode, reg1), len);
2071
2072 /* Compare! */
2073 if (TARGET_64BIT)
2074 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2075 else
2076 emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
2077
2078 emit_insn (gen_cmpint_si (operands[0]));
2079 DONE;
2080 }
2081 }")
2082
2083 ; Compare a block that is less than 256 bytes in length.
2084
2085 (define_insn "cmpstr_const"
2086 [(set (reg:CCS 33)
2087 (compare:CCS (match_operand:BLK 0 "s_operand" "oQ")
2088 (match_operand:BLK 1 "s_operand" "oQ")))
2089 (use (match_operand 2 "immediate_operand" "I"))]
2090 "(unsigned) INTVAL (operands[2]) < 256"
2091 "clc\\t%O0(%c2,%R0),%1"
2092 [(set_attr "op_type" "SS")
2093 (set_attr "atype" "mem")
2094 (set_attr "type" "cs")])
2095
2096 ; Compare a block that is larger than 255 bytes in length.
2097
2098 (define_insn "cmpstr_64"
2099 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2100 (clobber (match_operand:TI 1 "register_operand" "=d"))
2101 (set (reg:CCS 33)
2102 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2103 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))]
2104 "TARGET_64BIT"
2105 "clcl\\t%0,%1"
2106 [(set_attr "op_type" "RR")
2107 (set_attr "atype" "mem")
2108 (set_attr "type" "vs")])
2109
2110 (define_insn "cmpstr_31"
2111 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2112 (clobber (match_operand:DI 1 "register_operand" "=d"))
2113 (set (reg:CCS 33)
2114 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2115 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))]
2116 "!TARGET_64BIT"
2117 "clcl\\t%0,%1"
2118 [(set_attr "op_type" "RR")
2119 (set_attr "atype" "mem")
2120 (set_attr "type" "vs")])
2121
2122 ; Convert condition code to integer in range (-1, 0, 1)
2123
2124 (define_insn "cmpint_si"
2125 [(set (match_operand:SI 0 "register_operand" "=d")
2126 (compare:SI (reg:CCS 33) (const_int 0)))]
2127 ""
2128 "*
2129 {
2130 output_asm_insn (\"lhi\\t%0,1\", operands);
2131 output_asm_insn (\"jh\\t.+12\", operands);
2132 output_asm_insn (\"jl\\t.+6\", operands);
2133 output_asm_insn (\"sr\\t%0,%0\", operands);
2134 return \"lcr\\t%0,%0\";
2135 }"
2136 [(set_attr "op_type" "NN")
2137 (set_attr "length" "16")
2138 (set_attr "atype" "reg")
2139 (set_attr "type" "other")])
2140
2141 (define_insn "cmpint_di"
2142 [(set (match_operand:DI 0 "register_operand" "=d")
2143 (compare:DI (reg:CCS 33) (const_int 0)))]
2144 "TARGET_64BIT"
2145 "*
2146 {
2147 output_asm_insn (\"lghi\\t%0,1\", operands);
2148 output_asm_insn (\"jh\\t.+12\", operands);
2149 output_asm_insn (\"jl\\t.+6\", operands);
2150 output_asm_insn (\"sgr\\t%0,%0\", operands);
2151 return \"lcgr\\t%0,%0\";
2152 }"
2153 [(set_attr "op_type" "NN")
2154 (set_attr "length" "22")
2155 (set_attr "atype" "reg")
2156 (set_attr "type" "other")])
2157
2158
2159 ;;
2160 ;;- Conversion instructions.
2161 ;;
2162
2163 (define_insn "*sethighqisi"
2164 [(set (match_operand:SI 0 "register_operand" "=d")
2165 (unspec:SI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2166 (clobber (reg:CC 33))]
2167 ""
2168 "icm\\t%0,8,%1"
2169 [(set_attr "op_type" "RS")
2170 (set_attr "atype" "mem")])
2171
2172 (define_insn "*sethighhisi"
2173 [(set (match_operand:SI 0 "register_operand" "=d")
2174 (unspec:SI [(match_operand:HI 1 "s_operand" "Qo")] 10))
2175 (clobber (reg:CC 33))]
2176 ""
2177 "icm\\t%0,12,%1"
2178 [(set_attr "op_type" "RS")
2179 (set_attr "atype" "mem")])
2180
2181 (define_insn "*sethighqidi_64"
2182 [(set (match_operand:DI 0 "register_operand" "=d")
2183 (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2184 (clobber (reg:CC 33))]
2185 "TARGET_64BIT"
2186 "icmh\\t%0,8,%1"
2187 [(set_attr "op_type" "RSE")
2188 (set_attr "atype" "mem")])
2189
2190 (define_insn "*sethighqidi_31"
2191 [(set (match_operand:DI 0 "register_operand" "=d")
2192 (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2193 (clobber (reg:CC 33))]
2194 "!TARGET_64BIT"
2195 "icm\\t%0,8,%1"
2196 [(set_attr "op_type" "RS")
2197 (set_attr "atype" "mem")])
2198
2199 (define_split
2200 [(set (match_operand:SI 0 "register_operand" "")
2201 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2202 (match_operand 2 "const_int_operand" "")
2203 (const_int 0)))]
2204 "!TARGET_64BIT && !reload_completed
2205 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2206 [(parallel
2207 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2208 (clobber (reg:CC 33))])
2209 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2210 "
2211 {
2212 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2213 operands[1] = change_address (operands[1], QImode, 0);
2214 }")
2215
2216 (define_split
2217 [(set (match_operand:SI 0 "register_operand" "")
2218 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2219 (match_operand 2 "const_int_operand" "")
2220 (const_int 0)))]
2221 "!TARGET_64BIT && !reload_completed
2222 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2223 [(parallel
2224 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2225 (clobber (reg:CC 33))])
2226 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2227 "
2228 {
2229 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2230 operands[1] = change_address (operands[1], HImode, 0);
2231 }")
2232
2233 ;
2234 ; extendsidi2 instruction pattern(s).
2235 ;
2236
2237 (define_expand "extendsidi2"
2238 [(set (match_operand:DI 0 "register_operand" "")
2239 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2240 ""
2241 "
2242 {
2243 if (!TARGET_64BIT)
2244 {
2245 rtx insns, subword;
2246
2247 operands[1] = force_reg (SImode, operands[1]);
2248 subword = operand_subword (operands[0], 0, 1, DImode);
2249
2250 start_sequence ();
2251 emit_move_insn (subword, operands[1]);
2252 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2253 insns = get_insns ();
2254 end_sequence ();
2255
2256 emit_no_conflict_block (insns, operands[0], operands[1], 0,
2257 gen_rtx_SIGN_EXTEND (DImode, operands[1]));
2258
2259 /* Avoid having the REG_RETVAL destroyed by someone attaching
2260 other REG_EQUAL notes. */
2261 emit_move_insn (operands[0], operands[0]);
2262 DONE;
2263 }
2264 }
2265 ")
2266
2267 (define_insn "*extendsidi2"
2268 [(set (match_operand:DI 0 "register_operand" "=d,d")
2269 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2270 "TARGET_64BIT"
2271 "@
2272 lgfr\\t%0,%1
2273 lgf\\t%0,%1"
2274 [(set_attr "op_type" "RRE,RXE")
2275 (set_attr "atype" "reg,mem")])
2276
2277 ;
2278 ; extendhidi2 instruction pattern(s).
2279 ;
2280
2281 (define_expand "extendhidi2"
2282 [(set (match_operand:DI 0 "register_operand" "")
2283 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2284 ""
2285 "
2286 {
2287 if (!TARGET_64BIT)
2288 {
2289 rtx tmp = gen_reg_rtx (SImode);
2290 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2291 emit_insn (gen_extendsidi2 (operands[0], tmp));
2292 DONE;
2293 }
2294 else
2295 {
2296 operands[1] = gen_lowpart (DImode, operands[1]);
2297 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2298 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2299 DONE;
2300 }
2301 }
2302 ")
2303
2304 (define_insn "*extendhidi2"
2305 [(set (match_operand:DI 0 "register_operand" "=d")
2306 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2307 "TARGET_64BIT"
2308 "lgh\\t%0,%1"
2309 [(set_attr "op_type" "RXE")
2310 (set_attr "atype" "mem")])
2311
2312 ;
2313 ; extendqidi2 instruction pattern(s).
2314 ;
2315
2316 (define_expand "extendqidi2"
2317 [(set (match_operand:DI 0 "register_operand" "")
2318 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2319 ""
2320 "
2321 {
2322 if (!TARGET_64BIT)
2323 {
2324 rtx tmp = gen_reg_rtx (SImode);
2325 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2326 emit_insn (gen_extendsidi2 (operands[0], tmp));
2327 DONE;
2328 }
2329 else
2330 {
2331 operands[1] = gen_lowpart (DImode, operands[1]);
2332 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2333 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2334 DONE;
2335 }
2336 }
2337 ")
2338
2339 (define_split
2340 [(set (match_operand:DI 0 "register_operand" "")
2341 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2342 "TARGET_64BIT && !reload_completed"
2343 [(parallel
2344 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2345 (clobber (reg:CC 33))])
2346 (parallel
2347 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2348 (clobber (reg:CC 33))])]
2349 "")
2350
2351 ;
2352 ; extendhisi2 instruction pattern(s).
2353 ;
2354
2355 (define_expand "extendhisi2"
2356 [(set (match_operand:SI 0 "register_operand" "")
2357 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2358 ""
2359 "
2360 {
2361 operands[1] = gen_lowpart (SImode, operands[1]);
2362 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2363 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2364 DONE;
2365 }
2366 ")
2367
2368 (define_insn "*extendhisi2"
2369 [(set (match_operand:SI 0 "register_operand" "=d")
2370 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2371 ""
2372 "lh\\t%0,%1"
2373 [(set_attr "op_type" "RX")
2374 (set_attr "atype" "mem")])
2375
2376 ;
2377 ; extendqisi2 instruction pattern(s).
2378 ;
2379
2380 (define_expand "extendqisi2"
2381 [(set (match_operand:SI 0 "register_operand" "")
2382 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2383 ""
2384 "
2385 {
2386 operands[1] = gen_lowpart (SImode, operands[1]);
2387 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2388 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2389 DONE;
2390 }
2391 ")
2392
2393 (define_split
2394 [(set (match_operand:SI 0 "register_operand" "")
2395 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2396 "!reload_completed"
2397 [(parallel
2398 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2399 (clobber (reg:CC 33))])
2400 (parallel
2401 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2402 (clobber (reg:CC 33))])]
2403 "")
2404
2405 ;
2406 ; extendqihi2 instruction pattern(s).
2407 ;
2408
2409
2410 ;
2411 ; zero_extendsidi2 instruction pattern(s).
2412 ;
2413
2414 (define_expand "zero_extendsidi2"
2415 [(set (match_operand:DI 0 "register_operand" "")
2416 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2417 ""
2418 "
2419 {
2420 if (!TARGET_64BIT)
2421 {
2422 rtx insns, subword;
2423
2424 operands[1] = force_reg (SImode, operands[1]);
2425 subword = operand_subword (operands[0], 0, 1, DImode);
2426
2427 start_sequence ();
2428 emit_move_insn (subword, operands[1]);
2429 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (32)));
2430 insns = get_insns ();
2431 end_sequence ();
2432
2433 emit_no_conflict_block (insns, operands[0], operands[1], 0,
2434 gen_rtx_ZERO_EXTEND (DImode, operands[1]));
2435
2436 /* Avoid having the REG_RETVAL destroyed by someone attaching
2437 other REG_EQUAL notes. */
2438 emit_move_insn (operands[0], operands[0]);
2439 DONE;
2440 }
2441 }
2442 ")
2443
2444 (define_insn "*zero_extendsidi2"
2445 [(set (match_operand:DI 0 "register_operand" "=d,d")
2446 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2447 "TARGET_64BIT"
2448 "@
2449 llgfr\\t%0,%1
2450 llgf\\t%0,%1"
2451 [(set_attr "op_type" "RRE,RXE")
2452 (set_attr "atype" "reg,mem")])
2453
2454 ;
2455 ; zero_extendhidi2 instruction pattern(s).
2456 ;
2457
2458 (define_expand "zero_extendhidi2"
2459 [(set (match_operand:DI 0 "register_operand" "")
2460 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2461 ""
2462 "
2463 {
2464 if (!TARGET_64BIT)
2465 {
2466 rtx tmp = gen_reg_rtx (SImode);
2467 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2468 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2469 DONE;
2470 }
2471 else
2472 {
2473 operands[1] = gen_lowpart (DImode, operands[1]);
2474 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2475 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2476 DONE;
2477 }
2478 }
2479 ")
2480
2481 (define_insn "*zero_extendhidi2"
2482 [(set (match_operand:DI 0 "register_operand" "=d")
2483 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2484 "TARGET_64BIT"
2485 "llgh\\t%0,%1"
2486 [(set_attr "op_type" "RXE")
2487 (set_attr "atype" "mem")])
2488
2489 ;
2490 ; zero_extendqidi2 instruction pattern(s)
2491 ;
2492
2493 (define_expand "zero_extendqidi2"
2494 [(set (match_operand:DI 0 "register_operand" "")
2495 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2496 ""
2497 "
2498 {
2499 if (!TARGET_64BIT)
2500 {
2501 rtx tmp = gen_reg_rtx (SImode);
2502 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2503 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2504 DONE;
2505 }
2506 else
2507 {
2508 operands[1] = gen_lowpart (DImode, operands[1]);
2509 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2510 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2511 DONE;
2512 }
2513 }
2514 ")
2515
2516 (define_insn "*zero_extendqidi2"
2517 [(set (match_operand:DI 0 "register_operand" "=d")
2518 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2519 "TARGET_64BIT"
2520 "llgc\\t%0,%1"
2521 [(set_attr "op_type" "RXE")
2522 (set_attr "atype" "mem")])
2523
2524 ;
2525 ; zero_extendhisi2 instruction pattern(s).
2526 ;
2527
2528 (define_expand "zero_extendhisi2"
2529 [(set (match_operand:SI 0 "register_operand" "")
2530 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2531 ""
2532 "
2533 {
2534 operands[1] = gen_lowpart (SImode, operands[1]);
2535 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2536 DONE;
2537 }
2538 ")
2539
2540 (define_insn "*zero_extendhisi2_64"
2541 [(set (match_operand:SI 0 "register_operand" "=d")
2542 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2543 "TARGET_64BIT"
2544 "llgh\\t%0,%1"
2545 [(set_attr "op_type" "RXE")
2546 (set_attr "atype" "mem")])
2547
2548 ;
2549 ; zero_extendqisi2 instruction pattern(s).
2550 ;
2551
2552 (define_expand "zero_extendqisi2"
2553 [(set (match_operand:SI 0 "register_operand" "")
2554 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2555 ""
2556 "
2557 {
2558 operands[1] = gen_lowpart (SImode, operands[1]);
2559 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2560 DONE;
2561 }
2562 ")
2563
2564 (define_insn "*zero_extendqisi2_64"
2565 [(set (match_operand:SI 0 "register_operand" "=d")
2566 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2567 "TARGET_64BIT"
2568 "llgc\\t%0,%1"
2569 [(set_attr "op_type" "RXE")
2570 (set_attr "atype" "mem")])
2571
2572 ;
2573 ; zero_extendqihi2 instruction pattern(s).
2574 ;
2575
2576 (define_expand "zero_extendqihi2"
2577 [(set (match_operand:HI 0 "register_operand" "")
2578 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2579 "TARGET_64BIT"
2580 "
2581 {
2582 operands[1] = gen_lowpart (HImode, operands[1]);
2583 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2584 DONE;
2585 }
2586 ")
2587
2588 (define_insn "*zero_extendqihi2_64"
2589 [(set (match_operand:HI 0 "register_operand" "=d")
2590 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2591 (clobber (reg:CC 33))]
2592 "TARGET_64BIT"
2593 "llgc\\t%0,%1"
2594 [(set_attr "op_type" "RXE")
2595 (set_attr "atype" "mem")])
2596
2597 ;
2598 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2599 ;
2600
2601 (define_expand "fixuns_truncdfdi2"
2602 [(set (match_operand:DI 0 "register_operand" "")
2603 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2604 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2605 "
2606 {
2607 rtx label1 = gen_label_rtx ();
2608 rtx label2 = gen_label_rtx ();
2609 rtx temp = gen_reg_rtx (DFmode);
2610 operands[1] = force_reg (DFmode, operands[1]);
2611
2612 emit_insn (gen_cmpdf (operands[1],
2613 CONST_DOUBLE_FROM_REAL_VALUE (
2614 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2615 emit_jump_insn (gen_blt (label1));
2616 emit_insn (gen_subdf3 (temp, operands[1],
2617 CONST_DOUBLE_FROM_REAL_VALUE (
2618 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2619 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2620 emit_jump (label2);
2621
2622 emit_label (label1);
2623 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2624 emit_label (label2);
2625 DONE;
2626 }")
2627
2628 (define_expand "fix_truncdfdi2"
2629 [(set (match_operand:DI 0 "register_operand" "")
2630 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2631 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2632 "
2633 {
2634 operands[1] = force_reg (DFmode, operands[1]);
2635 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2636 DONE;
2637 }")
2638
2639 (define_insn "fix_truncdfdi2_ieee"
2640 [(set (match_operand:DI 0 "register_operand" "=d")
2641 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2642 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2643 (clobber (reg:CC 33))]
2644 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2645 "cgdbr\\t%0,%h2,%1"
2646 [(set_attr "op_type" "RRE")
2647 (set_attr "type" "other")])
2648
2649 ;
2650 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2651 ;
2652
2653 (define_expand "fixuns_truncdfsi2"
2654 [(set (match_operand:SI 0 "register_operand" "")
2655 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2656 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2657 "
2658 {
2659 rtx label1 = gen_label_rtx ();
2660 rtx label2 = gen_label_rtx ();
2661 rtx temp = gen_reg_rtx (DFmode);
2662
2663 operands[1] = force_reg (DFmode,operands[1]);
2664 emit_insn (gen_cmpdf (operands[1],
2665 CONST_DOUBLE_FROM_REAL_VALUE (
2666 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2667 emit_jump_insn (gen_blt (label1));
2668 emit_insn (gen_subdf3 (temp, operands[1],
2669 CONST_DOUBLE_FROM_REAL_VALUE (
2670 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2671 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2672 emit_jump (label2);
2673
2674 emit_label (label1);
2675 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2676 emit_label (label2);
2677 DONE;
2678 }")
2679
2680 (define_expand "fix_truncdfsi2"
2681 [(set (match_operand:SI 0 "register_operand" "")
2682 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2683 "TARGET_HARD_FLOAT"
2684 "
2685 {
2686 if (TARGET_IBM_FLOAT)
2687 {
2688 /* This is the algorithm from POP chapter A.5.7.2. */
2689
2690 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2691 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2692 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2693
2694 operands[1] = force_reg (DFmode, operands[1]);
2695 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2696 two31r, two32, temp));
2697 }
2698 else
2699 {
2700 operands[1] = force_reg (DFmode, operands[1]);
2701 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2702 }
2703
2704 DONE;
2705 }")
2706
2707 (define_insn "fix_truncdfsi2_ieee"
2708 [(set (match_operand:SI 0 "register_operand" "=d")
2709 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2710 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2711 (clobber (reg:CC 33))]
2712 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2713 "cfdbr\\t%0,%h2,%1"
2714 [(set_attr "op_type" "RRE")
2715 (set_attr "type" "other" )])
2716
2717 (define_insn "fix_truncdfsi2_ibm"
2718 [(set (match_operand:SI 0 "register_operand" "=d")
2719 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2720 (use (match_operand:DI 2 "immediate_operand" "m"))
2721 (use (match_operand:DI 3 "immediate_operand" "m"))
2722 (use (match_operand:BLK 4 "memory_operand" "m"))
2723 (clobber (reg:CC 33))]
2724 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2725 "*
2726 {
2727 output_asm_insn (\"sd\\t%1,%2\", operands);
2728 output_asm_insn (\"aw\\t%1,%3\", operands);
2729 output_asm_insn (\"std\\t%1,%4\", operands);
2730 output_asm_insn (\"xi\\t%N4,128\", operands);
2731 return \"l\\t%0,%N4\";
2732 }"
2733 [(set_attr "op_type" "NN")
2734 (set_attr "type" "other")
2735 (set_attr "length" "20")])
2736
2737 ;
2738 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2739 ;
2740
2741 (define_expand "fixuns_truncsfdi2"
2742 [(set (match_operand:DI 0 "register_operand" "")
2743 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2744 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2745 "
2746 {
2747 rtx label1 = gen_label_rtx ();
2748 rtx label2 = gen_label_rtx ();
2749 rtx temp = gen_reg_rtx (SFmode);
2750
2751 operands[1] = force_reg (SFmode, operands[1]);
2752 emit_insn (gen_cmpsf (operands[1],
2753 CONST_DOUBLE_FROM_REAL_VALUE (
2754 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2755 emit_jump_insn (gen_blt (label1));
2756
2757 emit_insn (gen_subsf3 (temp, operands[1],
2758 CONST_DOUBLE_FROM_REAL_VALUE (
2759 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2760 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2761 emit_jump (label2);
2762
2763 emit_label (label1);
2764 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2765 emit_label (label2);
2766 DONE;
2767 }")
2768
2769 (define_expand "fix_truncsfdi2"
2770 [(set (match_operand:DI 0 "register_operand" "")
2771 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2772 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2773 "
2774 {
2775 operands[1] = force_reg (SFmode, operands[1]);
2776 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2777 DONE;
2778 }")
2779
2780 (define_insn "fix_truncsfdi2_ieee"
2781 [(set (match_operand:DI 0 "register_operand" "=d")
2782 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2783 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2784 (clobber (reg:CC 33))]
2785 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2786 "cgebr\\t%0,%h2,%1"
2787 [(set_attr "op_type" "RRE")
2788 (set_attr "type" "other")])
2789
2790 ;
2791 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2792 ;
2793
2794 (define_expand "fixuns_truncsfsi2"
2795 [(set (match_operand:SI 0 "register_operand" "")
2796 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2797 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2798 "
2799 {
2800 rtx label1 = gen_label_rtx ();
2801 rtx label2 = gen_label_rtx ();
2802 rtx temp = gen_reg_rtx (SFmode);
2803
2804 operands[1] = force_reg (SFmode, operands[1]);
2805 emit_insn (gen_cmpsf (operands[1],
2806 CONST_DOUBLE_FROM_REAL_VALUE (
2807 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2808 emit_jump_insn (gen_blt (label1));
2809 emit_insn (gen_subsf3 (temp, operands[1],
2810 CONST_DOUBLE_FROM_REAL_VALUE (
2811 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2812 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2813 emit_jump (label2);
2814
2815 emit_label (label1);
2816 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2817 emit_label (label2);
2818 DONE;
2819 }")
2820
2821 (define_expand "fix_truncsfsi2"
2822 [(set (match_operand:SI 0 "register_operand" "")
2823 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2824 "TARGET_HARD_FLOAT"
2825 "
2826 {
2827 if (TARGET_IBM_FLOAT)
2828 {
2829 /* Convert to DFmode and then use the POP algorithm. */
2830 rtx temp = gen_reg_rtx (DFmode);
2831 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2832 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2833 }
2834 else
2835 {
2836 operands[1] = force_reg (SFmode, operands[1]);
2837 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2838 }
2839
2840 DONE;
2841 }")
2842
2843 (define_insn "fix_truncsfsi2_ieee"
2844 [(set (match_operand:SI 0 "register_operand" "=d")
2845 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2846 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2847 (clobber (reg:CC 33))]
2848 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2849 "cfebr\\t%0,%h2,%1"
2850 [(set_attr "op_type" "RRE")
2851 (set_attr "type" "other")])
2852
2853 ;
2854 ; floatdidf2 instruction pattern(s).
2855 ;
2856
2857 (define_insn "floatdidf2"
2858 [(set (match_operand:DF 0 "register_operand" "=f")
2859 (float:DF (match_operand:DI 1 "register_operand" "d")))
2860 (clobber (reg:CC 33))]
2861 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2862 "cdgbr\\t%0,%1"
2863 [(set_attr "op_type" "RRE")
2864 (set_attr "type" "other" )])
2865
2866 ;
2867 ; floatdisf2 instruction pattern(s).
2868 ;
2869
2870 (define_insn "floatdisf2"
2871 [(set (match_operand:SF 0 "register_operand" "=f")
2872 (float:SF (match_operand:DI 1 "register_operand" "d")))
2873 (clobber (reg:CC 33))]
2874 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2875 "cegbr\\t%0,%1"
2876 [(set_attr "op_type" "RRE")
2877 (set_attr "type" "other" )])
2878
2879 ;
2880 ; floatsidf2 instruction pattern(s).
2881 ;
2882
2883 (define_expand "floatsidf2"
2884 [(parallel
2885 [(set (match_operand:DF 0 "register_operand" "")
2886 (float:DF (match_operand:SI 1 "register_operand" "")))
2887 (clobber (reg:CC 33))])]
2888 "TARGET_HARD_FLOAT"
2889 "
2890 {
2891 if (TARGET_IBM_FLOAT)
2892 {
2893 /* This is the algorithm from POP chapter A.5.7.1. */
2894
2895 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2896 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2897
2898 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2899 DONE;
2900 }
2901 }")
2902
2903 (define_insn "floatsidf2_ieee"
2904 [(set (match_operand:DF 0 "register_operand" "=f")
2905 (float:DF (match_operand:SI 1 "register_operand" "d")))
2906 (clobber (reg:CC 33))]
2907 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2908 "cdfbr\\t%0,%1"
2909 [(set_attr "op_type" "RRE")
2910 (set_attr "type" "other" )])
2911
2912 (define_insn "floatsidf2_ibm"
2913 [(set (match_operand:DF 0 "register_operand" "=f")
2914 (float:DF (match_operand:SI 1 "register_operand" "d")))
2915 (use (match_operand:DI 2 "immediate_operand" "m"))
2916 (use (match_operand:BLK 3 "memory_operand" "m"))
2917 (clobber (reg:CC 33))]
2918 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2919 "*
2920 {
2921 output_asm_insn (\"st\\t%1,%N3\", operands);
2922 output_asm_insn (\"xi\\t%N3,128\", operands);
2923 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2924 output_asm_insn (\"ld\\t%0,%3\", operands);
2925 return \"sd\\t%0,%2\";
2926 }"
2927 [(set_attr "op_type" "NN")
2928 (set_attr "type" "other" )
2929 (set_attr "length" "20")])
2930
2931 ;
2932 ; floatsisf2 instruction pattern(s).
2933 ;
2934
2935 (define_expand "floatsisf2"
2936 [(parallel
2937 [(set (match_operand:SF 0 "register_operand" "")
2938 (float:SF (match_operand:SI 1 "register_operand" "")))
2939 (clobber (reg:CC 33))])]
2940 "TARGET_HARD_FLOAT"
2941 "
2942 {
2943 if (TARGET_IBM_FLOAT)
2944 {
2945 /* Use the POP algorithm to convert to DFmode and then truncate. */
2946 rtx temp = gen_reg_rtx (DFmode);
2947 emit_insn (gen_floatsidf2 (temp, operands[1]));
2948 emit_insn (gen_truncdfsf2 (operands[0], temp));
2949 DONE;
2950 }
2951 }")
2952
2953 (define_insn "floatsisf2_ieee"
2954 [(set (match_operand:SF 0 "register_operand" "=f")
2955 (float:SF (match_operand:SI 1 "register_operand" "d")))
2956 (clobber (reg:CC 33))]
2957 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2958 "cefbr\\t%0,%1"
2959 [(set_attr "op_type" "RRE")
2960 (set_attr "type" "other" )])
2961
2962 ;
2963 ; truncdfsf2 instruction pattern(s).
2964 ;
2965
2966 (define_expand "truncdfsf2"
2967 [(set (match_operand:SF 0 "register_operand" "")
2968 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2969 "TARGET_HARD_FLOAT"
2970 "")
2971
2972 (define_insn "truncdfsf2_ieee"
2973 [(set (match_operand:SF 0 "register_operand" "=f")
2974 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2975 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2976 "ledbr\\t%0,%1"
2977 [(set_attr "op_type" "RR")])
2978
2979 (define_insn "truncdfsf2_ibm"
2980 [(set (match_operand:SF 0 "register_operand" "=f,f")
2981 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2982 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2983 "@
2984 lrer\\t%0,%1
2985 le\\t%0,%1"
2986 [(set_attr "op_type" "RR,RX")
2987 (set_attr "atype" "reg,mem")])
2988
2989 ;
2990 ; extendsfdf2 instruction pattern(s).
2991 ;
2992
2993 (define_expand "extendsfdf2"
2994 [(set (match_operand:DF 0 "register_operand" "")
2995 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2996 "TARGET_HARD_FLOAT"
2997 "
2998 {
2999 if (TARGET_IBM_FLOAT)
3000 {
3001 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3002 DONE;
3003 }
3004 }")
3005
3006 (define_insn "extendsfdf2_ieee"
3007 [(set (match_operand:DF 0 "register_operand" "=f,f")
3008 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
3009 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3010 "@
3011 ldebr\\t%0,%1
3012 ldeb\\t%0,%1"
3013 [(set_attr "op_type" "RRE,RXE")])
3014
3015 (define_insn "extendsfdf2_ibm"
3016 [(set (match_operand:DF 0 "register_operand" "=f,f")
3017 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
3018 (clobber (reg:CC 33))]
3019 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3020 "@
3021 sdr\\t%0,%0\;ler\\t%0,%1
3022 sdr\\t%0,%0\;le\\t%0,%1"
3023 [(set_attr "op_type" "RRE,RXE")
3024 (set_attr "atype" "reg,mem")
3025 (set_attr "type" "o2,o2")])
3026
3027
3028 ;;
3029 ;; ARITHMETRIC OPERATIONS
3030 ;;
3031 ; arithmetric operations set the ConditionCode,
3032 ; because of unpredictable Bits in Register for Halfword and Byte
3033 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3034
3035 ;;
3036 ;;- Add instructions.
3037 ;;
3038
3039 ;
3040 ; adddi3 instruction pattern(s).
3041 ;
3042
3043 (define_insn "addaddr_esame"
3044 [(set (match_operand:DI 0 "register_operand" "=a,a")
3045 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
3046 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
3047 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3048 (REGNO (operands[1]) == BASE_REGISTER)) &&
3049 (GET_CODE (operands[2]) == REG ||
3050 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3051 "@
3052 la\\t%0,%c2(,%1)
3053 la\\t%0,0(%1,%2)"
3054 [(set_attr "op_type" "RX")
3055 (set_attr "atype" "mem")
3056 (set_attr "type" "la")])
3057
3058 (define_insn "adddi3_64"
3059 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3060 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3061 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3062 (clobber (reg:CC 33))]
3063 "TARGET_64BIT"
3064 "@
3065 agr\\t%0,%2
3066 aghi\\t%0,%h2
3067 ag\\t%0,%2"
3068 [(set_attr "op_type" "RRE,RI,RXE")
3069 (set_attr "atype" "reg,reg,mem")])
3070
3071 ;
3072 ; For weakness of reload, need (set (reg x) (plus (reg y) (reg x)))
3073 ;
3074
3075 (define_insn "adddi3_inv_64"
3076 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3077 (plus:DI (match_operand:DI 1 "general_operand" "%d,K,m")
3078 (match_operand:DI 2 "register_operand" "0,0,0") ) )
3079 (clobber (reg:CC 33))]
3080 "TARGET_64BIT"
3081 "@
3082 agr\\t%0,%1
3083 aghi\\t%0,%h1
3084 ag\\t%0,%1"
3085 [(set_attr "op_type" "RRE,RI,RXE")
3086 (set_attr "atype" "reg,reg,mem")])
3087
3088 (define_insn "adddi3_31"
3089 [(set (match_operand:DI 0 "register_operand" "=d,d")
3090 (plus:DI (match_operand:DI 1 "register_operand" "0,0")
3091 (match_operand:DI 2 "general_operand" "d,m") ) )
3092 (clobber (reg:CC 33))]
3093 "!TARGET_64BIT"
3094 "*
3095 {
3096 switch (which_alternative)
3097 {
3098 case 0: /* d <- d */
3099 output_asm_insn (\"ar\\t%0,%2\", operands);
3100 output_asm_insn (\"alr\\t%N0,%N2\", operands);
3101 break;
3102
3103 case 1: /* d <- m */
3104 output_asm_insn (\"a\\t%0,%2\", operands);
3105 output_asm_insn (\"al\\t%N0,%N2\", operands);
3106 break;
3107
3108 default:
3109 abort ();
3110 }
3111
3112 output_asm_insn (\"brc\\t12,.+8\", operands);
3113 return \"ahi\\t%0,1\";
3114 }"
3115 [(set_attr "op_type" "NN,NN")
3116 (set_attr "atype" "reg,mem")
3117 (set_attr "type" "o2,o2")
3118 (set_attr "length" "12,16")])
3119
3120 (define_expand "adddi3"
3121 [(set (match_operand:DI 0 "register_operand" "")
3122 (plus:DI (match_operand:DI 1 "register_operand" "")
3123 (match_operand:DI 2 "general_operand" "")))]
3124 ""
3125 "
3126 {
3127 if (TARGET_64BIT)
3128 emit_insn(gen_adddi3_64 (operands[0],operands[1],operands[2]));
3129 else
3130 emit_insn(gen_adddi3_31 (operands[0],operands[1],operands[2]));
3131 DONE;
3132 }")
3133
3134 (define_insn "reload_load_address"
3135 [(set (match_operand:DI 0 "register_operand" "=a")
3136 (match_operand:QI 1 "address_operand" "p"))]
3137 "TARGET_64BIT"
3138 "la\\t%0,%a1"
3139 [(set_attr "op_type" "RX")
3140 (set_attr "atype" "mem")
3141 (set_attr "type" "la")])
3142
3143 (define_insn "*reload_load_address_reg_0"
3144 [(set (match_operand:DI 0 "register_operand" "=d")
3145 (plus:DI (match_operand:DI 1 "register_operand" "%0")
3146 (match_operand:DI 2 "register_operand" "d")))]
3147 "TARGET_64BIT"
3148 "brxlg\\t%0,%2,.+6"
3149 [(set_attr "op_type" "RIE")
3150 (set_attr "atype" "reg")])
3151
3152 (define_insn "*reload_la_64"
3153 [(set (match_operand:DI 0 "register_operand" "=d")
3154 (plus:DI (match_operand:DI 1 "general_operand" "g")
3155 (match_operand:DI 2 "general_operand" "g")))]
3156 "TARGET_64BIT && reload_in_progress
3157 && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
3158 && !rtx_equal_p (operands[0], operands[1])
3159 && !rtx_equal_p (operands[0], operands[2])"
3160 "#")
3161
3162 (define_split
3163 [(set (match_operand:DI 0 "register_operand" "")
3164 (plus:DI (match_operand:DI 1 "general_operand" "")
3165 (match_operand:DI 2 "register_operand" "")))]
3166 "TARGET_64BIT && reload_completed
3167 && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
3168 && !rtx_equal_p (operands[0], operands[1])
3169 && !rtx_equal_p (operands[0], operands[2])"
3170 [(set (match_dup 0) (match_dup 1))
3171 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3172 "
3173 {
3174 if (CONSTANT_P (operands[1])
3175 && !legitimate_reload_constant_p (operands[1]))
3176 operands[1] = force_const_mem (DImode, operands[1]);
3177 }")
3178
3179 (define_split
3180 [(set (match_operand:DI 0 "register_operand" "")
3181 (plus:DI (match_operand:DI 1 "register_operand" "")
3182 (match_operand:DI 2 "general_operand" "")))]
3183 "TARGET_64BIT && reload_completed
3184 && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
3185 && !rtx_equal_p (operands[0], operands[1])
3186 && !rtx_equal_p (operands[0], operands[2])"
3187 [(set (match_dup 0) (match_dup 2))
3188 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))]
3189 "
3190 {
3191 if (CONSTANT_P (operands[2])
3192 && !legitimate_reload_constant_p (operands[2]))
3193 operands[2] = force_const_mem (DImode, operands[2]);
3194 }")
3195
3196 ;
3197 ; addsi3 instruction pattern(s).
3198 ;
3199
3200 (define_insn "*la_ccclobber"
3201 [(set (match_operand:SI 0 "register_operand" "=a")
3202 (match_operand:QI 1 "address_operand" "p"))
3203 (clobber (reg:CC 33))]
3204 "legitimate_la_operand_p (operands[1])"
3205 "la\\t%0,%a1"
3206 [(set_attr "op_type" "RX")
3207 (set_attr "atype" "mem")
3208 (set_attr "type" "la")])
3209
3210 (define_insn "*addaddr_ccclobber"
3211 [(set (match_operand:SI 0 "register_operand" "=d,d")
3212 (plus:SI (match_operand:SI 1 "register_operand" "%a,a")
3213 (match_operand:SI 2 "nonmemory_operand" "J,a")))
3214 (clobber (reg:CC 33))]
3215 "(((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3216 (REGNO (operands[1]) == FRAME_POINTER_REGNUM ) ||
3217 (REGNO (operands[1]) == BASE_REGISTER)) &&
3218 (GET_CODE (operands[2]) == REG ||
3219 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3220 "@
3221 la\\t%0,%c2(,%1)
3222 la\\t%0,0(%1,%2)"
3223 [(set_attr "op_type" "RX")
3224 (set_attr "atype" "mem")
3225 (set_attr "type" "la")])
3226
3227 (define_insn "*addsi3_cc"
3228 [(set (reg 33)
3229 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3230 (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3231 (const_int 0)))
3232 (set (match_operand:SI 0 "register_operand" "=d,d")
3233 (plus:SI (match_dup 1) (match_dup 2)))]
3234 "s390_match_ccmode(insn, CCLmode)"
3235 "@
3236 alr\\t%0,%2
3237 al\\t%0,%2"
3238 [(set_attr "op_type" "RR,RX")
3239 (set_attr "atype" "reg,mem")])
3240
3241 (define_insn "*addsi3_cconly"
3242 [(set (reg 33)
3243 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3244 (match_operand:SI 2 "general_operand" "d,m"))
3245 (const_int 0)))
3246 (clobber (match_scratch:SI 0 "=d,d"))]
3247 "s390_match_ccmode(insn, CCLmode)"
3248 "@
3249 alr\\t%0,%2
3250 al\\t%0,%2"
3251 [(set_attr "op_type" "RR,RX")
3252 (set_attr "atype" "reg,mem")])
3253
3254 (define_insn "*addsi3_cconly2"
3255 [(set (reg 33)
3256 (compare (match_operand:SI 1 "register_operand" "%0,0")
3257 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3258 (clobber (match_scratch:SI 0 "=d,d"))]
3259 "s390_match_ccmode(insn, CCLmode)"
3260 "@
3261 alr\\t%0,%2
3262 al\\t%0,%2"
3263 [(set_attr "op_type" "RR,RX")
3264 (set_attr "atype" "reg,mem")])
3265
3266 (define_insn "addsi3"
3267 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3268 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3269 (match_operand:SI 2 "general_operand" "d,K,m")))
3270 (clobber (reg:CC 33))]
3271 ""
3272 "@
3273 ar\\t%0,%2
3274 ahi\\t%0,%h2
3275 a\\t%0,%2"
3276 [(set_attr "op_type" "RR,RI,RX")
3277 (set_attr "atype" "reg,reg,mem")])
3278
3279 (define_insn "*la"
3280 [(set (match_operand:SI 0 "register_operand" "=a")
3281 (match_operand:QI 1 "address_operand" "p"))]
3282 "reload_in_progress || reload_completed
3283 || legitimate_la_operand_p (operands[1])"
3284 "la\\t%0,%a1"
3285 [(set_attr "op_type" "RX")
3286 (set_attr "atype" "mem")
3287 (set_attr "type" "la")])
3288
3289 (define_insn "*do_la_reg_0"
3290 [(set (match_operand:SI 0 "register_operand" "=d")
3291 (plus:SI (match_operand:SI 1 "register_operand" "%0")
3292 (match_operand:SI 2 "register_operand" "d")))]
3293 "reload_in_progress || reload_completed"
3294 "brxle\\t%0,%2,.+4"
3295 [(set_attr "op_type" "RSI")
3296 (set_attr "atype" "reg")])
3297
3298 (define_insn "*reload_la_31"
3299 [(set (match_operand:SI 0 "register_operand" "=d")
3300 (plus:SI (match_operand:SI 1 "general_operand" "g")
3301 (match_operand:SI 2 "general_operand" "g")))]
3302 "reload_in_progress
3303 && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3304 && !rtx_equal_p (operands[0], operands[1])
3305 && !rtx_equal_p (operands[0], operands[2])"
3306 "#")
3307
3308 (define_split
3309 [(set (match_operand:SI 0 "register_operand" "")
3310 (plus:SI (match_operand:SI 1 "general_operand" "")
3311 (match_operand:SI 2 "register_operand" "")))]
3312 "reload_completed
3313 && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3314 && !rtx_equal_p (operands[0], operands[1])
3315 && !rtx_equal_p (operands[0], operands[2])"
3316 [(set (match_dup 0) (match_dup 1))
3317 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3318 "
3319 {
3320 if (CONSTANT_P (operands[1])
3321 && !legitimate_reload_constant_p (operands[1]))
3322 operands[1] = force_const_mem (SImode, operands[1]);
3323 }")
3324
3325 (define_split
3326 [(set (match_operand:SI 0 "register_operand" "")
3327 (plus:SI (match_operand:SI 1 "register_operand" "")
3328 (match_operand:SI 2 "general_operand" "")))]
3329 "reload_completed
3330 && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3331 && !rtx_equal_p (operands[0], operands[1])
3332 && !rtx_equal_p (operands[0], operands[2])"
3333 [(set (match_dup 0) (match_dup 2))
3334 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
3335 "
3336 {
3337 if (CONSTANT_P (operands[2])
3338 && !legitimate_reload_constant_p (operands[2]))
3339 operands[2] = force_const_mem (SImode, operands[2]);
3340 }")
3341
3342
3343 ;
3344 ; addhi3 instruction pattern(s).
3345 ;
3346
3347 (define_insn "addhi3"
3348 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3349 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
3350 (match_operand:HI 2 "general_operand" "d,K,m")))
3351 (clobber (reg:CC 33))]
3352 ""
3353 "@
3354 ar\\t%0,%2
3355 ahi\\t%0,%h2
3356 ah\\t%0,%2"
3357 [(set_attr "op_type" "RR,RI,RX")
3358 (set_attr "atype" "reg,reg,mem")])
3359
3360
3361 ;
3362 ; addqi3 instruction pattern(s).
3363 ;
3364
3365 (define_insn "addqi3"
3366 [(set (match_operand:QI 0 "register_operand" "=d,d")
3367 (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
3368 (match_operand:QI 2 "general_operand" "a,n")))
3369 (clobber (reg:CC 33))]
3370 ""
3371 "@
3372 ar\\t%0,%2
3373 ahi\\t%0,%h2"
3374 [(set_attr "op_type" "RX,RX")
3375 (set_attr "atype" "reg,mem")])
3376
3377
3378 ;
3379 ; adddf3 instruction pattern(s).
3380 ;
3381
3382 (define_expand "adddf3"
3383 [(parallel
3384 [(set (match_operand:DF 0 "register_operand" "=f,f")
3385 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3386 (match_operand:DF 2 "general_operand" "f,m")))
3387 (clobber (reg:CC 33))])]
3388 "TARGET_HARD_FLOAT"
3389 "")
3390
3391 (define_insn "*adddf3"
3392 [(set (match_operand:DF 0 "register_operand" "=f,f")
3393 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3394 (match_operand:DF 2 "general_operand" "f,m")))
3395 (clobber (reg:CC 33))]
3396 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3397 "@
3398 adbr\\t%0,%2
3399 adb\\t%0,%2"
3400 [(set_attr "op_type" "RR,RX")
3401 (set_attr "atype" "reg,mem")])
3402
3403 (define_insn "*adddf3_ibm"
3404 [(set (match_operand:DF 0 "register_operand" "=f,f")
3405 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3406 (match_operand:DF 2 "general_operand" "f,m")))
3407 (clobber (reg:CC 33))]
3408 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3409 "@
3410 adr\\t%0,%2
3411 ad\\t%0,%2"
3412 [(set_attr "op_type" "RR,RX")
3413 (set_attr "atype" "reg,mem")])
3414
3415 ;
3416 ; addsf3 instruction pattern(s).
3417 ;
3418
3419 (define_expand "addsf3"
3420 [(parallel
3421 [(set (match_operand:SF 0 "register_operand" "=f,f")
3422 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3423 (match_operand:SF 2 "general_operand" "f,m")))
3424 (clobber (reg:CC 33))])]
3425 "TARGET_HARD_FLOAT"
3426 "")
3427
3428 (define_insn "*addsf3"
3429 [(set (match_operand:SF 0 "register_operand" "=f,f")
3430 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3431 (match_operand:SF 2 "general_operand" "f,m")))
3432 (clobber (reg:CC 33))]
3433 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3434 "@
3435 aebr\\t%0,%2
3436 aeb\\t%0,%2"
3437 [(set_attr "op_type" "RR,RX")
3438 (set_attr "atype" "reg,mem")])
3439
3440 (define_insn "*addsf3"
3441 [(set (match_operand:SF 0 "register_operand" "=f,f")
3442 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3443 (match_operand:SF 2 "general_operand" "f,m")))
3444 (clobber (reg:CC 33))]
3445 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3446 "@
3447 aer\\t%0,%2
3448 ae\\t%0,%2"
3449 [(set_attr "op_type" "RR,RX")
3450 (set_attr "atype" "reg,mem")])
3451
3452
3453 ;;
3454 ;;- Subtract instructions.
3455 ;;
3456
3457 ;
3458 ; subdi3 instruction pattern(s).
3459 ;
3460
3461 (define_insn "*subdi3_64"
3462 [(set (match_operand:DI 0 "register_operand" "=d,d")
3463 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3464 (match_operand:DI 2 "general_operand" "d,m") ) )
3465 (clobber (reg:CC 33))]
3466 "TARGET_64BIT"
3467 "@
3468 sgr\\t%0,%2
3469 sg\\t%0,%2"
3470 [(set_attr "op_type" "RRE,RRE")
3471 (set_attr "atype" "reg,mem")])
3472
3473 (define_insn "subdi3"
3474 [(set (match_operand:DI 0 "register_operand" "=d,d")
3475 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3476 (match_operand:DI 2 "general_operand" "d,m")))
3477 (clobber (reg:CC 33))]
3478 ""
3479 "*
3480 {
3481 switch (which_alternative)
3482 {
3483 case 0: /* d <- d */
3484 output_asm_insn (\"sr\\t%0,%2\", operands);
3485 output_asm_insn (\"slr\\t%N0,%N2\", operands);
3486 break;
3487 case 1: /* d <- m */
3488 output_asm_insn (\"s\\t%0,%2\", operands);
3489 output_asm_insn (\"sl\\t%N0,%N2\", operands);
3490 break;
3491
3492 default:
3493 abort ();
3494 }
3495
3496 output_asm_insn (\"brc\\t11,.+8\", operands);
3497 return \"ahi\\t%0,-1\";
3498 }"
3499 [(set_attr "op_type" "NN,NN")
3500 (set_attr "atype" "reg,mem")
3501 (set_attr "type" "other,other")
3502 (set_attr "length" "12,16")])
3503
3504 ;
3505 ; subsi3 instruction pattern(s).
3506 ;
3507
3508 (define_insn "*subsi3_cc"
3509 [(set (reg 33)
3510 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3511 (match_operand:SI 2 "general_operand" "d,m"))
3512 (const_int 0)))
3513 (set (match_operand:SI 0 "register_operand" "=d,d")
3514 (minus:SI (match_dup 1) (match_dup 2)))]
3515 "s390_match_ccmode(insn, CCLmode)"
3516 "@
3517 slr\\t%0,%2
3518 sl\\t%0,%2"
3519 [(set_attr "op_type" "RR,RX")
3520 (set_attr "atype" "reg,mem")])
3521
3522 (define_insn "*subsi3_cconly"
3523 [(set (reg 33)
3524 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3525 (match_operand:SI 2 "general_operand" "d,m"))
3526 (const_int 0)))
3527 (clobber (match_scratch:SI 0 "=d,d"))]
3528 "s390_match_ccmode(insn, CCLmode)"
3529 "@
3530 slr\\t%0,%2
3531 sl\\t%0,%2"
3532 [(set_attr "op_type" "RR,RX")
3533 (set_attr "atype" "reg,mem")])
3534
3535 (define_insn "subsi3"
3536 [(set (match_operand:SI 0 "register_operand" "=d,d")
3537 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3538 (match_operand:SI 2 "general_operand" "d,m")))
3539 (clobber (reg:CC 33))]
3540 ""
3541 "@
3542 sr\\t%0,%2
3543 s\\t%0,%2"
3544 [(set_attr "op_type" "RR,RX")
3545 (set_attr "atype" "reg,mem")])
3546
3547 ;
3548 ; subhi3 instruction pattern(s).
3549 ;
3550
3551 (define_insn "subhi3"
3552 [(set (match_operand:HI 0 "register_operand" "=d,d")
3553 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
3554 (match_operand:HI 2 "general_operand" "d,m")))
3555 (clobber (reg:CC 33))]
3556 ""
3557 "@
3558 sr\\t%0,%2
3559 sh\\t%0,%2"
3560 [(set_attr "op_type" "RR,RX")
3561 (set_attr "atype" "reg,mem")])
3562
3563 ;
3564 ; subqi3 instruction pattern(s).
3565 ;
3566
3567 (define_insn "subqi3"
3568 [(set (match_operand:QI 0 "register_operand" "=d")
3569 (minus:QI (match_operand:QI 1 "register_operand" "0")
3570 (match_operand:QI 2 "register_operand" "d")))
3571 (clobber (reg:CC 33))]
3572 ""
3573 "sr\\t%0,%2"
3574 [(set_attr "op_type" "RR")])
3575
3576 ;
3577 ; subdf3 instruction pattern(s).
3578 ;
3579
3580 (define_expand "subdf3"
3581 [(parallel
3582 [(set (match_operand:DF 0 "register_operand" "=f,f")
3583 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3584 (match_operand:DF 2 "general_operand" "f,m")))
3585 (clobber (reg:CC 33))])]
3586 "TARGET_HARD_FLOAT"
3587 "")
3588
3589 (define_insn "*subdf3"
3590 [(set (match_operand:DF 0 "register_operand" "=f,f")
3591 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3592 (match_operand:DF 2 "general_operand" "f,m")))
3593 (clobber (reg:CC 33))]
3594 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3595 "@
3596 sdbr\\t%0,%2
3597 sdb\\t%0,%2"
3598 [(set_attr "op_type" "RR,RX")
3599 (set_attr "atype" "reg,mem")])
3600
3601 (define_insn "*subdf3_ibm"
3602 [(set (match_operand:DF 0 "register_operand" "=f,f")
3603 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3604 (match_operand:DF 2 "general_operand" "f,m")))
3605 (clobber (reg:CC 33))]
3606 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3607 "@
3608 sdr\\t%0,%2
3609 sd\\t%0,%2"
3610 [(set_attr "op_type" "RR,RX")
3611 (set_attr "atype" "reg,mem")])
3612
3613 ;
3614 ; subsf3 instruction pattern(s).
3615 ;
3616
3617 (define_expand "subsf3"
3618 [(parallel
3619 [(set (match_operand:SF 0 "register_operand" "=f,f")
3620 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3621 (match_operand:SF 2 "general_operand" "f,m")))
3622 (clobber (reg:CC 33))])]
3623 "TARGET_HARD_FLOAT"
3624 "")
3625
3626 (define_insn "*subsf3"
3627 [(set (match_operand:SF 0 "register_operand" "=f,f")
3628 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3629 (match_operand:SF 2 "general_operand" "f,m")))
3630 (clobber (reg:CC 33))]
3631 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3632 "@
3633 sebr\\t%0,%2
3634 seb\\t%0,%2"
3635 [(set_attr "op_type" "RR,RX")
3636 (set_attr "atype" "reg,mem")])
3637
3638 (define_insn "*subsf3_ibm"
3639 [(set (match_operand:SF 0 "register_operand" "=f,f")
3640 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3641 (match_operand:SF 2 "general_operand" "f,m")))
3642 (clobber (reg:CC 33))]
3643 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3644 "@
3645 ser\\t%0,%2
3646 se\\t%0,%2"
3647 [(set_attr "op_type" "RR,RX")
3648 (set_attr "atype" "reg,mem")])
3649
3650
3651 ;;
3652 ;;- Multiply instructions.
3653 ;;
3654
3655 ;
3656 ; muldi3 instruction pattern(s).
3657 ;
3658
3659 (define_insn "muldi3"
3660 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3661 (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3662 (match_operand:DI 2 "general_operand" "d,K,m")))
3663 (clobber (reg:CC 33))]
3664 "TARGET_64BIT"
3665 "@
3666 msgr\\t%0,%2
3667 mghi\\t%0,%h2
3668 msg\\t%0,%2"
3669 [(set_attr "op_type" "RRE,RI,RX")
3670 (set_attr "atype" "reg,reg,mem")
3671 (set_attr "type" "imul")])
3672
3673 ;
3674 ; mulsi3 instruction pattern(s).
3675 ;
3676
3677 (define_insn "mulsi3"
3678 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3679 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3680 (match_operand:SI 2 "general_operand" "d,K,m")))
3681 (clobber (reg:CC 33))]
3682 ""
3683 "@
3684 msr\\t%0,%2
3685 mhi\\t%0,%h2
3686 ms\\t%0,%2"
3687 [(set_attr "op_type" "RRE,RI,RX")
3688 (set_attr "atype" "reg,reg,mem")
3689 (set_attr "type" "imul")])
3690
3691 ;
3692 ; mulsidi3 instruction pattern(s).
3693 ;
3694
3695 (define_expand "mulsidi3"
3696 [(set (match_operand:DI 0 "register_operand" "")
3697 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3698 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3699 "!TARGET_64BIT"
3700 "
3701 {
3702 rtx insn;
3703
3704 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
3705 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3706 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3707
3708 REG_NOTES (insn) =
3709 gen_rtx_EXPR_LIST (REG_EQUAL,
3710 gen_rtx_MULT (DImode,
3711 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3712 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3713 REG_NOTES (insn));
3714 DONE;
3715 }")
3716
3717 (define_insn "mulsi_6432"
3718 [(set (match_operand:DI 0 "register_operand" "=d,d")
3719 (mult:DI (sign_extend:DI
3720 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3721 (sign_extend:DI
3722 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3723 (clobber (reg:CC 33))]
3724 "!TARGET_64BIT"
3725 "@
3726 mr\\t%0,%2
3727 m\\t%0,%2"
3728 [(set_attr "op_type" "RR,RX")
3729 (set_attr "atype" "reg,mem")
3730 (set_attr "type" "imul")])
3731
3732 ;
3733 ; muldf3 instruction pattern(s).
3734 ;
3735
3736 (define_expand "muldf3"
3737 [(parallel
3738 [(set (match_operand:DF 0 "register_operand" "=f,f")
3739 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3740 (match_operand:DF 2 "general_operand" "f,m")))
3741 (clobber (reg:CC 33))])]
3742 "TARGET_HARD_FLOAT"
3743 "")
3744
3745 (define_insn "*muldf3"
3746 [(set (match_operand:DF 0 "register_operand" "=f,f")
3747 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3748 (match_operand:DF 2 "general_operand" "f,m")))
3749 (clobber (reg:CC 33))]
3750 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3751 "@
3752 mdbr\\t%0,%2
3753 mdb\\t%0,%2"
3754 [(set_attr "op_type" "RR,RX")
3755 (set_attr "type" "fmul")
3756 (set_attr "atype" "reg,mem")])
3757
3758 (define_insn "*muldf3_ibm"
3759 [(set (match_operand:DF 0 "register_operand" "=f,f")
3760 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3761 (match_operand:DF 2 "general_operand" "f,m")))
3762 (clobber (reg:CC 33))]
3763 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3764 "@
3765 mdr\\t%0,%2
3766 md\\t%0,%2"
3767 [(set_attr "op_type" "RR,RX")
3768 (set_attr "type" "fmul")
3769 (set_attr "atype" "reg,mem")])
3770
3771 ;
3772 ; mulsf3 instruction pattern(s).
3773 ;
3774
3775 (define_expand "mulsf3"
3776 [(parallel
3777 [(set (match_operand:SF 0 "register_operand" "=f,f")
3778 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3779 (match_operand:SF 2 "general_operand" "f,m")))
3780 (clobber (reg:CC 33))])]
3781 "TARGET_HARD_FLOAT"
3782 "")
3783
3784 (define_insn "*mulsf3"
3785 [(set (match_operand:SF 0 "register_operand" "=f,f")
3786 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3787 (match_operand:SF 2 "general_operand" "f,m")))
3788 (clobber (reg:CC 33))]
3789 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3790 "@
3791 meebr\\t%0,%2
3792 meeb\\t%0,%2"
3793 [(set_attr "op_type" "RR,RX")
3794 (set_attr "type" "fmul")
3795 (set_attr "atype" "reg,mem")])
3796
3797 (define_insn "*mulsf3_ibm"
3798 [(set (match_operand:SF 0 "register_operand" "=f,f")
3799 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3800 (match_operand:SF 2 "general_operand" "f,m")))
3801 (clobber (reg:CC 33))]
3802 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3803 "@
3804 mer\\t%0,%2
3805 me\\t%0,%2"
3806 [(set_attr "op_type" "RR,RX")
3807 (set_attr "type" "fmul")
3808 (set_attr "atype" "reg,mem")])
3809
3810
3811 ;;
3812 ;;- Divide and modulo instructions.
3813 ;;
3814
3815 ;
3816 ; divmoddi4 instruction pattern(s).
3817 ;
3818
3819 (define_expand "divmoddi4"
3820 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3821 (div:DI (match_operand:DI 1 "general_operand" "")
3822 (match_operand:DI 2 "general_operand" "")))
3823 (set (match_operand:DI 3 "general_operand" "")
3824 (mod:DI (match_dup 1) (match_dup 2)))])
3825 (clobber (match_dup 4))]
3826 "TARGET_64BIT"
3827 "
3828 {
3829 rtx insn, div_equal, mod_equal, equal;
3830
3831 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3832 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3833 equal = gen_rtx_IOR (TImode,
3834 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3835 gen_rtx_ASHIFT (TImode,
3836 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3837 GEN_INT (64)));
3838
3839 operands[4] = gen_reg_rtx(TImode);
3840 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3841 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3842 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3843 REG_NOTES (insn) =
3844 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3845
3846 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3847 REG_NOTES (insn) =
3848 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3849
3850 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3851 REG_NOTES (insn) =
3852 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3853
3854 DONE;
3855 }")
3856
3857 (define_insn "divmodtidi3"
3858 [(set (match_operand:TI 0 "register_operand" "=d,d")
3859 (ior:TI
3860 (zero_extend:TI
3861 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3862 (match_operand:DI 2 "general_operand" "d,m")))
3863 (ashift:TI
3864 (zero_extend:TI
3865 (mod:DI (truncate:DI (match_dup 1))
3866 (match_dup 2)))
3867 (const_int 64))))]
3868 "TARGET_64BIT"
3869 "@
3870 dsgr\\t%0,%2
3871 dsg\\t%0,%2"
3872 [(set_attr "op_type" "RRE,RXE")
3873 (set_attr "type" "idiv")
3874 (set_attr "atype" "reg,mem")])
3875
3876 (define_insn "divmodtisi3"
3877 [(set (match_operand:TI 0 "register_operand" "=d,d")
3878 (ior:TI
3879 (zero_extend:TI
3880 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3881 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3882 (ashift:TI
3883 (zero_extend:TI
3884 (mod:DI (truncate:DI (match_dup 1))
3885 (sign_extend:DI (match_dup 2))))
3886 (const_int 64))))]
3887 "TARGET_64BIT"
3888 "@
3889 dsgfr\\t%0,%2
3890 dsgf\\t%0,%2"
3891 [(set_attr "op_type" "RRE,RXE")
3892 (set_attr "type" "idiv")
3893 (set_attr "atype" "reg,mem")])
3894
3895 ;
3896 ; udivmoddi4 instruction pattern(s).
3897 ;
3898
3899 (define_expand "udivmoddi4"
3900 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3901 (udiv:DI (match_operand:DI 1 "general_operand" "")
3902 (match_operand:DI 2 "nonimmediate_operand" "")))
3903 (set (match_operand:DI 3 "general_operand" "")
3904 (umod:DI (match_dup 1) (match_dup 2)))])
3905 (clobber (match_dup 4))]
3906 "TARGET_64BIT"
3907 "
3908 {
3909 rtx insn, div_equal, mod_equal, equal;
3910
3911 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3912 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3913 equal = gen_rtx_IOR (TImode,
3914 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3915 gen_rtx_ASHIFT (TImode,
3916 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3917 GEN_INT (64)));
3918
3919 operands[4] = gen_reg_rtx(TImode);
3920 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3921 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3922 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3923 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3924 REG_NOTES (insn) =
3925 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3926
3927 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3928 REG_NOTES (insn) =
3929 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3930
3931 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3932 REG_NOTES (insn) =
3933 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3934
3935 DONE;
3936 }")
3937
3938 (define_insn "udivmodtidi3"
3939 [(set (match_operand:TI 0 "register_operand" "=d,d")
3940 (ior:TI (zero_extend:TI
3941 (truncate:DI
3942 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3943 (zero_extend:TI
3944 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3945 (ashift:TI
3946 (zero_extend:TI
3947 (truncate:DI
3948 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3949 (const_int 64))))]
3950 "TARGET_64BIT"
3951 "@
3952 dlgr\\t%0,%2
3953 dlg\\t%0,%2"
3954 [(set_attr "op_type" "RRE,RXE")
3955 (set_attr "type" "idiv")
3956 (set_attr "atype" "reg,mem")])
3957
3958 ;
3959 ; divmodsi4 instruction pattern(s).
3960 ;
3961
3962 (define_expand "divmodsi4"
3963 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3964 (div:SI (match_operand:SI 1 "general_operand" "")
3965 (match_operand:SI 2 "nonimmediate_operand" "")))
3966 (set (match_operand:SI 3 "general_operand" "")
3967 (mod:SI (match_dup 1) (match_dup 2)))])
3968 (clobber (match_dup 4))]
3969 "!TARGET_64BIT"
3970 "
3971 {
3972 rtx insn, div_equal, mod_equal, equal;
3973
3974 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3975 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3976 equal = gen_rtx_IOR (DImode,
3977 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3978 gen_rtx_ASHIFT (DImode,
3979 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3980 GEN_INT (32)));
3981
3982 operands[4] = gen_reg_rtx(DImode);
3983 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3984 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3985 REG_NOTES (insn) =
3986 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3987
3988 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3989 REG_NOTES (insn) =
3990 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3991
3992 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3993 REG_NOTES (insn) =
3994 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3995
3996 DONE;
3997 }")
3998
3999 (define_insn "divmoddisi3"
4000 [(set (match_operand:DI 0 "register_operand" "=d,d")
4001 (ior:DI (zero_extend:DI
4002 (truncate:SI
4003 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4004 (sign_extend:DI
4005 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4006 (ashift:DI
4007 (zero_extend:DI
4008 (truncate:SI
4009 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4010 (const_int 32))))]
4011 "!TARGET_64BIT"
4012 "@
4013 dr\\t%0,%2
4014 d\\t%0,%2"
4015 [(set_attr "op_type" "RR,RX")
4016 (set_attr "type" "idiv")
4017 (set_attr "atype" "reg,mem")])
4018
4019 ;
4020 ; udivsi3 and umodsi3 instruction pattern(s).
4021 ;
4022
4023
4024 (define_expand "udivsi3"
4025 [(set (match_operand:SI 0 "register_operand" "=d")
4026 (udiv:SI (match_operand:SI 1 "general_operand" "")
4027 (match_operand:SI 2 "general_operand" "")))
4028 (clobber (match_dup 3))]
4029 "!TARGET_64BIT"
4030 "
4031 {
4032 rtx insn, udiv_equal, umod_equal, equal;
4033
4034 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4035 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4036 equal = gen_rtx_IOR (DImode,
4037 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4038 gen_rtx_ASHIFT (DImode,
4039 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4040 GEN_INT (32)));
4041
4042 operands[3] = gen_reg_rtx (DImode);
4043
4044 if (CONSTANT_P (operands[2]))
4045 {
4046 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4047 {
4048 rtx label1 = gen_label_rtx ();
4049
4050 operands[1] = make_safe_from (operands[1], operands[0]);
4051 emit_move_insn (operands[0], const0_rtx);
4052 emit_insn (gen_cmpsi (operands[1], operands[2]));
4053 emit_jump_insn (gen_bltu (label1));
4054 emit_move_insn (operands[0], const1_rtx);
4055 emit_label (label1);
4056 }
4057 else
4058 {
4059 operands[2] = force_reg (SImode, operands[2]);
4060 operands[2] = make_safe_from (operands[2], operands[0]);
4061
4062 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4063 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4064 operands[2]));
4065 REG_NOTES (insn) =
4066 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4067
4068 insn = emit_move_insn (operands[0],
4069 gen_lowpart (SImode, operands[3]));
4070 REG_NOTES (insn) =
4071 gen_rtx_EXPR_LIST (REG_EQUAL,
4072 udiv_equal, REG_NOTES (insn));
4073 }
4074 }
4075 else
4076 {
4077 rtx label1 = gen_label_rtx ();
4078 rtx label2 = gen_label_rtx ();
4079 rtx label3 = gen_label_rtx ();
4080
4081 operands[1] = force_reg (SImode, operands[1]);
4082 operands[1] = make_safe_from (operands[1], operands[0]);
4083 operands[2] = force_reg (SImode, operands[2]);
4084 operands[2] = make_safe_from (operands[2], operands[0]);
4085
4086 emit_move_insn (operands[0], const0_rtx);
4087 emit_insn (gen_cmpsi (operands[2], operands[1]));
4088 emit_jump_insn (gen_bgtu (label3));
4089 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4090 emit_jump_insn (gen_blt (label2));
4091 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4092 emit_jump_insn (gen_beq (label1));
4093 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4094 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4095 operands[2]));
4096 REG_NOTES (insn) =
4097 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4098
4099 insn = emit_move_insn (operands[0],
4100 gen_lowpart (SImode, operands[3]));
4101 REG_NOTES (insn) =
4102 gen_rtx_EXPR_LIST (REG_EQUAL,
4103 udiv_equal, REG_NOTES (insn));
4104 emit_jump (label3);
4105 emit_label (label1);
4106 emit_move_insn (operands[0], operands[1]);
4107 emit_jump (label3);
4108 emit_label (label2);
4109 emit_move_insn (operands[0], const1_rtx);
4110 emit_label (label3);
4111 }
4112 emit_move_insn (operands[0], operands[0]);
4113 DONE;
4114 }")
4115
4116 (define_expand "umodsi3"
4117 [(set (match_operand:SI 0 "register_operand" "=d")
4118 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4119 (match_operand:SI 2 "nonimmediate_operand" "")))
4120 (clobber (match_dup 3))]
4121 "!TARGET_64BIT"
4122 "
4123 {
4124 rtx insn, udiv_equal, umod_equal, equal;
4125
4126 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4127 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4128 equal = gen_rtx_IOR (DImode,
4129 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4130 gen_rtx_ASHIFT (DImode,
4131 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4132 GEN_INT (32)));
4133
4134 operands[3] = gen_reg_rtx (DImode);
4135
4136 if (CONSTANT_P (operands[2]))
4137 {
4138 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4139 {
4140 rtx label1 = gen_label_rtx ();
4141
4142 operands[1] = make_safe_from (operands[1], operands[0]);
4143 emit_move_insn (operands[0], operands[1]);
4144 emit_insn (gen_cmpsi (operands[0], operands[2]));
4145 emit_jump_insn (gen_bltu (label1));
4146 emit_insn (gen_abssi2 (operands[0], operands[2]));
4147 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4148 emit_label (label1);
4149 }
4150 else
4151 {
4152 operands[2] = force_reg (SImode, operands[2]);
4153 operands[2] = make_safe_from (operands[2], operands[0]);
4154
4155 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4156 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4157 operands[2]));
4158 REG_NOTES (insn) =
4159 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4160
4161 insn = emit_move_insn (operands[0],
4162 gen_highpart (SImode, operands[3]));
4163 REG_NOTES (insn) =
4164 gen_rtx_EXPR_LIST (REG_EQUAL,
4165 umod_equal, REG_NOTES (insn));
4166 }
4167 }
4168 else
4169 {
4170 rtx label1 = gen_label_rtx ();
4171 rtx label2 = gen_label_rtx ();
4172 rtx label3 = gen_label_rtx ();
4173
4174 operands[1] = force_reg (SImode, operands[1]);
4175 operands[1] = make_safe_from (operands[1], operands[0]);
4176 operands[2] = force_reg (SImode, operands[2]);
4177 operands[2] = make_safe_from (operands[2], operands[0]);
4178
4179 emit_move_insn(operands[0], operands[1]);
4180 emit_insn (gen_cmpsi (operands[2], operands[1]));
4181 emit_jump_insn (gen_bgtu (label3));
4182 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4183 emit_jump_insn (gen_blt (label2));
4184 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4185 emit_jump_insn (gen_beq (label1));
4186 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4187 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4188 operands[2]));
4189 REG_NOTES (insn) =
4190 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4191
4192 insn = emit_move_insn (operands[0],
4193 gen_highpart (SImode, operands[3]));
4194 REG_NOTES (insn) =
4195 gen_rtx_EXPR_LIST (REG_EQUAL,
4196 umod_equal, REG_NOTES (insn));
4197 emit_jump (label3);
4198 emit_label (label1);
4199 emit_move_insn (operands[0], const0_rtx);
4200 emit_jump (label3);
4201 emit_label (label2);
4202 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4203 emit_label (label3);
4204 }
4205 DONE;
4206 }")
4207
4208 ;
4209 ; divdf3 instruction pattern(s).
4210 ;
4211
4212 (define_expand "divdf3"
4213 [(parallel
4214 [(set (match_operand:DF 0 "register_operand" "=f,f")
4215 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4216 (match_operand:DF 2 "general_operand" "f,m")))
4217 (clobber (reg:CC 33))])]
4218 "TARGET_HARD_FLOAT"
4219 "")
4220
4221 (define_insn "*divdf3"
4222 [(set (match_operand:DF 0 "register_operand" "=f,f")
4223 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4224 (match_operand:DF 2 "general_operand" "f,m")))
4225 (clobber (reg:CC 33))]
4226 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4227 "@
4228 ddbr\\t%0,%2
4229 ddb\\t%0,%2"
4230 [(set_attr "op_type" "RR,RX")
4231 (set_attr "type" "fdiv")
4232 (set_attr "atype" "reg,mem")])
4233
4234 (define_insn "*divdf3_ibm"
4235 [(set (match_operand:DF 0 "register_operand" "=f,f")
4236 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4237 (match_operand:DF 2 "general_operand" "f,m")))
4238 (clobber (reg:CC 33))]
4239 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4240 "@
4241 ddr\\t%0,%2
4242 dd\\t%0,%2"
4243 [(set_attr "op_type" "RR,RX")
4244 (set_attr "type" "fdiv")
4245 (set_attr "atype" "reg,mem")])
4246
4247 ;
4248 ; divsf3 instruction pattern(s).
4249 ;
4250
4251 (define_expand "divsf3"
4252 [(parallel
4253 [(set (match_operand:SF 0 "register_operand" "=f,f")
4254 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4255 (match_operand:SF 2 "general_operand" "f,m")))
4256 (clobber (reg:CC 33))])]
4257 "TARGET_HARD_FLOAT"
4258 "")
4259
4260 (define_insn "*divsf3"
4261 [(set (match_operand:SF 0 "register_operand" "=f,f")
4262 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4263 (match_operand:SF 2 "general_operand" "f,m")))
4264 (clobber (reg:CC 33))]
4265 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4266 "@
4267 debr\\t%0,%2
4268 deb\\t%0,%2"
4269 [(set_attr "op_type" "RR,RX")
4270 (set_attr "type" "fdiv")
4271 (set_attr "atype" "reg,mem")])
4272
4273 (define_insn "*divsf3"
4274 [(set (match_operand:SF 0 "register_operand" "=f,f")
4275 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4276 (match_operand:SF 2 "general_operand" "f,m")))
4277 (clobber (reg:CC 33))]
4278 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4279 "@
4280 der\\t%0,%2
4281 de\\t%0,%2"
4282 [(set_attr "op_type" "RR,RX")
4283 (set_attr "type" "fdiv")
4284 (set_attr "atype" "reg,mem")])
4285
4286
4287 ;;
4288 ;;- And instructions.
4289 ;;
4290
4291 ;
4292 ; anddi3 instruction pattern(s).
4293 ;
4294
4295 (define_insn "*anddi3_cc"
4296 [(set (reg 33)
4297 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4298 (match_operand:DI 2 "general_operand" "d,m"))
4299 (const_int 0)))
4300 (set (match_operand:DI 0 "register_operand" "=d,d")
4301 (and:DI (match_dup 1) (match_dup 2)))]
4302 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4303 "@
4304 ngr\\t%0,%2
4305 ng\\t%0,%2"
4306 [(set_attr "op_type" "RRE,RXE")
4307 (set_attr "atype" "reg,mem")])
4308
4309 (define_insn "*anddi3_cconly"
4310 [(set (reg 33)
4311 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4312 (match_operand:DI 2 "general_operand" "d,m"))
4313 (const_int 0)))
4314 (clobber (match_scratch:DI 0 "=d,d"))]
4315 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4316 "@
4317 ngr\\t%0,%2
4318 ng\\t%0,%2"
4319 [(set_attr "op_type" "RRE,RXE")
4320 (set_attr "atype" "reg,mem")])
4321
4322 (define_insn "*anddi3_ni"
4323 [(set (match_operand:DI 0 "register_operand" "=d")
4324 (and:DI (match_operand:DI 1 "register_operand" "%0")
4325 (match_operand:DI 2 "immediate_operand" "n")))
4326 (clobber (reg:CC 33))]
4327 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4328 "*
4329 {
4330 int part = s390_single_hi (operands[2], DImode, -1);
4331 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4332
4333 switch (part)
4334 {
4335 case 0: return \"nihh\\t%0,%x2\";
4336 case 1: return \"nihl\\t%0,%x2\";
4337 case 2: return \"nilh\\t%0,%x2\";
4338 case 3: return \"nill\\t%0,%x2\";
4339 default: abort ();
4340 }
4341 }"
4342 [(set_attr "op_type" "RI")
4343 (set_attr "atype" "reg")])
4344
4345 (define_insn "anddi3"
4346 [(set (match_operand:DI 0 "register_operand" "=d,d")
4347 (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4348 (match_operand:DI 2 "general_operand" "d,m")))
4349 (clobber (reg:CC 33))]
4350 "TARGET_64BIT"
4351 "@
4352 ngr\\t%0,%2
4353 ng\\t%0,%2"
4354 [(set_attr "op_type" "RRE,RXE")
4355 (set_attr "atype" "reg,mem")])
4356
4357 (define_insn "*anddi3_ss"
4358 [(set (match_operand:DI 0 "s_operand" "=Qo")
4359 (and:DI (match_dup 0)
4360 (match_operand:DI 1 "s_imm_operand" "Qo")))
4361 (clobber (reg:CC 33))]
4362 ""
4363 "nc\\t%O0(8,%R0),%1"
4364 [(set_attr "op_type" "SS")
4365 (set_attr "atype" "mem")])
4366
4367 (define_insn "*anddi3_ss_inv"
4368 [(set (match_operand:DI 0 "s_operand" "=Qo")
4369 (and:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4370 (match_dup 0)))
4371 (clobber (reg:CC 33))]
4372 ""
4373 "nc\\t%O0(8,%R0),%1"
4374 [(set_attr "op_type" "SS")
4375 (set_attr "atype" "mem")])
4376
4377 ;
4378 ; andsi3 instruction pattern(s).
4379 ;
4380
4381 (define_insn "*andsi3_cc"
4382 [(set (reg 33)
4383 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4384 (match_operand:SI 2 "general_operand" "d,m"))
4385 (const_int 0)))
4386 (set (match_operand:SI 0 "register_operand" "=d,d")
4387 (and:SI (match_dup 1) (match_dup 2)))]
4388 "s390_match_ccmode(insn, CCTmode)"
4389 "@
4390 nr\\t%0,%2
4391 n\\t%0,%2"
4392 [(set_attr "op_type" "RR,RX")
4393 (set_attr "atype" "reg,mem")])
4394
4395 (define_insn "*andsi3_cconly"
4396 [(set (reg 33)
4397 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4398 (match_operand:SI 2 "general_operand" "d,m"))
4399 (const_int 0)))
4400 (clobber (match_scratch:SI 0 "=d,d"))]
4401 "s390_match_ccmode(insn, CCTmode)"
4402 "@
4403 nr\\t%0,%2
4404 n\\t%0,%2"
4405 [(set_attr "op_type" "RR,RX")
4406 (set_attr "atype" "reg,mem")])
4407
4408 (define_insn "*andsi3_ni"
4409 [(set (match_operand:SI 0 "register_operand" "=d")
4410 (and:SI (match_operand:SI 1 "register_operand" "%0")
4411 (match_operand:SI 2 "immediate_operand" "n")))
4412 (clobber (reg:CC 33))]
4413 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4414 "*
4415 {
4416 int part = s390_single_hi (operands[2], SImode, -1);
4417 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4418
4419 switch (part)
4420 {
4421 case 0: return \"nilh\\t%0,%x2\";
4422 case 1: return \"nill\\t%0,%x2\";
4423 default: abort ();
4424 }
4425 }"
4426 [(set_attr "op_type" "RI")
4427 (set_attr "atype" "reg")])
4428
4429 (define_insn "andsi3"
4430 [(set (match_operand:SI 0 "register_operand" "=d,d")
4431 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4432 (match_operand:SI 2 "general_operand" "d,m")))
4433 (clobber (reg:CC 33))]
4434 ""
4435 "@
4436 nr\\t%0,%2
4437 n\\t%0,%2"
4438 [(set_attr "op_type" "RR,RX")
4439 (set_attr "atype" "reg,mem")])
4440
4441 (define_insn "*andsi3_ss"
4442 [(set (match_operand:SI 0 "s_operand" "=Qo")
4443 (and:SI (match_dup 0)
4444 (match_operand:SI 1 "s_imm_operand" "Qo")))
4445 (clobber (reg:CC 33))]
4446 ""
4447 "nc\\t%O0(4,%R0),%1"
4448 [(set_attr "op_type" "SS")
4449 (set_attr "atype" "mem")])
4450
4451 (define_insn "*andsi3_ss_inv"
4452 [(set (match_operand:SI 0 "s_operand" "=Qo")
4453 (and:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4454 (match_dup 0)))
4455 (clobber (reg:CC 33))]
4456 ""
4457 "nc\\t%O0(4,%R0),%1"
4458 [(set_attr "op_type" "SS")
4459 (set_attr "atype" "mem")])
4460
4461 ;
4462 ; andhi3 instruction pattern(s).
4463 ;
4464
4465 (define_insn "*andhi3_ni"
4466 [(set (match_operand:HI 0 "register_operand" "=d,d")
4467 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4468 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4469 (clobber (reg:CC 33))]
4470 "TARGET_64BIT"
4471 "@
4472 nr\\t%0,%2
4473 nill\\t%0,%x2"
4474 [(set_attr "op_type" "RR,RI")
4475 (set_attr "atype" "reg")])
4476
4477 (define_insn "andhi3"
4478 [(set (match_operand:HI 0 "register_operand" "=d")
4479 (and:HI (match_operand:HI 1 "register_operand" "%0")
4480 (match_operand:HI 2 "nonmemory_operand" "d")))
4481 (clobber (reg:CC 33))]
4482 ""
4483 "nr\\t%0,%2"
4484 [(set_attr "op_type" "RR")
4485 (set_attr "atype" "reg")])
4486
4487 (define_insn "*andhi3_ss"
4488 [(set (match_operand:HI 0 "s_operand" "=Qo")
4489 (and:HI (match_dup 0)
4490 (match_operand:HI 1 "s_imm_operand" "Qo")))
4491 (clobber (reg:CC 33))]
4492 ""
4493 "nc\\t%O0(2,%R0),%1"
4494 [(set_attr "op_type" "SS")
4495 (set_attr "atype" "mem")])
4496
4497 (define_insn "*andhi3_ss_inv"
4498 [(set (match_operand:HI 0 "s_operand" "=Qo")
4499 (and:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4500 (match_dup 0)))
4501 (clobber (reg:CC 33))]
4502 ""
4503 "nc\\t%O0(2,%R0),%1"
4504 [(set_attr "op_type" "SS")
4505 (set_attr "atype" "mem")])
4506
4507 ;
4508 ; andqi3 instruction pattern(s).
4509 ;
4510
4511 (define_insn "*andqi3_ni"
4512 [(set (match_operand:QI 0 "register_operand" "=d,d")
4513 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4514 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4515 (clobber (reg:CC 33))]
4516 "TARGET_64BIT"
4517 "@
4518 nr\\t%0,%2
4519 nill\\t%0,%b2"
4520 [(set_attr "op_type" "RR,RI")
4521 (set_attr "atype" "reg")])
4522
4523 (define_insn "andqi3"
4524 [(set (match_operand:QI 0 "register_operand" "=d")
4525 (and:QI (match_operand:QI 1 "register_operand" "%0")
4526 (match_operand:QI 2 "nonmemory_operand" "d")))
4527 (clobber (reg:CC 33))]
4528 ""
4529 "nr\\t%0,%2"
4530 [(set_attr "op_type" "RR")
4531 (set_attr "atype" "reg")])
4532
4533 (define_insn "*andqi3_ss"
4534 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4535 (and:QI (match_dup 0)
4536 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4537 (clobber (reg:CC 33))]
4538 ""
4539 "@
4540 ni\\t%0,%b1
4541 nc\\t%O0(1,%R0),%1"
4542 [(set_attr "op_type" "SI,SS")
4543 (set_attr "atype" "mem")])
4544
4545 (define_insn "*andqi3_ss_inv"
4546 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4547 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4548 (match_dup 0)))
4549 (clobber (reg:CC 33))]
4550 ""
4551 "@
4552 ni\\t%0,%b1
4553 nc\\t%O0(1,%R0),%1"
4554 [(set_attr "op_type" "SI,SS")
4555 (set_attr "atype" "mem")])
4556
4557
4558 ;;
4559 ;;- Bit set (inclusive or) instructions.
4560 ;;
4561
4562 ;
4563 ; iordi3 instruction pattern(s).
4564 ;
4565
4566 (define_insn "*iordi3_cc"
4567 [(set (reg 33)
4568 (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4569 (match_operand:DI 2 "general_operand" "d,m"))
4570 (const_int 0)))
4571 (set (match_operand:DI 0 "register_operand" "=d,d")
4572 (ior:DI (match_dup 1) (match_dup 2)))]
4573 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4574 "@
4575 ogr\\t%0,%2
4576 og\\t%0,%2"
4577 [(set_attr "op_type" "RRE,RXE")
4578 (set_attr "atype" "reg,mem")])
4579
4580 (define_insn "*iordi3_cconly"
4581 [(set (reg 33)
4582 (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4583 (match_operand:DI 2 "general_operand" "d,m"))
4584 (const_int 0)))
4585 (clobber (match_scratch:DI 0 "=d,d"))]
4586 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4587 "@
4588 ogr\\t%0,%2
4589 og\\t%0,%2"
4590 [(set_attr "op_type" "RRE,RXE")
4591 (set_attr "atype" "reg,mem")])
4592
4593 (define_insn "*iordi3_oi"
4594 [(set (match_operand:DI 0 "register_operand" "=d")
4595 (ior:DI (match_operand:DI 1 "register_operand" "%0")
4596 (match_operand:DI 2 "immediate_operand" "n")))
4597 (clobber (reg:CC 33))]
4598 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4599 "*
4600 {
4601 int part = s390_single_hi (operands[2], DImode, 0);
4602 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4603
4604 switch (part)
4605 {
4606 case 0: return \"oihh\\t%0,%x2\";
4607 case 1: return \"oihl\\t%0,%x2\";
4608 case 2: return \"oilh\\t%0,%x2\";
4609 case 3: return \"oill\\t%0,%x2\";
4610 default: abort ();
4611 }
4612 }"
4613 [(set_attr "op_type" "RI")
4614 (set_attr "atype" "reg")])
4615
4616 (define_insn "iordi3"
4617 [(set (match_operand:DI 0 "register_operand" "=d,d")
4618 (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4619 (match_operand:DI 2 "general_operand" "d,m")))
4620 (clobber (reg:CC 33))]
4621 "TARGET_64BIT"
4622 "@
4623 ogr\\t%0,%2
4624 og\\t%0,%2"
4625 [(set_attr "op_type" "RRE,RXE")
4626 (set_attr "atype" "reg,mem")])
4627
4628 (define_insn "*iordi3_ss"
4629 [(set (match_operand:DI 0 "s_operand" "=Qo")
4630 (ior:DI (match_dup 0)
4631 (match_operand:DI 1 "s_imm_operand" "Qo")))
4632 (clobber (reg:CC 33))]
4633 ""
4634 "oc\\t%O0(8,%R0),%1"
4635 [(set_attr "op_type" "SS")
4636 (set_attr "atype" "mem")])
4637
4638 (define_insn "*iordi3_ss_inv"
4639 [(set (match_operand:DI 0 "s_operand" "=Qo")
4640 (ior:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4641 (match_dup 0)))
4642 (clobber (reg:CC 33))]
4643 ""
4644 "oc\\t%O0(8,%R0),%1"
4645 [(set_attr "op_type" "SS")
4646 (set_attr "atype" "mem")])
4647
4648 ;
4649 ; iorsi3 instruction pattern(s).
4650 ;
4651
4652 (define_insn "*iorsi3_cc"
4653 [(set (reg 33)
4654 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4655 (match_operand:SI 2 "general_operand" "d,m"))
4656 (const_int 0)))
4657 (set (match_operand:SI 0 "register_operand" "=d,d")
4658 (ior:SI (match_dup 1) (match_dup 2)))]
4659 "s390_match_ccmode(insn, CCTmode)"
4660 "@
4661 or\\t%0,%2
4662 o\\t%0,%2"
4663 [(set_attr "op_type" "RR,RX")
4664 (set_attr "atype" "reg,mem")])
4665
4666 (define_insn "*iorsi3_cconly"
4667 [(set (reg 33)
4668 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4669 (match_operand:SI 2 "general_operand" "d,m"))
4670 (const_int 0)))
4671 (clobber (match_scratch:SI 0 "=d,d"))]
4672 "s390_match_ccmode(insn, CCTmode)"
4673 "@
4674 or\\t%0,%2
4675 o\\t%0,%2"
4676 [(set_attr "op_type" "RR,RX")
4677 (set_attr "atype" "reg,mem")])
4678
4679 (define_insn "*iorsi3_oi"
4680 [(set (match_operand:SI 0 "register_operand" "=d")
4681 (ior:SI (match_operand:SI 1 "register_operand" "%0")
4682 (match_operand:SI 2 "immediate_operand" "n")))
4683 (clobber (reg:CC 33))]
4684 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4685 "*
4686 {
4687 int part = s390_single_hi (operands[2], SImode, 0);
4688 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4689
4690 switch (part)
4691 {
4692 case 0: return \"oilh\\t%0,%x2\";
4693 case 1: return \"oill\\t%0,%x2\";
4694 default: abort ();
4695 }
4696 }"
4697 [(set_attr "op_type" "RI")
4698 (set_attr "atype" "reg")])
4699
4700 (define_insn "iorsi3"
4701 [(set (match_operand:SI 0 "register_operand" "=d,d")
4702 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4703 (match_operand:SI 2 "general_operand" "d,m")))
4704 (clobber (reg:CC 33))]
4705 ""
4706 "@
4707 or\\t%0,%2
4708 o\\t%0,%2"
4709 [(set_attr "op_type" "RR,RX")
4710 (set_attr "atype" "reg,mem")])
4711
4712 (define_insn "*iorsi3_ss"
4713 [(set (match_operand:SI 0 "s_operand" "=Qo")
4714 (ior:SI (match_dup 0)
4715 (match_operand:SI 1 "s_imm_operand" "Qo")))
4716 (clobber (reg:CC 33))]
4717 ""
4718 "oc\\t%O0(4,%R0),%1"
4719 [(set_attr "op_type" "SS")
4720 (set_attr "atype" "mem")])
4721
4722 (define_insn "*iorsi3_ss_inv"
4723 [(set (match_operand:SI 0 "s_operand" "=Qo")
4724 (ior:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4725 (match_dup 0)))
4726 (clobber (reg:CC 33))]
4727 ""
4728 "oc\\t%O0(4,%R0),%1"
4729 [(set_attr "op_type" "SS")
4730 (set_attr "atype" "mem")])
4731
4732 ;
4733 ; iorhi3 instruction pattern(s).
4734 ;
4735
4736 (define_insn "*iorhi3_oi"
4737 [(set (match_operand:HI 0 "register_operand" "=d,d")
4738 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4739 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4740 (clobber (reg:CC 33))]
4741 "TARGET_64BIT"
4742 "@
4743 or\\t%0,%2
4744 oill\\t%0,%x2"
4745 [(set_attr "op_type" "RR,RI")
4746 (set_attr "atype" "reg")])
4747
4748 (define_insn "iorhi3"
4749 [(set (match_operand:HI 0 "register_operand" "=d")
4750 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4751 (match_operand:HI 2 "nonmemory_operand" "d")))
4752 (clobber (reg:CC 33))]
4753 ""
4754 "or\\t%0,%2"
4755 [(set_attr "op_type" "RR")
4756 (set_attr "atype" "reg")])
4757
4758 (define_insn "*iorhi3_ss"
4759 [(set (match_operand:HI 0 "s_operand" "=Qo")
4760 (ior:HI (match_dup 0)
4761 (match_operand:HI 1 "s_imm_operand" "Qo")))
4762 (clobber (reg:CC 33))]
4763 ""
4764 "oc\\t%O0(2,%R0),%1"
4765 [(set_attr "op_type" "SS")
4766 (set_attr "atype" "mem")])
4767
4768 (define_insn "*iorhi3_ss_inv"
4769 [(set (match_operand:HI 0 "s_operand" "=Qo")
4770 (ior:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4771 (match_dup 0)))
4772 (clobber (reg:CC 33))]
4773 ""
4774 "oc\\t%O0(2,%R0),%1"
4775 [(set_attr "op_type" "SS")
4776 (set_attr "atype" "mem")])
4777
4778 ;
4779 ; iorqi3 instruction pattern(s).
4780 ;
4781
4782 (define_insn "*iorqi3_oi"
4783 [(set (match_operand:QI 0 "register_operand" "=d,d")
4784 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4785 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4786 (clobber (reg:CC 33))]
4787 "TARGET_64BIT"
4788 "@
4789 or\\t%0,%2
4790 oill\\t%0,%b2"
4791 [(set_attr "op_type" "RR,RI")
4792 (set_attr "atype" "reg")])
4793
4794 (define_insn "iorqi3"
4795 [(set (match_operand:QI 0 "register_operand" "=d")
4796 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4797 (match_operand:QI 2 "nonmemory_operand" "d")))
4798 (clobber (reg:CC 33))]
4799 ""
4800 "or\\t%0,%2"
4801 [(set_attr "op_type" "RR")
4802 (set_attr "atype" "reg")])
4803
4804 (define_insn "*iorqi3_ss"
4805 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4806 (ior:QI (match_dup 0)
4807 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4808 (clobber (reg:CC 33))]
4809 ""
4810 "@
4811 oi\\t%0,%b1
4812 oc\\t%O0(1,%R0),%1"
4813 [(set_attr "op_type" "SI,SS")
4814 (set_attr "atype" "reg,mem")])
4815
4816 (define_insn "*iorqi3_ss_inv"
4817 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4818 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4819 (match_dup 0)))
4820 (clobber (reg:CC 33))]
4821 ""
4822 "@
4823 oi\\t%0,%b1
4824 oc\\t%O0(1,%R0),%1"
4825 [(set_attr "op_type" "SI,SS")
4826 (set_attr "atype" "reg,mem")])
4827
4828
4829 ;;
4830 ;;- Xor instructions.
4831 ;;
4832
4833 ;
4834 ; xordi3 instruction pattern(s).
4835 ;
4836
4837 (define_insn "*xordi3_cc"
4838 [(set (reg 33)
4839 (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4840 (match_operand:DI 2 "general_operand" "d,m"))
4841 (const_int 0)))
4842 (set (match_operand:DI 0 "register_operand" "=d,d")
4843 (xor:DI (match_dup 1) (match_dup 2)))]
4844 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4845 "@
4846 xgr\\t%0,%2
4847 xg\\t%0,%2"
4848 [(set_attr "op_type" "RRE,RXE")
4849 (set_attr "atype" "reg,mem")])
4850
4851 (define_insn "*xordi3_cconly"
4852 [(set (reg 33)
4853 (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4854 (match_operand:DI 2 "general_operand" "d,m"))
4855 (const_int 0)))
4856 (clobber (match_scratch:DI 0 "=d,d"))]
4857 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4858 "@
4859 xgr\\t%0,%2
4860 xr\\t%0,%2"
4861 [(set_attr "op_type" "RRE,RXE")
4862 (set_attr "atype" "reg,mem")])
4863
4864 (define_insn "xordi3"
4865 [(set (match_operand:DI 0 "register_operand" "=d,d")
4866 (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4867 (match_operand:DI 2 "general_operand" "d,m")))
4868 (clobber (reg:CC 33))]
4869 "TARGET_64BIT"
4870 "@
4871 xgr\\t%0,%2
4872 xg\\t%0,%2"
4873 [(set_attr "op_type" "RRE,RXE")
4874 (set_attr "atype" "reg,mem")])
4875
4876 (define_insn "*xordi3_ss"
4877 [(set (match_operand:DI 0 "s_operand" "=Qo")
4878 (xor:DI (match_dup 0)
4879 (match_operand:DI 1 "s_imm_operand" "Qo")))
4880 (clobber (reg:CC 33))]
4881 ""
4882 "xc\\t%O0(8,%R0),%1"
4883 [(set_attr "op_type" "SS")
4884 (set_attr "atype" "mem")])
4885
4886 (define_insn "*xordi3_ss_inv"
4887 [(set (match_operand:DI 0 "s_operand" "=Qo")
4888 (xor:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4889 (match_dup 0)))
4890 (clobber (reg:CC 33))]
4891 ""
4892 "xc\\t%O0(8,%R0),%1"
4893 [(set_attr "op_type" "SS")
4894 (set_attr "atype" "mem")])
4895
4896 ;
4897 ; xorsi3 instruction pattern(s).
4898 ;
4899
4900 (define_insn "*xorsi3_cc"
4901 [(set (reg 33)
4902 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4903 (match_operand:SI 2 "general_operand" "d,m"))
4904 (const_int 0)))
4905 (set (match_operand:SI 0 "register_operand" "=d,d")
4906 (xor:SI (match_dup 1) (match_dup 2)))]
4907 "s390_match_ccmode(insn, CCTmode)"
4908 "@
4909 xr\\t%0,%2
4910 x\\t%0,%2"
4911 [(set_attr "op_type" "RR,RX")
4912 (set_attr "atype" "reg,mem")])
4913
4914 (define_insn "*xorsi3_cconly"
4915 [(set (reg 33)
4916 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4917 (match_operand:SI 2 "general_operand" "d,m"))
4918 (const_int 0)))
4919 (clobber (match_scratch:SI 0 "=d,d"))]
4920 "s390_match_ccmode(insn, CCTmode)"
4921 "@
4922 xr\\t%0,%2
4923 x\\t%0,%2"
4924 [(set_attr "op_type" "RR,RX")
4925 (set_attr "atype" "reg,mem")])
4926
4927 (define_insn "xorsi3"
4928 [(set (match_operand:SI 0 "register_operand" "=d,d")
4929 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4930 (match_operand:SI 2 "general_operand" "d,m")))
4931 (clobber (reg:CC 33))]
4932 ""
4933 "@
4934 xr\\t%0,%2
4935 x\\t%0,%2"
4936 [(set_attr "op_type" "RR,RX")
4937 (set_attr "atype" "reg,mem")])
4938
4939 (define_insn "*xorsi3_ss"
4940 [(set (match_operand:SI 0 "s_operand" "=Qo")
4941 (xor:SI (match_dup 0)
4942 (match_operand:SI 1 "s_imm_operand" "Qo")))
4943 (clobber (reg:CC 33))]
4944 ""
4945 "xc\\t%O0(4,%R0),%1"
4946 [(set_attr "op_type" "SS")
4947 (set_attr "atype" "mem")])
4948
4949 (define_insn "*xorsi3_ss_inv"
4950 [(set (match_operand:SI 0 "s_operand" "=Qo")
4951 (xor:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4952 (match_dup 0)))
4953 (clobber (reg:CC 33))]
4954 ""
4955 "xc\\t%O0(4,%R0),%1"
4956 [(set_attr "op_type" "SS")
4957 (set_attr "atype" "mem")])
4958
4959 ;
4960 ; xorhi3 instruction pattern(s).
4961 ;
4962
4963 (define_insn "xorhi3"
4964 [(set (match_operand:HI 0 "register_operand" "=d")
4965 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4966 (match_operand:HI 2 "nonmemory_operand" "d")))
4967 (clobber (reg:CC 33))]
4968 ""
4969 "xr\\t%0,%2"
4970 [(set_attr "op_type" "RR")
4971 (set_attr "atype" "reg")])
4972
4973 (define_insn "*xorhi3_ss"
4974 [(set (match_operand:HI 0 "s_operand" "=Qo")
4975 (xor:HI (match_dup 0)
4976 (match_operand:HI 1 "s_imm_operand" "Qo")))
4977 (clobber (reg:CC 33))]
4978 ""
4979 "xc\\t%O0(2,%R0),%1"
4980 [(set_attr "op_type" "SS")
4981 (set_attr "atype" "mem")])
4982
4983 (define_insn "*xorhi3_ss_inv"
4984 [(set (match_operand:HI 0 "s_operand" "=Qo")
4985 (xor:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4986 (match_dup 0)))
4987 (clobber (reg:CC 33))]
4988 ""
4989 "xc\\t%O0(2,%R0),%1"
4990 [(set_attr "op_type" "SS")
4991 (set_attr "atype" "mem")])
4992
4993 ;
4994 ; xorqi3 instruction pattern(s).
4995 ;
4996
4997 (define_insn "xorqi3"
4998 [(set (match_operand:QI 0 "register_operand" "=d")
4999 (xor:QI (match_operand:QI 1 "register_operand" "%0")
5000 (match_operand:QI 2 "nonmemory_operand" "d")))
5001 (clobber (reg:CC 33))]
5002 ""
5003 "xr\\t%0,%2"
5004 [(set_attr "op_type" "RR")
5005 (set_attr "atype" "reg")])
5006
5007 (define_insn "*xorqi3_ss"
5008 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
5009 (xor:QI (match_dup 0)
5010 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
5011 (clobber (reg:CC 33))]
5012 ""
5013 "@
5014 xi\\t%0,%b1
5015 xc\\t%O0(1,%R0),%1"
5016 [(set_attr "op_type" "SI,SS")
5017 (set_attr "atype" "mem")])
5018
5019 (define_insn "*xorqi3_ss_inv"
5020 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
5021 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
5022 (match_dup 0)))
5023 (clobber (reg:CC 33))]
5024 ""
5025 "@
5026 xi\\t%0,%b1
5027 xc\\t%O0(1,%R0),%1"
5028 [(set_attr "op_type" "SI,SS")
5029 (set_attr "atype" "mem")])
5030
5031
5032 ;;
5033 ;;- Negate instructions.
5034 ;;
5035
5036 ;
5037 ; negdi2 instruction pattern(s).
5038 ;
5039
5040 (define_expand "negdi2"
5041 [(parallel
5042 [(set (match_operand:DI 0 "register_operand" "=d")
5043 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5044 (clobber (reg:CC 33))])]
5045 ""
5046 "")
5047
5048 (define_insn "*negdi2_64"
5049 [(set (match_operand:DI 0 "register_operand" "=d")
5050 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5051 (clobber (reg:CC 33))]
5052 "TARGET_64BIT"
5053 "lcgr\\t%0,%1"
5054 [(set_attr "op_type" "RR")])
5055
5056 (define_insn "*negdi2_31"
5057 [(set (match_operand:DI 0 "register_operand" "=d")
5058 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5059 (clobber (reg:CC 33))]
5060 "!TARGET_64BIT"
5061 "*
5062 {
5063 rtx xop[1];
5064 xop[0] = gen_label_rtx ();
5065 output_asm_insn (\"lcr\\t%0,%1\", operands);
5066 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5067 output_asm_insn (\"je\\t%l0\", xop);
5068 output_asm_insn (\"bctr\\t%0,0\", operands);
5069 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5070 CODE_LABEL_NUMBER (xop[0]));
5071 return \"\";
5072 }"
5073 [(set_attr "op_type" "NN")
5074 (set_attr "type" "other")
5075 (set_attr "length" "10")])
5076
5077 ;
5078 ; negsi2 instruction pattern(s).
5079 ;
5080
5081 (define_insn "negsi2"
5082 [(set (match_operand:SI 0 "register_operand" "=d")
5083 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5084 (clobber (reg:CC 33))]
5085 ""
5086 "lcr\\t%0,%1"
5087 [(set_attr "op_type" "RR")])
5088
5089 ;
5090 ; negdf2 instruction pattern(s).
5091 ;
5092
5093 (define_expand "negdf2"
5094 [(parallel
5095 [(set (match_operand:DF 0 "register_operand" "=f")
5096 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5097 (clobber (reg:CC 33))])]
5098 "TARGET_HARD_FLOAT"
5099 "")
5100
5101 (define_insn "*negdf2"
5102 [(set (match_operand:DF 0 "register_operand" "=f")
5103 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5104 (clobber (reg:CC 33))]
5105 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5106 "lcdbr\\t%0,%1"
5107 [(set_attr "op_type" "RR")])
5108
5109 (define_insn "*negdf2_ibm"
5110 [(set (match_operand:DF 0 "register_operand" "=f")
5111 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5112 (clobber (reg:CC 33))]
5113 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5114 "lcdr\\t%0,%1"
5115 [(set_attr "op_type" "RR")])
5116
5117 ;
5118 ; negsf2 instruction pattern(s).
5119 ;
5120
5121 (define_expand "negsf2"
5122 [(parallel
5123 [(set (match_operand:SF 0 "register_operand" "=f")
5124 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5125 (clobber (reg:CC 33))])]
5126 "TARGET_HARD_FLOAT"
5127 "")
5128
5129 (define_insn "*negsf2"
5130 [(set (match_operand:SF 0 "register_operand" "=f")
5131 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5132 (clobber (reg:CC 33))]
5133 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5134 "lcebr\\t%0,%1"
5135 [(set_attr "op_type" "RR")])
5136
5137 (define_insn "*negsf2"
5138 [(set (match_operand:SF 0 "register_operand" "=f")
5139 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5140 (clobber (reg:CC 33))]
5141 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5142 "lcer\\t%0,%1"
5143 [(set_attr "op_type" "RR")])
5144
5145
5146 ;;
5147 ;;- Absolute value instructions.
5148 ;;
5149
5150 ;
5151 ; absdi2 instruction pattern(s).
5152 ;
5153
5154 (define_insn "absdi2"
5155 [(set (match_operand:DI 0 "register_operand" "=d")
5156 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5157 (clobber (reg:CC 33))]
5158 "TARGET_64BIT"
5159 "lpgr\\t%0,%1"
5160 [(set_attr "op_type" "RRE")])
5161
5162 ;
5163 ; abssi2 instruction pattern(s).
5164 ;
5165
5166 (define_insn "abssi2"
5167 [(set (match_operand:SI 0 "register_operand" "=d")
5168 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5169 (clobber (reg:CC 33))]
5170 ""
5171 "lpr\\t%0,%1"
5172 [(set_attr "op_type" "RR")])
5173
5174 ;
5175 ; absdf2 instruction pattern(s).
5176 ;
5177
5178 (define_expand "absdf2"
5179 [(parallel
5180 [(set (match_operand:DF 0 "register_operand" "=f")
5181 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5182 (clobber (reg:CC 33))])]
5183 "TARGET_HARD_FLOAT"
5184 "")
5185
5186 (define_insn "*absdf2"
5187 [(set (match_operand:DF 0 "register_operand" "=f")
5188 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5189 (clobber (reg:CC 33))]
5190 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5191 "lpdbr\\t%0,%1"
5192 [(set_attr "op_type" "RR")])
5193
5194 (define_insn "*absdf2_ibm"
5195 [(set (match_operand:DF 0 "register_operand" "=f")
5196 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5197 (clobber (reg:CC 33))]
5198 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5199 "lpdr\\t%0,%1"
5200 [(set_attr "op_type" "RR")])
5201
5202 ;
5203 ; abssf2 instruction pattern(s).
5204 ;
5205
5206 (define_expand "abssf2"
5207 [(parallel
5208 [(set (match_operand:SF 0 "register_operand" "=f")
5209 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5210 (clobber (reg:CC 33))])]
5211 "TARGET_HARD_FLOAT"
5212 "")
5213
5214 (define_insn "*abssf2"
5215 [(set (match_operand:SF 0 "register_operand" "=f")
5216 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5217 (clobber (reg:CC 33))]
5218 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5219 "lpebr\\t%0,%1"
5220 [(set_attr "op_type" "RR")])
5221
5222 (define_insn "*abssf2_ibm"
5223 [(set (match_operand:SF 0 "register_operand" "=f")
5224 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5225 (clobber (reg:CC 33))]
5226 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5227 "lper\\t%0,%1"
5228 [(set_attr "op_type" "RR")])
5229
5230 ;;
5231 ;;- Square root instructions.
5232 ;;
5233
5234 ;
5235 ; sqrtdf2 instruction pattern(s).
5236 ;
5237
5238 (define_insn "sqrtdf2"
5239 [(set (match_operand:DF 0 "register_operand" "=f,f")
5240 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5241 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5242 "@
5243 sqdbr\\t%0,%1
5244 sqdb\\t%0,%1"
5245 [(set_attr "op_type" "RRE,RSE")])
5246
5247 ;
5248 ; sqrtsf2 instruction pattern(s).
5249 ;
5250
5251 (define_insn "sqrtsf2"
5252 [(set (match_operand:SF 0 "register_operand" "=f,f")
5253 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5254 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5255 "@
5256 sqebr\\t%0,%1
5257 sqeb\\t%0,%1"
5258 [(set_attr "op_type" "RRE,RSE")])
5259
5260 ;;
5261 ;;- One complement instructions.
5262 ;;
5263
5264 ;
5265 ; one_cmpldi2 instruction pattern(s).
5266 ;
5267
5268 (define_expand "one_cmpldi2"
5269 [(parallel
5270 [(set (match_operand:DI 0 "register_operand" "")
5271 (xor:DI (match_operand:DI 1 "register_operand" "")
5272 (const_int -1)))
5273 (clobber (reg:CC 33))])]
5274 "TARGET_64BIT"
5275 "")
5276
5277 ;
5278 ; one_cmplsi2 instruction pattern(s).
5279 ;
5280
5281 (define_expand "one_cmplsi2"
5282 [(parallel
5283 [(set (match_operand:SI 0 "register_operand" "")
5284 (xor:SI (match_operand:SI 1 "register_operand" "")
5285 (const_int -1)))
5286 (clobber (reg:CC 33))])]
5287 ""
5288 "")
5289
5290 ;
5291 ; one_cmplhi2 instruction pattern(s).
5292 ;
5293
5294 (define_expand "one_cmplhi2"
5295 [(parallel
5296 [(set (match_operand:HI 0 "register_operand" "")
5297 (xor:HI (match_operand:HI 1 "register_operand" "")
5298 (const_int -1)))
5299 (clobber (reg:CC 33))])]
5300 ""
5301 "")
5302
5303 ;
5304 ; one_cmplqi2 instruction pattern(s).
5305 ;
5306
5307 (define_expand "one_cmplqi2"
5308 [(parallel
5309 [(set (match_operand:QI 0 "register_operand" "")
5310 (xor:QI (match_operand:QI 1 "register_operand" "")
5311 (const_int -1)))
5312 (clobber (reg:CC 33))])]
5313 ""
5314 "")
5315
5316
5317 ;;
5318 ;;- Rotate instructions.
5319 ;;
5320
5321 ;
5322 ; rotldi3 instruction pattern(s).
5323 ;
5324
5325 (define_insn "rotldi3"
5326 [(set (match_operand:DI 0 "register_operand" "=d,d")
5327 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5328 (match_operand:DI 2 "nonmemory_operand" "J,a")))
5329 (clobber (reg:CC 33))]
5330 "TARGET_64BIT"
5331 "@
5332 rllg\\t%0,%1,%c2
5333 rllg\\t%0,%1,0(%2)"
5334 [(set_attr "op_type" "RSE")])
5335
5336 ;
5337 ; rotlsi3 instruction pattern(s).
5338 ;
5339
5340 (define_insn "rotlsi3"
5341 [(set (match_operand:SI 0 "register_operand" "=d,d")
5342 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5343 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5344 (clobber (reg:CC 33))]
5345 "TARGET_64BIT"
5346 "@
5347 rll\\t%0,%1,%c2
5348 rll\\t%0,%1,0(%2)"
5349 [(set_attr "op_type" "RSE")])
5350
5351
5352 ;;
5353 ;;- Arithmetic shift instructions.
5354 ;;
5355 ;; for left shifts always setal shifts are used (ANSI-C)
5356
5357 ;
5358 ; ashldi3 instruction pattern(s).
5359 ;
5360
5361 (define_expand "ashldi3"
5362 [(parallel
5363 [(set (match_operand:DI 0 "register_operand" "")
5364 (ashift:DI (match_operand:DI 1 "register_operand" "")
5365 (match_operand:SI 2 "nonmemory_operand" "")))
5366 (clobber (reg:CC 33))])]
5367 ""
5368 "")
5369
5370 (define_insn "*ashldi3_31"
5371 [(set (match_operand:DI 0 "register_operand" "=d,d")
5372 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5373 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5374 (clobber (reg:CC 33))]
5375 "!TARGET_64BIT"
5376 "@
5377 sldl\\t%0,%c2
5378 sldl\\t%0,0(%2)"
5379 [(set_attr "op_type" "RS")])
5380
5381 (define_insn "*ashldi3_64"
5382 [(set (match_operand:DI 0 "register_operand" "=d,d")
5383 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5384 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5385 (clobber (reg:CC 33))]
5386 "TARGET_64BIT"
5387 "@
5388 sllg\\t%0,%1,%2
5389 sllg\\t%0,%1,0(%2)"
5390 [(set_attr "op_type" "RSE")])
5391
5392 ;
5393 ; ashrdi3 instruction pattern(s).
5394 ;
5395
5396 (define_expand "ashrdi3"
5397 [(parallel
5398 [(set (match_operand:DI 0 "register_operand" "")
5399 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5400 (match_operand:SI 2 "nonmemory_operand" "")))
5401 (clobber (reg:CC 33))])]
5402 ""
5403 "")
5404
5405 (define_insn "*ashrdi3_31"
5406 [(set (match_operand:DI 0 "register_operand" "=d,d")
5407 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5408 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5409 (clobber (reg:CC 33))]
5410 "!TARGET_64BIT"
5411 "@
5412 srda\\t%0,%c2
5413 srda\\t%0,0(%2)"
5414 [(set_attr "op_type" "RS")])
5415
5416 (define_insn "*ashrdi3_64"
5417 [(set (match_operand:DI 0 "register_operand" "=d,d")
5418 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5419 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5420 (clobber (reg:CC 33))]
5421 "TARGET_64BIT"
5422 "@
5423 srag\\t%0,%1,%c2
5424 srag\\t%0,%1,0(%2)"
5425 [(set_attr "op_type" "RSE")])
5426
5427 ;
5428 ; ashlsi3 instruction pattern(s).
5429 ;
5430 ; all 32 bits has to be shifted (testcase co750c)
5431
5432 (define_insn "ashlsi3"
5433 [(set (match_operand:SI 0 "register_operand" "=d,d")
5434 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5435 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5436 (clobber (reg:CC 33))]
5437 ""
5438 "@
5439 sll\\t%0,%c2
5440 sll\\t%0,0(%2)"
5441 [(set_attr "op_type" "RS")])
5442
5443 ;
5444 ; ashrsi3 instruction pattern(s).
5445 ;
5446
5447 (define_insn "ashrsi3"
5448 [(set (match_operand:SI 0 "register_operand" "=d,d")
5449 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5450 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5451 (clobber (reg:CC 33))]
5452 ""
5453 "@
5454 sra\\t%0,%c2
5455 sra\\t%0,0(%2)"
5456 [(set_attr "op_type" "RS")])
5457
5458
5459 ;;
5460 ;;- logical shift instructions.
5461 ;;
5462
5463 ;
5464 ; lshrdi3 instruction pattern(s).
5465 ;
5466
5467 (define_expand "lshrdi3"
5468 [(parallel
5469 [(set (match_operand:DI 0 "register_operand" "")
5470 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5471 (match_operand:SI 2 "nonmemory_operand" "")))
5472 (clobber (reg:CC 33))])]
5473 ""
5474 "")
5475
5476 (define_insn "*lshrdi3_31"
5477 [(set (match_operand:DI 0 "register_operand" "=d,d")
5478 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5479 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5480 (clobber (reg:CC 33))]
5481 "!TARGET_64BIT"
5482 "@
5483 srdl\\t%0,%c2
5484 srdl\\t%0,0(%2)"
5485 [(set_attr "op_type" "RS,RS")])
5486
5487 (define_insn "*lshrdi3_64"
5488 [(set (match_operand:DI 0 "register_operand" "=d,d")
5489 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5490 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5491 (clobber (reg:CC 33))]
5492 "TARGET_64BIT"
5493 "@
5494 srlg\\t%0,%1,%c2
5495 srlg\\t%0,%1,0(%2)"
5496 [(set_attr "op_type" "RS,RS")])
5497
5498 ;
5499 ; lshrsi3 instruction pattern(s).
5500 ;
5501
5502 (define_insn "lshrsi3"
5503 [(set (match_operand:SI 0 "register_operand" "=d,d")
5504 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5505 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5506 (clobber (reg:CC 33))]
5507 ""
5508 "@
5509 srl\\t%0,%c2
5510 srl\\t%0,0(%2)"
5511 [(set_attr "op_type" "RS")])
5512
5513
5514 ;;
5515 ;; Branch instruction patterns.
5516 ;;
5517
5518 (define_expand "beq"
5519 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5520 (set (pc)
5521 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5522 (label_ref (match_operand 0 "" ""))
5523 (pc)))]
5524 ""
5525 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5526
5527 (define_expand "bne"
5528 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5529 (set (pc)
5530 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5531 (label_ref (match_operand 0 "" ""))
5532 (pc)))]
5533 ""
5534 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5535
5536 (define_expand "bgt"
5537 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5538 (set (pc)
5539 (if_then_else (gt (reg:CCS 33) (const_int 0))
5540 (label_ref (match_operand 0 "" ""))
5541 (pc)))]
5542 ""
5543 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5544
5545 (define_expand "bgtu"
5546 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5547 (set (pc)
5548 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5549 (label_ref (match_operand 0 "" ""))
5550 (pc)))]
5551 ""
5552 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5553
5554 (define_expand "blt"
5555 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5556 (set (pc)
5557 (if_then_else (lt (reg:CCS 33) (const_int 0))
5558 (label_ref (match_operand 0 "" ""))
5559 (pc)))]
5560 ""
5561 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5562
5563 (define_expand "bltu"
5564 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5565 (set (pc)
5566 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5567 (label_ref (match_operand 0 "" ""))
5568 (pc)))]
5569 ""
5570 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5571
5572 (define_expand "bge"
5573 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5574 (set (pc)
5575 (if_then_else (ge (reg:CCS 33) (const_int 0))
5576 (label_ref (match_operand 0 "" ""))
5577 (pc)))]
5578 ""
5579 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5580
5581 (define_expand "bgeu"
5582 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5583 (set (pc)
5584 (if_then_else (geu (reg:CCU 33) (const_int 0))
5585 (label_ref (match_operand 0 "" ""))
5586 (pc)))]
5587 ""
5588 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5589
5590 (define_expand "ble"
5591 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5592 (set (pc)
5593 (if_then_else (le (reg:CCS 33) (const_int 0))
5594 (label_ref (match_operand 0 "" ""))
5595 (pc)))]
5596 ""
5597 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5598
5599 (define_expand "bleu"
5600 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5601 (set (pc)
5602 (if_then_else (leu (reg:CCU 33) (const_int 0))
5603 (label_ref (match_operand 0 "" ""))
5604 (pc)))]
5605 ""
5606 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5607
5608 (define_expand "bunordered"
5609 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5610 (set (pc)
5611 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5612 (label_ref (match_operand 0 "" ""))
5613 (pc)))]
5614 ""
5615 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5616
5617 (define_expand "bordered"
5618 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5619 (set (pc)
5620 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5621 (label_ref (match_operand 0 "" ""))
5622 (pc)))]
5623 ""
5624 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5625
5626 (define_expand "buneq"
5627 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5628 (set (pc)
5629 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5630 (label_ref (match_operand 0 "" ""))
5631 (pc)))]
5632 ""
5633 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5634
5635 (define_expand "bungt"
5636 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5637 (set (pc)
5638 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5639 (label_ref (match_operand 0 "" ""))
5640 (pc)))]
5641 ""
5642 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5643
5644 (define_expand "bunlt"
5645 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5646 (set (pc)
5647 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5648 (label_ref (match_operand 0 "" ""))
5649 (pc)))]
5650 ""
5651 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5652
5653 (define_expand "bunge"
5654 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5655 (set (pc)
5656 (if_then_else (unge (reg:CCS 33) (const_int 0))
5657 (label_ref (match_operand 0 "" ""))
5658 (pc)))]
5659 ""
5660 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5661
5662 (define_expand "bunle"
5663 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5664 (set (pc)
5665 (if_then_else (unle (reg:CCS 33) (const_int 0))
5666 (label_ref (match_operand 0 "" ""))
5667 (pc)))]
5668 ""
5669 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5670
5671 (define_expand "bltgt"
5672 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5673 (set (pc)
5674 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5675 (label_ref (match_operand 0 "" ""))
5676 (pc)))]
5677 ""
5678 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5679
5680
5681 ;;
5682 ;;- Conditional jump instructions.
5683 ;;
5684
5685 (define_insn "cjump"
5686 [(set (pc)
5687 (if_then_else
5688 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5689 (label_ref (match_operand 0 "" ""))
5690 (pc)))]
5691 ""
5692 "*
5693 {
5694 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5695 return \"j%C1\\t%l0\";
5696 else
5697 return \"jg%C1\\t%l0\";
5698 }"
5699 [(set_attr "op_type" "RI")
5700 (set (attr "length") (if_then_else
5701 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5702 (const_int 4) (const_int 6)))])
5703
5704 (define_insn "*cjump_long"
5705 [(set (pc)
5706 (if_then_else
5707 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5708 (match_operand 0 "address_operand" "p")
5709 (pc)))]
5710 ""
5711 "*
5712 {
5713 if (get_attr_op_type (insn) == OP_TYPE_RR)
5714 return \"b%C1r\\t%0\";
5715 else
5716 return \"b%C1\\t%a0\";
5717 }"
5718 [(set (attr "op_type")
5719 (if_then_else (match_operand 0 "register_operand" "")
5720 (const_string "RR") (const_string "RX")))
5721 (set_attr "atype" "mem")])
5722
5723
5724 ;;
5725 ;;- Negated conditional jump instructions.
5726 ;;
5727
5728 (define_insn "icjump"
5729 [(set (pc)
5730 (if_then_else
5731 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5732 (pc)
5733 (label_ref (match_operand 0 "" ""))))]
5734 ""
5735 "*
5736 {
5737 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5738 return \"j%D1\\t%l0\";
5739 else
5740 return \"jg%D1\\t%l0\";
5741 }"
5742 [(set_attr "op_type" "RI")
5743 (set (attr "length") (if_then_else
5744 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5745 (const_int 4) (const_int 6)))])
5746
5747 (define_insn "*icjump_long"
5748 [(set (pc)
5749 (if_then_else
5750 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5751 (pc)
5752 (match_operand 0 "address_operand" "p")))]
5753 ""
5754 "*
5755 {
5756 if (get_attr_op_type (insn) == OP_TYPE_RR)
5757 return \"b%D1r\\t%0\";
5758 else
5759 return \"b%D1\\t%a0\";
5760 }"
5761 [(set (attr "op_type")
5762 (if_then_else (match_operand 0 "register_operand" "")
5763 (const_string "RR") (const_string "RX")))
5764 (set_attr "atype" "mem")])
5765
5766
5767 ;;
5768 ;;- Subtract one and jump if not zero.
5769 ;;
5770
5771 ;(define_expand "decrement_and_branch_on_count"
5772 ; [(use (match_operand 0 "register_operand" ""))
5773 ; (use (label_ref (match_operand 1 "" "")))]
5774 ; ""
5775 ; "
5776 ;{
5777 ;/* if (TARGET_64BIT)
5778 ; emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5779 ; else */
5780 ; emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5781 ; DONE;
5782 ;}")
5783 ;
5784 ;(define_insn "brctsi"
5785 ; [(set (pc)
5786 ; (if_then_else
5787 ; (ne (match_operand:SI 0 "register_operand" "+a")
5788 ; (const_int 1))
5789 ; (label_ref (match_operand 1 "" ""))
5790 ; (pc)))
5791 ; (set (match_dup 0)
5792 ; (plus:SI (match_dup 0) (const_int -1)))]
5793 ; ""
5794 ; "brct\\t%0,%l1"
5795 ; [(set_attr "op_type" "RI")
5796 ; (set_attr "type" "branch")]
5797 ;)
5798 ;
5799 ;(define_insn "ibrctsi"
5800 ; [(set (pc)
5801 ; (if_then_else
5802 ; (eq (match_operand:SI 0 "register_operand" "+a")
5803 ; (const_int 1))
5804 ; (pc)
5805 ; (label_ref (match_operand 1 "" ""))))
5806 ; (set (match_dup 0)
5807 ; (plus:SI (match_dup 0) (const_int -1)))]
5808 ; ""
5809 ; "brct\\t%0,%l1"
5810 ; [(set_attr "op_type" "RI")
5811 ; (set_attr "type" "branch")]
5812 ;)
5813
5814
5815 ;;
5816 ;;- Unconditional jump instructions.
5817 ;;
5818
5819 ;
5820 ; jump instruction pattern(s).
5821 ;
5822
5823 (define_insn "jump"
5824 [(set (pc) (label_ref (match_operand 0 "" "")))]
5825 ""
5826 "*
5827 {
5828 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5829 return \"j\\t%l0\";
5830 else
5831 return \"jg\\t%l0\";
5832 }"
5833 [(set_attr "op_type" "RI")
5834 (set (attr "length") (if_then_else
5835 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5836 (const_int 4) (const_int 6)))])
5837
5838 ;
5839 ; indirect-jump instruction pattern(s).
5840 ;
5841
5842 (define_insn "indirect_jump"
5843 [(set (pc) (match_operand 0 "address_operand" "p"))]
5844 ""
5845 "*
5846 {
5847 if (get_attr_op_type (insn) == OP_TYPE_RR)
5848 return \"br\\t%0\";
5849 else
5850 return \"b\\t%a0\";
5851 }"
5852 [(set (attr "op_type")
5853 (if_then_else (match_operand 0 "register_operand" "")
5854 (const_string "RR") (const_string "RX")))
5855 (set_attr "atype" "mem")])
5856
5857 ;
5858 ; casesi instruction pattern(s).
5859 ;
5860
5861 (define_insn "casesi_jump"
5862 [(set (pc) (match_operand 0 "address_operand" "p"))
5863 (use (label_ref (match_operand 1 "" "")))]
5864 ""
5865 "*
5866 {
5867 if (get_attr_op_type (insn) == OP_TYPE_RR)
5868 return \"br\\t%0\";
5869 else
5870 return \"b\\t%a0\";
5871 }"
5872 [(set (attr "op_type")
5873 (if_then_else (match_operand 0 "register_operand" "")
5874 (const_string "RR") (const_string "RX")))
5875 (set_attr "atype" "mem")])
5876
5877 (define_expand "casesi"
5878 [(match_operand:SI 0 "general_operand" "")
5879 (match_operand:SI 1 "general_operand" "")
5880 (match_operand:SI 2 "general_operand" "")
5881 (label_ref (match_operand 3 "" ""))
5882 (label_ref (match_operand 4 "" ""))]
5883 ""
5884 "
5885 {
5886 rtx index = gen_reg_rtx (SImode);
5887 rtx base = gen_reg_rtx (Pmode);
5888 rtx target = gen_reg_rtx (Pmode);
5889
5890 emit_move_insn (index, operands[0]);
5891 emit_insn (gen_subsi3 (index, index, operands[1]));
5892 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
5893 operands[4]);
5894
5895 if (Pmode != SImode)
5896 index = convert_to_mode (Pmode, index, 1);
5897 if (GET_CODE (index) != REG)
5898 index = copy_to_mode_reg (Pmode, index);
5899
5900 if (TARGET_64BIT)
5901 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
5902 else
5903 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
5904
5905 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
5906
5907 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
5908 emit_move_insn (target, index);
5909
5910 if (flag_pic)
5911 target = gen_rtx_PLUS (Pmode, base, target);
5912 emit_jump_insn (gen_casesi_jump (target, operands[3]));
5913
5914 DONE;
5915 }")
5916
5917
5918 ;;
5919 ;;- Jump to subroutine.
5920 ;;
5921 ;;
5922
5923 ;
5924 ; untyped call instruction pattern(s).
5925 ;
5926
5927 ;; Call subroutine returning any type.
5928 (define_expand "untyped_call"
5929 [(parallel [(call (match_operand 0 "" "")
5930 (const_int 0))
5931 (match_operand 1 "" "")
5932 (match_operand 2 "" "")])]
5933 ""
5934 "
5935 {
5936 int i;
5937
5938 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
5939
5940 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5941 {
5942 rtx set = XVECEXP (operands[2], 0, i);
5943 emit_move_insn (SET_DEST (set), SET_SRC (set));
5944 }
5945
5946 /* The optimizer does not know that the call sets the function value
5947 registers we stored in the result block. We avoid problems by
5948 claiming that all hard registers are used and clobbered at this
5949 point. */
5950 emit_insn (gen_blockage ());
5951
5952 DONE;
5953 }")
5954
5955 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5956 ;; all of memory. This blocks insns from being moved across this point.
5957
5958 (define_insn "blockage"
5959 [(unspec_volatile [(const_int 0)] 0)]
5960 ""
5961 ""
5962 [(set_attr "type" "none")])
5963
5964
5965
5966 ;
5967 ; call instruction pattern(s).
5968 ;
5969
5970 (define_expand "call"
5971 [(parallel [(call (match_operand 0 "" "")
5972 (match_operand 1 "" ""))
5973 (clobber (match_operand 2 "" ""))])]
5974 ""
5975 "
5976 {
5977 /* Abuse operand 2 to hold the return register. */
5978 operands[2] = gen_rtx_REG (Pmode, RETURN_REGNUM);
5979
5980 /* In 31-bit, we must load the GOT register even if the
5981 compiler doesn't know about it, because the PLT glue
5982 code uses it. In 64-bit, this is not necessary. */
5983 if (flag_pic && !TARGET_64BIT)
5984 current_function_uses_pic_offset_table = 1;
5985
5986 /* Direct function calls need special treatment. */
5987 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5988 {
5989 rtx sym = XEXP (operands[0], 0);
5990
5991 /* When calling a global routine in PIC mode, we must
5992 replace the symbol itself with the PLT stub. */
5993 if (flag_pic && !SYMBOL_REF_FLAG(sym))
5994 {
5995 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5996 sym = gen_rtx_CONST (Pmode, sym);
5997 }
5998
5999 /* Unless we can use the bras(l) insn, force the
6000 routine address into a register. */
6001 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6002 {
6003 rtx target = gen_reg_rtx (Pmode);
6004 emit_move_insn (target, sym);
6005 sym = target;
6006 }
6007
6008 operands[0] = gen_rtx_MEM (QImode, sym);
6009 }
6010 }")
6011
6012 (define_insn "brasl"
6013 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6014 (match_operand:SI 1 "const_int_operand" "n"))
6015 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6016 "TARGET_64BIT"
6017 "brasl\\t%2,%0"
6018 [(set_attr "op_type" "RIL")
6019 (set_attr "type" "jsr")])
6020
6021 (define_insn "bras"
6022 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6023 (match_operand:SI 1 "const_int_operand" "n"))
6024 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6025 "TARGET_SMALL_EXEC"
6026 "bras\\t%2,%0"
6027 [(set_attr "op_type" "RI")
6028 (set_attr "type" "jsr")])
6029
6030 (define_insn "basr_64"
6031 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6032 (match_operand:SI 1 "const_int_operand" "n"))
6033 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6034 "TARGET_64BIT"
6035 "basr\\t%2,%0"
6036 [(set_attr "op_type" "RR")
6037 (set_attr "type" "jsr")
6038 (set_attr "atype" "mem")])
6039
6040 (define_insn "basr_31"
6041 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6042 (match_operand:SI 1 "const_int_operand" "n"))
6043 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6044 "!TARGET_64BIT"
6045 "basr\\t%2,%0"
6046 [(set_attr "op_type" "RR")
6047 (set_attr "type" "jsr")
6048 (set_attr "atype" "mem")])
6049
6050 (define_insn "bas_64"
6051 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6052 (match_operand:SI 1 "const_int_operand" "n"))
6053 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6054 "TARGET_64BIT"
6055 "bas\\t%2,%a0"
6056 [(set_attr "op_type" "RX")
6057 (set_attr "type" "jsr")
6058 (set_attr "atype" "mem")])
6059
6060 (define_insn "bas_31"
6061 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6062 (match_operand:SI 1 "const_int_operand" "n"))
6063 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6064 "!TARGET_64BIT"
6065 "bas\\t%2,%a0"
6066 [(set_attr "op_type" "RX")
6067 (set_attr "type" "jsr")
6068 (set_attr "atype" "mem")])
6069
6070
6071 ;
6072 ; call_value instruction pattern(s).
6073 ;
6074
6075 (define_expand "call_value"
6076 [(parallel [(set (match_operand 0 "" "")
6077 (call (match_operand 1 "" "")
6078 (match_operand 2 "" "")))
6079 (clobber (match_operand 3 "" ""))])]
6080 ""
6081 "
6082 {
6083 /* Abuse operand 3 to hold the return register. */
6084 operands[3] = gen_rtx_REG (Pmode, RETURN_REGNUM);
6085
6086 /* In 31-bit, we must load the GOT register even if the
6087 compiler doesn't know about it, because the PLT glue
6088 code uses it. In 64-bit, this is not necessary. */
6089 if (flag_pic && !TARGET_64BIT)
6090 current_function_uses_pic_offset_table = 1;
6091
6092 /* Direct function calls need special treatment. */
6093 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6094 {
6095 rtx sym = XEXP (operands[1], 0);
6096
6097 /* When calling a global routine in PIC mode, we must
6098 replace the symbol itself with the PLT stub. */
6099 if (flag_pic && !SYMBOL_REF_FLAG(sym))
6100 {
6101 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6102 sym = gen_rtx_CONST (Pmode, sym);
6103 }
6104
6105 /* Unless we can use the bras(l) insn, force the
6106 routine address into a register. */
6107 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6108 {
6109 rtx target = gen_reg_rtx (Pmode);
6110 emit_move_insn (target, sym);
6111 sym = target;
6112 }
6113
6114 operands[1] = gen_rtx_MEM (QImode, sym);
6115 }
6116 }")
6117
6118 (define_insn "brasl_r"
6119 [(set (match_operand 0 "register_operand" "=df")
6120 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6121 (match_operand:SI 2 "const_int_operand" "n")))
6122 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6123 "TARGET_64BIT"
6124 "brasl\\t%3,%1"
6125 [(set_attr "op_type" "RIL")
6126 (set_attr "type" "jsr")])
6127
6128 (define_insn "bras_r"
6129 [(set (match_operand 0 "register_operand" "=df")
6130 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6131 (match_operand:SI 2 "const_int_operand" "n")))
6132 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6133 "TARGET_SMALL_EXEC"
6134 "bras\\t%3,%1"
6135 [(set_attr "op_type" "RI")
6136 (set_attr "type" "jsr")])
6137
6138 (define_insn "basr_r_64"
6139 [(set (match_operand 0 "register_operand" "=df")
6140 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6141 (match_operand:SI 2 "const_int_operand" "n")))
6142 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6143 "TARGET_64BIT"
6144 "basr\\t%3,%1"
6145 [(set_attr "op_type" "RR")
6146 (set_attr "type" "jsr")])
6147
6148 (define_insn "basr_r_31"
6149 [(set (match_operand 0 "register_operand" "=df")
6150 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6151 (match_operand:SI 2 "const_int_operand" "n")))
6152 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6153 "!TARGET_64BIT"
6154 "basr\\t%3,%1"
6155 [(set_attr "op_type" "RR")
6156 (set_attr "type" "jsr")
6157 (set_attr "atype" "mem")])
6158
6159 (define_insn "bas_r_64"
6160 [(set (match_operand 0 "register_operand" "=df")
6161 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6162 (match_operand:SI 2 "const_int_operand" "n")))
6163 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6164 "TARGET_64BIT"
6165 "bas\\t%3,%a1"
6166 [(set_attr "op_type" "RX")
6167 (set_attr "type" "jsr")
6168 (set_attr "atype" "mem")])
6169
6170 (define_insn "bas_r_31"
6171 [(set (match_operand 0 "register_operand" "=df")
6172 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6173 (match_operand:SI 2 "const_int_operand" "n")))
6174 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6175 "!TARGET_64BIT"
6176 "bas\\t%3,%a1"
6177 [(set_attr "op_type" "RX")
6178 (set_attr "type" "jsr")
6179 (set_attr "atype" "mem")])
6180
6181
6182 ;;
6183 ;;- Miscellaneous instructions.
6184 ;;
6185
6186 ;
6187 ; allocate stack instruction pattern(s).
6188 ;
6189
6190 (define_expand "allocate_stack"
6191 [(set (reg 15)
6192 (plus (reg 15) (match_operand 1 "general_operand" "")))
6193 (set (match_operand 0 "general_operand" "")
6194 (reg 15))]
6195 ""
6196 "
6197 {
6198 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6199 rtx chain = gen_rtx (MEM, Pmode, stack);
6200 rtx temp = gen_reg_rtx (Pmode);
6201
6202 emit_move_insn (temp, chain);
6203
6204 if (TARGET_64BIT)
6205 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6206 else
6207 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6208
6209 emit_move_insn (chain, temp);
6210
6211 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6212 DONE;
6213 }")
6214
6215
6216 ;
6217 ; setjmp/longjmp instruction pattern(s).
6218 ;
6219
6220 (define_expand "builtin_setjmp_setup"
6221 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6222 ""
6223 "
6224 {
6225 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6226 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6227
6228 emit_move_insn (base, basereg);
6229 DONE;
6230 }")
6231
6232 (define_expand "builtin_setjmp_receiver"
6233 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6234 "flag_pic"
6235 "
6236 {
6237 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6238 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6239 SYMBOL_REF_FLAG (got) = 1;
6240
6241 emit_move_insn (gotreg, got);
6242 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6243 DONE;
6244 }")
6245
6246 (define_expand "builtin_longjmp"
6247 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6248 ""
6249 "
6250 {
6251 /* The elements of the buffer are, in order: */
6252 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6253 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6254 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6255 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6256 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6257 rtx jmp = gen_rtx_REG (Pmode, 14);
6258
6259 emit_move_insn (jmp, lab);
6260 emit_move_insn (basereg, base);
6261 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6262 emit_move_insn (hard_frame_pointer_rtx, fp);
6263
6264 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6265 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6266 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6267 emit_indirect_jump (jmp);
6268 DONE;
6269 }")
6270
6271
6272 ;; These patterns say how to save and restore the stack pointer. We need not
6273 ;; save the stack pointer at function level since we are careful to
6274 ;; preserve the backchain. At block level, we have to restore the backchain
6275 ;; when we restore the stack pointer.
6276 ;;
6277 ;; For nonlocal gotos, we must save both the stack pointer and its
6278 ;; backchain and restore both. Note that in the nonlocal case, the
6279 ;; save area is a memory location.
6280
6281 (define_expand "save_stack_function"
6282 [(match_operand 0 "general_operand" "")
6283 (match_operand 1 "general_operand" "")]
6284 ""
6285 "DONE;")
6286
6287 (define_expand "restore_stack_function"
6288 [(match_operand 0 "general_operand" "")
6289 (match_operand 1 "general_operand" "")]
6290 ""
6291 "DONE;")
6292
6293 (define_expand "restore_stack_block"
6294 [(use (match_operand 0 "register_operand" ""))
6295 (set (match_dup 2) (match_dup 3))
6296 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6297 (set (match_dup 3) (match_dup 2))]
6298 ""
6299 "
6300 {
6301 operands[2] = gen_reg_rtx (Pmode);
6302 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6303 }")
6304
6305 (define_expand "save_stack_nonlocal"
6306 [(match_operand 0 "memory_operand" "")
6307 (match_operand 1 "register_operand" "")]
6308 ""
6309 "
6310 {
6311 rtx temp = gen_reg_rtx (Pmode);
6312
6313 /* Copy the backchain to the first word, sp to the second. */
6314 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6315 emit_move_insn (operand_subword (operands[0], 0, 0,
6316 TARGET_64BIT ? TImode : DImode),
6317 temp);
6318 emit_move_insn (operand_subword (operands[0], 1, 0,
6319 TARGET_64BIT ? TImode : DImode),
6320 operands[1]);
6321 DONE;
6322 }")
6323
6324 (define_expand "restore_stack_nonlocal"
6325 [(match_operand 0 "register_operand" "")
6326 (match_operand 1 "memory_operand" "")]
6327 ""
6328 "
6329 {
6330 rtx temp = gen_reg_rtx (Pmode);
6331
6332 /* Restore the backchain from the first word, sp from the second. */
6333 emit_move_insn (temp,
6334 operand_subword (operands[1], 0, 0,
6335 TARGET_64BIT ? TImode : DImode));
6336 emit_move_insn (operands[0],
6337 operand_subword (operands[1], 1, 0,
6338 TARGET_64BIT ? TImode : DImode));
6339 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6340 DONE;
6341 }")
6342
6343
6344 ;
6345 ; nop instruction pattern(s).
6346 ;
6347
6348 (define_insn "nop"
6349 [(const_int 0)]
6350 ""
6351 "lr\\t0,0"
6352 [(set_attr "op_type" "RR")])
6353
6354
6355 ;
6356 ; Special literal pool access instruction pattern(s).
6357 ;
6358
6359 (define_insn "reload_base"
6360 [(parallel [(set (reg 13) (pc))
6361 (use (label_ref (match_operand 0 "" "")))])]
6362 ""
6363 "*
6364 {
6365 if (TARGET_64BIT)
6366 return \"larl\\t13,%y0\";
6367 else
6368 return \"basr\\t13,0\;ahi\\t13,%Y0\";
6369 }"
6370 [(set_attr "op_type" "NN")
6371 (set_attr "type" "la")
6372 (set_attr "length" "8")])
6373
6374 (define_insn "ltorg"
6375 [(parallel [(set (reg 13) (pc))
6376 (use (match_operand:SI 0 "const_int_operand" ""))])]
6377 ""
6378 "*
6379 {
6380 s390_dump_literal_pool (insn, operands[0]);
6381 return \"0:\";
6382 }"
6383 [(set_attr "op_type" "NN")
6384 (set_attr "type" "other")
6385 (set_attr "length" "4096")])
6386
6387 ;;
6388 ;; Insns related to generating the function prologue and epilogue.
6389 ;;
6390
6391
6392 (define_expand "prologue"
6393 [(use (const_int 0))]
6394 ""
6395 "
6396 {
6397 s390_emit_prologue ();
6398 DONE;
6399 }")
6400
6401 (define_expand "epilogue"
6402 [(use (const_int 1))]
6403 ""
6404 "
6405 {
6406 s390_emit_epilogue ();
6407 DONE;
6408 }")
6409
6410
6411 (define_insn "*return_si"
6412 [(return)
6413 (use (match_operand:SI 0 "register_operand" "a"))]
6414 "!TARGET_64BIT"
6415 "br\\t%0"
6416 [(set_attr "op_type" "RR")
6417 (set_attr "type" "jsr")
6418 (set_attr "atype" "mem")])
6419
6420 (define_insn "*return_di"
6421 [(return)
6422 (use (match_operand:DI 0 "register_operand" "a"))]
6423 "TARGET_64BIT"
6424 "br\\t%0"
6425 [(set_attr "op_type" "RR")
6426 (set_attr "type" "jsr")
6427 (set_attr "atype" "mem")])
6428
6429
6430 (define_insn "lit"
6431 [(set (reg 13) (pc))
6432 (unspec_volatile [(const_int 0)] 200)]
6433 ""
6434 "*
6435 {
6436 s390_output_constant_pool (asm_out_file);
6437 return \"\";
6438 }"
6439 [(set_attr "op_type" "NN")
6440 (set_attr "type" "integer")])
6441
6442
6443 ;;
6444 ;; Peephole optimization patterns.
6445 ;;
6446
6447 (define_peephole
6448 [(set (match_operand:SI 0 "memory_operand" "m")
6449 (match_operand:SI 1 "register_operand" "d"))
6450 (set (match_dup 1)
6451 (match_dup 0))]
6452 ""
6453 "st\\t%1,%0")
6454
6455 (define_peephole
6456 [(set (match_operand:SI 0 "memory_operand" "m")
6457 (match_operand:SI 1 "register_operand" "d"))
6458 (set (match_dup 0)
6459 (match_dup 1))]
6460 ""
6461 "st\\t%1,%0")
6462
6463 (define_peephole
6464 [(set (match_operand:SI 0 "register_operand" "")
6465 (match_operand:SI 1 "register_operand" ""))
6466 (parallel
6467 [(set (match_dup 0)
6468 (plus:SI (match_dup 0)
6469 (match_operand:SI 2 "immediate_operand" "")))
6470 (clobber (reg:CC 33))])]
6471 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6472 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6473 REGNO (operands[0]) == BASE_REGISTER ||
6474 REGNO (operands[1]) == BASE_REGISTER) &&
6475 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6476 "la\\t%0,%c2(%1)")
6477
6478 ;
6479 ; peepholes for fast char instructions
6480 ;
6481
6482 ;(define_peephole
6483 ; [(set (match_operand:QI 0 "register_operand" "d")
6484 ; (match_operand:QI 1 "s_operand" "Q"))
6485 ; (set (match_operand:SI 2 "register_operand" "0")
6486 ; (zero_extend:SI (match_dup 0)))]
6487 ; "REGNO(operands[0]) == REGNO(operands[2])"
6488 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6489
6490 ;(define_peephole
6491 ; [(set (match_operand:QI 0 "register_operand" "d")
6492 ; (match_operand:QI 1 "s_operand" "Q"))
6493 ; (set (match_operand:SI 2 "register_operand" "0")
6494 ; (sign_extend:SI (match_dup 0)))]
6495 ; "REGNO(operands[0]) == REGNO(operands[2])"
6496 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6497
6498 (define_peephole
6499 [(set (match_operand:QI 0 "register_operand" "d")
6500 (match_operand:QI 1 "immediate_operand" "J"))
6501 (set (match_operand:SI 2 "register_operand" "0" )
6502 (sign_extend:SI (match_dup 0) ) )]
6503 "REGNO(operands[0]) == REGNO(operands[2])"
6504 "lhi\\t%0,%h1")
6505
6506 ;
6507 ; peepholes for fast short instructions
6508 ;
6509
6510 ;(define_peephole
6511 ; [(set (match_operand:HI 0 "register_operand" "d")
6512 ; (match_operand:HI 1 "s_operand" "Q"))
6513 ; (set (match_operand:SI 2 "register_operand" "0" )
6514 ; (zero_extend:SI (match_dup 0)))]
6515 ; "REGNO(operands[0]) == REGNO(operands[2])"
6516 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6517
6518 (define_peephole
6519 [(set (match_operand:HI 0 "register_operand" "d")
6520 (match_operand:HI 1 "memory_operand" "m"))
6521 (set (match_operand:SI 2 "register_operand" "0" )
6522 (sign_extend:SI (match_dup 0)))]
6523 "REGNO(operands[0]) == REGNO(operands[2])"
6524 "lh\\t%0,%1")
6525
6526 (define_peephole
6527 [(set (match_operand:HI 0 "register_operand" "d")
6528 (match_operand:HI 1 "immediate_operand" "K"))
6529 (set (match_operand:SI 2 "register_operand" "0" )
6530 (sign_extend:SI (match_dup 0) ) )]
6531 "REGNO(operands[0]) == REGNO(operands[2])"
6532 "lhi\\t%0,%h1")
6533
6534 ;
6535 ; peepholes for divide instructions
6536 ;
6537
6538 (define_peephole
6539 [(set (match_operand:DI 0 "register_operand" "d")
6540 (match_operand:DI 1 "memory_operand" "m"))
6541 (set (match_dup 0)
6542 (lshiftrt:DI (match_dup 0)
6543 (match_operand:SI 2 "immediate_operand" "J")))
6544 (set (match_dup 0)
6545 (div:SI (match_dup 0)
6546 (match_operand:SI 3 "nonimmediate_operand" "g")))
6547 (set (match_dup 1)
6548 (match_dup 0))]
6549 ""
6550 "*
6551 {
6552 output_asm_insn (\"l\\t%0,%1\", operands);
6553 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6554
6555 if (REG_P (operands[3]))
6556 output_asm_insn (\"dr\\t%0,%3\", operands);
6557 else
6558 output_asm_insn (\"d\\t%0,%3\", operands);
6559
6560 return \"st\\t%N0,%N1\";
6561 }")
6562
6563 (define_peephole
6564 [(set (match_operand:DI 0 "register_operand" "d")
6565 (match_operand:DI 1 "memory_operand" "m"))
6566 (set (match_dup 0)
6567 (lshiftrt:DI (match_dup 0)
6568 (match_operand:SI 2 "immediate_operand" "J")))
6569 (set (match_dup 0)
6570 (mod:SI (match_dup 0)
6571 (match_operand:SI 3 "nonimmediate_operand" "g")))
6572 (set (match_dup 1)
6573 (match_dup 0))]
6574 ""
6575 "*
6576 {
6577 output_asm_insn (\"l\\t%0,%1\", operands);
6578 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6579
6580 if (REG_P (operands[3]))
6581 output_asm_insn (\"dr\\t%0,%3\", operands);
6582 else
6583 output_asm_insn (\"d\\t%0,%3\", operands);
6584
6585 return \"st\\t%0,%1\";
6586 }")
6587