1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2016 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; The right hand side of an setmem
76 ; GOT/PLT and lt-relative accesses
97 ; TLS relocation specifiers
113 ; Stack Smashing Protector
117 ; Split stack support
120 ; Test Data Class (TDC)
132 UNSPEC_FPINT_NEARBYINT
141 UNSPEC_VEC_SMULT_EVEN
142 UNSPEC_VEC_UMULT_EVEN
156 UNSPEC_VEC_INSERT_AND_ZERO
157 UNSPEC_VEC_LOAD_BNDRY
162 UNSPEC_VEC_PACK_SATURATE
163 UNSPEC_VEC_PACK_SATURATE_CC
164 UNSPEC_VEC_PACK_SATURATE_GENCC
165 UNSPEC_VEC_PACK_UNSIGNED_SATURATE
166 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
167 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
179 UNSPEC_VEC_ADDEC_U128
184 UNSPEC_VEC_GFMSUM_128
185 UNSPEC_VEC_GFMSUM_ACCUM
186 UNSPEC_VEC_GFMSUM_ACCUM_128
205 UNSPEC_VEC_SUBEC_U128
239 ;; UNSPEC_VOLATILE usage
242 (define_c_enum "unspecv" [
264 ; Hotpatching (unremovable NOPs)
269 ; Transactional Execution support
279 ; Set and get floating point control register
283 ; Split stack support
284 UNSPECV_SPLIT_STACK_CALL
285 UNSPECV_SPLIT_STACK_DATA
292 ; Registers with special meaning
296 ; Sibling call register.
298 ; Literal pool base register.
300 ; Return address register.
302 ; Condition code register.
304 ; Thread local storage pointer register.
308 ; Hardware register names
312 ; General purpose registers
317 ; Floating point registers.
342 ;; PFPO GPR0 argument format
347 ; PFPO operation type
348 (PFPO_CONVERT 0x1000000)
350 (PFPO_OP_TYPE_SF 0x5)
351 (PFPO_OP_TYPE_DF 0x6)
352 (PFPO_OP_TYPE_TF 0x7)
353 (PFPO_OP_TYPE_SD 0x8)
354 (PFPO_OP_TYPE_DD 0x9)
355 (PFPO_OP_TYPE_TD 0xa)
356 ; Bitposition of operand types
357 (PFPO_OP0_TYPE_SHIFT 16)
358 (PFPO_OP1_TYPE_SHIFT 8)
361 ; Immediate operands for tbegin and tbeginc
362 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
363 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
365 ;; Instruction operand type as used in the Principles of Operation.
366 ;; Used to determine defaults for length and other attribute values.
368 (define_attr "op_type"
369 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
372 ;; Instruction type attribute used for scheduling.
374 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
375 cs,vs,store,sem,idiv,
376 imulhi,imulsi,imuldi,
377 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
378 floadtf,floaddf,floadsf,fstoredf,fstoresf,
379 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
380 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
382 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
383 itoftf, itofdf, itofsf, itofdd, itoftd,
384 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
385 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
387 (cond [(eq_attr "op_type" "NN") (const_string "other")
388 (eq_attr "op_type" "SS") (const_string "cs")]
389 (const_string "integer")))
391 ;; Another attribute used for scheduling purposes:
392 ;; agen: Instruction uses the address generation unit
393 ;; reg: Instruction does not use the agen unit
395 (define_attr "atype" "agen,reg"
396 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
398 (const_string "agen")))
400 ;; Properties concerning Z10 execution grouping and value forwarding.
401 ;; z10_super: instruction is superscalar.
402 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
403 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
404 ;; target register. It can forward this value to a second instruction that reads
405 ;; the same register if that second instruction is issued in the same group.
406 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
407 ;; instruction in the S pipe writes to the register, then the T instruction
408 ;; can immediately read the new value.
409 ;; z10_fr: union of Z10_fwd and z10_rec.
410 ;; z10_c: second operand of instruction is a register and read with complemented bits.
412 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
415 (define_attr "z10prop" "none,
416 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
417 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
419 z10_fr, z10_fr_A3, z10_fr_E1,
421 (const_string "none"))
423 ;; Properties concerning Z196 decoding
424 ;; z196_alone: must group alone
425 ;; z196_end: ends a group
426 ;; z196_cracked: instruction is cracked or expanded
427 (define_attr "z196prop" "none,
428 z196_alone, z196_ends,
430 (const_string "none"))
432 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
436 (define_attr "length" ""
437 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
438 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)]
442 ;; Processor type. This attribute must exactly match the processor_type
443 ;; enumeration in s390.h. The current machine description does not
444 ;; distinguish between g5 and g6, but there are differences between the two
445 ;; CPUs could in theory be modeled.
447 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
448 (const (symbol_ref "s390_tune_attr")))
450 (define_attr "cpu_facility"
451 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
452 (const_string "standard"))
454 (define_attr "enabled" ""
455 (cond [(eq_attr "cpu_facility" "standard")
458 (and (eq_attr "cpu_facility" "ieee")
459 (match_test "TARGET_CPU_IEEE_FLOAT"))
462 (and (eq_attr "cpu_facility" "zarch")
463 (match_test "TARGET_ZARCH"))
466 (and (eq_attr "cpu_facility" "longdisp")
467 (match_test "TARGET_LONG_DISPLACEMENT"))
470 (and (eq_attr "cpu_facility" "extimm")
471 (match_test "TARGET_EXTIMM"))
474 (and (eq_attr "cpu_facility" "dfp")
475 (match_test "TARGET_DFP"))
478 (and (eq_attr "cpu_facility" "cpu_zarch")
479 (match_test "TARGET_CPU_ZARCH"))
482 (and (eq_attr "cpu_facility" "z10")
483 (match_test "TARGET_Z10"))
486 (and (eq_attr "cpu_facility" "z196")
487 (match_test "TARGET_Z196"))
490 (and (eq_attr "cpu_facility" "zEC12")
491 (match_test "TARGET_ZEC12"))
494 (and (eq_attr "cpu_facility" "vec")
495 (match_test "TARGET_VX"))
499 ;; Pipeline description for z900. For lack of anything better,
500 ;; this description is also used for the g5 and g6.
503 ;; Pipeline description for z990, z9-109 and z9-ec.
506 ;; Pipeline description for z10
509 ;; Pipeline description for z196
512 ;; Pipeline description for zEC12
515 ;; Pipeline description for z13
519 (include "predicates.md")
521 ;; Constraint definitions
522 (include "constraints.md")
529 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
531 ;; These mode iterators allow floating point patterns to be generated from the
533 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
534 (SD "TARGET_HARD_DFP")])
535 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
536 (define_mode_iterator BFP [TF DF SF])
537 (define_mode_iterator DFP [TD DD])
538 (define_mode_iterator DFP_ALL [TD DD SD])
539 (define_mode_iterator DSF [DF SF])
540 (define_mode_iterator SD_SF [SF SD])
541 (define_mode_iterator DD_DF [DF DD])
542 (define_mode_iterator TD_TF [TF TD])
544 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
545 ;; from the same template.
546 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
547 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
548 (define_mode_iterator DSI [DI SI])
549 (define_mode_iterator TDI [TI DI])
551 ;; These mode iterators allow :P to be used for patterns that operate on
552 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
553 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
555 ;; These macros refer to the actual word_mode of the configuration.
556 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
557 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
558 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
560 ;; Used by the umul pattern to express modes having half the size.
561 (define_mode_attr DWH [(TI "DI") (DI "SI")])
562 (define_mode_attr dwh [(TI "di") (DI "si")])
564 ;; This mode iterator allows the QI and HI patterns to be defined from
565 ;; the same template.
566 (define_mode_iterator HQI [HI QI])
568 ;; This mode iterator allows the integer patterns to be defined from the
570 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
571 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
573 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
574 ;; the same template.
575 (define_code_iterator SHIFT [ashift lshiftrt])
577 ;; This iterator allows r[ox]sbg to be defined with the same template
578 (define_code_iterator IXOR [ior xor])
580 ;; This iterator is used to expand the patterns for the nearest
581 ;; integer functions.
582 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
583 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
584 UNSPEC_FPINT_NEARBYINT])
585 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
586 (UNSPEC_FPINT_BTRUNC "btrunc")
587 (UNSPEC_FPINT_ROUND "round")
588 (UNSPEC_FPINT_CEIL "ceil")
589 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
590 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
591 (UNSPEC_FPINT_BTRUNC "5")
592 (UNSPEC_FPINT_ROUND "1")
593 (UNSPEC_FPINT_CEIL "6")
594 (UNSPEC_FPINT_NEARBYINT "0")])
596 ;; This iterator and attribute allow to combine most atomic operations.
597 (define_code_iterator ATOMIC [and ior xor plus minus mult])
598 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
599 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
600 (plus "add") (minus "sub") (mult "nand")])
601 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
603 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
604 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
605 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
607 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
608 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
610 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
612 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
613 ;; Likewise for "<RXe>".
614 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
615 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
617 ;; The decimal floating point variants of add, sub, div and mul support 3
618 ;; fp register operands. The following attributes allow to merge the bfp and
619 ;; dfp variants in a single insn definition.
621 ;; These mode attributes are supposed to be used in the `enabled' insn
622 ;; attribute to disable certain alternatives for certain modes.
623 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
624 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
625 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
626 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
627 (TD "0") (DD "0") (DD "0")
628 (TI "0") (DI "*") (SI "0")])
630 ;; This attribute is used in the operand constraint list
631 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
632 ;; TFmode values are represented by a fp register pair. Since the
633 ;; sign bit instructions only handle single source and target fp registers
634 ;; these instructions can only be used for TFmode values if the source and
635 ;; target operand uses the same fp register.
636 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
638 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
639 ;; within instruction mnemonics.
640 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
642 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
643 ;; modes and to an empty string for bfp modes.
644 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
646 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
647 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
648 ;; version only operates on one register.
649 (define_mode_attr d0 [(DI "d") (SI "0")])
651 ;; In combination with d0 this allows to combine instructions of which the 31bit
652 ;; version only operates on one register. The DImode version needs an additional
653 ;; register for the assembler output.
654 (define_mode_attr 1 [(DI "%1,") (SI "")])
656 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
657 ;; 'ashift' and "srdl" in 'lshiftrt'.
658 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
660 ;; In SHIFT templates, this attribute holds the correct standard name for the
661 ;; pattern itself and the corresponding function calls.
662 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
664 ;; This attribute handles differences in the instruction 'type' and will result
665 ;; in "RRE" for DImode and "RR" for SImode.
666 (define_mode_attr E [(DI "E") (SI "")])
668 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
669 ;; to result in "RXY" for DImode and "RX" for SImode.
670 (define_mode_attr Y [(DI "Y") (SI "")])
672 ;; This attribute handles differences in the instruction 'type' and will result
673 ;; in "RSE" for TImode and "RS" for DImode.
674 (define_mode_attr TE [(TI "E") (DI "")])
676 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
677 ;; and "lcr" in SImode.
678 (define_mode_attr g [(DI "g") (SI "")])
680 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
681 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
682 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
683 ;; variant for long displacements.
684 (define_mode_attr y [(DI "g") (SI "y")])
686 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
687 ;; and "cds" in DImode.
688 (define_mode_attr tg [(TI "g") (DI "")])
690 ;; In TDI templates, a string like "c<d>sg".
691 (define_mode_attr td [(TI "d") (DI "")])
693 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
694 ;; and "cfdbr" in SImode.
695 (define_mode_attr gf [(DI "g") (SI "f")])
697 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
698 ;; and sllk for SI. This way it is possible to merge the new z196 SI
699 ;; 3 operands shift instructions into the existing patterns.
700 (define_mode_attr gk [(DI "g") (SI "k")])
702 ;; ICM mask required to load MODE value into the lowest subreg
703 ;; of a SImode register.
704 (define_mode_attr icm_lo [(HI "3") (QI "1")])
706 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
707 ;; HImode and "llgc" in QImode.
708 (define_mode_attr hc [(HI "h") (QI "c")])
710 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
712 (define_mode_attr DBL [(DI "TI") (SI "DI")])
714 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
715 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
716 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
718 ;; Maximum unsigned integer that fits in MODE.
719 (define_mode_attr max_uint [(HI "65535") (QI "255")])
721 ;; Start and end field computations for RISBG et al.
722 (define_mode_attr bfstart [(DI "s") (SI "t")])
723 (define_mode_attr bfend [(DI "e") (SI "f")])
725 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
726 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
728 ;; In place of GET_MODE_SIZE (<MODE>mode)
729 (define_mode_attr modesize [(DI "8") (SI "4")])
731 ;; Allow return and simple_return to be defined from a single template.
732 (define_code_iterator ANY_RETURN [return simple_return])
736 ; Condition code modes generated by vector fp comparisons. These will
737 ; be used also in single element mode.
738 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
739 ; Used with VFCMP to expand part of the mnemonic
740 ; For fp we have a mismatch: eq in the insn name - e in asm
741 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
742 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
744 ;; Subst pattern definitions
747 (include "vector.md")
750 ;;- Compare instructions.
753 ; Test-under-Mask instructions
755 (define_insn "*tmqi_mem"
756 [(set (reg CC_REGNUM)
757 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
758 (match_operand:QI 1 "immediate_operand" "n,n"))
759 (match_operand:QI 2 "immediate_operand" "n,n")))]
760 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
764 [(set_attr "op_type" "SI,SIY")
765 (set_attr "z10prop" "z10_super,z10_super")])
767 (define_insn "*tmdi_reg"
768 [(set (reg CC_REGNUM)
769 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
770 (match_operand:DI 1 "immediate_operand"
771 "N0HD0,N1HD0,N2HD0,N3HD0"))
772 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
774 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
775 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
781 [(set_attr "op_type" "RI")
782 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
784 (define_insn "*tmsi_reg"
785 [(set (reg CC_REGNUM)
786 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
787 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
788 (match_operand:SI 2 "immediate_operand" "n,n")))]
789 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
790 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
794 [(set_attr "op_type" "RI")
795 (set_attr "z10prop" "z10_super,z10_super")])
797 (define_insn "*tm<mode>_full"
798 [(set (reg CC_REGNUM)
799 (compare (match_operand:HQI 0 "register_operand" "d")
800 (match_operand:HQI 1 "immediate_operand" "n")))]
801 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
803 [(set_attr "op_type" "RI")
804 (set_attr "z10prop" "z10_super")])
808 ; Load-and-Test instructions
811 ; tst(di|si) instruction pattern(s).
813 (define_insn "*tstdi_sign"
814 [(set (reg CC_REGNUM)
818 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
819 (const_int 32)) (const_int 32))
820 (match_operand:DI 1 "const0_operand" "")))
821 (set (match_operand:DI 2 "register_operand" "=d,d")
822 (sign_extend:DI (match_dup 0)))]
823 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
826 [(set_attr "op_type" "RRE,RXY")
827 (set_attr "cpu_facility" "*,z10")
828 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
831 (define_insn "*tst<mode>_extimm"
832 [(set (reg CC_REGNUM)
833 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
834 (match_operand:GPR 1 "const0_operand" "")))
835 (set (match_operand:GPR 2 "register_operand" "=d,d")
837 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
841 [(set_attr "op_type" "RR<E>,RXY")
842 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
845 (define_insn "*tst<mode>_cconly_extimm"
846 [(set (reg CC_REGNUM)
847 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
848 (match_operand:GPR 1 "const0_operand" "")))
849 (clobber (match_scratch:GPR 2 "=X,d"))]
850 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
854 [(set_attr "op_type" "RR<E>,RXY")
855 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
857 (define_insn "*tstdi"
858 [(set (reg CC_REGNUM)
859 (compare (match_operand:DI 0 "register_operand" "d")
860 (match_operand:DI 1 "const0_operand" "")))
861 (set (match_operand:DI 2 "register_operand" "=d")
863 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
865 [(set_attr "op_type" "RRE")
866 (set_attr "z10prop" "z10_fr_E1")])
868 (define_insn "*tstsi"
869 [(set (reg CC_REGNUM)
870 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
871 (match_operand:SI 1 "const0_operand" "")))
872 (set (match_operand:SI 2 "register_operand" "=d,d,d")
874 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
879 [(set_attr "op_type" "RR,RS,RSY")
880 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
882 (define_insn "*tstsi_cconly"
883 [(set (reg CC_REGNUM)
884 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
885 (match_operand:SI 1 "const0_operand" "")))
886 (clobber (match_scratch:SI 2 "=X,d,d"))]
887 "s390_match_ccmode(insn, CCSmode)"
892 [(set_attr "op_type" "RR,RS,RSY")
893 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
895 (define_insn "*tstdi_cconly_31"
896 [(set (reg CC_REGNUM)
897 (compare (match_operand:DI 0 "register_operand" "d")
898 (match_operand:DI 1 "const0_operand" "")))]
899 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
901 [(set_attr "op_type" "RS")
902 (set_attr "atype" "reg")])
905 (define_insn "*tst<mode>_cconly2"
906 [(set (reg CC_REGNUM)
907 (compare (match_operand:GPR 0 "register_operand" "d")
908 (match_operand:GPR 1 "const0_operand" "")))]
909 "s390_match_ccmode(insn, CCSmode)"
911 [(set_attr "op_type" "RR<E>")
912 (set_attr "z10prop" "z10_fr_E1")])
914 ; tst(hi|qi) instruction pattern(s).
916 (define_insn "*tst<mode>CCT"
917 [(set (reg CC_REGNUM)
918 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
919 (match_operand:HQI 1 "const0_operand" "")))
920 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
922 "s390_match_ccmode(insn, CCTmode)"
925 icmy\t%2,<icm_lo>,%S0
927 [(set_attr "op_type" "RS,RSY,RI")
928 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
930 (define_insn "*tsthiCCT_cconly"
931 [(set (reg CC_REGNUM)
932 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
933 (match_operand:HI 1 "const0_operand" "")))
934 (clobber (match_scratch:HI 2 "=d,d,X"))]
935 "s390_match_ccmode(insn, CCTmode)"
940 [(set_attr "op_type" "RS,RSY,RI")
941 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
943 (define_insn "*tstqiCCT_cconly"
944 [(set (reg CC_REGNUM)
945 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
946 (match_operand:QI 1 "const0_operand" "")))]
947 "s390_match_ccmode(insn, CCTmode)"
952 [(set_attr "op_type" "SI,SIY,RI")
953 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
955 (define_insn "*tst<mode>"
956 [(set (reg CC_REGNUM)
957 (compare (match_operand:HQI 0 "s_operand" "Q,S")
958 (match_operand:HQI 1 "const0_operand" "")))
959 (set (match_operand:HQI 2 "register_operand" "=d,d")
961 "s390_match_ccmode(insn, CCSmode)"
964 icmy\t%2,<icm_lo>,%S0"
965 [(set_attr "op_type" "RS,RSY")
966 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
968 (define_insn "*tst<mode>_cconly"
969 [(set (reg CC_REGNUM)
970 (compare (match_operand:HQI 0 "s_operand" "Q,S")
971 (match_operand:HQI 1 "const0_operand" "")))
972 (clobber (match_scratch:HQI 2 "=d,d"))]
973 "s390_match_ccmode(insn, CCSmode)"
976 icmy\t%2,<icm_lo>,%S0"
977 [(set_attr "op_type" "RS,RSY")
978 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
981 ; Compare (equality) instructions
983 (define_insn "*cmpdi_cct"
984 [(set (reg CC_REGNUM)
985 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
986 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
987 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
994 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
995 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
997 (define_insn "*cmpsi_cct"
998 [(set (reg CC_REGNUM)
999 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1000 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1001 "s390_match_ccmode (insn, CCTmode)"
1009 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1010 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1012 ; Compare (signed) instructions
1014 (define_insn "*cmpdi_ccs_sign"
1015 [(set (reg CC_REGNUM)
1016 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1018 (match_operand:DI 0 "register_operand" "d, d,d")))]
1019 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1024 [(set_attr "op_type" "RRE,RXY,RIL")
1025 (set_attr "z10prop" "z10_c,*,*")
1026 (set_attr "type" "*,*,larl")])
1030 (define_insn "*cmpsi_ccs_sign"
1031 [(set (reg CC_REGNUM)
1032 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1033 (match_operand:SI 0 "register_operand" "d,d,d")))]
1034 "s390_match_ccmode(insn, CCSRmode)"
1039 [(set_attr "op_type" "RX,RXY,RIL")
1040 (set_attr "cpu_facility" "*,*,z10")
1041 (set_attr "type" "*,*,larl")
1042 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1044 (define_insn "*cmphi_ccs_z10"
1045 [(set (reg CC_REGNUM)
1046 (compare (match_operand:HI 0 "s_operand" "Q")
1047 (match_operand:HI 1 "immediate_operand" "K")))]
1048 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1050 [(set_attr "op_type" "SIL")
1051 (set_attr "z196prop" "z196_cracked")])
1053 (define_insn "*cmpdi_ccs_signhi_rl"
1054 [(set (reg CC_REGNUM)
1055 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
1056 (match_operand:GPR 0 "register_operand" "d,d")))]
1057 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1061 [(set_attr "op_type" "RXY,RIL")
1062 (set_attr "type" "*,larl")])
1064 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1065 (define_insn "*cmp<mode>_ccs"
1066 [(set (reg CC_REGNUM)
1067 (compare (match_operand:GPR 0 "nonimmediate_operand"
1069 (match_operand:GPR 1 "general_operand"
1070 "d,K,K,Os,R,T,b")))]
1071 "s390_match_ccmode(insn, CCSmode)"
1080 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1081 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
1082 (set_attr "type" "*,*,*,*,*,*,larl")
1083 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1086 ; Compare (unsigned) instructions
1088 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1089 [(set (reg CC_REGNUM)
1090 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1091 "larl_operand" "X")))
1092 (match_operand:SI 0 "register_operand" "d")))]
1093 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1095 [(set_attr "op_type" "RIL")
1096 (set_attr "type" "larl")
1097 (set_attr "z10prop" "z10_super")])
1100 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1101 [(set (reg CC_REGNUM)
1102 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1103 "larl_operand" "X")))
1104 (match_operand:GPR 0 "register_operand" "d")))]
1105 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1107 [(set_attr "op_type" "RIL")
1108 (set_attr "type" "larl")
1109 (set_attr "z10prop" "z10_super")])
1111 (define_insn "*cmpdi_ccu_zero"
1112 [(set (reg CC_REGNUM)
1113 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1115 (match_operand:DI 0 "register_operand" "d, d,d")))]
1116 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1121 [(set_attr "op_type" "RRE,RXY,RIL")
1122 (set_attr "cpu_facility" "*,*,z10")
1123 (set_attr "type" "*,*,larl")
1124 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1126 (define_insn "*cmpdi_ccu"
1127 [(set (reg CC_REGNUM)
1128 (compare (match_operand:DI 0 "nonimmediate_operand"
1129 "d, d,d,Q, d, Q,BQ")
1130 (match_operand:DI 1 "general_operand"
1131 "d,Op,b,D,RT,BQ,Q")))]
1132 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1141 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1142 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1143 (set_attr "type" "*,*,larl,*,*,*,*")
1144 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1146 (define_insn "*cmpsi_ccu"
1147 [(set (reg CC_REGNUM)
1148 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1149 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1150 "s390_match_ccmode (insn, CCUmode)"
1160 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1161 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1162 (set_attr "type" "*,*,larl,*,*,*,*,*")
1163 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1165 (define_insn "*cmphi_ccu"
1166 [(set (reg CC_REGNUM)
1167 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1168 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1169 "s390_match_ccmode (insn, CCUmode)
1170 && !register_operand (operands[1], HImode)"
1177 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1178 (set_attr "cpu_facility" "*,*,z10,*,*")
1179 (set_attr "z10prop" "*,*,z10_super,*,*")])
1181 (define_insn "*cmpqi_ccu"
1182 [(set (reg CC_REGNUM)
1183 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1184 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1185 "s390_match_ccmode (insn, CCUmode)
1186 && !register_operand (operands[1], QImode)"
1194 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1195 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1198 ; Block compare (CLC) instruction patterns.
1201 [(set (reg CC_REGNUM)
1202 (compare (match_operand:BLK 0 "memory_operand" "Q")
1203 (match_operand:BLK 1 "memory_operand" "Q")))
1204 (use (match_operand 2 "const_int_operand" "n"))]
1205 "s390_match_ccmode (insn, CCUmode)
1206 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1207 "clc\t%O0(%2,%R0),%S1"
1208 [(set_attr "op_type" "SS")])
1211 [(set (reg CC_REGNUM)
1212 (compare (match_operand 0 "memory_operand" "")
1213 (match_operand 1 "memory_operand" "")))]
1215 && s390_match_ccmode (insn, CCUmode)
1216 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1217 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1219 [(set (match_dup 0) (match_dup 1))
1220 (use (match_dup 2))])]
1222 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1223 operands[0] = adjust_address (operands[0], BLKmode, 0);
1224 operands[1] = adjust_address (operands[1], BLKmode, 0);
1226 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1227 operands[0], operands[1]);
1228 operands[0] = SET_DEST (PATTERN (curr_insn));
1232 ; (TF|DF|SF|TD|DD|SD) instructions
1234 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1235 (define_insn "*cmp<mode>_ccs_0"
1236 [(set (reg CC_REGNUM)
1237 (compare (match_operand:FP 0 "register_operand" "f")
1238 (match_operand:FP 1 "const0_operand" "")))]
1239 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1240 "lt<xde><bt>r\t%0,%0"
1241 [(set_attr "op_type" "RRE")
1242 (set_attr "type" "fsimp<mode>")])
1244 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1245 (define_insn "*cmp<mode>_ccs"
1246 [(set (reg CC_REGNUM)
1247 (compare (match_operand:FP 0 "register_operand" "f,f")
1248 (match_operand:FP 1 "general_operand" "f,R")))]
1249 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1253 [(set_attr "op_type" "RRE,RXE")
1254 (set_attr "type" "fsimp<mode>")
1255 (set_attr "enabled" "*,<DSF>")])
1257 ; wfcedbs, wfchdbs, wfchedbs
1258 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1259 [(set (reg:VFCMP CC_REGNUM)
1260 (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1261 (match_operand:DF 1 "register_operand" "v")))
1262 (clobber (match_scratch:V2DI 2 "=v"))]
1263 "TARGET_Z13 && TARGET_HARD_FLOAT"
1264 "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1265 [(set_attr "op_type" "VRR")])
1267 ; Compare and Branch instructions
1269 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1270 ; The following instructions do a complementary access of their second
1271 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1272 (define_insn "*cmp_and_br_signed_<mode>"
1274 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1275 [(match_operand:GPR 1 "register_operand" "d,d")
1276 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1277 (label_ref (match_operand 3 "" ""))
1279 (clobber (reg:CC CC_REGNUM))]
1280 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1282 if (get_attr_length (insn) == 6)
1283 return which_alternative ?
1284 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1286 return which_alternative ?
1287 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1289 [(set_attr "op_type" "RIE")
1290 (set_attr "type" "branch")
1291 (set_attr "z10prop" "z10_super_c,z10_super")
1292 (set (attr "length")
1293 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1294 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1295 ; 10 byte for cgr/jg
1297 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1298 ; The following instructions do a complementary access of their second
1299 ; operand (z10 only): clrj, clgrj, clr, clgr
1300 (define_insn "*cmp_and_br_unsigned_<mode>"
1302 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1303 [(match_operand:GPR 1 "register_operand" "d,d")
1304 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1305 (label_ref (match_operand 3 "" ""))
1307 (clobber (reg:CC CC_REGNUM))]
1308 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1310 if (get_attr_length (insn) == 6)
1311 return which_alternative ?
1312 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1314 return which_alternative ?
1315 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1317 [(set_attr "op_type" "RIE")
1318 (set_attr "type" "branch")
1319 (set_attr "z10prop" "z10_super_c,z10_super")
1320 (set (attr "length")
1321 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1322 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1323 ; 10 byte for clgr/jg
1325 ; And now the same two patterns as above but with a negated CC mask.
1327 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1328 ; The following instructions do a complementary access of their second
1329 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1330 (define_insn "*icmp_and_br_signed_<mode>"
1332 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1333 [(match_operand:GPR 1 "register_operand" "d,d")
1334 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1336 (label_ref (match_operand 3 "" ""))))
1337 (clobber (reg:CC CC_REGNUM))]
1338 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1340 if (get_attr_length (insn) == 6)
1341 return which_alternative ?
1342 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1344 return which_alternative ?
1345 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1347 [(set_attr "op_type" "RIE")
1348 (set_attr "type" "branch")
1349 (set_attr "z10prop" "z10_super_c,z10_super")
1350 (set (attr "length")
1351 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1352 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1353 ; 10 byte for cgr/jg
1355 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1356 ; The following instructions do a complementary access of their second
1357 ; operand (z10 only): clrj, clgrj, clr, clgr
1358 (define_insn "*icmp_and_br_unsigned_<mode>"
1360 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1361 [(match_operand:GPR 1 "register_operand" "d,d")
1362 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1364 (label_ref (match_operand 3 "" ""))))
1365 (clobber (reg:CC CC_REGNUM))]
1366 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1368 if (get_attr_length (insn) == 6)
1369 return which_alternative ?
1370 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1372 return which_alternative ?
1373 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1375 [(set_attr "op_type" "RIE")
1376 (set_attr "type" "branch")
1377 (set_attr "z10prop" "z10_super_c,z10_super")
1378 (set (attr "length")
1379 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1380 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1381 ; 10 byte for clgr/jg
1384 ;;- Move instructions.
1388 ; movti instruction pattern(s).
1391 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1392 ; for TImode (use double-int for the calculations)
1393 (define_insn "movti"
1394 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o")
1395 (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
1409 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1410 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1411 (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1414 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1415 (match_operand:TI 1 "general_operand" ""))]
1416 "TARGET_ZARCH && reload_completed
1417 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1418 [(set (match_dup 2) (match_dup 4))
1419 (set (match_dup 3) (match_dup 5))]
1421 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1422 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1423 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1424 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1428 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1429 (match_operand:TI 1 "general_operand" ""))]
1430 "TARGET_ZARCH && reload_completed
1431 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1432 [(set (match_dup 2) (match_dup 4))
1433 (set (match_dup 3) (match_dup 5))]
1435 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1436 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1437 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1438 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1441 ; Use part of the TImode target reg to perform the address
1442 ; calculation. If the TImode value is supposed to be copied into a VR
1443 ; this splitter is not necessary.
1445 [(set (match_operand:TI 0 "register_operand" "")
1446 (match_operand:TI 1 "memory_operand" ""))]
1447 "TARGET_ZARCH && reload_completed
1448 && !VECTOR_REG_P (operands[0])
1449 && !s_operand (operands[1], VOIDmode)"
1450 [(set (match_dup 0) (match_dup 1))]
1452 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1453 addr = gen_lowpart (Pmode, addr);
1454 s390_load_address (addr, XEXP (operands[1], 0));
1455 operands[1] = replace_equiv_address (operands[1], addr);
1459 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1460 ; For the higher order bits we do simply a DImode move while the
1461 ; second part is done via vec extract. Both will end up as vlgvg.
1463 [(set (match_operand:TI 0 "register_operand" "")
1464 (match_operand:TI 1 "register_operand" ""))]
1465 "TARGET_VX && reload_completed
1466 && GENERAL_REG_P (operands[0])
1467 && VECTOR_REG_P (operands[1])"
1468 [(set (match_dup 2) (match_dup 4))
1469 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1470 UNSPEC_VEC_EXTRACT))]
1472 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1473 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1474 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1475 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1479 ; Patterns used for secondary reloads
1482 ; z10 provides move instructions accepting larl memory operands.
1483 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1484 ; These patterns are also used for unaligned SI and DI accesses.
1486 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1487 [(parallel [(match_operand:ALL 0 "memory_operand" "")
1488 (match_operand:ALL 1 "register_operand" "=d")
1489 (match_operand:P 2 "register_operand" "=&a")])]
1492 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1496 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1497 [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1498 (match_operand:ALL 1 "memory_operand" "")
1499 (match_operand:P 2 "register_operand" "=a")])]
1502 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1506 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1507 [(parallel [(match_operand:P 0 "register_operand" "=d")
1508 (match_operand:P 1 "larl_operand" "")
1509 (match_operand:P 2 "register_operand" "=a")])]
1512 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1516 ; Handles loading a PLUS (load address) expression
1518 (define_expand "reload<mode>_plus"
1519 [(parallel [(match_operand:P 0 "register_operand" "=a")
1520 (match_operand:P 1 "s390_plus_operand" "")
1521 (match_operand:P 2 "register_operand" "=&a")])]
1524 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1528 ; Not all the indirect memory access instructions support the full
1529 ; format (long disp + index + base). So whenever a move from/to such
1530 ; an address is required and the instruction cannot deal with it we do
1531 ; a load address into a scratch register first and use this as the new
1533 ; This in particular is used for:
1534 ; - non-offsetable memory accesses for multiword moves
1535 ; - full vector reg moves with long displacements
1537 (define_expand "reload<mode>_la_in"
1538 [(parallel [(match_operand 0 "register_operand" "")
1539 (match_operand 1 "" "")
1540 (match_operand:P 2 "register_operand" "=&a")])]
1543 gcc_assert (MEM_P (operands[1]));
1544 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1545 operands[1] = replace_equiv_address (operands[1], operands[2]);
1546 emit_move_insn (operands[0], operands[1]);
1550 (define_expand "reload<mode>_la_out"
1551 [(parallel [(match_operand 0 "" "")
1552 (match_operand 1 "register_operand" "")
1553 (match_operand:P 2 "register_operand" "=&a")])]
1556 gcc_assert (MEM_P (operands[0]));
1557 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1558 operands[0] = replace_equiv_address (operands[0], operands[2]);
1559 emit_move_insn (operands[0], operands[1]);
1563 (define_expand "reload<mode>_PIC_addr"
1564 [(parallel [(match_operand 0 "register_operand" "=d")
1565 (match_operand 1 "larl_operand" "")
1566 (match_operand:P 2 "register_operand" "=a")])]
1569 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1570 emit_move_insn (operands[0], new_rtx);
1574 ; movdi instruction pattern(s).
1577 (define_expand "movdi"
1578 [(set (match_operand:DI 0 "general_operand" "")
1579 (match_operand:DI 1 "general_operand" ""))]
1582 /* Handle symbolic constants. */
1584 && (SYMBOLIC_CONST (operands[1])
1585 || (GET_CODE (operands[1]) == PLUS
1586 && XEXP (operands[1], 0) == pic_offset_table_rtx
1587 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1588 emit_symbolic_move (operands);
1591 (define_insn "*movdi_larl"
1592 [(set (match_operand:DI 0 "register_operand" "=d")
1593 (match_operand:DI 1 "larl_operand" "X"))]
1595 && !FP_REG_P (operands[0])"
1597 [(set_attr "op_type" "RIL")
1598 (set_attr "type" "larl")
1599 (set_attr "z10prop" "z10_super_A1")])
1601 (define_insn "*movdi_64"
1602 [(set (match_operand:DI 0 "nonimmediate_operand"
1603 "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
1604 (match_operand:DI 1 "general_operand"
1605 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
1640 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1641 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1642 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1643 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1645 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1646 z10,*,*,*,*,*,longdisp,*,longdisp,
1647 z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1648 (set_attr "z10prop" "z10_fwd_A1,
1677 [(set (match_operand:DI 0 "register_operand" "")
1678 (match_operand:DI 1 "register_operand" ""))]
1679 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1680 [(set (match_dup 2) (match_dup 3))
1681 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1682 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1683 "operands[2] = gen_lowpart (SImode, operands[0]);
1684 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1687 [(set (match_operand:DI 0 "register_operand" "")
1688 (match_operand:DI 1 "register_operand" ""))]
1689 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1690 && dead_or_set_p (insn, operands[1])"
1691 [(set (match_dup 3) (match_dup 2))
1692 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1693 (set (match_dup 4) (match_dup 2))]
1694 "operands[2] = gen_lowpart (SImode, operands[1]);
1695 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1698 [(set (match_operand:DI 0 "register_operand" "")
1699 (match_operand:DI 1 "register_operand" ""))]
1700 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1701 && !dead_or_set_p (insn, operands[1])"
1702 [(set (match_dup 3) (match_dup 2))
1703 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1704 (set (match_dup 4) (match_dup 2))
1705 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1706 "operands[2] = gen_lowpart (SImode, operands[1]);
1707 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1709 (define_insn "*movdi_31"
1710 [(set (match_operand:DI 0 "nonimmediate_operand"
1711 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1712 (match_operand:DI 1 "general_operand"
1713 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1728 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1729 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1730 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1732 ; For a load from a symbol ref we can use one of the target registers
1733 ; together with larl to load the address.
1735 [(set (match_operand:DI 0 "register_operand" "")
1736 (match_operand:DI 1 "memory_operand" ""))]
1737 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1738 && larl_operand (XEXP (operands[1], 0), SImode)"
1739 [(set (match_dup 2) (match_dup 3))
1740 (set (match_dup 0) (match_dup 1))]
1742 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1743 operands[3] = XEXP (operands[1], 0);
1744 operands[1] = replace_equiv_address (operands[1], operands[2]);
1748 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1749 (match_operand:DI 1 "general_operand" ""))]
1750 "!TARGET_ZARCH && reload_completed
1751 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1752 [(set (match_dup 2) (match_dup 4))
1753 (set (match_dup 3) (match_dup 5))]
1755 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1756 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1757 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1758 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1762 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1763 (match_operand:DI 1 "general_operand" ""))]
1764 "!TARGET_ZARCH && reload_completed
1765 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1766 [(set (match_dup 2) (match_dup 4))
1767 (set (match_dup 3) (match_dup 5))]
1769 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1770 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1771 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1772 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1776 [(set (match_operand:DI 0 "register_operand" "")
1777 (match_operand:DI 1 "memory_operand" ""))]
1778 "!TARGET_ZARCH && reload_completed
1779 && !FP_REG_P (operands[0])
1780 && !s_operand (operands[1], VOIDmode)"
1781 [(set (match_dup 0) (match_dup 1))]
1783 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1784 s390_load_address (addr, XEXP (operands[1], 0));
1785 operands[1] = replace_equiv_address (operands[1], addr);
1789 [(set (match_operand:DI 0 "register_operand" "")
1790 (mem:DI (match_operand 1 "address_operand" "")))]
1792 && !FP_REG_P (operands[0])
1793 && GET_CODE (operands[1]) == SYMBOL_REF
1794 && CONSTANT_POOL_ADDRESS_P (operands[1])
1795 && get_pool_mode (operands[1]) == DImode
1796 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1797 [(set (match_dup 0) (match_dup 2))]
1798 "operands[2] = get_pool_constant (operands[1]);")
1800 (define_insn "*la_64"
1801 [(set (match_operand:DI 0 "register_operand" "=d,d")
1802 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1807 [(set_attr "op_type" "RX,RXY")
1808 (set_attr "type" "la")
1809 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1813 [(set (match_operand:DI 0 "register_operand" "")
1814 (match_operand:QI 1 "address_operand" ""))
1815 (clobber (reg:CC CC_REGNUM))])]
1817 && preferred_la_operand_p (operands[1], const0_rtx)"
1818 [(set (match_dup 0) (match_dup 1))]
1822 [(set (match_operand:DI 0 "register_operand" "")
1823 (match_operand:DI 1 "register_operand" ""))
1826 (plus:DI (match_dup 0)
1827 (match_operand:DI 2 "nonmemory_operand" "")))
1828 (clobber (reg:CC CC_REGNUM))])]
1830 && !reg_overlap_mentioned_p (operands[0], operands[2])
1831 && preferred_la_operand_p (operands[1], operands[2])"
1832 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1836 ; movsi instruction pattern(s).
1839 (define_expand "movsi"
1840 [(set (match_operand:SI 0 "general_operand" "")
1841 (match_operand:SI 1 "general_operand" ""))]
1844 /* Handle symbolic constants. */
1846 && (SYMBOLIC_CONST (operands[1])
1847 || (GET_CODE (operands[1]) == PLUS
1848 && XEXP (operands[1], 0) == pic_offset_table_rtx
1849 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1850 emit_symbolic_move (operands);
1853 (define_insn "*movsi_larl"
1854 [(set (match_operand:SI 0 "register_operand" "=d")
1855 (match_operand:SI 1 "larl_operand" "X"))]
1856 "!TARGET_64BIT && TARGET_CPU_ZARCH
1857 && !FP_REG_P (operands[0])"
1859 [(set_attr "op_type" "RIL")
1860 (set_attr "type" "larl")
1861 (set_attr "z10prop" "z10_fwd_A1")])
1863 (define_insn "*movsi_zarch"
1864 [(set (match_operand:SI 0 "nonimmediate_operand"
1865 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
1866 (match_operand:SI 1 "general_operand"
1867 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
1900 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1901 RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1902 (set_attr "type" "*,
1926 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1927 vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1928 (set_attr "z10prop" "z10_fwd_A1,
1953 (define_insn "*movsi_esa"
1954 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
1955 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
1971 [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
1972 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
1973 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
1975 (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
1979 [(set (match_operand:SI 0 "register_operand" "")
1980 (mem:SI (match_operand 1 "address_operand" "")))]
1981 "!FP_REG_P (operands[0])
1982 && GET_CODE (operands[1]) == SYMBOL_REF
1983 && CONSTANT_POOL_ADDRESS_P (operands[1])
1984 && get_pool_mode (operands[1]) == SImode
1985 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1986 [(set (match_dup 0) (match_dup 2))]
1987 "operands[2] = get_pool_constant (operands[1]);")
1989 (define_insn "*la_31"
1990 [(set (match_operand:SI 0 "register_operand" "=d,d")
1991 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1992 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1996 [(set_attr "op_type" "RX,RXY")
1997 (set_attr "type" "la")
1998 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2002 [(set (match_operand:SI 0 "register_operand" "")
2003 (match_operand:QI 1 "address_operand" ""))
2004 (clobber (reg:CC CC_REGNUM))])]
2006 && preferred_la_operand_p (operands[1], const0_rtx)"
2007 [(set (match_dup 0) (match_dup 1))]
2011 [(set (match_operand:SI 0 "register_operand" "")
2012 (match_operand:SI 1 "register_operand" ""))
2015 (plus:SI (match_dup 0)
2016 (match_operand:SI 2 "nonmemory_operand" "")))
2017 (clobber (reg:CC CC_REGNUM))])]
2019 && !reg_overlap_mentioned_p (operands[0], operands[2])
2020 && preferred_la_operand_p (operands[1], operands[2])"
2021 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2024 (define_insn "*la_31_and"
2025 [(set (match_operand:SI 0 "register_operand" "=d,d")
2026 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
2027 (const_int 2147483647)))]
2032 [(set_attr "op_type" "RX,RXY")
2033 (set_attr "type" "la")
2034 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2036 (define_insn_and_split "*la_31_and_cc"
2037 [(set (match_operand:SI 0 "register_operand" "=d")
2038 (and:SI (match_operand:QI 1 "address_operand" "p")
2039 (const_int 2147483647)))
2040 (clobber (reg:CC CC_REGNUM))]
2043 "&& reload_completed"
2045 (and:SI (match_dup 1) (const_int 2147483647)))]
2047 [(set_attr "op_type" "RX")
2048 (set_attr "type" "la")])
2050 (define_insn "force_la_31"
2051 [(set (match_operand:SI 0 "register_operand" "=d,d")
2052 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
2053 (use (const_int 0))]
2058 [(set_attr "op_type" "RX")
2059 (set_attr "type" "la")
2060 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2063 ; movhi instruction pattern(s).
2066 (define_expand "movhi"
2067 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2068 (match_operand:HI 1 "general_operand" ""))]
2071 /* Make it explicit that loading a register from memory
2072 always sign-extends (at least) to SImode. */
2073 if (optimize && can_create_pseudo_p ()
2074 && register_operand (operands[0], VOIDmode)
2075 && GET_CODE (operands[1]) == MEM)
2077 rtx tmp = gen_reg_rtx (SImode);
2078 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2079 emit_insn (gen_rtx_SET (tmp, ext));
2080 operands[1] = gen_lowpart (HImode, tmp);
2084 (define_insn "*movhi"
2085 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
2086 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
2104 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2105 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2106 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
2107 (set_attr "z10prop" "z10_fr_E1,
2115 z10_super,*,*,*,*,*,*")])
2118 [(set (match_operand:HI 0 "register_operand" "")
2119 (mem:HI (match_operand 1 "address_operand" "")))]
2120 "GET_CODE (operands[1]) == SYMBOL_REF
2121 && CONSTANT_POOL_ADDRESS_P (operands[1])
2122 && get_pool_mode (operands[1]) == HImode
2123 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2124 [(set (match_dup 0) (match_dup 2))]
2125 "operands[2] = get_pool_constant (operands[1]);")
2128 ; movqi instruction pattern(s).
2131 (define_expand "movqi"
2132 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2133 (match_operand:QI 1 "general_operand" ""))]
2136 /* On z/Architecture, zero-extending from memory to register
2137 is just as fast as a QImode load. */
2138 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2139 && register_operand (operands[0], VOIDmode)
2140 && GET_CODE (operands[1]) == MEM)
2142 rtx tmp = gen_reg_rtx (DImode);
2143 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2144 emit_insn (gen_rtx_SET (tmp, ext));
2145 operands[1] = gen_lowpart (QImode, tmp);
2149 (define_insn "*movqi"
2150 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
2151 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
2169 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2170 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2171 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
2172 (set_attr "z10prop" "z10_fr_E1,
2183 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2184 (mem:QI (match_operand 1 "address_operand" "")))]
2185 "GET_CODE (operands[1]) == SYMBOL_REF
2186 && CONSTANT_POOL_ADDRESS_P (operands[1])
2187 && get_pool_mode (operands[1]) == QImode
2188 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2189 [(set (match_dup 0) (match_dup 2))]
2190 "operands[2] = get_pool_constant (operands[1]);")
2193 ; movstrictqi instruction pattern(s).
2196 (define_insn "*movstrictqi"
2197 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2198 (match_operand:QI 1 "memory_operand" "R,T"))]
2203 [(set_attr "op_type" "RX,RXY")
2204 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2207 ; movstricthi instruction pattern(s).
2210 (define_insn "*movstricthi"
2211 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2212 (match_operand:HI 1 "memory_operand" "Q,S"))
2213 (clobber (reg:CC CC_REGNUM))]
2218 [(set_attr "op_type" "RS,RSY")
2219 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2222 ; movstrictsi instruction pattern(s).
2225 (define_insn "movstrictsi"
2226 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2227 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2234 [(set_attr "op_type" "RR,RX,RXY,RRE")
2235 (set_attr "type" "lr,load,load,*")
2236 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2239 ; mov(tf|td) instruction pattern(s).
2242 (define_expand "mov<mode>"
2243 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2244 (match_operand:TD_TF 1 "general_operand" ""))]
2248 (define_insn "*mov<mode>_64"
2249 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2250 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2261 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2262 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2263 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2265 (define_insn "*mov<mode>_31"
2266 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2267 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2274 [(set_attr "op_type" "RRE,RRE,*,*")
2275 (set_attr "type" "fsimptf,fsimptf,*,*")
2276 (set_attr "cpu_facility" "z196,*,*,*")])
2278 ; TFmode in GPRs splitters
2281 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2282 (match_operand:TD_TF 1 "general_operand" ""))]
2283 "TARGET_ZARCH && reload_completed
2284 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2285 [(set (match_dup 2) (match_dup 4))
2286 (set (match_dup 3) (match_dup 5))]
2288 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2289 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2290 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2291 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2295 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2296 (match_operand:TD_TF 1 "general_operand" ""))]
2297 "TARGET_ZARCH && reload_completed
2298 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2299 [(set (match_dup 2) (match_dup 4))
2300 (set (match_dup 3) (match_dup 5))]
2302 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2303 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2304 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2305 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2309 [(set (match_operand:TD_TF 0 "register_operand" "")
2310 (match_operand:TD_TF 1 "memory_operand" ""))]
2311 "TARGET_ZARCH && reload_completed
2312 && GENERAL_REG_P (operands[0])
2313 && !s_operand (operands[1], VOIDmode)"
2314 [(set (match_dup 0) (match_dup 1))]
2316 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2317 addr = gen_lowpart (Pmode, addr);
2318 s390_load_address (addr, XEXP (operands[1], 0));
2319 operands[1] = replace_equiv_address (operands[1], addr);
2322 ; TFmode in BFPs splitters
2325 [(set (match_operand:TD_TF 0 "register_operand" "")
2326 (match_operand:TD_TF 1 "memory_operand" ""))]
2327 "reload_completed && offsettable_memref_p (operands[1])
2328 && FP_REG_P (operands[0])"
2329 [(set (match_dup 2) (match_dup 4))
2330 (set (match_dup 3) (match_dup 5))]
2332 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2334 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2336 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2337 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2341 [(set (match_operand:TD_TF 0 "memory_operand" "")
2342 (match_operand:TD_TF 1 "register_operand" ""))]
2343 "reload_completed && offsettable_memref_p (operands[0])
2344 && FP_REG_P (operands[1])"
2345 [(set (match_dup 2) (match_dup 4))
2346 (set (match_dup 3) (match_dup 5))]
2348 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2349 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2350 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2352 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2357 ; mov(df|dd) instruction pattern(s).
2360 (define_expand "mov<mode>"
2361 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2362 (match_operand:DD_DF 1 "general_operand" ""))]
2366 (define_insn "*mov<mode>_64dfp"
2367 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2368 "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
2369 (match_operand:DD_DF 1 "general_operand"
2370 " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
2392 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2393 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2394 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2395 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2396 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2398 (define_insn "*mov<mode>_64"
2399 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
2400 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
2418 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2419 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2420 fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2421 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2422 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
2424 (define_insn "*mov<mode>_31"
2425 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2426 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2427 (match_operand:DD_DF 1 "general_operand"
2428 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2443 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2444 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2445 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2446 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2449 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2450 (match_operand:DD_DF 1 "general_operand" ""))]
2451 "!TARGET_ZARCH && reload_completed
2452 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2453 [(set (match_dup 2) (match_dup 4))
2454 (set (match_dup 3) (match_dup 5))]
2456 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2457 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2458 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2459 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2463 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2464 (match_operand:DD_DF 1 "general_operand" ""))]
2465 "!TARGET_ZARCH && reload_completed
2466 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2467 [(set (match_dup 2) (match_dup 4))
2468 (set (match_dup 3) (match_dup 5))]
2470 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2471 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2472 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2473 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2477 [(set (match_operand:DD_DF 0 "register_operand" "")
2478 (match_operand:DD_DF 1 "memory_operand" ""))]
2479 "!TARGET_ZARCH && reload_completed
2480 && !FP_REG_P (operands[0])
2481 && !s_operand (operands[1], VOIDmode)"
2482 [(set (match_dup 0) (match_dup 1))]
2484 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2485 s390_load_address (addr, XEXP (operands[1], 0));
2486 operands[1] = replace_equiv_address (operands[1], addr);
2490 ; mov(sf|sd) instruction pattern(s).
2493 (define_insn "mov<mode>"
2494 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2495 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
2496 (match_operand:SD_SF 1 "general_operand"
2497 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
2522 [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2523 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2524 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2525 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2526 (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
2529 ; movcc instruction pattern
2532 (define_insn "movcc"
2533 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2534 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2544 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2545 (set_attr "type" "lr,*,*,load,load,store,store")
2546 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2547 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2550 ; Block move (MVC) patterns.
2554 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2555 (match_operand:BLK 1 "memory_operand" "Q"))
2556 (use (match_operand 2 "const_int_operand" "n"))]
2557 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2558 "mvc\t%O0(%2,%R0),%S1"
2559 [(set_attr "op_type" "SS")])
2561 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2562 ; order to have it implemented with mvc.
2565 [(set (match_operand:QI 0 "memory_operand" "")
2566 (match_operand:QI 1 "memory_operand" ""))]
2569 [(set (match_dup 0) (match_dup 1))
2570 (use (const_int 1))])]
2572 operands[0] = adjust_address (operands[0], BLKmode, 0);
2573 operands[1] = adjust_address (operands[1], BLKmode, 0);
2579 [(set (match_operand:BLK 0 "memory_operand" "")
2580 (match_operand:BLK 1 "memory_operand" ""))
2581 (use (match_operand 2 "const_int_operand" ""))])
2583 [(set (match_operand:BLK 3 "memory_operand" "")
2584 (match_operand:BLK 4 "memory_operand" ""))
2585 (use (match_operand 5 "const_int_operand" ""))])]
2586 "s390_offset_p (operands[0], operands[3], operands[2])
2587 && s390_offset_p (operands[1], operands[4], operands[2])
2588 && !s390_overlap_p (operands[0], operands[1],
2589 INTVAL (operands[2]) + INTVAL (operands[5]))
2590 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2592 [(set (match_dup 6) (match_dup 7))
2593 (use (match_dup 8))])]
2594 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2595 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2596 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2600 ; load_multiple pattern(s).
2602 ; ??? Due to reload problems with replacing registers inside match_parallel
2603 ; we currently support load_multiple/store_multiple only after reload.
2606 (define_expand "load_multiple"
2607 [(match_par_dup 3 [(set (match_operand 0 "" "")
2608 (match_operand 1 "" ""))
2609 (use (match_operand 2 "" ""))])]
2618 /* Support only loading a constant number of fixed-point registers from
2619 memory and only bother with this if more than two */
2620 if (GET_CODE (operands[2]) != CONST_INT
2621 || INTVAL (operands[2]) < 2
2622 || INTVAL (operands[2]) > 16
2623 || GET_CODE (operands[1]) != MEM
2624 || GET_CODE (operands[0]) != REG
2625 || REGNO (operands[0]) >= 16)
2628 count = INTVAL (operands[2]);
2629 regno = REGNO (operands[0]);
2630 mode = GET_MODE (operands[0]);
2631 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2634 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2635 if (!can_create_pseudo_p ())
2637 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2639 from = XEXP (operands[1], 0);
2642 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2643 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2644 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2646 from = XEXP (XEXP (operands[1], 0), 0);
2647 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2654 from = force_reg (Pmode, XEXP (operands[1], 0));
2658 for (i = 0; i < count; i++)
2659 XVECEXP (operands[3], 0, i)
2660 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2661 change_address (operands[1], mode,
2662 plus_constant (Pmode, from,
2663 off + i * GET_MODE_SIZE (mode))));
2666 (define_insn "*load_multiple_di"
2667 [(match_parallel 0 "load_multiple_operation"
2668 [(set (match_operand:DI 1 "register_operand" "=r")
2669 (match_operand:DI 2 "s_operand" "QS"))])]
2670 "reload_completed && TARGET_ZARCH"
2672 int words = XVECLEN (operands[0], 0);
2673 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2674 return "lmg\t%1,%0,%S2";
2676 [(set_attr "op_type" "RSY")
2677 (set_attr "type" "lm")])
2679 (define_insn "*load_multiple_si"
2680 [(match_parallel 0 "load_multiple_operation"
2681 [(set (match_operand:SI 1 "register_operand" "=r,r")
2682 (match_operand:SI 2 "s_operand" "Q,S"))])]
2685 int words = XVECLEN (operands[0], 0);
2686 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2687 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2689 [(set_attr "op_type" "RS,RSY")
2690 (set_attr "type" "lm")])
2693 ; store multiple pattern(s).
2696 (define_expand "store_multiple"
2697 [(match_par_dup 3 [(set (match_operand 0 "" "")
2698 (match_operand 1 "" ""))
2699 (use (match_operand 2 "" ""))])]
2708 /* Support only storing a constant number of fixed-point registers to
2709 memory and only bother with this if more than two. */
2710 if (GET_CODE (operands[2]) != CONST_INT
2711 || INTVAL (operands[2]) < 2
2712 || INTVAL (operands[2]) > 16
2713 || GET_CODE (operands[0]) != MEM
2714 || GET_CODE (operands[1]) != REG
2715 || REGNO (operands[1]) >= 16)
2718 count = INTVAL (operands[2]);
2719 regno = REGNO (operands[1]);
2720 mode = GET_MODE (operands[1]);
2721 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2724 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2726 if (!can_create_pseudo_p ())
2728 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2730 to = XEXP (operands[0], 0);
2733 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2734 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2735 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2737 to = XEXP (XEXP (operands[0], 0), 0);
2738 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2745 to = force_reg (Pmode, XEXP (operands[0], 0));
2749 for (i = 0; i < count; i++)
2750 XVECEXP (operands[3], 0, i)
2751 = gen_rtx_SET (change_address (operands[0], mode,
2752 plus_constant (Pmode, to,
2753 off + i * GET_MODE_SIZE (mode))),
2754 gen_rtx_REG (mode, regno + i));
2757 (define_insn "*store_multiple_di"
2758 [(match_parallel 0 "store_multiple_operation"
2759 [(set (match_operand:DI 1 "s_operand" "=QS")
2760 (match_operand:DI 2 "register_operand" "r"))])]
2761 "reload_completed && TARGET_ZARCH"
2763 int words = XVECLEN (operands[0], 0);
2764 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2765 return "stmg\t%2,%0,%S1";
2767 [(set_attr "op_type" "RSY")
2768 (set_attr "type" "stm")])
2771 (define_insn "*store_multiple_si"
2772 [(match_parallel 0 "store_multiple_operation"
2773 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2774 (match_operand:SI 2 "register_operand" "r,r"))])]
2777 int words = XVECLEN (operands[0], 0);
2778 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2779 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2781 [(set_attr "op_type" "RS,RSY")
2782 (set_attr "type" "stm")])
2785 ;; String instructions.
2788 (define_insn "*execute_rl"
2789 [(match_parallel 0 "execute_operation"
2790 [(unspec [(match_operand 1 "register_operand" "a")
2791 (match_operand 2 "" "")
2792 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2793 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2794 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2796 [(set_attr "op_type" "RIL")
2797 (set_attr "type" "cs")])
2799 (define_insn "*execute"
2800 [(match_parallel 0 "execute_operation"
2801 [(unspec [(match_operand 1 "register_operand" "a")
2802 (match_operand:BLK 2 "memory_operand" "R")
2803 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2804 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2805 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2807 [(set_attr "op_type" "RX")
2808 (set_attr "type" "cs")])
2812 ; strlenM instruction pattern(s).
2815 (define_expand "strlen<mode>"
2816 [(match_operand:P 0 "register_operand" "") ; result
2817 (match_operand:BLK 1 "memory_operand" "") ; input string
2818 (match_operand:SI 2 "immediate_operand" "") ; search character
2819 (match_operand:SI 3 "immediate_operand" "")] ; known alignment
2822 if (!TARGET_VX || operands[2] != const0_rtx)
2823 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2824 operands[2], operands[3]));
2826 s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2831 (define_expand "strlen_srst<mode>"
2832 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2835 (unspec:P [(const_int 0)
2836 (match_operand:BLK 1 "memory_operand" "")
2838 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2839 (clobber (scratch:P))
2840 (clobber (reg:CC CC_REGNUM))])
2842 [(set (match_operand:P 0 "register_operand" "")
2843 (minus:P (match_dup 4) (match_dup 5)))
2844 (clobber (reg:CC CC_REGNUM))])]
2847 operands[4] = gen_reg_rtx (Pmode);
2848 operands[5] = gen_reg_rtx (Pmode);
2849 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2850 operands[1] = replace_equiv_address (operands[1], operands[5]);
2853 (define_insn "*strlen<mode>"
2854 [(set (match_operand:P 0 "register_operand" "=a")
2855 (unspec:P [(match_operand:P 2 "general_operand" "0")
2856 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2858 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2859 (clobber (match_scratch:P 1 "=a"))
2860 (clobber (reg:CC CC_REGNUM))]
2862 "srst\t%0,%1\;jo\t.-4"
2863 [(set_attr "length" "8")
2864 (set_attr "type" "vs")])
2867 ; cmpstrM instruction pattern(s).
2870 (define_expand "cmpstrsi"
2871 [(set (reg:SI 0) (const_int 0))
2873 [(clobber (match_operand 3 "" ""))
2874 (clobber (match_dup 4))
2875 (set (reg:CCU CC_REGNUM)
2876 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2877 (match_operand:BLK 2 "memory_operand" "")))
2880 [(set (match_operand:SI 0 "register_operand" "=d")
2881 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2882 (clobber (reg:CC CC_REGNUM))])]
2885 /* As the result of CMPINT is inverted compared to what we need,
2886 we have to swap the operands. */
2887 rtx op1 = operands[2];
2888 rtx op2 = operands[1];
2889 rtx addr1 = gen_reg_rtx (Pmode);
2890 rtx addr2 = gen_reg_rtx (Pmode);
2892 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2893 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2894 operands[1] = replace_equiv_address_nv (op1, addr1);
2895 operands[2] = replace_equiv_address_nv (op2, addr2);
2896 operands[3] = addr1;
2897 operands[4] = addr2;
2900 (define_insn "*cmpstr<mode>"
2901 [(clobber (match_operand:P 0 "register_operand" "=d"))
2902 (clobber (match_operand:P 1 "register_operand" "=d"))
2903 (set (reg:CCU CC_REGNUM)
2904 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2905 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2908 "clst\t%0,%1\;jo\t.-4"
2909 [(set_attr "length" "8")
2910 (set_attr "type" "vs")])
2913 ; movstr instruction pattern.
2916 (define_expand "movstr"
2917 [(match_operand 0 "register_operand" "")
2918 (match_operand 1 "memory_operand" "")
2919 (match_operand 2 "memory_operand" "")]
2923 emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
2925 emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
2929 (define_expand "movstr<P:mode>"
2930 [(set (reg:SI 0) (const_int 0))
2932 [(clobber (match_dup 3))
2933 (set (match_operand:BLK 1 "memory_operand" "")
2934 (match_operand:BLK 2 "memory_operand" ""))
2935 (set (match_operand:P 0 "register_operand" "")
2936 (unspec:P [(match_dup 1)
2938 (reg:SI 0)] UNSPEC_MVST))
2939 (clobber (reg:CC CC_REGNUM))])]
2944 if (TARGET_VX && optimize_function_for_speed_p (cfun))
2946 s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
2950 addr1 = gen_reg_rtx (Pmode);
2951 addr2 = gen_reg_rtx (Pmode);
2953 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2954 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2955 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2956 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2957 operands[3] = addr2;
2960 (define_insn "*movstr"
2961 [(clobber (match_operand:P 2 "register_operand" "=d"))
2962 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2963 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2964 (set (match_operand:P 0 "register_operand" "=d")
2965 (unspec:P [(mem:BLK (match_dup 1))
2966 (mem:BLK (match_dup 3))
2967 (reg:SI 0)] UNSPEC_MVST))
2968 (clobber (reg:CC CC_REGNUM))]
2970 "mvst\t%1,%2\;jo\t.-4"
2971 [(set_attr "length" "8")
2972 (set_attr "type" "vs")])
2976 ; movmemM instruction pattern(s).
2979 (define_expand "movmem<mode>"
2980 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2981 (match_operand:BLK 1 "memory_operand" "")) ; source
2982 (use (match_operand:GPR 2 "general_operand" "")) ; count
2983 (match_operand 3 "" "")]
2986 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2992 ; Move a block that is up to 256 bytes in length.
2993 ; The block length is taken as (operands[2] % 256) + 1.
2995 (define_expand "movmem_short"
2997 [(set (match_operand:BLK 0 "memory_operand" "")
2998 (match_operand:BLK 1 "memory_operand" ""))
2999 (use (match_operand 2 "nonmemory_operand" ""))
3000 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3001 (clobber (match_dup 3))])]
3003 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3005 (define_insn "*movmem_short"
3006 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3007 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3008 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3009 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3010 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3011 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3013 [(set_attr "type" "cs")
3014 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3017 [(set (match_operand:BLK 0 "memory_operand" "")
3018 (match_operand:BLK 1 "memory_operand" ""))
3019 (use (match_operand 2 "const_int_operand" ""))
3020 (use (match_operand 3 "immediate_operand" ""))
3021 (clobber (scratch))]
3024 [(set (match_dup 0) (match_dup 1))
3025 (use (match_dup 2))])]
3026 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3029 [(set (match_operand:BLK 0 "memory_operand" "")
3030 (match_operand:BLK 1 "memory_operand" ""))
3031 (use (match_operand 2 "register_operand" ""))
3032 (use (match_operand 3 "memory_operand" ""))
3033 (clobber (scratch))]
3036 [(unspec [(match_dup 2) (match_dup 3)
3037 (const_int 0)] UNSPEC_EXECUTE)
3038 (set (match_dup 0) (match_dup 1))
3039 (use (const_int 1))])]
3043 [(set (match_operand:BLK 0 "memory_operand" "")
3044 (match_operand:BLK 1 "memory_operand" ""))
3045 (use (match_operand 2 "register_operand" ""))
3046 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3047 (clobber (scratch))]
3048 "TARGET_Z10 && reload_completed"
3050 [(unspec [(match_dup 2) (const_int 0)
3051 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3052 (set (match_dup 0) (match_dup 1))
3053 (use (const_int 1))])]
3054 "operands[3] = gen_label_rtx ();")
3057 [(set (match_operand:BLK 0 "memory_operand" "")
3058 (match_operand:BLK 1 "memory_operand" ""))
3059 (use (match_operand 2 "register_operand" ""))
3060 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3061 (clobber (match_operand 3 "register_operand" ""))]
3062 "reload_completed && TARGET_CPU_ZARCH"
3063 [(set (match_dup 3) (label_ref (match_dup 4)))
3065 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3066 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3067 (set (match_dup 0) (match_dup 1))
3068 (use (const_int 1))])]
3069 "operands[4] = gen_label_rtx ();")
3071 ; Move a block of arbitrary length.
3073 (define_expand "movmem_long"
3075 [(clobber (match_dup 2))
3076 (clobber (match_dup 3))
3077 (set (match_operand:BLK 0 "memory_operand" "")
3078 (match_operand:BLK 1 "memory_operand" ""))
3079 (use (match_operand 2 "general_operand" ""))
3081 (clobber (reg:CC CC_REGNUM))])]
3084 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3085 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3086 rtx reg0 = gen_reg_rtx (dreg_mode);
3087 rtx reg1 = gen_reg_rtx (dreg_mode);
3088 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3089 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3090 rtx len0 = gen_lowpart (Pmode, reg0);
3091 rtx len1 = gen_lowpart (Pmode, reg1);
3093 emit_clobber (reg0);
3094 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3095 emit_move_insn (len0, operands[2]);
3097 emit_clobber (reg1);
3098 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3099 emit_move_insn (len1, operands[2]);
3101 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3102 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3107 (define_insn "*movmem_long"
3108 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3109 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3110 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3111 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3114 (clobber (reg:CC CC_REGNUM))]
3115 "TARGET_64BIT || !TARGET_ZARCH"
3116 "mvcle\t%0,%1,0\;jo\t.-4"
3117 [(set_attr "length" "8")
3118 (set_attr "type" "vs")])
3120 (define_insn "*movmem_long_31z"
3121 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3122 (clobber (match_operand:TI 1 "register_operand" "=d"))
3123 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3124 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3127 (clobber (reg:CC CC_REGNUM))]
3128 "!TARGET_64BIT && TARGET_ZARCH"
3129 "mvcle\t%0,%1,0\;jo\t.-4"
3130 [(set_attr "length" "8")
3131 (set_attr "type" "vs")])
3138 (define_expand "signbit<mode>2"
3139 [(set (reg:CCZ CC_REGNUM)
3140 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3143 (set (match_operand:SI 0 "register_operand" "=d")
3144 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3147 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3150 (define_expand "isinf<mode>2"
3151 [(set (reg:CCZ CC_REGNUM)
3152 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3155 (set (match_operand:SI 0 "register_operand" "=d")
3156 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3159 operands[2] = GEN_INT (S390_TDC_INFINITY);
3162 ; This extracts CC into a GPR properly shifted. The actual IPM
3163 ; instruction will be issued by reload. The constraint of operand 1
3164 ; forces reload to use a GPR. So reload will issue a movcc insn for
3165 ; copying CC into a GPR first.
3166 (define_insn_and_split "*cc_to_int"
3167 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3168 (unspec:SI [(match_operand 1 "register_operand" "0")]
3173 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3175 ; This insn is used to generate all variants of the Test Data Class
3176 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
3177 ; is the register to be tested and the second one is the bit mask
3178 ; specifying the required test(s).
3180 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3181 (define_insn "*TDC_insn_<mode>"
3182 [(set (reg:CCZ CC_REGNUM)
3183 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3184 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3186 "t<_d>c<xde><bt>\t%0,%1"
3187 [(set_attr "op_type" "RXE")
3188 (set_attr "type" "fsimp<mode>")])
3193 ; setmemM instruction pattern(s).
3196 (define_expand "setmem<mode>"
3197 [(set (match_operand:BLK 0 "memory_operand" "")
3198 (match_operand:QI 2 "general_operand" ""))
3199 (use (match_operand:GPR 1 "general_operand" ""))
3200 (match_operand 3 "" "")]
3202 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3204 ; Clear a block that is up to 256 bytes in length.
3205 ; The block length is taken as (operands[1] % 256) + 1.
3207 (define_expand "clrmem_short"
3209 [(set (match_operand:BLK 0 "memory_operand" "")
3211 (use (match_operand 1 "nonmemory_operand" ""))
3212 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3213 (clobber (match_dup 2))
3214 (clobber (reg:CC CC_REGNUM))])]
3216 "operands[2] = gen_rtx_SCRATCH (Pmode);")
3218 (define_insn "*clrmem_short"
3219 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3221 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3222 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3223 (clobber (match_scratch:P 3 "=X,X,X,&a"))
3224 (clobber (reg:CC CC_REGNUM))]
3225 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3227 [(set_attr "type" "cs")
3228 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3231 [(set (match_operand:BLK 0 "memory_operand" "")
3233 (use (match_operand 1 "const_int_operand" ""))
3234 (use (match_operand 2 "immediate_operand" ""))
3236 (clobber (reg:CC CC_REGNUM))]
3239 [(set (match_dup 0) (const_int 0))
3241 (clobber (reg:CC CC_REGNUM))])]
3242 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3245 [(set (match_operand:BLK 0 "memory_operand" "")
3247 (use (match_operand 1 "register_operand" ""))
3248 (use (match_operand 2 "memory_operand" ""))
3250 (clobber (reg:CC CC_REGNUM))]
3253 [(unspec [(match_dup 1) (match_dup 2)
3254 (const_int 0)] UNSPEC_EXECUTE)
3255 (set (match_dup 0) (const_int 0))
3257 (clobber (reg:CC CC_REGNUM))])]
3261 [(set (match_operand:BLK 0 "memory_operand" "")
3263 (use (match_operand 1 "register_operand" ""))
3264 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3266 (clobber (reg:CC CC_REGNUM))]
3267 "TARGET_Z10 && reload_completed"
3269 [(unspec [(match_dup 1) (const_int 0)
3270 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3271 (set (match_dup 0) (const_int 0))
3273 (clobber (reg:CC CC_REGNUM))])]
3274 "operands[3] = gen_label_rtx ();")
3277 [(set (match_operand:BLK 0 "memory_operand" "")
3279 (use (match_operand 1 "register_operand" ""))
3280 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3281 (clobber (match_operand 2 "register_operand" ""))
3282 (clobber (reg:CC CC_REGNUM))]
3283 "reload_completed && TARGET_CPU_ZARCH"
3284 [(set (match_dup 2) (label_ref (match_dup 3)))
3286 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3287 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3288 (set (match_dup 0) (const_int 0))
3290 (clobber (reg:CC CC_REGNUM))])]
3291 "operands[3] = gen_label_rtx ();")
3293 ; Initialize a block of arbitrary length with (operands[2] % 256).
3295 (define_expand "setmem_long_<P:mode>"
3297 [(clobber (match_dup 1))
3298 (set (match_operand:BLK 0 "memory_operand" "")
3299 (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "")
3300 (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3302 (clobber (reg:CC CC_REGNUM))])]
3305 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3306 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3307 rtx reg0 = gen_reg_rtx (dreg_mode);
3308 rtx reg1 = gen_reg_rtx (dreg_mode);
3309 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3310 rtx len0 = gen_lowpart (Pmode, reg0);
3312 emit_clobber (reg0);
3313 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3314 emit_move_insn (len0, operands[1]);
3316 emit_move_insn (reg1, const0_rtx);
3318 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3321 operands[4] = gen_lowpart (Pmode, operands[1]);
3324 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3326 (define_insn "*setmem_long"
3327 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3328 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3329 (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y")
3330 (subreg:P (match_dup 3) <modesize>)]
3331 UNSPEC_REPLICATE_BYTE))
3332 (use (match_operand:<DBL> 1 "register_operand" "d"))
3333 (clobber (reg:CC CC_REGNUM))]
3334 "TARGET_64BIT || !TARGET_ZARCH"
3335 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3336 [(set_attr "length" "8")
3337 (set_attr "type" "vs")])
3339 (define_insn "*setmem_long_and"
3340 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3341 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3343 (match_operand:P 2 "shift_count_or_setmem_operand" "Y")
3344 (match_operand:P 4 "const_int_operand" "n"))
3345 (subreg:P (match_dup 3) <modesize>)]
3346 UNSPEC_REPLICATE_BYTE))
3347 (use (match_operand:<DBL> 1 "register_operand" "d"))
3348 (clobber (reg:CC CC_REGNUM))]
3349 "(TARGET_64BIT || !TARGET_ZARCH) &&
3350 (INTVAL (operands[4]) & 255) == 255"
3351 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3352 [(set_attr "length" "8")
3353 (set_attr "type" "vs")])
3355 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3356 ; of the SImode subregs.
3358 (define_insn "*setmem_long_31z"
3359 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3360 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3361 (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
3362 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3363 (use (match_operand:TI 1 "register_operand" "d"))
3364 (clobber (reg:CC CC_REGNUM))]
3365 "!TARGET_64BIT && TARGET_ZARCH"
3366 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3367 [(set_attr "length" "8")
3368 (set_attr "type" "vs")])
3370 (define_insn "*setmem_long_and_31z"
3371 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3372 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3373 (unspec:BLK [(and:SI
3374 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
3375 (match_operand:SI 4 "const_int_operand" "n"))
3376 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3377 (use (match_operand:TI 1 "register_operand" "d"))
3378 (clobber (reg:CC CC_REGNUM))]
3379 "(!TARGET_64BIT && TARGET_ZARCH) &&
3380 (INTVAL (operands[4]) & 255) == 255"
3381 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3382 [(set_attr "length" "8")
3383 (set_attr "type" "vs")])
3386 ; cmpmemM instruction pattern(s).
3389 (define_expand "cmpmemsi"
3390 [(set (match_operand:SI 0 "register_operand" "")
3391 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3392 (match_operand:BLK 2 "memory_operand" "") ) )
3393 (use (match_operand:SI 3 "general_operand" ""))
3394 (use (match_operand:SI 4 "" ""))]
3397 if (s390_expand_cmpmem (operands[0], operands[1],
3398 operands[2], operands[3]))
3404 ; Compare a block that is up to 256 bytes in length.
3405 ; The block length is taken as (operands[2] % 256) + 1.
3407 (define_expand "cmpmem_short"
3409 [(set (reg:CCU CC_REGNUM)
3410 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3411 (match_operand:BLK 1 "memory_operand" "")))
3412 (use (match_operand 2 "nonmemory_operand" ""))
3413 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3414 (clobber (match_dup 3))])]
3416 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3418 (define_insn "*cmpmem_short"
3419 [(set (reg:CCU CC_REGNUM)
3420 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3421 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3422 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3423 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3424 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3425 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3427 [(set_attr "type" "cs")
3428 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3431 [(set (reg:CCU CC_REGNUM)
3432 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3433 (match_operand:BLK 1 "memory_operand" "")))
3434 (use (match_operand 2 "const_int_operand" ""))
3435 (use (match_operand 3 "immediate_operand" ""))
3436 (clobber (scratch))]
3439 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3440 (use (match_dup 2))])]
3441 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3444 [(set (reg:CCU CC_REGNUM)
3445 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3446 (match_operand:BLK 1 "memory_operand" "")))
3447 (use (match_operand 2 "register_operand" ""))
3448 (use (match_operand 3 "memory_operand" ""))
3449 (clobber (scratch))]
3452 [(unspec [(match_dup 2) (match_dup 3)
3453 (const_int 0)] UNSPEC_EXECUTE)
3454 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3455 (use (const_int 1))])]
3459 [(set (reg:CCU CC_REGNUM)
3460 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3461 (match_operand:BLK 1 "memory_operand" "")))
3462 (use (match_operand 2 "register_operand" ""))
3463 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3464 (clobber (scratch))]
3465 "TARGET_Z10 && reload_completed"
3467 [(unspec [(match_dup 2) (const_int 0)
3468 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3469 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3470 (use (const_int 1))])]
3471 "operands[4] = gen_label_rtx ();")
3474 [(set (reg:CCU CC_REGNUM)
3475 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3476 (match_operand:BLK 1 "memory_operand" "")))
3477 (use (match_operand 2 "register_operand" ""))
3478 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3479 (clobber (match_operand 3 "register_operand" ""))]
3480 "reload_completed && TARGET_CPU_ZARCH"
3481 [(set (match_dup 3) (label_ref (match_dup 4)))
3483 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3484 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3485 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3486 (use (const_int 1))])]
3487 "operands[4] = gen_label_rtx ();")
3489 ; Compare a block of arbitrary length.
3491 (define_expand "cmpmem_long"
3493 [(clobber (match_dup 2))
3494 (clobber (match_dup 3))
3495 (set (reg:CCU CC_REGNUM)
3496 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3497 (match_operand:BLK 1 "memory_operand" "")))
3498 (use (match_operand 2 "general_operand" ""))
3499 (use (match_dup 3))])]
3502 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3503 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3504 rtx reg0 = gen_reg_rtx (dreg_mode);
3505 rtx reg1 = gen_reg_rtx (dreg_mode);
3506 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3507 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3508 rtx len0 = gen_lowpart (Pmode, reg0);
3509 rtx len1 = gen_lowpart (Pmode, reg1);
3511 emit_clobber (reg0);
3512 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3513 emit_move_insn (len0, operands[2]);
3515 emit_clobber (reg1);
3516 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3517 emit_move_insn (len1, operands[2]);
3519 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3520 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3525 (define_insn "*cmpmem_long"
3526 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3527 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3528 (set (reg:CCU CC_REGNUM)
3529 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3530 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3532 (use (match_dup 3))]
3533 "TARGET_64BIT || !TARGET_ZARCH"
3534 "clcle\t%0,%1,0\;jo\t.-4"
3535 [(set_attr "length" "8")
3536 (set_attr "type" "vs")])
3538 (define_insn "*cmpmem_long_31z"
3539 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3540 (clobber (match_operand:TI 1 "register_operand" "=d"))
3541 (set (reg:CCU CC_REGNUM)
3542 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3543 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3545 (use (match_dup 3))]
3546 "!TARGET_64BIT && TARGET_ZARCH"
3547 "clcle\t%0,%1,0\;jo\t.-4"
3548 [(set_attr "op_type" "NN")
3549 (set_attr "type" "vs")
3550 (set_attr "length" "8")])
3552 ; Convert CCUmode condition code to integer.
3553 ; Result is zero if EQ, positive if LTU, negative if GTU.
3555 (define_insn_and_split "cmpint"
3556 [(set (match_operand:SI 0 "register_operand" "=d")
3557 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3558 UNSPEC_STRCMPCC_TO_INT))
3559 (clobber (reg:CC CC_REGNUM))]
3563 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3565 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3566 (clobber (reg:CC CC_REGNUM))])])
3568 (define_insn_and_split "*cmpint_cc"
3569 [(set (reg CC_REGNUM)
3570 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3571 UNSPEC_STRCMPCC_TO_INT)
3573 (set (match_operand:SI 0 "register_operand" "=d")
3574 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3575 "s390_match_ccmode (insn, CCSmode)"
3577 "&& reload_completed"
3578 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3580 [(set (match_dup 2) (match_dup 3))
3581 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3583 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3584 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3585 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3588 (define_insn_and_split "*cmpint_sign"
3589 [(set (match_operand:DI 0 "register_operand" "=d")
3590 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3591 UNSPEC_STRCMPCC_TO_INT)))
3592 (clobber (reg:CC CC_REGNUM))]
3595 "&& reload_completed"
3596 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3598 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3599 (clobber (reg:CC CC_REGNUM))])])
3601 (define_insn_and_split "*cmpint_sign_cc"
3602 [(set (reg CC_REGNUM)
3603 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3604 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3605 UNSPEC_STRCMPCC_TO_INT) 0)
3606 (const_int 32)) (const_int 32))
3608 (set (match_operand:DI 0 "register_operand" "=d")
3609 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3610 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3612 "&& reload_completed"
3613 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3615 [(set (match_dup 2) (match_dup 3))
3616 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3618 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3619 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3620 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3625 ;;- Conversion instructions.
3628 (define_insn "*sethighpartsi"
3629 [(set (match_operand:SI 0 "register_operand" "=d,d")
3630 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3631 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3632 (clobber (reg:CC CC_REGNUM))]
3637 [(set_attr "op_type" "RS,RSY")
3638 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3640 (define_insn "*sethighpartdi_64"
3641 [(set (match_operand:DI 0 "register_operand" "=d")
3642 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3643 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3644 (clobber (reg:CC CC_REGNUM))]
3647 [(set_attr "op_type" "RSY")
3648 (set_attr "z10prop" "z10_super")])
3650 (define_insn "*sethighpartdi_31"
3651 [(set (match_operand:DI 0 "register_operand" "=d,d")
3652 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3653 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3654 (clobber (reg:CC CC_REGNUM))]
3659 [(set_attr "op_type" "RS,RSY")
3660 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3663 ; extv instruction patterns
3666 ; FIXME: This expander needs to be converted from DI to GPR as well
3667 ; after resolving some issues with it.
3669 (define_expand "extzv"
3671 [(set (match_operand:DI 0 "register_operand" "=d")
3673 (match_operand:DI 1 "register_operand" "d")
3674 (match_operand 2 "const_int_operand" "") ; size
3675 (match_operand 3 "const_int_operand" ""))) ; start
3676 (clobber (reg:CC CC_REGNUM))])]
3679 /* Starting with zEC12 there is risbgn not clobbering CC. */
3682 emit_move_insn (operands[0],
3683 gen_rtx_ZERO_EXTRACT (DImode,
3691 (define_insn "*extzv<mode>_zEC12"
3692 [(set (match_operand:GPR 0 "register_operand" "=d")
3694 (match_operand:GPR 1 "register_operand" "d")
3695 (match_operand 2 "const_int_operand" "") ; size
3696 (match_operand 3 "const_int_operand" "")))] ; start]
3698 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3699 [(set_attr "op_type" "RIE")])
3701 (define_insn "*extzv<mode>_z10"
3702 [(set (match_operand:GPR 0 "register_operand" "=d")
3704 (match_operand:GPR 1 "register_operand" "d")
3705 (match_operand 2 "const_int_operand" "") ; size
3706 (match_operand 3 "const_int_operand" ""))) ; start
3707 (clobber (reg:CC CC_REGNUM))]
3709 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3710 [(set_attr "op_type" "RIE")
3711 (set_attr "z10prop" "z10_super_E1")])
3713 (define_insn_and_split "*pre_z10_extzv<mode>"
3714 [(set (match_operand:GPR 0 "register_operand" "=d")
3715 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3716 (match_operand 2 "nonzero_shift_count_operand" "")
3718 (clobber (reg:CC CC_REGNUM))]
3721 "&& reload_completed"
3723 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3724 (clobber (reg:CC CC_REGNUM))])
3725 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3727 int bitsize = INTVAL (operands[2]);
3728 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3729 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3731 operands[1] = adjust_address (operands[1], BLKmode, 0);
3732 set_mem_size (operands[1], size);
3733 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3734 operands[3] = GEN_INT (mask);
3737 (define_insn_and_split "*pre_z10_extv<mode>"
3738 [(set (match_operand:GPR 0 "register_operand" "=d")
3739 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3740 (match_operand 2 "nonzero_shift_count_operand" "")
3742 (clobber (reg:CC CC_REGNUM))]
3745 "&& reload_completed"
3747 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3748 (clobber (reg:CC CC_REGNUM))])
3750 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3751 (clobber (reg:CC CC_REGNUM))])]
3753 int bitsize = INTVAL (operands[2]);
3754 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3755 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3757 operands[1] = adjust_address (operands[1], BLKmode, 0);
3758 set_mem_size (operands[1], size);
3759 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3760 operands[3] = GEN_INT (mask);
3764 ; insv instruction patterns
3767 (define_expand "insv"
3768 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3769 (match_operand 1 "const_int_operand" "")
3770 (match_operand 2 "const_int_operand" ""))
3771 (match_operand 3 "general_operand" ""))]
3774 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3780 ; The normal RTL expansion will never generate a zero_extract where
3781 ; the location operand isn't word mode. However, we do this in the
3782 ; back-end when generating atomic operations. See s390_two_part_insv.
3783 (define_insn "*insv<mode>_zEC12"
3784 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3785 (match_operand 1 "const_int_operand" "I") ; size
3786 (match_operand 2 "const_int_operand" "I")) ; pos
3787 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3789 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3790 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3791 [(set_attr "op_type" "RIE")])
3793 (define_insn "*insv<mode>_z10"
3794 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3795 (match_operand 1 "const_int_operand" "I") ; size
3796 (match_operand 2 "const_int_operand" "I")) ; pos
3797 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3798 (clobber (reg:CC CC_REGNUM))]
3800 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3801 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3802 [(set_attr "op_type" "RIE")
3803 (set_attr "z10prop" "z10_super_E1")])
3805 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3806 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3807 (define_insn "*insv<mode>_zEC12_noshift"
3808 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3809 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3810 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3811 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3812 (match_operand:GPR 4 "const_int_operand" ""))))]
3813 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3814 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3815 [(set_attr "op_type" "RIE")])
3817 (define_insn "*insv<mode>_z10_noshift"
3818 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3819 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3820 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3821 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3822 (match_operand:GPR 4 "const_int_operand" ""))))
3823 (clobber (reg:CC CC_REGNUM))]
3824 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3825 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3826 [(set_attr "op_type" "RIE")
3827 (set_attr "z10prop" "z10_super_E1")])
3829 ; Implement appending Y on the left of S bits of X
3830 ; x = (y << s) | (x & ((1 << s) - 1))
3831 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3832 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3833 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3834 (match_operand:GPR 2 "immediate_operand" ""))
3835 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3836 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3837 "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3838 "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3839 [(set_attr "op_type" "RIE")
3840 (set_attr "z10prop" "z10_super_E1")])
3842 (define_insn "*insv<mode>_z10_appendbitsleft"
3843 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3844 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3845 (match_operand:GPR 2 "immediate_operand" ""))
3846 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3847 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3848 (clobber (reg:CC CC_REGNUM))]
3849 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3850 "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3851 [(set_attr "op_type" "RIE")
3852 (set_attr "z10prop" "z10_super_E1")])
3854 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3855 ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3856 ; -> z = y >> d; z = risbg;
3859 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3860 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3861 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3862 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3863 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3864 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3866 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3868 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3869 (ashift:GPR (match_dup 3) (match_dup 4))))]
3871 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3872 if (rtx_equal_p (operands[0], operands[3]))
3874 if (!can_create_pseudo_p ())
3876 operands[6] = gen_reg_rtx (<MODE>mode);
3879 operands[6] = operands[0];
3884 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3885 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3886 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3887 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3888 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3889 (clobber (reg:CC CC_REGNUM))])]
3890 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3892 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3895 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3896 (ashift:GPR (match_dup 3) (match_dup 4))))
3897 (clobber (reg:CC CC_REGNUM))])]
3899 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3900 if (rtx_equal_p (operands[0], operands[3]))
3902 if (!can_create_pseudo_p ())
3904 operands[6] = gen_reg_rtx (<MODE>mode);
3907 operands[6] = operands[0];
3910 (define_insn "*r<noxa>sbg_<mode>_noshift"
3911 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3913 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3914 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3915 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3916 (clobber (reg:CC CC_REGNUM))]
3918 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3919 [(set_attr "op_type" "RIE")])
3921 (define_insn "*r<noxa>sbg_di_rotl"
3922 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3926 (match_operand:DI 1 "nonimmediate_operand" "d")
3927 (match_operand:DI 3 "const_int_operand" ""))
3928 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3929 (match_operand:DI 4 "nonimmediate_operand" "0")))
3930 (clobber (reg:CC CC_REGNUM))]
3932 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3933 [(set_attr "op_type" "RIE")])
3935 (define_insn "*r<noxa>sbg_<mode>_srl"
3936 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3940 (match_operand:GPR 1 "nonimmediate_operand" "d")
3941 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3942 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3943 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3944 (clobber (reg:CC CC_REGNUM))]
3946 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3947 INTVAL (operands[2]))"
3948 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3949 [(set_attr "op_type" "RIE")])
3951 (define_insn "*r<noxa>sbg_<mode>_sll"
3952 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3956 (match_operand:GPR 1 "nonimmediate_operand" "d")
3957 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3958 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3959 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3960 (clobber (reg:CC CC_REGNUM))]
3962 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3963 INTVAL (operands[2]))"
3964 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3965 [(set_attr "op_type" "RIE")])
3967 ;; These two are generated by combine for s.bf &= val.
3968 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3969 ;; shifts and ands, which results in some truly awful patterns
3970 ;; including subregs of operations. Rather unnecessisarily, IMO.
3973 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3974 ;; (const_int 24 [0x18])
3975 ;; (const_int 0 [0]))
3976 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3977 ;; (const_int 40 [0x28])) 4)
3978 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3980 ;; we should instead generate
3982 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3983 ;; (const_int 24 [0x18])
3984 ;; (const_int 0 [0]))
3985 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3986 ;; (const_int 40 [0x28]))
3987 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3989 ;; by noticing that we can push down the outer paradoxical subreg
3990 ;; into the operation.
3992 (define_insn "*insv_rnsbg_noshift"
3993 [(set (zero_extract:DI
3994 (match_operand:DI 0 "nonimmediate_operand" "+d")
3995 (match_operand 1 "const_int_operand" "")
3996 (match_operand 2 "const_int_operand" ""))
3999 (match_operand:DI 3 "nonimmediate_operand" "d")))
4000 (clobber (reg:CC CC_REGNUM))]
4002 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4003 "rnsbg\t%0,%3,%2,63,0"
4004 [(set_attr "op_type" "RIE")])
4006 (define_insn "*insv_rnsbg_srl"
4007 [(set (zero_extract:DI
4008 (match_operand:DI 0 "nonimmediate_operand" "+d")
4009 (match_operand 1 "const_int_operand" "")
4010 (match_operand 2 "const_int_operand" ""))
4014 (match_operand 3 "const_int_operand" ""))
4015 (match_operand:DI 4 "nonimmediate_operand" "d")))
4016 (clobber (reg:CC CC_REGNUM))]
4018 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4019 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4020 [(set_attr "op_type" "RIE")])
4022 (define_insn "*insv<mode>_mem_reg"
4023 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4024 (match_operand 1 "const_int_operand" "n,n")
4026 (match_operand:W 2 "register_operand" "d,d"))]
4027 "INTVAL (operands[1]) > 0
4028 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4029 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4031 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4033 operands[1] = GEN_INT ((1ul << size) - 1);
4034 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4035 : "stcmy\t%2,%1,%S0";
4037 [(set_attr "op_type" "RS,RSY")
4038 (set_attr "z10prop" "z10_super,z10_super")])
4040 (define_insn "*insvdi_mem_reghigh"
4041 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
4042 (match_operand 1 "const_int_operand" "n")
4044 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4047 && INTVAL (operands[1]) > 0
4048 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4049 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4051 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4053 operands[1] = GEN_INT ((1ul << size) - 1);
4054 return "stcmh\t%2,%1,%S0";
4056 [(set_attr "op_type" "RSY")
4057 (set_attr "z10prop" "z10_super")])
4059 (define_insn "*insvdi_reg_imm"
4060 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4062 (match_operand 1 "const_int_operand" "n"))
4063 (match_operand:DI 2 "const_int_operand" "n"))]
4065 && INTVAL (operands[1]) >= 0
4066 && INTVAL (operands[1]) < BITS_PER_WORD
4067 && INTVAL (operands[1]) % 16 == 0"
4069 switch (BITS_PER_WORD - INTVAL (operands[1]))
4071 case 64: return "iihh\t%0,%x2"; break;
4072 case 48: return "iihl\t%0,%x2"; break;
4073 case 32: return "iilh\t%0,%x2"; break;
4074 case 16: return "iill\t%0,%x2"; break;
4075 default: gcc_unreachable();
4078 [(set_attr "op_type" "RI")
4079 (set_attr "z10prop" "z10_super_E1")])
4081 ; Update the left-most 32 bit of a DI.
4082 (define_insn "*insv_h_di_reg_extimm"
4083 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4086 (match_operand:DI 1 "const_int_operand" "n"))]
4089 [(set_attr "op_type" "RIL")
4090 (set_attr "z10prop" "z10_fwd_E1")])
4092 ; Update the right-most 32 bit of a DI.
4093 (define_insn "*insv_l_di_reg_extimm"
4094 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4097 (match_operand:DI 1 "const_int_operand" "n"))]
4100 [(set_attr "op_type" "RIL")
4101 (set_attr "z10prop" "z10_fwd_A1")])
4104 ; extendsidi2 instruction pattern(s).
4107 (define_expand "extendsidi2"
4108 [(set (match_operand:DI 0 "register_operand" "")
4109 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4114 emit_clobber (operands[0]);
4115 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4116 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4117 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4122 (define_insn "*extendsidi2"
4123 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4124 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4130 [(set_attr "op_type" "RRE,RXY,RIL")
4131 (set_attr "type" "*,*,larl")
4132 (set_attr "cpu_facility" "*,*,z10")
4133 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4136 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4139 (define_expand "extend<HQI:mode><DSI:mode>2"
4140 [(set (match_operand:DSI 0 "register_operand" "")
4141 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4144 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4146 rtx tmp = gen_reg_rtx (SImode);
4147 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4148 emit_insn (gen_extendsidi2 (operands[0], tmp));
4151 else if (!TARGET_EXTIMM)
4153 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4155 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4156 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4157 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4163 ; extendhidi2 instruction pattern(s).
4166 (define_insn "*extendhidi2_extimm"
4167 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4168 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
4169 "TARGET_ZARCH && TARGET_EXTIMM"
4174 [(set_attr "op_type" "RRE,RXY,RIL")
4175 (set_attr "type" "*,*,larl")
4176 (set_attr "cpu_facility" "extimm,extimm,z10")
4177 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4179 (define_insn "*extendhidi2"
4180 [(set (match_operand:DI 0 "register_operand" "=d")
4181 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
4184 [(set_attr "op_type" "RXY")
4185 (set_attr "z10prop" "z10_super_E1")])
4188 ; extendhisi2 instruction pattern(s).
4191 (define_insn "*extendhisi2_extimm"
4192 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4193 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4200 [(set_attr "op_type" "RRE,RX,RXY,RIL")
4201 (set_attr "type" "*,*,*,larl")
4202 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4203 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4205 (define_insn "*extendhisi2"
4206 [(set (match_operand:SI 0 "register_operand" "=d,d")
4207 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4212 [(set_attr "op_type" "RX,RXY")
4213 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4216 ; extendqi(si|di)2 instruction pattern(s).
4219 ; lbr, lgbr, lb, lgb
4220 (define_insn "*extendqi<mode>2_extimm"
4221 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4222 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
4227 [(set_attr "op_type" "RRE,RXY")
4228 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4231 (define_insn "*extendqi<mode>2"
4232 [(set (match_operand:GPR 0 "register_operand" "=d")
4233 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
4234 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4236 [(set_attr "op_type" "RXY")
4237 (set_attr "z10prop" "z10_super_E1")])
4239 (define_insn_and_split "*extendqi<mode>2_short_displ"
4240 [(set (match_operand:GPR 0 "register_operand" "=d")
4241 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4242 (clobber (reg:CC CC_REGNUM))]
4243 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4245 "&& reload_completed"
4247 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4248 (clobber (reg:CC CC_REGNUM))])
4250 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4251 (clobber (reg:CC CC_REGNUM))])]
4253 operands[1] = adjust_address (operands[1], BLKmode, 0);
4254 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4255 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4259 ; zero_extendsidi2 instruction pattern(s).
4262 (define_expand "zero_extendsidi2"
4263 [(set (match_operand:DI 0 "register_operand" "")
4264 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4269 emit_clobber (operands[0]);
4270 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4271 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4276 (define_insn "*zero_extendsidi2"
4277 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4278 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4284 [(set_attr "op_type" "RRE,RXY,RIL")
4285 (set_attr "type" "*,*,larl")
4286 (set_attr "cpu_facility" "*,*,z10")
4287 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4290 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4293 (define_insn "*llgt_sidi"
4294 [(set (match_operand:DI 0 "register_operand" "=d")
4295 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4296 (const_int 2147483647)))]
4299 [(set_attr "op_type" "RXE")
4300 (set_attr "z10prop" "z10_super_E1")])
4302 (define_insn_and_split "*llgt_sidi_split"
4303 [(set (match_operand:DI 0 "register_operand" "=d")
4304 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4305 (const_int 2147483647)))
4306 (clobber (reg:CC CC_REGNUM))]
4309 "&& reload_completed"
4311 (and:DI (subreg:DI (match_dup 1) 0)
4312 (const_int 2147483647)))]
4315 (define_insn "*llgt_sisi"
4316 [(set (match_operand:SI 0 "register_operand" "=d,d")
4317 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
4318 (const_int 2147483647)))]
4323 [(set_attr "op_type" "RRE,RXE")
4324 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4326 (define_insn "*llgt_didi"
4327 [(set (match_operand:DI 0 "register_operand" "=d,d")
4328 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4329 (const_int 2147483647)))]
4334 [(set_attr "op_type" "RRE,RXE")
4335 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4338 [(set (match_operand:DSI 0 "register_operand" "")
4339 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4340 (const_int 2147483647)))
4341 (clobber (reg:CC CC_REGNUM))]
4342 "TARGET_ZARCH && reload_completed"
4344 (and:DSI (match_dup 1)
4345 (const_int 2147483647)))]
4349 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4352 (define_expand "zero_extend<mode>di2"
4353 [(set (match_operand:DI 0 "register_operand" "")
4354 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4359 rtx tmp = gen_reg_rtx (SImode);
4360 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4361 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4364 else if (!TARGET_EXTIMM)
4366 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4367 operands[1] = gen_lowpart (DImode, operands[1]);
4368 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4369 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4374 (define_expand "zero_extend<mode>si2"
4375 [(set (match_operand:SI 0 "register_operand" "")
4376 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4381 operands[1] = gen_lowpart (SImode, operands[1]);
4382 emit_insn (gen_andsi3 (operands[0], operands[1],
4383 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4389 (define_insn "*zero_extendhi<mode>2_z10"
4390 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4391 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4397 [(set_attr "op_type" "RXY,RRE,RIL")
4398 (set_attr "type" "*,*,larl")
4399 (set_attr "cpu_facility" "*,*,z10")
4400 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4402 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4403 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4404 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4405 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4410 [(set_attr "op_type" "RRE,RXY")
4411 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4414 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4415 [(set (match_operand:GPR 0 "register_operand" "=d")
4416 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4417 "TARGET_ZARCH && !TARGET_EXTIMM"
4419 [(set_attr "op_type" "RXY")
4420 (set_attr "z10prop" "z10_fwd_A3")])
4422 (define_insn_and_split "*zero_extendhisi2_31"
4423 [(set (match_operand:SI 0 "register_operand" "=&d")
4424 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4425 (clobber (reg:CC CC_REGNUM))]
4428 "&& reload_completed"
4429 [(set (match_dup 0) (const_int 0))
4431 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4432 (clobber (reg:CC CC_REGNUM))])]
4433 "operands[2] = gen_lowpart (HImode, operands[0]);")
4435 (define_insn_and_split "*zero_extendqisi2_31"
4436 [(set (match_operand:SI 0 "register_operand" "=&d")
4437 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4440 "&& reload_completed"
4441 [(set (match_dup 0) (const_int 0))
4442 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4443 "operands[2] = gen_lowpart (QImode, operands[0]);")
4446 ; zero_extendqihi2 instruction pattern(s).
4449 (define_expand "zero_extendqihi2"
4450 [(set (match_operand:HI 0 "register_operand" "")
4451 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4452 "TARGET_ZARCH && !TARGET_EXTIMM"
4454 operands[1] = gen_lowpart (HImode, operands[1]);
4455 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4459 (define_insn "*zero_extendqihi2_64"
4460 [(set (match_operand:HI 0 "register_operand" "=d")
4461 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4462 "TARGET_ZARCH && !TARGET_EXTIMM"
4464 [(set_attr "op_type" "RXY")
4465 (set_attr "z10prop" "z10_fwd_A3")])
4467 (define_insn_and_split "*zero_extendqihi2_31"
4468 [(set (match_operand:HI 0 "register_operand" "=&d")
4469 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4472 "&& reload_completed"
4473 [(set (match_dup 0) (const_int 0))
4474 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4475 "operands[2] = gen_lowpart (QImode, operands[0]);")
4478 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4481 (define_expand "fixuns_truncdddi2"
4483 [(set (match_operand:DI 0 "register_operand" "")
4484 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4485 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4486 (clobber (reg:CC CC_REGNUM))])]
4492 rtx_code_label *label1 = gen_label_rtx ();
4493 rtx_code_label *label2 = gen_label_rtx ();
4494 rtx temp = gen_reg_rtx (TDmode);
4495 REAL_VALUE_TYPE cmp, sub;
4497 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4498 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4500 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4501 solution is doing the check and the subtraction in TD mode and using a
4502 TD -> DI convert afterwards. */
4503 emit_insn (gen_extendddtd2 (temp, operands[1]));
4504 temp = force_reg (TDmode, temp);
4505 emit_cmp_and_jump_insns (temp,
4506 const_double_from_real_value (cmp, TDmode),
4507 LT, NULL_RTX, VOIDmode, 0, label1);
4508 emit_insn (gen_subtd3 (temp, temp,
4509 const_double_from_real_value (sub, TDmode)));
4510 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4513 emit_label (label1);
4514 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4515 emit_label (label2);
4520 (define_expand "fixuns_trunctddi2"
4522 [(set (match_operand:DI 0 "register_operand" "")
4523 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4524 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4525 (clobber (reg:CC CC_REGNUM))])]
4531 rtx_code_label *label1 = gen_label_rtx ();
4532 rtx_code_label *label2 = gen_label_rtx ();
4533 rtx temp = gen_reg_rtx (TDmode);
4534 REAL_VALUE_TYPE cmp, sub;
4536 operands[1] = force_reg (TDmode, operands[1]);
4537 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4538 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4540 emit_cmp_and_jump_insns (operands[1],
4541 const_double_from_real_value (cmp, TDmode),
4542 LT, NULL_RTX, VOIDmode, 0, label1);
4543 emit_insn (gen_subtd3 (temp, operands[1],
4544 const_double_from_real_value (sub, TDmode)));
4545 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4548 emit_label (label1);
4549 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4550 emit_label (label2);
4556 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4557 ; instruction pattern(s).
4560 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4562 [(set (match_operand:GPR 0 "register_operand" "")
4563 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4564 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4565 (clobber (reg:CC CC_REGNUM))])]
4570 rtx_code_label *label1 = gen_label_rtx ();
4571 rtx_code_label *label2 = gen_label_rtx ();
4572 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4573 REAL_VALUE_TYPE cmp, sub;
4575 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4576 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4577 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4579 emit_cmp_and_jump_insns (operands[1],
4580 const_double_from_real_value (cmp, <BFP:MODE>mode),
4581 LT, NULL_RTX, VOIDmode, 0, label1);
4582 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4583 const_double_from_real_value (sub, <BFP:MODE>mode)));
4584 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4588 emit_label (label1);
4589 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4590 operands[1], GEN_INT (5)));
4591 emit_label (label2);
4596 ; fixuns_trunc(td|dd)si2 expander
4597 (define_expand "fixuns_trunc<mode>si2"
4599 [(set (match_operand:SI 0 "register_operand" "")
4600 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4601 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4602 (clobber (reg:CC CC_REGNUM))])]
4603 "TARGET_Z196 && TARGET_HARD_DFP"
4606 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4608 (define_insn "*fixuns_truncdfdi2_z13"
4609 [(set (match_operand:DI 0 "register_operand" "=d,v")
4610 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4611 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4612 (clobber (reg:CC CC_REGNUM))]
4613 "TARGET_Z13 && TARGET_HARD_FLOAT"
4616 wclgdb\t%v0,%v1,0,%h2"
4617 [(set_attr "op_type" "RRF,VRR")
4618 (set_attr "type" "ftoi")])
4620 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4621 ; clfdtr, clfxtr, clgdtr, clgxtr
4622 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4623 [(set (match_operand:GPR 0 "register_operand" "=d")
4624 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4625 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4626 (clobber (reg:CC CC_REGNUM))]
4627 "TARGET_Z196 && TARGET_HARD_FLOAT
4628 && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4629 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4630 [(set_attr "op_type" "RRF")
4631 (set_attr "type" "ftoi")])
4633 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4634 [(set (match_operand:GPR 0 "register_operand" "")
4635 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4638 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4643 (define_insn "*fix_truncdfdi2_bfp_z13"
4644 [(set (match_operand:DI 0 "register_operand" "=d,v")
4645 (fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4646 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4647 (clobber (reg:CC CC_REGNUM))]
4648 "TARGET_Z13 && TARGET_HARD_FLOAT"
4651 wcgdb\t%v0,%v1,0,%h2"
4652 [(set_attr "op_type" "RRE,VRR")
4653 (set_attr "type" "ftoi")])
4655 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4656 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4657 [(set (match_operand:GPR 0 "register_operand" "=d")
4658 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4659 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4660 (clobber (reg:CC CC_REGNUM))]
4662 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4663 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4664 [(set_attr "op_type" "RRE")
4665 (set_attr "type" "ftoi")])
4667 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4669 [(set (match_operand:GPR 0 "register_operand" "=d")
4670 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4671 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4672 (clobber (reg:CC CC_REGNUM))])]
4673 "TARGET_HARD_FLOAT")
4675 ; fix_trunc(td|dd)di2 instruction pattern(s).
4678 (define_expand "fix_trunc<mode>di2"
4679 [(set (match_operand:DI 0 "register_operand" "")
4680 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4681 "TARGET_ZARCH && TARGET_HARD_DFP"
4683 operands[1] = force_reg (<MODE>mode, operands[1]);
4684 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4690 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4691 [(set (match_operand:DI 0 "register_operand" "=d")
4692 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4693 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4694 (clobber (reg:CC CC_REGNUM))]
4695 "TARGET_ZARCH && TARGET_HARD_DFP"
4696 "cg<DFP:xde>tr\t%0,%h2,%1"
4697 [(set_attr "op_type" "RRF")
4698 (set_attr "type" "ftoidfp")])
4702 ; fix_trunctf(si|di)2 instruction pattern(s).
4705 (define_expand "fix_trunctf<mode>2"
4706 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4707 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4708 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4709 (clobber (reg:CC CC_REGNUM))])]
4715 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4718 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4719 (define_insn "floatdi<mode>2"
4720 [(set (match_operand:FP 0 "register_operand" "=f,v")
4721 (float:FP (match_operand:DI 1 "register_operand" "d,v")))]
4722 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4726 [(set_attr "op_type" "RRE,VRR")
4727 (set_attr "type" "itof<mode>" )
4728 (set_attr "cpu_facility" "*,vec")
4729 (set_attr "enabled" "*,<DFDI>")])
4731 ; cxfbr, cdfbr, cefbr
4732 (define_insn "floatsi<mode>2"
4733 [(set (match_operand:BFP 0 "register_operand" "=f")
4734 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4737 [(set_attr "op_type" "RRE")
4738 (set_attr "type" "itof<mode>" )])
4741 (define_insn "floatsi<mode>2"
4742 [(set (match_operand:DFP 0 "register_operand" "=f")
4743 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4744 "TARGET_Z196 && TARGET_HARD_FLOAT"
4745 "c<xde>ftr\t%0,0,%1,0"
4746 [(set_attr "op_type" "RRE")
4747 (set_attr "type" "itof<mode>" )])
4750 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4753 (define_insn "*floatunsdidf2_z13"
4754 [(set (match_operand:DF 0 "register_operand" "=f,v")
4755 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
4756 "TARGET_Z13 && TARGET_HARD_FLOAT"
4759 wcdlgb\t%v0,%v1,0,0"
4760 [(set_attr "op_type" "RRE,VRR")
4761 (set_attr "type" "itofdf")])
4763 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4764 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4765 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4766 [(set (match_operand:FP 0 "register_operand" "=f")
4767 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4768 "TARGET_Z196 && TARGET_HARD_FLOAT
4769 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4770 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4771 [(set_attr "op_type" "RRE")
4772 (set_attr "type" "itof<FP:mode>")])
4774 (define_expand "floatuns<GPR:mode><FP:mode>2"
4775 [(set (match_operand:FP 0 "register_operand" "")
4776 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4777 "TARGET_Z196 && TARGET_HARD_FLOAT")
4780 ; truncdfsf2 instruction pattern(s).
4783 (define_insn "truncdfsf2"
4784 [(set (match_operand:SF 0 "register_operand" "=f,v")
4785 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))]
4789 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4790 ; According to BFP rounding mode
4791 [(set_attr "op_type" "RRE,VRR")
4792 (set_attr "type" "ftruncdf")
4793 (set_attr "cpu_facility" "*,vec")])
4796 ; trunctf(df|sf)2 instruction pattern(s).
4800 (define_insn "trunctf<mode>2"
4801 [(set (match_operand:DSF 0 "register_operand" "=f")
4802 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4803 (clobber (match_scratch:TF 2 "=f"))]
4805 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4806 [(set_attr "length" "6")
4807 (set_attr "type" "ftrunctf")])
4810 ; trunctddd2 and truncddsd2 instruction pattern(s).
4813 (define_insn "trunctddd2"
4814 [(set (match_operand:DD 0 "register_operand" "=f")
4815 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4816 (clobber (match_scratch:TD 2 "=f"))]
4818 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4819 [(set_attr "length" "6")
4820 (set_attr "type" "ftruncdd")])
4822 (define_insn "truncddsd2"
4823 [(set (match_operand:SD 0 "register_operand" "=f")
4824 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4827 [(set_attr "op_type" "RRF")
4828 (set_attr "type" "ftruncsd")])
4830 (define_expand "trunctdsd2"
4833 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4834 (clobber (match_scratch:TD 2 ""))])
4835 (set (match_operand:SD 0 "register_operand" "")
4836 (float_truncate:SD (match_dup 3)))]
4839 operands[3] = gen_reg_rtx (DDmode);
4843 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4846 (define_insn "*extendsfdf2_z13"
4847 [(set (match_operand:DF 0 "register_operand" "=f,f,v")
4848 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
4849 "TARGET_Z13 && TARGET_HARD_FLOAT"
4854 [(set_attr "op_type" "RRE,RXE,VRR")
4855 (set_attr "type" "fsimpdf, floaddf,fsimpdf")])
4857 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4858 (define_insn "*extend<DSF:mode><BFP:mode>2"
4859 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4860 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4862 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4863 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4865 l<BFP:xde><DSF:xde>br\t%0,%1
4866 l<BFP:xde><DSF:xde>b\t%0,%1"
4867 [(set_attr "op_type" "RRE,RXE")
4868 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4870 (define_expand "extend<DSF:mode><BFP:mode>2"
4871 [(set (match_operand:BFP 0 "register_operand" "")
4872 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4874 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4877 ; extendddtd2 and extendsddd2 instruction pattern(s).
4880 (define_insn "extendddtd2"
4881 [(set (match_operand:TD 0 "register_operand" "=f")
4882 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4885 [(set_attr "op_type" "RRF")
4886 (set_attr "type" "fsimptf")])
4888 (define_insn "extendsddd2"
4889 [(set (match_operand:DD 0 "register_operand" "=f")
4890 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4893 [(set_attr "op_type" "RRF")
4894 (set_attr "type" "fsimptf")])
4896 (define_expand "extendsdtd2"
4898 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4899 (set (match_operand:TD 0 "register_operand" "")
4900 (float_extend:TD (match_dup 2)))]
4903 operands[2] = gen_reg_rtx (DDmode);
4906 ; Binary Floating Point - load fp integer
4908 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4909 ; For all of them the inexact exceptions are suppressed.
4911 ; fiebra, fidbra, fixbra
4912 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4913 [(set (match_operand:BFP 0 "register_operand" "=f")
4914 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4917 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4918 [(set_attr "op_type" "RRF")
4919 (set_attr "type" "fsimp<BFP:mode>")])
4921 ; rint is supposed to raise an inexact exception so we can use the
4922 ; older instructions.
4924 ; fiebr, fidbr, fixbr
4925 (define_insn "rint<BFP:mode>2"
4926 [(set (match_operand:BFP 0 "register_operand" "=f")
4927 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4928 UNSPEC_FPINT_RINT))]
4930 "fi<BFP:xde>br\t%0,0,%1"
4931 [(set_attr "op_type" "RRF")
4932 (set_attr "type" "fsimp<BFP:mode>")])
4935 ; Decimal Floating Point - load fp integer
4938 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4939 [(set (match_operand:DFP 0 "register_operand" "=f")
4940 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4943 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4944 [(set_attr "op_type" "RRF")
4945 (set_attr "type" "fsimp<DFP:mode>")])
4948 (define_insn "rint<DFP:mode>2"
4949 [(set (match_operand:DFP 0 "register_operand" "=f")
4950 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4951 UNSPEC_FPINT_RINT))]
4953 "fi<DFP:xde>tr\t%0,0,%1,0"
4954 [(set_attr "op_type" "RRF")
4955 (set_attr "type" "fsimp<DFP:mode>")])
4958 ; Binary <-> Decimal floating point trunc patterns
4961 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4962 [(set (reg:DFP_ALL FPR0_REGNUM)
4963 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4964 (use (reg:SI GPR0_REGNUM))
4965 (clobber (reg:CC CC_REGNUM))
4966 (clobber (reg:SI GPR1_REGNUM))]
4970 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4971 [(set (reg:BFP FPR0_REGNUM)
4972 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4973 (use (reg:SI GPR0_REGNUM))
4974 (clobber (reg:CC CC_REGNUM))
4975 (clobber (reg:SI GPR1_REGNUM))]
4979 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4980 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4981 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4983 [(set (reg:DFP_ALL FPR0_REGNUM)
4984 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4985 (use (reg:SI GPR0_REGNUM))
4986 (clobber (reg:CC CC_REGNUM))
4987 (clobber (reg:SI GPR1_REGNUM))])
4988 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4989 (reg:DFP_ALL FPR0_REGNUM))]
4991 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4993 HOST_WIDE_INT flags;
4995 flags = (PFPO_CONVERT |
4996 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4997 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4999 operands[2] = GEN_INT (flags);
5002 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5003 [(set (reg:DFP_ALL FPR4_REGNUM)
5004 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5005 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5007 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5008 (use (reg:SI GPR0_REGNUM))
5009 (clobber (reg:CC CC_REGNUM))
5010 (clobber (reg:SI GPR1_REGNUM))])
5011 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5013 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5015 HOST_WIDE_INT flags;
5017 flags = (PFPO_CONVERT |
5018 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5019 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5021 operands[2] = GEN_INT (flags);
5025 ; Binary <-> Decimal floating point extend patterns
5028 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5029 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5030 (use (reg:SI GPR0_REGNUM))
5031 (clobber (reg:CC CC_REGNUM))
5032 (clobber (reg:SI GPR1_REGNUM))]
5036 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5037 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5038 (use (reg:SI GPR0_REGNUM))
5039 (clobber (reg:CC CC_REGNUM))
5040 (clobber (reg:SI GPR1_REGNUM))]
5044 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5045 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5046 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5048 [(set (reg:DFP_ALL FPR0_REGNUM)
5049 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5050 (use (reg:SI GPR0_REGNUM))
5051 (clobber (reg:CC CC_REGNUM))
5052 (clobber (reg:SI GPR1_REGNUM))])
5053 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5054 (reg:DFP_ALL FPR0_REGNUM))]
5056 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5058 HOST_WIDE_INT flags;
5060 flags = (PFPO_CONVERT |
5061 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5062 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5064 operands[2] = GEN_INT (flags);
5067 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5068 [(set (reg:DFP_ALL FPR4_REGNUM)
5069 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5070 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5072 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5073 (use (reg:SI GPR0_REGNUM))
5074 (clobber (reg:CC CC_REGNUM))
5075 (clobber (reg:SI GPR1_REGNUM))])
5076 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5078 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5080 HOST_WIDE_INT flags;
5082 flags = (PFPO_CONVERT |
5083 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5084 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5086 operands[2] = GEN_INT (flags);
5091 ;; ARITHMETIC OPERATIONS
5093 ; arithmetic operations set the ConditionCode,
5094 ; because of unpredictable Bits in Register for Halfword and Byte
5095 ; the ConditionCode can be set wrong in operations for Halfword and Byte
5098 ;;- Add instructions.
5102 ; addti3 instruction pattern(s).
5105 (define_expand "addti3"
5107 [(set (match_operand:TI 0 "register_operand" "")
5108 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5109 (match_operand:TI 2 "general_operand" "") ) )
5110 (clobber (reg:CC CC_REGNUM))])]
5113 /* For z13 we have vaq which doesn't set CC. */
5116 emit_insn (gen_rtx_SET (operands[0],
5117 gen_rtx_PLUS (TImode,
5118 copy_to_mode_reg (TImode, operands[1]),
5119 copy_to_mode_reg (TImode, operands[2]))));
5124 (define_insn_and_split "*addti3"
5125 [(set (match_operand:TI 0 "register_operand" "=&d")
5126 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5127 (match_operand:TI 2 "general_operand" "do") ) )
5128 (clobber (reg:CC CC_REGNUM))]
5131 "&& reload_completed"
5133 [(set (reg:CCL1 CC_REGNUM)
5134 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5136 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5138 [(set (match_dup 3) (plus:DI
5139 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5140 (match_dup 4)) (match_dup 5)))
5141 (clobber (reg:CC CC_REGNUM))])]
5142 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5143 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5144 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5145 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5146 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5147 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5148 [(set_attr "op_type" "*")
5149 (set_attr "cpu_facility" "*")])
5152 ; adddi3 instruction pattern(s).
5155 (define_expand "adddi3"
5157 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5158 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5159 (match_operand:DI 2 "general_operand" "")))
5160 (clobber (reg:CC CC_REGNUM))])]
5164 (define_insn "*adddi3_sign"
5165 [(set (match_operand:DI 0 "register_operand" "=d,d")
5166 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5167 (match_operand:DI 1 "register_operand" "0,0")))
5168 (clobber (reg:CC CC_REGNUM))]
5173 [(set_attr "op_type" "RRE,RXY")
5174 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5176 (define_insn "*adddi3_zero_cc"
5177 [(set (reg CC_REGNUM)
5178 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5179 (match_operand:DI 1 "register_operand" "0,0"))
5181 (set (match_operand:DI 0 "register_operand" "=d,d")
5182 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5183 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5187 [(set_attr "op_type" "RRE,RXY")
5188 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5190 (define_insn "*adddi3_zero_cconly"
5191 [(set (reg CC_REGNUM)
5192 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5193 (match_operand:DI 1 "register_operand" "0,0"))
5195 (clobber (match_scratch:DI 0 "=d,d"))]
5196 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5200 [(set_attr "op_type" "RRE,RXY")
5201 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5203 (define_insn "*adddi3_zero"
5204 [(set (match_operand:DI 0 "register_operand" "=d,d")
5205 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5206 (match_operand:DI 1 "register_operand" "0,0")))
5207 (clobber (reg:CC CC_REGNUM))]
5212 [(set_attr "op_type" "RRE,RXY")
5213 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5215 (define_insn_and_split "*adddi3_31z"
5216 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5217 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5218 (match_operand:DI 2 "general_operand" "do") ) )
5219 (clobber (reg:CC CC_REGNUM))]
5220 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5222 "&& reload_completed"
5224 [(set (reg:CCL1 CC_REGNUM)
5225 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5227 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5229 [(set (match_dup 3) (plus:SI
5230 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5231 (match_dup 4)) (match_dup 5)))
5232 (clobber (reg:CC CC_REGNUM))])]
5233 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5234 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5235 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5236 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5237 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5238 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5240 (define_insn_and_split "*adddi3_31"
5241 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5242 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5243 (match_operand:DI 2 "general_operand" "do") ) )
5244 (clobber (reg:CC CC_REGNUM))]
5247 "&& reload_completed"
5249 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5250 (clobber (reg:CC CC_REGNUM))])
5252 [(set (reg:CCL1 CC_REGNUM)
5253 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5255 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5257 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5259 (label_ref (match_dup 9))))
5261 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5262 (clobber (reg:CC CC_REGNUM))])
5264 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5265 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5266 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5267 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5268 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5269 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5270 operands[9] = gen_label_rtx ();")
5273 ; addsi3 instruction pattern(s).
5276 (define_expand "addsi3"
5278 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5279 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5280 (match_operand:SI 2 "general_operand" "")))
5281 (clobber (reg:CC CC_REGNUM))])]
5285 (define_insn "*addsi3_sign"
5286 [(set (match_operand:SI 0 "register_operand" "=d,d")
5287 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5288 (match_operand:SI 1 "register_operand" "0,0")))
5289 (clobber (reg:CC CC_REGNUM))]
5294 [(set_attr "op_type" "RX,RXY")
5295 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5298 ; add(di|si)3 instruction pattern(s).
5301 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5302 (define_insn "*add<mode>3"
5303 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
5304 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
5305 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
5306 (clobber (reg:CC CC_REGNUM))]
5318 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5319 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
5320 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5321 z10_super_E1,z10_super_E1,z10_super_E1")])
5323 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5324 (define_insn "*add<mode>3_carry1_cc"
5325 [(set (reg CC_REGNUM)
5326 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5327 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5329 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
5330 (plus:GPR (match_dup 1) (match_dup 2)))]
5331 "s390_match_ccmode (insn, CCL1mode)"
5337 al<g>hsik\t%0,%1,%h2
5341 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5342 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5343 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5344 z10_super_E1,z10_super_E1,z10_super_E1")])
5346 ; alr, al, aly, algr, alg, alrk, algrk
5347 (define_insn "*add<mode>3_carry1_cconly"
5348 [(set (reg CC_REGNUM)
5349 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5350 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5352 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5353 "s390_match_ccmode (insn, CCL1mode)"
5359 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5360 (set_attr "cpu_facility" "*,z196,*,*")
5361 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5363 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5364 (define_insn "*add<mode>3_carry2_cc"
5365 [(set (reg CC_REGNUM)
5366 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5367 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
5369 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
5370 (plus:GPR (match_dup 1) (match_dup 2)))]
5371 "s390_match_ccmode (insn, CCL1mode)"
5377 al<g>hsik\t%0,%1,%h2
5381 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5382 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5383 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5384 z10_super_E1,z10_super_E1,z10_super_E1")])
5386 ; alr, al, aly, algr, alg, alrk, algrk
5387 (define_insn "*add<mode>3_carry2_cconly"
5388 [(set (reg CC_REGNUM)
5389 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5390 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5392 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5393 "s390_match_ccmode (insn, CCL1mode)"
5399 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5400 (set_attr "cpu_facility" "*,z196,*,*")
5401 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5403 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5404 (define_insn "*add<mode>3_cc"
5405 [(set (reg CC_REGNUM)
5406 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5407 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
5409 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
5410 (plus:GPR (match_dup 1) (match_dup 2)))]
5411 "s390_match_ccmode (insn, CCLmode)"
5417 al<g>hsik\t%0,%1,%h2
5421 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5422 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5423 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5424 *,z10_super_E1,z10_super_E1,z10_super_E1")])
5426 ; alr, al, aly, algr, alg, alrk, algrk
5427 (define_insn "*add<mode>3_cconly"
5428 [(set (reg CC_REGNUM)
5429 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5430 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5432 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5433 "s390_match_ccmode (insn, CCLmode)"
5439 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5440 (set_attr "cpu_facility" "*,z196,*,*")
5441 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5443 ; alr, al, aly, algr, alg, alrk, algrk
5444 (define_insn "*add<mode>3_cconly2"
5445 [(set (reg CC_REGNUM)
5446 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5447 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5448 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5449 "s390_match_ccmode(insn, CCLmode)"
5455 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5456 (set_attr "cpu_facility" "*,z196,*,*")
5457 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5459 ; ahi, afi, aghi, agfi, asi, agsi
5460 (define_insn "*add<mode>3_imm_cc"
5461 [(set (reg CC_REGNUM)
5462 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5463 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
5465 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
5466 (plus:GPR (match_dup 1) (match_dup 2)))]
5467 "s390_match_ccmode (insn, CCAmode)
5468 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5469 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5470 /* Avoid INT32_MIN on 32 bit. */
5471 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5477 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5478 (set_attr "cpu_facility" "*,z196,extimm,z10")
5479 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5482 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5485 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5486 ; FIXME: wfadb does not clobber cc
5487 (define_insn "add<mode>3"
5488 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
5489 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
5490 (match_operand:FP 2 "general_operand" "f,f,R,v")))
5491 (clobber (reg:CC CC_REGNUM))]
5498 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
5499 (set_attr "type" "fsimp<mode>")
5500 (set_attr "cpu_facility" "*,*,*,vec")
5501 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5503 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5504 (define_insn "*add<mode>3_cc"
5505 [(set (reg CC_REGNUM)
5506 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5507 (match_operand:FP 2 "general_operand" "f,f,R"))
5508 (match_operand:FP 3 "const0_operand" "")))
5509 (set (match_operand:FP 0 "register_operand" "=f,f,f")
5510 (plus:FP (match_dup 1) (match_dup 2)))]
5511 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5516 [(set_attr "op_type" "RRF,RRE,RXE")
5517 (set_attr "type" "fsimp<mode>")
5518 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5520 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5521 (define_insn "*add<mode>3_cconly"
5522 [(set (reg CC_REGNUM)
5523 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5524 (match_operand:FP 2 "general_operand" "f,f,R"))
5525 (match_operand:FP 3 "const0_operand" "")))
5526 (clobber (match_scratch:FP 0 "=f,f,f"))]
5527 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5532 [(set_attr "op_type" "RRF,RRE,RXE")
5533 (set_attr "type" "fsimp<mode>")
5534 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5537 ; Pointer add instruction patterns
5540 ; This will match "*la_64"
5541 (define_expand "addptrdi3"
5542 [(set (match_operand:DI 0 "register_operand" "")
5543 (plus:DI (match_operand:DI 1 "register_operand" "")
5544 (match_operand:DI 2 "nonmemory_operand" "")))]
5547 if (GET_CODE (operands[2]) == CONST_INT)
5549 HOST_WIDE_INT c = INTVAL (operands[2]);
5551 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5552 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5554 operands[2] = force_const_mem (DImode, operands[2]);
5555 operands[2] = force_reg (DImode, operands[2]);
5557 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5558 operands[2] = force_reg (DImode, operands[2]);
5562 ; For 31 bit we have to prevent the generated pattern from matching
5563 ; normal ADDs since la only does a 31 bit add. This is supposed to
5564 ; match "force_la_31".
5565 (define_expand "addptrsi3"
5567 [(set (match_operand:SI 0 "register_operand" "")
5568 (plus:SI (match_operand:SI 1 "register_operand" "")
5569 (match_operand:SI 2 "nonmemory_operand" "")))
5570 (use (const_int 0))])]
5573 if (GET_CODE (operands[2]) == CONST_INT)
5575 HOST_WIDE_INT c = INTVAL (operands[2]);
5577 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5578 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5580 operands[2] = force_const_mem (SImode, operands[2]);
5581 operands[2] = force_reg (SImode, operands[2]);
5583 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5584 operands[2] = force_reg (SImode, operands[2]);
5589 ;;- Subtract instructions.
5593 ; subti3 instruction pattern(s).
5596 (define_expand "subti3"
5598 [(set (match_operand:TI 0 "register_operand" "")
5599 (minus:TI (match_operand:TI 1 "register_operand" "")
5600 (match_operand:TI 2 "general_operand" "") ) )
5601 (clobber (reg:CC CC_REGNUM))])]
5604 /* For z13 we have vaq which doesn't set CC. */
5607 emit_insn (gen_rtx_SET (operands[0],
5608 gen_rtx_MINUS (TImode,
5610 copy_to_mode_reg (TImode, operands[2]))));
5615 (define_insn_and_split "*subti3"
5616 [(set (match_operand:TI 0 "register_operand" "=&d")
5617 (minus:TI (match_operand:TI 1 "register_operand" "0")
5618 (match_operand:TI 2 "general_operand" "do") ) )
5619 (clobber (reg:CC CC_REGNUM))]
5622 "&& reload_completed"
5624 [(set (reg:CCL2 CC_REGNUM)
5625 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5627 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5629 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5630 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5631 (clobber (reg:CC CC_REGNUM))])]
5632 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5633 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5634 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5635 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5636 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5637 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5638 [(set_attr "op_type" "*")
5639 (set_attr "cpu_facility" "*")])
5642 ; subdi3 instruction pattern(s).
5645 (define_expand "subdi3"
5647 [(set (match_operand:DI 0 "register_operand" "")
5648 (minus:DI (match_operand:DI 1 "register_operand" "")
5649 (match_operand:DI 2 "general_operand" "")))
5650 (clobber (reg:CC CC_REGNUM))])]
5654 (define_insn "*subdi3_sign"
5655 [(set (match_operand:DI 0 "register_operand" "=d,d")
5656 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5657 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5658 (clobber (reg:CC CC_REGNUM))]
5663 [(set_attr "op_type" "RRE,RXY")
5664 (set_attr "z10prop" "z10_c,*")
5665 (set_attr "z196prop" "z196_cracked")])
5667 (define_insn "*subdi3_zero_cc"
5668 [(set (reg CC_REGNUM)
5669 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5670 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5672 (set (match_operand:DI 0 "register_operand" "=d,d")
5673 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5674 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5678 [(set_attr "op_type" "RRE,RXY")
5679 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5681 (define_insn "*subdi3_zero_cconly"
5682 [(set (reg CC_REGNUM)
5683 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5684 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5686 (clobber (match_scratch:DI 0 "=d,d"))]
5687 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5691 [(set_attr "op_type" "RRE,RXY")
5692 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5694 (define_insn "*subdi3_zero"
5695 [(set (match_operand:DI 0 "register_operand" "=d,d")
5696 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5697 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5698 (clobber (reg:CC CC_REGNUM))]
5703 [(set_attr "op_type" "RRE,RXY")
5704 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5706 (define_insn_and_split "*subdi3_31z"
5707 [(set (match_operand:DI 0 "register_operand" "=&d")
5708 (minus:DI (match_operand:DI 1 "register_operand" "0")
5709 (match_operand:DI 2 "general_operand" "do") ) )
5710 (clobber (reg:CC CC_REGNUM))]
5711 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5713 "&& reload_completed"
5715 [(set (reg:CCL2 CC_REGNUM)
5716 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5718 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5720 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5721 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5722 (clobber (reg:CC CC_REGNUM))])]
5723 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5724 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5725 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5726 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5727 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5728 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5730 (define_insn_and_split "*subdi3_31"
5731 [(set (match_operand:DI 0 "register_operand" "=&d")
5732 (minus:DI (match_operand:DI 1 "register_operand" "0")
5733 (match_operand:DI 2 "general_operand" "do") ) )
5734 (clobber (reg:CC CC_REGNUM))]
5737 "&& reload_completed"
5739 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5740 (clobber (reg:CC CC_REGNUM))])
5742 [(set (reg:CCL2 CC_REGNUM)
5743 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5745 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5747 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5749 (label_ref (match_dup 9))))
5751 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5752 (clobber (reg:CC CC_REGNUM))])
5754 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5755 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5756 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5757 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5758 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5759 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5760 operands[9] = gen_label_rtx ();")
5763 ; subsi3 instruction pattern(s).
5766 (define_expand "subsi3"
5768 [(set (match_operand:SI 0 "register_operand" "")
5769 (minus:SI (match_operand:SI 1 "register_operand" "")
5770 (match_operand:SI 2 "general_operand" "")))
5771 (clobber (reg:CC CC_REGNUM))])]
5775 (define_insn "*subsi3_sign"
5776 [(set (match_operand:SI 0 "register_operand" "=d,d")
5777 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5778 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5779 (clobber (reg:CC CC_REGNUM))]
5784 [(set_attr "op_type" "RX,RXY")
5785 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5788 ; sub(di|si)3 instruction pattern(s).
5791 ; sr, s, sy, sgr, sg, srk, sgrk
5792 (define_insn "*sub<mode>3"
5793 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5794 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5795 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5796 (clobber (reg:CC CC_REGNUM))]
5803 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5804 (set_attr "cpu_facility" "*,z196,*,*")
5805 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5807 ; slr, sl, sly, slgr, slg, slrk, slgrk
5808 (define_insn "*sub<mode>3_borrow_cc"
5809 [(set (reg CC_REGNUM)
5810 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5811 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5813 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5814 (minus:GPR (match_dup 1) (match_dup 2)))]
5815 "s390_match_ccmode (insn, CCL2mode)"
5821 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5822 (set_attr "cpu_facility" "*,z196,*,*")
5823 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5825 ; slr, sl, sly, slgr, slg, slrk, slgrk
5826 (define_insn "*sub<mode>3_borrow_cconly"
5827 [(set (reg CC_REGNUM)
5828 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5829 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5831 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5832 "s390_match_ccmode (insn, CCL2mode)"
5838 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5839 (set_attr "cpu_facility" "*,z196,*,*")
5840 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5842 ; slr, sl, sly, slgr, slg, slrk, slgrk
5843 (define_insn "*sub<mode>3_cc"
5844 [(set (reg CC_REGNUM)
5845 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5846 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5848 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5849 (minus:GPR (match_dup 1) (match_dup 2)))]
5850 "s390_match_ccmode (insn, CCLmode)"
5856 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5857 (set_attr "cpu_facility" "*,z196,*,*")
5858 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5860 ; slr, sl, sly, slgr, slg, slrk, slgrk
5861 (define_insn "*sub<mode>3_cc2"
5862 [(set (reg CC_REGNUM)
5863 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5864 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5865 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5866 (minus:GPR (match_dup 1) (match_dup 2)))]
5867 "s390_match_ccmode (insn, CCL3mode)"
5873 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5874 (set_attr "cpu_facility" "*,z196,*,*")
5875 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5877 ; slr, sl, sly, slgr, slg, slrk, slgrk
5878 (define_insn "*sub<mode>3_cconly"
5879 [(set (reg CC_REGNUM)
5880 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5881 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5883 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5884 "s390_match_ccmode (insn, CCLmode)"
5890 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5891 (set_attr "cpu_facility" "*,z196,*,*")
5892 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5895 ; slr, sl, sly, slgr, slg, slrk, slgrk
5896 (define_insn "*sub<mode>3_cconly2"
5897 [(set (reg CC_REGNUM)
5898 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5899 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5900 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5901 "s390_match_ccmode (insn, CCL3mode)"
5907 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5908 (set_attr "cpu_facility" "*,z196,*,*")
5909 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5913 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5916 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5917 (define_insn "sub<mode>3"
5918 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
5919 (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
5920 (match_operand:FP 2 "general_operand" "f,f,R,v")))
5921 (clobber (reg:CC CC_REGNUM))]
5928 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
5929 (set_attr "type" "fsimp<mode>")
5930 (set_attr "cpu_facility" "*,*,*,vec")
5931 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5933 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5934 (define_insn "*sub<mode>3_cc"
5935 [(set (reg CC_REGNUM)
5936 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
5937 (match_operand:FP 2 "general_operand" "f,f,R"))
5938 (match_operand:FP 3 "const0_operand" "")))
5939 (set (match_operand:FP 0 "register_operand" "=f,f,f")
5940 (minus:FP (match_dup 1) (match_dup 2)))]
5941 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5946 [(set_attr "op_type" "RRF,RRE,RXE")
5947 (set_attr "type" "fsimp<mode>")
5948 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5950 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5951 (define_insn "*sub<mode>3_cconly"
5952 [(set (reg CC_REGNUM)
5953 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
5954 (match_operand:FP 2 "general_operand" "f,f,R"))
5955 (match_operand:FP 3 "const0_operand" "")))
5956 (clobber (match_scratch:FP 0 "=f,f,f"))]
5957 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5962 [(set_attr "op_type" "RRF,RRE,RXE")
5963 (set_attr "type" "fsimp<mode>")
5964 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5968 ;;- Conditional add/subtract instructions.
5972 ; add(di|si)cc instruction pattern(s).
5975 ; the following 4 patterns are used when the result of an add with
5976 ; carry is checked for an overflow condition
5978 ; op1 + op2 + c < op1
5980 ; alcr, alc, alcgr, alcg
5981 (define_insn "*add<mode>3_alc_carry1_cc"
5982 [(set (reg CC_REGNUM)
5984 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5985 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5986 (match_operand:GPR 2 "general_operand" "d,RT"))
5988 (set (match_operand:GPR 0 "register_operand" "=d,d")
5989 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5990 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5994 [(set_attr "op_type" "RRE,RXY")
5995 (set_attr "z196prop" "z196_alone,z196_alone")])
5997 ; alcr, alc, alcgr, alcg
5998 (define_insn "*add<mode>3_alc_carry1_cconly"
5999 [(set (reg CC_REGNUM)
6001 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6002 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6003 (match_operand:GPR 2 "general_operand" "d,RT"))
6005 (clobber (match_scratch:GPR 0 "=d,d"))]
6006 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6010 [(set_attr "op_type" "RRE,RXY")
6011 (set_attr "z196prop" "z196_alone,z196_alone")])
6013 ; op1 + op2 + c < op2
6015 ; alcr, alc, alcgr, alcg
6016 (define_insn "*add<mode>3_alc_carry2_cc"
6017 [(set (reg CC_REGNUM)
6019 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6020 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6021 (match_operand:GPR 2 "general_operand" "d,RT"))
6023 (set (match_operand:GPR 0 "register_operand" "=d,d")
6024 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6025 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6029 [(set_attr "op_type" "RRE,RXY")])
6031 ; alcr, alc, alcgr, alcg
6032 (define_insn "*add<mode>3_alc_carry2_cconly"
6033 [(set (reg CC_REGNUM)
6035 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6036 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6037 (match_operand:GPR 2 "general_operand" "d,RT"))
6039 (clobber (match_scratch:GPR 0 "=d,d"))]
6040 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6044 [(set_attr "op_type" "RRE,RXY")])
6046 ; alcr, alc, alcgr, alcg
6047 (define_insn "*add<mode>3_alc_cc"
6048 [(set (reg CC_REGNUM)
6050 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6051 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6052 (match_operand:GPR 2 "general_operand" "d,RT"))
6054 (set (match_operand:GPR 0 "register_operand" "=d,d")
6055 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6056 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6060 [(set_attr "op_type" "RRE,RXY")])
6062 ; alcr, alc, alcgr, alcg
6063 (define_insn "*add<mode>3_alc"
6064 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6065 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6066 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6067 (match_operand:GPR 2 "general_operand" "d,RT")))
6068 (clobber (reg:CC CC_REGNUM))]
6073 [(set_attr "op_type" "RRE,RXY")])
6075 ; slbr, slb, slbgr, slbg
6076 (define_insn "*sub<mode>3_slb_cc"
6077 [(set (reg CC_REGNUM)
6079 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6080 (match_operand:GPR 2 "general_operand" "d,RT"))
6081 (match_operand:GPR 3 "s390_slb_comparison" ""))
6083 (set (match_operand:GPR 0 "register_operand" "=d,d")
6084 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6085 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6089 [(set_attr "op_type" "RRE,RXY")
6090 (set_attr "z10prop" "z10_c,*")])
6092 ; slbr, slb, slbgr, slbg
6093 (define_insn "*sub<mode>3_slb"
6094 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6095 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6096 (match_operand:GPR 2 "general_operand" "d,RT"))
6097 (match_operand:GPR 3 "s390_slb_comparison" "")))
6098 (clobber (reg:CC CC_REGNUM))]
6103 [(set_attr "op_type" "RRE,RXY")
6104 (set_attr "z10prop" "z10_c,*")])
6106 (define_expand "add<mode>cc"
6107 [(match_operand:GPR 0 "register_operand" "")
6108 (match_operand 1 "comparison_operator" "")
6109 (match_operand:GPR 2 "register_operand" "")
6110 (match_operand:GPR 3 "const_int_operand" "")]
6112 "if (!s390_expand_addcc (GET_CODE (operands[1]),
6113 XEXP (operands[1], 0), XEXP (operands[1], 1),
6114 operands[0], operands[2],
6115 operands[3])) FAIL; DONE;")
6118 ; scond instruction pattern(s).
6121 (define_insn_and_split "*scond<mode>"
6122 [(set (match_operand:GPR 0 "register_operand" "=&d")
6123 (match_operand:GPR 1 "s390_alc_comparison" ""))
6124 (clobber (reg:CC CC_REGNUM))]
6127 "&& reload_completed"
6128 [(set (match_dup 0) (const_int 0))
6130 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6132 (clobber (reg:CC CC_REGNUM))])]
6135 (define_insn_and_split "*scond<mode>_neg"
6136 [(set (match_operand:GPR 0 "register_operand" "=&d")
6137 (match_operand:GPR 1 "s390_slb_comparison" ""))
6138 (clobber (reg:CC CC_REGNUM))]
6141 "&& reload_completed"
6142 [(set (match_dup 0) (const_int 0))
6144 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6146 (clobber (reg:CC CC_REGNUM))])
6148 [(set (match_dup 0) (neg:GPR (match_dup 0)))
6149 (clobber (reg:CC CC_REGNUM))])]
6153 (define_expand "cstore<mode>4"
6154 [(set (match_operand:SI 0 "register_operand" "")
6155 (match_operator:SI 1 "s390_scond_operator"
6156 [(match_operand:GPR 2 "register_operand" "")
6157 (match_operand:GPR 3 "general_operand" "")]))]
6159 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6160 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6162 (define_expand "cstorecc4"
6164 [(set (match_operand:SI 0 "register_operand" "")
6165 (match_operator:SI 1 "s390_eqne_operator"
6166 [(match_operand:CCZ1 2 "register_operand")
6167 (match_operand 3 "const0_operand")]))
6168 (clobber (reg:CC CC_REGNUM))])]
6170 "emit_insn (gen_sne (operands[0], operands[2]));
6171 if (GET_CODE (operands[1]) == EQ)
6172 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6175 (define_insn_and_split "sne"
6176 [(set (match_operand:SI 0 "register_operand" "=d")
6177 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6179 (clobber (reg:CC CC_REGNUM))]
6184 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6185 (clobber (reg:CC CC_REGNUM))])])
6189 ;; - Conditional move instructions (introduced with z196)
6192 (define_expand "mov<mode>cc"
6193 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6194 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6195 (match_operand:GPR 2 "nonimmediate_operand" "")
6196 (match_operand:GPR 3 "nonimmediate_operand" "")))]
6199 /* Emit the comparison insn in case we do not already have a comparison result. */
6200 if (!s390_comparison (operands[1], VOIDmode))
6201 operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6202 XEXP (operands[1], 0),
6203 XEXP (operands[1], 1));
6206 ; locr, loc, stoc, locgr, locg, stocg
6207 (define_insn_and_split "*mov<mode>cc"
6208 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
6210 (match_operator 1 "s390_comparison"
6211 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
6212 (match_operand 5 "const_int_operand" "")])
6213 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
6214 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
6224 "&& reload_completed
6225 && MEM_P (operands[3]) && MEM_P (operands[4])"
6228 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6233 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6237 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
6240 ;;- Multiply instructions.
6244 ; muldi3 instruction pattern(s).
6247 (define_insn "*muldi3_sign"
6248 [(set (match_operand:DI 0 "register_operand" "=d,d")
6249 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
6250 (match_operand:DI 1 "register_operand" "0,0")))]
6255 [(set_attr "op_type" "RRE,RXY")
6256 (set_attr "type" "imuldi")])
6258 (define_insn "muldi3"
6259 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6260 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6261 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
6268 [(set_attr "op_type" "RRE,RI,RXY,RIL")
6269 (set_attr "type" "imuldi")
6270 (set_attr "cpu_facility" "*,*,*,z10")])
6273 ; mulsi3 instruction pattern(s).
6276 (define_insn "*mulsi3_sign"
6277 [(set (match_operand:SI 0 "register_operand" "=d,d")
6278 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6279 (match_operand:SI 1 "register_operand" "0,0")))]
6284 [(set_attr "op_type" "RX,RXY")
6285 (set_attr "type" "imulhi")
6286 (set_attr "cpu_facility" "*,z10")])
6288 (define_insn "mulsi3"
6289 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6290 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6291 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6299 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
6300 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
6301 (set_attr "cpu_facility" "*,*,*,*,z10")])
6304 ; mulsidi3 instruction pattern(s).
6307 (define_insn "mulsidi3"
6308 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6309 (mult:DI (sign_extend:DI
6310 (match_operand:SI 1 "register_operand" "%0,0,0"))
6312 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6318 [(set_attr "op_type" "RR,RX,RXY")
6319 (set_attr "type" "imulsi")
6320 (set_attr "cpu_facility" "*,*,z10")])
6323 ; umul instruction pattern(s).
6326 ; mlr, ml, mlgr, mlg
6327 (define_insn "umul<dwh><mode>3"
6328 [(set (match_operand:DW 0 "register_operand" "=d, d")
6329 (mult:DW (zero_extend:DW
6330 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
6332 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
6337 [(set_attr "op_type" "RRE,RXY")
6338 (set_attr "type" "imul<dwh>")])
6341 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6344 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6345 (define_insn "mul<mode>3"
6346 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6347 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
6348 (match_operand:FP 2 "general_operand" "f,f,R,v")))]
6355 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6356 (set_attr "type" "fmul<mode>")
6357 (set_attr "cpu_facility" "*,*,*,vec")
6358 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6360 ; madbr, maebr, maxb, madb, maeb
6361 (define_insn "fma<mode>4"
6362 [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
6363 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6364 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
6365 (match_operand:DSF 3 "register_operand" "0,0,v")))]
6370 wfmadb\t%v0,%v1,%v2,%v3"
6371 [(set_attr "op_type" "RRE,RXE,VRR")
6372 (set_attr "type" "fmadd<mode>")
6373 (set_attr "cpu_facility" "*,*,vec")
6374 (set_attr "enabled" "*,*,<DFDI>")])
6376 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6377 (define_insn "fms<mode>4"
6378 [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
6379 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6380 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
6381 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))]
6386 wfmsdb\t%v0,%v1,%v2,%v3"
6387 [(set_attr "op_type" "RRE,RXE,VRR")
6388 (set_attr "type" "fmadd<mode>")
6389 (set_attr "cpu_facility" "*,*,vec")
6390 (set_attr "enabled" "*,*,<DFDI>")])
6393 ;;- Divide and modulo instructions.
6397 ; divmoddi4 instruction pattern(s).
6400 (define_expand "divmoddi4"
6401 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6402 (div:DI (match_operand:DI 1 "register_operand" "")
6403 (match_operand:DI 2 "general_operand" "")))
6404 (set (match_operand:DI 3 "general_operand" "")
6405 (mod:DI (match_dup 1) (match_dup 2)))])
6406 (clobber (match_dup 4))]
6409 rtx insn, div_equal, mod_equal;
6411 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6412 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6414 operands[4] = gen_reg_rtx(TImode);
6415 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6417 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6418 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6420 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6421 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6426 (define_insn "divmodtidi3"
6427 [(set (match_operand:TI 0 "register_operand" "=d,d")
6431 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6432 (match_operand:DI 2 "general_operand" "d,RT")))
6434 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6439 [(set_attr "op_type" "RRE,RXY")
6440 (set_attr "type" "idiv")])
6442 (define_insn "divmodtisi3"
6443 [(set (match_operand:TI 0 "register_operand" "=d,d")
6447 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6449 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
6452 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6457 [(set_attr "op_type" "RRE,RXY")
6458 (set_attr "type" "idiv")])
6461 ; udivmoddi4 instruction pattern(s).
6464 (define_expand "udivmoddi4"
6465 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6466 (udiv:DI (match_operand:DI 1 "general_operand" "")
6467 (match_operand:DI 2 "nonimmediate_operand" "")))
6468 (set (match_operand:DI 3 "general_operand" "")
6469 (umod:DI (match_dup 1) (match_dup 2)))])
6470 (clobber (match_dup 4))]
6473 rtx insn, div_equal, mod_equal, equal;
6475 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6476 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6477 equal = gen_rtx_IOR (TImode,
6478 gen_rtx_ASHIFT (TImode,
6479 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6481 gen_rtx_ZERO_EXTEND (TImode, div_equal));
6483 operands[4] = gen_reg_rtx(TImode);
6484 emit_clobber (operands[4]);
6485 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6486 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6488 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6489 set_unique_reg_note (insn, REG_EQUAL, equal);
6491 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6492 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6494 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6495 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6500 (define_insn "udivmodtidi3"
6501 [(set (match_operand:TI 0 "register_operand" "=d,d")
6506 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6508 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6512 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6517 [(set_attr "op_type" "RRE,RXY")
6518 (set_attr "type" "idiv")])
6521 ; divmodsi4 instruction pattern(s).
6524 (define_expand "divmodsi4"
6525 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6526 (div:SI (match_operand:SI 1 "general_operand" "")
6527 (match_operand:SI 2 "nonimmediate_operand" "")))
6528 (set (match_operand:SI 3 "general_operand" "")
6529 (mod:SI (match_dup 1) (match_dup 2)))])
6530 (clobber (match_dup 4))]
6533 rtx insn, div_equal, mod_equal, equal;
6535 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6536 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6537 equal = gen_rtx_IOR (DImode,
6538 gen_rtx_ASHIFT (DImode,
6539 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6541 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6543 operands[4] = gen_reg_rtx(DImode);
6544 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6546 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6547 set_unique_reg_note (insn, REG_EQUAL, equal);
6549 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6550 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6552 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6553 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6558 (define_insn "divmoddisi3"
6559 [(set (match_operand:DI 0 "register_operand" "=d,d")
6564 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6566 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6570 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6575 [(set_attr "op_type" "RR,RX")
6576 (set_attr "type" "idiv")])
6579 ; udivsi3 and umodsi3 instruction pattern(s).
6582 (define_expand "udivmodsi4"
6583 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6584 (udiv:SI (match_operand:SI 1 "general_operand" "")
6585 (match_operand:SI 2 "nonimmediate_operand" "")))
6586 (set (match_operand:SI 3 "general_operand" "")
6587 (umod:SI (match_dup 1) (match_dup 2)))])
6588 (clobber (match_dup 4))]
6589 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6591 rtx insn, div_equal, mod_equal, equal;
6593 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6594 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6595 equal = gen_rtx_IOR (DImode,
6596 gen_rtx_ASHIFT (DImode,
6597 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6599 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6601 operands[4] = gen_reg_rtx(DImode);
6602 emit_clobber (operands[4]);
6603 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6604 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6606 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6607 set_unique_reg_note (insn, REG_EQUAL, equal);
6609 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6610 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6612 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6613 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6618 (define_insn "udivmoddisi3"
6619 [(set (match_operand:DI 0 "register_operand" "=d,d")
6624 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6626 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6630 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6631 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6635 [(set_attr "op_type" "RRE,RXY")
6636 (set_attr "type" "idiv")])
6638 (define_expand "udivsi3"
6639 [(set (match_operand:SI 0 "register_operand" "=d")
6640 (udiv:SI (match_operand:SI 1 "general_operand" "")
6641 (match_operand:SI 2 "general_operand" "")))
6642 (clobber (match_dup 3))]
6643 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6645 rtx insn, udiv_equal, umod_equal, equal;
6647 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6648 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6649 equal = gen_rtx_IOR (DImode,
6650 gen_rtx_ASHIFT (DImode,
6651 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6653 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6655 operands[3] = gen_reg_rtx (DImode);
6657 if (CONSTANT_P (operands[2]))
6659 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6661 rtx_code_label *label1 = gen_label_rtx ();
6663 operands[1] = make_safe_from (operands[1], operands[0]);
6664 emit_move_insn (operands[0], const0_rtx);
6665 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6667 emit_move_insn (operands[0], const1_rtx);
6668 emit_label (label1);
6672 operands[2] = force_reg (SImode, operands[2]);
6673 operands[2] = make_safe_from (operands[2], operands[0]);
6675 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6676 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6678 set_unique_reg_note (insn, REG_EQUAL, equal);
6680 insn = emit_move_insn (operands[0],
6681 gen_lowpart (SImode, operands[3]));
6682 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6687 rtx_code_label *label1 = gen_label_rtx ();
6688 rtx_code_label *label2 = gen_label_rtx ();
6689 rtx_code_label *label3 = gen_label_rtx ();
6691 operands[1] = force_reg (SImode, operands[1]);
6692 operands[1] = make_safe_from (operands[1], operands[0]);
6693 operands[2] = force_reg (SImode, operands[2]);
6694 operands[2] = make_safe_from (operands[2], operands[0]);
6696 emit_move_insn (operands[0], const0_rtx);
6697 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6699 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6701 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6703 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6704 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6706 set_unique_reg_note (insn, REG_EQUAL, equal);
6708 insn = emit_move_insn (operands[0],
6709 gen_lowpart (SImode, operands[3]));
6710 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6713 emit_label (label1);
6714 emit_move_insn (operands[0], operands[1]);
6716 emit_label (label2);
6717 emit_move_insn (operands[0], const1_rtx);
6718 emit_label (label3);
6720 emit_move_insn (operands[0], operands[0]);
6724 (define_expand "umodsi3"
6725 [(set (match_operand:SI 0 "register_operand" "=d")
6726 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6727 (match_operand:SI 2 "nonimmediate_operand" "")))
6728 (clobber (match_dup 3))]
6729 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6731 rtx insn, udiv_equal, umod_equal, equal;
6733 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6734 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6735 equal = gen_rtx_IOR (DImode,
6736 gen_rtx_ASHIFT (DImode,
6737 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6739 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6741 operands[3] = gen_reg_rtx (DImode);
6743 if (CONSTANT_P (operands[2]))
6745 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6747 rtx_code_label *label1 = gen_label_rtx ();
6749 operands[1] = make_safe_from (operands[1], operands[0]);
6750 emit_move_insn (operands[0], operands[1]);
6751 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6753 emit_insn (gen_abssi2 (operands[0], operands[2]));
6754 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6755 emit_label (label1);
6759 operands[2] = force_reg (SImode, operands[2]);
6760 operands[2] = make_safe_from (operands[2], operands[0]);
6762 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6763 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6765 set_unique_reg_note (insn, REG_EQUAL, equal);
6767 insn = emit_move_insn (operands[0],
6768 gen_highpart (SImode, operands[3]));
6769 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6774 rtx_code_label *label1 = gen_label_rtx ();
6775 rtx_code_label *label2 = gen_label_rtx ();
6776 rtx_code_label *label3 = gen_label_rtx ();
6778 operands[1] = force_reg (SImode, operands[1]);
6779 operands[1] = make_safe_from (operands[1], operands[0]);
6780 operands[2] = force_reg (SImode, operands[2]);
6781 operands[2] = make_safe_from (operands[2], operands[0]);
6783 emit_move_insn(operands[0], operands[1]);
6784 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6786 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6788 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6790 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6791 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6793 set_unique_reg_note (insn, REG_EQUAL, equal);
6795 insn = emit_move_insn (operands[0],
6796 gen_highpart (SImode, operands[3]));
6797 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6800 emit_label (label1);
6801 emit_move_insn (operands[0], const0_rtx);
6803 emit_label (label2);
6804 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6805 emit_label (label3);
6811 ; div(df|sf)3 instruction pattern(s).
6814 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6815 (define_insn "div<mode>3"
6816 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6817 (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
6818 (match_operand:FP 2 "general_operand" "f,f,R,v")))]
6825 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6826 (set_attr "type" "fdiv<mode>")
6827 (set_attr "cpu_facility" "*,*,*,vec")
6828 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6832 ;;- And instructions.
6835 (define_expand "and<mode>3"
6836 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6837 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6838 (match_operand:INT 2 "general_operand" "")))
6839 (clobber (reg:CC CC_REGNUM))]
6841 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6844 ; anddi3 instruction pattern(s).
6847 (define_insn "*anddi3_cc"
6848 [(set (reg CC_REGNUM)
6850 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6851 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6853 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6854 (and:DI (match_dup 1) (match_dup 2)))]
6855 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6860 risbg\t%0,%1,%s2,128+%e2,0"
6861 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6862 (set_attr "cpu_facility" "*,z196,*,z10")
6863 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6865 (define_insn "*anddi3_cconly"
6866 [(set (reg CC_REGNUM)
6868 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6869 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6871 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6873 && s390_match_ccmode(insn, CCTmode)
6874 /* Do not steal TM patterns. */
6875 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6880 risbg\t%0,%1,%s2,128+%e2,0"
6881 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6882 (set_attr "cpu_facility" "*,z196,*,z10")
6883 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6885 (define_insn "*anddi3"
6886 [(set (match_operand:DI 0 "nonimmediate_operand"
6887 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6889 (match_operand:DI 1 "nonimmediate_operand"
6890 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6891 (match_operand:DI 2 "general_operand"
6892 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6893 (clobber (reg:CC CC_REGNUM))]
6894 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6907 risbg\t%0,%1,%s2,128+%e2,0
6910 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6911 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6912 (set_attr "z10prop" "*,
6928 [(set (match_operand:DI 0 "s_operand" "")
6929 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6930 (clobber (reg:CC CC_REGNUM))]
6933 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6934 (clobber (reg:CC CC_REGNUM))])]
6935 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6937 ;; These two are what combine generates for (ashift (zero_extract)).
6938 (define_insn "*extzv_<mode>_srl"
6939 [(set (match_operand:GPR 0 "register_operand" "=d")
6940 (and:GPR (lshiftrt:GPR
6941 (match_operand:GPR 1 "register_operand" "d")
6942 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6943 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6944 (clobber (reg:CC CC_REGNUM))]
6946 /* Note that even for the SImode pattern, the rotate is always DImode. */
6947 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6948 INTVAL (operands[3]))"
6949 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6950 [(set_attr "op_type" "RIE")
6951 (set_attr "z10prop" "z10_super_E1")])
6953 (define_insn "*extzv_<mode>_sll"
6954 [(set (match_operand:GPR 0 "register_operand" "=d")
6955 (and:GPR (ashift:GPR
6956 (match_operand:GPR 1 "register_operand" "d")
6957 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6958 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6959 (clobber (reg:CC CC_REGNUM))]
6961 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6962 INTVAL (operands[3]))"
6963 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6964 [(set_attr "op_type" "RIE")
6965 (set_attr "z10prop" "z10_super_E1")])
6969 ; andsi3 instruction pattern(s).
6972 (define_insn "*andsi3_cc"
6973 [(set (reg CC_REGNUM)
6976 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6977 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6979 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6980 (and:SI (match_dup 1) (match_dup 2)))]
6981 "s390_match_ccmode(insn, CCTmode)"
6988 risbg\t%0,%1,%t2,128+%f2,0"
6989 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6990 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6991 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6992 z10_super_E1,z10_super_E1,z10_super_E1")])
6994 (define_insn "*andsi3_cconly"
6995 [(set (reg CC_REGNUM)
6998 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6999 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7001 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
7002 "s390_match_ccmode(insn, CCTmode)
7003 /* Do not steal TM patterns. */
7004 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7011 risbg\t%0,%1,%t2,128+%f2,0"
7012 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7013 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
7014 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7015 z10_super_E1,z10_super_E1,z10_super_E1")])
7017 (define_insn "*andsi3_zarch"
7018 [(set (match_operand:SI 0 "nonimmediate_operand"
7019 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
7020 (and:SI (match_operand:SI 1 "nonimmediate_operand"
7021 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
7022 (match_operand:SI 2 "general_operand"
7023 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
7024 (clobber (reg:CC CC_REGNUM))]
7025 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7036 risbg\t%0,%1,%t2,128+%f2,0
7039 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7040 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
7041 (set_attr "z10prop" "*,
7054 (define_insn "*andsi3_esa"
7055 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
7056 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
7057 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
7058 (clobber (reg:CC CC_REGNUM))]
7059 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7065 [(set_attr "op_type" "RR,RX,SI,SS")
7066 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7070 [(set (match_operand:SI 0 "s_operand" "")
7071 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7072 (clobber (reg:CC CC_REGNUM))]
7075 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7076 (clobber (reg:CC CC_REGNUM))])]
7077 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7080 ; andhi3 instruction pattern(s).
7083 (define_insn "*andhi3_zarch"
7084 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7085 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7086 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
7087 (clobber (reg:CC CC_REGNUM))]
7088 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7095 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7096 (set_attr "cpu_facility" "*,z196,*,*,*")
7097 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7100 (define_insn "*andhi3_esa"
7101 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7102 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7103 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7104 (clobber (reg:CC CC_REGNUM))]
7105 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7110 [(set_attr "op_type" "RR,SI,SS")
7111 (set_attr "z10prop" "z10_super_E1,*,*")
7115 [(set (match_operand:HI 0 "s_operand" "")
7116 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7117 (clobber (reg:CC CC_REGNUM))]
7120 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7121 (clobber (reg:CC CC_REGNUM))])]
7122 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7125 ; andqi3 instruction pattern(s).
7128 (define_insn "*andqi3_zarch"
7129 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7130 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7131 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7132 (clobber (reg:CC CC_REGNUM))]
7133 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7141 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7142 (set_attr "cpu_facility" "*,z196,*,*,*,*")
7143 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7145 (define_insn "*andqi3_esa"
7146 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7147 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7148 (match_operand:QI 2 "general_operand" "d,n,Q")))
7149 (clobber (reg:CC CC_REGNUM))]
7150 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7155 [(set_attr "op_type" "RR,SI,SS")
7156 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7159 ; Block and (NC) patterns.
7163 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7164 (and:BLK (match_dup 0)
7165 (match_operand:BLK 1 "memory_operand" "Q")))
7166 (use (match_operand 2 "const_int_operand" "n"))
7167 (clobber (reg:CC CC_REGNUM))]
7168 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7169 "nc\t%O0(%2,%R0),%S1"
7170 [(set_attr "op_type" "SS")
7171 (set_attr "z196prop" "z196_cracked")])
7174 [(set (match_operand 0 "memory_operand" "")
7176 (match_operand 1 "memory_operand" "")))
7177 (clobber (reg:CC CC_REGNUM))]
7179 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7180 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7182 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7184 (clobber (reg:CC CC_REGNUM))])]
7186 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7187 operands[0] = adjust_address (operands[0], BLKmode, 0);
7188 operands[1] = adjust_address (operands[1], BLKmode, 0);
7193 [(set (match_operand:BLK 0 "memory_operand" "")
7194 (and:BLK (match_dup 0)
7195 (match_operand:BLK 1 "memory_operand" "")))
7196 (use (match_operand 2 "const_int_operand" ""))
7197 (clobber (reg:CC CC_REGNUM))])
7199 [(set (match_operand:BLK 3 "memory_operand" "")
7200 (and:BLK (match_dup 3)
7201 (match_operand:BLK 4 "memory_operand" "")))
7202 (use (match_operand 5 "const_int_operand" ""))
7203 (clobber (reg:CC CC_REGNUM))])]
7204 "s390_offset_p (operands[0], operands[3], operands[2])
7205 && s390_offset_p (operands[1], operands[4], operands[2])
7206 && !s390_overlap_p (operands[0], operands[1],
7207 INTVAL (operands[2]) + INTVAL (operands[5]))
7208 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7210 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7212 (clobber (reg:CC CC_REGNUM))])]
7213 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7214 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7215 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7219 ;;- Bit set (inclusive or) instructions.
7222 (define_expand "ior<mode>3"
7223 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7224 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7225 (match_operand:INT 2 "general_operand" "")))
7226 (clobber (reg:CC CC_REGNUM))]
7228 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7231 ; iordi3 instruction pattern(s).
7234 (define_insn "*iordi3_cc"
7235 [(set (reg CC_REGNUM)
7236 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7237 (match_operand:DI 2 "general_operand" " d,d,RT"))
7239 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7240 (ior:DI (match_dup 1) (match_dup 2)))]
7241 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7246 [(set_attr "op_type" "RRE,RRF,RXY")
7247 (set_attr "cpu_facility" "*,z196,*")
7248 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7250 (define_insn "*iordi3_cconly"
7251 [(set (reg CC_REGNUM)
7252 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7253 (match_operand:DI 2 "general_operand" " d,d,RT"))
7255 (clobber (match_scratch:DI 0 "=d,d,d"))]
7256 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7261 [(set_attr "op_type" "RRE,RRF,RXY")
7262 (set_attr "cpu_facility" "*,z196,*")
7263 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7265 (define_insn "*iordi3"
7266 [(set (match_operand:DI 0 "nonimmediate_operand"
7267 "=d, d, d, d, d, d,d,d, d, AQ,Q")
7268 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7269 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
7270 (match_operand:DI 2 "general_operand"
7271 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7272 (clobber (reg:CC CC_REGNUM))]
7273 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7286 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7287 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7288 (set_attr "z10prop" "z10_super_E1,
7301 [(set (match_operand:DI 0 "s_operand" "")
7302 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7303 (clobber (reg:CC CC_REGNUM))]
7306 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7307 (clobber (reg:CC CC_REGNUM))])]
7308 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7311 ; iorsi3 instruction pattern(s).
7314 (define_insn "*iorsi3_cc"
7315 [(set (reg CC_REGNUM)
7316 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7317 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7319 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7320 (ior:SI (match_dup 1) (match_dup 2)))]
7321 "s390_match_ccmode(insn, CCTmode)"
7328 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7329 (set_attr "cpu_facility" "*,*,z196,*,*")
7330 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7332 (define_insn "*iorsi3_cconly"
7333 [(set (reg CC_REGNUM)
7334 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7335 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7337 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7338 "s390_match_ccmode(insn, CCTmode)"
7345 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7346 (set_attr "cpu_facility" "*,*,z196,*,*")
7347 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7349 (define_insn "*iorsi3_zarch"
7350 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
7351 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
7352 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7353 (clobber (reg:CC CC_REGNUM))]
7354 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7365 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7366 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
7367 (set_attr "z10prop" "z10_super_E1,
7377 (define_insn "*iorsi3_esa"
7378 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7379 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7380 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7381 (clobber (reg:CC CC_REGNUM))]
7382 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7388 [(set_attr "op_type" "RR,RX,SI,SS")
7389 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7392 [(set (match_operand:SI 0 "s_operand" "")
7393 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7394 (clobber (reg:CC CC_REGNUM))]
7397 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7398 (clobber (reg:CC CC_REGNUM))])]
7399 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7402 ; iorhi3 instruction pattern(s).
7405 (define_insn "*iorhi3_zarch"
7406 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7407 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7408 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
7409 (clobber (reg:CC CC_REGNUM))]
7410 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7417 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7418 (set_attr "cpu_facility" "*,z196,*,*,*")
7419 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7421 (define_insn "*iorhi3_esa"
7422 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7423 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7424 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7425 (clobber (reg:CC CC_REGNUM))]
7426 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7431 [(set_attr "op_type" "RR,SI,SS")
7432 (set_attr "z10prop" "z10_super_E1,*,*")])
7435 [(set (match_operand:HI 0 "s_operand" "")
7436 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7437 (clobber (reg:CC CC_REGNUM))]
7440 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7441 (clobber (reg:CC CC_REGNUM))])]
7442 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7445 ; iorqi3 instruction pattern(s).
7448 (define_insn "*iorqi3_zarch"
7449 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7450 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7451 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7452 (clobber (reg:CC CC_REGNUM))]
7453 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7461 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7462 (set_attr "cpu_facility" "*,z196,*,*,*,*")
7463 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7464 z10_super,z10_super,*")])
7466 (define_insn "*iorqi3_esa"
7467 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7468 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7469 (match_operand:QI 2 "general_operand" "d,n,Q")))
7470 (clobber (reg:CC CC_REGNUM))]
7471 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7476 [(set_attr "op_type" "RR,SI,SS")
7477 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7480 ; Block inclusive or (OC) patterns.
7484 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7485 (ior:BLK (match_dup 0)
7486 (match_operand:BLK 1 "memory_operand" "Q")))
7487 (use (match_operand 2 "const_int_operand" "n"))
7488 (clobber (reg:CC CC_REGNUM))]
7489 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7490 "oc\t%O0(%2,%R0),%S1"
7491 [(set_attr "op_type" "SS")
7492 (set_attr "z196prop" "z196_cracked")])
7495 [(set (match_operand 0 "memory_operand" "")
7497 (match_operand 1 "memory_operand" "")))
7498 (clobber (reg:CC CC_REGNUM))]
7500 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7501 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7503 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7505 (clobber (reg:CC CC_REGNUM))])]
7507 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7508 operands[0] = adjust_address (operands[0], BLKmode, 0);
7509 operands[1] = adjust_address (operands[1], BLKmode, 0);
7514 [(set (match_operand:BLK 0 "memory_operand" "")
7515 (ior:BLK (match_dup 0)
7516 (match_operand:BLK 1 "memory_operand" "")))
7517 (use (match_operand 2 "const_int_operand" ""))
7518 (clobber (reg:CC CC_REGNUM))])
7520 [(set (match_operand:BLK 3 "memory_operand" "")
7521 (ior:BLK (match_dup 3)
7522 (match_operand:BLK 4 "memory_operand" "")))
7523 (use (match_operand 5 "const_int_operand" ""))
7524 (clobber (reg:CC CC_REGNUM))])]
7525 "s390_offset_p (operands[0], operands[3], operands[2])
7526 && s390_offset_p (operands[1], operands[4], operands[2])
7527 && !s390_overlap_p (operands[0], operands[1],
7528 INTVAL (operands[2]) + INTVAL (operands[5]))
7529 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7531 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7533 (clobber (reg:CC CC_REGNUM))])]
7534 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7535 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7536 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7540 ;;- Xor instructions.
7543 (define_expand "xor<mode>3"
7544 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7545 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7546 (match_operand:INT 2 "general_operand" "")))
7547 (clobber (reg:CC CC_REGNUM))]
7549 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7551 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7552 ; simplifications. So its better to have something matching.
7554 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7555 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7558 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7559 (clobber (reg:CC CC_REGNUM))])]
7561 operands[2] = constm1_rtx;
7562 if (!s390_logical_operator_ok_p (operands))
7567 ; xordi3 instruction pattern(s).
7570 (define_insn "*xordi3_cc"
7571 [(set (reg CC_REGNUM)
7572 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7573 (match_operand:DI 2 "general_operand" " d,d,RT"))
7575 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7576 (xor:DI (match_dup 1) (match_dup 2)))]
7577 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7582 [(set_attr "op_type" "RRE,RRF,RXY")
7583 (set_attr "cpu_facility" "*,z196,*")
7584 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7586 (define_insn "*xordi3_cconly"
7587 [(set (reg CC_REGNUM)
7588 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7589 (match_operand:DI 2 "general_operand" " d,d,RT"))
7591 (clobber (match_scratch:DI 0 "=d,d, d"))]
7592 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7597 [(set_attr "op_type" "RRE,RRF,RXY")
7598 (set_attr "cpu_facility" "*,z196,*")
7599 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7601 (define_insn "*xordi3"
7602 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
7603 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
7604 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7605 (clobber (reg:CC CC_REGNUM))]
7606 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7615 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7616 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7617 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7618 *,z10_super_E1,*,*")])
7621 [(set (match_operand:DI 0 "s_operand" "")
7622 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7623 (clobber (reg:CC CC_REGNUM))]
7626 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7627 (clobber (reg:CC CC_REGNUM))])]
7628 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7631 ; xorsi3 instruction pattern(s).
7634 (define_insn "*xorsi3_cc"
7635 [(set (reg CC_REGNUM)
7636 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7637 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7639 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7640 (xor:SI (match_dup 1) (match_dup 2)))]
7641 "s390_match_ccmode(insn, CCTmode)"
7648 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7649 (set_attr "cpu_facility" "*,*,z196,*,*")
7650 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7651 z10_super_E1,z10_super_E1")])
7653 (define_insn "*xorsi3_cconly"
7654 [(set (reg CC_REGNUM)
7655 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7656 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7658 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7659 "s390_match_ccmode(insn, CCTmode)"
7666 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7667 (set_attr "cpu_facility" "*,*,z196,*,*")
7668 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7669 z10_super_E1,z10_super_E1")])
7671 (define_insn "*xorsi3"
7672 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7673 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7674 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7675 (clobber (reg:CC CC_REGNUM))]
7676 "s390_logical_operator_ok_p (operands)"
7685 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7686 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7687 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7688 z10_super_E1,z10_super_E1,*,*")])
7691 [(set (match_operand:SI 0 "s_operand" "")
7692 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7693 (clobber (reg:CC CC_REGNUM))]
7696 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7697 (clobber (reg:CC CC_REGNUM))])]
7698 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7701 ; xorhi3 instruction pattern(s).
7704 (define_insn "*xorhi3"
7705 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7706 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7707 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7708 (clobber (reg:CC CC_REGNUM))]
7709 "s390_logical_operator_ok_p (operands)"
7716 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7717 (set_attr "cpu_facility" "*,*,z196,*,*")
7718 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7721 [(set (match_operand:HI 0 "s_operand" "")
7722 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7723 (clobber (reg:CC CC_REGNUM))]
7726 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7727 (clobber (reg:CC CC_REGNUM))])]
7728 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7731 ; xorqi3 instruction pattern(s).
7734 (define_insn "*xorqi3"
7735 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7736 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7737 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7738 (clobber (reg:CC CC_REGNUM))]
7739 "s390_logical_operator_ok_p (operands)"
7747 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7748 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7749 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7753 ; Block exclusive or (XC) patterns.
7757 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7758 (xor:BLK (match_dup 0)
7759 (match_operand:BLK 1 "memory_operand" "Q")))
7760 (use (match_operand 2 "const_int_operand" "n"))
7761 (clobber (reg:CC CC_REGNUM))]
7762 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7763 "xc\t%O0(%2,%R0),%S1"
7764 [(set_attr "op_type" "SS")])
7767 [(set (match_operand 0 "memory_operand" "")
7769 (match_operand 1 "memory_operand" "")))
7770 (clobber (reg:CC CC_REGNUM))]
7772 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7773 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7775 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7777 (clobber (reg:CC CC_REGNUM))])]
7779 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7780 operands[0] = adjust_address (operands[0], BLKmode, 0);
7781 operands[1] = adjust_address (operands[1], BLKmode, 0);
7786 [(set (match_operand:BLK 0 "memory_operand" "")
7787 (xor:BLK (match_dup 0)
7788 (match_operand:BLK 1 "memory_operand" "")))
7789 (use (match_operand 2 "const_int_operand" ""))
7790 (clobber (reg:CC CC_REGNUM))])
7792 [(set (match_operand:BLK 3 "memory_operand" "")
7793 (xor:BLK (match_dup 3)
7794 (match_operand:BLK 4 "memory_operand" "")))
7795 (use (match_operand 5 "const_int_operand" ""))
7796 (clobber (reg:CC CC_REGNUM))])]
7797 "s390_offset_p (operands[0], operands[3], operands[2])
7798 && s390_offset_p (operands[1], operands[4], operands[2])
7799 && !s390_overlap_p (operands[0], operands[1],
7800 INTVAL (operands[2]) + INTVAL (operands[5]))
7801 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7803 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7805 (clobber (reg:CC CC_REGNUM))])]
7806 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7807 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7808 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7811 ; Block xor (XC) patterns with src == dest.
7814 (define_insn "*xc_zero"
7815 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7817 (use (match_operand 1 "const_int_operand" "n"))
7818 (clobber (reg:CC CC_REGNUM))]
7819 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7820 "xc\t%O0(%1,%R0),%S0"
7821 [(set_attr "op_type" "SS")
7822 (set_attr "z196prop" "z196_cracked")])
7826 [(set (match_operand:BLK 0 "memory_operand" "")
7828 (use (match_operand 1 "const_int_operand" ""))
7829 (clobber (reg:CC CC_REGNUM))])
7831 [(set (match_operand:BLK 2 "memory_operand" "")
7833 (use (match_operand 3 "const_int_operand" ""))
7834 (clobber (reg:CC CC_REGNUM))])]
7835 "s390_offset_p (operands[0], operands[2], operands[1])
7836 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7838 [(set (match_dup 4) (const_int 0))
7840 (clobber (reg:CC CC_REGNUM))])]
7841 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7842 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7846 ;;- Negate instructions.
7850 ; neg(di|si)2 instruction pattern(s).
7853 (define_expand "neg<mode>2"
7855 [(set (match_operand:DSI 0 "register_operand" "=d")
7856 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7857 (clobber (reg:CC CC_REGNUM))])]
7861 (define_insn "*negdi2_sign_cc"
7862 [(set (reg CC_REGNUM)
7863 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7864 (match_operand:SI 1 "register_operand" "d") 0)
7865 (const_int 32)) (const_int 32)))
7867 (set (match_operand:DI 0 "register_operand" "=d")
7868 (neg:DI (sign_extend:DI (match_dup 1))))]
7869 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7871 [(set_attr "op_type" "RRE")
7872 (set_attr "z10prop" "z10_c")])
7874 (define_insn "*negdi2_sign"
7875 [(set (match_operand:DI 0 "register_operand" "=d")
7876 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7877 (clobber (reg:CC CC_REGNUM))]
7880 [(set_attr "op_type" "RRE")
7881 (set_attr "z10prop" "z10_c")])
7884 (define_insn "*neg<mode>2_cc"
7885 [(set (reg CC_REGNUM)
7886 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7888 (set (match_operand:GPR 0 "register_operand" "=d")
7889 (neg:GPR (match_dup 1)))]
7890 "s390_match_ccmode (insn, CCAmode)"
7892 [(set_attr "op_type" "RR<E>")
7893 (set_attr "z10prop" "z10_super_c_E1")])
7896 (define_insn "*neg<mode>2_cconly"
7897 [(set (reg CC_REGNUM)
7898 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7900 (clobber (match_scratch:GPR 0 "=d"))]
7901 "s390_match_ccmode (insn, CCAmode)"
7903 [(set_attr "op_type" "RR<E>")
7904 (set_attr "z10prop" "z10_super_c_E1")])
7907 (define_insn "*neg<mode>2"
7908 [(set (match_operand:GPR 0 "register_operand" "=d")
7909 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7910 (clobber (reg:CC CC_REGNUM))]
7913 [(set_attr "op_type" "RR<E>")
7914 (set_attr "z10prop" "z10_super_c_E1")])
7916 (define_insn "*negdi2_31"
7917 [(set (match_operand:DI 0 "register_operand" "=d")
7918 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7919 (clobber (reg:CC CC_REGNUM))]
7923 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7925 ; Doing the twos complement separately on the SImode parts does an
7926 ; unwanted +1 on the high part which needs to be subtracted afterwards
7927 ; ... unless the +1 on the low part created an overflow.
7930 [(set (match_operand:DI 0 "register_operand" "")
7931 (neg:DI (match_operand:DI 1 "register_operand" "")))
7932 (clobber (reg:CC CC_REGNUM))]
7934 && (REGNO (operands[0]) == REGNO (operands[1])
7935 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7936 && reload_completed"
7938 [(set (match_dup 2) (neg:SI (match_dup 3)))
7939 (clobber (reg:CC CC_REGNUM))])
7941 [(set (reg:CCAP CC_REGNUM)
7942 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7943 (set (match_dup 4) (neg:SI (match_dup 5)))])
7945 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7947 (label_ref (match_dup 6))))
7949 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7950 (clobber (reg:CC CC_REGNUM))])
7952 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7953 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7954 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7955 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7956 operands[6] = gen_label_rtx ();")
7958 ; Like above but first make a copy of the low part of the src operand
7959 ; since it might overlap with the high part of the destination.
7962 [(set (match_operand:DI 0 "register_operand" "")
7963 (neg:DI (match_operand:DI 1 "register_operand" "")))
7964 (clobber (reg:CC CC_REGNUM))]
7966 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7967 && reload_completed"
7968 [; Make a backup of op5 first
7969 (set (match_dup 4) (match_dup 5))
7970 ; Setting op2 here might clobber op5
7972 [(set (match_dup 2) (neg:SI (match_dup 3)))
7973 (clobber (reg:CC CC_REGNUM))])
7975 [(set (reg:CCAP CC_REGNUM)
7976 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7977 (set (match_dup 4) (neg:SI (match_dup 4)))])
7979 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7981 (label_ref (match_dup 6))))
7983 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7984 (clobber (reg:CC CC_REGNUM))])
7986 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7987 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7988 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7989 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7990 operands[6] = gen_label_rtx ();")
7993 ; neg(df|sf)2 instruction pattern(s).
7996 (define_expand "neg<mode>2"
7998 [(set (match_operand:BFP 0 "register_operand" "=f")
7999 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
8000 (clobber (reg:CC CC_REGNUM))])]
8004 ; lcxbr, lcdbr, lcebr
8005 (define_insn "*neg<mode>2_cc"
8006 [(set (reg CC_REGNUM)
8007 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8008 (match_operand:BFP 2 "const0_operand" "")))
8009 (set (match_operand:BFP 0 "register_operand" "=f")
8010 (neg:BFP (match_dup 1)))]
8011 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8013 [(set_attr "op_type" "RRE")
8014 (set_attr "type" "fsimp<mode>")])
8016 ; lcxbr, lcdbr, lcebr
8017 (define_insn "*neg<mode>2_cconly"
8018 [(set (reg CC_REGNUM)
8019 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8020 (match_operand:BFP 2 "const0_operand" "")))
8021 (clobber (match_scratch:BFP 0 "=f"))]
8022 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8024 [(set_attr "op_type" "RRE")
8025 (set_attr "type" "fsimp<mode>")])
8028 (define_insn "*neg<mode>2_nocc"
8029 [(set (match_operand:FP 0 "register_operand" "=f")
8030 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8033 [(set_attr "op_type" "RRE")
8034 (set_attr "type" "fsimp<mode>")])
8036 ; lcxbr, lcdbr, lcebr
8037 ; FIXME: wflcdb does not clobber cc
8038 (define_insn "*neg<mode>2"
8039 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8040 (neg:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8041 (clobber (reg:CC CC_REGNUM))]
8046 [(set_attr "op_type" "RRE,VRR")
8047 (set_attr "cpu_facility" "*,vec")
8048 (set_attr "type" "fsimp<mode>,*")
8049 (set_attr "enabled" "*,<DFDI>")])
8053 ;;- Absolute value instructions.
8057 ; abs(di|si)2 instruction pattern(s).
8060 (define_insn "*absdi2_sign_cc"
8061 [(set (reg CC_REGNUM)
8062 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8063 (match_operand:SI 1 "register_operand" "d") 0)
8064 (const_int 32)) (const_int 32)))
8066 (set (match_operand:DI 0 "register_operand" "=d")
8067 (abs:DI (sign_extend:DI (match_dup 1))))]
8068 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8070 [(set_attr "op_type" "RRE")
8071 (set_attr "z10prop" "z10_c")])
8073 (define_insn "*absdi2_sign"
8074 [(set (match_operand:DI 0 "register_operand" "=d")
8075 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8076 (clobber (reg:CC CC_REGNUM))]
8079 [(set_attr "op_type" "RRE")
8080 (set_attr "z10prop" "z10_c")])
8083 (define_insn "*abs<mode>2_cc"
8084 [(set (reg CC_REGNUM)
8085 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8087 (set (match_operand:GPR 0 "register_operand" "=d")
8088 (abs:GPR (match_dup 1)))]
8089 "s390_match_ccmode (insn, CCAmode)"
8091 [(set_attr "op_type" "RR<E>")
8092 (set_attr "z10prop" "z10_c")])
8095 (define_insn "*abs<mode>2_cconly"
8096 [(set (reg CC_REGNUM)
8097 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8099 (clobber (match_scratch:GPR 0 "=d"))]
8100 "s390_match_ccmode (insn, CCAmode)"
8102 [(set_attr "op_type" "RR<E>")
8103 (set_attr "z10prop" "z10_c")])
8106 (define_insn "abs<mode>2"
8107 [(set (match_operand:GPR 0 "register_operand" "=d")
8108 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8109 (clobber (reg:CC CC_REGNUM))]
8112 [(set_attr "op_type" "RR<E>")
8113 (set_attr "z10prop" "z10_c")])
8116 ; abs(df|sf)2 instruction pattern(s).
8119 (define_expand "abs<mode>2"
8121 [(set (match_operand:BFP 0 "register_operand" "=f")
8122 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8123 (clobber (reg:CC CC_REGNUM))])]
8127 ; lpxbr, lpdbr, lpebr
8128 (define_insn "*abs<mode>2_cc"
8129 [(set (reg CC_REGNUM)
8130 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8131 (match_operand:BFP 2 "const0_operand" "")))
8132 (set (match_operand:BFP 0 "register_operand" "=f")
8133 (abs:BFP (match_dup 1)))]
8134 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8136 [(set_attr "op_type" "RRE")
8137 (set_attr "type" "fsimp<mode>")])
8139 ; lpxbr, lpdbr, lpebr
8140 (define_insn "*abs<mode>2_cconly"
8141 [(set (reg CC_REGNUM)
8142 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8143 (match_operand:BFP 2 "const0_operand" "")))
8144 (clobber (match_scratch:BFP 0 "=f"))]
8145 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8147 [(set_attr "op_type" "RRE")
8148 (set_attr "type" "fsimp<mode>")])
8151 (define_insn "*abs<mode>2_nocc"
8152 [(set (match_operand:FP 0 "register_operand" "=f")
8153 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8156 [(set_attr "op_type" "RRE")
8157 (set_attr "type" "fsimp<mode>")])
8159 ; lpxbr, lpdbr, lpebr
8160 ; FIXME: wflpdb does not clobber cc
8161 (define_insn "*abs<mode>2"
8162 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8163 (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8164 (clobber (reg:CC CC_REGNUM))]
8169 [(set_attr "op_type" "RRE,VRR")
8170 (set_attr "cpu_facility" "*,vec")
8171 (set_attr "type" "fsimp<mode>,*")
8172 (set_attr "enabled" "*,<DFDI>")])
8176 ;;- Negated absolute value instructions
8183 (define_insn "*negabsdi2_sign_cc"
8184 [(set (reg CC_REGNUM)
8185 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8186 (match_operand:SI 1 "register_operand" "d") 0)
8187 (const_int 32)) (const_int 32))))
8189 (set (match_operand:DI 0 "register_operand" "=d")
8190 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8191 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8193 [(set_attr "op_type" "RRE")
8194 (set_attr "z10prop" "z10_c")])
8196 (define_insn "*negabsdi2_sign"
8197 [(set (match_operand:DI 0 "register_operand" "=d")
8198 (neg:DI (abs:DI (sign_extend:DI
8199 (match_operand:SI 1 "register_operand" "d")))))
8200 (clobber (reg:CC CC_REGNUM))]
8203 [(set_attr "op_type" "RRE")
8204 (set_attr "z10prop" "z10_c")])
8207 (define_insn "*negabs<mode>2_cc"
8208 [(set (reg CC_REGNUM)
8209 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8211 (set (match_operand:GPR 0 "register_operand" "=d")
8212 (neg:GPR (abs:GPR (match_dup 1))))]
8213 "s390_match_ccmode (insn, CCAmode)"
8215 [(set_attr "op_type" "RR<E>")
8216 (set_attr "z10prop" "z10_c")])
8219 (define_insn "*negabs<mode>2_cconly"
8220 [(set (reg CC_REGNUM)
8221 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8223 (clobber (match_scratch:GPR 0 "=d"))]
8224 "s390_match_ccmode (insn, CCAmode)"
8226 [(set_attr "op_type" "RR<E>")
8227 (set_attr "z10prop" "z10_c")])
8230 (define_insn "*negabs<mode>2"
8231 [(set (match_operand:GPR 0 "register_operand" "=d")
8232 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8233 (clobber (reg:CC CC_REGNUM))]
8236 [(set_attr "op_type" "RR<E>")
8237 (set_attr "z10prop" "z10_c")])
8243 ; lnxbr, lndbr, lnebr
8244 (define_insn "*negabs<mode>2_cc"
8245 [(set (reg CC_REGNUM)
8246 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8247 (match_operand:BFP 2 "const0_operand" "")))
8248 (set (match_operand:BFP 0 "register_operand" "=f")
8249 (neg:BFP (abs:BFP (match_dup 1))))]
8250 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8252 [(set_attr "op_type" "RRE")
8253 (set_attr "type" "fsimp<mode>")])
8255 ; lnxbr, lndbr, lnebr
8256 (define_insn "*negabs<mode>2_cconly"
8257 [(set (reg CC_REGNUM)
8258 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8259 (match_operand:BFP 2 "const0_operand" "")))
8260 (clobber (match_scratch:BFP 0 "=f"))]
8261 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8263 [(set_attr "op_type" "RRE")
8264 (set_attr "type" "fsimp<mode>")])
8267 (define_insn "*negabs<mode>2_nocc"
8268 [(set (match_operand:FP 0 "register_operand" "=f")
8269 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8272 [(set_attr "op_type" "RRE")
8273 (set_attr "type" "fsimp<mode>")])
8275 ; lnxbr, lndbr, lnebr
8276 ; FIXME: wflndb does not clobber cc
8277 (define_insn "*negabs<mode>2"
8278 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8279 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))))
8280 (clobber (reg:CC CC_REGNUM))]
8285 [(set_attr "op_type" "RRE,VRR")
8286 (set_attr "cpu_facility" "*,vec")
8287 (set_attr "type" "fsimp<mode>,*")
8288 (set_attr "enabled" "*,<DFDI>")])
8291 ;;- Square root instructions.
8295 ; sqrt(df|sf)2 instruction pattern(s).
8298 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8299 (define_insn "sqrt<mode>2"
8300 [(set (match_operand:BFP 0 "register_operand" "=f,f,v")
8301 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))]
8307 [(set_attr "op_type" "RRE,RXE,VRR")
8308 (set_attr "type" "fsqrt<mode>")
8309 (set_attr "cpu_facility" "*,*,vec")
8310 (set_attr "enabled" "*,<DSF>,<DFDI>")])
8314 ;;- One complement instructions.
8318 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8321 (define_expand "one_cmpl<mode>2"
8323 [(set (match_operand:INT 0 "register_operand" "")
8324 (xor:INT (match_operand:INT 1 "register_operand" "")
8326 (clobber (reg:CC CC_REGNUM))])]
8332 ;; Find leftmost bit instructions.
8335 (define_expand "clzdi2"
8336 [(set (match_operand:DI 0 "register_operand" "=d")
8337 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8338 "TARGET_EXTIMM && TARGET_ZARCH"
8340 rtx insn, clz_equal;
8341 rtx wide_reg = gen_reg_rtx (TImode);
8342 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8344 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8346 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8348 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8349 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8354 (define_insn "clztidi2"
8355 [(set (match_operand:TI 0 "register_operand" "=d")
8359 (xor:DI (match_operand:DI 1 "register_operand" "d")
8360 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8361 (subreg:SI (clz:DI (match_dup 1)) 4))))
8364 (zero_extend:TI (clz:DI (match_dup 1)))))
8365 (clobber (reg:CC CC_REGNUM))]
8366 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8367 == (unsigned HOST_WIDE_INT) 1 << 63
8368 && TARGET_EXTIMM && TARGET_ZARCH"
8370 [(set_attr "op_type" "RRE")])
8374 ;;- Rotate instructions.
8378 ; rotl(di|si)3 instruction pattern(s).
8381 (define_expand "rotl<mode>3"
8382 [(set (match_operand:GPR 0 "register_operand" "")
8383 (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8384 (match_operand:SI 2 "nonmemory_operand" "")))]
8389 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8390 [(set (match_operand:GPR 0 "register_operand" "=d")
8391 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8392 (match_operand:SI 2 "nonmemory_operand" "an")))]
8394 "rll<g>\t%0,%1,<addr_style_op_ops>"
8395 [(set_attr "op_type" "RSE")
8396 (set_attr "atype" "reg")
8397 (set_attr "z10prop" "z10_super_E1")])
8401 ;;- Shift instructions.
8405 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8406 ; Left shifts and logical right shifts
8408 (define_expand "<shift><mode>3"
8409 [(set (match_operand:DSI 0 "register_operand" "")
8410 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8411 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
8416 (define_insn "*<shift>di3_31"
8417 [(set (match_operand:DI 0 "register_operand" "=d")
8418 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8419 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8422 [(set_attr "op_type" "RS")
8423 (set_attr "atype" "reg")
8424 (set_attr "z196prop" "z196_cracked")])
8426 ; sll, srl, sllg, srlg, sllk, srlk
8427 (define_insn "*<shift><mode>3"
8428 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8429 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8430 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
8433 s<lr>l<g>\t%0,<1>%Y2
8434 s<lr>l<gk>\t%0,%1,%Y2"
8435 [(set_attr "op_type" "RS<E>,RSY")
8436 (set_attr "atype" "reg,reg")
8437 (set_attr "cpu_facility" "*,z196")
8438 (set_attr "z10prop" "z10_super_E1,*")])
8441 (define_insn "*<shift>di3_31_and"
8442 [(set (match_operand:DI 0 "register_operand" "=d")
8443 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8444 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8445 (match_operand:SI 3 "const_int_operand" "n"))))]
8446 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8448 [(set_attr "op_type" "RS")
8449 (set_attr "atype" "reg")])
8451 ; sll, srl, sllg, srlg, sllk, srlk
8452 (define_insn "*<shift><mode>3_and"
8453 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8454 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8455 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8456 (match_operand:SI 3 "const_int_operand" "n,n"))))]
8457 "(INTVAL (operands[3]) & 63) == 63"
8459 s<lr>l<g>\t%0,<1>%Y2
8460 s<lr>l<gk>\t%0,%1,%Y2"
8461 [(set_attr "op_type" "RS<E>,RSY")
8462 (set_attr "atype" "reg,reg")
8463 (set_attr "cpu_facility" "*,z196")
8464 (set_attr "z10prop" "z10_super_E1,*")])
8467 ; ashr(di|si)3 instruction pattern(s).
8468 ; Arithmetic right shifts
8470 (define_expand "ashr<mode>3"
8472 [(set (match_operand:DSI 0 "register_operand" "")
8473 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8474 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
8475 (clobber (reg:CC CC_REGNUM))])]
8479 (define_insn "*ashrdi3_cc_31"
8480 [(set (reg CC_REGNUM)
8481 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8482 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8484 (set (match_operand:DI 0 "register_operand" "=d")
8485 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8486 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8488 [(set_attr "op_type" "RS")
8489 (set_attr "atype" "reg")])
8491 (define_insn "*ashrdi3_cconly_31"
8492 [(set (reg CC_REGNUM)
8493 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8494 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8496 (clobber (match_scratch:DI 0 "=d"))]
8497 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8499 [(set_attr "op_type" "RS")
8500 (set_attr "atype" "reg")])
8502 (define_insn "*ashrdi3_31"
8503 [(set (match_operand:DI 0 "register_operand" "=d")
8504 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8505 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
8506 (clobber (reg:CC CC_REGNUM))]
8509 [(set_attr "op_type" "RS")
8510 (set_attr "atype" "reg")])
8513 (define_insn "*ashr<mode>3_cc"
8514 [(set (reg CC_REGNUM)
8515 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8516 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8518 (set (match_operand:GPR 0 "register_operand" "=d,d")
8519 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
8520 "s390_match_ccmode(insn, CCSmode)"
8524 [(set_attr "op_type" "RS<E>,RSY")
8525 (set_attr "atype" "reg,reg")
8526 (set_attr "cpu_facility" "*,z196")
8527 (set_attr "z10prop" "z10_super_E1,*")])
8530 (define_insn "*ashr<mode>3_cconly"
8531 [(set (reg CC_REGNUM)
8532 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8533 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8535 (clobber (match_scratch:GPR 0 "=d,d"))]
8536 "s390_match_ccmode(insn, CCSmode)"
8540 [(set_attr "op_type" "RS<E>,RSY")
8541 (set_attr "atype" "reg,reg")
8542 (set_attr "cpu_facility" "*,z196")
8543 (set_attr "z10prop" "z10_super_E1,*")])
8546 (define_insn "*ashr<mode>3"
8547 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8548 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8549 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8550 (clobber (reg:CC CC_REGNUM))]
8555 [(set_attr "op_type" "RS<E>,RSY")
8556 (set_attr "atype" "reg,reg")
8557 (set_attr "cpu_facility" "*,z196")
8558 (set_attr "z10prop" "z10_super_E1,*")])
8561 ; shift pattern with implicit ANDs
8563 (define_insn "*ashrdi3_cc_31_and"
8564 [(set (reg CC_REGNUM)
8565 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8566 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8567 (match_operand:SI 3 "const_int_operand" "n")))
8569 (set (match_operand:DI 0 "register_operand" "=d")
8570 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8571 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8572 && (INTVAL (operands[3]) & 63) == 63"
8574 [(set_attr "op_type" "RS")
8575 (set_attr "atype" "reg")])
8577 (define_insn "*ashrdi3_cconly_31_and"
8578 [(set (reg CC_REGNUM)
8579 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8580 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8581 (match_operand:SI 3 "const_int_operand" "n")))
8583 (clobber (match_scratch:DI 0 "=d"))]
8584 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8585 && (INTVAL (operands[3]) & 63) == 63"
8587 [(set_attr "op_type" "RS")
8588 (set_attr "atype" "reg")])
8590 (define_insn "*ashrdi3_31_and"
8591 [(set (match_operand:DI 0 "register_operand" "=d")
8592 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8593 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8594 (match_operand:SI 3 "const_int_operand" "n"))))
8595 (clobber (reg:CC CC_REGNUM))]
8596 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8598 [(set_attr "op_type" "RS")
8599 (set_attr "atype" "reg")])
8602 (define_insn "*ashr<mode>3_cc_and"
8603 [(set (reg CC_REGNUM)
8604 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8605 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8606 (match_operand:SI 3 "const_int_operand" "n,n")))
8608 (set (match_operand:GPR 0 "register_operand" "=d,d")
8609 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8610 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8614 [(set_attr "op_type" "RS<E>,RSY")
8615 (set_attr "atype" "reg,reg")
8616 (set_attr "cpu_facility" "*,z196")
8617 (set_attr "z10prop" "z10_super_E1,*")])
8620 (define_insn "*ashr<mode>3_cconly_and"
8621 [(set (reg CC_REGNUM)
8622 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8623 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8624 (match_operand:SI 3 "const_int_operand" "n,n")))
8626 (clobber (match_scratch:GPR 0 "=d,d"))]
8627 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8631 [(set_attr "op_type" "RS<E>,RSY")
8632 (set_attr "atype" "reg,reg")
8633 (set_attr "cpu_facility" "*,z196")
8634 (set_attr "z10prop" "z10_super_E1,*")])
8637 (define_insn "*ashr<mode>3_and"
8638 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8639 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8640 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8641 (match_operand:SI 3 "const_int_operand" "n,n"))))
8642 (clobber (reg:CC CC_REGNUM))]
8643 "(INTVAL (operands[3]) & 63) == 63"
8647 [(set_attr "op_type" "RS<E>,RSY")
8648 (set_attr "atype" "reg,reg")
8649 (set_attr "cpu_facility" "*,z196")
8650 (set_attr "z10prop" "z10_super_E1,*")])
8654 ;; Branch instruction patterns.
8657 (define_expand "cbranch<mode>4"
8659 (if_then_else (match_operator 0 "comparison_operator"
8660 [(match_operand:GPR 1 "register_operand" "")
8661 (match_operand:GPR 2 "general_operand" "")])
8662 (label_ref (match_operand 3 "" ""))
8665 "s390_emit_jump (operands[3],
8666 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8669 (define_expand "cbranch<mode>4"
8671 (if_then_else (match_operator 0 "comparison_operator"
8672 [(match_operand:FP 1 "register_operand" "")
8673 (match_operand:FP 2 "general_operand" "")])
8674 (label_ref (match_operand 3 "" ""))
8677 "s390_emit_jump (operands[3],
8678 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8681 (define_expand "cbranchcc4"
8683 (if_then_else (match_operator 0 "s390_comparison"
8684 [(match_operand 1 "cc_reg_operand" "")
8685 (match_operand 2 "const_int_operand" "")])
8686 (label_ref (match_operand 3 "" ""))
8693 ;;- Conditional jump instructions.
8696 (define_insn "*cjump_64"
8699 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8700 (match_operand 2 "const_int_operand" "")])
8701 (label_ref (match_operand 0 "" ""))
8705 if (get_attr_length (insn) == 4)
8708 return "jg%C1\t%l0";
8710 [(set_attr "op_type" "RI")
8711 (set_attr "type" "branch")
8712 (set (attr "length")
8713 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8714 (const_int 4) (const_int 6)))])
8716 (define_insn "*cjump_31"
8719 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8720 (match_operand 2 "const_int_operand" "")])
8721 (label_ref (match_operand 0 "" ""))
8725 gcc_assert (get_attr_length (insn) == 4);
8728 [(set_attr "op_type" "RI")
8729 (set_attr "type" "branch")
8730 (set (attr "length")
8731 (if_then_else (not (match_test "flag_pic"))
8732 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8733 (const_int 4) (const_int 6))
8734 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8735 (const_int 4) (const_int 8))))])
8737 (define_insn "*cjump_long"
8740 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8741 (match_operand 0 "address_operand" "ZQZR")
8745 if (get_attr_op_type (insn) == OP_TYPE_RR)
8750 [(set (attr "op_type")
8751 (if_then_else (match_operand 0 "register_operand" "")
8752 (const_string "RR") (const_string "RX")))
8753 (set_attr "type" "branch")
8754 (set_attr "atype" "agen")])
8756 ;; A conditional return instruction.
8757 (define_insn "*c<code>"
8760 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8763 "s390_can_use_<code>_insn ()"
8765 [(set_attr "op_type" "RR")
8766 (set_attr "type" "jsr")
8767 (set_attr "atype" "agen")])
8770 ;;- Negated conditional jump instructions.
8773 (define_insn "*icjump_64"
8776 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8778 (label_ref (match_operand 0 "" ""))))]
8781 if (get_attr_length (insn) == 4)
8784 return "jg%D1\t%l0";
8786 [(set_attr "op_type" "RI")
8787 (set_attr "type" "branch")
8788 (set (attr "length")
8789 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8790 (const_int 4) (const_int 6)))])
8792 (define_insn "*icjump_31"
8795 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8797 (label_ref (match_operand 0 "" ""))))]
8800 gcc_assert (get_attr_length (insn) == 4);
8803 [(set_attr "op_type" "RI")
8804 (set_attr "type" "branch")
8805 (set (attr "length")
8806 (if_then_else (not (match_test "flag_pic"))
8807 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8808 (const_int 4) (const_int 6))
8809 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8810 (const_int 4) (const_int 8))))])
8812 (define_insn "*icjump_long"
8815 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8817 (match_operand 0 "address_operand" "ZQZR")))]
8820 if (get_attr_op_type (insn) == OP_TYPE_RR)
8825 [(set (attr "op_type")
8826 (if_then_else (match_operand 0 "register_operand" "")
8827 (const_string "RR") (const_string "RX")))
8828 (set_attr "type" "branch")
8829 (set_attr "atype" "agen")])
8832 ;;- Trap instructions.
8836 [(trap_if (const_int 1) (const_int 0))]
8839 [(set_attr "op_type" "RI")
8840 (set_attr "type" "branch")])
8842 (define_expand "ctrap<mode>4"
8843 [(trap_if (match_operator 0 "comparison_operator"
8844 [(match_operand:GPR 1 "register_operand" "")
8845 (match_operand:GPR 2 "general_operand" "")])
8846 (match_operand 3 "const0_operand" ""))]
8849 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8850 operands[1], operands[2]);
8851 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8855 (define_expand "ctrap<mode>4"
8856 [(trap_if (match_operator 0 "comparison_operator"
8857 [(match_operand:FP 1 "register_operand" "")
8858 (match_operand:FP 2 "general_operand" "")])
8859 (match_operand 3 "const0_operand" ""))]
8862 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8863 operands[1], operands[2]);
8864 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8868 (define_insn "condtrap"
8869 [(trap_if (match_operator 0 "s390_comparison"
8870 [(match_operand 1 "cc_reg_operand" "c")
8875 [(set_attr "op_type" "RI")
8876 (set_attr "type" "branch")])
8878 ; crt, cgrt, cit, cgit
8879 (define_insn "*cmp_and_trap_signed_int<mode>"
8880 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8881 [(match_operand:GPR 1 "register_operand" "d,d")
8882 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8888 [(set_attr "op_type" "RRF,RIE")
8889 (set_attr "type" "branch")
8890 (set_attr "z10prop" "z10_super_c,z10_super")])
8892 ; clrt, clgrt, clfit, clgit, clt, clgt
8893 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8894 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8895 [(match_operand:GPR 1 "register_operand" "d,d, d")
8896 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8903 [(set_attr "op_type" "RRF,RIE,RSY")
8904 (set_attr "type" "branch")
8905 (set_attr "z10prop" "z10_super_c,z10_super,*")
8906 (set_attr "cpu_facility" "z10,z10,zEC12")])
8909 (define_insn "*load_and_trap<mode>"
8910 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8913 (set (match_operand:GPR 1 "register_operand" "=d")
8917 [(set_attr "op_type" "RXY")])
8921 ;;- Loop instructions.
8923 ;; This is all complicated by the fact that since this is a jump insn
8924 ;; we must handle our own output reloads.
8928 ; This splitter will be matched by combine and has to add the 2 moves
8929 ; necessary to load the compare and the increment values into a
8930 ; register pair as needed by brxle.
8932 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8935 (match_operator 6 "s390_brx_operator"
8936 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8937 (match_operand:GPR 2 "general_operand" ""))
8938 (match_operand:GPR 3 "register_operand" "")])
8939 (label_ref (match_operand 0 "" ""))
8941 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8942 (plus:GPR (match_dup 1) (match_dup 2)))
8943 (clobber (match_scratch:GPR 5 ""))]
8946 "!reload_completed && !reload_in_progress"
8947 [(set (match_dup 7) (match_dup 2)) ; the increment
8948 (set (match_dup 8) (match_dup 3)) ; the comparison value
8949 (parallel [(set (pc)
8952 [(plus:GPR (match_dup 1) (match_dup 7))
8954 (label_ref (match_dup 0))
8957 (plus:GPR (match_dup 1) (match_dup 7)))
8958 (clobber (match_dup 5))
8959 (clobber (reg:CC CC_REGNUM))])]
8961 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8962 operands[7] = gen_lowpart (<GPR:MODE>mode,
8963 gen_highpart (word_mode, dreg));
8964 operands[8] = gen_lowpart (<GPR:MODE>mode,
8965 gen_lowpart (word_mode, dreg));
8970 (define_insn_and_split "*brxg_64bit"
8973 (match_operator 5 "s390_brx_operator"
8974 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8975 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8976 (subreg:DI (match_dup 2) 8)])
8977 (label_ref (match_operand 0 "" ""))
8979 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8980 (plus:DI (match_dup 1)
8981 (subreg:DI (match_dup 2) 0)))
8982 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8983 (clobber (reg:CC CC_REGNUM))]
8986 if (which_alternative != 0)
8988 else if (get_attr_length (insn) == 6)
8989 return "brx%E5g\t%1,%2,%l0";
8991 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8993 "&& reload_completed
8994 && (!REG_P (operands[3])
8995 || !rtx_equal_p (operands[1], operands[3]))"
8996 [(set (match_dup 4) (match_dup 1))
8997 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8998 (clobber (reg:CC CC_REGNUM))])
8999 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
9000 (set (match_dup 3) (match_dup 4))
9001 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9002 (label_ref (match_dup 0))
9005 [(set_attr "op_type" "RIE")
9006 (set_attr "type" "branch")
9007 (set (attr "length")
9008 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9009 (const_int 6) (const_int 16)))])
9013 (define_insn_and_split "*brx_64bit"
9016 (match_operator 5 "s390_brx_operator"
9017 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9018 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
9019 (subreg:SI (match_dup 2) 12)])
9020 (label_ref (match_operand 0 "" ""))
9022 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9023 (plus:SI (match_dup 1)
9024 (subreg:SI (match_dup 2) 4)))
9025 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9026 (clobber (reg:CC CC_REGNUM))]
9029 if (which_alternative != 0)
9031 else if (get_attr_length (insn) == 6)
9032 return "brx%C5\t%1,%2,%l0";
9034 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9036 "&& reload_completed
9037 && (!REG_P (operands[3])
9038 || !rtx_equal_p (operands[1], operands[3]))"
9039 [(set (match_dup 4) (match_dup 1))
9040 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
9041 (clobber (reg:CC CC_REGNUM))])
9042 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
9043 (set (match_dup 3) (match_dup 4))
9044 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9045 (label_ref (match_dup 0))
9048 [(set_attr "op_type" "RSI")
9049 (set_attr "type" "branch")
9050 (set (attr "length")
9051 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9052 (const_int 6) (const_int 14)))])
9056 (define_insn_and_split "*brx_31bit"
9059 (match_operator 5 "s390_brx_operator"
9060 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9061 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9062 (subreg:SI (match_dup 2) 4)])
9063 (label_ref (match_operand 0 "" ""))
9065 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9066 (plus:SI (match_dup 1)
9067 (subreg:SI (match_dup 2) 0)))
9068 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9069 (clobber (reg:CC CC_REGNUM))]
9070 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9072 if (which_alternative != 0)
9074 else if (get_attr_length (insn) == 6)
9075 return "brx%C5\t%1,%2,%l0";
9077 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9079 "&& reload_completed
9080 && (!REG_P (operands[3])
9081 || !rtx_equal_p (operands[1], operands[3]))"
9082 [(set (match_dup 4) (match_dup 1))
9083 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9084 (clobber (reg:CC CC_REGNUM))])
9085 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9086 (set (match_dup 3) (match_dup 4))
9087 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9088 (label_ref (match_dup 0))
9091 [(set_attr "op_type" "RSI")
9092 (set_attr "type" "branch")
9093 (set (attr "length")
9094 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9095 (const_int 6) (const_int 14)))])
9100 (define_expand "doloop_end"
9101 [(use (match_operand 0 "" "")) ; loop pseudo
9102 (use (match_operand 1 "" ""))] ; label
9105 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9106 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9107 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9108 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9109 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9110 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9117 (define_insn_and_split "doloop_si64"
9120 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9122 (label_ref (match_operand 0 "" ""))
9124 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9125 (plus:SI (match_dup 1) (const_int -1)))
9126 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9127 (clobber (reg:CC CC_REGNUM))]
9130 if (which_alternative != 0)
9132 else if (get_attr_length (insn) == 4)
9133 return "brct\t%1,%l0";
9135 return "ahi\t%1,-1\;jgne\t%l0";
9137 "&& reload_completed
9138 && (! REG_P (operands[2])
9139 || ! rtx_equal_p (operands[1], operands[2]))"
9140 [(set (match_dup 3) (match_dup 1))
9141 (parallel [(set (reg:CCAN CC_REGNUM)
9142 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9144 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9145 (set (match_dup 2) (match_dup 3))
9146 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9147 (label_ref (match_dup 0))
9150 [(set_attr "op_type" "RI")
9151 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9152 ; hurt us in the (rare) case of ahi.
9153 (set_attr "z10prop" "z10_super_E1")
9154 (set_attr "type" "branch")
9155 (set (attr "length")
9156 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9157 (const_int 4) (const_int 10)))])
9159 (define_insn_and_split "doloop_si31"
9162 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9164 (label_ref (match_operand 0 "" ""))
9166 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9167 (plus:SI (match_dup 1) (const_int -1)))
9168 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9169 (clobber (reg:CC CC_REGNUM))]
9172 if (which_alternative != 0)
9174 else if (get_attr_length (insn) == 4)
9175 return "brct\t%1,%l0";
9179 "&& reload_completed
9180 && (! REG_P (operands[2])
9181 || ! rtx_equal_p (operands[1], operands[2]))"
9182 [(set (match_dup 3) (match_dup 1))
9183 (parallel [(set (reg:CCAN CC_REGNUM)
9184 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9186 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9187 (set (match_dup 2) (match_dup 3))
9188 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9189 (label_ref (match_dup 0))
9192 [(set_attr "op_type" "RI")
9193 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9194 ; hurt us in the (rare) case of ahi.
9195 (set_attr "z10prop" "z10_super_E1")
9196 (set_attr "type" "branch")
9197 (set (attr "length")
9198 (if_then_else (not (match_test "flag_pic"))
9199 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9200 (const_int 4) (const_int 6))
9201 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9202 (const_int 4) (const_int 8))))])
9204 (define_insn "*doloop_si_long"
9207 (ne (match_operand:SI 1 "register_operand" "d")
9209 (match_operand 0 "address_operand" "ZQZR")
9211 (set (match_operand:SI 2 "register_operand" "=1")
9212 (plus:SI (match_dup 1) (const_int -1)))
9213 (clobber (match_scratch:SI 3 "=X"))
9214 (clobber (reg:CC CC_REGNUM))]
9217 if (get_attr_op_type (insn) == OP_TYPE_RR)
9218 return "bctr\t%1,%0";
9220 return "bct\t%1,%a0";
9222 [(set (attr "op_type")
9223 (if_then_else (match_operand 0 "register_operand" "")
9224 (const_string "RR") (const_string "RX")))
9225 (set_attr "type" "branch")
9226 (set_attr "atype" "agen")
9227 (set_attr "z10prop" "z10_c")
9228 (set_attr "z196prop" "z196_cracked")])
9230 (define_insn_and_split "doloop_di"
9233 (ne (match_operand:DI 1 "register_operand" "d,d,d")
9235 (label_ref (match_operand 0 "" ""))
9237 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9238 (plus:DI (match_dup 1) (const_int -1)))
9239 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9240 (clobber (reg:CC CC_REGNUM))]
9243 if (which_alternative != 0)
9245 else if (get_attr_length (insn) == 4)
9246 return "brctg\t%1,%l0";
9248 return "aghi\t%1,-1\;jgne\t%l0";
9250 "&& reload_completed
9251 && (! REG_P (operands[2])
9252 || ! rtx_equal_p (operands[1], operands[2]))"
9253 [(set (match_dup 3) (match_dup 1))
9254 (parallel [(set (reg:CCAN CC_REGNUM)
9255 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9257 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9258 (set (match_dup 2) (match_dup 3))
9259 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9260 (label_ref (match_dup 0))
9263 [(set_attr "op_type" "RI")
9264 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9265 ; hurt us in the (rare) case of ahi.
9266 (set_attr "z10prop" "z10_super_E1")
9267 (set_attr "type" "branch")
9268 (set (attr "length")
9269 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9270 (const_int 4) (const_int 10)))])
9273 ;;- Unconditional jump instructions.
9277 ; jump instruction pattern(s).
9280 (define_expand "jump"
9281 [(match_operand 0 "" "")]
9283 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9285 (define_insn "*jump64"
9286 [(set (pc) (label_ref (match_operand 0 "" "")))]
9289 if (get_attr_length (insn) == 4)
9294 [(set_attr "op_type" "RI")
9295 (set_attr "type" "branch")
9296 (set (attr "length")
9297 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9298 (const_int 4) (const_int 6)))])
9300 (define_insn "*jump31"
9301 [(set (pc) (label_ref (match_operand 0 "" "")))]
9304 gcc_assert (get_attr_length (insn) == 4);
9307 [(set_attr "op_type" "RI")
9308 (set_attr "type" "branch")
9309 (set (attr "length")
9310 (if_then_else (not (match_test "flag_pic"))
9311 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9312 (const_int 4) (const_int 6))
9313 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9314 (const_int 4) (const_int 8))))])
9317 ; indirect-jump instruction pattern(s).
9320 (define_insn "indirect_jump"
9321 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
9324 if (get_attr_op_type (insn) == OP_TYPE_RR)
9329 [(set (attr "op_type")
9330 (if_then_else (match_operand 0 "register_operand" "")
9331 (const_string "RR") (const_string "RX")))
9332 (set_attr "type" "branch")
9333 (set_attr "atype" "agen")])
9336 ; casesi instruction pattern(s).
9339 (define_insn "casesi_jump"
9340 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
9341 (use (label_ref (match_operand 1 "" "")))]
9344 if (get_attr_op_type (insn) == OP_TYPE_RR)
9349 [(set (attr "op_type")
9350 (if_then_else (match_operand 0 "register_operand" "")
9351 (const_string "RR") (const_string "RX")))
9352 (set_attr "type" "branch")
9353 (set_attr "atype" "agen")])
9355 (define_expand "casesi"
9356 [(match_operand:SI 0 "general_operand" "")
9357 (match_operand:SI 1 "general_operand" "")
9358 (match_operand:SI 2 "general_operand" "")
9359 (label_ref (match_operand 3 "" ""))
9360 (label_ref (match_operand 4 "" ""))]
9363 rtx index = gen_reg_rtx (SImode);
9364 rtx base = gen_reg_rtx (Pmode);
9365 rtx target = gen_reg_rtx (Pmode);
9367 emit_move_insn (index, operands[0]);
9368 emit_insn (gen_subsi3 (index, index, operands[1]));
9369 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9372 if (Pmode != SImode)
9373 index = convert_to_mode (Pmode, index, 1);
9374 if (GET_CODE (index) != REG)
9375 index = copy_to_mode_reg (Pmode, index);
9378 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9380 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9382 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9384 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9385 emit_move_insn (target, index);
9388 target = gen_rtx_PLUS (Pmode, base, target);
9389 emit_jump_insn (gen_casesi_jump (target, operands[3]));
9396 ;;- Jump to subroutine.
9401 ; untyped call instruction pattern(s).
9404 ;; Call subroutine returning any type.
9405 (define_expand "untyped_call"
9406 [(parallel [(call (match_operand 0 "" "")
9408 (match_operand 1 "" "")
9409 (match_operand 2 "" "")])]
9414 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9416 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9418 rtx set = XVECEXP (operands[2], 0, i);
9419 emit_move_insn (SET_DEST (set), SET_SRC (set));
9422 /* The optimizer does not know that the call sets the function value
9423 registers we stored in the result block. We avoid problems by
9424 claiming that all hard registers are used and clobbered at this
9426 emit_insn (gen_blockage ());
9431 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9432 ;; all of memory. This blocks insns from being moved across this point.
9434 (define_insn "blockage"
9435 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9438 [(set_attr "type" "none")
9439 (set_attr "length" "0")])
9445 (define_expand "sibcall"
9446 [(call (match_operand 0 "" "")
9447 (match_operand 1 "" ""))]
9450 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9454 (define_insn "*sibcall_br"
9455 [(call (mem:QI (reg SIBCALL_REGNUM))
9456 (match_operand 0 "const_int_operand" "n"))]
9457 "SIBLING_CALL_P (insn)
9458 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9460 [(set_attr "op_type" "RR")
9461 (set_attr "type" "branch")
9462 (set_attr "atype" "agen")])
9464 (define_insn "*sibcall_brc"
9465 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9466 (match_operand 1 "const_int_operand" "n"))]
9467 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9469 [(set_attr "op_type" "RI")
9470 (set_attr "type" "branch")])
9472 (define_insn "*sibcall_brcl"
9473 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9474 (match_operand 1 "const_int_operand" "n"))]
9475 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9477 [(set_attr "op_type" "RIL")
9478 (set_attr "type" "branch")])
9481 ; sibcall_value patterns
9484 (define_expand "sibcall_value"
9485 [(set (match_operand 0 "" "")
9486 (call (match_operand 1 "" "")
9487 (match_operand 2 "" "")))]
9490 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9494 (define_insn "*sibcall_value_br"
9495 [(set (match_operand 0 "" "")
9496 (call (mem:QI (reg SIBCALL_REGNUM))
9497 (match_operand 1 "const_int_operand" "n")))]
9498 "SIBLING_CALL_P (insn)
9499 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9501 [(set_attr "op_type" "RR")
9502 (set_attr "type" "branch")
9503 (set_attr "atype" "agen")])
9505 (define_insn "*sibcall_value_brc"
9506 [(set (match_operand 0 "" "")
9507 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9508 (match_operand 2 "const_int_operand" "n")))]
9509 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9511 [(set_attr "op_type" "RI")
9512 (set_attr "type" "branch")])
9514 (define_insn "*sibcall_value_brcl"
9515 [(set (match_operand 0 "" "")
9516 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9517 (match_operand 2 "const_int_operand" "n")))]
9518 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9520 [(set_attr "op_type" "RIL")
9521 (set_attr "type" "branch")])
9525 ; call instruction pattern(s).
9528 (define_expand "call"
9529 [(call (match_operand 0 "" "")
9530 (match_operand 1 "" ""))
9531 (use (match_operand 2 "" ""))]
9534 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9535 gen_rtx_REG (Pmode, RETURN_REGNUM));
9539 (define_insn "*bras"
9540 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9541 (match_operand 1 "const_int_operand" "n"))
9542 (clobber (match_operand 2 "register_operand" "=r"))]
9543 "!SIBLING_CALL_P (insn)
9544 && TARGET_SMALL_EXEC
9545 && GET_MODE (operands[2]) == Pmode"
9547 [(set_attr "op_type" "RI")
9548 (set_attr "type" "jsr")
9549 (set_attr "z196prop" "z196_cracked")])
9551 (define_insn "*brasl"
9552 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9553 (match_operand 1 "const_int_operand" "n"))
9554 (clobber (match_operand 2 "register_operand" "=r"))]
9555 "!SIBLING_CALL_P (insn)
9557 && GET_MODE (operands[2]) == Pmode"
9559 [(set_attr "op_type" "RIL")
9560 (set_attr "type" "jsr")
9561 (set_attr "z196prop" "z196_cracked")])
9563 (define_insn "*basr"
9564 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9565 (match_operand 1 "const_int_operand" "n"))
9566 (clobber (match_operand 2 "register_operand" "=r"))]
9567 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9569 if (get_attr_op_type (insn) == OP_TYPE_RR)
9570 return "basr\t%2,%0";
9572 return "bas\t%2,%a0";
9574 [(set (attr "op_type")
9575 (if_then_else (match_operand 0 "register_operand" "")
9576 (const_string "RR") (const_string "RX")))
9577 (set_attr "type" "jsr")
9578 (set_attr "atype" "agen")
9579 (set_attr "z196prop" "z196_cracked")])
9582 ; call_value instruction pattern(s).
9585 (define_expand "call_value"
9586 [(set (match_operand 0 "" "")
9587 (call (match_operand 1 "" "")
9588 (match_operand 2 "" "")))
9589 (use (match_operand 3 "" ""))]
9592 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9593 gen_rtx_REG (Pmode, RETURN_REGNUM));
9597 (define_insn "*bras_r"
9598 [(set (match_operand 0 "" "")
9599 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9600 (match_operand:SI 2 "const_int_operand" "n")))
9601 (clobber (match_operand 3 "register_operand" "=r"))]
9602 "!SIBLING_CALL_P (insn)
9603 && TARGET_SMALL_EXEC
9604 && GET_MODE (operands[3]) == Pmode"
9606 [(set_attr "op_type" "RI")
9607 (set_attr "type" "jsr")
9608 (set_attr "z196prop" "z196_cracked")])
9610 (define_insn "*brasl_r"
9611 [(set (match_operand 0 "" "")
9612 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9613 (match_operand 2 "const_int_operand" "n")))
9614 (clobber (match_operand 3 "register_operand" "=r"))]
9615 "!SIBLING_CALL_P (insn)
9617 && GET_MODE (operands[3]) == Pmode"
9619 [(set_attr "op_type" "RIL")
9620 (set_attr "type" "jsr")
9621 (set_attr "z196prop" "z196_cracked")])
9623 (define_insn "*basr_r"
9624 [(set (match_operand 0 "" "")
9625 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9626 (match_operand 2 "const_int_operand" "n")))
9627 (clobber (match_operand 3 "register_operand" "=r"))]
9628 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9630 if (get_attr_op_type (insn) == OP_TYPE_RR)
9631 return "basr\t%3,%1";
9633 return "bas\t%3,%a1";
9635 [(set (attr "op_type")
9636 (if_then_else (match_operand 1 "register_operand" "")
9637 (const_string "RR") (const_string "RX")))
9638 (set_attr "type" "jsr")
9639 (set_attr "atype" "agen")
9640 (set_attr "z196prop" "z196_cracked")])
9643 ;;- Thread-local storage support.
9646 (define_expand "get_thread_pointer<mode>"
9647 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9651 (define_expand "set_thread_pointer<mode>"
9652 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9653 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9657 (define_insn "*set_tp"
9658 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9661 [(set_attr "type" "none")
9662 (set_attr "length" "0")])
9664 (define_insn "*tls_load_64"
9665 [(set (match_operand:DI 0 "register_operand" "=d")
9666 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9667 (match_operand:DI 2 "" "")]
9671 [(set_attr "op_type" "RXE")
9672 (set_attr "z10prop" "z10_fwd_A3")])
9674 (define_insn "*tls_load_31"
9675 [(set (match_operand:SI 0 "register_operand" "=d,d")
9676 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9677 (match_operand:SI 2 "" "")]
9683 [(set_attr "op_type" "RX,RXY")
9684 (set_attr "type" "load")
9685 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9687 (define_insn "*bras_tls"
9688 [(set (match_operand 0 "" "")
9689 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9690 (match_operand 2 "const_int_operand" "n")))
9691 (clobber (match_operand 3 "register_operand" "=r"))
9692 (use (match_operand 4 "" ""))]
9693 "!SIBLING_CALL_P (insn)
9694 && TARGET_SMALL_EXEC
9695 && GET_MODE (operands[3]) == Pmode"
9697 [(set_attr "op_type" "RI")
9698 (set_attr "type" "jsr")
9699 (set_attr "z196prop" "z196_cracked")])
9701 (define_insn "*brasl_tls"
9702 [(set (match_operand 0 "" "")
9703 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9704 (match_operand 2 "const_int_operand" "n")))
9705 (clobber (match_operand 3 "register_operand" "=r"))
9706 (use (match_operand 4 "" ""))]
9707 "!SIBLING_CALL_P (insn)
9709 && GET_MODE (operands[3]) == Pmode"
9711 [(set_attr "op_type" "RIL")
9712 (set_attr "type" "jsr")
9713 (set_attr "z196prop" "z196_cracked")])
9715 (define_insn "*basr_tls"
9716 [(set (match_operand 0 "" "")
9717 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9718 (match_operand 2 "const_int_operand" "n")))
9719 (clobber (match_operand 3 "register_operand" "=r"))
9720 (use (match_operand 4 "" ""))]
9721 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9723 if (get_attr_op_type (insn) == OP_TYPE_RR)
9724 return "basr\t%3,%1%J4";
9726 return "bas\t%3,%a1%J4";
9728 [(set (attr "op_type")
9729 (if_then_else (match_operand 1 "register_operand" "")
9730 (const_string "RR") (const_string "RX")))
9731 (set_attr "type" "jsr")
9732 (set_attr "atype" "agen")
9733 (set_attr "z196prop" "z196_cracked")])
9736 ;;- Atomic operations
9740 ; memory barrier patterns.
9743 (define_expand "mem_signal_fence"
9744 [(match_operand:SI 0 "const_int_operand")] ;; model
9747 /* The s390 memory model is strong enough not to require any
9748 barrier in order to synchronize a thread with itself. */
9752 (define_expand "mem_thread_fence"
9753 [(match_operand:SI 0 "const_int_operand")] ;; model
9756 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9757 enough not to require barriers of any kind. */
9758 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9760 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9761 MEM_VOLATILE_P (mem) = 1;
9762 emit_insn (gen_mem_thread_fence_1 (mem));
9767 ; Although bcr is superscalar on Z10, this variant will never
9768 ; become part of an execution group.
9769 ; With z196 we can make use of the fast-BCR-serialization facility.
9770 ; This allows for a slightly faster sync which is sufficient for our
9772 (define_insn "mem_thread_fence_1"
9773 [(set (match_operand:BLK 0 "" "")
9774 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9782 [(set_attr "op_type" "RR")
9783 (set_attr "mnemonic" "bcr_flush")
9784 (set_attr "z196prop" "z196_alone")])
9787 ; atomic load/store operations
9790 ; Atomic loads need not examine the memory model at all.
9791 (define_expand "atomic_load<mode>"
9792 [(match_operand:DINT 0 "register_operand") ;; output
9793 (match_operand:DINT 1 "memory_operand") ;; memory
9794 (match_operand:SI 2 "const_int_operand")] ;; model
9797 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9800 if (<MODE>mode == TImode)
9801 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9802 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9803 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9805 emit_move_insn (operands[0], operands[1]);
9809 ; Different from movdi_31 in that we want no splitters.
9810 (define_insn "atomic_loaddi_1"
9811 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9812 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9820 [(set_attr "op_type" "RS,RSY,RS,RSY")
9821 (set_attr "type" "lm,lm,floaddf,floaddf")])
9823 (define_insn "atomic_loadti_1"
9824 [(set (match_operand:TI 0 "register_operand" "=r")
9825 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9829 [(set_attr "op_type" "RXY")
9830 (set_attr "type" "other")])
9832 ; Atomic stores must(?) enforce sequential consistency.
9833 (define_expand "atomic_store<mode>"
9834 [(match_operand:DINT 0 "memory_operand") ;; memory
9835 (match_operand:DINT 1 "register_operand") ;; input
9836 (match_operand:SI 2 "const_int_operand")] ;; model
9839 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9841 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9844 if (<MODE>mode == TImode)
9845 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9846 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9847 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9849 emit_move_insn (operands[0], operands[1]);
9850 if (is_mm_seq_cst (model))
9851 emit_insn (gen_mem_thread_fence (operands[2]));
9855 ; Different from movdi_31 in that we want no splitters.
9856 (define_insn "atomic_storedi_1"
9857 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9858 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9866 [(set_attr "op_type" "RS,RSY,RS,RSY")
9867 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9869 (define_insn "atomic_storeti_1"
9870 [(set (match_operand:TI 0 "memory_operand" "=RT")
9871 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9875 [(set_attr "op_type" "RXY")
9876 (set_attr "type" "other")])
9879 ; compare and swap patterns.
9882 (define_expand "atomic_compare_and_swap<mode>"
9883 [(match_operand:SI 0 "register_operand") ;; bool success output
9884 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9885 (match_operand:DGPR 2 "memory_operand") ;; memory
9886 (match_operand:DGPR 3 "register_operand") ;; expected intput
9887 (match_operand:DGPR 4 "register_operand") ;; newval intput
9888 (match_operand:SI 5 "const_int_operand") ;; is_weak
9889 (match_operand:SI 6 "const_int_operand") ;; success model
9890 (match_operand:SI 7 "const_int_operand")] ;; failure model
9893 rtx cc, cmp, output = operands[1];
9895 if (!register_operand (output, <MODE>mode))
9896 output = gen_reg_rtx (<MODE>mode);
9898 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9901 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9902 (output, operands[2], operands[3], operands[4]));
9904 /* We deliberately accept non-register operands in the predicate
9905 to ensure the write back to the output operand happens *before*
9906 the store-flags code below. This makes it easier for combine
9907 to merge the store-flags code with a potential test-and-branch
9908 pattern following (immediately!) afterwards. */
9909 if (output != operands[1])
9910 emit_move_insn (operands[1], output);
9912 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9913 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9914 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9918 (define_expand "atomic_compare_and_swap<mode>"
9919 [(match_operand:SI 0 "register_operand") ;; bool success output
9920 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9921 (match_operand:HQI 2 "memory_operand") ;; memory
9922 (match_operand:HQI 3 "general_operand") ;; expected intput
9923 (match_operand:HQI 4 "general_operand") ;; newval intput
9924 (match_operand:SI 5 "const_int_operand") ;; is_weak
9925 (match_operand:SI 6 "const_int_operand") ;; success model
9926 (match_operand:SI 7 "const_int_operand")] ;; failure model
9929 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9930 operands[3], operands[4], INTVAL (operands[5]));
9934 (define_expand "atomic_compare_and_swap<mode>_internal"
9936 [(set (match_operand:DGPR 0 "register_operand")
9937 (match_operand:DGPR 1 "memory_operand"))
9939 (unspec_volatile:DGPR
9941 (match_operand:DGPR 2 "register_operand")
9942 (match_operand:DGPR 3 "register_operand")]
9944 (set (reg:CCZ1 CC_REGNUM)
9945 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9949 (define_insn "*atomic_compare_and_swap<mode>_1"
9950 [(set (match_operand:TDI 0 "register_operand" "=r")
9951 (match_operand:TDI 1 "memory_operand" "+QS"))
9953 (unspec_volatile:TDI
9955 (match_operand:TDI 2 "register_operand" "0")
9956 (match_operand:TDI 3 "register_operand" "r")]
9958 (set (reg:CCZ1 CC_REGNUM)
9959 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9961 "c<td>sg\t%0,%3,%S1"
9962 [(set_attr "op_type" "RSY")
9963 (set_attr "type" "sem")])
9966 (define_insn "*atomic_compare_and_swapdi_2"
9967 [(set (match_operand:DI 0 "register_operand" "=r,r")
9968 (match_operand:DI 1 "memory_operand" "+Q,S"))
9972 (match_operand:DI 2 "register_operand" "0,0")
9973 (match_operand:DI 3 "register_operand" "r,r")]
9975 (set (reg:CCZ1 CC_REGNUM)
9976 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9981 [(set_attr "op_type" "RS,RSY")
9982 (set_attr "type" "sem")])
9985 (define_insn "*atomic_compare_and_swapsi_3"
9986 [(set (match_operand:SI 0 "register_operand" "=r,r")
9987 (match_operand:SI 1 "memory_operand" "+Q,S"))
9991 (match_operand:SI 2 "register_operand" "0,0")
9992 (match_operand:SI 3 "register_operand" "r,r")]
9994 (set (reg:CCZ1 CC_REGNUM)
9995 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10000 [(set_attr "op_type" "RS,RSY")
10001 (set_attr "type" "sem")])
10004 ; Other atomic instruction patterns.
10007 ; z196 load and add, xor, or and and instructions
10009 (define_expand "atomic_fetch_<atomic><mode>"
10010 [(match_operand:GPR 0 "register_operand") ;; val out
10012 (match_operand:GPR 1 "memory_operand") ;; memory
10013 (match_operand:GPR 2 "register_operand")) ;; val in
10014 (match_operand:SI 3 "const_int_operand")] ;; model
10017 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
10020 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
10021 (operands[0], operands[1], operands[2]));
10025 ; lan, lang, lao, laog, lax, laxg, laa, laag
10026 (define_insn "atomic_fetch_<atomic><mode>_iaf"
10027 [(set (match_operand:GPR 0 "register_operand" "=d")
10028 (match_operand:GPR 1 "memory_operand" "+QS"))
10030 (unspec_volatile:GPR
10031 [(ATOMIC_Z196:GPR (match_dup 1)
10032 (match_operand:GPR 2 "general_operand" "d"))]
10033 UNSPECV_ATOMIC_OP))
10034 (clobber (reg:CC CC_REGNUM))]
10036 "la<noxa><g>\t%0,%2,%1"
10037 [(set_attr "op_type" "RSY")
10038 (set_attr "type" "sem")])
10040 ;; For SImode and larger, the optabs.c code will do just fine in
10041 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
10042 ;; better by expanding our own loop.
10044 (define_expand "atomic_<atomic><mode>"
10046 (match_operand:HQI 0 "memory_operand") ;; memory
10047 (match_operand:HQI 1 "general_operand")) ;; val in
10048 (match_operand:SI 2 "const_int_operand")] ;; model
10051 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10052 operands[1], false);
10056 (define_expand "atomic_fetch_<atomic><mode>"
10057 [(match_operand:HQI 0 "register_operand") ;; val out
10059 (match_operand:HQI 1 "memory_operand") ;; memory
10060 (match_operand:HQI 2 "general_operand")) ;; val in
10061 (match_operand:SI 3 "const_int_operand")] ;; model
10064 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10065 operands[2], false);
10069 (define_expand "atomic_<atomic>_fetch<mode>"
10070 [(match_operand:HQI 0 "register_operand") ;; val out
10072 (match_operand:HQI 1 "memory_operand") ;; memory
10073 (match_operand:HQI 2 "general_operand")) ;; val in
10074 (match_operand:SI 3 "const_int_operand")] ;; model
10077 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10078 operands[2], true);
10082 (define_expand "atomic_exchange<mode>"
10083 [(match_operand:HQI 0 "register_operand") ;; val out
10084 (match_operand:HQI 1 "memory_operand") ;; memory
10085 (match_operand:HQI 2 "general_operand") ;; val in
10086 (match_operand:SI 3 "const_int_operand")] ;; model
10089 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10090 operands[2], false);
10095 ;;- Miscellaneous instructions.
10099 ; allocate stack instruction pattern(s).
10102 (define_expand "allocate_stack"
10103 [(match_operand 0 "general_operand" "")
10104 (match_operand 1 "general_operand" "")]
10107 rtx temp = gen_reg_rtx (Pmode);
10109 emit_move_insn (temp, s390_back_chain_rtx ());
10110 anti_adjust_stack (operands[1]);
10111 emit_move_insn (s390_back_chain_rtx (), temp);
10113 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10119 ; setjmp instruction pattern.
10122 (define_expand "builtin_setjmp_receiver"
10123 [(match_operand 0 "" "")]
10126 emit_insn (s390_load_got ());
10127 emit_use (pic_offset_table_rtx);
10131 ;; These patterns say how to save and restore the stack pointer. We need not
10132 ;; save the stack pointer at function level since we are careful to
10133 ;; preserve the backchain. At block level, we have to restore the backchain
10134 ;; when we restore the stack pointer.
10136 ;; For nonlocal gotos, we must save both the stack pointer and its
10137 ;; backchain and restore both. Note that in the nonlocal case, the
10138 ;; save area is a memory location.
10140 (define_expand "save_stack_function"
10141 [(match_operand 0 "general_operand" "")
10142 (match_operand 1 "general_operand" "")]
10146 (define_expand "restore_stack_function"
10147 [(match_operand 0 "general_operand" "")
10148 (match_operand 1 "general_operand" "")]
10152 (define_expand "restore_stack_block"
10153 [(match_operand 0 "register_operand" "")
10154 (match_operand 1 "register_operand" "")]
10157 rtx temp = gen_reg_rtx (Pmode);
10159 emit_move_insn (temp, s390_back_chain_rtx ());
10160 emit_move_insn (operands[0], operands[1]);
10161 emit_move_insn (s390_back_chain_rtx (), temp);
10166 (define_expand "save_stack_nonlocal"
10167 [(match_operand 0 "memory_operand" "")
10168 (match_operand 1 "register_operand" "")]
10171 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10173 /* Copy the backchain to the first word, sp to the second and the
10174 literal pool base to the third. */
10176 rtx save_bc = adjust_address (operands[0], Pmode, 0);
10177 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10178 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10180 if (TARGET_BACKCHAIN)
10181 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10183 emit_move_insn (save_sp, operands[1]);
10184 emit_move_insn (save_bp, base);
10189 (define_expand "restore_stack_nonlocal"
10190 [(match_operand 0 "register_operand" "")
10191 (match_operand 1 "memory_operand" "")]
10194 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10195 rtx temp = NULL_RTX;
10197 /* Restore the backchain from the first word, sp from the second and the
10198 literal pool base from the third. */
10200 rtx save_bc = adjust_address (operands[1], Pmode, 0);
10201 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10202 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10204 if (TARGET_BACKCHAIN)
10205 temp = force_reg (Pmode, save_bc);
10207 emit_move_insn (base, save_bp);
10208 emit_move_insn (operands[0], save_sp);
10211 emit_move_insn (s390_back_chain_rtx (), temp);
10217 (define_expand "exception_receiver"
10221 s390_set_has_landing_pad_p (true);
10226 ; nop instruction pattern(s).
10233 [(set_attr "op_type" "RR")
10234 (set_attr "z10prop" "z10_fr_E1")])
10236 (define_insn "nop1"
10240 [(set_attr "op_type" "RR")])
10242 ;;- Undeletable nops (used for hotpatching)
10244 (define_insn "nop_2_byte"
10245 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10248 [(set_attr "op_type" "RR")])
10250 (define_insn "nop_4_byte"
10251 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10254 [(set_attr "op_type" "RX")])
10256 (define_insn "nop_6_byte"
10257 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10260 [(set_attr "op_type" "RIL")])
10264 ; Special literal pool access instruction pattern(s).
10267 (define_insn "*pool_entry"
10268 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10269 UNSPECV_POOL_ENTRY)]
10272 machine_mode mode = GET_MODE (PATTERN (insn));
10273 unsigned int align = GET_MODE_BITSIZE (mode);
10274 s390_output_pool_entry (operands[0], mode, align);
10277 [(set (attr "length")
10278 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10280 (define_insn "pool_align"
10281 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10282 UNSPECV_POOL_ALIGN)]
10285 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10287 (define_insn "pool_section_start"
10288 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10291 switch_to_section (targetm.asm_out.function_rodata_section
10292 (current_function_decl));
10295 [(set_attr "length" "0")])
10297 (define_insn "pool_section_end"
10298 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10301 switch_to_section (current_function_section ());
10304 [(set_attr "length" "0")])
10306 (define_insn "main_base_31_small"
10307 [(set (match_operand 0 "register_operand" "=a")
10308 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10309 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10311 [(set_attr "op_type" "RR")
10312 (set_attr "type" "la")
10313 (set_attr "z196prop" "z196_cracked")])
10315 (define_insn "main_base_31_large"
10316 [(set (match_operand 0 "register_operand" "=a")
10317 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10318 (set (pc) (label_ref (match_operand 2 "" "")))]
10319 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10321 [(set_attr "op_type" "RI")
10322 (set_attr "z196prop" "z196_cracked")])
10324 (define_insn "main_base_64"
10325 [(set (match_operand 0 "register_operand" "=a")
10326 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10327 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10329 [(set_attr "op_type" "RIL")
10330 (set_attr "type" "larl")
10331 (set_attr "z10prop" "z10_fwd_A1")])
10333 (define_insn "main_pool"
10334 [(set (match_operand 0 "register_operand" "=a")
10335 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10336 "GET_MODE (operands[0]) == Pmode"
10338 gcc_unreachable ();
10340 [(set (attr "type")
10341 (if_then_else (match_test "TARGET_CPU_ZARCH")
10342 (const_string "larl") (const_string "la")))])
10344 (define_insn "reload_base_31"
10345 [(set (match_operand 0 "register_operand" "=a")
10346 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10347 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10348 "basr\t%0,0\;la\t%0,%1-.(%0)"
10349 [(set_attr "length" "6")
10350 (set_attr "type" "la")
10351 (set_attr "z196prop" "z196_cracked")])
10353 (define_insn "reload_base_64"
10354 [(set (match_operand 0 "register_operand" "=a")
10355 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10356 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10358 [(set_attr "op_type" "RIL")
10359 (set_attr "type" "larl")
10360 (set_attr "z10prop" "z10_fwd_A1")])
10362 (define_insn "pool"
10363 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10366 gcc_unreachable ();
10368 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10371 ;; Insns related to generating the function prologue and epilogue.
10375 (define_expand "prologue"
10376 [(use (const_int 0))]
10378 "s390_emit_prologue (); DONE;")
10380 (define_expand "epilogue"
10381 [(use (const_int 1))]
10383 "s390_emit_epilogue (false); DONE;")
10385 (define_expand "sibcall_epilogue"
10386 [(use (const_int 0))]
10388 "s390_emit_epilogue (true); DONE;")
10390 ;; A direct return instruction, without using an epilogue.
10391 (define_insn "<code>"
10393 "s390_can_use_<code>_insn ()"
10395 [(set_attr "op_type" "RR")
10396 (set_attr "type" "jsr")
10397 (set_attr "atype" "agen")])
10399 (define_insn "*return"
10401 (use (match_operand 0 "register_operand" "a"))]
10402 "GET_MODE (operands[0]) == Pmode"
10404 [(set_attr "op_type" "RR")
10405 (set_attr "type" "jsr")
10406 (set_attr "atype" "agen")])
10409 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10410 ;; pointer. This is used for compatibility.
10412 (define_expand "ptr_extend"
10413 [(set (match_operand:DI 0 "register_operand" "=r")
10414 (match_operand:SI 1 "register_operand" "r"))]
10417 emit_insn (gen_anddi3 (operands[0],
10418 gen_lowpart (DImode, operands[1]),
10419 GEN_INT (0x7fffffff)));
10423 ;; Instruction definition to expand eh_return macro to support
10424 ;; swapping in special linkage return addresses.
10426 (define_expand "eh_return"
10427 [(use (match_operand 0 "register_operand" ""))]
10430 s390_emit_tpf_eh_return (operands[0]);
10435 ; Stack Protector Patterns
10438 (define_expand "stack_protect_set"
10439 [(set (match_operand 0 "memory_operand" "")
10440 (match_operand 1 "memory_operand" ""))]
10443 #ifdef TARGET_THREAD_SSP_OFFSET
10445 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10446 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10449 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10451 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10456 (define_insn "stack_protect_set<mode>"
10457 [(set (match_operand:DSI 0 "memory_operand" "=Q")
10458 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10460 "mvc\t%O0(%G0,%R0),%S1"
10461 [(set_attr "op_type" "SS")])
10463 (define_expand "stack_protect_test"
10464 [(set (reg:CC CC_REGNUM)
10465 (compare (match_operand 0 "memory_operand" "")
10466 (match_operand 1 "memory_operand" "")))
10467 (match_operand 2 "" "")]
10471 #ifdef TARGET_THREAD_SSP_OFFSET
10473 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10474 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10477 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10479 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10481 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10482 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10483 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10487 (define_insn "stack_protect_test<mode>"
10488 [(set (reg:CCZ CC_REGNUM)
10489 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10490 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10492 "clc\t%O0(%G0,%R0),%S1"
10493 [(set_attr "op_type" "SS")])
10495 ; This is used in s390_emit_prologue in order to prevent insns
10496 ; adjusting the stack pointer to be moved over insns writing stack
10497 ; slots using a copy of the stack pointer in a different register.
10498 (define_insn "stack_tie"
10499 [(set (match_operand:BLK 0 "memory_operand" "+m")
10500 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10503 [(set_attr "length" "0")])
10507 ; Data prefetch patterns
10510 (define_insn "prefetch"
10511 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
10512 (match_operand:SI 1 "const_int_operand" " n,n")
10513 (match_operand:SI 2 "const_int_operand" " n,n"))]
10516 switch (which_alternative)
10519 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10521 if (larl_operand (operands[0], Pmode))
10522 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10525 /* This might be reached for symbolic operands with an odd
10526 addend. We simply omit the prefetch for such rare cases. */
10531 [(set_attr "type" "load,larl")
10532 (set_attr "op_type" "RXY,RIL")
10533 (set_attr "z10prop" "z10_super")
10534 (set_attr "z196prop" "z196_alone")])
10538 ; Byte swap instructions
10541 ; FIXME: There is also mvcin but we cannot use it since src and target
10543 (define_insn "bswap<mode>2"
10544 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,RT")
10545 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))]
10551 [(set_attr "type" "*,load,store")
10552 (set_attr "op_type" "RRE,RXY,RXY")
10553 (set_attr "z10prop" "z10_super")])
10555 (define_insn "bswaphi2"
10556 [(set (match_operand:HI 0 "nonimmediate_operand" "=d, d,RT")
10557 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))]
10563 [(set_attr "type" "*,load,store")
10564 (set_attr "op_type" "RRE,RXY,RXY")
10565 (set_attr "z10prop" "z10_super")])
10568 [(set (match_operand:HI 0 "register_operand" "")
10569 (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10571 [(set (match_dup 2) (bswap:SI (match_dup 3)))
10572 (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10574 operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10575 operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10580 ; Population count instruction
10583 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10584 ; portions and stores the result in the corresponding bytes in op0.
10585 (define_insn "*popcount<mode>"
10586 [(set (match_operand:INT 0 "register_operand" "=d")
10587 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10588 (clobber (reg:CC CC_REGNUM))]
10591 [(set_attr "op_type" "RRE")])
10593 (define_expand "popcountdi2"
10595 (parallel [(set (match_operand:DI 0 "register_operand" "")
10596 (unspec:DI [(match_operand:DI 1 "register_operand")]
10598 (clobber (reg:CC CC_REGNUM))])
10599 ; sllg op2, op0, 32
10600 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10602 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10603 (clobber (reg:CC CC_REGNUM))])
10604 ; sllg op2, op0, 16
10606 (ashift:DI (match_dup 0) (const_int 16)))
10608 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10609 (clobber (reg:CC CC_REGNUM))])
10611 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10613 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10614 (clobber (reg:CC CC_REGNUM))])
10615 ; srlg op0, op0, 56
10616 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10617 "TARGET_Z196 && TARGET_64BIT"
10618 "operands[2] = gen_reg_rtx (DImode);")
10620 (define_expand "popcountsi2"
10622 (parallel [(set (match_operand:SI 0 "register_operand" "")
10623 (unspec:SI [(match_operand:SI 1 "register_operand")]
10625 (clobber (reg:CC CC_REGNUM))])
10626 ; sllk op2, op0, 16
10628 (ashift:SI (match_dup 0) (const_int 16)))
10630 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10631 (clobber (reg:CC CC_REGNUM))])
10633 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10635 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10636 (clobber (reg:CC CC_REGNUM))])
10638 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10640 "operands[2] = gen_reg_rtx (SImode);")
10642 (define_expand "popcounthi2"
10644 (parallel [(set (match_operand:HI 0 "register_operand" "")
10645 (unspec:HI [(match_operand:HI 1 "register_operand")]
10647 (clobber (reg:CC CC_REGNUM))])
10650 (ashift:SI (match_dup 0) (const_int 8)))
10652 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10653 (clobber (reg:CC CC_REGNUM))])
10655 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10657 "operands[2] = gen_reg_rtx (SImode);")
10659 (define_expand "popcountqi2"
10661 (parallel [(set (match_operand:QI 0 "register_operand" "")
10662 (unspec:QI [(match_operand:QI 1 "register_operand")]
10664 (clobber (reg:CC CC_REGNUM))])]
10669 ;;- Copy sign instructions
10672 (define_insn "copysign<mode>3"
10673 [(set (match_operand:FP 0 "register_operand" "=f")
10674 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10675 (match_operand:FP 2 "register_operand" "f")]
10679 [(set_attr "op_type" "RRF")
10680 (set_attr "type" "fsimp<mode>")])
10684 ;;- Transactional execution instructions
10687 ; This splitter helps combine to make use of CC directly when
10688 ; comparing the integer result of a tbegin builtin with a constant.
10689 ; The unspec is already removed by canonicalize_comparison. So this
10690 ; splitters only job is to turn the PARALLEL into separate insns
10691 ; again. Unfortunately this only works with the very first cc/int
10692 ; compare since combine is not able to deal with data flow across
10693 ; basic block boundaries.
10695 ; It needs to be an insn pattern as well since combine does not apply
10696 ; the splitter directly. Combine would only use it if it actually
10697 ; would reduce the number of instructions.
10698 (define_insn_and_split "*ccraw_to_int"
10701 (match_operator 0 "s390_eqne_operator"
10702 [(reg:CCRAW CC_REGNUM)
10703 (match_operand 1 "const_int_operand" "")])
10704 (label_ref (match_operand 2 "" ""))
10706 (set (match_operand:SI 3 "register_operand" "=d")
10707 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10711 [(set (match_dup 3)
10712 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10714 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10715 (label_ref (match_dup 2))
10719 ; Non-constrained transaction begin
10721 (define_expand "tbegin"
10722 [(match_operand:SI 0 "register_operand" "")
10723 (match_operand:BLK 1 "memory_operand" "")]
10726 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10730 (define_expand "tbegin_nofloat"
10731 [(match_operand:SI 0 "register_operand" "")
10732 (match_operand:BLK 1 "memory_operand" "")]
10735 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10739 (define_expand "tbegin_retry"
10740 [(match_operand:SI 0 "register_operand" "")
10741 (match_operand:BLK 1 "memory_operand" "")
10742 (match_operand:SI 2 "general_operand" "")]
10745 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10749 (define_expand "tbegin_retry_nofloat"
10750 [(match_operand:SI 0 "register_operand" "")
10751 (match_operand:BLK 1 "memory_operand" "")
10752 (match_operand:SI 2 "general_operand" "")]
10755 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10759 ; Clobber VRs since they don't get restored
10760 (define_insn "tbegin_1_z13"
10761 [(set (reg:CCRAW CC_REGNUM)
10762 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10764 (set (match_operand:BLK 1 "memory_operand" "=Q")
10765 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10766 (clobber (reg:TI 16)) (clobber (reg:TI 38))
10767 (clobber (reg:TI 17)) (clobber (reg:TI 39))
10768 (clobber (reg:TI 18)) (clobber (reg:TI 40))
10769 (clobber (reg:TI 19)) (clobber (reg:TI 41))
10770 (clobber (reg:TI 20)) (clobber (reg:TI 42))
10771 (clobber (reg:TI 21)) (clobber (reg:TI 43))
10772 (clobber (reg:TI 22)) (clobber (reg:TI 44))
10773 (clobber (reg:TI 23)) (clobber (reg:TI 45))
10774 (clobber (reg:TI 24)) (clobber (reg:TI 46))
10775 (clobber (reg:TI 25)) (clobber (reg:TI 47))
10776 (clobber (reg:TI 26)) (clobber (reg:TI 48))
10777 (clobber (reg:TI 27)) (clobber (reg:TI 49))
10778 (clobber (reg:TI 28)) (clobber (reg:TI 50))
10779 (clobber (reg:TI 29)) (clobber (reg:TI 51))
10780 (clobber (reg:TI 30)) (clobber (reg:TI 52))
10781 (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10782 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10783 ; not supposed to be used for immediates (see genpreds.c).
10784 "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10786 [(set_attr "op_type" "SIL")])
10788 (define_insn "tbegin_1"
10789 [(set (reg:CCRAW CC_REGNUM)
10790 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10792 (set (match_operand:BLK 1 "memory_operand" "=Q")
10793 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10794 (clobber (reg:DF 16))
10795 (clobber (reg:DF 17))
10796 (clobber (reg:DF 18))
10797 (clobber (reg:DF 19))
10798 (clobber (reg:DF 20))
10799 (clobber (reg:DF 21))
10800 (clobber (reg:DF 22))
10801 (clobber (reg:DF 23))
10802 (clobber (reg:DF 24))
10803 (clobber (reg:DF 25))
10804 (clobber (reg:DF 26))
10805 (clobber (reg:DF 27))
10806 (clobber (reg:DF 28))
10807 (clobber (reg:DF 29))
10808 (clobber (reg:DF 30))
10809 (clobber (reg:DF 31))]
10810 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10811 ; not supposed to be used for immediates (see genpreds.c).
10812 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10814 [(set_attr "op_type" "SIL")])
10816 ; Same as above but without the FPR clobbers
10817 (define_insn "tbegin_nofloat_1"
10818 [(set (reg:CCRAW CC_REGNUM)
10819 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10821 (set (match_operand:BLK 1 "memory_operand" "=Q")
10822 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10823 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10825 [(set_attr "op_type" "SIL")])
10828 ; Constrained transaction begin
10830 (define_expand "tbeginc"
10831 [(set (reg:CCRAW CC_REGNUM)
10832 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10837 (define_insn "*tbeginc_1"
10838 [(set (reg:CCRAW CC_REGNUM)
10839 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10841 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10843 [(set_attr "op_type" "SIL")])
10847 (define_expand "tend"
10848 [(set (reg:CCRAW CC_REGNUM)
10849 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10850 (set (match_operand:SI 0 "register_operand" "")
10851 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10855 (define_insn "*tend_1"
10856 [(set (reg:CCRAW CC_REGNUM)
10857 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10860 [(set_attr "op_type" "S")])
10862 ; Transaction abort
10864 (define_expand "tabort"
10865 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10867 "TARGET_HTM && operands != NULL"
10869 if (CONST_INT_P (operands[0])
10870 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10872 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10873 ". Values in range 0 through 255 are reserved.",
10874 INTVAL (operands[0]));
10879 (define_insn "*tabort_1"
10880 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10882 "TARGET_HTM && operands != NULL"
10884 [(set_attr "op_type" "S")])
10886 ; Transaction extract nesting depth
10888 (define_insn "etnd"
10889 [(set (match_operand:SI 0 "register_operand" "=d")
10890 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10893 [(set_attr "op_type" "RRE")])
10895 ; Non-transactional store
10897 (define_insn "ntstg"
10898 [(set (match_operand:DI 0 "memory_operand" "=RT")
10899 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10903 [(set_attr "op_type" "RXY")])
10905 ; Transaction perform processor assist
10907 (define_expand "tx_assist"
10908 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10909 (reg:SI GPR0_REGNUM)
10915 (define_insn "*ppa"
10916 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10917 (match_operand:SI 1 "register_operand" "d")
10918 (match_operand 2 "const_int_operand" "I")]
10920 "TARGET_HTM && INTVAL (operands[2]) < 16"
10922 [(set_attr "op_type" "RRF")])
10925 ; Set and get floating point control register
10927 (define_insn "sfpc"
10928 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10930 "TARGET_HARD_FLOAT"
10933 (define_insn "efpc"
10934 [(set (match_operand:SI 0 "register_operand" "=d")
10935 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10936 "TARGET_HARD_FLOAT"
10940 ; Load count to block boundary
10942 (define_insn "lcbb"
10943 [(set (match_operand:SI 0 "register_operand" "=d")
10944 (unspec:SI [(match_operand 1 "address_operand" "ZQZR")
10945 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
10946 (clobber (reg:CC CC_REGNUM))]
10949 [(set_attr "op_type" "VRX")])
10951 ; Handle -fsplit-stack.
10953 (define_expand "split_stack_prologue"
10957 s390_expand_split_stack_prologue ();
10961 ;; If there are operand 0 bytes available on the stack, jump to
10964 (define_expand "split_stack_space_check"
10965 [(set (pc) (if_then_else
10966 (ltu (minus (reg 15)
10967 (match_operand 0 "register_operand"))
10968 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
10969 (label_ref (match_operand 1))
10973 /* Offset from thread pointer to __private_ss. */
10974 int psso = TARGET_64BIT ? 0x38 : 0x20;
10975 rtx tp = s390_get_thread_pointer ();
10976 rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
10977 rtx reg = gen_reg_rtx (Pmode);
10980 emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
10982 emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
10983 cc = s390_emit_compare (GT, reg, guard);
10984 s390_emit_jump (operands[1], cc);
10989 ;; __morestack parameter block for split stack prologue. Parameters are:
10990 ;; parameter block label, label to be called by __morestack, frame size,
10991 ;; stack parameter size.
10993 (define_insn "split_stack_data"
10994 [(unspec_volatile [(match_operand 0 "" "X")
10995 (match_operand 1 "" "X")
10996 (match_operand 2 "const_int_operand" "X")
10997 (match_operand 3 "const_int_operand" "X")]
10998 UNSPECV_SPLIT_STACK_DATA)]
11001 switch_to_section (targetm.asm_out.function_rodata_section
11002 (current_function_decl));
11005 output_asm_insn (".align\t8", operands);
11007 output_asm_insn (".align\t4", operands);
11008 (*targetm.asm_out.internal_label) (asm_out_file, "L",
11009 CODE_LABEL_NUMBER (operands[0]));
11012 output_asm_insn (".quad\t%2", operands);
11013 output_asm_insn (".quad\t%3", operands);
11014 output_asm_insn (".quad\t%1-%0", operands);
11018 output_asm_insn (".long\t%2", operands);
11019 output_asm_insn (".long\t%3", operands);
11020 output_asm_insn (".long\t%1-%0", operands);
11023 switch_to_section (current_function_section ());
11026 [(set_attr "length" "0")])
11029 ;; A jg with minimal fuss for use in split stack prologue.
11031 (define_expand "split_stack_call"
11032 [(match_operand 0 "bras_sym_operand" "X")
11033 (match_operand 1 "" "")]
11037 emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
11039 emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
11043 (define_insn "split_stack_call_<mode>"
11044 [(set (pc) (label_ref (match_operand 1 "" "")))
11045 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11047 UNSPECV_SPLIT_STACK_CALL))]
11050 [(set_attr "op_type" "RIL")
11051 (set_attr "type" "branch")])
11053 ;; Also a conditional one.
11055 (define_expand "split_stack_cond_call"
11056 [(match_operand 0 "bras_sym_operand" "X")
11057 (match_operand 1 "" "")
11058 (match_operand 2 "" "")]
11062 emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
11064 emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
11068 (define_insn "split_stack_cond_call_<mode>"
11071 (match_operand 1 "" "")
11072 (label_ref (match_operand 2 "" ""))
11074 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11076 UNSPECV_SPLIT_STACK_CALL))]
11079 [(set_attr "op_type" "RIL")
11080 (set_attr "type" "branch")])