1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
88 ; TLS relocation specifiers
93 (UNSPEC_GOTNTPOFF 504)
94 (UNSPEC_INDNTPOFF 505)
97 (UNSPEC_TLSLDM_NTPOFF 511)
104 ; Stack Smashing Protector
108 ; Copy sign instructions
109 (UNSPEC_COPYSIGN 800)
111 ; Test Data Class (TDC)
112 (UNSPEC_TDC_INSN 900)
116 ;; UNSPEC_VOLATILE usage
124 (UNSPECV_TPF_PROLOGUE 20)
125 (UNSPECV_TPF_EPILOGUE 21)
129 (UNSPECV_POOL_SECTION 201)
130 (UNSPECV_POOL_ALIGN 202)
131 (UNSPECV_POOL_ENTRY 203)
132 (UNSPECV_MAIN_POOL 300)
145 ; Registers with special meaning
149 ; Sibling call register.
151 ; Literal pool base register.
153 ; Return address register.
155 ; Condition code register.
157 ; Thread local storage pointer register.
161 ; Hardware register names
165 ; General purpose registers
167 ; Floating point registers.
173 ;; PFPO GPR0 argument format
178 ; PFPO operation type
179 (PFPO_CONVERT 0x1000000)
181 (PFPO_OP_TYPE_SF 0x5)
182 (PFPO_OP_TYPE_DF 0x6)
183 (PFPO_OP_TYPE_TF 0x7)
184 (PFPO_OP_TYPE_SD 0x8)
185 (PFPO_OP_TYPE_DD 0x9)
186 (PFPO_OP_TYPE_TD 0xa)
187 ; Bitposition of operand types
188 (PFPO_OP0_TYPE_SHIFT 16)
189 (PFPO_OP1_TYPE_SHIFT 8)
193 ;; Instruction operand type as used in the Principles of Operation.
194 ;; Used to determine defaults for length and other attribute values.
196 (define_attr "op_type"
197 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
200 ;; Instruction type attribute used for scheduling.
202 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
203 cs,vs,store,sem,idiv,
204 imulhi,imulsi,imuldi,
205 branch,jsr,fsimptf,fsimpdf,fsimpsf,
206 floadtf,floaddf,floadsf,fstoredf,fstoresf,
207 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
208 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
209 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
210 itoftf, itofdf, itofsf, itofdd, itoftd,
211 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
212 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
214 (cond [(eq_attr "op_type" "NN") (const_string "other")
215 (eq_attr "op_type" "SS") (const_string "cs")]
216 (const_string "integer")))
218 ;; Another attribute used for scheduling purposes:
219 ;; agen: Instruction uses the address generation unit
220 ;; reg: Instruction does not use the agen unit
222 (define_attr "atype" "agen,reg"
223 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
225 (const_string "agen")))
227 ;; Properties concerning Z10 execution grouping and value forwarding.
228 ;; z10_super: instruction is superscalar.
229 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
230 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
231 ;; target register. It can forward this value to a second instruction that reads
232 ;; the same register if that second instruction is issued in the same group.
233 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
234 ;; instruction in the S pipe writes to the register, then the T instruction
235 ;; can immediately read the new value.
236 ;; z10_fr: union of Z10_fwd and z10_rec.
237 ;; z10_c: second operand of instruction is a register and read with complemented bits.
238 ;; z10_cobra: its a compare and branch instruction
240 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
243 (define_attr "z10prop" "none,
244 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
245 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
247 z10_fr, z10_fr_A3, z10_fr_E1,
249 (const_string "none"))
254 (define_attr "length" ""
255 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
256 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
260 ;; Processor type. This attribute must exactly match the processor_type
261 ;; enumeration in s390.h. The current machine description does not
262 ;; distinguish between g5 and g6, but there are differences between the two
263 ;; CPUs could in theory be modeled.
265 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
266 (const (symbol_ref "s390_tune")))
268 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
269 (const_string "standard"))
271 (define_attr "enabled" ""
272 (cond [(eq_attr "cpu_facility" "standard")
275 (and (eq_attr "cpu_facility" "ieee")
276 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
279 (and (eq_attr "cpu_facility" "zarch")
280 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
283 (and (eq_attr "cpu_facility" "longdisp")
284 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
287 (and (eq_attr "cpu_facility" "extimm")
288 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
291 (and (eq_attr "cpu_facility" "dfp")
292 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
295 (and (eq_attr "cpu_facility" "z10")
296 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
300 ;; Pipeline description for z900. For lack of anything better,
301 ;; this description is also used for the g5 and g6.
304 ;; Pipeline description for z990, z9-109 and z9-ec.
307 ;; Pipeline description for z10
311 (include "predicates.md")
313 ;; Constraint definitions
314 (include "constraints.md")
321 ;; These mode iterators allow floating point patterns to be generated from the
323 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
324 (SD "TARGET_HARD_DFP")])
325 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
326 (define_mode_iterator FPALL [TF DF SF TD DD SD])
327 (define_mode_iterator BFP [TF DF SF])
328 (define_mode_iterator DFP [TD DD])
329 (define_mode_iterator DFP_ALL [TD DD SD])
330 (define_mode_iterator DSF [DF SF])
331 (define_mode_iterator SD_SF [SF SD])
332 (define_mode_iterator DD_DF [DF DD])
333 (define_mode_iterator TD_TF [TF TD])
335 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
336 ;; from the same template.
337 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
339 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
340 ;; from the same template.
341 (define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
342 (define_mode_iterator DSI [DI SI])
344 ;; These mode iterators allow :P to be used for patterns that operate on
345 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
346 (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
347 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
349 ;; This mode iterator allows the QI and HI patterns to be defined from
350 ;; the same template.
351 (define_mode_iterator HQI [HI QI])
353 ;; This mode iterator allows the integer patterns to be defined from the
355 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
356 (define_mode_iterator INTALL [TI DI SI HI QI])
358 ;; This iterator allows to unify all 'bCOND' expander patterns.
359 (define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
360 ordered uneq unlt ungt unle unge ltgt])
362 ;; This iterator allows to unify all 'sCOND' patterns.
363 (define_code_iterator SCOND [ltu gtu leu geu])
365 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
366 ;; the same template.
367 (define_code_iterator SHIFT [ashift lshiftrt])
369 ;; This iterator and attribute allow to combine most atomic operations.
370 (define_code_iterator ATOMIC [and ior xor plus minus mult])
371 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
372 (plus "add") (minus "sub") (mult "nand")])
374 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
375 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
376 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
378 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
379 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
381 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
383 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
384 ;; Likewise for "<RXe>".
385 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
386 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
388 ;; The decimal floating point variants of add, sub, div and mul support 3
389 ;; fp register operands. The following attributes allow to merge the bfp and
390 ;; dfp variants in a single insn definition.
392 ;; This attribute is used to set op_type accordingly.
393 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
394 (DD "RRR") (SD "RRR")])
396 ;; This attribute is used in the operand constraint list in order to have the
397 ;; first and the second operand match for bfp modes.
398 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
400 ;; This attribute is used in the operand list of the instruction to have an
401 ;; additional operand for the dfp instructions.
402 (define_mode_attr op1 [(TF "") (DF "") (SF "")
403 (TD "%1,") (DD "%1,") (SD "%1,")])
406 ;; This attribute is used in the operand constraint list
407 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
408 ;; TFmode values are represented by a fp register pair. Since the
409 ;; sign bit instructions only handle single source and target fp registers
410 ;; these instructions can only be used for TFmode values if the source and
411 ;; target operand uses the same fp register.
412 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
414 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
415 ;; This is used to disable the memory alternative in TFmode patterns.
416 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
418 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
419 ;; within instruction mnemonics.
420 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
422 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
423 ;; modes and to an empty string for bfp modes.
424 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
426 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
427 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
428 ;; version only operates on one register.
429 (define_mode_attr d0 [(DI "d") (SI "0")])
431 ;; In combination with d0 this allows to combine instructions of which the 31bit
432 ;; version only operates on one register. The DImode version needs an additional
433 ;; register for the assembler output.
434 (define_mode_attr 1 [(DI "%1,") (SI "")])
436 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
437 ;; 'ashift' and "srdl" in 'lshiftrt'.
438 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
440 ;; In SHIFT templates, this attribute holds the correct standard name for the
441 ;; pattern itself and the corresponding function calls.
442 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
444 ;; This attribute handles differences in the instruction 'type' and will result
445 ;; in "RRE" for DImode and "RR" for SImode.
446 (define_mode_attr E [(DI "E") (SI "")])
448 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
449 ;; to result in "RXY" for DImode and "RX" for SImode.
450 (define_mode_attr Y [(DI "Y") (SI "")])
452 ;; This attribute handles differences in the instruction 'type' and will result
453 ;; in "RSE" for TImode and "RS" for DImode.
454 (define_mode_attr TE [(TI "E") (DI "")])
456 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
457 ;; and "lcr" in SImode.
458 (define_mode_attr g [(DI "g") (SI "")])
460 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
461 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
462 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
463 ;; variant for long displacements.
464 (define_mode_attr y [(DI "g") (SI "y")])
466 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
467 ;; and "cds" in DImode.
468 (define_mode_attr tg [(TI "g") (DI "")])
470 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
471 ;; and "cfdbr" in SImode.
472 (define_mode_attr gf [(DI "g") (SI "f")])
474 ;; ICM mask required to load MODE value into the lowest subreg
475 ;; of a SImode register.
476 (define_mode_attr icm_lo [(HI "3") (QI "1")])
478 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
479 ;; HImode and "llgc" in QImode.
480 (define_mode_attr hc [(HI "h") (QI "c")])
482 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
484 (define_mode_attr DBL [(DI "TI") (SI "DI")])
486 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
487 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
488 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
490 ;; Maximum unsigned integer that fits in MODE.
491 (define_mode_attr max_uint [(HI "65535") (QI "255")])
494 ;;- Compare instructions.
497 (define_expand "cmp<mode>"
498 [(set (reg:CC CC_REGNUM)
499 (compare:CC (match_operand:GPR 0 "register_operand" "")
500 (match_operand:GPR 1 "general_operand" "")))]
503 s390_compare_op0 = operands[0];
504 s390_compare_op1 = operands[1];
508 (define_expand "cmp<mode>"
509 [(set (reg:CC CC_REGNUM)
510 (compare:CC (match_operand:FP 0 "register_operand" "")
511 (match_operand:FP 1 "general_operand" "")))]
514 s390_compare_op0 = operands[0];
515 s390_compare_op1 = operands[1];
520 ; Test-under-Mask instructions
522 (define_insn "*tmqi_mem"
523 [(set (reg CC_REGNUM)
524 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
525 (match_operand:QI 1 "immediate_operand" "n,n"))
526 (match_operand:QI 2 "immediate_operand" "n,n")))]
527 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
531 [(set_attr "op_type" "SI,SIY")
532 (set_attr "z10prop" "z10_super,z10_super")])
534 (define_insn "*tmdi_reg"
535 [(set (reg CC_REGNUM)
536 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
537 (match_operand:DI 1 "immediate_operand"
538 "N0HD0,N1HD0,N2HD0,N3HD0"))
539 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
541 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
542 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
548 [(set_attr "op_type" "RI")
549 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
551 (define_insn "*tmsi_reg"
552 [(set (reg CC_REGNUM)
553 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
554 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
555 (match_operand:SI 2 "immediate_operand" "n,n")))]
556 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
557 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
561 [(set_attr "op_type" "RI")])
563 (define_insn "*tm<mode>_full"
564 [(set (reg CC_REGNUM)
565 (compare (match_operand:HQI 0 "register_operand" "d")
566 (match_operand:HQI 1 "immediate_operand" "n")))]
567 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
569 [(set_attr "op_type" "RI")])
573 ; Load-and-Test instructions
576 ; tst(di|si) instruction pattern(s).
578 (define_insn "*tstdi_sign"
579 [(set (reg CC_REGNUM)
583 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
584 (const_int 32)) (const_int 32))
585 (match_operand:DI 1 "const0_operand" "")))
586 (set (match_operand:DI 2 "register_operand" "=d,d")
587 (sign_extend:DI (match_dup 0)))]
588 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
591 [(set_attr "op_type" "RRE,RXY")
592 (set_attr "cpu_facility" "*,z10")
593 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
596 (define_insn "*tst<mode>_extimm"
597 [(set (reg CC_REGNUM)
598 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
599 (match_operand:GPR 1 "const0_operand" "")))
600 (set (match_operand:GPR 2 "register_operand" "=d,d")
602 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
606 [(set_attr "op_type" "RR<E>,RXY")
607 (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ])
610 (define_insn "*tst<mode>_cconly_extimm"
611 [(set (reg CC_REGNUM)
612 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
613 (match_operand:GPR 1 "const0_operand" "")))
614 (clobber (match_scratch:GPR 2 "=X,d"))]
615 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
619 [(set_attr "op_type" "RR<E>,RXY")
620 (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")])
622 (define_insn "*tstdi"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:DI 0 "register_operand" "d")
625 (match_operand:DI 1 "const0_operand" "")))
626 (set (match_operand:DI 2 "register_operand" "=d")
628 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
630 [(set_attr "op_type" "RRE")
631 (set_attr "z10prop" "z10_fr_E1")])
633 (define_insn "*tstsi"
634 [(set (reg CC_REGNUM)
635 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
636 (match_operand:SI 1 "const0_operand" "")))
637 (set (match_operand:SI 2 "register_operand" "=d,d,d")
639 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
644 [(set_attr "op_type" "RR,RS,RSY")
645 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
647 (define_insn "*tstsi_cconly"
648 [(set (reg CC_REGNUM)
649 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
650 (match_operand:SI 1 "const0_operand" "")))
651 (clobber (match_scratch:SI 2 "=X,d,d"))]
652 "s390_match_ccmode(insn, CCSmode)"
657 [(set_attr "op_type" "RR,RS,RSY")
658 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
660 (define_insn "*tstdi_cconly_31"
661 [(set (reg CC_REGNUM)
662 (compare (match_operand:DI 0 "register_operand" "d")
663 (match_operand:DI 1 "const0_operand" "")))]
664 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
666 [(set_attr "op_type" "RS")
667 (set_attr "atype" "reg")])
670 (define_insn "*tst<mode>_cconly2"
671 [(set (reg CC_REGNUM)
672 (compare (match_operand:GPR 0 "register_operand" "d")
673 (match_operand:GPR 1 "const0_operand" "")))]
674 "s390_match_ccmode(insn, CCSmode)"
676 [(set_attr "op_type" "RR<E>")
677 (set_attr "z10prop" "z10_fr_E1")])
679 ; tst(hi|qi) instruction pattern(s).
681 (define_insn "*tst<mode>CCT"
682 [(set (reg CC_REGNUM)
683 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
684 (match_operand:HQI 1 "const0_operand" "")))
685 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
687 "s390_match_ccmode(insn, CCTmode)"
690 icmy\t%2,<icm_lo>,%S0
692 [(set_attr "op_type" "RS,RSY,RI")
693 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
695 (define_insn "*tsthiCCT_cconly"
696 [(set (reg CC_REGNUM)
697 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
698 (match_operand:HI 1 "const0_operand" "")))
699 (clobber (match_scratch:HI 2 "=d,d,X"))]
700 "s390_match_ccmode(insn, CCTmode)"
705 [(set_attr "op_type" "RS,RSY,RI")
706 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
708 (define_insn "*tstqiCCT_cconly"
709 [(set (reg CC_REGNUM)
710 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
711 (match_operand:QI 1 "const0_operand" "")))]
712 "s390_match_ccmode(insn, CCTmode)"
717 [(set_attr "op_type" "SI,SIY,RI")
718 (set_attr "z10prop" "z10_super,z10_super,*")])
720 (define_insn "*tst<mode>"
721 [(set (reg CC_REGNUM)
722 (compare (match_operand:HQI 0 "s_operand" "Q,S")
723 (match_operand:HQI 1 "const0_operand" "")))
724 (set (match_operand:HQI 2 "register_operand" "=d,d")
726 "s390_match_ccmode(insn, CCSmode)"
729 icmy\t%2,<icm_lo>,%S0"
730 [(set_attr "op_type" "RS,RSY")
731 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
733 (define_insn "*tst<mode>_cconly"
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:HQI 0 "s_operand" "Q,S")
736 (match_operand:HQI 1 "const0_operand" "")))
737 (clobber (match_scratch:HQI 2 "=d,d"))]
738 "s390_match_ccmode(insn, CCSmode)"
741 icmy\t%2,<icm_lo>,%S0"
742 [(set_attr "op_type" "RS,RSY")
743 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
746 ; Compare (equality) instructions
748 (define_insn "*cmpdi_cct"
749 [(set (reg CC_REGNUM)
750 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
751 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
752 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
759 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
760 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
762 (define_insn "*cmpsi_cct"
763 [(set (reg CC_REGNUM)
764 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
765 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
766 "s390_match_ccmode (insn, CCTmode)"
774 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
775 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super,z10_super,*")])
777 ; Compare (signed) instructions
779 (define_insn "*cmpdi_ccs_sign"
780 [(set (reg CC_REGNUM)
781 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
783 (match_operand:DI 0 "register_operand" "d, d,d")))]
784 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
789 [(set_attr "op_type" "RRE,RXY,RIL")
790 (set_attr "z10prop" "z10_c,*,*")
791 (set_attr "type" "*,*,larl")])
795 (define_insn "*cmpsi_ccs_sign"
796 [(set (reg CC_REGNUM)
797 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
798 (match_operand:SI 0 "register_operand" "d,d,d")))]
799 "s390_match_ccmode(insn, CCSRmode)"
804 [(set_attr "op_type" "RX,RXY,RIL")
805 (set_attr "cpu_facility" "*,*,z10")
806 (set_attr "type" "*,*,larl")])
808 (define_insn "*cmphi_ccs_z10"
809 [(set (reg CC_REGNUM)
810 (compare (match_operand:HI 0 "s_operand" "Q")
811 (match_operand:HI 1 "immediate_operand" "K")))]
812 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
814 [(set_attr "op_type" "SIL")])
816 (define_insn "*cmpdi_ccs_signhi_rl"
817 [(set (reg CC_REGNUM)
818 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
819 (match_operand:GPR 0 "register_operand" "d,d")))]
820 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
824 [(set_attr "op_type" "RXY,RIL")
825 (set_attr "type" "*,larl")])
827 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
828 (define_insn "*cmp<mode>_ccs"
829 [(set (reg CC_REGNUM)
830 (compare (match_operand:GPR 0 "nonimmediate_operand"
832 (match_operand:GPR 1 "general_operand"
834 "s390_match_ccmode(insn, CCSmode)"
843 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
844 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
845 (set_attr "type" "*,*,*,*,*,*,larl")
846 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
849 ; Compare (unsigned) instructions
851 (define_insn "*cmpsi_ccu_zerohi_rlsi"
852 [(set (reg CC_REGNUM)
853 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
854 "larl_operand" "X")))
855 (match_operand:SI 0 "register_operand" "d")))]
856 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
858 [(set_attr "op_type" "RIL")
859 (set_attr "type" "larl")])
862 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
863 [(set (reg CC_REGNUM)
864 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
865 "larl_operand" "X")))
866 (match_operand:GPR 0 "register_operand" "d")))]
867 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
869 [(set_attr "op_type" "RIL")
870 (set_attr "type" "larl")
871 (set_attr "z10prop" "z10_super")])
873 (define_insn "*cmpdi_ccu_zero"
874 [(set (reg CC_REGNUM)
875 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
877 (match_operand:DI 0 "register_operand" "d, d,d")))]
878 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
883 [(set_attr "op_type" "RRE,RXY,RIL")
884 (set_attr "cpu_facility" "*,*,z10")
885 (set_attr "type" "*,*,larl")
886 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
888 (define_insn "*cmpdi_ccu"
889 [(set (reg CC_REGNUM)
890 (compare (match_operand:DI 0 "nonimmediate_operand"
892 (match_operand:DI 1 "general_operand"
893 "d,Op,b,D,RT,BQ,Q")))]
894 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
903 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
904 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
905 (set_attr "type" "*,*,larl,*,*,*,*")
906 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
908 (define_insn "*cmpsi_ccu"
909 [(set (reg CC_REGNUM)
910 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
911 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
912 "s390_match_ccmode (insn, CCUmode)"
922 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
923 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
924 (set_attr "type" "*,*,larl,*,*,*,*,*")
925 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
927 (define_insn "*cmphi_ccu"
928 [(set (reg CC_REGNUM)
929 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
930 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
931 "s390_match_ccmode (insn, CCUmode)
932 && !register_operand (operands[1], HImode)"
939 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
940 (set_attr "cpu_facility" "*,*,z10,*,*")
941 (set_attr "z10prop" "*,*,z10_super,*,*")])
943 (define_insn "*cmpqi_ccu"
944 [(set (reg CC_REGNUM)
945 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
946 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
947 "s390_match_ccmode (insn, CCUmode)
948 && !register_operand (operands[1], QImode)"
956 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
957 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
960 ; Block compare (CLC) instruction patterns.
963 [(set (reg CC_REGNUM)
964 (compare (match_operand:BLK 0 "memory_operand" "Q")
965 (match_operand:BLK 1 "memory_operand" "Q")))
966 (use (match_operand 2 "const_int_operand" "n"))]
967 "s390_match_ccmode (insn, CCUmode)
968 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
969 "clc\t%O0(%2,%R0),%S1"
970 [(set_attr "op_type" "SS")])
973 [(set (reg CC_REGNUM)
974 (compare (match_operand 0 "memory_operand" "")
975 (match_operand 1 "memory_operand" "")))]
977 && s390_match_ccmode (insn, CCUmode)
978 && GET_MODE (operands[0]) == GET_MODE (operands[1])
979 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
981 [(set (match_dup 0) (match_dup 1))
982 (use (match_dup 2))])]
984 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
985 operands[0] = adjust_address (operands[0], BLKmode, 0);
986 operands[1] = adjust_address (operands[1], BLKmode, 0);
988 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
989 operands[0], operands[1]);
990 operands[0] = SET_DEST (PATTERN (curr_insn));
994 ; (TF|DF|SF|TD|DD|SD) instructions
996 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
997 (define_insn "*cmp<mode>_ccs_0"
998 [(set (reg CC_REGNUM)
999 (compare (match_operand:FP 0 "register_operand" "f")
1000 (match_operand:FP 1 "const0_operand" "")))]
1001 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1002 "lt<xde><bt>r\t%0,%0"
1003 [(set_attr "op_type" "RRE")
1004 (set_attr "type" "fsimp<mode>")])
1006 ; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr
1007 (define_insn "*cmp<mode>_ccs"
1008 [(set (reg CC_REGNUM)
1009 (compare (match_operand:FP 0 "register_operand" "f,f")
1010 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1011 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1015 [(set_attr "op_type" "RRE,RXE")
1016 (set_attr "type" "fsimp<mode>")])
1019 ; Compare and Branch instructions
1021 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1022 ; The following instructions do a complementary access of their second
1023 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1024 (define_insn "*cmp_and_br_signed_<mode>"
1026 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1027 [(match_operand:GPR 1 "register_operand" "d,d")
1028 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1029 (label_ref (match_operand 3 "" ""))
1031 (clobber (reg:CC CC_REGNUM))]
1034 if (get_attr_length (insn) == 6)
1035 return which_alternative ?
1036 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1038 return which_alternative ?
1039 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1041 [(set_attr "op_type" "RIE")
1042 (set_attr "type" "branch")
1043 (set_attr "z10prop" "z10_cobra,z10_super")
1044 (set (attr "length")
1045 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1046 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1047 ; 10 byte for cgr/jg
1049 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1050 ; The following instructions do a complementary access of their second
1051 ; operand (z10 only): clrj, clgrj, clr, clgr
1052 (define_insn "*cmp_and_br_unsigned_<mode>"
1054 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1055 [(match_operand:GPR 1 "register_operand" "d,d")
1056 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1057 (label_ref (match_operand 3 "" ""))
1059 (clobber (reg:CC CC_REGNUM))]
1062 if (get_attr_length (insn) == 6)
1063 return which_alternative ?
1064 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1066 return which_alternative ?
1067 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1069 [(set_attr "op_type" "RIE")
1070 (set_attr "type" "branch")
1071 (set_attr "z10prop" "z10_cobra,z10_super")
1072 (set (attr "length")
1073 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1074 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1075 ; 10 byte for clgr/jg
1078 ;;- Move instructions.
1082 ; movti instruction pattern(s).
1085 (define_insn "movti"
1086 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1087 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1094 [(set_attr "op_type" "RSY,RSY,*,*")
1095 (set_attr "type" "lm,stm,*,*")])
1098 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1099 (match_operand:TI 1 "general_operand" ""))]
1100 "TARGET_64BIT && reload_completed
1101 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1102 [(set (match_dup 2) (match_dup 4))
1103 (set (match_dup 3) (match_dup 5))]
1105 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1106 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1107 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1108 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1112 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1113 (match_operand:TI 1 "general_operand" ""))]
1114 "TARGET_64BIT && reload_completed
1115 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1116 [(set (match_dup 2) (match_dup 4))
1117 (set (match_dup 3) (match_dup 5))]
1119 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1120 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1121 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1122 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1126 [(set (match_operand:TI 0 "register_operand" "")
1127 (match_operand:TI 1 "memory_operand" ""))]
1128 "TARGET_64BIT && reload_completed
1129 && !s_operand (operands[1], VOIDmode)"
1130 [(set (match_dup 0) (match_dup 1))]
1132 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1133 s390_load_address (addr, XEXP (operands[1], 0));
1134 operands[1] = replace_equiv_address (operands[1], addr);
1139 ; Patterns used for secondary reloads
1142 ; z10 provides move instructions accepting larl memory operands.
1143 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1144 ; These patterns are also used for unaligned SI and DI accesses.
1146 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1147 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1148 (match_operand:INTALL 1 "register_operand" "=d")
1149 (match_operand:P 2 "register_operand" "=&a")])]
1152 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1156 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1157 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1158 (match_operand:INTALL 1 "memory_operand" "")
1159 (match_operand:P 2 "register_operand" "=a")])]
1162 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1166 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1167 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1168 (match_operand:FPALL 1 "register_operand" "=d")
1169 (match_operand:P 2 "register_operand" "=&a")])]
1172 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1176 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1177 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1178 (match_operand:FPALL 1 "memory_operand" "")
1179 (match_operand:P 2 "register_operand" "=a")])]
1182 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1186 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1187 [(parallel [(match_operand:P 0 "register_operand" "=d")
1188 (match_operand:P 1 "larl_operand" "")
1189 (match_operand:P 2 "register_operand" "=a")])]
1192 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1196 ; Handles loading a PLUS (load address) expression
1198 (define_expand "reload<mode>_plus"
1199 [(parallel [(match_operand:P 0 "register_operand" "=a")
1200 (match_operand:P 1 "s390_plus_operand" "")
1201 (match_operand:P 2 "register_operand" "=&a")])]
1204 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1208 ; Handles assessing a non-offsetable memory address
1210 (define_expand "reload<mode>_nonoffmem_in"
1211 [(parallel [(match_operand 0 "register_operand" "")
1212 (match_operand 1 "" "")
1213 (match_operand:P 2 "register_operand" "=&a")])]
1216 gcc_assert (MEM_P (operands[1]));
1217 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1218 operands[1] = replace_equiv_address (operands[1], operands[2]);
1219 emit_move_insn (operands[0], operands[1]);
1223 (define_expand "reload<mode>_nonoffmem_out"
1224 [(parallel [(match_operand 0 "" "")
1225 (match_operand 1 "register_operand" "")
1226 (match_operand:P 2 "register_operand" "=&a")])]
1229 gcc_assert (MEM_P (operands[0]));
1230 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1231 operands[0] = replace_equiv_address (operands[0], operands[2]);
1232 emit_move_insn (operands[0], operands[1]);
1236 (define_expand "reload<mode>_PIC_addr"
1237 [(parallel [(match_operand 0 "register_operand" "=d")
1238 (match_operand 1 "larl_operand" "")
1239 (match_operand:P 2 "register_operand" "=a")])]
1242 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1243 emit_move_insn (operands[0], new_rtx);
1247 ; movdi instruction pattern(s).
1250 (define_expand "movdi"
1251 [(set (match_operand:DI 0 "general_operand" "")
1252 (match_operand:DI 1 "general_operand" ""))]
1255 /* Handle symbolic constants. */
1257 && (SYMBOLIC_CONST (operands[1])
1258 || (GET_CODE (operands[1]) == PLUS
1259 && XEXP (operands[1], 0) == pic_offset_table_rtx
1260 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1261 emit_symbolic_move (operands);
1264 (define_insn "*movdi_larl"
1265 [(set (match_operand:DI 0 "register_operand" "=d")
1266 (match_operand:DI 1 "larl_operand" "X"))]
1268 && !FP_REG_P (operands[0])"
1270 [(set_attr "op_type" "RIL")
1271 (set_attr "type" "larl")
1272 (set_attr "z10prop" "z10_super_A1")])
1274 (define_insn "*movdi_64"
1275 [(set (match_operand:DI 0 "nonimmediate_operand"
1276 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1277 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1278 (match_operand:DI 1 "general_operand"
1279 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1280 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1309 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1310 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1311 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1312 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1314 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1315 z10,*,*,*,*,*,longdisp,*,longdisp,
1317 (set_attr "z10prop" "z10_fwd_A1,
1346 [(set (match_operand:DI 0 "register_operand" "")
1347 (match_operand:DI 1 "register_operand" ""))]
1348 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1349 [(set (match_dup 2) (match_dup 3))
1350 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1351 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1352 "operands[2] = gen_lowpart (SImode, operands[0]);
1353 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1356 [(set (match_operand:DI 0 "register_operand" "")
1357 (match_operand:DI 1 "register_operand" ""))]
1358 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1359 && dead_or_set_p (insn, operands[1])"
1360 [(set (match_dup 3) (match_dup 2))
1361 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1362 (set (match_dup 4) (match_dup 2))]
1363 "operands[2] = gen_lowpart (SImode, operands[1]);
1364 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1367 [(set (match_operand:DI 0 "register_operand" "")
1368 (match_operand:DI 1 "register_operand" ""))]
1369 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1370 && !dead_or_set_p (insn, operands[1])"
1371 [(set (match_dup 3) (match_dup 2))
1372 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1373 (set (match_dup 4) (match_dup 2))
1374 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1375 "operands[2] = gen_lowpart (SImode, operands[1]);
1376 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1378 (define_insn "*movdi_31"
1379 [(set (match_operand:DI 0 "nonimmediate_operand"
1380 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1381 (match_operand:DI 1 "general_operand"
1382 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1397 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1398 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1399 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1401 ; For a load from a symbol ref we can use one of the target registers
1402 ; together with larl to load the address.
1404 [(set (match_operand:DI 0 "register_operand" "")
1405 (match_operand:DI 1 "memory_operand" ""))]
1406 "!TARGET_64BIT && reload_completed && TARGET_Z10
1407 && larl_operand (XEXP (operands[1], 0), SImode)"
1408 [(set (match_dup 2) (match_dup 3))
1409 (set (match_dup 0) (match_dup 1))]
1411 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1412 operands[3] = XEXP (operands[1], 0);
1413 operands[1] = replace_equiv_address (operands[1], operands[2]);
1417 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1418 (match_operand:DI 1 "general_operand" ""))]
1419 "!TARGET_64BIT && reload_completed
1420 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1421 [(set (match_dup 2) (match_dup 4))
1422 (set (match_dup 3) (match_dup 5))]
1424 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1425 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1426 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1427 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1431 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1432 (match_operand:DI 1 "general_operand" ""))]
1433 "!TARGET_64BIT && reload_completed
1434 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1435 [(set (match_dup 2) (match_dup 4))
1436 (set (match_dup 3) (match_dup 5))]
1438 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1439 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1440 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1441 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1445 [(set (match_operand:DI 0 "register_operand" "")
1446 (match_operand:DI 1 "memory_operand" ""))]
1447 "!TARGET_64BIT && reload_completed
1448 && !FP_REG_P (operands[0])
1449 && !s_operand (operands[1], VOIDmode)"
1450 [(set (match_dup 0) (match_dup 1))]
1452 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1453 s390_load_address (addr, XEXP (operands[1], 0));
1454 operands[1] = replace_equiv_address (operands[1], addr);
1458 [(set (match_operand:DI 0 "register_operand" "")
1459 (mem:DI (match_operand 1 "address_operand" "")))]
1461 && !FP_REG_P (operands[0])
1462 && GET_CODE (operands[1]) == SYMBOL_REF
1463 && CONSTANT_POOL_ADDRESS_P (operands[1])
1464 && get_pool_mode (operands[1]) == DImode
1465 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1466 [(set (match_dup 0) (match_dup 2))]
1467 "operands[2] = get_pool_constant (operands[1]);")
1469 (define_insn "*la_64"
1470 [(set (match_operand:DI 0 "register_operand" "=d,d")
1471 (match_operand:QI 1 "address_operand" "U,W"))]
1476 [(set_attr "op_type" "RX,RXY")
1477 (set_attr "type" "la")
1478 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1482 [(set (match_operand:DI 0 "register_operand" "")
1483 (match_operand:QI 1 "address_operand" ""))
1484 (clobber (reg:CC CC_REGNUM))])]
1486 && preferred_la_operand_p (operands[1], const0_rtx)"
1487 [(set (match_dup 0) (match_dup 1))]
1491 [(set (match_operand:DI 0 "register_operand" "")
1492 (match_operand:DI 1 "register_operand" ""))
1495 (plus:DI (match_dup 0)
1496 (match_operand:DI 2 "nonmemory_operand" "")))
1497 (clobber (reg:CC CC_REGNUM))])]
1499 && !reg_overlap_mentioned_p (operands[0], operands[2])
1500 && preferred_la_operand_p (operands[1], operands[2])"
1501 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1505 ; movsi instruction pattern(s).
1508 (define_expand "movsi"
1509 [(set (match_operand:SI 0 "general_operand" "")
1510 (match_operand:SI 1 "general_operand" ""))]
1513 /* Handle symbolic constants. */
1515 && (SYMBOLIC_CONST (operands[1])
1516 || (GET_CODE (operands[1]) == PLUS
1517 && XEXP (operands[1], 0) == pic_offset_table_rtx
1518 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1519 emit_symbolic_move (operands);
1522 (define_insn "*movsi_larl"
1523 [(set (match_operand:SI 0 "register_operand" "=d")
1524 (match_operand:SI 1 "larl_operand" "X"))]
1525 "!TARGET_64BIT && TARGET_CPU_ZARCH
1526 && !FP_REG_P (operands[0])"
1528 [(set_attr "op_type" "RIL")
1529 (set_attr "type" "larl")
1530 (set_attr "z10prop" "z10_super_A1")])
1532 (define_insn "*movsi_zarch"
1533 [(set (match_operand:SI 0 "nonimmediate_operand"
1534 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1535 (match_operand:SI 1 "general_operand"
1536 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1561 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1562 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1563 (set_attr "type" "*,
1585 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1586 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1587 (set_attr "z10prop" "z10_fwd_A1,
1610 (define_insn "*movsi_esa"
1611 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1612 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1626 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1627 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1628 (set_attr "z10prop" "z10_fwd_A1,
1642 [(set (match_operand:SI 0 "register_operand" "")
1643 (mem:SI (match_operand 1 "address_operand" "")))]
1644 "!FP_REG_P (operands[0])
1645 && GET_CODE (operands[1]) == SYMBOL_REF
1646 && CONSTANT_POOL_ADDRESS_P (operands[1])
1647 && get_pool_mode (operands[1]) == SImode
1648 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1649 [(set (match_dup 0) (match_dup 2))]
1650 "operands[2] = get_pool_constant (operands[1]);")
1652 (define_insn "*la_31"
1653 [(set (match_operand:SI 0 "register_operand" "=d,d")
1654 (match_operand:QI 1 "address_operand" "U,W"))]
1655 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1659 [(set_attr "op_type" "RX,RXY")
1660 (set_attr "type" "la")
1661 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1665 [(set (match_operand:SI 0 "register_operand" "")
1666 (match_operand:QI 1 "address_operand" ""))
1667 (clobber (reg:CC CC_REGNUM))])]
1669 && preferred_la_operand_p (operands[1], const0_rtx)"
1670 [(set (match_dup 0) (match_dup 1))]
1674 [(set (match_operand:SI 0 "register_operand" "")
1675 (match_operand:SI 1 "register_operand" ""))
1678 (plus:SI (match_dup 0)
1679 (match_operand:SI 2 "nonmemory_operand" "")))
1680 (clobber (reg:CC CC_REGNUM))])]
1682 && !reg_overlap_mentioned_p (operands[0], operands[2])
1683 && preferred_la_operand_p (operands[1], operands[2])"
1684 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1687 (define_insn "*la_31_and"
1688 [(set (match_operand:SI 0 "register_operand" "=d,d")
1689 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1690 (const_int 2147483647)))]
1695 [(set_attr "op_type" "RX,RXY")
1696 (set_attr "type" "la")
1697 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1699 (define_insn_and_split "*la_31_and_cc"
1700 [(set (match_operand:SI 0 "register_operand" "=d")
1701 (and:SI (match_operand:QI 1 "address_operand" "p")
1702 (const_int 2147483647)))
1703 (clobber (reg:CC CC_REGNUM))]
1706 "&& reload_completed"
1708 (and:SI (match_dup 1) (const_int 2147483647)))]
1710 [(set_attr "op_type" "RX")
1711 (set_attr "type" "la")])
1713 (define_insn "force_la_31"
1714 [(set (match_operand:SI 0 "register_operand" "=d,d")
1715 (match_operand:QI 1 "address_operand" "U,W"))
1716 (use (const_int 0))]
1721 [(set_attr "op_type" "RX")
1722 (set_attr "type" "la")
1723 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1726 ; movhi instruction pattern(s).
1729 (define_expand "movhi"
1730 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1731 (match_operand:HI 1 "general_operand" ""))]
1734 /* Make it explicit that loading a register from memory
1735 always sign-extends (at least) to SImode. */
1736 if (optimize && can_create_pseudo_p ()
1737 && register_operand (operands[0], VOIDmode)
1738 && GET_CODE (operands[1]) == MEM)
1740 rtx tmp = gen_reg_rtx (SImode);
1741 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1742 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1743 operands[1] = gen_lowpart (HImode, tmp);
1747 (define_insn "*movhi"
1748 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1749 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1761 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1762 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1763 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1764 (set_attr "z10prop" "z10_fr_E1,
1775 [(set (match_operand:HI 0 "register_operand" "")
1776 (mem:HI (match_operand 1 "address_operand" "")))]
1777 "GET_CODE (operands[1]) == SYMBOL_REF
1778 && CONSTANT_POOL_ADDRESS_P (operands[1])
1779 && get_pool_mode (operands[1]) == HImode
1780 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1781 [(set (match_dup 0) (match_dup 2))]
1782 "operands[2] = get_pool_constant (operands[1]);")
1785 ; movqi instruction pattern(s).
1788 (define_expand "movqi"
1789 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1790 (match_operand:QI 1 "general_operand" ""))]
1793 /* On z/Architecture, zero-extending from memory to register
1794 is just as fast as a QImode load. */
1795 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1796 && register_operand (operands[0], VOIDmode)
1797 && GET_CODE (operands[1]) == MEM)
1799 rtx tmp = gen_reg_rtx (word_mode);
1800 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1801 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1802 operands[1] = gen_lowpart (QImode, tmp);
1806 (define_insn "*movqi"
1807 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
1808 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
1819 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
1820 (set_attr "type" "lr,*,*,*,store,store,store,store")
1821 (set_attr "z10prop" "z10_fr_E1,
1831 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1832 (mem:QI (match_operand 1 "address_operand" "")))]
1833 "GET_CODE (operands[1]) == SYMBOL_REF
1834 && CONSTANT_POOL_ADDRESS_P (operands[1])
1835 && get_pool_mode (operands[1]) == QImode
1836 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1837 [(set (match_dup 0) (match_dup 2))]
1838 "operands[2] = get_pool_constant (operands[1]);")
1841 ; movstrictqi instruction pattern(s).
1844 (define_insn "*movstrictqi"
1845 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1846 (match_operand:QI 1 "memory_operand" "R,T"))]
1851 [(set_attr "op_type" "RX,RXY")
1852 (set_attr "z10prop" "z10_super_E1,z10_super")])
1855 ; movstricthi instruction pattern(s).
1858 (define_insn "*movstricthi"
1859 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1860 (match_operand:HI 1 "memory_operand" "Q,S"))
1861 (clobber (reg:CC CC_REGNUM))]
1866 [(set_attr "op_type" "RS,RSY")
1867 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1870 ; movstrictsi instruction pattern(s).
1873 (define_insn "movstrictsi"
1874 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1875 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1882 [(set_attr "op_type" "RR,RX,RXY,RRE")
1883 (set_attr "type" "lr,load,load,*")
1884 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1887 ; mov(tf|td) instruction pattern(s).
1890 (define_expand "mov<mode>"
1891 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1892 (match_operand:TD_TF 1 "general_operand" ""))]
1896 (define_insn "*mov<mode>_64"
1897 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1898 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1909 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1910 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")])
1912 (define_insn "*mov<mode>_31"
1913 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1914 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1921 [(set_attr "op_type" "RRE,RRE,*,*")
1922 (set_attr "type" "fsimptf,fsimptf,*,*")])
1924 ; TFmode in GPRs splitters
1927 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1928 (match_operand:TD_TF 1 "general_operand" ""))]
1929 "TARGET_64BIT && reload_completed
1930 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1931 [(set (match_dup 2) (match_dup 4))
1932 (set (match_dup 3) (match_dup 5))]
1934 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1935 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1936 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1937 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1941 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1942 (match_operand:TD_TF 1 "general_operand" ""))]
1943 "TARGET_64BIT && reload_completed
1944 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1945 [(set (match_dup 2) (match_dup 4))
1946 (set (match_dup 3) (match_dup 5))]
1948 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1949 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1950 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1951 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1955 [(set (match_operand:TD_TF 0 "register_operand" "")
1956 (match_operand:TD_TF 1 "memory_operand" ""))]
1957 "TARGET_64BIT && reload_completed
1958 && !FP_REG_P (operands[0])
1959 && !s_operand (operands[1], VOIDmode)"
1960 [(set (match_dup 0) (match_dup 1))]
1962 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1963 s390_load_address (addr, XEXP (operands[1], 0));
1964 operands[1] = replace_equiv_address (operands[1], addr);
1967 ; TFmode in BFPs splitters
1970 [(set (match_operand:TD_TF 0 "register_operand" "")
1971 (match_operand:TD_TF 1 "memory_operand" ""))]
1972 "reload_completed && offsettable_memref_p (operands[1])
1973 && FP_REG_P (operands[0])"
1974 [(set (match_dup 2) (match_dup 4))
1975 (set (match_dup 3) (match_dup 5))]
1977 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1979 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1981 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
1982 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
1986 [(set (match_operand:TD_TF 0 "memory_operand" "")
1987 (match_operand:TD_TF 1 "register_operand" ""))]
1988 "reload_completed && offsettable_memref_p (operands[0])
1989 && FP_REG_P (operands[1])"
1990 [(set (match_dup 2) (match_dup 4))
1991 (set (match_dup 3) (match_dup 5))]
1993 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
1994 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
1995 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
1997 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2002 ; mov(df|dd) instruction pattern(s).
2005 (define_expand "mov<mode>"
2006 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2007 (match_operand:DD_DF 1 "general_operand" ""))]
2011 (define_insn "*mov<mode>_64dfp"
2012 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2013 "=f,f,f,d,f,f,R,T,d, d,RT")
2014 (match_operand:DD_DF 1 "general_operand"
2015 " G,f,d,f,R,T,f,f,d,RT, d"))]
2016 "TARGET_64BIT && TARGET_DFP"
2029 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
2030 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2031 fstoredf,fstoredf,lr,load,store")
2032 (set_attr "z10prop" "*,
2045 (define_insn "*mov<mode>_64"
2046 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
2047 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
2059 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
2060 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2061 fstore<mode>,fstore<mode>,lr,load,store")
2062 (set_attr "z10prop" "*,
2072 (define_insn "*mov<mode>_31"
2073 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2074 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2075 (match_operand:DD_DF 1 "general_operand"
2076 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2091 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2092 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2093 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2096 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2097 (match_operand:DD_DF 1 "general_operand" ""))]
2098 "!TARGET_64BIT && reload_completed
2099 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2100 [(set (match_dup 2) (match_dup 4))
2101 (set (match_dup 3) (match_dup 5))]
2103 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2104 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2105 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2106 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2110 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2111 (match_operand:DD_DF 1 "general_operand" ""))]
2112 "!TARGET_64BIT && reload_completed
2113 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2114 [(set (match_dup 2) (match_dup 4))
2115 (set (match_dup 3) (match_dup 5))]
2117 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2118 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2119 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2120 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2124 [(set (match_operand:DD_DF 0 "register_operand" "")
2125 (match_operand:DD_DF 1 "memory_operand" ""))]
2126 "!TARGET_64BIT && reload_completed
2127 && !FP_REG_P (operands[0])
2128 && !s_operand (operands[1], VOIDmode)"
2129 [(set (match_dup 0) (match_dup 1))]
2131 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2132 s390_load_address (addr, XEXP (operands[1], 0));
2133 operands[1] = replace_equiv_address (operands[1], addr);
2137 ; mov(sf|sd) instruction pattern(s).
2140 (define_insn "mov<mode>"
2141 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2142 "=f,f,f,f,R,T,d,d,d,R,T")
2143 (match_operand:SD_SF 1 "general_operand"
2144 " G,f,R,T,f,f,d,R,T,d,d"))]
2158 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
2159 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2160 fstore<mode>,fstore<mode>,lr,load,load,store,store")
2161 (set_attr "z10prop" "*,
2174 ; movcc instruction pattern
2177 (define_insn "movcc"
2178 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2179 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2189 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2190 (set_attr "type" "lr,*,*,store,store,load,load")
2191 (set_attr "z10prop" "z10_fr_E1,*,*,z10_super,z10_rec,z10_fwd_A3,z10_fwd_A3")])
2194 ; Block move (MVC) patterns.
2198 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2199 (match_operand:BLK 1 "memory_operand" "Q"))
2200 (use (match_operand 2 "const_int_operand" "n"))]
2201 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2202 "mvc\t%O0(%2,%R0),%S1"
2203 [(set_attr "op_type" "SS")])
2207 [(set (match_operand:BLK 0 "memory_operand" "")
2208 (match_operand:BLK 1 "memory_operand" ""))
2209 (use (match_operand 2 "const_int_operand" ""))])
2211 [(set (match_operand:BLK 3 "memory_operand" "")
2212 (match_operand:BLK 4 "memory_operand" ""))
2213 (use (match_operand 5 "const_int_operand" ""))])]
2214 "s390_offset_p (operands[0], operands[3], operands[2])
2215 && s390_offset_p (operands[1], operands[4], operands[2])
2216 && !s390_overlap_p (operands[0], operands[1],
2217 INTVAL (operands[2]) + INTVAL (operands[5]))
2218 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2220 [(set (match_dup 6) (match_dup 7))
2221 (use (match_dup 8))])]
2222 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2223 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2224 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2228 ; load_multiple pattern(s).
2230 ; ??? Due to reload problems with replacing registers inside match_parallel
2231 ; we currently support load_multiple/store_multiple only after reload.
2234 (define_expand "load_multiple"
2235 [(match_par_dup 3 [(set (match_operand 0 "" "")
2236 (match_operand 1 "" ""))
2237 (use (match_operand 2 "" ""))])]
2240 enum machine_mode mode;
2246 /* Support only loading a constant number of fixed-point registers from
2247 memory and only bother with this if more than two */
2248 if (GET_CODE (operands[2]) != CONST_INT
2249 || INTVAL (operands[2]) < 2
2250 || INTVAL (operands[2]) > 16
2251 || GET_CODE (operands[1]) != MEM
2252 || GET_CODE (operands[0]) != REG
2253 || REGNO (operands[0]) >= 16)
2256 count = INTVAL (operands[2]);
2257 regno = REGNO (operands[0]);
2258 mode = GET_MODE (operands[0]);
2259 if (mode != SImode && mode != word_mode)
2262 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2263 if (!can_create_pseudo_p ())
2265 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2267 from = XEXP (operands[1], 0);
2270 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2271 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2272 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2274 from = XEXP (XEXP (operands[1], 0), 0);
2275 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2282 from = force_reg (Pmode, XEXP (operands[1], 0));
2286 for (i = 0; i < count; i++)
2287 XVECEXP (operands[3], 0, i)
2288 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2289 change_address (operands[1], mode,
2290 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2293 (define_insn "*load_multiple_di"
2294 [(match_parallel 0 "load_multiple_operation"
2295 [(set (match_operand:DI 1 "register_operand" "=r")
2296 (match_operand:DI 2 "s_operand" "QS"))])]
2297 "reload_completed && word_mode == DImode"
2299 int words = XVECLEN (operands[0], 0);
2300 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2301 return "lmg\t%1,%0,%S2";
2303 [(set_attr "op_type" "RSY")
2304 (set_attr "type" "lm")])
2306 (define_insn "*load_multiple_si"
2307 [(match_parallel 0 "load_multiple_operation"
2308 [(set (match_operand:SI 1 "register_operand" "=r,r")
2309 (match_operand:SI 2 "s_operand" "Q,S"))])]
2312 int words = XVECLEN (operands[0], 0);
2313 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2314 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2316 [(set_attr "op_type" "RS,RSY")
2317 (set_attr "type" "lm")])
2320 ; store multiple pattern(s).
2323 (define_expand "store_multiple"
2324 [(match_par_dup 3 [(set (match_operand 0 "" "")
2325 (match_operand 1 "" ""))
2326 (use (match_operand 2 "" ""))])]
2329 enum machine_mode mode;
2335 /* Support only storing a constant number of fixed-point registers to
2336 memory and only bother with this if more than two. */
2337 if (GET_CODE (operands[2]) != CONST_INT
2338 || INTVAL (operands[2]) < 2
2339 || INTVAL (operands[2]) > 16
2340 || GET_CODE (operands[0]) != MEM
2341 || GET_CODE (operands[1]) != REG
2342 || REGNO (operands[1]) >= 16)
2345 count = INTVAL (operands[2]);
2346 regno = REGNO (operands[1]);
2347 mode = GET_MODE (operands[1]);
2348 if (mode != SImode && mode != word_mode)
2351 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2353 if (!can_create_pseudo_p ())
2355 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2357 to = XEXP (operands[0], 0);
2360 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2361 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2362 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2364 to = XEXP (XEXP (operands[0], 0), 0);
2365 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2372 to = force_reg (Pmode, XEXP (operands[0], 0));
2376 for (i = 0; i < count; i++)
2377 XVECEXP (operands[3], 0, i)
2378 = gen_rtx_SET (VOIDmode,
2379 change_address (operands[0], mode,
2380 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2381 gen_rtx_REG (mode, regno + i));
2384 (define_insn "*store_multiple_di"
2385 [(match_parallel 0 "store_multiple_operation"
2386 [(set (match_operand:DI 1 "s_operand" "=QS")
2387 (match_operand:DI 2 "register_operand" "r"))])]
2388 "reload_completed && word_mode == DImode"
2390 int words = XVECLEN (operands[0], 0);
2391 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2392 return "stmg\t%2,%0,%S1";
2394 [(set_attr "op_type" "RSY")
2395 (set_attr "type" "stm")])
2398 (define_insn "*store_multiple_si"
2399 [(match_parallel 0 "store_multiple_operation"
2400 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2401 (match_operand:SI 2 "register_operand" "r,r"))])]
2404 int words = XVECLEN (operands[0], 0);
2405 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2406 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2408 [(set_attr "op_type" "RS,RSY")
2409 (set_attr "type" "stm")])
2412 ;; String instructions.
2415 (define_insn "*execute_rl"
2416 [(match_parallel 0 ""
2417 [(unspec [(match_operand 1 "register_operand" "a")
2418 (match_operand 2 "" "")
2419 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2420 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2421 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2423 [(set_attr "op_type" "RIL")
2424 (set_attr "type" "cs")])
2426 (define_insn "*execute"
2427 [(match_parallel 0 ""
2428 [(unspec [(match_operand 1 "register_operand" "a")
2429 (match_operand:BLK 2 "memory_operand" "R")
2430 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2431 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2432 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2434 [(set_attr "op_type" "RX")
2435 (set_attr "type" "cs")])
2439 ; strlenM instruction pattern(s).
2442 (define_expand "strlen<mode>"
2443 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2446 (unspec:P [(const_int 0)
2447 (match_operand:BLK 1 "memory_operand" "")
2449 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2450 (clobber (scratch:P))
2451 (clobber (reg:CC CC_REGNUM))])
2453 [(set (match_operand:P 0 "register_operand" "")
2454 (minus:P (match_dup 4) (match_dup 5)))
2455 (clobber (reg:CC CC_REGNUM))])]
2458 operands[4] = gen_reg_rtx (Pmode);
2459 operands[5] = gen_reg_rtx (Pmode);
2460 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2461 operands[1] = replace_equiv_address (operands[1], operands[5]);
2464 (define_insn "*strlen<mode>"
2465 [(set (match_operand:P 0 "register_operand" "=a")
2466 (unspec:P [(match_operand:P 2 "general_operand" "0")
2467 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2469 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2470 (clobber (match_scratch:P 1 "=a"))
2471 (clobber (reg:CC CC_REGNUM))]
2473 "srst\t%0,%1\;jo\t.-4"
2474 [(set_attr "length" "8")
2475 (set_attr "type" "vs")])
2478 ; cmpstrM instruction pattern(s).
2481 (define_expand "cmpstrsi"
2482 [(set (reg:SI 0) (const_int 0))
2484 [(clobber (match_operand 3 "" ""))
2485 (clobber (match_dup 4))
2486 (set (reg:CCU CC_REGNUM)
2487 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2488 (match_operand:BLK 2 "memory_operand" "")))
2491 [(set (match_operand:SI 0 "register_operand" "=d")
2492 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2493 (clobber (reg:CC CC_REGNUM))])]
2496 /* As the result of CMPINT is inverted compared to what we need,
2497 we have to swap the operands. */
2498 rtx op1 = operands[2];
2499 rtx op2 = operands[1];
2500 rtx addr1 = gen_reg_rtx (Pmode);
2501 rtx addr2 = gen_reg_rtx (Pmode);
2503 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2504 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2505 operands[1] = replace_equiv_address_nv (op1, addr1);
2506 operands[2] = replace_equiv_address_nv (op2, addr2);
2507 operands[3] = addr1;
2508 operands[4] = addr2;
2511 (define_insn "*cmpstr<mode>"
2512 [(clobber (match_operand:P 0 "register_operand" "=d"))
2513 (clobber (match_operand:P 1 "register_operand" "=d"))
2514 (set (reg:CCU CC_REGNUM)
2515 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2516 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2519 "clst\t%0,%1\;jo\t.-4"
2520 [(set_attr "length" "8")
2521 (set_attr "type" "vs")])
2524 ; movstr instruction pattern.
2527 (define_expand "movstr"
2528 [(set (reg:SI 0) (const_int 0))
2530 [(clobber (match_dup 3))
2531 (set (match_operand:BLK 1 "memory_operand" "")
2532 (match_operand:BLK 2 "memory_operand" ""))
2533 (set (match_operand 0 "register_operand" "")
2534 (unspec [(match_dup 1)
2536 (reg:SI 0)] UNSPEC_MVST))
2537 (clobber (reg:CC CC_REGNUM))])]
2540 rtx addr1 = gen_reg_rtx (Pmode);
2541 rtx addr2 = gen_reg_rtx (Pmode);
2543 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2544 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2545 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2546 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2547 operands[3] = addr2;
2550 (define_insn "*movstr"
2551 [(clobber (match_operand:P 2 "register_operand" "=d"))
2552 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2553 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2554 (set (match_operand:P 0 "register_operand" "=d")
2555 (unspec [(mem:BLK (match_dup 1))
2556 (mem:BLK (match_dup 3))
2557 (reg:SI 0)] UNSPEC_MVST))
2558 (clobber (reg:CC CC_REGNUM))]
2560 "mvst\t%1,%2\;jo\t.-4"
2561 [(set_attr "length" "8")
2562 (set_attr "type" "vs")])
2566 ; movmemM instruction pattern(s).
2569 (define_expand "movmem<mode>"
2570 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2571 (match_operand:BLK 1 "memory_operand" "")) ; source
2572 (use (match_operand:GPR 2 "general_operand" "")) ; count
2573 (match_operand 3 "" "")]
2575 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2577 ; Move a block that is up to 256 bytes in length.
2578 ; The block length is taken as (operands[2] % 256) + 1.
2580 (define_expand "movmem_short"
2582 [(set (match_operand:BLK 0 "memory_operand" "")
2583 (match_operand:BLK 1 "memory_operand" ""))
2584 (use (match_operand 2 "nonmemory_operand" ""))
2585 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2586 (clobber (match_dup 3))])]
2588 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2590 (define_insn "*movmem_short"
2591 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2592 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2593 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2594 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2595 (clobber (match_scratch 4 "=X,X,X,&a"))]
2596 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2597 && GET_MODE (operands[4]) == Pmode"
2599 [(set_attr "type" "cs")
2600 (set_attr "cpu_facility" "*,*,z10,*")])
2603 [(set (match_operand:BLK 0 "memory_operand" "")
2604 (match_operand:BLK 1 "memory_operand" ""))
2605 (use (match_operand 2 "const_int_operand" ""))
2606 (use (match_operand 3 "immediate_operand" ""))
2607 (clobber (scratch))]
2610 [(set (match_dup 0) (match_dup 1))
2611 (use (match_dup 2))])]
2612 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2615 [(set (match_operand:BLK 0 "memory_operand" "")
2616 (match_operand:BLK 1 "memory_operand" ""))
2617 (use (match_operand 2 "register_operand" ""))
2618 (use (match_operand 3 "memory_operand" ""))
2619 (clobber (scratch))]
2622 [(unspec [(match_dup 2) (match_dup 3)
2623 (const_int 0)] UNSPEC_EXECUTE)
2624 (set (match_dup 0) (match_dup 1))
2625 (use (const_int 1))])]
2629 [(set (match_operand:BLK 0 "memory_operand" "")
2630 (match_operand:BLK 1 "memory_operand" ""))
2631 (use (match_operand 2 "register_operand" ""))
2632 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2633 (clobber (scratch))]
2634 "TARGET_Z10 && reload_completed"
2636 [(unspec [(match_dup 2) (const_int 0)
2637 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2638 (set (match_dup 0) (match_dup 1))
2639 (use (const_int 1))])]
2640 "operands[3] = gen_label_rtx ();")
2643 [(set (match_operand:BLK 0 "memory_operand" "")
2644 (match_operand:BLK 1 "memory_operand" ""))
2645 (use (match_operand 2 "register_operand" ""))
2646 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2647 (clobber (match_operand 3 "register_operand" ""))]
2648 "reload_completed && TARGET_CPU_ZARCH"
2649 [(set (match_dup 3) (label_ref (match_dup 4)))
2651 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2652 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2653 (set (match_dup 0) (match_dup 1))
2654 (use (const_int 1))])]
2655 "operands[4] = gen_label_rtx ();")
2657 ; Move a block of arbitrary length.
2659 (define_expand "movmem_long"
2661 [(clobber (match_dup 2))
2662 (clobber (match_dup 3))
2663 (set (match_operand:BLK 0 "memory_operand" "")
2664 (match_operand:BLK 1 "memory_operand" ""))
2665 (use (match_operand 2 "general_operand" ""))
2667 (clobber (reg:CC CC_REGNUM))])]
2670 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2671 rtx reg0 = gen_reg_rtx (dword_mode);
2672 rtx reg1 = gen_reg_rtx (dword_mode);
2673 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2674 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2675 rtx len0 = gen_lowpart (Pmode, reg0);
2676 rtx len1 = gen_lowpart (Pmode, reg1);
2678 emit_clobber (reg0);
2679 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2680 emit_move_insn (len0, operands[2]);
2682 emit_clobber (reg1);
2683 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2684 emit_move_insn (len1, operands[2]);
2686 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2687 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2692 (define_insn "*movmem_long"
2693 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2694 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2695 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2696 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2699 (clobber (reg:CC CC_REGNUM))]
2701 "mvcle\t%0,%1,0\;jo\t.-4"
2702 [(set_attr "length" "8")
2703 (set_attr "type" "vs")])
2710 (define_expand "signbit<mode>2"
2711 [(set (reg:CCZ CC_REGNUM)
2712 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2715 (set (match_operand:SI 0 "register_operand" "=d")
2716 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2719 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2722 (define_expand "isinf<mode>2"
2723 [(set (reg:CCZ CC_REGNUM)
2724 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2727 (set (match_operand:SI 0 "register_operand" "=d")
2728 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2731 operands[2] = GEN_INT (S390_TDC_INFINITY);
2734 ; This insn is used to generate all variants of the Test Data Class
2735 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2736 ; is the register to be tested and the second one is the bit mask
2737 ; specifying the required test(s).
2739 (define_insn "*TDC_insn_<mode>"
2740 [(set (reg:CCZ CC_REGNUM)
2741 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2742 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2744 "t<_d>c<xde><bt>\t%0,%1"
2745 [(set_attr "op_type" "RXE")
2746 (set_attr "type" "fsimp<mode>")])
2748 (define_insn_and_split "*ccz_to_int"
2749 [(set (match_operand:SI 0 "register_operand" "=d")
2750 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2751 UNSPEC_CCZ_TO_INT))]
2755 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2759 ; setmemM instruction pattern(s).
2762 (define_expand "setmem<mode>"
2763 [(set (match_operand:BLK 0 "memory_operand" "")
2764 (match_operand:QI 2 "general_operand" ""))
2765 (use (match_operand:GPR 1 "general_operand" ""))
2766 (match_operand 3 "" "")]
2768 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2770 ; Clear a block that is up to 256 bytes in length.
2771 ; The block length is taken as (operands[1] % 256) + 1.
2773 (define_expand "clrmem_short"
2775 [(set (match_operand:BLK 0 "memory_operand" "")
2777 (use (match_operand 1 "nonmemory_operand" ""))
2778 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2779 (clobber (match_dup 2))
2780 (clobber (reg:CC CC_REGNUM))])]
2782 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2784 (define_insn "*clrmem_short"
2785 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2787 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2788 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2789 (clobber (match_scratch 3 "=X,X,X,&a"))
2790 (clobber (reg:CC CC_REGNUM))]
2791 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2792 && GET_MODE (operands[3]) == Pmode"
2794 [(set_attr "type" "cs")
2795 (set_attr "cpu_facility" "*,*,z10,*")])
2798 [(set (match_operand:BLK 0 "memory_operand" "")
2800 (use (match_operand 1 "const_int_operand" ""))
2801 (use (match_operand 2 "immediate_operand" ""))
2803 (clobber (reg:CC CC_REGNUM))]
2806 [(set (match_dup 0) (const_int 0))
2808 (clobber (reg:CC CC_REGNUM))])]
2809 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2812 [(set (match_operand:BLK 0 "memory_operand" "")
2814 (use (match_operand 1 "register_operand" ""))
2815 (use (match_operand 2 "memory_operand" ""))
2817 (clobber (reg:CC CC_REGNUM))]
2820 [(unspec [(match_dup 1) (match_dup 2)
2821 (const_int 0)] UNSPEC_EXECUTE)
2822 (set (match_dup 0) (const_int 0))
2824 (clobber (reg:CC CC_REGNUM))])]
2828 [(set (match_operand:BLK 0 "memory_operand" "")
2830 (use (match_operand 1 "register_operand" ""))
2831 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2833 (clobber (reg:CC CC_REGNUM))]
2834 "TARGET_Z10 && reload_completed"
2836 [(unspec [(match_dup 1) (const_int 0)
2837 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2838 (set (match_dup 0) (const_int 0))
2840 (clobber (reg:CC CC_REGNUM))])]
2841 "operands[3] = gen_label_rtx ();")
2844 [(set (match_operand:BLK 0 "memory_operand" "")
2846 (use (match_operand 1 "register_operand" ""))
2847 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2848 (clobber (match_operand 2 "register_operand" ""))
2849 (clobber (reg:CC CC_REGNUM))]
2850 "reload_completed && TARGET_CPU_ZARCH"
2851 [(set (match_dup 2) (label_ref (match_dup 3)))
2853 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2854 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2855 (set (match_dup 0) (const_int 0))
2857 (clobber (reg:CC CC_REGNUM))])]
2858 "operands[3] = gen_label_rtx ();")
2860 ; Initialize a block of arbitrary length with (operands[2] % 256).
2862 (define_expand "setmem_long"
2864 [(clobber (match_dup 1))
2865 (set (match_operand:BLK 0 "memory_operand" "")
2866 (match_operand 2 "shift_count_or_setmem_operand" ""))
2867 (use (match_operand 1 "general_operand" ""))
2869 (clobber (reg:CC CC_REGNUM))])]
2872 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2873 rtx reg0 = gen_reg_rtx (dword_mode);
2874 rtx reg1 = gen_reg_rtx (dword_mode);
2875 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2876 rtx len0 = gen_lowpart (Pmode, reg0);
2878 emit_clobber (reg0);
2879 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2880 emit_move_insn (len0, operands[1]);
2882 emit_move_insn (reg1, const0_rtx);
2884 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2889 (define_insn "*setmem_long"
2890 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2891 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2892 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2894 (use (match_operand:<DBL> 1 "register_operand" "d"))
2895 (clobber (reg:CC CC_REGNUM))]
2897 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2898 [(set_attr "length" "8")
2899 (set_attr "type" "vs")])
2901 (define_insn "*setmem_long_and"
2902 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2903 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2904 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2905 (match_operand 4 "const_int_operand" "n")))
2907 (use (match_operand:<DBL> 1 "register_operand" "d"))
2908 (clobber (reg:CC CC_REGNUM))]
2909 "(INTVAL (operands[4]) & 255) == 255"
2910 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2911 [(set_attr "length" "8")
2912 (set_attr "type" "vs")])
2914 ; cmpmemM instruction pattern(s).
2917 (define_expand "cmpmemsi"
2918 [(set (match_operand:SI 0 "register_operand" "")
2919 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2920 (match_operand:BLK 2 "memory_operand" "") ) )
2921 (use (match_operand:SI 3 "general_operand" ""))
2922 (use (match_operand:SI 4 "" ""))]
2924 "s390_expand_cmpmem (operands[0], operands[1],
2925 operands[2], operands[3]); DONE;")
2927 ; Compare a block that is up to 256 bytes in length.
2928 ; The block length is taken as (operands[2] % 256) + 1.
2930 (define_expand "cmpmem_short"
2932 [(set (reg:CCU CC_REGNUM)
2933 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2934 (match_operand:BLK 1 "memory_operand" "")))
2935 (use (match_operand 2 "nonmemory_operand" ""))
2936 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2937 (clobber (match_dup 3))])]
2939 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2941 (define_insn "*cmpmem_short"
2942 [(set (reg:CCU CC_REGNUM)
2943 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
2944 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
2945 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2946 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2947 (clobber (match_scratch 4 "=X,X,X,&a"))]
2948 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2949 && GET_MODE (operands[4]) == Pmode"
2951 [(set_attr "type" "cs")
2952 (set_attr "cpu_facility" "*,*,z10,*")])
2955 [(set (reg:CCU CC_REGNUM)
2956 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2957 (match_operand:BLK 1 "memory_operand" "")))
2958 (use (match_operand 2 "const_int_operand" ""))
2959 (use (match_operand 3 "immediate_operand" ""))
2960 (clobber (scratch))]
2963 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2964 (use (match_dup 2))])]
2965 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2968 [(set (reg:CCU CC_REGNUM)
2969 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2970 (match_operand:BLK 1 "memory_operand" "")))
2971 (use (match_operand 2 "register_operand" ""))
2972 (use (match_operand 3 "memory_operand" ""))
2973 (clobber (scratch))]
2976 [(unspec [(match_dup 2) (match_dup 3)
2977 (const_int 0)] UNSPEC_EXECUTE)
2978 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2979 (use (const_int 1))])]
2983 [(set (reg:CCU CC_REGNUM)
2984 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2985 (match_operand:BLK 1 "memory_operand" "")))
2986 (use (match_operand 2 "register_operand" ""))
2987 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2988 (clobber (scratch))]
2989 "TARGET_Z10 && reload_completed"
2991 [(unspec [(match_dup 2) (const_int 0)
2992 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2993 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2994 (use (const_int 1))])]
2995 "operands[4] = gen_label_rtx ();")
2998 [(set (reg:CCU CC_REGNUM)
2999 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3000 (match_operand:BLK 1 "memory_operand" "")))
3001 (use (match_operand 2 "register_operand" ""))
3002 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3003 (clobber (match_operand 3 "register_operand" ""))]
3004 "reload_completed && TARGET_CPU_ZARCH"
3005 [(set (match_dup 3) (label_ref (match_dup 4)))
3007 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3008 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3009 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3010 (use (const_int 1))])]
3011 "operands[4] = gen_label_rtx ();")
3013 ; Compare a block of arbitrary length.
3015 (define_expand "cmpmem_long"
3017 [(clobber (match_dup 2))
3018 (clobber (match_dup 3))
3019 (set (reg:CCU CC_REGNUM)
3020 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3021 (match_operand:BLK 1 "memory_operand" "")))
3022 (use (match_operand 2 "general_operand" ""))
3023 (use (match_dup 3))])]
3026 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
3027 rtx reg0 = gen_reg_rtx (dword_mode);
3028 rtx reg1 = gen_reg_rtx (dword_mode);
3029 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
3030 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
3031 rtx len0 = gen_lowpart (Pmode, reg0);
3032 rtx len1 = gen_lowpart (Pmode, reg1);
3034 emit_clobber (reg0);
3035 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3036 emit_move_insn (len0, operands[2]);
3038 emit_clobber (reg1);
3039 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3040 emit_move_insn (len1, operands[2]);
3042 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3043 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3048 (define_insn "*cmpmem_long"
3049 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3050 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3051 (set (reg:CCU CC_REGNUM)
3052 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3053 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3055 (use (match_dup 3))]
3057 "clcle\t%0,%1,0\;jo\t.-4"
3058 [(set_attr "length" "8")
3059 (set_attr "type" "vs")])
3061 ; Convert CCUmode condition code to integer.
3062 ; Result is zero if EQ, positive if LTU, negative if GTU.
3064 (define_insn_and_split "cmpint"
3065 [(set (match_operand:SI 0 "register_operand" "=d")
3066 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3068 (clobber (reg:CC CC_REGNUM))]
3072 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3074 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3075 (clobber (reg:CC CC_REGNUM))])])
3077 (define_insn_and_split "*cmpint_cc"
3078 [(set (reg CC_REGNUM)
3079 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3082 (set (match_operand:SI 0 "register_operand" "=d")
3083 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3084 "s390_match_ccmode (insn, CCSmode)"
3086 "&& reload_completed"
3087 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3089 [(set (match_dup 2) (match_dup 3))
3090 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3092 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3093 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3094 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3097 (define_insn_and_split "*cmpint_sign"
3098 [(set (match_operand:DI 0 "register_operand" "=d")
3099 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3100 UNSPEC_CCU_TO_INT)))
3101 (clobber (reg:CC CC_REGNUM))]
3104 "&& reload_completed"
3105 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3107 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3108 (clobber (reg:CC CC_REGNUM))])])
3110 (define_insn_and_split "*cmpint_sign_cc"
3111 [(set (reg CC_REGNUM)
3112 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3113 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3114 UNSPEC_CCU_TO_INT) 0)
3115 (const_int 32)) (const_int 32))
3117 (set (match_operand:DI 0 "register_operand" "=d")
3118 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3119 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
3121 "&& reload_completed"
3122 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3124 [(set (match_dup 2) (match_dup 3))
3125 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3127 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3128 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3129 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3134 ;;- Conversion instructions.
3137 (define_insn "*sethighpartsi"
3138 [(set (match_operand:SI 0 "register_operand" "=d,d")
3139 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3140 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3141 (clobber (reg:CC CC_REGNUM))]
3146 [(set_attr "op_type" "RS,RSY")
3147 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3149 (define_insn "*sethighpartdi_64"
3150 [(set (match_operand:DI 0 "register_operand" "=d")
3151 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3152 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3153 (clobber (reg:CC CC_REGNUM))]
3156 [(set_attr "op_type" "RSY")])
3158 (define_insn "*sethighpartdi_31"
3159 [(set (match_operand:DI 0 "register_operand" "=d,d")
3160 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3161 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3162 (clobber (reg:CC CC_REGNUM))]
3167 [(set_attr "op_type" "RS,RSY")
3168 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3171 (define_insn_and_split "*extzv<mode>"
3172 [(set (match_operand:GPR 0 "register_operand" "=d")
3173 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3174 (match_operand 2 "const_int_operand" "n")
3176 (clobber (reg:CC CC_REGNUM))]
3177 "INTVAL (operands[2]) > 0
3178 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3180 "&& reload_completed"
3182 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3183 (clobber (reg:CC CC_REGNUM))])
3184 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3186 int bitsize = INTVAL (operands[2]);
3187 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3188 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3190 operands[1] = adjust_address (operands[1], BLKmode, 0);
3191 set_mem_size (operands[1], GEN_INT (size));
3192 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3193 operands[3] = GEN_INT (mask);
3196 (define_insn_and_split "*extv<mode>"
3197 [(set (match_operand:GPR 0 "register_operand" "=d")
3198 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3199 (match_operand 2 "const_int_operand" "n")
3201 (clobber (reg:CC CC_REGNUM))]
3202 "INTVAL (operands[2]) > 0
3203 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3205 "&& reload_completed"
3207 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3208 (clobber (reg:CC CC_REGNUM))])
3210 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3211 (clobber (reg:CC CC_REGNUM))])]
3213 int bitsize = INTVAL (operands[2]);
3214 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3215 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3217 operands[1] = adjust_address (operands[1], BLKmode, 0);
3218 set_mem_size (operands[1], GEN_INT (size));
3219 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3220 operands[3] = GEN_INT (mask);
3224 ; insv instruction patterns
3227 (define_expand "insv"
3228 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3229 (match_operand 1 "const_int_operand" "")
3230 (match_operand 2 "const_int_operand" ""))
3231 (match_operand 3 "general_operand" ""))]
3234 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3239 (define_insn "*insv<mode>_z10"
3240 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3241 (match_operand 1 "const_int_operand" "I")
3242 (match_operand 2 "const_int_operand" "I"))
3243 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3244 (clobber (reg:CC CC_REGNUM))]
3246 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3247 GET_MODE_BITSIZE (<MODE>mode)"
3249 int start = INTVAL (operands[2]);
3250 int size = INTVAL (operands[1]);
3251 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3253 operands[2] = GEN_INT (offset + start); /* start bit position */
3254 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3255 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3256 start - size); /* left shift count */
3258 return "risbg\t%0,%3,%b2,%b1,%b4";
3260 [(set_attr "op_type" "RIE")
3261 (set_attr "z10prop" "z10_super_E1")])
3263 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3264 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3265 (define_insn "*insv<mode>_z10_noshift"
3266 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3267 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3268 (match_operand 2 "const_int_operand" "n"))
3269 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3270 (match_operand 4 "const_int_operand" "n"))))
3271 (clobber (reg:CC CC_REGNUM))]
3273 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3274 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3275 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3281 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3282 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3284 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3285 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3286 operands[7] = const0_rtx; /* left shift count */
3288 return "risbg\t%0,%1,%b5,%b6,%b7";
3290 [(set_attr "op_type" "RIE")
3291 (set_attr "z10prop" "z10_super_E1")])
3293 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3294 (define_insn "*insv<mode>_or_z10_noshift"
3295 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3296 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3297 (match_operand 2 "const_int_operand" "n"))
3298 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3299 (clobber (reg:CC CC_REGNUM))]
3301 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3302 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3307 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3308 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3310 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3311 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3312 operands[6] = const0_rtx; /* left shift count */
3314 return "rosbg\t%0,%1,%b4,%b5,%b6";
3316 [(set_attr "op_type" "RIE")])
3318 (define_insn "*insv<mode>_mem_reg"
3319 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
3320 (match_operand 1 "const_int_operand" "n,n")
3322 (match_operand:P 2 "register_operand" "d,d"))]
3323 "INTVAL (operands[1]) > 0
3324 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3325 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3327 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3329 operands[1] = GEN_INT ((1ul << size) - 1);
3330 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3331 : "stcmy\t%2,%1,%S0";
3333 [(set_attr "op_type" "RS,RSY")
3334 (set_attr "z10prop" "z10_super,z10_super")])
3336 (define_insn "*insvdi_mem_reghigh"
3337 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3338 (match_operand 1 "const_int_operand" "n")
3340 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3343 && INTVAL (operands[1]) > 0
3344 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3345 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3347 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3349 operands[1] = GEN_INT ((1ul << size) - 1);
3350 return "stcmh\t%2,%1,%S0";
3352 [(set_attr "op_type" "RSY")
3353 (set_attr "z10prop" "z10_super")])
3355 (define_insn "*insv<mode>_reg_imm"
3356 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3358 (match_operand 1 "const_int_operand" "n"))
3359 (match_operand:P 2 "const_int_operand" "n"))]
3361 && INTVAL (operands[1]) >= 0
3362 && INTVAL (operands[1]) < BITS_PER_WORD
3363 && INTVAL (operands[1]) % 16 == 0"
3365 switch (BITS_PER_WORD - INTVAL (operands[1]))
3367 case 64: return "iihh\t%0,%x2"; break;
3368 case 48: return "iihl\t%0,%x2"; break;
3369 case 32: return "iilh\t%0,%x2"; break;
3370 case 16: return "iill\t%0,%x2"; break;
3371 default: gcc_unreachable();
3374 [(set_attr "op_type" "RI")
3375 (set_attr "z10prop" "z10_super_E1")])
3378 (define_insn "*insv<mode>_reg_extimm"
3379 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3381 (match_operand 1 "const_int_operand" "n"))
3382 (match_operand:P 2 "const_int_operand" "n"))]
3384 && INTVAL (operands[1]) >= 0
3385 && INTVAL (operands[1]) < BITS_PER_WORD
3386 && INTVAL (operands[1]) % 32 == 0"
3388 switch (BITS_PER_WORD - INTVAL (operands[1]))
3390 case 64: return "iihf\t%0,%o2"; break;
3391 case 32: return "iilf\t%0,%o2"; break;
3392 default: gcc_unreachable();
3395 [(set_attr "op_type" "RIL")
3396 (set_attr "z10prop" "z10_fwd_E1")])
3400 ; extendsidi2 instruction pattern(s).
3403 (define_expand "extendsidi2"
3404 [(set (match_operand:DI 0 "register_operand" "")
3405 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3410 emit_clobber (operands[0]);
3411 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3412 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3413 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3418 (define_insn "*extendsidi2"
3419 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3420 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3426 [(set_attr "op_type" "RRE,RXY,RIL")
3427 (set_attr "type" "*,*,larl")
3428 (set_attr "cpu_facility" "*,*,z10")
3429 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3432 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3435 (define_expand "extend<HQI:mode><DSI:mode>2"
3436 [(set (match_operand:DSI 0 "register_operand" "")
3437 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3440 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
3442 rtx tmp = gen_reg_rtx (SImode);
3443 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3444 emit_insn (gen_extendsidi2 (operands[0], tmp));
3447 else if (!TARGET_EXTIMM)
3449 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3450 GET_MODE_BITSIZE (<HQI:MODE>mode));
3452 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3453 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3454 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3460 ; extendhidi2 instruction pattern(s).
3463 (define_insn "*extendhidi2_extimm"
3464 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3465 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3466 "TARGET_64BIT && TARGET_EXTIMM"
3471 [(set_attr "op_type" "RRE,RXY,RIL")
3472 (set_attr "type" "*,*,larl")
3473 (set_attr "cpu_facility" "extimm,extimm,z10")
3474 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3476 (define_insn "*extendhidi2"
3477 [(set (match_operand:DI 0 "register_operand" "=d")
3478 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3481 [(set_attr "op_type" "RXY")
3482 (set_attr "z10prop" "z10_super_E1")])
3485 ; extendhisi2 instruction pattern(s).
3488 (define_insn "*extendhisi2_extimm"
3489 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3490 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3497 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3498 (set_attr "type" "*,*,*,larl")
3499 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3500 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3502 (define_insn "*extendhisi2"
3503 [(set (match_operand:SI 0 "register_operand" "=d,d")
3504 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3509 [(set_attr "op_type" "RX,RXY")
3510 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3513 ; extendqi(si|di)2 instruction pattern(s).
3516 ; lbr, lgbr, lb, lgb
3517 (define_insn "*extendqi<mode>2_extimm"
3518 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3519 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3524 [(set_attr "op_type" "RRE,RXY")
3525 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3528 (define_insn "*extendqi<mode>2"
3529 [(set (match_operand:GPR 0 "register_operand" "=d")
3530 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3531 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3533 [(set_attr "op_type" "RXY")
3534 (set_attr "z10prop" "z10_super_E1")])
3536 (define_insn_and_split "*extendqi<mode>2_short_displ"
3537 [(set (match_operand:GPR 0 "register_operand" "=d")
3538 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3539 (clobber (reg:CC CC_REGNUM))]
3540 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3542 "&& reload_completed"
3544 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3545 (clobber (reg:CC CC_REGNUM))])
3547 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3548 (clobber (reg:CC CC_REGNUM))])]
3550 operands[1] = adjust_address (operands[1], BLKmode, 0);
3551 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3552 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3553 - GET_MODE_BITSIZE (QImode));
3557 ; zero_extendsidi2 instruction pattern(s).
3560 (define_expand "zero_extendsidi2"
3561 [(set (match_operand:DI 0 "register_operand" "")
3562 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3567 emit_clobber (operands[0]);
3568 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3569 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3574 (define_insn "*zero_extendsidi2"
3575 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3576 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3582 [(set_attr "op_type" "RRE,RXY,RIL")
3583 (set_attr "type" "*,*,larl")
3584 (set_attr "cpu_facility" "*,*,z10")
3585 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3588 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3591 (define_insn "*llgt_sidi"
3592 [(set (match_operand:DI 0 "register_operand" "=d")
3593 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3594 (const_int 2147483647)))]
3597 [(set_attr "op_type" "RXE")
3598 (set_attr "z10prop" "z10_super_E1")])
3600 (define_insn_and_split "*llgt_sidi_split"
3601 [(set (match_operand:DI 0 "register_operand" "=d")
3602 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3603 (const_int 2147483647)))
3604 (clobber (reg:CC CC_REGNUM))]
3607 "&& reload_completed"
3609 (and:DI (subreg:DI (match_dup 1) 0)
3610 (const_int 2147483647)))]
3613 (define_insn "*llgt_sisi"
3614 [(set (match_operand:SI 0 "register_operand" "=d,d")
3615 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3616 (const_int 2147483647)))]
3621 [(set_attr "op_type" "RRE,RXE")
3622 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3624 (define_insn "*llgt_didi"
3625 [(set (match_operand:DI 0 "register_operand" "=d,d")
3626 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3627 (const_int 2147483647)))]
3632 [(set_attr "op_type" "RRE,RXE")
3633 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3636 [(set (match_operand:GPR 0 "register_operand" "")
3637 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3638 (const_int 2147483647)))
3639 (clobber (reg:CC CC_REGNUM))]
3640 "TARGET_ZARCH && reload_completed"
3642 (and:GPR (match_dup 1)
3643 (const_int 2147483647)))]
3647 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3650 (define_expand "zero_extend<mode>di2"
3651 [(set (match_operand:DI 0 "register_operand" "")
3652 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3657 rtx tmp = gen_reg_rtx (SImode);
3658 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3659 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3662 else if (!TARGET_EXTIMM)
3664 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3665 GET_MODE_BITSIZE(<MODE>mode));
3666 operands[1] = gen_lowpart (DImode, operands[1]);
3667 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3668 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3673 (define_expand "zero_extend<mode>si2"
3674 [(set (match_operand:SI 0 "register_operand" "")
3675 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3680 operands[1] = gen_lowpart (SImode, operands[1]);
3681 emit_insn (gen_andsi3 (operands[0], operands[1],
3682 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3688 (define_insn "*zero_extendhi<mode>2_z10"
3689 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3690 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3696 [(set_attr "op_type" "RXY,RRE,RIL")
3697 (set_attr "type" "*,*,larl")
3698 (set_attr "cpu_facility" "*,*,z10")
3699 (set_attr "z10prop" "z10_fwd_A3")])
3701 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3702 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3703 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3704 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3709 [(set_attr "op_type" "RRE,RXY")
3710 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3713 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3714 [(set (match_operand:GPR 0 "register_operand" "=d")
3715 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3716 "TARGET_ZARCH && !TARGET_EXTIMM"
3718 [(set_attr "op_type" "RXY")
3719 (set_attr "z10prop" "z10_fwd_A3")])
3721 (define_insn_and_split "*zero_extendhisi2_31"
3722 [(set (match_operand:SI 0 "register_operand" "=&d")
3723 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3724 (clobber (reg:CC CC_REGNUM))]
3727 "&& reload_completed"
3728 [(set (match_dup 0) (const_int 0))
3730 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3731 (clobber (reg:CC CC_REGNUM))])]
3732 "operands[2] = gen_lowpart (HImode, operands[0]);")
3734 (define_insn_and_split "*zero_extendqisi2_31"
3735 [(set (match_operand:SI 0 "register_operand" "=&d")
3736 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3739 "&& reload_completed"
3740 [(set (match_dup 0) (const_int 0))
3741 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3742 "operands[2] = gen_lowpart (QImode, operands[0]);")
3745 ; zero_extendqihi2 instruction pattern(s).
3748 (define_expand "zero_extendqihi2"
3749 [(set (match_operand:HI 0 "register_operand" "")
3750 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3751 "TARGET_ZARCH && !TARGET_EXTIMM"
3753 operands[1] = gen_lowpart (HImode, operands[1]);
3754 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3758 (define_insn "*zero_extendqihi2_64"
3759 [(set (match_operand:HI 0 "register_operand" "=d")
3760 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3761 "TARGET_ZARCH && !TARGET_EXTIMM"
3763 [(set_attr "op_type" "RXY")
3764 (set_attr "z10prop" "z10_fwd_A3")])
3766 (define_insn_and_split "*zero_extendqihi2_31"
3767 [(set (match_operand:HI 0 "register_operand" "=&d")
3768 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3771 "&& reload_completed"
3772 [(set (match_dup 0) (const_int 0))
3773 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3774 "operands[2] = gen_lowpart (QImode, operands[0]);")
3777 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3780 (define_expand "fixuns_truncdddi2"
3782 [(set (match_operand:DI 0 "register_operand" "")
3783 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3784 (clobber (match_scratch:TD 2 "=f"))])]
3788 rtx label1 = gen_label_rtx ();
3789 rtx label2 = gen_label_rtx ();
3790 rtx temp = gen_reg_rtx (TDmode);
3791 REAL_VALUE_TYPE cmp, sub;
3793 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3794 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3796 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3797 solution is doing the check and the subtraction in TD mode and using a
3798 TD -> DI convert afterwards. */
3799 emit_insn (gen_extendddtd2 (temp, operands[1]));
3800 temp = force_reg (TDmode, temp);
3801 emit_insn (gen_cmptd (temp,
3802 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3803 emit_jump_insn (gen_blt (label1));
3804 emit_insn (gen_subtd3 (temp, temp,
3805 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3806 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3809 emit_label (label1);
3810 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3811 emit_label (label2);
3815 (define_expand "fixuns_trunctddi2"
3816 [(set (match_operand:DI 0 "register_operand" "")
3817 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3820 rtx label1 = gen_label_rtx ();
3821 rtx label2 = gen_label_rtx ();
3822 rtx temp = gen_reg_rtx (TDmode);
3823 REAL_VALUE_TYPE cmp, sub;
3825 operands[1] = force_reg (TDmode, operands[1]);
3826 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3827 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3829 emit_insn (gen_cmptd (operands[1],
3830 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3831 emit_jump_insn (gen_blt (label1));
3832 emit_insn (gen_subtd3 (temp, operands[1],
3833 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3834 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3837 emit_label (label1);
3838 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3839 emit_label (label2);
3844 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3845 ; instruction pattern(s).
3848 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3849 [(set (match_operand:GPR 0 "register_operand" "")
3850 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3853 rtx label1 = gen_label_rtx ();
3854 rtx label2 = gen_label_rtx ();
3855 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3856 REAL_VALUE_TYPE cmp, sub;
3858 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3859 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3860 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3862 emit_insn (gen_cmp<BFP:mode> (operands[1],
3863 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
3864 emit_jump_insn (gen_blt (label1));
3865 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3866 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3867 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3871 emit_label (label1);
3872 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3873 operands[1], GEN_INT (5)));
3874 emit_label (label2);
3878 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3879 [(set (match_operand:GPR 0 "register_operand" "")
3880 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3883 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3888 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3889 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3890 [(set (match_operand:GPR 0 "register_operand" "=d")
3891 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3892 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3893 (clobber (reg:CC CC_REGNUM))]
3895 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3896 [(set_attr "op_type" "RRE")
3897 (set_attr "type" "ftoi")])
3901 ; fix_trunc(td|dd)di2 instruction pattern(s).
3904 (define_expand "fix_trunc<mode>di2"
3905 [(set (match_operand:DI 0 "register_operand" "")
3906 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3907 "TARGET_64BIT && TARGET_HARD_DFP"
3909 operands[1] = force_reg (<MODE>mode, operands[1]);
3910 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3916 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3917 [(set (match_operand:DI 0 "register_operand" "=d")
3918 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3919 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3920 (clobber (reg:CC CC_REGNUM))]
3921 "TARGET_64BIT && TARGET_HARD_DFP"
3922 "cg<DFP:xde>tr\t%0,%h2,%1"
3923 [(set_attr "op_type" "RRF")
3924 (set_attr "type" "ftoidfp")])
3928 ; fix_trunctf(si|di)2 instruction pattern(s).
3931 (define_expand "fix_trunctf<mode>2"
3932 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3933 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3934 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3935 (clobber (reg:CC CC_REGNUM))])]
3941 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
3944 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
3945 (define_insn "floatdi<mode>2"
3946 [(set (match_operand:FP 0 "register_operand" "=f")
3947 (float:FP (match_operand:DI 1 "register_operand" "d")))]
3948 "TARGET_64BIT && TARGET_HARD_FLOAT"
3949 "c<xde>g<bt>r\t%0,%1"
3950 [(set_attr "op_type" "RRE")
3951 (set_attr "type" "itof<mode>" )])
3953 ; cxfbr, cdfbr, cefbr
3954 (define_insn "floatsi<mode>2"
3955 [(set (match_operand:BFP 0 "register_operand" "=f")
3956 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
3959 [(set_attr "op_type" "RRE")
3960 (set_attr "type" "itof<mode>" )])
3964 ; truncdfsf2 instruction pattern(s).
3967 (define_insn "truncdfsf2"
3968 [(set (match_operand:SF 0 "register_operand" "=f")
3969 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3972 [(set_attr "op_type" "RRE")
3973 (set_attr "type" "ftruncdf")])
3976 ; trunctf(df|sf)2 instruction pattern(s).
3980 (define_insn "trunctf<mode>2"
3981 [(set (match_operand:DSF 0 "register_operand" "=f")
3982 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
3983 (clobber (match_scratch:TF 2 "=f"))]
3985 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
3986 [(set_attr "length" "6")
3987 (set_attr "type" "ftrunctf")])
3990 ; trunctddd2 and truncddsd2 instruction pattern(s).
3993 (define_insn "trunctddd2"
3994 [(set (match_operand:DD 0 "register_operand" "=f")
3995 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
3996 (clobber (match_scratch:TD 2 "=f"))]
3998 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
3999 [(set_attr "length" "6")
4000 (set_attr "type" "ftruncdd")])
4002 (define_insn "truncddsd2"
4003 [(set (match_operand:SD 0 "register_operand" "=f")
4004 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4007 [(set_attr "op_type" "RRF")
4008 (set_attr "type" "ftruncsd")])
4011 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4014 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4015 (define_insn "extend<DSF:mode><BFP:mode>2"
4016 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4017 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4019 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4021 l<BFP:xde><DSF:xde>br\t%0,%1
4022 l<BFP:xde><DSF:xde>b\t%0,%1"
4023 [(set_attr "op_type" "RRE,RXE")
4024 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4027 ; extendddtd2 and extendsddd2 instruction pattern(s).
4030 (define_insn "extendddtd2"
4031 [(set (match_operand:TD 0 "register_operand" "=f")
4032 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4035 [(set_attr "op_type" "RRF")
4036 (set_attr "type" "fsimptf")])
4038 (define_insn "extendsddd2"
4039 [(set (match_operand:DD 0 "register_operand" "=f")
4040 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4043 [(set_attr "op_type" "RRF")
4044 (set_attr "type" "fsimptf")])
4046 ; Binary <-> Decimal floating point trunc patterns
4049 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4050 [(set (reg:DFP_ALL FPR0_REGNUM)
4051 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4052 (use (reg:SI GPR0_REGNUM))
4053 (clobber (reg:CC CC_REGNUM))]
4057 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4058 [(set (reg:BFP FPR0_REGNUM)
4059 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4060 (use (reg:SI GPR0_REGNUM))
4061 (clobber (reg:CC CC_REGNUM))]
4065 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4066 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4067 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4069 [(set (reg:DFP_ALL FPR0_REGNUM)
4070 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4071 (use (reg:SI GPR0_REGNUM))
4072 (clobber (reg:CC CC_REGNUM))])
4073 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4074 (reg:DFP_ALL FPR0_REGNUM))]
4076 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4078 HOST_WIDE_INT flags;
4080 flags = (PFPO_CONVERT |
4081 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4082 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4084 operands[2] = GEN_INT (flags);
4087 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4088 [(set (reg:DFP_ALL FPR2_REGNUM)
4089 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4090 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4092 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4093 (use (reg:SI GPR0_REGNUM))
4094 (clobber (reg:CC CC_REGNUM))])
4095 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4097 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4099 HOST_WIDE_INT flags;
4101 flags = (PFPO_CONVERT |
4102 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4103 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4105 operands[2] = GEN_INT (flags);
4109 ; Binary <-> Decimal floating point extend patterns
4112 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4113 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4114 (use (reg:SI GPR0_REGNUM))
4115 (clobber (reg:CC CC_REGNUM))]
4119 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4120 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4121 (use (reg:SI GPR0_REGNUM))
4122 (clobber (reg:CC CC_REGNUM))]
4126 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4127 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4128 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4130 [(set (reg:DFP_ALL FPR0_REGNUM)
4131 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4132 (use (reg:SI GPR0_REGNUM))
4133 (clobber (reg:CC CC_REGNUM))])
4134 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4135 (reg:DFP_ALL FPR0_REGNUM))]
4137 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4139 HOST_WIDE_INT flags;
4141 flags = (PFPO_CONVERT |
4142 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4143 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4145 operands[2] = GEN_INT (flags);
4148 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4149 [(set (reg:DFP_ALL FPR2_REGNUM)
4150 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4151 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4153 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4154 (use (reg:SI GPR0_REGNUM))
4155 (clobber (reg:CC CC_REGNUM))])
4156 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4158 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4160 HOST_WIDE_INT flags;
4162 flags = (PFPO_CONVERT |
4163 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4164 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4166 operands[2] = GEN_INT (flags);
4171 ;; ARITHMETIC OPERATIONS
4173 ; arithmetic operations set the ConditionCode,
4174 ; because of unpredictable Bits in Register for Halfword and Byte
4175 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4178 ;;- Add instructions.
4182 ; addti3 instruction pattern(s).
4185 (define_insn_and_split "addti3"
4186 [(set (match_operand:TI 0 "register_operand" "=&d")
4187 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4188 (match_operand:TI 2 "general_operand" "do") ) )
4189 (clobber (reg:CC CC_REGNUM))]
4192 "&& reload_completed"
4194 [(set (reg:CCL1 CC_REGNUM)
4195 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4197 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4199 [(set (match_dup 3) (plus:DI
4200 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4201 (match_dup 4)) (match_dup 5)))
4202 (clobber (reg:CC CC_REGNUM))])]
4203 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4204 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4205 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4206 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4207 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4208 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4211 ; adddi3 instruction pattern(s).
4214 (define_expand "adddi3"
4216 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4217 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4218 (match_operand:DI 2 "general_operand" "")))
4219 (clobber (reg:CC CC_REGNUM))])]
4223 (define_insn "*adddi3_sign"
4224 [(set (match_operand:DI 0 "register_operand" "=d,d")
4225 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4226 (match_operand:DI 1 "register_operand" "0,0")))
4227 (clobber (reg:CC CC_REGNUM))]
4232 [(set_attr "op_type" "RRE,RXY")])
4234 (define_insn "*adddi3_zero_cc"
4235 [(set (reg CC_REGNUM)
4236 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4237 (match_operand:DI 1 "register_operand" "0,0"))
4239 (set (match_operand:DI 0 "register_operand" "=d,d")
4240 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4241 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4245 [(set_attr "op_type" "RRE,RXY")
4246 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4248 (define_insn "*adddi3_zero_cconly"
4249 [(set (reg CC_REGNUM)
4250 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4251 (match_operand:DI 1 "register_operand" "0,0"))
4253 (clobber (match_scratch:DI 0 "=d,d"))]
4254 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4258 [(set_attr "op_type" "RRE,RXY")
4259 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4261 (define_insn "*adddi3_zero"
4262 [(set (match_operand:DI 0 "register_operand" "=d,d")
4263 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4264 (match_operand:DI 1 "register_operand" "0,0")))
4265 (clobber (reg:CC CC_REGNUM))]
4270 [(set_attr "op_type" "RRE,RXY")
4271 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4273 (define_insn_and_split "*adddi3_31z"
4274 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4275 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4276 (match_operand:DI 2 "general_operand" "do") ) )
4277 (clobber (reg:CC CC_REGNUM))]
4278 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4280 "&& reload_completed"
4282 [(set (reg:CCL1 CC_REGNUM)
4283 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4285 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4287 [(set (match_dup 3) (plus:SI
4288 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4289 (match_dup 4)) (match_dup 5)))
4290 (clobber (reg:CC CC_REGNUM))])]
4291 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4292 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4293 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4294 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4295 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4296 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4298 (define_insn_and_split "*adddi3_31"
4299 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4300 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4301 (match_operand:DI 2 "general_operand" "do") ) )
4302 (clobber (reg:CC CC_REGNUM))]
4305 "&& reload_completed"
4307 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4308 (clobber (reg:CC CC_REGNUM))])
4310 [(set (reg:CCL1 CC_REGNUM)
4311 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4313 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4315 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4317 (label_ref (match_dup 9))))
4319 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4320 (clobber (reg:CC CC_REGNUM))])
4322 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4323 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4324 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4325 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4326 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4327 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4328 operands[9] = gen_label_rtx ();")
4331 ; addsi3 instruction pattern(s).
4334 (define_expand "addsi3"
4336 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4337 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4338 (match_operand:SI 2 "general_operand" "")))
4339 (clobber (reg:CC CC_REGNUM))])]
4343 (define_insn "*addsi3_sign"
4344 [(set (match_operand:SI 0 "register_operand" "=d,d")
4345 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4346 (match_operand:SI 1 "register_operand" "0,0")))
4347 (clobber (reg:CC CC_REGNUM))]
4352 [(set_attr "op_type" "RX,RXY")])
4355 ; add(di|si)3 instruction pattern(s).
4358 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4359 (define_insn "*add<mode>3"
4360 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
4361 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4362 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
4363 (clobber (reg:CC CC_REGNUM))]
4373 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
4374 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
4375 (set_attr "z10prop" "z10_super_E1,
4383 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4384 (define_insn "*add<mode>3_carry1_cc"
4385 [(set (reg CC_REGNUM)
4386 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4387 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4389 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
4390 (plus:GPR (match_dup 1) (match_dup 2)))]
4391 "s390_match_ccmode (insn, CCL1mode)"
4399 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4400 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4401 (set_attr "z10prop" "z10_super_E1,
4408 ; alr, al, aly, algr, alg
4409 (define_insn "*add<mode>3_carry1_cconly"
4410 [(set (reg CC_REGNUM)
4411 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4412 (match_operand:GPR 2 "general_operand" "d,R,T"))
4414 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4415 "s390_match_ccmode (insn, CCL1mode)"
4420 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4421 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4423 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4424 (define_insn "*add<mode>3_carry2_cc"
4425 [(set (reg CC_REGNUM)
4426 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4427 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4429 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4430 (plus:GPR (match_dup 1) (match_dup 2)))]
4431 "s390_match_ccmode (insn, CCL1mode)"
4439 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4440 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4441 (set_attr "z10prop" "z10_super_E1,
4448 ; alr, al, aly, algr, alg
4449 (define_insn "*add<mode>3_carry2_cconly"
4450 [(set (reg CC_REGNUM)
4451 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4452 (match_operand:GPR 2 "general_operand" "d,R,T"))
4454 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4455 "s390_match_ccmode (insn, CCL1mode)"
4460 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4461 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4463 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4464 (define_insn "*add<mode>3_cc"
4465 [(set (reg CC_REGNUM)
4466 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4467 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4469 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4470 (plus:GPR (match_dup 1) (match_dup 2)))]
4471 "s390_match_ccmode (insn, CCLmode)"
4479 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4480 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4481 (set_attr "z10prop" "z10_super_E1,
4488 ; alr, al, aly, algr, alg
4489 (define_insn "*add<mode>3_cconly"
4490 [(set (reg CC_REGNUM)
4491 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4492 (match_operand:GPR 2 "general_operand" "d,R,T"))
4494 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4495 "s390_match_ccmode (insn, CCLmode)"
4500 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4501 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4503 ; alr, al, aly, algr, alg
4504 (define_insn "*add<mode>3_cconly2"
4505 [(set (reg CC_REGNUM)
4506 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4507 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
4508 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4509 "s390_match_ccmode(insn, CCLmode)"
4514 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4515 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4517 ; ahi, afi, aghi, agfi, asi, agsi
4518 (define_insn "*add<mode>3_imm_cc"
4519 [(set (reg CC_REGNUM)
4520 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
4521 (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
4523 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
4524 (plus:GPR (match_dup 1) (match_dup 2)))]
4525 "s390_match_ccmode (insn, CCAmode)
4526 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4527 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4528 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4529 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4534 [(set_attr "op_type" "RI,RIL,SIY")
4535 (set_attr "cpu_facility" "*,extimm,z10")
4536 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4539 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4542 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4543 (define_insn "add<mode>3"
4544 [(set (match_operand:FP 0 "register_operand" "=f, f")
4545 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4546 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4547 (clobber (reg:CC CC_REGNUM))]
4550 a<xde><bt>r\t%0,<op1>%2
4552 [(set_attr "op_type" "<RRer>,RXE")
4553 (set_attr "type" "fsimp<mode>")])
4555 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4556 (define_insn "*add<mode>3_cc"
4557 [(set (reg CC_REGNUM)
4558 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4559 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4560 (match_operand:FP 3 "const0_operand" "")))
4561 (set (match_operand:FP 0 "register_operand" "=f,f")
4562 (plus:FP (match_dup 1) (match_dup 2)))]
4563 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4565 a<xde><bt>r\t%0,<op1>%2
4567 [(set_attr "op_type" "<RRer>,RXE")
4568 (set_attr "type" "fsimp<mode>")])
4570 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4571 (define_insn "*add<mode>3_cconly"
4572 [(set (reg CC_REGNUM)
4573 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4574 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4575 (match_operand:FP 3 "const0_operand" "")))
4576 (clobber (match_scratch:FP 0 "=f,f"))]
4577 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4579 a<xde><bt>r\t%0,<op1>%2
4581 [(set_attr "op_type" "<RRer>,RXE")
4582 (set_attr "type" "fsimp<mode>")])
4586 ;;- Subtract instructions.
4590 ; subti3 instruction pattern(s).
4593 (define_insn_and_split "subti3"
4594 [(set (match_operand:TI 0 "register_operand" "=&d")
4595 (minus:TI (match_operand:TI 1 "register_operand" "0")
4596 (match_operand:TI 2 "general_operand" "do") ) )
4597 (clobber (reg:CC CC_REGNUM))]
4600 "&& reload_completed"
4602 [(set (reg:CCL2 CC_REGNUM)
4603 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4605 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4607 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4608 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4609 (clobber (reg:CC CC_REGNUM))])]
4610 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4611 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4612 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4613 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4614 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4615 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4618 ; subdi3 instruction pattern(s).
4621 (define_expand "subdi3"
4623 [(set (match_operand:DI 0 "register_operand" "")
4624 (minus:DI (match_operand:DI 1 "register_operand" "")
4625 (match_operand:DI 2 "general_operand" "")))
4626 (clobber (reg:CC CC_REGNUM))])]
4630 (define_insn "*subdi3_sign"
4631 [(set (match_operand:DI 0 "register_operand" "=d,d")
4632 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4633 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4634 (clobber (reg:CC CC_REGNUM))]
4639 [(set_attr "op_type" "RRE,RXY")
4640 (set_attr "z10prop" "z10_c,*")])
4642 (define_insn "*subdi3_zero_cc"
4643 [(set (reg CC_REGNUM)
4644 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4645 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4647 (set (match_operand:DI 0 "register_operand" "=d,d")
4648 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4649 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4653 [(set_attr "op_type" "RRE,RXY")
4654 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4656 (define_insn "*subdi3_zero_cconly"
4657 [(set (reg CC_REGNUM)
4658 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4659 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4661 (clobber (match_scratch:DI 0 "=d,d"))]
4662 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4666 [(set_attr "op_type" "RRE,RXY")
4667 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4669 (define_insn "*subdi3_zero"
4670 [(set (match_operand:DI 0 "register_operand" "=d,d")
4671 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4672 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4673 (clobber (reg:CC CC_REGNUM))]
4678 [(set_attr "op_type" "RRE,RXY")
4679 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4681 (define_insn_and_split "*subdi3_31z"
4682 [(set (match_operand:DI 0 "register_operand" "=&d")
4683 (minus:DI (match_operand:DI 1 "register_operand" "0")
4684 (match_operand:DI 2 "general_operand" "do") ) )
4685 (clobber (reg:CC CC_REGNUM))]
4686 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4688 "&& reload_completed"
4690 [(set (reg:CCL2 CC_REGNUM)
4691 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4693 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4695 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4696 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4697 (clobber (reg:CC CC_REGNUM))])]
4698 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4699 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4700 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4701 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4702 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4703 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4705 (define_insn_and_split "*subdi3_31"
4706 [(set (match_operand:DI 0 "register_operand" "=&d")
4707 (minus:DI (match_operand:DI 1 "register_operand" "0")
4708 (match_operand:DI 2 "general_operand" "do") ) )
4709 (clobber (reg:CC CC_REGNUM))]
4712 "&& reload_completed"
4714 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4715 (clobber (reg:CC CC_REGNUM))])
4717 [(set (reg:CCL2 CC_REGNUM)
4718 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4720 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4722 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4724 (label_ref (match_dup 9))))
4726 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4727 (clobber (reg:CC CC_REGNUM))])
4729 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4730 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4731 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4732 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4733 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4734 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4735 operands[9] = gen_label_rtx ();")
4738 ; subsi3 instruction pattern(s).
4741 (define_expand "subsi3"
4743 [(set (match_operand:SI 0 "register_operand" "")
4744 (minus:SI (match_operand:SI 1 "register_operand" "")
4745 (match_operand:SI 2 "general_operand" "")))
4746 (clobber (reg:CC CC_REGNUM))])]
4750 (define_insn "*subsi3_sign"
4751 [(set (match_operand:SI 0 "register_operand" "=d,d")
4752 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4753 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4754 (clobber (reg:CC CC_REGNUM))]
4759 [(set_attr "op_type" "RX,RXY")])
4762 ; sub(di|si)3 instruction pattern(s).
4765 ; sr, s, sy, sgr, sg
4766 (define_insn "*sub<mode>3"
4767 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4768 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4769 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4770 (clobber (reg:CC CC_REGNUM))]
4776 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4777 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4779 ; slr, sl, sly, slgr, slg
4780 (define_insn "*sub<mode>3_borrow_cc"
4781 [(set (reg CC_REGNUM)
4782 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4783 (match_operand:GPR 2 "general_operand" "d,R,T"))
4785 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4786 (minus:GPR (match_dup 1) (match_dup 2)))]
4787 "s390_match_ccmode (insn, CCL2mode)"
4792 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4793 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4795 ; slr, sl, sly, slgr, slg
4796 (define_insn "*sub<mode>3_borrow_cconly"
4797 [(set (reg CC_REGNUM)
4798 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4799 (match_operand:GPR 2 "general_operand" "d,R,T"))
4801 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4802 "s390_match_ccmode (insn, CCL2mode)"
4807 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4808 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4810 ; slr, sl, sly, slgr, slg
4811 (define_insn "*sub<mode>3_cc"
4812 [(set (reg CC_REGNUM)
4813 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4814 (match_operand:GPR 2 "general_operand" "d,R,T"))
4816 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4817 (minus:GPR (match_dup 1) (match_dup 2)))]
4818 "s390_match_ccmode (insn, CCLmode)"
4823 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4824 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4826 ; slr, sl, sly, slgr, slg
4827 (define_insn "*sub<mode>3_cc2"
4828 [(set (reg CC_REGNUM)
4829 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4830 (match_operand:GPR 2 "general_operand" "d,R,T")))
4831 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4832 (minus:GPR (match_dup 1) (match_dup 2)))]
4833 "s390_match_ccmode (insn, CCL3mode)"
4838 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4839 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4841 ; slr, sl, sly, slgr, slg
4842 (define_insn "*sub<mode>3_cconly"
4843 [(set (reg CC_REGNUM)
4844 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4845 (match_operand:GPR 2 "general_operand" "d,R,T"))
4847 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4848 "s390_match_ccmode (insn, CCLmode)"
4853 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4854 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4857 ; slr, sl, sly, slgr, slg
4858 (define_insn "*sub<mode>3_cconly2"
4859 [(set (reg CC_REGNUM)
4860 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4861 (match_operand:GPR 2 "general_operand" "d,R,T")))
4862 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4863 "s390_match_ccmode (insn, CCL3mode)"
4868 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4869 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4873 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4876 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4877 (define_insn "sub<mode>3"
4878 [(set (match_operand:FP 0 "register_operand" "=f, f")
4879 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4880 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4881 (clobber (reg:CC CC_REGNUM))]
4884 s<xde><bt>r\t%0,<op1>%2
4886 [(set_attr "op_type" "<RRer>,RXE")
4887 (set_attr "type" "fsimp<mode>")])
4889 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4890 (define_insn "*sub<mode>3_cc"
4891 [(set (reg CC_REGNUM)
4892 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4893 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4894 (match_operand:FP 3 "const0_operand" "")))
4895 (set (match_operand:FP 0 "register_operand" "=f,f")
4896 (minus:FP (match_dup 1) (match_dup 2)))]
4897 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4899 s<xde><bt>r\t%0,<op1>%2
4901 [(set_attr "op_type" "<RRer>,RXE")
4902 (set_attr "type" "fsimp<mode>")])
4904 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4905 (define_insn "*sub<mode>3_cconly"
4906 [(set (reg CC_REGNUM)
4907 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4908 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4909 (match_operand:FP 3 "const0_operand" "")))
4910 (clobber (match_scratch:FP 0 "=f,f"))]
4911 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4913 s<xde><bt>r\t%0,<op1>%2
4915 [(set_attr "op_type" "<RRer>,RXE")
4916 (set_attr "type" "fsimp<mode>")])
4920 ;;- Conditional add/subtract instructions.
4924 ; add(di|si)cc instruction pattern(s).
4927 ; the following 4 patterns are used when the result of an add with
4928 ; carry is checked for an overflow condition
4930 ; op1 + op2 + c < op1
4932 ; alcr, alc, alcgr, alcg
4933 (define_insn "*add<mode>3_alc_carry1_cc"
4934 [(set (reg CC_REGNUM)
4936 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4937 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4938 (match_operand:GPR 2 "general_operand" "d,RT"))
4940 (set (match_operand:GPR 0 "register_operand" "=d,d")
4941 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4942 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4946 [(set_attr "op_type" "RRE,RXY")])
4948 ; alcr, alc, alcgr, alcg
4949 (define_insn "*add<mode>3_alc_carry1_cconly"
4950 [(set (reg CC_REGNUM)
4952 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4953 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4954 (match_operand:GPR 2 "general_operand" "d,RT"))
4956 (clobber (match_scratch:GPR 0 "=d,d"))]
4957 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4961 [(set_attr "op_type" "RRE,RXY")])
4963 ; op1 + op2 + c < op2
4965 ; alcr, alc, alcgr, alcg
4966 (define_insn "*add<mode>3_alc_carry2_cc"
4967 [(set (reg CC_REGNUM)
4969 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4970 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4971 (match_operand:GPR 2 "general_operand" "d,RT"))
4973 (set (match_operand:GPR 0 "register_operand" "=d,d")
4974 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4975 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4979 [(set_attr "op_type" "RRE,RXY")])
4981 ; alcr, alc, alcgr, alcg
4982 (define_insn "*add<mode>3_alc_carry2_cconly"
4983 [(set (reg CC_REGNUM)
4985 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4986 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4987 (match_operand:GPR 2 "general_operand" "d,RT"))
4989 (clobber (match_scratch:GPR 0 "=d,d"))]
4990 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4994 [(set_attr "op_type" "RRE,RXY")])
4996 ; alcr, alc, alcgr, alcg
4997 (define_insn "*add<mode>3_alc_cc"
4998 [(set (reg CC_REGNUM)
5000 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5001 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5002 (match_operand:GPR 2 "general_operand" "d,RT"))
5004 (set (match_operand:GPR 0 "register_operand" "=d,d")
5005 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5006 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5010 [(set_attr "op_type" "RRE,RXY")])
5012 ; alcr, alc, alcgr, alcg
5013 (define_insn "*add<mode>3_alc"
5014 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5015 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5016 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5017 (match_operand:GPR 2 "general_operand" "d,RT")))
5018 (clobber (reg:CC CC_REGNUM))]
5023 [(set_attr "op_type" "RRE,RXY")])
5025 ; slbr, slb, slbgr, slbg
5026 (define_insn "*sub<mode>3_slb_cc"
5027 [(set (reg CC_REGNUM)
5029 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5030 (match_operand:GPR 2 "general_operand" "d,RT"))
5031 (match_operand:GPR 3 "s390_slb_comparison" ""))
5033 (set (match_operand:GPR 0 "register_operand" "=d,d")
5034 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5035 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5039 [(set_attr "op_type" "RRE,RXY")
5040 (set_attr "z10prop" "z10_c,*")])
5042 ; slbr, slb, slbgr, slbg
5043 (define_insn "*sub<mode>3_slb"
5044 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5045 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5046 (match_operand:GPR 2 "general_operand" "d,RT"))
5047 (match_operand:GPR 3 "s390_slb_comparison" "")))
5048 (clobber (reg:CC CC_REGNUM))]
5053 [(set_attr "op_type" "RRE,RXY")
5054 (set_attr "z10prop" "z10_c,*")])
5056 (define_expand "add<mode>cc"
5057 [(match_operand:GPR 0 "register_operand" "")
5058 (match_operand 1 "comparison_operator" "")
5059 (match_operand:GPR 2 "register_operand" "")
5060 (match_operand:GPR 3 "const_int_operand" "")]
5062 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5063 s390_compare_op0, s390_compare_op1,
5064 operands[0], operands[2],
5065 operands[3])) FAIL; DONE;")
5068 ; scond instruction pattern(s).
5071 (define_insn_and_split "*scond<mode>"
5072 [(set (match_operand:GPR 0 "register_operand" "=&d")
5073 (match_operand:GPR 1 "s390_alc_comparison" ""))
5074 (clobber (reg:CC CC_REGNUM))]
5077 "&& reload_completed"
5078 [(set (match_dup 0) (const_int 0))
5080 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5082 (clobber (reg:CC CC_REGNUM))])]
5085 (define_insn_and_split "*scond<mode>_neg"
5086 [(set (match_operand:GPR 0 "register_operand" "=&d")
5087 (match_operand:GPR 1 "s390_slb_comparison" ""))
5088 (clobber (reg:CC CC_REGNUM))]
5091 "&& reload_completed"
5092 [(set (match_dup 0) (const_int 0))
5094 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5096 (clobber (reg:CC CC_REGNUM))])
5098 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5099 (clobber (reg:CC CC_REGNUM))])]
5103 (define_expand "s<code>"
5104 [(set (match_operand:SI 0 "register_operand" "")
5105 (SCOND (match_dup 0)
5108 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
5109 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5111 (define_expand "seq"
5113 [(set (match_operand:SI 0 "register_operand" "=d")
5115 (clobber (reg:CC CC_REGNUM))])
5117 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
5118 (clobber (reg:CC CC_REGNUM))])]
5121 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
5123 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
5124 PUT_MODE (operands[1], SImode);
5127 (define_insn_and_split "*sne"
5128 [(set (match_operand:SI 0 "register_operand" "=d")
5129 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5131 (clobber (reg:CC CC_REGNUM))]
5136 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5137 (clobber (reg:CC CC_REGNUM))])])
5141 ;;- Multiply instructions.
5145 ; muldi3 instruction pattern(s).
5148 (define_insn "*muldi3_sign"
5149 [(set (match_operand:DI 0 "register_operand" "=d,d")
5150 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5151 (match_operand:DI 1 "register_operand" "0,0")))]
5156 [(set_attr "op_type" "RRE,RXY")
5157 (set_attr "type" "imuldi")])
5159 (define_insn "muldi3"
5160 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5161 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5162 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5169 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5170 (set_attr "type" "imuldi")
5171 (set_attr "cpu_facility" "*,*,*,z10")])
5174 ; mulsi3 instruction pattern(s).
5177 (define_insn "*mulsi3_sign"
5178 [(set (match_operand:SI 0 "register_operand" "=d,d")
5179 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5180 (match_operand:SI 1 "register_operand" "0,0")))]
5185 [(set_attr "op_type" "RX,RXY")
5186 (set_attr "type" "imulhi")
5187 (set_attr "cpu_facility" "*,z10")])
5189 (define_insn "mulsi3"
5190 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5191 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5192 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5200 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5201 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5202 (set_attr "cpu_facility" "*,*,*,*,z10")])
5205 ; mulsidi3 instruction pattern(s).
5208 (define_insn "mulsidi3"
5209 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5210 (mult:DI (sign_extend:DI
5211 (match_operand:SI 1 "register_operand" "%0,0,0"))
5213 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5219 [(set_attr "op_type" "RR,RX,RXY")
5220 (set_attr "type" "imulsi")
5221 (set_attr "cpu_facility" "*,*,z10")])
5224 ; umulsidi3 instruction pattern(s).
5227 (define_insn "umulsidi3"
5228 [(set (match_operand:DI 0 "register_operand" "=d,d")
5229 (mult:DI (zero_extend:DI
5230 (match_operand:SI 1 "register_operand" "%0,0"))
5232 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5233 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5237 [(set_attr "op_type" "RRE,RXY")
5238 (set_attr "type" "imulsi")])
5241 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5244 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5245 (define_insn "mul<mode>3"
5246 [(set (match_operand:FP 0 "register_operand" "=f,f")
5247 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5248 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5251 m<xdee><bt>r\t%0,<op1>%2
5253 [(set_attr "op_type" "<RRer>,RXE")
5254 (set_attr "type" "fmul<mode>")])
5256 ; madbr, maebr, maxb, madb, maeb
5257 (define_insn "*fmadd<mode>"
5258 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5259 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
5260 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5261 (match_operand:DSF 3 "register_operand" "0,0")))]
5262 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5266 [(set_attr "op_type" "RRE,RXE")
5267 (set_attr "type" "fmul<mode>")])
5269 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5270 (define_insn "*fmsub<mode>"
5271 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5272 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
5273 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5274 (match_operand:DSF 3 "register_operand" "0,0")))]
5275 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5279 [(set_attr "op_type" "RRE,RXE")
5280 (set_attr "type" "fmul<mode>")])
5283 ;;- Divide and modulo instructions.
5287 ; divmoddi4 instruction pattern(s).
5290 (define_expand "divmoddi4"
5291 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5292 (div:DI (match_operand:DI 1 "register_operand" "")
5293 (match_operand:DI 2 "general_operand" "")))
5294 (set (match_operand:DI 3 "general_operand" "")
5295 (mod:DI (match_dup 1) (match_dup 2)))])
5296 (clobber (match_dup 4))]
5299 rtx insn, div_equal, mod_equal;
5301 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5302 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5304 operands[4] = gen_reg_rtx(TImode);
5305 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5307 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5308 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5310 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5311 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5316 (define_insn "divmodtidi3"
5317 [(set (match_operand:TI 0 "register_operand" "=d,d")
5321 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5322 (match_operand:DI 2 "general_operand" "d,RT")))
5324 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5329 [(set_attr "op_type" "RRE,RXY")
5330 (set_attr "type" "idiv")])
5332 (define_insn "divmodtisi3"
5333 [(set (match_operand:TI 0 "register_operand" "=d,d")
5337 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5339 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5342 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5347 [(set_attr "op_type" "RRE,RXY")
5348 (set_attr "type" "idiv")])
5351 ; udivmoddi4 instruction pattern(s).
5354 (define_expand "udivmoddi4"
5355 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5356 (udiv:DI (match_operand:DI 1 "general_operand" "")
5357 (match_operand:DI 2 "nonimmediate_operand" "")))
5358 (set (match_operand:DI 3 "general_operand" "")
5359 (umod:DI (match_dup 1) (match_dup 2)))])
5360 (clobber (match_dup 4))]
5363 rtx insn, div_equal, mod_equal, equal;
5365 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5366 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5367 equal = gen_rtx_IOR (TImode,
5368 gen_rtx_ASHIFT (TImode,
5369 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5371 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5373 operands[4] = gen_reg_rtx(TImode);
5374 emit_clobber (operands[4]);
5375 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5376 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5378 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5379 set_unique_reg_note (insn, REG_EQUAL, equal);
5381 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5382 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5384 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5385 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5390 (define_insn "udivmodtidi3"
5391 [(set (match_operand:TI 0 "register_operand" "=d,d")
5396 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5398 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5402 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5407 [(set_attr "op_type" "RRE,RXY")
5408 (set_attr "type" "idiv")])
5411 ; divmodsi4 instruction pattern(s).
5414 (define_expand "divmodsi4"
5415 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5416 (div:SI (match_operand:SI 1 "general_operand" "")
5417 (match_operand:SI 2 "nonimmediate_operand" "")))
5418 (set (match_operand:SI 3 "general_operand" "")
5419 (mod:SI (match_dup 1) (match_dup 2)))])
5420 (clobber (match_dup 4))]
5423 rtx insn, div_equal, mod_equal, equal;
5425 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5426 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5427 equal = gen_rtx_IOR (DImode,
5428 gen_rtx_ASHIFT (DImode,
5429 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5431 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5433 operands[4] = gen_reg_rtx(DImode);
5434 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5436 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5437 set_unique_reg_note (insn, REG_EQUAL, equal);
5439 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5440 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5442 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5443 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5448 (define_insn "divmoddisi3"
5449 [(set (match_operand:DI 0 "register_operand" "=d,d")
5454 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5456 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5460 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5465 [(set_attr "op_type" "RR,RX")
5466 (set_attr "type" "idiv")])
5469 ; udivsi3 and umodsi3 instruction pattern(s).
5472 (define_expand "udivmodsi4"
5473 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5474 (udiv:SI (match_operand:SI 1 "general_operand" "")
5475 (match_operand:SI 2 "nonimmediate_operand" "")))
5476 (set (match_operand:SI 3 "general_operand" "")
5477 (umod:SI (match_dup 1) (match_dup 2)))])
5478 (clobber (match_dup 4))]
5479 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5481 rtx insn, div_equal, mod_equal, equal;
5483 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5484 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5485 equal = gen_rtx_IOR (DImode,
5486 gen_rtx_ASHIFT (DImode,
5487 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5489 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5491 operands[4] = gen_reg_rtx(DImode);
5492 emit_clobber (operands[4]);
5493 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5494 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5496 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5497 set_unique_reg_note (insn, REG_EQUAL, equal);
5499 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5500 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5502 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5503 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5508 (define_insn "udivmoddisi3"
5509 [(set (match_operand:DI 0 "register_operand" "=d,d")
5514 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5516 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5520 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5521 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5525 [(set_attr "op_type" "RRE,RXY")
5526 (set_attr "type" "idiv")])
5528 (define_expand "udivsi3"
5529 [(set (match_operand:SI 0 "register_operand" "=d")
5530 (udiv:SI (match_operand:SI 1 "general_operand" "")
5531 (match_operand:SI 2 "general_operand" "")))
5532 (clobber (match_dup 3))]
5533 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5535 rtx insn, udiv_equal, umod_equal, equal;
5537 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5538 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5539 equal = gen_rtx_IOR (DImode,
5540 gen_rtx_ASHIFT (DImode,
5541 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5543 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5545 operands[3] = gen_reg_rtx (DImode);
5547 if (CONSTANT_P (operands[2]))
5549 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5551 rtx label1 = gen_label_rtx ();
5553 operands[1] = make_safe_from (operands[1], operands[0]);
5554 emit_move_insn (operands[0], const0_rtx);
5555 emit_insn (gen_cmpsi (operands[1], operands[2]));
5556 emit_jump_insn (gen_bltu (label1));
5557 emit_move_insn (operands[0], const1_rtx);
5558 emit_label (label1);
5562 operands[2] = force_reg (SImode, operands[2]);
5563 operands[2] = make_safe_from (operands[2], operands[0]);
5565 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5566 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5568 set_unique_reg_note (insn, REG_EQUAL, equal);
5570 insn = emit_move_insn (operands[0],
5571 gen_lowpart (SImode, operands[3]));
5572 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5577 rtx label1 = gen_label_rtx ();
5578 rtx label2 = gen_label_rtx ();
5579 rtx label3 = gen_label_rtx ();
5581 operands[1] = force_reg (SImode, operands[1]);
5582 operands[1] = make_safe_from (operands[1], operands[0]);
5583 operands[2] = force_reg (SImode, operands[2]);
5584 operands[2] = make_safe_from (operands[2], operands[0]);
5586 emit_move_insn (operands[0], const0_rtx);
5587 emit_insn (gen_cmpsi (operands[2], operands[1]));
5588 emit_jump_insn (gen_bgtu (label3));
5589 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5590 emit_jump_insn (gen_blt (label2));
5591 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5592 emit_jump_insn (gen_beq (label1));
5593 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5594 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5596 set_unique_reg_note (insn, REG_EQUAL, equal);
5598 insn = emit_move_insn (operands[0],
5599 gen_lowpart (SImode, operands[3]));
5600 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5603 emit_label (label1);
5604 emit_move_insn (operands[0], operands[1]);
5606 emit_label (label2);
5607 emit_move_insn (operands[0], const1_rtx);
5608 emit_label (label3);
5610 emit_move_insn (operands[0], operands[0]);
5614 (define_expand "umodsi3"
5615 [(set (match_operand:SI 0 "register_operand" "=d")
5616 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5617 (match_operand:SI 2 "nonimmediate_operand" "")))
5618 (clobber (match_dup 3))]
5619 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5621 rtx insn, udiv_equal, umod_equal, equal;
5623 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5624 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5625 equal = gen_rtx_IOR (DImode,
5626 gen_rtx_ASHIFT (DImode,
5627 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5629 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5631 operands[3] = gen_reg_rtx (DImode);
5633 if (CONSTANT_P (operands[2]))
5635 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5637 rtx label1 = gen_label_rtx ();
5639 operands[1] = make_safe_from (operands[1], operands[0]);
5640 emit_move_insn (operands[0], operands[1]);
5641 emit_insn (gen_cmpsi (operands[0], operands[2]));
5642 emit_jump_insn (gen_bltu (label1));
5643 emit_insn (gen_abssi2 (operands[0], operands[2]));
5644 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5645 emit_label (label1);
5649 operands[2] = force_reg (SImode, operands[2]);
5650 operands[2] = make_safe_from (operands[2], operands[0]);
5652 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5653 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5655 set_unique_reg_note (insn, REG_EQUAL, equal);
5657 insn = emit_move_insn (operands[0],
5658 gen_highpart (SImode, operands[3]));
5659 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5664 rtx label1 = gen_label_rtx ();
5665 rtx label2 = gen_label_rtx ();
5666 rtx label3 = gen_label_rtx ();
5668 operands[1] = force_reg (SImode, operands[1]);
5669 operands[1] = make_safe_from (operands[1], operands[0]);
5670 operands[2] = force_reg (SImode, operands[2]);
5671 operands[2] = make_safe_from (operands[2], operands[0]);
5673 emit_move_insn(operands[0], operands[1]);
5674 emit_insn (gen_cmpsi (operands[2], operands[1]));
5675 emit_jump_insn (gen_bgtu (label3));
5676 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5677 emit_jump_insn (gen_blt (label2));
5678 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5679 emit_jump_insn (gen_beq (label1));
5680 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5681 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5683 set_unique_reg_note (insn, REG_EQUAL, equal);
5685 insn = emit_move_insn (operands[0],
5686 gen_highpart (SImode, operands[3]));
5687 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5690 emit_label (label1);
5691 emit_move_insn (operands[0], const0_rtx);
5693 emit_label (label2);
5694 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5695 emit_label (label3);
5701 ; div(df|sf)3 instruction pattern(s).
5704 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5705 (define_insn "div<mode>3"
5706 [(set (match_operand:FP 0 "register_operand" "=f,f")
5707 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5708 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5711 d<xde><bt>r\t%0,<op1>%2
5713 [(set_attr "op_type" "<RRer>,RXE")
5714 (set_attr "type" "fdiv<mode>")])
5718 ;;- And instructions.
5721 (define_expand "and<mode>3"
5722 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5723 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5724 (match_operand:INT 2 "general_operand" "")))
5725 (clobber (reg:CC CC_REGNUM))]
5727 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5730 ; anddi3 instruction pattern(s).
5733 (define_insn "*anddi3_cc"
5734 [(set (reg CC_REGNUM)
5735 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5736 (match_operand:DI 2 "general_operand" "d,RT"))
5738 (set (match_operand:DI 0 "register_operand" "=d,d")
5739 (and:DI (match_dup 1) (match_dup 2)))]
5740 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5744 [(set_attr "op_type" "RRE,RXY")
5745 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5747 (define_insn "*anddi3_cconly"
5748 [(set (reg CC_REGNUM)
5749 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5750 (match_operand:DI 2 "general_operand" "d,RT"))
5752 (clobber (match_scratch:DI 0 "=d,d"))]
5753 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5754 /* Do not steal TM patterns. */
5755 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5759 [(set_attr "op_type" "RRE,RXY")
5760 (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
5762 (define_insn "*anddi3"
5763 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5764 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5765 "%d,o,0,0,0,0,0,0,0,0,0,0")
5766 (match_operand:DI 2 "general_operand"
5767 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5768 (clobber (reg:CC CC_REGNUM))]
5769 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5783 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
5784 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
5785 (set_attr "z10prop" "*,
5799 [(set (match_operand:DI 0 "s_operand" "")
5800 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5801 (clobber (reg:CC CC_REGNUM))]
5804 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5805 (clobber (reg:CC CC_REGNUM))])]
5806 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5810 ; andsi3 instruction pattern(s).
5813 (define_insn "*andsi3_cc"
5814 [(set (reg CC_REGNUM)
5815 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5816 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5818 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5819 (and:SI (match_dup 1) (match_dup 2)))]
5820 "s390_match_ccmode(insn, CCTmode)"
5826 [(set_attr "op_type" "RIL,RR,RX,RXY")
5827 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5829 (define_insn "*andsi3_cconly"
5830 [(set (reg CC_REGNUM)
5831 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5832 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5834 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5835 "s390_match_ccmode(insn, CCTmode)
5836 /* Do not steal TM patterns. */
5837 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5843 [(set_attr "op_type" "RIL,RR,RX,RXY")
5844 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5846 (define_insn "*andsi3_zarch"
5847 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5848 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5849 "%d,o,0,0,0,0,0,0,0,0")
5850 (match_operand:SI 2 "general_operand"
5851 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5852 (clobber (reg:CC CC_REGNUM))]
5853 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5865 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
5866 (set_attr "z10prop" "*,
5877 (define_insn "*andsi3_esa"
5878 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5879 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5880 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5881 (clobber (reg:CC CC_REGNUM))]
5882 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5888 [(set_attr "op_type" "RR,RX,SI,SS")
5889 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
5893 [(set (match_operand:SI 0 "s_operand" "")
5894 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5895 (clobber (reg:CC CC_REGNUM))]
5898 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5899 (clobber (reg:CC CC_REGNUM))])]
5900 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5903 ; andhi3 instruction pattern(s).
5906 (define_insn "*andhi3_zarch"
5907 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5908 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5909 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5910 (clobber (reg:CC CC_REGNUM))]
5911 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5917 [(set_attr "op_type" "RR,RI,SI,SS")
5918 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
5921 (define_insn "*andhi3_esa"
5922 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5923 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5924 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5925 (clobber (reg:CC CC_REGNUM))]
5926 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5931 [(set_attr "op_type" "RR,SI,SS")
5932 (set_attr "z10prop" "z10_super_E1,*,*")
5936 [(set (match_operand:HI 0 "s_operand" "")
5937 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5938 (clobber (reg:CC CC_REGNUM))]
5941 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5942 (clobber (reg:CC CC_REGNUM))])]
5943 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5946 ; andqi3 instruction pattern(s).
5949 (define_insn "*andqi3_zarch"
5950 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5951 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5952 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5953 (clobber (reg:CC CC_REGNUM))]
5954 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5961 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
5962 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
5964 (define_insn "*andqi3_esa"
5965 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5966 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5967 (match_operand:QI 2 "general_operand" "d,n,Q")))
5968 (clobber (reg:CC CC_REGNUM))]
5969 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5974 [(set_attr "op_type" "RR,SI,SS")
5975 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
5978 ; Block and (NC) patterns.
5982 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5983 (and:BLK (match_dup 0)
5984 (match_operand:BLK 1 "memory_operand" "Q")))
5985 (use (match_operand 2 "const_int_operand" "n"))
5986 (clobber (reg:CC CC_REGNUM))]
5987 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5988 "nc\t%O0(%2,%R0),%S1"
5989 [(set_attr "op_type" "SS")])
5992 [(set (match_operand 0 "memory_operand" "")
5994 (match_operand 1 "memory_operand" "")))
5995 (clobber (reg:CC CC_REGNUM))]
5997 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5998 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6000 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6002 (clobber (reg:CC CC_REGNUM))])]
6004 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6005 operands[0] = adjust_address (operands[0], BLKmode, 0);
6006 operands[1] = adjust_address (operands[1], BLKmode, 0);
6011 [(set (match_operand:BLK 0 "memory_operand" "")
6012 (and:BLK (match_dup 0)
6013 (match_operand:BLK 1 "memory_operand" "")))
6014 (use (match_operand 2 "const_int_operand" ""))
6015 (clobber (reg:CC CC_REGNUM))])
6017 [(set (match_operand:BLK 3 "memory_operand" "")
6018 (and:BLK (match_dup 3)
6019 (match_operand:BLK 4 "memory_operand" "")))
6020 (use (match_operand 5 "const_int_operand" ""))
6021 (clobber (reg:CC CC_REGNUM))])]
6022 "s390_offset_p (operands[0], operands[3], operands[2])
6023 && s390_offset_p (operands[1], operands[4], operands[2])
6024 && !s390_overlap_p (operands[0], operands[1],
6025 INTVAL (operands[2]) + INTVAL (operands[5]))
6026 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6028 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6030 (clobber (reg:CC CC_REGNUM))])]
6031 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6032 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6033 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6037 ;;- Bit set (inclusive or) instructions.
6040 (define_expand "ior<mode>3"
6041 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6042 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6043 (match_operand:INT 2 "general_operand" "")))
6044 (clobber (reg:CC CC_REGNUM))]
6046 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6049 ; iordi3 instruction pattern(s).
6052 (define_insn "*iordi3_cc"
6053 [(set (reg CC_REGNUM)
6054 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6055 (match_operand:DI 2 "general_operand" "d,RT"))
6057 (set (match_operand:DI 0 "register_operand" "=d,d")
6058 (ior:DI (match_dup 1) (match_dup 2)))]
6059 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6063 [(set_attr "op_type" "RRE,RXY")
6064 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6066 (define_insn "*iordi3_cconly"
6067 [(set (reg CC_REGNUM)
6068 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6069 (match_operand:DI 2 "general_operand" "d,RT"))
6071 (clobber (match_scratch:DI 0 "=d,d"))]
6072 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6076 [(set_attr "op_type" "RRE,RXY")
6077 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6079 (define_insn "*iordi3"
6080 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6081 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6082 (match_operand:DI 2 "general_operand"
6083 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6084 (clobber (reg:CC CC_REGNUM))]
6085 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6097 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
6098 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
6099 (set_attr "z10prop" "z10_super_E1,
6111 [(set (match_operand:DI 0 "s_operand" "")
6112 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6113 (clobber (reg:CC CC_REGNUM))]
6116 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6117 (clobber (reg:CC CC_REGNUM))])]
6118 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6121 ; iorsi3 instruction pattern(s).
6124 (define_insn "*iorsi3_cc"
6125 [(set (reg CC_REGNUM)
6126 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6127 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6129 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6130 (ior:SI (match_dup 1) (match_dup 2)))]
6131 "s390_match_ccmode(insn, CCTmode)"
6137 [(set_attr "op_type" "RIL,RR,RX,RXY")
6138 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6140 (define_insn "*iorsi3_cconly"
6141 [(set (reg CC_REGNUM)
6142 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6143 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6145 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6146 "s390_match_ccmode(insn, CCTmode)"
6152 [(set_attr "op_type" "RIL,RR,RX,RXY")
6153 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6155 (define_insn "*iorsi3_zarch"
6156 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
6157 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
6158 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
6159 (clobber (reg:CC CC_REGNUM))]
6160 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6170 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
6171 (set_attr "z10prop" "z10_super_E1,
6180 (define_insn "*iorsi3_esa"
6181 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6182 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6183 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6184 (clobber (reg:CC CC_REGNUM))]
6185 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6191 [(set_attr "op_type" "RR,RX,SI,SS")
6192 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6195 [(set (match_operand:SI 0 "s_operand" "")
6196 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6197 (clobber (reg:CC CC_REGNUM))]
6200 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6201 (clobber (reg:CC CC_REGNUM))])]
6202 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6205 ; iorhi3 instruction pattern(s).
6208 (define_insn "*iorhi3_zarch"
6209 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6210 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6211 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
6212 (clobber (reg:CC CC_REGNUM))]
6213 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6219 [(set_attr "op_type" "RR,RI,SI,SS")
6220 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6222 (define_insn "*iorhi3_esa"
6223 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6224 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6225 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6226 (clobber (reg:CC CC_REGNUM))]
6227 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6232 [(set_attr "op_type" "RR,SI,SS")
6233 (set_attr "z10prop" "z10_super_E1,*,*")])
6236 [(set (match_operand:HI 0 "s_operand" "")
6237 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6238 (clobber (reg:CC CC_REGNUM))]
6241 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6242 (clobber (reg:CC CC_REGNUM))])]
6243 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6246 ; iorqi3 instruction pattern(s).
6249 (define_insn "*iorqi3_zarch"
6250 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6251 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6252 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6253 (clobber (reg:CC CC_REGNUM))]
6254 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6261 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6262 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6264 (define_insn "*iorqi3_esa"
6265 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6266 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6267 (match_operand:QI 2 "general_operand" "d,n,Q")))
6268 (clobber (reg:CC CC_REGNUM))]
6269 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6274 [(set_attr "op_type" "RR,SI,SS")
6275 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6278 ; Block inclusive or (OC) patterns.
6282 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6283 (ior:BLK (match_dup 0)
6284 (match_operand:BLK 1 "memory_operand" "Q")))
6285 (use (match_operand 2 "const_int_operand" "n"))
6286 (clobber (reg:CC CC_REGNUM))]
6287 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6288 "oc\t%O0(%2,%R0),%S1"
6289 [(set_attr "op_type" "SS")])
6292 [(set (match_operand 0 "memory_operand" "")
6294 (match_operand 1 "memory_operand" "")))
6295 (clobber (reg:CC CC_REGNUM))]
6297 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6298 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6300 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6302 (clobber (reg:CC CC_REGNUM))])]
6304 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6305 operands[0] = adjust_address (operands[0], BLKmode, 0);
6306 operands[1] = adjust_address (operands[1], BLKmode, 0);
6311 [(set (match_operand:BLK 0 "memory_operand" "")
6312 (ior:BLK (match_dup 0)
6313 (match_operand:BLK 1 "memory_operand" "")))
6314 (use (match_operand 2 "const_int_operand" ""))
6315 (clobber (reg:CC CC_REGNUM))])
6317 [(set (match_operand:BLK 3 "memory_operand" "")
6318 (ior:BLK (match_dup 3)
6319 (match_operand:BLK 4 "memory_operand" "")))
6320 (use (match_operand 5 "const_int_operand" ""))
6321 (clobber (reg:CC CC_REGNUM))])]
6322 "s390_offset_p (operands[0], operands[3], operands[2])
6323 && s390_offset_p (operands[1], operands[4], operands[2])
6324 && !s390_overlap_p (operands[0], operands[1],
6325 INTVAL (operands[2]) + INTVAL (operands[5]))
6326 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6328 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6330 (clobber (reg:CC CC_REGNUM))])]
6331 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6332 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6333 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6337 ;;- Xor instructions.
6340 (define_expand "xor<mode>3"
6341 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6342 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6343 (match_operand:INT 2 "general_operand" "")))
6344 (clobber (reg:CC CC_REGNUM))]
6346 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6349 ; xordi3 instruction pattern(s).
6352 (define_insn "*xordi3_cc"
6353 [(set (reg CC_REGNUM)
6354 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6355 (match_operand:DI 2 "general_operand" "d,RT"))
6357 (set (match_operand:DI 0 "register_operand" "=d,d")
6358 (xor:DI (match_dup 1) (match_dup 2)))]
6359 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6363 [(set_attr "op_type" "RRE,RXY")
6364 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6366 (define_insn "*xordi3_cconly"
6367 [(set (reg CC_REGNUM)
6368 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6369 (match_operand:DI 2 "general_operand" "d,RT"))
6371 (clobber (match_scratch:DI 0 "=d,d"))]
6372 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6376 [(set_attr "op_type" "RRE,RXY")
6377 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6379 (define_insn "*xordi3"
6380 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6381 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6382 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6383 (clobber (reg:CC CC_REGNUM))]
6384 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6392 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
6393 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
6394 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6397 [(set (match_operand:DI 0 "s_operand" "")
6398 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6399 (clobber (reg:CC CC_REGNUM))]
6402 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6403 (clobber (reg:CC CC_REGNUM))])]
6404 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6407 ; xorsi3 instruction pattern(s).
6410 (define_insn "*xorsi3_cc"
6411 [(set (reg CC_REGNUM)
6412 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6413 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6415 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6416 (xor:SI (match_dup 1) (match_dup 2)))]
6417 "s390_match_ccmode(insn, CCTmode)"
6423 [(set_attr "op_type" "RIL,RR,RX,RXY")
6424 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6426 (define_insn "*xorsi3_cconly"
6427 [(set (reg CC_REGNUM)
6428 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6429 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6431 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6432 "s390_match_ccmode(insn, CCTmode)"
6438 [(set_attr "op_type" "RIL,RR,RX,RXY")
6439 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6441 (define_insn "*xorsi3"
6442 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6443 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6444 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
6445 (clobber (reg:CC CC_REGNUM))]
6446 "s390_logical_operator_ok_p (operands)"
6454 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
6455 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6458 [(set (match_operand:SI 0 "s_operand" "")
6459 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6460 (clobber (reg:CC CC_REGNUM))]
6463 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6464 (clobber (reg:CC CC_REGNUM))])]
6465 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6468 ; xorhi3 instruction pattern(s).
6471 (define_insn "*xorhi3"
6472 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6473 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6474 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6475 (clobber (reg:CC CC_REGNUM))]
6476 "s390_logical_operator_ok_p (operands)"
6482 [(set_attr "op_type" "RIL,RR,SI,SS")
6483 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6486 [(set (match_operand:HI 0 "s_operand" "")
6487 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6488 (clobber (reg:CC CC_REGNUM))]
6491 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6492 (clobber (reg:CC CC_REGNUM))])]
6493 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6496 ; xorqi3 instruction pattern(s).
6499 (define_insn "*xorqi3"
6500 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6501 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6502 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6503 (clobber (reg:CC CC_REGNUM))]
6504 "s390_logical_operator_ok_p (operands)"
6511 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
6512 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6516 ; Block exclusive or (XC) patterns.
6520 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6521 (xor:BLK (match_dup 0)
6522 (match_operand:BLK 1 "memory_operand" "Q")))
6523 (use (match_operand 2 "const_int_operand" "n"))
6524 (clobber (reg:CC CC_REGNUM))]
6525 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6526 "xc\t%O0(%2,%R0),%S1"
6527 [(set_attr "op_type" "SS")])
6530 [(set (match_operand 0 "memory_operand" "")
6532 (match_operand 1 "memory_operand" "")))
6533 (clobber (reg:CC CC_REGNUM))]
6535 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6536 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6538 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6540 (clobber (reg:CC CC_REGNUM))])]
6542 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6543 operands[0] = adjust_address (operands[0], BLKmode, 0);
6544 operands[1] = adjust_address (operands[1], BLKmode, 0);
6549 [(set (match_operand:BLK 0 "memory_operand" "")
6550 (xor:BLK (match_dup 0)
6551 (match_operand:BLK 1 "memory_operand" "")))
6552 (use (match_operand 2 "const_int_operand" ""))
6553 (clobber (reg:CC CC_REGNUM))])
6555 [(set (match_operand:BLK 3 "memory_operand" "")
6556 (xor:BLK (match_dup 3)
6557 (match_operand:BLK 4 "memory_operand" "")))
6558 (use (match_operand 5 "const_int_operand" ""))
6559 (clobber (reg:CC CC_REGNUM))])]
6560 "s390_offset_p (operands[0], operands[3], operands[2])
6561 && s390_offset_p (operands[1], operands[4], operands[2])
6562 && !s390_overlap_p (operands[0], operands[1],
6563 INTVAL (operands[2]) + INTVAL (operands[5]))
6564 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6566 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6568 (clobber (reg:CC CC_REGNUM))])]
6569 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6570 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6571 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6574 ; Block xor (XC) patterns with src == dest.
6577 (define_insn "*xc_zero"
6578 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6580 (use (match_operand 1 "const_int_operand" "n"))
6581 (clobber (reg:CC CC_REGNUM))]
6582 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6583 "xc\t%O0(%1,%R0),%S0"
6584 [(set_attr "op_type" "SS")])
6588 [(set (match_operand:BLK 0 "memory_operand" "")
6590 (use (match_operand 1 "const_int_operand" ""))
6591 (clobber (reg:CC CC_REGNUM))])
6593 [(set (match_operand:BLK 2 "memory_operand" "")
6595 (use (match_operand 3 "const_int_operand" ""))
6596 (clobber (reg:CC CC_REGNUM))])]
6597 "s390_offset_p (operands[0], operands[2], operands[1])
6598 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6600 [(set (match_dup 4) (const_int 0))
6602 (clobber (reg:CC CC_REGNUM))])]
6603 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6604 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6608 ;;- Negate instructions.
6612 ; neg(di|si)2 instruction pattern(s).
6615 (define_expand "neg<mode>2"
6617 [(set (match_operand:DSI 0 "register_operand" "=d")
6618 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6619 (clobber (reg:CC CC_REGNUM))])]
6623 (define_insn "*negdi2_sign_cc"
6624 [(set (reg CC_REGNUM)
6625 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6626 (match_operand:SI 1 "register_operand" "d") 0)
6627 (const_int 32)) (const_int 32)))
6629 (set (match_operand:DI 0 "register_operand" "=d")
6630 (neg:DI (sign_extend:DI (match_dup 1))))]
6631 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6633 [(set_attr "op_type" "RRE")])
6635 (define_insn "*negdi2_sign"
6636 [(set (match_operand:DI 0 "register_operand" "=d")
6637 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6638 (clobber (reg:CC CC_REGNUM))]
6641 [(set_attr "op_type" "RRE")])
6644 (define_insn "*neg<mode>2_cc"
6645 [(set (reg CC_REGNUM)
6646 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6648 (set (match_operand:GPR 0 "register_operand" "=d")
6649 (neg:GPR (match_dup 1)))]
6650 "s390_match_ccmode (insn, CCAmode)"
6652 [(set_attr "op_type" "RR<E>")
6653 (set_attr "z10prop" "z10_super_c_E1")])
6656 (define_insn "*neg<mode>2_cconly"
6657 [(set (reg CC_REGNUM)
6658 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6660 (clobber (match_scratch:GPR 0 "=d"))]
6661 "s390_match_ccmode (insn, CCAmode)"
6663 [(set_attr "op_type" "RR<E>")
6664 (set_attr "z10prop" "z10_super_c_E1")])
6667 (define_insn "*neg<mode>2"
6668 [(set (match_operand:GPR 0 "register_operand" "=d")
6669 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6670 (clobber (reg:CC CC_REGNUM))]
6673 [(set_attr "op_type" "RR<E>")
6674 (set_attr "z10prop" "z10_super_c_E1")])
6676 (define_insn_and_split "*negdi2_31"
6677 [(set (match_operand:DI 0 "register_operand" "=d")
6678 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6679 (clobber (reg:CC CC_REGNUM))]
6682 "&& reload_completed"
6684 [(set (match_dup 2) (neg:SI (match_dup 3)))
6685 (clobber (reg:CC CC_REGNUM))])
6687 [(set (reg:CCAP CC_REGNUM)
6688 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6689 (set (match_dup 4) (neg:SI (match_dup 5)))])
6691 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6693 (label_ref (match_dup 6))))
6695 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6696 (clobber (reg:CC CC_REGNUM))])
6698 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6699 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6700 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6701 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6702 operands[6] = gen_label_rtx ();")
6705 ; neg(df|sf)2 instruction pattern(s).
6708 (define_expand "neg<mode>2"
6710 [(set (match_operand:BFP 0 "register_operand" "=f")
6711 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6712 (clobber (reg:CC CC_REGNUM))])]
6716 ; lcxbr, lcdbr, lcebr
6717 (define_insn "*neg<mode>2_cc"
6718 [(set (reg CC_REGNUM)
6719 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6720 (match_operand:BFP 2 "const0_operand" "")))
6721 (set (match_operand:BFP 0 "register_operand" "=f")
6722 (neg:BFP (match_dup 1)))]
6723 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6725 [(set_attr "op_type" "RRE")
6726 (set_attr "type" "fsimp<mode>")])
6728 ; lcxbr, lcdbr, lcebr
6729 (define_insn "*neg<mode>2_cconly"
6730 [(set (reg CC_REGNUM)
6731 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6732 (match_operand:BFP 2 "const0_operand" "")))
6733 (clobber (match_scratch:BFP 0 "=f"))]
6734 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6736 [(set_attr "op_type" "RRE")
6737 (set_attr "type" "fsimp<mode>")])
6740 (define_insn "*neg<mode>2_nocc"
6741 [(set (match_operand:FP 0 "register_operand" "=f")
6742 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6745 [(set_attr "op_type" "RRE")
6746 (set_attr "type" "fsimp<mode>")])
6748 ; lcxbr, lcdbr, lcebr
6749 (define_insn "*neg<mode>2"
6750 [(set (match_operand:BFP 0 "register_operand" "=f")
6751 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6752 (clobber (reg:CC CC_REGNUM))]
6755 [(set_attr "op_type" "RRE")
6756 (set_attr "type" "fsimp<mode>")])
6760 ;;- Absolute value instructions.
6764 ; abs(di|si)2 instruction pattern(s).
6767 (define_insn "*absdi2_sign_cc"
6768 [(set (reg CC_REGNUM)
6769 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6770 (match_operand:SI 1 "register_operand" "d") 0)
6771 (const_int 32)) (const_int 32)))
6773 (set (match_operand:DI 0 "register_operand" "=d")
6774 (abs:DI (sign_extend:DI (match_dup 1))))]
6775 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6777 [(set_attr "op_type" "RRE")])
6779 (define_insn "*absdi2_sign"
6780 [(set (match_operand:DI 0 "register_operand" "=d")
6781 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6782 (clobber (reg:CC CC_REGNUM))]
6785 [(set_attr "op_type" "RRE")])
6788 (define_insn "*abs<mode>2_cc"
6789 [(set (reg CC_REGNUM)
6790 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6792 (set (match_operand:GPR 0 "register_operand" "=d")
6793 (abs:GPR (match_dup 1)))]
6794 "s390_match_ccmode (insn, CCAmode)"
6796 [(set_attr "op_type" "RR<E>")
6797 (set_attr "z10prop" "z10_c")])
6800 (define_insn "*abs<mode>2_cconly"
6801 [(set (reg CC_REGNUM)
6802 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6804 (clobber (match_scratch:GPR 0 "=d"))]
6805 "s390_match_ccmode (insn, CCAmode)"
6807 [(set_attr "op_type" "RR<E>")
6808 (set_attr "z10prop" "z10_c")])
6811 (define_insn "abs<mode>2"
6812 [(set (match_operand:GPR 0 "register_operand" "=d")
6813 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6814 (clobber (reg:CC CC_REGNUM))]
6817 [(set_attr "op_type" "RR<E>")
6818 (set_attr "z10prop" "z10_c")])
6821 ; abs(df|sf)2 instruction pattern(s).
6824 (define_expand "abs<mode>2"
6826 [(set (match_operand:BFP 0 "register_operand" "=f")
6827 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6828 (clobber (reg:CC CC_REGNUM))])]
6832 ; lpxbr, lpdbr, lpebr
6833 (define_insn "*abs<mode>2_cc"
6834 [(set (reg CC_REGNUM)
6835 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6836 (match_operand:BFP 2 "const0_operand" "")))
6837 (set (match_operand:BFP 0 "register_operand" "=f")
6838 (abs:BFP (match_dup 1)))]
6839 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6841 [(set_attr "op_type" "RRE")
6842 (set_attr "type" "fsimp<mode>")])
6844 ; lpxbr, lpdbr, lpebr
6845 (define_insn "*abs<mode>2_cconly"
6846 [(set (reg CC_REGNUM)
6847 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6848 (match_operand:BFP 2 "const0_operand" "")))
6849 (clobber (match_scratch:BFP 0 "=f"))]
6850 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6852 [(set_attr "op_type" "RRE")
6853 (set_attr "type" "fsimp<mode>")])
6856 (define_insn "*abs<mode>2_nocc"
6857 [(set (match_operand:FP 0 "register_operand" "=f")
6858 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6861 [(set_attr "op_type" "RRE")
6862 (set_attr "type" "fsimp<mode>")])
6864 ; lpxbr, lpdbr, lpebr
6865 (define_insn "*abs<mode>2"
6866 [(set (match_operand:BFP 0 "register_operand" "=f")
6867 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6868 (clobber (reg:CC CC_REGNUM))]
6871 [(set_attr "op_type" "RRE")
6872 (set_attr "type" "fsimp<mode>")])
6876 ;;- Negated absolute value instructions
6883 (define_insn "*negabsdi2_sign_cc"
6884 [(set (reg CC_REGNUM)
6885 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6886 (match_operand:SI 1 "register_operand" "d") 0)
6887 (const_int 32)) (const_int 32))))
6889 (set (match_operand:DI 0 "register_operand" "=d")
6890 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6891 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6893 [(set_attr "op_type" "RRE")])
6895 (define_insn "*negabsdi2_sign"
6896 [(set (match_operand:DI 0 "register_operand" "=d")
6897 (neg:DI (abs:DI (sign_extend:DI
6898 (match_operand:SI 1 "register_operand" "d")))))
6899 (clobber (reg:CC CC_REGNUM))]
6902 [(set_attr "op_type" "RRE")])
6905 (define_insn "*negabs<mode>2_cc"
6906 [(set (reg CC_REGNUM)
6907 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6909 (set (match_operand:GPR 0 "register_operand" "=d")
6910 (neg:GPR (abs:GPR (match_dup 1))))]
6911 "s390_match_ccmode (insn, CCAmode)"
6913 [(set_attr "op_type" "RR<E>")
6914 (set_attr "z10prop" "z10_c")])
6917 (define_insn "*negabs<mode>2_cconly"
6918 [(set (reg CC_REGNUM)
6919 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6921 (clobber (match_scratch:GPR 0 "=d"))]
6922 "s390_match_ccmode (insn, CCAmode)"
6924 [(set_attr "op_type" "RR<E>")
6925 (set_attr "z10prop" "z10_c")])
6928 (define_insn "*negabs<mode>2"
6929 [(set (match_operand:GPR 0 "register_operand" "=d")
6930 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6931 (clobber (reg:CC CC_REGNUM))]
6934 [(set_attr "op_type" "RR<E>")
6935 (set_attr "z10prop" "z10_c")])
6941 ; lnxbr, lndbr, lnebr
6942 (define_insn "*negabs<mode>2_cc"
6943 [(set (reg CC_REGNUM)
6944 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6945 (match_operand:BFP 2 "const0_operand" "")))
6946 (set (match_operand:BFP 0 "register_operand" "=f")
6947 (neg:BFP (abs:BFP (match_dup 1))))]
6948 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6950 [(set_attr "op_type" "RRE")
6951 (set_attr "type" "fsimp<mode>")])
6953 ; lnxbr, lndbr, lnebr
6954 (define_insn "*negabs<mode>2_cconly"
6955 [(set (reg CC_REGNUM)
6956 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6957 (match_operand:BFP 2 "const0_operand" "")))
6958 (clobber (match_scratch:BFP 0 "=f"))]
6959 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6961 [(set_attr "op_type" "RRE")
6962 (set_attr "type" "fsimp<mode>")])
6965 (define_insn "*negabs<mode>2_nocc"
6966 [(set (match_operand:FP 0 "register_operand" "=f")
6967 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
6970 [(set_attr "op_type" "RRE")
6971 (set_attr "type" "fsimp<mode>")])
6973 ; lnxbr, lndbr, lnebr
6974 (define_insn "*negabs<mode>2"
6975 [(set (match_operand:BFP 0 "register_operand" "=f")
6976 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
6977 (clobber (reg:CC CC_REGNUM))]
6980 [(set_attr "op_type" "RRE")
6981 (set_attr "type" "fsimp<mode>")])
6984 ;;- Copy sign instructions
6988 (define_insn "copysign<mode>3"
6989 [(set (match_operand:FP 0 "register_operand" "=f")
6990 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
6991 (match_operand:FP 2 "register_operand" "f")]
6995 [(set_attr "op_type" "RRF")
6996 (set_attr "type" "fsimp<mode>")])
6999 ;;- Square root instructions.
7003 ; sqrt(df|sf)2 instruction pattern(s).
7006 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7007 (define_insn "sqrt<mode>2"
7008 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7009 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7014 [(set_attr "op_type" "RRE,RXE")
7015 (set_attr "type" "fsqrt<mode>")])
7019 ;;- One complement instructions.
7023 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7026 (define_expand "one_cmpl<mode>2"
7028 [(set (match_operand:INT 0 "register_operand" "")
7029 (xor:INT (match_operand:INT 1 "register_operand" "")
7031 (clobber (reg:CC CC_REGNUM))])]
7037 ;; Find leftmost bit instructions.
7040 (define_expand "clzdi2"
7041 [(set (match_operand:DI 0 "register_operand" "=d")
7042 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7043 "TARGET_EXTIMM && TARGET_64BIT"
7045 rtx insn, clz_equal;
7046 rtx wide_reg = gen_reg_rtx (TImode);
7047 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7049 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7051 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7053 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7054 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7059 (define_insn "clztidi2"
7060 [(set (match_operand:TI 0 "register_operand" "=d")
7064 (xor:DI (match_operand:DI 1 "register_operand" "d")
7065 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7066 (subreg:SI (clz:DI (match_dup 1)) 4))))
7069 (zero_extend:TI (clz:DI (match_dup 1)))))
7070 (clobber (reg:CC CC_REGNUM))]
7071 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7072 == (unsigned HOST_WIDE_INT) 1 << 63
7073 && TARGET_EXTIMM && TARGET_64BIT"
7075 [(set_attr "op_type" "RRE")])
7079 ;;- Rotate instructions.
7083 ; rotl(di|si)3 instruction pattern(s).
7087 (define_insn "rotl<mode>3"
7088 [(set (match_operand:GPR 0 "register_operand" "=d")
7089 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7090 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7093 [(set_attr "op_type" "RSE")
7094 (set_attr "atype" "reg")
7095 (set_attr "z10prop" "z10_super_E1")])
7098 (define_insn "*rotl<mode>3_and"
7099 [(set (match_operand:GPR 0 "register_operand" "=d")
7100 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7101 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7102 (match_operand:SI 3 "const_int_operand" "n"))))]
7103 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7105 [(set_attr "op_type" "RSE")
7106 (set_attr "atype" "reg")
7107 (set_attr "z10prop" "z10_super_E1")])
7111 ;;- Shift instructions.
7115 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7118 (define_expand "<shift><mode>3"
7119 [(set (match_operand:DSI 0 "register_operand" "")
7120 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7121 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7126 (define_insn "*<shift>di3_31"
7127 [(set (match_operand:DI 0 "register_operand" "=d")
7128 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7129 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7132 [(set_attr "op_type" "RS")
7133 (set_attr "atype" "reg")])
7135 ; sll, srl, sllg, srlg
7136 (define_insn "*<shift><mode>3"
7137 [(set (match_operand:GPR 0 "register_operand" "=d")
7138 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7139 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7141 "s<lr>l<g>\t%0,<1>%Y2"
7142 [(set_attr "op_type" "RS<E>")
7143 (set_attr "atype" "reg")
7144 (set_attr "z10prop" "z10_super_E1")])
7147 (define_insn "*<shift>di3_31_and"
7148 [(set (match_operand:DI 0 "register_operand" "=d")
7149 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7150 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7151 (match_operand:SI 3 "const_int_operand" "n"))))]
7152 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7154 [(set_attr "op_type" "RS")
7155 (set_attr "atype" "reg")])
7157 ; sll, srl, sllg, srlg
7158 (define_insn "*<shift><mode>3_and"
7159 [(set (match_operand:GPR 0 "register_operand" "=d")
7160 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7161 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7162 (match_operand:SI 3 "const_int_operand" "n"))))]
7163 "(INTVAL (operands[3]) & 63) == 63"
7164 "s<lr>l<g>\t%0,<1>%Y2"
7165 [(set_attr "op_type" "RS<E>")
7166 (set_attr "atype" "reg")
7167 (set_attr "z10prop" "z10_super_E1")])
7170 ; ashr(di|si)3 instruction pattern(s).
7173 (define_expand "ashr<mode>3"
7175 [(set (match_operand:DSI 0 "register_operand" "")
7176 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7177 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7178 (clobber (reg:CC CC_REGNUM))])]
7182 (define_insn "*ashrdi3_cc_31"
7183 [(set (reg CC_REGNUM)
7184 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7185 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7187 (set (match_operand:DI 0 "register_operand" "=d")
7188 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7189 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7191 [(set_attr "op_type" "RS")
7192 (set_attr "atype" "reg")])
7194 (define_insn "*ashrdi3_cconly_31"
7195 [(set (reg CC_REGNUM)
7196 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7197 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7199 (clobber (match_scratch:DI 0 "=d"))]
7200 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7202 [(set_attr "op_type" "RS")
7203 (set_attr "atype" "reg")])
7205 (define_insn "*ashrdi3_31"
7206 [(set (match_operand:DI 0 "register_operand" "=d")
7207 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7208 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7209 (clobber (reg:CC CC_REGNUM))]
7212 [(set_attr "op_type" "RS")
7213 (set_attr "atype" "reg")])
7216 (define_insn "*ashr<mode>3_cc"
7217 [(set (reg CC_REGNUM)
7218 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7219 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7221 (set (match_operand:GPR 0 "register_operand" "=d")
7222 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7223 "s390_match_ccmode(insn, CCSmode)"
7225 [(set_attr "op_type" "RS<E>")
7226 (set_attr "atype" "reg")
7227 (set_attr "z10prop" "z10_super_E1")])
7230 (define_insn "*ashr<mode>3_cconly"
7231 [(set (reg CC_REGNUM)
7232 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7233 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7235 (clobber (match_scratch:GPR 0 "=d"))]
7236 "s390_match_ccmode(insn, CCSmode)"
7238 [(set_attr "op_type" "RS<E>")
7239 (set_attr "atype" "reg")
7240 (set_attr "z10prop" "z10_super_E1")])
7243 (define_insn "*ashr<mode>3"
7244 [(set (match_operand:GPR 0 "register_operand" "=d")
7245 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7246 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7247 (clobber (reg:CC CC_REGNUM))]
7250 [(set_attr "op_type" "RS<E>")
7251 (set_attr "atype" "reg")
7252 (set_attr "z10prop" "z10_super_E1")])
7255 ; shift pattern with implicit ANDs
7257 (define_insn "*ashrdi3_cc_31_and"
7258 [(set (reg CC_REGNUM)
7259 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7260 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7261 (match_operand:SI 3 "const_int_operand" "n")))
7263 (set (match_operand:DI 0 "register_operand" "=d")
7264 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7265 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7266 && (INTVAL (operands[3]) & 63) == 63"
7268 [(set_attr "op_type" "RS")
7269 (set_attr "atype" "reg")])
7271 (define_insn "*ashrdi3_cconly_31_and"
7272 [(set (reg CC_REGNUM)
7273 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7274 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7275 (match_operand:SI 3 "const_int_operand" "n")))
7277 (clobber (match_scratch:DI 0 "=d"))]
7278 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7279 && (INTVAL (operands[3]) & 63) == 63"
7281 [(set_attr "op_type" "RS")
7282 (set_attr "atype" "reg")])
7284 (define_insn "*ashrdi3_31_and"
7285 [(set (match_operand:DI 0 "register_operand" "=d")
7286 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7287 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7288 (match_operand:SI 3 "const_int_operand" "n"))))
7289 (clobber (reg:CC CC_REGNUM))]
7290 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7292 [(set_attr "op_type" "RS")
7293 (set_attr "atype" "reg")])
7296 (define_insn "*ashr<mode>3_cc_and"
7297 [(set (reg CC_REGNUM)
7298 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7299 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7300 (match_operand:SI 3 "const_int_operand" "n")))
7302 (set (match_operand:GPR 0 "register_operand" "=d")
7303 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7304 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7306 [(set_attr "op_type" "RS<E>")
7307 (set_attr "atype" "reg")
7308 (set_attr "z10prop" "z10_super_E1")])
7311 (define_insn "*ashr<mode>3_cconly_and"
7312 [(set (reg CC_REGNUM)
7313 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7314 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7315 (match_operand:SI 3 "const_int_operand" "n")))
7317 (clobber (match_scratch:GPR 0 "=d"))]
7318 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7320 [(set_attr "op_type" "RS<E>")
7321 (set_attr "atype" "reg")
7322 (set_attr "z10prop" "z10_super_E1")])
7325 (define_insn "*ashr<mode>3_and"
7326 [(set (match_operand:GPR 0 "register_operand" "=d")
7327 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7328 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7329 (match_operand:SI 3 "const_int_operand" "n"))))
7330 (clobber (reg:CC CC_REGNUM))]
7331 "(INTVAL (operands[3]) & 63) == 63"
7333 [(set_attr "op_type" "RS<E>")
7334 (set_attr "atype" "reg")
7335 (set_attr "z10prop" "z10_super_E1")])
7339 ;; Branch instruction patterns.
7342 (define_expand "b<code>"
7344 (if_then_else (COMPARE (match_operand 0 "" "")
7349 "s390_emit_jump (operands[0],
7350 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
7354 ;;- Conditional jump instructions.
7357 (define_insn "*cjump_64"
7360 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7361 (label_ref (match_operand 0 "" ""))
7365 if (get_attr_length (insn) == 4)
7368 return "jg%C1\t%l0";
7370 [(set_attr "op_type" "RI")
7371 (set_attr "type" "branch")
7372 (set (attr "length")
7373 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7374 (const_int 4) (const_int 6)))])
7376 (define_insn "*cjump_31"
7379 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7380 (label_ref (match_operand 0 "" ""))
7384 gcc_assert (get_attr_length (insn) == 4);
7387 [(set_attr "op_type" "RI")
7388 (set_attr "type" "branch")
7389 (set (attr "length")
7390 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7391 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7392 (const_int 4) (const_int 6))
7393 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7394 (const_int 4) (const_int 8))))])
7396 (define_insn "*cjump_long"
7399 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7400 (match_operand 0 "address_operand" "U")
7404 if (get_attr_op_type (insn) == OP_TYPE_RR)
7409 [(set (attr "op_type")
7410 (if_then_else (match_operand 0 "register_operand" "")
7411 (const_string "RR") (const_string "RX")))
7412 (set_attr "type" "branch")
7413 (set_attr "atype" "agen")])
7417 ;;- Negated conditional jump instructions.
7420 (define_insn "*icjump_64"
7423 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7425 (label_ref (match_operand 0 "" ""))))]
7428 if (get_attr_length (insn) == 4)
7431 return "jg%D1\t%l0";
7433 [(set_attr "op_type" "RI")
7434 (set_attr "type" "branch")
7435 (set (attr "length")
7436 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7437 (const_int 4) (const_int 6)))])
7439 (define_insn "*icjump_31"
7442 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7444 (label_ref (match_operand 0 "" ""))))]
7447 gcc_assert (get_attr_length (insn) == 4);
7450 [(set_attr "op_type" "RI")
7451 (set_attr "type" "branch")
7452 (set (attr "length")
7453 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7454 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7455 (const_int 4) (const_int 6))
7456 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7457 (const_int 4) (const_int 8))))])
7459 (define_insn "*icjump_long"
7462 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7464 (match_operand 0 "address_operand" "U")))]
7467 if (get_attr_op_type (insn) == OP_TYPE_RR)
7472 [(set (attr "op_type")
7473 (if_then_else (match_operand 0 "register_operand" "")
7474 (const_string "RR") (const_string "RX")))
7475 (set_attr "type" "branch")
7476 (set_attr "atype" "agen")])
7479 ;;- Trap instructions.
7483 [(trap_if (const_int 1) (const_int 0))]
7486 [(set_attr "op_type" "RI")
7487 (set_attr "type" "branch")])
7489 (define_expand "conditional_trap"
7490 [(trap_if (match_operand 0 "comparison_operator" "")
7491 (match_operand 1 "general_operand" ""))]
7494 if (operands[1] != const0_rtx) FAIL;
7495 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
7496 s390_compare_op0, s390_compare_op1);
7499 (define_insn "*trap"
7500 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7504 [(set_attr "op_type" "RI")
7505 (set_attr "type" "branch")])
7507 ; crt, cgrt, cit, cgit
7508 (define_insn "*cmp_and_trap_signed_int<mode>"
7509 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7510 [(match_operand:GPR 1 "register_operand" "d,d")
7511 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7517 [(set_attr "op_type" "RRF,RIE")
7518 (set_attr "type" "branch")
7519 (set_attr "z10prop" "z10_c,*")])
7521 ; clrt, clgrt, clfit, clgit
7522 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7523 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7524 [(match_operand:GPR 1 "register_operand" "d,d")
7525 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7530 cl<gf>it%C0\t%1,%x2"
7531 [(set_attr "op_type" "RRF,RIE")
7532 (set_attr "type" "branch")
7533 (set_attr "z10prop" "z10_c,*")])
7536 ;;- Loop instructions.
7538 ;; This is all complicated by the fact that since this is a jump insn
7539 ;; we must handle our own output reloads.
7541 (define_expand "doloop_end"
7542 [(use (match_operand 0 "" "")) ; loop pseudo
7543 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7544 (use (match_operand 2 "" "")) ; max iterations
7545 (use (match_operand 3 "" "")) ; loop level
7546 (use (match_operand 4 "" ""))] ; label
7549 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7550 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7551 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7552 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7553 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7554 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7561 (define_insn_and_split "doloop_si64"
7564 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7566 (label_ref (match_operand 0 "" ""))
7568 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7569 (plus:SI (match_dup 1) (const_int -1)))
7570 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7571 (clobber (reg:CC CC_REGNUM))]
7574 if (which_alternative != 0)
7576 else if (get_attr_length (insn) == 4)
7577 return "brct\t%1,%l0";
7579 return "ahi\t%1,-1\;jgne\t%l0";
7581 "&& reload_completed
7582 && (! REG_P (operands[2])
7583 || ! rtx_equal_p (operands[1], operands[2]))"
7584 [(set (match_dup 3) (match_dup 1))
7585 (parallel [(set (reg:CCAN CC_REGNUM)
7586 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7588 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7589 (set (match_dup 2) (match_dup 3))
7590 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7591 (label_ref (match_dup 0))
7594 [(set_attr "op_type" "RI")
7595 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7596 ; hurt us in the (rare) case of ahi.
7597 (set_attr "z10prop" "z10_super")
7598 (set_attr "type" "branch")
7599 (set (attr "length")
7600 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7601 (const_int 4) (const_int 10)))])
7603 (define_insn_and_split "doloop_si31"
7606 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7608 (label_ref (match_operand 0 "" ""))
7610 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7611 (plus:SI (match_dup 1) (const_int -1)))
7612 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7613 (clobber (reg:CC CC_REGNUM))]
7616 if (which_alternative != 0)
7618 else if (get_attr_length (insn) == 4)
7619 return "brct\t%1,%l0";
7623 "&& reload_completed
7624 && (! REG_P (operands[2])
7625 || ! rtx_equal_p (operands[1], operands[2]))"
7626 [(set (match_dup 3) (match_dup 1))
7627 (parallel [(set (reg:CCAN CC_REGNUM)
7628 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7630 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7631 (set (match_dup 2) (match_dup 3))
7632 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7633 (label_ref (match_dup 0))
7636 [(set_attr "op_type" "RI")
7637 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7638 ; hurt us in the (rare) case of ahi.
7639 (set_attr "z10prop" "z10_super")
7640 (set_attr "type" "branch")
7641 (set (attr "length")
7642 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7643 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7644 (const_int 4) (const_int 6))
7645 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7646 (const_int 4) (const_int 8))))])
7648 (define_insn "*doloop_si_long"
7651 (ne (match_operand:SI 1 "register_operand" "d")
7653 (match_operand 0 "address_operand" "U")
7655 (set (match_operand:SI 2 "register_operand" "=1")
7656 (plus:SI (match_dup 1) (const_int -1)))
7657 (clobber (match_scratch:SI 3 "=X"))
7658 (clobber (reg:CC CC_REGNUM))]
7661 if (get_attr_op_type (insn) == OP_TYPE_RR)
7662 return "bctr\t%1,%0";
7664 return "bct\t%1,%a0";
7666 [(set (attr "op_type")
7667 (if_then_else (match_operand 0 "register_operand" "")
7668 (const_string "RR") (const_string "RX")))
7669 (set_attr "type" "branch")
7670 (set_attr "atype" "agen")])
7672 (define_insn_and_split "doloop_di"
7675 (ne (match_operand:DI 1 "register_operand" "d,d,d")
7677 (label_ref (match_operand 0 "" ""))
7679 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7680 (plus:DI (match_dup 1) (const_int -1)))
7681 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7682 (clobber (reg:CC CC_REGNUM))]
7685 if (which_alternative != 0)
7687 else if (get_attr_length (insn) == 4)
7688 return "brctg\t%1,%l0";
7690 return "aghi\t%1,-1\;jgne\t%l0";
7692 "&& reload_completed
7693 && (! REG_P (operands[2])
7694 || ! rtx_equal_p (operands[1], operands[2]))"
7695 [(set (match_dup 3) (match_dup 1))
7696 (parallel [(set (reg:CCAN CC_REGNUM)
7697 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7699 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7700 (set (match_dup 2) (match_dup 3))
7701 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7702 (label_ref (match_dup 0))
7705 [(set_attr "op_type" "RI")
7706 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7707 ; hurt us in the (rare) case of ahi.
7708 (set_attr "z10prop" "z10_super")
7709 (set_attr "type" "branch")
7710 (set (attr "length")
7711 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7712 (const_int 4) (const_int 10)))])
7715 ;;- Unconditional jump instructions.
7719 ; jump instruction pattern(s).
7722 (define_expand "jump"
7723 [(match_operand 0 "" "")]
7725 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7727 (define_insn "*jump64"
7728 [(set (pc) (label_ref (match_operand 0 "" "")))]
7731 if (get_attr_length (insn) == 4)
7736 [(set_attr "op_type" "RI")
7737 (set_attr "type" "branch")
7738 (set (attr "length")
7739 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7740 (const_int 4) (const_int 6)))])
7742 (define_insn "*jump31"
7743 [(set (pc) (label_ref (match_operand 0 "" "")))]
7746 gcc_assert (get_attr_length (insn) == 4);
7749 [(set_attr "op_type" "RI")
7750 (set_attr "type" "branch")
7751 (set (attr "length")
7752 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7753 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7754 (const_int 4) (const_int 6))
7755 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7756 (const_int 4) (const_int 8))))])
7759 ; indirect-jump instruction pattern(s).
7762 (define_insn "indirect_jump"
7763 [(set (pc) (match_operand 0 "address_operand" "U"))]
7766 if (get_attr_op_type (insn) == OP_TYPE_RR)
7771 [(set (attr "op_type")
7772 (if_then_else (match_operand 0 "register_operand" "")
7773 (const_string "RR") (const_string "RX")))
7774 (set_attr "type" "branch")
7775 (set_attr "atype" "agen")
7776 (set_attr "z10prop" "z10_super")])
7779 ; casesi instruction pattern(s).
7782 (define_insn "casesi_jump"
7783 [(set (pc) (match_operand 0 "address_operand" "U"))
7784 (use (label_ref (match_operand 1 "" "")))]
7787 if (get_attr_op_type (insn) == OP_TYPE_RR)
7792 [(set (attr "op_type")
7793 (if_then_else (match_operand 0 "register_operand" "")
7794 (const_string "RR") (const_string "RX")))
7795 (set_attr "type" "branch")
7796 (set_attr "atype" "agen")])
7798 (define_expand "casesi"
7799 [(match_operand:SI 0 "general_operand" "")
7800 (match_operand:SI 1 "general_operand" "")
7801 (match_operand:SI 2 "general_operand" "")
7802 (label_ref (match_operand 3 "" ""))
7803 (label_ref (match_operand 4 "" ""))]
7806 rtx index = gen_reg_rtx (SImode);
7807 rtx base = gen_reg_rtx (Pmode);
7808 rtx target = gen_reg_rtx (Pmode);
7810 emit_move_insn (index, operands[0]);
7811 emit_insn (gen_subsi3 (index, index, operands[1]));
7812 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7815 if (Pmode != SImode)
7816 index = convert_to_mode (Pmode, index, 1);
7817 if (GET_CODE (index) != REG)
7818 index = copy_to_mode_reg (Pmode, index);
7821 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7823 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7825 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7827 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7828 emit_move_insn (target, index);
7831 target = gen_rtx_PLUS (Pmode, base, target);
7832 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7839 ;;- Jump to subroutine.
7844 ; untyped call instruction pattern(s).
7847 ;; Call subroutine returning any type.
7848 (define_expand "untyped_call"
7849 [(parallel [(call (match_operand 0 "" "")
7851 (match_operand 1 "" "")
7852 (match_operand 2 "" "")])]
7857 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7859 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7861 rtx set = XVECEXP (operands[2], 0, i);
7862 emit_move_insn (SET_DEST (set), SET_SRC (set));
7865 /* The optimizer does not know that the call sets the function value
7866 registers we stored in the result block. We avoid problems by
7867 claiming that all hard registers are used and clobbered at this
7869 emit_insn (gen_blockage ());
7874 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7875 ;; all of memory. This blocks insns from being moved across this point.
7877 (define_insn "blockage"
7878 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7881 [(set_attr "type" "none")
7882 (set_attr "length" "0")])
7888 (define_expand "sibcall"
7889 [(call (match_operand 0 "" "")
7890 (match_operand 1 "" ""))]
7893 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7897 (define_insn "*sibcall_br"
7898 [(call (mem:QI (reg SIBCALL_REGNUM))
7899 (match_operand 0 "const_int_operand" "n"))]
7900 "SIBLING_CALL_P (insn)
7901 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7903 [(set_attr "op_type" "RR")
7904 (set_attr "type" "branch")
7905 (set_attr "atype" "agen")])
7907 (define_insn "*sibcall_brc"
7908 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7909 (match_operand 1 "const_int_operand" "n"))]
7910 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7912 [(set_attr "op_type" "RI")
7913 (set_attr "type" "branch")])
7915 (define_insn "*sibcall_brcl"
7916 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7917 (match_operand 1 "const_int_operand" "n"))]
7918 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7920 [(set_attr "op_type" "RIL")
7921 (set_attr "type" "branch")])
7924 ; sibcall_value patterns
7927 (define_expand "sibcall_value"
7928 [(set (match_operand 0 "" "")
7929 (call (match_operand 1 "" "")
7930 (match_operand 2 "" "")))]
7933 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7937 (define_insn "*sibcall_value_br"
7938 [(set (match_operand 0 "" "")
7939 (call (mem:QI (reg SIBCALL_REGNUM))
7940 (match_operand 1 "const_int_operand" "n")))]
7941 "SIBLING_CALL_P (insn)
7942 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7944 [(set_attr "op_type" "RR")
7945 (set_attr "type" "branch")
7946 (set_attr "atype" "agen")])
7948 (define_insn "*sibcall_value_brc"
7949 [(set (match_operand 0 "" "")
7950 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7951 (match_operand 2 "const_int_operand" "n")))]
7952 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7954 [(set_attr "op_type" "RI")
7955 (set_attr "type" "branch")])
7957 (define_insn "*sibcall_value_brcl"
7958 [(set (match_operand 0 "" "")
7959 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7960 (match_operand 2 "const_int_operand" "n")))]
7961 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7963 [(set_attr "op_type" "RIL")
7964 (set_attr "type" "branch")])
7968 ; call instruction pattern(s).
7971 (define_expand "call"
7972 [(call (match_operand 0 "" "")
7973 (match_operand 1 "" ""))
7974 (use (match_operand 2 "" ""))]
7977 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7978 gen_rtx_REG (Pmode, RETURN_REGNUM));
7982 (define_insn "*bras"
7983 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7984 (match_operand 1 "const_int_operand" "n"))
7985 (clobber (match_operand 2 "register_operand" "=r"))]
7986 "!SIBLING_CALL_P (insn)
7987 && TARGET_SMALL_EXEC
7988 && GET_MODE (operands[2]) == Pmode"
7990 [(set_attr "op_type" "RI")
7991 (set_attr "type" "jsr")])
7993 (define_insn "*brasl"
7994 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7995 (match_operand 1 "const_int_operand" "n"))
7996 (clobber (match_operand 2 "register_operand" "=r"))]
7997 "!SIBLING_CALL_P (insn)
7999 && GET_MODE (operands[2]) == Pmode"
8001 [(set_attr "op_type" "RIL")
8002 (set_attr "type" "jsr")])
8004 (define_insn "*basr"
8005 [(call (mem:QI (match_operand 0 "address_operand" "U"))
8006 (match_operand 1 "const_int_operand" "n"))
8007 (clobber (match_operand 2 "register_operand" "=r"))]
8008 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8010 if (get_attr_op_type (insn) == OP_TYPE_RR)
8011 return "basr\t%2,%0";
8013 return "bas\t%2,%a0";
8015 [(set (attr "op_type")
8016 (if_then_else (match_operand 0 "register_operand" "")
8017 (const_string "RR") (const_string "RX")))
8018 (set_attr "type" "jsr")
8019 (set_attr "atype" "agen")])
8022 ; call_value instruction pattern(s).
8025 (define_expand "call_value"
8026 [(set (match_operand 0 "" "")
8027 (call (match_operand 1 "" "")
8028 (match_operand 2 "" "")))
8029 (use (match_operand 3 "" ""))]
8032 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8033 gen_rtx_REG (Pmode, RETURN_REGNUM));
8037 (define_insn "*bras_r"
8038 [(set (match_operand 0 "" "")
8039 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8040 (match_operand:SI 2 "const_int_operand" "n")))
8041 (clobber (match_operand 3 "register_operand" "=r"))]
8042 "!SIBLING_CALL_P (insn)
8043 && TARGET_SMALL_EXEC
8044 && GET_MODE (operands[3]) == Pmode"
8046 [(set_attr "op_type" "RI")
8047 (set_attr "type" "jsr")])
8049 (define_insn "*brasl_r"
8050 [(set (match_operand 0 "" "")
8051 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8052 (match_operand 2 "const_int_operand" "n")))
8053 (clobber (match_operand 3 "register_operand" "=r"))]
8054 "!SIBLING_CALL_P (insn)
8056 && GET_MODE (operands[3]) == Pmode"
8058 [(set_attr "op_type" "RIL")
8059 (set_attr "type" "jsr")])
8061 (define_insn "*basr_r"
8062 [(set (match_operand 0 "" "")
8063 (call (mem:QI (match_operand 1 "address_operand" "U"))
8064 (match_operand 2 "const_int_operand" "n")))
8065 (clobber (match_operand 3 "register_operand" "=r"))]
8066 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8068 if (get_attr_op_type (insn) == OP_TYPE_RR)
8069 return "basr\t%3,%1";
8071 return "bas\t%3,%a1";
8073 [(set (attr "op_type")
8074 (if_then_else (match_operand 1 "register_operand" "")
8075 (const_string "RR") (const_string "RX")))
8076 (set_attr "type" "jsr")
8077 (set_attr "atype" "agen")])
8080 ;;- Thread-local storage support.
8083 (define_expand "get_tp_64"
8084 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8088 (define_expand "get_tp_31"
8089 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8093 (define_expand "set_tp_64"
8094 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8095 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8099 (define_expand "set_tp_31"
8100 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8101 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8105 (define_insn "*set_tp"
8106 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8109 [(set_attr "type" "none")
8110 (set_attr "length" "0")])
8112 (define_insn "*tls_load_64"
8113 [(set (match_operand:DI 0 "register_operand" "=d")
8114 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8115 (match_operand:DI 2 "" "")]
8119 [(set_attr "op_type" "RXE")
8120 (set_attr "z10prop" "z10_fwd_A3")])
8122 (define_insn "*tls_load_31"
8123 [(set (match_operand:SI 0 "register_operand" "=d,d")
8124 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8125 (match_operand:SI 2 "" "")]
8131 [(set_attr "op_type" "RX,RXY")
8132 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8134 (define_insn "*bras_tls"
8135 [(set (match_operand 0 "" "")
8136 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8137 (match_operand 2 "const_int_operand" "n")))
8138 (clobber (match_operand 3 "register_operand" "=r"))
8139 (use (match_operand 4 "" ""))]
8140 "!SIBLING_CALL_P (insn)
8141 && TARGET_SMALL_EXEC
8142 && GET_MODE (operands[3]) == Pmode"
8144 [(set_attr "op_type" "RI")
8145 (set_attr "type" "jsr")])
8147 (define_insn "*brasl_tls"
8148 [(set (match_operand 0 "" "")
8149 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8150 (match_operand 2 "const_int_operand" "n")))
8151 (clobber (match_operand 3 "register_operand" "=r"))
8152 (use (match_operand 4 "" ""))]
8153 "!SIBLING_CALL_P (insn)
8155 && GET_MODE (operands[3]) == Pmode"
8157 [(set_attr "op_type" "RIL")
8158 (set_attr "type" "jsr")])
8160 (define_insn "*basr_tls"
8161 [(set (match_operand 0 "" "")
8162 (call (mem:QI (match_operand 1 "address_operand" "U"))
8163 (match_operand 2 "const_int_operand" "n")))
8164 (clobber (match_operand 3 "register_operand" "=r"))
8165 (use (match_operand 4 "" ""))]
8166 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8168 if (get_attr_op_type (insn) == OP_TYPE_RR)
8169 return "basr\t%3,%1%J4";
8171 return "bas\t%3,%a1%J4";
8173 [(set (attr "op_type")
8174 (if_then_else (match_operand 1 "register_operand" "")
8175 (const_string "RR") (const_string "RX")))
8176 (set_attr "type" "jsr")
8177 (set_attr "atype" "agen")])
8180 ;;- Atomic operations
8184 ; memory barrier pattern.
8187 (define_expand "memory_barrier"
8189 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8192 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8193 MEM_VOLATILE_P (operands[0]) = 1;
8196 (define_insn "*memory_barrier"
8197 [(set (match_operand:BLK 0 "" "")
8198 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8201 [(set_attr "op_type" "RR")])
8203 ; Although bcr is superscalar on Z10, this variant will never become part of
8204 ; an execution group.
8207 ; compare and swap patterns.
8210 (define_expand "sync_compare_and_swap<mode>"
8212 [(set (match_operand:TDSI 0 "register_operand" "")
8213 (match_operand:TDSI 1 "memory_operand" ""))
8215 (unspec_volatile:TDSI
8217 (match_operand:TDSI 2 "register_operand" "")
8218 (match_operand:TDSI 3 "register_operand" "")]
8220 (set (reg:CCZ1 CC_REGNUM)
8221 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8224 (define_expand "sync_compare_and_swap<mode>"
8226 [(set (match_operand:HQI 0 "register_operand" "")
8227 (match_operand:HQI 1 "memory_operand" ""))
8229 (unspec_volatile:HQI
8231 (match_operand:HQI 2 "general_operand" "")
8232 (match_operand:HQI 3 "general_operand" "")]
8234 (set (reg:CCZ1 CC_REGNUM)
8235 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8237 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8238 operands[2], operands[3]); DONE;")
8240 (define_expand "sync_compare_and_swap_cc<mode>"
8242 [(set (match_operand:TDSI 0 "register_operand" "")
8243 (match_operand:TDSI 1 "memory_operand" ""))
8245 (unspec_volatile:TDSI
8247 (match_operand:TDSI 2 "register_operand" "")
8248 (match_operand:TDSI 3 "register_operand" "")]
8251 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8254 /* Emulate compare. */
8255 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
8256 s390_compare_op0 = operands[1];
8257 s390_compare_op1 = operands[2];
8258 s390_compare_emitted = operands[4];
8262 (define_insn "*sync_compare_and_swap<mode>"
8263 [(set (match_operand:DP 0 "register_operand" "=r")
8264 (match_operand:DP 1 "memory_operand" "+Q"))
8268 (match_operand:DP 2 "register_operand" "0")
8269 (match_operand:DP 3 "register_operand" "r")]
8271 (set (reg:CCZ1 CC_REGNUM)
8272 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8274 "cds<tg>\t%0,%3,%S1"
8275 [(set_attr "op_type" "RS<TE>")
8276 (set_attr "type" "sem")])
8279 (define_insn "*sync_compare_and_swap<mode>"
8280 [(set (match_operand:GPR 0 "register_operand" "=r")
8281 (match_operand:GPR 1 "memory_operand" "+Q"))
8283 (unspec_volatile:GPR
8285 (match_operand:GPR 2 "register_operand" "0")
8286 (match_operand:GPR 3 "register_operand" "r")]
8288 (set (reg:CCZ1 CC_REGNUM)
8289 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8292 [(set_attr "op_type" "RS<E>")
8293 (set_attr "type" "sem")])
8297 ; Other atomic instruction patterns.
8300 (define_expand "sync_lock_test_and_set<mode>"
8301 [(match_operand:HQI 0 "register_operand")
8302 (match_operand:HQI 1 "memory_operand")
8303 (match_operand:HQI 2 "general_operand")]
8305 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8306 operands[2], false); DONE;")
8308 (define_expand "sync_<atomic><mode>"
8309 [(set (match_operand:HQI 0 "memory_operand")
8310 (ATOMIC:HQI (match_dup 0)
8311 (match_operand:HQI 1 "general_operand")))]
8313 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8314 operands[1], false); DONE;")
8316 (define_expand "sync_old_<atomic><mode>"
8317 [(set (match_operand:HQI 0 "register_operand")
8318 (match_operand:HQI 1 "memory_operand"))
8320 (ATOMIC:HQI (match_dup 1)
8321 (match_operand:HQI 2 "general_operand")))]
8323 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8324 operands[2], false); DONE;")
8326 (define_expand "sync_new_<atomic><mode>"
8327 [(set (match_operand:HQI 0 "register_operand")
8328 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8329 (match_operand:HQI 2 "general_operand")))
8330 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8332 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8333 operands[2], true); DONE;")
8336 ;;- Miscellaneous instructions.
8340 ; allocate stack instruction pattern(s).
8343 (define_expand "allocate_stack"
8344 [(match_operand 0 "general_operand" "")
8345 (match_operand 1 "general_operand" "")]
8348 rtx temp = gen_reg_rtx (Pmode);
8350 emit_move_insn (temp, s390_back_chain_rtx ());
8351 anti_adjust_stack (operands[1]);
8352 emit_move_insn (s390_back_chain_rtx (), temp);
8354 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8360 ; setjmp instruction pattern.
8363 (define_expand "builtin_setjmp_receiver"
8364 [(match_operand 0 "" "")]
8367 emit_insn (s390_load_got ());
8368 emit_use (pic_offset_table_rtx);
8372 ;; These patterns say how to save and restore the stack pointer. We need not
8373 ;; save the stack pointer at function level since we are careful to
8374 ;; preserve the backchain. At block level, we have to restore the backchain
8375 ;; when we restore the stack pointer.
8377 ;; For nonlocal gotos, we must save both the stack pointer and its
8378 ;; backchain and restore both. Note that in the nonlocal case, the
8379 ;; save area is a memory location.
8381 (define_expand "save_stack_function"
8382 [(match_operand 0 "general_operand" "")
8383 (match_operand 1 "general_operand" "")]
8387 (define_expand "restore_stack_function"
8388 [(match_operand 0 "general_operand" "")
8389 (match_operand 1 "general_operand" "")]
8393 (define_expand "restore_stack_block"
8394 [(match_operand 0 "register_operand" "")
8395 (match_operand 1 "register_operand" "")]
8398 rtx temp = gen_reg_rtx (Pmode);
8400 emit_move_insn (temp, s390_back_chain_rtx ());
8401 emit_move_insn (operands[0], operands[1]);
8402 emit_move_insn (s390_back_chain_rtx (), temp);
8407 (define_expand "save_stack_nonlocal"
8408 [(match_operand 0 "memory_operand" "")
8409 (match_operand 1 "register_operand" "")]
8412 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8413 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8415 /* Copy the backchain to the first word, sp to the second and the
8416 literal pool base to the third. */
8418 if (TARGET_BACKCHAIN)
8420 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
8421 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
8424 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
8425 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
8430 (define_expand "restore_stack_nonlocal"
8431 [(match_operand 0 "register_operand" "")
8432 (match_operand 1 "memory_operand" "")]
8435 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8436 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8437 rtx temp = NULL_RTX;
8439 /* Restore the backchain from the first word, sp from the second and the
8440 literal pool base from the third. */
8442 if (TARGET_BACKCHAIN)
8443 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
8445 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
8446 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
8449 emit_move_insn (s390_back_chain_rtx (), temp);
8455 (define_expand "exception_receiver"
8459 s390_set_has_landing_pad_p (true);
8464 ; nop instruction pattern(s).
8471 [(set_attr "op_type" "RR")])
8477 [(set_attr "op_type" "RR")])
8481 ; Special literal pool access instruction pattern(s).
8484 (define_insn "*pool_entry"
8485 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8486 UNSPECV_POOL_ENTRY)]
8489 enum machine_mode mode = GET_MODE (PATTERN (insn));
8490 unsigned int align = GET_MODE_BITSIZE (mode);
8491 s390_output_pool_entry (operands[0], mode, align);
8494 [(set (attr "length")
8495 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8497 (define_insn "pool_align"
8498 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8499 UNSPECV_POOL_ALIGN)]
8502 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8504 (define_insn "pool_section_start"
8505 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8508 [(set_attr "length" "0")])
8510 (define_insn "pool_section_end"
8511 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8514 [(set_attr "length" "0")])
8516 (define_insn "main_base_31_small"
8517 [(set (match_operand 0 "register_operand" "=a")
8518 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8519 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8521 [(set_attr "op_type" "RR")
8522 (set_attr "type" "la")])
8524 (define_insn "main_base_31_large"
8525 [(set (match_operand 0 "register_operand" "=a")
8526 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8527 (set (pc) (label_ref (match_operand 2 "" "")))]
8528 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8530 [(set_attr "op_type" "RI")])
8532 (define_insn "main_base_64"
8533 [(set (match_operand 0 "register_operand" "=a")
8534 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8535 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8537 [(set_attr "op_type" "RIL")
8538 (set_attr "type" "larl")
8539 (set_attr "z10prop" "z10_super_A1")])
8541 (define_insn "main_pool"
8542 [(set (match_operand 0 "register_operand" "=a")
8543 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8544 "GET_MODE (operands[0]) == Pmode"
8549 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8550 (const_string "larl") (const_string "la")))])
8552 (define_insn "reload_base_31"
8553 [(set (match_operand 0 "register_operand" "=a")
8554 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8555 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8556 "basr\t%0,0\;la\t%0,%1-.(%0)"
8557 [(set_attr "length" "6")
8558 (set_attr "type" "la")])
8560 (define_insn "reload_base_64"
8561 [(set (match_operand 0 "register_operand" "=a")
8562 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8563 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8565 [(set_attr "op_type" "RIL")
8566 (set_attr "type" "larl")
8567 (set_attr "z10prop" "z10_super_A1")])
8570 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8575 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8578 ;; Insns related to generating the function prologue and epilogue.
8582 (define_expand "prologue"
8583 [(use (const_int 0))]
8585 "s390_emit_prologue (); DONE;")
8587 (define_expand "epilogue"
8588 [(use (const_int 1))]
8590 "s390_emit_epilogue (false); DONE;")
8592 (define_expand "sibcall_epilogue"
8593 [(use (const_int 0))]
8595 "s390_emit_epilogue (true); DONE;")
8597 (define_insn "*return"
8599 (use (match_operand 0 "register_operand" "a"))]
8600 "GET_MODE (operands[0]) == Pmode"
8602 [(set_attr "op_type" "RR")
8603 (set_attr "type" "jsr")
8604 (set_attr "atype" "agen")])
8607 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8608 ;; pointer. This is used for compatibility.
8610 (define_expand "ptr_extend"
8611 [(set (match_operand:DI 0 "register_operand" "=r")
8612 (match_operand:SI 1 "register_operand" "r"))]
8615 emit_insn (gen_anddi3 (operands[0],
8616 gen_lowpart (DImode, operands[1]),
8617 GEN_INT (0x7fffffff)));
8621 ;; Instruction definition to expand eh_return macro to support
8622 ;; swapping in special linkage return addresses.
8624 (define_expand "eh_return"
8625 [(use (match_operand 0 "register_operand" ""))]
8628 s390_emit_tpf_eh_return (operands[0]);
8633 ; Stack Protector Patterns
8636 (define_expand "stack_protect_set"
8637 [(set (match_operand 0 "memory_operand" "")
8638 (match_operand 1 "memory_operand" ""))]
8641 #ifdef TARGET_THREAD_SSP_OFFSET
8643 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8644 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8647 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8649 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8654 (define_insn "stack_protect_set<mode>"
8655 [(set (match_operand:DSI 0 "memory_operand" "=Q")
8656 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8658 "mvc\t%O0(%G0,%R0),%S1"
8659 [(set_attr "op_type" "SS")])
8661 (define_expand "stack_protect_test"
8662 [(set (reg:CC CC_REGNUM)
8663 (compare (match_operand 0 "memory_operand" "")
8664 (match_operand 1 "memory_operand" "")))
8665 (match_operand 2 "" "")]
8668 #ifdef TARGET_THREAD_SSP_OFFSET
8670 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8671 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8673 s390_compare_op0 = operands[0];
8674 s390_compare_op1 = operands[1];
8675 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
8678 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8680 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8682 emit_jump_insn (gen_beq (operands[2]));
8687 (define_insn "stack_protect_test<mode>"
8688 [(set (reg:CCZ CC_REGNUM)
8689 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8690 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8692 "clc\t%O0(%G0,%R0),%S1"
8693 [(set_attr "op_type" "SS")])
8695 ; This is used in s390_emit_prologue in order to prevent insns
8696 ; adjusting the stack pointer to be moved over insns writing stack
8697 ; slots using a copy of the stack pointer in a different register.
8698 (define_insn "stack_tie"
8699 [(set (match_operand:BLK 0 "memory_operand" "+m")
8700 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
8703 [(set_attr "length" "0")])
8707 ; Data prefetch patterns
8710 (define_insn "prefetch"
8711 [(prefetch (match_operand 0 "address_operand" "UW,X")
8712 (match_operand:SI 1 "const_int_operand" "n,n")
8713 (match_operand:SI 2 "const_int_operand" "n,n"))]
8716 if (larl_operand (operands[0], Pmode))
8717 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
8719 if (s390_mem_constraint ("W", operands[0])
8720 || s390_mem_constraint ("U", operands[0]))
8721 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
8723 /* This point might be reached if op0 is a larl operand with an
8724 uneven addend. In this case we simply omit issuing a prefetch
8729 [(set_attr "type" "load,larl")
8730 (set_attr "op_type" "RXY,RIL")
8731 (set_attr "z10prop" "z10_super")])