1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
60 (define_c_enum "unspec" [
68 ; GOT/PLT and lt-relative accesses
89 ; TLS relocation specifiers
105 ; Stack Smashing Protector
109 ; Test Data Class (TDC)
118 ;; UNSPEC_VOLATILE usage
121 (define_c_enum "unspecv" [
148 ; Registers with special meaning
152 ; Sibling call register.
154 ; Literal pool base register.
156 ; Return address register.
158 ; Condition code register.
160 ; Thread local storage pointer register.
164 ; Hardware register names
168 ; General purpose registers
170 ; Floating point registers.
176 ;; PFPO GPR0 argument format
181 ; PFPO operation type
182 (PFPO_CONVERT 0x1000000)
184 (PFPO_OP_TYPE_SF 0x5)
185 (PFPO_OP_TYPE_DF 0x6)
186 (PFPO_OP_TYPE_TF 0x7)
187 (PFPO_OP_TYPE_SD 0x8)
188 (PFPO_OP_TYPE_DD 0x9)
189 (PFPO_OP_TYPE_TD 0xa)
190 ; Bitposition of operand types
191 (PFPO_OP0_TYPE_SHIFT 16)
192 (PFPO_OP1_TYPE_SHIFT 8)
196 ;; Instruction operand type as used in the Principles of Operation.
197 ;; Used to determine defaults for length and other attribute values.
199 (define_attr "op_type"
200 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
203 ;; Instruction type attribute used for scheduling.
205 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
206 cs,vs,store,sem,idiv,
207 imulhi,imulsi,imuldi,
208 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
209 floadtf,floaddf,floadsf,fstoredf,fstoresf,
210 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
211 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
213 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
214 itoftf, itofdf, itofsf, itofdd, itoftd,
215 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
216 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
218 (cond [(eq_attr "op_type" "NN") (const_string "other")
219 (eq_attr "op_type" "SS") (const_string "cs")]
220 (const_string "integer")))
222 ;; Another attribute used for scheduling purposes:
223 ;; agen: Instruction uses the address generation unit
224 ;; reg: Instruction does not use the agen unit
226 (define_attr "atype" "agen,reg"
227 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
229 (const_string "agen")))
231 ;; Properties concerning Z10 execution grouping and value forwarding.
232 ;; z10_super: instruction is superscalar.
233 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
234 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
235 ;; target register. It can forward this value to a second instruction that reads
236 ;; the same register if that second instruction is issued in the same group.
237 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
238 ;; instruction in the S pipe writes to the register, then the T instruction
239 ;; can immediately read the new value.
240 ;; z10_fr: union of Z10_fwd and z10_rec.
241 ;; z10_c: second operand of instruction is a register and read with complemented bits.
243 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
246 (define_attr "z10prop" "none,
247 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
248 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
250 z10_fr, z10_fr_A3, z10_fr_E1,
252 (const_string "none"))
254 ;; Properties concerning Z196 decoding
255 ;; z196_alone: must group alone
256 ;; z196_end: ends a group
257 ;; z196_cracked: instruction is cracked or expanded
258 (define_attr "z196prop" "none,
259 z196_alone, z196_ends,
261 (const_string "none"))
263 (define_attr "mnemonic" "unknown" (const_string "unknown"))
267 (define_attr "length" ""
268 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
269 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
273 ;; Processor type. This attribute must exactly match the processor_type
274 ;; enumeration in s390.h. The current machine description does not
275 ;; distinguish between g5 and g6, but there are differences between the two
276 ;; CPUs could in theory be modeled.
278 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
279 (const (symbol_ref "s390_tune_attr")))
281 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196,zEC12"
282 (const_string "standard"))
284 (define_attr "enabled" ""
285 (cond [(eq_attr "cpu_facility" "standard")
288 (and (eq_attr "cpu_facility" "ieee")
289 (match_test "TARGET_CPU_IEEE_FLOAT"))
292 (and (eq_attr "cpu_facility" "zarch")
293 (match_test "TARGET_ZARCH"))
296 (and (eq_attr "cpu_facility" "longdisp")
297 (match_test "TARGET_LONG_DISPLACEMENT"))
300 (and (eq_attr "cpu_facility" "extimm")
301 (match_test "TARGET_EXTIMM"))
304 (and (eq_attr "cpu_facility" "dfp")
305 (match_test "TARGET_DFP"))
308 (and (eq_attr "cpu_facility" "z10")
309 (match_test "TARGET_Z10"))
312 (and (eq_attr "cpu_facility" "z196")
313 (match_test "TARGET_Z196"))
316 (and (eq_attr "cpu_facility" "zEC12")
317 (match_test "TARGET_ZEC12"))
321 ;; Pipeline description for z900. For lack of anything better,
322 ;; this description is also used for the g5 and g6.
325 ;; Pipeline description for z990, z9-109 and z9-ec.
328 ;; Pipeline description for z10
331 ;; Pipeline description for z196
334 ;; Pipeline description for zEC12
338 (include "predicates.md")
340 ;; Constraint definitions
341 (include "constraints.md")
348 ;; These mode iterators allow floating point patterns to be generated from the
350 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
351 (SD "TARGET_HARD_DFP")])
352 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
353 (define_mode_iterator FPALL [TF DF SF TD DD SD])
354 (define_mode_iterator BFP [TF DF SF])
355 (define_mode_iterator DFP [TD DD])
356 (define_mode_iterator DFP_ALL [TD DD SD])
357 (define_mode_iterator DSF [DF SF])
358 (define_mode_iterator SD_SF [SF SD])
359 (define_mode_iterator DD_DF [DF DD])
360 (define_mode_iterator TD_TF [TF TD])
362 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
363 ;; from the same template.
364 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
365 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
366 (define_mode_iterator DSI [DI SI])
367 (define_mode_iterator TDI [TI DI])
369 ;; These mode iterators allow :P to be used for patterns that operate on
370 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
371 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
373 ;; These macros refer to the actual word_mode of the configuration.
374 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
375 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
376 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
378 ;; Used by the umul pattern to express modes having half the size.
379 (define_mode_attr DWH [(TI "DI") (DI "SI")])
380 (define_mode_attr dwh [(TI "di") (DI "si")])
382 ;; This mode iterator allows the QI and HI patterns to be defined from
383 ;; the same template.
384 (define_mode_iterator HQI [HI QI])
386 ;; This mode iterator allows the integer patterns to be defined from the
388 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
389 (define_mode_iterator INTALL [TI DI SI HI QI])
390 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
392 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
393 ;; the same template.
394 (define_code_iterator SHIFT [ashift lshiftrt])
396 ;; This iterator and attribute allow to combine most atomic operations.
397 (define_code_iterator ATOMIC [and ior xor plus minus mult])
398 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
399 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
400 (plus "add") (minus "sub") (mult "nand")])
401 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
403 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
404 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
405 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
407 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
408 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
410 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
412 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
413 ;; Likewise for "<RXe>".
414 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
415 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
417 ;; The decimal floating point variants of add, sub, div and mul support 3
418 ;; fp register operands. The following attributes allow to merge the bfp and
419 ;; dfp variants in a single insn definition.
421 ;; This attribute is used to set op_type accordingly.
422 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
423 (DD "RRR") (SD "RRR")])
425 ;; This attribute is used in the operand constraint list in order to have the
426 ;; first and the second operand match for bfp modes.
427 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
429 ;; This attribute is used in the operand list of the instruction to have an
430 ;; additional operand for the dfp instructions.
431 (define_mode_attr op1 [(TF "") (DF "") (SF "")
432 (TD "%1,") (DD "%1,") (SD "%1,")])
435 ;; This attribute is used in the operand constraint list
436 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
437 ;; TFmode values are represented by a fp register pair. Since the
438 ;; sign bit instructions only handle single source and target fp registers
439 ;; these instructions can only be used for TFmode values if the source and
440 ;; target operand uses the same fp register.
441 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
443 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
444 ;; This is used to disable the memory alternative in TFmode patterns.
445 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
447 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
448 ;; within instruction mnemonics.
449 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
451 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
452 ;; modes and to an empty string for bfp modes.
453 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
455 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
456 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
457 ;; version only operates on one register.
458 (define_mode_attr d0 [(DI "d") (SI "0")])
460 ;; In combination with d0 this allows to combine instructions of which the 31bit
461 ;; version only operates on one register. The DImode version needs an additional
462 ;; register for the assembler output.
463 (define_mode_attr 1 [(DI "%1,") (SI "")])
465 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
466 ;; 'ashift' and "srdl" in 'lshiftrt'.
467 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
469 ;; In SHIFT templates, this attribute holds the correct standard name for the
470 ;; pattern itself and the corresponding function calls.
471 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
473 ;; This attribute handles differences in the instruction 'type' and will result
474 ;; in "RRE" for DImode and "RR" for SImode.
475 (define_mode_attr E [(DI "E") (SI "")])
477 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
478 ;; to result in "RXY" for DImode and "RX" for SImode.
479 (define_mode_attr Y [(DI "Y") (SI "")])
481 ;; This attribute handles differences in the instruction 'type' and will result
482 ;; in "RSE" for TImode and "RS" for DImode.
483 (define_mode_attr TE [(TI "E") (DI "")])
485 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
486 ;; and "lcr" in SImode.
487 (define_mode_attr g [(DI "g") (SI "")])
489 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
490 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
491 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
492 ;; variant for long displacements.
493 (define_mode_attr y [(DI "g") (SI "y")])
495 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
496 ;; and "cds" in DImode.
497 (define_mode_attr tg [(TI "g") (DI "")])
499 ;; In TDI templates, a string like "c<d>sg".
500 (define_mode_attr td [(TI "d") (DI "")])
502 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
503 ;; and "cfdbr" in SImode.
504 (define_mode_attr gf [(DI "g") (SI "f")])
506 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
507 ;; and sllk for SI. This way it is possible to merge the new z196 SI
508 ;; 3 operands shift instructions into the existing patterns.
509 (define_mode_attr gk [(DI "g") (SI "k")])
511 ;; ICM mask required to load MODE value into the lowest subreg
512 ;; of a SImode register.
513 (define_mode_attr icm_lo [(HI "3") (QI "1")])
515 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
516 ;; HImode and "llgc" in QImode.
517 (define_mode_attr hc [(HI "h") (QI "c")])
519 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
521 (define_mode_attr DBL [(DI "TI") (SI "DI")])
523 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
524 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
525 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
527 ;; Maximum unsigned integer that fits in MODE.
528 (define_mode_attr max_uint [(HI "65535") (QI "255")])
530 ;; Start and end field computations for RISBG et al.
531 (define_mode_attr bfstart [(DI "s") (SI "t")])
532 (define_mode_attr bfend [(DI "e") (SI "f")])
534 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
535 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
538 ;;- Compare instructions.
541 ; Test-under-Mask instructions
543 (define_insn "*tmqi_mem"
544 [(set (reg CC_REGNUM)
545 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
546 (match_operand:QI 1 "immediate_operand" "n,n"))
547 (match_operand:QI 2 "immediate_operand" "n,n")))]
548 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
552 [(set_attr "op_type" "SI,SIY")
553 (set_attr "z10prop" "z10_super,z10_super")])
555 (define_insn "*tmdi_reg"
556 [(set (reg CC_REGNUM)
557 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
558 (match_operand:DI 1 "immediate_operand"
559 "N0HD0,N1HD0,N2HD0,N3HD0"))
560 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
562 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
563 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
569 [(set_attr "op_type" "RI")
570 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
572 (define_insn "*tmsi_reg"
573 [(set (reg CC_REGNUM)
574 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
575 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
576 (match_operand:SI 2 "immediate_operand" "n,n")))]
577 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
578 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
582 [(set_attr "op_type" "RI")
583 (set_attr "z10prop" "z10_super,z10_super")])
585 (define_insn "*tm<mode>_full"
586 [(set (reg CC_REGNUM)
587 (compare (match_operand:HQI 0 "register_operand" "d")
588 (match_operand:HQI 1 "immediate_operand" "n")))]
589 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
591 [(set_attr "op_type" "RI")
592 (set_attr "z10prop" "z10_super")])
596 ; Load-and-Test instructions
599 ; tst(di|si) instruction pattern(s).
601 (define_insn "*tstdi_sign"
602 [(set (reg CC_REGNUM)
606 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
607 (const_int 32)) (const_int 32))
608 (match_operand:DI 1 "const0_operand" "")))
609 (set (match_operand:DI 2 "register_operand" "=d,d")
610 (sign_extend:DI (match_dup 0)))]
611 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
614 [(set_attr "op_type" "RRE,RXY")
615 (set_attr "cpu_facility" "*,z10")
616 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
619 (define_insn "*tst<mode>_extimm"
620 [(set (reg CC_REGNUM)
621 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
622 (match_operand:GPR 1 "const0_operand" "")))
623 (set (match_operand:GPR 2 "register_operand" "=d,d")
625 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
629 [(set_attr "op_type" "RR<E>,RXY")
630 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
633 (define_insn "*tst<mode>_cconly_extimm"
634 [(set (reg CC_REGNUM)
635 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
636 (match_operand:GPR 1 "const0_operand" "")))
637 (clobber (match_scratch:GPR 2 "=X,d"))]
638 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
642 [(set_attr "op_type" "RR<E>,RXY")
643 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
645 (define_insn "*tstdi"
646 [(set (reg CC_REGNUM)
647 (compare (match_operand:DI 0 "register_operand" "d")
648 (match_operand:DI 1 "const0_operand" "")))
649 (set (match_operand:DI 2 "register_operand" "=d")
651 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
653 [(set_attr "op_type" "RRE")
654 (set_attr "z10prop" "z10_fr_E1")])
656 (define_insn "*tstsi"
657 [(set (reg CC_REGNUM)
658 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
659 (match_operand:SI 1 "const0_operand" "")))
660 (set (match_operand:SI 2 "register_operand" "=d,d,d")
662 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
667 [(set_attr "op_type" "RR,RS,RSY")
668 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
670 (define_insn "*tstsi_cconly"
671 [(set (reg CC_REGNUM)
672 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
673 (match_operand:SI 1 "const0_operand" "")))
674 (clobber (match_scratch:SI 2 "=X,d,d"))]
675 "s390_match_ccmode(insn, CCSmode)"
680 [(set_attr "op_type" "RR,RS,RSY")
681 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
683 (define_insn "*tstdi_cconly_31"
684 [(set (reg CC_REGNUM)
685 (compare (match_operand:DI 0 "register_operand" "d")
686 (match_operand:DI 1 "const0_operand" "")))]
687 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
689 [(set_attr "op_type" "RS")
690 (set_attr "atype" "reg")])
693 (define_insn "*tst<mode>_cconly2"
694 [(set (reg CC_REGNUM)
695 (compare (match_operand:GPR 0 "register_operand" "d")
696 (match_operand:GPR 1 "const0_operand" "")))]
697 "s390_match_ccmode(insn, CCSmode)"
699 [(set_attr "op_type" "RR<E>")
700 (set_attr "z10prop" "z10_fr_E1")])
702 ; tst(hi|qi) instruction pattern(s).
704 (define_insn "*tst<mode>CCT"
705 [(set (reg CC_REGNUM)
706 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
707 (match_operand:HQI 1 "const0_operand" "")))
708 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
710 "s390_match_ccmode(insn, CCTmode)"
713 icmy\t%2,<icm_lo>,%S0
715 [(set_attr "op_type" "RS,RSY,RI")
716 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
718 (define_insn "*tsthiCCT_cconly"
719 [(set (reg CC_REGNUM)
720 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
721 (match_operand:HI 1 "const0_operand" "")))
722 (clobber (match_scratch:HI 2 "=d,d,X"))]
723 "s390_match_ccmode(insn, CCTmode)"
728 [(set_attr "op_type" "RS,RSY,RI")
729 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
731 (define_insn "*tstqiCCT_cconly"
732 [(set (reg CC_REGNUM)
733 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
734 (match_operand:QI 1 "const0_operand" "")))]
735 "s390_match_ccmode(insn, CCTmode)"
740 [(set_attr "op_type" "SI,SIY,RI")
741 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
743 (define_insn "*tst<mode>"
744 [(set (reg CC_REGNUM)
745 (compare (match_operand:HQI 0 "s_operand" "Q,S")
746 (match_operand:HQI 1 "const0_operand" "")))
747 (set (match_operand:HQI 2 "register_operand" "=d,d")
749 "s390_match_ccmode(insn, CCSmode)"
752 icmy\t%2,<icm_lo>,%S0"
753 [(set_attr "op_type" "RS,RSY")
754 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
756 (define_insn "*tst<mode>_cconly"
757 [(set (reg CC_REGNUM)
758 (compare (match_operand:HQI 0 "s_operand" "Q,S")
759 (match_operand:HQI 1 "const0_operand" "")))
760 (clobber (match_scratch:HQI 2 "=d,d"))]
761 "s390_match_ccmode(insn, CCSmode)"
764 icmy\t%2,<icm_lo>,%S0"
765 [(set_attr "op_type" "RS,RSY")
766 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
769 ; Compare (equality) instructions
771 (define_insn "*cmpdi_cct"
772 [(set (reg CC_REGNUM)
773 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
774 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
775 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
782 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
783 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
785 (define_insn "*cmpsi_cct"
786 [(set (reg CC_REGNUM)
787 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
788 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
789 "s390_match_ccmode (insn, CCTmode)"
797 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
798 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
800 ; Compare (signed) instructions
802 (define_insn "*cmpdi_ccs_sign"
803 [(set (reg CC_REGNUM)
804 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
806 (match_operand:DI 0 "register_operand" "d, d,d")))]
807 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
812 [(set_attr "op_type" "RRE,RXY,RIL")
813 (set_attr "z10prop" "z10_c,*,*")
814 (set_attr "type" "*,*,larl")])
818 (define_insn "*cmpsi_ccs_sign"
819 [(set (reg CC_REGNUM)
820 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
821 (match_operand:SI 0 "register_operand" "d,d,d")))]
822 "s390_match_ccmode(insn, CCSRmode)"
827 [(set_attr "op_type" "RX,RXY,RIL")
828 (set_attr "cpu_facility" "*,*,z10")
829 (set_attr "type" "*,*,larl")
830 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
832 (define_insn "*cmphi_ccs_z10"
833 [(set (reg CC_REGNUM)
834 (compare (match_operand:HI 0 "s_operand" "Q")
835 (match_operand:HI 1 "immediate_operand" "K")))]
836 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
838 [(set_attr "op_type" "SIL")
839 (set_attr "z196prop" "z196_cracked")])
841 (define_insn "*cmpdi_ccs_signhi_rl"
842 [(set (reg CC_REGNUM)
843 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
844 (match_operand:GPR 0 "register_operand" "d,d")))]
845 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
849 [(set_attr "op_type" "RXY,RIL")
850 (set_attr "type" "*,larl")])
852 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
853 (define_insn "*cmp<mode>_ccs"
854 [(set (reg CC_REGNUM)
855 (compare (match_operand:GPR 0 "nonimmediate_operand"
857 (match_operand:GPR 1 "general_operand"
859 "s390_match_ccmode(insn, CCSmode)"
868 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
869 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
870 (set_attr "type" "*,*,*,*,*,*,larl")
871 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
874 ; Compare (unsigned) instructions
876 (define_insn "*cmpsi_ccu_zerohi_rlsi"
877 [(set (reg CC_REGNUM)
878 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
879 "larl_operand" "X")))
880 (match_operand:SI 0 "register_operand" "d")))]
881 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
883 [(set_attr "op_type" "RIL")
884 (set_attr "type" "larl")
885 (set_attr "z10prop" "z10_super")])
888 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
889 [(set (reg CC_REGNUM)
890 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
891 "larl_operand" "X")))
892 (match_operand:GPR 0 "register_operand" "d")))]
893 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
895 [(set_attr "op_type" "RIL")
896 (set_attr "type" "larl")
897 (set_attr "z10prop" "z10_super")])
899 (define_insn "*cmpdi_ccu_zero"
900 [(set (reg CC_REGNUM)
901 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
903 (match_operand:DI 0 "register_operand" "d, d,d")))]
904 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
909 [(set_attr "op_type" "RRE,RXY,RIL")
910 (set_attr "cpu_facility" "*,*,z10")
911 (set_attr "type" "*,*,larl")
912 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
914 (define_insn "*cmpdi_ccu"
915 [(set (reg CC_REGNUM)
916 (compare (match_operand:DI 0 "nonimmediate_operand"
918 (match_operand:DI 1 "general_operand"
919 "d,Op,b,D,RT,BQ,Q")))]
920 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
929 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
930 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
931 (set_attr "type" "*,*,larl,*,*,*,*")
932 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
934 (define_insn "*cmpsi_ccu"
935 [(set (reg CC_REGNUM)
936 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
937 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
938 "s390_match_ccmode (insn, CCUmode)"
948 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
949 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
950 (set_attr "type" "*,*,larl,*,*,*,*,*")
951 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
953 (define_insn "*cmphi_ccu"
954 [(set (reg CC_REGNUM)
955 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
956 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
957 "s390_match_ccmode (insn, CCUmode)
958 && !register_operand (operands[1], HImode)"
965 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
966 (set_attr "cpu_facility" "*,*,z10,*,*")
967 (set_attr "z10prop" "*,*,z10_super,*,*")])
969 (define_insn "*cmpqi_ccu"
970 [(set (reg CC_REGNUM)
971 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
972 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
973 "s390_match_ccmode (insn, CCUmode)
974 && !register_operand (operands[1], QImode)"
982 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
983 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
986 ; Block compare (CLC) instruction patterns.
989 [(set (reg CC_REGNUM)
990 (compare (match_operand:BLK 0 "memory_operand" "Q")
991 (match_operand:BLK 1 "memory_operand" "Q")))
992 (use (match_operand 2 "const_int_operand" "n"))]
993 "s390_match_ccmode (insn, CCUmode)
994 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
995 "clc\t%O0(%2,%R0),%S1"
996 [(set_attr "op_type" "SS")])
999 [(set (reg CC_REGNUM)
1000 (compare (match_operand 0 "memory_operand" "")
1001 (match_operand 1 "memory_operand" "")))]
1003 && s390_match_ccmode (insn, CCUmode)
1004 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1005 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1007 [(set (match_dup 0) (match_dup 1))
1008 (use (match_dup 2))])]
1010 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1011 operands[0] = adjust_address (operands[0], BLKmode, 0);
1012 operands[1] = adjust_address (operands[1], BLKmode, 0);
1014 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1015 operands[0], operands[1]);
1016 operands[0] = SET_DEST (PATTERN (curr_insn));
1020 ; (TF|DF|SF|TD|DD|SD) instructions
1022 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1023 (define_insn "*cmp<mode>_ccs_0"
1024 [(set (reg CC_REGNUM)
1025 (compare (match_operand:FP 0 "register_operand" "f")
1026 (match_operand:FP 1 "const0_operand" "")))]
1027 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1028 "lt<xde><bt>r\t%0,%0"
1029 [(set_attr "op_type" "RRE")
1030 (set_attr "type" "fsimp<mode>")])
1032 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1033 (define_insn "*cmp<mode>_ccs"
1034 [(set (reg CC_REGNUM)
1035 (compare (match_operand:FP 0 "register_operand" "f,f")
1036 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1037 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1041 [(set_attr "op_type" "RRE,RXE")
1042 (set_attr "type" "fsimp<mode>")])
1045 ; Compare and Branch instructions
1047 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1048 ; The following instructions do a complementary access of their second
1049 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1050 (define_insn "*cmp_and_br_signed_<mode>"
1052 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1053 [(match_operand:GPR 1 "register_operand" "d,d")
1054 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1055 (label_ref (match_operand 3 "" ""))
1057 (clobber (reg:CC CC_REGNUM))]
1058 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1060 if (get_attr_length (insn) == 6)
1061 return which_alternative ?
1062 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1064 return which_alternative ?
1065 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1067 [(set_attr "op_type" "RIE")
1068 (set_attr "type" "branch")
1069 (set_attr "z10prop" "z10_super_c,z10_super")
1070 (set (attr "length")
1071 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1072 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1073 ; 10 byte for cgr/jg
1075 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1076 ; The following instructions do a complementary access of their second
1077 ; operand (z10 only): clrj, clgrj, clr, clgr
1078 (define_insn "*cmp_and_br_unsigned_<mode>"
1080 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1081 [(match_operand:GPR 1 "register_operand" "d,d")
1082 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1083 (label_ref (match_operand 3 "" ""))
1085 (clobber (reg:CC CC_REGNUM))]
1086 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1088 if (get_attr_length (insn) == 6)
1089 return which_alternative ?
1090 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1092 return which_alternative ?
1093 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1095 [(set_attr "op_type" "RIE")
1096 (set_attr "type" "branch")
1097 (set_attr "z10prop" "z10_super_c,z10_super")
1098 (set (attr "length")
1099 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1100 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1101 ; 10 byte for clgr/jg
1103 ; And now the same two patterns as above but with a negated CC mask.
1105 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1106 ; The following instructions do a complementary access of their second
1107 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1108 (define_insn "*icmp_and_br_signed_<mode>"
1110 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1111 [(match_operand:GPR 1 "register_operand" "d,d")
1112 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1114 (label_ref (match_operand 3 "" ""))))
1115 (clobber (reg:CC CC_REGNUM))]
1116 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1118 if (get_attr_length (insn) == 6)
1119 return which_alternative ?
1120 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1122 return which_alternative ?
1123 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1125 [(set_attr "op_type" "RIE")
1126 (set_attr "type" "branch")
1127 (set_attr "z10prop" "z10_super_c,z10_super")
1128 (set (attr "length")
1129 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1130 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1131 ; 10 byte for cgr/jg
1133 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1134 ; The following instructions do a complementary access of their second
1135 ; operand (z10 only): clrj, clgrj, clr, clgr
1136 (define_insn "*icmp_and_br_unsigned_<mode>"
1138 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1139 [(match_operand:GPR 1 "register_operand" "d,d")
1140 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1142 (label_ref (match_operand 3 "" ""))))
1143 (clobber (reg:CC CC_REGNUM))]
1144 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1146 if (get_attr_length (insn) == 6)
1147 return which_alternative ?
1148 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1150 return which_alternative ?
1151 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1153 [(set_attr "op_type" "RIE")
1154 (set_attr "type" "branch")
1155 (set_attr "z10prop" "z10_super_c,z10_super")
1156 (set (attr "length")
1157 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1158 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1159 ; 10 byte for clgr/jg
1162 ;;- Move instructions.
1166 ; movti instruction pattern(s).
1169 (define_insn "movti"
1170 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1171 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1178 [(set_attr "op_type" "RSY,RSY,*,*")
1179 (set_attr "type" "lm,stm,*,*")])
1182 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1183 (match_operand:TI 1 "general_operand" ""))]
1184 "TARGET_ZARCH && reload_completed
1185 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1186 [(set (match_dup 2) (match_dup 4))
1187 (set (match_dup 3) (match_dup 5))]
1189 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1190 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1191 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1192 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1196 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1197 (match_operand:TI 1 "general_operand" ""))]
1198 "TARGET_ZARCH && reload_completed
1199 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1200 [(set (match_dup 2) (match_dup 4))
1201 (set (match_dup 3) (match_dup 5))]
1203 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1204 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1205 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1206 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1210 [(set (match_operand:TI 0 "register_operand" "")
1211 (match_operand:TI 1 "memory_operand" ""))]
1212 "TARGET_ZARCH && reload_completed
1213 && !s_operand (operands[1], VOIDmode)"
1214 [(set (match_dup 0) (match_dup 1))]
1216 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1217 addr = gen_lowpart (Pmode, addr);
1218 s390_load_address (addr, XEXP (operands[1], 0));
1219 operands[1] = replace_equiv_address (operands[1], addr);
1224 ; Patterns used for secondary reloads
1227 ; z10 provides move instructions accepting larl memory operands.
1228 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1229 ; These patterns are also used for unaligned SI and DI accesses.
1231 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1232 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1233 (match_operand:INTALL 1 "register_operand" "=d")
1234 (match_operand:P 2 "register_operand" "=&a")])]
1237 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1241 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1242 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1243 (match_operand:INTALL 1 "memory_operand" "")
1244 (match_operand:P 2 "register_operand" "=a")])]
1247 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1251 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1252 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1253 (match_operand:FPALL 1 "register_operand" "=d")
1254 (match_operand:P 2 "register_operand" "=&a")])]
1257 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1261 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1262 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1263 (match_operand:FPALL 1 "memory_operand" "")
1264 (match_operand:P 2 "register_operand" "=a")])]
1267 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1271 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1272 [(parallel [(match_operand:P 0 "register_operand" "=d")
1273 (match_operand:P 1 "larl_operand" "")
1274 (match_operand:P 2 "register_operand" "=a")])]
1277 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1281 ; Handles loading a PLUS (load address) expression
1283 (define_expand "reload<mode>_plus"
1284 [(parallel [(match_operand:P 0 "register_operand" "=a")
1285 (match_operand:P 1 "s390_plus_operand" "")
1286 (match_operand:P 2 "register_operand" "=&a")])]
1289 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1293 ; Handles assessing a non-offsetable memory address
1295 (define_expand "reload<mode>_nonoffmem_in"
1296 [(parallel [(match_operand 0 "register_operand" "")
1297 (match_operand 1 "" "")
1298 (match_operand:P 2 "register_operand" "=&a")])]
1301 gcc_assert (MEM_P (operands[1]));
1302 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1303 operands[1] = replace_equiv_address (operands[1], operands[2]);
1304 emit_move_insn (operands[0], operands[1]);
1308 (define_expand "reload<mode>_nonoffmem_out"
1309 [(parallel [(match_operand 0 "" "")
1310 (match_operand 1 "register_operand" "")
1311 (match_operand:P 2 "register_operand" "=&a")])]
1314 gcc_assert (MEM_P (operands[0]));
1315 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1316 operands[0] = replace_equiv_address (operands[0], operands[2]);
1317 emit_move_insn (operands[0], operands[1]);
1321 (define_expand "reload<mode>_PIC_addr"
1322 [(parallel [(match_operand 0 "register_operand" "=d")
1323 (match_operand 1 "larl_operand" "")
1324 (match_operand:P 2 "register_operand" "=a")])]
1327 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1328 emit_move_insn (operands[0], new_rtx);
1332 ; movdi instruction pattern(s).
1335 (define_expand "movdi"
1336 [(set (match_operand:DI 0 "general_operand" "")
1337 (match_operand:DI 1 "general_operand" ""))]
1340 /* Handle symbolic constants. */
1342 && (SYMBOLIC_CONST (operands[1])
1343 || (GET_CODE (operands[1]) == PLUS
1344 && XEXP (operands[1], 0) == pic_offset_table_rtx
1345 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1346 emit_symbolic_move (operands);
1349 (define_insn "*movdi_larl"
1350 [(set (match_operand:DI 0 "register_operand" "=d")
1351 (match_operand:DI 1 "larl_operand" "X"))]
1353 && !FP_REG_P (operands[0])"
1355 [(set_attr "op_type" "RIL")
1356 (set_attr "type" "larl")
1357 (set_attr "z10prop" "z10_super_A1")])
1359 (define_insn "*movdi_64"
1360 [(set (match_operand:DI 0 "nonimmediate_operand"
1361 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1362 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1363 (match_operand:DI 1 "general_operand"
1364 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1365 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1394 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1395 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1396 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1397 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1399 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1400 z10,*,*,*,*,*,longdisp,*,longdisp,
1402 (set_attr "z10prop" "z10_fwd_A1,
1431 [(set (match_operand:DI 0 "register_operand" "")
1432 (match_operand:DI 1 "register_operand" ""))]
1433 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1434 [(set (match_dup 2) (match_dup 3))
1435 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1436 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1437 "operands[2] = gen_lowpart (SImode, operands[0]);
1438 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1441 [(set (match_operand:DI 0 "register_operand" "")
1442 (match_operand:DI 1 "register_operand" ""))]
1443 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1444 && dead_or_set_p (insn, operands[1])"
1445 [(set (match_dup 3) (match_dup 2))
1446 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1447 (set (match_dup 4) (match_dup 2))]
1448 "operands[2] = gen_lowpart (SImode, operands[1]);
1449 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1452 [(set (match_operand:DI 0 "register_operand" "")
1453 (match_operand:DI 1 "register_operand" ""))]
1454 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1455 && !dead_or_set_p (insn, operands[1])"
1456 [(set (match_dup 3) (match_dup 2))
1457 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1458 (set (match_dup 4) (match_dup 2))
1459 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1460 "operands[2] = gen_lowpart (SImode, operands[1]);
1461 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1463 (define_insn "*movdi_31"
1464 [(set (match_operand:DI 0 "nonimmediate_operand"
1465 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1466 (match_operand:DI 1 "general_operand"
1467 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1482 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1483 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1484 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1486 ; For a load from a symbol ref we can use one of the target registers
1487 ; together with larl to load the address.
1489 [(set (match_operand:DI 0 "register_operand" "")
1490 (match_operand:DI 1 "memory_operand" ""))]
1491 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1492 && larl_operand (XEXP (operands[1], 0), SImode)"
1493 [(set (match_dup 2) (match_dup 3))
1494 (set (match_dup 0) (match_dup 1))]
1496 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1497 operands[3] = XEXP (operands[1], 0);
1498 operands[1] = replace_equiv_address (operands[1], operands[2]);
1502 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1503 (match_operand:DI 1 "general_operand" ""))]
1504 "!TARGET_ZARCH && reload_completed
1505 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1506 [(set (match_dup 2) (match_dup 4))
1507 (set (match_dup 3) (match_dup 5))]
1509 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1510 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1511 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1512 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1516 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1517 (match_operand:DI 1 "general_operand" ""))]
1518 "!TARGET_ZARCH && reload_completed
1519 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1520 [(set (match_dup 2) (match_dup 4))
1521 (set (match_dup 3) (match_dup 5))]
1523 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1524 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1525 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1526 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1530 [(set (match_operand:DI 0 "register_operand" "")
1531 (match_operand:DI 1 "memory_operand" ""))]
1532 "!TARGET_ZARCH && reload_completed
1533 && !FP_REG_P (operands[0])
1534 && !s_operand (operands[1], VOIDmode)"
1535 [(set (match_dup 0) (match_dup 1))]
1537 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1538 s390_load_address (addr, XEXP (operands[1], 0));
1539 operands[1] = replace_equiv_address (operands[1], addr);
1543 [(set (match_operand:DI 0 "register_operand" "")
1544 (mem:DI (match_operand 1 "address_operand" "")))]
1546 && !FP_REG_P (operands[0])
1547 && GET_CODE (operands[1]) == SYMBOL_REF
1548 && CONSTANT_POOL_ADDRESS_P (operands[1])
1549 && get_pool_mode (operands[1]) == DImode
1550 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1551 [(set (match_dup 0) (match_dup 2))]
1552 "operands[2] = get_pool_constant (operands[1]);")
1554 (define_insn "*la_64"
1555 [(set (match_operand:DI 0 "register_operand" "=d,d")
1556 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1561 [(set_attr "op_type" "RX,RXY")
1562 (set_attr "type" "la")
1563 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1567 [(set (match_operand:DI 0 "register_operand" "")
1568 (match_operand:QI 1 "address_operand" ""))
1569 (clobber (reg:CC CC_REGNUM))])]
1571 && preferred_la_operand_p (operands[1], const0_rtx)"
1572 [(set (match_dup 0) (match_dup 1))]
1576 [(set (match_operand:DI 0 "register_operand" "")
1577 (match_operand:DI 1 "register_operand" ""))
1580 (plus:DI (match_dup 0)
1581 (match_operand:DI 2 "nonmemory_operand" "")))
1582 (clobber (reg:CC CC_REGNUM))])]
1584 && !reg_overlap_mentioned_p (operands[0], operands[2])
1585 && preferred_la_operand_p (operands[1], operands[2])"
1586 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1590 ; movsi instruction pattern(s).
1593 (define_expand "movsi"
1594 [(set (match_operand:SI 0 "general_operand" "")
1595 (match_operand:SI 1 "general_operand" ""))]
1598 /* Handle symbolic constants. */
1600 && (SYMBOLIC_CONST (operands[1])
1601 || (GET_CODE (operands[1]) == PLUS
1602 && XEXP (operands[1], 0) == pic_offset_table_rtx
1603 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1604 emit_symbolic_move (operands);
1607 (define_insn "*movsi_larl"
1608 [(set (match_operand:SI 0 "register_operand" "=d")
1609 (match_operand:SI 1 "larl_operand" "X"))]
1610 "!TARGET_64BIT && TARGET_CPU_ZARCH
1611 && !FP_REG_P (operands[0])"
1613 [(set_attr "op_type" "RIL")
1614 (set_attr "type" "larl")
1615 (set_attr "z10prop" "z10_fwd_A1")])
1617 (define_insn "*movsi_zarch"
1618 [(set (match_operand:SI 0 "nonimmediate_operand"
1619 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1620 (match_operand:SI 1 "general_operand"
1621 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1646 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1647 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1648 (set_attr "type" "*,
1670 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1671 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1672 (set_attr "z10prop" "z10_fwd_A1,
1695 (define_insn "*movsi_esa"
1696 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1697 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1711 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1712 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1713 (set_attr "z10prop" "z10_fwd_A1,
1727 [(set (match_operand:SI 0 "register_operand" "")
1728 (mem:SI (match_operand 1 "address_operand" "")))]
1729 "!FP_REG_P (operands[0])
1730 && GET_CODE (operands[1]) == SYMBOL_REF
1731 && CONSTANT_POOL_ADDRESS_P (operands[1])
1732 && get_pool_mode (operands[1]) == SImode
1733 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1734 [(set (match_dup 0) (match_dup 2))]
1735 "operands[2] = get_pool_constant (operands[1]);")
1737 (define_insn "*la_31"
1738 [(set (match_operand:SI 0 "register_operand" "=d,d")
1739 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1740 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1744 [(set_attr "op_type" "RX,RXY")
1745 (set_attr "type" "la")
1746 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1750 [(set (match_operand:SI 0 "register_operand" "")
1751 (match_operand:QI 1 "address_operand" ""))
1752 (clobber (reg:CC CC_REGNUM))])]
1754 && preferred_la_operand_p (operands[1], const0_rtx)"
1755 [(set (match_dup 0) (match_dup 1))]
1759 [(set (match_operand:SI 0 "register_operand" "")
1760 (match_operand:SI 1 "register_operand" ""))
1763 (plus:SI (match_dup 0)
1764 (match_operand:SI 2 "nonmemory_operand" "")))
1765 (clobber (reg:CC CC_REGNUM))])]
1767 && !reg_overlap_mentioned_p (operands[0], operands[2])
1768 && preferred_la_operand_p (operands[1], operands[2])"
1769 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1772 (define_insn "*la_31_and"
1773 [(set (match_operand:SI 0 "register_operand" "=d,d")
1774 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1775 (const_int 2147483647)))]
1780 [(set_attr "op_type" "RX,RXY")
1781 (set_attr "type" "la")
1782 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1784 (define_insn_and_split "*la_31_and_cc"
1785 [(set (match_operand:SI 0 "register_operand" "=d")
1786 (and:SI (match_operand:QI 1 "address_operand" "p")
1787 (const_int 2147483647)))
1788 (clobber (reg:CC CC_REGNUM))]
1791 "&& reload_completed"
1793 (and:SI (match_dup 1) (const_int 2147483647)))]
1795 [(set_attr "op_type" "RX")
1796 (set_attr "type" "la")])
1798 (define_insn "force_la_31"
1799 [(set (match_operand:SI 0 "register_operand" "=d,d")
1800 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1801 (use (const_int 0))]
1806 [(set_attr "op_type" "RX")
1807 (set_attr "type" "la")
1808 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1811 ; movhi instruction pattern(s).
1814 (define_expand "movhi"
1815 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1816 (match_operand:HI 1 "general_operand" ""))]
1819 /* Make it explicit that loading a register from memory
1820 always sign-extends (at least) to SImode. */
1821 if (optimize && can_create_pseudo_p ()
1822 && register_operand (operands[0], VOIDmode)
1823 && GET_CODE (operands[1]) == MEM)
1825 rtx tmp = gen_reg_rtx (SImode);
1826 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1827 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1828 operands[1] = gen_lowpart (HImode, tmp);
1832 (define_insn "*movhi"
1833 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1834 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1846 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1847 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1848 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1849 (set_attr "z10prop" "z10_fr_E1,
1860 [(set (match_operand:HI 0 "register_operand" "")
1861 (mem:HI (match_operand 1 "address_operand" "")))]
1862 "GET_CODE (operands[1]) == SYMBOL_REF
1863 && CONSTANT_POOL_ADDRESS_P (operands[1])
1864 && get_pool_mode (operands[1]) == HImode
1865 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1866 [(set (match_dup 0) (match_dup 2))]
1867 "operands[2] = get_pool_constant (operands[1]);")
1870 ; movqi instruction pattern(s).
1873 (define_expand "movqi"
1874 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1875 (match_operand:QI 1 "general_operand" ""))]
1878 /* On z/Architecture, zero-extending from memory to register
1879 is just as fast as a QImode load. */
1880 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1881 && register_operand (operands[0], VOIDmode)
1882 && GET_CODE (operands[1]) == MEM)
1884 rtx tmp = gen_reg_rtx (DImode);
1885 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1886 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1887 operands[1] = gen_lowpart (QImode, tmp);
1891 (define_insn "*movqi"
1892 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1893 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1905 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1906 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1907 (set_attr "z10prop" "z10_fr_E1,
1918 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1919 (mem:QI (match_operand 1 "address_operand" "")))]
1920 "GET_CODE (operands[1]) == SYMBOL_REF
1921 && CONSTANT_POOL_ADDRESS_P (operands[1])
1922 && get_pool_mode (operands[1]) == QImode
1923 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1924 [(set (match_dup 0) (match_dup 2))]
1925 "operands[2] = get_pool_constant (operands[1]);")
1928 ; movstrictqi instruction pattern(s).
1931 (define_insn "*movstrictqi"
1932 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1933 (match_operand:QI 1 "memory_operand" "R,T"))]
1938 [(set_attr "op_type" "RX,RXY")
1939 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1942 ; movstricthi instruction pattern(s).
1945 (define_insn "*movstricthi"
1946 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1947 (match_operand:HI 1 "memory_operand" "Q,S"))
1948 (clobber (reg:CC CC_REGNUM))]
1953 [(set_attr "op_type" "RS,RSY")
1954 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1957 ; movstrictsi instruction pattern(s).
1960 (define_insn "movstrictsi"
1961 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1962 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1969 [(set_attr "op_type" "RR,RX,RXY,RRE")
1970 (set_attr "type" "lr,load,load,*")
1971 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1974 ; mov(tf|td) instruction pattern(s).
1977 (define_expand "mov<mode>"
1978 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1979 (match_operand:TD_TF 1 "general_operand" ""))]
1983 (define_insn "*mov<mode>_64"
1984 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1985 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1996 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1997 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
1998 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2000 (define_insn "*mov<mode>_31"
2001 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2002 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2009 [(set_attr "op_type" "RRE,RRE,*,*")
2010 (set_attr "type" "fsimptf,fsimptf,*,*")
2011 (set_attr "cpu_facility" "z196,*,*,*")])
2013 ; TFmode in GPRs splitters
2016 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2017 (match_operand:TD_TF 1 "general_operand" ""))]
2018 "TARGET_ZARCH && reload_completed
2019 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2020 [(set (match_dup 2) (match_dup 4))
2021 (set (match_dup 3) (match_dup 5))]
2023 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2024 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2025 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2026 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2030 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2031 (match_operand:TD_TF 1 "general_operand" ""))]
2032 "TARGET_ZARCH && reload_completed
2033 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2034 [(set (match_dup 2) (match_dup 4))
2035 (set (match_dup 3) (match_dup 5))]
2037 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2038 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2039 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2040 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2044 [(set (match_operand:TD_TF 0 "register_operand" "")
2045 (match_operand:TD_TF 1 "memory_operand" ""))]
2046 "TARGET_ZARCH && reload_completed
2047 && !FP_REG_P (operands[0])
2048 && !s_operand (operands[1], VOIDmode)"
2049 [(set (match_dup 0) (match_dup 1))]
2051 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2052 addr = gen_lowpart (Pmode, addr);
2053 s390_load_address (addr, XEXP (operands[1], 0));
2054 operands[1] = replace_equiv_address (operands[1], addr);
2057 ; TFmode in BFPs splitters
2060 [(set (match_operand:TD_TF 0 "register_operand" "")
2061 (match_operand:TD_TF 1 "memory_operand" ""))]
2062 "reload_completed && offsettable_memref_p (operands[1])
2063 && FP_REG_P (operands[0])"
2064 [(set (match_dup 2) (match_dup 4))
2065 (set (match_dup 3) (match_dup 5))]
2067 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2069 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2071 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2072 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2076 [(set (match_operand:TD_TF 0 "memory_operand" "")
2077 (match_operand:TD_TF 1 "register_operand" ""))]
2078 "reload_completed && offsettable_memref_p (operands[0])
2079 && FP_REG_P (operands[1])"
2080 [(set (match_dup 2) (match_dup 4))
2081 (set (match_dup 3) (match_dup 5))]
2083 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2084 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2085 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2087 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2092 ; mov(df|dd) instruction pattern(s).
2095 (define_expand "mov<mode>"
2096 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2097 (match_operand:DD_DF 1 "general_operand" ""))]
2101 (define_insn "*mov<mode>_64dfp"
2102 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2103 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2104 (match_operand:DD_DF 1 "general_operand"
2105 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2120 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2121 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2122 fstoredf,fstoredf,*,lr,load,store")
2123 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2124 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2126 (define_insn "*mov<mode>_64"
2127 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2128 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2141 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2142 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2143 fstore<mode>,fstore<mode>,*,lr,load,store")
2144 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2145 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2147 (define_insn "*mov<mode>_31"
2148 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2149 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2150 (match_operand:DD_DF 1 "general_operand"
2151 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2166 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2167 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2168 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2169 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2172 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2173 (match_operand:DD_DF 1 "general_operand" ""))]
2174 "!TARGET_ZARCH && reload_completed
2175 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2176 [(set (match_dup 2) (match_dup 4))
2177 (set (match_dup 3) (match_dup 5))]
2179 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2180 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2181 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2182 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2186 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2187 (match_operand:DD_DF 1 "general_operand" ""))]
2188 "!TARGET_ZARCH && reload_completed
2189 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2190 [(set (match_dup 2) (match_dup 4))
2191 (set (match_dup 3) (match_dup 5))]
2193 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2194 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2195 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2196 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2200 [(set (match_operand:DD_DF 0 "register_operand" "")
2201 (match_operand:DD_DF 1 "memory_operand" ""))]
2202 "!TARGET_ZARCH && reload_completed
2203 && !FP_REG_P (operands[0])
2204 && !s_operand (operands[1], VOIDmode)"
2205 [(set (match_dup 0) (match_dup 1))]
2207 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2208 s390_load_address (addr, XEXP (operands[1], 0));
2209 operands[1] = replace_equiv_address (operands[1], addr);
2213 ; mov(sf|sd) instruction pattern(s).
2216 (define_insn "mov<mode>"
2217 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2218 "=f,f,f,f,R,T,d,d,d,d,R,T")
2219 (match_operand:SD_SF 1 "general_operand"
2220 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2235 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2236 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2237 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2238 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2239 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2242 ; movcc instruction pattern
2245 (define_insn "movcc"
2246 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2247 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2257 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2258 (set_attr "type" "lr,*,*,store,store,load,load")
2259 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2260 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2263 ; Block move (MVC) patterns.
2267 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2268 (match_operand:BLK 1 "memory_operand" "Q"))
2269 (use (match_operand 2 "const_int_operand" "n"))]
2270 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2271 "mvc\t%O0(%2,%R0),%S1"
2272 [(set_attr "op_type" "SS")])
2274 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2275 ; order to have it implemented with mvc.
2278 [(set (match_operand:QI 0 "memory_operand" "")
2279 (match_operand:QI 1 "memory_operand" ""))]
2282 [(set (match_dup 0) (match_dup 1))
2283 (use (const_int 1))])]
2285 operands[0] = adjust_address (operands[0], BLKmode, 0);
2286 operands[1] = adjust_address (operands[1], BLKmode, 0);
2292 [(set (match_operand:BLK 0 "memory_operand" "")
2293 (match_operand:BLK 1 "memory_operand" ""))
2294 (use (match_operand 2 "const_int_operand" ""))])
2296 [(set (match_operand:BLK 3 "memory_operand" "")
2297 (match_operand:BLK 4 "memory_operand" ""))
2298 (use (match_operand 5 "const_int_operand" ""))])]
2299 "s390_offset_p (operands[0], operands[3], operands[2])
2300 && s390_offset_p (operands[1], operands[4], operands[2])
2301 && !s390_overlap_p (operands[0], operands[1],
2302 INTVAL (operands[2]) + INTVAL (operands[5]))
2303 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2305 [(set (match_dup 6) (match_dup 7))
2306 (use (match_dup 8))])]
2307 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2308 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2309 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2313 ; load_multiple pattern(s).
2315 ; ??? Due to reload problems with replacing registers inside match_parallel
2316 ; we currently support load_multiple/store_multiple only after reload.
2319 (define_expand "load_multiple"
2320 [(match_par_dup 3 [(set (match_operand 0 "" "")
2321 (match_operand 1 "" ""))
2322 (use (match_operand 2 "" ""))])]
2325 enum machine_mode mode;
2331 /* Support only loading a constant number of fixed-point registers from
2332 memory and only bother with this if more than two */
2333 if (GET_CODE (operands[2]) != CONST_INT
2334 || INTVAL (operands[2]) < 2
2335 || INTVAL (operands[2]) > 16
2336 || GET_CODE (operands[1]) != MEM
2337 || GET_CODE (operands[0]) != REG
2338 || REGNO (operands[0]) >= 16)
2341 count = INTVAL (operands[2]);
2342 regno = REGNO (operands[0]);
2343 mode = GET_MODE (operands[0]);
2344 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2347 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2348 if (!can_create_pseudo_p ())
2350 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2352 from = XEXP (operands[1], 0);
2355 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2356 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2357 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2359 from = XEXP (XEXP (operands[1], 0), 0);
2360 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2367 from = force_reg (Pmode, XEXP (operands[1], 0));
2371 for (i = 0; i < count; i++)
2372 XVECEXP (operands[3], 0, i)
2373 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2374 change_address (operands[1], mode,
2375 plus_constant (Pmode, from,
2376 off + i * GET_MODE_SIZE (mode))));
2379 (define_insn "*load_multiple_di"
2380 [(match_parallel 0 "load_multiple_operation"
2381 [(set (match_operand:DI 1 "register_operand" "=r")
2382 (match_operand:DI 2 "s_operand" "QS"))])]
2383 "reload_completed && TARGET_ZARCH"
2385 int words = XVECLEN (operands[0], 0);
2386 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2387 return "lmg\t%1,%0,%S2";
2389 [(set_attr "op_type" "RSY")
2390 (set_attr "type" "lm")])
2392 (define_insn "*load_multiple_si"
2393 [(match_parallel 0 "load_multiple_operation"
2394 [(set (match_operand:SI 1 "register_operand" "=r,r")
2395 (match_operand:SI 2 "s_operand" "Q,S"))])]
2398 int words = XVECLEN (operands[0], 0);
2399 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2400 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2402 [(set_attr "op_type" "RS,RSY")
2403 (set_attr "type" "lm")])
2406 ; store multiple pattern(s).
2409 (define_expand "store_multiple"
2410 [(match_par_dup 3 [(set (match_operand 0 "" "")
2411 (match_operand 1 "" ""))
2412 (use (match_operand 2 "" ""))])]
2415 enum machine_mode mode;
2421 /* Support only storing a constant number of fixed-point registers to
2422 memory and only bother with this if more than two. */
2423 if (GET_CODE (operands[2]) != CONST_INT
2424 || INTVAL (operands[2]) < 2
2425 || INTVAL (operands[2]) > 16
2426 || GET_CODE (operands[0]) != MEM
2427 || GET_CODE (operands[1]) != REG
2428 || REGNO (operands[1]) >= 16)
2431 count = INTVAL (operands[2]);
2432 regno = REGNO (operands[1]);
2433 mode = GET_MODE (operands[1]);
2434 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2437 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2439 if (!can_create_pseudo_p ())
2441 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2443 to = XEXP (operands[0], 0);
2446 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2447 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2448 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2450 to = XEXP (XEXP (operands[0], 0), 0);
2451 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2458 to = force_reg (Pmode, XEXP (operands[0], 0));
2462 for (i = 0; i < count; i++)
2463 XVECEXP (operands[3], 0, i)
2464 = gen_rtx_SET (VOIDmode,
2465 change_address (operands[0], mode,
2466 plus_constant (Pmode, to,
2467 off + i * GET_MODE_SIZE (mode))),
2468 gen_rtx_REG (mode, regno + i));
2471 (define_insn "*store_multiple_di"
2472 [(match_parallel 0 "store_multiple_operation"
2473 [(set (match_operand:DI 1 "s_operand" "=QS")
2474 (match_operand:DI 2 "register_operand" "r"))])]
2475 "reload_completed && TARGET_ZARCH"
2477 int words = XVECLEN (operands[0], 0);
2478 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2479 return "stmg\t%2,%0,%S1";
2481 [(set_attr "op_type" "RSY")
2482 (set_attr "type" "stm")])
2485 (define_insn "*store_multiple_si"
2486 [(match_parallel 0 "store_multiple_operation"
2487 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2488 (match_operand:SI 2 "register_operand" "r,r"))])]
2491 int words = XVECLEN (operands[0], 0);
2492 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2493 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2495 [(set_attr "op_type" "RS,RSY")
2496 (set_attr "type" "stm")])
2499 ;; String instructions.
2502 (define_insn "*execute_rl"
2503 [(match_parallel 0 "execute_operation"
2504 [(unspec [(match_operand 1 "register_operand" "a")
2505 (match_operand 2 "" "")
2506 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2507 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2508 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2510 [(set_attr "op_type" "RIL")
2511 (set_attr "type" "cs")])
2513 (define_insn "*execute"
2514 [(match_parallel 0 "execute_operation"
2515 [(unspec [(match_operand 1 "register_operand" "a")
2516 (match_operand:BLK 2 "memory_operand" "R")
2517 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2518 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2519 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2521 [(set_attr "op_type" "RX")
2522 (set_attr "type" "cs")])
2526 ; strlenM instruction pattern(s).
2529 (define_expand "strlen<mode>"
2530 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2533 (unspec:P [(const_int 0)
2534 (match_operand:BLK 1 "memory_operand" "")
2536 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2537 (clobber (scratch:P))
2538 (clobber (reg:CC CC_REGNUM))])
2540 [(set (match_operand:P 0 "register_operand" "")
2541 (minus:P (match_dup 4) (match_dup 5)))
2542 (clobber (reg:CC CC_REGNUM))])]
2545 operands[4] = gen_reg_rtx (Pmode);
2546 operands[5] = gen_reg_rtx (Pmode);
2547 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2548 operands[1] = replace_equiv_address (operands[1], operands[5]);
2551 (define_insn "*strlen<mode>"
2552 [(set (match_operand:P 0 "register_operand" "=a")
2553 (unspec:P [(match_operand:P 2 "general_operand" "0")
2554 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2556 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2557 (clobber (match_scratch:P 1 "=a"))
2558 (clobber (reg:CC CC_REGNUM))]
2560 "srst\t%0,%1\;jo\t.-4"
2561 [(set_attr "length" "8")
2562 (set_attr "type" "vs")])
2565 ; cmpstrM instruction pattern(s).
2568 (define_expand "cmpstrsi"
2569 [(set (reg:SI 0) (const_int 0))
2571 [(clobber (match_operand 3 "" ""))
2572 (clobber (match_dup 4))
2573 (set (reg:CCU CC_REGNUM)
2574 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2575 (match_operand:BLK 2 "memory_operand" "")))
2578 [(set (match_operand:SI 0 "register_operand" "=d")
2579 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2580 (clobber (reg:CC CC_REGNUM))])]
2583 /* As the result of CMPINT is inverted compared to what we need,
2584 we have to swap the operands. */
2585 rtx op1 = operands[2];
2586 rtx op2 = operands[1];
2587 rtx addr1 = gen_reg_rtx (Pmode);
2588 rtx addr2 = gen_reg_rtx (Pmode);
2590 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2591 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2592 operands[1] = replace_equiv_address_nv (op1, addr1);
2593 operands[2] = replace_equiv_address_nv (op2, addr2);
2594 operands[3] = addr1;
2595 operands[4] = addr2;
2598 (define_insn "*cmpstr<mode>"
2599 [(clobber (match_operand:P 0 "register_operand" "=d"))
2600 (clobber (match_operand:P 1 "register_operand" "=d"))
2601 (set (reg:CCU CC_REGNUM)
2602 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2603 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2606 "clst\t%0,%1\;jo\t.-4"
2607 [(set_attr "length" "8")
2608 (set_attr "type" "vs")])
2611 ; movstr instruction pattern.
2614 (define_expand "movstr"
2615 [(set (reg:SI 0) (const_int 0))
2617 [(clobber (match_dup 3))
2618 (set (match_operand:BLK 1 "memory_operand" "")
2619 (match_operand:BLK 2 "memory_operand" ""))
2620 (set (match_operand 0 "register_operand" "")
2621 (unspec [(match_dup 1)
2623 (reg:SI 0)] UNSPEC_MVST))
2624 (clobber (reg:CC CC_REGNUM))])]
2627 rtx addr1 = gen_reg_rtx (Pmode);
2628 rtx addr2 = gen_reg_rtx (Pmode);
2630 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2631 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2632 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2633 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2634 operands[3] = addr2;
2637 (define_insn "*movstr"
2638 [(clobber (match_operand:P 2 "register_operand" "=d"))
2639 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2640 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2641 (set (match_operand:P 0 "register_operand" "=d")
2642 (unspec [(mem:BLK (match_dup 1))
2643 (mem:BLK (match_dup 3))
2644 (reg:SI 0)] UNSPEC_MVST))
2645 (clobber (reg:CC CC_REGNUM))]
2647 "mvst\t%1,%2\;jo\t.-4"
2648 [(set_attr "length" "8")
2649 (set_attr "type" "vs")])
2653 ; movmemM instruction pattern(s).
2656 (define_expand "movmem<mode>"
2657 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2658 (match_operand:BLK 1 "memory_operand" "")) ; source
2659 (use (match_operand:GPR 2 "general_operand" "")) ; count
2660 (match_operand 3 "" "")]
2663 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2669 ; Move a block that is up to 256 bytes in length.
2670 ; The block length is taken as (operands[2] % 256) + 1.
2672 (define_expand "movmem_short"
2674 [(set (match_operand:BLK 0 "memory_operand" "")
2675 (match_operand:BLK 1 "memory_operand" ""))
2676 (use (match_operand 2 "nonmemory_operand" ""))
2677 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2678 (clobber (match_dup 3))])]
2680 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2682 (define_insn "*movmem_short"
2683 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2684 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2685 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2686 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2687 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2688 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2690 [(set_attr "type" "cs")
2691 (set_attr "cpu_facility" "*,*,z10,*")])
2694 [(set (match_operand:BLK 0 "memory_operand" "")
2695 (match_operand:BLK 1 "memory_operand" ""))
2696 (use (match_operand 2 "const_int_operand" ""))
2697 (use (match_operand 3 "immediate_operand" ""))
2698 (clobber (scratch))]
2701 [(set (match_dup 0) (match_dup 1))
2702 (use (match_dup 2))])]
2703 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2706 [(set (match_operand:BLK 0 "memory_operand" "")
2707 (match_operand:BLK 1 "memory_operand" ""))
2708 (use (match_operand 2 "register_operand" ""))
2709 (use (match_operand 3 "memory_operand" ""))
2710 (clobber (scratch))]
2713 [(unspec [(match_dup 2) (match_dup 3)
2714 (const_int 0)] UNSPEC_EXECUTE)
2715 (set (match_dup 0) (match_dup 1))
2716 (use (const_int 1))])]
2720 [(set (match_operand:BLK 0 "memory_operand" "")
2721 (match_operand:BLK 1 "memory_operand" ""))
2722 (use (match_operand 2 "register_operand" ""))
2723 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2724 (clobber (scratch))]
2725 "TARGET_Z10 && reload_completed"
2727 [(unspec [(match_dup 2) (const_int 0)
2728 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2729 (set (match_dup 0) (match_dup 1))
2730 (use (const_int 1))])]
2731 "operands[3] = gen_label_rtx ();")
2734 [(set (match_operand:BLK 0 "memory_operand" "")
2735 (match_operand:BLK 1 "memory_operand" ""))
2736 (use (match_operand 2 "register_operand" ""))
2737 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2738 (clobber (match_operand 3 "register_operand" ""))]
2739 "reload_completed && TARGET_CPU_ZARCH"
2740 [(set (match_dup 3) (label_ref (match_dup 4)))
2742 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2743 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2744 (set (match_dup 0) (match_dup 1))
2745 (use (const_int 1))])]
2746 "operands[4] = gen_label_rtx ();")
2748 ; Move a block of arbitrary length.
2750 (define_expand "movmem_long"
2752 [(clobber (match_dup 2))
2753 (clobber (match_dup 3))
2754 (set (match_operand:BLK 0 "memory_operand" "")
2755 (match_operand:BLK 1 "memory_operand" ""))
2756 (use (match_operand 2 "general_operand" ""))
2758 (clobber (reg:CC CC_REGNUM))])]
2761 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2762 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2763 rtx reg0 = gen_reg_rtx (dreg_mode);
2764 rtx reg1 = gen_reg_rtx (dreg_mode);
2765 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2766 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2767 rtx len0 = gen_lowpart (Pmode, reg0);
2768 rtx len1 = gen_lowpart (Pmode, reg1);
2770 emit_clobber (reg0);
2771 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2772 emit_move_insn (len0, operands[2]);
2774 emit_clobber (reg1);
2775 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2776 emit_move_insn (len1, operands[2]);
2778 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2779 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2784 (define_insn "*movmem_long"
2785 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2786 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2787 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2788 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2791 (clobber (reg:CC CC_REGNUM))]
2792 "TARGET_64BIT || !TARGET_ZARCH"
2793 "mvcle\t%0,%1,0\;jo\t.-4"
2794 [(set_attr "length" "8")
2795 (set_attr "type" "vs")])
2797 (define_insn "*movmem_long_31z"
2798 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2799 (clobber (match_operand:TI 1 "register_operand" "=d"))
2800 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2801 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2804 (clobber (reg:CC CC_REGNUM))]
2805 "!TARGET_64BIT && TARGET_ZARCH"
2806 "mvcle\t%0,%1,0\;jo\t.-4"
2807 [(set_attr "length" "8")
2808 (set_attr "type" "vs")])
2815 (define_expand "signbit<mode>2"
2816 [(set (reg:CCZ CC_REGNUM)
2817 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2820 (set (match_operand:SI 0 "register_operand" "=d")
2821 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2824 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2827 (define_expand "isinf<mode>2"
2828 [(set (reg:CCZ CC_REGNUM)
2829 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2832 (set (match_operand:SI 0 "register_operand" "=d")
2833 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2836 operands[2] = GEN_INT (S390_TDC_INFINITY);
2839 ; This insn is used to generate all variants of the Test Data Class
2840 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2841 ; is the register to be tested and the second one is the bit mask
2842 ; specifying the required test(s).
2844 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2845 (define_insn "*TDC_insn_<mode>"
2846 [(set (reg:CCZ CC_REGNUM)
2847 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2848 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2850 "t<_d>c<xde><bt>\t%0,%1"
2851 [(set_attr "op_type" "RXE")
2852 (set_attr "type" "fsimp<mode>")])
2854 (define_insn_and_split "*ccz_to_int"
2855 [(set (match_operand:SI 0 "register_operand" "=d")
2856 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2857 UNSPEC_CCZ_TO_INT))]
2861 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2865 ; setmemM instruction pattern(s).
2868 (define_expand "setmem<mode>"
2869 [(set (match_operand:BLK 0 "memory_operand" "")
2870 (match_operand:QI 2 "general_operand" ""))
2871 (use (match_operand:GPR 1 "general_operand" ""))
2872 (match_operand 3 "" "")]
2874 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2876 ; Clear a block that is up to 256 bytes in length.
2877 ; The block length is taken as (operands[1] % 256) + 1.
2879 (define_expand "clrmem_short"
2881 [(set (match_operand:BLK 0 "memory_operand" "")
2883 (use (match_operand 1 "nonmemory_operand" ""))
2884 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2885 (clobber (match_dup 2))
2886 (clobber (reg:CC CC_REGNUM))])]
2888 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2890 (define_insn "*clrmem_short"
2891 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2893 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2894 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2895 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2896 (clobber (reg:CC CC_REGNUM))]
2897 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2899 [(set_attr "type" "cs")
2900 (set_attr "cpu_facility" "*,*,z10,*")])
2903 [(set (match_operand:BLK 0 "memory_operand" "")
2905 (use (match_operand 1 "const_int_operand" ""))
2906 (use (match_operand 2 "immediate_operand" ""))
2908 (clobber (reg:CC CC_REGNUM))]
2911 [(set (match_dup 0) (const_int 0))
2913 (clobber (reg:CC CC_REGNUM))])]
2914 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2917 [(set (match_operand:BLK 0 "memory_operand" "")
2919 (use (match_operand 1 "register_operand" ""))
2920 (use (match_operand 2 "memory_operand" ""))
2922 (clobber (reg:CC CC_REGNUM))]
2925 [(unspec [(match_dup 1) (match_dup 2)
2926 (const_int 0)] UNSPEC_EXECUTE)
2927 (set (match_dup 0) (const_int 0))
2929 (clobber (reg:CC CC_REGNUM))])]
2933 [(set (match_operand:BLK 0 "memory_operand" "")
2935 (use (match_operand 1 "register_operand" ""))
2936 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2938 (clobber (reg:CC CC_REGNUM))]
2939 "TARGET_Z10 && reload_completed"
2941 [(unspec [(match_dup 1) (const_int 0)
2942 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2943 (set (match_dup 0) (const_int 0))
2945 (clobber (reg:CC CC_REGNUM))])]
2946 "operands[3] = gen_label_rtx ();")
2949 [(set (match_operand:BLK 0 "memory_operand" "")
2951 (use (match_operand 1 "register_operand" ""))
2952 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2953 (clobber (match_operand 2 "register_operand" ""))
2954 (clobber (reg:CC CC_REGNUM))]
2955 "reload_completed && TARGET_CPU_ZARCH"
2956 [(set (match_dup 2) (label_ref (match_dup 3)))
2958 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2959 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2960 (set (match_dup 0) (const_int 0))
2962 (clobber (reg:CC CC_REGNUM))])]
2963 "operands[3] = gen_label_rtx ();")
2965 ; Initialize a block of arbitrary length with (operands[2] % 256).
2967 (define_expand "setmem_long"
2969 [(clobber (match_dup 1))
2970 (set (match_operand:BLK 0 "memory_operand" "")
2971 (match_operand 2 "shift_count_or_setmem_operand" ""))
2972 (use (match_operand 1 "general_operand" ""))
2974 (clobber (reg:CC CC_REGNUM))])]
2977 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2978 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2979 rtx reg0 = gen_reg_rtx (dreg_mode);
2980 rtx reg1 = gen_reg_rtx (dreg_mode);
2981 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2982 rtx len0 = gen_lowpart (Pmode, reg0);
2984 emit_clobber (reg0);
2985 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2986 emit_move_insn (len0, operands[1]);
2988 emit_move_insn (reg1, const0_rtx);
2990 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2995 (define_insn "*setmem_long"
2996 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2997 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2998 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3000 (use (match_operand:<DBL> 1 "register_operand" "d"))
3001 (clobber (reg:CC CC_REGNUM))]
3002 "TARGET_64BIT || !TARGET_ZARCH"
3003 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3004 [(set_attr "length" "8")
3005 (set_attr "type" "vs")])
3007 (define_insn "*setmem_long_and"
3008 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3009 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3010 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3011 (match_operand 4 "const_int_operand" "n")))
3013 (use (match_operand:<DBL> 1 "register_operand" "d"))
3014 (clobber (reg:CC CC_REGNUM))]
3015 "(TARGET_64BIT || !TARGET_ZARCH) &&
3016 (INTVAL (operands[4]) & 255) == 255"
3017 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3018 [(set_attr "length" "8")
3019 (set_attr "type" "vs")])
3021 (define_insn "*setmem_long_31z"
3022 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3023 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3024 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3026 (use (match_operand:TI 1 "register_operand" "d"))
3027 (clobber (reg:CC CC_REGNUM))]
3028 "!TARGET_64BIT && TARGET_ZARCH"
3029 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3030 [(set_attr "length" "8")
3031 (set_attr "type" "vs")])
3034 ; cmpmemM instruction pattern(s).
3037 (define_expand "cmpmemsi"
3038 [(set (match_operand:SI 0 "register_operand" "")
3039 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3040 (match_operand:BLK 2 "memory_operand" "") ) )
3041 (use (match_operand:SI 3 "general_operand" ""))
3042 (use (match_operand:SI 4 "" ""))]
3045 if (s390_expand_cmpmem (operands[0], operands[1],
3046 operands[2], operands[3]))
3052 ; Compare a block that is up to 256 bytes in length.
3053 ; The block length is taken as (operands[2] % 256) + 1.
3055 (define_expand "cmpmem_short"
3057 [(set (reg:CCU CC_REGNUM)
3058 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3059 (match_operand:BLK 1 "memory_operand" "")))
3060 (use (match_operand 2 "nonmemory_operand" ""))
3061 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3062 (clobber (match_dup 3))])]
3064 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3066 (define_insn "*cmpmem_short"
3067 [(set (reg:CCU CC_REGNUM)
3068 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3069 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3070 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3071 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3072 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3073 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3075 [(set_attr "type" "cs")
3076 (set_attr "cpu_facility" "*,*,z10,*")])
3079 [(set (reg:CCU CC_REGNUM)
3080 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3081 (match_operand:BLK 1 "memory_operand" "")))
3082 (use (match_operand 2 "const_int_operand" ""))
3083 (use (match_operand 3 "immediate_operand" ""))
3084 (clobber (scratch))]
3087 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3088 (use (match_dup 2))])]
3089 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3092 [(set (reg:CCU CC_REGNUM)
3093 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3094 (match_operand:BLK 1 "memory_operand" "")))
3095 (use (match_operand 2 "register_operand" ""))
3096 (use (match_operand 3 "memory_operand" ""))
3097 (clobber (scratch))]
3100 [(unspec [(match_dup 2) (match_dup 3)
3101 (const_int 0)] UNSPEC_EXECUTE)
3102 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3103 (use (const_int 1))])]
3107 [(set (reg:CCU CC_REGNUM)
3108 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3109 (match_operand:BLK 1 "memory_operand" "")))
3110 (use (match_operand 2 "register_operand" ""))
3111 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3112 (clobber (scratch))]
3113 "TARGET_Z10 && reload_completed"
3115 [(unspec [(match_dup 2) (const_int 0)
3116 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3117 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3118 (use (const_int 1))])]
3119 "operands[4] = gen_label_rtx ();")
3122 [(set (reg:CCU CC_REGNUM)
3123 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3124 (match_operand:BLK 1 "memory_operand" "")))
3125 (use (match_operand 2 "register_operand" ""))
3126 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3127 (clobber (match_operand 3 "register_operand" ""))]
3128 "reload_completed && TARGET_CPU_ZARCH"
3129 [(set (match_dup 3) (label_ref (match_dup 4)))
3131 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3132 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3133 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3134 (use (const_int 1))])]
3135 "operands[4] = gen_label_rtx ();")
3137 ; Compare a block of arbitrary length.
3139 (define_expand "cmpmem_long"
3141 [(clobber (match_dup 2))
3142 (clobber (match_dup 3))
3143 (set (reg:CCU CC_REGNUM)
3144 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3145 (match_operand:BLK 1 "memory_operand" "")))
3146 (use (match_operand 2 "general_operand" ""))
3147 (use (match_dup 3))])]
3150 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3151 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3152 rtx reg0 = gen_reg_rtx (dreg_mode);
3153 rtx reg1 = gen_reg_rtx (dreg_mode);
3154 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3155 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3156 rtx len0 = gen_lowpart (Pmode, reg0);
3157 rtx len1 = gen_lowpart (Pmode, reg1);
3159 emit_clobber (reg0);
3160 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3161 emit_move_insn (len0, operands[2]);
3163 emit_clobber (reg1);
3164 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3165 emit_move_insn (len1, operands[2]);
3167 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3168 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3173 (define_insn "*cmpmem_long"
3174 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3175 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3176 (set (reg:CCU CC_REGNUM)
3177 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3178 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3180 (use (match_dup 3))]
3181 "TARGET_64BIT || !TARGET_ZARCH"
3182 "clcle\t%0,%1,0\;jo\t.-4"
3183 [(set_attr "length" "8")
3184 (set_attr "type" "vs")])
3186 (define_insn "*cmpmem_long_31z"
3187 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3188 (clobber (match_operand:TI 1 "register_operand" "=d"))
3189 (set (reg:CCU CC_REGNUM)
3190 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3191 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3193 (use (match_dup 3))]
3194 "!TARGET_64BIT && TARGET_ZARCH"
3195 "clcle\t%0,%1,0\;jo\t.-4"
3196 [(set_attr "op_type" "NN")
3197 (set_attr "type" "vs")
3198 (set_attr "length" "8")])
3200 ; Convert CCUmode condition code to integer.
3201 ; Result is zero if EQ, positive if LTU, negative if GTU.
3203 (define_insn_and_split "cmpint"
3204 [(set (match_operand:SI 0 "register_operand" "=d")
3205 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3207 (clobber (reg:CC CC_REGNUM))]
3211 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3213 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3214 (clobber (reg:CC CC_REGNUM))])])
3216 (define_insn_and_split "*cmpint_cc"
3217 [(set (reg CC_REGNUM)
3218 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3221 (set (match_operand:SI 0 "register_operand" "=d")
3222 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3223 "s390_match_ccmode (insn, CCSmode)"
3225 "&& reload_completed"
3226 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3228 [(set (match_dup 2) (match_dup 3))
3229 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3231 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3232 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3233 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3236 (define_insn_and_split "*cmpint_sign"
3237 [(set (match_operand:DI 0 "register_operand" "=d")
3238 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3239 UNSPEC_CCU_TO_INT)))
3240 (clobber (reg:CC CC_REGNUM))]
3243 "&& reload_completed"
3244 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3246 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3247 (clobber (reg:CC CC_REGNUM))])])
3249 (define_insn_and_split "*cmpint_sign_cc"
3250 [(set (reg CC_REGNUM)
3251 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3252 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3253 UNSPEC_CCU_TO_INT) 0)
3254 (const_int 32)) (const_int 32))
3256 (set (match_operand:DI 0 "register_operand" "=d")
3257 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3258 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3260 "&& reload_completed"
3261 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3263 [(set (match_dup 2) (match_dup 3))
3264 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3266 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3267 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3268 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3273 ;;- Conversion instructions.
3276 (define_insn "*sethighpartsi"
3277 [(set (match_operand:SI 0 "register_operand" "=d,d")
3278 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3279 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3280 (clobber (reg:CC CC_REGNUM))]
3285 [(set_attr "op_type" "RS,RSY")
3286 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3288 (define_insn "*sethighpartdi_64"
3289 [(set (match_operand:DI 0 "register_operand" "=d")
3290 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3291 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3292 (clobber (reg:CC CC_REGNUM))]
3295 [(set_attr "op_type" "RSY")
3296 (set_attr "z10prop" "z10_super")])
3298 (define_insn "*sethighpartdi_31"
3299 [(set (match_operand:DI 0 "register_operand" "=d,d")
3300 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3301 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3302 (clobber (reg:CC CC_REGNUM))]
3307 [(set_attr "op_type" "RS,RSY")
3308 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3311 (define_insn_and_split "*extzv<mode>"
3312 [(set (match_operand:GPR 0 "register_operand" "=d")
3313 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3314 (match_operand 2 "const_int_operand" "n")
3316 (clobber (reg:CC CC_REGNUM))]
3317 "INTVAL (operands[2]) > 0
3318 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3320 "&& reload_completed"
3322 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3323 (clobber (reg:CC CC_REGNUM))])
3324 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3326 int bitsize = INTVAL (operands[2]);
3327 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3328 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3330 operands[1] = adjust_address (operands[1], BLKmode, 0);
3331 set_mem_size (operands[1], size);
3332 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3333 operands[3] = GEN_INT (mask);
3336 (define_insn_and_split "*extv<mode>"
3337 [(set (match_operand:GPR 0 "register_operand" "=d")
3338 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3339 (match_operand 2 "const_int_operand" "n")
3341 (clobber (reg:CC CC_REGNUM))]
3342 "INTVAL (operands[2]) > 0
3343 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3345 "&& reload_completed"
3347 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3348 (clobber (reg:CC CC_REGNUM))])
3350 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3351 (clobber (reg:CC CC_REGNUM))])]
3353 int bitsize = INTVAL (operands[2]);
3354 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3355 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3357 operands[1] = adjust_address (operands[1], BLKmode, 0);
3358 set_mem_size (operands[1], size);
3359 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3360 operands[3] = GEN_INT (mask);
3364 ; insv instruction patterns
3367 (define_expand "insv"
3368 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3369 (match_operand 1 "const_int_operand" "")
3370 (match_operand 2 "const_int_operand" ""))
3371 (match_operand 3 "general_operand" ""))]
3374 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3380 ; The normal RTL expansion will never generate a zero_extract where
3381 ; the location operand isn't word mode. However, we do this in the
3382 ; back-end when generating atomic operations. See s390_two_part_insv.
3383 (define_insn "*insv<mode>_zEC12"
3384 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3385 (match_operand 1 "const_int_operand" "I") ; size
3386 (match_operand 2 "const_int_operand" "I")) ; pos
3387 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3389 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3390 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3391 [(set_attr "op_type" "RIE")])
3393 (define_insn "*insv<mode>_z10"
3394 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3395 (match_operand 1 "const_int_operand" "I") ; size
3396 (match_operand 2 "const_int_operand" "I")) ; pos
3397 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3398 (clobber (reg:CC CC_REGNUM))]
3400 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3401 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3402 [(set_attr "op_type" "RIE")
3403 (set_attr "z10prop" "z10_super_E1")])
3405 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3406 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3407 (define_insn "*insv<mode>_zEC12_noshift"
3408 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3409 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3410 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3411 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3412 (match_operand:GPR 4 "const_int_operand" ""))))]
3413 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3414 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3415 [(set_attr "op_type" "RIE")])
3417 (define_insn "*insv<mode>_z10_noshift"
3418 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3419 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3420 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3421 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3422 (match_operand:GPR 4 "const_int_operand" ""))))
3423 (clobber (reg:CC CC_REGNUM))]
3424 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3425 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3426 [(set_attr "op_type" "RIE")
3427 (set_attr "z10prop" "z10_super_E1")])
3429 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3430 (define_insn "*insv<mode>_or_z10_noshift"
3431 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3432 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3433 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3434 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3435 (clobber (reg:CC CC_REGNUM))]
3437 "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3438 [(set_attr "op_type" "RIE")])
3440 (define_insn "*insv<mode>_mem_reg"
3441 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3442 (match_operand 1 "const_int_operand" "n,n")
3444 (match_operand:W 2 "register_operand" "d,d"))]
3445 "INTVAL (operands[1]) > 0
3446 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3447 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3449 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3451 operands[1] = GEN_INT ((1ul << size) - 1);
3452 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3453 : "stcmy\t%2,%1,%S0";
3455 [(set_attr "op_type" "RS,RSY")
3456 (set_attr "z10prop" "z10_super,z10_super")])
3458 (define_insn "*insvdi_mem_reghigh"
3459 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3460 (match_operand 1 "const_int_operand" "n")
3462 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3465 && INTVAL (operands[1]) > 0
3466 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3467 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3469 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3471 operands[1] = GEN_INT ((1ul << size) - 1);
3472 return "stcmh\t%2,%1,%S0";
3474 [(set_attr "op_type" "RSY")
3475 (set_attr "z10prop" "z10_super")])
3477 (define_insn "*insvdi_reg_imm"
3478 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3480 (match_operand 1 "const_int_operand" "n"))
3481 (match_operand:DI 2 "const_int_operand" "n"))]
3483 && INTVAL (operands[1]) >= 0
3484 && INTVAL (operands[1]) < BITS_PER_WORD
3485 && INTVAL (operands[1]) % 16 == 0"
3487 switch (BITS_PER_WORD - INTVAL (operands[1]))
3489 case 64: return "iihh\t%0,%x2"; break;
3490 case 48: return "iihl\t%0,%x2"; break;
3491 case 32: return "iilh\t%0,%x2"; break;
3492 case 16: return "iill\t%0,%x2"; break;
3493 default: gcc_unreachable();
3496 [(set_attr "op_type" "RI")
3497 (set_attr "z10prop" "z10_super_E1")])
3499 ; Update the left-most 32 bit of a DI.
3500 (define_insn "*insv_h_di_reg_extimm"
3501 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3504 (match_operand:DI 1 "const_int_operand" "n"))]
3507 [(set_attr "op_type" "RIL")
3508 (set_attr "z10prop" "z10_fwd_E1")])
3510 ; Update the right-most 32 bit of a DI.
3511 (define_insn "*insv_l_di_reg_extimm"
3512 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3515 (match_operand:DI 1 "const_int_operand" "n"))]
3518 [(set_attr "op_type" "RIL")
3519 (set_attr "z10prop" "z10_fwd_A1")])
3522 ; extendsidi2 instruction pattern(s).
3525 (define_expand "extendsidi2"
3526 [(set (match_operand:DI 0 "register_operand" "")
3527 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3532 emit_clobber (operands[0]);
3533 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3534 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3535 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3540 (define_insn "*extendsidi2"
3541 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3542 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3548 [(set_attr "op_type" "RRE,RXY,RIL")
3549 (set_attr "type" "*,*,larl")
3550 (set_attr "cpu_facility" "*,*,z10")
3551 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3554 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3557 (define_expand "extend<HQI:mode><DSI:mode>2"
3558 [(set (match_operand:DSI 0 "register_operand" "")
3559 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3562 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3564 rtx tmp = gen_reg_rtx (SImode);
3565 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3566 emit_insn (gen_extendsidi2 (operands[0], tmp));
3569 else if (!TARGET_EXTIMM)
3571 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3573 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3574 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3575 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3581 ; extendhidi2 instruction pattern(s).
3584 (define_insn "*extendhidi2_extimm"
3585 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3586 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3587 "TARGET_ZARCH && TARGET_EXTIMM"
3592 [(set_attr "op_type" "RRE,RXY,RIL")
3593 (set_attr "type" "*,*,larl")
3594 (set_attr "cpu_facility" "extimm,extimm,z10")
3595 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3597 (define_insn "*extendhidi2"
3598 [(set (match_operand:DI 0 "register_operand" "=d")
3599 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3602 [(set_attr "op_type" "RXY")
3603 (set_attr "z10prop" "z10_super_E1")])
3606 ; extendhisi2 instruction pattern(s).
3609 (define_insn "*extendhisi2_extimm"
3610 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3611 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3618 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3619 (set_attr "type" "*,*,*,larl")
3620 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3621 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3623 (define_insn "*extendhisi2"
3624 [(set (match_operand:SI 0 "register_operand" "=d,d")
3625 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3630 [(set_attr "op_type" "RX,RXY")
3631 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3634 ; extendqi(si|di)2 instruction pattern(s).
3637 ; lbr, lgbr, lb, lgb
3638 (define_insn "*extendqi<mode>2_extimm"
3639 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3640 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3645 [(set_attr "op_type" "RRE,RXY")
3646 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3649 (define_insn "*extendqi<mode>2"
3650 [(set (match_operand:GPR 0 "register_operand" "=d")
3651 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3652 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3654 [(set_attr "op_type" "RXY")
3655 (set_attr "z10prop" "z10_super_E1")])
3657 (define_insn_and_split "*extendqi<mode>2_short_displ"
3658 [(set (match_operand:GPR 0 "register_operand" "=d")
3659 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3660 (clobber (reg:CC CC_REGNUM))]
3661 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3663 "&& reload_completed"
3665 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3666 (clobber (reg:CC CC_REGNUM))])
3668 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3669 (clobber (reg:CC CC_REGNUM))])]
3671 operands[1] = adjust_address (operands[1], BLKmode, 0);
3672 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3673 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3677 ; zero_extendsidi2 instruction pattern(s).
3680 (define_expand "zero_extendsidi2"
3681 [(set (match_operand:DI 0 "register_operand" "")
3682 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3687 emit_clobber (operands[0]);
3688 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3689 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3694 (define_insn "*zero_extendsidi2"
3695 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3696 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3702 [(set_attr "op_type" "RRE,RXY,RIL")
3703 (set_attr "type" "*,*,larl")
3704 (set_attr "cpu_facility" "*,*,z10")
3705 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3708 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3711 (define_insn "*llgt_sidi"
3712 [(set (match_operand:DI 0 "register_operand" "=d")
3713 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3714 (const_int 2147483647)))]
3717 [(set_attr "op_type" "RXE")
3718 (set_attr "z10prop" "z10_super_E1")])
3720 (define_insn_and_split "*llgt_sidi_split"
3721 [(set (match_operand:DI 0 "register_operand" "=d")
3722 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3723 (const_int 2147483647)))
3724 (clobber (reg:CC CC_REGNUM))]
3727 "&& reload_completed"
3729 (and:DI (subreg:DI (match_dup 1) 0)
3730 (const_int 2147483647)))]
3733 (define_insn "*llgt_sisi"
3734 [(set (match_operand:SI 0 "register_operand" "=d,d")
3735 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3736 (const_int 2147483647)))]
3741 [(set_attr "op_type" "RRE,RXE")
3742 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3744 (define_insn "*llgt_didi"
3745 [(set (match_operand:DI 0 "register_operand" "=d,d")
3746 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3747 (const_int 2147483647)))]
3752 [(set_attr "op_type" "RRE,RXE")
3753 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3756 [(set (match_operand:DSI 0 "register_operand" "")
3757 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3758 (const_int 2147483647)))
3759 (clobber (reg:CC CC_REGNUM))]
3760 "TARGET_ZARCH && reload_completed"
3762 (and:DSI (match_dup 1)
3763 (const_int 2147483647)))]
3767 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3770 (define_expand "zero_extend<mode>di2"
3771 [(set (match_operand:DI 0 "register_operand" "")
3772 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3777 rtx tmp = gen_reg_rtx (SImode);
3778 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3779 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3782 else if (!TARGET_EXTIMM)
3784 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
3785 operands[1] = gen_lowpart (DImode, operands[1]);
3786 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3787 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3792 (define_expand "zero_extend<mode>si2"
3793 [(set (match_operand:SI 0 "register_operand" "")
3794 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3799 operands[1] = gen_lowpart (SImode, operands[1]);
3800 emit_insn (gen_andsi3 (operands[0], operands[1],
3801 GEN_INT ((1 << <HQI:bitsize>) - 1)));
3807 (define_insn "*zero_extendhi<mode>2_z10"
3808 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3809 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3815 [(set_attr "op_type" "RXY,RRE,RIL")
3816 (set_attr "type" "*,*,larl")
3817 (set_attr "cpu_facility" "*,*,z10")
3818 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3820 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3821 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3822 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3823 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3828 [(set_attr "op_type" "RRE,RXY")
3829 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3832 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3833 [(set (match_operand:GPR 0 "register_operand" "=d")
3834 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3835 "TARGET_ZARCH && !TARGET_EXTIMM"
3837 [(set_attr "op_type" "RXY")
3838 (set_attr "z10prop" "z10_fwd_A3")])
3840 (define_insn_and_split "*zero_extendhisi2_31"
3841 [(set (match_operand:SI 0 "register_operand" "=&d")
3842 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3843 (clobber (reg:CC CC_REGNUM))]
3846 "&& reload_completed"
3847 [(set (match_dup 0) (const_int 0))
3849 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3850 (clobber (reg:CC CC_REGNUM))])]
3851 "operands[2] = gen_lowpart (HImode, operands[0]);")
3853 (define_insn_and_split "*zero_extendqisi2_31"
3854 [(set (match_operand:SI 0 "register_operand" "=&d")
3855 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3858 "&& reload_completed"
3859 [(set (match_dup 0) (const_int 0))
3860 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3861 "operands[2] = gen_lowpart (QImode, operands[0]);")
3864 ; zero_extendqihi2 instruction pattern(s).
3867 (define_expand "zero_extendqihi2"
3868 [(set (match_operand:HI 0 "register_operand" "")
3869 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3870 "TARGET_ZARCH && !TARGET_EXTIMM"
3872 operands[1] = gen_lowpart (HImode, operands[1]);
3873 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3877 (define_insn "*zero_extendqihi2_64"
3878 [(set (match_operand:HI 0 "register_operand" "=d")
3879 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3880 "TARGET_ZARCH && !TARGET_EXTIMM"
3882 [(set_attr "op_type" "RXY")
3883 (set_attr "z10prop" "z10_fwd_A3")])
3885 (define_insn_and_split "*zero_extendqihi2_31"
3886 [(set (match_operand:HI 0 "register_operand" "=&d")
3887 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3890 "&& reload_completed"
3891 [(set (match_dup 0) (const_int 0))
3892 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3893 "operands[2] = gen_lowpart (QImode, operands[0]);")
3896 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3899 (define_expand "fixuns_truncdddi2"
3901 [(set (match_operand:DI 0 "register_operand" "")
3902 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3903 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3904 (clobber (reg:CC CC_REGNUM))])]
3910 rtx label1 = gen_label_rtx ();
3911 rtx label2 = gen_label_rtx ();
3912 rtx temp = gen_reg_rtx (TDmode);
3913 REAL_VALUE_TYPE cmp, sub;
3915 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3916 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3918 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3919 solution is doing the check and the subtraction in TD mode and using a
3920 TD -> DI convert afterwards. */
3921 emit_insn (gen_extendddtd2 (temp, operands[1]));
3922 temp = force_reg (TDmode, temp);
3923 emit_cmp_and_jump_insns (temp,
3924 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3925 LT, NULL_RTX, VOIDmode, 0, label1);
3926 emit_insn (gen_subtd3 (temp, temp,
3927 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3928 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3931 emit_label (label1);
3932 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3933 emit_label (label2);
3938 (define_expand "fixuns_trunctddi2"
3940 [(set (match_operand:DI 0 "register_operand" "")
3941 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
3942 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3943 (clobber (reg:CC CC_REGNUM))])]
3949 rtx label1 = gen_label_rtx ();
3950 rtx label2 = gen_label_rtx ();
3951 rtx temp = gen_reg_rtx (TDmode);
3952 REAL_VALUE_TYPE cmp, sub;
3954 operands[1] = force_reg (TDmode, operands[1]);
3955 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3956 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3958 emit_cmp_and_jump_insns (operands[1],
3959 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3960 LT, NULL_RTX, VOIDmode, 0, label1);
3961 emit_insn (gen_subtd3 (temp, operands[1],
3962 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3963 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3966 emit_label (label1);
3967 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3968 emit_label (label2);
3974 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
3975 ; instruction pattern(s).
3978 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3980 [(set (match_operand:GPR 0 "register_operand" "")
3981 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
3982 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3983 (clobber (reg:CC CC_REGNUM))])]
3988 rtx label1 = gen_label_rtx ();
3989 rtx label2 = gen_label_rtx ();
3990 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3991 REAL_VALUE_TYPE cmp, sub;
3993 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3994 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
3995 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
3997 emit_cmp_and_jump_insns (operands[1],
3998 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
3999 LT, NULL_RTX, VOIDmode, 0, label1);
4000 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4001 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4002 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4006 emit_label (label1);
4007 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4008 operands[1], GEN_INT (5)));
4009 emit_label (label2);
4014 ; fixuns_trunc(td|dd)si2 expander
4015 (define_expand "fixuns_trunc<mode>si2"
4017 [(set (match_operand:SI 0 "register_operand" "")
4018 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4019 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4020 (clobber (reg:CC CC_REGNUM))])]
4021 "TARGET_Z196 && TARGET_HARD_DFP"
4024 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4026 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4027 ; clfdtr, clfxtr, clgdtr, clgxtr
4028 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4029 [(set (match_operand:GPR 0 "register_operand" "=r")
4030 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4031 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4032 (clobber (reg:CC CC_REGNUM))]
4034 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4035 [(set_attr "op_type" "RRF")
4036 (set_attr "type" "ftoi")])
4038 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4039 [(set (match_operand:GPR 0 "register_operand" "")
4040 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4043 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4048 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4049 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4050 [(set (match_operand:GPR 0 "register_operand" "=d")
4051 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4052 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4053 (clobber (reg:CC CC_REGNUM))]
4055 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4056 [(set_attr "op_type" "RRE")
4057 (set_attr "type" "ftoi")])
4061 ; fix_trunc(td|dd)di2 instruction pattern(s).
4064 (define_expand "fix_trunc<mode>di2"
4065 [(set (match_operand:DI 0 "register_operand" "")
4066 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4067 "TARGET_ZARCH && TARGET_HARD_DFP"
4069 operands[1] = force_reg (<MODE>mode, operands[1]);
4070 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4076 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4077 [(set (match_operand:DI 0 "register_operand" "=d")
4078 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4079 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4080 (clobber (reg:CC CC_REGNUM))]
4081 "TARGET_ZARCH && TARGET_HARD_DFP"
4082 "cg<DFP:xde>tr\t%0,%h2,%1"
4083 [(set_attr "op_type" "RRF")
4084 (set_attr "type" "ftoidfp")])
4088 ; fix_trunctf(si|di)2 instruction pattern(s).
4091 (define_expand "fix_trunctf<mode>2"
4092 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4093 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4094 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4095 (clobber (reg:CC CC_REGNUM))])]
4101 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4104 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4105 (define_insn "floatdi<mode>2"
4106 [(set (match_operand:FP 0 "register_operand" "=f")
4107 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4108 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4109 "c<xde>g<bt>r\t%0,%1"
4110 [(set_attr "op_type" "RRE")
4111 (set_attr "type" "itof<mode>" )])
4113 ; cxfbr, cdfbr, cefbr
4114 (define_insn "floatsi<mode>2"
4115 [(set (match_operand:BFP 0 "register_operand" "=f")
4116 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4119 [(set_attr "op_type" "RRE")
4120 (set_attr "type" "itof<mode>" )])
4123 (define_insn "floatsi<mode>2"
4124 [(set (match_operand:DFP 0 "register_operand" "=f")
4125 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4126 "TARGET_Z196 && TARGET_HARD_FLOAT"
4127 "c<xde>ftr\t%0,0,%1,0"
4128 [(set_attr "op_type" "RRE")
4129 (set_attr "type" "itof<mode>" )])
4132 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4135 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4136 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4137 (define_insn "floatuns<GPR:mode><FP:mode>2"
4138 [(set (match_operand:FP 0 "register_operand" "=f")
4139 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4140 "TARGET_Z196 && TARGET_HARD_FLOAT"
4141 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4142 [(set_attr "op_type" "RRE")
4143 (set_attr "type" "itof<FP:mode>" )])
4146 ; truncdfsf2 instruction pattern(s).
4149 (define_insn "truncdfsf2"
4150 [(set (match_operand:SF 0 "register_operand" "=f")
4151 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4154 [(set_attr "op_type" "RRE")
4155 (set_attr "type" "ftruncdf")])
4158 ; trunctf(df|sf)2 instruction pattern(s).
4162 (define_insn "trunctf<mode>2"
4163 [(set (match_operand:DSF 0 "register_operand" "=f")
4164 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4165 (clobber (match_scratch:TF 2 "=f"))]
4167 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4168 [(set_attr "length" "6")
4169 (set_attr "type" "ftrunctf")])
4172 ; trunctddd2 and truncddsd2 instruction pattern(s).
4175 (define_insn "trunctddd2"
4176 [(set (match_operand:DD 0 "register_operand" "=f")
4177 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4178 (clobber (match_scratch:TD 2 "=f"))]
4180 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4181 [(set_attr "length" "6")
4182 (set_attr "type" "ftruncdd")])
4184 (define_insn "truncddsd2"
4185 [(set (match_operand:SD 0 "register_operand" "=f")
4186 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4189 [(set_attr "op_type" "RRF")
4190 (set_attr "type" "ftruncsd")])
4193 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4196 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4197 (define_insn "extend<DSF:mode><BFP:mode>2"
4198 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4199 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4201 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4203 l<BFP:xde><DSF:xde>br\t%0,%1
4204 l<BFP:xde><DSF:xde>b\t%0,%1"
4205 [(set_attr "op_type" "RRE,RXE")
4206 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4209 ; extendddtd2 and extendsddd2 instruction pattern(s).
4212 (define_insn "extendddtd2"
4213 [(set (match_operand:TD 0 "register_operand" "=f")
4214 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4217 [(set_attr "op_type" "RRF")
4218 (set_attr "type" "fsimptf")])
4220 (define_insn "extendsddd2"
4221 [(set (match_operand:DD 0 "register_operand" "=f")
4222 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4225 [(set_attr "op_type" "RRF")
4226 (set_attr "type" "fsimptf")])
4228 ; Binary <-> Decimal floating point trunc patterns
4231 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4232 [(set (reg:DFP_ALL FPR0_REGNUM)
4233 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4234 (use (reg:SI GPR0_REGNUM))
4235 (clobber (reg:CC CC_REGNUM))]
4239 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4240 [(set (reg:BFP FPR0_REGNUM)
4241 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4242 (use (reg:SI GPR0_REGNUM))
4243 (clobber (reg:CC CC_REGNUM))]
4247 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4248 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4249 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4251 [(set (reg:DFP_ALL FPR0_REGNUM)
4252 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4253 (use (reg:SI GPR0_REGNUM))
4254 (clobber (reg:CC CC_REGNUM))])
4255 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4256 (reg:DFP_ALL FPR0_REGNUM))]
4258 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4260 HOST_WIDE_INT flags;
4262 flags = (PFPO_CONVERT |
4263 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4264 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4266 operands[2] = GEN_INT (flags);
4269 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4270 [(set (reg:DFP_ALL FPR2_REGNUM)
4271 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4272 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4274 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4275 (use (reg:SI GPR0_REGNUM))
4276 (clobber (reg:CC CC_REGNUM))])
4277 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4279 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4281 HOST_WIDE_INT flags;
4283 flags = (PFPO_CONVERT |
4284 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4285 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4287 operands[2] = GEN_INT (flags);
4291 ; Binary <-> Decimal floating point extend patterns
4294 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4295 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4296 (use (reg:SI GPR0_REGNUM))
4297 (clobber (reg:CC CC_REGNUM))]
4301 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4302 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4303 (use (reg:SI GPR0_REGNUM))
4304 (clobber (reg:CC CC_REGNUM))]
4308 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4309 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4310 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4312 [(set (reg:DFP_ALL FPR0_REGNUM)
4313 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4314 (use (reg:SI GPR0_REGNUM))
4315 (clobber (reg:CC CC_REGNUM))])
4316 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4317 (reg:DFP_ALL FPR0_REGNUM))]
4319 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4321 HOST_WIDE_INT flags;
4323 flags = (PFPO_CONVERT |
4324 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4325 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4327 operands[2] = GEN_INT (flags);
4330 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4331 [(set (reg:DFP_ALL FPR2_REGNUM)
4332 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4333 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4335 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4336 (use (reg:SI GPR0_REGNUM))
4337 (clobber (reg:CC CC_REGNUM))])
4338 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4340 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4342 HOST_WIDE_INT flags;
4344 flags = (PFPO_CONVERT |
4345 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4346 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4348 operands[2] = GEN_INT (flags);
4353 ;; ARITHMETIC OPERATIONS
4355 ; arithmetic operations set the ConditionCode,
4356 ; because of unpredictable Bits in Register for Halfword and Byte
4357 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4360 ;;- Add instructions.
4364 ; addti3 instruction pattern(s).
4367 (define_insn_and_split "addti3"
4368 [(set (match_operand:TI 0 "register_operand" "=&d")
4369 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4370 (match_operand:TI 2 "general_operand" "do") ) )
4371 (clobber (reg:CC CC_REGNUM))]
4374 "&& reload_completed"
4376 [(set (reg:CCL1 CC_REGNUM)
4377 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4379 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4381 [(set (match_dup 3) (plus:DI
4382 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4383 (match_dup 4)) (match_dup 5)))
4384 (clobber (reg:CC CC_REGNUM))])]
4385 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4386 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4387 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4388 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4389 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4390 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4393 ; adddi3 instruction pattern(s).
4396 (define_expand "adddi3"
4398 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4399 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4400 (match_operand:DI 2 "general_operand" "")))
4401 (clobber (reg:CC CC_REGNUM))])]
4405 (define_insn "*adddi3_sign"
4406 [(set (match_operand:DI 0 "register_operand" "=d,d")
4407 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4408 (match_operand:DI 1 "register_operand" "0,0")))
4409 (clobber (reg:CC CC_REGNUM))]
4414 [(set_attr "op_type" "RRE,RXY")
4415 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4417 (define_insn "*adddi3_zero_cc"
4418 [(set (reg CC_REGNUM)
4419 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4420 (match_operand:DI 1 "register_operand" "0,0"))
4422 (set (match_operand:DI 0 "register_operand" "=d,d")
4423 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4424 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4428 [(set_attr "op_type" "RRE,RXY")
4429 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4431 (define_insn "*adddi3_zero_cconly"
4432 [(set (reg CC_REGNUM)
4433 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4434 (match_operand:DI 1 "register_operand" "0,0"))
4436 (clobber (match_scratch:DI 0 "=d,d"))]
4437 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4441 [(set_attr "op_type" "RRE,RXY")
4442 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4444 (define_insn "*adddi3_zero"
4445 [(set (match_operand:DI 0 "register_operand" "=d,d")
4446 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4447 (match_operand:DI 1 "register_operand" "0,0")))
4448 (clobber (reg:CC CC_REGNUM))]
4453 [(set_attr "op_type" "RRE,RXY")
4454 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4456 (define_insn_and_split "*adddi3_31z"
4457 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4458 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4459 (match_operand:DI 2 "general_operand" "do") ) )
4460 (clobber (reg:CC CC_REGNUM))]
4461 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4463 "&& reload_completed"
4465 [(set (reg:CCL1 CC_REGNUM)
4466 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4468 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4470 [(set (match_dup 3) (plus:SI
4471 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4472 (match_dup 4)) (match_dup 5)))
4473 (clobber (reg:CC CC_REGNUM))])]
4474 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4475 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4476 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4477 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4478 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4479 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4481 (define_insn_and_split "*adddi3_31"
4482 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4483 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4484 (match_operand:DI 2 "general_operand" "do") ) )
4485 (clobber (reg:CC CC_REGNUM))]
4488 "&& reload_completed"
4490 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4491 (clobber (reg:CC CC_REGNUM))])
4493 [(set (reg:CCL1 CC_REGNUM)
4494 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4496 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4498 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4500 (label_ref (match_dup 9))))
4502 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4503 (clobber (reg:CC CC_REGNUM))])
4505 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4506 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4507 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4508 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4509 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4510 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4511 operands[9] = gen_label_rtx ();")
4514 ; addsi3 instruction pattern(s).
4517 (define_expand "addsi3"
4519 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4520 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4521 (match_operand:SI 2 "general_operand" "")))
4522 (clobber (reg:CC CC_REGNUM))])]
4526 (define_insn "*addsi3_sign"
4527 [(set (match_operand:SI 0 "register_operand" "=d,d")
4528 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4529 (match_operand:SI 1 "register_operand" "0,0")))
4530 (clobber (reg:CC CC_REGNUM))]
4535 [(set_attr "op_type" "RX,RXY")
4536 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4539 ; add(di|si)3 instruction pattern(s).
4542 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4543 (define_insn "*add<mode>3"
4544 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4545 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4546 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4547 (clobber (reg:CC CC_REGNUM))]
4559 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4560 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4561 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4562 z10_super_E1,z10_super_E1,z10_super_E1")])
4564 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4565 (define_insn "*add<mode>3_carry1_cc"
4566 [(set (reg CC_REGNUM)
4567 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4568 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4570 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4571 (plus:GPR (match_dup 1) (match_dup 2)))]
4572 "s390_match_ccmode (insn, CCL1mode)"
4578 al<g>hsik\t%0,%1,%h2
4582 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4583 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4584 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4585 z10_super_E1,z10_super_E1,z10_super_E1")])
4587 ; alr, al, aly, algr, alg, alrk, algrk
4588 (define_insn "*add<mode>3_carry1_cconly"
4589 [(set (reg CC_REGNUM)
4590 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4591 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4593 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4594 "s390_match_ccmode (insn, CCL1mode)"
4600 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4601 (set_attr "cpu_facility" "*,z196,*,*")
4602 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4604 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4605 (define_insn "*add<mode>3_carry2_cc"
4606 [(set (reg CC_REGNUM)
4607 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4608 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4610 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4611 (plus:GPR (match_dup 1) (match_dup 2)))]
4612 "s390_match_ccmode (insn, CCL1mode)"
4618 al<g>hsik\t%0,%1,%h2
4622 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4623 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4624 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4625 z10_super_E1,z10_super_E1,z10_super_E1")])
4627 ; alr, al, aly, algr, alg, alrk, algrk
4628 (define_insn "*add<mode>3_carry2_cconly"
4629 [(set (reg CC_REGNUM)
4630 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4631 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4633 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4634 "s390_match_ccmode (insn, CCL1mode)"
4640 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4641 (set_attr "cpu_facility" "*,z196,*,*")
4642 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4644 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4645 (define_insn "*add<mode>3_cc"
4646 [(set (reg CC_REGNUM)
4647 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4648 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4650 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4651 (plus:GPR (match_dup 1) (match_dup 2)))]
4652 "s390_match_ccmode (insn, CCLmode)"
4658 al<g>hsik\t%0,%1,%h2
4662 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4663 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4664 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4665 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4667 ; alr, al, aly, algr, alg, alrk, algrk
4668 (define_insn "*add<mode>3_cconly"
4669 [(set (reg CC_REGNUM)
4670 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4671 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4673 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4674 "s390_match_ccmode (insn, CCLmode)"
4680 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4681 (set_attr "cpu_facility" "*,z196,*,*")
4682 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4684 ; alr, al, aly, algr, alg, alrk, algrk
4685 (define_insn "*add<mode>3_cconly2"
4686 [(set (reg CC_REGNUM)
4687 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4688 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4689 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4690 "s390_match_ccmode(insn, CCLmode)"
4696 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4697 (set_attr "cpu_facility" "*,z196,*,*")
4698 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4700 ; ahi, afi, aghi, agfi, asi, agsi
4701 (define_insn "*add<mode>3_imm_cc"
4702 [(set (reg CC_REGNUM)
4703 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4704 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4706 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4707 (plus:GPR (match_dup 1) (match_dup 2)))]
4708 "s390_match_ccmode (insn, CCAmode)
4709 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4710 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4711 /* Avoid INT32_MIN on 32 bit. */
4712 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
4718 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4719 (set_attr "cpu_facility" "*,z196,extimm,z10")
4720 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4723 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4726 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4727 (define_insn "add<mode>3"
4728 [(set (match_operand:FP 0 "register_operand" "=f, f")
4729 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4730 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4731 (clobber (reg:CC CC_REGNUM))]
4734 a<xde><bt>r\t%0,<op1>%2
4736 [(set_attr "op_type" "<RRer>,RXE")
4737 (set_attr "type" "fsimp<mode>")])
4739 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4740 (define_insn "*add<mode>3_cc"
4741 [(set (reg CC_REGNUM)
4742 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4743 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4744 (match_operand:FP 3 "const0_operand" "")))
4745 (set (match_operand:FP 0 "register_operand" "=f,f")
4746 (plus:FP (match_dup 1) (match_dup 2)))]
4747 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4749 a<xde><bt>r\t%0,<op1>%2
4751 [(set_attr "op_type" "<RRer>,RXE")
4752 (set_attr "type" "fsimp<mode>")])
4754 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4755 (define_insn "*add<mode>3_cconly"
4756 [(set (reg CC_REGNUM)
4757 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4758 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4759 (match_operand:FP 3 "const0_operand" "")))
4760 (clobber (match_scratch:FP 0 "=f,f"))]
4761 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4763 a<xde><bt>r\t%0,<op1>%2
4765 [(set_attr "op_type" "<RRer>,RXE")
4766 (set_attr "type" "fsimp<mode>")])
4770 ;;- Subtract instructions.
4774 ; subti3 instruction pattern(s).
4777 (define_insn_and_split "subti3"
4778 [(set (match_operand:TI 0 "register_operand" "=&d")
4779 (minus:TI (match_operand:TI 1 "register_operand" "0")
4780 (match_operand:TI 2 "general_operand" "do") ) )
4781 (clobber (reg:CC CC_REGNUM))]
4784 "&& reload_completed"
4786 [(set (reg:CCL2 CC_REGNUM)
4787 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4789 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4791 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4792 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4793 (clobber (reg:CC CC_REGNUM))])]
4794 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4795 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4796 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4797 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4798 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4799 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4802 ; subdi3 instruction pattern(s).
4805 (define_expand "subdi3"
4807 [(set (match_operand:DI 0 "register_operand" "")
4808 (minus:DI (match_operand:DI 1 "register_operand" "")
4809 (match_operand:DI 2 "general_operand" "")))
4810 (clobber (reg:CC CC_REGNUM))])]
4814 (define_insn "*subdi3_sign"
4815 [(set (match_operand:DI 0 "register_operand" "=d,d")
4816 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4817 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4818 (clobber (reg:CC CC_REGNUM))]
4823 [(set_attr "op_type" "RRE,RXY")
4824 (set_attr "z10prop" "z10_c,*")
4825 (set_attr "z196prop" "z196_cracked")])
4827 (define_insn "*subdi3_zero_cc"
4828 [(set (reg CC_REGNUM)
4829 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4830 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4832 (set (match_operand:DI 0 "register_operand" "=d,d")
4833 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4834 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4838 [(set_attr "op_type" "RRE,RXY")
4839 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4841 (define_insn "*subdi3_zero_cconly"
4842 [(set (reg CC_REGNUM)
4843 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4844 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4846 (clobber (match_scratch:DI 0 "=d,d"))]
4847 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4851 [(set_attr "op_type" "RRE,RXY")
4852 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4854 (define_insn "*subdi3_zero"
4855 [(set (match_operand:DI 0 "register_operand" "=d,d")
4856 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4857 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4858 (clobber (reg:CC CC_REGNUM))]
4863 [(set_attr "op_type" "RRE,RXY")
4864 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4866 (define_insn_and_split "*subdi3_31z"
4867 [(set (match_operand:DI 0 "register_operand" "=&d")
4868 (minus:DI (match_operand:DI 1 "register_operand" "0")
4869 (match_operand:DI 2 "general_operand" "do") ) )
4870 (clobber (reg:CC CC_REGNUM))]
4871 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4873 "&& reload_completed"
4875 [(set (reg:CCL2 CC_REGNUM)
4876 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4878 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4880 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4881 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4882 (clobber (reg:CC CC_REGNUM))])]
4883 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4884 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4885 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4886 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4887 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4888 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4890 (define_insn_and_split "*subdi3_31"
4891 [(set (match_operand:DI 0 "register_operand" "=&d")
4892 (minus:DI (match_operand:DI 1 "register_operand" "0")
4893 (match_operand:DI 2 "general_operand" "do") ) )
4894 (clobber (reg:CC CC_REGNUM))]
4897 "&& reload_completed"
4899 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4900 (clobber (reg:CC CC_REGNUM))])
4902 [(set (reg:CCL2 CC_REGNUM)
4903 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4905 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4907 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4909 (label_ref (match_dup 9))))
4911 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4912 (clobber (reg:CC CC_REGNUM))])
4914 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4915 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4916 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4917 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4918 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4919 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4920 operands[9] = gen_label_rtx ();")
4923 ; subsi3 instruction pattern(s).
4926 (define_expand "subsi3"
4928 [(set (match_operand:SI 0 "register_operand" "")
4929 (minus:SI (match_operand:SI 1 "register_operand" "")
4930 (match_operand:SI 2 "general_operand" "")))
4931 (clobber (reg:CC CC_REGNUM))])]
4935 (define_insn "*subsi3_sign"
4936 [(set (match_operand:SI 0 "register_operand" "=d,d")
4937 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4938 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4939 (clobber (reg:CC CC_REGNUM))]
4944 [(set_attr "op_type" "RX,RXY")
4945 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4948 ; sub(di|si)3 instruction pattern(s).
4951 ; sr, s, sy, sgr, sg, srk, sgrk
4952 (define_insn "*sub<mode>3"
4953 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4954 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4955 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
4956 (clobber (reg:CC CC_REGNUM))]
4963 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4964 (set_attr "cpu_facility" "*,z196,*,*")
4965 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
4967 ; slr, sl, sly, slgr, slg, slrk, slgrk
4968 (define_insn "*sub<mode>3_borrow_cc"
4969 [(set (reg CC_REGNUM)
4970 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4971 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4973 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
4974 (minus:GPR (match_dup 1) (match_dup 2)))]
4975 "s390_match_ccmode (insn, CCL2mode)"
4981 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4982 (set_attr "cpu_facility" "*,z196,*,*")
4983 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
4985 ; slr, sl, sly, slgr, slg, slrk, slgrk
4986 (define_insn "*sub<mode>3_borrow_cconly"
4987 [(set (reg CC_REGNUM)
4988 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
4989 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4991 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4992 "s390_match_ccmode (insn, CCL2mode)"
4998 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4999 (set_attr "cpu_facility" "*,z196,*,*")
5000 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5002 ; slr, sl, sly, slgr, slg, slrk, slgrk
5003 (define_insn "*sub<mode>3_cc"
5004 [(set (reg CC_REGNUM)
5005 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5006 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5008 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5009 (minus:GPR (match_dup 1) (match_dup 2)))]
5010 "s390_match_ccmode (insn, CCLmode)"
5016 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5017 (set_attr "cpu_facility" "*,z196,*,*")
5018 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5020 ; slr, sl, sly, slgr, slg, slrk, slgrk
5021 (define_insn "*sub<mode>3_cc2"
5022 [(set (reg CC_REGNUM)
5023 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5024 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5025 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5026 (minus:GPR (match_dup 1) (match_dup 2)))]
5027 "s390_match_ccmode (insn, CCL3mode)"
5033 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5034 (set_attr "cpu_facility" "*,z196,*,*")
5035 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5037 ; slr, sl, sly, slgr, slg, slrk, slgrk
5038 (define_insn "*sub<mode>3_cconly"
5039 [(set (reg CC_REGNUM)
5040 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5041 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5043 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5044 "s390_match_ccmode (insn, CCLmode)"
5050 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5051 (set_attr "cpu_facility" "*,z196,*,*")
5052 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5055 ; slr, sl, sly, slgr, slg, slrk, slgrk
5056 (define_insn "*sub<mode>3_cconly2"
5057 [(set (reg CC_REGNUM)
5058 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5059 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5060 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5061 "s390_match_ccmode (insn, CCL3mode)"
5067 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5068 (set_attr "cpu_facility" "*,z196,*,*")
5069 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5073 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5076 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5077 (define_insn "sub<mode>3"
5078 [(set (match_operand:FP 0 "register_operand" "=f, f")
5079 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5080 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5081 (clobber (reg:CC CC_REGNUM))]
5084 s<xde><bt>r\t%0,<op1>%2
5086 [(set_attr "op_type" "<RRer>,RXE")
5087 (set_attr "type" "fsimp<mode>")])
5089 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5090 (define_insn "*sub<mode>3_cc"
5091 [(set (reg CC_REGNUM)
5092 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5093 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5094 (match_operand:FP 3 "const0_operand" "")))
5095 (set (match_operand:FP 0 "register_operand" "=f,f")
5096 (minus:FP (match_dup 1) (match_dup 2)))]
5097 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5099 s<xde><bt>r\t%0,<op1>%2
5101 [(set_attr "op_type" "<RRer>,RXE")
5102 (set_attr "type" "fsimp<mode>")])
5104 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5105 (define_insn "*sub<mode>3_cconly"
5106 [(set (reg CC_REGNUM)
5107 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5108 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5109 (match_operand:FP 3 "const0_operand" "")))
5110 (clobber (match_scratch:FP 0 "=f,f"))]
5111 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5113 s<xde><bt>r\t%0,<op1>%2
5115 [(set_attr "op_type" "<RRer>,RXE")
5116 (set_attr "type" "fsimp<mode>")])
5120 ;;- Conditional add/subtract instructions.
5124 ; add(di|si)cc instruction pattern(s).
5127 ; the following 4 patterns are used when the result of an add with
5128 ; carry is checked for an overflow condition
5130 ; op1 + op2 + c < op1
5132 ; alcr, alc, alcgr, alcg
5133 (define_insn "*add<mode>3_alc_carry1_cc"
5134 [(set (reg CC_REGNUM)
5136 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5137 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5138 (match_operand:GPR 2 "general_operand" "d,RT"))
5140 (set (match_operand:GPR 0 "register_operand" "=d,d")
5141 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5142 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5146 [(set_attr "op_type" "RRE,RXY")
5147 (set_attr "z196prop" "z196_alone,z196_alone")])
5149 ; alcr, alc, alcgr, alcg
5150 (define_insn "*add<mode>3_alc_carry1_cconly"
5151 [(set (reg CC_REGNUM)
5153 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5154 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5155 (match_operand:GPR 2 "general_operand" "d,RT"))
5157 (clobber (match_scratch:GPR 0 "=d,d"))]
5158 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5162 [(set_attr "op_type" "RRE,RXY")
5163 (set_attr "z196prop" "z196_alone,z196_alone")])
5165 ; op1 + op2 + c < op2
5167 ; alcr, alc, alcgr, alcg
5168 (define_insn "*add<mode>3_alc_carry2_cc"
5169 [(set (reg CC_REGNUM)
5171 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5172 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5173 (match_operand:GPR 2 "general_operand" "d,RT"))
5175 (set (match_operand:GPR 0 "register_operand" "=d,d")
5176 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5177 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5181 [(set_attr "op_type" "RRE,RXY")])
5183 ; alcr, alc, alcgr, alcg
5184 (define_insn "*add<mode>3_alc_carry2_cconly"
5185 [(set (reg CC_REGNUM)
5187 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5188 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5189 (match_operand:GPR 2 "general_operand" "d,RT"))
5191 (clobber (match_scratch:GPR 0 "=d,d"))]
5192 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5196 [(set_attr "op_type" "RRE,RXY")])
5198 ; alcr, alc, alcgr, alcg
5199 (define_insn "*add<mode>3_alc_cc"
5200 [(set (reg CC_REGNUM)
5202 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5203 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5204 (match_operand:GPR 2 "general_operand" "d,RT"))
5206 (set (match_operand:GPR 0 "register_operand" "=d,d")
5207 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5208 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5212 [(set_attr "op_type" "RRE,RXY")])
5214 ; alcr, alc, alcgr, alcg
5215 (define_insn "*add<mode>3_alc"
5216 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5217 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5218 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5219 (match_operand:GPR 2 "general_operand" "d,RT")))
5220 (clobber (reg:CC CC_REGNUM))]
5225 [(set_attr "op_type" "RRE,RXY")])
5227 ; slbr, slb, slbgr, slbg
5228 (define_insn "*sub<mode>3_slb_cc"
5229 [(set (reg CC_REGNUM)
5231 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5232 (match_operand:GPR 2 "general_operand" "d,RT"))
5233 (match_operand:GPR 3 "s390_slb_comparison" ""))
5235 (set (match_operand:GPR 0 "register_operand" "=d,d")
5236 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5237 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5241 [(set_attr "op_type" "RRE,RXY")
5242 (set_attr "z10prop" "z10_c,*")])
5244 ; slbr, slb, slbgr, slbg
5245 (define_insn "*sub<mode>3_slb"
5246 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5247 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5248 (match_operand:GPR 2 "general_operand" "d,RT"))
5249 (match_operand:GPR 3 "s390_slb_comparison" "")))
5250 (clobber (reg:CC CC_REGNUM))]
5255 [(set_attr "op_type" "RRE,RXY")
5256 (set_attr "z10prop" "z10_c,*")])
5258 (define_expand "add<mode>cc"
5259 [(match_operand:GPR 0 "register_operand" "")
5260 (match_operand 1 "comparison_operator" "")
5261 (match_operand:GPR 2 "register_operand" "")
5262 (match_operand:GPR 3 "const_int_operand" "")]
5264 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5265 XEXP (operands[1], 0), XEXP (operands[1], 1),
5266 operands[0], operands[2],
5267 operands[3])) FAIL; DONE;")
5270 ; scond instruction pattern(s).
5273 (define_insn_and_split "*scond<mode>"
5274 [(set (match_operand:GPR 0 "register_operand" "=&d")
5275 (match_operand:GPR 1 "s390_alc_comparison" ""))
5276 (clobber (reg:CC CC_REGNUM))]
5279 "&& reload_completed"
5280 [(set (match_dup 0) (const_int 0))
5282 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5284 (clobber (reg:CC CC_REGNUM))])]
5287 (define_insn_and_split "*scond<mode>_neg"
5288 [(set (match_operand:GPR 0 "register_operand" "=&d")
5289 (match_operand:GPR 1 "s390_slb_comparison" ""))
5290 (clobber (reg:CC CC_REGNUM))]
5293 "&& reload_completed"
5294 [(set (match_dup 0) (const_int 0))
5296 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5298 (clobber (reg:CC CC_REGNUM))])
5300 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5301 (clobber (reg:CC CC_REGNUM))])]
5305 (define_expand "cstore<mode>4"
5306 [(set (match_operand:SI 0 "register_operand" "")
5307 (match_operator:SI 1 "s390_scond_operator"
5308 [(match_operand:GPR 2 "register_operand" "")
5309 (match_operand:GPR 3 "general_operand" "")]))]
5311 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5312 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5314 (define_expand "cstorecc4"
5316 [(set (match_operand:SI 0 "register_operand" "")
5317 (match_operator:SI 1 "s390_eqne_operator"
5318 [(match_operand:CCZ1 2 "register_operand")
5319 (match_operand 3 "const0_operand")]))
5320 (clobber (reg:CC CC_REGNUM))])]
5322 "emit_insn (gen_sne (operands[0], operands[2]));
5323 if (GET_CODE (operands[1]) == EQ)
5324 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5327 (define_insn_and_split "sne"
5328 [(set (match_operand:SI 0 "register_operand" "=d")
5329 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5331 (clobber (reg:CC CC_REGNUM))]
5336 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5337 (clobber (reg:CC CC_REGNUM))])])
5341 ;; - Conditional move instructions (introduced with z196)
5344 (define_expand "mov<mode>cc"
5345 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5346 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5347 (match_operand:GPR 2 "nonimmediate_operand" "")
5348 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5350 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5351 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5353 ; locr, loc, stoc, locgr, locg, stocg
5354 (define_insn_and_split "*mov<mode>cc"
5355 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5357 (match_operator 1 "s390_comparison"
5358 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5360 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5361 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5371 "&& reload_completed
5372 && MEM_P (operands[3]) && MEM_P (operands[4])"
5375 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5380 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5384 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5387 ;;- Multiply instructions.
5391 ; muldi3 instruction pattern(s).
5394 (define_insn "*muldi3_sign"
5395 [(set (match_operand:DI 0 "register_operand" "=d,d")
5396 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5397 (match_operand:DI 1 "register_operand" "0,0")))]
5402 [(set_attr "op_type" "RRE,RXY")
5403 (set_attr "type" "imuldi")])
5405 (define_insn "muldi3"
5406 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5407 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5408 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5415 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5416 (set_attr "type" "imuldi")
5417 (set_attr "cpu_facility" "*,*,*,z10")])
5420 ; mulsi3 instruction pattern(s).
5423 (define_insn "*mulsi3_sign"
5424 [(set (match_operand:SI 0 "register_operand" "=d,d")
5425 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5426 (match_operand:SI 1 "register_operand" "0,0")))]
5431 [(set_attr "op_type" "RX,RXY")
5432 (set_attr "type" "imulhi")
5433 (set_attr "cpu_facility" "*,z10")])
5435 (define_insn "mulsi3"
5436 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5437 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5438 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5446 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5447 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5448 (set_attr "cpu_facility" "*,*,*,*,z10")])
5451 ; mulsidi3 instruction pattern(s).
5454 (define_insn "mulsidi3"
5455 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5456 (mult:DI (sign_extend:DI
5457 (match_operand:SI 1 "register_operand" "%0,0,0"))
5459 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5465 [(set_attr "op_type" "RR,RX,RXY")
5466 (set_attr "type" "imulsi")
5467 (set_attr "cpu_facility" "*,*,z10")])
5470 ; umul instruction pattern(s).
5473 ; mlr, ml, mlgr, mlg
5474 (define_insn "umul<dwh><mode>3"
5475 [(set (match_operand:DW 0 "register_operand" "=d, d")
5476 (mult:DW (zero_extend:DW
5477 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5479 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5484 [(set_attr "op_type" "RRE,RXY")
5485 (set_attr "type" "imul<dwh>")])
5488 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5491 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5492 (define_insn "mul<mode>3"
5493 [(set (match_operand:FP 0 "register_operand" "=f,f")
5494 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5495 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5498 m<xdee><bt>r\t%0,<op1>%2
5500 [(set_attr "op_type" "<RRer>,RXE")
5501 (set_attr "type" "fmul<mode>")])
5503 ; madbr, maebr, maxb, madb, maeb
5504 (define_insn "fma<mode>4"
5505 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5506 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5507 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5508 (match_operand:DSF 3 "register_operand" "0,0")))]
5513 [(set_attr "op_type" "RRE,RXE")
5514 (set_attr "type" "fmadd<mode>")])
5516 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5517 (define_insn "fms<mode>4"
5518 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5519 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5520 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5521 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5526 [(set_attr "op_type" "RRE,RXE")
5527 (set_attr "type" "fmadd<mode>")])
5530 ;;- Divide and modulo instructions.
5534 ; divmoddi4 instruction pattern(s).
5537 (define_expand "divmoddi4"
5538 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5539 (div:DI (match_operand:DI 1 "register_operand" "")
5540 (match_operand:DI 2 "general_operand" "")))
5541 (set (match_operand:DI 3 "general_operand" "")
5542 (mod:DI (match_dup 1) (match_dup 2)))])
5543 (clobber (match_dup 4))]
5546 rtx insn, div_equal, mod_equal;
5548 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5549 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5551 operands[4] = gen_reg_rtx(TImode);
5552 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5554 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5555 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5557 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5558 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5563 (define_insn "divmodtidi3"
5564 [(set (match_operand:TI 0 "register_operand" "=d,d")
5568 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5569 (match_operand:DI 2 "general_operand" "d,RT")))
5571 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5576 [(set_attr "op_type" "RRE,RXY")
5577 (set_attr "type" "idiv")])
5579 (define_insn "divmodtisi3"
5580 [(set (match_operand:TI 0 "register_operand" "=d,d")
5584 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5586 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5589 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5594 [(set_attr "op_type" "RRE,RXY")
5595 (set_attr "type" "idiv")])
5598 ; udivmoddi4 instruction pattern(s).
5601 (define_expand "udivmoddi4"
5602 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5603 (udiv:DI (match_operand:DI 1 "general_operand" "")
5604 (match_operand:DI 2 "nonimmediate_operand" "")))
5605 (set (match_operand:DI 3 "general_operand" "")
5606 (umod:DI (match_dup 1) (match_dup 2)))])
5607 (clobber (match_dup 4))]
5610 rtx insn, div_equal, mod_equal, equal;
5612 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5613 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5614 equal = gen_rtx_IOR (TImode,
5615 gen_rtx_ASHIFT (TImode,
5616 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5618 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5620 operands[4] = gen_reg_rtx(TImode);
5621 emit_clobber (operands[4]);
5622 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5623 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5625 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5626 set_unique_reg_note (insn, REG_EQUAL, equal);
5628 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5629 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5631 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5632 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5637 (define_insn "udivmodtidi3"
5638 [(set (match_operand:TI 0 "register_operand" "=d,d")
5643 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5645 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5649 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5654 [(set_attr "op_type" "RRE,RXY")
5655 (set_attr "type" "idiv")])
5658 ; divmodsi4 instruction pattern(s).
5661 (define_expand "divmodsi4"
5662 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5663 (div:SI (match_operand:SI 1 "general_operand" "")
5664 (match_operand:SI 2 "nonimmediate_operand" "")))
5665 (set (match_operand:SI 3 "general_operand" "")
5666 (mod:SI (match_dup 1) (match_dup 2)))])
5667 (clobber (match_dup 4))]
5670 rtx insn, div_equal, mod_equal, equal;
5672 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5673 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5674 equal = gen_rtx_IOR (DImode,
5675 gen_rtx_ASHIFT (DImode,
5676 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5678 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5680 operands[4] = gen_reg_rtx(DImode);
5681 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5683 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5684 set_unique_reg_note (insn, REG_EQUAL, equal);
5686 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5687 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5689 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5690 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5695 (define_insn "divmoddisi3"
5696 [(set (match_operand:DI 0 "register_operand" "=d,d")
5701 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5703 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5707 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5712 [(set_attr "op_type" "RR,RX")
5713 (set_attr "type" "idiv")])
5716 ; udivsi3 and umodsi3 instruction pattern(s).
5719 (define_expand "udivmodsi4"
5720 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5721 (udiv:SI (match_operand:SI 1 "general_operand" "")
5722 (match_operand:SI 2 "nonimmediate_operand" "")))
5723 (set (match_operand:SI 3 "general_operand" "")
5724 (umod:SI (match_dup 1) (match_dup 2)))])
5725 (clobber (match_dup 4))]
5726 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5728 rtx insn, div_equal, mod_equal, equal;
5730 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5731 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5732 equal = gen_rtx_IOR (DImode,
5733 gen_rtx_ASHIFT (DImode,
5734 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5736 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5738 operands[4] = gen_reg_rtx(DImode);
5739 emit_clobber (operands[4]);
5740 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5741 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5743 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5744 set_unique_reg_note (insn, REG_EQUAL, equal);
5746 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5747 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5749 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5750 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5755 (define_insn "udivmoddisi3"
5756 [(set (match_operand:DI 0 "register_operand" "=d,d")
5761 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5763 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5767 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5768 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5772 [(set_attr "op_type" "RRE,RXY")
5773 (set_attr "type" "idiv")])
5775 (define_expand "udivsi3"
5776 [(set (match_operand:SI 0 "register_operand" "=d")
5777 (udiv:SI (match_operand:SI 1 "general_operand" "")
5778 (match_operand:SI 2 "general_operand" "")))
5779 (clobber (match_dup 3))]
5780 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5782 rtx insn, udiv_equal, umod_equal, equal;
5784 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5785 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5786 equal = gen_rtx_IOR (DImode,
5787 gen_rtx_ASHIFT (DImode,
5788 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5790 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5792 operands[3] = gen_reg_rtx (DImode);
5794 if (CONSTANT_P (operands[2]))
5796 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5798 rtx label1 = gen_label_rtx ();
5800 operands[1] = make_safe_from (operands[1], operands[0]);
5801 emit_move_insn (operands[0], const0_rtx);
5802 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5804 emit_move_insn (operands[0], const1_rtx);
5805 emit_label (label1);
5809 operands[2] = force_reg (SImode, operands[2]);
5810 operands[2] = make_safe_from (operands[2], operands[0]);
5812 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5813 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5815 set_unique_reg_note (insn, REG_EQUAL, equal);
5817 insn = emit_move_insn (operands[0],
5818 gen_lowpart (SImode, operands[3]));
5819 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5824 rtx label1 = gen_label_rtx ();
5825 rtx label2 = gen_label_rtx ();
5826 rtx label3 = gen_label_rtx ();
5828 operands[1] = force_reg (SImode, operands[1]);
5829 operands[1] = make_safe_from (operands[1], operands[0]);
5830 operands[2] = force_reg (SImode, operands[2]);
5831 operands[2] = make_safe_from (operands[2], operands[0]);
5833 emit_move_insn (operands[0], const0_rtx);
5834 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5836 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5838 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5840 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5841 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5843 set_unique_reg_note (insn, REG_EQUAL, equal);
5845 insn = emit_move_insn (operands[0],
5846 gen_lowpart (SImode, operands[3]));
5847 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5850 emit_label (label1);
5851 emit_move_insn (operands[0], operands[1]);
5853 emit_label (label2);
5854 emit_move_insn (operands[0], const1_rtx);
5855 emit_label (label3);
5857 emit_move_insn (operands[0], operands[0]);
5861 (define_expand "umodsi3"
5862 [(set (match_operand:SI 0 "register_operand" "=d")
5863 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5864 (match_operand:SI 2 "nonimmediate_operand" "")))
5865 (clobber (match_dup 3))]
5866 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5868 rtx insn, udiv_equal, umod_equal, equal;
5870 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5871 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5872 equal = gen_rtx_IOR (DImode,
5873 gen_rtx_ASHIFT (DImode,
5874 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5876 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5878 operands[3] = gen_reg_rtx (DImode);
5880 if (CONSTANT_P (operands[2]))
5882 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5884 rtx label1 = gen_label_rtx ();
5886 operands[1] = make_safe_from (operands[1], operands[0]);
5887 emit_move_insn (operands[0], operands[1]);
5888 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5890 emit_insn (gen_abssi2 (operands[0], operands[2]));
5891 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5892 emit_label (label1);
5896 operands[2] = force_reg (SImode, operands[2]);
5897 operands[2] = make_safe_from (operands[2], operands[0]);
5899 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5900 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5902 set_unique_reg_note (insn, REG_EQUAL, equal);
5904 insn = emit_move_insn (operands[0],
5905 gen_highpart (SImode, operands[3]));
5906 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5911 rtx label1 = gen_label_rtx ();
5912 rtx label2 = gen_label_rtx ();
5913 rtx label3 = gen_label_rtx ();
5915 operands[1] = force_reg (SImode, operands[1]);
5916 operands[1] = make_safe_from (operands[1], operands[0]);
5917 operands[2] = force_reg (SImode, operands[2]);
5918 operands[2] = make_safe_from (operands[2], operands[0]);
5920 emit_move_insn(operands[0], operands[1]);
5921 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5923 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5925 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5927 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5928 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5930 set_unique_reg_note (insn, REG_EQUAL, equal);
5932 insn = emit_move_insn (operands[0],
5933 gen_highpart (SImode, operands[3]));
5934 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5937 emit_label (label1);
5938 emit_move_insn (operands[0], const0_rtx);
5940 emit_label (label2);
5941 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5942 emit_label (label3);
5948 ; div(df|sf)3 instruction pattern(s).
5951 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5952 (define_insn "div<mode>3"
5953 [(set (match_operand:FP 0 "register_operand" "=f,f")
5954 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5955 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5958 d<xde><bt>r\t%0,<op1>%2
5960 [(set_attr "op_type" "<RRer>,RXE")
5961 (set_attr "type" "fdiv<mode>")])
5965 ;;- And instructions.
5968 (define_expand "and<mode>3"
5969 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5970 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5971 (match_operand:INT 2 "general_operand" "")))
5972 (clobber (reg:CC CC_REGNUM))]
5974 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5977 ; anddi3 instruction pattern(s).
5980 (define_insn "*anddi3_cc"
5981 [(set (reg CC_REGNUM)
5983 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
5984 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
5986 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
5987 (and:DI (match_dup 1) (match_dup 2)))]
5988 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
5993 risbg\t%0,%1,%s2,128+%e2,0"
5994 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
5995 (set_attr "cpu_facility" "*,z196,*,z10")
5996 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5998 (define_insn "*anddi3_cconly"
5999 [(set (reg CC_REGNUM)
6001 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6002 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6004 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6006 && s390_match_ccmode(insn, CCTmode)
6007 /* Do not steal TM patterns. */
6008 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6013 risbg\t%0,%1,%s2,128+%e2,0"
6014 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6015 (set_attr "cpu_facility" "*,z196,*,z10")
6016 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6018 (define_insn "*anddi3"
6019 [(set (match_operand:DI 0 "nonimmediate_operand"
6020 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6022 (match_operand:DI 1 "nonimmediate_operand"
6023 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6024 (match_operand:DI 2 "general_operand"
6025 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6026 (clobber (reg:CC CC_REGNUM))]
6027 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6040 risbg\t%0,%1,%s2,128+%e2,0
6043 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6044 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6045 (set_attr "z10prop" "*,
6061 [(set (match_operand:DI 0 "s_operand" "")
6062 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6063 (clobber (reg:CC CC_REGNUM))]
6066 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6067 (clobber (reg:CC CC_REGNUM))])]
6068 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6072 ; andsi3 instruction pattern(s).
6075 (define_insn "*andsi3_cc"
6076 [(set (reg CC_REGNUM)
6079 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6080 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6082 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6083 (and:SI (match_dup 1) (match_dup 2)))]
6084 "s390_match_ccmode(insn, CCTmode)"
6091 risbg\t%0,%1,%t2,128+%f2,0"
6092 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6093 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6094 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6095 z10_super_E1,z10_super_E1,z10_super_E1")])
6097 (define_insn "*andsi3_cconly"
6098 [(set (reg CC_REGNUM)
6101 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6102 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6104 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6105 "s390_match_ccmode(insn, CCTmode)
6106 /* Do not steal TM patterns. */
6107 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6114 risbg\t%0,%1,%t2,128+%f2,0"
6115 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6116 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6117 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6118 z10_super_E1,z10_super_E1,z10_super_E1")])
6120 (define_insn "*andsi3_zarch"
6121 [(set (match_operand:SI 0 "nonimmediate_operand"
6122 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6123 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6124 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6125 (match_operand:SI 2 "general_operand"
6126 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6127 (clobber (reg:CC CC_REGNUM))]
6128 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6139 risbg\t%0,%1,%t2,128+%f2,0
6142 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6143 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6144 (set_attr "z10prop" "*,
6157 (define_insn "*andsi3_esa"
6158 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6159 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6160 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6161 (clobber (reg:CC CC_REGNUM))]
6162 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6168 [(set_attr "op_type" "RR,RX,SI,SS")
6169 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6173 [(set (match_operand:SI 0 "s_operand" "")
6174 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6175 (clobber (reg:CC CC_REGNUM))]
6178 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6179 (clobber (reg:CC CC_REGNUM))])]
6180 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6183 ; andhi3 instruction pattern(s).
6186 (define_insn "*andhi3_zarch"
6187 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6188 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6189 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6190 (clobber (reg:CC CC_REGNUM))]
6191 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6198 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6199 (set_attr "cpu_facility" "*,z196,*,*,*")
6200 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6203 (define_insn "*andhi3_esa"
6204 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6205 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6206 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6207 (clobber (reg:CC CC_REGNUM))]
6208 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6213 [(set_attr "op_type" "RR,SI,SS")
6214 (set_attr "z10prop" "z10_super_E1,*,*")
6218 [(set (match_operand:HI 0 "s_operand" "")
6219 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6220 (clobber (reg:CC CC_REGNUM))]
6223 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6224 (clobber (reg:CC CC_REGNUM))])]
6225 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6228 ; andqi3 instruction pattern(s).
6231 (define_insn "*andqi3_zarch"
6232 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6233 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6234 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6235 (clobber (reg:CC CC_REGNUM))]
6236 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6244 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6245 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6246 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6248 (define_insn "*andqi3_esa"
6249 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6250 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6251 (match_operand:QI 2 "general_operand" "d,n,Q")))
6252 (clobber (reg:CC CC_REGNUM))]
6253 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6258 [(set_attr "op_type" "RR,SI,SS")
6259 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6262 ; Block and (NC) patterns.
6266 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6267 (and:BLK (match_dup 0)
6268 (match_operand:BLK 1 "memory_operand" "Q")))
6269 (use (match_operand 2 "const_int_operand" "n"))
6270 (clobber (reg:CC CC_REGNUM))]
6271 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6272 "nc\t%O0(%2,%R0),%S1"
6273 [(set_attr "op_type" "SS")
6274 (set_attr "z196prop" "z196_cracked")])
6277 [(set (match_operand 0 "memory_operand" "")
6279 (match_operand 1 "memory_operand" "")))
6280 (clobber (reg:CC CC_REGNUM))]
6282 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6283 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6285 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6287 (clobber (reg:CC CC_REGNUM))])]
6289 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6290 operands[0] = adjust_address (operands[0], BLKmode, 0);
6291 operands[1] = adjust_address (operands[1], BLKmode, 0);
6296 [(set (match_operand:BLK 0 "memory_operand" "")
6297 (and:BLK (match_dup 0)
6298 (match_operand:BLK 1 "memory_operand" "")))
6299 (use (match_operand 2 "const_int_operand" ""))
6300 (clobber (reg:CC CC_REGNUM))])
6302 [(set (match_operand:BLK 3 "memory_operand" "")
6303 (and:BLK (match_dup 3)
6304 (match_operand:BLK 4 "memory_operand" "")))
6305 (use (match_operand 5 "const_int_operand" ""))
6306 (clobber (reg:CC CC_REGNUM))])]
6307 "s390_offset_p (operands[0], operands[3], operands[2])
6308 && s390_offset_p (operands[1], operands[4], operands[2])
6309 && !s390_overlap_p (operands[0], operands[1],
6310 INTVAL (operands[2]) + INTVAL (operands[5]))
6311 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6313 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6315 (clobber (reg:CC CC_REGNUM))])]
6316 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6317 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6318 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6322 ;;- Bit set (inclusive or) instructions.
6325 (define_expand "ior<mode>3"
6326 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6327 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6328 (match_operand:INT 2 "general_operand" "")))
6329 (clobber (reg:CC CC_REGNUM))]
6331 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6334 ; iordi3 instruction pattern(s).
6337 (define_insn "*iordi3_cc"
6338 [(set (reg CC_REGNUM)
6339 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6340 (match_operand:DI 2 "general_operand" " d,d,RT"))
6342 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6343 (ior:DI (match_dup 1) (match_dup 2)))]
6344 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6349 [(set_attr "op_type" "RRE,RRF,RXY")
6350 (set_attr "cpu_facility" "*,z196,*")
6351 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6353 (define_insn "*iordi3_cconly"
6354 [(set (reg CC_REGNUM)
6355 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6356 (match_operand:DI 2 "general_operand" " d,d,RT"))
6358 (clobber (match_scratch:DI 0 "=d,d,d"))]
6359 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6364 [(set_attr "op_type" "RRE,RRF,RXY")
6365 (set_attr "cpu_facility" "*,z196,*")
6366 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6368 (define_insn "*iordi3"
6369 [(set (match_operand:DI 0 "nonimmediate_operand"
6370 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6371 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6372 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6373 (match_operand:DI 2 "general_operand"
6374 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6375 (clobber (reg:CC CC_REGNUM))]
6376 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6389 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6390 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6391 (set_attr "z10prop" "z10_super_E1,
6404 [(set (match_operand:DI 0 "s_operand" "")
6405 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6406 (clobber (reg:CC CC_REGNUM))]
6409 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6410 (clobber (reg:CC CC_REGNUM))])]
6411 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6414 ; iorsi3 instruction pattern(s).
6417 (define_insn "*iorsi3_cc"
6418 [(set (reg CC_REGNUM)
6419 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6420 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6422 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6423 (ior:SI (match_dup 1) (match_dup 2)))]
6424 "s390_match_ccmode(insn, CCTmode)"
6431 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6432 (set_attr "cpu_facility" "*,*,z196,*,*")
6433 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6435 (define_insn "*iorsi3_cconly"
6436 [(set (reg CC_REGNUM)
6437 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6438 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6440 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6441 "s390_match_ccmode(insn, CCTmode)"
6448 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6449 (set_attr "cpu_facility" "*,*,z196,*,*")
6450 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6452 (define_insn "*iorsi3_zarch"
6453 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6454 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6455 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6456 (clobber (reg:CC CC_REGNUM))]
6457 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6468 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6469 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6470 (set_attr "z10prop" "z10_super_E1,
6480 (define_insn "*iorsi3_esa"
6481 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6482 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6483 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6484 (clobber (reg:CC CC_REGNUM))]
6485 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6491 [(set_attr "op_type" "RR,RX,SI,SS")
6492 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6495 [(set (match_operand:SI 0 "s_operand" "")
6496 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6497 (clobber (reg:CC CC_REGNUM))]
6500 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6501 (clobber (reg:CC CC_REGNUM))])]
6502 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6505 ; iorhi3 instruction pattern(s).
6508 (define_insn "*iorhi3_zarch"
6509 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6510 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6511 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6512 (clobber (reg:CC CC_REGNUM))]
6513 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6520 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6521 (set_attr "cpu_facility" "*,z196,*,*,*")
6522 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6524 (define_insn "*iorhi3_esa"
6525 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6526 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6527 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6528 (clobber (reg:CC CC_REGNUM))]
6529 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6534 [(set_attr "op_type" "RR,SI,SS")
6535 (set_attr "z10prop" "z10_super_E1,*,*")])
6538 [(set (match_operand:HI 0 "s_operand" "")
6539 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6540 (clobber (reg:CC CC_REGNUM))]
6543 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6544 (clobber (reg:CC CC_REGNUM))])]
6545 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6548 ; iorqi3 instruction pattern(s).
6551 (define_insn "*iorqi3_zarch"
6552 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6553 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6554 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6555 (clobber (reg:CC CC_REGNUM))]
6556 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6564 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6565 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6566 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6567 z10_super,z10_super,*")])
6569 (define_insn "*iorqi3_esa"
6570 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6571 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6572 (match_operand:QI 2 "general_operand" "d,n,Q")))
6573 (clobber (reg:CC CC_REGNUM))]
6574 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6579 [(set_attr "op_type" "RR,SI,SS")
6580 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6583 ; Block inclusive or (OC) patterns.
6587 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6588 (ior:BLK (match_dup 0)
6589 (match_operand:BLK 1 "memory_operand" "Q")))
6590 (use (match_operand 2 "const_int_operand" "n"))
6591 (clobber (reg:CC CC_REGNUM))]
6592 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6593 "oc\t%O0(%2,%R0),%S1"
6594 [(set_attr "op_type" "SS")
6595 (set_attr "z196prop" "z196_cracked")])
6598 [(set (match_operand 0 "memory_operand" "")
6600 (match_operand 1 "memory_operand" "")))
6601 (clobber (reg:CC CC_REGNUM))]
6603 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6604 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6606 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6608 (clobber (reg:CC CC_REGNUM))])]
6610 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6611 operands[0] = adjust_address (operands[0], BLKmode, 0);
6612 operands[1] = adjust_address (operands[1], BLKmode, 0);
6617 [(set (match_operand:BLK 0 "memory_operand" "")
6618 (ior:BLK (match_dup 0)
6619 (match_operand:BLK 1 "memory_operand" "")))
6620 (use (match_operand 2 "const_int_operand" ""))
6621 (clobber (reg:CC CC_REGNUM))])
6623 [(set (match_operand:BLK 3 "memory_operand" "")
6624 (ior:BLK (match_dup 3)
6625 (match_operand:BLK 4 "memory_operand" "")))
6626 (use (match_operand 5 "const_int_operand" ""))
6627 (clobber (reg:CC CC_REGNUM))])]
6628 "s390_offset_p (operands[0], operands[3], operands[2])
6629 && s390_offset_p (operands[1], operands[4], operands[2])
6630 && !s390_overlap_p (operands[0], operands[1],
6631 INTVAL (operands[2]) + INTVAL (operands[5]))
6632 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6634 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6636 (clobber (reg:CC CC_REGNUM))])]
6637 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6638 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6639 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6643 ;;- Xor instructions.
6646 (define_expand "xor<mode>3"
6647 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6648 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6649 (match_operand:INT 2 "general_operand" "")))
6650 (clobber (reg:CC CC_REGNUM))]
6652 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6655 ; xordi3 instruction pattern(s).
6658 (define_insn "*xordi3_cc"
6659 [(set (reg CC_REGNUM)
6660 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6661 (match_operand:DI 2 "general_operand" " d,d,RT"))
6663 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6664 (xor:DI (match_dup 1) (match_dup 2)))]
6665 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6670 [(set_attr "op_type" "RRE,RRF,RXY")
6671 (set_attr "cpu_facility" "*,z196,*")
6672 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6674 (define_insn "*xordi3_cconly"
6675 [(set (reg CC_REGNUM)
6676 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6677 (match_operand:DI 2 "general_operand" " d,d,RT"))
6679 (clobber (match_scratch:DI 0 "=d,d, d"))]
6680 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6685 [(set_attr "op_type" "RRE,RRF,RXY")
6686 (set_attr "cpu_facility" "*,z196,*")
6687 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6689 (define_insn "*xordi3"
6690 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6691 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6692 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6693 (clobber (reg:CC CC_REGNUM))]
6694 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6703 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6704 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6705 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6706 *,z10_super_E1,*,*")])
6709 [(set (match_operand:DI 0 "s_operand" "")
6710 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6711 (clobber (reg:CC CC_REGNUM))]
6714 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6715 (clobber (reg:CC CC_REGNUM))])]
6716 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6719 ; xorsi3 instruction pattern(s).
6722 (define_insn "*xorsi3_cc"
6723 [(set (reg CC_REGNUM)
6724 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6725 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6727 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6728 (xor:SI (match_dup 1) (match_dup 2)))]
6729 "s390_match_ccmode(insn, CCTmode)"
6736 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6737 (set_attr "cpu_facility" "*,*,z196,*,*")
6738 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6739 z10_super_E1,z10_super_E1")])
6741 (define_insn "*xorsi3_cconly"
6742 [(set (reg CC_REGNUM)
6743 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6744 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6746 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6747 "s390_match_ccmode(insn, CCTmode)"
6754 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6755 (set_attr "cpu_facility" "*,*,z196,*,*")
6756 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6757 z10_super_E1,z10_super_E1")])
6759 (define_insn "*xorsi3"
6760 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6761 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6762 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6763 (clobber (reg:CC CC_REGNUM))]
6764 "s390_logical_operator_ok_p (operands)"
6773 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6774 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6775 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6776 z10_super_E1,z10_super_E1,*,*")])
6779 [(set (match_operand:SI 0 "s_operand" "")
6780 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6781 (clobber (reg:CC CC_REGNUM))]
6784 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6785 (clobber (reg:CC CC_REGNUM))])]
6786 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6789 ; xorhi3 instruction pattern(s).
6792 (define_insn "*xorhi3"
6793 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6794 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6795 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6796 (clobber (reg:CC CC_REGNUM))]
6797 "s390_logical_operator_ok_p (operands)"
6804 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6805 (set_attr "cpu_facility" "*,*,z196,*,*")
6806 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6809 [(set (match_operand:HI 0 "s_operand" "")
6810 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6811 (clobber (reg:CC CC_REGNUM))]
6814 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6815 (clobber (reg:CC CC_REGNUM))])]
6816 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6819 ; xorqi3 instruction pattern(s).
6822 (define_insn "*xorqi3"
6823 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6824 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
6825 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
6826 (clobber (reg:CC CC_REGNUM))]
6827 "s390_logical_operator_ok_p (operands)"
6835 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
6836 (set_attr "cpu_facility" "*,*,z196,*,*,*")
6837 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
6841 ; Block exclusive or (XC) patterns.
6845 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6846 (xor:BLK (match_dup 0)
6847 (match_operand:BLK 1 "memory_operand" "Q")))
6848 (use (match_operand 2 "const_int_operand" "n"))
6849 (clobber (reg:CC CC_REGNUM))]
6850 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6851 "xc\t%O0(%2,%R0),%S1"
6852 [(set_attr "op_type" "SS")])
6855 [(set (match_operand 0 "memory_operand" "")
6857 (match_operand 1 "memory_operand" "")))
6858 (clobber (reg:CC CC_REGNUM))]
6860 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6861 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6863 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6865 (clobber (reg:CC CC_REGNUM))])]
6867 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6868 operands[0] = adjust_address (operands[0], BLKmode, 0);
6869 operands[1] = adjust_address (operands[1], BLKmode, 0);
6874 [(set (match_operand:BLK 0 "memory_operand" "")
6875 (xor:BLK (match_dup 0)
6876 (match_operand:BLK 1 "memory_operand" "")))
6877 (use (match_operand 2 "const_int_operand" ""))
6878 (clobber (reg:CC CC_REGNUM))])
6880 [(set (match_operand:BLK 3 "memory_operand" "")
6881 (xor:BLK (match_dup 3)
6882 (match_operand:BLK 4 "memory_operand" "")))
6883 (use (match_operand 5 "const_int_operand" ""))
6884 (clobber (reg:CC CC_REGNUM))])]
6885 "s390_offset_p (operands[0], operands[3], operands[2])
6886 && s390_offset_p (operands[1], operands[4], operands[2])
6887 && !s390_overlap_p (operands[0], operands[1],
6888 INTVAL (operands[2]) + INTVAL (operands[5]))
6889 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6891 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6893 (clobber (reg:CC CC_REGNUM))])]
6894 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6895 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6896 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6899 ; Block xor (XC) patterns with src == dest.
6902 (define_insn "*xc_zero"
6903 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6905 (use (match_operand 1 "const_int_operand" "n"))
6906 (clobber (reg:CC CC_REGNUM))]
6907 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6908 "xc\t%O0(%1,%R0),%S0"
6909 [(set_attr "op_type" "SS")
6910 (set_attr "z196prop" "z196_cracked")])
6914 [(set (match_operand:BLK 0 "memory_operand" "")
6916 (use (match_operand 1 "const_int_operand" ""))
6917 (clobber (reg:CC CC_REGNUM))])
6919 [(set (match_operand:BLK 2 "memory_operand" "")
6921 (use (match_operand 3 "const_int_operand" ""))
6922 (clobber (reg:CC CC_REGNUM))])]
6923 "s390_offset_p (operands[0], operands[2], operands[1])
6924 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6926 [(set (match_dup 4) (const_int 0))
6928 (clobber (reg:CC CC_REGNUM))])]
6929 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6930 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6934 ;;- Negate instructions.
6938 ; neg(di|si)2 instruction pattern(s).
6941 (define_expand "neg<mode>2"
6943 [(set (match_operand:DSI 0 "register_operand" "=d")
6944 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6945 (clobber (reg:CC CC_REGNUM))])]
6949 (define_insn "*negdi2_sign_cc"
6950 [(set (reg CC_REGNUM)
6951 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6952 (match_operand:SI 1 "register_operand" "d") 0)
6953 (const_int 32)) (const_int 32)))
6955 (set (match_operand:DI 0 "register_operand" "=d")
6956 (neg:DI (sign_extend:DI (match_dup 1))))]
6957 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6959 [(set_attr "op_type" "RRE")
6960 (set_attr "z10prop" "z10_c")])
6962 (define_insn "*negdi2_sign"
6963 [(set (match_operand:DI 0 "register_operand" "=d")
6964 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6965 (clobber (reg:CC CC_REGNUM))]
6968 [(set_attr "op_type" "RRE")
6969 (set_attr "z10prop" "z10_c")])
6972 (define_insn "*neg<mode>2_cc"
6973 [(set (reg CC_REGNUM)
6974 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6976 (set (match_operand:GPR 0 "register_operand" "=d")
6977 (neg:GPR (match_dup 1)))]
6978 "s390_match_ccmode (insn, CCAmode)"
6980 [(set_attr "op_type" "RR<E>")
6981 (set_attr "z10prop" "z10_super_c_E1")])
6984 (define_insn "*neg<mode>2_cconly"
6985 [(set (reg CC_REGNUM)
6986 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6988 (clobber (match_scratch:GPR 0 "=d"))]
6989 "s390_match_ccmode (insn, CCAmode)"
6991 [(set_attr "op_type" "RR<E>")
6992 (set_attr "z10prop" "z10_super_c_E1")])
6995 (define_insn "*neg<mode>2"
6996 [(set (match_operand:GPR 0 "register_operand" "=d")
6997 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6998 (clobber (reg:CC CC_REGNUM))]
7001 [(set_attr "op_type" "RR<E>")
7002 (set_attr "z10prop" "z10_super_c_E1")])
7004 (define_insn_and_split "*negdi2_31"
7005 [(set (match_operand:DI 0 "register_operand" "=d")
7006 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7007 (clobber (reg:CC CC_REGNUM))]
7010 "&& reload_completed"
7012 [(set (match_dup 2) (neg:SI (match_dup 3)))
7013 (clobber (reg:CC CC_REGNUM))])
7015 [(set (reg:CCAP CC_REGNUM)
7016 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7017 (set (match_dup 4) (neg:SI (match_dup 5)))])
7019 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7021 (label_ref (match_dup 6))))
7023 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7024 (clobber (reg:CC CC_REGNUM))])
7026 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7027 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7028 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7029 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7030 operands[6] = gen_label_rtx ();")
7033 ; neg(df|sf)2 instruction pattern(s).
7036 (define_expand "neg<mode>2"
7038 [(set (match_operand:BFP 0 "register_operand" "=f")
7039 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7040 (clobber (reg:CC CC_REGNUM))])]
7044 ; lcxbr, lcdbr, lcebr
7045 (define_insn "*neg<mode>2_cc"
7046 [(set (reg CC_REGNUM)
7047 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7048 (match_operand:BFP 2 "const0_operand" "")))
7049 (set (match_operand:BFP 0 "register_operand" "=f")
7050 (neg:BFP (match_dup 1)))]
7051 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7053 [(set_attr "op_type" "RRE")
7054 (set_attr "type" "fsimp<mode>")])
7056 ; lcxbr, lcdbr, lcebr
7057 (define_insn "*neg<mode>2_cconly"
7058 [(set (reg CC_REGNUM)
7059 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7060 (match_operand:BFP 2 "const0_operand" "")))
7061 (clobber (match_scratch:BFP 0 "=f"))]
7062 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7064 [(set_attr "op_type" "RRE")
7065 (set_attr "type" "fsimp<mode>")])
7068 (define_insn "*neg<mode>2_nocc"
7069 [(set (match_operand:FP 0 "register_operand" "=f")
7070 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7073 [(set_attr "op_type" "RRE")
7074 (set_attr "type" "fsimp<mode>")])
7076 ; lcxbr, lcdbr, lcebr
7077 (define_insn "*neg<mode>2"
7078 [(set (match_operand:BFP 0 "register_operand" "=f")
7079 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7080 (clobber (reg:CC CC_REGNUM))]
7083 [(set_attr "op_type" "RRE")
7084 (set_attr "type" "fsimp<mode>")])
7088 ;;- Absolute value instructions.
7092 ; abs(di|si)2 instruction pattern(s).
7095 (define_insn "*absdi2_sign_cc"
7096 [(set (reg CC_REGNUM)
7097 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7098 (match_operand:SI 1 "register_operand" "d") 0)
7099 (const_int 32)) (const_int 32)))
7101 (set (match_operand:DI 0 "register_operand" "=d")
7102 (abs:DI (sign_extend:DI (match_dup 1))))]
7103 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7105 [(set_attr "op_type" "RRE")
7106 (set_attr "z10prop" "z10_c")])
7108 (define_insn "*absdi2_sign"
7109 [(set (match_operand:DI 0 "register_operand" "=d")
7110 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7111 (clobber (reg:CC CC_REGNUM))]
7114 [(set_attr "op_type" "RRE")
7115 (set_attr "z10prop" "z10_c")])
7118 (define_insn "*abs<mode>2_cc"
7119 [(set (reg CC_REGNUM)
7120 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7122 (set (match_operand:GPR 0 "register_operand" "=d")
7123 (abs:GPR (match_dup 1)))]
7124 "s390_match_ccmode (insn, CCAmode)"
7126 [(set_attr "op_type" "RR<E>")
7127 (set_attr "z10prop" "z10_c")])
7130 (define_insn "*abs<mode>2_cconly"
7131 [(set (reg CC_REGNUM)
7132 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7134 (clobber (match_scratch:GPR 0 "=d"))]
7135 "s390_match_ccmode (insn, CCAmode)"
7137 [(set_attr "op_type" "RR<E>")
7138 (set_attr "z10prop" "z10_c")])
7141 (define_insn "abs<mode>2"
7142 [(set (match_operand:GPR 0 "register_operand" "=d")
7143 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7144 (clobber (reg:CC CC_REGNUM))]
7147 [(set_attr "op_type" "RR<E>")
7148 (set_attr "z10prop" "z10_c")])
7151 ; abs(df|sf)2 instruction pattern(s).
7154 (define_expand "abs<mode>2"
7156 [(set (match_operand:BFP 0 "register_operand" "=f")
7157 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7158 (clobber (reg:CC CC_REGNUM))])]
7162 ; lpxbr, lpdbr, lpebr
7163 (define_insn "*abs<mode>2_cc"
7164 [(set (reg CC_REGNUM)
7165 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7166 (match_operand:BFP 2 "const0_operand" "")))
7167 (set (match_operand:BFP 0 "register_operand" "=f")
7168 (abs:BFP (match_dup 1)))]
7169 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7171 [(set_attr "op_type" "RRE")
7172 (set_attr "type" "fsimp<mode>")])
7174 ; lpxbr, lpdbr, lpebr
7175 (define_insn "*abs<mode>2_cconly"
7176 [(set (reg CC_REGNUM)
7177 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7178 (match_operand:BFP 2 "const0_operand" "")))
7179 (clobber (match_scratch:BFP 0 "=f"))]
7180 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7182 [(set_attr "op_type" "RRE")
7183 (set_attr "type" "fsimp<mode>")])
7186 (define_insn "*abs<mode>2_nocc"
7187 [(set (match_operand:FP 0 "register_operand" "=f")
7188 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7191 [(set_attr "op_type" "RRE")
7192 (set_attr "type" "fsimp<mode>")])
7194 ; lpxbr, lpdbr, lpebr
7195 (define_insn "*abs<mode>2"
7196 [(set (match_operand:BFP 0 "register_operand" "=f")
7197 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7198 (clobber (reg:CC CC_REGNUM))]
7201 [(set_attr "op_type" "RRE")
7202 (set_attr "type" "fsimp<mode>")])
7206 ;;- Negated absolute value instructions
7213 (define_insn "*negabsdi2_sign_cc"
7214 [(set (reg CC_REGNUM)
7215 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7216 (match_operand:SI 1 "register_operand" "d") 0)
7217 (const_int 32)) (const_int 32))))
7219 (set (match_operand:DI 0 "register_operand" "=d")
7220 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7221 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7223 [(set_attr "op_type" "RRE")
7224 (set_attr "z10prop" "z10_c")])
7226 (define_insn "*negabsdi2_sign"
7227 [(set (match_operand:DI 0 "register_operand" "=d")
7228 (neg:DI (abs:DI (sign_extend:DI
7229 (match_operand:SI 1 "register_operand" "d")))))
7230 (clobber (reg:CC CC_REGNUM))]
7233 [(set_attr "op_type" "RRE")
7234 (set_attr "z10prop" "z10_c")])
7237 (define_insn "*negabs<mode>2_cc"
7238 [(set (reg CC_REGNUM)
7239 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7241 (set (match_operand:GPR 0 "register_operand" "=d")
7242 (neg:GPR (abs:GPR (match_dup 1))))]
7243 "s390_match_ccmode (insn, CCAmode)"
7245 [(set_attr "op_type" "RR<E>")
7246 (set_attr "z10prop" "z10_c")])
7249 (define_insn "*negabs<mode>2_cconly"
7250 [(set (reg CC_REGNUM)
7251 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7253 (clobber (match_scratch:GPR 0 "=d"))]
7254 "s390_match_ccmode (insn, CCAmode)"
7256 [(set_attr "op_type" "RR<E>")
7257 (set_attr "z10prop" "z10_c")])
7260 (define_insn "*negabs<mode>2"
7261 [(set (match_operand:GPR 0 "register_operand" "=d")
7262 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7263 (clobber (reg:CC CC_REGNUM))]
7266 [(set_attr "op_type" "RR<E>")
7267 (set_attr "z10prop" "z10_c")])
7273 ; lnxbr, lndbr, lnebr
7274 (define_insn "*negabs<mode>2_cc"
7275 [(set (reg CC_REGNUM)
7276 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7277 (match_operand:BFP 2 "const0_operand" "")))
7278 (set (match_operand:BFP 0 "register_operand" "=f")
7279 (neg:BFP (abs:BFP (match_dup 1))))]
7280 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7282 [(set_attr "op_type" "RRE")
7283 (set_attr "type" "fsimp<mode>")])
7285 ; lnxbr, lndbr, lnebr
7286 (define_insn "*negabs<mode>2_cconly"
7287 [(set (reg CC_REGNUM)
7288 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7289 (match_operand:BFP 2 "const0_operand" "")))
7290 (clobber (match_scratch:BFP 0 "=f"))]
7291 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7293 [(set_attr "op_type" "RRE")
7294 (set_attr "type" "fsimp<mode>")])
7297 (define_insn "*negabs<mode>2_nocc"
7298 [(set (match_operand:FP 0 "register_operand" "=f")
7299 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7302 [(set_attr "op_type" "RRE")
7303 (set_attr "type" "fsimp<mode>")])
7305 ; lnxbr, lndbr, lnebr
7306 (define_insn "*negabs<mode>2"
7307 [(set (match_operand:BFP 0 "register_operand" "=f")
7308 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7309 (clobber (reg:CC CC_REGNUM))]
7312 [(set_attr "op_type" "RRE")
7313 (set_attr "type" "fsimp<mode>")])
7316 ;;- Square root instructions.
7320 ; sqrt(df|sf)2 instruction pattern(s).
7323 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7324 (define_insn "sqrt<mode>2"
7325 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7326 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7331 [(set_attr "op_type" "RRE,RXE")
7332 (set_attr "type" "fsqrt<mode>")])
7336 ;;- One complement instructions.
7340 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7343 (define_expand "one_cmpl<mode>2"
7345 [(set (match_operand:INT 0 "register_operand" "")
7346 (xor:INT (match_operand:INT 1 "register_operand" "")
7348 (clobber (reg:CC CC_REGNUM))])]
7354 ;; Find leftmost bit instructions.
7357 (define_expand "clzdi2"
7358 [(set (match_operand:DI 0 "register_operand" "=d")
7359 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7360 "TARGET_EXTIMM && TARGET_ZARCH"
7362 rtx insn, clz_equal;
7363 rtx wide_reg = gen_reg_rtx (TImode);
7364 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7366 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7368 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7370 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7371 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7376 (define_insn "clztidi2"
7377 [(set (match_operand:TI 0 "register_operand" "=d")
7381 (xor:DI (match_operand:DI 1 "register_operand" "d")
7382 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7383 (subreg:SI (clz:DI (match_dup 1)) 4))))
7386 (zero_extend:TI (clz:DI (match_dup 1)))))
7387 (clobber (reg:CC CC_REGNUM))]
7388 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7389 == (unsigned HOST_WIDE_INT) 1 << 63
7390 && TARGET_EXTIMM && TARGET_ZARCH"
7392 [(set_attr "op_type" "RRE")])
7396 ;;- Rotate instructions.
7400 ; rotl(di|si)3 instruction pattern(s).
7404 (define_insn "rotl<mode>3"
7405 [(set (match_operand:GPR 0 "register_operand" "=d")
7406 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7407 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7410 [(set_attr "op_type" "RSE")
7411 (set_attr "atype" "reg")
7412 (set_attr "z10prop" "z10_super_E1")])
7415 (define_insn "*rotl<mode>3_and"
7416 [(set (match_operand:GPR 0 "register_operand" "=d")
7417 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7418 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7419 (match_operand:SI 3 "const_int_operand" "n"))))]
7420 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7422 [(set_attr "op_type" "RSE")
7423 (set_attr "atype" "reg")
7424 (set_attr "z10prop" "z10_super_E1")])
7428 ;;- Shift instructions.
7432 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7433 ; Left shifts and logical right shifts
7435 (define_expand "<shift><mode>3"
7436 [(set (match_operand:DSI 0 "register_operand" "")
7437 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7438 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7443 (define_insn "*<shift>di3_31"
7444 [(set (match_operand:DI 0 "register_operand" "=d")
7445 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7446 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7449 [(set_attr "op_type" "RS")
7450 (set_attr "atype" "reg")
7451 (set_attr "z196prop" "z196_cracked")])
7453 ; sll, srl, sllg, srlg, sllk, srlk
7454 (define_insn "*<shift><mode>3"
7455 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7456 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7457 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7460 s<lr>l<g>\t%0,<1>%Y2
7461 s<lr>l<gk>\t%0,%1,%Y2"
7462 [(set_attr "op_type" "RS<E>,RSY")
7463 (set_attr "atype" "reg,reg")
7464 (set_attr "cpu_facility" "*,z196")
7465 (set_attr "z10prop" "z10_super_E1,*")])
7468 (define_insn "*<shift>di3_31_and"
7469 [(set (match_operand:DI 0 "register_operand" "=d")
7470 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7471 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7472 (match_operand:SI 3 "const_int_operand" "n"))))]
7473 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7475 [(set_attr "op_type" "RS")
7476 (set_attr "atype" "reg")])
7478 ; sll, srl, sllg, srlg, sllk, srlk
7479 (define_insn "*<shift><mode>3_and"
7480 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7481 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7482 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7483 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7484 "(INTVAL (operands[3]) & 63) == 63"
7486 s<lr>l<g>\t%0,<1>%Y2
7487 s<lr>l<gk>\t%0,%1,%Y2"
7488 [(set_attr "op_type" "RS<E>,RSY")
7489 (set_attr "atype" "reg,reg")
7490 (set_attr "cpu_facility" "*,z196")
7491 (set_attr "z10prop" "z10_super_E1,*")])
7494 ; ashr(di|si)3 instruction pattern(s).
7495 ; Arithmetic right shifts
7497 (define_expand "ashr<mode>3"
7499 [(set (match_operand:DSI 0 "register_operand" "")
7500 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7501 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7502 (clobber (reg:CC CC_REGNUM))])]
7506 (define_insn "*ashrdi3_cc_31"
7507 [(set (reg CC_REGNUM)
7508 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7509 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7511 (set (match_operand:DI 0 "register_operand" "=d")
7512 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7513 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7515 [(set_attr "op_type" "RS")
7516 (set_attr "atype" "reg")])
7518 (define_insn "*ashrdi3_cconly_31"
7519 [(set (reg CC_REGNUM)
7520 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7521 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7523 (clobber (match_scratch:DI 0 "=d"))]
7524 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7526 [(set_attr "op_type" "RS")
7527 (set_attr "atype" "reg")])
7529 (define_insn "*ashrdi3_31"
7530 [(set (match_operand:DI 0 "register_operand" "=d")
7531 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7532 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7533 (clobber (reg:CC CC_REGNUM))]
7536 [(set_attr "op_type" "RS")
7537 (set_attr "atype" "reg")])
7540 (define_insn "*ashr<mode>3_cc"
7541 [(set (reg CC_REGNUM)
7542 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7543 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7545 (set (match_operand:GPR 0 "register_operand" "=d,d")
7546 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7547 "s390_match_ccmode(insn, CCSmode)"
7551 [(set_attr "op_type" "RS<E>,RSY")
7552 (set_attr "atype" "reg,reg")
7553 (set_attr "cpu_facility" "*,z196")
7554 (set_attr "z10prop" "z10_super_E1,*")])
7557 (define_insn "*ashr<mode>3_cconly"
7558 [(set (reg CC_REGNUM)
7559 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7560 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7562 (clobber (match_scratch:GPR 0 "=d,d"))]
7563 "s390_match_ccmode(insn, CCSmode)"
7567 [(set_attr "op_type" "RS<E>,RSY")
7568 (set_attr "atype" "reg,reg")
7569 (set_attr "cpu_facility" "*,z196")
7570 (set_attr "z10prop" "z10_super_E1,*")])
7573 (define_insn "*ashr<mode>3"
7574 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7575 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7576 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7577 (clobber (reg:CC CC_REGNUM))]
7582 [(set_attr "op_type" "RS<E>,RSY")
7583 (set_attr "atype" "reg,reg")
7584 (set_attr "cpu_facility" "*,z196")
7585 (set_attr "z10prop" "z10_super_E1,*")])
7588 ; shift pattern with implicit ANDs
7590 (define_insn "*ashrdi3_cc_31_and"
7591 [(set (reg CC_REGNUM)
7592 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7593 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7594 (match_operand:SI 3 "const_int_operand" "n")))
7596 (set (match_operand:DI 0 "register_operand" "=d")
7597 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7598 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7599 && (INTVAL (operands[3]) & 63) == 63"
7601 [(set_attr "op_type" "RS")
7602 (set_attr "atype" "reg")])
7604 (define_insn "*ashrdi3_cconly_31_and"
7605 [(set (reg CC_REGNUM)
7606 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7607 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7608 (match_operand:SI 3 "const_int_operand" "n")))
7610 (clobber (match_scratch:DI 0 "=d"))]
7611 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7612 && (INTVAL (operands[3]) & 63) == 63"
7614 [(set_attr "op_type" "RS")
7615 (set_attr "atype" "reg")])
7617 (define_insn "*ashrdi3_31_and"
7618 [(set (match_operand:DI 0 "register_operand" "=d")
7619 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7620 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7621 (match_operand:SI 3 "const_int_operand" "n"))))
7622 (clobber (reg:CC CC_REGNUM))]
7623 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7625 [(set_attr "op_type" "RS")
7626 (set_attr "atype" "reg")])
7629 (define_insn "*ashr<mode>3_cc_and"
7630 [(set (reg CC_REGNUM)
7631 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7632 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7633 (match_operand:SI 3 "const_int_operand" "n,n")))
7635 (set (match_operand:GPR 0 "register_operand" "=d,d")
7636 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7637 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7641 [(set_attr "op_type" "RS<E>,RSY")
7642 (set_attr "atype" "reg,reg")
7643 (set_attr "cpu_facility" "*,z196")
7644 (set_attr "z10prop" "z10_super_E1,*")])
7647 (define_insn "*ashr<mode>3_cconly_and"
7648 [(set (reg CC_REGNUM)
7649 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7650 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7651 (match_operand:SI 3 "const_int_operand" "n,n")))
7653 (clobber (match_scratch:GPR 0 "=d,d"))]
7654 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7658 [(set_attr "op_type" "RS<E>,RSY")
7659 (set_attr "atype" "reg,reg")
7660 (set_attr "cpu_facility" "*,z196")
7661 (set_attr "z10prop" "z10_super_E1,*")])
7664 (define_insn "*ashr<mode>3_and"
7665 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7666 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7667 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7668 (match_operand:SI 3 "const_int_operand" "n,n"))))
7669 (clobber (reg:CC CC_REGNUM))]
7670 "(INTVAL (operands[3]) & 63) == 63"
7674 [(set_attr "op_type" "RS<E>,RSY")
7675 (set_attr "atype" "reg,reg")
7676 (set_attr "cpu_facility" "*,z196")
7677 (set_attr "z10prop" "z10_super_E1,*")])
7681 ;; Branch instruction patterns.
7684 (define_expand "cbranch<mode>4"
7686 (if_then_else (match_operator 0 "comparison_operator"
7687 [(match_operand:GPR 1 "register_operand" "")
7688 (match_operand:GPR 2 "general_operand" "")])
7689 (label_ref (match_operand 3 "" ""))
7692 "s390_emit_jump (operands[3],
7693 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7696 (define_expand "cbranch<mode>4"
7698 (if_then_else (match_operator 0 "comparison_operator"
7699 [(match_operand:FP 1 "register_operand" "")
7700 (match_operand:FP 2 "general_operand" "")])
7701 (label_ref (match_operand 3 "" ""))
7704 "s390_emit_jump (operands[3],
7705 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7708 (define_expand "cbranchcc4"
7710 (if_then_else (match_operator 0 "s390_eqne_operator"
7711 [(match_operand 1 "cc_reg_operand" "")
7712 (match_operand 2 "const0_operand" "")])
7713 (label_ref (match_operand 3 "" ""))
7716 "s390_emit_jump (operands[3],
7717 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7723 ;;- Conditional jump instructions.
7726 (define_insn "*cjump_64"
7729 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7730 (label_ref (match_operand 0 "" ""))
7734 if (get_attr_length (insn) == 4)
7737 return "jg%C1\t%l0";
7739 [(set_attr "op_type" "RI")
7740 (set_attr "type" "branch")
7741 (set (attr "length")
7742 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7743 (const_int 4) (const_int 6)))])
7745 (define_insn "*cjump_31"
7748 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7749 (label_ref (match_operand 0 "" ""))
7753 gcc_assert (get_attr_length (insn) == 4);
7756 [(set_attr "op_type" "RI")
7757 (set_attr "type" "branch")
7758 (set (attr "length")
7759 (if_then_else (not (match_test "flag_pic"))
7760 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7761 (const_int 4) (const_int 6))
7762 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7763 (const_int 4) (const_int 8))))])
7765 (define_insn "*cjump_long"
7768 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7769 (match_operand 0 "address_operand" "ZQZR")
7773 if (get_attr_op_type (insn) == OP_TYPE_RR)
7778 [(set (attr "op_type")
7779 (if_then_else (match_operand 0 "register_operand" "")
7780 (const_string "RR") (const_string "RX")))
7781 (set_attr "type" "branch")
7782 (set_attr "atype" "agen")])
7786 ;;- Negated conditional jump instructions.
7789 (define_insn "*icjump_64"
7792 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7794 (label_ref (match_operand 0 "" ""))))]
7797 if (get_attr_length (insn) == 4)
7800 return "jg%D1\t%l0";
7802 [(set_attr "op_type" "RI")
7803 (set_attr "type" "branch")
7804 (set (attr "length")
7805 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7806 (const_int 4) (const_int 6)))])
7808 (define_insn "*icjump_31"
7811 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7813 (label_ref (match_operand 0 "" ""))))]
7816 gcc_assert (get_attr_length (insn) == 4);
7819 [(set_attr "op_type" "RI")
7820 (set_attr "type" "branch")
7821 (set (attr "length")
7822 (if_then_else (not (match_test "flag_pic"))
7823 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7824 (const_int 4) (const_int 6))
7825 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7826 (const_int 4) (const_int 8))))])
7828 (define_insn "*icjump_long"
7831 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7833 (match_operand 0 "address_operand" "ZQZR")))]
7836 if (get_attr_op_type (insn) == OP_TYPE_RR)
7841 [(set (attr "op_type")
7842 (if_then_else (match_operand 0 "register_operand" "")
7843 (const_string "RR") (const_string "RX")))
7844 (set_attr "type" "branch")
7845 (set_attr "atype" "agen")])
7848 ;;- Trap instructions.
7852 [(trap_if (const_int 1) (const_int 0))]
7855 [(set_attr "op_type" "RI")
7856 (set_attr "type" "branch")])
7858 (define_expand "ctrap<mode>4"
7859 [(trap_if (match_operator 0 "comparison_operator"
7860 [(match_operand:GPR 1 "register_operand" "")
7861 (match_operand:GPR 2 "general_operand" "")])
7862 (match_operand 3 "const0_operand" ""))]
7865 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7866 operands[1], operands[2]);
7867 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7871 (define_expand "ctrap<mode>4"
7872 [(trap_if (match_operator 0 "comparison_operator"
7873 [(match_operand:FP 1 "register_operand" "")
7874 (match_operand:FP 2 "general_operand" "")])
7875 (match_operand 3 "const0_operand" ""))]
7878 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7879 operands[1], operands[2]);
7880 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7884 (define_insn "condtrap"
7885 [(trap_if (match_operator 0 "s390_comparison"
7886 [(match_operand 1 "cc_reg_operand" "c")
7891 [(set_attr "op_type" "RI")
7892 (set_attr "type" "branch")])
7894 ; crt, cgrt, cit, cgit
7895 (define_insn "*cmp_and_trap_signed_int<mode>"
7896 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7897 [(match_operand:GPR 1 "register_operand" "d,d")
7898 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7904 [(set_attr "op_type" "RRF,RIE")
7905 (set_attr "type" "branch")
7906 (set_attr "z10prop" "z10_super_c,z10_super")])
7908 ; clrt, clgrt, clfit, clgit, clt, clgt
7909 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7910 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7911 [(match_operand:GPR 1 "register_operand" "d,d, d")
7912 (match_operand:GPR 2 "general_operand" "d,D,RT")])
7919 [(set_attr "op_type" "RRF,RIE,RSY")
7920 (set_attr "type" "branch")
7921 (set_attr "z10prop" "z10_super_c,z10_super,*")
7922 (set_attr "cpu_facility" "z10,z10,zEC12")])
7925 (define_insn "*load_and_trap<mode>"
7926 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
7929 (set (match_operand:GPR 1 "register_operand" "=d")
7933 [(set_attr "op_type" "RXY")])
7937 ;;- Loop instructions.
7939 ;; This is all complicated by the fact that since this is a jump insn
7940 ;; we must handle our own output reloads.
7944 ; This splitter will be matched by combine and has to add the 2 moves
7945 ; necessary to load the compare and the increment values into a
7946 ; register pair as needed by brxle.
7948 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7951 (match_operator 6 "s390_brx_operator"
7952 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
7953 (match_operand:GPR 2 "general_operand" ""))
7954 (match_operand:GPR 3 "register_operand" "")])
7955 (label_ref (match_operand 0 "" ""))
7957 (set (match_operand:GPR 4 "nonimmediate_operand" "")
7958 (plus:GPR (match_dup 1) (match_dup 2)))
7959 (clobber (match_scratch:GPR 5 ""))]
7962 "!reload_completed && !reload_in_progress"
7963 [(set (match_dup 7) (match_dup 2)) ; the increment
7964 (set (match_dup 8) (match_dup 3)) ; the comparison value
7965 (parallel [(set (pc)
7968 [(plus:GPR (match_dup 1) (match_dup 7))
7970 (label_ref (match_dup 0))
7973 (plus:GPR (match_dup 1) (match_dup 7)))
7974 (clobber (match_dup 5))
7975 (clobber (reg:CC CC_REGNUM))])]
7977 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
7978 operands[7] = gen_lowpart (<GPR:MODE>mode,
7979 gen_highpart (word_mode, dreg));
7980 operands[8] = gen_lowpart (<GPR:MODE>mode,
7981 gen_lowpart (word_mode, dreg));
7986 (define_insn_and_split "*brxg_64bit"
7989 (match_operator 5 "s390_brx_operator"
7990 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
7991 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
7992 (subreg:DI (match_dup 2) 8)])
7993 (label_ref (match_operand 0 "" ""))
7995 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
7996 (plus:DI (match_dup 1)
7997 (subreg:DI (match_dup 2) 0)))
7998 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
7999 (clobber (reg:CC CC_REGNUM))]
8002 if (which_alternative != 0)
8004 else if (get_attr_length (insn) == 6)
8005 return "brx%E5g\t%1,%2,%l0";
8007 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8009 "&& reload_completed
8010 && (!REG_P (operands[3])
8011 || !rtx_equal_p (operands[1], operands[3]))"
8012 [(set (match_dup 4) (match_dup 1))
8013 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8014 (clobber (reg:CC CC_REGNUM))])
8015 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8016 (set (match_dup 3) (match_dup 4))
8017 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8018 (label_ref (match_dup 0))
8021 [(set_attr "op_type" "RIE")
8022 (set_attr "type" "branch")
8023 (set (attr "length")
8024 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8025 (const_int 6) (const_int 16)))])
8029 (define_insn_and_split "*brx_64bit"
8032 (match_operator 5 "s390_brx_operator"
8033 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8034 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8035 (subreg:SI (match_dup 2) 12)])
8036 (label_ref (match_operand 0 "" ""))
8038 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8039 (plus:SI (match_dup 1)
8040 (subreg:SI (match_dup 2) 4)))
8041 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8042 (clobber (reg:CC CC_REGNUM))]
8045 if (which_alternative != 0)
8047 else if (get_attr_length (insn) == 6)
8048 return "brx%C5\t%1,%2,%l0";
8050 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8052 "&& reload_completed
8053 && (!REG_P (operands[3])
8054 || !rtx_equal_p (operands[1], operands[3]))"
8055 [(set (match_dup 4) (match_dup 1))
8056 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8057 (clobber (reg:CC CC_REGNUM))])
8058 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8059 (set (match_dup 3) (match_dup 4))
8060 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8061 (label_ref (match_dup 0))
8064 [(set_attr "op_type" "RSI")
8065 (set_attr "type" "branch")
8066 (set (attr "length")
8067 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8068 (const_int 6) (const_int 14)))])
8072 (define_insn_and_split "*brx_31bit"
8075 (match_operator 5 "s390_brx_operator"
8076 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8077 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8078 (subreg:SI (match_dup 2) 4)])
8079 (label_ref (match_operand 0 "" ""))
8081 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8082 (plus:SI (match_dup 1)
8083 (subreg:SI (match_dup 2) 0)))
8084 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8085 (clobber (reg:CC CC_REGNUM))]
8086 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8088 if (which_alternative != 0)
8090 else if (get_attr_length (insn) == 6)
8091 return "brx%C5\t%1,%2,%l0";
8093 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8095 "&& reload_completed
8096 && (!REG_P (operands[3])
8097 || !rtx_equal_p (operands[1], operands[3]))"
8098 [(set (match_dup 4) (match_dup 1))
8099 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8100 (clobber (reg:CC CC_REGNUM))])
8101 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8102 (set (match_dup 3) (match_dup 4))
8103 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8104 (label_ref (match_dup 0))
8107 [(set_attr "op_type" "RSI")
8108 (set_attr "type" "branch")
8109 (set (attr "length")
8110 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8111 (const_int 6) (const_int 14)))])
8116 (define_expand "doloop_end"
8117 [(use (match_operand 0 "" "")) ; loop pseudo
8118 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8119 (use (match_operand 2 "" "")) ; max iterations
8120 (use (match_operand 3 "" "")) ; loop level
8121 (use (match_operand 4 "" "")) ; label
8122 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
8125 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8126 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8127 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8128 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8129 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8130 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8137 (define_insn_and_split "doloop_si64"
8140 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8142 (label_ref (match_operand 0 "" ""))
8144 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8145 (plus:SI (match_dup 1) (const_int -1)))
8146 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8147 (clobber (reg:CC CC_REGNUM))]
8150 if (which_alternative != 0)
8152 else if (get_attr_length (insn) == 4)
8153 return "brct\t%1,%l0";
8155 return "ahi\t%1,-1\;jgne\t%l0";
8157 "&& reload_completed
8158 && (! REG_P (operands[2])
8159 || ! rtx_equal_p (operands[1], operands[2]))"
8160 [(set (match_dup 3) (match_dup 1))
8161 (parallel [(set (reg:CCAN CC_REGNUM)
8162 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8164 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8165 (set (match_dup 2) (match_dup 3))
8166 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8167 (label_ref (match_dup 0))
8170 [(set_attr "op_type" "RI")
8171 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8172 ; hurt us in the (rare) case of ahi.
8173 (set_attr "z10prop" "z10_super_E1")
8174 (set_attr "type" "branch")
8175 (set (attr "length")
8176 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8177 (const_int 4) (const_int 10)))])
8179 (define_insn_and_split "doloop_si31"
8182 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8184 (label_ref (match_operand 0 "" ""))
8186 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8187 (plus:SI (match_dup 1) (const_int -1)))
8188 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8189 (clobber (reg:CC CC_REGNUM))]
8192 if (which_alternative != 0)
8194 else if (get_attr_length (insn) == 4)
8195 return "brct\t%1,%l0";
8199 "&& reload_completed
8200 && (! REG_P (operands[2])
8201 || ! rtx_equal_p (operands[1], operands[2]))"
8202 [(set (match_dup 3) (match_dup 1))
8203 (parallel [(set (reg:CCAN CC_REGNUM)
8204 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8206 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8207 (set (match_dup 2) (match_dup 3))
8208 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8209 (label_ref (match_dup 0))
8212 [(set_attr "op_type" "RI")
8213 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8214 ; hurt us in the (rare) case of ahi.
8215 (set_attr "z10prop" "z10_super_E1")
8216 (set_attr "type" "branch")
8217 (set (attr "length")
8218 (if_then_else (not (match_test "flag_pic"))
8219 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8220 (const_int 4) (const_int 6))
8221 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8222 (const_int 4) (const_int 8))))])
8224 (define_insn "*doloop_si_long"
8227 (ne (match_operand:SI 1 "register_operand" "d")
8229 (match_operand 0 "address_operand" "ZQZR")
8231 (set (match_operand:SI 2 "register_operand" "=1")
8232 (plus:SI (match_dup 1) (const_int -1)))
8233 (clobber (match_scratch:SI 3 "=X"))
8234 (clobber (reg:CC CC_REGNUM))]
8237 if (get_attr_op_type (insn) == OP_TYPE_RR)
8238 return "bctr\t%1,%0";
8240 return "bct\t%1,%a0";
8242 [(set (attr "op_type")
8243 (if_then_else (match_operand 0 "register_operand" "")
8244 (const_string "RR") (const_string "RX")))
8245 (set_attr "type" "branch")
8246 (set_attr "atype" "agen")
8247 (set_attr "z10prop" "z10_c")
8248 (set_attr "z196prop" "z196_cracked")])
8250 (define_insn_and_split "doloop_di"
8253 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8255 (label_ref (match_operand 0 "" ""))
8257 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8258 (plus:DI (match_dup 1) (const_int -1)))
8259 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8260 (clobber (reg:CC CC_REGNUM))]
8263 if (which_alternative != 0)
8265 else if (get_attr_length (insn) == 4)
8266 return "brctg\t%1,%l0";
8268 return "aghi\t%1,-1\;jgne\t%l0";
8270 "&& reload_completed
8271 && (! REG_P (operands[2])
8272 || ! rtx_equal_p (operands[1], operands[2]))"
8273 [(set (match_dup 3) (match_dup 1))
8274 (parallel [(set (reg:CCAN CC_REGNUM)
8275 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8277 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8278 (set (match_dup 2) (match_dup 3))
8279 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8280 (label_ref (match_dup 0))
8283 [(set_attr "op_type" "RI")
8284 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8285 ; hurt us in the (rare) case of ahi.
8286 (set_attr "z10prop" "z10_super_E1")
8287 (set_attr "type" "branch")
8288 (set (attr "length")
8289 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8290 (const_int 4) (const_int 10)))])
8293 ;;- Unconditional jump instructions.
8297 ; jump instruction pattern(s).
8300 (define_expand "jump"
8301 [(match_operand 0 "" "")]
8303 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8305 (define_insn "*jump64"
8306 [(set (pc) (label_ref (match_operand 0 "" "")))]
8309 if (get_attr_length (insn) == 4)
8314 [(set_attr "op_type" "RI")
8315 (set_attr "type" "branch")
8316 (set (attr "length")
8317 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8318 (const_int 4) (const_int 6)))])
8320 (define_insn "*jump31"
8321 [(set (pc) (label_ref (match_operand 0 "" "")))]
8324 gcc_assert (get_attr_length (insn) == 4);
8327 [(set_attr "op_type" "RI")
8328 (set_attr "type" "branch")
8329 (set (attr "length")
8330 (if_then_else (not (match_test "flag_pic"))
8331 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8332 (const_int 4) (const_int 6))
8333 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8334 (const_int 4) (const_int 8))))])
8337 ; indirect-jump instruction pattern(s).
8340 (define_insn "indirect_jump"
8341 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8344 if (get_attr_op_type (insn) == OP_TYPE_RR)
8349 [(set (attr "op_type")
8350 (if_then_else (match_operand 0 "register_operand" "")
8351 (const_string "RR") (const_string "RX")))
8352 (set_attr "type" "branch")
8353 (set_attr "atype" "agen")])
8356 ; casesi instruction pattern(s).
8359 (define_insn "casesi_jump"
8360 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8361 (use (label_ref (match_operand 1 "" "")))]
8364 if (get_attr_op_type (insn) == OP_TYPE_RR)
8369 [(set (attr "op_type")
8370 (if_then_else (match_operand 0 "register_operand" "")
8371 (const_string "RR") (const_string "RX")))
8372 (set_attr "type" "branch")
8373 (set_attr "atype" "agen")])
8375 (define_expand "casesi"
8376 [(match_operand:SI 0 "general_operand" "")
8377 (match_operand:SI 1 "general_operand" "")
8378 (match_operand:SI 2 "general_operand" "")
8379 (label_ref (match_operand 3 "" ""))
8380 (label_ref (match_operand 4 "" ""))]
8383 rtx index = gen_reg_rtx (SImode);
8384 rtx base = gen_reg_rtx (Pmode);
8385 rtx target = gen_reg_rtx (Pmode);
8387 emit_move_insn (index, operands[0]);
8388 emit_insn (gen_subsi3 (index, index, operands[1]));
8389 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8392 if (Pmode != SImode)
8393 index = convert_to_mode (Pmode, index, 1);
8394 if (GET_CODE (index) != REG)
8395 index = copy_to_mode_reg (Pmode, index);
8398 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8400 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8402 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8404 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8405 emit_move_insn (target, index);
8408 target = gen_rtx_PLUS (Pmode, base, target);
8409 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8416 ;;- Jump to subroutine.
8421 ; untyped call instruction pattern(s).
8424 ;; Call subroutine returning any type.
8425 (define_expand "untyped_call"
8426 [(parallel [(call (match_operand 0 "" "")
8428 (match_operand 1 "" "")
8429 (match_operand 2 "" "")])]
8434 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8436 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8438 rtx set = XVECEXP (operands[2], 0, i);
8439 emit_move_insn (SET_DEST (set), SET_SRC (set));
8442 /* The optimizer does not know that the call sets the function value
8443 registers we stored in the result block. We avoid problems by
8444 claiming that all hard registers are used and clobbered at this
8446 emit_insn (gen_blockage ());
8451 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8452 ;; all of memory. This blocks insns from being moved across this point.
8454 (define_insn "blockage"
8455 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8458 [(set_attr "type" "none")
8459 (set_attr "length" "0")])
8465 (define_expand "sibcall"
8466 [(call (match_operand 0 "" "")
8467 (match_operand 1 "" ""))]
8470 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8474 (define_insn "*sibcall_br"
8475 [(call (mem:QI (reg SIBCALL_REGNUM))
8476 (match_operand 0 "const_int_operand" "n"))]
8477 "SIBLING_CALL_P (insn)
8478 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8480 [(set_attr "op_type" "RR")
8481 (set_attr "type" "branch")
8482 (set_attr "atype" "agen")])
8484 (define_insn "*sibcall_brc"
8485 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8486 (match_operand 1 "const_int_operand" "n"))]
8487 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8489 [(set_attr "op_type" "RI")
8490 (set_attr "type" "branch")])
8492 (define_insn "*sibcall_brcl"
8493 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8494 (match_operand 1 "const_int_operand" "n"))]
8495 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8497 [(set_attr "op_type" "RIL")
8498 (set_attr "type" "branch")])
8501 ; sibcall_value patterns
8504 (define_expand "sibcall_value"
8505 [(set (match_operand 0 "" "")
8506 (call (match_operand 1 "" "")
8507 (match_operand 2 "" "")))]
8510 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8514 (define_insn "*sibcall_value_br"
8515 [(set (match_operand 0 "" "")
8516 (call (mem:QI (reg SIBCALL_REGNUM))
8517 (match_operand 1 "const_int_operand" "n")))]
8518 "SIBLING_CALL_P (insn)
8519 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8521 [(set_attr "op_type" "RR")
8522 (set_attr "type" "branch")
8523 (set_attr "atype" "agen")])
8525 (define_insn "*sibcall_value_brc"
8526 [(set (match_operand 0 "" "")
8527 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8528 (match_operand 2 "const_int_operand" "n")))]
8529 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8531 [(set_attr "op_type" "RI")
8532 (set_attr "type" "branch")])
8534 (define_insn "*sibcall_value_brcl"
8535 [(set (match_operand 0 "" "")
8536 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8537 (match_operand 2 "const_int_operand" "n")))]
8538 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8540 [(set_attr "op_type" "RIL")
8541 (set_attr "type" "branch")])
8545 ; call instruction pattern(s).
8548 (define_expand "call"
8549 [(call (match_operand 0 "" "")
8550 (match_operand 1 "" ""))
8551 (use (match_operand 2 "" ""))]
8554 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8555 gen_rtx_REG (Pmode, RETURN_REGNUM));
8559 (define_insn "*bras"
8560 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8561 (match_operand 1 "const_int_operand" "n"))
8562 (clobber (match_operand 2 "register_operand" "=r"))]
8563 "!SIBLING_CALL_P (insn)
8564 && TARGET_SMALL_EXEC
8565 && GET_MODE (operands[2]) == Pmode"
8567 [(set_attr "op_type" "RI")
8568 (set_attr "type" "jsr")
8569 (set_attr "z196prop" "z196_cracked")])
8571 (define_insn "*brasl"
8572 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8573 (match_operand 1 "const_int_operand" "n"))
8574 (clobber (match_operand 2 "register_operand" "=r"))]
8575 "!SIBLING_CALL_P (insn)
8577 && GET_MODE (operands[2]) == Pmode"
8579 [(set_attr "op_type" "RIL")
8580 (set_attr "type" "jsr")
8581 (set_attr "z196prop" "z196_cracked")])
8583 (define_insn "*basr"
8584 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8585 (match_operand 1 "const_int_operand" "n"))
8586 (clobber (match_operand 2 "register_operand" "=r"))]
8587 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8589 if (get_attr_op_type (insn) == OP_TYPE_RR)
8590 return "basr\t%2,%0";
8592 return "bas\t%2,%a0";
8594 [(set (attr "op_type")
8595 (if_then_else (match_operand 0 "register_operand" "")
8596 (const_string "RR") (const_string "RX")))
8597 (set_attr "type" "jsr")
8598 (set_attr "atype" "agen")
8599 (set_attr "z196prop" "z196_cracked")])
8602 ; call_value instruction pattern(s).
8605 (define_expand "call_value"
8606 [(set (match_operand 0 "" "")
8607 (call (match_operand 1 "" "")
8608 (match_operand 2 "" "")))
8609 (use (match_operand 3 "" ""))]
8612 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8613 gen_rtx_REG (Pmode, RETURN_REGNUM));
8617 (define_insn "*bras_r"
8618 [(set (match_operand 0 "" "")
8619 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8620 (match_operand:SI 2 "const_int_operand" "n")))
8621 (clobber (match_operand 3 "register_operand" "=r"))]
8622 "!SIBLING_CALL_P (insn)
8623 && TARGET_SMALL_EXEC
8624 && GET_MODE (operands[3]) == Pmode"
8626 [(set_attr "op_type" "RI")
8627 (set_attr "type" "jsr")
8628 (set_attr "z196prop" "z196_cracked")])
8630 (define_insn "*brasl_r"
8631 [(set (match_operand 0 "" "")
8632 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8633 (match_operand 2 "const_int_operand" "n")))
8634 (clobber (match_operand 3 "register_operand" "=r"))]
8635 "!SIBLING_CALL_P (insn)
8637 && GET_MODE (operands[3]) == Pmode"
8639 [(set_attr "op_type" "RIL")
8640 (set_attr "type" "jsr")
8641 (set_attr "z196prop" "z196_cracked")])
8643 (define_insn "*basr_r"
8644 [(set (match_operand 0 "" "")
8645 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8646 (match_operand 2 "const_int_operand" "n")))
8647 (clobber (match_operand 3 "register_operand" "=r"))]
8648 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8650 if (get_attr_op_type (insn) == OP_TYPE_RR)
8651 return "basr\t%3,%1";
8653 return "bas\t%3,%a1";
8655 [(set (attr "op_type")
8656 (if_then_else (match_operand 1 "register_operand" "")
8657 (const_string "RR") (const_string "RX")))
8658 (set_attr "type" "jsr")
8659 (set_attr "atype" "agen")
8660 (set_attr "z196prop" "z196_cracked")])
8663 ;;- Thread-local storage support.
8666 (define_expand "get_thread_pointer<mode>"
8667 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8671 (define_expand "set_thread_pointer<mode>"
8672 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8673 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8677 (define_insn "*set_tp"
8678 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8681 [(set_attr "type" "none")
8682 (set_attr "length" "0")])
8684 (define_insn "*tls_load_64"
8685 [(set (match_operand:DI 0 "register_operand" "=d")
8686 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8687 (match_operand:DI 2 "" "")]
8691 [(set_attr "op_type" "RXE")
8692 (set_attr "z10prop" "z10_fwd_A3")])
8694 (define_insn "*tls_load_31"
8695 [(set (match_operand:SI 0 "register_operand" "=d,d")
8696 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8697 (match_operand:SI 2 "" "")]
8703 [(set_attr "op_type" "RX,RXY")
8704 (set_attr "type" "load")
8705 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8707 (define_insn "*bras_tls"
8708 [(set (match_operand 0 "" "")
8709 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8710 (match_operand 2 "const_int_operand" "n")))
8711 (clobber (match_operand 3 "register_operand" "=r"))
8712 (use (match_operand 4 "" ""))]
8713 "!SIBLING_CALL_P (insn)
8714 && TARGET_SMALL_EXEC
8715 && GET_MODE (operands[3]) == Pmode"
8717 [(set_attr "op_type" "RI")
8718 (set_attr "type" "jsr")
8719 (set_attr "z196prop" "z196_cracked")])
8721 (define_insn "*brasl_tls"
8722 [(set (match_operand 0 "" "")
8723 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8724 (match_operand 2 "const_int_operand" "n")))
8725 (clobber (match_operand 3 "register_operand" "=r"))
8726 (use (match_operand 4 "" ""))]
8727 "!SIBLING_CALL_P (insn)
8729 && GET_MODE (operands[3]) == Pmode"
8731 [(set_attr "op_type" "RIL")
8732 (set_attr "type" "jsr")
8733 (set_attr "z196prop" "z196_cracked")])
8735 (define_insn "*basr_tls"
8736 [(set (match_operand 0 "" "")
8737 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8738 (match_operand 2 "const_int_operand" "n")))
8739 (clobber (match_operand 3 "register_operand" "=r"))
8740 (use (match_operand 4 "" ""))]
8741 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8743 if (get_attr_op_type (insn) == OP_TYPE_RR)
8744 return "basr\t%3,%1%J4";
8746 return "bas\t%3,%a1%J4";
8748 [(set (attr "op_type")
8749 (if_then_else (match_operand 1 "register_operand" "")
8750 (const_string "RR") (const_string "RX")))
8751 (set_attr "type" "jsr")
8752 (set_attr "atype" "agen")
8753 (set_attr "z196prop" "z196_cracked")])
8756 ;;- Atomic operations
8760 ; memory barrier patterns.
8763 (define_expand "mem_signal_fence"
8764 [(match_operand:SI 0 "const_int_operand")] ;; model
8767 /* The s390 memory model is strong enough not to require any
8768 barrier in order to synchronize a thread with itself. */
8772 (define_expand "mem_thread_fence"
8773 [(match_operand:SI 0 "const_int_operand")] ;; model
8776 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8777 enough not to require barriers of any kind. */
8778 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
8780 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8781 MEM_VOLATILE_P (mem) = 1;
8782 emit_insn (gen_mem_thread_fence_1 (mem));
8787 ; Although bcr is superscalar on Z10, this variant will never
8788 ; become part of an execution group.
8789 (define_insn "mem_thread_fence_1"
8790 [(set (match_operand:BLK 0 "" "")
8791 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8794 [(set_attr "op_type" "RR")])
8797 ; atomic load/store operations
8800 ; Atomic loads need not examine the memory model at all.
8801 (define_expand "atomic_load<mode>"
8802 [(match_operand:DINT 0 "register_operand") ;; output
8803 (match_operand:DINT 1 "memory_operand") ;; memory
8804 (match_operand:SI 2 "const_int_operand")] ;; model
8807 if (<MODE>mode == TImode)
8808 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
8809 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8810 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
8812 emit_move_insn (operands[0], operands[1]);
8816 ; Different from movdi_31 in that we want no splitters.
8817 (define_insn "atomic_loaddi_1"
8818 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
8819 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
8827 [(set_attr "op_type" "RS,RSY,RS,RSY")
8828 (set_attr "type" "lm,lm,floaddf,floaddf")])
8830 (define_insn "atomic_loadti_1"
8831 [(set (match_operand:TI 0 "register_operand" "=r")
8832 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
8836 [(set_attr "op_type" "RXY")
8837 (set_attr "type" "other")])
8839 ; Atomic stores must(?) enforce sequential consistency.
8840 (define_expand "atomic_store<mode>"
8841 [(match_operand:DINT 0 "memory_operand") ;; memory
8842 (match_operand:DINT 1 "register_operand") ;; input
8843 (match_operand:SI 2 "const_int_operand")] ;; model
8846 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
8848 if (<MODE>mode == TImode)
8849 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
8850 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8851 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
8853 emit_move_insn (operands[0], operands[1]);
8854 if (model == MEMMODEL_SEQ_CST)
8855 emit_insn (gen_mem_thread_fence (operands[2]));
8859 ; Different from movdi_31 in that we want no splitters.
8860 (define_insn "atomic_storedi_1"
8861 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
8862 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
8870 [(set_attr "op_type" "RS,RSY,RS,RSY")
8871 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
8873 (define_insn "atomic_storeti_1"
8874 [(set (match_operand:TI 0 "memory_operand" "=RT")
8875 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
8879 [(set_attr "op_type" "RXY")
8880 (set_attr "type" "other")])
8883 ; compare and swap patterns.
8886 (define_expand "atomic_compare_and_swap<mode>"
8887 [(match_operand:SI 0 "register_operand") ;; bool success output
8888 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
8889 (match_operand:DGPR 2 "memory_operand") ;; memory
8890 (match_operand:DGPR 3 "register_operand") ;; expected intput
8891 (match_operand:DGPR 4 "register_operand") ;; newval intput
8892 (match_operand:SI 5 "const_int_operand") ;; is_weak
8893 (match_operand:SI 6 "const_int_operand") ;; success model
8894 (match_operand:SI 7 "const_int_operand")] ;; failure model
8897 rtx cc, cmp, output = operands[1];
8899 if (!register_operand (output, <MODE>mode))
8900 output = gen_reg_rtx (<MODE>mode);
8902 emit_insn (gen_atomic_compare_and_swap<mode>_internal
8903 (output, operands[2], operands[3], operands[4]));
8905 /* We deliberately accept non-register operands in the predicate
8906 to ensure the write back to the output operand happens *before*
8907 the store-flags code below. This makes it easier for combine
8908 to merge the store-flags code with a potential test-and-branch
8909 pattern following (immediately!) afterwards. */
8910 if (output != operands[1])
8911 emit_move_insn (operands[1], output);
8913 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
8914 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
8915 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
8919 (define_expand "atomic_compare_and_swap<mode>"
8920 [(match_operand:SI 0 "register_operand") ;; bool success output
8921 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
8922 (match_operand:HQI 2 "memory_operand") ;; memory
8923 (match_operand:HQI 3 "general_operand") ;; expected intput
8924 (match_operand:HQI 4 "general_operand") ;; newval intput
8925 (match_operand:SI 5 "const_int_operand") ;; is_weak
8926 (match_operand:SI 6 "const_int_operand") ;; success model
8927 (match_operand:SI 7 "const_int_operand")] ;; failure model
8930 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
8931 operands[3], operands[4], INTVAL (operands[5]));
8935 (define_expand "atomic_compare_and_swap<mode>_internal"
8937 [(set (match_operand:DGPR 0 "register_operand")
8938 (match_operand:DGPR 1 "memory_operand"))
8940 (unspec_volatile:DGPR
8942 (match_operand:DGPR 2 "register_operand")
8943 (match_operand:DGPR 3 "register_operand")]
8945 (set (reg:CCZ1 CC_REGNUM)
8946 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8950 (define_insn "*atomic_compare_and_swap<mode>_1"
8951 [(set (match_operand:TDI 0 "register_operand" "=r")
8952 (match_operand:TDI 1 "memory_operand" "+QS"))
8954 (unspec_volatile:TDI
8956 (match_operand:TDI 2 "register_operand" "0")
8957 (match_operand:TDI 3 "register_operand" "r")]
8959 (set (reg:CCZ1 CC_REGNUM)
8960 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8962 "c<td>sg\t%0,%3,%S1"
8963 [(set_attr "op_type" "RSY")
8964 (set_attr "type" "sem")])
8967 (define_insn "*atomic_compare_and_swapdi_2"
8968 [(set (match_operand:DI 0 "register_operand" "=r,r")
8969 (match_operand:DI 1 "memory_operand" "+Q,S"))
8973 (match_operand:DI 2 "register_operand" "0,0")
8974 (match_operand:DI 3 "register_operand" "r,r")]
8976 (set (reg:CCZ1 CC_REGNUM)
8977 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8982 [(set_attr "op_type" "RS,RSY")
8983 (set_attr "type" "sem")])
8986 (define_insn "*atomic_compare_and_swapsi_3"
8987 [(set (match_operand:SI 0 "register_operand" "=r,r")
8988 (match_operand:SI 1 "memory_operand" "+Q,S"))
8992 (match_operand:SI 2 "register_operand" "0,0")
8993 (match_operand:SI 3 "register_operand" "r,r")]
8995 (set (reg:CCZ1 CC_REGNUM)
8996 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9001 [(set_attr "op_type" "RS,RSY")
9002 (set_attr "type" "sem")])
9005 ; Other atomic instruction patterns.
9008 ; z196 load and add, xor, or and and instructions
9010 (define_expand "atomic_fetch_<atomic><mode>"
9011 [(match_operand:GPR 0 "register_operand") ;; val out
9013 (match_operand:GPR 1 "memory_operand") ;; memory
9014 (match_operand:GPR 2 "register_operand")) ;; val in
9015 (match_operand:SI 3 "const_int_operand")] ;; model
9018 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9019 (operands[0], operands[1], operands[2]));
9023 ; lan, lang, lao, laog, lax, laxg, laa, laag
9024 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9025 [(set (match_operand:GPR 0 "register_operand" "=d")
9026 (match_operand:GPR 1 "memory_operand" "+QS"))
9028 (unspec_volatile:GPR
9029 [(ATOMIC_Z196:GPR (match_dup 1)
9030 (match_operand:GPR 2 "general_operand" "d"))]
9032 (clobber (reg:CC CC_REGNUM))]
9034 "la<noxa><g>\t%0,%2,%1"
9035 [(set_attr "op_type" "RSY")
9036 (set_attr "type" "sem")])
9038 ;; For SImode and larger, the optabs.c code will do just fine in
9039 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9040 ;; better by expanding our own loop.
9042 (define_expand "atomic_<atomic><mode>"
9044 (match_operand:HQI 0 "memory_operand") ;; memory
9045 (match_operand:HQI 1 "general_operand")) ;; val in
9046 (match_operand:SI 2 "const_int_operand")] ;; model
9049 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9050 operands[1], false);
9054 (define_expand "atomic_fetch_<atomic><mode>"
9055 [(match_operand:HQI 0 "register_operand") ;; val out
9057 (match_operand:HQI 1 "memory_operand") ;; memory
9058 (match_operand:HQI 2 "general_operand")) ;; val in
9059 (match_operand:SI 3 "const_int_operand")] ;; model
9062 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9063 operands[2], false);
9067 (define_expand "atomic_<atomic>_fetch<mode>"
9068 [(match_operand:HQI 0 "register_operand") ;; val out
9070 (match_operand:HQI 1 "memory_operand") ;; memory
9071 (match_operand:HQI 2 "general_operand")) ;; val in
9072 (match_operand:SI 3 "const_int_operand")] ;; model
9075 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9080 (define_expand "atomic_exchange<mode>"
9081 [(match_operand:HQI 0 "register_operand") ;; val out
9082 (match_operand:HQI 1 "memory_operand") ;; memory
9083 (match_operand:HQI 2 "general_operand") ;; val in
9084 (match_operand:SI 3 "const_int_operand")] ;; model
9087 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9088 operands[2], false);
9093 ;;- Miscellaneous instructions.
9097 ; allocate stack instruction pattern(s).
9100 (define_expand "allocate_stack"
9101 [(match_operand 0 "general_operand" "")
9102 (match_operand 1 "general_operand" "")]
9105 rtx temp = gen_reg_rtx (Pmode);
9107 emit_move_insn (temp, s390_back_chain_rtx ());
9108 anti_adjust_stack (operands[1]);
9109 emit_move_insn (s390_back_chain_rtx (), temp);
9111 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9117 ; setjmp instruction pattern.
9120 (define_expand "builtin_setjmp_receiver"
9121 [(match_operand 0 "" "")]
9124 emit_insn (s390_load_got ());
9125 emit_use (pic_offset_table_rtx);
9129 ;; These patterns say how to save and restore the stack pointer. We need not
9130 ;; save the stack pointer at function level since we are careful to
9131 ;; preserve the backchain. At block level, we have to restore the backchain
9132 ;; when we restore the stack pointer.
9134 ;; For nonlocal gotos, we must save both the stack pointer and its
9135 ;; backchain and restore both. Note that in the nonlocal case, the
9136 ;; save area is a memory location.
9138 (define_expand "save_stack_function"
9139 [(match_operand 0 "general_operand" "")
9140 (match_operand 1 "general_operand" "")]
9144 (define_expand "restore_stack_function"
9145 [(match_operand 0 "general_operand" "")
9146 (match_operand 1 "general_operand" "")]
9150 (define_expand "restore_stack_block"
9151 [(match_operand 0 "register_operand" "")
9152 (match_operand 1 "register_operand" "")]
9155 rtx temp = gen_reg_rtx (Pmode);
9157 emit_move_insn (temp, s390_back_chain_rtx ());
9158 emit_move_insn (operands[0], operands[1]);
9159 emit_move_insn (s390_back_chain_rtx (), temp);
9164 (define_expand "save_stack_nonlocal"
9165 [(match_operand 0 "memory_operand" "")
9166 (match_operand 1 "register_operand" "")]
9169 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9171 /* Copy the backchain to the first word, sp to the second and the
9172 literal pool base to the third. */
9174 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9175 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9176 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9178 if (TARGET_BACKCHAIN)
9179 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9181 emit_move_insn (save_sp, operands[1]);
9182 emit_move_insn (save_bp, base);
9187 (define_expand "restore_stack_nonlocal"
9188 [(match_operand 0 "register_operand" "")
9189 (match_operand 1 "memory_operand" "")]
9192 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9193 rtx temp = NULL_RTX;
9195 /* Restore the backchain from the first word, sp from the second and the
9196 literal pool base from the third. */
9198 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9199 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9200 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9202 if (TARGET_BACKCHAIN)
9203 temp = force_reg (Pmode, save_bc);
9205 emit_move_insn (base, save_bp);
9206 emit_move_insn (operands[0], save_sp);
9209 emit_move_insn (s390_back_chain_rtx (), temp);
9215 (define_expand "exception_receiver"
9219 s390_set_has_landing_pad_p (true);
9224 ; nop instruction pattern(s).
9231 [(set_attr "op_type" "RR")
9232 (set_attr "z10prop" "z10_fr_E1")])
9238 [(set_attr "op_type" "RR")])
9242 ; Special literal pool access instruction pattern(s).
9245 (define_insn "*pool_entry"
9246 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9247 UNSPECV_POOL_ENTRY)]
9250 enum machine_mode mode = GET_MODE (PATTERN (insn));
9251 unsigned int align = GET_MODE_BITSIZE (mode);
9252 s390_output_pool_entry (operands[0], mode, align);
9255 [(set (attr "length")
9256 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9258 (define_insn "pool_align"
9259 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9260 UNSPECV_POOL_ALIGN)]
9263 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9265 (define_insn "pool_section_start"
9266 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9269 [(set_attr "length" "0")])
9271 (define_insn "pool_section_end"
9272 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9275 [(set_attr "length" "0")])
9277 (define_insn "main_base_31_small"
9278 [(set (match_operand 0 "register_operand" "=a")
9279 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9280 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9282 [(set_attr "op_type" "RR")
9283 (set_attr "type" "la")
9284 (set_attr "z196prop" "z196_cracked")])
9286 (define_insn "main_base_31_large"
9287 [(set (match_operand 0 "register_operand" "=a")
9288 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9289 (set (pc) (label_ref (match_operand 2 "" "")))]
9290 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9292 [(set_attr "op_type" "RI")
9293 (set_attr "z196prop" "z196_cracked")])
9295 (define_insn "main_base_64"
9296 [(set (match_operand 0 "register_operand" "=a")
9297 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9298 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9300 [(set_attr "op_type" "RIL")
9301 (set_attr "type" "larl")
9302 (set_attr "z10prop" "z10_fwd_A1")])
9304 (define_insn "main_pool"
9305 [(set (match_operand 0 "register_operand" "=a")
9306 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9307 "GET_MODE (operands[0]) == Pmode"
9312 (if_then_else (match_test "TARGET_CPU_ZARCH")
9313 (const_string "larl") (const_string "la")))])
9315 (define_insn "reload_base_31"
9316 [(set (match_operand 0 "register_operand" "=a")
9317 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9318 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9319 "basr\t%0,0\;la\t%0,%1-.(%0)"
9320 [(set_attr "length" "6")
9321 (set_attr "type" "la")
9322 (set_attr "z196prop" "z196_cracked")])
9324 (define_insn "reload_base_64"
9325 [(set (match_operand 0 "register_operand" "=a")
9326 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9327 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9329 [(set_attr "op_type" "RIL")
9330 (set_attr "type" "larl")
9331 (set_attr "z10prop" "z10_fwd_A1")])
9334 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9339 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9342 ;; Insns related to generating the function prologue and epilogue.
9346 (define_expand "prologue"
9347 [(use (const_int 0))]
9349 "s390_emit_prologue (); DONE;")
9351 (define_expand "epilogue"
9352 [(use (const_int 1))]
9354 "s390_emit_epilogue (false); DONE;")
9356 (define_expand "sibcall_epilogue"
9357 [(use (const_int 0))]
9359 "s390_emit_epilogue (true); DONE;")
9361 (define_insn "*return"
9363 (use (match_operand 0 "register_operand" "a"))]
9364 "GET_MODE (operands[0]) == Pmode"
9366 [(set_attr "op_type" "RR")
9367 (set_attr "type" "jsr")
9368 (set_attr "atype" "agen")])
9371 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9372 ;; pointer. This is used for compatibility.
9374 (define_expand "ptr_extend"
9375 [(set (match_operand:DI 0 "register_operand" "=r")
9376 (match_operand:SI 1 "register_operand" "r"))]
9379 emit_insn (gen_anddi3 (operands[0],
9380 gen_lowpart (DImode, operands[1]),
9381 GEN_INT (0x7fffffff)));
9385 ;; Instruction definition to expand eh_return macro to support
9386 ;; swapping in special linkage return addresses.
9388 (define_expand "eh_return"
9389 [(use (match_operand 0 "register_operand" ""))]
9392 s390_emit_tpf_eh_return (operands[0]);
9397 ; Stack Protector Patterns
9400 (define_expand "stack_protect_set"
9401 [(set (match_operand 0 "memory_operand" "")
9402 (match_operand 1 "memory_operand" ""))]
9405 #ifdef TARGET_THREAD_SSP_OFFSET
9407 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9408 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9411 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9413 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9418 (define_insn "stack_protect_set<mode>"
9419 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9420 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9422 "mvc\t%O0(%G0,%R0),%S1"
9423 [(set_attr "op_type" "SS")])
9425 (define_expand "stack_protect_test"
9426 [(set (reg:CC CC_REGNUM)
9427 (compare (match_operand 0 "memory_operand" "")
9428 (match_operand 1 "memory_operand" "")))
9429 (match_operand 2 "" "")]
9433 #ifdef TARGET_THREAD_SSP_OFFSET
9435 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9436 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9439 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9441 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9443 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9444 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9445 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9449 (define_insn "stack_protect_test<mode>"
9450 [(set (reg:CCZ CC_REGNUM)
9451 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9452 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9454 "clc\t%O0(%G0,%R0),%S1"
9455 [(set_attr "op_type" "SS")])
9457 ; This is used in s390_emit_prologue in order to prevent insns
9458 ; adjusting the stack pointer to be moved over insns writing stack
9459 ; slots using a copy of the stack pointer in a different register.
9460 (define_insn "stack_tie"
9461 [(set (match_operand:BLK 0 "memory_operand" "+m")
9462 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9465 [(set_attr "length" "0")])
9469 ; Data prefetch patterns
9472 (define_insn "prefetch"
9473 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9474 (match_operand:SI 1 "const_int_operand" " n,n")
9475 (match_operand:SI 2 "const_int_operand" " n,n"))]
9478 switch (which_alternative)
9481 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9483 if (larl_operand (operands[0], Pmode))
9484 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9487 /* This might be reached for symbolic operands with an odd
9488 addend. We simply omit the prefetch for such rare cases. */
9493 [(set_attr "type" "load,larl")
9494 (set_attr "op_type" "RXY,RIL")
9495 (set_attr "z10prop" "z10_super")
9496 (set_attr "z196prop" "z196_alone")])
9500 ; Byte swap instructions
9503 (define_insn "bswap<mode>2"
9504 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9505 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9510 [(set_attr "type" "*,load")
9511 (set_attr "op_type" "RRE,RXY")
9512 (set_attr "z10prop" "z10_super")])
9516 ; Population count instruction
9519 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9520 ; portions and stores the result in the corresponding bytes in op0.
9521 (define_insn "*popcount<mode>"
9522 [(set (match_operand:INT 0 "register_operand" "=d")
9523 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9524 (clobber (reg:CC CC_REGNUM))]
9527 [(set_attr "op_type" "RRE")])
9529 (define_expand "popcountdi2"
9531 (parallel [(set (match_operand:DI 0 "register_operand" "")
9532 (unspec:DI [(match_operand:DI 1 "register_operand")]
9534 (clobber (reg:CC CC_REGNUM))])
9536 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9538 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9539 (clobber (reg:CC CC_REGNUM))])
9542 (ashift:DI (match_dup 0) (const_int 16)))
9544 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9545 (clobber (reg:CC CC_REGNUM))])
9547 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9549 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9550 (clobber (reg:CC CC_REGNUM))])
9552 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9553 "TARGET_Z196 && TARGET_64BIT"
9554 "operands[2] = gen_reg_rtx (DImode);")
9556 (define_expand "popcountsi2"
9558 (parallel [(set (match_operand:SI 0 "register_operand" "")
9559 (unspec:SI [(match_operand:SI 1 "register_operand")]
9561 (clobber (reg:CC CC_REGNUM))])
9564 (ashift:SI (match_dup 0) (const_int 16)))
9566 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9567 (clobber (reg:CC CC_REGNUM))])
9569 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9571 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9572 (clobber (reg:CC CC_REGNUM))])
9574 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9576 "operands[2] = gen_reg_rtx (SImode);")
9578 (define_expand "popcounthi2"
9580 (parallel [(set (match_operand:HI 0 "register_operand" "")
9581 (unspec:HI [(match_operand:HI 1 "register_operand")]
9583 (clobber (reg:CC CC_REGNUM))])
9586 (ashift:SI (match_dup 0) (const_int 8)))
9588 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9589 (clobber (reg:CC CC_REGNUM))])
9591 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9593 "operands[2] = gen_reg_rtx (SImode);")
9595 (define_expand "popcountqi2"
9597 (parallel [(set (match_operand:QI 0 "register_operand" "")
9598 (unspec:QI [(match_operand:QI 1 "register_operand")]
9600 (clobber (reg:CC CC_REGNUM))])]
9605 ;;- Copy sign instructions
9608 (define_insn "copysign<mode>3"
9609 [(set (match_operand:FP 0 "register_operand" "=f")
9610 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9611 (match_operand:FP 2 "register_operand" "f")]
9615 [(set_attr "op_type" "RRF")
9616 (set_attr "type" "fsimp<mode>")])