1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2017 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; The right hand side of an setmem
76 ; GOT/PLT and lt-relative accesses
97 ; TLS relocation specifiers
113 ; Stack Smashing Protector
117 ; Split stack support
120 ; Test Data Class (TDC)
132 UNSPEC_FPINT_NEARBYINT
141 UNSPEC_VEC_SMULT_EVEN
142 UNSPEC_VEC_UMULT_EVEN
156 UNSPEC_VEC_INSERT_AND_ZERO
157 UNSPEC_VEC_LOAD_BNDRY
162 UNSPEC_VEC_PACK_SATURATE
163 UNSPEC_VEC_PACK_SATURATE_CC
164 UNSPEC_VEC_PACK_SATURATE_GENCC
165 UNSPEC_VEC_PACK_UNSIGNED_SATURATE
166 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
167 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
178 UNSPEC_VEC_ADDEC_U128
183 UNSPEC_VEC_GFMSUM_128
184 UNSPEC_VEC_GFMSUM_ACCUM
185 UNSPEC_VEC_GFMSUM_ACCUM_128
202 UNSPEC_VEC_SUBEC_U128
236 ;; UNSPEC_VOLATILE usage
239 (define_c_enum "unspecv" [
261 ; Hotpatching (unremovable NOPs)
266 ; Transactional Execution support
276 ; Set and get floating point control register
280 ; Split stack support
281 UNSPECV_SPLIT_STACK_CALL
282 UNSPECV_SPLIT_STACK_DATA
291 ; Registers with special meaning
295 ; Sibling call register.
297 ; Literal pool base register.
299 ; Return address register.
301 ; Stack pointer register.
303 ; Condition code register.
305 ; Thread local storage pointer register.
309 ; Hardware register names
313 ; General purpose registers
318 ; Floating point registers.
342 ; Rounding modes for binary floating point numbers
345 (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
346 (BFP_RND_PREP_FOR_SHORT_PREC 3)
347 (BFP_RND_NEAREST_TIE_TO_EVEN 4)
349 (BFP_RND_TOWARD_INF 6)
350 (BFP_RND_TOWARD_MINF 7)])
352 ; Rounding modes for decimal floating point numbers
353 ; 1-7 were introduced with the floating point extension facility
354 ; available with z196
355 ; With these rounding modes (1-7) a quantum exception might occur
356 ; which is suppressed for the other modes.
359 (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
360 (DFP_RND_CURRENT_QUANTEXC 2)
361 (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3)
362 (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4)
363 (DFP_RND_TOWARD_0_QUANTEXC 5)
364 (DFP_RND_TOWARD_INF_QUANTEXC 6)
365 (DFP_RND_TOWARD_MINF_QUANTEXC 7)
366 (DFP_RND_NEAREST_TIE_TO_EVEN 8)
368 (DFP_RND_TOWARD_INF 10)
369 (DFP_RND_TOWARD_MINF 11)
370 (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12)
371 (DFP_RND_NEAREST_TIE_TO_0 13)
372 (DFP_RND_AWAY_FROM_0 14)
373 (DFP_RND_PREP_FOR_SHORT_PREC 15)])
376 ;; PFPO GPR0 argument format
381 ; PFPO operation type
382 (PFPO_CONVERT 0x1000000)
384 (PFPO_OP_TYPE_SF 0x5)
385 (PFPO_OP_TYPE_DF 0x6)
386 (PFPO_OP_TYPE_TF 0x7)
387 (PFPO_OP_TYPE_SD 0x8)
388 (PFPO_OP_TYPE_DD 0x9)
389 (PFPO_OP_TYPE_TD 0xa)
390 ; Bitposition of operand types
391 (PFPO_OP0_TYPE_SHIFT 16)
392 (PFPO_OP1_TYPE_SHIFT 8)
395 ; Immediate operands for tbegin and tbeginc
396 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
397 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
399 ;; Instruction operand type as used in the Principles of Operation.
400 ;; Used to determine defaults for length and other attribute values.
402 (define_attr "op_type"
403 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
406 ;; Instruction type attribute used for scheduling.
408 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
409 cs,vs,store,sem,idiv,
410 imulhi,imulsi,imuldi,
411 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
412 floadtf,floaddf,floadsf,fstoredf,fstoresf,
413 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
414 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
416 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
417 itoftf, itofdf, itofsf, itofdd, itoftd,
418 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
419 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
421 (cond [(eq_attr "op_type" "NN") (const_string "other")
422 (eq_attr "op_type" "SS") (const_string "cs")]
423 (const_string "integer")))
425 ;; Another attribute used for scheduling purposes:
426 ;; agen: Instruction uses the address generation unit
427 ;; reg: Instruction does not use the agen unit
429 (define_attr "atype" "agen,reg"
430 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
432 (const_string "agen")))
434 ;; Properties concerning Z10 execution grouping and value forwarding.
435 ;; z10_super: instruction is superscalar.
436 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
437 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
438 ;; target register. It can forward this value to a second instruction that reads
439 ;; the same register if that second instruction is issued in the same group.
440 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
441 ;; instruction in the S pipe writes to the register, then the T instruction
442 ;; can immediately read the new value.
443 ;; z10_fr: union of Z10_fwd and z10_rec.
444 ;; z10_c: second operand of instruction is a register and read with complemented bits.
446 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
449 (define_attr "z10prop" "none,
450 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
451 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
453 z10_fr, z10_fr_A3, z10_fr_E1,
455 (const_string "none"))
457 ;; Properties concerning Z196 decoding
458 ;; z196_alone: must group alone
459 ;; z196_end: ends a group
460 ;; z196_cracked: instruction is cracked or expanded
461 (define_attr "z196prop" "none,
462 z196_alone, z196_ends,
464 (const_string "none"))
466 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
470 (define_attr "length" ""
471 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
472 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)]
476 ;; Processor type. This attribute must exactly match the processor_type
477 ;; enumeration in s390.h. The current machine description does not
478 ;; distinguish between g5 and g6, but there are differences between the two
479 ;; CPUs could in theory be modeled.
481 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
482 (const (symbol_ref "s390_tune_attr")))
484 (define_attr "cpu_facility"
485 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13"
486 (const_string "standard"))
488 (define_attr "enabled" ""
489 (cond [(eq_attr "cpu_facility" "standard")
492 (and (eq_attr "cpu_facility" "ieee")
493 (match_test "TARGET_CPU_IEEE_FLOAT"))
496 (and (eq_attr "cpu_facility" "zarch")
497 (match_test "TARGET_ZARCH"))
500 (and (eq_attr "cpu_facility" "longdisp")
501 (match_test "TARGET_LONG_DISPLACEMENT"))
504 (and (eq_attr "cpu_facility" "extimm")
505 (match_test "TARGET_EXTIMM"))
508 (and (eq_attr "cpu_facility" "dfp")
509 (match_test "TARGET_DFP"))
512 (and (eq_attr "cpu_facility" "cpu_zarch")
513 (match_test "TARGET_CPU_ZARCH"))
516 (and (eq_attr "cpu_facility" "z10")
517 (match_test "TARGET_Z10"))
520 (and (eq_attr "cpu_facility" "z196")
521 (match_test "TARGET_Z196"))
524 (and (eq_attr "cpu_facility" "zEC12")
525 (match_test "TARGET_ZEC12"))
528 (and (eq_attr "cpu_facility" "vx")
529 (match_test "TARGET_VX"))
532 (and (eq_attr "cpu_facility" "z13")
533 (match_test "TARGET_Z13"))
538 ;; Pipeline description for z900. For lack of anything better,
539 ;; this description is also used for the g5 and g6.
542 ;; Pipeline description for z990, z9-109 and z9-ec.
545 ;; Pipeline description for z10
548 ;; Pipeline description for z196
551 ;; Pipeline description for zEC12
554 ;; Pipeline description for z13
558 (include "predicates.md")
560 ;; Constraint definitions
561 (include "constraints.md")
568 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
570 ;; These mode iterators allow floating point patterns to be generated from the
572 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
573 (SD "TARGET_HARD_DFP")])
574 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
575 (define_mode_iterator BFP [TF DF SF])
576 (define_mode_iterator DFP [TD DD])
577 (define_mode_iterator DFP_ALL [TD DD SD])
578 (define_mode_iterator DSF [DF SF])
579 (define_mode_iterator SD_SF [SF SD])
580 (define_mode_iterator DD_DF [DF DD])
581 (define_mode_iterator TD_TF [TF TD])
583 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
584 ;; from the same template.
585 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
586 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
587 (define_mode_iterator DSI [DI SI])
588 (define_mode_iterator TDI [TI DI])
590 ;; These mode iterators allow :P to be used for patterns that operate on
591 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
592 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
594 ;; These macros refer to the actual word_mode of the configuration.
595 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
596 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
597 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
599 ;; Used by the umul pattern to express modes having half the size.
600 (define_mode_attr DWH [(TI "DI") (DI "SI")])
601 (define_mode_attr dwh [(TI "di") (DI "si")])
603 ;; This mode iterator allows the QI and HI patterns to be defined from
604 ;; the same template.
605 (define_mode_iterator HQI [HI QI])
607 ;; This mode iterator allows the integer patterns to be defined from the
609 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
610 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
611 (define_mode_iterator SINT [SI HI QI])
613 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
614 ;; the same template.
615 (define_code_iterator SHIFT [ashift lshiftrt])
617 ;; This iterator allows r[ox]sbg to be defined with the same template
618 (define_code_iterator IXOR [ior xor])
620 ;; This iterator is used to expand the patterns for the nearest
621 ;; integer functions.
622 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
623 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
624 UNSPEC_FPINT_NEARBYINT])
625 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
626 (UNSPEC_FPINT_BTRUNC "btrunc")
627 (UNSPEC_FPINT_ROUND "round")
628 (UNSPEC_FPINT_CEIL "ceil")
629 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
630 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
631 (UNSPEC_FPINT_BTRUNC "5")
632 (UNSPEC_FPINT_ROUND "1")
633 (UNSPEC_FPINT_CEIL "6")
634 (UNSPEC_FPINT_NEARBYINT "0")])
636 ;; This iterator and attribute allow to combine most atomic operations.
637 (define_code_iterator ATOMIC [and ior xor plus minus mult])
638 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
639 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
640 (plus "add") (minus "sub") (mult "nand")])
641 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
643 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
644 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
645 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
647 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
648 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
650 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
652 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
653 ;; Likewise for "<RXe>".
654 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
655 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
657 ;; The decimal floating point variants of add, sub, div and mul support 3
658 ;; fp register operands. The following attributes allow to merge the bfp and
659 ;; dfp variants in a single insn definition.
661 ;; These mode attributes are supposed to be used in the `enabled' insn
662 ;; attribute to disable certain alternatives for certain modes.
663 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
664 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
665 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
666 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
667 (TD "0") (DD "0") (DD "0")
668 (TI "0") (DI "*") (SI "0")])
670 ;; This attribute is used in the operand constraint list
671 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
672 ;; TFmode values are represented by a fp register pair. Since the
673 ;; sign bit instructions only handle single source and target fp registers
674 ;; these instructions can only be used for TFmode values if the source and
675 ;; target operand uses the same fp register.
676 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
678 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
679 ;; within instruction mnemonics.
680 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
682 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
683 ;; modes and to an empty string for bfp modes.
684 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
686 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
687 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
688 ;; version only operates on one register.
689 (define_mode_attr d0 [(DI "d") (SI "0")])
691 ;; In combination with d0 this allows to combine instructions of which the 31bit
692 ;; version only operates on one register. The DImode version needs an additional
693 ;; register for the assembler output.
694 (define_mode_attr 1 [(DI "%1,") (SI "")])
696 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
697 ;; 'ashift' and "srdl" in 'lshiftrt'.
698 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
700 ;; In SHIFT templates, this attribute holds the correct standard name for the
701 ;; pattern itself and the corresponding function calls.
702 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
704 ;; This attribute handles differences in the instruction 'type' and will result
705 ;; in "RRE" for DImode and "RR" for SImode.
706 (define_mode_attr E [(DI "E") (SI "")])
708 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
709 ;; to result in "RXY" for DImode and "RX" for SImode.
710 (define_mode_attr Y [(DI "Y") (SI "")])
712 ;; This attribute handles differences in the instruction 'type' and will result
713 ;; in "RSE" for TImode and "RS" for DImode.
714 (define_mode_attr TE [(TI "E") (DI "")])
716 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
717 ;; and "lcr" in SImode.
718 (define_mode_attr g [(DI "g") (SI "")])
720 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
721 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
722 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
723 ;; variant for long displacements.
724 (define_mode_attr y [(DI "g") (SI "y")])
726 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
727 ;; and "cds" in DImode.
728 (define_mode_attr tg [(TI "g") (DI "")])
730 ;; In TDI templates, a string like "c<d>sg".
731 (define_mode_attr td [(TI "d") (DI "")])
733 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
734 ;; and "cfdbr" in SImode.
735 (define_mode_attr gf [(DI "g") (SI "f")])
737 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
738 ;; and sllk for SI. This way it is possible to merge the new z196 SI
739 ;; 3 operands shift instructions into the existing patterns.
740 (define_mode_attr gk [(DI "g") (SI "k")])
742 ;; ICM mask required to load MODE value into the lowest subreg
743 ;; of a SImode register.
744 (define_mode_attr icm_lo [(HI "3") (QI "1")])
746 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
747 ;; HImode and "llgc" in QImode.
748 (define_mode_attr hc [(HI "h") (QI "c")])
750 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
752 (define_mode_attr DBL [(DI "TI") (SI "DI")])
754 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
755 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
756 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
758 ;; Maximum unsigned integer that fits in MODE.
759 (define_mode_attr max_uint [(HI "65535") (QI "255")])
761 ;; Start and end field computations for RISBG et al.
762 (define_mode_attr bfstart [(DI "s") (SI "t")])
763 (define_mode_attr bfend [(DI "e") (SI "f")])
765 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
766 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
768 (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
769 (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
771 ;; In place of GET_MODE_SIZE (<MODE>mode)
772 (define_mode_attr modesize [(DI "8") (SI "4")])
774 ;; Allow return and simple_return to be defined from a single template.
775 (define_code_iterator ANY_RETURN [return simple_return])
779 ; Condition code modes generated by vector fp comparisons. These will
780 ; be used also in single element mode.
781 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
782 ; Used with VFCMP to expand part of the mnemonic
783 ; For fp we have a mismatch: eq in the insn name - e in asm
784 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
785 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")])
787 ;; Subst pattern definitions
790 (include "vector.md")
793 ;;- Compare instructions.
796 ; Test-under-Mask instructions
798 (define_insn "*tmqi_mem"
799 [(set (reg CC_REGNUM)
800 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
801 (match_operand:QI 1 "immediate_operand" "n,n"))
802 (match_operand:QI 2 "immediate_operand" "n,n")))]
803 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
807 [(set_attr "op_type" "SI,SIY")
808 (set_attr "cpu_facility" "*,longdisp")
809 (set_attr "z10prop" "z10_super,z10_super")])
811 (define_insn "*tmdi_reg"
812 [(set (reg CC_REGNUM)
813 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
814 (match_operand:DI 1 "immediate_operand"
815 "N0HD0,N1HD0,N2HD0,N3HD0"))
816 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
818 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
819 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
825 [(set_attr "op_type" "RI")
826 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
828 (define_insn "*tmsi_reg"
829 [(set (reg CC_REGNUM)
830 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
831 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
832 (match_operand:SI 2 "immediate_operand" "n,n")))]
833 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
834 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
838 [(set_attr "op_type" "RI")
839 (set_attr "z10prop" "z10_super,z10_super")])
841 (define_insn "*tm<mode>_full"
842 [(set (reg CC_REGNUM)
843 (compare (match_operand:HQI 0 "register_operand" "d")
844 (match_operand:HQI 1 "immediate_operand" "n")))]
845 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
847 [(set_attr "op_type" "RI")
848 (set_attr "z10prop" "z10_super")])
852 ; Load-and-Test instructions
855 ; tst(di|si) instruction pattern(s).
857 (define_insn "*tstdi_sign"
858 [(set (reg CC_REGNUM)
862 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
863 (const_int 32)) (const_int 32))
864 (match_operand:DI 1 "const0_operand" "")))
865 (set (match_operand:DI 2 "register_operand" "=d,d")
866 (sign_extend:DI (match_dup 0)))]
867 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
870 [(set_attr "op_type" "RRE,RXY")
871 (set_attr "cpu_facility" "*,z10")
872 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
875 (define_insn "*tst<mode>_extimm"
876 [(set (reg CC_REGNUM)
877 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
878 (match_operand:GPR 1 "const0_operand" "")))
879 (set (match_operand:GPR 2 "register_operand" "=d,d")
881 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
885 [(set_attr "op_type" "RR<E>,RXY")
886 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
889 (define_insn "*tst<mode>_cconly_extimm"
890 [(set (reg CC_REGNUM)
891 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
892 (match_operand:GPR 1 "const0_operand" "")))
893 (clobber (match_scratch:GPR 2 "=X,d"))]
894 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
898 [(set_attr "op_type" "RR<E>,RXY")
899 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
901 (define_insn "*tstdi"
902 [(set (reg CC_REGNUM)
903 (compare (match_operand:DI 0 "register_operand" "d")
904 (match_operand:DI 1 "const0_operand" "")))
905 (set (match_operand:DI 2 "register_operand" "=d")
907 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
909 [(set_attr "op_type" "RRE")
910 (set_attr "z10prop" "z10_fr_E1")])
912 (define_insn "*tstsi"
913 [(set (reg CC_REGNUM)
914 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
915 (match_operand:SI 1 "const0_operand" "")))
916 (set (match_operand:SI 2 "register_operand" "=d,d,d")
918 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
923 [(set_attr "op_type" "RR,RS,RSY")
924 (set_attr "cpu_facility" "*,*,longdisp")
925 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
927 (define_insn "*tstsi_cconly"
928 [(set (reg CC_REGNUM)
929 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
930 (match_operand:SI 1 "const0_operand" "")))
931 (clobber (match_scratch:SI 2 "=X,d,d"))]
932 "s390_match_ccmode(insn, CCSmode)"
937 [(set_attr "op_type" "RR,RS,RSY")
938 (set_attr "cpu_facility" "*,*,longdisp")
939 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
941 (define_insn "*tstdi_cconly_31"
942 [(set (reg CC_REGNUM)
943 (compare (match_operand:DI 0 "register_operand" "d")
944 (match_operand:DI 1 "const0_operand" "")))]
945 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
947 [(set_attr "op_type" "RS")
948 (set_attr "atype" "reg")])
951 (define_insn "*tst<mode>_cconly2"
952 [(set (reg CC_REGNUM)
953 (compare (match_operand:GPR 0 "register_operand" "d")
954 (match_operand:GPR 1 "const0_operand" "")))]
955 "s390_match_ccmode(insn, CCSmode)"
957 [(set_attr "op_type" "RR<E>")
958 (set_attr "z10prop" "z10_fr_E1")])
960 ; tst(hi|qi) instruction pattern(s).
962 (define_insn "*tst<mode>CCT"
963 [(set (reg CC_REGNUM)
964 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
965 (match_operand:HQI 1 "const0_operand" "")))
966 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
968 "s390_match_ccmode(insn, CCTmode)"
971 icmy\t%2,<icm_lo>,%S0
973 [(set_attr "op_type" "RS,RSY,RI")
974 (set_attr "cpu_facility" "*,longdisp,*")
975 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
977 (define_insn "*tsthiCCT_cconly"
978 [(set (reg CC_REGNUM)
979 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
980 (match_operand:HI 1 "const0_operand" "")))
981 (clobber (match_scratch:HI 2 "=d,d,X"))]
982 "s390_match_ccmode(insn, CCTmode)"
987 [(set_attr "op_type" "RS,RSY,RI")
988 (set_attr "cpu_facility" "*,longdisp,*")
989 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
991 (define_insn "*tstqiCCT_cconly"
992 [(set (reg CC_REGNUM)
993 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
994 (match_operand:QI 1 "const0_operand" "")))]
995 "s390_match_ccmode(insn, CCTmode)"
1000 [(set_attr "op_type" "SI,SIY,RI")
1001 (set_attr "cpu_facility" "*,longdisp,*")
1002 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
1004 (define_insn "*tst<mode>"
1005 [(set (reg CC_REGNUM)
1006 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1007 (match_operand:HQI 1 "const0_operand" "")))
1008 (set (match_operand:HQI 2 "register_operand" "=d,d")
1010 "s390_match_ccmode(insn, CCSmode)"
1012 icm\t%2,<icm_lo>,%S0
1013 icmy\t%2,<icm_lo>,%S0"
1014 [(set_attr "op_type" "RS,RSY")
1015 (set_attr "cpu_facility" "*,longdisp")
1016 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1018 (define_insn "*tst<mode>_cconly"
1019 [(set (reg CC_REGNUM)
1020 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1021 (match_operand:HQI 1 "const0_operand" "")))
1022 (clobber (match_scratch:HQI 2 "=d,d"))]
1023 "s390_match_ccmode(insn, CCSmode)"
1025 icm\t%2,<icm_lo>,%S0
1026 icmy\t%2,<icm_lo>,%S0"
1027 [(set_attr "op_type" "RS,RSY")
1028 (set_attr "cpu_facility" "*,longdisp")
1029 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1032 ; Compare (equality) instructions
1034 (define_insn "*cmpdi_cct"
1035 [(set (reg CC_REGNUM)
1036 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
1037 (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
1038 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
1045 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
1046 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
1048 (define_insn "*cmpsi_cct"
1049 [(set (reg CC_REGNUM)
1050 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1051 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1052 "s390_match_ccmode (insn, CCTmode)"
1060 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1061 (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
1062 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1064 ; Compare (signed) instructions
1066 (define_insn "*cmpdi_ccs_sign"
1067 [(set (reg CC_REGNUM)
1068 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1070 (match_operand:DI 0 "register_operand" "d, d,d")))]
1071 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1076 [(set_attr "op_type" "RRE,RXY,RIL")
1077 (set_attr "z10prop" "z10_c,*,*")
1078 (set_attr "type" "*,*,larl")])
1082 (define_insn "*cmpsi_ccs_sign"
1083 [(set (reg CC_REGNUM)
1084 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1085 (match_operand:SI 0 "register_operand" "d,d,d")))]
1086 "s390_match_ccmode(insn, CCSRmode)"
1091 [(set_attr "op_type" "RX,RXY,RIL")
1092 (set_attr "cpu_facility" "*,longdisp,z10")
1093 (set_attr "type" "*,*,larl")
1094 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1096 (define_insn "*cmphi_ccs_z10"
1097 [(set (reg CC_REGNUM)
1098 (compare (match_operand:HI 0 "s_operand" "Q")
1099 (match_operand:HI 1 "immediate_operand" "K")))]
1100 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1102 [(set_attr "op_type" "SIL")
1103 (set_attr "z196prop" "z196_cracked")])
1105 (define_insn "*cmpdi_ccs_signhi_rl"
1106 [(set (reg CC_REGNUM)
1107 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
1108 (match_operand:GPR 0 "register_operand" "d,d")))]
1109 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1113 [(set_attr "op_type" "RXY,RIL")
1114 (set_attr "type" "*,larl")])
1116 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1117 (define_insn "*cmp<mode>_ccs"
1118 [(set (reg CC_REGNUM)
1119 (compare (match_operand:GPR 0 "nonimmediate_operand"
1121 (match_operand:GPR 1 "general_operand"
1122 "d,K,K,Os,R,T,b")))]
1123 "s390_match_ccmode(insn, CCSmode)"
1132 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1133 (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
1134 (set_attr "type" "*,*,*,*,*,*,larl")
1135 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1138 ; Compare (unsigned) instructions
1140 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1141 [(set (reg CC_REGNUM)
1142 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1143 "larl_operand" "X")))
1144 (match_operand:SI 0 "register_operand" "d")))]
1145 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1147 [(set_attr "op_type" "RIL")
1148 (set_attr "type" "larl")
1149 (set_attr "z10prop" "z10_super")])
1152 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1153 [(set (reg CC_REGNUM)
1154 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1155 "larl_operand" "X")))
1156 (match_operand:GPR 0 "register_operand" "d")))]
1157 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1159 [(set_attr "op_type" "RIL")
1160 (set_attr "type" "larl")
1161 (set_attr "z10prop" "z10_super")])
1163 (define_insn "*cmpdi_ccu_zero"
1164 [(set (reg CC_REGNUM)
1165 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1167 (match_operand:DI 0 "register_operand" "d,d,d")))]
1168 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1173 [(set_attr "op_type" "RRE,RXY,RIL")
1174 (set_attr "cpu_facility" "*,*,z10")
1175 (set_attr "type" "*,*,larl")
1176 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1178 (define_insn "*cmpdi_ccu"
1179 [(set (reg CC_REGNUM)
1180 (compare (match_operand:DI 0 "nonimmediate_operand"
1182 (match_operand:DI 1 "general_operand"
1183 "d,Op,b,D,T,BQ,Q")))]
1184 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1193 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1194 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1195 (set_attr "type" "*,*,larl,*,*,*,*")
1196 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1198 (define_insn "*cmpsi_ccu"
1199 [(set (reg CC_REGNUM)
1200 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1201 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1202 "s390_match_ccmode (insn, CCUmode)"
1212 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1213 (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
1214 (set_attr "type" "*,*,larl,*,*,*,*,*")
1215 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1217 (define_insn "*cmphi_ccu"
1218 [(set (reg CC_REGNUM)
1219 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1220 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1221 "s390_match_ccmode (insn, CCUmode)
1222 && !register_operand (operands[1], HImode)"
1229 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1230 (set_attr "cpu_facility" "*,longdisp,z10,*,*")
1231 (set_attr "z10prop" "*,*,z10_super,*,*")])
1233 (define_insn "*cmpqi_ccu"
1234 [(set (reg CC_REGNUM)
1235 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1236 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1237 "s390_match_ccmode (insn, CCUmode)
1238 && !register_operand (operands[1], QImode)"
1246 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1247 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
1248 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1251 ; Block compare (CLC) instruction patterns.
1254 [(set (reg CC_REGNUM)
1255 (compare (match_operand:BLK 0 "memory_operand" "Q")
1256 (match_operand:BLK 1 "memory_operand" "Q")))
1257 (use (match_operand 2 "const_int_operand" "n"))]
1258 "s390_match_ccmode (insn, CCUmode)
1259 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1260 "clc\t%O0(%2,%R0),%S1"
1261 [(set_attr "op_type" "SS")])
1264 [(set (reg CC_REGNUM)
1265 (compare (match_operand 0 "memory_operand" "")
1266 (match_operand 1 "memory_operand" "")))]
1268 && s390_match_ccmode (insn, CCUmode)
1269 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1270 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1272 [(set (match_dup 0) (match_dup 1))
1273 (use (match_dup 2))])]
1275 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1276 operands[0] = adjust_address (operands[0], BLKmode, 0);
1277 operands[1] = adjust_address (operands[1], BLKmode, 0);
1279 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1280 operands[0], operands[1]);
1281 operands[0] = SET_DEST (PATTERN (curr_insn));
1285 ; (TF|DF|SF|TD|DD|SD) instructions
1288 ; load and test instructions turn SNaN into QNaN what is not
1289 ; acceptable if the target will be used afterwards. On the other hand
1290 ; they are quite convenient for implementing comparisons with 0.0. So
1291 ; try to enable them via splitter if the value isn't needed anymore.
1293 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1294 (define_insn "*cmp<mode>_ccs_0"
1295 [(set (reg CC_REGNUM)
1296 (compare (match_operand:FP 0 "register_operand" "f")
1297 (match_operand:FP 1 "const0_operand" "")))
1298 (clobber (match_operand:FP 2 "register_operand" "=0"))]
1299 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1300 "lt<xde><bt>r\t%0,%0"
1301 [(set_attr "op_type" "RRE")
1302 (set_attr "type" "fsimp<mode>")])
1305 [(set (match_operand 0 "cc_reg_operand")
1306 (compare (match_operand:FP 1 "register_operand")
1307 (match_operand:FP 2 "const0_operand")))]
1308 "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])"
1310 [(set (match_dup 0) (match_dup 3))
1311 (clobber (match_dup 1))])]
1313 /* s390_match_ccmode requires the compare to have the same CC mode
1314 as the CC destination register. */
1315 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]),
1316 operands[1], operands[2]);
1320 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1321 (define_insn "*cmp<mode>_ccs"
1322 [(set (reg CC_REGNUM)
1323 (compare (match_operand:FP 0 "register_operand" "f,f")
1324 (match_operand:FP 1 "general_operand" "f,R")))]
1325 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1329 [(set_attr "op_type" "RRE,RXE")
1330 (set_attr "type" "fsimp<mode>")
1331 (set_attr "enabled" "*,<DSF>")])
1333 ; wfcedbs, wfchdbs, wfchedbs
1334 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1335 [(set (reg:VFCMP CC_REGNUM)
1336 (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1337 (match_operand:DF 1 "register_operand" "v")))
1338 (clobber (match_scratch:V2DI 2 "=v"))]
1339 "TARGET_VX && TARGET_HARD_FLOAT"
1340 "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1341 [(set_attr "op_type" "VRR")])
1343 ; Compare and Branch instructions
1345 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1346 ; The following instructions do a complementary access of their second
1347 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1348 (define_insn "*cmp_and_br_signed_<mode>"
1350 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1351 [(match_operand:GPR 1 "register_operand" "d,d")
1352 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1353 (label_ref (match_operand 3 "" ""))
1355 (clobber (reg:CC CC_REGNUM))]
1356 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1358 if (get_attr_length (insn) == 6)
1359 return which_alternative ?
1360 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1362 return which_alternative ?
1363 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1365 [(set_attr "op_type" "RIE")
1366 (set_attr "type" "branch")
1367 (set_attr "z10prop" "z10_super_c,z10_super")
1368 (set (attr "length")
1369 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1370 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1371 ; 10 byte for cgr/jg
1373 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1374 ; The following instructions do a complementary access of their second
1375 ; operand (z10 only): clrj, clgrj, clr, clgr
1376 (define_insn "*cmp_and_br_unsigned_<mode>"
1378 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1379 [(match_operand:GPR 1 "register_operand" "d,d")
1380 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1381 (label_ref (match_operand 3 "" ""))
1383 (clobber (reg:CC CC_REGNUM))]
1384 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1386 if (get_attr_length (insn) == 6)
1387 return which_alternative ?
1388 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1390 return which_alternative ?
1391 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1393 [(set_attr "op_type" "RIE")
1394 (set_attr "type" "branch")
1395 (set_attr "z10prop" "z10_super_c,z10_super")
1396 (set (attr "length")
1397 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1398 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1399 ; 10 byte for clgr/jg
1401 ; And now the same two patterns as above but with a negated CC mask.
1403 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1404 ; The following instructions do a complementary access of their second
1405 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1406 (define_insn "*icmp_and_br_signed_<mode>"
1408 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1409 [(match_operand:GPR 1 "register_operand" "d,d")
1410 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1412 (label_ref (match_operand 3 "" ""))))
1413 (clobber (reg:CC CC_REGNUM))]
1414 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1416 if (get_attr_length (insn) == 6)
1417 return which_alternative ?
1418 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1420 return which_alternative ?
1421 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1423 [(set_attr "op_type" "RIE")
1424 (set_attr "type" "branch")
1425 (set_attr "z10prop" "z10_super_c,z10_super")
1426 (set (attr "length")
1427 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1428 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1429 ; 10 byte for cgr/jg
1431 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1432 ; The following instructions do a complementary access of their second
1433 ; operand (z10 only): clrj, clgrj, clr, clgr
1434 (define_insn "*icmp_and_br_unsigned_<mode>"
1436 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1437 [(match_operand:GPR 1 "register_operand" "d,d")
1438 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1440 (label_ref (match_operand 3 "" ""))))
1441 (clobber (reg:CC CC_REGNUM))]
1442 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1444 if (get_attr_length (insn) == 6)
1445 return which_alternative ?
1446 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1448 return which_alternative ?
1449 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1451 [(set_attr "op_type" "RIE")
1452 (set_attr "type" "branch")
1453 (set_attr "z10prop" "z10_super_c,z10_super")
1454 (set (attr "length")
1455 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1456 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1457 ; 10 byte for clgr/jg
1460 ;;- Move instructions.
1464 ; movti instruction pattern(s).
1467 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1468 ; for TImode (use double-int for the calculations)
1469 (define_insn "movti"
1470 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o")
1471 (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dPT,d"))]
1485 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1486 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1487 (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")])
1490 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1491 (match_operand:TI 1 "general_operand" ""))]
1492 "TARGET_ZARCH && reload_completed
1493 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1494 [(set (match_dup 2) (match_dup 4))
1495 (set (match_dup 3) (match_dup 5))]
1497 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1498 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1499 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1500 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1504 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1505 (match_operand:TI 1 "general_operand" ""))]
1506 "TARGET_ZARCH && reload_completed
1507 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1508 [(set (match_dup 2) (match_dup 4))
1509 (set (match_dup 3) (match_dup 5))]
1511 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1512 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1513 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1514 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1517 ; Use part of the TImode target reg to perform the address
1518 ; calculation. If the TImode value is supposed to be copied into a VR
1519 ; this splitter is not necessary.
1521 [(set (match_operand:TI 0 "register_operand" "")
1522 (match_operand:TI 1 "memory_operand" ""))]
1523 "TARGET_ZARCH && reload_completed
1524 && !VECTOR_REG_P (operands[0])
1525 && !s_operand (operands[1], VOIDmode)"
1526 [(set (match_dup 0) (match_dup 1))]
1528 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1529 addr = gen_lowpart (Pmode, addr);
1530 s390_load_address (addr, XEXP (operands[1], 0));
1531 operands[1] = replace_equiv_address (operands[1], addr);
1535 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1536 ; For the higher order bits we do simply a DImode move while the
1537 ; second part is done via vec extract. Both will end up as vlgvg.
1539 [(set (match_operand:TI 0 "register_operand" "")
1540 (match_operand:TI 1 "register_operand" ""))]
1541 "TARGET_VX && reload_completed
1542 && GENERAL_REG_P (operands[0])
1543 && VECTOR_REG_P (operands[1])"
1544 [(set (match_dup 2) (match_dup 4))
1545 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1546 UNSPEC_VEC_EXTRACT))]
1548 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1549 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1550 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1551 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1555 ; Patterns used for secondary reloads
1558 ; z10 provides move instructions accepting larl memory operands.
1559 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1560 ; These patterns are also used for unaligned SI and DI accesses.
1562 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1563 [(parallel [(match_operand:ALL 0 "memory_operand" "")
1564 (match_operand:ALL 1 "register_operand" "=d")
1565 (match_operand:P 2 "register_operand" "=&a")])]
1568 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1572 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1573 [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1574 (match_operand:ALL 1 "memory_operand" "")
1575 (match_operand:P 2 "register_operand" "=a")])]
1578 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1582 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1583 [(parallel [(match_operand:P 0 "register_operand" "=d")
1584 (match_operand:P 1 "larl_operand" "")
1585 (match_operand:P 2 "register_operand" "=a")])]
1588 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1592 ; Handles loading a PLUS (load address) expression
1594 (define_expand "reload<mode>_plus"
1595 [(parallel [(match_operand:P 0 "register_operand" "=a")
1596 (match_operand:P 1 "s390_plus_operand" "")
1597 (match_operand:P 2 "register_operand" "=&a")])]
1600 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1604 ; Not all the indirect memory access instructions support the full
1605 ; format (long disp + index + base). So whenever a move from/to such
1606 ; an address is required and the instruction cannot deal with it we do
1607 ; a load address into a scratch register first and use this as the new
1609 ; This in particular is used for:
1610 ; - non-offsetable memory accesses for multiword moves
1611 ; - full vector reg moves with long displacements
1613 (define_expand "reload<mode>_la_in"
1614 [(parallel [(match_operand 0 "register_operand" "")
1615 (match_operand 1 "" "")
1616 (match_operand:P 2 "register_operand" "=&a")])]
1619 gcc_assert (MEM_P (operands[1]));
1620 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1621 operands[1] = replace_equiv_address (operands[1], operands[2]);
1622 emit_move_insn (operands[0], operands[1]);
1626 (define_expand "reload<mode>_la_out"
1627 [(parallel [(match_operand 0 "" "")
1628 (match_operand 1 "register_operand" "")
1629 (match_operand:P 2 "register_operand" "=&a")])]
1632 gcc_assert (MEM_P (operands[0]));
1633 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1634 operands[0] = replace_equiv_address (operands[0], operands[2]);
1635 emit_move_insn (operands[0], operands[1]);
1639 (define_expand "reload<mode>_PIC_addr"
1640 [(parallel [(match_operand 0 "register_operand" "=d")
1641 (match_operand 1 "larl_operand" "")
1642 (match_operand:P 2 "register_operand" "=a")])]
1645 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1646 emit_move_insn (operands[0], new_rtx);
1650 ; movdi instruction pattern(s).
1653 (define_expand "movdi"
1654 [(set (match_operand:DI 0 "general_operand" "")
1655 (match_operand:DI 1 "general_operand" ""))]
1658 /* Handle symbolic constants. */
1660 && (SYMBOLIC_CONST (operands[1])
1661 || (GET_CODE (operands[1]) == PLUS
1662 && XEXP (operands[1], 0) == pic_offset_table_rtx
1663 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1664 emit_symbolic_move (operands);
1667 (define_insn "*movdi_larl"
1668 [(set (match_operand:DI 0 "register_operand" "=d")
1669 (match_operand:DI 1 "larl_operand" "X"))]
1671 && !FP_REG_P (operands[0])"
1673 [(set_attr "op_type" "RIL")
1674 (set_attr "type" "larl")
1675 (set_attr "z10prop" "z10_super_A1")])
1677 (define_insn "*movdi_64"
1678 [(set (match_operand:DI 0 "nonimmediate_operand"
1679 "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R")
1680 (match_operand:DI 1 "general_operand"
1681 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))]
1716 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1717 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1718 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1719 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1721 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1722 z10,*,*,*,*,*,longdisp,*,longdisp,
1723 z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx")
1724 (set_attr "z10prop" "z10_fwd_A1,
1753 [(set (match_operand:DI 0 "register_operand" "")
1754 (match_operand:DI 1 "register_operand" ""))]
1755 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1756 [(set (match_dup 2) (match_dup 3))
1757 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1758 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1759 "operands[2] = gen_lowpart (SImode, operands[0]);
1760 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1763 [(set (match_operand:DI 0 "register_operand" "")
1764 (match_operand:DI 1 "register_operand" ""))]
1765 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1766 && dead_or_set_p (insn, operands[1])"
1767 [(set (match_dup 3) (match_dup 2))
1768 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1769 (set (match_dup 4) (match_dup 2))]
1770 "operands[2] = gen_lowpart (SImode, operands[1]);
1771 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1774 [(set (match_operand:DI 0 "register_operand" "")
1775 (match_operand:DI 1 "register_operand" ""))]
1776 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1777 && !dead_or_set_p (insn, operands[1])"
1778 [(set (match_dup 3) (match_dup 2))
1779 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1780 (set (match_dup 4) (match_dup 2))
1781 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1782 "operands[2] = gen_lowpart (SImode, operands[1]);
1783 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1785 (define_insn "*movdi_31"
1786 [(set (match_operand:DI 0 "nonimmediate_operand"
1787 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1788 (match_operand:DI 1 "general_operand"
1789 " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))]
1804 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1805 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1806 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
1808 ; For a load from a symbol ref we can use one of the target registers
1809 ; together with larl to load the address.
1811 [(set (match_operand:DI 0 "register_operand" "")
1812 (match_operand:DI 1 "memory_operand" ""))]
1813 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1814 && larl_operand (XEXP (operands[1], 0), SImode)"
1815 [(set (match_dup 2) (match_dup 3))
1816 (set (match_dup 0) (match_dup 1))]
1818 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1819 operands[3] = XEXP (operands[1], 0);
1820 operands[1] = replace_equiv_address (operands[1], operands[2]);
1824 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1825 (match_operand:DI 1 "general_operand" ""))]
1826 "!TARGET_ZARCH && reload_completed
1827 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1828 [(set (match_dup 2) (match_dup 4))
1829 (set (match_dup 3) (match_dup 5))]
1831 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1832 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1833 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1834 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1838 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1839 (match_operand:DI 1 "general_operand" ""))]
1840 "!TARGET_ZARCH && reload_completed
1841 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1842 [(set (match_dup 2) (match_dup 4))
1843 (set (match_dup 3) (match_dup 5))]
1845 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1846 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1847 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1848 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1852 [(set (match_operand:DI 0 "register_operand" "")
1853 (match_operand:DI 1 "memory_operand" ""))]
1854 "!TARGET_ZARCH && reload_completed
1855 && !FP_REG_P (operands[0])
1856 && !s_operand (operands[1], VOIDmode)"
1857 [(set (match_dup 0) (match_dup 1))]
1859 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1860 s390_load_address (addr, XEXP (operands[1], 0));
1861 operands[1] = replace_equiv_address (operands[1], addr);
1865 [(set (match_operand:DI 0 "register_operand" "")
1866 (mem:DI (match_operand 1 "address_operand" "")))]
1868 && !FP_REG_P (operands[0])
1869 && GET_CODE (operands[1]) == SYMBOL_REF
1870 && CONSTANT_POOL_ADDRESS_P (operands[1])
1871 && get_pool_mode (operands[1]) == DImode
1872 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1873 [(set (match_dup 0) (match_dup 2))]
1874 "operands[2] = get_pool_constant (operands[1]);")
1876 (define_insn "*la_64"
1877 [(set (match_operand:DI 0 "register_operand" "=d,d")
1878 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
1883 [(set_attr "op_type" "RX,RXY")
1884 (set_attr "type" "la")
1885 (set_attr "cpu_facility" "*,longdisp")
1886 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1890 [(set (match_operand:DI 0 "register_operand" "")
1891 (match_operand:QI 1 "address_operand" ""))
1892 (clobber (reg:CC CC_REGNUM))])]
1894 && preferred_la_operand_p (operands[1], const0_rtx)"
1895 [(set (match_dup 0) (match_dup 1))]
1899 [(set (match_operand:DI 0 "register_operand" "")
1900 (match_operand:DI 1 "register_operand" ""))
1903 (plus:DI (match_dup 0)
1904 (match_operand:DI 2 "nonmemory_operand" "")))
1905 (clobber (reg:CC CC_REGNUM))])]
1907 && !reg_overlap_mentioned_p (operands[0], operands[2])
1908 && preferred_la_operand_p (operands[1], operands[2])"
1909 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1913 ; movsi instruction pattern(s).
1916 (define_expand "movsi"
1917 [(set (match_operand:SI 0 "general_operand" "")
1918 (match_operand:SI 1 "general_operand" ""))]
1921 /* Handle symbolic constants. */
1923 && (SYMBOLIC_CONST (operands[1])
1924 || (GET_CODE (operands[1]) == PLUS
1925 && XEXP (operands[1], 0) == pic_offset_table_rtx
1926 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1927 emit_symbolic_move (operands);
1930 (define_insn "*movsi_larl"
1931 [(set (match_operand:SI 0 "register_operand" "=d")
1932 (match_operand:SI 1 "larl_operand" "X"))]
1933 "!TARGET_64BIT && TARGET_CPU_ZARCH
1934 && !FP_REG_P (operands[0])"
1936 [(set_attr "op_type" "RIL")
1937 (set_attr "type" "larl")
1938 (set_attr "z10prop" "z10_fwd_A1")])
1940 (define_insn "*movsi_zarch"
1941 [(set (match_operand:SI 0 "nonimmediate_operand"
1942 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
1943 (match_operand:SI 1 "general_operand"
1944 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
1977 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1978 RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1979 (set_attr "type" "*,
2003 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
2004 vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx")
2005 (set_attr "z10prop" "z10_fwd_A1,
2030 (define_insn "*movsi_esa"
2031 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
2032 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
2048 [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
2049 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
2050 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
2052 (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*")
2056 [(set (match_operand:SI 0 "register_operand" "")
2057 (mem:SI (match_operand 1 "address_operand" "")))]
2058 "!FP_REG_P (operands[0])
2059 && GET_CODE (operands[1]) == SYMBOL_REF
2060 && CONSTANT_POOL_ADDRESS_P (operands[1])
2061 && get_pool_mode (operands[1]) == SImode
2062 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
2063 [(set (match_dup 0) (match_dup 2))]
2064 "operands[2] = get_pool_constant (operands[1]);")
2066 (define_insn "*la_31"
2067 [(set (match_operand:SI 0 "register_operand" "=d,d")
2068 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
2069 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
2073 [(set_attr "op_type" "RX,RXY")
2074 (set_attr "type" "la")
2075 (set_attr "cpu_facility" "*,longdisp")
2076 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2080 [(set (match_operand:SI 0 "register_operand" "")
2081 (match_operand:QI 1 "address_operand" ""))
2082 (clobber (reg:CC CC_REGNUM))])]
2084 && preferred_la_operand_p (operands[1], const0_rtx)"
2085 [(set (match_dup 0) (match_dup 1))]
2089 [(set (match_operand:SI 0 "register_operand" "")
2090 (match_operand:SI 1 "register_operand" ""))
2093 (plus:SI (match_dup 0)
2094 (match_operand:SI 2 "nonmemory_operand" "")))
2095 (clobber (reg:CC CC_REGNUM))])]
2097 && !reg_overlap_mentioned_p (operands[0], operands[2])
2098 && preferred_la_operand_p (operands[1], operands[2])"
2099 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2102 (define_insn "*la_31_and"
2103 [(set (match_operand:SI 0 "register_operand" "=d,d")
2104 (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
2105 (const_int 2147483647)))]
2110 [(set_attr "op_type" "RX,RXY")
2111 (set_attr "type" "la")
2112 (set_attr "cpu_facility" "*,longdisp")
2113 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2115 (define_insn_and_split "*la_31_and_cc"
2116 [(set (match_operand:SI 0 "register_operand" "=d")
2117 (and:SI (match_operand:QI 1 "address_operand" "p")
2118 (const_int 2147483647)))
2119 (clobber (reg:CC CC_REGNUM))]
2122 "&& reload_completed"
2124 (and:SI (match_dup 1) (const_int 2147483647)))]
2126 [(set_attr "op_type" "RX")
2127 (set_attr "type" "la")])
2129 (define_insn "force_la_31"
2130 [(set (match_operand:SI 0 "register_operand" "=d,d")
2131 (match_operand:QI 1 "address_operand" "ZR,ZT"))
2132 (use (const_int 0))]
2137 [(set_attr "op_type" "RX")
2138 (set_attr "type" "la")
2139 (set_attr "cpu_facility" "*,longdisp")
2140 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2143 ; movhi instruction pattern(s).
2146 (define_expand "movhi"
2147 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2148 (match_operand:HI 1 "general_operand" ""))]
2151 /* Make it explicit that loading a register from memory
2152 always sign-extends (at least) to SImode. */
2153 if (optimize && can_create_pseudo_p ()
2154 && register_operand (operands[0], VOIDmode)
2155 && GET_CODE (operands[1]) == MEM)
2157 rtx tmp = gen_reg_rtx (SImode);
2158 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2159 emit_insn (gen_rtx_SET (tmp, ext));
2160 operands[1] = gen_lowpart (HImode, tmp);
2164 (define_insn "*movhi"
2165 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
2166 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
2184 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2185 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2186 (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx")
2187 (set_attr "z10prop" "z10_fr_E1,
2195 z10_super,*,*,*,*,*,*")])
2198 [(set (match_operand:HI 0 "register_operand" "")
2199 (mem:HI (match_operand 1 "address_operand" "")))]
2200 "GET_CODE (operands[1]) == SYMBOL_REF
2201 && CONSTANT_POOL_ADDRESS_P (operands[1])
2202 && get_pool_mode (operands[1]) == HImode
2203 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2204 [(set (match_dup 0) (match_dup 2))]
2205 "operands[2] = get_pool_constant (operands[1]);")
2208 ; movqi instruction pattern(s).
2211 (define_expand "movqi"
2212 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2213 (match_operand:QI 1 "general_operand" ""))]
2216 /* On z/Architecture, zero-extending from memory to register
2217 is just as fast as a QImode load. */
2218 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2219 && register_operand (operands[0], VOIDmode)
2220 && GET_CODE (operands[1]) == MEM)
2222 rtx tmp = gen_reg_rtx (DImode);
2223 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2224 emit_insn (gen_rtx_SET (tmp, ext));
2225 operands[1] = gen_lowpart (QImode, tmp);
2229 (define_insn "*movqi"
2230 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
2231 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
2249 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2250 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2251 (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx")
2252 (set_attr "z10prop" "z10_fr_E1,
2263 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2264 (mem:QI (match_operand 1 "address_operand" "")))]
2265 "GET_CODE (operands[1]) == SYMBOL_REF
2266 && CONSTANT_POOL_ADDRESS_P (operands[1])
2267 && get_pool_mode (operands[1]) == QImode
2268 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2269 [(set (match_dup 0) (match_dup 2))]
2270 "operands[2] = get_pool_constant (operands[1]);")
2273 ; movstrictqi instruction pattern(s).
2276 (define_insn "*movstrictqi"
2277 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2278 (match_operand:QI 1 "memory_operand" "R,T"))]
2283 [(set_attr "op_type" "RX,RXY")
2284 (set_attr "cpu_facility" "*,longdisp")
2285 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2288 ; movstricthi instruction pattern(s).
2291 (define_insn "*movstricthi"
2292 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2293 (match_operand:HI 1 "memory_operand" "Q,S"))
2294 (clobber (reg:CC CC_REGNUM))]
2299 [(set_attr "op_type" "RS,RSY")
2300 (set_attr "cpu_facility" "*,longdisp")
2301 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2304 ; movstrictsi instruction pattern(s).
2307 (define_insn "movstrictsi"
2308 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2309 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2316 [(set_attr "op_type" "RR,RX,RXY,RRE")
2317 (set_attr "type" "lr,load,load,*")
2318 (set_attr "cpu_facility" "*,*,longdisp,*")
2319 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2322 ; mov(tf|td) instruction pattern(s).
2325 (define_expand "mov<mode>"
2326 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2327 (match_operand:TD_TF 1 "general_operand" ""))]
2331 (define_insn "*mov<mode>_64"
2332 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
2333 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))]
2344 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2345 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2346 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2348 (define_insn "*mov<mode>_31"
2349 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2350 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2357 [(set_attr "op_type" "RRE,RRE,*,*")
2358 (set_attr "type" "fsimptf,fsimptf,*,*")
2359 (set_attr "cpu_facility" "z196,*,*,*")])
2361 ; TFmode in GPRs splitters
2364 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2365 (match_operand:TD_TF 1 "general_operand" ""))]
2366 "TARGET_ZARCH && reload_completed
2367 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2368 [(set (match_dup 2) (match_dup 4))
2369 (set (match_dup 3) (match_dup 5))]
2371 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2372 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2373 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2374 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2378 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2379 (match_operand:TD_TF 1 "general_operand" ""))]
2380 "TARGET_ZARCH && reload_completed
2381 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2382 [(set (match_dup 2) (match_dup 4))
2383 (set (match_dup 3) (match_dup 5))]
2385 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2386 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2387 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2388 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2392 [(set (match_operand:TD_TF 0 "register_operand" "")
2393 (match_operand:TD_TF 1 "memory_operand" ""))]
2394 "TARGET_ZARCH && reload_completed
2395 && GENERAL_REG_P (operands[0])
2396 && !s_operand (operands[1], VOIDmode)"
2397 [(set (match_dup 0) (match_dup 1))]
2399 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2400 addr = gen_lowpart (Pmode, addr);
2401 s390_load_address (addr, XEXP (operands[1], 0));
2402 operands[1] = replace_equiv_address (operands[1], addr);
2405 ; TFmode in BFPs splitters
2408 [(set (match_operand:TD_TF 0 "register_operand" "")
2409 (match_operand:TD_TF 1 "memory_operand" ""))]
2410 "reload_completed && offsettable_memref_p (operands[1])
2411 && FP_REG_P (operands[0])"
2412 [(set (match_dup 2) (match_dup 4))
2413 (set (match_dup 3) (match_dup 5))]
2415 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2417 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2419 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2420 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2424 [(set (match_operand:TD_TF 0 "memory_operand" "")
2425 (match_operand:TD_TF 1 "register_operand" ""))]
2426 "reload_completed && offsettable_memref_p (operands[0])
2427 && FP_REG_P (operands[1])"
2428 [(set (match_dup 2) (match_dup 4))
2429 (set (match_dup 3) (match_dup 5))]
2431 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2432 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2433 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2435 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2440 ; mov(df|dd) instruction pattern(s).
2443 (define_expand "mov<mode>"
2444 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2445 (match_operand:DD_DF 1 "general_operand" ""))]
2449 (define_insn "*mov<mode>_64dfp"
2450 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2451 "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,d,v,R")
2452 (match_operand:DD_DF 1 "general_operand"
2453 " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,d,v,R,v"))]
2475 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2476 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2477 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2478 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2479 (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx")])
2481 (define_insn "*mov<mode>_64"
2482 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T,v,v,R")
2483 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d,v,R,v"))]
2501 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2502 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2503 fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2504 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2505 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx")])
2507 (define_insn "*mov<mode>_31"
2508 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2509 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2510 (match_operand:DD_DF 1 "general_operand"
2511 " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
2526 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2527 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2528 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2529 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
2532 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2533 (match_operand:DD_DF 1 "general_operand" ""))]
2534 "!TARGET_ZARCH && reload_completed
2535 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2536 [(set (match_dup 2) (match_dup 4))
2537 (set (match_dup 3) (match_dup 5))]
2539 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2540 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2541 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2542 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2546 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2547 (match_operand:DD_DF 1 "general_operand" ""))]
2548 "!TARGET_ZARCH && reload_completed
2549 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2550 [(set (match_dup 2) (match_dup 4))
2551 (set (match_dup 3) (match_dup 5))]
2553 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2554 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2555 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2556 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2560 [(set (match_operand:DD_DF 0 "register_operand" "")
2561 (match_operand:DD_DF 1 "memory_operand" ""))]
2562 "!TARGET_ZARCH && reload_completed
2563 && !FP_REG_P (operands[0])
2564 && !s_operand (operands[1], VOIDmode)"
2565 [(set (match_dup 0) (match_dup 1))]
2567 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2568 s390_load_address (addr, XEXP (operands[1], 0));
2569 operands[1] = replace_equiv_address (operands[1], addr);
2573 ; mov(sf|sd) instruction pattern(s).
2576 (define_insn "mov<mode>"
2577 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2578 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
2579 (match_operand:SD_SF 1 "general_operand"
2580 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
2605 [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2606 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2607 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2608 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2609 (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")])
2612 ; movcc instruction pattern
2615 (define_insn "movcc"
2616 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2617 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2627 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2628 (set_attr "type" "lr,*,*,load,load,store,store")
2629 (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
2630 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2631 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2634 ; Block move (MVC) patterns.
2638 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2639 (match_operand:BLK 1 "memory_operand" "Q"))
2640 (use (match_operand 2 "const_int_operand" "n"))]
2641 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2642 "mvc\t%O0(%2,%R0),%S1"
2643 [(set_attr "op_type" "SS")])
2645 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2646 ; order to have it implemented with mvc.
2649 [(set (match_operand:QI 0 "memory_operand" "")
2650 (match_operand:QI 1 "memory_operand" ""))]
2653 [(set (match_dup 0) (match_dup 1))
2654 (use (const_int 1))])]
2656 operands[0] = adjust_address (operands[0], BLKmode, 0);
2657 operands[1] = adjust_address (operands[1], BLKmode, 0);
2663 [(set (match_operand:BLK 0 "memory_operand" "")
2664 (match_operand:BLK 1 "memory_operand" ""))
2665 (use (match_operand 2 "const_int_operand" ""))])
2667 [(set (match_operand:BLK 3 "memory_operand" "")
2668 (match_operand:BLK 4 "memory_operand" ""))
2669 (use (match_operand 5 "const_int_operand" ""))])]
2670 "s390_offset_p (operands[0], operands[3], operands[2])
2671 && s390_offset_p (operands[1], operands[4], operands[2])
2672 && !s390_overlap_p (operands[0], operands[1],
2673 INTVAL (operands[2]) + INTVAL (operands[5]))
2674 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2676 [(set (match_dup 6) (match_dup 7))
2677 (use (match_dup 8))])]
2678 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2679 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2680 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2684 ; load_multiple pattern(s).
2686 ; ??? Due to reload problems with replacing registers inside match_parallel
2687 ; we currently support load_multiple/store_multiple only after reload.
2690 (define_expand "load_multiple"
2691 [(match_par_dup 3 [(set (match_operand 0 "" "")
2692 (match_operand 1 "" ""))
2693 (use (match_operand 2 "" ""))])]
2702 /* Support only loading a constant number of fixed-point registers from
2703 memory and only bother with this if more than two */
2704 if (GET_CODE (operands[2]) != CONST_INT
2705 || INTVAL (operands[2]) < 2
2706 || INTVAL (operands[2]) > 16
2707 || GET_CODE (operands[1]) != MEM
2708 || GET_CODE (operands[0]) != REG
2709 || REGNO (operands[0]) >= 16)
2712 count = INTVAL (operands[2]);
2713 regno = REGNO (operands[0]);
2714 mode = GET_MODE (operands[0]);
2715 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2718 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2719 if (!can_create_pseudo_p ())
2721 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2723 from = XEXP (operands[1], 0);
2726 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2727 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2728 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2730 from = XEXP (XEXP (operands[1], 0), 0);
2731 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2738 from = force_reg (Pmode, XEXP (operands[1], 0));
2742 for (i = 0; i < count; i++)
2743 XVECEXP (operands[3], 0, i)
2744 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2745 change_address (operands[1], mode,
2746 plus_constant (Pmode, from,
2747 off + i * GET_MODE_SIZE (mode))));
2750 (define_insn "*load_multiple_di"
2751 [(match_parallel 0 "load_multiple_operation"
2752 [(set (match_operand:DI 1 "register_operand" "=r")
2753 (match_operand:DI 2 "s_operand" "S"))])]
2754 "reload_completed && TARGET_ZARCH"
2756 int words = XVECLEN (operands[0], 0);
2757 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2758 return "lmg\t%1,%0,%S2";
2760 [(set_attr "op_type" "RSY")
2761 (set_attr "type" "lm")])
2763 (define_insn "*load_multiple_si"
2764 [(match_parallel 0 "load_multiple_operation"
2765 [(set (match_operand:SI 1 "register_operand" "=r,r")
2766 (match_operand:SI 2 "s_operand" "Q,S"))])]
2769 int words = XVECLEN (operands[0], 0);
2770 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2771 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2773 [(set_attr "op_type" "RS,RSY")
2774 (set_attr "cpu_facility" "*,longdisp")
2775 (set_attr "type" "lm")])
2778 ; store multiple pattern(s).
2781 (define_expand "store_multiple"
2782 [(match_par_dup 3 [(set (match_operand 0 "" "")
2783 (match_operand 1 "" ""))
2784 (use (match_operand 2 "" ""))])]
2793 /* Support only storing a constant number of fixed-point registers to
2794 memory and only bother with this if more than two. */
2795 if (GET_CODE (operands[2]) != CONST_INT
2796 || INTVAL (operands[2]) < 2
2797 || INTVAL (operands[2]) > 16
2798 || GET_CODE (operands[0]) != MEM
2799 || GET_CODE (operands[1]) != REG
2800 || REGNO (operands[1]) >= 16)
2803 count = INTVAL (operands[2]);
2804 regno = REGNO (operands[1]);
2805 mode = GET_MODE (operands[1]);
2806 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2809 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2811 if (!can_create_pseudo_p ())
2813 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2815 to = XEXP (operands[0], 0);
2818 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2819 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2820 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2822 to = XEXP (XEXP (operands[0], 0), 0);
2823 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2830 to = force_reg (Pmode, XEXP (operands[0], 0));
2834 for (i = 0; i < count; i++)
2835 XVECEXP (operands[3], 0, i)
2836 = gen_rtx_SET (change_address (operands[0], mode,
2837 plus_constant (Pmode, to,
2838 off + i * GET_MODE_SIZE (mode))),
2839 gen_rtx_REG (mode, regno + i));
2842 (define_insn "*store_multiple_di"
2843 [(match_parallel 0 "store_multiple_operation"
2844 [(set (match_operand:DI 1 "s_operand" "=S")
2845 (match_operand:DI 2 "register_operand" "r"))])]
2846 "reload_completed && TARGET_ZARCH"
2848 int words = XVECLEN (operands[0], 0);
2849 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2850 return "stmg\t%2,%0,%S1";
2852 [(set_attr "op_type" "RSY")
2853 (set_attr "type" "stm")])
2856 (define_insn "*store_multiple_si"
2857 [(match_parallel 0 "store_multiple_operation"
2858 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2859 (match_operand:SI 2 "register_operand" "r,r"))])]
2862 int words = XVECLEN (operands[0], 0);
2863 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2864 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2866 [(set_attr "op_type" "RS,RSY")
2867 (set_attr "cpu_facility" "*,longdisp")
2868 (set_attr "type" "stm")])
2871 ;; String instructions.
2874 (define_insn "*execute_rl"
2875 [(match_parallel 0 "execute_operation"
2876 [(unspec [(match_operand 1 "register_operand" "a")
2877 (match_operand 2 "" "")
2878 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2879 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2880 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2882 [(set_attr "op_type" "RIL")
2883 (set_attr "type" "cs")])
2885 (define_insn "*execute"
2886 [(match_parallel 0 "execute_operation"
2887 [(unspec [(match_operand 1 "register_operand" "a")
2888 (match_operand:BLK 2 "memory_operand" "R")
2889 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2890 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2891 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2893 [(set_attr "op_type" "RX")
2894 (set_attr "type" "cs")])
2898 ; strlenM instruction pattern(s).
2901 (define_expand "strlen<mode>"
2902 [(match_operand:P 0 "register_operand" "") ; result
2903 (match_operand:BLK 1 "memory_operand" "") ; input string
2904 (match_operand:SI 2 "immediate_operand" "") ; search character
2905 (match_operand:SI 3 "immediate_operand" "")] ; known alignment
2908 if (!TARGET_VX || operands[2] != const0_rtx)
2909 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2910 operands[2], operands[3]));
2912 s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2917 (define_expand "strlen_srst<mode>"
2918 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2921 (unspec:P [(const_int 0)
2922 (match_operand:BLK 1 "memory_operand" "")
2924 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2925 (clobber (scratch:P))
2926 (clobber (reg:CC CC_REGNUM))])
2928 [(set (match_operand:P 0 "register_operand" "")
2929 (minus:P (match_dup 4) (match_dup 5)))
2930 (clobber (reg:CC CC_REGNUM))])]
2933 operands[4] = gen_reg_rtx (Pmode);
2934 operands[5] = gen_reg_rtx (Pmode);
2935 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2936 operands[1] = replace_equiv_address (operands[1], operands[5]);
2939 (define_insn "*strlen<mode>"
2940 [(set (match_operand:P 0 "register_operand" "=a")
2941 (unspec:P [(match_operand:P 2 "general_operand" "0")
2942 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2944 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2945 (clobber (match_scratch:P 1 "=a"))
2946 (clobber (reg:CC CC_REGNUM))]
2948 "srst\t%0,%1\;jo\t.-4"
2949 [(set_attr "length" "8")
2950 (set_attr "type" "vs")])
2953 ; cmpstrM instruction pattern(s).
2956 (define_expand "cmpstrsi"
2957 [(set (reg:SI 0) (const_int 0))
2959 [(clobber (match_operand 3 "" ""))
2960 (clobber (match_dup 4))
2961 (set (reg:CCU CC_REGNUM)
2962 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2963 (match_operand:BLK 2 "memory_operand" "")))
2966 [(set (match_operand:SI 0 "register_operand" "=d")
2967 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2968 (clobber (reg:CC CC_REGNUM))])]
2971 /* As the result of CMPINT is inverted compared to what we need,
2972 we have to swap the operands. */
2973 rtx op1 = operands[2];
2974 rtx op2 = operands[1];
2975 rtx addr1 = gen_reg_rtx (Pmode);
2976 rtx addr2 = gen_reg_rtx (Pmode);
2978 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2979 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2980 operands[1] = replace_equiv_address_nv (op1, addr1);
2981 operands[2] = replace_equiv_address_nv (op2, addr2);
2982 operands[3] = addr1;
2983 operands[4] = addr2;
2986 (define_insn "*cmpstr<mode>"
2987 [(clobber (match_operand:P 0 "register_operand" "=d"))
2988 (clobber (match_operand:P 1 "register_operand" "=d"))
2989 (set (reg:CCU CC_REGNUM)
2990 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2991 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2994 "clst\t%0,%1\;jo\t.-4"
2995 [(set_attr "length" "8")
2996 (set_attr "type" "vs")])
2999 ; movstr instruction pattern.
3002 (define_expand "movstr"
3003 [(match_operand 0 "register_operand" "")
3004 (match_operand 1 "memory_operand" "")
3005 (match_operand 2 "memory_operand" "")]
3009 emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
3011 emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
3015 (define_expand "movstr<P:mode>"
3016 [(set (reg:SI 0) (const_int 0))
3018 [(clobber (match_dup 3))
3019 (set (match_operand:BLK 1 "memory_operand" "")
3020 (match_operand:BLK 2 "memory_operand" ""))
3021 (set (match_operand:P 0 "register_operand" "")
3022 (unspec:P [(match_dup 1)
3024 (reg:SI 0)] UNSPEC_MVST))
3025 (clobber (reg:CC CC_REGNUM))])]
3030 if (TARGET_VX && optimize_function_for_speed_p (cfun))
3032 s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
3036 addr1 = gen_reg_rtx (Pmode);
3037 addr2 = gen_reg_rtx (Pmode);
3039 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3040 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
3041 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3042 operands[2] = replace_equiv_address_nv (operands[2], addr2);
3043 operands[3] = addr2;
3046 (define_insn "*movstr"
3047 [(clobber (match_operand:P 2 "register_operand" "=d"))
3048 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
3049 (mem:BLK (match_operand:P 3 "register_operand" "2")))
3050 (set (match_operand:P 0 "register_operand" "=d")
3051 (unspec:P [(mem:BLK (match_dup 1))
3052 (mem:BLK (match_dup 3))
3053 (reg:SI 0)] UNSPEC_MVST))
3054 (clobber (reg:CC CC_REGNUM))]
3056 "mvst\t%1,%2\;jo\t.-4"
3057 [(set_attr "length" "8")
3058 (set_attr "type" "vs")])
3062 ; movmemM instruction pattern(s).
3065 (define_expand "movmem<mode>"
3066 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
3067 (match_operand:BLK 1 "memory_operand" "")) ; source
3068 (use (match_operand:GPR 2 "general_operand" "")) ; count
3069 (match_operand 3 "" "")]
3072 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
3078 ; Move a block that is up to 256 bytes in length.
3079 ; The block length is taken as (operands[2] % 256) + 1.
3081 (define_expand "movmem_short"
3083 [(set (match_operand:BLK 0 "memory_operand" "")
3084 (match_operand:BLK 1 "memory_operand" ""))
3085 (use (match_operand 2 "nonmemory_operand" ""))
3086 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3087 (clobber (match_dup 3))])]
3089 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3091 (define_insn "*movmem_short"
3092 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3093 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3094 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3095 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3096 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3097 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3099 [(set_attr "type" "cs")
3100 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3103 [(set (match_operand:BLK 0 "memory_operand" "")
3104 (match_operand:BLK 1 "memory_operand" ""))
3105 (use (match_operand 2 "const_int_operand" ""))
3106 (use (match_operand 3 "immediate_operand" ""))
3107 (clobber (scratch))]
3110 [(set (match_dup 0) (match_dup 1))
3111 (use (match_dup 2))])]
3112 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3115 [(set (match_operand:BLK 0 "memory_operand" "")
3116 (match_operand:BLK 1 "memory_operand" ""))
3117 (use (match_operand 2 "register_operand" ""))
3118 (use (match_operand 3 "memory_operand" ""))
3119 (clobber (scratch))]
3122 [(unspec [(match_dup 2) (match_dup 3)
3123 (const_int 0)] UNSPEC_EXECUTE)
3124 (set (match_dup 0) (match_dup 1))
3125 (use (const_int 1))])]
3129 [(set (match_operand:BLK 0 "memory_operand" "")
3130 (match_operand:BLK 1 "memory_operand" ""))
3131 (use (match_operand 2 "register_operand" ""))
3132 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3133 (clobber (scratch))]
3134 "TARGET_Z10 && reload_completed"
3136 [(unspec [(match_dup 2) (const_int 0)
3137 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3138 (set (match_dup 0) (match_dup 1))
3139 (use (const_int 1))])]
3140 "operands[3] = gen_label_rtx ();")
3143 [(set (match_operand:BLK 0 "memory_operand" "")
3144 (match_operand:BLK 1 "memory_operand" ""))
3145 (use (match_operand 2 "register_operand" ""))
3146 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3147 (clobber (match_operand 3 "register_operand" ""))]
3148 "reload_completed && TARGET_CPU_ZARCH"
3149 [(set (match_dup 3) (label_ref (match_dup 4)))
3151 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3152 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3153 (set (match_dup 0) (match_dup 1))
3154 (use (const_int 1))])]
3155 "operands[4] = gen_label_rtx ();")
3157 ; Move a block of arbitrary length.
3159 (define_expand "movmem_long"
3161 [(clobber (match_dup 2))
3162 (clobber (match_dup 3))
3163 (set (match_operand:BLK 0 "memory_operand" "")
3164 (match_operand:BLK 1 "memory_operand" ""))
3165 (use (match_operand 2 "general_operand" ""))
3167 (clobber (reg:CC CC_REGNUM))])]
3170 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3171 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3172 rtx reg0 = gen_reg_rtx (dreg_mode);
3173 rtx reg1 = gen_reg_rtx (dreg_mode);
3174 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3175 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3176 rtx len0 = gen_lowpart (Pmode, reg0);
3177 rtx len1 = gen_lowpart (Pmode, reg1);
3179 emit_clobber (reg0);
3180 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3181 emit_move_insn (len0, operands[2]);
3183 emit_clobber (reg1);
3184 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3185 emit_move_insn (len1, operands[2]);
3187 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3188 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3193 (define_insn "*movmem_long"
3194 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3195 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3196 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3197 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3200 (clobber (reg:CC CC_REGNUM))]
3201 "TARGET_64BIT || !TARGET_ZARCH"
3202 "mvcle\t%0,%1,0\;jo\t.-4"
3203 [(set_attr "length" "8")
3204 (set_attr "type" "vs")])
3206 (define_insn "*movmem_long_31z"
3207 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3208 (clobber (match_operand:TI 1 "register_operand" "=d"))
3209 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3210 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3213 (clobber (reg:CC CC_REGNUM))]
3214 "!TARGET_64BIT && TARGET_ZARCH"
3215 "mvcle\t%0,%1,0\;jo\t.-4"
3216 [(set_attr "length" "8")
3217 (set_attr "type" "vs")])
3224 (define_expand "signbit<mode>2"
3225 [(set (reg:CCZ CC_REGNUM)
3226 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3229 (set (match_operand:SI 0 "register_operand" "=d")
3230 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3233 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3236 (define_expand "isinf<mode>2"
3237 [(set (reg:CCZ CC_REGNUM)
3238 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3241 (set (match_operand:SI 0 "register_operand" "=d")
3242 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3245 operands[2] = GEN_INT (S390_TDC_INFINITY);
3248 ; This extracts CC into a GPR properly shifted. The actual IPM
3249 ; instruction will be issued by reload. The constraint of operand 1
3250 ; forces reload to use a GPR. So reload will issue a movcc insn for
3251 ; copying CC into a GPR first.
3252 (define_insn_and_split "*cc_to_int"
3253 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3254 (unspec:SI [(match_operand 1 "register_operand" "0")]
3259 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3261 ; This insn is used to generate all variants of the Test Data Class
3262 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
3263 ; is the register to be tested and the second one is the bit mask
3264 ; specifying the required test(s).
3266 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3267 (define_insn "*TDC_insn_<mode>"
3268 [(set (reg:CCZ CC_REGNUM)
3269 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3270 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3272 "t<_d>c<xde><bt>\t%0,%1"
3273 [(set_attr "op_type" "RXE")
3274 (set_attr "type" "fsimp<mode>")])
3279 ; setmemM instruction pattern(s).
3282 (define_expand "setmem<mode>"
3283 [(set (match_operand:BLK 0 "memory_operand" "")
3284 (match_operand:QI 2 "general_operand" ""))
3285 (use (match_operand:GPR 1 "general_operand" ""))
3286 (match_operand 3 "" "")]
3288 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3290 ; Clear a block that is up to 256 bytes in length.
3291 ; The block length is taken as (operands[1] % 256) + 1.
3293 (define_expand "clrmem_short"
3295 [(set (match_operand:BLK 0 "memory_operand" "")
3297 (use (match_operand 1 "nonmemory_operand" ""))
3298 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3299 (clobber (match_dup 2))
3300 (clobber (reg:CC CC_REGNUM))])]
3302 "operands[2] = gen_rtx_SCRATCH (Pmode);")
3304 (define_insn "*clrmem_short"
3305 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3307 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3308 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3309 (clobber (match_scratch:P 3 "=X,X,X,&a"))
3310 (clobber (reg:CC CC_REGNUM))]
3311 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3313 [(set_attr "type" "cs")
3314 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3317 [(set (match_operand:BLK 0 "memory_operand" "")
3319 (use (match_operand 1 "const_int_operand" ""))
3320 (use (match_operand 2 "immediate_operand" ""))
3322 (clobber (reg:CC CC_REGNUM))]
3325 [(set (match_dup 0) (const_int 0))
3327 (clobber (reg:CC CC_REGNUM))])]
3328 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3331 [(set (match_operand:BLK 0 "memory_operand" "")
3333 (use (match_operand 1 "register_operand" ""))
3334 (use (match_operand 2 "memory_operand" ""))
3336 (clobber (reg:CC CC_REGNUM))]
3339 [(unspec [(match_dup 1) (match_dup 2)
3340 (const_int 0)] UNSPEC_EXECUTE)
3341 (set (match_dup 0) (const_int 0))
3343 (clobber (reg:CC CC_REGNUM))])]
3347 [(set (match_operand:BLK 0 "memory_operand" "")
3349 (use (match_operand 1 "register_operand" ""))
3350 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3352 (clobber (reg:CC CC_REGNUM))]
3353 "TARGET_Z10 && reload_completed"
3355 [(unspec [(match_dup 1) (const_int 0)
3356 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3357 (set (match_dup 0) (const_int 0))
3359 (clobber (reg:CC CC_REGNUM))])]
3360 "operands[3] = gen_label_rtx ();")
3363 [(set (match_operand:BLK 0 "memory_operand" "")
3365 (use (match_operand 1 "register_operand" ""))
3366 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3367 (clobber (match_operand 2 "register_operand" ""))
3368 (clobber (reg:CC CC_REGNUM))]
3369 "reload_completed && TARGET_CPU_ZARCH"
3370 [(set (match_dup 2) (label_ref (match_dup 3)))
3372 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3373 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3374 (set (match_dup 0) (const_int 0))
3376 (clobber (reg:CC CC_REGNUM))])]
3377 "operands[3] = gen_label_rtx ();")
3379 ; Initialize a block of arbitrary length with (operands[2] % 256).
3381 (define_expand "setmem_long_<P:mode>"
3383 [(clobber (match_dup 1))
3384 (set (match_operand:BLK 0 "memory_operand" "")
3385 (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
3386 (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3388 (clobber (reg:CC CC_REGNUM))])]
3391 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3392 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3393 rtx reg0 = gen_reg_rtx (dreg_mode);
3394 rtx reg1 = gen_reg_rtx (dreg_mode);
3395 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3396 rtx len0 = gen_lowpart (Pmode, reg0);
3398 emit_clobber (reg0);
3399 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3400 emit_move_insn (len0, operands[1]);
3402 emit_move_insn (reg1, const0_rtx);
3404 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3407 operands[4] = gen_lowpart (Pmode, operands[1]);
3410 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3412 (define_insn "*setmem_long"
3413 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3414 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3415 (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
3416 (subreg:P (match_dup 3) <modesize>)]
3417 UNSPEC_REPLICATE_BYTE))
3418 (use (match_operand:<DBL> 1 "register_operand" "d"))
3419 (clobber (reg:CC CC_REGNUM))]
3420 "TARGET_64BIT || !TARGET_ZARCH"
3421 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3422 [(set_attr "length" "8")
3423 (set_attr "type" "vs")])
3425 (define_insn "*setmem_long_and"
3426 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3427 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3428 (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y"))
3429 (subreg:P (match_dup 3) <modesize>)]
3430 UNSPEC_REPLICATE_BYTE))
3431 (use (match_operand:<DBL> 1 "register_operand" "d"))
3432 (clobber (reg:CC CC_REGNUM))]
3433 "(TARGET_64BIT || !TARGET_ZARCH)"
3434 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3435 [(set_attr "length" "8")
3436 (set_attr "type" "vs")])
3438 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3439 ; of the SImode subregs.
3441 (define_insn "*setmem_long_31z"
3442 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3443 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3444 (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
3445 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3446 (use (match_operand:TI 1 "register_operand" "d"))
3447 (clobber (reg:CC CC_REGNUM))]
3448 "!TARGET_64BIT && TARGET_ZARCH"
3449 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3450 [(set_attr "length" "8")
3451 (set_attr "type" "vs")])
3453 (define_insn "*setmem_long_and_31z"
3454 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3455 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3456 (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y"))
3457 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3458 (use (match_operand:TI 1 "register_operand" "d"))
3459 (clobber (reg:CC CC_REGNUM))]
3460 "(!TARGET_64BIT && TARGET_ZARCH)"
3461 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3462 [(set_attr "length" "8")
3463 (set_attr "type" "vs")])
3466 ; cmpmemM instruction pattern(s).
3469 (define_expand "cmpmemsi"
3470 [(set (match_operand:SI 0 "register_operand" "")
3471 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3472 (match_operand:BLK 2 "memory_operand" "") ) )
3473 (use (match_operand:SI 3 "general_operand" ""))
3474 (use (match_operand:SI 4 "" ""))]
3477 if (s390_expand_cmpmem (operands[0], operands[1],
3478 operands[2], operands[3]))
3484 ; Compare a block that is up to 256 bytes in length.
3485 ; The block length is taken as (operands[2] % 256) + 1.
3487 (define_expand "cmpmem_short"
3489 [(set (reg:CCU CC_REGNUM)
3490 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3491 (match_operand:BLK 1 "memory_operand" "")))
3492 (use (match_operand 2 "nonmemory_operand" ""))
3493 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3494 (clobber (match_dup 3))])]
3496 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3498 (define_insn "*cmpmem_short"
3499 [(set (reg:CCU CC_REGNUM)
3500 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3501 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3502 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3503 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3504 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3505 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3507 [(set_attr "type" "cs")
3508 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3511 [(set (reg:CCU CC_REGNUM)
3512 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3513 (match_operand:BLK 1 "memory_operand" "")))
3514 (use (match_operand 2 "const_int_operand" ""))
3515 (use (match_operand 3 "immediate_operand" ""))
3516 (clobber (scratch))]
3519 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3520 (use (match_dup 2))])]
3521 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3524 [(set (reg:CCU CC_REGNUM)
3525 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3526 (match_operand:BLK 1 "memory_operand" "")))
3527 (use (match_operand 2 "register_operand" ""))
3528 (use (match_operand 3 "memory_operand" ""))
3529 (clobber (scratch))]
3532 [(unspec [(match_dup 2) (match_dup 3)
3533 (const_int 0)] UNSPEC_EXECUTE)
3534 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3535 (use (const_int 1))])]
3539 [(set (reg:CCU CC_REGNUM)
3540 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3541 (match_operand:BLK 1 "memory_operand" "")))
3542 (use (match_operand 2 "register_operand" ""))
3543 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3544 (clobber (scratch))]
3545 "TARGET_Z10 && reload_completed"
3547 [(unspec [(match_dup 2) (const_int 0)
3548 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3549 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3550 (use (const_int 1))])]
3551 "operands[4] = gen_label_rtx ();")
3554 [(set (reg:CCU CC_REGNUM)
3555 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3556 (match_operand:BLK 1 "memory_operand" "")))
3557 (use (match_operand 2 "register_operand" ""))
3558 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3559 (clobber (match_operand 3 "register_operand" ""))]
3560 "reload_completed && TARGET_CPU_ZARCH"
3561 [(set (match_dup 3) (label_ref (match_dup 4)))
3563 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3564 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3565 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3566 (use (const_int 1))])]
3567 "operands[4] = gen_label_rtx ();")
3569 ; Compare a block of arbitrary length.
3571 (define_expand "cmpmem_long"
3573 [(clobber (match_dup 2))
3574 (clobber (match_dup 3))
3575 (set (reg:CCU CC_REGNUM)
3576 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3577 (match_operand:BLK 1 "memory_operand" "")))
3578 (use (match_operand 2 "general_operand" ""))
3579 (use (match_dup 3))])]
3582 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3583 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3584 rtx reg0 = gen_reg_rtx (dreg_mode);
3585 rtx reg1 = gen_reg_rtx (dreg_mode);
3586 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3587 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3588 rtx len0 = gen_lowpart (Pmode, reg0);
3589 rtx len1 = gen_lowpart (Pmode, reg1);
3591 emit_clobber (reg0);
3592 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3593 emit_move_insn (len0, operands[2]);
3595 emit_clobber (reg1);
3596 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3597 emit_move_insn (len1, operands[2]);
3599 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3600 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3605 (define_insn "*cmpmem_long"
3606 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3607 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3608 (set (reg:CCU CC_REGNUM)
3609 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3610 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3612 (use (match_dup 3))]
3613 "TARGET_64BIT || !TARGET_ZARCH"
3614 "clcle\t%0,%1,0\;jo\t.-4"
3615 [(set_attr "length" "8")
3616 (set_attr "type" "vs")])
3618 (define_insn "*cmpmem_long_31z"
3619 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3620 (clobber (match_operand:TI 1 "register_operand" "=d"))
3621 (set (reg:CCU CC_REGNUM)
3622 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3623 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3625 (use (match_dup 3))]
3626 "!TARGET_64BIT && TARGET_ZARCH"
3627 "clcle\t%0,%1,0\;jo\t.-4"
3628 [(set_attr "op_type" "NN")
3629 (set_attr "type" "vs")
3630 (set_attr "length" "8")])
3632 ; Convert CCUmode condition code to integer.
3633 ; Result is zero if EQ, positive if LTU, negative if GTU.
3635 (define_insn_and_split "cmpint"
3636 [(set (match_operand:SI 0 "register_operand" "=d")
3637 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3638 UNSPEC_STRCMPCC_TO_INT))
3639 (clobber (reg:CC CC_REGNUM))]
3643 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3645 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3646 (clobber (reg:CC CC_REGNUM))])])
3648 (define_insn_and_split "*cmpint_cc"
3649 [(set (reg CC_REGNUM)
3650 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3651 UNSPEC_STRCMPCC_TO_INT)
3653 (set (match_operand:SI 0 "register_operand" "=d")
3654 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3655 "s390_match_ccmode (insn, CCSmode)"
3657 "&& reload_completed"
3658 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3660 [(set (match_dup 2) (match_dup 3))
3661 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3663 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3664 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3665 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3668 (define_insn_and_split "*cmpint_sign"
3669 [(set (match_operand:DI 0 "register_operand" "=d")
3670 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3671 UNSPEC_STRCMPCC_TO_INT)))
3672 (clobber (reg:CC CC_REGNUM))]
3675 "&& reload_completed"
3676 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3678 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3679 (clobber (reg:CC CC_REGNUM))])])
3681 (define_insn_and_split "*cmpint_sign_cc"
3682 [(set (reg CC_REGNUM)
3683 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3684 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3685 UNSPEC_STRCMPCC_TO_INT) 0)
3686 (const_int 32)) (const_int 32))
3688 (set (match_operand:DI 0 "register_operand" "=d")
3689 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3690 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3692 "&& reload_completed"
3693 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3695 [(set (match_dup 2) (match_dup 3))
3696 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3698 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3699 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3700 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3705 ;;- Conversion instructions.
3708 (define_insn "*sethighpartsi"
3709 [(set (match_operand:SI 0 "register_operand" "=d,d")
3710 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3711 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3712 (clobber (reg:CC CC_REGNUM))]
3717 [(set_attr "op_type" "RS,RSY")
3718 (set_attr "cpu_facility" "*,longdisp")
3719 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3721 (define_insn "*sethighpartdi_64"
3722 [(set (match_operand:DI 0 "register_operand" "=d")
3723 (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
3724 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3725 (clobber (reg:CC CC_REGNUM))]
3728 [(set_attr "op_type" "RSY")
3729 (set_attr "z10prop" "z10_super")])
3731 (define_insn "*sethighpartdi_31"
3732 [(set (match_operand:DI 0 "register_operand" "=d,d")
3733 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3734 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3735 (clobber (reg:CC CC_REGNUM))]
3740 [(set_attr "op_type" "RS,RSY")
3741 (set_attr "cpu_facility" "*,longdisp")
3742 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3745 ; extv instruction patterns
3748 ; FIXME: This expander needs to be converted from DI to GPR as well
3749 ; after resolving some issues with it.
3751 (define_expand "extzv"
3753 [(set (match_operand:DI 0 "register_operand" "=d")
3755 (match_operand:DI 1 "register_operand" "d")
3756 (match_operand 2 "const_int_operand" "") ; size
3757 (match_operand 3 "const_int_operand" ""))) ; start
3758 (clobber (reg:CC CC_REGNUM))])]
3761 if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64))
3763 /* Starting with zEC12 there is risbgn not clobbering CC. */
3766 emit_move_insn (operands[0],
3767 gen_rtx_ZERO_EXTRACT (DImode,
3775 (define_insn "*extzv<mode><clobbercc_or_nocc>"
3776 [(set (match_operand:GPR 0 "register_operand" "=d")
3778 (match_operand:GPR 1 "register_operand" "d")
3779 (match_operand 2 "const_int_operand" "") ; size
3780 (match_operand 3 "const_int_operand" ""))) ; start
3782 "<z10_or_zEC12_cond>
3783 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]),
3784 GET_MODE_BITSIZE (<MODE>mode))"
3785 "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
3786 [(set_attr "op_type" "RIE")
3787 (set_attr "z10prop" "z10_super_E1")])
3789 ; 64 bit: (a & -16) | ((b >> 8) & 15)
3790 (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt"
3791 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3792 (match_operand 1 "const_int_operand" "") ; size
3793 (match_operand 2 "const_int_operand" "")) ; start
3794 (lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
3795 (match_operand:DI 4 "nonzero_shift_count_operand" "")))]
3796 "<z10_or_zEC12_cond>
3797 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
3798 && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
3799 "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
3800 [(set_attr "op_type" "RIE")
3801 (set_attr "z10prop" "z10_super_E1")])
3803 ; 32 bit: (a & -16) | ((b >> 8) & 15)
3804 (define_insn "*<risbg_n>_ior_and_sr_ze"
3805 [(set (match_operand:SI 0 "register_operand" "=d")
3807 (match_operand:SI 1 "register_operand" "0")
3808 (match_operand:SI 2 "const_int_operand" ""))
3811 (match_operand:DI 3 "register_operand" "d")
3812 (match_operand 4 "const_int_operand" "") ; size
3813 (match_operand 5 "const_int_operand" "")) ; start
3815 "<z10_or_zEC12_cond>
3816 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
3817 && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
3818 "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
3819 [(set_attr "op_type" "RIE")
3820 (set_attr "z10prop" "z10_super_E1")])
3822 ; ((int)foo >> 10) & 1;
3823 (define_insn "*extract1bitdi<clobbercc_or_nocc>"
3824 [(set (match_operand:DI 0 "register_operand" "=d")
3825 (ne:DI (zero_extract:DI
3826 (match_operand:DI 1 "register_operand" "d")
3827 (const_int 1) ; size
3828 (match_operand 2 "const_int_operand" "")) ; start
3830 "<z10_or_zEC12_cond>
3831 && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)"
3832 "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
3833 [(set_attr "op_type" "RIE")
3834 (set_attr "z10prop" "z10_super_E1")])
3836 (define_insn "*<risbg_n>_and_subregdi_rotr"
3837 [(set (match_operand:DI 0 "register_operand" "=d")
3839 (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3840 (match_operand:SINT 2 "const_int_operand" "")) 0)
3841 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3842 "<z10_or_zEC12_cond>
3843 && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))"
3844 "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
3845 [(set_attr "op_type" "RIE")
3846 (set_attr "z10prop" "z10_super_E1")])
3848 (define_insn "*<risbg_n>_and_subregdi_rotl"
3849 [(set (match_operand:DI 0 "register_operand" "=d")
3851 (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3852 (match_operand:SINT 2 "const_int_operand" "")) 0)
3853 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3854 "<z10_or_zEC12_cond>
3855 && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))"
3856 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3857 [(set_attr "op_type" "RIE")
3858 (set_attr "z10prop" "z10_super_E1")])
3860 (define_insn "*<risbg_n>_di_and_rot"
3861 [(set (match_operand:DI 0 "register_operand" "=d")
3862 (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d")
3863 (match_operand:DI 2 "const_int_operand" ""))
3864 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3865 "<z10_or_zEC12_cond>"
3866 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3867 [(set_attr "op_type" "RIE")
3868 (set_attr "z10prop" "z10_super_E1")])
3870 (define_insn_and_split "*pre_z10_extzv<mode>"
3871 [(set (match_operand:GPR 0 "register_operand" "=d")
3872 (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
3873 (match_operand 2 "nonzero_shift_count_operand" "")
3875 (clobber (reg:CC CC_REGNUM))]
3878 "&& reload_completed"
3880 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3881 (clobber (reg:CC CC_REGNUM))])
3882 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3884 int bitsize = INTVAL (operands[2]);
3885 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3886 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3888 operands[1] = adjust_address (operands[1], BLKmode, 0);
3889 set_mem_size (operands[1], size);
3890 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3891 operands[3] = GEN_INT (mask);
3894 (define_insn_and_split "*pre_z10_extv<mode>"
3895 [(set (match_operand:GPR 0 "register_operand" "=d")
3896 (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
3897 (match_operand 2 "nonzero_shift_count_operand" "")
3899 (clobber (reg:CC CC_REGNUM))]
3902 "&& reload_completed"
3904 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3905 (clobber (reg:CC CC_REGNUM))])
3907 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3908 (clobber (reg:CC CC_REGNUM))])]
3910 int bitsize = INTVAL (operands[2]);
3911 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3912 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3914 operands[1] = adjust_address (operands[1], BLKmode, 0);
3915 set_mem_size (operands[1], size);
3916 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3917 operands[3] = GEN_INT (mask);
3921 ; insv instruction patterns
3924 (define_expand "insv"
3925 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3926 (match_operand 1 "const_int_operand" "")
3927 (match_operand 2 "const_int_operand" ""))
3928 (match_operand 3 "general_operand" ""))]
3931 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3937 ; The normal RTL expansion will never generate a zero_extract where
3938 ; the location operand isn't word mode. However, we do this in the
3939 ; back-end when generating atomic operations. See s390_two_part_insv.
3940 (define_insn "*insv<mode><clobbercc_or_nocc>"
3941 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3942 (match_operand 1 "const_int_operand" "I") ; size
3943 (match_operand 2 "const_int_operand" "I")) ; pos
3944 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3945 "<z10_or_zEC12_cond>
3946 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]),
3947 GET_MODE_BITSIZE (<MODE>mode))
3948 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3949 "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
3950 [(set_attr "op_type" "RIE")
3951 (set_attr "z10prop" "z10_super_E1")])
3953 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3954 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3955 (define_insn "*insv<mode><clobbercc_or_nocc>_noshift"
3956 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d")
3957 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0")
3958 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3959 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d")
3960 (match_operand:GPR 4 "const_int_operand" ""))))]
3961 "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3963 <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0
3964 <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0"
3965 [(set_attr "op_type" "RIE")
3966 (set_attr "z10prop" "z10_super_E1")])
3968 (define_insn "*insv_z10_noshift_cc"
3969 [(set (reg CC_REGNUM)
3972 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
3973 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3974 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
3975 (match_operand:DI 4 "const_int_operand" "")))
3977 (set (match_operand:DI 0 "nonimmediate_operand" "=d,d")
3978 (ior:DI (and:DI (match_dup 1) (match_dup 2))
3979 (and:DI (match_dup 3) (match_dup 4))))]
3980 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
3981 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3983 risbg\t%0,%1,%s2,%e2,0
3984 risbg\t%0,%3,%s4,%e4,0"
3985 [(set_attr "op_type" "RIE")
3986 (set_attr "z10prop" "z10_super_E1")])
3988 (define_insn "*insv_z10_noshift_cconly"
3993 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
3994 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3995 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
3996 (match_operand:DI 4 "const_int_operand" "")))
3998 (clobber (match_scratch:DI 0 "=d,d"))]
3999 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
4000 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
4002 risbg\t%0,%1,%s2,%e2,0
4003 risbg\t%0,%3,%s4,%e4,0"
4004 [(set_attr "op_type" "RIE")
4005 (set_attr "z10prop" "z10_super_E1")])
4007 ; Implement appending Y on the left of S bits of X
4008 ; x = (y << s) | (x & ((1 << s) - 1))
4009 (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft"
4010 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4011 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
4012 (match_operand:GPR 2 "immediate_operand" ""))
4013 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
4014 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4015 "<z10_or_zEC12_cond>
4016 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
4017 "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
4018 [(set_attr "op_type" "RIE")
4019 (set_attr "z10prop" "z10_super_E1")])
4021 ; a = ((i32)a & -16777216) | (((ui32)b) >> 8)
4022 (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt"
4023 [(set (match_operand:GPR 0 "register_operand" "=d")
4025 (match_operand:GPR 1 "register_operand" "0")
4026 (match_operand:GPR 2 "const_int_operand" ""))
4028 (match_operand:GPR 3 "register_operand" "d")
4029 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4030 "<z10_or_zEC12_cond> && UINTVAL (operands[2])
4031 == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
4032 "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
4033 [(set_attr "op_type" "RIE")
4034 (set_attr "z10prop" "z10_super_E1")])
4036 ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536);
4037 (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt"
4038 [(set (match_operand:SI 0 "register_operand" "=d")
4040 (match_operand:SI 1 "register_operand" "0")
4041 (match_operand:SI 2 "const_int_operand" ""))
4044 (match_operand:DI 3 "register_operand" "d")
4045 (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
4046 "<z10_or_zEC12_cond>
4047 && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))"
4048 "<risbg_n>\t%0,%3,%4,63,64-%4"
4049 [(set_attr "op_type" "RIE")
4050 (set_attr "z10prop" "z10_super_E1")])
4052 ; (ui32)(((ui64)x) >> 12) & -4
4053 (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>"
4054 [(set (match_operand:SI 0 "register_operand" "=d")
4056 (subreg:SI (lshiftrt:DI
4057 (match_operand:DI 1 "register_operand" "d")
4058 (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4)
4059 (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))]
4060 "<z10_or_zEC12_cond>"
4061 "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2"
4062 [(set_attr "op_type" "RIE")
4063 (set_attr "z10prop" "z10_super_E1")])
4065 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
4066 ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
4067 ; -> z = y >> d; z = risbg;
4070 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4071 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4072 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4073 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4074 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4075 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4077 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4079 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4080 (ashift:GPR (match_dup 3) (match_dup 4))))]
4082 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4083 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4085 if (!can_create_pseudo_p ())
4087 operands[6] = gen_reg_rtx (<MODE>mode);
4090 operands[6] = operands[0];
4095 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4096 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4097 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4098 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4099 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
4100 (clobber (reg:CC CC_REGNUM))])]
4101 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4103 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4106 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4107 (ashift:GPR (match_dup 3) (match_dup 4))))
4108 (clobber (reg:CC CC_REGNUM))])]
4110 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4111 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4113 if (!can_create_pseudo_p ())
4115 operands[6] = gen_reg_rtx (<MODE>mode);
4118 operands[6] = operands[0];
4122 (define_insn "*r<noxa>sbg_<mode>_noshift"
4123 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4125 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
4126 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4127 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4128 (clobber (reg:CC CC_REGNUM))]
4130 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
4131 [(set_attr "op_type" "RIE")])
4134 (define_insn "*r<noxa>sbg_di_rotl"
4135 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4139 (match_operand:DI 1 "nonimmediate_operand" "d")
4140 (match_operand:DI 3 "const_int_operand" ""))
4141 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4142 (match_operand:DI 4 "nonimmediate_operand" "0")))
4143 (clobber (reg:CC CC_REGNUM))]
4145 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
4146 [(set_attr "op_type" "RIE")])
4149 (define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
4150 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4154 (match_operand:GPR 1 "nonimmediate_operand" "d")
4155 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4156 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
4157 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4158 (clobber (reg:CC CC_REGNUM))]
4160 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
4161 INTVAL (operands[2]))"
4162 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
4163 [(set_attr "op_type" "RIE")])
4166 (define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
4167 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4171 (match_operand:GPR 1 "nonimmediate_operand" "d")
4172 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4173 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
4174 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4175 (clobber (reg:CC CC_REGNUM))]
4177 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
4178 INTVAL (operands[2]))"
4179 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
4180 [(set_attr "op_type" "RIE")])
4182 ;; unsigned {int,long} a, b
4183 ;; a = a | (b << const_int)
4184 ;; a = a ^ (b << const_int)
4186 (define_insn "*r<noxa>sbg_<mode>_sll"
4187 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4190 (match_operand:GPR 1 "nonimmediate_operand" "d")
4191 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4192 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4193 (clobber (reg:CC CC_REGNUM))]
4195 "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2"
4196 [(set_attr "op_type" "RIE")])
4198 ;; unsigned {int,long} a, b
4199 ;; a = a | (b >> const_int)
4200 ;; a = a ^ (b >> const_int)
4202 (define_insn "*r<noxa>sbg_<mode>_srl"
4203 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4206 (match_operand:GPR 1 "nonimmediate_operand" "d")
4207 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4208 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4209 (clobber (reg:CC CC_REGNUM))]
4211 "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2"
4212 [(set_attr "op_type" "RIE")])
4214 ;; These two are generated by combine for s.bf &= val.
4215 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
4216 ;; shifts and ands, which results in some truly awful patterns
4217 ;; including subregs of operations. Rather unnecessisarily, IMO.
4220 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4221 ;; (const_int 24 [0x18])
4222 ;; (const_int 0 [0]))
4223 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
4224 ;; (const_int 40 [0x28])) 4)
4225 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
4227 ;; we should instead generate
4229 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4230 ;; (const_int 24 [0x18])
4231 ;; (const_int 0 [0]))
4232 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
4233 ;; (const_int 40 [0x28]))
4234 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
4236 ;; by noticing that we can push down the outer paradoxical subreg
4237 ;; into the operation.
4239 (define_insn "*insv_rnsbg_noshift"
4240 [(set (zero_extract:DI
4241 (match_operand:DI 0 "nonimmediate_operand" "+d")
4242 (match_operand 1 "const_int_operand" "")
4243 (match_operand 2 "const_int_operand" ""))
4246 (match_operand:DI 3 "nonimmediate_operand" "d")))
4247 (clobber (reg:CC CC_REGNUM))]
4249 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
4250 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4251 "rnsbg\t%0,%3,%2,63,0"
4252 [(set_attr "op_type" "RIE")])
4254 (define_insn "*insv_rnsbg_srl"
4255 [(set (zero_extract:DI
4256 (match_operand:DI 0 "nonimmediate_operand" "+d")
4257 (match_operand 1 "const_int_operand" "")
4258 (match_operand 2 "const_int_operand" ""))
4262 (match_operand 3 "const_int_operand" ""))
4263 (match_operand:DI 4 "nonimmediate_operand" "d")))
4264 (clobber (reg:CC CC_REGNUM))]
4266 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
4267 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4268 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4269 [(set_attr "op_type" "RIE")])
4271 (define_insn "*insv<mode>_mem_reg"
4272 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4273 (match_operand 1 "const_int_operand" "n,n")
4275 (match_operand:W 2 "register_operand" "d,d"))]
4276 "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
4277 && INTVAL (operands[1]) > 0
4278 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4279 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4281 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4283 operands[1] = GEN_INT ((1ul << size) - 1);
4284 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4285 : "stcmy\t%2,%1,%S0";
4287 [(set_attr "op_type" "RS,RSY")
4288 (set_attr "cpu_facility" "*,longdisp")
4289 (set_attr "z10prop" "z10_super,z10_super")])
4291 (define_insn "*insvdi_mem_reghigh"
4292 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
4293 (match_operand 1 "const_int_operand" "n")
4295 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4298 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
4299 && INTVAL (operands[1]) > 0
4300 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4301 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4303 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4305 operands[1] = GEN_INT ((1ul << size) - 1);
4306 return "stcmh\t%2,%1,%S0";
4308 [(set_attr "op_type" "RSY")
4309 (set_attr "z10prop" "z10_super")])
4311 (define_insn "*insvdi_reg_imm"
4312 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4314 (match_operand 1 "const_int_operand" "n"))
4315 (match_operand:DI 2 "const_int_operand" "n"))]
4317 && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64)
4318 && INTVAL (operands[1]) >= 0
4319 && INTVAL (operands[1]) < BITS_PER_WORD
4320 && INTVAL (operands[1]) % 16 == 0"
4322 switch (BITS_PER_WORD - INTVAL (operands[1]))
4324 case 64: return "iihh\t%0,%x2"; break;
4325 case 48: return "iihl\t%0,%x2"; break;
4326 case 32: return "iilh\t%0,%x2"; break;
4327 case 16: return "iill\t%0,%x2"; break;
4328 default: gcc_unreachable();
4331 [(set_attr "op_type" "RI")
4332 (set_attr "z10prop" "z10_super_E1")])
4334 ; Update the left-most 32 bit of a DI.
4335 (define_insn "*insv_h_di_reg_extimm"
4336 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4339 (match_operand:DI 1 "const_int_operand" "n"))]
4342 [(set_attr "op_type" "RIL")
4343 (set_attr "z10prop" "z10_fwd_E1")])
4345 ; Update the right-most 32 bit of a DI.
4346 (define_insn "*insv_l_di_reg_extimm"
4347 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4350 (match_operand:DI 1 "const_int_operand" "n"))]
4353 [(set_attr "op_type" "RIL")
4354 (set_attr "z10prop" "z10_fwd_A1")])
4357 ; extendsidi2 instruction pattern(s).
4360 (define_expand "extendsidi2"
4361 [(set (match_operand:DI 0 "register_operand" "")
4362 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4367 emit_clobber (operands[0]);
4368 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4369 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4370 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4375 (define_insn "*extendsidi2"
4376 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4377 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4383 [(set_attr "op_type" "RRE,RXY,RIL")
4384 (set_attr "type" "*,*,larl")
4385 (set_attr "cpu_facility" "*,*,z10")
4386 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4389 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4392 (define_expand "extend<HQI:mode><DSI:mode>2"
4393 [(set (match_operand:DSI 0 "register_operand" "")
4394 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4397 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4399 rtx tmp = gen_reg_rtx (SImode);
4400 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4401 emit_insn (gen_extendsidi2 (operands[0], tmp));
4404 else if (!TARGET_EXTIMM)
4406 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4408 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4409 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4410 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4416 ; extendhidi2 instruction pattern(s).
4419 (define_insn "*extendhidi2_extimm"
4420 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4421 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
4422 "TARGET_ZARCH && TARGET_EXTIMM"
4427 [(set_attr "op_type" "RRE,RXY,RIL")
4428 (set_attr "type" "*,*,larl")
4429 (set_attr "cpu_facility" "extimm,extimm,z10")
4430 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4432 (define_insn "*extendhidi2"
4433 [(set (match_operand:DI 0 "register_operand" "=d")
4434 (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
4437 [(set_attr "op_type" "RXY")
4438 (set_attr "z10prop" "z10_super_E1")])
4441 ; extendhisi2 instruction pattern(s).
4444 (define_insn "*extendhisi2_extimm"
4445 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4446 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4453 [(set_attr "op_type" "RRE,RX,RXY,RIL")
4454 (set_attr "type" "*,*,*,larl")
4455 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4456 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4458 (define_insn "*extendhisi2"
4459 [(set (match_operand:SI 0 "register_operand" "=d,d")
4460 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4465 [(set_attr "op_type" "RX,RXY")
4466 (set_attr "cpu_facility" "*,longdisp")
4467 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4470 ; extendqi(si|di)2 instruction pattern(s).
4473 ; lbr, lgbr, lb, lgb
4474 (define_insn "*extendqi<mode>2_extimm"
4475 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4476 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
4481 [(set_attr "op_type" "RRE,RXY")
4482 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4485 (define_insn "*extendqi<mode>2"
4486 [(set (match_operand:GPR 0 "register_operand" "=d")
4487 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
4488 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4490 [(set_attr "op_type" "RXY")
4491 (set_attr "z10prop" "z10_super_E1")])
4493 (define_insn_and_split "*extendqi<mode>2_short_displ"
4494 [(set (match_operand:GPR 0 "register_operand" "=d")
4495 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4496 (clobber (reg:CC CC_REGNUM))]
4497 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4499 "&& reload_completed"
4501 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4502 (clobber (reg:CC CC_REGNUM))])
4504 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4505 (clobber (reg:CC CC_REGNUM))])]
4507 operands[1] = adjust_address (operands[1], BLKmode, 0);
4508 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4509 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4513 ; zero_extendsidi2 instruction pattern(s).
4516 (define_expand "zero_extendsidi2"
4517 [(set (match_operand:DI 0 "register_operand" "")
4518 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4523 emit_clobber (operands[0]);
4524 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4525 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4530 (define_insn "*zero_extendsidi2"
4531 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4532 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4538 [(set_attr "op_type" "RRE,RXY,RIL")
4539 (set_attr "type" "*,*,larl")
4540 (set_attr "cpu_facility" "*,*,z10")
4541 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4544 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4547 (define_insn "*llgt_sidi"
4548 [(set (match_operand:DI 0 "register_operand" "=d")
4549 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4550 (const_int 2147483647)))]
4553 [(set_attr "op_type" "RXE")
4554 (set_attr "z10prop" "z10_super_E1")])
4556 (define_insn_and_split "*llgt_sidi_split"
4557 [(set (match_operand:DI 0 "register_operand" "=d")
4558 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4559 (const_int 2147483647)))
4560 (clobber (reg:CC CC_REGNUM))]
4563 "&& reload_completed"
4565 (and:DI (subreg:DI (match_dup 1) 0)
4566 (const_int 2147483647)))]
4569 (define_insn "*llgt_sisi"
4570 [(set (match_operand:SI 0 "register_operand" "=d,d")
4571 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
4572 (const_int 2147483647)))]
4577 [(set_attr "op_type" "RRE,RXE")
4578 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4580 (define_insn "*llgt_didi"
4581 [(set (match_operand:DI 0 "register_operand" "=d,d")
4582 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4583 (const_int 2147483647)))]
4588 [(set_attr "op_type" "RRE,RXE")
4589 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4592 [(set (match_operand:DSI 0 "register_operand" "")
4593 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4594 (const_int 2147483647)))
4595 (clobber (reg:CC CC_REGNUM))]
4596 "TARGET_ZARCH && reload_completed"
4598 (and:DSI (match_dup 1)
4599 (const_int 2147483647)))]
4603 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4606 (define_expand "zero_extend<mode>di2"
4607 [(set (match_operand:DI 0 "register_operand" "")
4608 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4613 rtx tmp = gen_reg_rtx (SImode);
4614 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4615 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4618 else if (!TARGET_EXTIMM)
4620 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4621 operands[1] = gen_lowpart (DImode, operands[1]);
4622 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4623 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4628 (define_expand "zero_extend<mode>si2"
4629 [(set (match_operand:SI 0 "register_operand" "")
4630 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4635 operands[1] = gen_lowpart (SImode, operands[1]);
4636 emit_insn (gen_andsi3 (operands[0], operands[1],
4637 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4643 (define_insn "*zero_extendhi<mode>2_z10"
4644 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4645 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
4651 [(set_attr "op_type" "RXY,RRE,RIL")
4652 (set_attr "type" "*,*,larl")
4653 (set_attr "cpu_facility" "*,*,z10")
4654 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4656 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4657 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4658 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4659 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
4664 [(set_attr "op_type" "RRE,RXY")
4665 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4668 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4669 [(set (match_operand:GPR 0 "register_operand" "=d")
4670 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
4671 "TARGET_ZARCH && !TARGET_EXTIMM"
4673 [(set_attr "op_type" "RXY")
4674 (set_attr "z10prop" "z10_fwd_A3")])
4676 (define_insn_and_split "*zero_extendhisi2_31"
4677 [(set (match_operand:SI 0 "register_operand" "=&d")
4678 (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
4679 (clobber (reg:CC CC_REGNUM))]
4682 "&& reload_completed"
4683 [(set (match_dup 0) (const_int 0))
4685 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4686 (clobber (reg:CC CC_REGNUM))])]
4687 "operands[2] = gen_lowpart (HImode, operands[0]);")
4689 (define_insn_and_split "*zero_extendqisi2_31"
4690 [(set (match_operand:SI 0 "register_operand" "=&d")
4691 (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
4694 "&& reload_completed"
4695 [(set (match_dup 0) (const_int 0))
4696 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4697 "operands[2] = gen_lowpart (QImode, operands[0]);")
4700 ; zero_extendqihi2 instruction pattern(s).
4703 (define_expand "zero_extendqihi2"
4704 [(set (match_operand:HI 0 "register_operand" "")
4705 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4706 "TARGET_ZARCH && !TARGET_EXTIMM"
4708 operands[1] = gen_lowpart (HImode, operands[1]);
4709 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4713 (define_insn "*zero_extendqihi2_64"
4714 [(set (match_operand:HI 0 "register_operand" "=d")
4715 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4716 "TARGET_ZARCH && !TARGET_EXTIMM"
4718 [(set_attr "op_type" "RXY")
4719 (set_attr "z10prop" "z10_fwd_A3")])
4721 (define_insn_and_split "*zero_extendqihi2_31"
4722 [(set (match_operand:HI 0 "register_operand" "=&d")
4723 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4726 "&& reload_completed"
4727 [(set (match_dup 0) (const_int 0))
4728 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4729 "operands[2] = gen_lowpart (QImode, operands[0]);")
4732 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4735 (define_expand "fixuns_truncdddi2"
4737 [(set (match_operand:DI 0 "register_operand" "")
4738 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4739 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4740 (clobber (reg:CC CC_REGNUM))])]
4746 rtx_code_label *label1 = gen_label_rtx ();
4747 rtx_code_label *label2 = gen_label_rtx ();
4748 rtx temp = gen_reg_rtx (TDmode);
4749 REAL_VALUE_TYPE cmp, sub;
4751 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4752 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4754 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4755 solution is doing the check and the subtraction in TD mode and using a
4756 TD -> DI convert afterwards. */
4757 emit_insn (gen_extendddtd2 (temp, operands[1]));
4758 temp = force_reg (TDmode, temp);
4759 emit_cmp_and_jump_insns (temp,
4760 const_double_from_real_value (cmp, TDmode),
4761 LT, NULL_RTX, VOIDmode, 0, label1);
4762 emit_insn (gen_subtd3 (temp, temp,
4763 const_double_from_real_value (sub, TDmode)));
4764 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4765 GEN_INT (DFP_RND_TOWARD_MINF)));
4768 emit_label (label1);
4769 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
4770 GEN_INT (DFP_RND_TOWARD_0)));
4771 emit_label (label2);
4776 (define_expand "fixuns_trunctddi2"
4778 [(set (match_operand:DI 0 "register_operand" "")
4779 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4780 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4781 (clobber (reg:CC CC_REGNUM))])]
4787 rtx_code_label *label1 = gen_label_rtx ();
4788 rtx_code_label *label2 = gen_label_rtx ();
4789 rtx temp = gen_reg_rtx (TDmode);
4790 REAL_VALUE_TYPE cmp, sub;
4792 operands[1] = force_reg (TDmode, operands[1]);
4793 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4794 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4796 emit_cmp_and_jump_insns (operands[1],
4797 const_double_from_real_value (cmp, TDmode),
4798 LT, NULL_RTX, VOIDmode, 0, label1);
4799 emit_insn (gen_subtd3 (temp, operands[1],
4800 const_double_from_real_value (sub, TDmode)));
4801 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4802 GEN_INT (DFP_RND_TOWARD_MINF)));
4805 emit_label (label1);
4806 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
4807 GEN_INT (DFP_RND_TOWARD_0)));
4808 emit_label (label2);
4814 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4815 ; instruction pattern(s).
4818 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4820 [(set (match_operand:GPR 0 "register_operand" "")
4821 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4822 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4823 (clobber (reg:CC CC_REGNUM))])]
4828 rtx_code_label *label1 = gen_label_rtx ();
4829 rtx_code_label *label2 = gen_label_rtx ();
4830 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4831 REAL_VALUE_TYPE cmp, sub;
4833 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4834 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4835 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4837 emit_cmp_and_jump_insns (operands[1],
4838 const_double_from_real_value (cmp, <BFP:MODE>mode),
4839 LT, NULL_RTX, VOIDmode, 0, label1);
4840 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4841 const_double_from_real_value (sub, <BFP:MODE>mode)));
4842 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4843 GEN_INT (BFP_RND_TOWARD_MINF)));
4846 emit_label (label1);
4847 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4848 operands[1], GEN_INT (BFP_RND_TOWARD_0)));
4849 emit_label (label2);
4854 ; fixuns_trunc(td|dd)si2 expander
4855 (define_expand "fixuns_trunc<mode>si2"
4857 [(set (match_operand:SI 0 "register_operand" "")
4858 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4859 (unspec:SI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4860 (clobber (reg:CC CC_REGNUM))])]
4861 "TARGET_Z196 && TARGET_HARD_DFP"
4864 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4866 (define_insn "*fixuns_truncdfdi2_z13"
4867 [(set (match_operand:DI 0 "register_operand" "=d,v")
4868 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4869 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4870 (clobber (reg:CC CC_REGNUM))]
4871 "TARGET_VX && TARGET_HARD_FLOAT"
4874 wclgdb\t%v0,%v1,0,%h2"
4875 [(set_attr "op_type" "RRF,VRR")
4876 (set_attr "type" "ftoi")])
4878 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4879 ; clfdtr, clfxtr, clgdtr, clgxtr
4880 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4881 [(set (match_operand:GPR 0 "register_operand" "=d")
4882 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4883 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4884 (clobber (reg:CC CC_REGNUM))]
4885 "TARGET_Z196 && TARGET_HARD_FLOAT
4886 && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4887 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4888 [(set_attr "op_type" "RRF")
4889 (set_attr "type" "ftoi")])
4891 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4892 [(set (match_operand:GPR 0 "register_operand" "")
4893 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4896 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4897 GEN_INT (BFP_RND_TOWARD_0)));
4901 (define_insn "*fix_truncdfdi2_bfp_z13"
4902 [(set (match_operand:DI 0 "register_operand" "=d,v")
4903 (fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4904 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4905 (clobber (reg:CC CC_REGNUM))]
4906 "TARGET_VX && TARGET_HARD_FLOAT"
4909 wcgdb\t%v0,%v1,0,%h2"
4910 [(set_attr "op_type" "RRE,VRR")
4911 (set_attr "type" "ftoi")])
4913 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4914 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4915 [(set (match_operand:GPR 0 "register_operand" "=d")
4916 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4917 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4918 (clobber (reg:CC CC_REGNUM))]
4920 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4921 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4922 [(set_attr "op_type" "RRE")
4923 (set_attr "type" "ftoi")])
4925 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4927 [(set (match_operand:GPR 0 "register_operand" "=d")
4928 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4929 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4930 (clobber (reg:CC CC_REGNUM))])]
4931 "TARGET_HARD_FLOAT")
4933 ; fix_trunc(td|dd)di2 instruction pattern(s).
4936 (define_expand "fix_trunc<mode>di2"
4937 [(set (match_operand:DI 0 "register_operand" "")
4938 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4939 "TARGET_ZARCH && TARGET_HARD_DFP"
4941 operands[1] = force_reg (<MODE>mode, operands[1]);
4942 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4943 GEN_INT (DFP_RND_TOWARD_0)));
4948 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4949 [(set (match_operand:DI 0 "register_operand" "=d")
4950 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4951 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4952 (clobber (reg:CC CC_REGNUM))]
4953 "TARGET_ZARCH && TARGET_HARD_DFP"
4954 "cg<DFP:xde>tr\t%0,%h2,%1"
4955 [(set_attr "op_type" "RRF")
4956 (set_attr "type" "ftoidfp")])
4960 ; fix_trunctf(si|di)2 instruction pattern(s).
4963 (define_expand "fix_trunctf<mode>2"
4964 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4965 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4966 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4967 (clobber (reg:CC CC_REGNUM))])]
4973 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4976 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4977 (define_insn "floatdi<mode>2"
4978 [(set (match_operand:FP 0 "register_operand" "=f,v")
4979 (float:FP (match_operand:DI 1 "register_operand" "d,v")))]
4980 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4984 [(set_attr "op_type" "RRE,VRR")
4985 (set_attr "type" "itof<mode>" )
4986 (set_attr "cpu_facility" "*,vx")
4987 (set_attr "enabled" "*,<DFDI>")])
4989 ; cxfbr, cdfbr, cefbr
4990 (define_insn "floatsi<mode>2"
4991 [(set (match_operand:BFP 0 "register_operand" "=f")
4992 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4995 [(set_attr "op_type" "RRE")
4996 (set_attr "type" "itof<mode>" )])
4999 (define_insn "floatsi<mode>2"
5000 [(set (match_operand:DFP 0 "register_operand" "=f")
5001 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
5002 "TARGET_Z196 && TARGET_HARD_FLOAT"
5003 "c<xde>ftr\t%0,0,%1,0"
5004 [(set_attr "op_type" "RRE")
5005 (set_attr "type" "itof<mode>" )])
5008 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
5011 (define_insn "*floatunsdidf2_z13"
5012 [(set (match_operand:DF 0 "register_operand" "=f,v")
5013 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
5014 "TARGET_VX && TARGET_HARD_FLOAT"
5017 wcdlgb\t%v0,%v1,0,0"
5018 [(set_attr "op_type" "RRE,VRR")
5019 (set_attr "type" "itofdf")])
5021 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
5022 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
5023 (define_insn "*floatuns<GPR:mode><FP:mode>2"
5024 [(set (match_operand:FP 0 "register_operand" "=f")
5025 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
5026 "TARGET_Z196 && TARGET_HARD_FLOAT
5027 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
5028 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
5029 [(set_attr "op_type" "RRE")
5030 (set_attr "type" "itof<FP:mode>")])
5032 (define_expand "floatuns<GPR:mode><FP:mode>2"
5033 [(set (match_operand:FP 0 "register_operand" "")
5034 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
5035 "TARGET_Z196 && TARGET_HARD_FLOAT")
5038 ; truncdfsf2 instruction pattern(s).
5041 (define_insn "truncdfsf2"
5042 [(set (match_operand:SF 0 "register_operand" "=f,v")
5043 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))]
5047 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
5048 ; According to BFP rounding mode
5049 [(set_attr "op_type" "RRE,VRR")
5050 (set_attr "type" "ftruncdf")
5051 (set_attr "cpu_facility" "*,vx")])
5054 ; trunctf(df|sf)2 instruction pattern(s).
5058 (define_insn "trunctf<mode>2"
5059 [(set (match_operand:DSF 0 "register_operand" "=f")
5060 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
5061 (clobber (match_scratch:TF 2 "=f"))]
5063 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
5064 [(set_attr "length" "6")
5065 (set_attr "type" "ftrunctf")])
5068 ; trunctddd2 and truncddsd2 instruction pattern(s).
5072 (define_expand "trunctddd2"
5074 [(set (match_operand:DD 0 "register_operand" "")
5075 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5076 (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
5077 (clobber (scratch:TD))])]
5080 (define_insn "*trunctddd2"
5081 [(set (match_operand:DD 0 "register_operand" "=f")
5082 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
5083 (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
5084 (clobber (match_scratch:TD 3 "=f"))]
5086 "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
5087 [(set_attr "length" "6")
5088 (set_attr "type" "ftruncdd")])
5090 (define_insn "truncddsd2"
5091 [(set (match_operand:SD 0 "register_operand" "=f")
5092 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
5095 [(set_attr "op_type" "RRF")
5096 (set_attr "type" "ftruncsd")])
5098 (define_expand "trunctdsd2"
5101 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5102 (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
5103 (clobber (match_scratch:TD 3 ""))])
5104 (set (match_operand:SD 0 "register_operand" "")
5105 (float_truncate:SD (match_dup 2)))]
5108 operands[2] = gen_reg_rtx (DDmode);
5112 ; extend(sf|df)(df|tf)2 instruction pattern(s).
5115 (define_insn "*extendsfdf2_z13"
5116 [(set (match_operand:DF 0 "register_operand" "=f,f,v")
5117 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
5118 "TARGET_VX && TARGET_HARD_FLOAT"
5123 [(set_attr "op_type" "RRE,RXE,VRR")
5124 (set_attr "type" "fsimpdf, floaddf,fsimpdf")])
5126 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
5127 (define_insn "*extend<DSF:mode><BFP:mode>2"
5128 [(set (match_operand:BFP 0 "register_operand" "=f,f")
5129 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
5131 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
5132 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
5134 l<BFP:xde><DSF:xde>br\t%0,%1
5135 l<BFP:xde><DSF:xde>b\t%0,%1"
5136 [(set_attr "op_type" "RRE,RXE")
5137 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
5139 (define_expand "extend<DSF:mode><BFP:mode>2"
5140 [(set (match_operand:BFP 0 "register_operand" "")
5141 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
5143 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
5146 ; extendddtd2 and extendsddd2 instruction pattern(s).
5149 (define_insn "extendddtd2"
5150 [(set (match_operand:TD 0 "register_operand" "=f")
5151 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
5154 [(set_attr "op_type" "RRF")
5155 (set_attr "type" "fsimptf")])
5157 (define_insn "extendsddd2"
5158 [(set (match_operand:DD 0 "register_operand" "=f")
5159 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
5162 [(set_attr "op_type" "RRF")
5163 (set_attr "type" "fsimptf")])
5165 (define_expand "extendsdtd2"
5167 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
5168 (set (match_operand:TD 0 "register_operand" "")
5169 (float_extend:TD (match_dup 2)))]
5172 operands[2] = gen_reg_rtx (DDmode);
5175 ; Binary Floating Point - load fp integer
5177 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
5178 ; For all of them the inexact exceptions are suppressed.
5180 ; fiebra, fidbra, fixbra
5181 (define_insn "<FPINT:fpint_name><BFP:mode>2"
5182 [(set (match_operand:BFP 0 "register_operand" "=f")
5183 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5186 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
5187 [(set_attr "op_type" "RRF")
5188 (set_attr "type" "fsimp<BFP:mode>")])
5190 ; rint is supposed to raise an inexact exception so we can use the
5191 ; older instructions.
5193 ; fiebr, fidbr, fixbr
5194 (define_insn "rint<BFP:mode>2"
5195 [(set (match_operand:BFP 0 "register_operand" "=f")
5196 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5197 UNSPEC_FPINT_RINT))]
5199 "fi<BFP:xde>br\t%0,0,%1"
5200 [(set_attr "op_type" "RRF")
5201 (set_attr "type" "fsimp<BFP:mode>")])
5204 ; Decimal Floating Point - load fp integer
5207 (define_insn "<FPINT:fpint_name><DFP:mode>2"
5208 [(set (match_operand:DFP 0 "register_operand" "=f")
5209 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5212 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
5213 [(set_attr "op_type" "RRF")
5214 (set_attr "type" "fsimp<DFP:mode>")])
5217 (define_insn "rint<DFP:mode>2"
5218 [(set (match_operand:DFP 0 "register_operand" "=f")
5219 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5220 UNSPEC_FPINT_RINT))]
5222 "fi<DFP:xde>tr\t%0,0,%1,0"
5223 [(set_attr "op_type" "RRF")
5224 (set_attr "type" "fsimp<DFP:mode>")])
5227 ; Binary <-> Decimal floating point trunc patterns
5230 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
5231 [(set (reg:DFP_ALL FPR0_REGNUM)
5232 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5233 (use (reg:SI GPR0_REGNUM))
5234 (clobber (reg:CC CC_REGNUM))
5235 (clobber (reg:SI GPR1_REGNUM))]
5239 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
5240 [(set (reg:BFP FPR0_REGNUM)
5241 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5242 (use (reg:SI GPR0_REGNUM))
5243 (clobber (reg:CC CC_REGNUM))
5244 (clobber (reg:SI GPR1_REGNUM))]
5248 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
5249 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5250 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5252 [(set (reg:DFP_ALL FPR0_REGNUM)
5253 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5254 (use (reg:SI GPR0_REGNUM))
5255 (clobber (reg:CC CC_REGNUM))
5256 (clobber (reg:SI GPR1_REGNUM))])
5257 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5258 (reg:DFP_ALL FPR0_REGNUM))]
5260 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5262 HOST_WIDE_INT flags;
5264 flags = (PFPO_CONVERT |
5265 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5266 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5268 operands[2] = GEN_INT (flags);
5271 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5272 [(set (reg:DFP_ALL FPR4_REGNUM)
5273 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5274 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5276 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5277 (use (reg:SI GPR0_REGNUM))
5278 (clobber (reg:CC CC_REGNUM))
5279 (clobber (reg:SI GPR1_REGNUM))])
5280 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5282 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5284 HOST_WIDE_INT flags;
5286 flags = (PFPO_CONVERT |
5287 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5288 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5290 operands[2] = GEN_INT (flags);
5294 ; Binary <-> Decimal floating point extend patterns
5297 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5298 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5299 (use (reg:SI GPR0_REGNUM))
5300 (clobber (reg:CC CC_REGNUM))
5301 (clobber (reg:SI GPR1_REGNUM))]
5305 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5306 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5307 (use (reg:SI GPR0_REGNUM))
5308 (clobber (reg:CC CC_REGNUM))
5309 (clobber (reg:SI GPR1_REGNUM))]
5313 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5314 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5315 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5317 [(set (reg:DFP_ALL FPR0_REGNUM)
5318 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5319 (use (reg:SI GPR0_REGNUM))
5320 (clobber (reg:CC CC_REGNUM))
5321 (clobber (reg:SI GPR1_REGNUM))])
5322 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5323 (reg:DFP_ALL FPR0_REGNUM))]
5325 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5327 HOST_WIDE_INT flags;
5329 flags = (PFPO_CONVERT |
5330 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5331 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5333 operands[2] = GEN_INT (flags);
5336 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5337 [(set (reg:DFP_ALL FPR4_REGNUM)
5338 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5339 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5341 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5342 (use (reg:SI GPR0_REGNUM))
5343 (clobber (reg:CC CC_REGNUM))
5344 (clobber (reg:SI GPR1_REGNUM))])
5345 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5347 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5349 HOST_WIDE_INT flags;
5351 flags = (PFPO_CONVERT |
5352 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5353 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5355 operands[2] = GEN_INT (flags);
5360 ;; ARITHMETIC OPERATIONS
5362 ; arithmetic operations set the ConditionCode,
5363 ; because of unpredictable Bits in Register for Halfword and Byte
5364 ; the ConditionCode can be set wrong in operations for Halfword and Byte
5367 ;;- Add instructions.
5371 ; addti3 instruction pattern(s).
5374 (define_expand "addti3"
5376 [(set (match_operand:TI 0 "register_operand" "")
5377 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5378 (match_operand:TI 2 "general_operand" "") ) )
5379 (clobber (reg:CC CC_REGNUM))])]
5382 /* For z13 we have vaq which doesn't set CC. */
5385 emit_insn (gen_rtx_SET (operands[0],
5386 gen_rtx_PLUS (TImode,
5387 copy_to_mode_reg (TImode, operands[1]),
5388 copy_to_mode_reg (TImode, operands[2]))));
5393 (define_insn_and_split "*addti3"
5394 [(set (match_operand:TI 0 "register_operand" "=&d")
5395 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5396 (match_operand:TI 2 "general_operand" "do") ) )
5397 (clobber (reg:CC CC_REGNUM))]
5400 "&& reload_completed"
5402 [(set (reg:CCL1 CC_REGNUM)
5403 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5405 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5407 [(set (match_dup 3) (plus:DI
5408 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5409 (match_dup 4)) (match_dup 5)))
5410 (clobber (reg:CC CC_REGNUM))])]
5411 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5412 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5413 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5414 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5415 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5416 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5417 [(set_attr "op_type" "*")
5418 (set_attr "cpu_facility" "*")])
5421 ; adddi3 instruction pattern(s).
5424 (define_expand "adddi3"
5426 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5427 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5428 (match_operand:DI 2 "general_operand" "")))
5429 (clobber (reg:CC CC_REGNUM))])]
5433 (define_insn "*adddi3_sign"
5434 [(set (match_operand:DI 0 "register_operand" "=d,d")
5435 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5436 (match_operand:DI 1 "register_operand" "0,0")))
5437 (clobber (reg:CC CC_REGNUM))]
5442 [(set_attr "op_type" "RRE,RXY")
5443 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5445 (define_insn "*adddi3_zero_cc"
5446 [(set (reg CC_REGNUM)
5447 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5448 (match_operand:DI 1 "register_operand" "0,0"))
5450 (set (match_operand:DI 0 "register_operand" "=d,d")
5451 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5452 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5456 [(set_attr "op_type" "RRE,RXY")
5457 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5459 (define_insn "*adddi3_zero_cconly"
5460 [(set (reg CC_REGNUM)
5461 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5462 (match_operand:DI 1 "register_operand" "0,0"))
5464 (clobber (match_scratch:DI 0 "=d,d"))]
5465 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5469 [(set_attr "op_type" "RRE,RXY")
5470 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5472 (define_insn "*adddi3_zero"
5473 [(set (match_operand:DI 0 "register_operand" "=d,d")
5474 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5475 (match_operand:DI 1 "register_operand" "0,0")))
5476 (clobber (reg:CC CC_REGNUM))]
5481 [(set_attr "op_type" "RRE,RXY")
5482 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5484 (define_insn_and_split "*adddi3_31z"
5485 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5486 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5487 (match_operand:DI 2 "general_operand" "do") ) )
5488 (clobber (reg:CC CC_REGNUM))]
5489 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5491 "&& reload_completed"
5493 [(set (reg:CCL1 CC_REGNUM)
5494 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5496 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5498 [(set (match_dup 3) (plus:SI
5499 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5500 (match_dup 4)) (match_dup 5)))
5501 (clobber (reg:CC CC_REGNUM))])]
5502 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5503 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5504 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5505 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5506 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5507 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5509 (define_insn_and_split "*adddi3_31"
5510 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5511 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5512 (match_operand:DI 2 "general_operand" "do") ) )
5513 (clobber (reg:CC CC_REGNUM))]
5516 "&& reload_completed"
5518 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5519 (clobber (reg:CC CC_REGNUM))])
5521 [(set (reg:CCL1 CC_REGNUM)
5522 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5524 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5526 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5528 (label_ref (match_dup 9))))
5530 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5531 (clobber (reg:CC CC_REGNUM))])
5533 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5534 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5535 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5536 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5537 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5538 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5539 operands[9] = gen_label_rtx ();")
5542 ; addsi3 instruction pattern(s).
5545 (define_expand "addsi3"
5547 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5548 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5549 (match_operand:SI 2 "general_operand" "")))
5550 (clobber (reg:CC CC_REGNUM))])]
5554 (define_insn "*addsi3_sign"
5555 [(set (match_operand:SI 0 "register_operand" "=d,d")
5556 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5557 (match_operand:SI 1 "register_operand" "0,0")))
5558 (clobber (reg:CC CC_REGNUM))]
5563 [(set_attr "op_type" "RX,RXY")
5564 (set_attr "cpu_facility" "*,longdisp")
5565 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5568 ; add(di|si)3 instruction pattern(s).
5571 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5572 (define_insn "*add<mode>3"
5573 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S")
5574 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
5575 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) )
5576 (clobber (reg:CC CC_REGNUM))]
5588 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5589 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
5590 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5591 z10_super_E1,z10_super_E1,z10_super_E1")])
5593 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5594 (define_insn "*add<mode>3_carry1_cc"
5595 [(set (reg CC_REGNUM)
5596 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5597 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5599 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
5600 (plus:GPR (match_dup 1) (match_dup 2)))]
5601 "s390_match_ccmode (insn, CCL1mode)"
5607 al<g>hsik\t%0,%1,%h2
5611 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5612 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5613 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5614 z10_super_E1,z10_super_E1,z10_super_E1")])
5616 ; alr, al, aly, algr, alg, alrk, algrk
5617 (define_insn "*add<mode>3_carry1_cconly"
5618 [(set (reg CC_REGNUM)
5619 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5620 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5622 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5623 "s390_match_ccmode (insn, CCL1mode)"
5629 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5630 (set_attr "cpu_facility" "*,z196,*,longdisp")
5631 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5633 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5634 (define_insn "*add<mode>3_carry2_cc"
5635 [(set (reg CC_REGNUM)
5636 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5637 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5639 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5640 (plus:GPR (match_dup 1) (match_dup 2)))]
5641 "s390_match_ccmode (insn, CCL1mode)"
5647 al<g>hsik\t%0,%1,%h2
5651 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5652 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5653 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5654 z10_super_E1,z10_super_E1,z10_super_E1")])
5656 ; alr, al, aly, algr, alg, alrk, algrk
5657 (define_insn "*add<mode>3_carry2_cconly"
5658 [(set (reg CC_REGNUM)
5659 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5660 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5662 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5663 "s390_match_ccmode (insn, CCL1mode)"
5669 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5670 (set_attr "cpu_facility" "*,z196,*,longdisp")
5671 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5673 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5674 (define_insn "*add<mode>3_cc"
5675 [(set (reg CC_REGNUM)
5676 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5677 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5679 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5680 (plus:GPR (match_dup 1) (match_dup 2)))]
5681 "s390_match_ccmode (insn, CCLmode)"
5687 al<g>hsik\t%0,%1,%h2
5691 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5692 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5693 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5694 *,z10_super_E1,z10_super_E1,z10_super_E1")])
5696 ; alr, al, aly, algr, alg, alrk, algrk
5697 (define_insn "*add<mode>3_cconly"
5698 [(set (reg CC_REGNUM)
5699 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5700 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5702 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5703 "s390_match_ccmode (insn, CCLmode)"
5709 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5710 (set_attr "cpu_facility" "*,z196,*,longdisp")
5711 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5713 ; alr, al, aly, algr, alg, alrk, algrk
5714 (define_insn "*add<mode>3_cconly2"
5715 [(set (reg CC_REGNUM)
5716 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5717 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5718 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5719 "s390_match_ccmode(insn, CCLmode)"
5725 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5726 (set_attr "cpu_facility" "*,z196,*,longdisp")
5727 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5729 ; ahi, afi, aghi, agfi, asi, agsi
5730 (define_insn "*add<mode>3_imm_cc"
5731 [(set (reg CC_REGNUM)
5732 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5733 (match_operand:GPR 2 "const_int_operand" " K, K,Os,C"))
5735 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S")
5736 (plus:GPR (match_dup 1) (match_dup 2)))]
5737 "s390_match_ccmode (insn, CCAmode)
5738 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5739 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5740 /* Avoid INT32_MIN on 32 bit. */
5741 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5747 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5748 (set_attr "cpu_facility" "*,z196,extimm,z10")
5749 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5752 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5755 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5756 ; FIXME: wfadb does not clobber cc
5757 (define_insn "add<mode>3"
5758 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
5759 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
5760 (match_operand:FP 2 "general_operand" "f,f,R,v")))
5761 (clobber (reg:CC CC_REGNUM))]
5768 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
5769 (set_attr "type" "fsimp<mode>")
5770 (set_attr "cpu_facility" "*,*,*,vx")
5771 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5773 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5774 (define_insn "*add<mode>3_cc"
5775 [(set (reg CC_REGNUM)
5776 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5777 (match_operand:FP 2 "general_operand" "f,f,R"))
5778 (match_operand:FP 3 "const0_operand" "")))
5779 (set (match_operand:FP 0 "register_operand" "=f,f,f")
5780 (plus:FP (match_dup 1) (match_dup 2)))]
5781 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5786 [(set_attr "op_type" "RRF,RRE,RXE")
5787 (set_attr "type" "fsimp<mode>")
5788 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5790 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5791 (define_insn "*add<mode>3_cconly"
5792 [(set (reg CC_REGNUM)
5793 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5794 (match_operand:FP 2 "general_operand" "f,f,R"))
5795 (match_operand:FP 3 "const0_operand" "")))
5796 (clobber (match_scratch:FP 0 "=f,f,f"))]
5797 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5802 [(set_attr "op_type" "RRF,RRE,RXE")
5803 (set_attr "type" "fsimp<mode>")
5804 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5807 ; Pointer add instruction patterns
5810 ; This will match "*la_64"
5811 (define_expand "addptrdi3"
5812 [(set (match_operand:DI 0 "register_operand" "")
5813 (plus:DI (match_operand:DI 1 "register_operand" "")
5814 (match_operand:DI 2 "nonmemory_operand" "")))]
5817 if (GET_CODE (operands[2]) == CONST_INT)
5819 HOST_WIDE_INT c = INTVAL (operands[2]);
5821 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5822 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5824 operands[2] = force_const_mem (DImode, operands[2]);
5825 operands[2] = force_reg (DImode, operands[2]);
5827 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5828 operands[2] = force_reg (DImode, operands[2]);
5832 ; For 31 bit we have to prevent the generated pattern from matching
5833 ; normal ADDs since la only does a 31 bit add. This is supposed to
5834 ; match "force_la_31".
5835 (define_expand "addptrsi3"
5837 [(set (match_operand:SI 0 "register_operand" "")
5838 (plus:SI (match_operand:SI 1 "register_operand" "")
5839 (match_operand:SI 2 "nonmemory_operand" "")))
5840 (use (const_int 0))])]
5843 if (GET_CODE (operands[2]) == CONST_INT)
5845 HOST_WIDE_INT c = INTVAL (operands[2]);
5847 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5848 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5850 operands[2] = force_const_mem (SImode, operands[2]);
5851 operands[2] = force_reg (SImode, operands[2]);
5853 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5854 operands[2] = force_reg (SImode, operands[2]);
5859 ;;- Subtract instructions.
5863 ; subti3 instruction pattern(s).
5866 (define_expand "subti3"
5868 [(set (match_operand:TI 0 "register_operand" "")
5869 (minus:TI (match_operand:TI 1 "register_operand" "")
5870 (match_operand:TI 2 "general_operand" "") ) )
5871 (clobber (reg:CC CC_REGNUM))])]
5874 /* For z13 we have vsq which doesn't set CC. */
5877 emit_insn (gen_rtx_SET (operands[0],
5878 gen_rtx_MINUS (TImode,
5880 copy_to_mode_reg (TImode, operands[2]))));
5885 (define_insn_and_split "*subti3"
5886 [(set (match_operand:TI 0 "register_operand" "=&d")
5887 (minus:TI (match_operand:TI 1 "register_operand" "0")
5888 (match_operand:TI 2 "general_operand" "do") ) )
5889 (clobber (reg:CC CC_REGNUM))]
5892 "&& reload_completed"
5894 [(set (reg:CCL2 CC_REGNUM)
5895 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5897 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5899 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5900 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5901 (clobber (reg:CC CC_REGNUM))])]
5902 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5903 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5904 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5905 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5906 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5907 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5908 [(set_attr "op_type" "*")
5909 (set_attr "cpu_facility" "*")])
5912 ; subdi3 instruction pattern(s).
5915 (define_expand "subdi3"
5917 [(set (match_operand:DI 0 "register_operand" "")
5918 (minus:DI (match_operand:DI 1 "register_operand" "")
5919 (match_operand:DI 2 "general_operand" "")))
5920 (clobber (reg:CC CC_REGNUM))])]
5924 (define_insn "*subdi3_sign"
5925 [(set (match_operand:DI 0 "register_operand" "=d,d")
5926 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5927 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5928 (clobber (reg:CC CC_REGNUM))]
5933 [(set_attr "op_type" "RRE,RXY")
5934 (set_attr "z10prop" "z10_c,*")
5935 (set_attr "z196prop" "z196_cracked")])
5937 (define_insn "*subdi3_zero_cc"
5938 [(set (reg CC_REGNUM)
5939 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5940 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5942 (set (match_operand:DI 0 "register_operand" "=d,d")
5943 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5944 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5948 [(set_attr "op_type" "RRE,RXY")
5949 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5951 (define_insn "*subdi3_zero_cconly"
5952 [(set (reg CC_REGNUM)
5953 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5954 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5956 (clobber (match_scratch:DI 0 "=d,d"))]
5957 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5961 [(set_attr "op_type" "RRE,RXY")
5962 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5964 (define_insn "*subdi3_zero"
5965 [(set (match_operand:DI 0 "register_operand" "=d,d")
5966 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5967 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5968 (clobber (reg:CC CC_REGNUM))]
5973 [(set_attr "op_type" "RRE,RXY")
5974 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5976 (define_insn_and_split "*subdi3_31z"
5977 [(set (match_operand:DI 0 "register_operand" "=&d")
5978 (minus:DI (match_operand:DI 1 "register_operand" "0")
5979 (match_operand:DI 2 "general_operand" "do") ) )
5980 (clobber (reg:CC CC_REGNUM))]
5981 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5983 "&& reload_completed"
5985 [(set (reg:CCL2 CC_REGNUM)
5986 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5988 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5990 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5991 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5992 (clobber (reg:CC CC_REGNUM))])]
5993 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5994 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5995 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5996 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5997 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5998 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
6000 (define_insn_and_split "*subdi3_31"
6001 [(set (match_operand:DI 0 "register_operand" "=&d")
6002 (minus:DI (match_operand:DI 1 "register_operand" "0")
6003 (match_operand:DI 2 "general_operand" "do") ) )
6004 (clobber (reg:CC CC_REGNUM))]
6007 "&& reload_completed"
6009 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
6010 (clobber (reg:CC CC_REGNUM))])
6012 [(set (reg:CCL2 CC_REGNUM)
6013 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
6015 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
6017 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
6019 (label_ref (match_dup 9))))
6021 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
6022 (clobber (reg:CC CC_REGNUM))])
6024 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
6025 operands[4] = operand_subword (operands[1], 0, 0, DImode);
6026 operands[5] = operand_subword (operands[2], 0, 0, DImode);
6027 operands[6] = operand_subword (operands[0], 1, 0, DImode);
6028 operands[7] = operand_subword (operands[1], 1, 0, DImode);
6029 operands[8] = operand_subword (operands[2], 1, 0, DImode);
6030 operands[9] = gen_label_rtx ();")
6033 ; subsi3 instruction pattern(s).
6036 (define_expand "subsi3"
6038 [(set (match_operand:SI 0 "register_operand" "")
6039 (minus:SI (match_operand:SI 1 "register_operand" "")
6040 (match_operand:SI 2 "general_operand" "")))
6041 (clobber (reg:CC CC_REGNUM))])]
6045 (define_insn "*subsi3_sign"
6046 [(set (match_operand:SI 0 "register_operand" "=d,d")
6047 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6048 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
6049 (clobber (reg:CC CC_REGNUM))]
6054 [(set_attr "op_type" "RX,RXY")
6055 (set_attr "cpu_facility" "*,longdisp")
6056 (set_attr "z196prop" "z196_cracked,z196_cracked")])
6059 ; sub(di|si)3 instruction pattern(s).
6062 ; sr, s, sy, sgr, sg, srk, sgrk
6063 (define_insn "*sub<mode>3"
6064 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6065 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6066 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
6067 (clobber (reg:CC CC_REGNUM))]
6074 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6075 (set_attr "cpu_facility" "*,z196,*,longdisp")
6076 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6078 ; slr, sl, sly, slgr, slg, slrk, slgrk
6079 (define_insn "*sub<mode>3_borrow_cc"
6080 [(set (reg CC_REGNUM)
6081 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6082 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6084 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6085 (minus:GPR (match_dup 1) (match_dup 2)))]
6086 "s390_match_ccmode (insn, CCL2mode)"
6092 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6093 (set_attr "cpu_facility" "*,z196,*,longdisp")
6094 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6096 ; slr, sl, sly, slgr, slg, slrk, slgrk
6097 (define_insn "*sub<mode>3_borrow_cconly"
6098 [(set (reg CC_REGNUM)
6099 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6100 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6102 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6103 "s390_match_ccmode (insn, CCL2mode)"
6109 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6110 (set_attr "cpu_facility" "*,z196,*,longdisp")
6111 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6113 ; slr, sl, sly, slgr, slg, slrk, slgrk
6114 (define_insn "*sub<mode>3_cc"
6115 [(set (reg CC_REGNUM)
6116 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6117 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6119 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6120 (minus:GPR (match_dup 1) (match_dup 2)))]
6121 "s390_match_ccmode (insn, CCLmode)"
6127 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6128 (set_attr "cpu_facility" "*,z196,*,longdisp")
6129 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6131 ; slr, sl, sly, slgr, slg, slrk, slgrk
6132 (define_insn "*sub<mode>3_cc2"
6133 [(set (reg CC_REGNUM)
6134 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6135 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6136 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6137 (minus:GPR (match_dup 1) (match_dup 2)))]
6138 "s390_match_ccmode (insn, CCL3mode)"
6144 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6145 (set_attr "cpu_facility" "*,z196,*,longdisp")
6146 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6148 ; slr, sl, sly, slgr, slg, slrk, slgrk
6149 (define_insn "*sub<mode>3_cconly"
6150 [(set (reg CC_REGNUM)
6151 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6152 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6154 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6155 "s390_match_ccmode (insn, CCLmode)"
6161 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6162 (set_attr "cpu_facility" "*,z196,*,longdisp")
6163 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6166 ; slr, sl, sly, slgr, slg, slrk, slgrk
6167 (define_insn "*sub<mode>3_cconly2"
6168 [(set (reg CC_REGNUM)
6169 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6170 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6171 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6172 "s390_match_ccmode (insn, CCL3mode)"
6178 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6179 (set_attr "cpu_facility" "*,z196,*,longdisp")
6180 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6184 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
6187 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6188 (define_insn "sub<mode>3"
6189 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6190 (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
6191 (match_operand:FP 2 "general_operand" "f,f,R,v")))
6192 (clobber (reg:CC CC_REGNUM))]
6199 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6200 (set_attr "type" "fsimp<mode>")
6201 (set_attr "cpu_facility" "*,*,*,vx")
6202 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6204 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6205 (define_insn "*sub<mode>3_cc"
6206 [(set (reg CC_REGNUM)
6207 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6208 (match_operand:FP 2 "general_operand" "f,f,R"))
6209 (match_operand:FP 3 "const0_operand" "")))
6210 (set (match_operand:FP 0 "register_operand" "=f,f,f")
6211 (minus:FP (match_dup 1) (match_dup 2)))]
6212 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6217 [(set_attr "op_type" "RRF,RRE,RXE")
6218 (set_attr "type" "fsimp<mode>")
6219 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6221 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6222 (define_insn "*sub<mode>3_cconly"
6223 [(set (reg CC_REGNUM)
6224 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6225 (match_operand:FP 2 "general_operand" "f,f,R"))
6226 (match_operand:FP 3 "const0_operand" "")))
6227 (clobber (match_scratch:FP 0 "=f,f,f"))]
6228 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6233 [(set_attr "op_type" "RRF,RRE,RXE")
6234 (set_attr "type" "fsimp<mode>")
6235 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6239 ;;- Conditional add/subtract instructions.
6243 ; add(di|si)cc instruction pattern(s).
6246 ; the following 4 patterns are used when the result of an add with
6247 ; carry is checked for an overflow condition
6249 ; op1 + op2 + c < op1
6251 ; alcr, alc, alcgr, alcg
6252 (define_insn "*add<mode>3_alc_carry1_cc"
6253 [(set (reg CC_REGNUM)
6255 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6256 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6257 (match_operand:GPR 2 "general_operand" "d,T"))
6259 (set (match_operand:GPR 0 "register_operand" "=d,d")
6260 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6261 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6265 [(set_attr "op_type" "RRE,RXY")
6266 (set_attr "z196prop" "z196_alone,z196_alone")])
6268 ; alcr, alc, alcgr, alcg
6269 (define_insn "*add<mode>3_alc_carry1_cconly"
6270 [(set (reg CC_REGNUM)
6272 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6273 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6274 (match_operand:GPR 2 "general_operand" "d,T"))
6276 (clobber (match_scratch:GPR 0 "=d,d"))]
6277 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6281 [(set_attr "op_type" "RRE,RXY")
6282 (set_attr "z196prop" "z196_alone,z196_alone")])
6284 ; op1 + op2 + c < op2
6286 ; alcr, alc, alcgr, alcg
6287 (define_insn "*add<mode>3_alc_carry2_cc"
6288 [(set (reg CC_REGNUM)
6290 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6291 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6292 (match_operand:GPR 2 "general_operand" "d,T"))
6294 (set (match_operand:GPR 0 "register_operand" "=d,d")
6295 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6296 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6300 [(set_attr "op_type" "RRE,RXY")])
6302 ; alcr, alc, alcgr, alcg
6303 (define_insn "*add<mode>3_alc_carry2_cconly"
6304 [(set (reg CC_REGNUM)
6306 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6307 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6308 (match_operand:GPR 2 "general_operand" "d,T"))
6310 (clobber (match_scratch:GPR 0 "=d,d"))]
6311 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6315 [(set_attr "op_type" "RRE,RXY")])
6317 ; alcr, alc, alcgr, alcg
6318 (define_insn "*add<mode>3_alc_cc"
6319 [(set (reg CC_REGNUM)
6321 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6322 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6323 (match_operand:GPR 2 "general_operand" "d,T"))
6325 (set (match_operand:GPR 0 "register_operand" "=d,d")
6326 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6327 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6331 [(set_attr "op_type" "RRE,RXY")])
6333 ; alcr, alc, alcgr, alcg
6334 (define_insn "*add<mode>3_alc"
6335 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6336 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6337 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6338 (match_operand:GPR 2 "general_operand" "d,T")))
6339 (clobber (reg:CC CC_REGNUM))]
6344 [(set_attr "op_type" "RRE,RXY")])
6346 ; slbr, slb, slbgr, slbg
6347 (define_insn "*sub<mode>3_slb_cc"
6348 [(set (reg CC_REGNUM)
6350 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6351 (match_operand:GPR 2 "general_operand" "d,T"))
6352 (match_operand:GPR 3 "s390_slb_comparison" ""))
6354 (set (match_operand:GPR 0 "register_operand" "=d,d")
6355 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6356 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6360 [(set_attr "op_type" "RRE,RXY")
6361 (set_attr "z10prop" "z10_c,*")])
6363 ; slbr, slb, slbgr, slbg
6364 (define_insn "*sub<mode>3_slb"
6365 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6366 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6367 (match_operand:GPR 2 "general_operand" "d,T"))
6368 (match_operand:GPR 3 "s390_slb_comparison" "")))
6369 (clobber (reg:CC CC_REGNUM))]
6374 [(set_attr "op_type" "RRE,RXY")
6375 (set_attr "z10prop" "z10_c,*")])
6377 (define_expand "add<mode>cc"
6378 [(match_operand:GPR 0 "register_operand" "")
6379 (match_operand 1 "comparison_operator" "")
6380 (match_operand:GPR 2 "register_operand" "")
6381 (match_operand:GPR 3 "const_int_operand" "")]
6383 "if (!s390_expand_addcc (GET_CODE (operands[1]),
6384 XEXP (operands[1], 0), XEXP (operands[1], 1),
6385 operands[0], operands[2],
6386 operands[3])) FAIL; DONE;")
6389 ; scond instruction pattern(s).
6392 (define_insn_and_split "*scond<mode>"
6393 [(set (match_operand:GPR 0 "register_operand" "=&d")
6394 (match_operand:GPR 1 "s390_alc_comparison" ""))
6395 (clobber (reg:CC CC_REGNUM))]
6398 "&& reload_completed"
6399 [(set (match_dup 0) (const_int 0))
6401 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6403 (clobber (reg:CC CC_REGNUM))])]
6406 (define_insn_and_split "*scond<mode>_neg"
6407 [(set (match_operand:GPR 0 "register_operand" "=&d")
6408 (match_operand:GPR 1 "s390_slb_comparison" ""))
6409 (clobber (reg:CC CC_REGNUM))]
6412 "&& reload_completed"
6413 [(set (match_dup 0) (const_int 0))
6415 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6417 (clobber (reg:CC CC_REGNUM))])
6419 [(set (match_dup 0) (neg:GPR (match_dup 0)))
6420 (clobber (reg:CC CC_REGNUM))])]
6424 (define_expand "cstore<mode>4"
6425 [(set (match_operand:SI 0 "register_operand" "")
6426 (match_operator:SI 1 "s390_scond_operator"
6427 [(match_operand:GPR 2 "register_operand" "")
6428 (match_operand:GPR 3 "general_operand" "")]))]
6430 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6431 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6433 (define_expand "cstorecc4"
6435 [(set (match_operand:SI 0 "register_operand" "")
6436 (match_operator:SI 1 "s390_eqne_operator"
6437 [(match_operand:CCZ1 2 "register_operand")
6438 (match_operand 3 "const0_operand")]))
6439 (clobber (reg:CC CC_REGNUM))])]
6441 "emit_insn (gen_sne (operands[0], operands[2]));
6442 if (GET_CODE (operands[1]) == EQ)
6443 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6446 (define_insn_and_split "sne"
6447 [(set (match_operand:SI 0 "register_operand" "=d")
6448 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6450 (clobber (reg:CC CC_REGNUM))]
6455 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6456 (clobber (reg:CC CC_REGNUM))])])
6460 ;; - Conditional move instructions (introduced with z196)
6463 (define_expand "mov<mode>cc"
6464 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6465 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6466 (match_operand:GPR 2 "nonimmediate_operand" "")
6467 (match_operand:GPR 3 "nonimmediate_operand" "")))]
6470 /* Emit the comparison insn in case we do not already have a comparison result. */
6471 if (!s390_comparison (operands[1], VOIDmode))
6472 operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6473 XEXP (operands[1], 0),
6474 XEXP (operands[1], 1));
6477 ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
6478 (define_insn_and_split "*mov<mode>cc"
6479 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S,&d")
6481 (match_operator 1 "s390_comparison"
6482 [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c")
6483 (match_operand 5 "const_int_operand" "")])
6484 (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S")
6485 (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))]
6497 "&& reload_completed
6498 && MEM_P (operands[3]) && MEM_P (operands[4])"
6501 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6506 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6510 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*")
6511 (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")])
6514 ;;- Multiply instructions.
6518 ; muldi3 instruction pattern(s).
6521 (define_insn "*muldi3_sign"
6522 [(set (match_operand:DI 0 "register_operand" "=d,d")
6523 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
6524 (match_operand:DI 1 "register_operand" "0,0")))]
6529 [(set_attr "op_type" "RRE,RXY")
6530 (set_attr "type" "imuldi")])
6532 (define_insn "muldi3"
6533 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6534 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6535 (match_operand:DI 2 "general_operand" "d,K,T,Os")))]
6542 [(set_attr "op_type" "RRE,RI,RXY,RIL")
6543 (set_attr "type" "imuldi")
6544 (set_attr "cpu_facility" "*,*,*,z10")])
6547 ; mulsi3 instruction pattern(s).
6550 (define_insn "*mulsi3_sign"
6551 [(set (match_operand:SI 0 "register_operand" "=d,d")
6552 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6553 (match_operand:SI 1 "register_operand" "0,0")))]
6558 [(set_attr "op_type" "RX,RXY")
6559 (set_attr "type" "imulhi")
6560 (set_attr "cpu_facility" "*,z10")])
6562 (define_insn "mulsi3"
6563 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6564 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6565 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6573 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
6574 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
6575 (set_attr "cpu_facility" "*,*,*,longdisp,z10")])
6578 ; mulsidi3 instruction pattern(s).
6581 (define_insn "mulsidi3"
6582 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6583 (mult:DI (sign_extend:DI
6584 (match_operand:SI 1 "register_operand" "%0,0,0"))
6586 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6592 [(set_attr "op_type" "RR,RX,RXY")
6593 (set_attr "type" "imulsi")
6594 (set_attr "cpu_facility" "*,*,z10")])
6597 ; umul instruction pattern(s).
6600 ; mlr, ml, mlgr, mlg
6601 (define_insn "umul<dwh><mode>3"
6602 [(set (match_operand:DW 0 "register_operand" "=d,d")
6603 (mult:DW (zero_extend:DW
6604 (match_operand:<DWH> 1 "register_operand" "%0,0"))
6606 (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
6611 [(set_attr "op_type" "RRE,RXY")
6612 (set_attr "type" "imul<dwh>")])
6615 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6618 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6619 (define_insn "mul<mode>3"
6620 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6621 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
6622 (match_operand:FP 2 "general_operand" "f,f,R,v")))]
6629 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6630 (set_attr "type" "fmul<mode>")
6631 (set_attr "cpu_facility" "*,*,*,vx")
6632 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6634 ; madbr, maebr, maxb, madb, maeb
6635 (define_insn "fma<mode>4"
6636 [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
6637 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6638 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
6639 (match_operand:DSF 3 "register_operand" "0,0,v")))]
6644 wfmadb\t%v0,%v1,%v2,%v3"
6645 [(set_attr "op_type" "RRE,RXE,VRR")
6646 (set_attr "type" "fmadd<mode>")
6647 (set_attr "cpu_facility" "*,*,vx")
6648 (set_attr "enabled" "*,*,<DFDI>")])
6650 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6651 (define_insn "fms<mode>4"
6652 [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
6653 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6654 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
6655 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))]
6660 wfmsdb\t%v0,%v1,%v2,%v3"
6661 [(set_attr "op_type" "RRE,RXE,VRR")
6662 (set_attr "type" "fmadd<mode>")
6663 (set_attr "cpu_facility" "*,*,vx")
6664 (set_attr "enabled" "*,*,<DFDI>")])
6667 ;;- Divide and modulo instructions.
6671 ; divmoddi4 instruction pattern(s).
6674 (define_expand "divmoddi4"
6675 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6676 (div:DI (match_operand:DI 1 "register_operand" "")
6677 (match_operand:DI 2 "general_operand" "")))
6678 (set (match_operand:DI 3 "general_operand" "")
6679 (mod:DI (match_dup 1) (match_dup 2)))])
6680 (clobber (match_dup 4))]
6683 rtx div_equal, mod_equal;
6686 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6687 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6689 operands[4] = gen_reg_rtx(TImode);
6690 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6692 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6693 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6695 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6696 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6701 (define_insn "divmodtidi3"
6702 [(set (match_operand:TI 0 "register_operand" "=d,d")
6706 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6707 (match_operand:DI 2 "general_operand" "d,T")))
6709 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6714 [(set_attr "op_type" "RRE,RXY")
6715 (set_attr "type" "idiv")])
6717 (define_insn "divmodtisi3"
6718 [(set (match_operand:TI 0 "register_operand" "=d,d")
6722 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6724 (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
6727 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6732 [(set_attr "op_type" "RRE,RXY")
6733 (set_attr "type" "idiv")])
6736 ; udivmoddi4 instruction pattern(s).
6739 (define_expand "udivmoddi4"
6740 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6741 (udiv:DI (match_operand:DI 1 "general_operand" "")
6742 (match_operand:DI 2 "nonimmediate_operand" "")))
6743 (set (match_operand:DI 3 "general_operand" "")
6744 (umod:DI (match_dup 1) (match_dup 2)))])
6745 (clobber (match_dup 4))]
6748 rtx div_equal, mod_equal, equal;
6751 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6752 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6753 equal = gen_rtx_IOR (TImode,
6754 gen_rtx_ASHIFT (TImode,
6755 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6757 gen_rtx_ZERO_EXTEND (TImode, div_equal));
6759 operands[4] = gen_reg_rtx(TImode);
6760 emit_clobber (operands[4]);
6761 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6762 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6764 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6765 set_unique_reg_note (insn, REG_EQUAL, equal);
6767 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6768 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6770 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6771 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6776 (define_insn "udivmodtidi3"
6777 [(set (match_operand:TI 0 "register_operand" "=d,d")
6782 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6784 (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
6788 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6793 [(set_attr "op_type" "RRE,RXY")
6794 (set_attr "type" "idiv")])
6797 ; divmodsi4 instruction pattern(s).
6800 (define_expand "divmodsi4"
6801 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6802 (div:SI (match_operand:SI 1 "general_operand" "")
6803 (match_operand:SI 2 "nonimmediate_operand" "")))
6804 (set (match_operand:SI 3 "general_operand" "")
6805 (mod:SI (match_dup 1) (match_dup 2)))])
6806 (clobber (match_dup 4))]
6809 rtx div_equal, mod_equal, equal;
6812 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6813 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6814 equal = gen_rtx_IOR (DImode,
6815 gen_rtx_ASHIFT (DImode,
6816 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6818 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6820 operands[4] = gen_reg_rtx(DImode);
6821 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6823 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6824 set_unique_reg_note (insn, REG_EQUAL, equal);
6826 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6827 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6829 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6830 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6835 (define_insn "divmoddisi3"
6836 [(set (match_operand:DI 0 "register_operand" "=d,d")
6841 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6843 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6847 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6852 [(set_attr "op_type" "RR,RX")
6853 (set_attr "type" "idiv")])
6856 ; udivsi3 and umodsi3 instruction pattern(s).
6859 (define_expand "udivmodsi4"
6860 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6861 (udiv:SI (match_operand:SI 1 "general_operand" "")
6862 (match_operand:SI 2 "nonimmediate_operand" "")))
6863 (set (match_operand:SI 3 "general_operand" "")
6864 (umod:SI (match_dup 1) (match_dup 2)))])
6865 (clobber (match_dup 4))]
6866 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6868 rtx div_equal, mod_equal, equal;
6871 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6872 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6873 equal = gen_rtx_IOR (DImode,
6874 gen_rtx_ASHIFT (DImode,
6875 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6877 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6879 operands[4] = gen_reg_rtx(DImode);
6880 emit_clobber (operands[4]);
6881 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6882 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6884 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6885 set_unique_reg_note (insn, REG_EQUAL, equal);
6887 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6888 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6890 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6891 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6896 (define_insn "udivmoddisi3"
6897 [(set (match_operand:DI 0 "register_operand" "=d,d")
6902 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6904 (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
6908 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6909 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6913 [(set_attr "op_type" "RRE,RXY")
6914 (set_attr "type" "idiv")])
6916 (define_expand "udivsi3"
6917 [(set (match_operand:SI 0 "register_operand" "=d")
6918 (udiv:SI (match_operand:SI 1 "general_operand" "")
6919 (match_operand:SI 2 "general_operand" "")))
6920 (clobber (match_dup 3))]
6921 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6923 rtx udiv_equal, umod_equal, equal;
6926 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6927 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6928 equal = gen_rtx_IOR (DImode,
6929 gen_rtx_ASHIFT (DImode,
6930 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6932 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6934 operands[3] = gen_reg_rtx (DImode);
6936 if (CONSTANT_P (operands[2]))
6938 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6940 rtx_code_label *label1 = gen_label_rtx ();
6942 operands[1] = make_safe_from (operands[1], operands[0]);
6943 emit_move_insn (operands[0], const0_rtx);
6944 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6946 emit_move_insn (operands[0], const1_rtx);
6947 emit_label (label1);
6951 operands[2] = force_reg (SImode, operands[2]);
6952 operands[2] = make_safe_from (operands[2], operands[0]);
6954 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6955 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6957 set_unique_reg_note (insn, REG_EQUAL, equal);
6959 insn = emit_move_insn (operands[0],
6960 gen_lowpart (SImode, operands[3]));
6961 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6966 rtx_code_label *label1 = gen_label_rtx ();
6967 rtx_code_label *label2 = gen_label_rtx ();
6968 rtx_code_label *label3 = gen_label_rtx ();
6970 operands[1] = force_reg (SImode, operands[1]);
6971 operands[1] = make_safe_from (operands[1], operands[0]);
6972 operands[2] = force_reg (SImode, operands[2]);
6973 operands[2] = make_safe_from (operands[2], operands[0]);
6975 emit_move_insn (operands[0], const0_rtx);
6976 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6978 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6980 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6982 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6983 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6985 set_unique_reg_note (insn, REG_EQUAL, equal);
6987 insn = emit_move_insn (operands[0],
6988 gen_lowpart (SImode, operands[3]));
6989 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6992 emit_label (label1);
6993 emit_move_insn (operands[0], operands[1]);
6995 emit_label (label2);
6996 emit_move_insn (operands[0], const1_rtx);
6997 emit_label (label3);
6999 emit_move_insn (operands[0], operands[0]);
7003 (define_expand "umodsi3"
7004 [(set (match_operand:SI 0 "register_operand" "=d")
7005 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
7006 (match_operand:SI 2 "nonimmediate_operand" "")))
7007 (clobber (match_dup 3))]
7008 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
7010 rtx udiv_equal, umod_equal, equal;
7013 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
7014 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
7015 equal = gen_rtx_IOR (DImode,
7016 gen_rtx_ASHIFT (DImode,
7017 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
7019 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
7021 operands[3] = gen_reg_rtx (DImode);
7023 if (CONSTANT_P (operands[2]))
7025 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
7027 rtx_code_label *label1 = gen_label_rtx ();
7029 operands[1] = make_safe_from (operands[1], operands[0]);
7030 emit_move_insn (operands[0], operands[1]);
7031 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
7033 emit_insn (gen_abssi2 (operands[0], operands[2]));
7034 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
7035 emit_label (label1);
7039 operands[2] = force_reg (SImode, operands[2]);
7040 operands[2] = make_safe_from (operands[2], operands[0]);
7042 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7043 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7045 set_unique_reg_note (insn, REG_EQUAL, equal);
7047 insn = emit_move_insn (operands[0],
7048 gen_highpart (SImode, operands[3]));
7049 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
7054 rtx_code_label *label1 = gen_label_rtx ();
7055 rtx_code_label *label2 = gen_label_rtx ();
7056 rtx_code_label *label3 = gen_label_rtx ();
7058 operands[1] = force_reg (SImode, operands[1]);
7059 operands[1] = make_safe_from (operands[1], operands[0]);
7060 operands[2] = force_reg (SImode, operands[2]);
7061 operands[2] = make_safe_from (operands[2], operands[0]);
7063 emit_move_insn(operands[0], operands[1]);
7064 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
7066 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
7068 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
7070 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7071 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7073 set_unique_reg_note (insn, REG_EQUAL, equal);
7075 insn = emit_move_insn (operands[0],
7076 gen_highpart (SImode, operands[3]));
7077 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
7080 emit_label (label1);
7081 emit_move_insn (operands[0], const0_rtx);
7083 emit_label (label2);
7084 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
7085 emit_label (label3);
7091 ; div(df|sf)3 instruction pattern(s).
7094 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
7095 (define_insn "div<mode>3"
7096 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
7097 (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
7098 (match_operand:FP 2 "general_operand" "f,f,R,v")))]
7105 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
7106 (set_attr "type" "fdiv<mode>")
7107 (set_attr "cpu_facility" "*,*,*,vx")
7108 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
7112 ;;- And instructions.
7115 (define_expand "and<mode>3"
7116 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7117 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
7118 (match_operand:INT 2 "general_operand" "")))
7119 (clobber (reg:CC CC_REGNUM))]
7121 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
7124 ; anddi3 instruction pattern(s).
7127 (define_insn "*anddi3_cc"
7128 [(set (reg CC_REGNUM)
7130 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
7131 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
7133 (set (match_operand:DI 0 "register_operand" "=d,d,d, d")
7134 (and:DI (match_dup 1) (match_dup 2)))]
7135 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
7140 risbg\t%0,%1,%s2,128+%e2,0"
7141 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
7142 (set_attr "cpu_facility" "*,z196,*,z10")
7143 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7145 (define_insn "*anddi3_cconly"
7146 [(set (reg CC_REGNUM)
7148 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
7149 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
7151 (clobber (match_scratch:DI 0 "=d,d,d, d"))]
7153 && s390_match_ccmode(insn, CCTmode)
7154 /* Do not steal TM patterns. */
7155 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
7160 risbg\t%0,%1,%s2,128+%e2,0"
7161 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
7162 (set_attr "cpu_facility" "*,z196,*,z10")
7163 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7165 (define_insn "*anddi3"
7166 [(set (match_operand:DI 0 "nonimmediate_operand"
7167 "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q")
7169 (match_operand:DI 1 "nonimmediate_operand"
7170 "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0")
7171 (match_operand:DI 2 "general_operand"
7172 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q")))
7173 (clobber (reg:CC CC_REGNUM))]
7174 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7187 risbg\t%0,%1,%s2,128+%e2,0
7190 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
7191 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
7192 (set_attr "z10prop" "*,
7208 [(set (match_operand:DI 0 "s_operand" "")
7209 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7210 (clobber (reg:CC CC_REGNUM))]
7213 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7214 (clobber (reg:CC CC_REGNUM))])]
7215 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7217 ;; These two are what combine generates for (ashift (zero_extract)).
7218 (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>"
7219 [(set (match_operand:GPR 0 "register_operand" "=d")
7220 (and:GPR (lshiftrt:GPR
7221 (match_operand:GPR 1 "register_operand" "d")
7222 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7223 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
7224 "<z10_or_zEC12_cond>
7225 /* Note that even for the SImode pattern, the rotate is always DImode. */
7226 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
7227 INTVAL (operands[3]))"
7228 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
7229 [(set_attr "op_type" "RIE")
7230 (set_attr "z10prop" "z10_super_E1")])
7232 (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>"
7233 [(set (match_operand:GPR 0 "register_operand" "=d")
7234 (and:GPR (ashift:GPR
7235 (match_operand:GPR 1 "register_operand" "d")
7236 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7237 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
7238 "<z10_or_zEC12_cond>
7239 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
7240 INTVAL (operands[3]))"
7241 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
7242 [(set_attr "op_type" "RIE")
7243 (set_attr "z10prop" "z10_super_E1")])
7247 ; andsi3 instruction pattern(s).
7250 (define_insn "*andsi3_cc"
7251 [(set (reg CC_REGNUM)
7254 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7255 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7257 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
7258 (and:SI (match_dup 1) (match_dup 2)))]
7259 "s390_match_ccmode(insn, CCTmode)"
7266 risbg\t%0,%1,%t2,128+%f2,0"
7267 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7268 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7269 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7270 z10_super_E1,z10_super_E1,z10_super_E1")])
7272 (define_insn "*andsi3_cconly"
7273 [(set (reg CC_REGNUM)
7276 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7277 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7279 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
7280 "s390_match_ccmode(insn, CCTmode)
7281 /* Do not steal TM patterns. */
7282 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7289 risbg\t%0,%1,%t2,128+%f2,0"
7290 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7291 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7292 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7293 z10_super_E1,z10_super_E1,z10_super_E1")])
7295 (define_insn "*andsi3_zarch"
7296 [(set (match_operand:SI 0 "nonimmediate_operand"
7297 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
7298 (and:SI (match_operand:SI 1 "nonimmediate_operand"
7299 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
7300 (match_operand:SI 2 "general_operand"
7301 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q")))
7302 (clobber (reg:CC CC_REGNUM))]
7303 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7314 risbg\t%0,%1,%t2,128+%f2,0
7317 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7318 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
7319 (set_attr "z10prop" "*,
7332 (define_insn "*andsi3_esa"
7333 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
7334 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
7335 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
7336 (clobber (reg:CC CC_REGNUM))]
7337 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7343 [(set_attr "op_type" "RR,RX,SI,SS")
7344 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7348 [(set (match_operand:SI 0 "s_operand" "")
7349 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7350 (clobber (reg:CC CC_REGNUM))]
7353 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7354 (clobber (reg:CC CC_REGNUM))])]
7355 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7358 ; andhi3 instruction pattern(s).
7361 (define_insn "*andhi3_zarch"
7362 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7363 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7364 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
7365 (clobber (reg:CC CC_REGNUM))]
7366 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7373 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7374 (set_attr "cpu_facility" "*,z196,*,*,*")
7375 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7378 (define_insn "*andhi3_esa"
7379 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7380 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7381 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7382 (clobber (reg:CC CC_REGNUM))]
7383 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7388 [(set_attr "op_type" "RR,SI,SS")
7389 (set_attr "z10prop" "z10_super_E1,*,*")
7393 [(set (match_operand:HI 0 "s_operand" "")
7394 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7395 (clobber (reg:CC CC_REGNUM))]
7398 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7399 (clobber (reg:CC CC_REGNUM))])]
7400 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7403 ; andqi3 instruction pattern(s).
7406 (define_insn "*andqi3_zarch"
7407 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7408 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7409 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7410 (clobber (reg:CC CC_REGNUM))]
7411 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7419 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7420 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7421 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7423 (define_insn "*andqi3_esa"
7424 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7425 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7426 (match_operand:QI 2 "general_operand" "d,n,Q")))
7427 (clobber (reg:CC CC_REGNUM))]
7428 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7433 [(set_attr "op_type" "RR,SI,SS")
7434 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7437 ; And with complement
7439 ; c = ~b & a = (b & a) ^ a
7441 (define_insn_and_split "*andc_split_<mode>"
7442 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
7443 (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
7444 (match_operand:GPR 2 "general_operand" "")))
7445 (clobber (reg:CC CC_REGNUM))]
7447 && (GET_CODE (operands[0]) != MEM
7448 /* Ensure that s390_logical_operator_ok_p will succeed even
7449 on the split xor if (b & a) is stored into a pseudo. */
7450 || rtx_equal_p (operands[0], operands[2]))"
7455 [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2)))
7456 (clobber (reg:CC CC_REGNUM))])
7458 [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2)))
7459 (clobber (reg:CC CC_REGNUM))])]
7461 if (reg_overlap_mentioned_p (operands[0], operands[2]))
7462 operands[3] = gen_reg_rtx (<MODE>mode);
7464 operands[3] = operands[0];
7468 ; Block and (NC) patterns.
7472 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7473 (and:BLK (match_dup 0)
7474 (match_operand:BLK 1 "memory_operand" "Q")))
7475 (use (match_operand 2 "const_int_operand" "n"))
7476 (clobber (reg:CC CC_REGNUM))]
7477 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7478 "nc\t%O0(%2,%R0),%S1"
7479 [(set_attr "op_type" "SS")
7480 (set_attr "z196prop" "z196_cracked")])
7483 [(set (match_operand 0 "memory_operand" "")
7485 (match_operand 1 "memory_operand" "")))
7486 (clobber (reg:CC CC_REGNUM))]
7488 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7489 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7491 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7493 (clobber (reg:CC CC_REGNUM))])]
7495 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7496 operands[0] = adjust_address (operands[0], BLKmode, 0);
7497 operands[1] = adjust_address (operands[1], BLKmode, 0);
7502 [(set (match_operand:BLK 0 "memory_operand" "")
7503 (and:BLK (match_dup 0)
7504 (match_operand:BLK 1 "memory_operand" "")))
7505 (use (match_operand 2 "const_int_operand" ""))
7506 (clobber (reg:CC CC_REGNUM))])
7508 [(set (match_operand:BLK 3 "memory_operand" "")
7509 (and:BLK (match_dup 3)
7510 (match_operand:BLK 4 "memory_operand" "")))
7511 (use (match_operand 5 "const_int_operand" ""))
7512 (clobber (reg:CC CC_REGNUM))])]
7513 "s390_offset_p (operands[0], operands[3], operands[2])
7514 && s390_offset_p (operands[1], operands[4], operands[2])
7515 && !s390_overlap_p (operands[0], operands[1],
7516 INTVAL (operands[2]) + INTVAL (operands[5]))
7517 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7519 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7521 (clobber (reg:CC CC_REGNUM))])]
7522 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7523 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7524 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7528 ;;- Bit set (inclusive or) instructions.
7531 (define_expand "ior<mode>3"
7532 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7533 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7534 (match_operand:INT 2 "general_operand" "")))
7535 (clobber (reg:CC CC_REGNUM))]
7537 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7540 ; iordi3 instruction pattern(s).
7543 (define_insn "*iordi3_cc"
7544 [(set (reg CC_REGNUM)
7545 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7546 (match_operand:DI 2 "general_operand" " d,d,T"))
7548 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7549 (ior:DI (match_dup 1) (match_dup 2)))]
7550 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7555 [(set_attr "op_type" "RRE,RRF,RXY")
7556 (set_attr "cpu_facility" "*,z196,*")
7557 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7559 (define_insn "*iordi3_cconly"
7560 [(set (reg CC_REGNUM)
7561 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7562 (match_operand:DI 2 "general_operand" " d,d,T"))
7564 (clobber (match_scratch:DI 0 "=d,d,d"))]
7565 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7570 [(set_attr "op_type" "RRE,RRF,RXY")
7571 (set_attr "cpu_facility" "*,z196,*")
7572 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7574 (define_insn "*iordi3"
7575 [(set (match_operand:DI 0 "nonimmediate_operand"
7576 "=d, d, d, d, d, d,d,d,d, AQ,Q")
7577 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7578 " %0, 0, 0, 0, 0, 0,0,d,0, 0,0")
7579 (match_operand:DI 2 "general_operand"
7580 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7581 (clobber (reg:CC CC_REGNUM))]
7582 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7595 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7596 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7597 (set_attr "z10prop" "z10_super_E1,
7610 [(set (match_operand:DI 0 "s_operand" "")
7611 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7612 (clobber (reg:CC CC_REGNUM))]
7615 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7616 (clobber (reg:CC CC_REGNUM))])]
7617 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7620 ; iorsi3 instruction pattern(s).
7623 (define_insn "*iorsi3_cc"
7624 [(set (reg CC_REGNUM)
7625 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7626 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7628 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7629 (ior:SI (match_dup 1) (match_dup 2)))]
7630 "s390_match_ccmode(insn, CCTmode)"
7637 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7638 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7639 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7641 (define_insn "*iorsi3_cconly"
7642 [(set (reg CC_REGNUM)
7643 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7644 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7646 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7647 "s390_match_ccmode(insn, CCTmode)"
7654 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7655 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7656 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7658 (define_insn "*iorsi3_zarch"
7659 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
7660 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
7661 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7662 (clobber (reg:CC CC_REGNUM))]
7663 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7674 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7675 (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
7676 (set_attr "z10prop" "z10_super_E1,
7686 (define_insn "*iorsi3_esa"
7687 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7688 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7689 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7690 (clobber (reg:CC CC_REGNUM))]
7691 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7697 [(set_attr "op_type" "RR,RX,SI,SS")
7698 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7701 [(set (match_operand:SI 0 "s_operand" "")
7702 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7703 (clobber (reg:CC CC_REGNUM))]
7706 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7707 (clobber (reg:CC CC_REGNUM))])]
7708 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7711 ; iorhi3 instruction pattern(s).
7714 (define_insn "*iorhi3_zarch"
7715 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7716 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7717 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
7718 (clobber (reg:CC CC_REGNUM))]
7719 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7726 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7727 (set_attr "cpu_facility" "*,z196,*,*,*")
7728 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7730 (define_insn "*iorhi3_esa"
7731 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7732 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7733 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7734 (clobber (reg:CC CC_REGNUM))]
7735 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7740 [(set_attr "op_type" "RR,SI,SS")
7741 (set_attr "z10prop" "z10_super_E1,*,*")])
7744 [(set (match_operand:HI 0 "s_operand" "")
7745 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7746 (clobber (reg:CC CC_REGNUM))]
7749 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7750 (clobber (reg:CC CC_REGNUM))])]
7751 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7754 ; iorqi3 instruction pattern(s).
7757 (define_insn "*iorqi3_zarch"
7758 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7759 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7760 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7761 (clobber (reg:CC CC_REGNUM))]
7762 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7770 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7771 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7772 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7773 z10_super,z10_super,*")])
7775 (define_insn "*iorqi3_esa"
7776 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7777 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7778 (match_operand:QI 2 "general_operand" "d,n,Q")))
7779 (clobber (reg:CC CC_REGNUM))]
7780 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7785 [(set_attr "op_type" "RR,SI,SS")
7786 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7789 ; Block inclusive or (OC) patterns.
7793 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7794 (ior:BLK (match_dup 0)
7795 (match_operand:BLK 1 "memory_operand" "Q")))
7796 (use (match_operand 2 "const_int_operand" "n"))
7797 (clobber (reg:CC CC_REGNUM))]
7798 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7799 "oc\t%O0(%2,%R0),%S1"
7800 [(set_attr "op_type" "SS")
7801 (set_attr "z196prop" "z196_cracked")])
7804 [(set (match_operand 0 "memory_operand" "")
7806 (match_operand 1 "memory_operand" "")))
7807 (clobber (reg:CC CC_REGNUM))]
7809 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7810 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7812 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7814 (clobber (reg:CC CC_REGNUM))])]
7816 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7817 operands[0] = adjust_address (operands[0], BLKmode, 0);
7818 operands[1] = adjust_address (operands[1], BLKmode, 0);
7823 [(set (match_operand:BLK 0 "memory_operand" "")
7824 (ior:BLK (match_dup 0)
7825 (match_operand:BLK 1 "memory_operand" "")))
7826 (use (match_operand 2 "const_int_operand" ""))
7827 (clobber (reg:CC CC_REGNUM))])
7829 [(set (match_operand:BLK 3 "memory_operand" "")
7830 (ior:BLK (match_dup 3)
7831 (match_operand:BLK 4 "memory_operand" "")))
7832 (use (match_operand 5 "const_int_operand" ""))
7833 (clobber (reg:CC CC_REGNUM))])]
7834 "s390_offset_p (operands[0], operands[3], operands[2])
7835 && s390_offset_p (operands[1], operands[4], operands[2])
7836 && !s390_overlap_p (operands[0], operands[1],
7837 INTVAL (operands[2]) + INTVAL (operands[5]))
7838 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7840 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7842 (clobber (reg:CC CC_REGNUM))])]
7843 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7844 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7845 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7849 ;;- Xor instructions.
7852 (define_expand "xor<mode>3"
7853 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7854 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7855 (match_operand:INT 2 "general_operand" "")))
7856 (clobber (reg:CC CC_REGNUM))]
7858 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7860 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7861 ; simplifications. So its better to have something matching.
7863 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7864 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7867 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7868 (clobber (reg:CC CC_REGNUM))])]
7870 operands[2] = constm1_rtx;
7871 if (!s390_logical_operator_ok_p (operands))
7876 ; xordi3 instruction pattern(s).
7879 (define_insn "*xordi3_cc"
7880 [(set (reg CC_REGNUM)
7881 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7882 (match_operand:DI 2 "general_operand" " d,d,T"))
7884 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7885 (xor:DI (match_dup 1) (match_dup 2)))]
7886 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7891 [(set_attr "op_type" "RRE,RRF,RXY")
7892 (set_attr "cpu_facility" "*,z196,*")
7893 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7895 (define_insn "*xordi3_cconly"
7896 [(set (reg CC_REGNUM)
7897 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7898 (match_operand:DI 2 "general_operand" " d,d,T"))
7900 (clobber (match_scratch:DI 0 "=d,d,d"))]
7901 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7906 [(set_attr "op_type" "RRE,RRF,RXY")
7907 (set_attr "cpu_facility" "*,z196,*")
7908 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7910 (define_insn "*xordi3"
7911 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q")
7912 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0")
7913 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7914 (clobber (reg:CC CC_REGNUM))]
7915 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7924 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7925 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7926 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7927 *,z10_super_E1,*,*")])
7930 [(set (match_operand:DI 0 "s_operand" "")
7931 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7932 (clobber (reg:CC CC_REGNUM))]
7935 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7936 (clobber (reg:CC CC_REGNUM))])]
7937 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7940 ; xorsi3 instruction pattern(s).
7943 (define_insn "*xorsi3_cc"
7944 [(set (reg CC_REGNUM)
7945 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7946 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7948 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7949 (xor:SI (match_dup 1) (match_dup 2)))]
7950 "s390_match_ccmode(insn, CCTmode)"
7957 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7958 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7959 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7960 z10_super_E1,z10_super_E1")])
7962 (define_insn "*xorsi3_cconly"
7963 [(set (reg CC_REGNUM)
7964 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7965 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7967 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7968 "s390_match_ccmode(insn, CCTmode)"
7975 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7976 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7977 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7978 z10_super_E1,z10_super_E1")])
7980 (define_insn "*xorsi3"
7981 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7982 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7983 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7984 (clobber (reg:CC CC_REGNUM))]
7985 "s390_logical_operator_ok_p (operands)"
7994 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7995 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
7996 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7997 z10_super_E1,z10_super_E1,*,*")])
8000 [(set (match_operand:SI 0 "s_operand" "")
8001 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
8002 (clobber (reg:CC CC_REGNUM))]
8005 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
8006 (clobber (reg:CC CC_REGNUM))])]
8007 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
8010 ; xorhi3 instruction pattern(s).
8013 (define_insn "*xorhi3"
8014 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
8015 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
8016 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
8017 (clobber (reg:CC CC_REGNUM))]
8018 "s390_logical_operator_ok_p (operands)"
8025 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
8026 (set_attr "cpu_facility" "*,*,z196,*,*")
8027 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
8030 [(set (match_operand:HI 0 "s_operand" "")
8031 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
8032 (clobber (reg:CC CC_REGNUM))]
8035 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
8036 (clobber (reg:CC CC_REGNUM))])]
8037 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
8040 ; xorqi3 instruction pattern(s).
8043 (define_insn "*xorqi3"
8044 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
8045 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
8046 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
8047 (clobber (reg:CC CC_REGNUM))]
8048 "s390_logical_operator_ok_p (operands)"
8056 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
8057 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
8058 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
8062 ; Block exclusive or (XC) patterns.
8066 [(set (match_operand:BLK 0 "memory_operand" "=Q")
8067 (xor:BLK (match_dup 0)
8068 (match_operand:BLK 1 "memory_operand" "Q")))
8069 (use (match_operand 2 "const_int_operand" "n"))
8070 (clobber (reg:CC CC_REGNUM))]
8071 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
8072 "xc\t%O0(%2,%R0),%S1"
8073 [(set_attr "op_type" "SS")])
8076 [(set (match_operand 0 "memory_operand" "")
8078 (match_operand 1 "memory_operand" "")))
8079 (clobber (reg:CC CC_REGNUM))]
8081 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8082 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
8084 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
8086 (clobber (reg:CC CC_REGNUM))])]
8088 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
8089 operands[0] = adjust_address (operands[0], BLKmode, 0);
8090 operands[1] = adjust_address (operands[1], BLKmode, 0);
8095 [(set (match_operand:BLK 0 "memory_operand" "")
8096 (xor:BLK (match_dup 0)
8097 (match_operand:BLK 1 "memory_operand" "")))
8098 (use (match_operand 2 "const_int_operand" ""))
8099 (clobber (reg:CC CC_REGNUM))])
8101 [(set (match_operand:BLK 3 "memory_operand" "")
8102 (xor:BLK (match_dup 3)
8103 (match_operand:BLK 4 "memory_operand" "")))
8104 (use (match_operand 5 "const_int_operand" ""))
8105 (clobber (reg:CC CC_REGNUM))])]
8106 "s390_offset_p (operands[0], operands[3], operands[2])
8107 && s390_offset_p (operands[1], operands[4], operands[2])
8108 && !s390_overlap_p (operands[0], operands[1],
8109 INTVAL (operands[2]) + INTVAL (operands[5]))
8110 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
8112 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
8114 (clobber (reg:CC CC_REGNUM))])]
8115 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8116 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
8117 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
8120 ; Block xor (XC) patterns with src == dest.
8123 (define_insn "*xc_zero"
8124 [(set (match_operand:BLK 0 "memory_operand" "=Q")
8126 (use (match_operand 1 "const_int_operand" "n"))
8127 (clobber (reg:CC CC_REGNUM))]
8128 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
8129 "xc\t%O0(%1,%R0),%S0"
8130 [(set_attr "op_type" "SS")
8131 (set_attr "z196prop" "z196_cracked")])
8135 [(set (match_operand:BLK 0 "memory_operand" "")
8137 (use (match_operand 1 "const_int_operand" ""))
8138 (clobber (reg:CC CC_REGNUM))])
8140 [(set (match_operand:BLK 2 "memory_operand" "")
8142 (use (match_operand 3 "const_int_operand" ""))
8143 (clobber (reg:CC CC_REGNUM))])]
8144 "s390_offset_p (operands[0], operands[2], operands[1])
8145 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
8147 [(set (match_dup 4) (const_int 0))
8149 (clobber (reg:CC CC_REGNUM))])]
8150 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8151 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
8155 ;;- Negate instructions.
8159 ; neg(di|si)2 instruction pattern(s).
8162 (define_expand "neg<mode>2"
8164 [(set (match_operand:DSI 0 "register_operand" "=d")
8165 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
8166 (clobber (reg:CC CC_REGNUM))])]
8170 (define_insn "*negdi2_sign_cc"
8171 [(set (reg CC_REGNUM)
8172 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
8173 (match_operand:SI 1 "register_operand" "d") 0)
8174 (const_int 32)) (const_int 32)))
8176 (set (match_operand:DI 0 "register_operand" "=d")
8177 (neg:DI (sign_extend:DI (match_dup 1))))]
8178 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8180 [(set_attr "op_type" "RRE")
8181 (set_attr "z10prop" "z10_c")])
8183 (define_insn "*negdi2_sign"
8184 [(set (match_operand:DI 0 "register_operand" "=d")
8185 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8186 (clobber (reg:CC CC_REGNUM))]
8189 [(set_attr "op_type" "RRE")
8190 (set_attr "z10prop" "z10_c")])
8193 (define_insn "*neg<mode>2_cc"
8194 [(set (reg CC_REGNUM)
8195 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8197 (set (match_operand:GPR 0 "register_operand" "=d")
8198 (neg:GPR (match_dup 1)))]
8199 "s390_match_ccmode (insn, CCAmode)"
8201 [(set_attr "op_type" "RR<E>")
8202 (set_attr "z10prop" "z10_super_c_E1")])
8205 (define_insn "*neg<mode>2_cconly"
8206 [(set (reg CC_REGNUM)
8207 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8209 (clobber (match_scratch:GPR 0 "=d"))]
8210 "s390_match_ccmode (insn, CCAmode)"
8212 [(set_attr "op_type" "RR<E>")
8213 (set_attr "z10prop" "z10_super_c_E1")])
8216 (define_insn "*neg<mode>2"
8217 [(set (match_operand:GPR 0 "register_operand" "=d")
8218 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
8219 (clobber (reg:CC CC_REGNUM))]
8222 [(set_attr "op_type" "RR<E>")
8223 (set_attr "z10prop" "z10_super_c_E1")])
8225 (define_insn "*negdi2_31"
8226 [(set (match_operand:DI 0 "register_operand" "=d")
8227 (neg:DI (match_operand:DI 1 "register_operand" "d")))
8228 (clobber (reg:CC CC_REGNUM))]
8232 ; Split a DImode NEG on 31bit into 2 SImode NEGs
8234 ; Doing the twos complement separately on the SImode parts does an
8235 ; unwanted +1 on the high part which needs to be subtracted afterwards
8236 ; ... unless the +1 on the low part created an overflow.
8239 [(set (match_operand:DI 0 "register_operand" "")
8240 (neg:DI (match_operand:DI 1 "register_operand" "")))
8241 (clobber (reg:CC CC_REGNUM))]
8243 && (REGNO (operands[0]) == REGNO (operands[1])
8244 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
8245 && reload_completed"
8247 [(set (match_dup 2) (neg:SI (match_dup 3)))
8248 (clobber (reg:CC CC_REGNUM))])
8250 [(set (reg:CCAP CC_REGNUM)
8251 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
8252 (set (match_dup 4) (neg:SI (match_dup 5)))])
8254 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8256 (label_ref (match_dup 6))))
8258 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8259 (clobber (reg:CC CC_REGNUM))])
8261 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8262 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8263 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8264 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8265 operands[6] = gen_label_rtx ();")
8267 ; Like above but first make a copy of the low part of the src operand
8268 ; since it might overlap with the high part of the destination.
8271 [(set (match_operand:DI 0 "register_operand" "")
8272 (neg:DI (match_operand:DI 1 "register_operand" "")))
8273 (clobber (reg:CC CC_REGNUM))]
8275 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
8276 && reload_completed"
8277 [; Make a backup of op5 first
8278 (set (match_dup 4) (match_dup 5))
8279 ; Setting op2 here might clobber op5
8281 [(set (match_dup 2) (neg:SI (match_dup 3)))
8282 (clobber (reg:CC CC_REGNUM))])
8284 [(set (reg:CCAP CC_REGNUM)
8285 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
8286 (set (match_dup 4) (neg:SI (match_dup 4)))])
8288 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8290 (label_ref (match_dup 6))))
8292 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8293 (clobber (reg:CC CC_REGNUM))])
8295 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8296 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8297 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8298 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8299 operands[6] = gen_label_rtx ();")
8302 ; neg(df|sf)2 instruction pattern(s).
8305 (define_expand "neg<mode>2"
8307 [(set (match_operand:BFP 0 "register_operand" "=f")
8308 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
8309 (clobber (reg:CC CC_REGNUM))])]
8313 ; lcxbr, lcdbr, lcebr
8314 (define_insn "*neg<mode>2_cc"
8315 [(set (reg CC_REGNUM)
8316 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8317 (match_operand:BFP 2 "const0_operand" "")))
8318 (set (match_operand:BFP 0 "register_operand" "=f")
8319 (neg:BFP (match_dup 1)))]
8320 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8322 [(set_attr "op_type" "RRE")
8323 (set_attr "type" "fsimp<mode>")])
8325 ; lcxbr, lcdbr, lcebr
8326 (define_insn "*neg<mode>2_cconly"
8327 [(set (reg CC_REGNUM)
8328 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8329 (match_operand:BFP 2 "const0_operand" "")))
8330 (clobber (match_scratch:BFP 0 "=f"))]
8331 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8333 [(set_attr "op_type" "RRE")
8334 (set_attr "type" "fsimp<mode>")])
8337 (define_insn "*neg<mode>2_nocc"
8338 [(set (match_operand:FP 0 "register_operand" "=f")
8339 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8342 [(set_attr "op_type" "RRE")
8343 (set_attr "type" "fsimp<mode>")])
8345 ; lcxbr, lcdbr, lcebr
8346 ; FIXME: wflcdb does not clobber cc
8347 (define_insn "*neg<mode>2"
8348 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8349 (neg:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8350 (clobber (reg:CC CC_REGNUM))]
8355 [(set_attr "op_type" "RRE,VRR")
8356 (set_attr "cpu_facility" "*,vx")
8357 (set_attr "type" "fsimp<mode>,*")
8358 (set_attr "enabled" "*,<DFDI>")])
8362 ;;- Absolute value instructions.
8366 ; abs(di|si)2 instruction pattern(s).
8369 (define_insn "*absdi2_sign_cc"
8370 [(set (reg CC_REGNUM)
8371 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8372 (match_operand:SI 1 "register_operand" "d") 0)
8373 (const_int 32)) (const_int 32)))
8375 (set (match_operand:DI 0 "register_operand" "=d")
8376 (abs:DI (sign_extend:DI (match_dup 1))))]
8377 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8379 [(set_attr "op_type" "RRE")
8380 (set_attr "z10prop" "z10_c")])
8382 (define_insn "*absdi2_sign"
8383 [(set (match_operand:DI 0 "register_operand" "=d")
8384 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8385 (clobber (reg:CC CC_REGNUM))]
8388 [(set_attr "op_type" "RRE")
8389 (set_attr "z10prop" "z10_c")])
8392 (define_insn "*abs<mode>2_cc"
8393 [(set (reg CC_REGNUM)
8394 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8396 (set (match_operand:GPR 0 "register_operand" "=d")
8397 (abs:GPR (match_dup 1)))]
8398 "s390_match_ccmode (insn, CCAmode)"
8400 [(set_attr "op_type" "RR<E>")
8401 (set_attr "z10prop" "z10_c")])
8404 (define_insn "*abs<mode>2_cconly"
8405 [(set (reg CC_REGNUM)
8406 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8408 (clobber (match_scratch:GPR 0 "=d"))]
8409 "s390_match_ccmode (insn, CCAmode)"
8411 [(set_attr "op_type" "RR<E>")
8412 (set_attr "z10prop" "z10_c")])
8415 (define_insn "abs<mode>2"
8416 [(set (match_operand:GPR 0 "register_operand" "=d")
8417 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8418 (clobber (reg:CC CC_REGNUM))]
8421 [(set_attr "op_type" "RR<E>")
8422 (set_attr "z10prop" "z10_c")])
8425 ; abs(df|sf)2 instruction pattern(s).
8428 (define_expand "abs<mode>2"
8430 [(set (match_operand:BFP 0 "register_operand" "=f")
8431 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8432 (clobber (reg:CC CC_REGNUM))])]
8436 ; lpxbr, lpdbr, lpebr
8437 (define_insn "*abs<mode>2_cc"
8438 [(set (reg CC_REGNUM)
8439 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8440 (match_operand:BFP 2 "const0_operand" "")))
8441 (set (match_operand:BFP 0 "register_operand" "=f")
8442 (abs:BFP (match_dup 1)))]
8443 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8445 [(set_attr "op_type" "RRE")
8446 (set_attr "type" "fsimp<mode>")])
8448 ; lpxbr, lpdbr, lpebr
8449 (define_insn "*abs<mode>2_cconly"
8450 [(set (reg CC_REGNUM)
8451 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8452 (match_operand:BFP 2 "const0_operand" "")))
8453 (clobber (match_scratch:BFP 0 "=f"))]
8454 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8456 [(set_attr "op_type" "RRE")
8457 (set_attr "type" "fsimp<mode>")])
8460 (define_insn "*abs<mode>2_nocc"
8461 [(set (match_operand:FP 0 "register_operand" "=f")
8462 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8465 [(set_attr "op_type" "RRE")
8466 (set_attr "type" "fsimp<mode>")])
8468 ; lpxbr, lpdbr, lpebr
8469 ; FIXME: wflpdb does not clobber cc
8470 (define_insn "*abs<mode>2"
8471 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8472 (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8473 (clobber (reg:CC CC_REGNUM))]
8478 [(set_attr "op_type" "RRE,VRR")
8479 (set_attr "cpu_facility" "*,vx")
8480 (set_attr "type" "fsimp<mode>,*")
8481 (set_attr "enabled" "*,<DFDI>")])
8485 ;;- Negated absolute value instructions
8492 (define_insn "*negabsdi2_sign_cc"
8493 [(set (reg CC_REGNUM)
8494 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8495 (match_operand:SI 1 "register_operand" "d") 0)
8496 (const_int 32)) (const_int 32))))
8498 (set (match_operand:DI 0 "register_operand" "=d")
8499 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8500 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8502 [(set_attr "op_type" "RRE")
8503 (set_attr "z10prop" "z10_c")])
8505 (define_insn "*negabsdi2_sign"
8506 [(set (match_operand:DI 0 "register_operand" "=d")
8507 (neg:DI (abs:DI (sign_extend:DI
8508 (match_operand:SI 1 "register_operand" "d")))))
8509 (clobber (reg:CC CC_REGNUM))]
8512 [(set_attr "op_type" "RRE")
8513 (set_attr "z10prop" "z10_c")])
8516 (define_insn "*negabs<mode>2_cc"
8517 [(set (reg CC_REGNUM)
8518 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8520 (set (match_operand:GPR 0 "register_operand" "=d")
8521 (neg:GPR (abs:GPR (match_dup 1))))]
8522 "s390_match_ccmode (insn, CCAmode)"
8524 [(set_attr "op_type" "RR<E>")
8525 (set_attr "z10prop" "z10_c")])
8528 (define_insn "*negabs<mode>2_cconly"
8529 [(set (reg CC_REGNUM)
8530 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8532 (clobber (match_scratch:GPR 0 "=d"))]
8533 "s390_match_ccmode (insn, CCAmode)"
8535 [(set_attr "op_type" "RR<E>")
8536 (set_attr "z10prop" "z10_c")])
8539 (define_insn "*negabs<mode>2"
8540 [(set (match_operand:GPR 0 "register_operand" "=d")
8541 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8542 (clobber (reg:CC CC_REGNUM))]
8545 [(set_attr "op_type" "RR<E>")
8546 (set_attr "z10prop" "z10_c")])
8552 ; lnxbr, lndbr, lnebr
8553 (define_insn "*negabs<mode>2_cc"
8554 [(set (reg CC_REGNUM)
8555 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8556 (match_operand:BFP 2 "const0_operand" "")))
8557 (set (match_operand:BFP 0 "register_operand" "=f")
8558 (neg:BFP (abs:BFP (match_dup 1))))]
8559 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8561 [(set_attr "op_type" "RRE")
8562 (set_attr "type" "fsimp<mode>")])
8564 ; lnxbr, lndbr, lnebr
8565 (define_insn "*negabs<mode>2_cconly"
8566 [(set (reg CC_REGNUM)
8567 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8568 (match_operand:BFP 2 "const0_operand" "")))
8569 (clobber (match_scratch:BFP 0 "=f"))]
8570 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8572 [(set_attr "op_type" "RRE")
8573 (set_attr "type" "fsimp<mode>")])
8576 (define_insn "*negabs<mode>2_nocc"
8577 [(set (match_operand:FP 0 "register_operand" "=f")
8578 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8581 [(set_attr "op_type" "RRE")
8582 (set_attr "type" "fsimp<mode>")])
8584 ; lnxbr, lndbr, lnebr
8585 ; FIXME: wflndb does not clobber cc
8586 (define_insn "*negabs<mode>2"
8587 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8588 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))))
8589 (clobber (reg:CC CC_REGNUM))]
8594 [(set_attr "op_type" "RRE,VRR")
8595 (set_attr "cpu_facility" "*,vx")
8596 (set_attr "type" "fsimp<mode>,*")
8597 (set_attr "enabled" "*,<DFDI>")])
8600 ;;- Square root instructions.
8604 ; sqrt(df|sf)2 instruction pattern(s).
8607 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8608 (define_insn "sqrt<mode>2"
8609 [(set (match_operand:BFP 0 "register_operand" "=f,f,v")
8610 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))]
8616 [(set_attr "op_type" "RRE,RXE,VRR")
8617 (set_attr "type" "fsqrt<mode>")
8618 (set_attr "cpu_facility" "*,*,vx")
8619 (set_attr "enabled" "*,<DSF>,<DFDI>")])
8623 ;;- One complement instructions.
8627 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8630 (define_expand "one_cmpl<mode>2"
8632 [(set (match_operand:INT 0 "register_operand" "")
8633 (xor:INT (match_operand:INT 1 "register_operand" "")
8635 (clobber (reg:CC CC_REGNUM))])]
8641 ;; Find leftmost bit instructions.
8644 (define_expand "clzdi2"
8645 [(set (match_operand:DI 0 "register_operand" "=d")
8646 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8647 "TARGET_EXTIMM && TARGET_ZARCH"
8651 rtx wide_reg = gen_reg_rtx (TImode);
8652 rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63);
8654 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8656 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8658 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8659 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8664 (define_insn "clztidi2"
8665 [(set (match_operand:TI 0 "register_operand" "=d")
8669 (xor:DI (match_operand:DI 1 "register_operand" "d")
8670 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8671 (subreg:SI (clz:DI (match_dup 1)) 4))))
8674 (zero_extend:TI (clz:DI (match_dup 1)))))
8675 (clobber (reg:CC CC_REGNUM))]
8676 "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63
8677 && TARGET_EXTIMM && TARGET_ZARCH"
8679 [(set_attr "op_type" "RRE")])
8683 ;;- Rotate instructions.
8687 ; rotl(di|si)3 instruction pattern(s).
8690 (define_expand "rotl<mode>3"
8691 [(set (match_operand:GPR 0 "register_operand" "")
8692 (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8693 (match_operand:SI 2 "nonmemory_operand" "")))]
8698 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8699 [(set (match_operand:GPR 0 "register_operand" "=d")
8700 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8701 (match_operand:SI 2 "nonmemory_operand" "an")))]
8703 "rll<g>\t%0,%1,<addr_style_op_ops>"
8704 [(set_attr "op_type" "RSE")
8705 (set_attr "atype" "reg")
8706 (set_attr "z10prop" "z10_super_E1")])
8710 ;;- Shift instructions.
8714 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8715 ; Left shifts and logical right shifts
8717 (define_expand "<shift><mode>3"
8718 [(set (match_operand:DSI 0 "register_operand" "")
8719 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8720 (match_operand:SI 2 "nonmemory_operand" "")))]
8724 ; ESA 64 bit register pair shift with reg or imm shift count
8726 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8727 [(set (match_operand:DI 0 "register_operand" "=d")
8728 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8729 (match_operand:SI 2 "nonmemory_operand" "an")))]
8731 "s<lr>dl\t%0,<addr_style_op_ops>"
8732 [(set_attr "op_type" "RS")
8733 (set_attr "atype" "reg")
8734 (set_attr "z196prop" "z196_cracked")])
8737 ; 64 bit register shift with reg or imm shift count
8738 ; sll, srl, sllg, srlg, sllk, srlk
8739 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8740 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8741 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8742 (match_operand:SI 2 "nonmemory_operand" "an,an")))]
8745 s<lr>l<g>\t%0,<1><addr_style_op_ops>
8746 s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8747 [(set_attr "op_type" "RS<E>,RSY")
8748 (set_attr "atype" "reg,reg")
8749 (set_attr "cpu_facility" "*,z196")
8750 (set_attr "z10prop" "z10_super_E1,*")])
8753 ; ashr(di|si)3 instruction pattern(s).
8754 ; Arithmetic right shifts
8756 (define_expand "ashr<mode>3"
8758 [(set (match_operand:DSI 0 "register_operand" "")
8759 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8760 (match_operand:SI 2 "nonmemory_operand" "")))
8761 (clobber (reg:CC CC_REGNUM))])]
8765 ; FIXME: The number of alternatives is doubled here to match the fix
8766 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8767 ; The right fix should be to support match_scratch in the output
8768 ; pattern of a define_subst.
8769 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8770 [(set (match_operand:DI 0 "register_operand" "=d, d")
8771 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0")
8772 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8773 (clobber (reg:CC CC_REGNUM))]
8776 srda\t%0,<addr_style_op_cc_ops>
8777 srda\t%0,<addr_style_op_cc_ops>"
8778 [(set_attr "op_type" "RS")
8779 (set_attr "atype" "reg")])
8783 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8784 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8785 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8786 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8787 (clobber (reg:CC CC_REGNUM))]
8790 sra<g>\t%0,<1><addr_style_op_cc_ops>
8791 sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8792 [(set_attr "op_type" "RS<E>,RSY")
8793 (set_attr "atype" "reg")
8794 (set_attr "cpu_facility" "*,z196")
8795 (set_attr "z10prop" "z10_super_E1,*")])
8799 ;; Branch instruction patterns.
8802 (define_expand "cbranch<mode>4"
8804 (if_then_else (match_operator 0 "comparison_operator"
8805 [(match_operand:GPR 1 "register_operand" "")
8806 (match_operand:GPR 2 "general_operand" "")])
8807 (label_ref (match_operand 3 "" ""))
8810 "s390_emit_jump (operands[3],
8811 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8814 (define_expand "cbranch<mode>4"
8816 (if_then_else (match_operator 0 "comparison_operator"
8817 [(match_operand:FP 1 "register_operand" "")
8818 (match_operand:FP 2 "general_operand" "")])
8819 (label_ref (match_operand 3 "" ""))
8822 "s390_emit_jump (operands[3],
8823 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8826 (define_expand "cbranchcc4"
8828 (if_then_else (match_operator 0 "s390_comparison"
8829 [(match_operand 1 "cc_reg_operand" "")
8830 (match_operand 2 "const_int_operand" "")])
8831 (label_ref (match_operand 3 "" ""))
8838 ;;- Conditional jump instructions.
8841 (define_insn "*cjump_64"
8844 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8845 (match_operand 2 "const_int_operand" "")])
8846 (label_ref (match_operand 0 "" ""))
8850 if (get_attr_length (insn) == 4)
8853 return "jg%C1\t%l0";
8855 [(set_attr "op_type" "RI")
8856 (set_attr "type" "branch")
8857 (set (attr "length")
8858 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8859 (const_int 4) (const_int 6)))])
8861 (define_insn "*cjump_31"
8864 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8865 (match_operand 2 "const_int_operand" "")])
8866 (label_ref (match_operand 0 "" ""))
8870 gcc_assert (get_attr_length (insn) == 4);
8873 [(set_attr "op_type" "RI")
8874 (set_attr "type" "branch")
8875 (set (attr "length")
8876 (if_then_else (not (match_test "flag_pic"))
8877 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8878 (const_int 4) (const_int 6))
8879 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8880 (const_int 4) (const_int 8))))])
8882 (define_insn "*cjump_long"
8885 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8886 (match_operand 0 "address_operand" "ZQZR")
8890 if (get_attr_op_type (insn) == OP_TYPE_RR)
8895 [(set (attr "op_type")
8896 (if_then_else (match_operand 0 "register_operand" "")
8897 (const_string "RR") (const_string "RX")))
8898 (set_attr "type" "branch")
8899 (set_attr "atype" "agen")])
8901 ;; A conditional return instruction.
8902 (define_insn "*c<code>"
8905 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8908 "s390_can_use_<code>_insn ()"
8910 [(set_attr "op_type" "RR")
8911 (set_attr "type" "jsr")
8912 (set_attr "atype" "agen")])
8915 ;;- Negated conditional jump instructions.
8918 (define_insn "*icjump_64"
8921 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8923 (label_ref (match_operand 0 "" ""))))]
8926 if (get_attr_length (insn) == 4)
8929 return "jg%D1\t%l0";
8931 [(set_attr "op_type" "RI")
8932 (set_attr "type" "branch")
8933 (set (attr "length")
8934 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8935 (const_int 4) (const_int 6)))])
8937 (define_insn "*icjump_31"
8940 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8942 (label_ref (match_operand 0 "" ""))))]
8945 gcc_assert (get_attr_length (insn) == 4);
8948 [(set_attr "op_type" "RI")
8949 (set_attr "type" "branch")
8950 (set (attr "length")
8951 (if_then_else (not (match_test "flag_pic"))
8952 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8953 (const_int 4) (const_int 6))
8954 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8955 (const_int 4) (const_int 8))))])
8957 (define_insn "*icjump_long"
8960 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8962 (match_operand 0 "address_operand" "ZQZR")))]
8965 if (get_attr_op_type (insn) == OP_TYPE_RR)
8970 [(set (attr "op_type")
8971 (if_then_else (match_operand 0 "register_operand" "")
8972 (const_string "RR") (const_string "RX")))
8973 (set_attr "type" "branch")
8974 (set_attr "atype" "agen")])
8977 ;;- Trap instructions.
8981 [(trap_if (const_int 1) (const_int 0))]
8984 [(set_attr "op_type" "RI")
8985 (set_attr "type" "branch")])
8987 (define_expand "ctrap<mode>4"
8988 [(trap_if (match_operator 0 "comparison_operator"
8989 [(match_operand:GPR 1 "register_operand" "")
8990 (match_operand:GPR 2 "general_operand" "")])
8991 (match_operand 3 "const0_operand" ""))]
8994 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8995 operands[1], operands[2]);
8996 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
9000 (define_expand "ctrap<mode>4"
9001 [(trap_if (match_operator 0 "comparison_operator"
9002 [(match_operand:FP 1 "register_operand" "")
9003 (match_operand:FP 2 "general_operand" "")])
9004 (match_operand 3 "const0_operand" ""))]
9007 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
9008 operands[1], operands[2]);
9009 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
9013 (define_insn "condtrap"
9014 [(trap_if (match_operator 0 "s390_comparison"
9015 [(match_operand 1 "cc_reg_operand" "c")
9020 [(set_attr "op_type" "RI")
9021 (set_attr "type" "branch")])
9023 ; crt, cgrt, cit, cgit
9024 (define_insn "*cmp_and_trap_signed_int<mode>"
9025 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
9026 [(match_operand:GPR 1 "register_operand" "d,d")
9027 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
9033 [(set_attr "op_type" "RRF,RIE")
9034 (set_attr "type" "branch")
9035 (set_attr "z10prop" "z10_super_c,z10_super")])
9037 ; clrt, clgrt, clfit, clgit, clt, clgt
9038 (define_insn "*cmp_and_trap_unsigned_int<mode>"
9039 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
9040 [(match_operand:GPR 1 "register_operand" "d,d,d")
9041 (match_operand:GPR 2 "general_operand" "d,D,T")])
9048 [(set_attr "op_type" "RRF,RIE,RSY")
9049 (set_attr "type" "branch")
9050 (set_attr "z10prop" "z10_super_c,z10_super,*")
9051 (set_attr "cpu_facility" "z10,z10,zEC12")])
9054 (define_insn "*load_and_trap<mode>"
9055 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T")
9058 (set (match_operand:GPR 1 "register_operand" "=d")
9062 [(set_attr "op_type" "RXY")])
9066 ;;- Loop instructions.
9068 ;; This is all complicated by the fact that since this is a jump insn
9069 ;; we must handle our own output reloads.
9073 ; This splitter will be matched by combine and has to add the 2 moves
9074 ; necessary to load the compare and the increment values into a
9075 ; register pair as needed by brxle.
9077 (define_insn_and_split "*brx_stage1_<GPR:mode>"
9080 (match_operator 6 "s390_brx_operator"
9081 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
9082 (match_operand:GPR 2 "general_operand" ""))
9083 (match_operand:GPR 3 "register_operand" "")])
9084 (label_ref (match_operand 0 "" ""))
9086 (set (match_operand:GPR 4 "nonimmediate_operand" "")
9087 (plus:GPR (match_dup 1) (match_dup 2)))
9088 (clobber (match_scratch:GPR 5 ""))]
9091 "!reload_completed && !reload_in_progress"
9092 [(set (match_dup 7) (match_dup 2)) ; the increment
9093 (set (match_dup 8) (match_dup 3)) ; the comparison value
9094 (parallel [(set (pc)
9097 [(plus:GPR (match_dup 1) (match_dup 7))
9099 (label_ref (match_dup 0))
9102 (plus:GPR (match_dup 1) (match_dup 7)))
9103 (clobber (match_dup 5))
9104 (clobber (reg:CC CC_REGNUM))])]
9106 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
9107 operands[7] = gen_lowpart (<GPR:MODE>mode,
9108 gen_highpart (word_mode, dreg));
9109 operands[8] = gen_lowpart (<GPR:MODE>mode,
9110 gen_lowpart (word_mode, dreg));
9115 (define_insn_and_split "*brxg_64bit"
9118 (match_operator 5 "s390_brx_operator"
9119 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
9120 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
9121 (subreg:DI (match_dup 2) 8)])
9122 (label_ref (match_operand 0 "" ""))
9124 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
9125 (plus:DI (match_dup 1)
9126 (subreg:DI (match_dup 2) 0)))
9127 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
9128 (clobber (reg:CC CC_REGNUM))]
9131 if (which_alternative != 0)
9133 else if (get_attr_length (insn) == 6)
9134 return "brx%E5g\t%1,%2,%l0";
9136 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
9138 "&& reload_completed
9139 && (!REG_P (operands[3])
9140 || !rtx_equal_p (operands[1], operands[3]))"
9141 [(set (match_dup 4) (match_dup 1))
9142 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
9143 (clobber (reg:CC CC_REGNUM))])
9144 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
9145 (set (match_dup 3) (match_dup 4))
9146 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9147 (label_ref (match_dup 0))
9150 [(set_attr "op_type" "RIE")
9151 (set_attr "type" "branch")
9152 (set (attr "length")
9153 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9154 (const_int 6) (const_int 16)))])
9158 (define_insn_and_split "*brx_64bit"
9161 (match_operator 5 "s390_brx_operator"
9162 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9163 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
9164 (subreg:SI (match_dup 2) 12)])
9165 (label_ref (match_operand 0 "" ""))
9167 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9168 (plus:SI (match_dup 1)
9169 (subreg:SI (match_dup 2) 4)))
9170 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9171 (clobber (reg:CC CC_REGNUM))]
9174 if (which_alternative != 0)
9176 else if (get_attr_length (insn) == 6)
9177 return "brx%C5\t%1,%2,%l0";
9179 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9181 "&& reload_completed
9182 && (!REG_P (operands[3])
9183 || !rtx_equal_p (operands[1], operands[3]))"
9184 [(set (match_dup 4) (match_dup 1))
9185 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
9186 (clobber (reg:CC CC_REGNUM))])
9187 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
9188 (set (match_dup 3) (match_dup 4))
9189 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9190 (label_ref (match_dup 0))
9193 [(set_attr "op_type" "RSI")
9194 (set_attr "type" "branch")
9195 (set (attr "length")
9196 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9197 (const_int 6) (const_int 14)))])
9201 (define_insn_and_split "*brx_31bit"
9204 (match_operator 5 "s390_brx_operator"
9205 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9206 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9207 (subreg:SI (match_dup 2) 4)])
9208 (label_ref (match_operand 0 "" ""))
9210 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9211 (plus:SI (match_dup 1)
9212 (subreg:SI (match_dup 2) 0)))
9213 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9214 (clobber (reg:CC CC_REGNUM))]
9215 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9217 if (which_alternative != 0)
9219 else if (get_attr_length (insn) == 6)
9220 return "brx%C5\t%1,%2,%l0";
9222 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9224 "&& reload_completed
9225 && (!REG_P (operands[3])
9226 || !rtx_equal_p (operands[1], operands[3]))"
9227 [(set (match_dup 4) (match_dup 1))
9228 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9229 (clobber (reg:CC CC_REGNUM))])
9230 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9231 (set (match_dup 3) (match_dup 4))
9232 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9233 (label_ref (match_dup 0))
9236 [(set_attr "op_type" "RSI")
9237 (set_attr "type" "branch")
9238 (set (attr "length")
9239 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9240 (const_int 6) (const_int 14)))])
9245 (define_expand "doloop_end"
9246 [(use (match_operand 0 "" "")) ; loop pseudo
9247 (use (match_operand 1 "" ""))] ; label
9250 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9251 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9252 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9253 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9254 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9255 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9262 (define_insn_and_split "doloop_si64"
9265 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9267 (label_ref (match_operand 0 "" ""))
9269 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9270 (plus:SI (match_dup 1) (const_int -1)))
9271 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9272 (clobber (reg:CC CC_REGNUM))]
9275 if (which_alternative != 0)
9277 else if (get_attr_length (insn) == 4)
9278 return "brct\t%1,%l0";
9280 return "ahi\t%1,-1\;jgne\t%l0";
9282 "&& reload_completed
9283 && (! REG_P (operands[2])
9284 || ! rtx_equal_p (operands[1], operands[2]))"
9285 [(set (match_dup 3) (match_dup 1))
9286 (parallel [(set (reg:CCAN CC_REGNUM)
9287 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9289 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9290 (set (match_dup 2) (match_dup 3))
9291 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9292 (label_ref (match_dup 0))
9295 [(set_attr "op_type" "RI")
9296 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9297 ; hurt us in the (rare) case of ahi.
9298 (set_attr "z10prop" "z10_super_E1")
9299 (set_attr "type" "branch")
9300 (set (attr "length")
9301 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9302 (const_int 4) (const_int 10)))])
9304 (define_insn_and_split "doloop_si31"
9307 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9309 (label_ref (match_operand 0 "" ""))
9311 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9312 (plus:SI (match_dup 1) (const_int -1)))
9313 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9314 (clobber (reg:CC CC_REGNUM))]
9317 if (which_alternative != 0)
9319 else if (get_attr_length (insn) == 4)
9320 return "brct\t%1,%l0";
9324 "&& reload_completed
9325 && (! REG_P (operands[2])
9326 || ! rtx_equal_p (operands[1], operands[2]))"
9327 [(set (match_dup 3) (match_dup 1))
9328 (parallel [(set (reg:CCAN CC_REGNUM)
9329 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9331 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9332 (set (match_dup 2) (match_dup 3))
9333 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9334 (label_ref (match_dup 0))
9337 [(set_attr "op_type" "RI")
9338 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9339 ; hurt us in the (rare) case of ahi.
9340 (set_attr "z10prop" "z10_super_E1")
9341 (set_attr "type" "branch")
9342 (set (attr "length")
9343 (if_then_else (not (match_test "flag_pic"))
9344 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9345 (const_int 4) (const_int 6))
9346 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9347 (const_int 4) (const_int 8))))])
9349 (define_insn "*doloop_si_long"
9352 (ne (match_operand:SI 1 "register_operand" "d")
9354 (match_operand 0 "address_operand" "ZR")
9356 (set (match_operand:SI 2 "register_operand" "=1")
9357 (plus:SI (match_dup 1) (const_int -1)))
9358 (clobber (match_scratch:SI 3 "=X"))
9359 (clobber (reg:CC CC_REGNUM))]
9362 if (get_attr_op_type (insn) == OP_TYPE_RR)
9363 return "bctr\t%1,%0";
9365 return "bct\t%1,%a0";
9367 [(set (attr "op_type")
9368 (if_then_else (match_operand 0 "register_operand" "")
9369 (const_string "RR") (const_string "RX")))
9370 (set_attr "type" "branch")
9371 (set_attr "atype" "agen")
9372 (set_attr "z10prop" "z10_c")
9373 (set_attr "z196prop" "z196_cracked")])
9375 (define_insn_and_split "doloop_di"
9378 (ne (match_operand:DI 1 "register_operand" "d,d,d")
9380 (label_ref (match_operand 0 "" ""))
9382 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9383 (plus:DI (match_dup 1) (const_int -1)))
9384 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9385 (clobber (reg:CC CC_REGNUM))]
9388 if (which_alternative != 0)
9390 else if (get_attr_length (insn) == 4)
9391 return "brctg\t%1,%l0";
9393 return "aghi\t%1,-1\;jgne\t%l0";
9395 "&& reload_completed
9396 && (! REG_P (operands[2])
9397 || ! rtx_equal_p (operands[1], operands[2]))"
9398 [(set (match_dup 3) (match_dup 1))
9399 (parallel [(set (reg:CCAN CC_REGNUM)
9400 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9402 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9403 (set (match_dup 2) (match_dup 3))
9404 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9405 (label_ref (match_dup 0))
9408 [(set_attr "op_type" "RI")
9409 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9410 ; hurt us in the (rare) case of ahi.
9411 (set_attr "z10prop" "z10_super_E1")
9412 (set_attr "type" "branch")
9413 (set (attr "length")
9414 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9415 (const_int 4) (const_int 10)))])
9418 ;;- Unconditional jump instructions.
9422 ; jump instruction pattern(s).
9425 (define_expand "jump"
9426 [(match_operand 0 "" "")]
9428 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9430 (define_insn "*jump64"
9431 [(set (pc) (label_ref (match_operand 0 "" "")))]
9434 if (get_attr_length (insn) == 4)
9439 [(set_attr "op_type" "RI")
9440 (set_attr "type" "branch")
9441 (set (attr "length")
9442 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9443 (const_int 4) (const_int 6)))])
9445 (define_insn "*jump31"
9446 [(set (pc) (label_ref (match_operand 0 "" "")))]
9449 gcc_assert (get_attr_length (insn) == 4);
9452 [(set_attr "op_type" "RI")
9453 (set_attr "type" "branch")
9454 (set (attr "length")
9455 (if_then_else (not (match_test "flag_pic"))
9456 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9457 (const_int 4) (const_int 6))
9458 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9459 (const_int 4) (const_int 8))))])
9462 ; indirect-jump instruction pattern(s).
9465 (define_insn "indirect_jump"
9466 [(set (pc) (match_operand 0 "address_operand" "ZR"))]
9469 if (get_attr_op_type (insn) == OP_TYPE_RR)
9474 [(set (attr "op_type")
9475 (if_then_else (match_operand 0 "register_operand" "")
9476 (const_string "RR") (const_string "RX")))
9477 (set_attr "type" "branch")
9478 (set_attr "atype" "agen")])
9481 ; casesi instruction pattern(s).
9484 (define_insn "casesi_jump"
9485 [(set (pc) (match_operand 0 "address_operand" "ZR"))
9486 (use (label_ref (match_operand 1 "" "")))]
9489 if (get_attr_op_type (insn) == OP_TYPE_RR)
9494 [(set (attr "op_type")
9495 (if_then_else (match_operand 0 "register_operand" "")
9496 (const_string "RR") (const_string "RX")))
9497 (set_attr "type" "branch")
9498 (set_attr "atype" "agen")])
9500 (define_expand "casesi"
9501 [(match_operand:SI 0 "general_operand" "")
9502 (match_operand:SI 1 "general_operand" "")
9503 (match_operand:SI 2 "general_operand" "")
9504 (label_ref (match_operand 3 "" ""))
9505 (label_ref (match_operand 4 "" ""))]
9508 rtx index = gen_reg_rtx (SImode);
9509 rtx base = gen_reg_rtx (Pmode);
9510 rtx target = gen_reg_rtx (Pmode);
9512 emit_move_insn (index, operands[0]);
9513 emit_insn (gen_subsi3 (index, index, operands[1]));
9514 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9517 if (Pmode != SImode)
9518 index = convert_to_mode (Pmode, index, 1);
9519 if (GET_CODE (index) != REG)
9520 index = copy_to_mode_reg (Pmode, index);
9523 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9525 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9527 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9529 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9530 emit_move_insn (target, index);
9533 target = gen_rtx_PLUS (Pmode, base, target);
9534 emit_jump_insn (gen_casesi_jump (target, operands[3]));
9541 ;;- Jump to subroutine.
9546 ; untyped call instruction pattern(s).
9549 ;; Call subroutine returning any type.
9550 (define_expand "untyped_call"
9551 [(parallel [(call (match_operand 0 "" "")
9553 (match_operand 1 "" "")
9554 (match_operand 2 "" "")])]
9559 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9561 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9563 rtx set = XVECEXP (operands[2], 0, i);
9564 emit_move_insn (SET_DEST (set), SET_SRC (set));
9567 /* The optimizer does not know that the call sets the function value
9568 registers we stored in the result block. We avoid problems by
9569 claiming that all hard registers are used and clobbered at this
9571 emit_insn (gen_blockage ());
9576 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9577 ;; all of memory. This blocks insns from being moved across this point.
9579 (define_insn "blockage"
9580 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9583 [(set_attr "type" "none")
9584 (set_attr "length" "0")])
9590 (define_expand "sibcall"
9591 [(call (match_operand 0 "" "")
9592 (match_operand 1 "" ""))]
9595 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9599 (define_insn "*sibcall_br"
9600 [(call (mem:QI (reg SIBCALL_REGNUM))
9601 (match_operand 0 "const_int_operand" "n"))]
9602 "SIBLING_CALL_P (insn)
9603 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9605 [(set_attr "op_type" "RR")
9606 (set_attr "type" "branch")
9607 (set_attr "atype" "agen")])
9609 (define_insn "*sibcall_brc"
9610 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9611 (match_operand 1 "const_int_operand" "n"))]
9612 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9614 [(set_attr "op_type" "RI")
9615 (set_attr "type" "branch")])
9617 (define_insn "*sibcall_brcl"
9618 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9619 (match_operand 1 "const_int_operand" "n"))]
9620 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9622 [(set_attr "op_type" "RIL")
9623 (set_attr "type" "branch")])
9626 ; sibcall_value patterns
9629 (define_expand "sibcall_value"
9630 [(set (match_operand 0 "" "")
9631 (call (match_operand 1 "" "")
9632 (match_operand 2 "" "")))]
9635 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9639 (define_insn "*sibcall_value_br"
9640 [(set (match_operand 0 "" "")
9641 (call (mem:QI (reg SIBCALL_REGNUM))
9642 (match_operand 1 "const_int_operand" "n")))]
9643 "SIBLING_CALL_P (insn)
9644 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9646 [(set_attr "op_type" "RR")
9647 (set_attr "type" "branch")
9648 (set_attr "atype" "agen")])
9650 (define_insn "*sibcall_value_brc"
9651 [(set (match_operand 0 "" "")
9652 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9653 (match_operand 2 "const_int_operand" "n")))]
9654 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9656 [(set_attr "op_type" "RI")
9657 (set_attr "type" "branch")])
9659 (define_insn "*sibcall_value_brcl"
9660 [(set (match_operand 0 "" "")
9661 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9662 (match_operand 2 "const_int_operand" "n")))]
9663 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9665 [(set_attr "op_type" "RIL")
9666 (set_attr "type" "branch")])
9670 ; call instruction pattern(s).
9673 (define_expand "call"
9674 [(call (match_operand 0 "" "")
9675 (match_operand 1 "" ""))
9676 (use (match_operand 2 "" ""))]
9679 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9680 gen_rtx_REG (Pmode, RETURN_REGNUM));
9684 (define_insn "*bras"
9685 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9686 (match_operand 1 "const_int_operand" "n"))
9687 (clobber (match_operand 2 "register_operand" "=r"))]
9688 "!SIBLING_CALL_P (insn)
9689 && TARGET_SMALL_EXEC
9690 && GET_MODE (operands[2]) == Pmode"
9692 [(set_attr "op_type" "RI")
9693 (set_attr "type" "jsr")
9694 (set_attr "z196prop" "z196_cracked")])
9696 (define_insn "*brasl"
9697 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9698 (match_operand 1 "const_int_operand" "n"))
9699 (clobber (match_operand 2 "register_operand" "=r"))]
9700 "!SIBLING_CALL_P (insn)
9702 && GET_MODE (operands[2]) == Pmode"
9704 [(set_attr "op_type" "RIL")
9705 (set_attr "type" "jsr")
9706 (set_attr "z196prop" "z196_cracked")])
9708 (define_insn "*basr"
9709 [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
9710 (match_operand 1 "const_int_operand" "n"))
9711 (clobber (match_operand 2 "register_operand" "=r"))]
9712 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9714 if (get_attr_op_type (insn) == OP_TYPE_RR)
9715 return "basr\t%2,%0";
9717 return "bas\t%2,%a0";
9719 [(set (attr "op_type")
9720 (if_then_else (match_operand 0 "register_operand" "")
9721 (const_string "RR") (const_string "RX")))
9722 (set_attr "type" "jsr")
9723 (set_attr "atype" "agen")
9724 (set_attr "z196prop" "z196_cracked")])
9727 ; call_value instruction pattern(s).
9730 (define_expand "call_value"
9731 [(set (match_operand 0 "" "")
9732 (call (match_operand 1 "" "")
9733 (match_operand 2 "" "")))
9734 (use (match_operand 3 "" ""))]
9737 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9738 gen_rtx_REG (Pmode, RETURN_REGNUM));
9742 (define_insn "*bras_r"
9743 [(set (match_operand 0 "" "")
9744 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9745 (match_operand:SI 2 "const_int_operand" "n")))
9746 (clobber (match_operand 3 "register_operand" "=r"))]
9747 "!SIBLING_CALL_P (insn)
9748 && TARGET_SMALL_EXEC
9749 && GET_MODE (operands[3]) == Pmode"
9751 [(set_attr "op_type" "RI")
9752 (set_attr "type" "jsr")
9753 (set_attr "z196prop" "z196_cracked")])
9755 (define_insn "*brasl_r"
9756 [(set (match_operand 0 "" "")
9757 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9758 (match_operand 2 "const_int_operand" "n")))
9759 (clobber (match_operand 3 "register_operand" "=r"))]
9760 "!SIBLING_CALL_P (insn)
9762 && GET_MODE (operands[3]) == Pmode"
9764 [(set_attr "op_type" "RIL")
9765 (set_attr "type" "jsr")
9766 (set_attr "z196prop" "z196_cracked")])
9768 (define_insn "*basr_r"
9769 [(set (match_operand 0 "" "")
9770 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9771 (match_operand 2 "const_int_operand" "n")))
9772 (clobber (match_operand 3 "register_operand" "=r"))]
9773 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9775 if (get_attr_op_type (insn) == OP_TYPE_RR)
9776 return "basr\t%3,%1";
9778 return "bas\t%3,%a1";
9780 [(set (attr "op_type")
9781 (if_then_else (match_operand 1 "register_operand" "")
9782 (const_string "RR") (const_string "RX")))
9783 (set_attr "type" "jsr")
9784 (set_attr "atype" "agen")
9785 (set_attr "z196prop" "z196_cracked")])
9788 ;;- Thread-local storage support.
9791 (define_expand "get_thread_pointer<mode>"
9792 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9796 (define_expand "set_thread_pointer<mode>"
9797 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9798 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9802 (define_insn "*set_tp"
9803 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9806 [(set_attr "type" "none")
9807 (set_attr "length" "0")])
9809 (define_insn "*tls_load_64"
9810 [(set (match_operand:DI 0 "register_operand" "=d")
9811 (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
9812 (match_operand:DI 2 "" "")]
9816 [(set_attr "op_type" "RXE")
9817 (set_attr "z10prop" "z10_fwd_A3")])
9819 (define_insn "*tls_load_31"
9820 [(set (match_operand:SI 0 "register_operand" "=d,d")
9821 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9822 (match_operand:SI 2 "" "")]
9828 [(set_attr "op_type" "RX,RXY")
9829 (set_attr "type" "load")
9830 (set_attr "cpu_facility" "*,longdisp")
9831 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9833 (define_insn "*bras_tls"
9834 [(set (match_operand 0 "" "")
9835 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9836 (match_operand 2 "const_int_operand" "n")))
9837 (clobber (match_operand 3 "register_operand" "=r"))
9838 (use (match_operand 4 "" ""))]
9839 "!SIBLING_CALL_P (insn)
9840 && TARGET_SMALL_EXEC
9841 && GET_MODE (operands[3]) == Pmode"
9843 [(set_attr "op_type" "RI")
9844 (set_attr "type" "jsr")
9845 (set_attr "z196prop" "z196_cracked")])
9847 (define_insn "*brasl_tls"
9848 [(set (match_operand 0 "" "")
9849 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9850 (match_operand 2 "const_int_operand" "n")))
9851 (clobber (match_operand 3 "register_operand" "=r"))
9852 (use (match_operand 4 "" ""))]
9853 "!SIBLING_CALL_P (insn)
9855 && GET_MODE (operands[3]) == Pmode"
9857 [(set_attr "op_type" "RIL")
9858 (set_attr "type" "jsr")
9859 (set_attr "z196prop" "z196_cracked")])
9861 (define_insn "*basr_tls"
9862 [(set (match_operand 0 "" "")
9863 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9864 (match_operand 2 "const_int_operand" "n")))
9865 (clobber (match_operand 3 "register_operand" "=r"))
9866 (use (match_operand 4 "" ""))]
9867 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9869 if (get_attr_op_type (insn) == OP_TYPE_RR)
9870 return "basr\t%3,%1%J4";
9872 return "bas\t%3,%a1%J4";
9874 [(set (attr "op_type")
9875 (if_then_else (match_operand 1 "register_operand" "")
9876 (const_string "RR") (const_string "RX")))
9877 (set_attr "type" "jsr")
9878 (set_attr "atype" "agen")
9879 (set_attr "z196prop" "z196_cracked")])
9882 ;;- Atomic operations
9886 ; memory barrier patterns.
9889 (define_expand "mem_signal_fence"
9890 [(match_operand:SI 0 "const_int_operand")] ;; model
9893 /* The s390 memory model is strong enough not to require any
9894 barrier in order to synchronize a thread with itself. */
9898 (define_expand "mem_thread_fence"
9899 [(match_operand:SI 0 "const_int_operand")] ;; model
9902 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9903 enough not to require barriers of any kind. */
9904 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9906 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9907 MEM_VOLATILE_P (mem) = 1;
9908 emit_insn (gen_mem_thread_fence_1 (mem));
9913 ; Although bcr is superscalar on Z10, this variant will never
9914 ; become part of an execution group.
9915 ; With z196 we can make use of the fast-BCR-serialization facility.
9916 ; This allows for a slightly faster sync which is sufficient for our
9918 (define_insn "mem_thread_fence_1"
9919 [(set (match_operand:BLK 0 "" "")
9920 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9928 [(set_attr "op_type" "RR")
9929 (set_attr "mnemonic" "bcr_flush")
9930 (set_attr "z196prop" "z196_alone")])
9933 ; atomic load/store operations
9936 ; Atomic loads need not examine the memory model at all.
9937 (define_expand "atomic_load<mode>"
9938 [(match_operand:DINT 0 "register_operand") ;; output
9939 (match_operand:DINT 1 "memory_operand") ;; memory
9940 (match_operand:SI 2 "const_int_operand")] ;; model
9943 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9946 if (<MODE>mode == TImode)
9947 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9948 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9949 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9951 emit_move_insn (operands[0], operands[1]);
9955 ; Different from movdi_31 in that we want no splitters.
9956 (define_insn "atomic_loaddi_1"
9957 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9958 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9966 [(set_attr "op_type" "RS,RSY,RS,RSY")
9967 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
9968 (set_attr "type" "lm,lm,floaddf,floaddf")])
9970 (define_insn "atomic_loadti_1"
9971 [(set (match_operand:TI 0 "register_operand" "=r")
9972 (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
9976 [(set_attr "op_type" "RXY")
9977 (set_attr "type" "other")])
9979 ; Atomic stores must(?) enforce sequential consistency.
9980 (define_expand "atomic_store<mode>"
9981 [(match_operand:DINT 0 "memory_operand") ;; memory
9982 (match_operand:DINT 1 "register_operand") ;; input
9983 (match_operand:SI 2 "const_int_operand")] ;; model
9986 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9988 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9991 if (<MODE>mode == TImode)
9992 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9993 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9994 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9996 emit_move_insn (operands[0], operands[1]);
9997 if (is_mm_seq_cst (model))
9998 emit_insn (gen_mem_thread_fence (operands[2]));
10002 ; Different from movdi_31 in that we want no splitters.
10003 (define_insn "atomic_storedi_1"
10004 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
10005 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
10013 [(set_attr "op_type" "RS,RSY,RS,RSY")
10014 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
10015 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
10017 (define_insn "atomic_storeti_1"
10018 [(set (match_operand:TI 0 "memory_operand" "=T")
10019 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
10023 [(set_attr "op_type" "RXY")
10024 (set_attr "type" "other")])
10027 ; compare and swap patterns.
10030 (define_expand "atomic_compare_and_swap<mode>"
10031 [(match_operand:SI 0 "register_operand") ;; bool success output
10032 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
10033 (match_operand:DGPR 2 "memory_operand") ;; memory
10034 (match_operand:DGPR 3 "register_operand") ;; expected intput
10035 (match_operand:DGPR 4 "register_operand") ;; newval intput
10036 (match_operand:SI 5 "const_int_operand") ;; is_weak
10037 (match_operand:SI 6 "const_int_operand") ;; success model
10038 (match_operand:SI 7 "const_int_operand")] ;; failure model
10041 rtx cc, cmp, output = operands[1];
10043 if (!register_operand (output, <MODE>mode))
10044 output = gen_reg_rtx (<MODE>mode);
10046 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
10049 emit_insn (gen_atomic_compare_and_swap<mode>_internal
10050 (output, operands[2], operands[3], operands[4]));
10052 /* We deliberately accept non-register operands in the predicate
10053 to ensure the write back to the output operand happens *before*
10054 the store-flags code below. This makes it easier for combine
10055 to merge the store-flags code with a potential test-and-branch
10056 pattern following (immediately!) afterwards. */
10057 if (output != operands[1])
10058 emit_move_insn (operands[1], output);
10060 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
10061 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
10062 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
10066 (define_expand "atomic_compare_and_swap<mode>"
10067 [(match_operand:SI 0 "register_operand") ;; bool success output
10068 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
10069 (match_operand:HQI 2 "memory_operand") ;; memory
10070 (match_operand:HQI 3 "general_operand") ;; expected intput
10071 (match_operand:HQI 4 "general_operand") ;; newval intput
10072 (match_operand:SI 5 "const_int_operand") ;; is_weak
10073 (match_operand:SI 6 "const_int_operand") ;; success model
10074 (match_operand:SI 7 "const_int_operand")] ;; failure model
10077 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
10078 operands[3], operands[4], INTVAL (operands[5]));
10082 (define_expand "atomic_compare_and_swap<mode>_internal"
10084 [(set (match_operand:DGPR 0 "register_operand")
10085 (match_operand:DGPR 1 "memory_operand"))
10087 (unspec_volatile:DGPR
10089 (match_operand:DGPR 2 "register_operand")
10090 (match_operand:DGPR 3 "register_operand")]
10092 (set (reg:CCZ1 CC_REGNUM)
10093 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
10097 (define_insn "*atomic_compare_and_swap<mode>_1"
10098 [(set (match_operand:TDI 0 "register_operand" "=r")
10099 (match_operand:TDI 1 "memory_operand" "+S"))
10101 (unspec_volatile:TDI
10103 (match_operand:TDI 2 "register_operand" "0")
10104 (match_operand:TDI 3 "register_operand" "r")]
10106 (set (reg:CCZ1 CC_REGNUM)
10107 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10109 "c<td>sg\t%0,%3,%S1"
10110 [(set_attr "op_type" "RSY")
10111 (set_attr "type" "sem")])
10114 (define_insn "*atomic_compare_and_swapdi_2"
10115 [(set (match_operand:DI 0 "register_operand" "=r,r")
10116 (match_operand:DI 1 "memory_operand" "+Q,S"))
10118 (unspec_volatile:DI
10120 (match_operand:DI 2 "register_operand" "0,0")
10121 (match_operand:DI 3 "register_operand" "r,r")]
10123 (set (reg:CCZ1 CC_REGNUM)
10124 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10129 [(set_attr "op_type" "RS,RSY")
10130 (set_attr "cpu_facility" "*,longdisp")
10131 (set_attr "type" "sem")])
10134 (define_insn "*atomic_compare_and_swapsi_3"
10135 [(set (match_operand:SI 0 "register_operand" "=r,r")
10136 (match_operand:SI 1 "memory_operand" "+Q,S"))
10138 (unspec_volatile:SI
10140 (match_operand:SI 2 "register_operand" "0,0")
10141 (match_operand:SI 3 "register_operand" "r,r")]
10143 (set (reg:CCZ1 CC_REGNUM)
10144 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10149 [(set_attr "op_type" "RS,RSY")
10150 (set_attr "cpu_facility" "*,longdisp")
10151 (set_attr "type" "sem")])
10154 ; Other atomic instruction patterns.
10157 ; z196 load and add, xor, or and and instructions
10159 (define_expand "atomic_fetch_<atomic><mode>"
10160 [(match_operand:GPR 0 "register_operand") ;; val out
10162 (match_operand:GPR 1 "memory_operand") ;; memory
10163 (match_operand:GPR 2 "register_operand")) ;; val in
10164 (match_operand:SI 3 "const_int_operand")] ;; model
10167 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
10170 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
10171 (operands[0], operands[1], operands[2]));
10175 ; lan, lang, lao, laog, lax, laxg, laa, laag
10176 (define_insn "atomic_fetch_<atomic><mode>_iaf"
10177 [(set (match_operand:GPR 0 "register_operand" "=d")
10178 (match_operand:GPR 1 "memory_operand" "+S"))
10180 (unspec_volatile:GPR
10181 [(ATOMIC_Z196:GPR (match_dup 1)
10182 (match_operand:GPR 2 "general_operand" "d"))]
10183 UNSPECV_ATOMIC_OP))
10184 (clobber (reg:CC CC_REGNUM))]
10186 "la<noxa><g>\t%0,%2,%1"
10187 [(set_attr "op_type" "RSY")
10188 (set_attr "type" "sem")])
10190 ;; For SImode and larger, the optabs.c code will do just fine in
10191 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
10192 ;; better by expanding our own loop.
10194 (define_expand "atomic_<atomic><mode>"
10196 (match_operand:HQI 0 "memory_operand") ;; memory
10197 (match_operand:HQI 1 "general_operand")) ;; val in
10198 (match_operand:SI 2 "const_int_operand")] ;; model
10201 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10202 operands[1], false);
10206 (define_expand "atomic_fetch_<atomic><mode>"
10207 [(match_operand:HQI 0 "register_operand") ;; val out
10209 (match_operand:HQI 1 "memory_operand") ;; memory
10210 (match_operand:HQI 2 "general_operand")) ;; val in
10211 (match_operand:SI 3 "const_int_operand")] ;; model
10214 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10215 operands[2], false);
10219 (define_expand "atomic_<atomic>_fetch<mode>"
10220 [(match_operand:HQI 0 "register_operand") ;; val out
10222 (match_operand:HQI 1 "memory_operand") ;; memory
10223 (match_operand:HQI 2 "general_operand")) ;; val in
10224 (match_operand:SI 3 "const_int_operand")] ;; model
10227 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10228 operands[2], true);
10232 (define_expand "atomic_exchange<mode>"
10233 [(match_operand:HQI 0 "register_operand") ;; val out
10234 (match_operand:HQI 1 "memory_operand") ;; memory
10235 (match_operand:HQI 2 "general_operand") ;; val in
10236 (match_operand:SI 3 "const_int_operand")] ;; model
10239 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10240 operands[2], false);
10245 ;;- Miscellaneous instructions.
10249 ; allocate stack instruction pattern(s).
10252 (define_expand "allocate_stack"
10253 [(match_operand 0 "general_operand" "")
10254 (match_operand 1 "general_operand" "")]
10257 rtx temp = gen_reg_rtx (Pmode);
10259 emit_move_insn (temp, s390_back_chain_rtx ());
10260 anti_adjust_stack (operands[1]);
10261 emit_move_insn (s390_back_chain_rtx (), temp);
10263 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10269 ; setjmp instruction pattern.
10272 (define_expand "builtin_setjmp_receiver"
10273 [(match_operand 0 "" "")]
10276 emit_insn (s390_load_got ());
10277 emit_use (pic_offset_table_rtx);
10281 ;; These patterns say how to save and restore the stack pointer. We need not
10282 ;; save the stack pointer at function level since we are careful to
10283 ;; preserve the backchain. At block level, we have to restore the backchain
10284 ;; when we restore the stack pointer.
10286 ;; For nonlocal gotos, we must save both the stack pointer and its
10287 ;; backchain and restore both. Note that in the nonlocal case, the
10288 ;; save area is a memory location.
10290 (define_expand "save_stack_function"
10291 [(match_operand 0 "general_operand" "")
10292 (match_operand 1 "general_operand" "")]
10296 (define_expand "restore_stack_function"
10297 [(match_operand 0 "general_operand" "")
10298 (match_operand 1 "general_operand" "")]
10302 (define_expand "restore_stack_block"
10303 [(match_operand 0 "register_operand" "")
10304 (match_operand 1 "register_operand" "")]
10307 rtx temp = gen_reg_rtx (Pmode);
10309 emit_move_insn (temp, s390_back_chain_rtx ());
10310 emit_move_insn (operands[0], operands[1]);
10311 emit_move_insn (s390_back_chain_rtx (), temp);
10316 (define_expand "save_stack_nonlocal"
10317 [(match_operand 0 "memory_operand" "")
10318 (match_operand 1 "register_operand" "")]
10321 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10323 /* Copy the backchain to the first word, sp to the second and the
10324 literal pool base to the third. */
10326 rtx save_bc = adjust_address (operands[0], Pmode, 0);
10327 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10328 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10330 if (TARGET_BACKCHAIN)
10331 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10333 emit_move_insn (save_sp, operands[1]);
10334 emit_move_insn (save_bp, base);
10339 (define_expand "restore_stack_nonlocal"
10340 [(match_operand 0 "register_operand" "")
10341 (match_operand 1 "memory_operand" "")]
10344 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10345 rtx temp = NULL_RTX;
10347 /* Restore the backchain from the first word, sp from the second and the
10348 literal pool base from the third. */
10350 rtx save_bc = adjust_address (operands[1], Pmode, 0);
10351 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10352 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10354 if (TARGET_BACKCHAIN)
10355 temp = force_reg (Pmode, save_bc);
10357 emit_move_insn (base, save_bp);
10358 emit_move_insn (operands[0], save_sp);
10361 emit_move_insn (s390_back_chain_rtx (), temp);
10367 (define_expand "exception_receiver"
10371 s390_set_has_landing_pad_p (true);
10376 ; nop instruction pattern(s).
10383 [(set_attr "op_type" "RR")
10384 (set_attr "z10prop" "z10_fr_E1")])
10386 (define_insn "nop1"
10390 [(set_attr "op_type" "RR")])
10392 ;;- Undeletable nops (used for hotpatching)
10394 (define_insn "nop_2_byte"
10395 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10398 [(set_attr "op_type" "RR")])
10400 (define_insn "nop_4_byte"
10401 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10404 [(set_attr "op_type" "RX")])
10406 (define_insn "nop_6_byte"
10407 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10410 [(set_attr "op_type" "RIL")])
10414 ; Special literal pool access instruction pattern(s).
10417 (define_insn "*pool_entry"
10418 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10419 UNSPECV_POOL_ENTRY)]
10422 machine_mode mode = GET_MODE (PATTERN (insn));
10423 unsigned int align = GET_MODE_BITSIZE (mode);
10424 s390_output_pool_entry (operands[0], mode, align);
10427 [(set (attr "length")
10428 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10430 (define_insn "pool_align"
10431 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10432 UNSPECV_POOL_ALIGN)]
10435 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10437 (define_insn "pool_section_start"
10438 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10441 switch_to_section (targetm.asm_out.function_rodata_section
10442 (current_function_decl));
10445 [(set_attr "length" "0")])
10447 (define_insn "pool_section_end"
10448 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10451 switch_to_section (current_function_section ());
10454 [(set_attr "length" "0")])
10456 (define_insn "main_base_31_small"
10457 [(set (match_operand 0 "register_operand" "=a")
10458 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10459 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10461 [(set_attr "op_type" "RR")
10462 (set_attr "type" "la")
10463 (set_attr "z196prop" "z196_cracked")])
10465 (define_insn "main_base_31_large"
10466 [(set (match_operand 0 "register_operand" "=a")
10467 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10468 (set (pc) (label_ref (match_operand 2 "" "")))]
10469 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10471 [(set_attr "op_type" "RI")
10472 (set_attr "z196prop" "z196_cracked")])
10474 (define_insn "main_base_64"
10475 [(set (match_operand 0 "register_operand" "=a")
10476 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10477 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10479 [(set_attr "op_type" "RIL")
10480 (set_attr "type" "larl")
10481 (set_attr "z10prop" "z10_fwd_A1")])
10483 (define_insn "main_pool"
10484 [(set (match_operand 0 "register_operand" "=a")
10485 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10486 "GET_MODE (operands[0]) == Pmode"
10488 gcc_unreachable ();
10490 [(set (attr "type")
10491 (if_then_else (match_test "TARGET_CPU_ZARCH")
10492 (const_string "larl") (const_string "la")))])
10494 (define_insn "reload_base_31"
10495 [(set (match_operand 0 "register_operand" "=a")
10496 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10497 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10498 "basr\t%0,0\;la\t%0,%1-.(%0)"
10499 [(set_attr "length" "6")
10500 (set_attr "type" "la")
10501 (set_attr "z196prop" "z196_cracked")])
10503 (define_insn "reload_base_64"
10504 [(set (match_operand 0 "register_operand" "=a")
10505 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10506 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10508 [(set_attr "op_type" "RIL")
10509 (set_attr "type" "larl")
10510 (set_attr "z10prop" "z10_fwd_A1")])
10512 (define_insn "pool"
10513 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10516 gcc_unreachable ();
10518 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10521 ;; Insns related to generating the function prologue and epilogue.
10525 (define_expand "prologue"
10526 [(use (const_int 0))]
10528 "s390_emit_prologue (); DONE;")
10530 (define_expand "epilogue"
10531 [(use (const_int 1))]
10533 "s390_emit_epilogue (false); DONE;")
10535 (define_expand "sibcall_epilogue"
10536 [(use (const_int 0))]
10538 "s390_emit_epilogue (true); DONE;")
10540 ;; A direct return instruction, without using an epilogue.
10541 (define_insn "<code>"
10543 "s390_can_use_<code>_insn ()"
10545 [(set_attr "op_type" "RR")
10546 (set_attr "type" "jsr")
10547 (set_attr "atype" "agen")])
10549 (define_insn "*return"
10551 (use (match_operand 0 "register_operand" "a"))]
10552 "GET_MODE (operands[0]) == Pmode"
10554 [(set_attr "op_type" "RR")
10555 (set_attr "type" "jsr")
10556 (set_attr "atype" "agen")])
10559 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10560 ;; pointer. This is used for compatibility.
10562 (define_expand "ptr_extend"
10563 [(set (match_operand:DI 0 "register_operand" "=r")
10564 (match_operand:SI 1 "register_operand" "r"))]
10567 emit_insn (gen_anddi3 (operands[0],
10568 gen_lowpart (DImode, operands[1]),
10569 GEN_INT (0x7fffffff)));
10573 ;; Instruction definition to expand eh_return macro to support
10574 ;; swapping in special linkage return addresses.
10576 (define_expand "eh_return"
10577 [(use (match_operand 0 "register_operand" ""))]
10580 s390_emit_tpf_eh_return (operands[0]);
10585 ; Stack Protector Patterns
10588 (define_expand "stack_protect_set"
10589 [(set (match_operand 0 "memory_operand" "")
10590 (match_operand 1 "memory_operand" ""))]
10593 #ifdef TARGET_THREAD_SSP_OFFSET
10595 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10596 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10599 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10601 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10606 (define_insn "stack_protect_set<mode>"
10607 [(set (match_operand:DSI 0 "memory_operand" "=Q")
10608 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10610 "mvc\t%O0(%G0,%R0),%S1"
10611 [(set_attr "op_type" "SS")])
10613 (define_expand "stack_protect_test"
10614 [(set (reg:CC CC_REGNUM)
10615 (compare (match_operand 0 "memory_operand" "")
10616 (match_operand 1 "memory_operand" "")))
10617 (match_operand 2 "" "")]
10621 #ifdef TARGET_THREAD_SSP_OFFSET
10623 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10624 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10627 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10629 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10631 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10632 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10633 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10637 (define_insn "stack_protect_test<mode>"
10638 [(set (reg:CCZ CC_REGNUM)
10639 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10640 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10642 "clc\t%O0(%G0,%R0),%S1"
10643 [(set_attr "op_type" "SS")])
10645 ; This is used in s390_emit_prologue in order to prevent insns
10646 ; adjusting the stack pointer to be moved over insns writing stack
10647 ; slots using a copy of the stack pointer in a different register.
10648 (define_insn "stack_tie"
10649 [(set (match_operand:BLK 0 "memory_operand" "+m")
10650 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10653 [(set_attr "length" "0")])
10656 (define_insn "stack_restore_from_fpr"
10657 [(set (reg:DI STACK_REGNUM)
10658 (match_operand:DI 0 "register_operand" "f"))
10659 (clobber (mem:BLK (scratch)))]
10662 [(set_attr "op_type" "RRE")])
10665 ; Data prefetch patterns
10668 (define_insn "prefetch"
10669 [(prefetch (match_operand 0 "address_operand" "ZT,X")
10670 (match_operand:SI 1 "const_int_operand" " n,n")
10671 (match_operand:SI 2 "const_int_operand" " n,n"))]
10674 switch (which_alternative)
10677 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10679 if (larl_operand (operands[0], Pmode))
10680 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10684 /* This might be reached for symbolic operands with an odd
10685 addend. We simply omit the prefetch for such rare cases. */
10690 [(set_attr "type" "load,larl")
10691 (set_attr "op_type" "RXY,RIL")
10692 (set_attr "z10prop" "z10_super")
10693 (set_attr "z196prop" "z196_alone")])
10697 ; Byte swap instructions
10700 ; FIXME: There is also mvcin but we cannot use it since src and target
10702 ; lrvr, lrv, strv, lrvgr, lrvg, strvg
10703 (define_insn "bswap<mode>2"
10704 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
10705 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
10711 [(set_attr "type" "*,load,store")
10712 (set_attr "op_type" "RRE,RXY,RXY")
10713 (set_attr "z10prop" "z10_super")])
10715 (define_insn "bswaphi2"
10716 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
10717 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
10723 [(set_attr "type" "*,load,store")
10724 (set_attr "op_type" "RRE,RXY,RXY")
10725 (set_attr "z10prop" "z10_super")])
10728 [(set (match_operand:HI 0 "register_operand" "")
10729 (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10731 [(set (match_dup 2) (bswap:SI (match_dup 3)))
10732 (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10734 operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10735 operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10740 ; Population count instruction
10743 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10744 ; portions and stores the result in the corresponding bytes in op0.
10745 (define_insn "*popcount<mode>"
10746 [(set (match_operand:INT 0 "register_operand" "=d")
10747 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10748 (clobber (reg:CC CC_REGNUM))]
10751 [(set_attr "op_type" "RRE")])
10753 (define_expand "popcountdi2"
10755 (parallel [(set (match_operand:DI 0 "register_operand" "")
10756 (unspec:DI [(match_operand:DI 1 "register_operand")]
10758 (clobber (reg:CC CC_REGNUM))])
10759 ; sllg op2, op0, 32
10760 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10762 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10763 (clobber (reg:CC CC_REGNUM))])
10764 ; sllg op2, op0, 16
10766 (ashift:DI (match_dup 0) (const_int 16)))
10768 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10769 (clobber (reg:CC CC_REGNUM))])
10771 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10773 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10774 (clobber (reg:CC CC_REGNUM))])
10775 ; srlg op0, op0, 56
10776 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10777 "TARGET_Z196 && TARGET_64BIT"
10778 "operands[2] = gen_reg_rtx (DImode);")
10780 (define_expand "popcountsi2"
10782 (parallel [(set (match_operand:SI 0 "register_operand" "")
10783 (unspec:SI [(match_operand:SI 1 "register_operand")]
10785 (clobber (reg:CC CC_REGNUM))])
10786 ; sllk op2, op0, 16
10788 (ashift:SI (match_dup 0) (const_int 16)))
10790 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10791 (clobber (reg:CC CC_REGNUM))])
10793 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10795 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10796 (clobber (reg:CC CC_REGNUM))])
10798 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10800 "operands[2] = gen_reg_rtx (SImode);")
10802 (define_expand "popcounthi2"
10804 (parallel [(set (match_operand:HI 0 "register_operand" "")
10805 (unspec:HI [(match_operand:HI 1 "register_operand")]
10807 (clobber (reg:CC CC_REGNUM))])
10810 (ashift:SI (match_dup 0) (const_int 8)))
10812 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10813 (clobber (reg:CC CC_REGNUM))])
10815 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10817 "operands[2] = gen_reg_rtx (SImode);")
10819 (define_expand "popcountqi2"
10821 (parallel [(set (match_operand:QI 0 "register_operand" "")
10822 (unspec:QI [(match_operand:QI 1 "register_operand")]
10824 (clobber (reg:CC CC_REGNUM))])]
10829 ;;- Copy sign instructions
10832 (define_insn "copysign<mode>3"
10833 [(set (match_operand:FP 0 "register_operand" "=f")
10834 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10835 (match_operand:FP 2 "register_operand" "f")]
10839 [(set_attr "op_type" "RRF")
10840 (set_attr "type" "fsimp<mode>")])
10844 ;;- Transactional execution instructions
10847 ; This splitter helps combine to make use of CC directly when
10848 ; comparing the integer result of a tbegin builtin with a constant.
10849 ; The unspec is already removed by canonicalize_comparison. So this
10850 ; splitters only job is to turn the PARALLEL into separate insns
10851 ; again. Unfortunately this only works with the very first cc/int
10852 ; compare since combine is not able to deal with data flow across
10853 ; basic block boundaries.
10855 ; It needs to be an insn pattern as well since combine does not apply
10856 ; the splitter directly. Combine would only use it if it actually
10857 ; would reduce the number of instructions.
10858 (define_insn_and_split "*ccraw_to_int"
10861 (match_operator 0 "s390_eqne_operator"
10862 [(reg:CCRAW CC_REGNUM)
10863 (match_operand 1 "const_int_operand" "")])
10864 (label_ref (match_operand 2 "" ""))
10866 (set (match_operand:SI 3 "register_operand" "=d")
10867 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10871 [(set (match_dup 3)
10872 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10874 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10875 (label_ref (match_dup 2))
10879 ; Non-constrained transaction begin
10881 (define_expand "tbegin"
10882 [(match_operand:SI 0 "register_operand" "")
10883 (match_operand:BLK 1 "memory_operand" "")]
10886 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10890 (define_expand "tbegin_nofloat"
10891 [(match_operand:SI 0 "register_operand" "")
10892 (match_operand:BLK 1 "memory_operand" "")]
10895 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10899 (define_expand "tbegin_retry"
10900 [(match_operand:SI 0 "register_operand" "")
10901 (match_operand:BLK 1 "memory_operand" "")
10902 (match_operand:SI 2 "general_operand" "")]
10905 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10909 (define_expand "tbegin_retry_nofloat"
10910 [(match_operand:SI 0 "register_operand" "")
10911 (match_operand:BLK 1 "memory_operand" "")
10912 (match_operand:SI 2 "general_operand" "")]
10915 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10919 ; Clobber VRs since they don't get restored
10920 (define_insn "tbegin_1_z13"
10921 [(set (reg:CCRAW CC_REGNUM)
10922 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10924 (set (match_operand:BLK 1 "memory_operand" "=Q")
10925 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10926 (clobber (reg:TI 16)) (clobber (reg:TI 38))
10927 (clobber (reg:TI 17)) (clobber (reg:TI 39))
10928 (clobber (reg:TI 18)) (clobber (reg:TI 40))
10929 (clobber (reg:TI 19)) (clobber (reg:TI 41))
10930 (clobber (reg:TI 20)) (clobber (reg:TI 42))
10931 (clobber (reg:TI 21)) (clobber (reg:TI 43))
10932 (clobber (reg:TI 22)) (clobber (reg:TI 44))
10933 (clobber (reg:TI 23)) (clobber (reg:TI 45))
10934 (clobber (reg:TI 24)) (clobber (reg:TI 46))
10935 (clobber (reg:TI 25)) (clobber (reg:TI 47))
10936 (clobber (reg:TI 26)) (clobber (reg:TI 48))
10937 (clobber (reg:TI 27)) (clobber (reg:TI 49))
10938 (clobber (reg:TI 28)) (clobber (reg:TI 50))
10939 (clobber (reg:TI 29)) (clobber (reg:TI 51))
10940 (clobber (reg:TI 30)) (clobber (reg:TI 52))
10941 (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10942 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10943 ; not supposed to be used for immediates (see genpreds.c).
10944 "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10946 [(set_attr "op_type" "SIL")])
10948 (define_insn "tbegin_1"
10949 [(set (reg:CCRAW CC_REGNUM)
10950 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10952 (set (match_operand:BLK 1 "memory_operand" "=Q")
10953 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10954 (clobber (reg:DF 16))
10955 (clobber (reg:DF 17))
10956 (clobber (reg:DF 18))
10957 (clobber (reg:DF 19))
10958 (clobber (reg:DF 20))
10959 (clobber (reg:DF 21))
10960 (clobber (reg:DF 22))
10961 (clobber (reg:DF 23))
10962 (clobber (reg:DF 24))
10963 (clobber (reg:DF 25))
10964 (clobber (reg:DF 26))
10965 (clobber (reg:DF 27))
10966 (clobber (reg:DF 28))
10967 (clobber (reg:DF 29))
10968 (clobber (reg:DF 30))
10969 (clobber (reg:DF 31))]
10970 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10971 ; not supposed to be used for immediates (see genpreds.c).
10972 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10974 [(set_attr "op_type" "SIL")])
10976 ; Same as above but without the FPR clobbers
10977 (define_insn "tbegin_nofloat_1"
10978 [(set (reg:CCRAW CC_REGNUM)
10979 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10981 (set (match_operand:BLK 1 "memory_operand" "=Q")
10982 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10983 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10985 [(set_attr "op_type" "SIL")])
10988 ; Constrained transaction begin
10990 (define_expand "tbeginc"
10991 [(set (reg:CCRAW CC_REGNUM)
10992 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10997 (define_insn "*tbeginc_1"
10998 [(set (reg:CCRAW CC_REGNUM)
10999 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
11001 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11003 [(set_attr "op_type" "SIL")])
11007 (define_expand "tend"
11008 [(set (reg:CCRAW CC_REGNUM)
11009 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
11010 (set (match_operand:SI 0 "register_operand" "")
11011 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
11015 (define_insn "*tend_1"
11016 [(set (reg:CCRAW CC_REGNUM)
11017 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
11020 [(set_attr "op_type" "S")])
11022 ; Transaction abort
11024 (define_expand "tabort"
11025 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
11027 "TARGET_HTM && operands != NULL"
11029 if (CONST_INT_P (operands[0])
11030 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
11032 error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
11033 ". Values in range 0 through 255 are reserved.",
11034 INTVAL (operands[0]));
11039 (define_insn "*tabort_1"
11040 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
11042 "TARGET_HTM && operands != NULL"
11044 [(set_attr "op_type" "S")])
11046 (define_insn "*tabort_1_plus"
11047 [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a")
11048 (match_operand:SI 1 "const_int_operand" "J"))]
11050 "TARGET_HTM && operands != NULL
11051 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
11053 [(set_attr "op_type" "S")])
11055 ; Transaction extract nesting depth
11057 (define_insn "etnd"
11058 [(set (match_operand:SI 0 "register_operand" "=d")
11059 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
11062 [(set_attr "op_type" "RRE")])
11064 ; Non-transactional store
11066 (define_insn "ntstg"
11067 [(set (match_operand:DI 0 "memory_operand" "=T")
11068 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
11072 [(set_attr "op_type" "RXY")])
11074 ; Transaction perform processor assist
11076 (define_expand "tx_assist"
11077 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
11078 (reg:SI GPR0_REGNUM)
11084 (define_insn "*ppa"
11085 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
11086 (match_operand:SI 1 "register_operand" "d")
11087 (match_operand 2 "const_int_operand" "I")]
11089 "TARGET_HTM && INTVAL (operands[2]) < 16"
11091 [(set_attr "op_type" "RRF")])
11094 ; Set and get floating point control register
11096 (define_insn "sfpc"
11097 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
11099 "TARGET_HARD_FLOAT"
11102 (define_insn "efpc"
11103 [(set (match_operand:SI 0 "register_operand" "=d")
11104 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
11105 "TARGET_HARD_FLOAT"
11109 ; Load count to block boundary
11111 (define_insn "lcbb"
11112 [(set (match_operand:SI 0 "register_operand" "=d")
11113 (unspec:SI [(match_operand 1 "address_operand" "ZR")
11114 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
11115 (clobber (reg:CC CC_REGNUM))]
11118 [(set_attr "op_type" "VRX")])
11120 ; Handle -fsplit-stack.
11122 (define_expand "split_stack_prologue"
11126 s390_expand_split_stack_prologue ();
11130 ;; If there are operand 0 bytes available on the stack, jump to
11133 (define_expand "split_stack_space_check"
11134 [(set (pc) (if_then_else
11135 (ltu (minus (reg 15)
11136 (match_operand 0 "register_operand"))
11137 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
11138 (label_ref (match_operand 1))
11142 /* Offset from thread pointer to __private_ss. */
11143 int psso = TARGET_64BIT ? 0x38 : 0x20;
11144 rtx tp = s390_get_thread_pointer ();
11145 rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
11146 rtx reg = gen_reg_rtx (Pmode);
11149 emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
11151 emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
11152 cc = s390_emit_compare (GT, reg, guard);
11153 s390_emit_jump (operands[1], cc);
11158 ;; __morestack parameter block for split stack prologue. Parameters are:
11159 ;; parameter block label, label to be called by __morestack, frame size,
11160 ;; stack parameter size.
11162 (define_insn "split_stack_data"
11163 [(unspec_volatile [(match_operand 0 "" "X")
11164 (match_operand 1 "" "X")
11165 (match_operand 2 "const_int_operand" "X")
11166 (match_operand 3 "const_int_operand" "X")]
11167 UNSPECV_SPLIT_STACK_DATA)]
11170 switch_to_section (targetm.asm_out.function_rodata_section
11171 (current_function_decl));
11174 output_asm_insn (".align\t8", operands);
11176 output_asm_insn (".align\t4", operands);
11177 (*targetm.asm_out.internal_label) (asm_out_file, "L",
11178 CODE_LABEL_NUMBER (operands[0]));
11181 output_asm_insn (".quad\t%2", operands);
11182 output_asm_insn (".quad\t%3", operands);
11183 output_asm_insn (".quad\t%1-%0", operands);
11187 output_asm_insn (".long\t%2", operands);
11188 output_asm_insn (".long\t%3", operands);
11189 output_asm_insn (".long\t%1-%0", operands);
11192 switch_to_section (current_function_section ());
11195 [(set_attr "length" "0")])
11198 ;; A jg with minimal fuss for use in split stack prologue.
11200 (define_expand "split_stack_call"
11201 [(match_operand 0 "bras_sym_operand" "X")
11202 (match_operand 1 "" "")]
11206 emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
11208 emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
11212 (define_insn "split_stack_call_<mode>"
11213 [(set (pc) (label_ref (match_operand 1 "" "")))
11214 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11216 UNSPECV_SPLIT_STACK_CALL))]
11219 [(set_attr "op_type" "RIL")
11220 (set_attr "type" "branch")])
11222 ;; Also a conditional one.
11224 (define_expand "split_stack_cond_call"
11225 [(match_operand 0 "bras_sym_operand" "X")
11226 (match_operand 1 "" "")
11227 (match_operand 2 "" "")]
11231 emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
11233 emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
11237 (define_insn "split_stack_cond_call_<mode>"
11240 (match_operand 1 "" "")
11241 (label_ref (match_operand 2 "" ""))
11243 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11245 UNSPECV_SPLIT_STACK_CALL))]
11248 [(set_attr "op_type" "RIL")
11249 (set_attr "type" "branch")])
11251 (define_insn "osc_break"
11252 [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)]
11255 [(set_attr "op_type" "RR")])