gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999-2016 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com) and
   5 ;;                 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify it under
  10 ;; the terms of the GNU General Public License as published by the Free
  11 ;; Software Foundation; either version 3, or (at your option) any later
  12 ;; version.
  13
  14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 ;; for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;;
  24 ;; See constraints.md for a description of constraints specific to s390.
  25 ;;
  26
  27 ;; Special formats used for outputting 390 instructions.
  28 ;;
  29 ;;     %C: print opcode suffix for branch condition.
  30 ;;     %D: print opcode suffix for inverse branch condition.
  31 ;;     %J: print tls_load/tls_gdcall/tls_ldcall suffix
  32 ;;     %G: print the size of the operand in bytes.
  33 ;;     %O: print only the displacement of a memory reference.
  34 ;;     %R: print only the base register of a memory reference.
  35 ;;     %S: print S-type memory reference (base+displacement).
  36 ;;     %N: print the second word of a DImode operand.
  37 ;;     %M: print the second word of a TImode operand.
  38 ;;     %Y: print shift count operand.
  39 ;;
  40 ;;     %b: print integer X as if it's an unsigned byte.
  41 ;;     %c: print integer X as if it's an signed byte.
  42 ;;     %x: print integer X as if it's an unsigned halfword.
  43 ;;     %h: print integer X as if it's a signed halfword.
  44 ;;     %i: print the first nonzero HImode part of X.
  45 ;;     %j: print the first HImode part unequal to -1 of X.
  46 ;;     %k: print the first nonzero SImode part of X.
  47 ;;     %m: print the first SImode part unequal to -1 of X.
  48 ;;     %o: print integer X as if it's an unsigned 32bit word.
  49 ;;
  50 ;; We have a special constraint for pattern matching.
  51 ;;
  52 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  53 ;;
  54
  55 ;;
  56 ;; UNSPEC usage
  57 ;;
  58
  59 (define_c_enum "unspec" [
  60    ; Miscellaneous
  61    UNSPEC_ROUND
  62    UNSPEC_ICM
  63    UNSPEC_TIE
  64
  65    ; Convert CC into a str comparison result and copy it into an
  66    ; integer register
  67    ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
  68    UNSPEC_STRCMPCC_TO_INT
  69
  70    ; Copy CC as is into the lower 2 bits of an integer register
  71    UNSPEC_CC_TO_INT
  72
  73    ; The right hand side of an setmem
  74    UNSPEC_REPLICATE_BYTE
  75
  76    ; GOT/PLT and lt-relative accesses
  77    UNSPEC_LTREL_OFFSET
  78    UNSPEC_LTREL_BASE
  79    UNSPEC_POOL_OFFSET
  80    UNSPEC_GOTENT
  81    UNSPEC_GOT
  82    UNSPEC_GOTOFF
  83    UNSPEC_PLT
  84    UNSPEC_PLTOFF
  85
  86    ; Literal pool
  87    UNSPEC_RELOAD_BASE
  88    UNSPEC_MAIN_BASE
  89    UNSPEC_LTREF
  90    UNSPEC_INSN
  91    UNSPEC_EXECUTE
  92
  93    ; Atomic Support
  94    UNSPEC_MB
  95    UNSPEC_MOVA
  96
  97    ; TLS relocation specifiers
  98    UNSPEC_TLSGD
  99    UNSPEC_TLSLDM
 100    UNSPEC_NTPOFF
 101    UNSPEC_DTPOFF
 102    UNSPEC_GOTNTPOFF
 103    UNSPEC_INDNTPOFF
 104
 105    ; TLS support
 106    UNSPEC_TLSLDM_NTPOFF
 107    UNSPEC_TLS_LOAD
 108
 109    ; String Functions
 110    UNSPEC_SRST
 111    UNSPEC_MVST
 112
 113    ; Stack Smashing Protector
 114    UNSPEC_SP_SET
 115    UNSPEC_SP_TEST
 116
 117    ; Split stack support
 118    UNSPEC_STACK_CHECK
 119
 120    ; Test Data Class (TDC)
 121    UNSPEC_TDC_INSN
 122
 123    ; Population Count
 124    UNSPEC_POPCNT
 125    UNSPEC_COPYSIGN
 126
 127    ; Load FP Integer
 128    UNSPEC_FPINT_FLOOR
 129    UNSPEC_FPINT_BTRUNC
 130    UNSPEC_FPINT_ROUND
 131    UNSPEC_FPINT_CEIL
 132    UNSPEC_FPINT_NEARBYINT
 133    UNSPEC_FPINT_RINT
 134
 135    UNSPEC_LCBB
 136
 137    ; Vector
 138    UNSPEC_VEC_SMULT_HI
 139    UNSPEC_VEC_UMULT_HI
 140    UNSPEC_VEC_SMULT_LO
 141    UNSPEC_VEC_SMULT_EVEN
 142    UNSPEC_VEC_UMULT_EVEN
 143    UNSPEC_VEC_SMULT_ODD
 144    UNSPEC_VEC_UMULT_ODD
 145
 146    UNSPEC_VEC_VMAL
 147    UNSPEC_VEC_VMAH
 148    UNSPEC_VEC_VMALH
 149    UNSPEC_VEC_VMAE
 150    UNSPEC_VEC_VMALE
 151    UNSPEC_VEC_VMAO
 152    UNSPEC_VEC_VMALO
 153
 154    UNSPEC_VEC_GATHER
 155    UNSPEC_VEC_EXTRACT
 156    UNSPEC_VEC_INSERT_AND_ZERO
 157    UNSPEC_VEC_LOAD_BNDRY
 158    UNSPEC_VEC_LOAD_LEN
 159    UNSPEC_VEC_MERGEH
 160    UNSPEC_VEC_MERGEL
 161    UNSPEC_VEC_PACK
 162    UNSPEC_VEC_PACK_SATURATE
 163    UNSPEC_VEC_PACK_SATURATE_CC
 164    UNSPEC_VEC_PACK_SATURATE_GENCC
 165    UNSPEC_VEC_PACK_UNSIGNED_SATURATE
 166    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
 167    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
 168    UNSPEC_VEC_PERM
 169    UNSPEC_VEC_PERMI
 170    UNSPEC_VEC_EXTEND
 171    UNSPEC_VEC_STORE_LEN
 172    UNSPEC_VEC_UNPACKH
 173    UNSPEC_VEC_UNPACKH_L
 174    UNSPEC_VEC_UNPACKL
 175    UNSPEC_VEC_UNPACKL_L
 176    UNSPEC_VEC_ADDC
 177    UNSPEC_VEC_ADDE_U128
 178    UNSPEC_VEC_ADDEC_U128
 179    UNSPEC_VEC_AVG
 180    UNSPEC_VEC_AVGU
 181    UNSPEC_VEC_CHECKSUM
 182    UNSPEC_VEC_GFMSUM
 183    UNSPEC_VEC_GFMSUM_128
 184    UNSPEC_VEC_GFMSUM_ACCUM
 185    UNSPEC_VEC_GFMSUM_ACCUM_128
 186    UNSPEC_VEC_SET
 187
 188    UNSPEC_VEC_VSUMG
 189    UNSPEC_VEC_VSUMQ
 190    UNSPEC_VEC_VSUM
 191    UNSPEC_VEC_RL_MASK
 192    UNSPEC_VEC_SLL
 193    UNSPEC_VEC_SLB
 194    UNSPEC_VEC_SLDB
 195    UNSPEC_VEC_SRAL
 196    UNSPEC_VEC_SRAB
 197    UNSPEC_VEC_SRL
 198    UNSPEC_VEC_SRLB
 199
 200    UNSPEC_VEC_SUBC
 201    UNSPEC_VEC_SUBE_U128
 202    UNSPEC_VEC_SUBEC_U128
 203
 204    UNSPEC_VEC_TEST_MASK
 205
 206    UNSPEC_VEC_VFAE
 207    UNSPEC_VEC_VFAECC
 208
 209    UNSPEC_VEC_VFEE
 210    UNSPEC_VEC_VFEECC
 211    UNSPEC_VEC_VFENE
 212    UNSPEC_VEC_VFENECC
 213
 214    UNSPEC_VEC_VISTR
 215    UNSPEC_VEC_VISTRCC
 216
 217    UNSPEC_VEC_VSTRC
 218    UNSPEC_VEC_VSTRCCC
 219
 220    UNSPEC_VEC_VCDGB
 221    UNSPEC_VEC_VCDLGB
 222
 223    UNSPEC_VEC_VCGDB
 224    UNSPEC_VEC_VCLGDB
 225
 226    UNSPEC_VEC_VFIDB
 227
 228    UNSPEC_VEC_VLDEB
 229    UNSPEC_VEC_VLEDB
 230
 231    UNSPEC_VEC_VFTCIDB
 232    UNSPEC_VEC_VFTCIDBCC
 233 ])
 234
 235 ;;
 236 ;; UNSPEC_VOLATILE usage
 237 ;;
 238
 239 (define_c_enum "unspecv" [
 240    ; Blockage
 241    UNSPECV_BLOCKAGE
 242
 243    ; TPF Support
 244    UNSPECV_TPF_PROLOGUE
 245    UNSPECV_TPF_EPILOGUE
 246
 247    ; Literal pool
 248    UNSPECV_POOL
 249    UNSPECV_POOL_SECTION
 250    UNSPECV_POOL_ALIGN
 251    UNSPECV_POOL_ENTRY
 252    UNSPECV_MAIN_POOL
 253
 254    ; TLS support
 255    UNSPECV_SET_TP
 256
 257    ; Atomic Support
 258    UNSPECV_CAS
 259    UNSPECV_ATOMIC_OP
 260
 261    ; Hotpatching (unremovable NOPs)
 262    UNSPECV_NOP_2_BYTE
 263    UNSPECV_NOP_4_BYTE
 264    UNSPECV_NOP_6_BYTE
 265
 266    ; Transactional Execution support
 267    UNSPECV_TBEGIN
 268    UNSPECV_TBEGIN_TDB
 269    UNSPECV_TBEGINC
 270    UNSPECV_TEND
 271    UNSPECV_TABORT
 272    UNSPECV_ETND
 273    UNSPECV_NTSTG
 274    UNSPECV_PPA
 275
 276    ; Set and get floating point control register
 277    UNSPECV_SFPC
 278    UNSPECV_EFPC
 279
 280    ; Split stack support
 281    UNSPECV_SPLIT_STACK_CALL
 282    UNSPECV_SPLIT_STACK_DATA
 283   ])
 284
 285 ;;
 286 ;; Registers
 287 ;;
 288
 289 ; Registers with special meaning
 290
 291 (define_constants
 292   [
 293    ; Sibling call register.
 294    (SIBCALL_REGNUM               1)
 295    ; Literal pool base register.
 296    (BASE_REGNUM                 13)
 297    ; Return address register.
 298    (RETURN_REGNUM               14)
 299    ; Stack pointer register.
 300    (STACK_REGNUM                15)
 301    ; Condition code register.
 302    (CC_REGNUM                   33)
 303    ; Thread local storage pointer register.
 304    (TP_REGNUM                   36)
 305   ])
 306
 307 ; Hardware register names
 308
 309 (define_constants
 310   [
 311    ; General purpose registers
 312    (GPR0_REGNUM                  0)
 313    (GPR1_REGNUM                  1)
 314    (GPR2_REGNUM                  2)
 315    (GPR6_REGNUM                  6)
 316    ; Floating point registers.
 317    (FPR0_REGNUM                 16)
 318    (FPR1_REGNUM                 20)
 319    (FPR2_REGNUM                 17)
 320    (FPR3_REGNUM                 21)
 321    (FPR4_REGNUM                 18)
 322    (FPR5_REGNUM                 22)
 323    (FPR6_REGNUM                 19)
 324    (FPR7_REGNUM                 23)
 325    (FPR8_REGNUM                 24)
 326    (FPR9_REGNUM                 28)
 327    (FPR10_REGNUM                25)
 328    (FPR11_REGNUM                29)
 329    (FPR12_REGNUM                26)
 330    (FPR13_REGNUM                30)
 331    (FPR14_REGNUM                27)
 332    (FPR15_REGNUM                31)
 333    (VR0_REGNUM                  16)
 334    (VR16_REGNUM                 38)
 335    (VR23_REGNUM                 45)
 336    (VR24_REGNUM                 46)
 337    (VR31_REGNUM                 53)
 338   ])
 339
 340 ; Rounding modes for binary floating point numbers
 341 (define_constants
 342   [(BFP_RND_CURRENT                 0)
 343    (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
 344    (BFP_RND_PREP_FOR_SHORT_PREC     3)
 345    (BFP_RND_NEAREST_TIE_TO_EVEN     4)
 346    (BFP_RND_TOWARD_0                5)
 347    (BFP_RND_TOWARD_INF              6)
 348    (BFP_RND_TOWARD_MINF             7)])
 349
 350 ; Rounding modes for decimal floating point numbers
 351 ; 1-7 were introduced with the floating point extension facility
 352 ; available with z196
 353 ; With these rounding modes (1-7) a quantum exception might occur
 354 ; which is suppressed for the other modes.
 355 (define_constants
 356   [(DFP_RND_CURRENT                          0)
 357    (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
 358    (DFP_RND_CURRENT_QUANTEXC                 2)
 359    (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC     3)
 360    (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC     4)
 361    (DFP_RND_TOWARD_0_QUANTEXC                5)
 362    (DFP_RND_TOWARD_INF_QUANTEXC              6)
 363    (DFP_RND_TOWARD_MINF_QUANTEXC             7)
 364    (DFP_RND_NEAREST_TIE_TO_EVEN              8)
 365    (DFP_RND_TOWARD_0                         9)
 366    (DFP_RND_TOWARD_INF                      10)
 367    (DFP_RND_TOWARD_MINF                     11)
 368    (DFP_RND_NEAREST_TIE_AWAY_FROM_0         12)
 369    (DFP_RND_NEAREST_TIE_TO_0                13)
 370    (DFP_RND_AWAY_FROM_0                     14)
 371    (DFP_RND_PREP_FOR_SHORT_PREC             15)])
 372
 373 ;;
 374 ;; PFPO GPR0 argument format
 375 ;;
 376
 377 (define_constants
 378   [
 379    ; PFPO operation type
 380    (PFPO_CONVERT          0x1000000)
 381    ; PFPO operand types
 382    (PFPO_OP_TYPE_SF             0x5)
 383    (PFPO_OP_TYPE_DF             0x6)
 384    (PFPO_OP_TYPE_TF             0x7)
 385    (PFPO_OP_TYPE_SD             0x8)
 386    (PFPO_OP_TYPE_DD             0x9)
 387    (PFPO_OP_TYPE_TD             0xa)
 388    ; Bitposition of operand types
 389    (PFPO_OP0_TYPE_SHIFT          16)
 390    (PFPO_OP1_TYPE_SHIFT           8)
 391   ])
 392
 393 ; Immediate operands for tbegin and tbeginc
 394 (define_constants [(TBEGIN_MASK  65292)]) ; 0xff0c
 395 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
 396
 397 ;; Instruction operand type as used in the Principles of Operation.
 398 ;; Used to determine defaults for length and other attribute values.
 399
 400 (define_attr "op_type"
 401   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
 402   (const_string "NN"))
 403
 404 ;; Instruction type attribute used for scheduling.
 405
 406 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
 407                      cs,vs,store,sem,idiv,
 408                      imulhi,imulsi,imuldi,
 409                      branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
 410                      floadtf,floaddf,floadsf,fstoredf,fstoresf,
 411                      fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
 412                      ftoi,fsqrttf,fsqrtdf,fsqrtsf,
 413                      fmadddf,fmaddsf,
 414                      ftrunctf,ftruncdf, ftruncsd, ftruncdd,
 415                      itoftf, itofdf, itofsf, itofdd, itoftd,
 416                      fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
 417                      fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
 418                      ftoidfp, other"
 419   (cond [(eq_attr "op_type" "NN")  (const_string "other")
 420          (eq_attr "op_type" "SS")  (const_string "cs")]
 421     (const_string "integer")))
 422
 423 ;; Another attribute used for scheduling purposes:
 424 ;;   agen: Instruction uses the address generation unit
 425 ;;   reg: Instruction does not use the agen unit
 426
 427 (define_attr "atype" "agen,reg"
 428   (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
 429                 (const_string "reg")
 430                 (const_string "agen")))
 431
 432 ;; Properties concerning Z10 execution grouping and value forwarding.
 433 ;; z10_super: instruction is superscalar.
 434 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
 435 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
 436 ;;   target register.  It can forward this value to a second instruction that reads
 437 ;;   the same register if that second instruction is issued in the same group.
 438 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
 439 ;;   instruction in the S pipe writes to the register, then the T instruction
 440 ;;   can immediately read the new value.
 441 ;; z10_fr: union of Z10_fwd and z10_rec.
 442 ;; z10_c: second operand of instruction is a register and read with complemented bits.
 443 ;;
 444 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
 445
 446
 447 (define_attr "z10prop" "none,
 448                         z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
 449                         z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
 450                         z10_rec,
 451                         z10_fr, z10_fr_A3, z10_fr_E1,
 452                         z10_c"
 453              (const_string "none"))
 454
 455 ;; Properties concerning Z196 decoding
 456 ;; z196_alone: must group alone
 457 ;; z196_end: ends a group
 458 ;; z196_cracked: instruction is cracked or expanded
 459 (define_attr "z196prop" "none,
 460                          z196_alone, z196_ends,
 461                          z196_cracked"
 462              (const_string "none"))
 463
 464 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
 465
 466 ;; Length in bytes.
 467
 468 (define_attr "length" ""
 469   (cond [(eq_attr "op_type" "E,RR")                       (const_int 2)
 470          (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF")  (const_int 4)]
 471     (const_int 6)))
 472
 473
 474 ;; Processor type.  This attribute must exactly match the processor_type
 475 ;; enumeration in s390.h.  The current machine description does not
 476 ;; distinguish between g5 and g6, but there are differences between the two
 477 ;; CPUs could in theory be modeled.
 478
 479 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
 480   (const (symbol_ref "s390_tune_attr")))
 481
 482 (define_attr "cpu_facility"
 483   "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec,z13"
 484   (const_string "standard"))
 485
 486 (define_attr "enabled" ""
 487   (cond [(eq_attr "cpu_facility" "standard")
 488          (const_int 1)
 489
 490          (and (eq_attr "cpu_facility" "ieee")
 491               (match_test "TARGET_CPU_IEEE_FLOAT"))
 492          (const_int 1)
 493
 494          (and (eq_attr "cpu_facility" "zarch")
 495               (match_test "TARGET_ZARCH"))
 496          (const_int 1)
 497
 498          (and (eq_attr "cpu_facility" "longdisp")
 499               (match_test "TARGET_LONG_DISPLACEMENT"))
 500          (const_int 1)
 501
 502          (and (eq_attr "cpu_facility" "extimm")
 503               (match_test "TARGET_EXTIMM"))
 504          (const_int 1)
 505
 506          (and (eq_attr "cpu_facility" "dfp")
 507               (match_test "TARGET_DFP"))
 508          (const_int 1)
 509
 510          (and (eq_attr "cpu_facility" "cpu_zarch")
 511               (match_test "TARGET_CPU_ZARCH"))
 512          (const_int 1)
 513
 514          (and (eq_attr "cpu_facility" "z10")
 515               (match_test "TARGET_Z10"))
 516          (const_int 1)
 517
 518          (and (eq_attr "cpu_facility" "z196")
 519               (match_test "TARGET_Z196"))
 520          (const_int 1)
 521
 522          (and (eq_attr "cpu_facility" "zEC12")
 523               (match_test "TARGET_ZEC12"))
 524          (const_int 1)
 525
 526          (and (eq_attr "cpu_facility" "vec")
 527               (match_test "TARGET_VX"))
 528          (const_int 1)
 529
 530          (and (eq_attr "cpu_facility" "z13")
 531               (match_test "TARGET_Z13"))
 532          (const_int 1)
 533          ]
 534         (const_int 0)))
 535
 536 ;; Pipeline description for z900.  For lack of anything better,
 537 ;; this description is also used for the g5 and g6.
 538 (include "2064.md")
 539
 540 ;; Pipeline description for z990, z9-109 and z9-ec.
 541 (include "2084.md")
 542
 543 ;; Pipeline description for z10
 544 (include "2097.md")
 545
 546 ;; Pipeline description for z196
 547 (include "2817.md")
 548
 549 ;; Pipeline description for zEC12
 550 (include "2827.md")
 551
 552 ;; Pipeline description for z13
 553 (include "2964.md")
 554
 555 ;; Predicates
 556 (include "predicates.md")
 557
 558 ;; Constraint definitions
 559 (include "constraints.md")
 560
 561 ;; Other includes
 562 (include "tpf.md")
 563
 564 ;; Iterators
 565
 566 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
 567
 568 ;; These mode iterators allow floating point patterns to be generated from the
 569 ;; same template.
 570 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
 571                               (SD "TARGET_HARD_DFP")])
 572 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
 573 (define_mode_iterator BFP [TF DF SF])
 574 (define_mode_iterator DFP [TD DD])
 575 (define_mode_iterator DFP_ALL [TD DD SD])
 576 (define_mode_iterator DSF [DF SF])
 577 (define_mode_iterator SD_SF [SF SD])
 578 (define_mode_iterator DD_DF [DF DD])
 579 (define_mode_iterator TD_TF [TF TD])
 580
 581 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
 582 ;; from the same template.
 583 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
 584 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
 585 (define_mode_iterator DSI [DI SI])
 586 (define_mode_iterator TDI [TI DI])
 587
 588 ;; These mode iterators allow :P to be used for patterns that operate on
 589 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 590 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
 591
 592 ;; These macros refer to the actual word_mode of the configuration.
 593 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
 594 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
 595 (define_mode_iterator W  [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
 596
 597 ;; Used by the umul pattern to express modes having half the size.
 598 (define_mode_attr DWH [(TI "DI") (DI "SI")])
 599 (define_mode_attr dwh [(TI "di") (DI "si")])
 600
 601 ;; This mode iterator allows the QI and HI patterns to be defined from
 602 ;; the same template.
 603 (define_mode_iterator HQI [HI QI])
 604
 605 ;; This mode iterator allows the integer patterns to be defined from the
 606 ;; same template.
 607 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
 608 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
 609
 610 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
 611 ;; the same template.
 612 (define_code_iterator SHIFT [ashift lshiftrt])
 613
 614 ;; This iterator allows r[ox]sbg to be defined with the same template
 615 (define_code_iterator IXOR [ior xor])
 616
 617 ;; This iterator is used to expand the patterns for the nearest
 618 ;; integer functions.
 619 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
 620                             UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
 621                             UNSPEC_FPINT_NEARBYINT])
 622 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
 623                              (UNSPEC_FPINT_BTRUNC "btrunc")
 624                              (UNSPEC_FPINT_ROUND "round")
 625                              (UNSPEC_FPINT_CEIL "ceil")
 626                              (UNSPEC_FPINT_NEARBYINT "nearbyint")])
 627 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
 628                                      (UNSPEC_FPINT_BTRUNC "5")
 629                                      (UNSPEC_FPINT_ROUND "1")
 630                                      (UNSPEC_FPINT_CEIL "6")
 631                                      (UNSPEC_FPINT_NEARBYINT "0")])
 632
 633 ;; This iterator and attribute allow to combine most atomic operations.
 634 (define_code_iterator ATOMIC [and ior xor plus minus mult])
 635 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
 636 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
 637                           (plus "add") (minus "sub") (mult "nand")])
 638 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
 639
 640 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
 641 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
 642 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
 643
 644 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
 645 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
 646 ;; SDmode.
 647 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
 648
 649 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
 650 ;; Likewise for "<RXe>".
 651 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
 652 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 653
 654 ;; The decimal floating point variants of add, sub, div and mul support 3
 655 ;; fp register operands.  The following attributes allow to merge the bfp and
 656 ;; dfp variants in a single insn definition.
 657
 658 ;; These mode attributes are supposed to be used in the `enabled' insn
 659 ;; attribute to disable certain alternatives for certain modes.
 660 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
 661 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
 662 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
 663 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
 664                         (TD "0") (DD "0") (DD "0")
 665                         (TI "0") (DI "*") (SI "0")])
 666
 667 ;; This attribute is used in the operand constraint list
 668 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
 669 ;; TFmode values are represented by a fp register pair.  Since the
 670 ;; sign bit instructions only handle single source and target fp registers
 671 ;; these instructions can only be used for TFmode values if the source and
 672 ;; target operand uses the same fp register.
 673 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 674
 675 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 676 ;; within instruction mnemonics.
 677 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 678
 679 ;; This attribute is used within instruction mnemonics.  It evaluates to d for dfp
 680 ;; modes and to an empty string for bfp modes.
 681 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
 682
 683 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
 684 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
 685 ;; version only operates on one register.
 686 (define_mode_attr d0 [(DI "d") (SI "0")])
 687
 688 ;; In combination with d0 this allows to combine instructions of which the 31bit
 689 ;; version only operates on one register. The DImode version needs an additional
 690 ;; register for the assembler output.
 691 (define_mode_attr 1 [(DI "%1,") (SI "")])
 692
 693 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
 694 ;; 'ashift' and "srdl" in 'lshiftrt'.
 695 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
 696
 697 ;; In SHIFT templates, this attribute holds the correct standard name for the
 698 ;; pattern itself and the corresponding function calls.
 699 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
 700
 701 ;; This attribute handles differences in the instruction 'type' and will result
 702 ;; in "RRE" for DImode and "RR" for SImode.
 703 (define_mode_attr E [(DI "E") (SI "")])
 704
 705 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
 706 ;; to result in "RXY" for DImode and "RX" for SImode.
 707 (define_mode_attr Y [(DI "Y") (SI "")])
 708
 709 ;; This attribute handles differences in the instruction 'type' and will result
 710 ;; in "RSE" for TImode and "RS" for DImode.
 711 (define_mode_attr TE [(TI "E") (DI "")])
 712
 713 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
 714 ;; and "lcr" in SImode.
 715 (define_mode_attr g [(DI "g") (SI "")])
 716
 717 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
 718 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
 719 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
 720 ;; variant for long displacements.
 721 (define_mode_attr y [(DI "g") (SI "y")])
 722
 723 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
 724 ;; and "cds" in DImode.
 725 (define_mode_attr tg [(TI "g") (DI "")])
 726
 727 ;; In TDI templates, a string like "c<d>sg".
 728 (define_mode_attr td [(TI "d") (DI "")])
 729
 730 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
 731 ;; and "cfdbr" in SImode.
 732 (define_mode_attr gf [(DI "g") (SI "f")])
 733
 734 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
 735 ;; and sllk for SI.  This way it is possible to merge the new z196 SI
 736 ;; 3 operands shift instructions into the existing patterns.
 737 (define_mode_attr gk [(DI "g") (SI "k")])
 738
 739 ;; ICM mask required to load MODE value into the lowest subreg
 740 ;; of a SImode register.
 741 (define_mode_attr icm_lo [(HI "3") (QI "1")])
 742
 743 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
 744 ;; HImode and "llgc" in QImode.
 745 (define_mode_attr hc [(HI "h") (QI "c")])
 746
 747 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
 748 ;; in SImode.
 749 (define_mode_attr DBL [(DI "TI") (SI "DI")])
 750
 751 ;; This attribute expands to DF for TFmode and to DD for TDmode .  It is
 752 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
 753 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
 754
 755 ;; Maximum unsigned integer that fits in MODE.
 756 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 757
 758 ;; Start and end field computations for RISBG et al.
 759 (define_mode_attr bfstart [(DI "s") (SI "t")])
 760 (define_mode_attr bfend   [(DI "e") (SI "f")])
 761
 762 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
 763 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
 764
 765 ;; In place of GET_MODE_SIZE (<MODE>mode)
 766 (define_mode_attr modesize [(DI "8") (SI "4")])
 767
 768 ;; Allow return and simple_return to be defined from a single template.
 769 (define_code_iterator ANY_RETURN [return simple_return])
 770
 771
 772
 773 ; Condition code modes generated by vector fp comparisons.  These will
 774 ; be used also in single element mode.
 775 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
 776 ; Used with VFCMP to expand part of the mnemonic
 777 ; For fp we have a mismatch: eq in the insn name - e in asm
 778 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
 779 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
 780
 781 ;; Subst pattern definitions
 782 (include "subst.md")
 783
 784 (include "vector.md")
 785
 786 ;;
 787 ;;- Compare instructions.
 788 ;;
 789
 790 ; Test-under-Mask instructions
 791
 792 (define_insn "*tmqi_mem"
 793   [(set (reg CC_REGNUM)
 794         (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
 795                          (match_operand:QI 1 "immediate_operand" "n,n"))
 796                  (match_operand:QI 2 "immediate_operand" "n,n")))]
 797   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
 798   "@
 799    tm\t%S0,%b1
 800    tmy\t%S0,%b1"
 801   [(set_attr "op_type" "SI,SIY")
 802    (set_attr "cpu_facility" "*,longdisp")
 803    (set_attr "z10prop" "z10_super,z10_super")])
 804
 805 (define_insn "*tmdi_reg"
 806   [(set (reg CC_REGNUM)
 807         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
 808                          (match_operand:DI 1 "immediate_operand"
 809                                              "N0HD0,N1HD0,N2HD0,N3HD0"))
 810                  (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
 811   "TARGET_ZARCH
 812    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 813    && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
 814   "@
 815    tmhh\t%0,%i1
 816    tmhl\t%0,%i1
 817    tmlh\t%0,%i1
 818    tmll\t%0,%i1"
 819   [(set_attr "op_type" "RI")
 820    (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
 821
 822 (define_insn "*tmsi_reg"
 823   [(set (reg CC_REGNUM)
 824         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
 825                          (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
 826                  (match_operand:SI 2 "immediate_operand" "n,n")))]
 827   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 828    && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
 829   "@
 830    tmh\t%0,%i1
 831    tml\t%0,%i1"
 832   [(set_attr "op_type" "RI")
 833    (set_attr "z10prop" "z10_super,z10_super")])
 834
 835 (define_insn "*tm<mode>_full"
 836   [(set (reg CC_REGNUM)
 837         (compare (match_operand:HQI 0 "register_operand" "d")
 838                  (match_operand:HQI 1 "immediate_operand" "n")))]
 839   "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
 840   "tml\t%0,<max_uint>"
 841   [(set_attr "op_type" "RI")
 842    (set_attr "z10prop" "z10_super")])
 843
 844
 845 ;
 846 ; Load-and-Test instructions
 847 ;
 848
 849 ; tst(di|si) instruction pattern(s).
 850
 851 (define_insn "*tstdi_sign"
 852   [(set (reg CC_REGNUM)
 853         (compare
 854           (ashiftrt:DI
 855             (ashift:DI
 856               (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
 857               (const_int 32)) (const_int 32))
 858           (match_operand:DI 1 "const0_operand" "")))
 859    (set (match_operand:DI 2 "register_operand" "=d,d")
 860         (sign_extend:DI (match_dup 0)))]
 861   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
 862   "ltgfr\t%2,%0
 863    ltgf\t%2,%0"
 864   [(set_attr "op_type"      "RRE,RXY")
 865    (set_attr "cpu_facility" "*,z10")
 866    (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
 867
 868 ; ltr, lt, ltgr, ltg
 869 (define_insn "*tst<mode>_extimm"
 870   [(set (reg CC_REGNUM)
 871         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
 872                  (match_operand:GPR 1 "const0_operand" "")))
 873    (set (match_operand:GPR 2 "register_operand" "=d,d")
 874         (match_dup 0))]
 875   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 876   "@
 877    lt<g>r\t%2,%0
 878    lt<g>\t%2,%0"
 879   [(set_attr "op_type" "RR<E>,RXY")
 880    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
 881
 882 ; ltr, lt, ltgr, ltg
 883 (define_insn "*tst<mode>_cconly_extimm"
 884   [(set (reg CC_REGNUM)
 885         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
 886                  (match_operand:GPR 1 "const0_operand" "")))
 887    (clobber (match_scratch:GPR 2 "=X,d"))]
 888   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 889   "@
 890    lt<g>r\t%0,%0
 891    lt<g>\t%2,%0"
 892   [(set_attr "op_type" "RR<E>,RXY")
 893    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
 894
 895 (define_insn "*tstdi"
 896   [(set (reg CC_REGNUM)
 897         (compare (match_operand:DI 0 "register_operand" "d")
 898                  (match_operand:DI 1 "const0_operand" "")))
 899    (set (match_operand:DI 2 "register_operand" "=d")
 900         (match_dup 0))]
 901   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
 902   "ltgr\t%2,%0"
 903   [(set_attr "op_type" "RRE")
 904    (set_attr "z10prop" "z10_fr_E1")])
 905
 906 (define_insn "*tstsi"
 907   [(set (reg CC_REGNUM)
 908         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 909                  (match_operand:SI 1 "const0_operand" "")))
 910    (set (match_operand:SI 2 "register_operand" "=d,d,d")
 911         (match_dup 0))]
 912   "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
 913   "@
 914    ltr\t%2,%0
 915    icm\t%2,15,%S0
 916    icmy\t%2,15,%S0"
 917   [(set_attr "op_type" "RR,RS,RSY")
 918    (set_attr "cpu_facility" "*,*,longdisp")
 919    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 920
 921 (define_insn "*tstsi_cconly"
 922   [(set (reg CC_REGNUM)
 923         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 924                  (match_operand:SI 1 "const0_operand" "")))
 925    (clobber (match_scratch:SI 2 "=X,d,d"))]
 926   "s390_match_ccmode(insn, CCSmode)"
 927   "@
 928    ltr\t%0,%0
 929    icm\t%2,15,%S0
 930    icmy\t%2,15,%S0"
 931   [(set_attr "op_type" "RR,RS,RSY")
 932    (set_attr "cpu_facility" "*,*,longdisp")
 933    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 934
 935 (define_insn "*tstdi_cconly_31"
 936   [(set (reg CC_REGNUM)
 937         (compare (match_operand:DI 0 "register_operand" "d")
 938                  (match_operand:DI 1 "const0_operand" "")))]
 939   "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
 940   "srda\t%0,0"
 941   [(set_attr "op_type" "RS")
 942    (set_attr "atype"   "reg")])
 943
 944 ; ltr, ltgr
 945 (define_insn "*tst<mode>_cconly2"
 946   [(set (reg CC_REGNUM)
 947         (compare (match_operand:GPR 0 "register_operand" "d")
 948                  (match_operand:GPR 1 "const0_operand" "")))]
 949   "s390_match_ccmode(insn, CCSmode)"
 950   "lt<g>r\t%0,%0"
 951   [(set_attr "op_type" "RR<E>")
 952    (set_attr "z10prop" "z10_fr_E1")])
 953
 954 ; tst(hi|qi) instruction pattern(s).
 955
 956 (define_insn "*tst<mode>CCT"
 957   [(set (reg CC_REGNUM)
 958         (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
 959                  (match_operand:HQI 1 "const0_operand" "")))
 960    (set (match_operand:HQI 2 "register_operand" "=d,d,0")
 961         (match_dup 0))]
 962   "s390_match_ccmode(insn, CCTmode)"
 963   "@
 964    icm\t%2,<icm_lo>,%S0
 965    icmy\t%2,<icm_lo>,%S0
 966    tml\t%0,<max_uint>"
 967   [(set_attr "op_type" "RS,RSY,RI")
 968    (set_attr "cpu_facility" "*,longdisp,*")
 969    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 970
 971 (define_insn "*tsthiCCT_cconly"
 972   [(set (reg CC_REGNUM)
 973         (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
 974                  (match_operand:HI 1 "const0_operand" "")))
 975    (clobber (match_scratch:HI 2 "=d,d,X"))]
 976   "s390_match_ccmode(insn, CCTmode)"
 977   "@
 978    icm\t%2,3,%S0
 979    icmy\t%2,3,%S0
 980    tml\t%0,65535"
 981   [(set_attr "op_type" "RS,RSY,RI")
 982    (set_attr "cpu_facility" "*,longdisp,*")
 983    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 984
 985 (define_insn "*tstqiCCT_cconly"
 986   [(set (reg CC_REGNUM)
 987         (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
 988                  (match_operand:QI 1 "const0_operand" "")))]
 989   "s390_match_ccmode(insn, CCTmode)"
 990   "@
 991    cli\t%S0,0
 992    cliy\t%S0,0
 993    tml\t%0,255"
 994   [(set_attr "op_type" "SI,SIY,RI")
 995    (set_attr "cpu_facility" "*,longdisp,*")
 996    (set_attr "z10prop" "z10_super,z10_super,z10_super")])
 997
 998 (define_insn "*tst<mode>"
 999   [(set (reg CC_REGNUM)
1000         (compare (match_operand:HQI 0 "s_operand" "Q,S")
1001                  (match_operand:HQI 1 "const0_operand" "")))
1002    (set (match_operand:HQI 2 "register_operand" "=d,d")
1003         (match_dup 0))]
1004   "s390_match_ccmode(insn, CCSmode)"
1005   "@
1006    icm\t%2,<icm_lo>,%S0
1007    icmy\t%2,<icm_lo>,%S0"
1008   [(set_attr "op_type" "RS,RSY")
1009    (set_attr "cpu_facility" "*,longdisp")
1010    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1011
1012 (define_insn "*tst<mode>_cconly"
1013   [(set (reg CC_REGNUM)
1014         (compare (match_operand:HQI 0 "s_operand" "Q,S")
1015                  (match_operand:HQI 1 "const0_operand" "")))
1016    (clobber (match_scratch:HQI 2 "=d,d"))]
1017   "s390_match_ccmode(insn, CCSmode)"
1018   "@
1019    icm\t%2,<icm_lo>,%S0
1020    icmy\t%2,<icm_lo>,%S0"
1021   [(set_attr "op_type" "RS,RSY")
1022    (set_attr "cpu_facility" "*,longdisp")
1023    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1024
1025
1026 ; Compare (equality) instructions
1027
1028 (define_insn "*cmpdi_cct"
1029   [(set (reg CC_REGNUM)
1030         (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
1031                  (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
1032   "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
1033   "@
1034    cgr\t%0,%1
1035    cghi\t%0,%h1
1036    cgfi\t%0,%1
1037    cg\t%0,%1
1038    #"
1039   [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
1040    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
1041
1042 (define_insn "*cmpsi_cct"
1043   [(set (reg CC_REGNUM)
1044         (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1045                  (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1046   "s390_match_ccmode (insn, CCTmode)"
1047   "@
1048    cr\t%0,%1
1049    chi\t%0,%h1
1050    cfi\t%0,%1
1051    c\t%0,%1
1052    cy\t%0,%1
1053    #"
1054   [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1055    (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
1056    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1057
1058 ; Compare (signed) instructions
1059
1060 (define_insn "*cmpdi_ccs_sign"
1061   [(set (reg CC_REGNUM)
1062         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1063                                                      "d,T,b"))
1064                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1065   "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1066   "@
1067    cgfr\t%0,%1
1068    cgf\t%0,%1
1069    cgfrl\t%0,%1"
1070   [(set_attr "op_type"      "RRE,RXY,RIL")
1071    (set_attr "z10prop" "z10_c,*,*")
1072    (set_attr "type"         "*,*,larl")])
1073
1074
1075
1076 (define_insn "*cmpsi_ccs_sign"
1077   [(set (reg CC_REGNUM)
1078         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1079                  (match_operand:SI 0 "register_operand" "d,d,d")))]
1080   "s390_match_ccmode(insn, CCSRmode)"
1081   "@
1082    ch\t%0,%1
1083    chy\t%0,%1
1084    chrl\t%0,%1"
1085   [(set_attr "op_type"      "RX,RXY,RIL")
1086    (set_attr "cpu_facility" "*,longdisp,z10")
1087    (set_attr "type"         "*,*,larl")
1088    (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1089
1090 (define_insn "*cmphi_ccs_z10"
1091   [(set (reg CC_REGNUM)
1092         (compare (match_operand:HI 0 "s_operand"         "Q")
1093                  (match_operand:HI 1 "immediate_operand" "K")))]
1094   "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1095   "chhsi\t%0,%1"
1096   [(set_attr "op_type" "SIL")
1097    (set_attr "z196prop" "z196_cracked")])
1098
1099 (define_insn "*cmpdi_ccs_signhi_rl"
1100   [(set (reg CC_REGNUM)
1101         (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
1102                  (match_operand:GPR 0 "register_operand"  "d,d")))]
1103   "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1104   "@
1105    cgh\t%0,%1
1106    cghrl\t%0,%1"
1107   [(set_attr "op_type" "RXY,RIL")
1108    (set_attr "type"    "*,larl")])
1109
1110 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1111 (define_insn "*cmp<mode>_ccs"
1112   [(set (reg CC_REGNUM)
1113         (compare (match_operand:GPR 0 "nonimmediate_operand"
1114                                       "d,d,Q, d,d,d,d")
1115                  (match_operand:GPR 1 "general_operand"
1116                                       "d,K,K,Os,R,T,b")))]
1117   "s390_match_ccmode(insn, CCSmode)"
1118   "@
1119    c<g>r\t%0,%1
1120    c<g>hi\t%0,%h1
1121    c<g>hsi\t%0,%h1
1122    c<g>fi\t%0,%1
1123    c<g>\t%0,%1
1124    c<y>\t%0,%1
1125    c<g>rl\t%0,%1"
1126   [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1127    (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
1128    (set_attr "type" "*,*,*,*,*,*,larl")
1129    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1130
1131
1132 ; Compare (unsigned) instructions
1133
1134 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1135   [(set (reg CC_REGNUM)
1136         (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1137                                           "larl_operand" "X")))
1138                  (match_operand:SI 0 "register_operand" "d")))]
1139   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1140   "clhrl\t%0,%1"
1141   [(set_attr "op_type" "RIL")
1142    (set_attr "type"    "larl")
1143    (set_attr "z10prop" "z10_super")])
1144
1145 ; clhrl, clghrl
1146 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1147   [(set (reg CC_REGNUM)
1148         (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1149                                           "larl_operand" "X")))
1150                  (match_operand:GPR 0 "register_operand" "d")))]
1151   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1152   "cl<g>hrl\t%0,%1"
1153   [(set_attr "op_type" "RIL")
1154    (set_attr "type"    "larl")
1155    (set_attr "z10prop" "z10_super")])
1156
1157 (define_insn "*cmpdi_ccu_zero"
1158   [(set (reg CC_REGNUM)
1159         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1160                                                         "d,T,b"))
1161                  (match_operand:DI 0 "register_operand" "d,d,d")))]
1162   "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1163   "@
1164    clgfr\t%0,%1
1165    clgf\t%0,%1
1166    clgfrl\t%0,%1"
1167   [(set_attr "op_type"      "RRE,RXY,RIL")
1168    (set_attr "cpu_facility" "*,*,z10")
1169    (set_attr "type"         "*,*,larl")
1170    (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1171
1172 (define_insn "*cmpdi_ccu"
1173   [(set (reg CC_REGNUM)
1174         (compare (match_operand:DI 0 "nonimmediate_operand"
1175                                      "d, d,d,Q,d, Q,BQ")
1176                  (match_operand:DI 1 "general_operand"
1177                                      "d,Op,b,D,T,BQ,Q")))]
1178   "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1179   "@
1180    clgr\t%0,%1
1181    clgfi\t%0,%1
1182    clgrl\t%0,%1
1183    clghsi\t%0,%x1
1184    clg\t%0,%1
1185    #
1186    #"
1187   [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1188    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1189    (set_attr "type"         "*,*,larl,*,*,*,*")
1190    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1191
1192 (define_insn "*cmpsi_ccu"
1193   [(set (reg CC_REGNUM)
1194         (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1195                  (match_operand:SI 1 "general_operand"      "d,Os,b,D,R,T,BQ, Q")))]
1196   "s390_match_ccmode (insn, CCUmode)"
1197   "@
1198    clr\t%0,%1
1199    clfi\t%0,%o1
1200    clrl\t%0,%1
1201    clfhsi\t%0,%x1
1202    cl\t%0,%1
1203    cly\t%0,%1
1204    #
1205    #"
1206   [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1207    (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
1208    (set_attr "type"         "*,*,larl,*,*,*,*,*")
1209    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1210
1211 (define_insn "*cmphi_ccu"
1212   [(set (reg CC_REGNUM)
1213         (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1214                  (match_operand:HI 1 "general_operand"      "Q,S,D,BQ,Q")))]
1215   "s390_match_ccmode (insn, CCUmode)
1216    && !register_operand (operands[1], HImode)"
1217   "@
1218    clm\t%0,3,%S1
1219    clmy\t%0,3,%S1
1220    clhhsi\t%0,%1
1221    #
1222    #"
1223   [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1224    (set_attr "cpu_facility" "*,longdisp,z10,*,*")
1225    (set_attr "z10prop" "*,*,z10_super,*,*")])
1226
1227 (define_insn "*cmpqi_ccu"
1228   [(set (reg CC_REGNUM)
1229         (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1230                  (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1231   "s390_match_ccmode (insn, CCUmode)
1232    && !register_operand (operands[1], QImode)"
1233   "@
1234    clm\t%0,1,%S1
1235    clmy\t%0,1,%S1
1236    cli\t%S0,%b1
1237    cliy\t%S0,%b1
1238    #
1239    #"
1240   [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1241    (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
1242    (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1243
1244
1245 ; Block compare (CLC) instruction patterns.
1246
1247 (define_insn "*clc"
1248   [(set (reg CC_REGNUM)
1249         (compare (match_operand:BLK 0 "memory_operand" "Q")
1250                  (match_operand:BLK 1 "memory_operand" "Q")))
1251    (use (match_operand 2 "const_int_operand" "n"))]
1252   "s390_match_ccmode (insn, CCUmode)
1253    && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1254   "clc\t%O0(%2,%R0),%S1"
1255   [(set_attr "op_type" "SS")])
1256
1257 (define_split
1258   [(set (reg CC_REGNUM)
1259         (compare (match_operand 0 "memory_operand" "")
1260                  (match_operand 1 "memory_operand" "")))]
1261   "reload_completed
1262    && s390_match_ccmode (insn, CCUmode)
1263    && GET_MODE (operands[0]) == GET_MODE (operands[1])
1264    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1265   [(parallel
1266     [(set (match_dup 0) (match_dup 1))
1267      (use (match_dup 2))])]
1268 {
1269   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1270   operands[0] = adjust_address (operands[0], BLKmode, 0);
1271   operands[1] = adjust_address (operands[1], BLKmode, 0);
1272
1273   operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1274                                  operands[0], operands[1]);
1275   operands[0] = SET_DEST (PATTERN (curr_insn));
1276 })
1277
1278
1279 ; (TF|DF|SF|TD|DD|SD) instructions
1280
1281 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1282 (define_insn "*cmp<mode>_ccs_0"
1283   [(set (reg CC_REGNUM)
1284         (compare (match_operand:FP 0 "register_operand" "f")
1285                  (match_operand:FP 1 "const0_operand"   "")))]
1286   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1287   "lt<xde><bt>r\t%0,%0"
1288    [(set_attr "op_type" "RRE")
1289     (set_attr "type"  "fsimp<mode>")])
1290
1291 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1292 (define_insn "*cmp<mode>_ccs"
1293   [(set (reg CC_REGNUM)
1294         (compare (match_operand:FP 0 "register_operand" "f,f")
1295                  (match_operand:FP 1 "general_operand"  "f,R")))]
1296   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1297   "@
1298    c<xde><bt>r\t%0,%1
1299    c<xde>b\t%0,%1"
1300    [(set_attr "op_type" "RRE,RXE")
1301     (set_attr "type"  "fsimp<mode>")
1302     (set_attr "enabled" "*,<DSF>")])
1303
1304 ; wfcedbs, wfchdbs, wfchedbs
1305 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1306   [(set (reg:VFCMP CC_REGNUM)
1307         (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1308                        (match_operand:DF 1 "register_operand" "v")))
1309    (clobber (match_scratch:V2DI 2 "=v"))]
1310   "TARGET_VX && TARGET_HARD_FLOAT"
1311   "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1312   [(set_attr "op_type" "VRR")])
1313
1314 ; Compare and Branch instructions
1315
1316 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1317 ; The following instructions do a complementary access of their second
1318 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1319 (define_insn "*cmp_and_br_signed_<mode>"
1320   [(set (pc)
1321         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1322                         [(match_operand:GPR 1 "register_operand"  "d,d")
1323                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1324                       (label_ref (match_operand 3 "" ""))
1325                       (pc)))
1326    (clobber (reg:CC CC_REGNUM))]
1327   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1328 {
1329   if (get_attr_length (insn) == 6)
1330     return which_alternative ?
1331       "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1332   else
1333     return which_alternative ?
1334       "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1335 }
1336   [(set_attr "op_type" "RIE")
1337    (set_attr "type"    "branch")
1338    (set_attr "z10prop" "z10_super_c,z10_super")
1339    (set (attr "length")
1340         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1341                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1342                                                        ; 10 byte for cgr/jg
1343
1344 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1345 ; The following instructions do a complementary access of their second
1346 ; operand (z10 only): clrj, clgrj, clr, clgr
1347 (define_insn "*cmp_and_br_unsigned_<mode>"
1348   [(set (pc)
1349         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1350                         [(match_operand:GPR 1 "register_operand"  "d,d")
1351                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1352                       (label_ref (match_operand 3 "" ""))
1353                       (pc)))
1354    (clobber (reg:CC CC_REGNUM))]
1355   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1356 {
1357   if (get_attr_length (insn) == 6)
1358     return which_alternative ?
1359       "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1360   else
1361     return which_alternative ?
1362       "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1363 }
1364   [(set_attr "op_type" "RIE")
1365    (set_attr "type"    "branch")
1366    (set_attr "z10prop" "z10_super_c,z10_super")
1367    (set (attr "length")
1368         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1369                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1370                                                        ; 10 byte for clgr/jg
1371
1372 ; And now the same two patterns as above but with a negated CC mask.
1373
1374 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1375 ; The following instructions do a complementary access of their second
1376 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1377 (define_insn "*icmp_and_br_signed_<mode>"
1378   [(set (pc)
1379         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1380                         [(match_operand:GPR 1 "register_operand"  "d,d")
1381                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1382                       (pc)
1383                       (label_ref (match_operand 3 "" ""))))
1384    (clobber (reg:CC CC_REGNUM))]
1385   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1386 {
1387   if (get_attr_length (insn) == 6)
1388     return which_alternative ?
1389       "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1390   else
1391     return which_alternative ?
1392       "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1393 }
1394   [(set_attr "op_type" "RIE")
1395    (set_attr "type"    "branch")
1396    (set_attr "z10prop" "z10_super_c,z10_super")
1397    (set (attr "length")
1398         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1399                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1400                                                        ; 10 byte for cgr/jg
1401
1402 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1403 ; The following instructions do a complementary access of their second
1404 ; operand (z10 only): clrj, clgrj, clr, clgr
1405 (define_insn "*icmp_and_br_unsigned_<mode>"
1406   [(set (pc)
1407         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1408                         [(match_operand:GPR 1 "register_operand"  "d,d")
1409                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1410                       (pc)
1411                       (label_ref (match_operand 3 "" ""))))
1412    (clobber (reg:CC CC_REGNUM))]
1413   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1414 {
1415   if (get_attr_length (insn) == 6)
1416     return which_alternative ?
1417       "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1418   else
1419     return which_alternative ?
1420       "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1421 }
1422   [(set_attr "op_type" "RIE")
1423    (set_attr "type"    "branch")
1424    (set_attr "z10prop" "z10_super_c,z10_super")
1425    (set (attr "length")
1426         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1427                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1428                                                        ; 10 byte for clgr/jg
1429
1430 ;;
1431 ;;- Move instructions.
1432 ;;
1433
1434 ;
1435 ; movti instruction pattern(s).
1436 ;
1437
1438 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1439 ; for TImode (use double-int for the calculations)
1440 (define_insn "movti"
1441   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v,  v,  v,v,d,v,R,  d,o")
1442         (match_operand:TI 1 "general_operand"      " S,d,v,j00,jm1,d,v,R,v,dPT,d"))]
1443   "TARGET_ZARCH"
1444   "@
1445    lmg\t%0,%N0,%S1
1446    stmg\t%1,%N1,%S0
1447    vlr\t%v0,%v1
1448    vzero\t%v0
1449    vone\t%v0
1450    vlvgp\t%v0,%1,%N1
1451    #
1452    vl\t%v0,%1
1453    vst\t%v1,%0
1454    #
1455    #"
1456   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1457    (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1458    (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1459
1460 (define_split
1461   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1462         (match_operand:TI 1 "general_operand" ""))]
1463   "TARGET_ZARCH && reload_completed
1464    && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1465   [(set (match_dup 2) (match_dup 4))
1466    (set (match_dup 3) (match_dup 5))]
1467 {
1468   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1469   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1470   operands[4] = operand_subword (operands[1], 0, 0, TImode);
1471   operands[5] = operand_subword (operands[1], 1, 0, TImode);
1472 })
1473
1474 (define_split
1475   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1476         (match_operand:TI 1 "general_operand" ""))]
1477   "TARGET_ZARCH && reload_completed
1478    && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1479   [(set (match_dup 2) (match_dup 4))
1480    (set (match_dup 3) (match_dup 5))]
1481 {
1482   operands[2] = operand_subword (operands[0], 1, 0, TImode);
1483   operands[3] = operand_subword (operands[0], 0, 0, TImode);
1484   operands[4] = operand_subword (operands[1], 1, 0, TImode);
1485   operands[5] = operand_subword (operands[1], 0, 0, TImode);
1486 })
1487
1488 ; Use part of the TImode target reg to perform the address
1489 ; calculation.  If the TImode value is supposed to be copied into a VR
1490 ; this splitter is not necessary.
1491 (define_split
1492   [(set (match_operand:TI 0 "register_operand" "")
1493         (match_operand:TI 1 "memory_operand" ""))]
1494   "TARGET_ZARCH && reload_completed
1495    && !VECTOR_REG_P (operands[0])
1496    && !s_operand (operands[1], VOIDmode)"
1497   [(set (match_dup 0) (match_dup 1))]
1498 {
1499   rtx addr = operand_subword (operands[0], 1, 0, TImode);
1500   addr = gen_lowpart (Pmode, addr);
1501   s390_load_address (addr, XEXP (operands[1], 0));
1502   operands[1] = replace_equiv_address (operands[1], addr);
1503 })
1504
1505
1506 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1507 ; For the higher order bits we do simply a DImode move while the
1508 ; second part is done via vec extract.  Both will end up as vlgvg.
1509 (define_split
1510   [(set (match_operand:TI 0 "register_operand" "")
1511         (match_operand:TI 1 "register_operand" ""))]
1512   "TARGET_VX && reload_completed
1513    && GENERAL_REG_P (operands[0])
1514    && VECTOR_REG_P (operands[1])"
1515   [(set (match_dup 2) (match_dup 4))
1516    (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1517                                  UNSPEC_VEC_EXTRACT))]
1518 {
1519   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1520   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1521   operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1522   operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1523 })
1524
1525 ;
1526 ; Patterns used for secondary reloads
1527 ;
1528
1529 ; z10 provides move instructions accepting larl memory operands.
1530 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1531 ; These patterns are also used for unaligned SI and DI accesses.
1532
1533 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1534   [(parallel [(match_operand:ALL 0 "memory_operand"   "")
1535               (match_operand:ALL 1 "register_operand" "=d")
1536               (match_operand:P   2 "register_operand" "=&a")])]
1537   "TARGET_Z10"
1538 {
1539   s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1540   DONE;
1541 })
1542
1543 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1544   [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1545               (match_operand:ALL 1 "memory_operand"   "")
1546               (match_operand:P   2 "register_operand" "=a")])]
1547   "TARGET_Z10"
1548 {
1549   s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1550   DONE;
1551 })
1552
1553 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1554   [(parallel [(match_operand:P 0 "register_operand" "=d")
1555               (match_operand:P 1 "larl_operand"     "")
1556               (match_operand:P 2 "register_operand" "=a")])]
1557   "TARGET_Z10"
1558 {
1559   s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1560   DONE;
1561 })
1562
1563 ; Handles loading a PLUS (load address) expression
1564
1565 (define_expand "reload<mode>_plus"
1566   [(parallel [(match_operand:P 0 "register_operand"  "=a")
1567               (match_operand:P 1 "s390_plus_operand" "")
1568               (match_operand:P 2 "register_operand"  "=&a")])]
1569   ""
1570 {
1571   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1572   DONE;
1573 })
1574
1575 ; Not all the indirect memory access instructions support the full
1576 ; format (long disp + index + base).  So whenever a move from/to such
1577 ; an address is required and the instruction cannot deal with it we do
1578 ; a load address into a scratch register first and use this as the new
1579 ; base register.
1580 ; This in particular is used for:
1581 ; - non-offsetable memory accesses for multiword moves
1582 ; - full vector reg moves with long displacements
1583
1584 (define_expand "reload<mode>_la_in"
1585   [(parallel [(match_operand 0   "register_operand" "")
1586               (match_operand 1   "" "")
1587               (match_operand:P 2 "register_operand" "=&a")])]
1588   ""
1589 {
1590   gcc_assert (MEM_P (operands[1]));
1591   s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1592   operands[1] = replace_equiv_address (operands[1], operands[2]);
1593   emit_move_insn (operands[0], operands[1]);
1594   DONE;
1595 })
1596
1597 (define_expand "reload<mode>_la_out"
1598   [(parallel [(match_operand   0 "" "")
1599               (match_operand   1 "register_operand" "")
1600               (match_operand:P 2 "register_operand" "=&a")])]
1601   ""
1602 {
1603   gcc_assert (MEM_P (operands[0]));
1604   s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1605   operands[0] = replace_equiv_address (operands[0], operands[2]);
1606   emit_move_insn (operands[0], operands[1]);
1607   DONE;
1608 })
1609
1610 (define_expand "reload<mode>_PIC_addr"
1611   [(parallel [(match_operand   0 "register_operand" "=d")
1612               (match_operand   1 "larl_operand"     "")
1613               (match_operand:P 2 "register_operand" "=a")])]
1614   ""
1615 {
1616   rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1617   emit_move_insn (operands[0], new_rtx);
1618 })
1619
1620 ;
1621 ; movdi instruction pattern(s).
1622 ;
1623
1624 (define_expand "movdi"
1625   [(set (match_operand:DI 0 "general_operand" "")
1626         (match_operand:DI 1 "general_operand" ""))]
1627   ""
1628 {
1629   /* Handle symbolic constants.  */
1630   if (TARGET_64BIT
1631       && (SYMBOLIC_CONST (operands[1])
1632           || (GET_CODE (operands[1]) == PLUS
1633               && XEXP (operands[1], 0) == pic_offset_table_rtx
1634               && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1635     emit_symbolic_move (operands);
1636 })
1637
1638 (define_insn "*movdi_larl"
1639   [(set (match_operand:DI 0 "register_operand" "=d")
1640         (match_operand:DI 1 "larl_operand" "X"))]
1641   "TARGET_64BIT
1642    && !FP_REG_P (operands[0])"
1643   "larl\t%0,%1"
1644    [(set_attr "op_type" "RIL")
1645     (set_attr "type"    "larl")
1646     (set_attr "z10prop" "z10_super_A1")])
1647
1648 (define_insn "*movdi_64"
1649   [(set (match_operand:DI 0 "nonimmediate_operand"
1650          "=d,    d,    d,    d,    d, d,    d,    d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R")
1651         (match_operand:DI 1 "general_operand"
1652          " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f,  R,  T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))]
1653   "TARGET_ZARCH"
1654   "@
1655    lghi\t%0,%h1
1656    llihh\t%0,%i1
1657    llihl\t%0,%i1
1658    llilh\t%0,%i1
1659    llill\t%0,%i1
1660    lgfi\t%0,%1
1661    llihf\t%0,%k1
1662    llilf\t%0,%k1
1663    ldgr\t%0,%1
1664    lgdr\t%0,%1
1665    lay\t%0,%a1
1666    lgrl\t%0,%1
1667    lgr\t%0,%1
1668    lg\t%0,%1
1669    stg\t%1,%0
1670    ldr\t%0,%1
1671    ld\t%0,%1
1672    ldy\t%0,%1
1673    std\t%1,%0
1674    stdy\t%1,%0
1675    stgrl\t%1,%0
1676    mvghi\t%0,%1
1677    #
1678    #
1679    stam\t%1,%N1,%S0
1680    lam\t%0,%N0,%S1
1681    vleig\t%v0,%h1,0
1682    vlr\t%v0,%v1
1683    vlvgg\t%v0,%1,0
1684    vlgvg\t%0,%v1,0
1685    vleg\t%v0,%1,0
1686    vsteg\t%v1,%0,0"
1687   [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1688                         RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1689    (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1690                      floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1691                      *,*,*,*,*,*,*")
1692    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1693                              z10,*,*,*,*,*,longdisp,*,longdisp,
1694                              z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1695    (set_attr "z10prop" "z10_fwd_A1,
1696                         z10_fwd_E1,
1697                         z10_fwd_E1,
1698                         z10_fwd_E1,
1699                         z10_fwd_E1,
1700                         z10_fwd_A1,
1701                         z10_fwd_E1,
1702                         z10_fwd_E1,
1703                         *,
1704                         *,
1705                         z10_fwd_A1,
1706                         z10_fwd_A3,
1707                         z10_fr_E1,
1708                         z10_fwd_A3,
1709                         z10_rec,
1710                         *,
1711                         *,
1712                         *,
1713                         *,
1714                         *,
1715                         z10_rec,
1716                         z10_super,
1717                         *,
1718                         *,
1719                         *,
1720                         *,*,*,*,*,*,*")
1721 ])
1722
1723 (define_split
1724   [(set (match_operand:DI 0 "register_operand" "")
1725         (match_operand:DI 1 "register_operand" ""))]
1726   "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1727   [(set (match_dup 2) (match_dup 3))
1728    (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1729    (set (strict_low_part (match_dup 2)) (match_dup 4))]
1730   "operands[2] = gen_lowpart (SImode, operands[0]);
1731    s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1732
1733 (define_split
1734   [(set (match_operand:DI 0 "register_operand" "")
1735         (match_operand:DI 1 "register_operand" ""))]
1736   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1737    && dead_or_set_p (insn, operands[1])"
1738   [(set (match_dup 3) (match_dup 2))
1739    (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1740    (set (match_dup 4) (match_dup 2))]
1741   "operands[2] = gen_lowpart (SImode, operands[1]);
1742    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1743
1744 (define_split
1745   [(set (match_operand:DI 0 "register_operand" "")
1746         (match_operand:DI 1 "register_operand" ""))]
1747   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1748    && !dead_or_set_p (insn, operands[1])"
1749   [(set (match_dup 3) (match_dup 2))
1750    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1751    (set (match_dup 4) (match_dup 2))
1752    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1753   "operands[2] = gen_lowpart (SImode, operands[1]);
1754    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1755
1756 (define_insn "*movdi_31"
1757   [(set (match_operand:DI 0 "nonimmediate_operand"
1758                             "=d,d,Q,S,d  ,o,!*f,!*f,!*f,!R,!T,d")
1759         (match_operand:DI 1 "general_operand"
1760                             " Q,S,d,d,dPT,d, *f,  R,  T,*f,*f,b"))]
1761   "!TARGET_ZARCH"
1762   "@
1763    lm\t%0,%N0,%S1
1764    lmy\t%0,%N0,%S1
1765    stm\t%1,%N1,%S0
1766    stmy\t%1,%N1,%S0
1767    #
1768    #
1769    ldr\t%0,%1
1770    ld\t%0,%1
1771    ldy\t%0,%1
1772    std\t%1,%0
1773    stdy\t%1,%0
1774    #"
1775   [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1776    (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1777    (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
1778
1779 ; For a load from a symbol ref we can use one of the target registers
1780 ; together with larl to load the address.
1781 (define_split
1782   [(set (match_operand:DI 0 "register_operand" "")
1783         (match_operand:DI 1 "memory_operand" ""))]
1784   "!TARGET_ZARCH && reload_completed && TARGET_Z10
1785    && larl_operand (XEXP (operands[1], 0), SImode)"
1786   [(set (match_dup 2) (match_dup 3))
1787    (set (match_dup 0) (match_dup 1))]
1788 {
1789   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1790   operands[3] = XEXP (operands[1], 0);
1791   operands[1] = replace_equiv_address (operands[1], operands[2]);
1792 })
1793
1794 (define_split
1795   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1796         (match_operand:DI 1 "general_operand" ""))]
1797   "!TARGET_ZARCH && reload_completed
1798    && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1799   [(set (match_dup 2) (match_dup 4))
1800    (set (match_dup 3) (match_dup 5))]
1801 {
1802   operands[2] = operand_subword (operands[0], 0, 0, DImode);
1803   operands[3] = operand_subword (operands[0], 1, 0, DImode);
1804   operands[4] = operand_subword (operands[1], 0, 0, DImode);
1805   operands[5] = operand_subword (operands[1], 1, 0, DImode);
1806 })
1807
1808 (define_split
1809   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1810         (match_operand:DI 1 "general_operand" ""))]
1811   "!TARGET_ZARCH && reload_completed
1812    && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1813   [(set (match_dup 2) (match_dup 4))
1814    (set (match_dup 3) (match_dup 5))]
1815 {
1816   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1817   operands[3] = operand_subword (operands[0], 0, 0, DImode);
1818   operands[4] = operand_subword (operands[1], 1, 0, DImode);
1819   operands[5] = operand_subword (operands[1], 0, 0, DImode);
1820 })
1821
1822 (define_split
1823   [(set (match_operand:DI 0 "register_operand" "")
1824         (match_operand:DI 1 "memory_operand" ""))]
1825   "!TARGET_ZARCH && reload_completed
1826    && !FP_REG_P (operands[0])
1827    && !s_operand (operands[1], VOIDmode)"
1828   [(set (match_dup 0) (match_dup 1))]
1829 {
1830   rtx addr = operand_subword (operands[0], 1, 0, DImode);
1831   s390_load_address (addr, XEXP (operands[1], 0));
1832   operands[1] = replace_equiv_address (operands[1], addr);
1833 })
1834
1835 (define_peephole2
1836   [(set (match_operand:DI 0 "register_operand" "")
1837         (mem:DI (match_operand 1 "address_operand" "")))]
1838   "TARGET_ZARCH
1839    && !FP_REG_P (operands[0])
1840    && GET_CODE (operands[1]) == SYMBOL_REF
1841    && CONSTANT_POOL_ADDRESS_P (operands[1])
1842    && get_pool_mode (operands[1]) == DImode
1843    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1844   [(set (match_dup 0) (match_dup 2))]
1845   "operands[2] = get_pool_constant (operands[1]);")
1846
1847 (define_insn "*la_64"
1848   [(set (match_operand:DI 0 "register_operand" "=d,d")
1849         (match_operand:QI 1 "address_operand" "ZR,ZT"))]
1850   "TARGET_64BIT"
1851   "@
1852    la\t%0,%a1
1853    lay\t%0,%a1"
1854   [(set_attr "op_type" "RX,RXY")
1855    (set_attr "type"    "la")
1856    (set_attr "cpu_facility" "*,longdisp")
1857    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1858
1859 (define_peephole2
1860   [(parallel
1861     [(set (match_operand:DI 0 "register_operand" "")
1862           (match_operand:QI 1 "address_operand" ""))
1863      (clobber (reg:CC CC_REGNUM))])]
1864   "TARGET_64BIT
1865    && preferred_la_operand_p (operands[1], const0_rtx)"
1866   [(set (match_dup 0) (match_dup 1))]
1867   "")
1868
1869 (define_peephole2
1870   [(set (match_operand:DI 0 "register_operand" "")
1871         (match_operand:DI 1 "register_operand" ""))
1872    (parallel
1873     [(set (match_dup 0)
1874           (plus:DI (match_dup 0)
1875                    (match_operand:DI 2 "nonmemory_operand" "")))
1876      (clobber (reg:CC CC_REGNUM))])]
1877   "TARGET_64BIT
1878    && !reg_overlap_mentioned_p (operands[0], operands[2])
1879    && preferred_la_operand_p (operands[1], operands[2])"
1880   [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1881   "")
1882
1883 ;
1884 ; movsi instruction pattern(s).
1885 ;
1886
1887 (define_expand "movsi"
1888   [(set (match_operand:SI 0 "general_operand" "")
1889         (match_operand:SI 1 "general_operand" ""))]
1890   ""
1891 {
1892   /* Handle symbolic constants.  */
1893   if (!TARGET_64BIT
1894       && (SYMBOLIC_CONST (operands[1])
1895           || (GET_CODE (operands[1]) == PLUS
1896               && XEXP (operands[1], 0) == pic_offset_table_rtx
1897               && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1898     emit_symbolic_move (operands);
1899 })
1900
1901 (define_insn "*movsi_larl"
1902   [(set (match_operand:SI 0 "register_operand" "=d")
1903         (match_operand:SI 1 "larl_operand" "X"))]
1904   "!TARGET_64BIT && TARGET_CPU_ZARCH
1905    && !FP_REG_P (operands[0])"
1906   "larl\t%0,%1"
1907    [(set_attr "op_type" "RIL")
1908     (set_attr "type"    "larl")
1909     (set_attr "z10prop" "z10_fwd_A1")])
1910
1911 (define_insn "*movsi_zarch"
1912   [(set (match_operand:SI 0 "nonimmediate_operand"
1913          "=d,    d,    d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
1914         (match_operand:SI 1 "general_operand"
1915          " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f,  R,  R,  T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
1916   "TARGET_ZARCH"
1917   "@
1918    lhi\t%0,%h1
1919    llilh\t%0,%i1
1920    llill\t%0,%i1
1921    iilf\t%0,%o1
1922    lay\t%0,%a1
1923    lrl\t%0,%1
1924    lr\t%0,%1
1925    l\t%0,%1
1926    ly\t%0,%1
1927    st\t%1,%0
1928    sty\t%1,%0
1929    ldr\t%0,%1
1930    ler\t%0,%1
1931    lde\t%0,%1
1932    le\t%0,%1
1933    ley\t%0,%1
1934    ste\t%1,%0
1935    stey\t%1,%0
1936    ear\t%0,%1
1937    sar\t%0,%1
1938    stam\t%1,%1,%S0
1939    strl\t%1,%0
1940    mvhi\t%0,%1
1941    lam\t%0,%0,%S1
1942    vleif\t%v0,%h1,0
1943    vlr\t%v0,%v1
1944    vlvgf\t%v0,%1,0
1945    vlgvf\t%0,%v1,0
1946    vlef\t%v0,%1,0
1947    vstef\t%v1,%0,0"
1948   [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1949                         RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1950    (set_attr "type" "*,
1951                      *,
1952                      *,
1953                      *,
1954                      la,
1955                      larl,
1956                      lr,
1957                      load,
1958                      load,
1959                      store,
1960                      store,
1961                      floadsf,
1962                      floadsf,
1963                      floadsf,
1964                      floadsf,
1965                      floadsf,
1966                      fstoresf,
1967                      fstoresf,
1968                      *,
1969                      *,
1970                      *,
1971                      larl,
1972                      *,
1973                      *,*,*,*,*,*,*")
1974    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1975                              vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1976    (set_attr "z10prop" "z10_fwd_A1,
1977                         z10_fwd_E1,
1978                         z10_fwd_E1,
1979                         z10_fwd_A1,
1980                         z10_fwd_A1,
1981                         z10_fwd_A3,
1982                         z10_fr_E1,
1983                         z10_fwd_A3,
1984                         z10_fwd_A3,
1985                         z10_rec,
1986                         z10_rec,
1987                         *,
1988                         *,
1989                         *,
1990                         *,
1991                         *,
1992                         *,
1993                         *,
1994                         z10_super_E1,
1995                         z10_super,
1996                         *,
1997                         z10_rec,
1998                         z10_super,
1999                         *,*,*,*,*,*,*")])
2000
2001 (define_insn "*movsi_esa"
2002   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
2003         (match_operand:SI 1 "general_operand"       "K,d,R,d, *f, *f,  R,  R,*f,t,d,t,Q"))]
2004   "!TARGET_ZARCH"
2005   "@
2006    lhi\t%0,%h1
2007    lr\t%0,%1
2008    l\t%0,%1
2009    st\t%1,%0
2010    ldr\t%0,%1
2011    ler\t%0,%1
2012    lde\t%0,%1
2013    le\t%0,%1
2014    ste\t%1,%0
2015    ear\t%0,%1
2016    sar\t%0,%1
2017    stam\t%1,%1,%S0
2018    lam\t%0,%0,%S1"
2019   [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
2020    (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
2021    (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
2022                         z10_super,*,*")
2023    (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
2024 ])
2025
2026 (define_peephole2
2027   [(set (match_operand:SI 0 "register_operand" "")
2028         (mem:SI (match_operand 1 "address_operand" "")))]
2029   "!FP_REG_P (operands[0])
2030    && GET_CODE (operands[1]) == SYMBOL_REF
2031    && CONSTANT_POOL_ADDRESS_P (operands[1])
2032    && get_pool_mode (operands[1]) == SImode
2033    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
2034   [(set (match_dup 0) (match_dup 2))]
2035   "operands[2] = get_pool_constant (operands[1]);")
2036
2037 (define_insn "*la_31"
2038   [(set (match_operand:SI 0 "register_operand" "=d,d")
2039         (match_operand:QI 1 "address_operand" "ZR,ZT"))]
2040   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
2041   "@
2042    la\t%0,%a1
2043    lay\t%0,%a1"
2044   [(set_attr "op_type"  "RX,RXY")
2045    (set_attr "type"     "la")
2046    (set_attr "cpu_facility" "*,longdisp")
2047    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2048
2049 (define_peephole2
2050   [(parallel
2051     [(set (match_operand:SI 0 "register_operand" "")
2052           (match_operand:QI 1 "address_operand" ""))
2053      (clobber (reg:CC CC_REGNUM))])]
2054   "!TARGET_64BIT
2055    && preferred_la_operand_p (operands[1], const0_rtx)"
2056   [(set (match_dup 0) (match_dup 1))]
2057   "")
2058
2059 (define_peephole2
2060   [(set (match_operand:SI 0 "register_operand" "")
2061         (match_operand:SI 1 "register_operand" ""))
2062    (parallel
2063     [(set (match_dup 0)
2064           (plus:SI (match_dup 0)
2065                    (match_operand:SI 2 "nonmemory_operand" "")))
2066      (clobber (reg:CC CC_REGNUM))])]
2067   "!TARGET_64BIT
2068    && !reg_overlap_mentioned_p (operands[0], operands[2])
2069    && preferred_la_operand_p (operands[1], operands[2])"
2070   [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2071   "")
2072
2073 (define_insn "*la_31_and"
2074   [(set (match_operand:SI 0 "register_operand" "=d,d")
2075         (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
2076                 (const_int 2147483647)))]
2077   "!TARGET_64BIT"
2078   "@
2079    la\t%0,%a1
2080    lay\t%0,%a1"
2081   [(set_attr "op_type"  "RX,RXY")
2082    (set_attr "type"     "la")
2083    (set_attr "cpu_facility" "*,longdisp")
2084    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2085
2086 (define_insn_and_split "*la_31_and_cc"
2087   [(set (match_operand:SI 0 "register_operand" "=d")
2088         (and:SI (match_operand:QI 1 "address_operand" "p")
2089                 (const_int 2147483647)))
2090    (clobber (reg:CC CC_REGNUM))]
2091   "!TARGET_64BIT"
2092   "#"
2093   "&& reload_completed"
2094   [(set (match_dup 0)
2095         (and:SI (match_dup 1) (const_int 2147483647)))]
2096   ""
2097   [(set_attr "op_type"  "RX")
2098    (set_attr "type"     "la")])
2099
2100 (define_insn "force_la_31"
2101   [(set (match_operand:SI 0 "register_operand" "=d,d")
2102         (match_operand:QI 1 "address_operand" "ZR,ZT"))
2103    (use (const_int 0))]
2104   "!TARGET_64BIT"
2105   "@
2106    la\t%0,%a1
2107    lay\t%0,%a1"
2108   [(set_attr "op_type"  "RX")
2109    (set_attr "type"     "la")
2110    (set_attr "cpu_facility" "*,longdisp")
2111    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2112
2113 ;
2114 ; movhi instruction pattern(s).
2115 ;
2116
2117 (define_expand "movhi"
2118   [(set (match_operand:HI 0 "nonimmediate_operand" "")
2119         (match_operand:HI 1 "general_operand" ""))]
2120   ""
2121 {
2122   /* Make it explicit that loading a register from memory
2123      always sign-extends (at least) to SImode.  */
2124   if (optimize && can_create_pseudo_p ()
2125       && register_operand (operands[0], VOIDmode)
2126       && GET_CODE (operands[1]) == MEM)
2127     {
2128       rtx tmp = gen_reg_rtx (SImode);
2129       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2130       emit_insn (gen_rtx_SET (tmp, ext));
2131       operands[1] = gen_lowpart (HImode, tmp);
2132     }
2133 })
2134
2135 (define_insn "*movhi"
2136   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
2137         (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
2138   ""
2139   "@
2140    lr\t%0,%1
2141    lhi\t%0,%h1
2142    lh\t%0,%1
2143    lhy\t%0,%1
2144    lhrl\t%0,%1
2145    sth\t%1,%0
2146    sthy\t%1,%0
2147    sthrl\t%1,%0
2148    mvhhi\t%0,%1
2149    vleih\t%v0,%h1,0
2150    vlr\t%v0,%v1
2151    vlvgh\t%v0,%1,0
2152    vlgvh\t%0,%v1,0
2153    vleh\t%v0,%1,0
2154    vsteh\t%v1,%0,0"
2155   [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2156    (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2157    (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vec,vec,vec,vec,vec,vec")
2158    (set_attr "z10prop" "z10_fr_E1,
2159                        z10_fwd_A1,
2160                        z10_super_E1,
2161                        z10_super_E1,
2162                        z10_super_E1,
2163                        z10_rec,
2164                        z10_rec,
2165                        z10_rec,
2166                        z10_super,*,*,*,*,*,*")])
2167
2168 (define_peephole2
2169   [(set (match_operand:HI 0 "register_operand" "")
2170         (mem:HI (match_operand 1 "address_operand" "")))]
2171   "GET_CODE (operands[1]) == SYMBOL_REF
2172    && CONSTANT_POOL_ADDRESS_P (operands[1])
2173    && get_pool_mode (operands[1]) == HImode
2174    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2175   [(set (match_dup 0) (match_dup 2))]
2176   "operands[2] = get_pool_constant (operands[1]);")
2177
2178 ;
2179 ; movqi instruction pattern(s).
2180 ;
2181
2182 (define_expand "movqi"
2183   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2184         (match_operand:QI 1 "general_operand" ""))]
2185   ""
2186 {
2187   /* On z/Architecture, zero-extending from memory to register
2188      is just as fast as a QImode load.  */
2189   if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2190       && register_operand (operands[0], VOIDmode)
2191       && GET_CODE (operands[1]) == MEM)
2192     {
2193       rtx tmp = gen_reg_rtx (DImode);
2194       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2195       emit_insn (gen_rtx_SET (tmp, ext));
2196       operands[1] = gen_lowpart (QImode, tmp);
2197     }
2198 })
2199
2200 (define_insn "*movqi"
2201   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
2202         (match_operand:QI 1 "general_operand"      " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
2203   ""
2204   "@
2205    lr\t%0,%1
2206    lhi\t%0,%b1
2207    ic\t%0,%1
2208    icy\t%0,%1
2209    stc\t%1,%0
2210    stcy\t%1,%0
2211    mvi\t%S0,%b1
2212    mviy\t%S0,%b1
2213    #
2214    vleib\t%v0,%b1,0
2215    vlr\t%v0,%v1
2216    vlvgb\t%v0,%1,0
2217    vlgvb\t%0,%v1,0
2218    vleb\t%v0,%1,0
2219    vsteb\t%v1,%0,0"
2220   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2221    (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2222    (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vec,vec,vec,vec,vec,vec")
2223    (set_attr "z10prop" "z10_fr_E1,
2224                         z10_fwd_A1,
2225                         z10_super_E1,
2226                         z10_super_E1,
2227                         z10_rec,
2228                         z10_rec,
2229                         z10_super,
2230                         z10_super,
2231                         *,*,*,*,*,*,*")])
2232
2233 (define_peephole2
2234   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2235         (mem:QI (match_operand 1 "address_operand" "")))]
2236   "GET_CODE (operands[1]) == SYMBOL_REF
2237    && CONSTANT_POOL_ADDRESS_P (operands[1])
2238    && get_pool_mode (operands[1]) == QImode
2239    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2240   [(set (match_dup 0) (match_dup 2))]
2241   "operands[2] = get_pool_constant (operands[1]);")
2242
2243 ;
2244 ; movstrictqi instruction pattern(s).
2245 ;
2246
2247 (define_insn "*movstrictqi"
2248   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2249                          (match_operand:QI 1 "memory_operand" "R,T"))]
2250   ""
2251   "@
2252    ic\t%0,%1
2253    icy\t%0,%1"
2254   [(set_attr "op_type"  "RX,RXY")
2255    (set_attr "cpu_facility" "*,longdisp")
2256    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2257
2258 ;
2259 ; movstricthi instruction pattern(s).
2260 ;
2261
2262 (define_insn "*movstricthi"
2263   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2264                          (match_operand:HI 1 "memory_operand" "Q,S"))
2265    (clobber (reg:CC CC_REGNUM))]
2266   ""
2267   "@
2268    icm\t%0,3,%S1
2269    icmy\t%0,3,%S1"
2270   [(set_attr "op_type" "RS,RSY")
2271    (set_attr "cpu_facility" "*,longdisp")
2272    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2273
2274 ;
2275 ; movstrictsi instruction pattern(s).
2276 ;
2277
2278 (define_insn "movstrictsi"
2279   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2280                          (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2281   "TARGET_ZARCH"
2282   "@
2283    lr\t%0,%1
2284    l\t%0,%1
2285    ly\t%0,%1
2286    ear\t%0,%1"
2287   [(set_attr "op_type" "RR,RX,RXY,RRE")
2288    (set_attr "type" "lr,load,load,*")
2289    (set_attr "cpu_facility" "*,*,longdisp,*")
2290    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2291
2292 ;
2293 ; mov(tf|td) instruction pattern(s).
2294 ;
2295
2296 (define_expand "mov<mode>"
2297   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2298         (match_operand:TD_TF 1 "general_operand"      ""))]
2299   ""
2300   "")
2301
2302 (define_insn "*mov<mode>_64"
2303   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
2304         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,S,d,dT,d"))]
2305   "TARGET_ZARCH"
2306   "@
2307    lzxr\t%0
2308    lxr\t%0,%1
2309    #
2310    #
2311    lmg\t%0,%N0,%S1
2312    stmg\t%1,%N1,%S0
2313    #
2314    #"
2315   [(set_attr "op_type"      "RRE,RRE,*,*,RSY,RSY,*,*")
2316    (set_attr "type"         "fsimptf,fsimptf,*,*,lm,stm,*,*")
2317    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2318
2319 (define_insn "*mov<mode>_31"
2320   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2321         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
2322   "!TARGET_ZARCH"
2323   "@
2324    lzxr\t%0
2325    lxr\t%0,%1
2326    #
2327    #"
2328   [(set_attr "op_type"      "RRE,RRE,*,*")
2329    (set_attr "type"         "fsimptf,fsimptf,*,*")
2330    (set_attr "cpu_facility" "z196,*,*,*")])
2331
2332 ; TFmode in GPRs splitters
2333
2334 (define_split
2335   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2336         (match_operand:TD_TF 1 "general_operand"      ""))]
2337   "TARGET_ZARCH && reload_completed
2338    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2339   [(set (match_dup 2) (match_dup 4))
2340    (set (match_dup 3) (match_dup 5))]
2341 {
2342   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2343   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2344   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2345   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2346 })
2347
2348 (define_split
2349   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2350         (match_operand:TD_TF 1 "general_operand"      ""))]
2351   "TARGET_ZARCH && reload_completed
2352    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2353   [(set (match_dup 2) (match_dup 4))
2354    (set (match_dup 3) (match_dup 5))]
2355 {
2356   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2357   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2358   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2359   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2360 })
2361
2362 (define_split
2363   [(set (match_operand:TD_TF 0 "register_operand" "")
2364         (match_operand:TD_TF 1 "memory_operand"   ""))]
2365   "TARGET_ZARCH && reload_completed
2366    && GENERAL_REG_P (operands[0])
2367    && !s_operand (operands[1], VOIDmode)"
2368   [(set (match_dup 0) (match_dup 1))]
2369 {
2370   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2371   addr = gen_lowpart (Pmode, addr);
2372   s390_load_address (addr, XEXP (operands[1], 0));
2373   operands[1] = replace_equiv_address (operands[1], addr);
2374 })
2375
2376 ; TFmode in BFPs splitters
2377
2378 (define_split
2379   [(set (match_operand:TD_TF 0 "register_operand" "")
2380         (match_operand:TD_TF 1 "memory_operand" ""))]
2381   "reload_completed && offsettable_memref_p (operands[1])
2382    && FP_REG_P (operands[0])"
2383   [(set (match_dup 2) (match_dup 4))
2384    (set (match_dup 3) (match_dup 5))]
2385 {
2386   operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2387                                      <MODE>mode, 0);
2388   operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2389                                      <MODE>mode, 8);
2390   operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2391   operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2392 })
2393
2394 (define_split
2395   [(set (match_operand:TD_TF 0 "memory_operand" "")
2396         (match_operand:TD_TF 1 "register_operand" ""))]
2397   "reload_completed && offsettable_memref_p (operands[0])
2398    && FP_REG_P (operands[1])"
2399   [(set (match_dup 2) (match_dup 4))
2400    (set (match_dup 3) (match_dup 5))]
2401 {
2402   operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2403   operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2404   operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2405                                      <MODE>mode, 0);
2406   operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2407                                      <MODE>mode, 8);
2408 })
2409
2410 ;
2411 ; mov(df|dd) instruction pattern(s).
2412 ;
2413
2414 (define_expand "mov<mode>"
2415   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2416         (match_operand:DD_DF 1 "general_operand"  ""))]
2417   ""
2418   "")
2419
2420 (define_insn "*mov<mode>_64dfp"
2421   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2422                                "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,d,v,R")
2423         (match_operand:DD_DF 1 "general_operand"
2424                                " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,d,v,R,v"))]
2425   "TARGET_DFP"
2426   "@
2427    lzdr\t%0
2428    ldr\t%0,%1
2429    ldgr\t%0,%1
2430    lgdr\t%0,%1
2431    ld\t%0,%1
2432    ldy\t%0,%1
2433    std\t%1,%0
2434    stdy\t%1,%0
2435    lghi\t%0,0
2436    lgr\t%0,%1
2437    lgrl\t%0,%1
2438    lg\t%0,%1
2439    stgrl\t%1,%0
2440    stg\t%1,%0
2441    vlr\t%v0,%v1
2442    vlvgg\t%v0,%1,0
2443    vlgvg\t%0,%v1,0
2444    vleg\t%0,%1,0
2445    vsteg\t%1,%0,0"
2446   [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2447    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2448                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2449    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2450    (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2451
2452 (define_insn "*mov<mode>_64"
2453   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T,v,v,R")
2454         (match_operand:DD_DF 1 "general_operand"      " G,f,R,T,f,f,G,d,b,T,d,d,v,R,v"))]
2455   "TARGET_ZARCH"
2456   "@
2457    lzdr\t%0
2458    ldr\t%0,%1
2459    ld\t%0,%1
2460    ldy\t%0,%1
2461    std\t%1,%0
2462    stdy\t%1,%0
2463    lghi\t%0,0
2464    lgr\t%0,%1
2465    lgrl\t%0,%1
2466    lg\t%0,%1
2467    stgrl\t%1,%0
2468    stg\t%1,%0
2469    vlr\t%v0,%v1
2470    vleg\t%v0,%1,0
2471    vsteg\t%v1,%0,0"
2472   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2473    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2474                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2475    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2476    (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec")])
2477
2478 (define_insn "*mov<mode>_31"
2479   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2480                                "=f,f,f,f,R,T,d,d,Q,S,  d,o")
2481         (match_operand:DD_DF 1 "general_operand"
2482                                " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
2483   "!TARGET_ZARCH"
2484   "@
2485    lzdr\t%0
2486    ldr\t%0,%1
2487    ld\t%0,%1
2488    ldy\t%0,%1
2489    std\t%1,%0
2490    stdy\t%1,%0
2491    lm\t%0,%N0,%S1
2492    lmy\t%0,%N0,%S1
2493    stm\t%1,%N1,%S0
2494    stmy\t%1,%N1,%S0
2495    #
2496    #"
2497   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2498    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2499                         fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2500    (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
2501
2502 (define_split
2503   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2504         (match_operand:DD_DF 1 "general_operand" ""))]
2505   "!TARGET_ZARCH && reload_completed
2506    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2507   [(set (match_dup 2) (match_dup 4))
2508    (set (match_dup 3) (match_dup 5))]
2509 {
2510   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2511   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2512   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2513   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2514 })
2515
2516 (define_split
2517   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2518         (match_operand:DD_DF 1 "general_operand" ""))]
2519   "!TARGET_ZARCH && reload_completed
2520    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2521   [(set (match_dup 2) (match_dup 4))
2522    (set (match_dup 3) (match_dup 5))]
2523 {
2524   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2525   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2526   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2527   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2528 })
2529
2530 (define_split
2531   [(set (match_operand:DD_DF 0 "register_operand" "")
2532         (match_operand:DD_DF 1 "memory_operand" ""))]
2533   "!TARGET_ZARCH && reload_completed
2534    && !FP_REG_P (operands[0])
2535    && !s_operand (operands[1], VOIDmode)"
2536   [(set (match_dup 0) (match_dup 1))]
2537 {
2538   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2539   s390_load_address (addr, XEXP (operands[1], 0));
2540   operands[1] = replace_equiv_address (operands[1], addr);
2541 })
2542
2543 ;
2544 ; mov(sf|sd) instruction pattern(s).
2545 ;
2546
2547 (define_insn "mov<mode>"
2548   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2549                                "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
2550         (match_operand:SD_SF 1 "general_operand"
2551                                " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
2552   ""
2553   "@
2554    lzer\t%0
2555    ldr\t%0,%1
2556    ler\t%0,%1
2557    lde\t%0,%1
2558    le\t%0,%1
2559    ley\t%0,%1
2560    ste\t%1,%0
2561    stey\t%1,%0
2562    lhi\t%0,0
2563    lr\t%0,%1
2564    lrl\t%0,%1
2565    l\t%0,%1
2566    ly\t%0,%1
2567    strl\t%1,%0
2568    st\t%1,%0
2569    sty\t%1,%0
2570    vlr\t%v0,%v1
2571    vleif\t%v0,0
2572    vlvgf\t%v0,%1,0
2573    vlgvf\t%0,%v1,0
2574    vleg\t%0,%1,0
2575    vsteg\t%1,%0,0"
2576   [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2577    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2578                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2579    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2580    (set_attr "cpu_facility" "z196,vec,*,vec,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vec,vec,vec,vec,vec,vec")])
2581
2582 ;
2583 ; movcc instruction pattern
2584 ;
2585
2586 (define_insn "movcc"
2587   [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2588         (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2589   ""
2590   "@
2591    lr\t%0,%1
2592    tmh\t%1,12288
2593    ipm\t%0
2594    l\t%0,%1
2595    ly\t%0,%1
2596    st\t%1,%0
2597    sty\t%1,%0"
2598   [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2599    (set_attr "type" "lr,*,*,load,load,store,store")
2600    (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
2601    (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2602    (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2603
2604 ;
2605 ; Block move (MVC) patterns.
2606 ;
2607
2608 (define_insn "*mvc"
2609   [(set (match_operand:BLK 0 "memory_operand" "=Q")
2610         (match_operand:BLK 1 "memory_operand" "Q"))
2611    (use (match_operand 2 "const_int_operand" "n"))]
2612   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2613   "mvc\t%O0(%2,%R0),%S1"
2614   [(set_attr "op_type" "SS")])
2615
2616 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2617 ; order to have it implemented with mvc.
2618
2619 (define_split
2620   [(set (match_operand:QI 0 "memory_operand" "")
2621         (match_operand:QI 1 "memory_operand" ""))]
2622   "reload_completed"
2623   [(parallel
2624     [(set (match_dup 0) (match_dup 1))
2625      (use (const_int 1))])]
2626 {
2627   operands[0] = adjust_address (operands[0], BLKmode, 0);
2628   operands[1] = adjust_address (operands[1], BLKmode, 0);
2629 })
2630
2631
2632 (define_peephole2
2633   [(parallel
2634     [(set (match_operand:BLK 0 "memory_operand" "")
2635           (match_operand:BLK 1 "memory_operand" ""))
2636      (use (match_operand 2 "const_int_operand" ""))])
2637    (parallel
2638     [(set (match_operand:BLK 3 "memory_operand" "")
2639           (match_operand:BLK 4 "memory_operand" ""))
2640      (use (match_operand 5 "const_int_operand" ""))])]
2641   "s390_offset_p (operands[0], operands[3], operands[2])
2642    && s390_offset_p (operands[1], operands[4], operands[2])
2643    && !s390_overlap_p (operands[0], operands[1],
2644                        INTVAL (operands[2]) + INTVAL (operands[5]))
2645    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2646   [(parallel
2647     [(set (match_dup 6) (match_dup 7))
2648      (use (match_dup 8))])]
2649   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2650    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2651    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2652
2653
2654 ;
2655 ; load_multiple pattern(s).
2656 ;
2657 ; ??? Due to reload problems with replacing registers inside match_parallel
2658 ; we currently support load_multiple/store_multiple only after reload.
2659 ;
2660
2661 (define_expand "load_multiple"
2662   [(match_par_dup 3 [(set (match_operand 0 "" "")
2663                           (match_operand 1 "" ""))
2664                      (use (match_operand 2 "" ""))])]
2665   "reload_completed"
2666 {
2667   machine_mode mode;
2668   int regno;
2669   int count;
2670   rtx from;
2671   int i, off;
2672
2673   /* Support only loading a constant number of fixed-point registers from
2674      memory and only bother with this if more than two */
2675   if (GET_CODE (operands[2]) != CONST_INT
2676       || INTVAL (operands[2]) < 2
2677       || INTVAL (operands[2]) > 16
2678       || GET_CODE (operands[1]) != MEM
2679       || GET_CODE (operands[0]) != REG
2680       || REGNO (operands[0]) >= 16)
2681     FAIL;
2682
2683   count = INTVAL (operands[2]);
2684   regno = REGNO (operands[0]);
2685   mode = GET_MODE (operands[0]);
2686   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2687     FAIL;
2688
2689   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2690   if (!can_create_pseudo_p ())
2691     {
2692       if (GET_CODE (XEXP (operands[1], 0)) == REG)
2693         {
2694           from = XEXP (operands[1], 0);
2695           off = 0;
2696         }
2697       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2698                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2699                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2700         {
2701           from = XEXP (XEXP (operands[1], 0), 0);
2702           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2703         }
2704       else
2705         FAIL;
2706     }
2707   else
2708     {
2709       from = force_reg (Pmode, XEXP (operands[1], 0));
2710       off = 0;
2711     }
2712
2713   for (i = 0; i < count; i++)
2714     XVECEXP (operands[3], 0, i)
2715       = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2716                      change_address (operands[1], mode,
2717                        plus_constant (Pmode, from,
2718                                       off + i * GET_MODE_SIZE (mode))));
2719 })
2720
2721 (define_insn "*load_multiple_di"
2722   [(match_parallel 0 "load_multiple_operation"
2723                    [(set (match_operand:DI 1 "register_operand" "=r")
2724                          (match_operand:DI 2 "s_operand" "S"))])]
2725   "reload_completed && TARGET_ZARCH"
2726 {
2727   int words = XVECLEN (operands[0], 0);
2728   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2729   return "lmg\t%1,%0,%S2";
2730 }
2731    [(set_attr "op_type" "RSY")
2732     (set_attr "type"    "lm")])
2733
2734 (define_insn "*load_multiple_si"
2735   [(match_parallel 0 "load_multiple_operation"
2736                    [(set (match_operand:SI 1 "register_operand" "=r,r")
2737                          (match_operand:SI 2 "s_operand" "Q,S"))])]
2738   "reload_completed"
2739 {
2740   int words = XVECLEN (operands[0], 0);
2741   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2742   return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2743 }
2744    [(set_attr "op_type" "RS,RSY")
2745     (set_attr "cpu_facility" "*,longdisp")
2746     (set_attr "type"    "lm")])
2747
2748 ;
2749 ; store multiple pattern(s).
2750 ;
2751
2752 (define_expand "store_multiple"
2753   [(match_par_dup 3 [(set (match_operand 0 "" "")
2754                           (match_operand 1 "" ""))
2755                      (use (match_operand 2 "" ""))])]
2756   "reload_completed"
2757 {
2758   machine_mode mode;
2759   int regno;
2760   int count;
2761   rtx to;
2762   int i, off;
2763
2764   /* Support only storing a constant number of fixed-point registers to
2765      memory and only bother with this if more than two.  */
2766   if (GET_CODE (operands[2]) != CONST_INT
2767       || INTVAL (operands[2]) < 2
2768       || INTVAL (operands[2]) > 16
2769       || GET_CODE (operands[0]) != MEM
2770       || GET_CODE (operands[1]) != REG
2771       || REGNO (operands[1]) >= 16)
2772     FAIL;
2773
2774   count = INTVAL (operands[2]);
2775   regno = REGNO (operands[1]);
2776   mode = GET_MODE (operands[1]);
2777   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2778     FAIL;
2779
2780   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2781
2782   if (!can_create_pseudo_p ())
2783     {
2784       if (GET_CODE (XEXP (operands[0], 0)) == REG)
2785         {
2786           to = XEXP (operands[0], 0);
2787           off = 0;
2788         }
2789       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2790                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2791                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2792         {
2793           to = XEXP (XEXP (operands[0], 0), 0);
2794           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2795         }
2796       else
2797         FAIL;
2798     }
2799   else
2800     {
2801       to = force_reg (Pmode, XEXP (operands[0], 0));
2802       off = 0;
2803     }
2804
2805   for (i = 0; i < count; i++)
2806     XVECEXP (operands[3], 0, i)
2807       = gen_rtx_SET (change_address (operands[0], mode,
2808                        plus_constant (Pmode, to,
2809                                       off + i * GET_MODE_SIZE (mode))),
2810                      gen_rtx_REG (mode, regno + i));
2811 })
2812
2813 (define_insn "*store_multiple_di"
2814   [(match_parallel 0 "store_multiple_operation"
2815                    [(set (match_operand:DI 1 "s_operand" "=S")
2816                          (match_operand:DI 2 "register_operand" "r"))])]
2817   "reload_completed && TARGET_ZARCH"
2818 {
2819   int words = XVECLEN (operands[0], 0);
2820   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2821   return "stmg\t%2,%0,%S1";
2822 }
2823    [(set_attr "op_type" "RSY")
2824     (set_attr "type"    "stm")])
2825
2826
2827 (define_insn "*store_multiple_si"
2828   [(match_parallel 0 "store_multiple_operation"
2829                    [(set (match_operand:SI 1 "s_operand" "=Q,S")
2830                          (match_operand:SI 2 "register_operand" "r,r"))])]
2831   "reload_completed"
2832 {
2833   int words = XVECLEN (operands[0], 0);
2834   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2835   return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2836 }
2837    [(set_attr "op_type" "RS,RSY")
2838     (set_attr "cpu_facility" "*,longdisp")
2839     (set_attr "type"    "stm")])
2840
2841 ;;
2842 ;; String instructions.
2843 ;;
2844
2845 (define_insn "*execute_rl"
2846   [(match_parallel 0 "execute_operation"
2847     [(unspec [(match_operand 1    "register_operand" "a")
2848               (match_operand 2    "" "")
2849               (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2850   "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2851    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2852   "exrl\t%1,%3"
2853   [(set_attr "op_type" "RIL")
2854    (set_attr "type"    "cs")])
2855
2856 (define_insn "*execute"
2857   [(match_parallel 0 "execute_operation"
2858     [(unspec [(match_operand 1 "register_operand" "a")
2859               (match_operand:BLK 2 "memory_operand" "R")
2860               (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2861   "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2862    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2863   "ex\t%1,%2"
2864   [(set_attr "op_type" "RX")
2865    (set_attr "type" "cs")])
2866
2867
2868 ;
2869 ; strlenM instruction pattern(s).
2870 ;
2871
2872 (define_expand "strlen<mode>"
2873   [(match_operand:P   0 "register_operand" "")  ; result
2874    (match_operand:BLK 1 "memory_operand" "")    ; input string
2875    (match_operand:SI  2 "immediate_operand" "") ; search character
2876    (match_operand:SI  3 "immediate_operand" "")] ; known alignment
2877   ""
2878 {
2879   if (!TARGET_VX || operands[2] != const0_rtx)
2880     emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2881                                       operands[2], operands[3]));
2882   else
2883     s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2884
2885   DONE;
2886 })
2887
2888 (define_expand "strlen_srst<mode>"
2889   [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2890    (parallel
2891     [(set (match_dup 4)
2892           (unspec:P [(const_int 0)
2893                       (match_operand:BLK 1 "memory_operand" "")
2894                       (reg:SI 0)
2895                       (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2896      (clobber (scratch:P))
2897      (clobber (reg:CC CC_REGNUM))])
2898    (parallel
2899     [(set (match_operand:P 0 "register_operand" "")
2900           (minus:P (match_dup 4) (match_dup 5)))
2901      (clobber (reg:CC CC_REGNUM))])]
2902   ""
2903 {
2904   operands[4] = gen_reg_rtx (Pmode);
2905   operands[5] = gen_reg_rtx (Pmode);
2906   emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2907   operands[1] = replace_equiv_address (operands[1], operands[5]);
2908 })
2909
2910 (define_insn "*strlen<mode>"
2911   [(set (match_operand:P 0 "register_operand" "=a")
2912         (unspec:P [(match_operand:P 2 "general_operand" "0")
2913                     (mem:BLK (match_operand:P 3 "register_operand" "1"))
2914                     (reg:SI 0)
2915                     (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2916    (clobber (match_scratch:P 1 "=a"))
2917    (clobber (reg:CC CC_REGNUM))]
2918   ""
2919   "srst\t%0,%1\;jo\t.-4"
2920   [(set_attr "length" "8")
2921    (set_attr "type" "vs")])
2922
2923 ;
2924 ; cmpstrM instruction pattern(s).
2925 ;
2926
2927 (define_expand "cmpstrsi"
2928   [(set (reg:SI 0) (const_int 0))
2929    (parallel
2930     [(clobber (match_operand 3 "" ""))
2931      (clobber (match_dup 4))
2932      (set (reg:CCU CC_REGNUM)
2933           (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2934                        (match_operand:BLK 2 "memory_operand" "")))
2935      (use (reg:SI 0))])
2936    (parallel
2937     [(set (match_operand:SI 0 "register_operand" "=d")
2938           (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2939      (clobber (reg:CC CC_REGNUM))])]
2940   ""
2941 {
2942   /* As the result of CMPINT is inverted compared to what we need,
2943      we have to swap the operands.  */
2944   rtx op1 = operands[2];
2945   rtx op2 = operands[1];
2946   rtx addr1 = gen_reg_rtx (Pmode);
2947   rtx addr2 = gen_reg_rtx (Pmode);
2948
2949   emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2950   emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2951   operands[1] = replace_equiv_address_nv (op1, addr1);
2952   operands[2] = replace_equiv_address_nv (op2, addr2);
2953   operands[3] = addr1;
2954   operands[4] = addr2;
2955 })
2956
2957 (define_insn "*cmpstr<mode>"
2958   [(clobber (match_operand:P 0 "register_operand" "=d"))
2959    (clobber (match_operand:P 1 "register_operand" "=d"))
2960    (set (reg:CCU CC_REGNUM)
2961         (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2962                      (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2963    (use (reg:SI 0))]
2964   ""
2965   "clst\t%0,%1\;jo\t.-4"
2966   [(set_attr "length" "8")
2967    (set_attr "type" "vs")])
2968
2969 ;
2970 ; movstr instruction pattern.
2971 ;
2972
2973 (define_expand "movstr"
2974   [(match_operand 0 "register_operand" "")
2975    (match_operand 1 "memory_operand" "")
2976    (match_operand 2 "memory_operand" "")]
2977   ""
2978 {
2979   if (TARGET_64BIT)
2980     emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
2981   else
2982     emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
2983   DONE;
2984 })
2985
2986 (define_expand "movstr<P:mode>"
2987   [(set (reg:SI 0) (const_int 0))
2988    (parallel
2989     [(clobber (match_dup 3))
2990      (set (match_operand:BLK 1 "memory_operand" "")
2991           (match_operand:BLK 2 "memory_operand" ""))
2992      (set (match_operand:P 0 "register_operand" "")
2993           (unspec:P [(match_dup 1)
2994                    (match_dup 2)
2995                    (reg:SI 0)] UNSPEC_MVST))
2996      (clobber (reg:CC CC_REGNUM))])]
2997   ""
2998 {
2999   rtx addr1, addr2;
3000
3001   if (TARGET_VX && optimize_function_for_speed_p (cfun))
3002     {
3003       s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
3004       DONE;
3005     }
3006
3007   addr1 = gen_reg_rtx (Pmode);
3008   addr2 = gen_reg_rtx (Pmode);
3009
3010   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3011   emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
3012   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3013   operands[2] = replace_equiv_address_nv (operands[2], addr2);
3014   operands[3] = addr2;
3015 })
3016
3017 (define_insn "*movstr"
3018   [(clobber (match_operand:P 2 "register_operand" "=d"))
3019    (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
3020         (mem:BLK (match_operand:P 3 "register_operand" "2")))
3021    (set (match_operand:P 0 "register_operand" "=d")
3022         (unspec:P [(mem:BLK (match_dup 1))
3023                  (mem:BLK (match_dup 3))
3024                  (reg:SI 0)] UNSPEC_MVST))
3025    (clobber (reg:CC CC_REGNUM))]
3026   ""
3027   "mvst\t%1,%2\;jo\t.-4"
3028   [(set_attr "length" "8")
3029    (set_attr "type" "vs")])
3030
3031
3032 ;
3033 ; movmemM instruction pattern(s).
3034 ;
3035
3036 (define_expand "movmem<mode>"
3037   [(set (match_operand:BLK 0 "memory_operand" "")   ; destination
3038         (match_operand:BLK 1 "memory_operand" ""))  ; source
3039    (use (match_operand:GPR 2 "general_operand" "")) ; count
3040    (match_operand 3 "" "")]
3041   ""
3042 {
3043   if (s390_expand_movmem (operands[0], operands[1], operands[2]))
3044     DONE;
3045   else
3046     FAIL;
3047 })
3048
3049 ; Move a block that is up to 256 bytes in length.
3050 ; The block length is taken as (operands[2] % 256) + 1.
3051
3052 (define_expand "movmem_short"
3053   [(parallel
3054     [(set (match_operand:BLK 0 "memory_operand" "")
3055           (match_operand:BLK 1 "memory_operand" ""))
3056      (use (match_operand 2 "nonmemory_operand" ""))
3057      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3058      (clobber (match_dup 3))])]
3059   ""
3060   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3061
3062 (define_insn "*movmem_short"
3063   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3064         (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3065    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3066    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3067    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3068   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3069   "#"
3070   [(set_attr "type"         "cs")
3071    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3072
3073 (define_split
3074   [(set (match_operand:BLK 0 "memory_operand" "")
3075         (match_operand:BLK 1 "memory_operand" ""))
3076    (use (match_operand 2 "const_int_operand" ""))
3077    (use (match_operand 3 "immediate_operand" ""))
3078    (clobber (scratch))]
3079   "reload_completed"
3080   [(parallel
3081     [(set (match_dup 0) (match_dup 1))
3082      (use (match_dup 2))])]
3083   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3084
3085 (define_split
3086   [(set (match_operand:BLK 0 "memory_operand" "")
3087         (match_operand:BLK 1 "memory_operand" ""))
3088    (use (match_operand 2 "register_operand" ""))
3089    (use (match_operand 3 "memory_operand" ""))
3090    (clobber (scratch))]
3091   "reload_completed"
3092   [(parallel
3093     [(unspec [(match_dup 2) (match_dup 3)
3094               (const_int 0)] UNSPEC_EXECUTE)
3095      (set (match_dup 0) (match_dup 1))
3096      (use (const_int 1))])]
3097   "")
3098
3099 (define_split
3100   [(set (match_operand:BLK 0 "memory_operand" "")
3101         (match_operand:BLK 1 "memory_operand" ""))
3102    (use (match_operand 2 "register_operand" ""))
3103    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3104    (clobber (scratch))]
3105   "TARGET_Z10 && reload_completed"
3106   [(parallel
3107     [(unspec [(match_dup 2) (const_int 0)
3108               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3109      (set (match_dup 0) (match_dup 1))
3110      (use (const_int 1))])]
3111   "operands[3] = gen_label_rtx ();")
3112
3113 (define_split
3114   [(set (match_operand:BLK 0 "memory_operand" "")
3115         (match_operand:BLK 1 "memory_operand" ""))
3116    (use (match_operand 2 "register_operand" ""))
3117    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3118    (clobber (match_operand 3 "register_operand" ""))]
3119   "reload_completed && TARGET_CPU_ZARCH"
3120   [(set (match_dup 3) (label_ref (match_dup 4)))
3121    (parallel
3122     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3123               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3124      (set (match_dup 0) (match_dup 1))
3125      (use (const_int 1))])]
3126   "operands[4] = gen_label_rtx ();")
3127
3128 ; Move a block of arbitrary length.
3129
3130 (define_expand "movmem_long"
3131   [(parallel
3132     [(clobber (match_dup 2))
3133      (clobber (match_dup 3))
3134      (set (match_operand:BLK 0 "memory_operand" "")
3135           (match_operand:BLK 1 "memory_operand" ""))
3136      (use (match_operand 2 "general_operand" ""))
3137      (use (match_dup 3))
3138      (clobber (reg:CC CC_REGNUM))])]
3139   ""
3140 {
3141   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3142   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3143   rtx reg0 = gen_reg_rtx (dreg_mode);
3144   rtx reg1 = gen_reg_rtx (dreg_mode);
3145   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3146   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3147   rtx len0 = gen_lowpart (Pmode, reg0);
3148   rtx len1 = gen_lowpart (Pmode, reg1);
3149
3150   emit_clobber (reg0);
3151   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3152   emit_move_insn (len0, operands[2]);
3153
3154   emit_clobber (reg1);
3155   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3156   emit_move_insn (len1, operands[2]);
3157
3158   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3159   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3160   operands[2] = reg0;
3161   operands[3] = reg1;
3162 })
3163
3164 (define_insn "*movmem_long"
3165   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3166    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3167    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3168         (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3169    (use (match_dup 2))
3170    (use (match_dup 3))
3171    (clobber (reg:CC CC_REGNUM))]
3172   "TARGET_64BIT || !TARGET_ZARCH"
3173   "mvcle\t%0,%1,0\;jo\t.-4"
3174   [(set_attr "length" "8")
3175    (set_attr "type" "vs")])
3176
3177 (define_insn "*movmem_long_31z"
3178   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3179    (clobber (match_operand:TI 1 "register_operand" "=d"))
3180    (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3181         (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3182    (use (match_dup 2))
3183    (use (match_dup 3))
3184    (clobber (reg:CC CC_REGNUM))]
3185   "!TARGET_64BIT && TARGET_ZARCH"
3186   "mvcle\t%0,%1,0\;jo\t.-4"
3187   [(set_attr "length" "8")
3188    (set_attr "type" "vs")])
3189
3190
3191 ;
3192 ; Test data class.
3193 ;
3194
3195 (define_expand "signbit<mode>2"
3196   [(set (reg:CCZ CC_REGNUM)
3197         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3198                      (match_dup 2)]
3199                      UNSPEC_TDC_INSN))
3200    (set (match_operand:SI 0 "register_operand" "=d")
3201         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3202   "TARGET_HARD_FLOAT"
3203 {
3204   operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3205 })
3206
3207 (define_expand "isinf<mode>2"
3208   [(set (reg:CCZ CC_REGNUM)
3209         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3210                      (match_dup 2)]
3211                      UNSPEC_TDC_INSN))
3212    (set (match_operand:SI 0 "register_operand" "=d")
3213         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3214   "TARGET_HARD_FLOAT"
3215 {
3216   operands[2] = GEN_INT (S390_TDC_INFINITY);
3217 })
3218
3219 ; This extracts CC into a GPR properly shifted.  The actual IPM
3220 ; instruction will be issued by reload.  The constraint of operand 1
3221 ; forces reload to use a GPR.  So reload will issue a movcc insn for
3222 ; copying CC into a GPR first.
3223 (define_insn_and_split "*cc_to_int"
3224   [(set (match_operand:SI 0 "nonimmediate_operand"     "=d")
3225         (unspec:SI [(match_operand 1 "register_operand" "0")]
3226                    UNSPEC_CC_TO_INT))]
3227   "operands != NULL"
3228   "#"
3229   "reload_completed"
3230   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3231
3232 ; This insn is used to generate all variants of the Test Data Class
3233 ; instruction, namely tcxb, tcdb, and tceb.  The insn's first operand
3234 ; is the register to be tested and the second one is the bit mask
3235 ; specifying the required test(s).
3236 ;
3237 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3238 (define_insn "*TDC_insn_<mode>"
3239   [(set (reg:CCZ CC_REGNUM)
3240         (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3241                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3242   "TARGET_HARD_FLOAT"
3243   "t<_d>c<xde><bt>\t%0,%1"
3244    [(set_attr "op_type" "RXE")
3245     (set_attr "type"  "fsimp<mode>")])
3246
3247
3248
3249 ;
3250 ; setmemM instruction pattern(s).
3251 ;
3252
3253 (define_expand "setmem<mode>"
3254   [(set (match_operand:BLK 0 "memory_operand" "")
3255         (match_operand:QI 2 "general_operand" ""))
3256    (use (match_operand:GPR 1 "general_operand" ""))
3257    (match_operand 3 "" "")]
3258   ""
3259   "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3260
3261 ; Clear a block that is up to 256 bytes in length.
3262 ; The block length is taken as (operands[1] % 256) + 1.
3263
3264 (define_expand "clrmem_short"
3265   [(parallel
3266     [(set (match_operand:BLK 0 "memory_operand" "")
3267           (const_int 0))
3268      (use (match_operand 1 "nonmemory_operand" ""))
3269      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3270      (clobber (match_dup 2))
3271      (clobber (reg:CC CC_REGNUM))])]
3272   ""
3273   "operands[2] = gen_rtx_SCRATCH (Pmode);")
3274
3275 (define_insn "*clrmem_short"
3276   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3277         (const_int 0))
3278    (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3279    (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3280    (clobber (match_scratch:P 3 "=X,X,X,&a"))
3281    (clobber (reg:CC CC_REGNUM))]
3282   "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3283   "#"
3284   [(set_attr "type" "cs")
3285    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3286
3287 (define_split
3288   [(set (match_operand:BLK 0 "memory_operand" "")
3289         (const_int 0))
3290    (use (match_operand 1 "const_int_operand" ""))
3291    (use (match_operand 2 "immediate_operand" ""))
3292    (clobber (scratch))
3293    (clobber (reg:CC CC_REGNUM))]
3294   "reload_completed"
3295   [(parallel
3296     [(set (match_dup 0) (const_int 0))
3297      (use (match_dup 1))
3298      (clobber (reg:CC CC_REGNUM))])]
3299   "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3300
3301 (define_split
3302   [(set (match_operand:BLK 0 "memory_operand" "")
3303         (const_int 0))
3304    (use (match_operand 1 "register_operand" ""))
3305    (use (match_operand 2 "memory_operand" ""))
3306    (clobber (scratch))
3307    (clobber (reg:CC CC_REGNUM))]
3308   "reload_completed"
3309   [(parallel
3310     [(unspec [(match_dup 1) (match_dup 2)
3311               (const_int 0)] UNSPEC_EXECUTE)
3312      (set (match_dup 0) (const_int 0))
3313      (use (const_int 1))
3314      (clobber (reg:CC CC_REGNUM))])]
3315   "")
3316
3317 (define_split
3318   [(set (match_operand:BLK 0 "memory_operand" "")
3319         (const_int 0))
3320    (use (match_operand 1 "register_operand" ""))
3321    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3322    (clobber (scratch))
3323    (clobber (reg:CC CC_REGNUM))]
3324   "TARGET_Z10 && reload_completed"
3325   [(parallel
3326     [(unspec [(match_dup 1) (const_int 0)
3327               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3328      (set (match_dup 0) (const_int 0))
3329      (use (const_int 1))
3330      (clobber (reg:CC CC_REGNUM))])]
3331   "operands[3] = gen_label_rtx ();")
3332
3333 (define_split
3334   [(set (match_operand:BLK 0 "memory_operand" "")
3335         (const_int 0))
3336    (use (match_operand 1 "register_operand" ""))
3337    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3338    (clobber (match_operand 2 "register_operand" ""))
3339    (clobber (reg:CC CC_REGNUM))]
3340   "reload_completed && TARGET_CPU_ZARCH"
3341   [(set (match_dup 2) (label_ref (match_dup 3)))
3342    (parallel
3343     [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3344               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3345      (set (match_dup 0) (const_int 0))
3346      (use (const_int 1))
3347      (clobber (reg:CC CC_REGNUM))])]
3348   "operands[3] = gen_label_rtx ();")
3349
3350 ; Initialize a block of arbitrary length with (operands[2] % 256).
3351
3352 (define_expand "setmem_long_<P:mode>"
3353   [(parallel
3354     [(clobber (match_dup 1))
3355      (set (match_operand:BLK 0 "memory_operand" "")
3356           (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
3357                       (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3358      (use (match_dup 3))
3359      (clobber (reg:CC CC_REGNUM))])]
3360   ""
3361 {
3362   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3363   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3364   rtx reg0 = gen_reg_rtx (dreg_mode);
3365   rtx reg1 = gen_reg_rtx (dreg_mode);
3366   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3367   rtx len0 = gen_lowpart (Pmode, reg0);
3368
3369   emit_clobber (reg0);
3370   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3371   emit_move_insn (len0, operands[1]);
3372
3373   emit_move_insn (reg1, const0_rtx);
3374
3375   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3376   operands[1] = reg0;
3377   operands[3] = reg1;
3378   operands[4] = gen_lowpart (Pmode, operands[1]);
3379 })
3380
3381 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3382
3383 (define_insn "*setmem_long"
3384   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3385    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3386         (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
3387                      (subreg:P (match_dup 3) <modesize>)]
3388                      UNSPEC_REPLICATE_BYTE))
3389    (use (match_operand:<DBL> 1 "register_operand" "d"))
3390    (clobber (reg:CC CC_REGNUM))]
3391   "TARGET_64BIT || !TARGET_ZARCH"
3392   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3393   [(set_attr "length" "8")
3394    (set_attr "type" "vs")])
3395
3396 (define_insn "*setmem_long_and"
3397   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3398    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3399         (unspec:BLK [(and:P
3400                       (match_operand:P 2 "setmem_operand" "Y")
3401                       (match_operand:P 4 "const_int_operand"             "n"))
3402                     (subreg:P (match_dup 3) <modesize>)]
3403                     UNSPEC_REPLICATE_BYTE))
3404    (use (match_operand:<DBL> 1 "register_operand" "d"))
3405    (clobber (reg:CC CC_REGNUM))]
3406   "(TARGET_64BIT || !TARGET_ZARCH) &&
3407    (INTVAL (operands[4]) & 255) == 255"
3408   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3409   [(set_attr "length" "8")
3410    (set_attr "type" "vs")])
3411
3412 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3413 ; of the SImode subregs.
3414
3415 (define_insn "*setmem_long_31z"
3416   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3417    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3418         (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
3419                      (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3420    (use (match_operand:TI 1 "register_operand" "d"))
3421    (clobber (reg:CC CC_REGNUM))]
3422   "!TARGET_64BIT && TARGET_ZARCH"
3423   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3424   [(set_attr "length" "8")
3425    (set_attr "type" "vs")])
3426
3427 (define_insn "*setmem_long_and_31z"
3428   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3429    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3430         (unspec:BLK [(and:SI
3431                       (match_operand:SI 2 "setmem_operand" "Y")
3432                       (match_operand:SI 4 "const_int_operand" "n"))
3433                     (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3434    (use (match_operand:TI 1 "register_operand" "d"))
3435    (clobber (reg:CC CC_REGNUM))]
3436   "(!TARGET_64BIT && TARGET_ZARCH) &&
3437    (INTVAL (operands[4]) & 255) == 255"
3438   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3439   [(set_attr "length" "8")
3440    (set_attr "type" "vs")])
3441
3442 ;
3443 ; cmpmemM instruction pattern(s).
3444 ;
3445
3446 (define_expand "cmpmemsi"
3447   [(set (match_operand:SI 0 "register_operand" "")
3448         (compare:SI (match_operand:BLK 1 "memory_operand" "")
3449                     (match_operand:BLK 2 "memory_operand" "") ) )
3450    (use (match_operand:SI 3 "general_operand" ""))
3451    (use (match_operand:SI 4 "" ""))]
3452   ""
3453 {
3454   if (s390_expand_cmpmem (operands[0], operands[1],
3455                           operands[2], operands[3]))
3456     DONE;
3457   else
3458     FAIL;
3459 })
3460
3461 ; Compare a block that is up to 256 bytes in length.
3462 ; The block length is taken as (operands[2] % 256) + 1.
3463
3464 (define_expand "cmpmem_short"
3465   [(parallel
3466     [(set (reg:CCU CC_REGNUM)
3467           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3468                        (match_operand:BLK 1 "memory_operand" "")))
3469      (use (match_operand 2 "nonmemory_operand" ""))
3470      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3471      (clobber (match_dup 3))])]
3472   ""
3473   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3474
3475 (define_insn "*cmpmem_short"
3476   [(set (reg:CCU CC_REGNUM)
3477         (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3478                      (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3479    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3480    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3481    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3482   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3483   "#"
3484   [(set_attr "type" "cs")
3485    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3486
3487 (define_split
3488   [(set (reg:CCU CC_REGNUM)
3489         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3490                      (match_operand:BLK 1 "memory_operand" "")))
3491    (use (match_operand 2 "const_int_operand" ""))
3492    (use (match_operand 3 "immediate_operand" ""))
3493    (clobber (scratch))]
3494   "reload_completed"
3495   [(parallel
3496     [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3497      (use (match_dup 2))])]
3498   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3499
3500 (define_split
3501   [(set (reg:CCU CC_REGNUM)
3502         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3503                      (match_operand:BLK 1 "memory_operand" "")))
3504    (use (match_operand 2 "register_operand" ""))
3505    (use (match_operand 3 "memory_operand" ""))
3506    (clobber (scratch))]
3507   "reload_completed"
3508   [(parallel
3509     [(unspec [(match_dup 2) (match_dup 3)
3510               (const_int 0)] UNSPEC_EXECUTE)
3511      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3512      (use (const_int 1))])]
3513   "")
3514
3515 (define_split
3516   [(set (reg:CCU CC_REGNUM)
3517         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3518                      (match_operand:BLK 1 "memory_operand" "")))
3519    (use (match_operand 2 "register_operand" ""))
3520    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3521    (clobber (scratch))]
3522   "TARGET_Z10 && reload_completed"
3523   [(parallel
3524     [(unspec [(match_dup 2) (const_int 0)
3525               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3526      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3527      (use (const_int 1))])]
3528   "operands[4] = gen_label_rtx ();")
3529
3530 (define_split
3531   [(set (reg:CCU CC_REGNUM)
3532         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3533                      (match_operand:BLK 1 "memory_operand" "")))
3534    (use (match_operand 2 "register_operand" ""))
3535    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3536    (clobber (match_operand 3 "register_operand" ""))]
3537   "reload_completed && TARGET_CPU_ZARCH"
3538   [(set (match_dup 3) (label_ref (match_dup 4)))
3539    (parallel
3540     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3541               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3542      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3543      (use (const_int 1))])]
3544   "operands[4] = gen_label_rtx ();")
3545
3546 ; Compare a block of arbitrary length.
3547
3548 (define_expand "cmpmem_long"
3549   [(parallel
3550     [(clobber (match_dup 2))
3551      (clobber (match_dup 3))
3552      (set (reg:CCU CC_REGNUM)
3553           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3554                        (match_operand:BLK 1 "memory_operand" "")))
3555      (use (match_operand 2 "general_operand" ""))
3556      (use (match_dup 3))])]
3557   ""
3558 {
3559   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3560   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3561   rtx reg0 = gen_reg_rtx (dreg_mode);
3562   rtx reg1 = gen_reg_rtx (dreg_mode);
3563   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3564   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3565   rtx len0 = gen_lowpart (Pmode, reg0);
3566   rtx len1 = gen_lowpart (Pmode, reg1);
3567
3568   emit_clobber (reg0);
3569   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3570   emit_move_insn (len0, operands[2]);
3571
3572   emit_clobber (reg1);
3573   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3574   emit_move_insn (len1, operands[2]);
3575
3576   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3577   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3578   operands[2] = reg0;
3579   operands[3] = reg1;
3580 })
3581
3582 (define_insn "*cmpmem_long"
3583   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3584    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3585    (set (reg:CCU CC_REGNUM)
3586         (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3587                      (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3588    (use (match_dup 2))
3589    (use (match_dup 3))]
3590   "TARGET_64BIT || !TARGET_ZARCH"
3591   "clcle\t%0,%1,0\;jo\t.-4"
3592   [(set_attr "length" "8")
3593    (set_attr "type" "vs")])
3594
3595 (define_insn "*cmpmem_long_31z"
3596   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3597    (clobber (match_operand:TI 1 "register_operand" "=d"))
3598    (set (reg:CCU CC_REGNUM)
3599         (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3600                      (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3601    (use (match_dup 2))
3602    (use (match_dup 3))]
3603   "!TARGET_64BIT && TARGET_ZARCH"
3604   "clcle\t%0,%1,0\;jo\t.-4"
3605   [(set_attr "op_type" "NN")
3606    (set_attr "type"    "vs")
3607    (set_attr "length"  "8")])
3608
3609 ; Convert CCUmode condition code to integer.
3610 ; Result is zero if EQ, positive if LTU, negative if GTU.
3611
3612 (define_insn_and_split "cmpint"
3613   [(set (match_operand:SI 0 "register_operand" "=d")
3614         (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3615                    UNSPEC_STRCMPCC_TO_INT))
3616    (clobber (reg:CC CC_REGNUM))]
3617   ""
3618   "#"
3619   "reload_completed"
3620   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3621    (parallel
3622     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3623      (clobber (reg:CC CC_REGNUM))])])
3624
3625 (define_insn_and_split "*cmpint_cc"
3626   [(set (reg CC_REGNUM)
3627         (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3628                             UNSPEC_STRCMPCC_TO_INT)
3629                  (const_int 0)))
3630    (set (match_operand:SI 0 "register_operand" "=d")
3631         (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3632   "s390_match_ccmode (insn, CCSmode)"
3633   "#"
3634   "&& reload_completed"
3635   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3636    (parallel
3637     [(set (match_dup 2) (match_dup 3))
3638      (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3639 {
3640   rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3641   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3642   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3643 })
3644
3645 (define_insn_and_split "*cmpint_sign"
3646   [(set (match_operand:DI 0 "register_operand" "=d")
3647         (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3648                                    UNSPEC_STRCMPCC_TO_INT)))
3649    (clobber (reg:CC CC_REGNUM))]
3650   "TARGET_ZARCH"
3651   "#"
3652   "&& reload_completed"
3653   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3654    (parallel
3655     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3656      (clobber (reg:CC CC_REGNUM))])])
3657
3658 (define_insn_and_split "*cmpint_sign_cc"
3659   [(set (reg CC_REGNUM)
3660         (compare (ashiftrt:DI (ashift:DI (subreg:DI
3661                    (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3662                               UNSPEC_STRCMPCC_TO_INT) 0)
3663                    (const_int 32)) (const_int 32))
3664                  (const_int 0)))
3665    (set (match_operand:DI 0 "register_operand" "=d")
3666         (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3667   "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3668   "#"
3669   "&& reload_completed"
3670   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3671    (parallel
3672     [(set (match_dup 2) (match_dup 3))
3673      (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3674 {
3675   rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3676   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3677   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3678 })
3679
3680
3681 ;;
3682 ;;- Conversion instructions.
3683 ;;
3684
3685 (define_insn "*sethighpartsi"
3686   [(set (match_operand:SI 0 "register_operand" "=d,d")
3687         (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3688                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3689    (clobber (reg:CC CC_REGNUM))]
3690   ""
3691   "@
3692    icm\t%0,%2,%S1
3693    icmy\t%0,%2,%S1"
3694   [(set_attr "op_type" "RS,RSY")
3695    (set_attr "cpu_facility" "*,longdisp")
3696    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3697
3698 (define_insn "*sethighpartdi_64"
3699   [(set (match_operand:DI 0 "register_operand" "=d")
3700         (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
3701                     (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3702    (clobber (reg:CC CC_REGNUM))]
3703   "TARGET_ZARCH"
3704   "icmh\t%0,%2,%S1"
3705   [(set_attr "op_type" "RSY")
3706    (set_attr "z10prop" "z10_super")])
3707
3708 (define_insn "*sethighpartdi_31"
3709   [(set (match_operand:DI 0 "register_operand" "=d,d")
3710         (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3711                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3712    (clobber (reg:CC CC_REGNUM))]
3713   "!TARGET_ZARCH"
3714   "@
3715    icm\t%0,%2,%S1
3716    icmy\t%0,%2,%S1"
3717   [(set_attr "op_type" "RS,RSY")
3718    (set_attr "cpu_facility" "*,longdisp")
3719    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3720
3721 ;
3722 ; extv instruction patterns
3723 ;
3724
3725 ; FIXME: This expander needs to be converted from DI to GPR as well
3726 ; after resolving some issues with it.
3727
3728 (define_expand "extzv"
3729   [(parallel
3730     [(set (match_operand:DI 0 "register_operand" "=d")
3731         (zero_extract:DI
3732          (match_operand:DI 1 "register_operand" "d")
3733          (match_operand 2 "const_int_operand" "")   ; size
3734          (match_operand 3 "const_int_operand" ""))) ; start
3735      (clobber (reg:CC CC_REGNUM))])]
3736   "TARGET_Z10"
3737 {
3738   /* Starting with zEC12 there is risbgn not clobbering CC.  */
3739   if (TARGET_ZEC12)
3740     {
3741       emit_move_insn (operands[0],
3742                     gen_rtx_ZERO_EXTRACT (DImode,
3743                                           operands[1],
3744                                           operands[2],
3745                                           operands[3]));
3746       DONE;
3747     }
3748 })
3749
3750 (define_insn "*extzv<mode>_zEC12"
3751   [(set (match_operand:GPR 0 "register_operand" "=d")
3752       (zero_extract:GPR
3753         (match_operand:GPR 1 "register_operand" "d")
3754         (match_operand 2 "const_int_operand" "")   ; size
3755         (match_operand 3 "const_int_operand" "")))] ; start]
3756   "TARGET_ZEC12"
3757   "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3758   [(set_attr "op_type" "RIE")])
3759
3760 (define_insn "*extzv<mode>_z10"
3761   [(set (match_operand:GPR 0 "register_operand" "=d")
3762       (zero_extract:GPR
3763        (match_operand:GPR 1 "register_operand" "d")
3764        (match_operand 2 "const_int_operand" "")   ; size
3765        (match_operand 3 "const_int_operand" ""))) ; start
3766    (clobber (reg:CC CC_REGNUM))]
3767   "TARGET_Z10"
3768   "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3769   [(set_attr "op_type" "RIE")
3770    (set_attr "z10prop" "z10_super_E1")])
3771
3772 (define_insn_and_split "*pre_z10_extzv<mode>"
3773   [(set (match_operand:GPR 0 "register_operand" "=d")
3774         (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
3775                           (match_operand 2 "nonzero_shift_count_operand" "")
3776                           (const_int 0)))
3777    (clobber (reg:CC CC_REGNUM))]
3778   "!TARGET_Z10"
3779   "#"
3780   "&& reload_completed"
3781   [(parallel
3782     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3783      (clobber (reg:CC CC_REGNUM))])
3784    (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3785 {
3786   int bitsize = INTVAL (operands[2]);
3787   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3788   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3789
3790   operands[1] = adjust_address (operands[1], BLKmode, 0);
3791   set_mem_size (operands[1], size);
3792   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3793   operands[3] = GEN_INT (mask);
3794 })
3795
3796 (define_insn_and_split "*pre_z10_extv<mode>"
3797   [(set (match_operand:GPR 0 "register_operand" "=d")
3798         (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
3799                           (match_operand 2 "nonzero_shift_count_operand" "")
3800                           (const_int 0)))
3801    (clobber (reg:CC CC_REGNUM))]
3802   ""
3803   "#"
3804   "&& reload_completed"
3805   [(parallel
3806     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3807      (clobber (reg:CC CC_REGNUM))])
3808    (parallel
3809     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3810      (clobber (reg:CC CC_REGNUM))])]
3811 {
3812   int bitsize = INTVAL (operands[2]);
3813   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3814   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3815
3816   operands[1] = adjust_address (operands[1], BLKmode, 0);
3817   set_mem_size (operands[1], size);
3818   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3819   operands[3] = GEN_INT (mask);
3820 })
3821
3822 ;
3823 ; insv instruction patterns
3824 ;
3825
3826 (define_expand "insv"
3827   [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3828                       (match_operand 1 "const_int_operand" "")
3829                       (match_operand 2 "const_int_operand" ""))
3830         (match_operand 3 "general_operand" ""))]
3831   ""
3832 {
3833   if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3834     DONE;
3835   FAIL;
3836 })
3837
3838
3839 ; The normal RTL expansion will never generate a zero_extract where
3840 ; the location operand isn't word mode.  However, we do this in the
3841 ; back-end when generating atomic operations. See s390_two_part_insv.
3842 (define_insn "*insv<mode>_zEC12"
3843   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3844                           (match_operand 1 "const_int_operand"    "I")  ; size
3845                           (match_operand 2 "const_int_operand"    "I")) ; pos
3846         (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3847   "TARGET_ZEC12
3848    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3849   "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3850   [(set_attr "op_type" "RIE")])
3851
3852 (define_insn "*insv<mode>_z10"
3853   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3854                           (match_operand 1 "const_int_operand"    "I")  ; size
3855                           (match_operand 2 "const_int_operand"    "I")) ; pos
3856         (match_operand:GPR 3 "nonimmediate_operand" "d"))
3857    (clobber (reg:CC CC_REGNUM))]
3858   "TARGET_Z10
3859    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3860   "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3861   [(set_attr "op_type" "RIE")
3862    (set_attr "z10prop" "z10_super_E1")])
3863
3864 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3865 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3866 (define_insn "*insv<mode>_zEC12_noshift"
3867   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3868         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3869                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3870                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3871                           (match_operand:GPR 4 "const_int_operand" ""))))]
3872   "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3873   "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3874   [(set_attr "op_type" "RIE")])
3875
3876 (define_insn "*insv<mode>_z10_noshift"
3877   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3878         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3879                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3880                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3881                           (match_operand:GPR 4 "const_int_operand" ""))))
3882    (clobber (reg:CC CC_REGNUM))]
3883   "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3884   "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3885   [(set_attr "op_type" "RIE")
3886    (set_attr "z10prop" "z10_super_E1")])
3887
3888 ; Implement appending Y on the left of S bits of X
3889 ; x = (y << s) | (x & ((1 << s) - 1))
3890 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3891   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3892         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3893                           (match_operand:GPR 2 "immediate_operand" ""))
3894                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3895                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3896   "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3897   "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3898   [(set_attr "op_type" "RIE")
3899    (set_attr "z10prop" "z10_super_E1")])
3900
3901 (define_insn "*insv<mode>_z10_appendbitsleft"
3902   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3903         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3904                           (match_operand:GPR 2 "immediate_operand" ""))
3905                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3906                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3907    (clobber (reg:CC CC_REGNUM))]
3908   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3909   "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3910   [(set_attr "op_type" "RIE")
3911    (set_attr "z10prop" "z10_super_E1")])
3912
3913 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3914 ;  -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3915 ;  -> z = y >> d; z = risbg;
3916
3917 (define_split
3918   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3919         (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3920                                (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3921                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3922                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3923   "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3924   [(set (match_dup 6)
3925         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3926    (set (match_dup 0)
3927         (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3928                  (ashift:GPR (match_dup 3) (match_dup 4))))]
3929 {
3930   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3931   if (reg_overlap_mentioned_p (operands[0], operands[3]))
3932     {
3933       if (!can_create_pseudo_p ())
3934         FAIL;
3935       operands[6] = gen_reg_rtx (<MODE>mode);
3936     }
3937   else
3938     operands[6] = operands[0];
3939 })
3940
3941 (define_split
3942   [(parallel
3943     [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3944           (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3945                                  (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3946                    (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3947                                (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3948      (clobber (reg:CC CC_REGNUM))])]
3949   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3950   [(set (match_dup 6)
3951         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3952    (parallel
3953     [(set (match_dup 0)
3954           (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3955                    (ashift:GPR (match_dup 3) (match_dup 4))))
3956      (clobber (reg:CC CC_REGNUM))])]
3957 {
3958   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3959   if (reg_overlap_mentioned_p (operands[0], operands[3]))
3960     {
3961       if (!can_create_pseudo_p ())
3962         FAIL;
3963       operands[6] = gen_reg_rtx (<MODE>mode);
3964     }
3965   else
3966     operands[6] = operands[0];
3967 })
3968
3969 (define_insn "*r<noxa>sbg_<mode>_noshift"
3970   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3971         (IXOR:GPR
3972           (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3973                    (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3974           (match_operand:GPR 3 "nonimmediate_operand" "0")))
3975    (clobber (reg:CC CC_REGNUM))]
3976   "TARGET_Z10"
3977   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3978   [(set_attr "op_type" "RIE")])
3979
3980 (define_insn "*r<noxa>sbg_di_rotl"
3981   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3982         (IXOR:DI
3983           (and:DI
3984             (rotate:DI
3985               (match_operand:DI 1 "nonimmediate_operand" "d")
3986               (match_operand:DI 3 "const_int_operand" ""))
3987             (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3988           (match_operand:DI 4 "nonimmediate_operand" "0")))
3989    (clobber (reg:CC CC_REGNUM))]
3990   "TARGET_Z10"
3991   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3992   [(set_attr "op_type" "RIE")])
3993
3994 (define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
3995   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3996         (IXOR:GPR
3997           (and:GPR
3998             (lshiftrt:GPR
3999               (match_operand:GPR 1 "nonimmediate_operand" "d")
4000               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4001             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4002           (match_operand:GPR 4 "nonimmediate_operand" "0")))
4003    (clobber (reg:CC CC_REGNUM))]
4004   "TARGET_Z10
4005    && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
4006                            INTVAL (operands[2]))"
4007   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
4008   [(set_attr "op_type" "RIE")])
4009
4010 (define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
4011   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4012         (IXOR:GPR
4013           (and:GPR
4014             (ashift:GPR
4015               (match_operand:GPR 1 "nonimmediate_operand" "d")
4016               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4017             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4018           (match_operand:GPR 4 "nonimmediate_operand" "0")))
4019    (clobber (reg:CC CC_REGNUM))]
4020   "TARGET_Z10
4021    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
4022                            INTVAL (operands[2]))"
4023   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
4024   [(set_attr "op_type" "RIE")])
4025
4026 ;; unsigned {int,long} a, b
4027 ;; a = a | (b << const_int)
4028 ;; a = a ^ (b << const_int)
4029 (define_insn "*r<noxa>sbg_<mode>_sll"
4030   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4031         (IXOR:GPR
4032           (ashift:GPR
4033             (match_operand:GPR 1 "nonimmediate_operand" "d")
4034             (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4035           (match_operand:GPR 3 "nonimmediate_operand" "0")))
4036    (clobber (reg:CC CC_REGNUM))]
4037   "TARGET_Z10"
4038   "r<noxa>sbg\t%0,%1,64-<bitsize>,63-%2,%2"
4039   [(set_attr "op_type" "RIE")])
4040
4041 ;; unsigned {int,long} a, b
4042 ;; a = a | (b >> const_int)
4043 ;; a = a ^ (b >> const_int)
4044 (define_insn "*r<noxa>sbg_<mode>_srl"
4045   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4046         (IXOR:GPR
4047           (lshiftrt:GPR
4048             (match_operand:GPR 1 "nonimmediate_operand" "d")
4049             (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4050           (match_operand:GPR 3 "nonimmediate_operand" "0")))
4051    (clobber (reg:CC CC_REGNUM))]
4052   "TARGET_Z10"
4053   "r<noxa>sbg\t%0,%1,64-<bitsize>+%2,63,64-%2"
4054   [(set_attr "op_type" "RIE")])
4055
4056 ;; These two are generated by combine for s.bf &= val.
4057 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
4058 ;; shifts and ands, which results in some truly awful patterns
4059 ;; including subregs of operations.  Rather unnecessisarily, IMO.
4060 ;; Instead of
4061 ;;
4062 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4063 ;;        (const_int 24 [0x18])
4064 ;;        (const_int 0 [0]))
4065 ;;    (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
4066 ;;                    (const_int 40 [0x28])) 4)
4067 ;;            (reg:SI 4 %r4 [ y+4 ])) 0))
4068 ;;
4069 ;; we should instead generate
4070 ;;
4071 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4072 ;;        (const_int 24 [0x18])
4073 ;;        (const_int 0 [0]))
4074 ;;    (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
4075 ;;                    (const_int 40 [0x28]))
4076 ;;            (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
4077 ;;
4078 ;; by noticing that we can push down the outer paradoxical subreg
4079 ;; into the operation.
4080
4081 (define_insn "*insv_rnsbg_noshift"
4082   [(set (zero_extract:DI
4083           (match_operand:DI 0 "nonimmediate_operand" "+d")
4084           (match_operand 1 "const_int_operand" "")
4085           (match_operand 2 "const_int_operand" ""))
4086         (and:DI
4087           (match_dup 0)
4088           (match_operand:DI 3 "nonimmediate_operand" "d")))
4089    (clobber (reg:CC CC_REGNUM))]
4090   "TARGET_Z10
4091    && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4092   "rnsbg\t%0,%3,%2,63,0"
4093   [(set_attr "op_type" "RIE")])
4094
4095 (define_insn "*insv_rnsbg_srl"
4096   [(set (zero_extract:DI
4097           (match_operand:DI 0 "nonimmediate_operand" "+d")
4098           (match_operand 1 "const_int_operand" "")
4099           (match_operand 2 "const_int_operand" ""))
4100         (and:DI
4101           (lshiftrt:DI
4102             (match_dup 0)
4103             (match_operand 3 "const_int_operand" ""))
4104           (match_operand:DI 4 "nonimmediate_operand" "d")))
4105    (clobber (reg:CC CC_REGNUM))]
4106   "TARGET_Z10
4107    && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4108   "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4109   [(set_attr "op_type" "RIE")])
4110
4111 (define_insn "*insv<mode>_mem_reg"
4112   [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4113                         (match_operand 1 "const_int_operand" "n,n")
4114                         (const_int 0))
4115         (match_operand:W 2 "register_operand" "d,d"))]
4116   "INTVAL (operands[1]) > 0
4117    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4118    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4119 {
4120     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4121
4122     operands[1] = GEN_INT ((1ul << size) - 1);
4123     return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4124                                     : "stcmy\t%2,%1,%S0";
4125 }
4126   [(set_attr "op_type" "RS,RSY")
4127    (set_attr "cpu_facility" "*,longdisp")
4128    (set_attr "z10prop" "z10_super,z10_super")])
4129
4130 (define_insn "*insvdi_mem_reghigh"
4131   [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
4132                          (match_operand 1 "const_int_operand" "n")
4133                          (const_int 0))
4134         (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4135                      (const_int 32)))]
4136   "TARGET_ZARCH
4137    && INTVAL (operands[1]) > 0
4138    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4139    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4140 {
4141     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4142
4143     operands[1] = GEN_INT ((1ul << size) - 1);
4144     return "stcmh\t%2,%1,%S0";
4145 }
4146 [(set_attr "op_type" "RSY")
4147  (set_attr "z10prop" "z10_super")])
4148
4149 (define_insn "*insvdi_reg_imm"
4150   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4151                          (const_int 16)
4152                          (match_operand 1 "const_int_operand" "n"))
4153         (match_operand:DI 2 "const_int_operand" "n"))]
4154   "TARGET_ZARCH
4155    && INTVAL (operands[1]) >= 0
4156    && INTVAL (operands[1]) < BITS_PER_WORD
4157    && INTVAL (operands[1]) % 16 == 0"
4158 {
4159   switch (BITS_PER_WORD - INTVAL (operands[1]))
4160     {
4161       case 64: return "iihh\t%0,%x2"; break;
4162       case 48: return "iihl\t%0,%x2"; break;
4163       case 32: return "iilh\t%0,%x2"; break;
4164       case 16: return "iill\t%0,%x2"; break;
4165       default: gcc_unreachable();
4166     }
4167 }
4168   [(set_attr "op_type" "RI")
4169    (set_attr "z10prop" "z10_super_E1")])
4170
4171 ; Update the left-most 32 bit of a DI.
4172 (define_insn "*insv_h_di_reg_extimm"
4173   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4174                          (const_int 32)
4175                          (const_int 0))
4176         (match_operand:DI 1 "const_int_operand" "n"))]
4177   "TARGET_EXTIMM"
4178   "iihf\t%0,%o1"
4179   [(set_attr "op_type" "RIL")
4180    (set_attr "z10prop" "z10_fwd_E1")])
4181
4182 ; Update the right-most 32 bit of a DI.
4183 (define_insn "*insv_l_di_reg_extimm"
4184   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4185                          (const_int 32)
4186                          (const_int 32))
4187         (match_operand:DI 1 "const_int_operand" "n"))]
4188   "TARGET_EXTIMM"
4189   "iilf\t%0,%o1"
4190   [(set_attr "op_type" "RIL")
4191    (set_attr "z10prop" "z10_fwd_A1")])
4192
4193 ;
4194 ; extendsidi2 instruction pattern(s).
4195 ;
4196
4197 (define_expand "extendsidi2"
4198   [(set (match_operand:DI 0 "register_operand" "")
4199         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4200   ""
4201 {
4202   if (!TARGET_ZARCH)
4203     {
4204       emit_clobber (operands[0]);
4205       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4206       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4207       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4208       DONE;
4209     }
4210 })
4211
4212 (define_insn "*extendsidi2"
4213   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4214         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4215   "TARGET_ZARCH"
4216   "@
4217    lgfr\t%0,%1
4218    lgf\t%0,%1
4219    lgfrl\t%0,%1"
4220   [(set_attr "op_type"      "RRE,RXY,RIL")
4221    (set_attr "type"         "*,*,larl")
4222    (set_attr "cpu_facility" "*,*,z10")
4223    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4224
4225 ;
4226 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4227 ;
4228
4229 (define_expand "extend<HQI:mode><DSI:mode>2"
4230   [(set (match_operand:DSI 0 "register_operand" "")
4231         (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4232   ""
4233 {
4234   if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4235     {
4236       rtx tmp = gen_reg_rtx (SImode);
4237       emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4238       emit_insn (gen_extendsidi2 (operands[0], tmp));
4239       DONE;
4240     }
4241   else if (!TARGET_EXTIMM)
4242     {
4243       rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4244
4245       operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4246       emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4247       emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4248       DONE;
4249     }
4250 })
4251
4252 ;
4253 ; extendhidi2 instruction pattern(s).
4254 ;
4255
4256 (define_insn "*extendhidi2_extimm"
4257   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4258         (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
4259   "TARGET_ZARCH && TARGET_EXTIMM"
4260   "@
4261    lghr\t%0,%1
4262    lgh\t%0,%1
4263    lghrl\t%0,%1"
4264   [(set_attr "op_type"      "RRE,RXY,RIL")
4265    (set_attr "type"         "*,*,larl")
4266    (set_attr "cpu_facility" "extimm,extimm,z10")
4267    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4268
4269 (define_insn "*extendhidi2"
4270   [(set (match_operand:DI 0 "register_operand" "=d")
4271         (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
4272   "TARGET_ZARCH"
4273   "lgh\t%0,%1"
4274   [(set_attr "op_type" "RXY")
4275    (set_attr "z10prop" "z10_super_E1")])
4276
4277 ;
4278 ; extendhisi2 instruction pattern(s).
4279 ;
4280
4281 (define_insn "*extendhisi2_extimm"
4282   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4283         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4284   "TARGET_EXTIMM"
4285   "@
4286    lhr\t%0,%1
4287    lh\t%0,%1
4288    lhy\t%0,%1
4289    lhrl\t%0,%1"
4290   [(set_attr "op_type"      "RRE,RX,RXY,RIL")
4291    (set_attr "type"         "*,*,*,larl")
4292    (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4293    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4294
4295 (define_insn "*extendhisi2"
4296   [(set (match_operand:SI 0 "register_operand" "=d,d")
4297         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4298   "!TARGET_EXTIMM"
4299   "@
4300    lh\t%0,%1
4301    lhy\t%0,%1"
4302   [(set_attr "op_type" "RX,RXY")
4303    (set_attr "cpu_facility" "*,longdisp")
4304    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4305
4306 ;
4307 ; extendqi(si|di)2 instruction pattern(s).
4308 ;
4309
4310 ; lbr, lgbr, lb, lgb
4311 (define_insn "*extendqi<mode>2_extimm"
4312   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4313         (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
4314   "TARGET_EXTIMM"
4315   "@
4316    l<g>br\t%0,%1
4317    l<g>b\t%0,%1"
4318   [(set_attr "op_type" "RRE,RXY")
4319    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4320
4321 ; lb, lgb
4322 (define_insn "*extendqi<mode>2"
4323   [(set (match_operand:GPR 0 "register_operand" "=d")
4324         (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
4325   "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4326   "l<g>b\t%0,%1"
4327   [(set_attr "op_type" "RXY")
4328    (set_attr "z10prop" "z10_super_E1")])
4329
4330 (define_insn_and_split "*extendqi<mode>2_short_displ"
4331   [(set (match_operand:GPR 0 "register_operand" "=d")
4332         (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4333    (clobber (reg:CC CC_REGNUM))]
4334   "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4335   "#"
4336   "&& reload_completed"
4337   [(parallel
4338     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4339      (clobber (reg:CC CC_REGNUM))])
4340    (parallel
4341     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4342      (clobber (reg:CC CC_REGNUM))])]
4343 {
4344   operands[1] = adjust_address (operands[1], BLKmode, 0);
4345   set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4346   operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4347 })
4348
4349 ;
4350 ; zero_extendsidi2 instruction pattern(s).
4351 ;
4352
4353 (define_expand "zero_extendsidi2"
4354   [(set (match_operand:DI 0 "register_operand" "")
4355         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4356   ""
4357 {
4358   if (!TARGET_ZARCH)
4359     {
4360       emit_clobber (operands[0]);
4361       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4362       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4363       DONE;
4364     }
4365 })
4366
4367 (define_insn "*zero_extendsidi2"
4368   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4369         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4370   "TARGET_ZARCH"
4371   "@
4372    llgfr\t%0,%1
4373    llgf\t%0,%1
4374    llgfrl\t%0,%1"
4375   [(set_attr "op_type"      "RRE,RXY,RIL")
4376    (set_attr "type"         "*,*,larl")
4377    (set_attr "cpu_facility" "*,*,z10")
4378    (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4379
4380 ;
4381 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4382 ;
4383
4384 (define_insn "*llgt_sidi"
4385   [(set (match_operand:DI 0 "register_operand" "=d")
4386         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4387                 (const_int 2147483647)))]
4388   "TARGET_ZARCH"
4389   "llgt\t%0,%1"
4390   [(set_attr "op_type"  "RXE")
4391    (set_attr "z10prop" "z10_super_E1")])
4392
4393 (define_insn_and_split "*llgt_sidi_split"
4394   [(set (match_operand:DI 0 "register_operand" "=d")
4395         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4396                 (const_int 2147483647)))
4397    (clobber (reg:CC CC_REGNUM))]
4398   "TARGET_ZARCH"
4399   "#"
4400   "&& reload_completed"
4401   [(set (match_dup 0)
4402         (and:DI (subreg:DI (match_dup 1) 0)
4403                 (const_int 2147483647)))]
4404   "")
4405
4406 (define_insn "*llgt_sisi"
4407   [(set (match_operand:SI 0 "register_operand" "=d,d")
4408         (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
4409                 (const_int 2147483647)))]
4410   "TARGET_ZARCH"
4411   "@
4412    llgtr\t%0,%1
4413    llgt\t%0,%1"
4414   [(set_attr "op_type"  "RRE,RXE")
4415    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4416
4417 (define_insn "*llgt_didi"
4418   [(set (match_operand:DI 0 "register_operand" "=d,d")
4419         (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4420                 (const_int 2147483647)))]
4421   "TARGET_ZARCH"
4422   "@
4423    llgtr\t%0,%1
4424    llgt\t%0,%N1"
4425   [(set_attr "op_type"  "RRE,RXE")
4426    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4427
4428 (define_split
4429   [(set (match_operand:DSI 0 "register_operand" "")
4430         (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4431                  (const_int 2147483647)))
4432    (clobber (reg:CC CC_REGNUM))]
4433   "TARGET_ZARCH && reload_completed"
4434   [(set (match_dup 0)
4435         (and:DSI (match_dup 1)
4436                  (const_int 2147483647)))]
4437   "")
4438
4439 ;
4440 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4441 ;
4442
4443 (define_expand "zero_extend<mode>di2"
4444   [(set (match_operand:DI 0 "register_operand" "")
4445         (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4446   ""
4447 {
4448   if (!TARGET_ZARCH)
4449     {
4450       rtx tmp = gen_reg_rtx (SImode);
4451       emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4452       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4453       DONE;
4454     }
4455   else if (!TARGET_EXTIMM)
4456     {
4457       rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4458       operands[1] = gen_lowpart (DImode, operands[1]);
4459       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4460       emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4461       DONE;
4462     }
4463 })
4464
4465 (define_expand "zero_extend<mode>si2"
4466   [(set (match_operand:SI 0 "register_operand" "")
4467         (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4468   ""
4469 {
4470   if (!TARGET_EXTIMM)
4471     {
4472       operands[1] = gen_lowpart (SImode, operands[1]);
4473       emit_insn (gen_andsi3 (operands[0], operands[1],
4474                              GEN_INT ((1 << <HQI:bitsize>) - 1)));
4475       DONE;
4476     }
4477 })
4478
4479 ; llhrl, llghrl
4480 (define_insn "*zero_extendhi<mode>2_z10"
4481   [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4482         (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
4483   "TARGET_Z10"
4484   "@
4485    ll<g>hr\t%0,%1
4486    ll<g>h\t%0,%1
4487    ll<g>hrl\t%0,%1"
4488   [(set_attr "op_type"      "RXY,RRE,RIL")
4489    (set_attr "type"         "*,*,larl")
4490    (set_attr "cpu_facility" "*,*,z10")
4491    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4492
4493 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4494 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4495   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4496         (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
4497   "TARGET_EXTIMM"
4498   "@
4499    ll<g><hc>r\t%0,%1
4500    ll<g><hc>\t%0,%1"
4501   [(set_attr "op_type" "RRE,RXY")
4502    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4503
4504 ; llgh, llgc
4505 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4506   [(set (match_operand:GPR 0 "register_operand" "=d")
4507         (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
4508   "TARGET_ZARCH && !TARGET_EXTIMM"
4509   "llg<hc>\t%0,%1"
4510   [(set_attr "op_type" "RXY")
4511    (set_attr "z10prop" "z10_fwd_A3")])
4512
4513 (define_insn_and_split "*zero_extendhisi2_31"
4514   [(set (match_operand:SI 0 "register_operand" "=&d")
4515         (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
4516    (clobber (reg:CC CC_REGNUM))]
4517   "!TARGET_ZARCH"
4518   "#"
4519   "&& reload_completed"
4520   [(set (match_dup 0) (const_int 0))
4521    (parallel
4522     [(set (strict_low_part (match_dup 2)) (match_dup 1))
4523      (clobber (reg:CC CC_REGNUM))])]
4524   "operands[2] = gen_lowpart (HImode, operands[0]);")
4525
4526 (define_insn_and_split "*zero_extendqisi2_31"
4527   [(set (match_operand:SI 0 "register_operand" "=&d")
4528         (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
4529   "!TARGET_ZARCH"
4530   "#"
4531   "&& reload_completed"
4532   [(set (match_dup 0) (const_int 0))
4533    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4534   "operands[2] = gen_lowpart (QImode, operands[0]);")
4535
4536 ;
4537 ; zero_extendqihi2 instruction pattern(s).
4538 ;
4539
4540 (define_expand "zero_extendqihi2"
4541   [(set (match_operand:HI 0 "register_operand" "")
4542         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4543   "TARGET_ZARCH && !TARGET_EXTIMM"
4544 {
4545   operands[1] = gen_lowpart (HImode, operands[1]);
4546   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4547   DONE;
4548 })
4549
4550 (define_insn "*zero_extendqihi2_64"
4551   [(set (match_operand:HI 0 "register_operand" "=d")
4552         (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4553   "TARGET_ZARCH && !TARGET_EXTIMM"
4554   "llgc\t%0,%1"
4555   [(set_attr "op_type" "RXY")
4556    (set_attr "z10prop" "z10_fwd_A3")])
4557
4558 (define_insn_and_split "*zero_extendqihi2_31"
4559   [(set (match_operand:HI 0 "register_operand" "=&d")
4560         (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4561   "!TARGET_ZARCH"
4562   "#"
4563   "&& reload_completed"
4564   [(set (match_dup 0) (const_int 0))
4565    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4566   "operands[2] = gen_lowpart (QImode, operands[0]);")
4567
4568 ;
4569 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4570 ;
4571
4572 (define_expand "fixuns_truncdddi2"
4573   [(parallel
4574     [(set (match_operand:DI 0 "register_operand" "")
4575           (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4576      (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4577      (clobber (reg:CC CC_REGNUM))])]
4578
4579   "TARGET_HARD_DFP"
4580 {
4581   if (!TARGET_Z196)
4582     {
4583       rtx_code_label *label1 = gen_label_rtx ();
4584       rtx_code_label *label2 = gen_label_rtx ();
4585       rtx temp = gen_reg_rtx (TDmode);
4586       REAL_VALUE_TYPE cmp, sub;
4587
4588       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4589       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4590
4591       /* 2^63 can't be represented as 64bit DFP number with full precision.  The
4592          solution is doing the check and the subtraction in TD mode and using a
4593          TD -> DI convert afterwards.  */
4594       emit_insn (gen_extendddtd2 (temp, operands[1]));
4595       temp = force_reg (TDmode, temp);
4596       emit_cmp_and_jump_insns (temp,
4597             const_double_from_real_value (cmp, TDmode),
4598             LT, NULL_RTX, VOIDmode, 0, label1);
4599       emit_insn (gen_subtd3 (temp, temp,
4600             const_double_from_real_value (sub, TDmode)));
4601       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4602                                          GEN_INT (DFP_RND_TOWARD_MINF)));
4603       emit_jump (label2);
4604
4605       emit_label (label1);
4606       emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
4607                                          GEN_INT (DFP_RND_TOWARD_0)));
4608       emit_label (label2);
4609       DONE;
4610     }
4611 })
4612
4613 (define_expand "fixuns_trunctddi2"
4614   [(parallel
4615     [(set (match_operand:DI 0 "register_operand" "")
4616           (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4617      (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4618      (clobber (reg:CC CC_REGNUM))])]
4619
4620   "TARGET_HARD_DFP"
4621 {
4622   if (!TARGET_Z196)
4623     {
4624       rtx_code_label *label1 = gen_label_rtx ();
4625       rtx_code_label *label2 = gen_label_rtx ();
4626       rtx temp = gen_reg_rtx (TDmode);
4627       REAL_VALUE_TYPE cmp, sub;
4628
4629       operands[1] = force_reg (TDmode, operands[1]);
4630       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4631       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4632
4633       emit_cmp_and_jump_insns (operands[1],
4634             const_double_from_real_value (cmp, TDmode),
4635             LT, NULL_RTX, VOIDmode, 0, label1);
4636       emit_insn (gen_subtd3 (temp, operands[1],
4637             const_double_from_real_value (sub, TDmode)));
4638       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4639                                          GEN_INT (DFP_RND_TOWARD_MINF)));
4640       emit_jump (label2);
4641
4642       emit_label (label1);
4643       emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
4644                                          GEN_INT (DFP_RND_TOWARD_0)));
4645       emit_label (label2);
4646       DONE;
4647     }
4648 })
4649
4650 ;
4651 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4652 ; instruction pattern(s).
4653 ;
4654
4655 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4656   [(parallel
4657     [(set (match_operand:GPR 0 "register_operand" "")
4658           (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4659      (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4660      (clobber (reg:CC CC_REGNUM))])]
4661   "TARGET_HARD_FLOAT"
4662 {
4663   if (!TARGET_Z196)
4664     {
4665       rtx_code_label *label1 = gen_label_rtx ();
4666       rtx_code_label *label2 = gen_label_rtx ();
4667       rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4668       REAL_VALUE_TYPE cmp, sub;
4669
4670       operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4671       real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4672       real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4673
4674       emit_cmp_and_jump_insns (operands[1],
4675             const_double_from_real_value (cmp, <BFP:MODE>mode),
4676             LT, NULL_RTX, VOIDmode, 0, label1);
4677       emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4678             const_double_from_real_value (sub, <BFP:MODE>mode)));
4679       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4680             GEN_INT (BFP_RND_TOWARD_MINF)));
4681       emit_jump (label2);
4682
4683       emit_label (label1);
4684       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4685             operands[1], GEN_INT (BFP_RND_TOWARD_0)));
4686       emit_label (label2);
4687       DONE;
4688     }
4689 })
4690
4691 ; fixuns_trunc(td|dd)si2 expander
4692 (define_expand "fixuns_trunc<mode>si2"
4693   [(parallel
4694     [(set (match_operand:SI 0 "register_operand" "")
4695           (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4696      (unspec:SI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4697      (clobber (reg:CC CC_REGNUM))])]
4698   "TARGET_Z196 && TARGET_HARD_DFP"
4699   "")
4700
4701 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4702
4703 (define_insn "*fixuns_truncdfdi2_z13"
4704   [(set (match_operand:DI                  0 "register_operand" "=d,v")
4705         (unsigned_fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4706    (unspec:DI [(match_operand:DI           2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4707    (clobber (reg:CC CC_REGNUM))]
4708    "TARGET_VX && TARGET_HARD_FLOAT"
4709    "@
4710     clgdbr\t%0,%h2,%1,0
4711     wclgdb\t%v0,%v1,0,%h2"
4712    [(set_attr "op_type" "RRF,VRR")
4713     (set_attr "type"    "ftoi")])
4714
4715 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4716 ;         clfdtr, clfxtr,         clgdtr, clgxtr
4717 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4718   [(set (match_operand:GPR                  0 "register_operand" "=d")
4719         (unsigned_fix:GPR (match_operand:FP 1 "register_operand"  "f")))
4720    (unspec:GPR [(match_operand:GPR          2 "immediate_operand" "K")] UNSPEC_ROUND)
4721    (clobber (reg:CC CC_REGNUM))]
4722    "TARGET_Z196 && TARGET_HARD_FLOAT
4723     && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4724    "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4725    [(set_attr "op_type" "RRF")
4726     (set_attr "type"    "ftoi")])
4727
4728 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4729   [(set (match_operand:GPR 0 "register_operand" "")
4730         (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4731   "TARGET_HARD_FLOAT"
4732 {
4733   emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4734              GEN_INT (BFP_RND_TOWARD_0)));
4735   DONE;
4736 })
4737
4738 (define_insn "*fix_truncdfdi2_bfp_z13"
4739   [(set (match_operand:DI         0 "register_operand" "=d,v")
4740         (fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4741    (unspec:DI [(match_operand:DI  2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4742    (clobber (reg:CC CC_REGNUM))]
4743   "TARGET_VX && TARGET_HARD_FLOAT"
4744   "@
4745    cgdbr\t%0,%h2,%1
4746    wcgdb\t%v0,%v1,0,%h2"
4747   [(set_attr "op_type" "RRE,VRR")
4748    (set_attr "type"    "ftoi")])
4749
4750 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4751 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4752   [(set (match_operand:GPR          0 "register_operand" "=d")
4753         (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4754    (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4755    (clobber (reg:CC CC_REGNUM))]
4756   "TARGET_HARD_FLOAT
4757     && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4758   "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4759   [(set_attr "op_type" "RRE")
4760    (set_attr "type"    "ftoi")])
4761
4762 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4763   [(parallel
4764     [(set (match_operand:GPR          0 "register_operand" "=d")
4765           (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4766      (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4767      (clobber (reg:CC CC_REGNUM))])]
4768   "TARGET_HARD_FLOAT")
4769 ;
4770 ; fix_trunc(td|dd)di2 instruction pattern(s).
4771 ;
4772
4773 (define_expand "fix_trunc<mode>di2"
4774   [(set (match_operand:DI 0 "register_operand" "")
4775         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4776   "TARGET_ZARCH && TARGET_HARD_DFP"
4777 {
4778   operands[1] = force_reg (<MODE>mode, operands[1]);
4779   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4780       GEN_INT (DFP_RND_TOWARD_0)));
4781   DONE;
4782 })
4783
4784 ; cgxtr, cgdtr
4785 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4786   [(set (match_operand:DI 0 "register_operand" "=d")
4787         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4788    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4789    (clobber (reg:CC CC_REGNUM))]
4790   "TARGET_ZARCH && TARGET_HARD_DFP"
4791   "cg<DFP:xde>tr\t%0,%h2,%1"
4792   [(set_attr "op_type" "RRF")
4793    (set_attr "type"    "ftoidfp")])
4794
4795
4796 ;
4797 ; fix_trunctf(si|di)2 instruction pattern(s).
4798 ;
4799
4800 (define_expand "fix_trunctf<mode>2"
4801   [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4802                    (fix:GPR (match_operand:TF 1 "register_operand" "")))
4803               (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4804               (clobber (reg:CC CC_REGNUM))])]
4805   "TARGET_HARD_FLOAT"
4806   "")
4807
4808
4809 ;
4810 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4811 ;
4812
4813 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4814 (define_insn "floatdi<mode>2"
4815   [(set (match_operand:FP           0 "register_operand" "=f,v")
4816         (float:FP (match_operand:DI 1 "register_operand"  "d,v")))]
4817   "TARGET_ZARCH && TARGET_HARD_FLOAT"
4818   "@
4819    c<xde>g<bt>r\t%0,%1
4820    wcdgb\t%v0,%v1,0,0"
4821   [(set_attr "op_type"      "RRE,VRR")
4822    (set_attr "type"         "itof<mode>" )
4823    (set_attr "cpu_facility" "*,vec")
4824    (set_attr "enabled"      "*,<DFDI>")])
4825
4826 ; cxfbr, cdfbr, cefbr
4827 (define_insn "floatsi<mode>2"
4828   [(set (match_operand:BFP 0 "register_operand" "=f")
4829         (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4830   "TARGET_HARD_FLOAT"
4831   "c<xde>fbr\t%0,%1"
4832   [(set_attr "op_type" "RRE")
4833    (set_attr "type"   "itof<mode>" )])
4834
4835 ; cxftr, cdftr
4836 (define_insn "floatsi<mode>2"
4837   [(set (match_operand:DFP 0 "register_operand" "=f")
4838         (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4839   "TARGET_Z196 && TARGET_HARD_FLOAT"
4840   "c<xde>ftr\t%0,0,%1,0"
4841   [(set_attr "op_type" "RRE")
4842    (set_attr "type"   "itof<mode>" )])
4843
4844 ;
4845 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4846 ;
4847
4848 (define_insn "*floatunsdidf2_z13"
4849   [(set (match_operand:DF                    0 "register_operand" "=f,v")
4850         (unsigned_float:DF (match_operand:DI 1 "register_operand"  "d,v")))]
4851   "TARGET_VX && TARGET_HARD_FLOAT"
4852   "@
4853    cdlgbr\t%0,0,%1,0
4854    wcdlgb\t%v0,%v1,0,0"
4855   [(set_attr "op_type" "RRE,VRR")
4856    (set_attr "type"    "itofdf")])
4857
4858 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4859 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4860 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4861   [(set (match_operand:FP                     0 "register_operand" "=f")
4862         (unsigned_float:FP (match_operand:GPR 1 "register_operand"  "d")))]
4863   "TARGET_Z196 && TARGET_HARD_FLOAT
4864    && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4865   "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4866   [(set_attr "op_type" "RRE")
4867    (set_attr "type"    "itof<FP:mode>")])
4868
4869 (define_expand "floatuns<GPR:mode><FP:mode>2"
4870   [(set (match_operand:FP                     0 "register_operand" "")
4871         (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4872   "TARGET_Z196 && TARGET_HARD_FLOAT")
4873
4874 ;
4875 ; truncdfsf2 instruction pattern(s).
4876 ;
4877
4878 (define_insn "truncdfsf2"
4879   [(set (match_operand:SF                    0 "register_operand" "=f,v")
4880         (float_truncate:SF (match_operand:DF 1 "register_operand"  "f,v")))]
4881   "TARGET_HARD_FLOAT"
4882   "@
4883    ledbr\t%0,%1
4884    wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4885                        ; According to BFP rounding mode
4886   [(set_attr "op_type"      "RRE,VRR")
4887    (set_attr "type"         "ftruncdf")
4888    (set_attr "cpu_facility" "*,vec")])
4889
4890 ;
4891 ; trunctf(df|sf)2 instruction pattern(s).
4892 ;
4893
4894 ; ldxbr, lexbr
4895 (define_insn "trunctf<mode>2"
4896   [(set (match_operand:DSF 0 "register_operand" "=f")
4897         (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4898    (clobber (match_scratch:TF 2 "=f"))]
4899   "TARGET_HARD_FLOAT"
4900   "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4901   [(set_attr "length" "6")
4902    (set_attr "type"   "ftrunctf")])
4903
4904 ;
4905 ; trunctddd2 and truncddsd2 instruction pattern(s).
4906 ;
4907
4908
4909 (define_expand "trunctddd2"
4910   [(parallel
4911     [(set (match_operand:DD 0 "register_operand" "")
4912           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4913      (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
4914      (clobber (scratch:TD))])]
4915   "TARGET_HARD_DFP")
4916
4917 (define_insn "*trunctddd2"
4918   [(set (match_operand:DD 0 "register_operand" "=f")
4919         (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4920    (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
4921    (clobber (match_scratch:TD 3 "=f"))]
4922   "TARGET_HARD_DFP"
4923   "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
4924   [(set_attr "length"  "6")
4925    (set_attr "type"    "ftruncdd")])
4926
4927 (define_insn "truncddsd2"
4928   [(set (match_operand:SD 0 "register_operand" "=f")
4929         (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4930   "TARGET_HARD_DFP"
4931   "ledtr\t%0,0,%1,0"
4932   [(set_attr "op_type" "RRF")
4933    (set_attr "type"    "ftruncsd")])
4934
4935 (define_expand "trunctdsd2"
4936   [(parallel
4937     [(set (match_dup 3)
4938           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4939      (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
4940      (clobber (match_scratch:TD 2 ""))])
4941    (set (match_operand:SD 0 "register_operand" "")
4942         (float_truncate:SD (match_dup 3)))]
4943   "TARGET_HARD_DFP"
4944 {
4945   operands[3] = gen_reg_rtx (DDmode);
4946 })
4947
4948 ;
4949 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4950 ;
4951
4952 (define_insn "*extendsfdf2_z13"
4953   [(set (match_operand:DF                  0 "register_operand"     "=f,f,v")
4954         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R,v")))]
4955   "TARGET_VX && TARGET_HARD_FLOAT"
4956   "@
4957    ldebr\t%0,%1
4958    ldeb\t%0,%1
4959    wldeb\t%v0,%v1"
4960   [(set_attr "op_type" "RRE,RXE,VRR")
4961    (set_attr "type"    "fsimpdf, floaddf,fsimpdf")])
4962
4963 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4964 (define_insn "*extend<DSF:mode><BFP:mode>2"
4965   [(set (match_operand:BFP                   0 "register_operand"     "=f,f")
4966         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand"  "f,R")))]
4967   "TARGET_HARD_FLOAT
4968    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4969    && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4970   "@
4971    l<BFP:xde><DSF:xde>br\t%0,%1
4972    l<BFP:xde><DSF:xde>b\t%0,%1"
4973   [(set_attr "op_type" "RRE,RXE")
4974    (set_attr "type"    "fsimp<BFP:mode>, fload<BFP:mode>")])
4975
4976 (define_expand "extend<DSF:mode><BFP:mode>2"
4977   [(set (match_operand:BFP                   0 "register_operand"     "")
4978         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4979   "TARGET_HARD_FLOAT
4980    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4981
4982 ;
4983 ; extendddtd2 and extendsddd2 instruction pattern(s).
4984 ;
4985
4986 (define_insn "extendddtd2"
4987   [(set (match_operand:TD 0 "register_operand" "=f")
4988         (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4989   "TARGET_HARD_DFP"
4990   "lxdtr\t%0,%1,0"
4991   [(set_attr "op_type" "RRF")
4992    (set_attr "type"    "fsimptf")])
4993
4994 (define_insn "extendsddd2"
4995   [(set (match_operand:DD 0 "register_operand" "=f")
4996         (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4997   "TARGET_HARD_DFP"
4998   "ldetr\t%0,%1,0"
4999   [(set_attr "op_type" "RRF")
5000    (set_attr "type"    "fsimptf")])
5001
5002 (define_expand "extendsdtd2"
5003   [(set (match_dup 2)
5004         (float_extend:DD (match_operand:SD 1 "register_operand" "")))
5005    (set (match_operand:TD 0 "register_operand" "")
5006         (float_extend:TD (match_dup 2)))]
5007   "TARGET_HARD_DFP"
5008 {
5009   operands[2] = gen_reg_rtx (DDmode);
5010 })
5011
5012 ; Binary Floating Point - load fp integer
5013
5014 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
5015 ; For all of them the inexact exceptions are suppressed.
5016
5017 ; fiebra, fidbra, fixbra
5018 (define_insn "<FPINT:fpint_name><BFP:mode>2"
5019   [(set (match_operand:BFP 0 "register_operand" "=f")
5020         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5021                     FPINT))]
5022   "TARGET_Z196"
5023   "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
5024   [(set_attr "op_type"   "RRF")
5025    (set_attr "type"      "fsimp<BFP:mode>")])
5026
5027 ; rint is supposed to raise an inexact exception so we can use the
5028 ; older instructions.
5029
5030 ; fiebr, fidbr, fixbr
5031 (define_insn "rint<BFP:mode>2"
5032   [(set (match_operand:BFP 0 "register_operand" "=f")
5033         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5034                     UNSPEC_FPINT_RINT))]
5035   ""
5036   "fi<BFP:xde>br\t%0,0,%1"
5037   [(set_attr "op_type"   "RRF")
5038    (set_attr "type"      "fsimp<BFP:mode>")])
5039
5040
5041 ; Decimal Floating Point - load fp integer
5042
5043 ; fidtr, fixtr
5044 (define_insn "<FPINT:fpint_name><DFP:mode>2"
5045   [(set (match_operand:DFP 0 "register_operand" "=f")
5046         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5047                     FPINT))]
5048   "TARGET_HARD_DFP"
5049   "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
5050   [(set_attr "op_type"   "RRF")
5051    (set_attr "type"      "fsimp<DFP:mode>")])
5052
5053 ; fidtr, fixtr
5054 (define_insn "rint<DFP:mode>2"
5055   [(set (match_operand:DFP 0 "register_operand" "=f")
5056         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5057                     UNSPEC_FPINT_RINT))]
5058   "TARGET_HARD_DFP"
5059   "fi<DFP:xde>tr\t%0,0,%1,0"
5060   [(set_attr "op_type"   "RRF")
5061    (set_attr "type"      "fsimp<DFP:mode>")])
5062
5063 ;
5064 ; Binary <-> Decimal floating point trunc patterns
5065 ;
5066
5067 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
5068   [(set (reg:DFP_ALL FPR0_REGNUM)
5069         (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5070    (use (reg:SI GPR0_REGNUM))
5071    (clobber (reg:CC CC_REGNUM))
5072    (clobber (reg:SI GPR1_REGNUM))]
5073   "TARGET_HARD_DFP"
5074   "pfpo")
5075
5076 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
5077   [(set (reg:BFP FPR0_REGNUM)
5078         (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5079    (use (reg:SI GPR0_REGNUM))
5080    (clobber (reg:CC CC_REGNUM))
5081    (clobber (reg:SI GPR1_REGNUM))]
5082   "TARGET_HARD_DFP"
5083   "pfpo")
5084
5085 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
5086   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5087    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5088    (parallel
5089     [(set (reg:DFP_ALL FPR0_REGNUM)
5090           (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5091      (use (reg:SI GPR0_REGNUM))
5092      (clobber (reg:CC CC_REGNUM))
5093      (clobber (reg:SI GPR1_REGNUM))])
5094    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5095         (reg:DFP_ALL FPR0_REGNUM))]
5096   "TARGET_HARD_DFP
5097    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5098 {
5099   HOST_WIDE_INT flags;
5100
5101   flags = (PFPO_CONVERT |
5102            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5103            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5104
5105   operands[2] = GEN_INT (flags);
5106 })
5107
5108 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5109   [(set (reg:DFP_ALL FPR4_REGNUM)
5110         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5111    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5112    (parallel
5113     [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5114      (use (reg:SI GPR0_REGNUM))
5115      (clobber (reg:CC CC_REGNUM))
5116      (clobber (reg:SI GPR1_REGNUM))])
5117    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5118   "TARGET_HARD_DFP
5119    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5120 {
5121   HOST_WIDE_INT flags;
5122
5123   flags = (PFPO_CONVERT |
5124            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5125            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5126
5127   operands[2] = GEN_INT (flags);
5128 })
5129
5130 ;
5131 ; Binary <-> Decimal floating point extend patterns
5132 ;
5133
5134 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5135   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5136    (use (reg:SI GPR0_REGNUM))
5137    (clobber (reg:CC CC_REGNUM))
5138    (clobber (reg:SI GPR1_REGNUM))]
5139   "TARGET_HARD_DFP"
5140   "pfpo")
5141
5142 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5143   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5144    (use (reg:SI GPR0_REGNUM))
5145    (clobber (reg:CC CC_REGNUM))
5146    (clobber (reg:SI GPR1_REGNUM))]
5147   "TARGET_HARD_DFP"
5148   "pfpo")
5149
5150 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5151   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5152    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5153    (parallel
5154     [(set (reg:DFP_ALL FPR0_REGNUM)
5155           (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5156      (use (reg:SI GPR0_REGNUM))
5157      (clobber (reg:CC CC_REGNUM))
5158      (clobber (reg:SI GPR1_REGNUM))])
5159    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5160         (reg:DFP_ALL FPR0_REGNUM))]
5161   "TARGET_HARD_DFP
5162    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5163 {
5164   HOST_WIDE_INT flags;
5165
5166   flags = (PFPO_CONVERT |
5167            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5168            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5169
5170   operands[2] = GEN_INT (flags);
5171 })
5172
5173 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5174   [(set (reg:DFP_ALL FPR4_REGNUM)
5175         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5176    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5177    (parallel
5178     [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5179      (use (reg:SI GPR0_REGNUM))
5180      (clobber (reg:CC CC_REGNUM))
5181      (clobber (reg:SI GPR1_REGNUM))])
5182    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5183   "TARGET_HARD_DFP
5184    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5185 {
5186   HOST_WIDE_INT flags;
5187
5188   flags = (PFPO_CONVERT |
5189            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5190            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5191
5192   operands[2] = GEN_INT (flags);
5193 })
5194
5195
5196 ;;
5197 ;; ARITHMETIC OPERATIONS
5198 ;;
5199 ;  arithmetic operations set the ConditionCode,
5200 ;  because of unpredictable Bits in Register for Halfword and Byte
5201 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
5202
5203 ;;
5204 ;;- Add instructions.
5205 ;;
5206
5207 ;
5208 ; addti3 instruction pattern(s).
5209 ;
5210
5211 (define_expand "addti3"
5212   [(parallel
5213     [(set (match_operand:TI          0 "register_operand"     "")
5214           (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5215                    (match_operand:TI 2 "general_operand"      "") ) )
5216      (clobber (reg:CC CC_REGNUM))])]
5217   "TARGET_ZARCH"
5218 {
5219   /* For z13 we have vaq which doesn't set CC.  */
5220   if (TARGET_VX)
5221     {
5222       emit_insn (gen_rtx_SET (operands[0],
5223                               gen_rtx_PLUS (TImode,
5224                                             copy_to_mode_reg (TImode, operands[1]),
5225                                             copy_to_mode_reg (TImode, operands[2]))));
5226       DONE;
5227     }
5228 })
5229
5230 (define_insn_and_split "*addti3"
5231   [(set (match_operand:TI          0 "register_operand"    "=&d")
5232         (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5233                  (match_operand:TI 2 "general_operand"      "do") ) )
5234    (clobber (reg:CC CC_REGNUM))]
5235   "TARGET_ZARCH"
5236   "#"
5237   "&& reload_completed"
5238   [(parallel
5239     [(set (reg:CCL1 CC_REGNUM)
5240           (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5241                         (match_dup 7)))
5242      (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5243    (parallel
5244     [(set (match_dup 3) (plus:DI
5245                           (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5246                                    (match_dup 4)) (match_dup 5)))
5247      (clobber (reg:CC CC_REGNUM))])]
5248   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5249    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5250    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5251    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5252    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5253    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5254   [(set_attr "op_type"  "*")
5255    (set_attr "cpu_facility" "*")])
5256
5257 ;
5258 ; adddi3 instruction pattern(s).
5259 ;
5260
5261 (define_expand "adddi3"
5262   [(parallel
5263     [(set (match_operand:DI 0 "nonimmediate_operand" "")
5264           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5265                    (match_operand:DI 2 "general_operand" "")))
5266      (clobber (reg:CC CC_REGNUM))])]
5267   ""
5268   "")
5269
5270 (define_insn "*adddi3_sign"
5271   [(set (match_operand:DI 0 "register_operand" "=d,d")
5272         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5273                  (match_operand:DI 1 "register_operand" "0,0")))
5274    (clobber (reg:CC CC_REGNUM))]
5275   "TARGET_ZARCH"
5276   "@
5277    agfr\t%0,%2
5278    agf\t%0,%2"
5279   [(set_attr "op_type"  "RRE,RXY")
5280    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5281
5282 (define_insn "*adddi3_zero_cc"
5283   [(set (reg CC_REGNUM)
5284         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5285                           (match_operand:DI 1 "register_operand" "0,0"))
5286                  (const_int 0)))
5287    (set (match_operand:DI 0 "register_operand" "=d,d")
5288         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5289   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5290   "@
5291    algfr\t%0,%2
5292    algf\t%0,%2"
5293   [(set_attr "op_type"  "RRE,RXY")
5294    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5295
5296 (define_insn "*adddi3_zero_cconly"
5297   [(set (reg CC_REGNUM)
5298         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5299                           (match_operand:DI 1 "register_operand" "0,0"))
5300                  (const_int 0)))
5301    (clobber (match_scratch:DI 0 "=d,d"))]
5302   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5303   "@
5304    algfr\t%0,%2
5305    algf\t%0,%2"
5306   [(set_attr "op_type"  "RRE,RXY")
5307    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5308
5309 (define_insn "*adddi3_zero"
5310   [(set (match_operand:DI 0 "register_operand" "=d,d")
5311         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5312                  (match_operand:DI 1 "register_operand" "0,0")))
5313    (clobber (reg:CC CC_REGNUM))]
5314   "TARGET_ZARCH"
5315   "@
5316    algfr\t%0,%2
5317    algf\t%0,%2"
5318   [(set_attr "op_type"  "RRE,RXY")
5319    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5320
5321 (define_insn_and_split "*adddi3_31z"
5322   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5323         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5324                  (match_operand:DI 2 "general_operand" "do") ) )
5325    (clobber (reg:CC CC_REGNUM))]
5326   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5327   "#"
5328   "&& reload_completed"
5329   [(parallel
5330     [(set (reg:CCL1 CC_REGNUM)
5331           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5332                         (match_dup 7)))
5333      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5334    (parallel
5335     [(set (match_dup 3) (plus:SI
5336                           (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5337                                    (match_dup 4)) (match_dup 5)))
5338      (clobber (reg:CC CC_REGNUM))])]
5339   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5340    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5341    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5342    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5343    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5344    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5345
5346 (define_insn_and_split "*adddi3_31"
5347   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5348         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5349                  (match_operand:DI 2 "general_operand" "do") ) )
5350    (clobber (reg:CC CC_REGNUM))]
5351   "!TARGET_CPU_ZARCH"
5352   "#"
5353   "&& reload_completed"
5354   [(parallel
5355     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5356      (clobber (reg:CC CC_REGNUM))])
5357    (parallel
5358     [(set (reg:CCL1 CC_REGNUM)
5359           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5360                         (match_dup 7)))
5361      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5362    (set (pc)
5363         (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5364                       (pc)
5365                       (label_ref (match_dup 9))))
5366    (parallel
5367     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5368      (clobber (reg:CC CC_REGNUM))])
5369    (match_dup 9)]
5370   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5371    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5372    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5373    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5374    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5375    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5376    operands[9] = gen_label_rtx ();")
5377
5378 ;
5379 ; addsi3 instruction pattern(s).
5380 ;
5381
5382 (define_expand "addsi3"
5383   [(parallel
5384     [(set (match_operand:SI 0 "nonimmediate_operand" "")
5385           (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5386                    (match_operand:SI 2 "general_operand" "")))
5387      (clobber (reg:CC CC_REGNUM))])]
5388   ""
5389   "")
5390
5391 (define_insn "*addsi3_sign"
5392   [(set (match_operand:SI 0 "register_operand" "=d,d")
5393         (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5394                  (match_operand:SI 1 "register_operand" "0,0")))
5395    (clobber (reg:CC CC_REGNUM))]
5396   ""
5397   "@
5398    ah\t%0,%2
5399    ahy\t%0,%2"
5400   [(set_attr "op_type"  "RX,RXY")
5401    (set_attr "cpu_facility" "*,longdisp")
5402    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5403
5404 ;
5405 ; add(di|si)3 instruction pattern(s).
5406 ;
5407
5408 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5409 (define_insn "*add<mode>3"
5410   [(set (match_operand:GPR 0 "nonimmediate_operand"           "=d,d,d,d, d, d,d,d,S")
5411         (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
5412                   (match_operand:GPR 2 "general_operand"      " d,d,K,K,Op,On,R,T,C") ) )
5413    (clobber (reg:CC CC_REGNUM))]
5414   ""
5415   "@
5416    a<g>r\t%0,%2
5417    a<g>rk\t%0,%1,%2
5418    a<g>hi\t%0,%h2
5419    a<g>hik\t%0,%1,%h2
5420    al<g>fi\t%0,%2
5421    sl<g>fi\t%0,%n2
5422    a<g>\t%0,%2
5423    a<y>\t%0,%2
5424    a<g>si\t%0,%c2"
5425   [(set_attr "op_type"  "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5426    (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
5427    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5428                         z10_super_E1,z10_super_E1,z10_super_E1")])
5429
5430 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5431 (define_insn "*add<mode>3_carry1_cc"
5432   [(set (reg CC_REGNUM)
5433         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5434                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5435                  (match_dup 1)))
5436    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,d")
5437         (plus:GPR (match_dup 1) (match_dup 2)))]
5438   "s390_match_ccmode (insn, CCL1mode)"
5439   "@
5440    al<g>r\t%0,%2
5441    al<g>rk\t%0,%1,%2
5442    al<g>fi\t%0,%2
5443    sl<g>fi\t%0,%n2
5444    al<g>hsik\t%0,%1,%h2
5445    al<g>\t%0,%2
5446    al<y>\t%0,%2
5447    al<g>si\t%0,%c2"
5448   [(set_attr "op_type"      "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5449    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5450    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5451                         z10_super_E1,z10_super_E1,z10_super_E1")])
5452
5453 ; alr, al, aly, algr, alg, alrk, algrk
5454 (define_insn "*add<mode>3_carry1_cconly"
5455   [(set (reg CC_REGNUM)
5456         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5457                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5458                  (match_dup 1)))
5459    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5460   "s390_match_ccmode (insn, CCL1mode)"
5461   "@
5462    al<g>r\t%0,%2
5463    al<g>rk\t%0,%1,%2
5464    al<g>\t%0,%2
5465    al<y>\t%0,%2"
5466   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5467    (set_attr "cpu_facility" "*,z196,*,longdisp")
5468    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5469
5470 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5471 (define_insn "*add<mode>3_carry2_cc"
5472   [(set (reg CC_REGNUM)
5473         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5474                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5475                  (match_dup 2)))
5476    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,S")
5477         (plus:GPR (match_dup 1) (match_dup 2)))]
5478   "s390_match_ccmode (insn, CCL1mode)"
5479   "@
5480    al<g>r\t%0,%2
5481    al<g>rk\t%0,%1,%2
5482    al<g>fi\t%0,%2
5483    sl<g>fi\t%0,%n2
5484    al<g>hsik\t%0,%1,%h2
5485    al<g>\t%0,%2
5486    al<y>\t%0,%2
5487    al<g>si\t%0,%c2"
5488   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5489    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5490    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5491                         z10_super_E1,z10_super_E1,z10_super_E1")])
5492
5493 ; alr, al, aly, algr, alg, alrk, algrk
5494 (define_insn "*add<mode>3_carry2_cconly"
5495   [(set (reg CC_REGNUM)
5496         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5497                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5498                  (match_dup 2)))
5499    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5500   "s390_match_ccmode (insn, CCL1mode)"
5501   "@
5502    al<g>r\t%0,%2
5503    al<g>rk\t%0,%1,%2
5504    al<g>\t%0,%2
5505    al<y>\t%0,%2"
5506   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5507    (set_attr "cpu_facility" "*,z196,*,longdisp")
5508    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5509
5510 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5511 (define_insn "*add<mode>3_cc"
5512   [(set (reg CC_REGNUM)
5513         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5514                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5515                  (const_int 0)))
5516    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,S")
5517         (plus:GPR (match_dup 1) (match_dup 2)))]
5518   "s390_match_ccmode (insn, CCLmode)"
5519   "@
5520    al<g>r\t%0,%2
5521    al<g>rk\t%0,%1,%2
5522    al<g>fi\t%0,%2
5523    sl<g>fi\t%0,%n2
5524    al<g>hsik\t%0,%1,%h2
5525    al<g>\t%0,%2
5526    al<y>\t%0,%2
5527    al<g>si\t%0,%c2"
5528   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5529    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5530    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5531                         *,z10_super_E1,z10_super_E1,z10_super_E1")])
5532
5533 ; alr, al, aly, algr, alg, alrk, algrk
5534 (define_insn "*add<mode>3_cconly"
5535   [(set (reg CC_REGNUM)
5536         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5537                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5538                  (const_int 0)))
5539    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5540   "s390_match_ccmode (insn, CCLmode)"
5541   "@
5542    al<g>r\t%0,%2
5543    al<g>rk\t%0,%1,%2
5544    al<g>\t%0,%2
5545    al<y>\t%0,%2"
5546   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5547    (set_attr "cpu_facility" "*,z196,*,longdisp")
5548    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5549
5550 ; alr, al, aly, algr, alg, alrk, algrk
5551 (define_insn "*add<mode>3_cconly2"
5552   [(set (reg CC_REGNUM)
5553         (compare (match_operand:GPR 1 "nonimmediate_operand"    "%0,d,0,0")
5554                  (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5555    (clobber (match_scratch:GPR 0                                "=d,d,d,d"))]
5556   "s390_match_ccmode(insn, CCLmode)"
5557   "@
5558    al<g>r\t%0,%2
5559    al<g>rk\t%0,%1,%2
5560    al<g>\t%0,%2
5561    al<y>\t%0,%2"
5562   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5563    (set_attr "cpu_facility" "*,z196,*,longdisp")
5564    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5565
5566 ; ahi, afi, aghi, agfi, asi, agsi
5567 (define_insn "*add<mode>3_imm_cc"
5568   [(set (reg CC_REGNUM)
5569         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5570                            (match_operand:GPR 2 "const_int_operand"    " K, K,Os,C"))
5571                  (const_int 0)))
5572    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d, d,d, S")
5573         (plus:GPR (match_dup 1) (match_dup 2)))]
5574   "s390_match_ccmode (insn, CCAmode)
5575    && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5576        || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5577            /* Avoid INT32_MIN on 32 bit.  */
5578            && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5579   "@
5580    a<g>hi\t%0,%h2
5581    a<g>hik\t%0,%1,%h2
5582    a<g>fi\t%0,%2
5583    a<g>si\t%0,%c2"
5584   [(set_attr "op_type"      "RI,RIE,RIL,SIY")
5585    (set_attr "cpu_facility" "*,z196,extimm,z10")
5586    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5587
5588 ;
5589 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5590 ;
5591
5592 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5593 ; FIXME: wfadb does not clobber cc
5594 (define_insn "add<mode>3"
5595   [(set (match_operand:FP 0 "register_operand"              "=f,f,f,v")
5596         (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
5597                  (match_operand:FP 2 "general_operand"       "f,f,R,v")))
5598    (clobber (reg:CC CC_REGNUM))]
5599   "TARGET_HARD_FLOAT"
5600   "@
5601    a<xde>tr\t%0,%1,%2
5602    a<xde>br\t%0,%2
5603    a<xde>b\t%0,%2
5604    wfadb\t%v0,%v1,%v2"
5605   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
5606    (set_attr "type"         "fsimp<mode>")
5607    (set_attr "cpu_facility" "*,*,*,vec")
5608    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5609
5610 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5611 (define_insn "*add<mode>3_cc"
5612   [(set (reg CC_REGNUM)
5613         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5614                           (match_operand:FP 2 "general_operand"       "f,f,R"))
5615                  (match_operand:FP 3 "const0_operand" "")))
5616    (set (match_operand:FP 0 "register_operand" "=f,f,f")
5617         (plus:FP (match_dup 1) (match_dup 2)))]
5618   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5619   "@
5620    a<xde>tr\t%0,%1,%2
5621    a<xde>br\t%0,%2
5622    a<xde>b\t%0,%2"
5623   [(set_attr "op_type"  "RRF,RRE,RXE")
5624    (set_attr "type"     "fsimp<mode>")
5625    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5626
5627 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5628 (define_insn "*add<mode>3_cconly"
5629   [(set (reg CC_REGNUM)
5630         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5631                           (match_operand:FP 2 "general_operand"       "f,f,R"))
5632                  (match_operand:FP 3 "const0_operand" "")))
5633    (clobber (match_scratch:FP 0 "=f,f,f"))]
5634   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5635   "@
5636    a<xde>tr\t%0,%1,%2
5637    a<xde>br\t%0,%2
5638    a<xde>b\t%0,%2"
5639   [(set_attr "op_type"  "RRF,RRE,RXE")
5640    (set_attr "type"     "fsimp<mode>")
5641    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5642
5643 ;
5644 ; Pointer add instruction patterns
5645 ;
5646
5647 ; This will match "*la_64"
5648 (define_expand "addptrdi3"
5649   [(set (match_operand:DI 0 "register_operand" "")
5650         (plus:DI (match_operand:DI 1 "register_operand" "")
5651                  (match_operand:DI 2 "nonmemory_operand" "")))]
5652   "TARGET_64BIT"
5653 {
5654   if (GET_CODE (operands[2]) == CONST_INT)
5655     {
5656       HOST_WIDE_INT c = INTVAL (operands[2]);
5657
5658       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5659           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5660         {
5661           operands[2] = force_const_mem (DImode, operands[2]);
5662           operands[2] = force_reg (DImode, operands[2]);
5663         }
5664       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5665         operands[2] = force_reg (DImode, operands[2]);
5666     }
5667 })
5668
5669 ; For 31 bit we have to prevent the generated pattern from matching
5670 ; normal ADDs since la only does a 31 bit add.  This is supposed to
5671 ; match "force_la_31".
5672 (define_expand "addptrsi3"
5673   [(parallel
5674     [(set (match_operand:SI 0 "register_operand" "")
5675           (plus:SI (match_operand:SI 1 "register_operand" "")
5676                    (match_operand:SI 2 "nonmemory_operand" "")))
5677                    (use (const_int 0))])]
5678   "!TARGET_64BIT"
5679 {
5680   if (GET_CODE (operands[2]) == CONST_INT)
5681     {
5682       HOST_WIDE_INT c = INTVAL (operands[2]);
5683
5684       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5685           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5686         {
5687           operands[2] = force_const_mem (SImode, operands[2]);
5688           operands[2] = force_reg (SImode, operands[2]);
5689         }
5690       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5691         operands[2] = force_reg (SImode, operands[2]);
5692     }
5693 })
5694
5695 ;;
5696 ;;- Subtract instructions.
5697 ;;
5698
5699 ;
5700 ; subti3 instruction pattern(s).
5701 ;
5702
5703 (define_expand "subti3"
5704   [(parallel
5705     [(set (match_operand:TI           0 "register_operand" "")
5706           (minus:TI (match_operand:TI 1 "register_operand" "")
5707                     (match_operand:TI 2 "general_operand"  "") ) )
5708      (clobber (reg:CC CC_REGNUM))])]
5709   "TARGET_ZARCH"
5710 {
5711   /* For z13 we have vsq which doesn't set CC.  */
5712   if (TARGET_VX)
5713     {
5714       emit_insn (gen_rtx_SET (operands[0],
5715                               gen_rtx_MINUS (TImode,
5716                                             operands[1],
5717                                             copy_to_mode_reg (TImode, operands[2]))));
5718       DONE;
5719     }
5720 })
5721
5722 (define_insn_and_split "*subti3"
5723   [(set (match_operand:TI           0 "register_operand" "=&d")
5724         (minus:TI (match_operand:TI 1 "register_operand"   "0")
5725                   (match_operand:TI 2 "general_operand"   "do") ) )
5726    (clobber (reg:CC CC_REGNUM))]
5727   "TARGET_ZARCH"
5728   "#"
5729   "&& reload_completed"
5730   [(parallel
5731     [(set (reg:CCL2 CC_REGNUM)
5732           (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5733                         (match_dup 7)))
5734      (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5735    (parallel
5736     [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5737                                   (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5738      (clobber (reg:CC CC_REGNUM))])]
5739   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5740    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5741    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5742    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5743    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5744    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5745   [(set_attr "op_type"      "*")
5746    (set_attr "cpu_facility" "*")])
5747
5748 ;
5749 ; subdi3 instruction pattern(s).
5750 ;
5751
5752 (define_expand "subdi3"
5753   [(parallel
5754     [(set (match_operand:DI 0 "register_operand" "")
5755           (minus:DI (match_operand:DI 1 "register_operand" "")
5756                     (match_operand:DI 2 "general_operand" "")))
5757      (clobber (reg:CC CC_REGNUM))])]
5758   ""
5759   "")
5760
5761 (define_insn "*subdi3_sign"
5762   [(set (match_operand:DI 0 "register_operand" "=d,d")
5763         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5764                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5765    (clobber (reg:CC CC_REGNUM))]
5766   "TARGET_ZARCH"
5767   "@
5768    sgfr\t%0,%2
5769    sgf\t%0,%2"
5770   [(set_attr "op_type"  "RRE,RXY")
5771    (set_attr "z10prop" "z10_c,*")
5772    (set_attr "z196prop" "z196_cracked")])
5773
5774 (define_insn "*subdi3_zero_cc"
5775   [(set (reg CC_REGNUM)
5776         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5777                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5778                  (const_int 0)))
5779    (set (match_operand:DI 0 "register_operand" "=d,d")
5780         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5781   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5782   "@
5783    slgfr\t%0,%2
5784    slgf\t%0,%2"
5785   [(set_attr "op_type"  "RRE,RXY")
5786    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5787
5788 (define_insn "*subdi3_zero_cconly"
5789   [(set (reg CC_REGNUM)
5790         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5791                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5792                  (const_int 0)))
5793    (clobber (match_scratch:DI 0 "=d,d"))]
5794   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5795   "@
5796    slgfr\t%0,%2
5797    slgf\t%0,%2"
5798   [(set_attr "op_type"  "RRE,RXY")
5799    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5800
5801 (define_insn "*subdi3_zero"
5802   [(set (match_operand:DI 0 "register_operand" "=d,d")
5803         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5804                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5805    (clobber (reg:CC CC_REGNUM))]
5806   "TARGET_ZARCH"
5807   "@
5808    slgfr\t%0,%2
5809    slgf\t%0,%2"
5810   [(set_attr "op_type"  "RRE,RXY")
5811    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5812
5813 (define_insn_and_split "*subdi3_31z"
5814   [(set (match_operand:DI 0 "register_operand" "=&d")
5815         (minus:DI (match_operand:DI 1 "register_operand" "0")
5816                   (match_operand:DI 2 "general_operand" "do") ) )
5817    (clobber (reg:CC CC_REGNUM))]
5818   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5819   "#"
5820   "&& reload_completed"
5821   [(parallel
5822     [(set (reg:CCL2 CC_REGNUM)
5823           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5824                         (match_dup 7)))
5825      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5826    (parallel
5827     [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5828                                   (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5829      (clobber (reg:CC CC_REGNUM))])]
5830   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5831    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5832    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5833    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5834    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5835    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5836
5837 (define_insn_and_split "*subdi3_31"
5838   [(set (match_operand:DI 0 "register_operand" "=&d")
5839         (minus:DI (match_operand:DI 1 "register_operand" "0")
5840                   (match_operand:DI 2 "general_operand" "do") ) )
5841    (clobber (reg:CC CC_REGNUM))]
5842   "!TARGET_CPU_ZARCH"
5843   "#"
5844   "&& reload_completed"
5845   [(parallel
5846     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5847      (clobber (reg:CC CC_REGNUM))])
5848    (parallel
5849     [(set (reg:CCL2 CC_REGNUM)
5850           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5851                         (match_dup 7)))
5852      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5853    (set (pc)
5854         (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5855                       (pc)
5856                       (label_ref (match_dup 9))))
5857    (parallel
5858     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5859      (clobber (reg:CC CC_REGNUM))])
5860    (match_dup 9)]
5861   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5862    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5863    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5864    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5865    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5866    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5867    operands[9] = gen_label_rtx ();")
5868
5869 ;
5870 ; subsi3 instruction pattern(s).
5871 ;
5872
5873 (define_expand "subsi3"
5874   [(parallel
5875     [(set (match_operand:SI 0 "register_operand" "")
5876           (minus:SI (match_operand:SI 1 "register_operand" "")
5877                     (match_operand:SI 2 "general_operand" "")))
5878      (clobber (reg:CC CC_REGNUM))])]
5879   ""
5880   "")
5881
5882 (define_insn "*subsi3_sign"
5883   [(set (match_operand:SI 0 "register_operand" "=d,d")
5884         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5885                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5886    (clobber (reg:CC CC_REGNUM))]
5887   ""
5888   "@
5889    sh\t%0,%2
5890    shy\t%0,%2"
5891   [(set_attr "op_type"  "RX,RXY")
5892    (set_attr "cpu_facility" "*,longdisp")
5893    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5894
5895 ;
5896 ; sub(di|si)3 instruction pattern(s).
5897 ;
5898
5899 ; sr, s, sy, sgr, sg, srk, sgrk
5900 (define_insn "*sub<mode>3"
5901   [(set (match_operand:GPR 0 "register_operand"           "=d,d,d,d")
5902         (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5903                    (match_operand:GPR 2 "general_operand"  "d,d,R,T") ) )
5904    (clobber (reg:CC CC_REGNUM))]
5905   ""
5906   "@
5907    s<g>r\t%0,%2
5908    s<g>rk\t%0,%1,%2
5909    s<g>\t%0,%2
5910    s<y>\t%0,%2"
5911   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5912    (set_attr "cpu_facility" "*,z196,*,longdisp")
5913    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5914
5915 ; slr, sl, sly, slgr, slg, slrk, slgrk
5916 (define_insn "*sub<mode>3_borrow_cc"
5917   [(set (reg CC_REGNUM)
5918         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5919                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5920                  (match_dup 1)))
5921    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5922         (minus:GPR (match_dup 1) (match_dup 2)))]
5923   "s390_match_ccmode (insn, CCL2mode)"
5924   "@
5925    sl<g>r\t%0,%2
5926    sl<g>rk\t%0,%1,%2
5927    sl<g>\t%0,%2
5928    sl<y>\t%0,%2"
5929   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5930    (set_attr "cpu_facility" "*,z196,*,longdisp")
5931    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5932
5933 ; slr, sl, sly, slgr, slg, slrk, slgrk
5934 (define_insn "*sub<mode>3_borrow_cconly"
5935   [(set (reg CC_REGNUM)
5936         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5937                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5938                  (match_dup 1)))
5939    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5940   "s390_match_ccmode (insn, CCL2mode)"
5941   "@
5942    sl<g>r\t%0,%2
5943    sl<g>rk\t%0,%1,%2
5944    sl<g>\t%0,%2
5945    sl<y>\t%0,%2"
5946   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5947    (set_attr "cpu_facility" "*,z196,*,longdisp")
5948    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5949
5950 ; slr, sl, sly, slgr, slg, slrk, slgrk
5951 (define_insn "*sub<mode>3_cc"
5952   [(set (reg CC_REGNUM)
5953         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5954                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5955                  (const_int 0)))
5956    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5957         (minus:GPR (match_dup 1) (match_dup 2)))]
5958   "s390_match_ccmode (insn, CCLmode)"
5959   "@
5960    sl<g>r\t%0,%2
5961    sl<g>rk\t%0,%1,%2
5962    sl<g>\t%0,%2
5963    sl<y>\t%0,%2"
5964   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5965    (set_attr "cpu_facility" "*,z196,*,longdisp")
5966    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5967
5968 ; slr, sl, sly, slgr, slg, slrk, slgrk
5969 (define_insn "*sub<mode>3_cc2"
5970   [(set (reg CC_REGNUM)
5971         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5972                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5973    (set (match_operand:GPR 0 "register_operand"         "=d,d,d,d")
5974         (minus:GPR (match_dup 1) (match_dup 2)))]
5975   "s390_match_ccmode (insn, CCL3mode)"
5976   "@
5977    sl<g>r\t%0,%2
5978    sl<g>rk\t%0,%1,%2
5979    sl<g>\t%0,%2
5980    sl<y>\t%0,%2"
5981   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5982    (set_attr "cpu_facility" "*,z196,*,longdisp")
5983    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5984
5985 ; slr, sl, sly, slgr, slg, slrk, slgrk
5986 (define_insn "*sub<mode>3_cconly"
5987   [(set (reg CC_REGNUM)
5988         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5989                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5990                  (const_int 0)))
5991    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5992   "s390_match_ccmode (insn, CCLmode)"
5993   "@
5994    sl<g>r\t%0,%2
5995    sl<g>rk\t%0,%1,%2
5996    sl<g>\t%0,%2
5997    sl<y>\t%0,%2"
5998   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5999    (set_attr "cpu_facility" "*,z196,*,longdisp")
6000    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6001
6002
6003 ; slr, sl, sly, slgr, slg, slrk, slgrk
6004 (define_insn "*sub<mode>3_cconly2"
6005   [(set (reg CC_REGNUM)
6006         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6007                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
6008    (clobber (match_scratch:GPR 0                        "=d,d,d,d"))]
6009   "s390_match_ccmode (insn, CCL3mode)"
6010   "@
6011    sl<g>r\t%0,%2
6012    sl<g>rk\t%0,%1,%2
6013    sl<g>\t%0,%2
6014    sl<y>\t%0,%2"
6015   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
6016    (set_attr "cpu_facility" "*,z196,*,longdisp")
6017    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6018
6019
6020 ;
6021 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
6022 ;
6023
6024 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6025 (define_insn "sub<mode>3"
6026   [(set (match_operand:FP           0 "register_operand" "=f,f,f,v")
6027         (minus:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
6028                   (match_operand:FP 2 "general_operand"   "f,f,R,v")))
6029    (clobber (reg:CC CC_REGNUM))]
6030   "TARGET_HARD_FLOAT"
6031   "@
6032    s<xde>tr\t%0,%1,%2
6033    s<xde>br\t%0,%2
6034    s<xde>b\t%0,%2
6035    wfsdb\t%v0,%v1,%v2"
6036   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6037    (set_attr "type"         "fsimp<mode>")
6038    (set_attr "cpu_facility" "*,*,*,vec")
6039    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6040
6041 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6042 (define_insn "*sub<mode>3_cc"
6043   [(set (reg CC_REGNUM)
6044         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6045                            (match_operand:FP 2 "general_operand"      "f,f,R"))
6046                  (match_operand:FP 3 "const0_operand" "")))
6047    (set (match_operand:FP 0 "register_operand" "=f,f,f")
6048         (minus:FP (match_dup 1) (match_dup 2)))]
6049   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6050   "@
6051    s<xde>tr\t%0,%1,%2
6052    s<xde>br\t%0,%2
6053    s<xde>b\t%0,%2"
6054   [(set_attr "op_type"  "RRF,RRE,RXE")
6055    (set_attr "type"     "fsimp<mode>")
6056    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
6057
6058 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6059 (define_insn "*sub<mode>3_cconly"
6060   [(set (reg CC_REGNUM)
6061         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6062                            (match_operand:FP 2 "general_operand"      "f,f,R"))
6063                  (match_operand:FP 3 "const0_operand" "")))
6064    (clobber (match_scratch:FP 0 "=f,f,f"))]
6065   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6066   "@
6067    s<xde>tr\t%0,%1,%2
6068    s<xde>br\t%0,%2
6069    s<xde>b\t%0,%2"
6070   [(set_attr "op_type"  "RRF,RRE,RXE")
6071    (set_attr "type"     "fsimp<mode>")
6072    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
6073
6074
6075 ;;
6076 ;;- Conditional add/subtract instructions.
6077 ;;
6078
6079 ;
6080 ; add(di|si)cc instruction pattern(s).
6081 ;
6082
6083 ; the following 4 patterns are used when the result of an add with
6084 ; carry is checked for an overflow condition
6085
6086 ; op1 + op2 + c < op1
6087
6088 ; alcr, alc, alcgr, alcg
6089 (define_insn "*add<mode>3_alc_carry1_cc"
6090   [(set (reg CC_REGNUM)
6091         (compare
6092           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6093                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6094                     (match_operand:GPR 2 "general_operand" "d,T"))
6095           (match_dup 1)))
6096    (set (match_operand:GPR 0 "register_operand" "=d,d")
6097         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6098   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6099   "@
6100    alc<g>r\t%0,%2
6101    alc<g>\t%0,%2"
6102   [(set_attr "op_type"  "RRE,RXY")
6103    (set_attr "z196prop" "z196_alone,z196_alone")])
6104
6105 ; alcr, alc, alcgr, alcg
6106 (define_insn "*add<mode>3_alc_carry1_cconly"
6107   [(set (reg CC_REGNUM)
6108         (compare
6109           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6110                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6111                     (match_operand:GPR 2 "general_operand" "d,T"))
6112           (match_dup 1)))
6113    (clobber (match_scratch:GPR 0 "=d,d"))]
6114   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6115   "@
6116    alc<g>r\t%0,%2
6117    alc<g>\t%0,%2"
6118   [(set_attr "op_type"  "RRE,RXY")
6119    (set_attr "z196prop" "z196_alone,z196_alone")])
6120
6121 ; op1 + op2 + c < op2
6122
6123 ; alcr, alc, alcgr, alcg
6124 (define_insn "*add<mode>3_alc_carry2_cc"
6125   [(set (reg CC_REGNUM)
6126         (compare
6127           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6128                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6129                     (match_operand:GPR 2 "general_operand" "d,T"))
6130           (match_dup 2)))
6131    (set (match_operand:GPR 0 "register_operand" "=d,d")
6132         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6133   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6134   "@
6135    alc<g>r\t%0,%2
6136    alc<g>\t%0,%2"
6137   [(set_attr "op_type"  "RRE,RXY")])
6138
6139 ; alcr, alc, alcgr, alcg
6140 (define_insn "*add<mode>3_alc_carry2_cconly"
6141   [(set (reg CC_REGNUM)
6142         (compare
6143           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6144                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6145                     (match_operand:GPR 2 "general_operand" "d,T"))
6146           (match_dup 2)))
6147    (clobber (match_scratch:GPR 0 "=d,d"))]
6148   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6149   "@
6150    alc<g>r\t%0,%2
6151    alc<g>\t%0,%2"
6152   [(set_attr "op_type"  "RRE,RXY")])
6153
6154 ; alcr, alc, alcgr, alcg
6155 (define_insn "*add<mode>3_alc_cc"
6156   [(set (reg CC_REGNUM)
6157         (compare
6158           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6159                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6160                     (match_operand:GPR 2 "general_operand" "d,T"))
6161           (const_int 0)))
6162    (set (match_operand:GPR 0 "register_operand" "=d,d")
6163         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6164   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6165   "@
6166    alc<g>r\t%0,%2
6167    alc<g>\t%0,%2"
6168   [(set_attr "op_type"  "RRE,RXY")])
6169
6170 ; alcr, alc, alcgr, alcg
6171 (define_insn "*add<mode>3_alc"
6172   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6173         (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6174                             (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6175                   (match_operand:GPR 2 "general_operand" "d,T")))
6176    (clobber (reg:CC CC_REGNUM))]
6177   "TARGET_CPU_ZARCH"
6178   "@
6179    alc<g>r\t%0,%2
6180    alc<g>\t%0,%2"
6181   [(set_attr "op_type"  "RRE,RXY")])
6182
6183 ; slbr, slb, slbgr, slbg
6184 (define_insn "*sub<mode>3_slb_cc"
6185   [(set (reg CC_REGNUM)
6186         (compare
6187           (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6188                                 (match_operand:GPR 2 "general_operand" "d,T"))
6189                      (match_operand:GPR 3 "s390_slb_comparison" ""))
6190           (const_int 0)))
6191    (set (match_operand:GPR 0 "register_operand" "=d,d")
6192         (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6193   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6194   "@
6195    slb<g>r\t%0,%2
6196    slb<g>\t%0,%2"
6197   [(set_attr "op_type"  "RRE,RXY")
6198    (set_attr "z10prop" "z10_c,*")])
6199
6200 ; slbr, slb, slbgr, slbg
6201 (define_insn "*sub<mode>3_slb"
6202   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6203         (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6204                               (match_operand:GPR 2 "general_operand" "d,T"))
6205                    (match_operand:GPR 3 "s390_slb_comparison" "")))
6206    (clobber (reg:CC CC_REGNUM))]
6207   "TARGET_CPU_ZARCH"
6208   "@
6209    slb<g>r\t%0,%2
6210    slb<g>\t%0,%2"
6211   [(set_attr "op_type"  "RRE,RXY")
6212    (set_attr "z10prop" "z10_c,*")])
6213
6214 (define_expand "add<mode>cc"
6215   [(match_operand:GPR 0 "register_operand" "")
6216    (match_operand 1 "comparison_operator" "")
6217    (match_operand:GPR 2 "register_operand" "")
6218    (match_operand:GPR 3 "const_int_operand" "")]
6219   "TARGET_CPU_ZARCH"
6220   "if (!s390_expand_addcc (GET_CODE (operands[1]),
6221                            XEXP (operands[1], 0), XEXP (operands[1], 1),
6222                            operands[0], operands[2],
6223                            operands[3])) FAIL; DONE;")
6224
6225 ;
6226 ; scond instruction pattern(s).
6227 ;
6228
6229 (define_insn_and_split "*scond<mode>"
6230   [(set (match_operand:GPR 0 "register_operand" "=&d")
6231         (match_operand:GPR 1 "s390_alc_comparison" ""))
6232    (clobber (reg:CC CC_REGNUM))]
6233   "TARGET_CPU_ZARCH"
6234   "#"
6235   "&& reload_completed"
6236   [(set (match_dup 0) (const_int 0))
6237    (parallel
6238     [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6239                                   (match_dup 0)))
6240      (clobber (reg:CC CC_REGNUM))])]
6241   "")
6242
6243 (define_insn_and_split "*scond<mode>_neg"
6244   [(set (match_operand:GPR 0 "register_operand" "=&d")
6245         (match_operand:GPR 1 "s390_slb_comparison" ""))
6246    (clobber (reg:CC CC_REGNUM))]
6247   "TARGET_CPU_ZARCH"
6248   "#"
6249   "&& reload_completed"
6250   [(set (match_dup 0) (const_int 0))
6251    (parallel
6252     [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6253                                    (match_dup 1)))
6254      (clobber (reg:CC CC_REGNUM))])
6255    (parallel
6256     [(set (match_dup 0) (neg:GPR (match_dup 0)))
6257      (clobber (reg:CC CC_REGNUM))])]
6258   "")
6259
6260
6261 (define_expand "cstore<mode>4"
6262   [(set (match_operand:SI 0 "register_operand" "")
6263         (match_operator:SI 1 "s390_scond_operator"
6264          [(match_operand:GPR 2 "register_operand" "")
6265           (match_operand:GPR 3 "general_operand" "")]))]
6266   "TARGET_CPU_ZARCH"
6267   "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6268                            operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6269
6270 (define_expand "cstorecc4"
6271   [(parallel
6272     [(set (match_operand:SI 0 "register_operand" "")
6273           (match_operator:SI 1 "s390_eqne_operator"
6274            [(match_operand:CCZ1 2 "register_operand")
6275             (match_operand 3 "const0_operand")]))
6276      (clobber (reg:CC CC_REGNUM))])]
6277   ""
6278   "emit_insn (gen_sne (operands[0], operands[2]));
6279    if (GET_CODE (operands[1]) == EQ)
6280      emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6281    DONE;")
6282
6283 (define_insn_and_split "sne"
6284   [(set (match_operand:SI 0 "register_operand" "=d")
6285         (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6286                (const_int 0)))
6287    (clobber (reg:CC CC_REGNUM))]
6288   ""
6289   "#"
6290   "reload_completed"
6291   [(parallel
6292     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6293      (clobber (reg:CC CC_REGNUM))])])
6294
6295
6296 ;;
6297 ;; - Conditional move instructions (introduced with z196)
6298 ;;
6299
6300 (define_expand "mov<mode>cc"
6301   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6302         (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6303                           (match_operand:GPR 2 "nonimmediate_operand" "")
6304                           (match_operand:GPR 3 "nonimmediate_operand" "")))]
6305   "TARGET_Z196"
6306 {
6307   /* Emit the comparison insn in case we do not already have a comparison result.  */
6308   if (!s390_comparison (operands[1], VOIDmode))
6309     operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6310                                      XEXP (operands[1], 0),
6311                                      XEXP (operands[1], 1));
6312 })
6313
6314 ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
6315 (define_insn_and_split "*mov<mode>cc"
6316   [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d,d,d,d,d,S,S,&d")
6317         (if_then_else:GPR
6318           (match_operator 1 "s390_comparison"
6319             [(match_operand 2 "cc_reg_operand"        " c,c,c,c,c,c,c,c,c")
6320              (match_operand 5 "const_int_operand"     "")])
6321           (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S")
6322           (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))]
6323   "TARGET_Z196"
6324   "@
6325    loc<g>r%C1\t%0,%3
6326    loc<g>r%D1\t%0,%4
6327    loc<g>%C1\t%0,%3
6328    loc<g>%D1\t%0,%4
6329    loc<g>hi%C1\t%0,%h3
6330    loc<g>hi%D1\t%0,%h4
6331    stoc<g>%C1\t%3,%0
6332    stoc<g>%D1\t%4,%0
6333    #"
6334   "&& reload_completed
6335    && MEM_P (operands[3]) && MEM_P (operands[4])"
6336   [(set (match_dup 0)
6337         (if_then_else:GPR
6338          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6339          (match_dup 3)
6340          (match_dup 0)))
6341    (set (match_dup 0)
6342         (if_then_else:GPR
6343          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6344          (match_dup 0)
6345          (match_dup 4)))]
6346   ""
6347   [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*")
6348    (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")])
6349
6350 ;;
6351 ;;- Multiply instructions.
6352 ;;
6353
6354 ;
6355 ; muldi3 instruction pattern(s).
6356 ;
6357
6358 (define_insn "*muldi3_sign"
6359   [(set (match_operand:DI 0 "register_operand" "=d,d")
6360         (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
6361                  (match_operand:DI 1 "register_operand" "0,0")))]
6362   "TARGET_ZARCH"
6363   "@
6364    msgfr\t%0,%2
6365    msgf\t%0,%2"
6366   [(set_attr "op_type"      "RRE,RXY")
6367    (set_attr "type"         "imuldi")])
6368
6369 (define_insn "muldi3"
6370   [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6371         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6372                  (match_operand:DI 2 "general_operand" "d,K,T,Os")))]
6373   "TARGET_ZARCH"
6374   "@
6375    msgr\t%0,%2
6376    mghi\t%0,%h2
6377    msg\t%0,%2
6378    msgfi\t%0,%2"
6379   [(set_attr "op_type"      "RRE,RI,RXY,RIL")
6380    (set_attr "type"         "imuldi")
6381    (set_attr "cpu_facility" "*,*,*,z10")])
6382
6383 ;
6384 ; mulsi3 instruction pattern(s).
6385 ;
6386
6387 (define_insn "*mulsi3_sign"
6388   [(set (match_operand:SI 0 "register_operand" "=d,d")
6389         (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6390                  (match_operand:SI 1 "register_operand" "0,0")))]
6391   ""
6392   "@
6393    mh\t%0,%2
6394    mhy\t%0,%2"
6395   [(set_attr "op_type"      "RX,RXY")
6396    (set_attr "type"         "imulhi")
6397    (set_attr "cpu_facility" "*,z10")])
6398
6399 (define_insn "mulsi3"
6400   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6401         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6402                   (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6403   ""
6404   "@
6405    msr\t%0,%2
6406    mhi\t%0,%h2
6407    ms\t%0,%2
6408    msy\t%0,%2
6409    msfi\t%0,%2"
6410   [(set_attr "op_type"      "RRE,RI,RX,RXY,RIL")
6411    (set_attr "type"         "imulsi,imulhi,imulsi,imulsi,imulsi")
6412    (set_attr "cpu_facility" "*,*,*,longdisp,z10")])
6413
6414 ;
6415 ; mulsidi3 instruction pattern(s).
6416 ;
6417
6418 (define_insn "mulsidi3"
6419   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6420         (mult:DI (sign_extend:DI
6421                    (match_operand:SI 1 "register_operand" "%0,0,0"))
6422                  (sign_extend:DI
6423                    (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6424   "!TARGET_ZARCH"
6425   "@
6426    mr\t%0,%2
6427    m\t%0,%2
6428    mfy\t%0,%2"
6429   [(set_attr "op_type"      "RR,RX,RXY")
6430    (set_attr "type"         "imulsi")
6431    (set_attr "cpu_facility" "*,*,z10")])
6432
6433 ;
6434 ; umul instruction pattern(s).
6435 ;
6436
6437 ; mlr, ml, mlgr, mlg
6438 (define_insn "umul<dwh><mode>3"
6439   [(set (match_operand:DW 0 "register_operand"                   "=d,d")
6440         (mult:DW (zero_extend:DW
6441                    (match_operand:<DWH> 1 "register_operand"     "%0,0"))
6442                  (zero_extend:DW
6443                    (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
6444   "TARGET_CPU_ZARCH"
6445   "@
6446    ml<tg>r\t%0,%2
6447    ml<tg>\t%0,%2"
6448   [(set_attr "op_type"  "RRE,RXY")
6449    (set_attr "type"     "imul<dwh>")])
6450
6451 ;
6452 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6453 ;
6454
6455 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6456 (define_insn "mul<mode>3"
6457   [(set (match_operand:FP          0 "register_operand"     "=f,f,f,v")
6458         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
6459                  (match_operand:FP 2 "general_operand"       "f,f,R,v")))]
6460   "TARGET_HARD_FLOAT"
6461   "@
6462    m<xdee>tr\t%0,%1,%2
6463    m<xdee>br\t%0,%2
6464    m<xdee>b\t%0,%2
6465    wfmdb\t%v0,%v1,%v2"
6466   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6467    (set_attr "type"         "fmul<mode>")
6468    (set_attr "cpu_facility" "*,*,*,vec")
6469    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6470
6471 ; madbr, maebr, maxb, madb, maeb
6472 (define_insn "fma<mode>4"
6473   [(set (match_operand:DSF          0 "register_operand"     "=f,f,v")
6474         (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6475                  (match_operand:DSF 2 "nonimmediate_operand"  "f,R,v")
6476                  (match_operand:DSF 3 "register_operand"      "0,0,v")))]
6477   "TARGET_HARD_FLOAT"
6478   "@
6479    ma<xde>br\t%0,%1,%2
6480    ma<xde>b\t%0,%1,%2
6481    wfmadb\t%v0,%v1,%v2,%v3"
6482   [(set_attr "op_type"      "RRE,RXE,VRR")
6483    (set_attr "type"         "fmadd<mode>")
6484    (set_attr "cpu_facility" "*,*,vec")
6485    (set_attr "enabled"      "*,*,<DFDI>")])
6486
6487 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6488 (define_insn "fms<mode>4"
6489   [(set (match_operand:DSF                   0 "register_operand"     "=f,f,v")
6490         (fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,v")
6491                  (match_operand:DSF          2 "nonimmediate_operand"  "f,R,v")
6492                  (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,v"))))]
6493   "TARGET_HARD_FLOAT"
6494   "@
6495    ms<xde>br\t%0,%1,%2
6496    ms<xde>b\t%0,%1,%2
6497    wfmsdb\t%v0,%v1,%v2,%v3"
6498   [(set_attr "op_type"      "RRE,RXE,VRR")
6499    (set_attr "type"         "fmadd<mode>")
6500    (set_attr "cpu_facility" "*,*,vec")
6501    (set_attr "enabled"      "*,*,<DFDI>")])
6502
6503 ;;
6504 ;;- Divide and modulo instructions.
6505 ;;
6506
6507 ;
6508 ; divmoddi4 instruction pattern(s).
6509 ;
6510
6511 (define_expand "divmoddi4"
6512   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6513                    (div:DI (match_operand:DI 1 "register_operand" "")
6514                            (match_operand:DI 2 "general_operand" "")))
6515               (set (match_operand:DI 3 "general_operand" "")
6516                    (mod:DI (match_dup 1) (match_dup 2)))])
6517    (clobber (match_dup 4))]
6518   "TARGET_ZARCH"
6519 {
6520   rtx insn, div_equal, mod_equal;
6521
6522   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6523   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6524
6525   operands[4] = gen_reg_rtx(TImode);
6526   emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6527
6528   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6529   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6530
6531   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6532   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6533
6534   DONE;
6535 })
6536
6537 (define_insn "divmodtidi3"
6538   [(set (match_operand:TI 0 "register_operand" "=d,d")
6539         (ior:TI
6540           (ashift:TI
6541             (zero_extend:TI
6542               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6543                       (match_operand:DI 2 "general_operand" "d,T")))
6544             (const_int 64))
6545           (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6546   "TARGET_ZARCH"
6547   "@
6548    dsgr\t%0,%2
6549    dsg\t%0,%2"
6550   [(set_attr "op_type"  "RRE,RXY")
6551    (set_attr "type"     "idiv")])
6552
6553 (define_insn "divmodtisi3"
6554   [(set (match_operand:TI 0 "register_operand" "=d,d")
6555         (ior:TI
6556           (ashift:TI
6557             (zero_extend:TI
6558               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6559                       (sign_extend:DI
6560                         (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
6561             (const_int 64))
6562           (zero_extend:TI
6563             (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6564   "TARGET_ZARCH"
6565   "@
6566    dsgfr\t%0,%2
6567    dsgf\t%0,%2"
6568   [(set_attr "op_type"  "RRE,RXY")
6569    (set_attr "type"     "idiv")])
6570
6571 ;
6572 ; udivmoddi4 instruction pattern(s).
6573 ;
6574
6575 (define_expand "udivmoddi4"
6576   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6577                    (udiv:DI (match_operand:DI 1 "general_operand" "")
6578                             (match_operand:DI 2 "nonimmediate_operand" "")))
6579               (set (match_operand:DI 3 "general_operand" "")
6580                    (umod:DI (match_dup 1) (match_dup 2)))])
6581    (clobber (match_dup 4))]
6582   "TARGET_ZARCH"
6583 {
6584   rtx insn, div_equal, mod_equal, equal;
6585
6586   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6587   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6588   equal = gen_rtx_IOR (TImode,
6589                        gen_rtx_ASHIFT (TImode,
6590                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6591                                        GEN_INT (64)),
6592                        gen_rtx_ZERO_EXTEND (TImode, div_equal));
6593
6594   operands[4] = gen_reg_rtx(TImode);
6595   emit_clobber (operands[4]);
6596   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6597   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6598
6599   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6600   set_unique_reg_note (insn, REG_EQUAL, equal);
6601
6602   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6603   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6604
6605   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6606   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6607
6608   DONE;
6609 })
6610
6611 (define_insn "udivmodtidi3"
6612   [(set (match_operand:TI 0 "register_operand" "=d,d")
6613         (ior:TI
6614           (ashift:TI
6615             (zero_extend:TI
6616               (truncate:DI
6617                 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6618                          (zero_extend:TI
6619                            (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
6620             (const_int 64))
6621           (zero_extend:TI
6622             (truncate:DI
6623               (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6624   "TARGET_ZARCH"
6625   "@
6626    dlgr\t%0,%2
6627    dlg\t%0,%2"
6628   [(set_attr "op_type"  "RRE,RXY")
6629    (set_attr "type"     "idiv")])
6630
6631 ;
6632 ; divmodsi4 instruction pattern(s).
6633 ;
6634
6635 (define_expand "divmodsi4"
6636   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6637                    (div:SI (match_operand:SI 1 "general_operand" "")
6638                            (match_operand:SI 2 "nonimmediate_operand" "")))
6639               (set (match_operand:SI 3 "general_operand" "")
6640                    (mod:SI (match_dup 1) (match_dup 2)))])
6641    (clobber (match_dup 4))]
6642   "!TARGET_ZARCH"
6643 {
6644   rtx insn, div_equal, mod_equal, equal;
6645
6646   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6647   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6648   equal = gen_rtx_IOR (DImode,
6649                        gen_rtx_ASHIFT (DImode,
6650                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6651                                        GEN_INT (32)),
6652                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6653
6654   operands[4] = gen_reg_rtx(DImode);
6655   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6656
6657   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6658   set_unique_reg_note (insn, REG_EQUAL, equal);
6659
6660   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6661   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6662
6663   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6664   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6665
6666   DONE;
6667 })
6668
6669 (define_insn "divmoddisi3"
6670   [(set (match_operand:DI 0 "register_operand" "=d,d")
6671         (ior:DI
6672           (ashift:DI
6673             (zero_extend:DI
6674               (truncate:SI
6675                 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6676                         (sign_extend:DI
6677                           (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6678             (const_int 32))
6679           (zero_extend:DI
6680             (truncate:SI
6681               (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6682   "!TARGET_ZARCH"
6683   "@
6684    dr\t%0,%2
6685    d\t%0,%2"
6686   [(set_attr "op_type"  "RR,RX")
6687    (set_attr "type"     "idiv")])
6688
6689 ;
6690 ; udivsi3 and umodsi3 instruction pattern(s).
6691 ;
6692
6693 (define_expand "udivmodsi4"
6694   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6695                    (udiv:SI (match_operand:SI 1 "general_operand" "")
6696                             (match_operand:SI 2 "nonimmediate_operand" "")))
6697               (set (match_operand:SI 3 "general_operand" "")
6698                    (umod:SI (match_dup 1) (match_dup 2)))])
6699    (clobber (match_dup 4))]
6700   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6701 {
6702   rtx insn, div_equal, mod_equal, equal;
6703
6704   div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6705   mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6706   equal = gen_rtx_IOR (DImode,
6707                        gen_rtx_ASHIFT (DImode,
6708                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6709                                        GEN_INT (32)),
6710                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6711
6712   operands[4] = gen_reg_rtx(DImode);
6713   emit_clobber (operands[4]);
6714   emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6715   emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6716
6717   insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6718   set_unique_reg_note (insn, REG_EQUAL, equal);
6719
6720   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6721   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6722
6723   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6724   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6725
6726   DONE;
6727 })
6728
6729 (define_insn "udivmoddisi3"
6730   [(set (match_operand:DI 0 "register_operand" "=d,d")
6731         (ior:DI
6732           (ashift:DI
6733             (zero_extend:DI
6734               (truncate:SI
6735                 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6736                          (zero_extend:DI
6737                            (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
6738             (const_int 32))
6739           (zero_extend:DI
6740             (truncate:SI
6741               (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6742   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6743   "@
6744    dlr\t%0,%2
6745    dl\t%0,%2"
6746   [(set_attr "op_type"  "RRE,RXY")
6747    (set_attr "type"     "idiv")])
6748
6749 (define_expand "udivsi3"
6750   [(set (match_operand:SI 0 "register_operand" "=d")
6751         (udiv:SI (match_operand:SI 1 "general_operand" "")
6752                  (match_operand:SI 2 "general_operand" "")))
6753    (clobber (match_dup 3))]
6754   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6755 {
6756   rtx insn, udiv_equal, umod_equal, equal;
6757
6758   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6759   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6760   equal = gen_rtx_IOR (DImode,
6761                        gen_rtx_ASHIFT (DImode,
6762                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6763                                        GEN_INT (32)),
6764                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6765
6766   operands[3] = gen_reg_rtx (DImode);
6767
6768   if (CONSTANT_P (operands[2]))
6769     {
6770       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6771         {
6772           rtx_code_label *label1 = gen_label_rtx ();
6773
6774           operands[1] = make_safe_from (operands[1], operands[0]);
6775           emit_move_insn (operands[0], const0_rtx);
6776           emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6777                                    SImode, 1, label1);
6778           emit_move_insn (operands[0], const1_rtx);
6779           emit_label (label1);
6780         }
6781       else
6782         {
6783           operands[2] = force_reg (SImode, operands[2]);
6784           operands[2] = make_safe_from (operands[2], operands[0]);
6785
6786           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6787           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6788                                              operands[2]));
6789           set_unique_reg_note (insn, REG_EQUAL, equal);
6790
6791           insn = emit_move_insn (operands[0],
6792                                  gen_lowpart (SImode, operands[3]));
6793           set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6794         }
6795     }
6796   else
6797     {
6798       rtx_code_label *label1 = gen_label_rtx ();
6799       rtx_code_label *label2 = gen_label_rtx ();
6800       rtx_code_label *label3 = gen_label_rtx ();
6801
6802       operands[1] = force_reg (SImode, operands[1]);
6803       operands[1] = make_safe_from (operands[1], operands[0]);
6804       operands[2] = force_reg (SImode, operands[2]);
6805       operands[2] = make_safe_from (operands[2], operands[0]);
6806
6807       emit_move_insn (operands[0], const0_rtx);
6808       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6809                                SImode, 1, label3);
6810       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6811                                SImode, 0, label2);
6812       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6813                                SImode, 0, label1);
6814       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6815       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6816                                          operands[2]));
6817       set_unique_reg_note (insn, REG_EQUAL, equal);
6818
6819       insn = emit_move_insn (operands[0],
6820                              gen_lowpart (SImode, operands[3]));
6821       set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6822
6823       emit_jump (label3);
6824       emit_label (label1);
6825       emit_move_insn (operands[0], operands[1]);
6826       emit_jump (label3);
6827       emit_label (label2);
6828       emit_move_insn (operands[0], const1_rtx);
6829       emit_label (label3);
6830     }
6831   emit_move_insn (operands[0], operands[0]);
6832   DONE;
6833 })
6834
6835 (define_expand "umodsi3"
6836   [(set (match_operand:SI 0 "register_operand" "=d")
6837         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6838                  (match_operand:SI 2 "nonimmediate_operand" "")))
6839    (clobber (match_dup 3))]
6840   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6841 {
6842   rtx insn, udiv_equal, umod_equal, equal;
6843
6844   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6845   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6846   equal = gen_rtx_IOR (DImode,
6847                        gen_rtx_ASHIFT (DImode,
6848                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6849                                        GEN_INT (32)),
6850                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6851
6852   operands[3] = gen_reg_rtx (DImode);
6853
6854   if (CONSTANT_P (operands[2]))
6855     {
6856       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6857         {
6858           rtx_code_label *label1 = gen_label_rtx ();
6859
6860           operands[1] = make_safe_from (operands[1], operands[0]);
6861           emit_move_insn (operands[0], operands[1]);
6862           emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6863                                    SImode, 1, label1);
6864           emit_insn (gen_abssi2 (operands[0], operands[2]));
6865           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6866           emit_label (label1);
6867         }
6868       else
6869         {
6870           operands[2] = force_reg (SImode, operands[2]);
6871           operands[2] = make_safe_from (operands[2], operands[0]);
6872
6873           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6874           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6875                                              operands[2]));
6876           set_unique_reg_note (insn, REG_EQUAL, equal);
6877
6878           insn = emit_move_insn (operands[0],
6879                                  gen_highpart (SImode, operands[3]));
6880           set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6881         }
6882     }
6883   else
6884     {
6885       rtx_code_label *label1 = gen_label_rtx ();
6886       rtx_code_label *label2 = gen_label_rtx ();
6887       rtx_code_label *label3 = gen_label_rtx ();
6888
6889       operands[1] = force_reg (SImode, operands[1]);
6890       operands[1] = make_safe_from (operands[1], operands[0]);
6891       operands[2] = force_reg (SImode, operands[2]);
6892       operands[2] = make_safe_from (operands[2], operands[0]);
6893
6894       emit_move_insn(operands[0], operands[1]);
6895       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6896                                SImode, 1, label3);
6897       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6898                                SImode, 0, label2);
6899       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6900                                SImode, 0, label1);
6901       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6902       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6903                                          operands[2]));
6904       set_unique_reg_note (insn, REG_EQUAL, equal);
6905
6906       insn = emit_move_insn (operands[0],
6907                              gen_highpart (SImode, operands[3]));
6908       set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6909
6910       emit_jump (label3);
6911       emit_label (label1);
6912       emit_move_insn (operands[0], const0_rtx);
6913       emit_jump (label3);
6914       emit_label (label2);
6915       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6916       emit_label (label3);
6917     }
6918   DONE;
6919 })
6920
6921 ;
6922 ; div(df|sf)3 instruction pattern(s).
6923 ;
6924
6925 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6926 (define_insn "div<mode>3"
6927   [(set (match_operand:FP         0 "register_operand" "=f,f,f,v")
6928         (div:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
6929                 (match_operand:FP 2 "general_operand"   "f,f,R,v")))]
6930   "TARGET_HARD_FLOAT"
6931   "@
6932    d<xde>tr\t%0,%1,%2
6933    d<xde>br\t%0,%2
6934    d<xde>b\t%0,%2
6935    wfddb\t%v0,%v1,%v2"
6936   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6937    (set_attr "type"         "fdiv<mode>")
6938    (set_attr "cpu_facility" "*,*,*,vec")
6939    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6940
6941
6942 ;;
6943 ;;- And instructions.
6944 ;;
6945
6946 (define_expand "and<mode>3"
6947   [(set (match_operand:INT 0 "nonimmediate_operand" "")
6948         (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6949                  (match_operand:INT 2 "general_operand" "")))
6950    (clobber (reg:CC CC_REGNUM))]
6951   ""
6952   "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6953
6954 ;
6955 ; anddi3 instruction pattern(s).
6956 ;
6957
6958 (define_insn "*anddi3_cc"
6959   [(set (reg CC_REGNUM)
6960         (compare
6961           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,    d")
6962                   (match_operand:DI 2 "general_operand"      " d,d,T,NxxDq"))
6963           (const_int 0)))
6964    (set (match_operand:DI 0 "register_operand"               "=d,d,d,    d")
6965         (and:DI (match_dup 1) (match_dup 2)))]
6966   "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6967   "@
6968    ngr\t%0,%2
6969    ngrk\t%0,%1,%2
6970    ng\t%0,%2
6971    risbg\t%0,%1,%s2,128+%e2,0"
6972   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6973    (set_attr "cpu_facility" "*,z196,*,z10")
6974    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6975
6976 (define_insn "*anddi3_cconly"
6977   [(set (reg CC_REGNUM)
6978         (compare
6979           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,    d")
6980                   (match_operand:DI 2 "general_operand"      " d,d,T,NxxDq"))
6981                  (const_int 0)))
6982    (clobber (match_scratch:DI 0                              "=d,d,d,    d"))]
6983   "TARGET_ZARCH
6984    && s390_match_ccmode(insn, CCTmode)
6985    /* Do not steal TM patterns.  */
6986    && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6987   "@
6988    ngr\t%0,%2
6989    ngrk\t%0,%1,%2
6990    ng\t%0,%2
6991    risbg\t%0,%1,%s2,128+%e2,0"
6992   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6993    (set_attr "cpu_facility" "*,z196,*,z10")
6994    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6995
6996 (define_insn "*anddi3"
6997   [(set (match_operand:DI 0 "nonimmediate_operand"
6998             "=d,d,    d,    d,    d,    d,    d,    d,d,d,d,    d,   AQ,Q")
6999         (and:DI
7000           (match_operand:DI 1 "nonimmediate_operand"
7001             "%d,o,    0,    0,    0,    0,    0,    0,0,d,0,    d,    0,0")
7002           (match_operand:DI 2 "general_operand"
7003             "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDq,NxQDF,Q")))
7004    (clobber (reg:CC CC_REGNUM))]
7005   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7006   "@
7007    #
7008    #
7009    nihh\t%0,%j2
7010    nihl\t%0,%j2
7011    nilh\t%0,%j2
7012    nill\t%0,%j2
7013    nihf\t%0,%m2
7014    nilf\t%0,%m2
7015    ngr\t%0,%2
7016    ngrk\t%0,%1,%2
7017    ng\t%0,%2
7018    risbg\t%0,%1,%s2,128+%e2,0
7019    #
7020    #"
7021   [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
7022    (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
7023    (set_attr "z10prop" "*,
7024                         *,
7025                         z10_super_E1,
7026                         z10_super_E1,
7027                         z10_super_E1,
7028                         z10_super_E1,
7029                         z10_super_E1,
7030                         z10_super_E1,
7031                         z10_super_E1,
7032                         *,
7033                         z10_super_E1,
7034                         z10_super_E1,
7035                         *,
7036                         *")])
7037
7038 (define_split
7039   [(set (match_operand:DI 0 "s_operand" "")
7040         (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7041    (clobber (reg:CC CC_REGNUM))]
7042   "reload_completed"
7043   [(parallel
7044     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7045      (clobber (reg:CC CC_REGNUM))])]
7046   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7047
7048 ;; These two are what combine generates for (ashift (zero_extract)).
7049 (define_insn "*extzv_<mode>_srl"
7050   [(set (match_operand:GPR 0 "register_operand" "=d")
7051         (and:GPR (lshiftrt:GPR
7052                    (match_operand:GPR 1 "register_operand" "d")
7053                    (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7054                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
7055    (clobber (reg:CC CC_REGNUM))]
7056   "TARGET_Z10
7057    /* Note that even for the SImode pattern, the rotate is always DImode.  */
7058    && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
7059                            INTVAL (operands[3]))"
7060   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
7061   [(set_attr "op_type" "RIE")
7062    (set_attr "z10prop" "z10_super_E1")])
7063
7064 (define_insn "*extzv_<mode>_sll"
7065   [(set (match_operand:GPR 0 "register_operand" "=d")
7066         (and:GPR (ashift:GPR
7067                   (match_operand:GPR 1 "register_operand" "d")
7068                   (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7069                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
7070    (clobber (reg:CC CC_REGNUM))]
7071   "TARGET_Z10
7072    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
7073                            INTVAL (operands[3]))"
7074   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
7075   [(set_attr "op_type" "RIE")
7076    (set_attr "z10prop" "z10_super_E1")])
7077
7078
7079 ;
7080 ; andsi3 instruction pattern(s).
7081 ;
7082
7083 (define_insn "*andsi3_cc"
7084   [(set (reg CC_REGNUM)
7085         (compare
7086           (and:SI
7087             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
7088             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
7089           (const_int 0)))
7090    (set (match_operand:SI 0 "register_operand"         "=d,d,d,d,d,    d")
7091         (and:SI (match_dup 1) (match_dup 2)))]
7092   "s390_match_ccmode(insn, CCTmode)"
7093   "@
7094    nilf\t%0,%o2
7095    nr\t%0,%2
7096    nrk\t%0,%1,%2
7097    n\t%0,%2
7098    ny\t%0,%2
7099    risbg\t%0,%1,%t2,128+%f2,0"
7100   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
7101    (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7102    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7103                         z10_super_E1,z10_super_E1,z10_super_E1")])
7104
7105 (define_insn "*andsi3_cconly"
7106   [(set (reg CC_REGNUM)
7107         (compare
7108           (and:SI
7109             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
7110             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
7111           (const_int 0)))
7112    (clobber (match_scratch:SI 0                        "=d,d,d,d,d,    d"))]
7113   "s390_match_ccmode(insn, CCTmode)
7114    /* Do not steal TM patterns.  */
7115    && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7116   "@
7117    nilf\t%0,%o2
7118    nr\t%0,%2
7119    nrk\t%0,%1,%2
7120    n\t%0,%2
7121    ny\t%0,%2
7122    risbg\t%0,%1,%t2,128+%f2,0"
7123   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
7124    (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7125    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7126                         z10_super_E1,z10_super_E1,z10_super_E1")])
7127
7128 (define_insn "*andsi3_zarch"
7129   [(set (match_operand:SI 0 "nonimmediate_operand"
7130                             "=d,d,    d,    d, d,d,d,d,d,    d,   AQ,Q")
7131         (and:SI (match_operand:SI 1 "nonimmediate_operand"
7132                             "%d,o,    0,    0, 0,0,d,0,0,    d,    0,0")
7133                 (match_operand:SI 2 "general_operand"
7134                             " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
7135    (clobber (reg:CC CC_REGNUM))]
7136   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7137   "@
7138    #
7139    #
7140    nilh\t%0,%j2
7141    nill\t%0,%j2
7142    nilf\t%0,%o2
7143    nr\t%0,%2
7144    nrk\t%0,%1,%2
7145    n\t%0,%2
7146    ny\t%0,%2
7147    risbg\t%0,%1,%t2,128+%f2,0
7148    #
7149    #"
7150   [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7151    (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
7152    (set_attr "z10prop" "*,
7153                         *,
7154                         z10_super_E1,
7155                         z10_super_E1,
7156                         z10_super_E1,
7157                         z10_super_E1,
7158                         *,
7159                         z10_super_E1,
7160                         z10_super_E1,
7161                         z10_super_E1,
7162                         *,
7163                         *")])
7164
7165 (define_insn "*andsi3_esa"
7166   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,   AQ,Q")
7167         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,    0,0")
7168                 (match_operand:SI 2 "general_operand"      " d,R,NxQSF,Q")))
7169    (clobber (reg:CC CC_REGNUM))]
7170   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7171   "@
7172    nr\t%0,%2
7173    n\t%0,%2
7174    #
7175    #"
7176   [(set_attr "op_type"  "RR,RX,SI,SS")
7177    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7178
7179
7180 (define_split
7181   [(set (match_operand:SI 0 "s_operand" "")
7182         (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7183    (clobber (reg:CC CC_REGNUM))]
7184   "reload_completed"
7185   [(parallel
7186     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7187      (clobber (reg:CC CC_REGNUM))])]
7188   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7189
7190 ;
7191 ; andhi3 instruction pattern(s).
7192 ;
7193
7194 (define_insn "*andhi3_zarch"
7195   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7196         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7197                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQHF,Q")))
7198    (clobber (reg:CC CC_REGNUM))]
7199   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7200   "@
7201    nr\t%0,%2
7202    nrk\t%0,%1,%2
7203    nill\t%0,%x2
7204    #
7205    #"
7206   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7207    (set_attr "cpu_facility" "*,z196,*,*,*")
7208    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7209 ])
7210
7211 (define_insn "*andhi3_esa"
7212   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7213         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7214                 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7215    (clobber (reg:CC CC_REGNUM))]
7216   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7217   "@
7218    nr\t%0,%2
7219    #
7220    #"
7221   [(set_attr "op_type"  "RR,SI,SS")
7222    (set_attr "z10prop" "z10_super_E1,*,*")
7223 ])
7224
7225 (define_split
7226   [(set (match_operand:HI 0 "s_operand" "")
7227         (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7228    (clobber (reg:CC CC_REGNUM))]
7229   "reload_completed"
7230   [(parallel
7231     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7232      (clobber (reg:CC CC_REGNUM))])]
7233   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7234
7235 ;
7236 ; andqi3 instruction pattern(s).
7237 ;
7238
7239 (define_insn "*andqi3_zarch"
7240   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7241         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7242                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7243    (clobber (reg:CC CC_REGNUM))]
7244   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7245   "@
7246    nr\t%0,%2
7247    nrk\t%0,%1,%2
7248    nill\t%0,%b2
7249    ni\t%S0,%b2
7250    niy\t%S0,%b2
7251    #"
7252   [(set_attr "op_type"  "RR,RRF,RI,SI,SIY,SS")
7253    (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7254    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7255
7256 (define_insn "*andqi3_esa"
7257   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7258         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7259                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7260    (clobber (reg:CC CC_REGNUM))]
7261   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7262   "@
7263    nr\t%0,%2
7264    ni\t%S0,%b2
7265    #"
7266   [(set_attr "op_type"  "RR,SI,SS")
7267    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7268
7269 ;
7270 ; Block and (NC) patterns.
7271 ;
7272
7273 (define_insn "*nc"
7274   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7275         (and:BLK (match_dup 0)
7276                  (match_operand:BLK 1 "memory_operand" "Q")))
7277    (use (match_operand 2 "const_int_operand" "n"))
7278    (clobber (reg:CC CC_REGNUM))]
7279   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7280   "nc\t%O0(%2,%R0),%S1"
7281   [(set_attr "op_type" "SS")
7282    (set_attr "z196prop" "z196_cracked")])
7283
7284 (define_split
7285   [(set (match_operand 0 "memory_operand" "")
7286         (and (match_dup 0)
7287              (match_operand 1 "memory_operand" "")))
7288    (clobber (reg:CC CC_REGNUM))]
7289   "reload_completed
7290    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7291    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7292   [(parallel
7293     [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7294      (use (match_dup 2))
7295      (clobber (reg:CC CC_REGNUM))])]
7296 {
7297   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7298   operands[0] = adjust_address (operands[0], BLKmode, 0);
7299   operands[1] = adjust_address (operands[1], BLKmode, 0);
7300 })
7301
7302 (define_peephole2
7303   [(parallel
7304     [(set (match_operand:BLK 0 "memory_operand" "")
7305           (and:BLK (match_dup 0)
7306                    (match_operand:BLK 1 "memory_operand" "")))
7307      (use (match_operand 2 "const_int_operand" ""))
7308      (clobber (reg:CC CC_REGNUM))])
7309    (parallel
7310     [(set (match_operand:BLK 3 "memory_operand" "")
7311           (and:BLK (match_dup 3)
7312                    (match_operand:BLK 4 "memory_operand" "")))
7313      (use (match_operand 5 "const_int_operand" ""))
7314      (clobber (reg:CC CC_REGNUM))])]
7315   "s390_offset_p (operands[0], operands[3], operands[2])
7316    && s390_offset_p (operands[1], operands[4], operands[2])
7317    && !s390_overlap_p (operands[0], operands[1],
7318                        INTVAL (operands[2]) + INTVAL (operands[5]))
7319    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7320   [(parallel
7321     [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7322      (use (match_dup 8))
7323      (clobber (reg:CC CC_REGNUM))])]
7324   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7325    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7326    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7327
7328
7329 ;;
7330 ;;- Bit set (inclusive or) instructions.
7331 ;;
7332
7333 (define_expand "ior<mode>3"
7334   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7335         (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7336                  (match_operand:INT 2 "general_operand" "")))
7337    (clobber (reg:CC CC_REGNUM))]
7338   ""
7339   "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7340
7341 ;
7342 ; iordi3 instruction pattern(s).
7343 ;
7344
7345 (define_insn "*iordi3_cc"
7346   [(set (reg CC_REGNUM)
7347         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7348                          (match_operand:DI 2 "general_operand"      " d,d,T"))
7349                  (const_int 0)))
7350    (set (match_operand:DI 0 "register_operand"                      "=d,d,d")
7351         (ior:DI (match_dup 1) (match_dup 2)))]
7352   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7353   "@
7354    ogr\t%0,%2
7355    ogrk\t%0,%1,%2
7356    og\t%0,%2"
7357   [(set_attr "op_type"  "RRE,RRF,RXY")
7358    (set_attr "cpu_facility" "*,z196,*")
7359    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7360
7361 (define_insn "*iordi3_cconly"
7362   [(set (reg CC_REGNUM)
7363         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7364                          (match_operand:DI 2 "general_operand"      " d,d,T"))
7365                  (const_int 0)))
7366    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7367   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7368   "@
7369    ogr\t%0,%2
7370    ogrk\t%0,%1,%2
7371    og\t%0,%2"
7372   [(set_attr "op_type"  "RRE,RRF,RXY")
7373    (set_attr "cpu_facility" "*,z196,*")
7374    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7375
7376 (define_insn "*iordi3"
7377   [(set (match_operand:DI 0 "nonimmediate_operand"
7378                                "=d,    d,    d,    d,    d,    d,d,d,d,   AQ,Q")
7379         (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7380                             "   %0,    0,    0,    0,    0,    0,0,d,0,    0,0")
7381                 (match_operand:DI 2 "general_operand"
7382                             "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7383    (clobber (reg:CC CC_REGNUM))]
7384   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7385   "@
7386    oihh\t%0,%i2
7387    oihl\t%0,%i2
7388    oilh\t%0,%i2
7389    oill\t%0,%i2
7390    oihf\t%0,%k2
7391    oilf\t%0,%k2
7392    ogr\t%0,%2
7393    ogrk\t%0,%1,%2
7394    og\t%0,%2
7395    #
7396    #"
7397   [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7398    (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7399    (set_attr "z10prop" "z10_super_E1,
7400                         z10_super_E1,
7401                         z10_super_E1,
7402                         z10_super_E1,
7403                         z10_super_E1,
7404                         z10_super_E1,
7405                         z10_super_E1,
7406                         *,
7407                         z10_super_E1,
7408                         *,
7409                         *")])
7410
7411 (define_split
7412   [(set (match_operand:DI 0 "s_operand" "")
7413         (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7414    (clobber (reg:CC CC_REGNUM))]
7415   "reload_completed"
7416   [(parallel
7417     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7418      (clobber (reg:CC CC_REGNUM))])]
7419   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7420
7421 ;
7422 ; iorsi3 instruction pattern(s).
7423 ;
7424
7425 (define_insn "*iorsi3_cc"
7426   [(set (reg CC_REGNUM)
7427         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7428                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7429                  (const_int 0)))
7430    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7431         (ior:SI (match_dup 1) (match_dup 2)))]
7432   "s390_match_ccmode(insn, CCTmode)"
7433   "@
7434    oilf\t%0,%o2
7435    or\t%0,%2
7436    ork\t%0,%1,%2
7437    o\t%0,%2
7438    oy\t%0,%2"
7439   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7440    (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7441    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7442
7443 (define_insn "*iorsi3_cconly"
7444   [(set (reg CC_REGNUM)
7445         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7446                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7447                  (const_int 0)))
7448    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7449   "s390_match_ccmode(insn, CCTmode)"
7450   "@
7451    oilf\t%0,%o2
7452    or\t%0,%2
7453    ork\t%0,%1,%2
7454    o\t%0,%2
7455    oy\t%0,%2"
7456   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7457    (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7458    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7459
7460 (define_insn "*iorsi3_zarch"
7461   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,    d, d,d,d,d,d,   AQ,Q")
7462         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,    0, 0,0,d,0,0,    0,0")
7463                 (match_operand:SI 2 "general_operand"   "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7464    (clobber (reg:CC CC_REGNUM))]
7465   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7466   "@
7467    oilh\t%0,%i2
7468    oill\t%0,%i2
7469    oilf\t%0,%o2
7470    or\t%0,%2
7471    ork\t%0,%1,%2
7472    o\t%0,%2
7473    oy\t%0,%2
7474    #
7475    #"
7476   [(set_attr "op_type"  "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7477    (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
7478    (set_attr "z10prop" "z10_super_E1,
7479                         z10_super_E1,
7480                         z10_super_E1,
7481                         z10_super_E1,
7482                         *,
7483                         z10_super_E1,
7484                         z10_super_E1,
7485                         *,
7486                         *")])
7487
7488 (define_insn "*iorsi3_esa"
7489   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7490         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7491                 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7492    (clobber (reg:CC CC_REGNUM))]
7493   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7494   "@
7495    or\t%0,%2
7496    o\t%0,%2
7497    #
7498    #"
7499   [(set_attr "op_type"  "RR,RX,SI,SS")
7500    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7501
7502 (define_split
7503   [(set (match_operand:SI 0 "s_operand" "")
7504         (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7505    (clobber (reg:CC CC_REGNUM))]
7506   "reload_completed"
7507   [(parallel
7508     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7509      (clobber (reg:CC CC_REGNUM))])]
7510   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7511
7512 ;
7513 ; iorhi3 instruction pattern(s).
7514 ;
7515
7516 (define_insn "*iorhi3_zarch"
7517   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7518         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7519                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQH0,Q")))
7520    (clobber (reg:CC CC_REGNUM))]
7521   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7522   "@
7523    or\t%0,%2
7524    ork\t%0,%1,%2
7525    oill\t%0,%x2
7526    #
7527    #"
7528   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7529    (set_attr "cpu_facility" "*,z196,*,*,*")
7530    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7531
7532 (define_insn "*iorhi3_esa"
7533   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7534         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7535                 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7536    (clobber (reg:CC CC_REGNUM))]
7537   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7538   "@
7539    or\t%0,%2
7540    #
7541    #"
7542   [(set_attr "op_type"  "RR,SI,SS")
7543    (set_attr "z10prop" "z10_super_E1,*,*")])
7544
7545 (define_split
7546   [(set (match_operand:HI 0 "s_operand" "")
7547         (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7548    (clobber (reg:CC CC_REGNUM))]
7549   "reload_completed"
7550   [(parallel
7551     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7552      (clobber (reg:CC CC_REGNUM))])]
7553   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7554
7555 ;
7556 ; iorqi3 instruction pattern(s).
7557 ;
7558
7559 (define_insn "*iorqi3_zarch"
7560   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7561         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7562                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7563    (clobber (reg:CC CC_REGNUM))]
7564   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7565   "@
7566    or\t%0,%2
7567    ork\t%0,%1,%2
7568    oill\t%0,%b2
7569    oi\t%S0,%b2
7570    oiy\t%S0,%b2
7571    #"
7572   [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7573    (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7574    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7575                         z10_super,z10_super,*")])
7576
7577 (define_insn "*iorqi3_esa"
7578   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7579         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7580                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7581    (clobber (reg:CC CC_REGNUM))]
7582   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7583   "@
7584    or\t%0,%2
7585    oi\t%S0,%b2
7586    #"
7587   [(set_attr "op_type"  "RR,SI,SS")
7588    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7589
7590 ;
7591 ; Block inclusive or (OC) patterns.
7592 ;
7593
7594 (define_insn "*oc"
7595   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7596         (ior:BLK (match_dup 0)
7597                  (match_operand:BLK 1 "memory_operand" "Q")))
7598    (use (match_operand 2 "const_int_operand" "n"))
7599    (clobber (reg:CC CC_REGNUM))]
7600   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7601   "oc\t%O0(%2,%R0),%S1"
7602   [(set_attr "op_type" "SS")
7603    (set_attr "z196prop" "z196_cracked")])
7604
7605 (define_split
7606   [(set (match_operand 0 "memory_operand" "")
7607         (ior (match_dup 0)
7608              (match_operand 1 "memory_operand" "")))
7609    (clobber (reg:CC CC_REGNUM))]
7610   "reload_completed
7611    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7612    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7613   [(parallel
7614     [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7615      (use (match_dup 2))
7616      (clobber (reg:CC CC_REGNUM))])]
7617 {
7618   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7619   operands[0] = adjust_address (operands[0], BLKmode, 0);
7620   operands[1] = adjust_address (operands[1], BLKmode, 0);
7621 })
7622
7623 (define_peephole2
7624   [(parallel
7625     [(set (match_operand:BLK 0 "memory_operand" "")
7626           (ior:BLK (match_dup 0)
7627                    (match_operand:BLK 1 "memory_operand" "")))
7628      (use (match_operand 2 "const_int_operand" ""))
7629      (clobber (reg:CC CC_REGNUM))])
7630    (parallel
7631     [(set (match_operand:BLK 3 "memory_operand" "")
7632           (ior:BLK (match_dup 3)
7633                    (match_operand:BLK 4 "memory_operand" "")))
7634      (use (match_operand 5 "const_int_operand" ""))
7635      (clobber (reg:CC CC_REGNUM))])]
7636   "s390_offset_p (operands[0], operands[3], operands[2])
7637    && s390_offset_p (operands[1], operands[4], operands[2])
7638    && !s390_overlap_p (operands[0], operands[1],
7639                        INTVAL (operands[2]) + INTVAL (operands[5]))
7640    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7641   [(parallel
7642     [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7643      (use (match_dup 8))
7644      (clobber (reg:CC CC_REGNUM))])]
7645   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7646    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7647    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7648
7649
7650 ;;
7651 ;;- Xor instructions.
7652 ;;
7653
7654 (define_expand "xor<mode>3"
7655   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7656         (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7657                  (match_operand:INT 2 "general_operand" "")))
7658    (clobber (reg:CC CC_REGNUM))]
7659   ""
7660   "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7661
7662 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7663 ; simplifications.  So its better to have something matching.
7664 (define_split
7665   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7666         (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7667   ""
7668   [(parallel
7669     [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7670      (clobber (reg:CC CC_REGNUM))])]
7671 {
7672   operands[2] = constm1_rtx;
7673   if (!s390_logical_operator_ok_p (operands))
7674     FAIL;
7675 })
7676
7677 ;
7678 ; xordi3 instruction pattern(s).
7679 ;
7680
7681 (define_insn "*xordi3_cc"
7682   [(set (reg CC_REGNUM)
7683         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7684                          (match_operand:DI 2 "general_operand"      " d,d,T"))
7685                  (const_int 0)))
7686    (set (match_operand:DI 0 "register_operand"                      "=d,d,d")
7687         (xor:DI (match_dup 1) (match_dup 2)))]
7688   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7689   "@
7690    xgr\t%0,%2
7691    xgrk\t%0,%1,%2
7692    xg\t%0,%2"
7693   [(set_attr "op_type" "RRE,RRF,RXY")
7694    (set_attr "cpu_facility" "*,z196,*")
7695    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7696
7697 (define_insn "*xordi3_cconly"
7698   [(set (reg CC_REGNUM)
7699         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7700                          (match_operand:DI 2 "general_operand"      " d,d,T"))
7701                  (const_int 0)))
7702    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7703   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7704   "@
7705    xgr\t%0,%2
7706    xgrk\t%0,%1,%2
7707    xg\t%0,%2"
7708   [(set_attr "op_type" "RRE,RRF,RXY")
7709    (set_attr "cpu_facility" "*,z196,*")
7710    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7711
7712 (define_insn "*xordi3"
7713   [(set (match_operand:DI 0 "nonimmediate_operand"         "=d,    d,d,d,d,   AQ,Q")
7714         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,    0,0,d,0,    0,0")
7715                 (match_operand:DI 2 "general_operand"   "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7716    (clobber (reg:CC CC_REGNUM))]
7717   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7718   "@
7719    xihf\t%0,%k2
7720    xilf\t%0,%k2
7721    xgr\t%0,%2
7722    xgrk\t%0,%1,%2
7723    xg\t%0,%2
7724    #
7725    #"
7726   [(set_attr "op_type"  "RIL,RIL,RRE,RRF,RXY,SI,SS")
7727    (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7728    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7729                         *,z10_super_E1,*,*")])
7730
7731 (define_split
7732   [(set (match_operand:DI 0 "s_operand" "")
7733         (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7734    (clobber (reg:CC CC_REGNUM))]
7735   "reload_completed"
7736   [(parallel
7737     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7738      (clobber (reg:CC CC_REGNUM))])]
7739   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7740
7741 ;
7742 ; xorsi3 instruction pattern(s).
7743 ;
7744
7745 (define_insn "*xorsi3_cc"
7746   [(set (reg CC_REGNUM)
7747         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7748                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7749                  (const_int 0)))
7750    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7751         (xor:SI (match_dup 1) (match_dup 2)))]
7752   "s390_match_ccmode(insn, CCTmode)"
7753   "@
7754    xilf\t%0,%o2
7755    xr\t%0,%2
7756    xrk\t%0,%1,%2
7757    x\t%0,%2
7758    xy\t%0,%2"
7759   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7760    (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7761    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7762                         z10_super_E1,z10_super_E1")])
7763
7764 (define_insn "*xorsi3_cconly"
7765   [(set (reg CC_REGNUM)
7766         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7767                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7768                  (const_int 0)))
7769    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7770   "s390_match_ccmode(insn, CCTmode)"
7771   "@
7772    xilf\t%0,%o2
7773    xr\t%0,%2
7774    xrk\t%0,%1,%2
7775    x\t%0,%2
7776    xy\t%0,%2"
7777   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7778    (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7779    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7780                         z10_super_E1,z10_super_E1")])
7781
7782 (define_insn "*xorsi3"
7783   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,d,d,d,   AQ,Q")
7784         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    0,0")
7785                 (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxQS0,Q")))
7786    (clobber (reg:CC CC_REGNUM))]
7787   "s390_logical_operator_ok_p (operands)"
7788   "@
7789    xilf\t%0,%o2
7790    xr\t%0,%2
7791    xrk\t%0,%1,%2
7792    x\t%0,%2
7793    xy\t%0,%2
7794    #
7795    #"
7796   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,SI,SS")
7797    (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
7798    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7799                         z10_super_E1,z10_super_E1,*,*")])
7800
7801 (define_split
7802   [(set (match_operand:SI 0 "s_operand" "")
7803         (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7804    (clobber (reg:CC CC_REGNUM))]
7805   "reload_completed"
7806   [(parallel
7807     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7808      (clobber (reg:CC CC_REGNUM))])]
7809   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7810
7811 ;
7812 ; xorhi3 instruction pattern(s).
7813 ;
7814
7815 (define_insn "*xorhi3"
7816   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7817         (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d,    0,0")
7818                 (match_operand:HI 2 "general_operand"      "Os,d,d,NxQH0,Q")))
7819    (clobber (reg:CC CC_REGNUM))]
7820   "s390_logical_operator_ok_p (operands)"
7821   "@
7822    xilf\t%0,%x2
7823    xr\t%0,%2
7824    xrk\t%0,%1,%2
7825    #
7826    #"
7827   [(set_attr "op_type"  "RIL,RR,RRF,SI,SS")
7828    (set_attr "cpu_facility" "*,*,z196,*,*")
7829    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7830
7831 (define_split
7832   [(set (match_operand:HI 0 "s_operand" "")
7833         (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7834    (clobber (reg:CC CC_REGNUM))]
7835   "reload_completed"
7836   [(parallel
7837     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7838      (clobber (reg:CC CC_REGNUM))])]
7839   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7840
7841 ;
7842 ; xorqi3 instruction pattern(s).
7843 ;
7844
7845 (define_insn "*xorqi3"
7846   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7847         (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7848                 (match_operand:QI 2 "general_operand"      "Os,d,d,n,n,Q")))
7849    (clobber (reg:CC CC_REGNUM))]
7850   "s390_logical_operator_ok_p (operands)"
7851   "@
7852    xilf\t%0,%b2
7853    xr\t%0,%2
7854    xrk\t%0,%1,%2
7855    xi\t%S0,%b2
7856    xiy\t%S0,%b2
7857    #"
7858   [(set_attr "op_type"  "RIL,RR,RRF,SI,SIY,SS")
7859    (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
7860    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7861
7862
7863 ;
7864 ; Block exclusive or (XC) patterns.
7865 ;
7866
7867 (define_insn "*xc"
7868   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7869         (xor:BLK (match_dup 0)
7870                  (match_operand:BLK 1 "memory_operand" "Q")))
7871    (use (match_operand 2 "const_int_operand" "n"))
7872    (clobber (reg:CC CC_REGNUM))]
7873   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7874   "xc\t%O0(%2,%R0),%S1"
7875   [(set_attr "op_type" "SS")])
7876
7877 (define_split
7878   [(set (match_operand 0 "memory_operand" "")
7879         (xor (match_dup 0)
7880              (match_operand 1 "memory_operand" "")))
7881    (clobber (reg:CC CC_REGNUM))]
7882   "reload_completed
7883    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7884    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7885   [(parallel
7886     [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7887      (use (match_dup 2))
7888      (clobber (reg:CC CC_REGNUM))])]
7889 {
7890   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7891   operands[0] = adjust_address (operands[0], BLKmode, 0);
7892   operands[1] = adjust_address (operands[1], BLKmode, 0);
7893 })
7894
7895 (define_peephole2
7896   [(parallel
7897     [(set (match_operand:BLK 0 "memory_operand" "")
7898           (xor:BLK (match_dup 0)
7899                    (match_operand:BLK 1 "memory_operand" "")))
7900      (use (match_operand 2 "const_int_operand" ""))
7901      (clobber (reg:CC CC_REGNUM))])
7902    (parallel
7903     [(set (match_operand:BLK 3 "memory_operand" "")
7904           (xor:BLK (match_dup 3)
7905                    (match_operand:BLK 4 "memory_operand" "")))
7906      (use (match_operand 5 "const_int_operand" ""))
7907      (clobber (reg:CC CC_REGNUM))])]
7908   "s390_offset_p (operands[0], operands[3], operands[2])
7909    && s390_offset_p (operands[1], operands[4], operands[2])
7910    && !s390_overlap_p (operands[0], operands[1],
7911                        INTVAL (operands[2]) + INTVAL (operands[5]))
7912    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7913   [(parallel
7914     [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7915      (use (match_dup 8))
7916      (clobber (reg:CC CC_REGNUM))])]
7917   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7918    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7919    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7920
7921 ;
7922 ; Block xor (XC) patterns with src == dest.
7923 ;
7924
7925 (define_insn "*xc_zero"
7926   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7927         (const_int 0))
7928    (use (match_operand 1 "const_int_operand" "n"))
7929    (clobber (reg:CC CC_REGNUM))]
7930   "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7931   "xc\t%O0(%1,%R0),%S0"
7932   [(set_attr "op_type" "SS")
7933    (set_attr "z196prop" "z196_cracked")])
7934
7935 (define_peephole2
7936   [(parallel
7937     [(set (match_operand:BLK 0 "memory_operand" "")
7938           (const_int 0))
7939      (use (match_operand 1 "const_int_operand" ""))
7940      (clobber (reg:CC CC_REGNUM))])
7941    (parallel
7942     [(set (match_operand:BLK 2 "memory_operand" "")
7943           (const_int 0))
7944      (use (match_operand 3 "const_int_operand" ""))
7945      (clobber (reg:CC CC_REGNUM))])]
7946   "s390_offset_p (operands[0], operands[2], operands[1])
7947    && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7948   [(parallel
7949     [(set (match_dup 4) (const_int 0))
7950      (use (match_dup 5))
7951      (clobber (reg:CC CC_REGNUM))])]
7952   "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7953    operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7954
7955
7956 ;;
7957 ;;- Negate instructions.
7958 ;;
7959
7960 ;
7961 ; neg(di|si)2 instruction pattern(s).
7962 ;
7963
7964 (define_expand "neg<mode>2"
7965   [(parallel
7966     [(set (match_operand:DSI 0 "register_operand" "=d")
7967           (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7968      (clobber (reg:CC CC_REGNUM))])]
7969   ""
7970   "")
7971
7972 (define_insn "*negdi2_sign_cc"
7973   [(set (reg CC_REGNUM)
7974         (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7975                            (match_operand:SI 1 "register_operand" "d") 0)
7976                            (const_int 32)) (const_int 32)))
7977                  (const_int 0)))
7978    (set (match_operand:DI 0 "register_operand" "=d")
7979         (neg:DI (sign_extend:DI (match_dup 1))))]
7980   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7981   "lcgfr\t%0,%1"
7982   [(set_attr "op_type"  "RRE")
7983    (set_attr "z10prop" "z10_c")])
7984
7985 (define_insn "*negdi2_sign"
7986   [(set (match_operand:DI 0 "register_operand" "=d")
7987         (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7988    (clobber (reg:CC CC_REGNUM))]
7989   "TARGET_ZARCH"
7990   "lcgfr\t%0,%1"
7991   [(set_attr "op_type"  "RRE")
7992    (set_attr "z10prop" "z10_c")])
7993
7994 ; lcr, lcgr
7995 (define_insn "*neg<mode>2_cc"
7996   [(set (reg CC_REGNUM)
7997         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7998                  (const_int 0)))
7999    (set (match_operand:GPR 0 "register_operand" "=d")
8000         (neg:GPR (match_dup 1)))]
8001   "s390_match_ccmode (insn, CCAmode)"
8002   "lc<g>r\t%0,%1"
8003   [(set_attr "op_type"  "RR<E>")
8004    (set_attr "z10prop" "z10_super_c_E1")])
8005
8006 ; lcr, lcgr
8007 (define_insn "*neg<mode>2_cconly"
8008   [(set (reg CC_REGNUM)
8009         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8010                  (const_int 0)))
8011    (clobber (match_scratch:GPR 0 "=d"))]
8012   "s390_match_ccmode (insn, CCAmode)"
8013   "lc<g>r\t%0,%1"
8014   [(set_attr "op_type"  "RR<E>")
8015    (set_attr "z10prop" "z10_super_c_E1")])
8016
8017 ; lcr, lcgr
8018 (define_insn "*neg<mode>2"
8019   [(set (match_operand:GPR 0 "register_operand" "=d")
8020         (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
8021    (clobber (reg:CC CC_REGNUM))]
8022   ""
8023   "lc<g>r\t%0,%1"
8024   [(set_attr "op_type"  "RR<E>")
8025    (set_attr "z10prop" "z10_super_c_E1")])
8026
8027 (define_insn "*negdi2_31"
8028   [(set (match_operand:DI 0 "register_operand" "=d")
8029         (neg:DI (match_operand:DI 1 "register_operand" "d")))
8030    (clobber (reg:CC CC_REGNUM))]
8031   "!TARGET_ZARCH"
8032   "#")
8033
8034 ; Split a DImode NEG on 31bit into 2 SImode NEGs
8035
8036 ; Doing the twos complement separately on the SImode parts does an
8037 ; unwanted +1 on the high part which needs to be subtracted afterwards
8038 ; ... unless the +1 on the low part created an overflow.
8039
8040 (define_split
8041   [(set (match_operand:DI 0 "register_operand" "")
8042         (neg:DI (match_operand:DI 1 "register_operand" "")))
8043    (clobber (reg:CC CC_REGNUM))]
8044   "!TARGET_ZARCH
8045    && (REGNO (operands[0]) == REGNO (operands[1])
8046       || s390_split_ok_p (operands[0], operands[1], DImode, 0))
8047    && reload_completed"
8048   [(parallel
8049     [(set (match_dup 2) (neg:SI (match_dup 3)))
8050      (clobber (reg:CC CC_REGNUM))])
8051    (parallel
8052     [(set (reg:CCAP CC_REGNUM)
8053           (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
8054      (set (match_dup 4) (neg:SI (match_dup 5)))])
8055    (set (pc)
8056         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8057                       (pc)
8058                       (label_ref (match_dup 6))))
8059    (parallel
8060     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8061      (clobber (reg:CC CC_REGNUM))])
8062    (match_dup 6)]
8063   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8064    operands[3] = operand_subword (operands[1], 0, 0, DImode);
8065    operands[4] = operand_subword (operands[0], 1, 0, DImode);
8066    operands[5] = operand_subword (operands[1], 1, 0, DImode);
8067    operands[6] = gen_label_rtx ();")
8068
8069 ; Like above but first make a copy of the low part of the src operand
8070 ; since it might overlap with the high part of the destination.
8071
8072 (define_split
8073   [(set (match_operand:DI 0 "register_operand" "")
8074         (neg:DI (match_operand:DI 1 "register_operand" "")))
8075    (clobber (reg:CC CC_REGNUM))]
8076   "!TARGET_ZARCH
8077    && s390_split_ok_p (operands[0], operands[1], DImode, 1)
8078    && reload_completed"
8079   [; Make a backup of op5 first
8080    (set (match_dup 4) (match_dup 5))
8081    ; Setting op2 here might clobber op5
8082    (parallel
8083     [(set (match_dup 2) (neg:SI (match_dup 3)))
8084      (clobber (reg:CC CC_REGNUM))])
8085    (parallel
8086     [(set (reg:CCAP CC_REGNUM)
8087           (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
8088      (set (match_dup 4) (neg:SI (match_dup 4)))])
8089    (set (pc)
8090         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8091                       (pc)
8092                       (label_ref (match_dup 6))))
8093    (parallel
8094     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8095      (clobber (reg:CC CC_REGNUM))])
8096    (match_dup 6)]
8097   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8098    operands[3] = operand_subword (operands[1], 0, 0, DImode);
8099    operands[4] = operand_subword (operands[0], 1, 0, DImode);
8100    operands[5] = operand_subword (operands[1], 1, 0, DImode);
8101    operands[6] = gen_label_rtx ();")
8102
8103 ;
8104 ; neg(df|sf)2 instruction pattern(s).
8105 ;
8106
8107 (define_expand "neg<mode>2"
8108   [(parallel
8109     [(set (match_operand:BFP 0 "register_operand" "=f")
8110           (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
8111      (clobber (reg:CC CC_REGNUM))])]
8112   "TARGET_HARD_FLOAT"
8113   "")
8114
8115 ; lcxbr, lcdbr, lcebr
8116 (define_insn "*neg<mode>2_cc"
8117   [(set (reg CC_REGNUM)
8118         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8119                  (match_operand:BFP 2 "const0_operand" "")))
8120    (set (match_operand:BFP 0 "register_operand" "=f")
8121         (neg:BFP (match_dup 1)))]
8122   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8123   "lc<xde>br\t%0,%1"
8124   [(set_attr "op_type"  "RRE")
8125    (set_attr "type"     "fsimp<mode>")])
8126
8127 ; lcxbr, lcdbr, lcebr
8128 (define_insn "*neg<mode>2_cconly"
8129   [(set (reg CC_REGNUM)
8130         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8131                  (match_operand:BFP 2 "const0_operand" "")))
8132    (clobber (match_scratch:BFP 0 "=f"))]
8133   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8134   "lc<xde>br\t%0,%1"
8135   [(set_attr "op_type"  "RRE")
8136    (set_attr "type"     "fsimp<mode>")])
8137
8138 ; lcdfr
8139 (define_insn "*neg<mode>2_nocc"
8140   [(set (match_operand:FP 0 "register_operand"         "=f")
8141         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8142   "TARGET_DFP"
8143   "lcdfr\t%0,%1"
8144   [(set_attr "op_type"  "RRE")
8145    (set_attr "type"     "fsimp<mode>")])
8146
8147 ; lcxbr, lcdbr, lcebr
8148 ; FIXME: wflcdb does not clobber cc
8149 (define_insn "*neg<mode>2"
8150   [(set (match_operand:BFP          0 "register_operand" "=f,v")
8151         (neg:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
8152    (clobber (reg:CC CC_REGNUM))]
8153   "TARGET_HARD_FLOAT"
8154   "@
8155    lc<xde>br\t%0,%1
8156    wflcdb\t%0,%1"
8157   [(set_attr "op_type"      "RRE,VRR")
8158    (set_attr "cpu_facility" "*,vec")
8159    (set_attr "type"         "fsimp<mode>,*")
8160    (set_attr "enabled"      "*,<DFDI>")])
8161
8162
8163 ;;
8164 ;;- Absolute value instructions.
8165 ;;
8166
8167 ;
8168 ; abs(di|si)2 instruction pattern(s).
8169 ;
8170
8171 (define_insn "*absdi2_sign_cc"
8172   [(set (reg CC_REGNUM)
8173         (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8174                            (match_operand:SI 1 "register_operand" "d") 0)
8175                            (const_int 32)) (const_int 32)))
8176                  (const_int 0)))
8177    (set (match_operand:DI 0 "register_operand" "=d")
8178         (abs:DI (sign_extend:DI (match_dup 1))))]
8179   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8180   "lpgfr\t%0,%1"
8181   [(set_attr "op_type"  "RRE")
8182    (set_attr "z10prop" "z10_c")])
8183
8184 (define_insn "*absdi2_sign"
8185   [(set (match_operand:DI 0 "register_operand" "=d")
8186         (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8187    (clobber (reg:CC CC_REGNUM))]
8188   "TARGET_ZARCH"
8189   "lpgfr\t%0,%1"
8190   [(set_attr "op_type"  "RRE")
8191    (set_attr "z10prop" "z10_c")])
8192
8193 ; lpr, lpgr
8194 (define_insn "*abs<mode>2_cc"
8195   [(set (reg CC_REGNUM)
8196         (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8197                  (const_int 0)))
8198    (set (match_operand:GPR 0 "register_operand" "=d")
8199         (abs:GPR (match_dup 1)))]
8200   "s390_match_ccmode (insn, CCAmode)"
8201   "lp<g>r\t%0,%1"
8202   [(set_attr "op_type"  "RR<E>")
8203    (set_attr "z10prop" "z10_c")])
8204
8205 ; lpr, lpgr
8206 (define_insn "*abs<mode>2_cconly"
8207   [(set (reg CC_REGNUM)
8208         (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8209                  (const_int 0)))
8210    (clobber (match_scratch:GPR 0 "=d"))]
8211   "s390_match_ccmode (insn, CCAmode)"
8212   "lp<g>r\t%0,%1"
8213   [(set_attr "op_type"  "RR<E>")
8214    (set_attr "z10prop" "z10_c")])
8215
8216 ; lpr, lpgr
8217 (define_insn "abs<mode>2"
8218   [(set (match_operand:GPR 0 "register_operand" "=d")
8219         (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8220    (clobber (reg:CC CC_REGNUM))]
8221   ""
8222   "lp<g>r\t%0,%1"
8223   [(set_attr "op_type"  "RR<E>")
8224    (set_attr "z10prop" "z10_c")])
8225
8226 ;
8227 ; abs(df|sf)2 instruction pattern(s).
8228 ;
8229
8230 (define_expand "abs<mode>2"
8231   [(parallel
8232     [(set (match_operand:BFP 0 "register_operand" "=f")
8233           (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8234      (clobber (reg:CC CC_REGNUM))])]
8235   "TARGET_HARD_FLOAT"
8236   "")
8237
8238 ; lpxbr, lpdbr, lpebr
8239 (define_insn "*abs<mode>2_cc"
8240   [(set (reg CC_REGNUM)
8241         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8242                  (match_operand:BFP 2 "const0_operand" "")))
8243    (set (match_operand:BFP 0 "register_operand" "=f")
8244         (abs:BFP (match_dup 1)))]
8245   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8246   "lp<xde>br\t%0,%1"
8247   [(set_attr "op_type"  "RRE")
8248    (set_attr "type"     "fsimp<mode>")])
8249
8250 ; lpxbr, lpdbr, lpebr
8251 (define_insn "*abs<mode>2_cconly"
8252   [(set (reg CC_REGNUM)
8253         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8254                  (match_operand:BFP 2 "const0_operand" "")))
8255    (clobber (match_scratch:BFP 0 "=f"))]
8256   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8257   "lp<xde>br\t%0,%1"
8258   [(set_attr "op_type"  "RRE")
8259    (set_attr "type"     "fsimp<mode>")])
8260
8261 ; lpdfr
8262 (define_insn "*abs<mode>2_nocc"
8263   [(set (match_operand:FP 0 "register_operand"         "=f")
8264         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8265   "TARGET_DFP"
8266   "lpdfr\t%0,%1"
8267   [(set_attr "op_type"  "RRE")
8268    (set_attr "type"     "fsimp<mode>")])
8269
8270 ; lpxbr, lpdbr, lpebr
8271 ; FIXME: wflpdb does not clobber cc
8272 (define_insn "*abs<mode>2"
8273   [(set (match_operand:BFP          0 "register_operand" "=f,v")
8274         (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
8275    (clobber (reg:CC CC_REGNUM))]
8276   "TARGET_HARD_FLOAT"
8277   "@
8278     lp<xde>br\t%0,%1
8279     wflpdb\t%0,%1"
8280   [(set_attr "op_type"      "RRE,VRR")
8281    (set_attr "cpu_facility" "*,vec")
8282    (set_attr "type"         "fsimp<mode>,*")
8283    (set_attr "enabled"      "*,<DFDI>")])
8284
8285
8286 ;;
8287 ;;- Negated absolute value instructions
8288 ;;
8289
8290 ;
8291 ; Integer
8292 ;
8293
8294 (define_insn "*negabsdi2_sign_cc"
8295   [(set (reg CC_REGNUM)
8296         (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8297                            (match_operand:SI 1 "register_operand" "d") 0)
8298                            (const_int 32)) (const_int 32))))
8299                  (const_int 0)))
8300    (set (match_operand:DI 0 "register_operand" "=d")
8301         (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8302   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8303   "lngfr\t%0,%1"
8304   [(set_attr "op_type"  "RRE")
8305    (set_attr "z10prop" "z10_c")])
8306
8307 (define_insn "*negabsdi2_sign"
8308   [(set (match_operand:DI 0 "register_operand" "=d")
8309         (neg:DI (abs:DI (sign_extend:DI
8310                           (match_operand:SI 1 "register_operand" "d")))))
8311    (clobber (reg:CC CC_REGNUM))]
8312   "TARGET_ZARCH"
8313   "lngfr\t%0,%1"
8314   [(set_attr "op_type" "RRE")
8315    (set_attr "z10prop" "z10_c")])
8316
8317 ; lnr, lngr
8318 (define_insn "*negabs<mode>2_cc"
8319   [(set (reg CC_REGNUM)
8320         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8321                  (const_int 0)))
8322    (set (match_operand:GPR 0 "register_operand" "=d")
8323         (neg:GPR (abs:GPR (match_dup 1))))]
8324   "s390_match_ccmode (insn, CCAmode)"
8325   "ln<g>r\t%0,%1"
8326   [(set_attr "op_type"  "RR<E>")
8327    (set_attr "z10prop" "z10_c")])
8328
8329 ; lnr, lngr
8330 (define_insn "*negabs<mode>2_cconly"
8331   [(set (reg CC_REGNUM)
8332         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8333                  (const_int 0)))
8334    (clobber (match_scratch:GPR 0 "=d"))]
8335   "s390_match_ccmode (insn, CCAmode)"
8336   "ln<g>r\t%0,%1"
8337   [(set_attr "op_type"  "RR<E>")
8338    (set_attr "z10prop" "z10_c")])
8339
8340 ; lnr, lngr
8341 (define_insn "*negabs<mode>2"
8342   [(set (match_operand:GPR 0 "register_operand" "=d")
8343         (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8344    (clobber (reg:CC CC_REGNUM))]
8345   ""
8346   "ln<g>r\t%0,%1"
8347   [(set_attr "op_type" "RR<E>")
8348    (set_attr "z10prop" "z10_c")])
8349
8350 ;
8351 ; Floating point
8352 ;
8353
8354 ; lnxbr, lndbr, lnebr
8355 (define_insn "*negabs<mode>2_cc"
8356   [(set (reg CC_REGNUM)
8357         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8358                  (match_operand:BFP 2 "const0_operand" "")))
8359    (set (match_operand:BFP 0 "register_operand" "=f")
8360         (neg:BFP (abs:BFP (match_dup 1))))]
8361   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8362   "ln<xde>br\t%0,%1"
8363   [(set_attr "op_type"  "RRE")
8364    (set_attr "type"     "fsimp<mode>")])
8365
8366 ; lnxbr, lndbr, lnebr
8367 (define_insn "*negabs<mode>2_cconly"
8368   [(set (reg CC_REGNUM)
8369         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8370                  (match_operand:BFP 2 "const0_operand" "")))
8371    (clobber (match_scratch:BFP 0 "=f"))]
8372   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8373   "ln<xde>br\t%0,%1"
8374   [(set_attr "op_type"  "RRE")
8375    (set_attr "type"     "fsimp<mode>")])
8376
8377 ; lndfr
8378 (define_insn "*negabs<mode>2_nocc"
8379   [(set (match_operand:FP 0 "register_operand"                  "=f")
8380         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8381   "TARGET_DFP"
8382   "lndfr\t%0,%1"
8383   [(set_attr "op_type"  "RRE")
8384    (set_attr "type"     "fsimp<mode>")])
8385
8386 ; lnxbr, lndbr, lnebr
8387 ; FIXME: wflndb does not clobber cc
8388 (define_insn "*negabs<mode>2"
8389   [(set (match_operand:BFP                   0 "register_operand" "=f,v")
8390         (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v"))))
8391    (clobber (reg:CC CC_REGNUM))]
8392   "TARGET_HARD_FLOAT"
8393   "@
8394    ln<xde>br\t%0,%1
8395    wflndb\t%0,%1"
8396   [(set_attr "op_type"      "RRE,VRR")
8397    (set_attr "cpu_facility" "*,vec")
8398    (set_attr "type"         "fsimp<mode>,*")
8399    (set_attr "enabled"      "*,<DFDI>")])
8400
8401 ;;
8402 ;;- Square root instructions.
8403 ;;
8404
8405 ;
8406 ; sqrt(df|sf)2 instruction pattern(s).
8407 ;
8408
8409 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8410 (define_insn "sqrt<mode>2"
8411   [(set (match_operand:BFP           0 "register_operand" "=f,f,v")
8412         (sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,R,v")))]
8413   "TARGET_HARD_FLOAT"
8414   "@
8415    sq<xde>br\t%0,%1
8416    sq<xde>b\t%0,%1
8417    wfsqdb\t%v0,%v1"
8418   [(set_attr "op_type"      "RRE,RXE,VRR")
8419    (set_attr "type"         "fsqrt<mode>")
8420    (set_attr "cpu_facility" "*,*,vec")
8421    (set_attr "enabled"      "*,<DSF>,<DFDI>")])
8422
8423
8424 ;;
8425 ;;- One complement instructions.
8426 ;;
8427
8428 ;
8429 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8430 ;
8431
8432 (define_expand "one_cmpl<mode>2"
8433   [(parallel
8434     [(set (match_operand:INT 0 "register_operand" "")
8435           (xor:INT (match_operand:INT 1 "register_operand" "")
8436                    (const_int -1)))
8437      (clobber (reg:CC CC_REGNUM))])]
8438   ""
8439   "")
8440
8441
8442 ;;
8443 ;; Find leftmost bit instructions.
8444 ;;
8445
8446 (define_expand "clzdi2"
8447   [(set (match_operand:DI 0 "register_operand" "=d")
8448         (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8449   "TARGET_EXTIMM && TARGET_ZARCH"
8450 {
8451   rtx insn, clz_equal;
8452   rtx wide_reg = gen_reg_rtx (TImode);
8453   rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8454
8455   clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8456
8457   emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8458
8459   insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8460   set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8461
8462   DONE;
8463 })
8464
8465 (define_insn "clztidi2"
8466   [(set (match_operand:TI 0 "register_operand" "=d")
8467         (ior:TI
8468           (ashift:TI
8469             (zero_extend:TI
8470               (xor:DI (match_operand:DI 1 "register_operand" "d")
8471                       (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8472                                 (subreg:SI (clz:DI (match_dup 1)) 4))))
8473
8474             (const_int 64))
8475           (zero_extend:TI (clz:DI (match_dup 1)))))
8476    (clobber (reg:CC CC_REGNUM))]
8477   "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8478    == (unsigned HOST_WIDE_INT) 1 << 63
8479    && TARGET_EXTIMM && TARGET_ZARCH"
8480   "flogr\t%0,%1"
8481   [(set_attr "op_type"  "RRE")])
8482
8483
8484 ;;
8485 ;;- Rotate instructions.
8486 ;;
8487
8488 ;
8489 ; rotl(di|si)3 instruction pattern(s).
8490 ;
8491
8492 (define_expand "rotl<mode>3"
8493   [(set (match_operand:GPR 0 "register_operand" "")
8494         (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8495                     (match_operand:SI 2 "nonmemory_operand" "")))]
8496   "TARGET_CPU_ZARCH"
8497   "")
8498
8499 ; rll, rllg
8500 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8501   [(set (match_operand:GPR             0 "register_operand"  "=d")
8502         (rotate:GPR (match_operand:GPR 1 "register_operand"   "d")
8503                     (match_operand:SI  2 "nonmemory_operand" "an")))]
8504   "TARGET_CPU_ZARCH"
8505   "rll<g>\t%0,%1,<addr_style_op_ops>"
8506   [(set_attr "op_type"  "RSE")
8507    (set_attr "atype"    "reg")
8508    (set_attr "z10prop"  "z10_super_E1")])
8509
8510
8511 ;;
8512 ;;- Shift instructions.
8513 ;;
8514
8515 ;
8516 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8517 ; Left shifts and logical right shifts
8518
8519 (define_expand "<shift><mode>3"
8520   [(set (match_operand:DSI 0 "register_operand" "")
8521         (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8522                    (match_operand:SI 2 "nonmemory_operand" "")))]
8523   ""
8524   "")
8525
8526 ; ESA 64 bit register pair shift with reg or imm shift count
8527 ; sldl, srdl
8528 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8529   [(set (match_operand:DI 0 "register_operand"            "=d")
8530         (SHIFT:DI (match_operand:DI 1 "register_operand"   "0")
8531                   (match_operand:SI 2 "nonmemory_operand" "an")))]
8532   "!TARGET_ZARCH"
8533   "s<lr>dl\t%0,<addr_style_op_ops>"
8534   [(set_attr "op_type"  "RS")
8535    (set_attr "atype"    "reg")
8536    (set_attr "z196prop" "z196_cracked")])
8537
8538
8539 ; 64 bit register shift with reg or imm shift count
8540 ; sll, srl, sllg, srlg, sllk, srlk
8541 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8542   [(set (match_operand:GPR 0 "register_operand"              "=d, d")
8543         (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8544                    (match_operand:SI 2 "nonmemory_operand"   "an,an")))]
8545   ""
8546   "@
8547    s<lr>l<g>\t%0,<1><addr_style_op_ops>
8548    s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8549   [(set_attr "op_type"  "RS<E>,RSY")
8550    (set_attr "atype"    "reg,reg")
8551    (set_attr "cpu_facility" "*,z196")
8552    (set_attr "z10prop"  "z10_super_E1,*")])
8553
8554 ;
8555 ; ashr(di|si)3 instruction pattern(s).
8556 ; Arithmetic right shifts
8557
8558 (define_expand "ashr<mode>3"
8559   [(parallel
8560     [(set (match_operand:DSI 0 "register_operand" "")
8561           (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8562                         (match_operand:SI 2 "nonmemory_operand" "")))
8563      (clobber (reg:CC CC_REGNUM))])]
8564   ""
8565   "")
8566
8567 ; FIXME: The number of alternatives is doubled here to match the fix
8568 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8569 ; The right fix should be to support match_scratch in the output
8570 ; pattern of a define_subst.
8571 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8572   [(set (match_operand:DI 0 "register_operand"               "=d, d")
8573         (ashiftrt:DI (match_operand:DI 1 "register_operand"   "0, 0")
8574                      (match_operand:SI 2 "nonmemory_operand" "an,an")))
8575    (clobber (reg:CC CC_REGNUM))]
8576   "!TARGET_ZARCH"
8577   "@
8578    srda\t%0,<addr_style_op_cc_ops>
8579    srda\t%0,<addr_style_op_cc_ops>"
8580   [(set_attr "op_type" "RS")
8581    (set_attr "atype"   "reg")])
8582
8583
8584 ; sra, srag
8585 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8586   [(set (match_operand:GPR 0 "register_operand"                 "=d, d")
8587         (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8588                       (match_operand:SI 2 "nonmemory_operand"   "an,an")))
8589    (clobber (reg:CC CC_REGNUM))]
8590   ""
8591   "@
8592    sra<g>\t%0,<1><addr_style_op_cc_ops>
8593    sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8594   [(set_attr "op_type"  "RS<E>,RSY")
8595    (set_attr "atype"    "reg")
8596    (set_attr "cpu_facility" "*,z196")
8597    (set_attr "z10prop" "z10_super_E1,*")])
8598
8599
8600 ;;
8601 ;; Branch instruction patterns.
8602 ;;
8603
8604 (define_expand "cbranch<mode>4"
8605   [(set (pc)
8606         (if_then_else (match_operator 0 "comparison_operator"
8607                        [(match_operand:GPR 1 "register_operand" "")
8608                         (match_operand:GPR 2 "general_operand" "")])
8609                       (label_ref (match_operand 3 "" ""))
8610                       (pc)))]
8611   ""
8612   "s390_emit_jump (operands[3],
8613     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8614    DONE;")
8615
8616 (define_expand "cbranch<mode>4"
8617   [(set (pc)
8618         (if_then_else (match_operator 0 "comparison_operator"
8619                        [(match_operand:FP 1 "register_operand" "")
8620                         (match_operand:FP 2 "general_operand" "")])
8621                       (label_ref (match_operand 3 "" ""))
8622                       (pc)))]
8623   "TARGET_HARD_FLOAT"
8624   "s390_emit_jump (operands[3],
8625     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8626    DONE;")
8627
8628 (define_expand "cbranchcc4"
8629   [(set (pc)
8630         (if_then_else (match_operator 0 "s390_comparison"
8631                        [(match_operand 1 "cc_reg_operand" "")
8632                         (match_operand 2 "const_int_operand" "")])
8633                       (label_ref (match_operand 3 "" ""))
8634                       (pc)))]
8635   ""
8636   "")
8637
8638
8639 ;;
8640 ;;- Conditional jump instructions.
8641 ;;
8642
8643 (define_insn "*cjump_64"
8644   [(set (pc)
8645         (if_then_else
8646           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8647                                                (match_operand 2 "const_int_operand" "")])
8648           (label_ref (match_operand 0 "" ""))
8649           (pc)))]
8650   "TARGET_CPU_ZARCH"
8651 {
8652   if (get_attr_length (insn) == 4)
8653     return "j%C1\t%l0";
8654   else
8655     return "jg%C1\t%l0";
8656 }
8657   [(set_attr "op_type" "RI")
8658    (set_attr "type"    "branch")
8659    (set (attr "length")
8660         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8661                       (const_int 4) (const_int 6)))])
8662
8663 (define_insn "*cjump_31"
8664   [(set (pc)
8665         (if_then_else
8666           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8667                                                (match_operand 2 "const_int_operand" "")])
8668           (label_ref (match_operand 0 "" ""))
8669           (pc)))]
8670   "!TARGET_CPU_ZARCH"
8671 {
8672   gcc_assert (get_attr_length (insn) == 4);
8673   return "j%C1\t%l0";
8674 }
8675   [(set_attr "op_type" "RI")
8676    (set_attr "type"    "branch")
8677    (set (attr "length")
8678         (if_then_else (not (match_test "flag_pic"))
8679           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8680                         (const_int 4) (const_int 6))
8681           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8682                         (const_int 4) (const_int 8))))])
8683
8684 (define_insn "*cjump_long"
8685   [(set (pc)
8686         (if_then_else
8687           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8688           (match_operand 0 "address_operand" "ZQZR")
8689           (pc)))]
8690   ""
8691 {
8692   if (get_attr_op_type (insn) == OP_TYPE_RR)
8693     return "b%C1r\t%0";
8694   else
8695     return "b%C1\t%a0";
8696 }
8697   [(set (attr "op_type")
8698         (if_then_else (match_operand 0 "register_operand" "")
8699                       (const_string "RR") (const_string "RX")))
8700    (set_attr "type"  "branch")
8701    (set_attr "atype" "agen")])
8702
8703 ;; A conditional return instruction.
8704 (define_insn "*c<code>"
8705   [(set (pc)
8706         (if_then_else
8707           (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8708           (ANY_RETURN)
8709           (pc)))]
8710   "s390_can_use_<code>_insn ()"
8711   "b%C0r\t%%r14"
8712   [(set_attr "op_type" "RR")
8713    (set_attr "type"  "jsr")
8714    (set_attr "atype" "agen")])
8715
8716 ;;
8717 ;;- Negated conditional jump instructions.
8718 ;;
8719
8720 (define_insn "*icjump_64"
8721   [(set (pc)
8722         (if_then_else
8723           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8724           (pc)
8725           (label_ref (match_operand 0 "" ""))))]
8726   "TARGET_CPU_ZARCH"
8727 {
8728   if (get_attr_length (insn) == 4)
8729     return "j%D1\t%l0";
8730   else
8731     return "jg%D1\t%l0";
8732 }
8733   [(set_attr "op_type" "RI")
8734    (set_attr "type"    "branch")
8735    (set (attr "length")
8736         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8737                       (const_int 4) (const_int 6)))])
8738
8739 (define_insn "*icjump_31"
8740   [(set (pc)
8741         (if_then_else
8742           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8743           (pc)
8744           (label_ref (match_operand 0 "" ""))))]
8745   "!TARGET_CPU_ZARCH"
8746 {
8747   gcc_assert (get_attr_length (insn) == 4);
8748   return "j%D1\t%l0";
8749 }
8750   [(set_attr "op_type" "RI")
8751    (set_attr "type"    "branch")
8752    (set (attr "length")
8753         (if_then_else (not (match_test "flag_pic"))
8754           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8755                         (const_int 4) (const_int 6))
8756           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8757                         (const_int 4) (const_int 8))))])
8758
8759 (define_insn "*icjump_long"
8760   [(set (pc)
8761         (if_then_else
8762           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8763           (pc)
8764           (match_operand 0 "address_operand" "ZQZR")))]
8765   ""
8766 {
8767   if (get_attr_op_type (insn) == OP_TYPE_RR)
8768     return "b%D1r\t%0";
8769   else
8770     return "b%D1\t%a0";
8771 }
8772   [(set (attr "op_type")
8773         (if_then_else (match_operand 0 "register_operand" "")
8774                       (const_string "RR") (const_string "RX")))
8775    (set_attr "type"  "branch")
8776    (set_attr "atype" "agen")])
8777
8778 ;;
8779 ;;- Trap instructions.
8780 ;;
8781
8782 (define_insn "trap"
8783   [(trap_if (const_int 1) (const_int 0))]
8784   ""
8785   "j\t.+2"
8786   [(set_attr "op_type" "RI")
8787    (set_attr "type"  "branch")])
8788
8789 (define_expand "ctrap<mode>4"
8790   [(trap_if (match_operator 0 "comparison_operator"
8791              [(match_operand:GPR 1 "register_operand" "")
8792               (match_operand:GPR 2 "general_operand" "")])
8793              (match_operand 3 "const0_operand" ""))]
8794   ""
8795   {
8796     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8797                                   operands[1], operands[2]);
8798     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8799     DONE;
8800   })
8801
8802 (define_expand "ctrap<mode>4"
8803   [(trap_if (match_operator 0 "comparison_operator"
8804              [(match_operand:FP 1 "register_operand" "")
8805               (match_operand:FP 2 "general_operand" "")])
8806              (match_operand 3 "const0_operand" ""))]
8807   ""
8808   {
8809     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8810                                   operands[1], operands[2]);
8811     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8812     DONE;
8813   })
8814
8815 (define_insn "condtrap"
8816   [(trap_if (match_operator 0 "s390_comparison"
8817              [(match_operand 1 "cc_reg_operand" "c")
8818               (const_int 0)])
8819             (const_int 0))]
8820   ""
8821   "j%C0\t.+2";
8822   [(set_attr "op_type" "RI")
8823    (set_attr "type"  "branch")])
8824
8825 ; crt, cgrt, cit, cgit
8826 (define_insn "*cmp_and_trap_signed_int<mode>"
8827   [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8828                [(match_operand:GPR 1 "register_operand"  "d,d")
8829                 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8830             (const_int 0))]
8831   "TARGET_Z10"
8832   "@
8833    c<g>rt%C0\t%1,%2
8834    c<g>it%C0\t%1,%h2"
8835   [(set_attr "op_type" "RRF,RIE")
8836    (set_attr "type"    "branch")
8837    (set_attr "z10prop" "z10_super_c,z10_super")])
8838
8839 ; clrt, clgrt, clfit, clgit, clt, clgt
8840 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8841   [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8842                [(match_operand:GPR 1 "register_operand" "d,d,d")
8843                 (match_operand:GPR 2 "general_operand"  "d,D,T")])
8844             (const_int 0))]
8845   "TARGET_Z10"
8846   "@
8847    cl<g>rt%C0\t%1,%2
8848    cl<gf>it%C0\t%1,%x2
8849    cl<g>t%C0\t%1,%2"
8850   [(set_attr "op_type"      "RRF,RIE,RSY")
8851    (set_attr "type"         "branch")
8852    (set_attr "z10prop"      "z10_super_c,z10_super,*")
8853    (set_attr "cpu_facility" "z10,z10,zEC12")])
8854
8855 ; lat, lgat
8856 (define_insn "*load_and_trap<mode>"
8857   [(trap_if (eq (match_operand:GPR 0 "memory_operand"  "T")
8858                 (const_int 0))
8859             (const_int 0))
8860    (set (match_operand:GPR 1 "register_operand" "=d")
8861         (match_dup 0))]
8862   "TARGET_ZEC12"
8863   "l<g>at\t%1,%0"
8864   [(set_attr "op_type" "RXY")])
8865
8866
8867 ;;
8868 ;;- Loop instructions.
8869 ;;
8870 ;;  This is all complicated by the fact that since this is a jump insn
8871 ;;  we must handle our own output reloads.
8872
8873 ;; branch on index
8874
8875 ; This splitter will be matched by combine and has to add the 2 moves
8876 ; necessary to load the compare and the increment values into a
8877 ; register pair as needed by brxle.
8878
8879 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8880   [(set (pc)
8881         (if_then_else
8882          (match_operator 6 "s390_brx_operator"
8883             [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8884                        (match_operand:GPR 2 "general_operand"  ""))
8885              (match_operand:GPR 3 "register_operand" "")])
8886          (label_ref (match_operand 0 "" ""))
8887          (pc)))
8888    (set (match_operand:GPR 4 "nonimmediate_operand" "")
8889         (plus:GPR (match_dup 1) (match_dup 2)))
8890    (clobber (match_scratch:GPR 5 ""))]
8891   "TARGET_CPU_ZARCH"
8892   "#"
8893   "!reload_completed && !reload_in_progress"
8894   [(set (match_dup 7) (match_dup 2)) ; the increment
8895    (set (match_dup 8) (match_dup 3)) ; the comparison value
8896    (parallel [(set (pc)
8897                    (if_then_else
8898                     (match_op_dup 6
8899                        [(plus:GPR (match_dup 1) (match_dup 7))
8900                         (match_dup 8)])
8901                     (label_ref (match_dup 0))
8902                     (pc)))
8903               (set (match_dup 4)
8904                    (plus:GPR (match_dup 1) (match_dup 7)))
8905               (clobber (match_dup 5))
8906               (clobber (reg:CC CC_REGNUM))])]
8907   {
8908     rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8909     operands[7] = gen_lowpart (<GPR:MODE>mode,
8910                                gen_highpart (word_mode, dreg));
8911     operands[8] = gen_lowpart (<GPR:MODE>mode,
8912                                gen_lowpart (word_mode, dreg));
8913   })
8914
8915 ; brxlg, brxhg
8916
8917 (define_insn_and_split "*brxg_64bit"
8918   [(set (pc)
8919         (if_then_else
8920           (match_operator 5 "s390_brx_operator"
8921              [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8922                        (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8923               (subreg:DI (match_dup 2) 8)])
8924           (label_ref (match_operand 0 "" ""))
8925           (pc)))
8926    (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8927         (plus:DI (match_dup 1)
8928                  (subreg:DI (match_dup 2) 0)))
8929    (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8930    (clobber (reg:CC CC_REGNUM))]
8931   "TARGET_ZARCH"
8932 {
8933   if (which_alternative != 0)
8934     return "#";
8935   else if (get_attr_length (insn) == 6)
8936     return "brx%E5g\t%1,%2,%l0";
8937   else
8938     return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8939 }
8940   "&& reload_completed
8941    && (!REG_P (operands[3])
8942        || !rtx_equal_p (operands[1], operands[3]))"
8943   [(set (match_dup 4) (match_dup 1))
8944    (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8945               (clobber (reg:CC CC_REGNUM))])
8946    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8947    (set (match_dup 3) (match_dup 4))
8948    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8949                            (label_ref (match_dup 0))
8950                            (pc)))]
8951   ""
8952   [(set_attr "op_type"  "RIE")
8953    (set_attr "type"  "branch")
8954    (set (attr "length")
8955         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8956                       (const_int 6) (const_int 16)))])
8957
8958 ; brxle, brxh
8959
8960 (define_insn_and_split "*brx_64bit"
8961   [(set (pc)
8962         (if_then_else
8963           (match_operator 5 "s390_brx_operator"
8964              [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8965                        (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8966               (subreg:SI (match_dup 2) 12)])
8967           (label_ref (match_operand 0 "" ""))
8968           (pc)))
8969    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8970         (plus:SI (match_dup 1)
8971                  (subreg:SI (match_dup 2) 4)))
8972    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8973    (clobber (reg:CC CC_REGNUM))]
8974   "TARGET_ZARCH"
8975 {
8976   if (which_alternative != 0)
8977     return "#";
8978   else if (get_attr_length (insn) == 6)
8979     return "brx%C5\t%1,%2,%l0";
8980   else
8981     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8982 }
8983   "&& reload_completed
8984    && (!REG_P (operands[3])
8985        || !rtx_equal_p (operands[1], operands[3]))"
8986   [(set (match_dup 4) (match_dup 1))
8987    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8988               (clobber (reg:CC CC_REGNUM))])
8989    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8990    (set (match_dup 3) (match_dup 4))
8991    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8992                            (label_ref (match_dup 0))
8993                            (pc)))]
8994   ""
8995   [(set_attr "op_type"  "RSI")
8996    (set_attr "type"  "branch")
8997    (set (attr "length")
8998         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8999                       (const_int 6) (const_int 14)))])
9000
9001 ; brxle, brxh
9002
9003 (define_insn_and_split "*brx_31bit"
9004   [(set (pc)
9005         (if_then_else
9006           (match_operator 5 "s390_brx_operator"
9007             [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9008                       (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9009              (subreg:SI (match_dup 2) 4)])
9010           (label_ref (match_operand 0 "" ""))
9011           (pc)))
9012    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9013         (plus:SI (match_dup 1)
9014                  (subreg:SI (match_dup 2) 0)))
9015    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9016    (clobber (reg:CC CC_REGNUM))]
9017   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9018 {
9019   if (which_alternative != 0)
9020     return "#";
9021   else if (get_attr_length (insn) == 6)
9022     return "brx%C5\t%1,%2,%l0";
9023   else
9024     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9025 }
9026   "&& reload_completed
9027    && (!REG_P (operands[3])
9028        || !rtx_equal_p (operands[1], operands[3]))"
9029   [(set (match_dup 4) (match_dup 1))
9030    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9031               (clobber (reg:CC CC_REGNUM))])
9032    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9033    (set (match_dup 3) (match_dup 4))
9034    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9035                            (label_ref (match_dup 0))
9036                            (pc)))]
9037   ""
9038   [(set_attr "op_type"  "RSI")
9039    (set_attr "type"  "branch")
9040    (set (attr "length")
9041         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9042                       (const_int 6) (const_int 14)))])
9043
9044
9045 ;; branch on count
9046
9047 (define_expand "doloop_end"
9048   [(use (match_operand 0 "" ""))        ; loop pseudo
9049    (use (match_operand 1 "" ""))]       ; label
9050   ""
9051 {
9052   if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9053     emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9054   else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9055     emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9056   else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9057     emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9058   else
9059     FAIL;
9060
9061   DONE;
9062 })
9063
9064 (define_insn_and_split "doloop_si64"
9065   [(set (pc)
9066         (if_then_else
9067           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9068               (const_int 1))
9069           (label_ref (match_operand 0 "" ""))
9070           (pc)))
9071    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9072         (plus:SI (match_dup 1) (const_int -1)))
9073    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9074    (clobber (reg:CC CC_REGNUM))]
9075   "TARGET_CPU_ZARCH"
9076 {
9077   if (which_alternative != 0)
9078     return "#";
9079   else if (get_attr_length (insn) == 4)
9080     return "brct\t%1,%l0";
9081   else
9082     return "ahi\t%1,-1\;jgne\t%l0";
9083 }
9084   "&& reload_completed
9085    && (! REG_P (operands[2])
9086        || ! rtx_equal_p (operands[1], operands[2]))"
9087   [(set (match_dup 3) (match_dup 1))
9088    (parallel [(set (reg:CCAN CC_REGNUM)
9089                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9090                                  (const_int 0)))
9091               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9092    (set (match_dup 2) (match_dup 3))
9093    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9094                            (label_ref (match_dup 0))
9095                            (pc)))]
9096   ""
9097   [(set_attr "op_type"  "RI")
9098    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9099    ; hurt us in the (rare) case of ahi.
9100    (set_attr "z10prop"  "z10_super_E1")
9101    (set_attr "type"  "branch")
9102    (set (attr "length")
9103         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9104                       (const_int 4) (const_int 10)))])
9105
9106 (define_insn_and_split "doloop_si31"
9107   [(set (pc)
9108         (if_then_else
9109           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9110               (const_int 1))
9111           (label_ref (match_operand 0 "" ""))
9112           (pc)))
9113    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9114         (plus:SI (match_dup 1) (const_int -1)))
9115    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9116    (clobber (reg:CC CC_REGNUM))]
9117   "!TARGET_CPU_ZARCH"
9118 {
9119   if (which_alternative != 0)
9120     return "#";
9121   else if (get_attr_length (insn) == 4)
9122     return "brct\t%1,%l0";
9123   else
9124     gcc_unreachable ();
9125 }
9126   "&& reload_completed
9127    && (! REG_P (operands[2])
9128        || ! rtx_equal_p (operands[1], operands[2]))"
9129   [(set (match_dup 3) (match_dup 1))
9130    (parallel [(set (reg:CCAN CC_REGNUM)
9131                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9132                                  (const_int 0)))
9133               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9134    (set (match_dup 2) (match_dup 3))
9135    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9136                            (label_ref (match_dup 0))
9137                            (pc)))]
9138   ""
9139   [(set_attr "op_type"  "RI")
9140    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9141    ; hurt us in the (rare) case of ahi.
9142    (set_attr "z10prop"  "z10_super_E1")
9143    (set_attr "type"  "branch")
9144    (set (attr "length")
9145         (if_then_else (not (match_test "flag_pic"))
9146           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9147                         (const_int 4) (const_int 6))
9148           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9149                         (const_int 4) (const_int 8))))])
9150
9151 (define_insn "*doloop_si_long"
9152   [(set (pc)
9153         (if_then_else
9154           (ne (match_operand:SI 1 "register_operand" "d")
9155               (const_int 1))
9156           (match_operand 0 "address_operand" "ZR")
9157           (pc)))
9158    (set (match_operand:SI 2 "register_operand" "=1")
9159         (plus:SI (match_dup 1) (const_int -1)))
9160    (clobber (match_scratch:SI 3 "=X"))
9161    (clobber (reg:CC CC_REGNUM))]
9162   "!TARGET_CPU_ZARCH"
9163 {
9164   if (get_attr_op_type (insn) == OP_TYPE_RR)
9165     return "bctr\t%1,%0";
9166   else
9167     return "bct\t%1,%a0";
9168 }
9169   [(set (attr "op_type")
9170         (if_then_else (match_operand 0 "register_operand" "")
9171                       (const_string "RR") (const_string "RX")))
9172    (set_attr "type"  "branch")
9173    (set_attr "atype" "agen")
9174    (set_attr "z10prop"  "z10_c")
9175    (set_attr "z196prop" "z196_cracked")])
9176
9177 (define_insn_and_split "doloop_di"
9178   [(set (pc)
9179         (if_then_else
9180           (ne (match_operand:DI 1 "register_operand" "d,d,d")
9181               (const_int 1))
9182           (label_ref (match_operand 0 "" ""))
9183           (pc)))
9184    (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9185         (plus:DI (match_dup 1) (const_int -1)))
9186    (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9187    (clobber (reg:CC CC_REGNUM))]
9188   "TARGET_ZARCH"
9189 {
9190   if (which_alternative != 0)
9191     return "#";
9192   else if (get_attr_length (insn) == 4)
9193     return "brctg\t%1,%l0";
9194   else
9195     return "aghi\t%1,-1\;jgne\t%l0";
9196 }
9197   "&& reload_completed
9198    && (! REG_P (operands[2])
9199        || ! rtx_equal_p (operands[1], operands[2]))"
9200   [(set (match_dup 3) (match_dup 1))
9201    (parallel [(set (reg:CCAN CC_REGNUM)
9202                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9203                                  (const_int 0)))
9204               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9205    (set (match_dup 2) (match_dup 3))
9206    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9207                            (label_ref (match_dup 0))
9208                            (pc)))]
9209   ""
9210   [(set_attr "op_type"  "RI")
9211    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9212    ; hurt us in the (rare) case of ahi.
9213    (set_attr "z10prop"  "z10_super_E1")
9214    (set_attr "type"  "branch")
9215    (set (attr "length")
9216         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9217                       (const_int 4) (const_int 10)))])
9218
9219 ;;
9220 ;;- Unconditional jump instructions.
9221 ;;
9222
9223 ;
9224 ; jump instruction pattern(s).
9225 ;
9226
9227 (define_expand "jump"
9228   [(match_operand 0 "" "")]
9229   ""
9230   "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9231
9232 (define_insn "*jump64"
9233   [(set (pc) (label_ref (match_operand 0 "" "")))]
9234   "TARGET_CPU_ZARCH"
9235 {
9236   if (get_attr_length (insn) == 4)
9237     return "j\t%l0";
9238   else
9239     return "jg\t%l0";
9240 }
9241   [(set_attr "op_type" "RI")
9242    (set_attr "type"  "branch")
9243    (set (attr "length")
9244         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9245                       (const_int 4) (const_int 6)))])
9246
9247 (define_insn "*jump31"
9248   [(set (pc) (label_ref (match_operand 0 "" "")))]
9249   "!TARGET_CPU_ZARCH"
9250 {
9251   gcc_assert (get_attr_length (insn) == 4);
9252   return "j\t%l0";
9253 }
9254   [(set_attr "op_type" "RI")
9255    (set_attr "type"  "branch")
9256    (set (attr "length")
9257         (if_then_else (not (match_test "flag_pic"))
9258           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9259                         (const_int 4) (const_int 6))
9260           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9261                         (const_int 4) (const_int 8))))])
9262
9263 ;
9264 ; indirect-jump instruction pattern(s).
9265 ;
9266
9267 (define_insn "indirect_jump"
9268  [(set (pc) (match_operand 0 "address_operand" "ZR"))]
9269   ""
9270 {
9271   if (get_attr_op_type (insn) == OP_TYPE_RR)
9272     return "br\t%0";
9273   else
9274     return "b\t%a0";
9275 }
9276   [(set (attr "op_type")
9277         (if_then_else (match_operand 0 "register_operand" "")
9278                       (const_string "RR") (const_string "RX")))
9279    (set_attr "type"  "branch")
9280    (set_attr "atype" "agen")])
9281
9282 ;
9283 ; casesi instruction pattern(s).
9284 ;
9285
9286 (define_insn "casesi_jump"
9287  [(set (pc) (match_operand 0 "address_operand" "ZR"))
9288    (use (label_ref (match_operand 1 "" "")))]
9289   ""
9290 {
9291   if (get_attr_op_type (insn) == OP_TYPE_RR)
9292     return "br\t%0";
9293   else
9294     return "b\t%a0";
9295 }
9296   [(set (attr "op_type")
9297         (if_then_else (match_operand 0 "register_operand" "")
9298                       (const_string "RR") (const_string "RX")))
9299    (set_attr "type"  "branch")
9300    (set_attr "atype" "agen")])
9301
9302 (define_expand "casesi"
9303   [(match_operand:SI 0 "general_operand" "")
9304    (match_operand:SI 1 "general_operand" "")
9305    (match_operand:SI 2 "general_operand" "")
9306    (label_ref (match_operand 3 "" ""))
9307    (label_ref (match_operand 4 "" ""))]
9308   ""
9309 {
9310    rtx index  = gen_reg_rtx (SImode);
9311    rtx base   = gen_reg_rtx (Pmode);
9312    rtx target = gen_reg_rtx (Pmode);
9313
9314    emit_move_insn (index, operands[0]);
9315    emit_insn (gen_subsi3 (index, index, operands[1]));
9316    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9317                             operands[4]);
9318
9319    if (Pmode != SImode)
9320      index = convert_to_mode (Pmode, index, 1);
9321    if (GET_CODE (index) != REG)
9322      index = copy_to_mode_reg (Pmode, index);
9323
9324    if (TARGET_64BIT)
9325        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9326    else
9327        emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9328
9329    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9330
9331    index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9332    emit_move_insn (target, index);
9333
9334    if (flag_pic)
9335      target = gen_rtx_PLUS (Pmode, base, target);
9336    emit_jump_insn (gen_casesi_jump (target, operands[3]));
9337
9338    DONE;
9339 })
9340
9341
9342 ;;
9343 ;;- Jump to subroutine.
9344 ;;
9345 ;;
9346
9347 ;
9348 ; untyped call instruction pattern(s).
9349 ;
9350
9351 ;; Call subroutine returning any type.
9352 (define_expand "untyped_call"
9353   [(parallel [(call (match_operand 0 "" "")
9354                     (const_int 0))
9355               (match_operand 1 "" "")
9356               (match_operand 2 "" "")])]
9357   ""
9358 {
9359   int i;
9360
9361   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9362
9363   for (i = 0; i < XVECLEN (operands[2], 0); i++)
9364     {
9365       rtx set = XVECEXP (operands[2], 0, i);
9366       emit_move_insn (SET_DEST (set), SET_SRC (set));
9367     }
9368
9369   /* The optimizer does not know that the call sets the function value
9370      registers we stored in the result block.  We avoid problems by
9371      claiming that all hard registers are used and clobbered at this
9372      point.  */
9373   emit_insn (gen_blockage ());
9374
9375   DONE;
9376 })
9377
9378 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9379 ;; all of memory.  This blocks insns from being moved across this point.
9380
9381 (define_insn "blockage"
9382   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9383   ""
9384   ""
9385   [(set_attr "type"    "none")
9386    (set_attr "length"  "0")])
9387
9388 ;
9389 ; sibcall patterns
9390 ;
9391
9392 (define_expand "sibcall"
9393   [(call (match_operand 0 "" "")
9394          (match_operand 1 "" ""))]
9395   ""
9396 {
9397   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9398   DONE;
9399 })
9400
9401 (define_insn "*sibcall_br"
9402   [(call (mem:QI (reg SIBCALL_REGNUM))
9403          (match_operand 0 "const_int_operand" "n"))]
9404   "SIBLING_CALL_P (insn)
9405    && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9406   "br\t%%r1"
9407   [(set_attr "op_type" "RR")
9408    (set_attr "type"  "branch")
9409    (set_attr "atype" "agen")])
9410
9411 (define_insn "*sibcall_brc"
9412   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9413          (match_operand 1 "const_int_operand" "n"))]
9414   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9415   "j\t%0"
9416   [(set_attr "op_type" "RI")
9417    (set_attr "type"    "branch")])
9418
9419 (define_insn "*sibcall_brcl"
9420   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9421          (match_operand 1 "const_int_operand" "n"))]
9422   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9423   "jg\t%0"
9424   [(set_attr "op_type" "RIL")
9425    (set_attr "type"    "branch")])
9426
9427 ;
9428 ; sibcall_value patterns
9429 ;
9430
9431 (define_expand "sibcall_value"
9432   [(set (match_operand 0 "" "")
9433         (call (match_operand 1 "" "")
9434               (match_operand 2 "" "")))]
9435   ""
9436 {
9437   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9438   DONE;
9439 })
9440
9441 (define_insn "*sibcall_value_br"
9442   [(set (match_operand 0 "" "")
9443         (call (mem:QI (reg SIBCALL_REGNUM))
9444               (match_operand 1 "const_int_operand" "n")))]
9445   "SIBLING_CALL_P (insn)
9446    && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9447   "br\t%%r1"
9448   [(set_attr "op_type" "RR")
9449    (set_attr "type"  "branch")
9450    (set_attr "atype" "agen")])
9451
9452 (define_insn "*sibcall_value_brc"
9453   [(set (match_operand 0 "" "")
9454         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9455               (match_operand 2 "const_int_operand" "n")))]
9456   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9457   "j\t%1"
9458   [(set_attr "op_type" "RI")
9459    (set_attr "type"    "branch")])
9460
9461 (define_insn "*sibcall_value_brcl"
9462   [(set (match_operand 0 "" "")
9463         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9464               (match_operand 2 "const_int_operand" "n")))]
9465   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9466   "jg\t%1"
9467   [(set_attr "op_type" "RIL")
9468    (set_attr "type"    "branch")])
9469
9470
9471 ;
9472 ; call instruction pattern(s).
9473 ;
9474
9475 (define_expand "call"
9476   [(call (match_operand 0 "" "")
9477          (match_operand 1 "" ""))
9478    (use (match_operand 2 "" ""))]
9479   ""
9480 {
9481   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9482                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9483   DONE;
9484 })
9485
9486 (define_insn "*bras"
9487   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9488          (match_operand 1 "const_int_operand" "n"))
9489    (clobber (match_operand 2 "register_operand" "=r"))]
9490   "!SIBLING_CALL_P (insn)
9491    && TARGET_SMALL_EXEC
9492    && GET_MODE (operands[2]) == Pmode"
9493   "bras\t%2,%0"
9494   [(set_attr "op_type" "RI")
9495    (set_attr "type"    "jsr")
9496    (set_attr "z196prop" "z196_cracked")])
9497
9498 (define_insn "*brasl"
9499   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9500          (match_operand 1 "const_int_operand" "n"))
9501    (clobber (match_operand 2 "register_operand" "=r"))]
9502   "!SIBLING_CALL_P (insn)
9503    && TARGET_CPU_ZARCH
9504    && GET_MODE (operands[2]) == Pmode"
9505   "brasl\t%2,%0"
9506   [(set_attr "op_type" "RIL")
9507    (set_attr "type"    "jsr")
9508    (set_attr "z196prop" "z196_cracked")])
9509
9510 (define_insn "*basr"
9511   [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
9512          (match_operand 1 "const_int_operand" "n"))
9513    (clobber (match_operand 2 "register_operand" "=r"))]
9514   "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9515 {
9516   if (get_attr_op_type (insn) == OP_TYPE_RR)
9517     return "basr\t%2,%0";
9518   else
9519     return "bas\t%2,%a0";
9520 }
9521   [(set (attr "op_type")
9522         (if_then_else (match_operand 0 "register_operand" "")
9523                       (const_string "RR") (const_string "RX")))
9524    (set_attr "type"  "jsr")
9525    (set_attr "atype" "agen")
9526    (set_attr "z196prop" "z196_cracked")])
9527
9528 ;
9529 ; call_value instruction pattern(s).
9530 ;
9531
9532 (define_expand "call_value"
9533   [(set (match_operand 0 "" "")
9534         (call (match_operand 1 "" "")
9535               (match_operand 2 "" "")))
9536    (use (match_operand 3 "" ""))]
9537   ""
9538 {
9539   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9540                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9541   DONE;
9542 })
9543
9544 (define_insn "*bras_r"
9545   [(set (match_operand 0 "" "")
9546         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9547               (match_operand:SI 2 "const_int_operand" "n")))
9548    (clobber (match_operand 3 "register_operand" "=r"))]
9549   "!SIBLING_CALL_P (insn)
9550    && TARGET_SMALL_EXEC
9551    && GET_MODE (operands[3]) == Pmode"
9552   "bras\t%3,%1"
9553   [(set_attr "op_type" "RI")
9554    (set_attr "type"    "jsr")
9555    (set_attr "z196prop" "z196_cracked")])
9556
9557 (define_insn "*brasl_r"
9558   [(set (match_operand 0 "" "")
9559         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9560               (match_operand 2 "const_int_operand" "n")))
9561    (clobber (match_operand 3 "register_operand" "=r"))]
9562   "!SIBLING_CALL_P (insn)
9563    && TARGET_CPU_ZARCH
9564    && GET_MODE (operands[3]) == Pmode"
9565   "brasl\t%3,%1"
9566   [(set_attr "op_type" "RIL")
9567    (set_attr "type"    "jsr")
9568    (set_attr "z196prop" "z196_cracked")])
9569
9570 (define_insn "*basr_r"
9571   [(set (match_operand 0 "" "")
9572         (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9573               (match_operand 2 "const_int_operand" "n")))
9574    (clobber (match_operand 3 "register_operand" "=r"))]
9575   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9576 {
9577   if (get_attr_op_type (insn) == OP_TYPE_RR)
9578     return "basr\t%3,%1";
9579   else
9580     return "bas\t%3,%a1";
9581 }
9582   [(set (attr "op_type")
9583         (if_then_else (match_operand 1 "register_operand" "")
9584                       (const_string "RR") (const_string "RX")))
9585    (set_attr "type"  "jsr")
9586    (set_attr "atype" "agen")
9587    (set_attr "z196prop" "z196_cracked")])
9588
9589 ;;
9590 ;;- Thread-local storage support.
9591 ;;
9592
9593 (define_expand "get_thread_pointer<mode>"
9594   [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9595   ""
9596   "")
9597
9598 (define_expand "set_thread_pointer<mode>"
9599   [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9600    (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9601   ""
9602   "")
9603
9604 (define_insn "*set_tp"
9605   [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9606   ""
9607   ""
9608   [(set_attr "type" "none")
9609    (set_attr "length" "0")])
9610
9611 (define_insn "*tls_load_64"
9612   [(set (match_operand:DI 0 "register_operand" "=d")
9613         (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
9614                     (match_operand:DI 2 "" "")]
9615                    UNSPEC_TLS_LOAD))]
9616   "TARGET_64BIT"
9617   "lg\t%0,%1%J2"
9618   [(set_attr "op_type" "RXE")
9619    (set_attr "z10prop" "z10_fwd_A3")])
9620
9621 (define_insn "*tls_load_31"
9622   [(set (match_operand:SI 0 "register_operand" "=d,d")
9623         (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9624                     (match_operand:SI 2 "" "")]
9625                    UNSPEC_TLS_LOAD))]
9626   "!TARGET_64BIT"
9627   "@
9628    l\t%0,%1%J2
9629    ly\t%0,%1%J2"
9630   [(set_attr "op_type" "RX,RXY")
9631    (set_attr "type" "load")
9632    (set_attr "cpu_facility" "*,longdisp")
9633    (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9634
9635 (define_insn "*bras_tls"
9636   [(set (match_operand 0 "" "")
9637         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9638               (match_operand 2 "const_int_operand" "n")))
9639    (clobber (match_operand 3 "register_operand" "=r"))
9640    (use (match_operand 4 "" ""))]
9641   "!SIBLING_CALL_P (insn)
9642    && TARGET_SMALL_EXEC
9643    && GET_MODE (operands[3]) == Pmode"
9644   "bras\t%3,%1%J4"
9645   [(set_attr "op_type" "RI")
9646    (set_attr "type"    "jsr")
9647    (set_attr "z196prop" "z196_cracked")])
9648
9649 (define_insn "*brasl_tls"
9650   [(set (match_operand 0 "" "")
9651         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9652               (match_operand 2 "const_int_operand" "n")))
9653    (clobber (match_operand 3 "register_operand" "=r"))
9654    (use (match_operand 4 "" ""))]
9655   "!SIBLING_CALL_P (insn)
9656    && TARGET_CPU_ZARCH
9657    && GET_MODE (operands[3]) == Pmode"
9658   "brasl\t%3,%1%J4"
9659   [(set_attr "op_type" "RIL")
9660    (set_attr "type"    "jsr")
9661    (set_attr "z196prop" "z196_cracked")])
9662
9663 (define_insn "*basr_tls"
9664   [(set (match_operand 0 "" "")
9665         (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9666               (match_operand 2 "const_int_operand" "n")))
9667    (clobber (match_operand 3 "register_operand" "=r"))
9668    (use (match_operand 4 "" ""))]
9669   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9670 {
9671   if (get_attr_op_type (insn) == OP_TYPE_RR)
9672     return "basr\t%3,%1%J4";
9673   else
9674     return "bas\t%3,%a1%J4";
9675 }
9676   [(set (attr "op_type")
9677         (if_then_else (match_operand 1 "register_operand" "")
9678                       (const_string "RR") (const_string "RX")))
9679    (set_attr "type"  "jsr")
9680    (set_attr "atype" "agen")
9681    (set_attr "z196prop" "z196_cracked")])
9682
9683 ;;
9684 ;;- Atomic operations
9685 ;;
9686
9687 ;
9688 ; memory barrier patterns.
9689 ;
9690
9691 (define_expand "mem_signal_fence"
9692   [(match_operand:SI 0 "const_int_operand")]            ;; model
9693   ""
9694 {
9695   /* The s390 memory model is strong enough not to require any
9696      barrier in order to synchronize a thread with itself.  */
9697   DONE;
9698 })
9699
9700 (define_expand "mem_thread_fence"
9701   [(match_operand:SI 0 "const_int_operand")]            ;; model
9702   ""
9703 {
9704   /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9705      enough not to require barriers of any kind.  */
9706   if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9707     {
9708       rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9709       MEM_VOLATILE_P (mem) = 1;
9710       emit_insn (gen_mem_thread_fence_1 (mem));
9711     }
9712   DONE;
9713 })
9714
9715 ; Although bcr is superscalar on Z10, this variant will never
9716 ; become part of an execution group.
9717 ; With z196 we can make use of the fast-BCR-serialization facility.
9718 ; This allows for a slightly faster sync which is sufficient for our
9719 ; purposes.
9720 (define_insn "mem_thread_fence_1"
9721   [(set (match_operand:BLK 0 "" "")
9722         (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9723   ""
9724 {
9725   if (TARGET_Z196)
9726     return "bcr\t14,0";
9727   else
9728     return "bcr\t15,0";
9729 }
9730   [(set_attr "op_type" "RR")
9731    (set_attr "mnemonic" "bcr_flush")
9732    (set_attr "z196prop" "z196_alone")])
9733
9734 ;
9735 ; atomic load/store operations
9736 ;
9737
9738 ; Atomic loads need not examine the memory model at all.
9739 (define_expand "atomic_load<mode>"
9740   [(match_operand:DINT 0 "register_operand")    ;; output
9741    (match_operand:DINT 1 "memory_operand")      ;; memory
9742    (match_operand:SI 2 "const_int_operand")]    ;; model
9743   ""
9744 {
9745   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9746     FAIL;
9747
9748   if (<MODE>mode == TImode)
9749     emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9750   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9751     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9752   else
9753     emit_move_insn (operands[0], operands[1]);
9754   DONE;
9755 })
9756
9757 ; Different from movdi_31 in that we want no splitters.
9758 (define_insn "atomic_loaddi_1"
9759   [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9760         (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9761                    UNSPEC_MOVA))]
9762   "!TARGET_ZARCH"
9763   "@
9764    lm\t%0,%M0,%S1
9765    lmy\t%0,%M0,%S1
9766    ld\t%0,%1
9767    ldy\t%0,%1"
9768   [(set_attr "op_type" "RS,RSY,RS,RSY")
9769    (set_attr "cpu_facility" "*,longdisp,*,longdisp")
9770    (set_attr "type" "lm,lm,floaddf,floaddf")])
9771
9772 (define_insn "atomic_loadti_1"
9773   [(set (match_operand:TI 0 "register_operand" "=r")
9774         (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
9775                    UNSPEC_MOVA))]
9776   "TARGET_ZARCH"
9777   "lpq\t%0,%1"
9778   [(set_attr "op_type" "RXY")
9779    (set_attr "type" "other")])
9780
9781 ; Atomic stores must(?) enforce sequential consistency.
9782 (define_expand "atomic_store<mode>"
9783   [(match_operand:DINT 0 "memory_operand")      ;; memory
9784    (match_operand:DINT 1 "register_operand")    ;; input
9785    (match_operand:SI 2 "const_int_operand")]    ;; model
9786   ""
9787 {
9788   enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9789
9790   if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9791     FAIL;
9792
9793   if (<MODE>mode == TImode)
9794     emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9795   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9796     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9797   else
9798     emit_move_insn (operands[0], operands[1]);
9799   if (is_mm_seq_cst (model))
9800     emit_insn (gen_mem_thread_fence (operands[2]));
9801   DONE;
9802 })
9803
9804 ; Different from movdi_31 in that we want no splitters.
9805 (define_insn "atomic_storedi_1"
9806   [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9807         (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9808                    UNSPEC_MOVA))]
9809   "!TARGET_ZARCH"
9810   "@
9811    stm\t%1,%N1,%S0
9812    stmy\t%1,%N1,%S0
9813    std %1,%0
9814    stdy %1,%0"
9815   [(set_attr "op_type" "RS,RSY,RS,RSY")
9816    (set_attr "cpu_facility" "*,longdisp,*,longdisp")
9817    (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9818
9819 (define_insn "atomic_storeti_1"
9820   [(set (match_operand:TI 0 "memory_operand" "=T")
9821         (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9822                    UNSPEC_MOVA))]
9823   "TARGET_ZARCH"
9824   "stpq\t%1,%0"
9825   [(set_attr "op_type" "RXY")
9826    (set_attr "type" "other")])
9827
9828 ;
9829 ; compare and swap patterns.
9830 ;
9831
9832 (define_expand "atomic_compare_and_swap<mode>"
9833   [(match_operand:SI 0 "register_operand")      ;; bool success output
9834    (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9835    (match_operand:DGPR 2 "memory_operand")      ;; memory
9836    (match_operand:DGPR 3 "register_operand")    ;; expected intput
9837    (match_operand:DGPR 4 "register_operand")    ;; newval intput
9838    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9839    (match_operand:SI 6 "const_int_operand")     ;; success model
9840    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9841   ""
9842 {
9843   rtx cc, cmp, output = operands[1];
9844
9845   if (!register_operand (output, <MODE>mode))
9846     output = gen_reg_rtx (<MODE>mode);
9847
9848   if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9849     FAIL;
9850
9851   emit_insn (gen_atomic_compare_and_swap<mode>_internal
9852              (output, operands[2], operands[3], operands[4]));
9853
9854   /* We deliberately accept non-register operands in the predicate
9855      to ensure the write back to the output operand happens *before*
9856      the store-flags code below.  This makes it easier for combine
9857      to merge the store-flags code with a potential test-and-branch
9858      pattern following (immediately!) afterwards.  */
9859   if (output != operands[1])
9860     emit_move_insn (operands[1], output);
9861
9862   cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9863   cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9864   emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9865   DONE;
9866 })
9867
9868 (define_expand "atomic_compare_and_swap<mode>"
9869   [(match_operand:SI 0 "register_operand")      ;; bool success output
9870    (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9871    (match_operand:HQI 2 "memory_operand")       ;; memory
9872    (match_operand:HQI 3 "general_operand")      ;; expected intput
9873    (match_operand:HQI 4 "general_operand")      ;; newval intput
9874    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9875    (match_operand:SI 6 "const_int_operand")     ;; success model
9876    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9877   ""
9878 {
9879   s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9880                       operands[3], operands[4], INTVAL (operands[5]));
9881   DONE;
9882 })
9883
9884 (define_expand "atomic_compare_and_swap<mode>_internal"
9885   [(parallel
9886      [(set (match_operand:DGPR 0 "register_operand")
9887            (match_operand:DGPR 1 "memory_operand"))
9888       (set (match_dup 1)
9889            (unspec_volatile:DGPR
9890              [(match_dup 1)
9891               (match_operand:DGPR 2 "register_operand")
9892               (match_operand:DGPR 3 "register_operand")]
9893              UNSPECV_CAS))
9894       (set (reg:CCZ1 CC_REGNUM)
9895            (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9896   "")
9897
9898 ; cdsg, csg
9899 (define_insn "*atomic_compare_and_swap<mode>_1"
9900   [(set (match_operand:TDI 0 "register_operand" "=r")
9901         (match_operand:TDI 1 "memory_operand" "+S"))
9902    (set (match_dup 1)
9903         (unspec_volatile:TDI
9904           [(match_dup 1)
9905            (match_operand:TDI 2 "register_operand" "0")
9906            (match_operand:TDI 3 "register_operand" "r")]
9907           UNSPECV_CAS))
9908    (set (reg:CCZ1 CC_REGNUM)
9909         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9910   "TARGET_ZARCH"
9911   "c<td>sg\t%0,%3,%S1"
9912   [(set_attr "op_type" "RSY")
9913    (set_attr "type"   "sem")])
9914
9915 ; cds, cdsy
9916 (define_insn "*atomic_compare_and_swapdi_2"
9917   [(set (match_operand:DI 0 "register_operand" "=r,r")
9918         (match_operand:DI 1 "memory_operand" "+Q,S"))
9919    (set (match_dup 1)
9920         (unspec_volatile:DI
9921           [(match_dup 1)
9922            (match_operand:DI 2 "register_operand" "0,0")
9923            (match_operand:DI 3 "register_operand" "r,r")]
9924           UNSPECV_CAS))
9925    (set (reg:CCZ1 CC_REGNUM)
9926         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9927   "!TARGET_ZARCH"
9928   "@
9929    cds\t%0,%3,%S1
9930    cdsy\t%0,%3,%S1"
9931   [(set_attr "op_type" "RS,RSY")
9932    (set_attr "cpu_facility" "*,longdisp")
9933    (set_attr "type" "sem")])
9934
9935 ; cs, csy
9936 (define_insn "*atomic_compare_and_swapsi_3"
9937   [(set (match_operand:SI 0 "register_operand" "=r,r")
9938         (match_operand:SI 1 "memory_operand" "+Q,S"))
9939    (set (match_dup 1)
9940         (unspec_volatile:SI
9941           [(match_dup 1)
9942            (match_operand:SI 2 "register_operand" "0,0")
9943            (match_operand:SI 3 "register_operand" "r,r")]
9944           UNSPECV_CAS))
9945    (set (reg:CCZ1 CC_REGNUM)
9946         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9947   ""
9948   "@
9949    cs\t%0,%3,%S1
9950    csy\t%0,%3,%S1"
9951   [(set_attr "op_type" "RS,RSY")
9952    (set_attr "cpu_facility" "*,longdisp")
9953    (set_attr "type"   "sem")])
9954
9955 ;
9956 ; Other atomic instruction patterns.
9957 ;
9958
9959 ; z196 load and add, xor, or and and instructions
9960
9961 (define_expand "atomic_fetch_<atomic><mode>"
9962   [(match_operand:GPR 0 "register_operand")             ;; val out
9963    (ATOMIC_Z196:GPR
9964      (match_operand:GPR 1 "memory_operand")             ;; memory
9965      (match_operand:GPR 2 "register_operand"))          ;; val in
9966    (match_operand:SI 3 "const_int_operand")]            ;; model
9967   "TARGET_Z196"
9968 {
9969   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9970     FAIL;
9971
9972   emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9973              (operands[0], operands[1], operands[2]));
9974   DONE;
9975 })
9976
9977 ; lan, lang, lao, laog, lax, laxg, laa, laag
9978 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9979   [(set (match_operand:GPR 0 "register_operand" "=d")
9980         (match_operand:GPR 1 "memory_operand" "+S"))
9981    (set (match_dup 1)
9982         (unspec_volatile:GPR
9983          [(ATOMIC_Z196:GPR (match_dup 1)
9984                            (match_operand:GPR 2 "general_operand" "d"))]
9985          UNSPECV_ATOMIC_OP))
9986    (clobber (reg:CC CC_REGNUM))]
9987   "TARGET_Z196"
9988   "la<noxa><g>\t%0,%2,%1"
9989   [(set_attr "op_type" "RSY")
9990    (set_attr "type" "sem")])
9991
9992 ;; For SImode and larger, the optabs.c code will do just fine in
9993 ;; expanding a compare-and-swap loop.  For QI/HImode, we can do
9994 ;; better by expanding our own loop.
9995
9996 (define_expand "atomic_<atomic><mode>"
9997   [(ATOMIC:HQI
9998      (match_operand:HQI 0 "memory_operand")             ;; memory
9999      (match_operand:HQI 1 "general_operand"))           ;; val in
10000    (match_operand:SI 2 "const_int_operand")]            ;; model
10001   ""
10002 {
10003   s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10004                        operands[1], false);
10005   DONE;
10006 })
10007
10008 (define_expand "atomic_fetch_<atomic><mode>"
10009   [(match_operand:HQI 0 "register_operand")             ;; val out
10010    (ATOMIC:HQI
10011      (match_operand:HQI 1 "memory_operand")             ;; memory
10012      (match_operand:HQI 2 "general_operand"))           ;; val in
10013    (match_operand:SI 3 "const_int_operand")]            ;; model
10014   ""
10015 {
10016   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10017                       operands[2], false);
10018   DONE;
10019 })
10020
10021 (define_expand "atomic_<atomic>_fetch<mode>"
10022   [(match_operand:HQI 0 "register_operand")             ;; val out
10023    (ATOMIC:HQI
10024      (match_operand:HQI 1 "memory_operand")             ;; memory
10025      (match_operand:HQI 2 "general_operand"))           ;; val in
10026    (match_operand:SI 3 "const_int_operand")]            ;; model
10027   ""
10028 {
10029   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10030                       operands[2], true);
10031   DONE;
10032 })
10033
10034 (define_expand "atomic_exchange<mode>"
10035   [(match_operand:HQI 0 "register_operand")             ;; val out
10036    (match_operand:HQI 1 "memory_operand")               ;; memory
10037    (match_operand:HQI 2 "general_operand")              ;; val in
10038    (match_operand:SI 3 "const_int_operand")]            ;; model
10039   ""
10040 {
10041   s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10042                       operands[2], false);
10043   DONE;
10044 })
10045
10046 ;;
10047 ;;- Miscellaneous instructions.
10048 ;;
10049
10050 ;
10051 ; allocate stack instruction pattern(s).
10052 ;
10053
10054 (define_expand "allocate_stack"
10055   [(match_operand 0 "general_operand" "")
10056    (match_operand 1 "general_operand" "")]
10057  "TARGET_BACKCHAIN"
10058 {
10059   rtx temp = gen_reg_rtx (Pmode);
10060
10061   emit_move_insn (temp, s390_back_chain_rtx ());
10062   anti_adjust_stack (operands[1]);
10063   emit_move_insn (s390_back_chain_rtx (), temp);
10064
10065   emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10066   DONE;
10067 })
10068
10069
10070 ;
10071 ; setjmp instruction pattern.
10072 ;
10073
10074 (define_expand "builtin_setjmp_receiver"
10075   [(match_operand 0 "" "")]
10076   "flag_pic"
10077 {
10078   emit_insn (s390_load_got ());
10079   emit_use (pic_offset_table_rtx);
10080   DONE;
10081 })
10082
10083 ;; These patterns say how to save and restore the stack pointer.  We need not
10084 ;; save the stack pointer at function level since we are careful to
10085 ;; preserve the backchain.  At block level, we have to restore the backchain
10086 ;; when we restore the stack pointer.
10087 ;;
10088 ;; For nonlocal gotos, we must save both the stack pointer and its
10089 ;; backchain and restore both.  Note that in the nonlocal case, the
10090 ;; save area is a memory location.
10091
10092 (define_expand "save_stack_function"
10093   [(match_operand 0 "general_operand" "")
10094    (match_operand 1 "general_operand" "")]
10095   ""
10096   "DONE;")
10097
10098 (define_expand "restore_stack_function"
10099   [(match_operand 0 "general_operand" "")
10100    (match_operand 1 "general_operand" "")]
10101   ""
10102   "DONE;")
10103
10104 (define_expand "restore_stack_block"
10105   [(match_operand 0 "register_operand" "")
10106    (match_operand 1 "register_operand" "")]
10107   "TARGET_BACKCHAIN"
10108 {
10109   rtx temp = gen_reg_rtx (Pmode);
10110
10111   emit_move_insn (temp, s390_back_chain_rtx ());
10112   emit_move_insn (operands[0], operands[1]);
10113   emit_move_insn (s390_back_chain_rtx (), temp);
10114
10115   DONE;
10116 })
10117
10118 (define_expand "save_stack_nonlocal"
10119   [(match_operand 0 "memory_operand" "")
10120    (match_operand 1 "register_operand" "")]
10121   ""
10122 {
10123   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10124
10125   /* Copy the backchain to the first word, sp to the second and the
10126      literal pool base to the third.  */
10127
10128   rtx save_bc = adjust_address (operands[0], Pmode, 0);
10129   rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10130   rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10131
10132   if (TARGET_BACKCHAIN)
10133     emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10134
10135   emit_move_insn (save_sp, operands[1]);
10136   emit_move_insn (save_bp, base);
10137
10138   DONE;
10139 })
10140
10141 (define_expand "restore_stack_nonlocal"
10142   [(match_operand 0 "register_operand" "")
10143    (match_operand 1 "memory_operand" "")]
10144   ""
10145 {
10146   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10147   rtx temp = NULL_RTX;
10148
10149   /* Restore the backchain from the first word, sp from the second and the
10150      literal pool base from the third.  */
10151
10152   rtx save_bc = adjust_address (operands[1], Pmode, 0);
10153   rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10154   rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10155
10156   if (TARGET_BACKCHAIN)
10157     temp = force_reg (Pmode, save_bc);
10158
10159   emit_move_insn (base, save_bp);
10160   emit_move_insn (operands[0], save_sp);
10161
10162   if (temp)
10163     emit_move_insn (s390_back_chain_rtx (), temp);
10164
10165   emit_use (base);
10166   DONE;
10167 })
10168
10169 (define_expand "exception_receiver"
10170   [(const_int 0)]
10171   ""
10172 {
10173   s390_set_has_landing_pad_p (true);
10174   DONE;
10175 })
10176
10177 ;
10178 ; nop instruction pattern(s).
10179 ;
10180
10181 (define_insn "nop"
10182   [(const_int 0)]
10183   ""
10184   "lr\t0,0"
10185   [(set_attr "op_type" "RR")
10186    (set_attr "z10prop"  "z10_fr_E1")])
10187
10188 (define_insn "nop1"
10189   [(const_int 1)]
10190   ""
10191   "lr\t1,1"
10192   [(set_attr "op_type" "RR")])
10193
10194 ;;- Undeletable nops (used for hotpatching)
10195
10196 (define_insn "nop_2_byte"
10197   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10198   ""
10199   "nopr\t%%r7"
10200   [(set_attr "op_type" "RR")])
10201
10202 (define_insn "nop_4_byte"
10203   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10204   ""
10205   "nop\t0"
10206   [(set_attr "op_type" "RX")])
10207
10208 (define_insn "nop_6_byte"
10209   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10210   "TARGET_CPU_ZARCH"
10211   "brcl\t0, 0"
10212   [(set_attr "op_type" "RIL")])
10213
10214
10215 ;
10216 ; Special literal pool access instruction pattern(s).
10217 ;
10218
10219 (define_insn "*pool_entry"
10220   [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10221                     UNSPECV_POOL_ENTRY)]
10222   ""
10223 {
10224   machine_mode mode = GET_MODE (PATTERN (insn));
10225   unsigned int align = GET_MODE_BITSIZE (mode);
10226   s390_output_pool_entry (operands[0], mode, align);
10227   return "";
10228 }
10229   [(set (attr "length")
10230         (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10231
10232 (define_insn "pool_align"
10233   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10234                     UNSPECV_POOL_ALIGN)]
10235   ""
10236   ".align\t%0"
10237   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10238
10239 (define_insn "pool_section_start"
10240   [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10241   ""
10242 {
10243   switch_to_section (targetm.asm_out.function_rodata_section
10244                  (current_function_decl));
10245   return "";
10246 }
10247   [(set_attr "length" "0")])
10248
10249 (define_insn "pool_section_end"
10250   [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10251   ""
10252 {
10253   switch_to_section (current_function_section ());
10254   return "";
10255 }
10256   [(set_attr "length" "0")])
10257
10258 (define_insn "main_base_31_small"
10259   [(set (match_operand 0 "register_operand" "=a")
10260         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10261   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10262   "basr\t%0,0"
10263   [(set_attr "op_type" "RR")
10264    (set_attr "type"    "la")
10265    (set_attr "z196prop" "z196_cracked")])
10266
10267 (define_insn "main_base_31_large"
10268   [(set (match_operand 0 "register_operand" "=a")
10269         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10270    (set (pc) (label_ref (match_operand 2 "" "")))]
10271   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10272   "bras\t%0,%2"
10273   [(set_attr "op_type" "RI")
10274    (set_attr "z196prop" "z196_cracked")])
10275
10276 (define_insn "main_base_64"
10277   [(set (match_operand 0 "register_operand" "=a")
10278         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10279   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10280   "larl\t%0,%1"
10281   [(set_attr "op_type" "RIL")
10282    (set_attr "type"    "larl")
10283    (set_attr "z10prop" "z10_fwd_A1")])
10284
10285 (define_insn "main_pool"
10286   [(set (match_operand 0 "register_operand" "=a")
10287         (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10288   "GET_MODE (operands[0]) == Pmode"
10289 {
10290   gcc_unreachable ();
10291 }
10292   [(set (attr "type")
10293         (if_then_else (match_test "TARGET_CPU_ZARCH")
10294                       (const_string "larl") (const_string "la")))])
10295
10296 (define_insn "reload_base_31"
10297   [(set (match_operand 0 "register_operand" "=a")
10298         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10299   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10300   "basr\t%0,0\;la\t%0,%1-.(%0)"
10301   [(set_attr "length" "6")
10302    (set_attr "type" "la")
10303    (set_attr "z196prop" "z196_cracked")])
10304
10305 (define_insn "reload_base_64"
10306   [(set (match_operand 0 "register_operand" "=a")
10307         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10308   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10309   "larl\t%0,%1"
10310   [(set_attr "op_type" "RIL")
10311    (set_attr "type"    "larl")
10312    (set_attr "z10prop" "z10_fwd_A1")])
10313
10314 (define_insn "pool"
10315   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10316   ""
10317 {
10318   gcc_unreachable ();
10319 }
10320   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10321
10322 ;;
10323 ;; Insns related to generating the function prologue and epilogue.
10324 ;;
10325
10326
10327 (define_expand "prologue"
10328   [(use (const_int 0))]
10329   ""
10330   "s390_emit_prologue (); DONE;")
10331
10332 (define_expand "epilogue"
10333   [(use (const_int 1))]
10334   ""
10335   "s390_emit_epilogue (false); DONE;")
10336
10337 (define_expand "sibcall_epilogue"
10338   [(use (const_int 0))]
10339   ""
10340   "s390_emit_epilogue (true); DONE;")
10341
10342 ;; A direct return instruction, without using an epilogue.
10343 (define_insn "<code>"
10344   [(ANY_RETURN)]
10345   "s390_can_use_<code>_insn ()"
10346   "br\t%%r14"
10347   [(set_attr "op_type" "RR")
10348    (set_attr "type"    "jsr")
10349    (set_attr "atype"   "agen")])
10350
10351 (define_insn "*return"
10352   [(return)
10353    (use (match_operand 0 "register_operand" "a"))]
10354   "GET_MODE (operands[0]) == Pmode"
10355   "br\t%0"
10356   [(set_attr "op_type" "RR")
10357    (set_attr "type"    "jsr")
10358    (set_attr "atype"   "agen")])
10359
10360
10361 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10362 ;; pointer. This is used for compatibility.
10363
10364 (define_expand "ptr_extend"
10365   [(set (match_operand:DI 0 "register_operand" "=r")
10366         (match_operand:SI 1 "register_operand" "r"))]
10367   "TARGET_64BIT"
10368 {
10369   emit_insn (gen_anddi3 (operands[0],
10370                          gen_lowpart (DImode, operands[1]),
10371                          GEN_INT (0x7fffffff)));
10372   DONE;
10373 })
10374
10375 ;; Instruction definition to expand eh_return macro to support
10376 ;; swapping in special linkage return addresses.
10377
10378 (define_expand "eh_return"
10379   [(use (match_operand 0 "register_operand" ""))]
10380   "TARGET_TPF"
10381 {
10382   s390_emit_tpf_eh_return (operands[0]);
10383   DONE;
10384 })
10385
10386 ;
10387 ; Stack Protector Patterns
10388 ;
10389
10390 (define_expand "stack_protect_set"
10391   [(set (match_operand 0 "memory_operand" "")
10392         (match_operand 1 "memory_operand" ""))]
10393   ""
10394 {
10395 #ifdef TARGET_THREAD_SSP_OFFSET
10396   operands[1]
10397     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10398                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10399 #endif
10400   if (TARGET_64BIT)
10401     emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10402   else
10403     emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10404
10405   DONE;
10406 })
10407
10408 (define_insn "stack_protect_set<mode>"
10409   [(set (match_operand:DSI 0 "memory_operand" "=Q")
10410         (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10411   ""
10412   "mvc\t%O0(%G0,%R0),%S1"
10413   [(set_attr "op_type" "SS")])
10414
10415 (define_expand "stack_protect_test"
10416   [(set (reg:CC CC_REGNUM)
10417         (compare (match_operand 0 "memory_operand" "")
10418                  (match_operand 1 "memory_operand" "")))
10419    (match_operand 2 "" "")]
10420   ""
10421 {
10422   rtx cc_reg, test;
10423 #ifdef TARGET_THREAD_SSP_OFFSET
10424   operands[1]
10425     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10426                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10427 #endif
10428   if (TARGET_64BIT)
10429     emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10430   else
10431     emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10432
10433   cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10434   test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10435   emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10436   DONE;
10437 })
10438
10439 (define_insn "stack_protect_test<mode>"
10440   [(set (reg:CCZ CC_REGNUM)
10441         (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10442                      (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10443   ""
10444   "clc\t%O0(%G0,%R0),%S1"
10445   [(set_attr "op_type" "SS")])
10446
10447 ; This is used in s390_emit_prologue in order to prevent insns
10448 ; adjusting the stack pointer to be moved over insns writing stack
10449 ; slots using a copy of the stack pointer in a different register.
10450 (define_insn "stack_tie"
10451   [(set (match_operand:BLK 0 "memory_operand" "+m")
10452         (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10453   ""
10454   ""
10455   [(set_attr "length" "0")])
10456
10457
10458 (define_insn "stack_restore_from_fpr"
10459   [(set (reg:DI STACK_REGNUM)
10460         (match_operand:DI 0 "register_operand" "f"))
10461    (clobber (mem:BLK (scratch)))]
10462   "TARGET_Z10"
10463   "lgdr\t%%r15,%0"
10464   [(set_attr "op_type"  "RRE")])
10465
10466 ;
10467 ; Data prefetch patterns
10468 ;
10469
10470 (define_insn "prefetch"
10471   [(prefetch (match_operand 0    "address_operand"   "ZT,X")
10472              (match_operand:SI 1 "const_int_operand" " n,n")
10473              (match_operand:SI 2 "const_int_operand" " n,n"))]
10474   "TARGET_Z10"
10475 {
10476   switch (which_alternative)
10477     {
10478       case 0:
10479         return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10480       case 1:
10481         if (larl_operand (operands[0], Pmode))
10482           return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10483       default:
10484
10485         /* This might be reached for symbolic operands with an odd
10486            addend.  We simply omit the prefetch for such rare cases.  */
10487
10488         return "";
10489      }
10490 }
10491   [(set_attr "type" "load,larl")
10492    (set_attr "op_type" "RXY,RIL")
10493    (set_attr "z10prop" "z10_super")
10494    (set_attr "z196prop" "z196_alone")])
10495
10496
10497 ;
10498 ; Byte swap instructions
10499 ;
10500
10501 ; FIXME: There is also mvcin but we cannot use it since src and target
10502 ; may overlap.
10503 (define_insn "bswap<mode>2"
10504   [(set (match_operand:GPR 0            "nonimmediate_operand" "=d,d,T")
10505         (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
10506   "TARGET_CPU_ZARCH"
10507   "@
10508    lrv<g>r\t%0,%1
10509    lrv<g>\t%0,%1
10510    strv<g>\t%1,%0"
10511   [(set_attr "type" "*,load,store")
10512    (set_attr "op_type" "RRE,RXY,RXY")
10513    (set_attr "z10prop" "z10_super")])
10514
10515 (define_insn "bswaphi2"
10516   [(set (match_operand:HI 0           "nonimmediate_operand" "=d,d,T")
10517         (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
10518   "TARGET_CPU_ZARCH"
10519   "@
10520    #
10521    lrvh\t%0,%1
10522    strvh\t%1,%0"
10523   [(set_attr "type" "*,load,store")
10524    (set_attr "op_type" "RRE,RXY,RXY")
10525    (set_attr "z10prop" "z10_super")])
10526
10527 (define_split
10528   [(set (match_operand:HI 0           "register_operand" "")
10529         (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10530   "TARGET_CPU_ZARCH"
10531   [(set (match_dup 2) (bswap:SI (match_dup 3)))
10532    (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10533 {
10534   operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10535   operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10536 })
10537
10538
10539 ;
10540 ; Population count instruction
10541 ;
10542
10543 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10544 ; portions and stores the result in the corresponding bytes in op0.
10545 (define_insn "*popcount<mode>"
10546   [(set (match_operand:INT 0 "register_operand" "=d")
10547         (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10548    (clobber (reg:CC CC_REGNUM))]
10549   "TARGET_Z196"
10550   "popcnt\t%0,%1"
10551   [(set_attr "op_type" "RRE")])
10552
10553 (define_expand "popcountdi2"
10554   [; popcnt op0, op1
10555    (parallel [(set (match_operand:DI 0 "register_operand" "")
10556                    (unspec:DI [(match_operand:DI 1 "register_operand")]
10557                               UNSPEC_POPCNT))
10558               (clobber (reg:CC CC_REGNUM))])
10559    ; sllg op2, op0, 32
10560    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10561    ; agr op0, op2
10562    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10563               (clobber (reg:CC CC_REGNUM))])
10564    ; sllg op2, op0, 16
10565    (set (match_dup 2)
10566         (ashift:DI (match_dup 0) (const_int 16)))
10567    ; agr op0, op2
10568    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10569               (clobber (reg:CC CC_REGNUM))])
10570    ; sllg op2, op0, 8
10571    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10572    ; agr op0, op2
10573    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10574               (clobber (reg:CC CC_REGNUM))])
10575    ; srlg op0, op0, 56
10576    (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10577   "TARGET_Z196 && TARGET_64BIT"
10578   "operands[2] = gen_reg_rtx (DImode);")
10579
10580 (define_expand "popcountsi2"
10581   [; popcnt op0, op1
10582    (parallel [(set (match_operand:SI 0 "register_operand" "")
10583                    (unspec:SI [(match_operand:SI 1 "register_operand")]
10584                               UNSPEC_POPCNT))
10585               (clobber (reg:CC CC_REGNUM))])
10586    ; sllk op2, op0, 16
10587    (set (match_dup 2)
10588         (ashift:SI (match_dup 0) (const_int 16)))
10589    ; ar op0, op2
10590    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10591               (clobber (reg:CC CC_REGNUM))])
10592    ; sllk op2, op0, 8
10593    (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10594    ; ar op0, op2
10595    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10596               (clobber (reg:CC CC_REGNUM))])
10597    ; srl op0, op0, 24
10598    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10599   "TARGET_Z196"
10600   "operands[2] = gen_reg_rtx (SImode);")
10601
10602 (define_expand "popcounthi2"
10603   [; popcnt op0, op1
10604    (parallel [(set (match_operand:HI 0 "register_operand" "")
10605                    (unspec:HI [(match_operand:HI 1 "register_operand")]
10606                               UNSPEC_POPCNT))
10607               (clobber (reg:CC CC_REGNUM))])
10608    ; sllk op2, op0, 8
10609    (set (match_dup 2)
10610         (ashift:SI (match_dup 0) (const_int 8)))
10611    ; ar op0, op2
10612    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10613               (clobber (reg:CC CC_REGNUM))])
10614    ; srl op0, op0, 8
10615    (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10616   "TARGET_Z196"
10617   "operands[2] = gen_reg_rtx (SImode);")
10618
10619 (define_expand "popcountqi2"
10620   [; popcnt op0, op1
10621    (parallel [(set (match_operand:QI 0 "register_operand" "")
10622                    (unspec:QI [(match_operand:QI 1 "register_operand")]
10623                               UNSPEC_POPCNT))
10624               (clobber (reg:CC CC_REGNUM))])]
10625   "TARGET_Z196"
10626   "")
10627
10628 ;;
10629 ;;- Copy sign instructions
10630 ;;
10631
10632 (define_insn "copysign<mode>3"
10633   [(set (match_operand:FP 0 "register_operand" "=f")
10634       (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10635                   (match_operand:FP 2 "register_operand" "f")]
10636                   UNSPEC_COPYSIGN))]
10637   "TARGET_Z196"
10638   "cpsdr\t%0,%2,%1"
10639   [(set_attr "op_type"  "RRF")
10640    (set_attr "type"     "fsimp<mode>")])
10641
10642
10643 ;;
10644 ;;- Transactional execution instructions
10645 ;;
10646
10647 ; This splitter helps combine to make use of CC directly when
10648 ; comparing the integer result of a tbegin builtin with a constant.
10649 ; The unspec is already removed by canonicalize_comparison. So this
10650 ; splitters only job is to turn the PARALLEL into separate insns
10651 ; again.  Unfortunately this only works with the very first cc/int
10652 ; compare since combine is not able to deal with data flow across
10653 ; basic block boundaries.
10654
10655 ; It needs to be an insn pattern as well since combine does not apply
10656 ; the splitter directly.  Combine would only use it if it actually
10657 ; would reduce the number of instructions.
10658 (define_insn_and_split "*ccraw_to_int"
10659   [(set (pc)
10660         (if_then_else
10661          (match_operator 0 "s390_eqne_operator"
10662                          [(reg:CCRAW CC_REGNUM)
10663                           (match_operand 1 "const_int_operand" "")])
10664          (label_ref (match_operand 2 "" ""))
10665          (pc)))
10666    (set (match_operand:SI 3 "register_operand" "=d")
10667         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10668   ""
10669   "#"
10670   ""
10671   [(set (match_dup 3)
10672         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10673    (set (pc)
10674         (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10675                       (label_ref (match_dup 2))
10676                       (pc)))]
10677   "")
10678
10679 ; Non-constrained transaction begin
10680
10681 (define_expand "tbegin"
10682   [(match_operand:SI 0 "register_operand" "")
10683    (match_operand:BLK 1 "memory_operand" "")]
10684   "TARGET_HTM"
10685 {
10686   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10687   DONE;
10688 })
10689
10690 (define_expand "tbegin_nofloat"
10691   [(match_operand:SI 0 "register_operand" "")
10692    (match_operand:BLK 1 "memory_operand" "")]
10693   "TARGET_HTM"
10694 {
10695   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10696   DONE;
10697 })
10698
10699 (define_expand "tbegin_retry"
10700   [(match_operand:SI 0 "register_operand" "")
10701    (match_operand:BLK 1 "memory_operand" "")
10702    (match_operand:SI 2 "general_operand" "")]
10703   "TARGET_HTM"
10704 {
10705   s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10706   DONE;
10707 })
10708
10709 (define_expand "tbegin_retry_nofloat"
10710   [(match_operand:SI 0 "register_operand" "")
10711    (match_operand:BLK 1 "memory_operand" "")
10712    (match_operand:SI 2 "general_operand" "")]
10713   "TARGET_HTM"
10714 {
10715   s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10716   DONE;
10717 })
10718
10719 ; Clobber VRs since they don't get restored
10720 (define_insn "tbegin_1_z13"
10721   [(set (reg:CCRAW CC_REGNUM)
10722         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10723                                UNSPECV_TBEGIN))
10724    (set (match_operand:BLK 1 "memory_operand" "=Q")
10725         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10726    (clobber (reg:TI 16)) (clobber (reg:TI 38))
10727    (clobber (reg:TI 17)) (clobber (reg:TI 39))
10728    (clobber (reg:TI 18)) (clobber (reg:TI 40))
10729    (clobber (reg:TI 19)) (clobber (reg:TI 41))
10730    (clobber (reg:TI 20)) (clobber (reg:TI 42))
10731    (clobber (reg:TI 21)) (clobber (reg:TI 43))
10732    (clobber (reg:TI 22)) (clobber (reg:TI 44))
10733    (clobber (reg:TI 23)) (clobber (reg:TI 45))
10734    (clobber (reg:TI 24)) (clobber (reg:TI 46))
10735    (clobber (reg:TI 25)) (clobber (reg:TI 47))
10736    (clobber (reg:TI 26)) (clobber (reg:TI 48))
10737    (clobber (reg:TI 27)) (clobber (reg:TI 49))
10738    (clobber (reg:TI 28)) (clobber (reg:TI 50))
10739    (clobber (reg:TI 29)) (clobber (reg:TI 51))
10740    (clobber (reg:TI 30)) (clobber (reg:TI 52))
10741    (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10742 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10743 ; not supposed to be used for immediates (see genpreds.c).
10744   "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10745   "tbegin\t%1,%x0"
10746   [(set_attr "op_type" "SIL")])
10747
10748 (define_insn "tbegin_1"
10749   [(set (reg:CCRAW CC_REGNUM)
10750         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10751                                UNSPECV_TBEGIN))
10752    (set (match_operand:BLK 1 "memory_operand" "=Q")
10753         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10754    (clobber (reg:DF 16))
10755    (clobber (reg:DF 17))
10756    (clobber (reg:DF 18))
10757    (clobber (reg:DF 19))
10758    (clobber (reg:DF 20))
10759    (clobber (reg:DF 21))
10760    (clobber (reg:DF 22))
10761    (clobber (reg:DF 23))
10762    (clobber (reg:DF 24))
10763    (clobber (reg:DF 25))
10764    (clobber (reg:DF 26))
10765    (clobber (reg:DF 27))
10766    (clobber (reg:DF 28))
10767    (clobber (reg:DF 29))
10768    (clobber (reg:DF 30))
10769    (clobber (reg:DF 31))]
10770 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10771 ; not supposed to be used for immediates (see genpreds.c).
10772   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10773   "tbegin\t%1,%x0"
10774   [(set_attr "op_type" "SIL")])
10775
10776 ; Same as above but without the FPR clobbers
10777 (define_insn "tbegin_nofloat_1"
10778   [(set (reg:CCRAW CC_REGNUM)
10779         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10780                                UNSPECV_TBEGIN))
10781    (set (match_operand:BLK 1 "memory_operand" "=Q")
10782         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10783   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10784   "tbegin\t%1,%x0"
10785   [(set_attr "op_type" "SIL")])
10786
10787
10788 ; Constrained transaction begin
10789
10790 (define_expand "tbeginc"
10791   [(set (reg:CCRAW CC_REGNUM)
10792         (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10793                                UNSPECV_TBEGINC))]
10794   "TARGET_HTM"
10795   "")
10796
10797 (define_insn "*tbeginc_1"
10798   [(set (reg:CCRAW CC_REGNUM)
10799         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10800                                UNSPECV_TBEGINC))]
10801   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10802   "tbeginc\t0,%x0"
10803   [(set_attr "op_type" "SIL")])
10804
10805 ; Transaction end
10806
10807 (define_expand "tend"
10808   [(set (reg:CCRAW CC_REGNUM)
10809         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10810    (set (match_operand:SI 0 "register_operand" "")
10811         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10812   "TARGET_HTM"
10813   "")
10814
10815 (define_insn "*tend_1"
10816   [(set (reg:CCRAW CC_REGNUM)
10817         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10818   "TARGET_HTM"
10819   "tend"
10820   [(set_attr "op_type" "S")])
10821
10822 ; Transaction abort
10823
10824 (define_expand "tabort"
10825   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
10826                     UNSPECV_TABORT)]
10827   "TARGET_HTM && operands != NULL"
10828 {
10829   if (CONST_INT_P (operands[0])
10830       && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10831     {
10832       error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10833              ".  Values in range 0 through 255 are reserved.",
10834              INTVAL (operands[0]));
10835       FAIL;
10836     }
10837 })
10838
10839 (define_insn "*tabort_1"
10840   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
10841                     UNSPECV_TABORT)]
10842   "TARGET_HTM && operands != NULL"
10843   "tabort\t%Y0"
10844   [(set_attr "op_type" "S")])
10845
10846 (define_insn "*tabort_1_plus"
10847   [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand"  "a")
10848                               (match_operand:SI 1 "const_int_operand" "J"))]
10849                     UNSPECV_TABORT)]
10850   "TARGET_HTM && operands != NULL
10851    && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
10852   "tabort\t%1(%0)"
10853   [(set_attr "op_type" "S")])
10854
10855 ; Transaction extract nesting depth
10856
10857 (define_insn "etnd"
10858   [(set (match_operand:SI 0 "register_operand" "=d")
10859         (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10860   "TARGET_HTM"
10861   "etnd\t%0"
10862   [(set_attr "op_type" "RRE")])
10863
10864 ; Non-transactional store
10865
10866 (define_insn "ntstg"
10867   [(set (match_operand:DI 0 "memory_operand" "=T")
10868         (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10869                             UNSPECV_NTSTG))]
10870   "TARGET_HTM"
10871   "ntstg\t%1,%0"
10872   [(set_attr "op_type" "RXY")])
10873
10874 ; Transaction perform processor assist
10875
10876 (define_expand "tx_assist"
10877   [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10878                      (reg:SI GPR0_REGNUM)
10879                      (const_int 1)]
10880                     UNSPECV_PPA)]
10881   "TARGET_HTM"
10882   "")
10883
10884 (define_insn "*ppa"
10885   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10886                      (match_operand:SI 1 "register_operand" "d")
10887                      (match_operand 2 "const_int_operand" "I")]
10888                     UNSPECV_PPA)]
10889   "TARGET_HTM && INTVAL (operands[2]) < 16"
10890   "ppa\t%0,%1,%2"
10891   [(set_attr "op_type" "RRF")])
10892
10893
10894 ; Set and get floating point control register
10895
10896 (define_insn "sfpc"
10897   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10898                     UNSPECV_SFPC)]
10899   "TARGET_HARD_FLOAT"
10900   "sfpc\t%0")
10901
10902 (define_insn "efpc"
10903   [(set (match_operand:SI 0 "register_operand" "=d")
10904         (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10905   "TARGET_HARD_FLOAT"
10906   "efpc\t%0")
10907
10908
10909 ; Load count to block boundary
10910
10911 (define_insn "lcbb"
10912   [(set (match_operand:SI             0 "register_operand"  "=d")
10913         (unspec:SI [(match_operand    1 "address_operand" "ZR")
10914                     (match_operand:SI 2 "immediate_operand"  "C")] UNSPEC_LCBB))
10915    (clobber (reg:CC CC_REGNUM))]
10916   "TARGET_Z13"
10917   "lcbb\t%0,%a1,%b2"
10918   [(set_attr "op_type" "VRX")])
10919
10920 ; Handle -fsplit-stack.
10921
10922 (define_expand "split_stack_prologue"
10923   [(const_int 0)]
10924   ""
10925 {
10926   s390_expand_split_stack_prologue ();
10927   DONE;
10928 })
10929
10930 ;; If there are operand 0 bytes available on the stack, jump to
10931 ;; operand 1.
10932
10933 (define_expand "split_stack_space_check"
10934   [(set (pc) (if_then_else
10935               (ltu (minus (reg 15)
10936                           (match_operand 0 "register_operand"))
10937                    (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
10938               (label_ref (match_operand 1))
10939               (pc)))]
10940   ""
10941 {
10942   /* Offset from thread pointer to __private_ss.  */
10943   int psso = TARGET_64BIT ? 0x38 : 0x20;
10944   rtx tp = s390_get_thread_pointer ();
10945   rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
10946   rtx reg = gen_reg_rtx (Pmode);
10947   rtx cc;
10948   if (TARGET_64BIT)
10949     emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
10950   else
10951     emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
10952   cc = s390_emit_compare (GT, reg, guard);
10953   s390_emit_jump (operands[1], cc);
10954
10955   DONE;
10956 })
10957
10958 ;; __morestack parameter block for split stack prologue.  Parameters are:
10959 ;; parameter block label, label to be called by __morestack, frame size,
10960 ;; stack parameter size.
10961
10962 (define_insn "split_stack_data"
10963   [(unspec_volatile [(match_operand 0 "" "X")
10964                      (match_operand 1 "" "X")
10965                      (match_operand 2 "const_int_operand" "X")
10966                      (match_operand 3 "const_int_operand" "X")]
10967                     UNSPECV_SPLIT_STACK_DATA)]
10968   "TARGET_CPU_ZARCH"
10969 {
10970   switch_to_section (targetm.asm_out.function_rodata_section
10971                  (current_function_decl));
10972
10973   if (TARGET_64BIT)
10974     output_asm_insn (".align\t8", operands);
10975   else
10976     output_asm_insn (".align\t4", operands);
10977   (*targetm.asm_out.internal_label) (asm_out_file, "L",
10978                                      CODE_LABEL_NUMBER (operands[0]));
10979   if (TARGET_64BIT)
10980     {
10981       output_asm_insn (".quad\t%2", operands);
10982       output_asm_insn (".quad\t%3", operands);
10983       output_asm_insn (".quad\t%1-%0", operands);
10984     }
10985   else
10986     {
10987       output_asm_insn (".long\t%2", operands);
10988       output_asm_insn (".long\t%3", operands);
10989       output_asm_insn (".long\t%1-%0", operands);
10990     }
10991
10992   switch_to_section (current_function_section ());
10993   return "";
10994 }
10995   [(set_attr "length" "0")])
10996
10997
10998 ;; A jg with minimal fuss for use in split stack prologue.
10999
11000 (define_expand "split_stack_call"
11001   [(match_operand 0 "bras_sym_operand" "X")
11002    (match_operand 1 "" "")]
11003   "TARGET_CPU_ZARCH"
11004 {
11005   if (TARGET_64BIT)
11006     emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
11007   else
11008     emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
11009   DONE;
11010 })
11011
11012 (define_insn "split_stack_call_<mode>"
11013   [(set (pc) (label_ref (match_operand 1 "" "")))
11014    (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11015                                     (reg:P 1)]
11016                                    UNSPECV_SPLIT_STACK_CALL))]
11017   "TARGET_CPU_ZARCH"
11018   "jg\t%0"
11019   [(set_attr "op_type" "RIL")
11020    (set_attr "type"  "branch")])
11021
11022 ;; Also a conditional one.
11023
11024 (define_expand "split_stack_cond_call"
11025   [(match_operand 0 "bras_sym_operand" "X")
11026    (match_operand 1 "" "")
11027    (match_operand 2 "" "")]
11028   "TARGET_CPU_ZARCH"
11029 {
11030   if (TARGET_64BIT)
11031     emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
11032   else
11033     emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
11034   DONE;
11035 })
11036
11037 (define_insn "split_stack_cond_call_<mode>"
11038   [(set (pc)
11039         (if_then_else
11040           (match_operand 1 "" "")
11041           (label_ref (match_operand 2 "" ""))
11042           (pc)))
11043    (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11044                                     (reg:P 1)]
11045                                    UNSPECV_SPLIT_STACK_CALL))]
11046   "TARGET_CPU_ZARCH"
11047   "jg%C1\t%0"
11048   [(set_attr "op_type" "RIL")
11049    (set_attr "type"  "branch")])