1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
67 ; GOT/PLT and lt-relative accesses
88 ; TLS relocation specifiers
104 ; Stack Smashing Protector
108 ; Test Data Class (TDC)
117 ;; UNSPEC_VOLATILE usage
120 (define_c_enum "unspecv" [
147 ; Registers with special meaning
151 ; Sibling call register.
153 ; Literal pool base register.
155 ; Return address register.
157 ; Condition code register.
159 ; Thread local storage pointer register.
163 ; Hardware register names
167 ; General purpose registers
169 ; Floating point registers.
175 ;; PFPO GPR0 argument format
180 ; PFPO operation type
181 (PFPO_CONVERT 0x1000000)
183 (PFPO_OP_TYPE_SF 0x5)
184 (PFPO_OP_TYPE_DF 0x6)
185 (PFPO_OP_TYPE_TF 0x7)
186 (PFPO_OP_TYPE_SD 0x8)
187 (PFPO_OP_TYPE_DD 0x9)
188 (PFPO_OP_TYPE_TD 0xa)
189 ; Bitposition of operand types
190 (PFPO_OP0_TYPE_SHIFT 16)
191 (PFPO_OP1_TYPE_SHIFT 8)
195 ;; Instruction operand type as used in the Principles of Operation.
196 ;; Used to determine defaults for length and other attribute values.
198 (define_attr "op_type"
199 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
202 ;; Instruction type attribute used for scheduling.
204 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
205 cs,vs,store,sem,idiv,
206 imulhi,imulsi,imuldi,
207 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
208 floadtf,floaddf,floadsf,fstoredf,fstoresf,
209 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
210 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
212 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
213 itoftf, itofdf, itofsf, itofdd, itoftd,
214 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
215 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
217 (cond [(eq_attr "op_type" "NN") (const_string "other")
218 (eq_attr "op_type" "SS") (const_string "cs")]
219 (const_string "integer")))
221 ;; Another attribute used for scheduling purposes:
222 ;; agen: Instruction uses the address generation unit
223 ;; reg: Instruction does not use the agen unit
225 (define_attr "atype" "agen,reg"
226 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
228 (const_string "agen")))
230 ;; Properties concerning Z10 execution grouping and value forwarding.
231 ;; z10_super: instruction is superscalar.
232 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
233 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
234 ;; target register. It can forward this value to a second instruction that reads
235 ;; the same register if that second instruction is issued in the same group.
236 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
237 ;; instruction in the S pipe writes to the register, then the T instruction
238 ;; can immediately read the new value.
239 ;; z10_fr: union of Z10_fwd and z10_rec.
240 ;; z10_c: second operand of instruction is a register and read with complemented bits.
242 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
245 (define_attr "z10prop" "none,
246 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
247 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
249 z10_fr, z10_fr_A3, z10_fr_E1,
251 (const_string "none"))
253 ;; Properties concerning Z196 decoding
254 ;; z196_alone: must group alone
255 ;; z196_end: ends a group
256 ;; z196_cracked: instruction is cracked or expanded
257 (define_attr "z196prop" "none,
258 z196_alone, z196_ends,
260 (const_string "none"))
262 (define_attr "mnemonic" "unknown" (const_string "unknown"))
266 (define_attr "length" ""
267 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
268 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
272 ;; Processor type. This attribute must exactly match the processor_type
273 ;; enumeration in s390.h. The current machine description does not
274 ;; distinguish between g5 and g6, but there are differences between the two
275 ;; CPUs could in theory be modeled.
277 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
278 (const (symbol_ref "s390_tune_attr")))
280 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196,zEC12"
281 (const_string "standard"))
283 (define_attr "enabled" ""
284 (cond [(eq_attr "cpu_facility" "standard")
287 (and (eq_attr "cpu_facility" "ieee")
288 (match_test "TARGET_CPU_IEEE_FLOAT"))
291 (and (eq_attr "cpu_facility" "zarch")
292 (match_test "TARGET_ZARCH"))
295 (and (eq_attr "cpu_facility" "longdisp")
296 (match_test "TARGET_LONG_DISPLACEMENT"))
299 (and (eq_attr "cpu_facility" "extimm")
300 (match_test "TARGET_EXTIMM"))
303 (and (eq_attr "cpu_facility" "dfp")
304 (match_test "TARGET_DFP"))
307 (and (eq_attr "cpu_facility" "z10")
308 (match_test "TARGET_Z10"))
311 (and (eq_attr "cpu_facility" "z196")
312 (match_test "TARGET_Z196"))
315 (and (eq_attr "cpu_facility" "zEC12")
316 (match_test "TARGET_ZEC12"))
320 ;; Pipeline description for z900. For lack of anything better,
321 ;; this description is also used for the g5 and g6.
324 ;; Pipeline description for z990, z9-109 and z9-ec.
327 ;; Pipeline description for z10
330 ;; Pipeline description for z196
333 ;; Pipeline description for zEC12
337 (include "predicates.md")
339 ;; Constraint definitions
340 (include "constraints.md")
347 ;; These mode iterators allow floating point patterns to be generated from the
349 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
350 (SD "TARGET_HARD_DFP")])
351 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
352 (define_mode_iterator FPALL [TF DF SF TD DD SD])
353 (define_mode_iterator BFP [TF DF SF])
354 (define_mode_iterator DFP [TD DD])
355 (define_mode_iterator DFP_ALL [TD DD SD])
356 (define_mode_iterator DSF [DF SF])
357 (define_mode_iterator SD_SF [SF SD])
358 (define_mode_iterator DD_DF [DF DD])
359 (define_mode_iterator TD_TF [TF TD])
361 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
362 ;; from the same template.
363 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
364 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
365 (define_mode_iterator DSI [DI SI])
366 (define_mode_iterator TDI [TI DI])
368 ;; These mode iterators allow :P to be used for patterns that operate on
369 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
370 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
372 ;; These macros refer to the actual word_mode of the configuration.
373 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
374 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
375 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
377 ;; Used by the umul pattern to express modes having half the size.
378 (define_mode_attr DWH [(TI "DI") (DI "SI")])
379 (define_mode_attr dwh [(TI "di") (DI "si")])
381 ;; This mode iterator allows the QI and HI patterns to be defined from
382 ;; the same template.
383 (define_mode_iterator HQI [HI QI])
385 ;; This mode iterator allows the integer patterns to be defined from the
387 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
388 (define_mode_iterator INTALL [TI DI SI HI QI])
389 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
391 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
392 ;; the same template.
393 (define_code_iterator SHIFT [ashift lshiftrt])
395 ;; This iterator allow r[ox]sbg to be defined with the same template
396 (define_code_iterator IXOR [ior xor])
398 ;; This iterator and attribute allow to combine most atomic operations.
399 (define_code_iterator ATOMIC [and ior xor plus minus mult])
400 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
401 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
402 (plus "add") (minus "sub") (mult "nand")])
403 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
405 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
406 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
407 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
409 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
410 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
412 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
414 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
415 ;; Likewise for "<RXe>".
416 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
417 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
419 ;; The decimal floating point variants of add, sub, div and mul support 3
420 ;; fp register operands. The following attributes allow to merge the bfp and
421 ;; dfp variants in a single insn definition.
423 ;; This attribute is used to set op_type accordingly.
424 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
425 (DD "RRR") (SD "RRR")])
427 ;; This attribute is used in the operand constraint list in order to have the
428 ;; first and the second operand match for bfp modes.
429 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
431 ;; This attribute is used in the operand list of the instruction to have an
432 ;; additional operand for the dfp instructions.
433 (define_mode_attr op1 [(TF "") (DF "") (SF "")
434 (TD "%1,") (DD "%1,") (SD "%1,")])
437 ;; This attribute is used in the operand constraint list
438 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
439 ;; TFmode values are represented by a fp register pair. Since the
440 ;; sign bit instructions only handle single source and target fp registers
441 ;; these instructions can only be used for TFmode values if the source and
442 ;; target operand uses the same fp register.
443 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
445 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
446 ;; This is used to disable the memory alternative in TFmode patterns.
447 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
449 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
450 ;; within instruction mnemonics.
451 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
453 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
454 ;; modes and to an empty string for bfp modes.
455 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
457 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
458 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
459 ;; version only operates on one register.
460 (define_mode_attr d0 [(DI "d") (SI "0")])
462 ;; In combination with d0 this allows to combine instructions of which the 31bit
463 ;; version only operates on one register. The DImode version needs an additional
464 ;; register for the assembler output.
465 (define_mode_attr 1 [(DI "%1,") (SI "")])
467 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
468 ;; 'ashift' and "srdl" in 'lshiftrt'.
469 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
471 ;; In SHIFT templates, this attribute holds the correct standard name for the
472 ;; pattern itself and the corresponding function calls.
473 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
475 ;; This attribute handles differences in the instruction 'type' and will result
476 ;; in "RRE" for DImode and "RR" for SImode.
477 (define_mode_attr E [(DI "E") (SI "")])
479 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
480 ;; to result in "RXY" for DImode and "RX" for SImode.
481 (define_mode_attr Y [(DI "Y") (SI "")])
483 ;; This attribute handles differences in the instruction 'type' and will result
484 ;; in "RSE" for TImode and "RS" for DImode.
485 (define_mode_attr TE [(TI "E") (DI "")])
487 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
488 ;; and "lcr" in SImode.
489 (define_mode_attr g [(DI "g") (SI "")])
491 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
492 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
493 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
494 ;; variant for long displacements.
495 (define_mode_attr y [(DI "g") (SI "y")])
497 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
498 ;; and "cds" in DImode.
499 (define_mode_attr tg [(TI "g") (DI "")])
501 ;; In TDI templates, a string like "c<d>sg".
502 (define_mode_attr td [(TI "d") (DI "")])
504 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
505 ;; and "cfdbr" in SImode.
506 (define_mode_attr gf [(DI "g") (SI "f")])
508 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
509 ;; and sllk for SI. This way it is possible to merge the new z196 SI
510 ;; 3 operands shift instructions into the existing patterns.
511 (define_mode_attr gk [(DI "g") (SI "k")])
513 ;; ICM mask required to load MODE value into the lowest subreg
514 ;; of a SImode register.
515 (define_mode_attr icm_lo [(HI "3") (QI "1")])
517 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
518 ;; HImode and "llgc" in QImode.
519 (define_mode_attr hc [(HI "h") (QI "c")])
521 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
523 (define_mode_attr DBL [(DI "TI") (SI "DI")])
525 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
526 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
527 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
529 ;; Maximum unsigned integer that fits in MODE.
530 (define_mode_attr max_uint [(HI "65535") (QI "255")])
532 ;; Start and end field computations for RISBG et al.
533 (define_mode_attr bfstart [(DI "s") (SI "t")])
534 (define_mode_attr bfend [(DI "e") (SI "f")])
536 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
537 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
540 ;;- Compare instructions.
543 ; Test-under-Mask instructions
545 (define_insn "*tmqi_mem"
546 [(set (reg CC_REGNUM)
547 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
548 (match_operand:QI 1 "immediate_operand" "n,n"))
549 (match_operand:QI 2 "immediate_operand" "n,n")))]
550 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
554 [(set_attr "op_type" "SI,SIY")
555 (set_attr "z10prop" "z10_super,z10_super")])
557 (define_insn "*tmdi_reg"
558 [(set (reg CC_REGNUM)
559 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
560 (match_operand:DI 1 "immediate_operand"
561 "N0HD0,N1HD0,N2HD0,N3HD0"))
562 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
564 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
565 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
571 [(set_attr "op_type" "RI")
572 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
574 (define_insn "*tmsi_reg"
575 [(set (reg CC_REGNUM)
576 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
577 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
578 (match_operand:SI 2 "immediate_operand" "n,n")))]
579 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
580 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
584 [(set_attr "op_type" "RI")
585 (set_attr "z10prop" "z10_super,z10_super")])
587 (define_insn "*tm<mode>_full"
588 [(set (reg CC_REGNUM)
589 (compare (match_operand:HQI 0 "register_operand" "d")
590 (match_operand:HQI 1 "immediate_operand" "n")))]
591 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
593 [(set_attr "op_type" "RI")
594 (set_attr "z10prop" "z10_super")])
598 ; Load-and-Test instructions
601 ; tst(di|si) instruction pattern(s).
603 (define_insn "*tstdi_sign"
604 [(set (reg CC_REGNUM)
608 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
609 (const_int 32)) (const_int 32))
610 (match_operand:DI 1 "const0_operand" "")))
611 (set (match_operand:DI 2 "register_operand" "=d,d")
612 (sign_extend:DI (match_dup 0)))]
613 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
616 [(set_attr "op_type" "RRE,RXY")
617 (set_attr "cpu_facility" "*,z10")
618 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
621 (define_insn "*tst<mode>_extimm"
622 [(set (reg CC_REGNUM)
623 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
624 (match_operand:GPR 1 "const0_operand" "")))
625 (set (match_operand:GPR 2 "register_operand" "=d,d")
627 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
631 [(set_attr "op_type" "RR<E>,RXY")
632 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
635 (define_insn "*tst<mode>_cconly_extimm"
636 [(set (reg CC_REGNUM)
637 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
638 (match_operand:GPR 1 "const0_operand" "")))
639 (clobber (match_scratch:GPR 2 "=X,d"))]
640 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
644 [(set_attr "op_type" "RR<E>,RXY")
645 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
647 (define_insn "*tstdi"
648 [(set (reg CC_REGNUM)
649 (compare (match_operand:DI 0 "register_operand" "d")
650 (match_operand:DI 1 "const0_operand" "")))
651 (set (match_operand:DI 2 "register_operand" "=d")
653 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
655 [(set_attr "op_type" "RRE")
656 (set_attr "z10prop" "z10_fr_E1")])
658 (define_insn "*tstsi"
659 [(set (reg CC_REGNUM)
660 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
661 (match_operand:SI 1 "const0_operand" "")))
662 (set (match_operand:SI 2 "register_operand" "=d,d,d")
664 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
669 [(set_attr "op_type" "RR,RS,RSY")
670 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
672 (define_insn "*tstsi_cconly"
673 [(set (reg CC_REGNUM)
674 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
675 (match_operand:SI 1 "const0_operand" "")))
676 (clobber (match_scratch:SI 2 "=X,d,d"))]
677 "s390_match_ccmode(insn, CCSmode)"
682 [(set_attr "op_type" "RR,RS,RSY")
683 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
685 (define_insn "*tstdi_cconly_31"
686 [(set (reg CC_REGNUM)
687 (compare (match_operand:DI 0 "register_operand" "d")
688 (match_operand:DI 1 "const0_operand" "")))]
689 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
691 [(set_attr "op_type" "RS")
692 (set_attr "atype" "reg")])
695 (define_insn "*tst<mode>_cconly2"
696 [(set (reg CC_REGNUM)
697 (compare (match_operand:GPR 0 "register_operand" "d")
698 (match_operand:GPR 1 "const0_operand" "")))]
699 "s390_match_ccmode(insn, CCSmode)"
701 [(set_attr "op_type" "RR<E>")
702 (set_attr "z10prop" "z10_fr_E1")])
704 ; tst(hi|qi) instruction pattern(s).
706 (define_insn "*tst<mode>CCT"
707 [(set (reg CC_REGNUM)
708 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
709 (match_operand:HQI 1 "const0_operand" "")))
710 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
712 "s390_match_ccmode(insn, CCTmode)"
715 icmy\t%2,<icm_lo>,%S0
717 [(set_attr "op_type" "RS,RSY,RI")
718 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
720 (define_insn "*tsthiCCT_cconly"
721 [(set (reg CC_REGNUM)
722 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
723 (match_operand:HI 1 "const0_operand" "")))
724 (clobber (match_scratch:HI 2 "=d,d,X"))]
725 "s390_match_ccmode(insn, CCTmode)"
730 [(set_attr "op_type" "RS,RSY,RI")
731 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
733 (define_insn "*tstqiCCT_cconly"
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
736 (match_operand:QI 1 "const0_operand" "")))]
737 "s390_match_ccmode(insn, CCTmode)"
742 [(set_attr "op_type" "SI,SIY,RI")
743 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
745 (define_insn "*tst<mode>"
746 [(set (reg CC_REGNUM)
747 (compare (match_operand:HQI 0 "s_operand" "Q,S")
748 (match_operand:HQI 1 "const0_operand" "")))
749 (set (match_operand:HQI 2 "register_operand" "=d,d")
751 "s390_match_ccmode(insn, CCSmode)"
754 icmy\t%2,<icm_lo>,%S0"
755 [(set_attr "op_type" "RS,RSY")
756 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
758 (define_insn "*tst<mode>_cconly"
759 [(set (reg CC_REGNUM)
760 (compare (match_operand:HQI 0 "s_operand" "Q,S")
761 (match_operand:HQI 1 "const0_operand" "")))
762 (clobber (match_scratch:HQI 2 "=d,d"))]
763 "s390_match_ccmode(insn, CCSmode)"
766 icmy\t%2,<icm_lo>,%S0"
767 [(set_attr "op_type" "RS,RSY")
768 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
771 ; Compare (equality) instructions
773 (define_insn "*cmpdi_cct"
774 [(set (reg CC_REGNUM)
775 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
776 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
777 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
784 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
785 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
787 (define_insn "*cmpsi_cct"
788 [(set (reg CC_REGNUM)
789 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
790 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
791 "s390_match_ccmode (insn, CCTmode)"
799 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
800 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
802 ; Compare (signed) instructions
804 (define_insn "*cmpdi_ccs_sign"
805 [(set (reg CC_REGNUM)
806 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
808 (match_operand:DI 0 "register_operand" "d, d,d")))]
809 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
814 [(set_attr "op_type" "RRE,RXY,RIL")
815 (set_attr "z10prop" "z10_c,*,*")
816 (set_attr "type" "*,*,larl")])
820 (define_insn "*cmpsi_ccs_sign"
821 [(set (reg CC_REGNUM)
822 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
823 (match_operand:SI 0 "register_operand" "d,d,d")))]
824 "s390_match_ccmode(insn, CCSRmode)"
829 [(set_attr "op_type" "RX,RXY,RIL")
830 (set_attr "cpu_facility" "*,*,z10")
831 (set_attr "type" "*,*,larl")
832 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
834 (define_insn "*cmphi_ccs_z10"
835 [(set (reg CC_REGNUM)
836 (compare (match_operand:HI 0 "s_operand" "Q")
837 (match_operand:HI 1 "immediate_operand" "K")))]
838 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
840 [(set_attr "op_type" "SIL")
841 (set_attr "z196prop" "z196_cracked")])
843 (define_insn "*cmpdi_ccs_signhi_rl"
844 [(set (reg CC_REGNUM)
845 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
846 (match_operand:GPR 0 "register_operand" "d,d")))]
847 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
851 [(set_attr "op_type" "RXY,RIL")
852 (set_attr "type" "*,larl")])
854 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
855 (define_insn "*cmp<mode>_ccs"
856 [(set (reg CC_REGNUM)
857 (compare (match_operand:GPR 0 "nonimmediate_operand"
859 (match_operand:GPR 1 "general_operand"
861 "s390_match_ccmode(insn, CCSmode)"
870 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
871 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
872 (set_attr "type" "*,*,*,*,*,*,larl")
873 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
876 ; Compare (unsigned) instructions
878 (define_insn "*cmpsi_ccu_zerohi_rlsi"
879 [(set (reg CC_REGNUM)
880 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
881 "larl_operand" "X")))
882 (match_operand:SI 0 "register_operand" "d")))]
883 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
885 [(set_attr "op_type" "RIL")
886 (set_attr "type" "larl")
887 (set_attr "z10prop" "z10_super")])
890 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
891 [(set (reg CC_REGNUM)
892 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
893 "larl_operand" "X")))
894 (match_operand:GPR 0 "register_operand" "d")))]
895 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
897 [(set_attr "op_type" "RIL")
898 (set_attr "type" "larl")
899 (set_attr "z10prop" "z10_super")])
901 (define_insn "*cmpdi_ccu_zero"
902 [(set (reg CC_REGNUM)
903 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
905 (match_operand:DI 0 "register_operand" "d, d,d")))]
906 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
911 [(set_attr "op_type" "RRE,RXY,RIL")
912 (set_attr "cpu_facility" "*,*,z10")
913 (set_attr "type" "*,*,larl")
914 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
916 (define_insn "*cmpdi_ccu"
917 [(set (reg CC_REGNUM)
918 (compare (match_operand:DI 0 "nonimmediate_operand"
920 (match_operand:DI 1 "general_operand"
921 "d,Op,b,D,RT,BQ,Q")))]
922 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
931 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
932 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
933 (set_attr "type" "*,*,larl,*,*,*,*")
934 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
936 (define_insn "*cmpsi_ccu"
937 [(set (reg CC_REGNUM)
938 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
939 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
940 "s390_match_ccmode (insn, CCUmode)"
950 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
951 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
952 (set_attr "type" "*,*,larl,*,*,*,*,*")
953 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
955 (define_insn "*cmphi_ccu"
956 [(set (reg CC_REGNUM)
957 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
958 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
959 "s390_match_ccmode (insn, CCUmode)
960 && !register_operand (operands[1], HImode)"
967 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
968 (set_attr "cpu_facility" "*,*,z10,*,*")
969 (set_attr "z10prop" "*,*,z10_super,*,*")])
971 (define_insn "*cmpqi_ccu"
972 [(set (reg CC_REGNUM)
973 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
974 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
975 "s390_match_ccmode (insn, CCUmode)
976 && !register_operand (operands[1], QImode)"
984 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
985 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
988 ; Block compare (CLC) instruction patterns.
991 [(set (reg CC_REGNUM)
992 (compare (match_operand:BLK 0 "memory_operand" "Q")
993 (match_operand:BLK 1 "memory_operand" "Q")))
994 (use (match_operand 2 "const_int_operand" "n"))]
995 "s390_match_ccmode (insn, CCUmode)
996 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
997 "clc\t%O0(%2,%R0),%S1"
998 [(set_attr "op_type" "SS")])
1001 [(set (reg CC_REGNUM)
1002 (compare (match_operand 0 "memory_operand" "")
1003 (match_operand 1 "memory_operand" "")))]
1005 && s390_match_ccmode (insn, CCUmode)
1006 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1007 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1009 [(set (match_dup 0) (match_dup 1))
1010 (use (match_dup 2))])]
1012 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1013 operands[0] = adjust_address (operands[0], BLKmode, 0);
1014 operands[1] = adjust_address (operands[1], BLKmode, 0);
1016 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1017 operands[0], operands[1]);
1018 operands[0] = SET_DEST (PATTERN (curr_insn));
1022 ; (TF|DF|SF|TD|DD|SD) instructions
1024 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1025 (define_insn "*cmp<mode>_ccs_0"
1026 [(set (reg CC_REGNUM)
1027 (compare (match_operand:FP 0 "register_operand" "f")
1028 (match_operand:FP 1 "const0_operand" "")))]
1029 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1030 "lt<xde><bt>r\t%0,%0"
1031 [(set_attr "op_type" "RRE")
1032 (set_attr "type" "fsimp<mode>")])
1034 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1035 (define_insn "*cmp<mode>_ccs"
1036 [(set (reg CC_REGNUM)
1037 (compare (match_operand:FP 0 "register_operand" "f,f")
1038 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1039 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1043 [(set_attr "op_type" "RRE,RXE")
1044 (set_attr "type" "fsimp<mode>")])
1047 ; Compare and Branch instructions
1049 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1050 ; The following instructions do a complementary access of their second
1051 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1052 (define_insn "*cmp_and_br_signed_<mode>"
1054 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1055 [(match_operand:GPR 1 "register_operand" "d,d")
1056 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1057 (label_ref (match_operand 3 "" ""))
1059 (clobber (reg:CC CC_REGNUM))]
1060 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1062 if (get_attr_length (insn) == 6)
1063 return which_alternative ?
1064 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1066 return which_alternative ?
1067 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1069 [(set_attr "op_type" "RIE")
1070 (set_attr "type" "branch")
1071 (set_attr "z10prop" "z10_super_c,z10_super")
1072 (set (attr "length")
1073 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1074 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1075 ; 10 byte for cgr/jg
1077 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1078 ; The following instructions do a complementary access of their second
1079 ; operand (z10 only): clrj, clgrj, clr, clgr
1080 (define_insn "*cmp_and_br_unsigned_<mode>"
1082 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1083 [(match_operand:GPR 1 "register_operand" "d,d")
1084 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1085 (label_ref (match_operand 3 "" ""))
1087 (clobber (reg:CC CC_REGNUM))]
1088 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1090 if (get_attr_length (insn) == 6)
1091 return which_alternative ?
1092 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1094 return which_alternative ?
1095 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1097 [(set_attr "op_type" "RIE")
1098 (set_attr "type" "branch")
1099 (set_attr "z10prop" "z10_super_c,z10_super")
1100 (set (attr "length")
1101 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1102 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1103 ; 10 byte for clgr/jg
1105 ; And now the same two patterns as above but with a negated CC mask.
1107 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1108 ; The following instructions do a complementary access of their second
1109 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1110 (define_insn "*icmp_and_br_signed_<mode>"
1112 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1113 [(match_operand:GPR 1 "register_operand" "d,d")
1114 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1116 (label_ref (match_operand 3 "" ""))))
1117 (clobber (reg:CC CC_REGNUM))]
1118 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1120 if (get_attr_length (insn) == 6)
1121 return which_alternative ?
1122 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1124 return which_alternative ?
1125 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1127 [(set_attr "op_type" "RIE")
1128 (set_attr "type" "branch")
1129 (set_attr "z10prop" "z10_super_c,z10_super")
1130 (set (attr "length")
1131 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1132 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1133 ; 10 byte for cgr/jg
1135 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1136 ; The following instructions do a complementary access of their second
1137 ; operand (z10 only): clrj, clgrj, clr, clgr
1138 (define_insn "*icmp_and_br_unsigned_<mode>"
1140 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1141 [(match_operand:GPR 1 "register_operand" "d,d")
1142 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1144 (label_ref (match_operand 3 "" ""))))
1145 (clobber (reg:CC CC_REGNUM))]
1146 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1148 if (get_attr_length (insn) == 6)
1149 return which_alternative ?
1150 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1152 return which_alternative ?
1153 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1155 [(set_attr "op_type" "RIE")
1156 (set_attr "type" "branch")
1157 (set_attr "z10prop" "z10_super_c,z10_super")
1158 (set (attr "length")
1159 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1160 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1161 ; 10 byte for clgr/jg
1164 ;;- Move instructions.
1168 ; movti instruction pattern(s).
1171 (define_insn "movti"
1172 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1173 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1180 [(set_attr "op_type" "RSY,RSY,*,*")
1181 (set_attr "type" "lm,stm,*,*")])
1184 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1185 (match_operand:TI 1 "general_operand" ""))]
1186 "TARGET_ZARCH && reload_completed
1187 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1188 [(set (match_dup 2) (match_dup 4))
1189 (set (match_dup 3) (match_dup 5))]
1191 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1192 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1193 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1194 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1198 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1199 (match_operand:TI 1 "general_operand" ""))]
1200 "TARGET_ZARCH && reload_completed
1201 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1202 [(set (match_dup 2) (match_dup 4))
1203 (set (match_dup 3) (match_dup 5))]
1205 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1206 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1207 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1208 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1212 [(set (match_operand:TI 0 "register_operand" "")
1213 (match_operand:TI 1 "memory_operand" ""))]
1214 "TARGET_ZARCH && reload_completed
1215 && !s_operand (operands[1], VOIDmode)"
1216 [(set (match_dup 0) (match_dup 1))]
1218 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1219 addr = gen_lowpart (Pmode, addr);
1220 s390_load_address (addr, XEXP (operands[1], 0));
1221 operands[1] = replace_equiv_address (operands[1], addr);
1226 ; Patterns used for secondary reloads
1229 ; z10 provides move instructions accepting larl memory operands.
1230 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1231 ; These patterns are also used for unaligned SI and DI accesses.
1233 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1234 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1235 (match_operand:INTALL 1 "register_operand" "=d")
1236 (match_operand:P 2 "register_operand" "=&a")])]
1239 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1243 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1244 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1245 (match_operand:INTALL 1 "memory_operand" "")
1246 (match_operand:P 2 "register_operand" "=a")])]
1249 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1253 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1254 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1255 (match_operand:FPALL 1 "register_operand" "=d")
1256 (match_operand:P 2 "register_operand" "=&a")])]
1259 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1263 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1264 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1265 (match_operand:FPALL 1 "memory_operand" "")
1266 (match_operand:P 2 "register_operand" "=a")])]
1269 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1273 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1274 [(parallel [(match_operand:P 0 "register_operand" "=d")
1275 (match_operand:P 1 "larl_operand" "")
1276 (match_operand:P 2 "register_operand" "=a")])]
1279 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1283 ; Handles loading a PLUS (load address) expression
1285 (define_expand "reload<mode>_plus"
1286 [(parallel [(match_operand:P 0 "register_operand" "=a")
1287 (match_operand:P 1 "s390_plus_operand" "")
1288 (match_operand:P 2 "register_operand" "=&a")])]
1291 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1295 ; Handles assessing a non-offsetable memory address
1297 (define_expand "reload<mode>_nonoffmem_in"
1298 [(parallel [(match_operand 0 "register_operand" "")
1299 (match_operand 1 "" "")
1300 (match_operand:P 2 "register_operand" "=&a")])]
1303 gcc_assert (MEM_P (operands[1]));
1304 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1305 operands[1] = replace_equiv_address (operands[1], operands[2]);
1306 emit_move_insn (operands[0], operands[1]);
1310 (define_expand "reload<mode>_nonoffmem_out"
1311 [(parallel [(match_operand 0 "" "")
1312 (match_operand 1 "register_operand" "")
1313 (match_operand:P 2 "register_operand" "=&a")])]
1316 gcc_assert (MEM_P (operands[0]));
1317 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1318 operands[0] = replace_equiv_address (operands[0], operands[2]);
1319 emit_move_insn (operands[0], operands[1]);
1323 (define_expand "reload<mode>_PIC_addr"
1324 [(parallel [(match_operand 0 "register_operand" "=d")
1325 (match_operand 1 "larl_operand" "")
1326 (match_operand:P 2 "register_operand" "=a")])]
1329 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1330 emit_move_insn (operands[0], new_rtx);
1334 ; movdi instruction pattern(s).
1337 (define_expand "movdi"
1338 [(set (match_operand:DI 0 "general_operand" "")
1339 (match_operand:DI 1 "general_operand" ""))]
1342 /* Handle symbolic constants. */
1344 && (SYMBOLIC_CONST (operands[1])
1345 || (GET_CODE (operands[1]) == PLUS
1346 && XEXP (operands[1], 0) == pic_offset_table_rtx
1347 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1348 emit_symbolic_move (operands);
1351 (define_insn "*movdi_larl"
1352 [(set (match_operand:DI 0 "register_operand" "=d")
1353 (match_operand:DI 1 "larl_operand" "X"))]
1355 && !FP_REG_P (operands[0])"
1357 [(set_attr "op_type" "RIL")
1358 (set_attr "type" "larl")
1359 (set_attr "z10prop" "z10_super_A1")])
1361 (define_insn "*movdi_64"
1362 [(set (match_operand:DI 0 "nonimmediate_operand"
1363 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1364 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1365 (match_operand:DI 1 "general_operand"
1366 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1367 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1396 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1397 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1398 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1399 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1401 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1402 z10,*,*,*,*,*,longdisp,*,longdisp,
1404 (set_attr "z10prop" "z10_fwd_A1,
1433 [(set (match_operand:DI 0 "register_operand" "")
1434 (match_operand:DI 1 "register_operand" ""))]
1435 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1436 [(set (match_dup 2) (match_dup 3))
1437 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1438 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1439 "operands[2] = gen_lowpart (SImode, operands[0]);
1440 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1443 [(set (match_operand:DI 0 "register_operand" "")
1444 (match_operand:DI 1 "register_operand" ""))]
1445 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1446 && dead_or_set_p (insn, operands[1])"
1447 [(set (match_dup 3) (match_dup 2))
1448 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1449 (set (match_dup 4) (match_dup 2))]
1450 "operands[2] = gen_lowpart (SImode, operands[1]);
1451 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1454 [(set (match_operand:DI 0 "register_operand" "")
1455 (match_operand:DI 1 "register_operand" ""))]
1456 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1457 && !dead_or_set_p (insn, operands[1])"
1458 [(set (match_dup 3) (match_dup 2))
1459 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1460 (set (match_dup 4) (match_dup 2))
1461 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1462 "operands[2] = gen_lowpart (SImode, operands[1]);
1463 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1465 (define_insn "*movdi_31"
1466 [(set (match_operand:DI 0 "nonimmediate_operand"
1467 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1468 (match_operand:DI 1 "general_operand"
1469 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1484 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1485 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1486 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1488 ; For a load from a symbol ref we can use one of the target registers
1489 ; together with larl to load the address.
1491 [(set (match_operand:DI 0 "register_operand" "")
1492 (match_operand:DI 1 "memory_operand" ""))]
1493 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1494 && larl_operand (XEXP (operands[1], 0), SImode)"
1495 [(set (match_dup 2) (match_dup 3))
1496 (set (match_dup 0) (match_dup 1))]
1498 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1499 operands[3] = XEXP (operands[1], 0);
1500 operands[1] = replace_equiv_address (operands[1], operands[2]);
1504 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1505 (match_operand:DI 1 "general_operand" ""))]
1506 "!TARGET_ZARCH && reload_completed
1507 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1508 [(set (match_dup 2) (match_dup 4))
1509 (set (match_dup 3) (match_dup 5))]
1511 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1512 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1513 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1514 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1518 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1519 (match_operand:DI 1 "general_operand" ""))]
1520 "!TARGET_ZARCH && reload_completed
1521 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1522 [(set (match_dup 2) (match_dup 4))
1523 (set (match_dup 3) (match_dup 5))]
1525 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1526 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1527 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1528 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1532 [(set (match_operand:DI 0 "register_operand" "")
1533 (match_operand:DI 1 "memory_operand" ""))]
1534 "!TARGET_ZARCH && reload_completed
1535 && !FP_REG_P (operands[0])
1536 && !s_operand (operands[1], VOIDmode)"
1537 [(set (match_dup 0) (match_dup 1))]
1539 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1540 s390_load_address (addr, XEXP (operands[1], 0));
1541 operands[1] = replace_equiv_address (operands[1], addr);
1545 [(set (match_operand:DI 0 "register_operand" "")
1546 (mem:DI (match_operand 1 "address_operand" "")))]
1548 && !FP_REG_P (operands[0])
1549 && GET_CODE (operands[1]) == SYMBOL_REF
1550 && CONSTANT_POOL_ADDRESS_P (operands[1])
1551 && get_pool_mode (operands[1]) == DImode
1552 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1553 [(set (match_dup 0) (match_dup 2))]
1554 "operands[2] = get_pool_constant (operands[1]);")
1556 (define_insn "*la_64"
1557 [(set (match_operand:DI 0 "register_operand" "=d,d")
1558 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1563 [(set_attr "op_type" "RX,RXY")
1564 (set_attr "type" "la")
1565 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1569 [(set (match_operand:DI 0 "register_operand" "")
1570 (match_operand:QI 1 "address_operand" ""))
1571 (clobber (reg:CC CC_REGNUM))])]
1573 && preferred_la_operand_p (operands[1], const0_rtx)"
1574 [(set (match_dup 0) (match_dup 1))]
1578 [(set (match_operand:DI 0 "register_operand" "")
1579 (match_operand:DI 1 "register_operand" ""))
1582 (plus:DI (match_dup 0)
1583 (match_operand:DI 2 "nonmemory_operand" "")))
1584 (clobber (reg:CC CC_REGNUM))])]
1586 && !reg_overlap_mentioned_p (operands[0], operands[2])
1587 && preferred_la_operand_p (operands[1], operands[2])"
1588 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1592 ; movsi instruction pattern(s).
1595 (define_expand "movsi"
1596 [(set (match_operand:SI 0 "general_operand" "")
1597 (match_operand:SI 1 "general_operand" ""))]
1600 /* Handle symbolic constants. */
1602 && (SYMBOLIC_CONST (operands[1])
1603 || (GET_CODE (operands[1]) == PLUS
1604 && XEXP (operands[1], 0) == pic_offset_table_rtx
1605 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1606 emit_symbolic_move (operands);
1609 (define_insn "*movsi_larl"
1610 [(set (match_operand:SI 0 "register_operand" "=d")
1611 (match_operand:SI 1 "larl_operand" "X"))]
1612 "!TARGET_64BIT && TARGET_CPU_ZARCH
1613 && !FP_REG_P (operands[0])"
1615 [(set_attr "op_type" "RIL")
1616 (set_attr "type" "larl")
1617 (set_attr "z10prop" "z10_fwd_A1")])
1619 (define_insn "*movsi_zarch"
1620 [(set (match_operand:SI 0 "nonimmediate_operand"
1621 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1622 (match_operand:SI 1 "general_operand"
1623 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1648 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1649 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1650 (set_attr "type" "*,
1672 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1673 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1674 (set_attr "z10prop" "z10_fwd_A1,
1697 (define_insn "*movsi_esa"
1698 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1699 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1713 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1714 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1715 (set_attr "z10prop" "z10_fwd_A1,
1729 [(set (match_operand:SI 0 "register_operand" "")
1730 (mem:SI (match_operand 1 "address_operand" "")))]
1731 "!FP_REG_P (operands[0])
1732 && GET_CODE (operands[1]) == SYMBOL_REF
1733 && CONSTANT_POOL_ADDRESS_P (operands[1])
1734 && get_pool_mode (operands[1]) == SImode
1735 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1736 [(set (match_dup 0) (match_dup 2))]
1737 "operands[2] = get_pool_constant (operands[1]);")
1739 (define_insn "*la_31"
1740 [(set (match_operand:SI 0 "register_operand" "=d,d")
1741 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1742 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1746 [(set_attr "op_type" "RX,RXY")
1747 (set_attr "type" "la")
1748 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1752 [(set (match_operand:SI 0 "register_operand" "")
1753 (match_operand:QI 1 "address_operand" ""))
1754 (clobber (reg:CC CC_REGNUM))])]
1756 && preferred_la_operand_p (operands[1], const0_rtx)"
1757 [(set (match_dup 0) (match_dup 1))]
1761 [(set (match_operand:SI 0 "register_operand" "")
1762 (match_operand:SI 1 "register_operand" ""))
1765 (plus:SI (match_dup 0)
1766 (match_operand:SI 2 "nonmemory_operand" "")))
1767 (clobber (reg:CC CC_REGNUM))])]
1769 && !reg_overlap_mentioned_p (operands[0], operands[2])
1770 && preferred_la_operand_p (operands[1], operands[2])"
1771 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1774 (define_insn "*la_31_and"
1775 [(set (match_operand:SI 0 "register_operand" "=d,d")
1776 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1777 (const_int 2147483647)))]
1782 [(set_attr "op_type" "RX,RXY")
1783 (set_attr "type" "la")
1784 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1786 (define_insn_and_split "*la_31_and_cc"
1787 [(set (match_operand:SI 0 "register_operand" "=d")
1788 (and:SI (match_operand:QI 1 "address_operand" "p")
1789 (const_int 2147483647)))
1790 (clobber (reg:CC CC_REGNUM))]
1793 "&& reload_completed"
1795 (and:SI (match_dup 1) (const_int 2147483647)))]
1797 [(set_attr "op_type" "RX")
1798 (set_attr "type" "la")])
1800 (define_insn "force_la_31"
1801 [(set (match_operand:SI 0 "register_operand" "=d,d")
1802 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1803 (use (const_int 0))]
1808 [(set_attr "op_type" "RX")
1809 (set_attr "type" "la")
1810 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1813 ; movhi instruction pattern(s).
1816 (define_expand "movhi"
1817 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1818 (match_operand:HI 1 "general_operand" ""))]
1821 /* Make it explicit that loading a register from memory
1822 always sign-extends (at least) to SImode. */
1823 if (optimize && can_create_pseudo_p ()
1824 && register_operand (operands[0], VOIDmode)
1825 && GET_CODE (operands[1]) == MEM)
1827 rtx tmp = gen_reg_rtx (SImode);
1828 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1829 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1830 operands[1] = gen_lowpart (HImode, tmp);
1834 (define_insn "*movhi"
1835 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1836 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1848 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1849 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1850 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1851 (set_attr "z10prop" "z10_fr_E1,
1862 [(set (match_operand:HI 0 "register_operand" "")
1863 (mem:HI (match_operand 1 "address_operand" "")))]
1864 "GET_CODE (operands[1]) == SYMBOL_REF
1865 && CONSTANT_POOL_ADDRESS_P (operands[1])
1866 && get_pool_mode (operands[1]) == HImode
1867 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1868 [(set (match_dup 0) (match_dup 2))]
1869 "operands[2] = get_pool_constant (operands[1]);")
1872 ; movqi instruction pattern(s).
1875 (define_expand "movqi"
1876 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1877 (match_operand:QI 1 "general_operand" ""))]
1880 /* On z/Architecture, zero-extending from memory to register
1881 is just as fast as a QImode load. */
1882 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1883 && register_operand (operands[0], VOIDmode)
1884 && GET_CODE (operands[1]) == MEM)
1886 rtx tmp = gen_reg_rtx (DImode);
1887 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1888 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1889 operands[1] = gen_lowpart (QImode, tmp);
1893 (define_insn "*movqi"
1894 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1895 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1907 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1908 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1909 (set_attr "z10prop" "z10_fr_E1,
1920 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1921 (mem:QI (match_operand 1 "address_operand" "")))]
1922 "GET_CODE (operands[1]) == SYMBOL_REF
1923 && CONSTANT_POOL_ADDRESS_P (operands[1])
1924 && get_pool_mode (operands[1]) == QImode
1925 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1926 [(set (match_dup 0) (match_dup 2))]
1927 "operands[2] = get_pool_constant (operands[1]);")
1930 ; movstrictqi instruction pattern(s).
1933 (define_insn "*movstrictqi"
1934 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1935 (match_operand:QI 1 "memory_operand" "R,T"))]
1940 [(set_attr "op_type" "RX,RXY")
1941 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1944 ; movstricthi instruction pattern(s).
1947 (define_insn "*movstricthi"
1948 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1949 (match_operand:HI 1 "memory_operand" "Q,S"))
1950 (clobber (reg:CC CC_REGNUM))]
1955 [(set_attr "op_type" "RS,RSY")
1956 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1959 ; movstrictsi instruction pattern(s).
1962 (define_insn "movstrictsi"
1963 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1964 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1971 [(set_attr "op_type" "RR,RX,RXY,RRE")
1972 (set_attr "type" "lr,load,load,*")
1973 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1976 ; mov(tf|td) instruction pattern(s).
1979 (define_expand "mov<mode>"
1980 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1981 (match_operand:TD_TF 1 "general_operand" ""))]
1985 (define_insn "*mov<mode>_64"
1986 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1987 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1998 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1999 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2000 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2002 (define_insn "*mov<mode>_31"
2003 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2004 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2011 [(set_attr "op_type" "RRE,RRE,*,*")
2012 (set_attr "type" "fsimptf,fsimptf,*,*")
2013 (set_attr "cpu_facility" "z196,*,*,*")])
2015 ; TFmode in GPRs splitters
2018 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2019 (match_operand:TD_TF 1 "general_operand" ""))]
2020 "TARGET_ZARCH && reload_completed
2021 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2022 [(set (match_dup 2) (match_dup 4))
2023 (set (match_dup 3) (match_dup 5))]
2025 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2026 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2027 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2028 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2032 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2033 (match_operand:TD_TF 1 "general_operand" ""))]
2034 "TARGET_ZARCH && reload_completed
2035 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2036 [(set (match_dup 2) (match_dup 4))
2037 (set (match_dup 3) (match_dup 5))]
2039 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2040 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2041 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2042 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2046 [(set (match_operand:TD_TF 0 "register_operand" "")
2047 (match_operand:TD_TF 1 "memory_operand" ""))]
2048 "TARGET_ZARCH && reload_completed
2049 && !FP_REG_P (operands[0])
2050 && !s_operand (operands[1], VOIDmode)"
2051 [(set (match_dup 0) (match_dup 1))]
2053 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2054 addr = gen_lowpart (Pmode, addr);
2055 s390_load_address (addr, XEXP (operands[1], 0));
2056 operands[1] = replace_equiv_address (operands[1], addr);
2059 ; TFmode in BFPs splitters
2062 [(set (match_operand:TD_TF 0 "register_operand" "")
2063 (match_operand:TD_TF 1 "memory_operand" ""))]
2064 "reload_completed && offsettable_memref_p (operands[1])
2065 && FP_REG_P (operands[0])"
2066 [(set (match_dup 2) (match_dup 4))
2067 (set (match_dup 3) (match_dup 5))]
2069 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2071 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2073 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2074 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2078 [(set (match_operand:TD_TF 0 "memory_operand" "")
2079 (match_operand:TD_TF 1 "register_operand" ""))]
2080 "reload_completed && offsettable_memref_p (operands[0])
2081 && FP_REG_P (operands[1])"
2082 [(set (match_dup 2) (match_dup 4))
2083 (set (match_dup 3) (match_dup 5))]
2085 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2086 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2087 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2089 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2094 ; mov(df|dd) instruction pattern(s).
2097 (define_expand "mov<mode>"
2098 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2099 (match_operand:DD_DF 1 "general_operand" ""))]
2103 (define_insn "*mov<mode>_64dfp"
2104 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2105 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2106 (match_operand:DD_DF 1 "general_operand"
2107 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2122 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2123 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2124 fstoredf,fstoredf,*,lr,load,store")
2125 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2126 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2128 (define_insn "*mov<mode>_64"
2129 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2130 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2143 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2144 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2145 fstore<mode>,fstore<mode>,*,lr,load,store")
2146 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2147 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2149 (define_insn "*mov<mode>_31"
2150 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2151 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2152 (match_operand:DD_DF 1 "general_operand"
2153 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2168 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2169 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2170 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2171 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2174 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2175 (match_operand:DD_DF 1 "general_operand" ""))]
2176 "!TARGET_ZARCH && reload_completed
2177 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2178 [(set (match_dup 2) (match_dup 4))
2179 (set (match_dup 3) (match_dup 5))]
2181 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2182 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2183 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2184 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2188 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2189 (match_operand:DD_DF 1 "general_operand" ""))]
2190 "!TARGET_ZARCH && reload_completed
2191 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2192 [(set (match_dup 2) (match_dup 4))
2193 (set (match_dup 3) (match_dup 5))]
2195 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2196 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2197 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2198 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2202 [(set (match_operand:DD_DF 0 "register_operand" "")
2203 (match_operand:DD_DF 1 "memory_operand" ""))]
2204 "!TARGET_ZARCH && reload_completed
2205 && !FP_REG_P (operands[0])
2206 && !s_operand (operands[1], VOIDmode)"
2207 [(set (match_dup 0) (match_dup 1))]
2209 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2210 s390_load_address (addr, XEXP (operands[1], 0));
2211 operands[1] = replace_equiv_address (operands[1], addr);
2215 ; mov(sf|sd) instruction pattern(s).
2218 (define_insn "mov<mode>"
2219 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2220 "=f,f,f,f,R,T,d,d,d,d,R,T")
2221 (match_operand:SD_SF 1 "general_operand"
2222 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2237 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2238 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2239 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2240 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2241 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2244 ; movcc instruction pattern
2247 (define_insn "movcc"
2248 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2249 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2259 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2260 (set_attr "type" "lr,*,*,store,store,load,load")
2261 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2262 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2265 ; Block move (MVC) patterns.
2269 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2270 (match_operand:BLK 1 "memory_operand" "Q"))
2271 (use (match_operand 2 "const_int_operand" "n"))]
2272 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2273 "mvc\t%O0(%2,%R0),%S1"
2274 [(set_attr "op_type" "SS")])
2276 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2277 ; order to have it implemented with mvc.
2280 [(set (match_operand:QI 0 "memory_operand" "")
2281 (match_operand:QI 1 "memory_operand" ""))]
2284 [(set (match_dup 0) (match_dup 1))
2285 (use (const_int 1))])]
2287 operands[0] = adjust_address (operands[0], BLKmode, 0);
2288 operands[1] = adjust_address (operands[1], BLKmode, 0);
2294 [(set (match_operand:BLK 0 "memory_operand" "")
2295 (match_operand:BLK 1 "memory_operand" ""))
2296 (use (match_operand 2 "const_int_operand" ""))])
2298 [(set (match_operand:BLK 3 "memory_operand" "")
2299 (match_operand:BLK 4 "memory_operand" ""))
2300 (use (match_operand 5 "const_int_operand" ""))])]
2301 "s390_offset_p (operands[0], operands[3], operands[2])
2302 && s390_offset_p (operands[1], operands[4], operands[2])
2303 && !s390_overlap_p (operands[0], operands[1],
2304 INTVAL (operands[2]) + INTVAL (operands[5]))
2305 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2307 [(set (match_dup 6) (match_dup 7))
2308 (use (match_dup 8))])]
2309 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2310 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2311 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2315 ; load_multiple pattern(s).
2317 ; ??? Due to reload problems with replacing registers inside match_parallel
2318 ; we currently support load_multiple/store_multiple only after reload.
2321 (define_expand "load_multiple"
2322 [(match_par_dup 3 [(set (match_operand 0 "" "")
2323 (match_operand 1 "" ""))
2324 (use (match_operand 2 "" ""))])]
2327 enum machine_mode mode;
2333 /* Support only loading a constant number of fixed-point registers from
2334 memory and only bother with this if more than two */
2335 if (GET_CODE (operands[2]) != CONST_INT
2336 || INTVAL (operands[2]) < 2
2337 || INTVAL (operands[2]) > 16
2338 || GET_CODE (operands[1]) != MEM
2339 || GET_CODE (operands[0]) != REG
2340 || REGNO (operands[0]) >= 16)
2343 count = INTVAL (operands[2]);
2344 regno = REGNO (operands[0]);
2345 mode = GET_MODE (operands[0]);
2346 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2349 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2350 if (!can_create_pseudo_p ())
2352 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2354 from = XEXP (operands[1], 0);
2357 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2358 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2359 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2361 from = XEXP (XEXP (operands[1], 0), 0);
2362 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2369 from = force_reg (Pmode, XEXP (operands[1], 0));
2373 for (i = 0; i < count; i++)
2374 XVECEXP (operands[3], 0, i)
2375 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2376 change_address (operands[1], mode,
2377 plus_constant (Pmode, from,
2378 off + i * GET_MODE_SIZE (mode))));
2381 (define_insn "*load_multiple_di"
2382 [(match_parallel 0 "load_multiple_operation"
2383 [(set (match_operand:DI 1 "register_operand" "=r")
2384 (match_operand:DI 2 "s_operand" "QS"))])]
2385 "reload_completed && TARGET_ZARCH"
2387 int words = XVECLEN (operands[0], 0);
2388 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2389 return "lmg\t%1,%0,%S2";
2391 [(set_attr "op_type" "RSY")
2392 (set_attr "type" "lm")])
2394 (define_insn "*load_multiple_si"
2395 [(match_parallel 0 "load_multiple_operation"
2396 [(set (match_operand:SI 1 "register_operand" "=r,r")
2397 (match_operand:SI 2 "s_operand" "Q,S"))])]
2400 int words = XVECLEN (operands[0], 0);
2401 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2402 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2404 [(set_attr "op_type" "RS,RSY")
2405 (set_attr "type" "lm")])
2408 ; store multiple pattern(s).
2411 (define_expand "store_multiple"
2412 [(match_par_dup 3 [(set (match_operand 0 "" "")
2413 (match_operand 1 "" ""))
2414 (use (match_operand 2 "" ""))])]
2417 enum machine_mode mode;
2423 /* Support only storing a constant number of fixed-point registers to
2424 memory and only bother with this if more than two. */
2425 if (GET_CODE (operands[2]) != CONST_INT
2426 || INTVAL (operands[2]) < 2
2427 || INTVAL (operands[2]) > 16
2428 || GET_CODE (operands[0]) != MEM
2429 || GET_CODE (operands[1]) != REG
2430 || REGNO (operands[1]) >= 16)
2433 count = INTVAL (operands[2]);
2434 regno = REGNO (operands[1]);
2435 mode = GET_MODE (operands[1]);
2436 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2439 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2441 if (!can_create_pseudo_p ())
2443 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2445 to = XEXP (operands[0], 0);
2448 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2449 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2450 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2452 to = XEXP (XEXP (operands[0], 0), 0);
2453 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2460 to = force_reg (Pmode, XEXP (operands[0], 0));
2464 for (i = 0; i < count; i++)
2465 XVECEXP (operands[3], 0, i)
2466 = gen_rtx_SET (VOIDmode,
2467 change_address (operands[0], mode,
2468 plus_constant (Pmode, to,
2469 off + i * GET_MODE_SIZE (mode))),
2470 gen_rtx_REG (mode, regno + i));
2473 (define_insn "*store_multiple_di"
2474 [(match_parallel 0 "store_multiple_operation"
2475 [(set (match_operand:DI 1 "s_operand" "=QS")
2476 (match_operand:DI 2 "register_operand" "r"))])]
2477 "reload_completed && TARGET_ZARCH"
2479 int words = XVECLEN (operands[0], 0);
2480 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2481 return "stmg\t%2,%0,%S1";
2483 [(set_attr "op_type" "RSY")
2484 (set_attr "type" "stm")])
2487 (define_insn "*store_multiple_si"
2488 [(match_parallel 0 "store_multiple_operation"
2489 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2490 (match_operand:SI 2 "register_operand" "r,r"))])]
2493 int words = XVECLEN (operands[0], 0);
2494 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2495 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2497 [(set_attr "op_type" "RS,RSY")
2498 (set_attr "type" "stm")])
2501 ;; String instructions.
2504 (define_insn "*execute_rl"
2505 [(match_parallel 0 "execute_operation"
2506 [(unspec [(match_operand 1 "register_operand" "a")
2507 (match_operand 2 "" "")
2508 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2509 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2510 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2512 [(set_attr "op_type" "RIL")
2513 (set_attr "type" "cs")])
2515 (define_insn "*execute"
2516 [(match_parallel 0 "execute_operation"
2517 [(unspec [(match_operand 1 "register_operand" "a")
2518 (match_operand:BLK 2 "memory_operand" "R")
2519 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2520 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2521 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2523 [(set_attr "op_type" "RX")
2524 (set_attr "type" "cs")])
2528 ; strlenM instruction pattern(s).
2531 (define_expand "strlen<mode>"
2532 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2535 (unspec:P [(const_int 0)
2536 (match_operand:BLK 1 "memory_operand" "")
2538 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2539 (clobber (scratch:P))
2540 (clobber (reg:CC CC_REGNUM))])
2542 [(set (match_operand:P 0 "register_operand" "")
2543 (minus:P (match_dup 4) (match_dup 5)))
2544 (clobber (reg:CC CC_REGNUM))])]
2547 operands[4] = gen_reg_rtx (Pmode);
2548 operands[5] = gen_reg_rtx (Pmode);
2549 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2550 operands[1] = replace_equiv_address (operands[1], operands[5]);
2553 (define_insn "*strlen<mode>"
2554 [(set (match_operand:P 0 "register_operand" "=a")
2555 (unspec:P [(match_operand:P 2 "general_operand" "0")
2556 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2558 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2559 (clobber (match_scratch:P 1 "=a"))
2560 (clobber (reg:CC CC_REGNUM))]
2562 "srst\t%0,%1\;jo\t.-4"
2563 [(set_attr "length" "8")
2564 (set_attr "type" "vs")])
2567 ; cmpstrM instruction pattern(s).
2570 (define_expand "cmpstrsi"
2571 [(set (reg:SI 0) (const_int 0))
2573 [(clobber (match_operand 3 "" ""))
2574 (clobber (match_dup 4))
2575 (set (reg:CCU CC_REGNUM)
2576 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2577 (match_operand:BLK 2 "memory_operand" "")))
2580 [(set (match_operand:SI 0 "register_operand" "=d")
2581 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2582 (clobber (reg:CC CC_REGNUM))])]
2585 /* As the result of CMPINT is inverted compared to what we need,
2586 we have to swap the operands. */
2587 rtx op1 = operands[2];
2588 rtx op2 = operands[1];
2589 rtx addr1 = gen_reg_rtx (Pmode);
2590 rtx addr2 = gen_reg_rtx (Pmode);
2592 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2593 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2594 operands[1] = replace_equiv_address_nv (op1, addr1);
2595 operands[2] = replace_equiv_address_nv (op2, addr2);
2596 operands[3] = addr1;
2597 operands[4] = addr2;
2600 (define_insn "*cmpstr<mode>"
2601 [(clobber (match_operand:P 0 "register_operand" "=d"))
2602 (clobber (match_operand:P 1 "register_operand" "=d"))
2603 (set (reg:CCU CC_REGNUM)
2604 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2605 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2608 "clst\t%0,%1\;jo\t.-4"
2609 [(set_attr "length" "8")
2610 (set_attr "type" "vs")])
2613 ; movstr instruction pattern.
2616 (define_expand "movstr"
2617 [(set (reg:SI 0) (const_int 0))
2619 [(clobber (match_dup 3))
2620 (set (match_operand:BLK 1 "memory_operand" "")
2621 (match_operand:BLK 2 "memory_operand" ""))
2622 (set (match_operand 0 "register_operand" "")
2623 (unspec [(match_dup 1)
2625 (reg:SI 0)] UNSPEC_MVST))
2626 (clobber (reg:CC CC_REGNUM))])]
2629 rtx addr1 = gen_reg_rtx (Pmode);
2630 rtx addr2 = gen_reg_rtx (Pmode);
2632 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2633 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2634 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2635 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2636 operands[3] = addr2;
2639 (define_insn "*movstr"
2640 [(clobber (match_operand:P 2 "register_operand" "=d"))
2641 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2642 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2643 (set (match_operand:P 0 "register_operand" "=d")
2644 (unspec [(mem:BLK (match_dup 1))
2645 (mem:BLK (match_dup 3))
2646 (reg:SI 0)] UNSPEC_MVST))
2647 (clobber (reg:CC CC_REGNUM))]
2649 "mvst\t%1,%2\;jo\t.-4"
2650 [(set_attr "length" "8")
2651 (set_attr "type" "vs")])
2655 ; movmemM instruction pattern(s).
2658 (define_expand "movmem<mode>"
2659 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2660 (match_operand:BLK 1 "memory_operand" "")) ; source
2661 (use (match_operand:GPR 2 "general_operand" "")) ; count
2662 (match_operand 3 "" "")]
2665 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2671 ; Move a block that is up to 256 bytes in length.
2672 ; The block length is taken as (operands[2] % 256) + 1.
2674 (define_expand "movmem_short"
2676 [(set (match_operand:BLK 0 "memory_operand" "")
2677 (match_operand:BLK 1 "memory_operand" ""))
2678 (use (match_operand 2 "nonmemory_operand" ""))
2679 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2680 (clobber (match_dup 3))])]
2682 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2684 (define_insn "*movmem_short"
2685 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2686 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2687 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2688 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2689 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2690 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2692 [(set_attr "type" "cs")
2693 (set_attr "cpu_facility" "*,*,z10,zarch")])
2696 [(set (match_operand:BLK 0 "memory_operand" "")
2697 (match_operand:BLK 1 "memory_operand" ""))
2698 (use (match_operand 2 "const_int_operand" ""))
2699 (use (match_operand 3 "immediate_operand" ""))
2700 (clobber (scratch))]
2703 [(set (match_dup 0) (match_dup 1))
2704 (use (match_dup 2))])]
2705 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2708 [(set (match_operand:BLK 0 "memory_operand" "")
2709 (match_operand:BLK 1 "memory_operand" ""))
2710 (use (match_operand 2 "register_operand" ""))
2711 (use (match_operand 3 "memory_operand" ""))
2712 (clobber (scratch))]
2715 [(unspec [(match_dup 2) (match_dup 3)
2716 (const_int 0)] UNSPEC_EXECUTE)
2717 (set (match_dup 0) (match_dup 1))
2718 (use (const_int 1))])]
2722 [(set (match_operand:BLK 0 "memory_operand" "")
2723 (match_operand:BLK 1 "memory_operand" ""))
2724 (use (match_operand 2 "register_operand" ""))
2725 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2726 (clobber (scratch))]
2727 "TARGET_Z10 && reload_completed"
2729 [(unspec [(match_dup 2) (const_int 0)
2730 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2731 (set (match_dup 0) (match_dup 1))
2732 (use (const_int 1))])]
2733 "operands[3] = gen_label_rtx ();")
2736 [(set (match_operand:BLK 0 "memory_operand" "")
2737 (match_operand:BLK 1 "memory_operand" ""))
2738 (use (match_operand 2 "register_operand" ""))
2739 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2740 (clobber (match_operand 3 "register_operand" ""))]
2741 "reload_completed && TARGET_CPU_ZARCH"
2742 [(set (match_dup 3) (label_ref (match_dup 4)))
2744 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2745 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2746 (set (match_dup 0) (match_dup 1))
2747 (use (const_int 1))])]
2748 "operands[4] = gen_label_rtx ();")
2750 ; Move a block of arbitrary length.
2752 (define_expand "movmem_long"
2754 [(clobber (match_dup 2))
2755 (clobber (match_dup 3))
2756 (set (match_operand:BLK 0 "memory_operand" "")
2757 (match_operand:BLK 1 "memory_operand" ""))
2758 (use (match_operand 2 "general_operand" ""))
2760 (clobber (reg:CC CC_REGNUM))])]
2763 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2764 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2765 rtx reg0 = gen_reg_rtx (dreg_mode);
2766 rtx reg1 = gen_reg_rtx (dreg_mode);
2767 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2768 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2769 rtx len0 = gen_lowpart (Pmode, reg0);
2770 rtx len1 = gen_lowpart (Pmode, reg1);
2772 emit_clobber (reg0);
2773 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2774 emit_move_insn (len0, operands[2]);
2776 emit_clobber (reg1);
2777 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2778 emit_move_insn (len1, operands[2]);
2780 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2781 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2786 (define_insn "*movmem_long"
2787 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2788 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2789 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2790 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2793 (clobber (reg:CC CC_REGNUM))]
2794 "TARGET_64BIT || !TARGET_ZARCH"
2795 "mvcle\t%0,%1,0\;jo\t.-4"
2796 [(set_attr "length" "8")
2797 (set_attr "type" "vs")])
2799 (define_insn "*movmem_long_31z"
2800 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2801 (clobber (match_operand:TI 1 "register_operand" "=d"))
2802 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2803 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2806 (clobber (reg:CC CC_REGNUM))]
2807 "!TARGET_64BIT && TARGET_ZARCH"
2808 "mvcle\t%0,%1,0\;jo\t.-4"
2809 [(set_attr "length" "8")
2810 (set_attr "type" "vs")])
2817 (define_expand "signbit<mode>2"
2818 [(set (reg:CCZ CC_REGNUM)
2819 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2822 (set (match_operand:SI 0 "register_operand" "=d")
2823 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2826 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2829 (define_expand "isinf<mode>2"
2830 [(set (reg:CCZ CC_REGNUM)
2831 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2834 (set (match_operand:SI 0 "register_operand" "=d")
2835 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2838 operands[2] = GEN_INT (S390_TDC_INFINITY);
2841 ; This insn is used to generate all variants of the Test Data Class
2842 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2843 ; is the register to be tested and the second one is the bit mask
2844 ; specifying the required test(s).
2846 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2847 (define_insn "*TDC_insn_<mode>"
2848 [(set (reg:CCZ CC_REGNUM)
2849 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2850 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2852 "t<_d>c<xde><bt>\t%0,%1"
2853 [(set_attr "op_type" "RXE")
2854 (set_attr "type" "fsimp<mode>")])
2856 (define_insn_and_split "*ccz_to_int"
2857 [(set (match_operand:SI 0 "register_operand" "=d")
2858 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2859 UNSPEC_CCZ_TO_INT))]
2863 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2867 ; setmemM instruction pattern(s).
2870 (define_expand "setmem<mode>"
2871 [(set (match_operand:BLK 0 "memory_operand" "")
2872 (match_operand:QI 2 "general_operand" ""))
2873 (use (match_operand:GPR 1 "general_operand" ""))
2874 (match_operand 3 "" "")]
2876 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2878 ; Clear a block that is up to 256 bytes in length.
2879 ; The block length is taken as (operands[1] % 256) + 1.
2881 (define_expand "clrmem_short"
2883 [(set (match_operand:BLK 0 "memory_operand" "")
2885 (use (match_operand 1 "nonmemory_operand" ""))
2886 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2887 (clobber (match_dup 2))
2888 (clobber (reg:CC CC_REGNUM))])]
2890 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2892 (define_insn "*clrmem_short"
2893 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2895 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2896 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2897 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2898 (clobber (reg:CC CC_REGNUM))]
2899 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2901 [(set_attr "type" "cs")
2902 (set_attr "cpu_facility" "*,*,z10,zarch")])
2905 [(set (match_operand:BLK 0 "memory_operand" "")
2907 (use (match_operand 1 "const_int_operand" ""))
2908 (use (match_operand 2 "immediate_operand" ""))
2910 (clobber (reg:CC CC_REGNUM))]
2913 [(set (match_dup 0) (const_int 0))
2915 (clobber (reg:CC CC_REGNUM))])]
2916 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2919 [(set (match_operand:BLK 0 "memory_operand" "")
2921 (use (match_operand 1 "register_operand" ""))
2922 (use (match_operand 2 "memory_operand" ""))
2924 (clobber (reg:CC CC_REGNUM))]
2927 [(unspec [(match_dup 1) (match_dup 2)
2928 (const_int 0)] UNSPEC_EXECUTE)
2929 (set (match_dup 0) (const_int 0))
2931 (clobber (reg:CC CC_REGNUM))])]
2935 [(set (match_operand:BLK 0 "memory_operand" "")
2937 (use (match_operand 1 "register_operand" ""))
2938 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2940 (clobber (reg:CC CC_REGNUM))]
2941 "TARGET_Z10 && reload_completed"
2943 [(unspec [(match_dup 1) (const_int 0)
2944 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2945 (set (match_dup 0) (const_int 0))
2947 (clobber (reg:CC CC_REGNUM))])]
2948 "operands[3] = gen_label_rtx ();")
2951 [(set (match_operand:BLK 0 "memory_operand" "")
2953 (use (match_operand 1 "register_operand" ""))
2954 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2955 (clobber (match_operand 2 "register_operand" ""))
2956 (clobber (reg:CC CC_REGNUM))]
2957 "reload_completed && TARGET_CPU_ZARCH"
2958 [(set (match_dup 2) (label_ref (match_dup 3)))
2960 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2961 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2962 (set (match_dup 0) (const_int 0))
2964 (clobber (reg:CC CC_REGNUM))])]
2965 "operands[3] = gen_label_rtx ();")
2967 ; Initialize a block of arbitrary length with (operands[2] % 256).
2969 (define_expand "setmem_long"
2971 [(clobber (match_dup 1))
2972 (set (match_operand:BLK 0 "memory_operand" "")
2973 (match_operand 2 "shift_count_or_setmem_operand" ""))
2974 (use (match_operand 1 "general_operand" ""))
2976 (clobber (reg:CC CC_REGNUM))])]
2979 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2980 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2981 rtx reg0 = gen_reg_rtx (dreg_mode);
2982 rtx reg1 = gen_reg_rtx (dreg_mode);
2983 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2984 rtx len0 = gen_lowpart (Pmode, reg0);
2986 emit_clobber (reg0);
2987 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2988 emit_move_insn (len0, operands[1]);
2990 emit_move_insn (reg1, const0_rtx);
2992 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2997 (define_insn "*setmem_long"
2998 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2999 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3000 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3002 (use (match_operand:<DBL> 1 "register_operand" "d"))
3003 (clobber (reg:CC CC_REGNUM))]
3004 "TARGET_64BIT || !TARGET_ZARCH"
3005 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3006 [(set_attr "length" "8")
3007 (set_attr "type" "vs")])
3009 (define_insn "*setmem_long_and"
3010 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3011 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3012 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3013 (match_operand 4 "const_int_operand" "n")))
3015 (use (match_operand:<DBL> 1 "register_operand" "d"))
3016 (clobber (reg:CC CC_REGNUM))]
3017 "(TARGET_64BIT || !TARGET_ZARCH) &&
3018 (INTVAL (operands[4]) & 255) == 255"
3019 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3020 [(set_attr "length" "8")
3021 (set_attr "type" "vs")])
3023 (define_insn "*setmem_long_31z"
3024 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3025 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3026 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3028 (use (match_operand:TI 1 "register_operand" "d"))
3029 (clobber (reg:CC CC_REGNUM))]
3030 "!TARGET_64BIT && TARGET_ZARCH"
3031 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3032 [(set_attr "length" "8")
3033 (set_attr "type" "vs")])
3036 ; cmpmemM instruction pattern(s).
3039 (define_expand "cmpmemsi"
3040 [(set (match_operand:SI 0 "register_operand" "")
3041 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3042 (match_operand:BLK 2 "memory_operand" "") ) )
3043 (use (match_operand:SI 3 "general_operand" ""))
3044 (use (match_operand:SI 4 "" ""))]
3047 if (s390_expand_cmpmem (operands[0], operands[1],
3048 operands[2], operands[3]))
3054 ; Compare a block that is up to 256 bytes in length.
3055 ; The block length is taken as (operands[2] % 256) + 1.
3057 (define_expand "cmpmem_short"
3059 [(set (reg:CCU CC_REGNUM)
3060 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3061 (match_operand:BLK 1 "memory_operand" "")))
3062 (use (match_operand 2 "nonmemory_operand" ""))
3063 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3064 (clobber (match_dup 3))])]
3066 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3068 (define_insn "*cmpmem_short"
3069 [(set (reg:CCU CC_REGNUM)
3070 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3071 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3072 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3073 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3074 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3075 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3077 [(set_attr "type" "cs")
3078 (set_attr "cpu_facility" "*,*,z10,zarch")])
3081 [(set (reg:CCU CC_REGNUM)
3082 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3083 (match_operand:BLK 1 "memory_operand" "")))
3084 (use (match_operand 2 "const_int_operand" ""))
3085 (use (match_operand 3 "immediate_operand" ""))
3086 (clobber (scratch))]
3089 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3090 (use (match_dup 2))])]
3091 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3094 [(set (reg:CCU CC_REGNUM)
3095 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3096 (match_operand:BLK 1 "memory_operand" "")))
3097 (use (match_operand 2 "register_operand" ""))
3098 (use (match_operand 3 "memory_operand" ""))
3099 (clobber (scratch))]
3102 [(unspec [(match_dup 2) (match_dup 3)
3103 (const_int 0)] UNSPEC_EXECUTE)
3104 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3105 (use (const_int 1))])]
3109 [(set (reg:CCU CC_REGNUM)
3110 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3111 (match_operand:BLK 1 "memory_operand" "")))
3112 (use (match_operand 2 "register_operand" ""))
3113 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3114 (clobber (scratch))]
3115 "TARGET_Z10 && reload_completed"
3117 [(unspec [(match_dup 2) (const_int 0)
3118 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3119 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3120 (use (const_int 1))])]
3121 "operands[4] = gen_label_rtx ();")
3124 [(set (reg:CCU CC_REGNUM)
3125 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3126 (match_operand:BLK 1 "memory_operand" "")))
3127 (use (match_operand 2 "register_operand" ""))
3128 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3129 (clobber (match_operand 3 "register_operand" ""))]
3130 "reload_completed && TARGET_CPU_ZARCH"
3131 [(set (match_dup 3) (label_ref (match_dup 4)))
3133 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3134 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3135 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3136 (use (const_int 1))])]
3137 "operands[4] = gen_label_rtx ();")
3139 ; Compare a block of arbitrary length.
3141 (define_expand "cmpmem_long"
3143 [(clobber (match_dup 2))
3144 (clobber (match_dup 3))
3145 (set (reg:CCU CC_REGNUM)
3146 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3147 (match_operand:BLK 1 "memory_operand" "")))
3148 (use (match_operand 2 "general_operand" ""))
3149 (use (match_dup 3))])]
3152 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3153 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3154 rtx reg0 = gen_reg_rtx (dreg_mode);
3155 rtx reg1 = gen_reg_rtx (dreg_mode);
3156 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3157 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3158 rtx len0 = gen_lowpart (Pmode, reg0);
3159 rtx len1 = gen_lowpart (Pmode, reg1);
3161 emit_clobber (reg0);
3162 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3163 emit_move_insn (len0, operands[2]);
3165 emit_clobber (reg1);
3166 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3167 emit_move_insn (len1, operands[2]);
3169 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3170 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3175 (define_insn "*cmpmem_long"
3176 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3177 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3178 (set (reg:CCU CC_REGNUM)
3179 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3180 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3182 (use (match_dup 3))]
3183 "TARGET_64BIT || !TARGET_ZARCH"
3184 "clcle\t%0,%1,0\;jo\t.-4"
3185 [(set_attr "length" "8")
3186 (set_attr "type" "vs")])
3188 (define_insn "*cmpmem_long_31z"
3189 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3190 (clobber (match_operand:TI 1 "register_operand" "=d"))
3191 (set (reg:CCU CC_REGNUM)
3192 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3193 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3195 (use (match_dup 3))]
3196 "!TARGET_64BIT && TARGET_ZARCH"
3197 "clcle\t%0,%1,0\;jo\t.-4"
3198 [(set_attr "op_type" "NN")
3199 (set_attr "type" "vs")
3200 (set_attr "length" "8")])
3202 ; Convert CCUmode condition code to integer.
3203 ; Result is zero if EQ, positive if LTU, negative if GTU.
3205 (define_insn_and_split "cmpint"
3206 [(set (match_operand:SI 0 "register_operand" "=d")
3207 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3209 (clobber (reg:CC CC_REGNUM))]
3213 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3215 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3216 (clobber (reg:CC CC_REGNUM))])])
3218 (define_insn_and_split "*cmpint_cc"
3219 [(set (reg CC_REGNUM)
3220 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3223 (set (match_operand:SI 0 "register_operand" "=d")
3224 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3225 "s390_match_ccmode (insn, CCSmode)"
3227 "&& reload_completed"
3228 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3230 [(set (match_dup 2) (match_dup 3))
3231 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3233 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3234 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3235 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3238 (define_insn_and_split "*cmpint_sign"
3239 [(set (match_operand:DI 0 "register_operand" "=d")
3240 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3241 UNSPEC_CCU_TO_INT)))
3242 (clobber (reg:CC CC_REGNUM))]
3245 "&& reload_completed"
3246 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3248 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3249 (clobber (reg:CC CC_REGNUM))])])
3251 (define_insn_and_split "*cmpint_sign_cc"
3252 [(set (reg CC_REGNUM)
3253 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3254 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3255 UNSPEC_CCU_TO_INT) 0)
3256 (const_int 32)) (const_int 32))
3258 (set (match_operand:DI 0 "register_operand" "=d")
3259 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3260 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3262 "&& reload_completed"
3263 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3265 [(set (match_dup 2) (match_dup 3))
3266 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3268 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3269 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3270 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3275 ;;- Conversion instructions.
3278 (define_insn "*sethighpartsi"
3279 [(set (match_operand:SI 0 "register_operand" "=d,d")
3280 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3281 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3282 (clobber (reg:CC CC_REGNUM))]
3287 [(set_attr "op_type" "RS,RSY")
3288 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3290 (define_insn "*sethighpartdi_64"
3291 [(set (match_operand:DI 0 "register_operand" "=d")
3292 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3293 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3294 (clobber (reg:CC CC_REGNUM))]
3297 [(set_attr "op_type" "RSY")
3298 (set_attr "z10prop" "z10_super")])
3300 (define_insn "*sethighpartdi_31"
3301 [(set (match_operand:DI 0 "register_operand" "=d,d")
3302 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3303 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3304 (clobber (reg:CC CC_REGNUM))]
3309 [(set_attr "op_type" "RS,RSY")
3310 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3313 ; extv instruction patterns
3316 ; FIXME: This expander needs to be converted from DI to GPR as well
3317 ; after resolving some issues with it.
3319 (define_expand "extzv"
3321 [(set (match_operand:DI 0 "register_operand" "=d")
3323 (match_operand:DI 1 "register_operand" "d")
3324 (match_operand 2 "const_int_operand" "") ; size
3325 (match_operand 3 "const_int_operand" ""))) ; start
3326 (clobber (reg:CC CC_REGNUM))])]
3329 /* Starting with zEC12 there is risbgn not clobbering CC. */
3332 emit_move_insn (operands[0],
3333 gen_rtx_ZERO_EXTRACT (DImode,
3341 (define_insn "*extzv<mode>_zEC12"
3342 [(set (match_operand:GPR 0 "register_operand" "=d")
3344 (match_operand:GPR 1 "register_operand" "d")
3345 (match_operand 2 "const_int_operand" "") ; size
3346 (match_operand 3 "const_int_operand" "")))] ; start]
3348 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3349 [(set_attr "op_type" "RIE")])
3351 (define_insn "*extzv<mode>_z10"
3352 [(set (match_operand:GPR 0 "register_operand" "=d")
3354 (match_operand:GPR 1 "register_operand" "d")
3355 (match_operand 2 "const_int_operand" "") ; size
3356 (match_operand 3 "const_int_operand" ""))) ; start
3357 (clobber (reg:CC CC_REGNUM))]
3359 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3360 [(set_attr "op_type" "RIE")
3361 (set_attr "z10prop" "z10_super_E1")])
3363 (define_insn_and_split "*pre_z10_extzv<mode>"
3364 [(set (match_operand:GPR 0 "register_operand" "=d")
3365 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3366 (match_operand 2 "nonzero_shift_count_operand" "")
3368 (clobber (reg:CC CC_REGNUM))]
3371 "&& reload_completed"
3373 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3374 (clobber (reg:CC CC_REGNUM))])
3375 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3377 int bitsize = INTVAL (operands[2]);
3378 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3379 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3381 operands[1] = adjust_address (operands[1], BLKmode, 0);
3382 set_mem_size (operands[1], size);
3383 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3384 operands[3] = GEN_INT (mask);
3387 (define_insn_and_split "*pre_z10_extv<mode>"
3388 [(set (match_operand:GPR 0 "register_operand" "=d")
3389 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3390 (match_operand 2 "nonzero_shift_count_operand" "")
3392 (clobber (reg:CC CC_REGNUM))]
3395 "&& reload_completed"
3397 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3398 (clobber (reg:CC CC_REGNUM))])
3400 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3401 (clobber (reg:CC CC_REGNUM))])]
3403 int bitsize = INTVAL (operands[2]);
3404 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3405 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3407 operands[1] = adjust_address (operands[1], BLKmode, 0);
3408 set_mem_size (operands[1], size);
3409 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3410 operands[3] = GEN_INT (mask);
3414 ; insv instruction patterns
3417 (define_expand "insv"
3418 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3419 (match_operand 1 "const_int_operand" "")
3420 (match_operand 2 "const_int_operand" ""))
3421 (match_operand 3 "general_operand" ""))]
3424 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3430 ; The normal RTL expansion will never generate a zero_extract where
3431 ; the location operand isn't word mode. However, we do this in the
3432 ; back-end when generating atomic operations. See s390_two_part_insv.
3433 (define_insn "*insv<mode>_zEC12"
3434 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3435 (match_operand 1 "const_int_operand" "I") ; size
3436 (match_operand 2 "const_int_operand" "I")) ; pos
3437 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3439 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3440 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3441 [(set_attr "op_type" "RIE")])
3443 (define_insn "*insv<mode>_z10"
3444 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3445 (match_operand 1 "const_int_operand" "I") ; size
3446 (match_operand 2 "const_int_operand" "I")) ; pos
3447 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3448 (clobber (reg:CC CC_REGNUM))]
3450 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3451 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3452 [(set_attr "op_type" "RIE")
3453 (set_attr "z10prop" "z10_super_E1")])
3455 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3456 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3457 (define_insn "*insv<mode>_zEC12_noshift"
3458 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3459 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3460 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3461 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3462 (match_operand:GPR 4 "const_int_operand" ""))))]
3463 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3464 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3465 [(set_attr "op_type" "RIE")])
3467 (define_insn "*insv<mode>_z10_noshift"
3468 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3469 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3470 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3471 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3472 (match_operand:GPR 4 "const_int_operand" ""))))
3473 (clobber (reg:CC CC_REGNUM))]
3474 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3475 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3476 [(set_attr "op_type" "RIE")
3477 (set_attr "z10prop" "z10_super_E1")])
3479 (define_insn "*r<noxa>sbg_<mode>_noshift"
3480 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3482 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3483 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3484 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3485 (clobber (reg:CC CC_REGNUM))]
3487 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3488 [(set_attr "op_type" "RIE")])
3490 (define_insn "*r<noxa>sbg_di_rotl"
3491 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3495 (match_operand:DI 1 "nonimmediate_operand" "d")
3496 (match_operand:DI 3 "const_int_operand" ""))
3497 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3498 (match_operand:DI 4 "nonimmediate_operand" "0")))
3499 (clobber (reg:CC CC_REGNUM))]
3501 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3502 [(set_attr "op_type" "RIE")])
3504 (define_insn "*r<noxa>sbg_<mode>_srl"
3505 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3509 (match_operand:GPR 1 "nonimmediate_operand" "d")
3510 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3511 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3512 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3513 (clobber (reg:CC CC_REGNUM))]
3515 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3516 INTVAL (operands[2]))"
3517 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3518 [(set_attr "op_type" "RIE")])
3520 (define_insn "*r<noxa>sbg_<mode>_sll"
3521 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3525 (match_operand:GPR 1 "nonimmediate_operand" "d")
3526 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3527 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3528 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3529 (clobber (reg:CC CC_REGNUM))]
3531 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3532 INTVAL (operands[2]))"
3533 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3534 [(set_attr "op_type" "RIE")])
3536 ;; These two are generated by combine for s.bf &= val.
3537 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3538 ;; shifts and ands, which results in some truly awful patterns
3539 ;; including subregs of operations. Rather unnecessisarily, IMO.
3542 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3543 ;; (const_int 24 [0x18])
3544 ;; (const_int 0 [0]))
3545 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3546 ;; (const_int 40 [0x28])) 4)
3547 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3549 ;; we should instead generate
3551 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3552 ;; (const_int 24 [0x18])
3553 ;; (const_int 0 [0]))
3554 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3555 ;; (const_int 40 [0x28]))
3556 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3558 ;; by noticing that we can push down the outer paradoxical subreg
3559 ;; into the operation.
3561 (define_insn "*insv_rnsbg_noshift"
3562 [(set (zero_extract:DI
3563 (match_operand:DI 0 "nonimmediate_operand" "+d")
3564 (match_operand 1 "const_int_operand" "")
3565 (match_operand 2 "const_int_operand" ""))
3568 (match_operand:DI 3 "nonimmediate_operand" "d")))
3569 (clobber (reg:CC CC_REGNUM))]
3571 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3572 "rnsbg\t%0,%3,%2,63,0"
3573 [(set_attr "op_type" "RIE")])
3575 (define_insn "*insv_rnsbg_srl"
3576 [(set (zero_extract:DI
3577 (match_operand:DI 0 "nonimmediate_operand" "+d")
3578 (match_operand 1 "const_int_operand" "")
3579 (match_operand 2 "const_int_operand" ""))
3583 (match_operand 3 "const_int_operand" ""))
3584 (match_operand:DI 4 "nonimmediate_operand" "d")))
3585 (clobber (reg:CC CC_REGNUM))]
3587 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3588 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3589 [(set_attr "op_type" "RIE")])
3591 (define_insn "*insv<mode>_mem_reg"
3592 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3593 (match_operand 1 "const_int_operand" "n,n")
3595 (match_operand:W 2 "register_operand" "d,d"))]
3596 "INTVAL (operands[1]) > 0
3597 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3598 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3600 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3602 operands[1] = GEN_INT ((1ul << size) - 1);
3603 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3604 : "stcmy\t%2,%1,%S0";
3606 [(set_attr "op_type" "RS,RSY")
3607 (set_attr "z10prop" "z10_super,z10_super")])
3609 (define_insn "*insvdi_mem_reghigh"
3610 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3611 (match_operand 1 "const_int_operand" "n")
3613 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3616 && INTVAL (operands[1]) > 0
3617 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3618 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3620 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3622 operands[1] = GEN_INT ((1ul << size) - 1);
3623 return "stcmh\t%2,%1,%S0";
3625 [(set_attr "op_type" "RSY")
3626 (set_attr "z10prop" "z10_super")])
3628 (define_insn "*insvdi_reg_imm"
3629 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3631 (match_operand 1 "const_int_operand" "n"))
3632 (match_operand:DI 2 "const_int_operand" "n"))]
3634 && INTVAL (operands[1]) >= 0
3635 && INTVAL (operands[1]) < BITS_PER_WORD
3636 && INTVAL (operands[1]) % 16 == 0"
3638 switch (BITS_PER_WORD - INTVAL (operands[1]))
3640 case 64: return "iihh\t%0,%x2"; break;
3641 case 48: return "iihl\t%0,%x2"; break;
3642 case 32: return "iilh\t%0,%x2"; break;
3643 case 16: return "iill\t%0,%x2"; break;
3644 default: gcc_unreachable();
3647 [(set_attr "op_type" "RI")
3648 (set_attr "z10prop" "z10_super_E1")])
3650 ; Update the left-most 32 bit of a DI.
3651 (define_insn "*insv_h_di_reg_extimm"
3652 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3655 (match_operand:DI 1 "const_int_operand" "n"))]
3658 [(set_attr "op_type" "RIL")
3659 (set_attr "z10prop" "z10_fwd_E1")])
3661 ; Update the right-most 32 bit of a DI.
3662 (define_insn "*insv_l_di_reg_extimm"
3663 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3666 (match_operand:DI 1 "const_int_operand" "n"))]
3669 [(set_attr "op_type" "RIL")
3670 (set_attr "z10prop" "z10_fwd_A1")])
3673 ; extendsidi2 instruction pattern(s).
3676 (define_expand "extendsidi2"
3677 [(set (match_operand:DI 0 "register_operand" "")
3678 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3683 emit_clobber (operands[0]);
3684 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3685 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3686 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3691 (define_insn "*extendsidi2"
3692 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3693 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3699 [(set_attr "op_type" "RRE,RXY,RIL")
3700 (set_attr "type" "*,*,larl")
3701 (set_attr "cpu_facility" "*,*,z10")
3702 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3705 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3708 (define_expand "extend<HQI:mode><DSI:mode>2"
3709 [(set (match_operand:DSI 0 "register_operand" "")
3710 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3713 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3715 rtx tmp = gen_reg_rtx (SImode);
3716 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3717 emit_insn (gen_extendsidi2 (operands[0], tmp));
3720 else if (!TARGET_EXTIMM)
3722 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3724 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3725 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3726 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3732 ; extendhidi2 instruction pattern(s).
3735 (define_insn "*extendhidi2_extimm"
3736 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3737 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3738 "TARGET_ZARCH && TARGET_EXTIMM"
3743 [(set_attr "op_type" "RRE,RXY,RIL")
3744 (set_attr "type" "*,*,larl")
3745 (set_attr "cpu_facility" "extimm,extimm,z10")
3746 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3748 (define_insn "*extendhidi2"
3749 [(set (match_operand:DI 0 "register_operand" "=d")
3750 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3753 [(set_attr "op_type" "RXY")
3754 (set_attr "z10prop" "z10_super_E1")])
3757 ; extendhisi2 instruction pattern(s).
3760 (define_insn "*extendhisi2_extimm"
3761 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3762 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3769 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3770 (set_attr "type" "*,*,*,larl")
3771 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3772 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3774 (define_insn "*extendhisi2"
3775 [(set (match_operand:SI 0 "register_operand" "=d,d")
3776 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3781 [(set_attr "op_type" "RX,RXY")
3782 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3785 ; extendqi(si|di)2 instruction pattern(s).
3788 ; lbr, lgbr, lb, lgb
3789 (define_insn "*extendqi<mode>2_extimm"
3790 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3791 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3796 [(set_attr "op_type" "RRE,RXY")
3797 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3800 (define_insn "*extendqi<mode>2"
3801 [(set (match_operand:GPR 0 "register_operand" "=d")
3802 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3803 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3805 [(set_attr "op_type" "RXY")
3806 (set_attr "z10prop" "z10_super_E1")])
3808 (define_insn_and_split "*extendqi<mode>2_short_displ"
3809 [(set (match_operand:GPR 0 "register_operand" "=d")
3810 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3811 (clobber (reg:CC CC_REGNUM))]
3812 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3814 "&& reload_completed"
3816 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3817 (clobber (reg:CC CC_REGNUM))])
3819 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3820 (clobber (reg:CC CC_REGNUM))])]
3822 operands[1] = adjust_address (operands[1], BLKmode, 0);
3823 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3824 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3828 ; zero_extendsidi2 instruction pattern(s).
3831 (define_expand "zero_extendsidi2"
3832 [(set (match_operand:DI 0 "register_operand" "")
3833 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3838 emit_clobber (operands[0]);
3839 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3840 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3845 (define_insn "*zero_extendsidi2"
3846 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3847 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3853 [(set_attr "op_type" "RRE,RXY,RIL")
3854 (set_attr "type" "*,*,larl")
3855 (set_attr "cpu_facility" "*,*,z10")
3856 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3859 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3862 (define_insn "*llgt_sidi"
3863 [(set (match_operand:DI 0 "register_operand" "=d")
3864 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3865 (const_int 2147483647)))]
3868 [(set_attr "op_type" "RXE")
3869 (set_attr "z10prop" "z10_super_E1")])
3871 (define_insn_and_split "*llgt_sidi_split"
3872 [(set (match_operand:DI 0 "register_operand" "=d")
3873 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3874 (const_int 2147483647)))
3875 (clobber (reg:CC CC_REGNUM))]
3878 "&& reload_completed"
3880 (and:DI (subreg:DI (match_dup 1) 0)
3881 (const_int 2147483647)))]
3884 (define_insn "*llgt_sisi"
3885 [(set (match_operand:SI 0 "register_operand" "=d,d")
3886 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3887 (const_int 2147483647)))]
3892 [(set_attr "op_type" "RRE,RXE")
3893 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3895 (define_insn "*llgt_didi"
3896 [(set (match_operand:DI 0 "register_operand" "=d,d")
3897 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3898 (const_int 2147483647)))]
3903 [(set_attr "op_type" "RRE,RXE")
3904 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3907 [(set (match_operand:DSI 0 "register_operand" "")
3908 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3909 (const_int 2147483647)))
3910 (clobber (reg:CC CC_REGNUM))]
3911 "TARGET_ZARCH && reload_completed"
3913 (and:DSI (match_dup 1)
3914 (const_int 2147483647)))]
3918 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3921 (define_expand "zero_extend<mode>di2"
3922 [(set (match_operand:DI 0 "register_operand" "")
3923 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3928 rtx tmp = gen_reg_rtx (SImode);
3929 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3930 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3933 else if (!TARGET_EXTIMM)
3935 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
3936 operands[1] = gen_lowpart (DImode, operands[1]);
3937 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3938 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3943 (define_expand "zero_extend<mode>si2"
3944 [(set (match_operand:SI 0 "register_operand" "")
3945 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3950 operands[1] = gen_lowpart (SImode, operands[1]);
3951 emit_insn (gen_andsi3 (operands[0], operands[1],
3952 GEN_INT ((1 << <HQI:bitsize>) - 1)));
3958 (define_insn "*zero_extendhi<mode>2_z10"
3959 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3960 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3966 [(set_attr "op_type" "RXY,RRE,RIL")
3967 (set_attr "type" "*,*,larl")
3968 (set_attr "cpu_facility" "*,*,z10")
3969 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3971 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3972 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3973 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3974 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3979 [(set_attr "op_type" "RRE,RXY")
3980 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3983 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3984 [(set (match_operand:GPR 0 "register_operand" "=d")
3985 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3986 "TARGET_ZARCH && !TARGET_EXTIMM"
3988 [(set_attr "op_type" "RXY")
3989 (set_attr "z10prop" "z10_fwd_A3")])
3991 (define_insn_and_split "*zero_extendhisi2_31"
3992 [(set (match_operand:SI 0 "register_operand" "=&d")
3993 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3994 (clobber (reg:CC CC_REGNUM))]
3997 "&& reload_completed"
3998 [(set (match_dup 0) (const_int 0))
4000 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4001 (clobber (reg:CC CC_REGNUM))])]
4002 "operands[2] = gen_lowpart (HImode, operands[0]);")
4004 (define_insn_and_split "*zero_extendqisi2_31"
4005 [(set (match_operand:SI 0 "register_operand" "=&d")
4006 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4009 "&& reload_completed"
4010 [(set (match_dup 0) (const_int 0))
4011 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4012 "operands[2] = gen_lowpart (QImode, operands[0]);")
4015 ; zero_extendqihi2 instruction pattern(s).
4018 (define_expand "zero_extendqihi2"
4019 [(set (match_operand:HI 0 "register_operand" "")
4020 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4021 "TARGET_ZARCH && !TARGET_EXTIMM"
4023 operands[1] = gen_lowpart (HImode, operands[1]);
4024 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4028 (define_insn "*zero_extendqihi2_64"
4029 [(set (match_operand:HI 0 "register_operand" "=d")
4030 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4031 "TARGET_ZARCH && !TARGET_EXTIMM"
4033 [(set_attr "op_type" "RXY")
4034 (set_attr "z10prop" "z10_fwd_A3")])
4036 (define_insn_and_split "*zero_extendqihi2_31"
4037 [(set (match_operand:HI 0 "register_operand" "=&d")
4038 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4041 "&& reload_completed"
4042 [(set (match_dup 0) (const_int 0))
4043 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4044 "operands[2] = gen_lowpart (QImode, operands[0]);")
4047 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4050 (define_expand "fixuns_truncdddi2"
4052 [(set (match_operand:DI 0 "register_operand" "")
4053 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4054 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4055 (clobber (reg:CC CC_REGNUM))])]
4061 rtx label1 = gen_label_rtx ();
4062 rtx label2 = gen_label_rtx ();
4063 rtx temp = gen_reg_rtx (TDmode);
4064 REAL_VALUE_TYPE cmp, sub;
4066 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4067 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4069 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4070 solution is doing the check and the subtraction in TD mode and using a
4071 TD -> DI convert afterwards. */
4072 emit_insn (gen_extendddtd2 (temp, operands[1]));
4073 temp = force_reg (TDmode, temp);
4074 emit_cmp_and_jump_insns (temp,
4075 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4076 LT, NULL_RTX, VOIDmode, 0, label1);
4077 emit_insn (gen_subtd3 (temp, temp,
4078 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4079 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4082 emit_label (label1);
4083 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4084 emit_label (label2);
4089 (define_expand "fixuns_trunctddi2"
4091 [(set (match_operand:DI 0 "register_operand" "")
4092 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4093 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4094 (clobber (reg:CC CC_REGNUM))])]
4100 rtx label1 = gen_label_rtx ();
4101 rtx label2 = gen_label_rtx ();
4102 rtx temp = gen_reg_rtx (TDmode);
4103 REAL_VALUE_TYPE cmp, sub;
4105 operands[1] = force_reg (TDmode, operands[1]);
4106 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4107 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4109 emit_cmp_and_jump_insns (operands[1],
4110 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4111 LT, NULL_RTX, VOIDmode, 0, label1);
4112 emit_insn (gen_subtd3 (temp, operands[1],
4113 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4114 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4117 emit_label (label1);
4118 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4119 emit_label (label2);
4125 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4126 ; instruction pattern(s).
4129 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4131 [(set (match_operand:GPR 0 "register_operand" "")
4132 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4133 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4134 (clobber (reg:CC CC_REGNUM))])]
4139 rtx label1 = gen_label_rtx ();
4140 rtx label2 = gen_label_rtx ();
4141 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4142 REAL_VALUE_TYPE cmp, sub;
4144 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4145 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4146 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4148 emit_cmp_and_jump_insns (operands[1],
4149 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4150 LT, NULL_RTX, VOIDmode, 0, label1);
4151 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4152 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4153 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4157 emit_label (label1);
4158 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4159 operands[1], GEN_INT (5)));
4160 emit_label (label2);
4165 ; fixuns_trunc(td|dd)si2 expander
4166 (define_expand "fixuns_trunc<mode>si2"
4168 [(set (match_operand:SI 0 "register_operand" "")
4169 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4170 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4171 (clobber (reg:CC CC_REGNUM))])]
4172 "TARGET_Z196 && TARGET_HARD_DFP"
4175 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4177 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4178 ; clfdtr, clfxtr, clgdtr, clgxtr
4179 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4180 [(set (match_operand:GPR 0 "register_operand" "=r")
4181 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4182 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4183 (clobber (reg:CC CC_REGNUM))]
4185 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4186 [(set_attr "op_type" "RRF")
4187 (set_attr "type" "ftoi")])
4189 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4190 [(set (match_operand:GPR 0 "register_operand" "")
4191 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4194 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4199 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4200 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4201 [(set (match_operand:GPR 0 "register_operand" "=d")
4202 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4203 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4204 (clobber (reg:CC CC_REGNUM))]
4206 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4207 [(set_attr "op_type" "RRE")
4208 (set_attr "type" "ftoi")])
4212 ; fix_trunc(td|dd)di2 instruction pattern(s).
4215 (define_expand "fix_trunc<mode>di2"
4216 [(set (match_operand:DI 0 "register_operand" "")
4217 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4218 "TARGET_ZARCH && TARGET_HARD_DFP"
4220 operands[1] = force_reg (<MODE>mode, operands[1]);
4221 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4227 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4228 [(set (match_operand:DI 0 "register_operand" "=d")
4229 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4230 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4231 (clobber (reg:CC CC_REGNUM))]
4232 "TARGET_ZARCH && TARGET_HARD_DFP"
4233 "cg<DFP:xde>tr\t%0,%h2,%1"
4234 [(set_attr "op_type" "RRF")
4235 (set_attr "type" "ftoidfp")])
4239 ; fix_trunctf(si|di)2 instruction pattern(s).
4242 (define_expand "fix_trunctf<mode>2"
4243 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4244 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4245 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4246 (clobber (reg:CC CC_REGNUM))])]
4252 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4255 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4256 (define_insn "floatdi<mode>2"
4257 [(set (match_operand:FP 0 "register_operand" "=f")
4258 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4259 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4260 "c<xde>g<bt>r\t%0,%1"
4261 [(set_attr "op_type" "RRE")
4262 (set_attr "type" "itof<mode>" )])
4264 ; cxfbr, cdfbr, cefbr
4265 (define_insn "floatsi<mode>2"
4266 [(set (match_operand:BFP 0 "register_operand" "=f")
4267 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4270 [(set_attr "op_type" "RRE")
4271 (set_attr "type" "itof<mode>" )])
4274 (define_insn "floatsi<mode>2"
4275 [(set (match_operand:DFP 0 "register_operand" "=f")
4276 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4277 "TARGET_Z196 && TARGET_HARD_FLOAT"
4278 "c<xde>ftr\t%0,0,%1,0"
4279 [(set_attr "op_type" "RRE")
4280 (set_attr "type" "itof<mode>" )])
4283 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4286 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4287 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4288 (define_insn "floatuns<GPR:mode><FP:mode>2"
4289 [(set (match_operand:FP 0 "register_operand" "=f")
4290 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4291 "TARGET_Z196 && TARGET_HARD_FLOAT"
4292 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4293 [(set_attr "op_type" "RRE")
4294 (set_attr "type" "itof<FP:mode>" )])
4297 ; truncdfsf2 instruction pattern(s).
4300 (define_insn "truncdfsf2"
4301 [(set (match_operand:SF 0 "register_operand" "=f")
4302 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4305 [(set_attr "op_type" "RRE")
4306 (set_attr "type" "ftruncdf")])
4309 ; trunctf(df|sf)2 instruction pattern(s).
4313 (define_insn "trunctf<mode>2"
4314 [(set (match_operand:DSF 0 "register_operand" "=f")
4315 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4316 (clobber (match_scratch:TF 2 "=f"))]
4318 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4319 [(set_attr "length" "6")
4320 (set_attr "type" "ftrunctf")])
4323 ; trunctddd2 and truncddsd2 instruction pattern(s).
4326 (define_insn "trunctddd2"
4327 [(set (match_operand:DD 0 "register_operand" "=f")
4328 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4329 (clobber (match_scratch:TD 2 "=f"))]
4331 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4332 [(set_attr "length" "6")
4333 (set_attr "type" "ftruncdd")])
4335 (define_insn "truncddsd2"
4336 [(set (match_operand:SD 0 "register_operand" "=f")
4337 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4340 [(set_attr "op_type" "RRF")
4341 (set_attr "type" "ftruncsd")])
4344 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4347 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4348 (define_insn "extend<DSF:mode><BFP:mode>2"
4349 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4350 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4352 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4354 l<BFP:xde><DSF:xde>br\t%0,%1
4355 l<BFP:xde><DSF:xde>b\t%0,%1"
4356 [(set_attr "op_type" "RRE,RXE")
4357 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4360 ; extendddtd2 and extendsddd2 instruction pattern(s).
4363 (define_insn "extendddtd2"
4364 [(set (match_operand:TD 0 "register_operand" "=f")
4365 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4368 [(set_attr "op_type" "RRF")
4369 (set_attr "type" "fsimptf")])
4371 (define_insn "extendsddd2"
4372 [(set (match_operand:DD 0 "register_operand" "=f")
4373 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4376 [(set_attr "op_type" "RRF")
4377 (set_attr "type" "fsimptf")])
4379 ; Binary <-> Decimal floating point trunc patterns
4382 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4383 [(set (reg:DFP_ALL FPR0_REGNUM)
4384 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4385 (use (reg:SI GPR0_REGNUM))
4386 (clobber (reg:CC CC_REGNUM))]
4390 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4391 [(set (reg:BFP FPR0_REGNUM)
4392 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4393 (use (reg:SI GPR0_REGNUM))
4394 (clobber (reg:CC CC_REGNUM))]
4398 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4399 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4400 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4402 [(set (reg:DFP_ALL FPR0_REGNUM)
4403 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4404 (use (reg:SI GPR0_REGNUM))
4405 (clobber (reg:CC CC_REGNUM))])
4406 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4407 (reg:DFP_ALL FPR0_REGNUM))]
4409 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4411 HOST_WIDE_INT flags;
4413 flags = (PFPO_CONVERT |
4414 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4415 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4417 operands[2] = GEN_INT (flags);
4420 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4421 [(set (reg:DFP_ALL FPR2_REGNUM)
4422 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4423 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4425 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4426 (use (reg:SI GPR0_REGNUM))
4427 (clobber (reg:CC CC_REGNUM))])
4428 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4430 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4432 HOST_WIDE_INT flags;
4434 flags = (PFPO_CONVERT |
4435 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4436 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4438 operands[2] = GEN_INT (flags);
4442 ; Binary <-> Decimal floating point extend patterns
4445 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4446 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4447 (use (reg:SI GPR0_REGNUM))
4448 (clobber (reg:CC CC_REGNUM))]
4452 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4453 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4454 (use (reg:SI GPR0_REGNUM))
4455 (clobber (reg:CC CC_REGNUM))]
4459 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4460 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4461 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4463 [(set (reg:DFP_ALL FPR0_REGNUM)
4464 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4465 (use (reg:SI GPR0_REGNUM))
4466 (clobber (reg:CC CC_REGNUM))])
4467 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4468 (reg:DFP_ALL FPR0_REGNUM))]
4470 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4472 HOST_WIDE_INT flags;
4474 flags = (PFPO_CONVERT |
4475 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4476 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4478 operands[2] = GEN_INT (flags);
4481 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4482 [(set (reg:DFP_ALL FPR2_REGNUM)
4483 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4484 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4486 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4487 (use (reg:SI GPR0_REGNUM))
4488 (clobber (reg:CC CC_REGNUM))])
4489 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4491 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4493 HOST_WIDE_INT flags;
4495 flags = (PFPO_CONVERT |
4496 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4497 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4499 operands[2] = GEN_INT (flags);
4504 ;; ARITHMETIC OPERATIONS
4506 ; arithmetic operations set the ConditionCode,
4507 ; because of unpredictable Bits in Register for Halfword and Byte
4508 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4511 ;;- Add instructions.
4515 ; addti3 instruction pattern(s).
4518 (define_insn_and_split "addti3"
4519 [(set (match_operand:TI 0 "register_operand" "=&d")
4520 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4521 (match_operand:TI 2 "general_operand" "do") ) )
4522 (clobber (reg:CC CC_REGNUM))]
4525 "&& reload_completed"
4527 [(set (reg:CCL1 CC_REGNUM)
4528 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4530 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4532 [(set (match_dup 3) (plus:DI
4533 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4534 (match_dup 4)) (match_dup 5)))
4535 (clobber (reg:CC CC_REGNUM))])]
4536 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4537 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4538 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4539 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4540 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4541 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4544 ; adddi3 instruction pattern(s).
4547 (define_expand "adddi3"
4549 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4550 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4551 (match_operand:DI 2 "general_operand" "")))
4552 (clobber (reg:CC CC_REGNUM))])]
4556 (define_insn "*adddi3_sign"
4557 [(set (match_operand:DI 0 "register_operand" "=d,d")
4558 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4559 (match_operand:DI 1 "register_operand" "0,0")))
4560 (clobber (reg:CC CC_REGNUM))]
4565 [(set_attr "op_type" "RRE,RXY")
4566 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4568 (define_insn "*adddi3_zero_cc"
4569 [(set (reg CC_REGNUM)
4570 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4571 (match_operand:DI 1 "register_operand" "0,0"))
4573 (set (match_operand:DI 0 "register_operand" "=d,d")
4574 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4575 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4579 [(set_attr "op_type" "RRE,RXY")
4580 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4582 (define_insn "*adddi3_zero_cconly"
4583 [(set (reg CC_REGNUM)
4584 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4585 (match_operand:DI 1 "register_operand" "0,0"))
4587 (clobber (match_scratch:DI 0 "=d,d"))]
4588 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4592 [(set_attr "op_type" "RRE,RXY")
4593 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4595 (define_insn "*adddi3_zero"
4596 [(set (match_operand:DI 0 "register_operand" "=d,d")
4597 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4598 (match_operand:DI 1 "register_operand" "0,0")))
4599 (clobber (reg:CC CC_REGNUM))]
4604 [(set_attr "op_type" "RRE,RXY")
4605 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4607 (define_insn_and_split "*adddi3_31z"
4608 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4609 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4610 (match_operand:DI 2 "general_operand" "do") ) )
4611 (clobber (reg:CC CC_REGNUM))]
4612 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4614 "&& reload_completed"
4616 [(set (reg:CCL1 CC_REGNUM)
4617 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4619 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4621 [(set (match_dup 3) (plus:SI
4622 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4623 (match_dup 4)) (match_dup 5)))
4624 (clobber (reg:CC CC_REGNUM))])]
4625 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4626 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4627 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4628 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4629 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4630 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4632 (define_insn_and_split "*adddi3_31"
4633 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4634 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4635 (match_operand:DI 2 "general_operand" "do") ) )
4636 (clobber (reg:CC CC_REGNUM))]
4639 "&& reload_completed"
4641 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4642 (clobber (reg:CC CC_REGNUM))])
4644 [(set (reg:CCL1 CC_REGNUM)
4645 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4647 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4649 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4651 (label_ref (match_dup 9))))
4653 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4654 (clobber (reg:CC CC_REGNUM))])
4656 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4657 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4658 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4659 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4660 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4661 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4662 operands[9] = gen_label_rtx ();")
4665 ; addsi3 instruction pattern(s).
4668 (define_expand "addsi3"
4670 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4671 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4672 (match_operand:SI 2 "general_operand" "")))
4673 (clobber (reg:CC CC_REGNUM))])]
4677 (define_insn "*addsi3_sign"
4678 [(set (match_operand:SI 0 "register_operand" "=d,d")
4679 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4680 (match_operand:SI 1 "register_operand" "0,0")))
4681 (clobber (reg:CC CC_REGNUM))]
4686 [(set_attr "op_type" "RX,RXY")
4687 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4690 ; add(di|si)3 instruction pattern(s).
4693 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4694 (define_insn "*add<mode>3"
4695 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4696 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4697 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4698 (clobber (reg:CC CC_REGNUM))]
4710 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4711 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4712 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4713 z10_super_E1,z10_super_E1,z10_super_E1")])
4715 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4716 (define_insn "*add<mode>3_carry1_cc"
4717 [(set (reg CC_REGNUM)
4718 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4719 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4721 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4722 (plus:GPR (match_dup 1) (match_dup 2)))]
4723 "s390_match_ccmode (insn, CCL1mode)"
4729 al<g>hsik\t%0,%1,%h2
4733 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4734 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4735 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4736 z10_super_E1,z10_super_E1,z10_super_E1")])
4738 ; alr, al, aly, algr, alg, alrk, algrk
4739 (define_insn "*add<mode>3_carry1_cconly"
4740 [(set (reg CC_REGNUM)
4741 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4742 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4744 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4745 "s390_match_ccmode (insn, CCL1mode)"
4751 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4752 (set_attr "cpu_facility" "*,z196,*,*")
4753 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4755 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4756 (define_insn "*add<mode>3_carry2_cc"
4757 [(set (reg CC_REGNUM)
4758 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4759 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4761 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4762 (plus:GPR (match_dup 1) (match_dup 2)))]
4763 "s390_match_ccmode (insn, CCL1mode)"
4769 al<g>hsik\t%0,%1,%h2
4773 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4774 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4775 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4776 z10_super_E1,z10_super_E1,z10_super_E1")])
4778 ; alr, al, aly, algr, alg, alrk, algrk
4779 (define_insn "*add<mode>3_carry2_cconly"
4780 [(set (reg CC_REGNUM)
4781 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4782 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4784 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4785 "s390_match_ccmode (insn, CCL1mode)"
4791 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4792 (set_attr "cpu_facility" "*,z196,*,*")
4793 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4795 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4796 (define_insn "*add<mode>3_cc"
4797 [(set (reg CC_REGNUM)
4798 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4799 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4801 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4802 (plus:GPR (match_dup 1) (match_dup 2)))]
4803 "s390_match_ccmode (insn, CCLmode)"
4809 al<g>hsik\t%0,%1,%h2
4813 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4814 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4815 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4816 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4818 ; alr, al, aly, algr, alg, alrk, algrk
4819 (define_insn "*add<mode>3_cconly"
4820 [(set (reg CC_REGNUM)
4821 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4822 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4824 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4825 "s390_match_ccmode (insn, CCLmode)"
4831 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4832 (set_attr "cpu_facility" "*,z196,*,*")
4833 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4835 ; alr, al, aly, algr, alg, alrk, algrk
4836 (define_insn "*add<mode>3_cconly2"
4837 [(set (reg CC_REGNUM)
4838 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4839 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4840 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4841 "s390_match_ccmode(insn, CCLmode)"
4847 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4848 (set_attr "cpu_facility" "*,z196,*,*")
4849 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4851 ; ahi, afi, aghi, agfi, asi, agsi
4852 (define_insn "*add<mode>3_imm_cc"
4853 [(set (reg CC_REGNUM)
4854 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4855 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4857 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4858 (plus:GPR (match_dup 1) (match_dup 2)))]
4859 "s390_match_ccmode (insn, CCAmode)
4860 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4861 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4862 /* Avoid INT32_MIN on 32 bit. */
4863 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
4869 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4870 (set_attr "cpu_facility" "*,z196,extimm,z10")
4871 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4874 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4877 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4878 (define_insn "add<mode>3"
4879 [(set (match_operand:FP 0 "register_operand" "=f, f")
4880 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4881 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4882 (clobber (reg:CC CC_REGNUM))]
4885 a<xde><bt>r\t%0,<op1>%2
4887 [(set_attr "op_type" "<RRer>,RXE")
4888 (set_attr "type" "fsimp<mode>")])
4890 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4891 (define_insn "*add<mode>3_cc"
4892 [(set (reg CC_REGNUM)
4893 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4894 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4895 (match_operand:FP 3 "const0_operand" "")))
4896 (set (match_operand:FP 0 "register_operand" "=f,f")
4897 (plus:FP (match_dup 1) (match_dup 2)))]
4898 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4900 a<xde><bt>r\t%0,<op1>%2
4902 [(set_attr "op_type" "<RRer>,RXE")
4903 (set_attr "type" "fsimp<mode>")])
4905 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4906 (define_insn "*add<mode>3_cconly"
4907 [(set (reg CC_REGNUM)
4908 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4909 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4910 (match_operand:FP 3 "const0_operand" "")))
4911 (clobber (match_scratch:FP 0 "=f,f"))]
4912 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4914 a<xde><bt>r\t%0,<op1>%2
4916 [(set_attr "op_type" "<RRer>,RXE")
4917 (set_attr "type" "fsimp<mode>")])
4921 ;;- Subtract instructions.
4925 ; subti3 instruction pattern(s).
4928 (define_insn_and_split "subti3"
4929 [(set (match_operand:TI 0 "register_operand" "=&d")
4930 (minus:TI (match_operand:TI 1 "register_operand" "0")
4931 (match_operand:TI 2 "general_operand" "do") ) )
4932 (clobber (reg:CC CC_REGNUM))]
4935 "&& reload_completed"
4937 [(set (reg:CCL2 CC_REGNUM)
4938 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4940 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4942 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4943 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4944 (clobber (reg:CC CC_REGNUM))])]
4945 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4946 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4947 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4948 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4949 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4950 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4953 ; subdi3 instruction pattern(s).
4956 (define_expand "subdi3"
4958 [(set (match_operand:DI 0 "register_operand" "")
4959 (minus:DI (match_operand:DI 1 "register_operand" "")
4960 (match_operand:DI 2 "general_operand" "")))
4961 (clobber (reg:CC CC_REGNUM))])]
4965 (define_insn "*subdi3_sign"
4966 [(set (match_operand:DI 0 "register_operand" "=d,d")
4967 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4968 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4969 (clobber (reg:CC CC_REGNUM))]
4974 [(set_attr "op_type" "RRE,RXY")
4975 (set_attr "z10prop" "z10_c,*")
4976 (set_attr "z196prop" "z196_cracked")])
4978 (define_insn "*subdi3_zero_cc"
4979 [(set (reg CC_REGNUM)
4980 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4981 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4983 (set (match_operand:DI 0 "register_operand" "=d,d")
4984 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4985 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4989 [(set_attr "op_type" "RRE,RXY")
4990 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4992 (define_insn "*subdi3_zero_cconly"
4993 [(set (reg CC_REGNUM)
4994 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4995 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4997 (clobber (match_scratch:DI 0 "=d,d"))]
4998 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5002 [(set_attr "op_type" "RRE,RXY")
5003 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5005 (define_insn "*subdi3_zero"
5006 [(set (match_operand:DI 0 "register_operand" "=d,d")
5007 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5008 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5009 (clobber (reg:CC CC_REGNUM))]
5014 [(set_attr "op_type" "RRE,RXY")
5015 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5017 (define_insn_and_split "*subdi3_31z"
5018 [(set (match_operand:DI 0 "register_operand" "=&d")
5019 (minus:DI (match_operand:DI 1 "register_operand" "0")
5020 (match_operand:DI 2 "general_operand" "do") ) )
5021 (clobber (reg:CC CC_REGNUM))]
5022 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5024 "&& reload_completed"
5026 [(set (reg:CCL2 CC_REGNUM)
5027 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5029 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5031 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5032 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5033 (clobber (reg:CC CC_REGNUM))])]
5034 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5035 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5036 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5037 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5038 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5039 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5041 (define_insn_and_split "*subdi3_31"
5042 [(set (match_operand:DI 0 "register_operand" "=&d")
5043 (minus:DI (match_operand:DI 1 "register_operand" "0")
5044 (match_operand:DI 2 "general_operand" "do") ) )
5045 (clobber (reg:CC CC_REGNUM))]
5048 "&& reload_completed"
5050 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5051 (clobber (reg:CC CC_REGNUM))])
5053 [(set (reg:CCL2 CC_REGNUM)
5054 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5056 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5058 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5060 (label_ref (match_dup 9))))
5062 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5063 (clobber (reg:CC CC_REGNUM))])
5065 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5066 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5067 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5068 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5069 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5070 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5071 operands[9] = gen_label_rtx ();")
5074 ; subsi3 instruction pattern(s).
5077 (define_expand "subsi3"
5079 [(set (match_operand:SI 0 "register_operand" "")
5080 (minus:SI (match_operand:SI 1 "register_operand" "")
5081 (match_operand:SI 2 "general_operand" "")))
5082 (clobber (reg:CC CC_REGNUM))])]
5086 (define_insn "*subsi3_sign"
5087 [(set (match_operand:SI 0 "register_operand" "=d,d")
5088 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5089 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5090 (clobber (reg:CC CC_REGNUM))]
5095 [(set_attr "op_type" "RX,RXY")
5096 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5099 ; sub(di|si)3 instruction pattern(s).
5102 ; sr, s, sy, sgr, sg, srk, sgrk
5103 (define_insn "*sub<mode>3"
5104 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5105 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5106 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5107 (clobber (reg:CC CC_REGNUM))]
5114 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5115 (set_attr "cpu_facility" "*,z196,*,*")
5116 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5118 ; slr, sl, sly, slgr, slg, slrk, slgrk
5119 (define_insn "*sub<mode>3_borrow_cc"
5120 [(set (reg CC_REGNUM)
5121 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5122 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5124 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5125 (minus:GPR (match_dup 1) (match_dup 2)))]
5126 "s390_match_ccmode (insn, CCL2mode)"
5132 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5133 (set_attr "cpu_facility" "*,z196,*,*")
5134 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5136 ; slr, sl, sly, slgr, slg, slrk, slgrk
5137 (define_insn "*sub<mode>3_borrow_cconly"
5138 [(set (reg CC_REGNUM)
5139 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5140 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5142 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5143 "s390_match_ccmode (insn, CCL2mode)"
5149 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5150 (set_attr "cpu_facility" "*,z196,*,*")
5151 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5153 ; slr, sl, sly, slgr, slg, slrk, slgrk
5154 (define_insn "*sub<mode>3_cc"
5155 [(set (reg CC_REGNUM)
5156 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5157 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5159 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5160 (minus:GPR (match_dup 1) (match_dup 2)))]
5161 "s390_match_ccmode (insn, CCLmode)"
5167 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5168 (set_attr "cpu_facility" "*,z196,*,*")
5169 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5171 ; slr, sl, sly, slgr, slg, slrk, slgrk
5172 (define_insn "*sub<mode>3_cc2"
5173 [(set (reg CC_REGNUM)
5174 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5175 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5176 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5177 (minus:GPR (match_dup 1) (match_dup 2)))]
5178 "s390_match_ccmode (insn, CCL3mode)"
5184 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5185 (set_attr "cpu_facility" "*,z196,*,*")
5186 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5188 ; slr, sl, sly, slgr, slg, slrk, slgrk
5189 (define_insn "*sub<mode>3_cconly"
5190 [(set (reg CC_REGNUM)
5191 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5192 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5194 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5195 "s390_match_ccmode (insn, CCLmode)"
5201 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5202 (set_attr "cpu_facility" "*,z196,*,*")
5203 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5206 ; slr, sl, sly, slgr, slg, slrk, slgrk
5207 (define_insn "*sub<mode>3_cconly2"
5208 [(set (reg CC_REGNUM)
5209 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5210 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5211 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5212 "s390_match_ccmode (insn, CCL3mode)"
5218 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5219 (set_attr "cpu_facility" "*,z196,*,*")
5220 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5224 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5227 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5228 (define_insn "sub<mode>3"
5229 [(set (match_operand:FP 0 "register_operand" "=f, f")
5230 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5231 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5232 (clobber (reg:CC CC_REGNUM))]
5235 s<xde><bt>r\t%0,<op1>%2
5237 [(set_attr "op_type" "<RRer>,RXE")
5238 (set_attr "type" "fsimp<mode>")])
5240 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5241 (define_insn "*sub<mode>3_cc"
5242 [(set (reg CC_REGNUM)
5243 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5244 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5245 (match_operand:FP 3 "const0_operand" "")))
5246 (set (match_operand:FP 0 "register_operand" "=f,f")
5247 (minus:FP (match_dup 1) (match_dup 2)))]
5248 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5250 s<xde><bt>r\t%0,<op1>%2
5252 [(set_attr "op_type" "<RRer>,RXE")
5253 (set_attr "type" "fsimp<mode>")])
5255 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5256 (define_insn "*sub<mode>3_cconly"
5257 [(set (reg CC_REGNUM)
5258 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5259 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5260 (match_operand:FP 3 "const0_operand" "")))
5261 (clobber (match_scratch:FP 0 "=f,f"))]
5262 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5264 s<xde><bt>r\t%0,<op1>%2
5266 [(set_attr "op_type" "<RRer>,RXE")
5267 (set_attr "type" "fsimp<mode>")])
5271 ;;- Conditional add/subtract instructions.
5275 ; add(di|si)cc instruction pattern(s).
5278 ; the following 4 patterns are used when the result of an add with
5279 ; carry is checked for an overflow condition
5281 ; op1 + op2 + c < op1
5283 ; alcr, alc, alcgr, alcg
5284 (define_insn "*add<mode>3_alc_carry1_cc"
5285 [(set (reg CC_REGNUM)
5287 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5288 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5289 (match_operand:GPR 2 "general_operand" "d,RT"))
5291 (set (match_operand:GPR 0 "register_operand" "=d,d")
5292 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5293 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5297 [(set_attr "op_type" "RRE,RXY")
5298 (set_attr "z196prop" "z196_alone,z196_alone")])
5300 ; alcr, alc, alcgr, alcg
5301 (define_insn "*add<mode>3_alc_carry1_cconly"
5302 [(set (reg CC_REGNUM)
5304 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5305 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5306 (match_operand:GPR 2 "general_operand" "d,RT"))
5308 (clobber (match_scratch:GPR 0 "=d,d"))]
5309 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5313 [(set_attr "op_type" "RRE,RXY")
5314 (set_attr "z196prop" "z196_alone,z196_alone")])
5316 ; op1 + op2 + c < op2
5318 ; alcr, alc, alcgr, alcg
5319 (define_insn "*add<mode>3_alc_carry2_cc"
5320 [(set (reg CC_REGNUM)
5322 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5323 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5324 (match_operand:GPR 2 "general_operand" "d,RT"))
5326 (set (match_operand:GPR 0 "register_operand" "=d,d")
5327 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5328 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5332 [(set_attr "op_type" "RRE,RXY")])
5334 ; alcr, alc, alcgr, alcg
5335 (define_insn "*add<mode>3_alc_carry2_cconly"
5336 [(set (reg CC_REGNUM)
5338 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5339 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5340 (match_operand:GPR 2 "general_operand" "d,RT"))
5342 (clobber (match_scratch:GPR 0 "=d,d"))]
5343 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5347 [(set_attr "op_type" "RRE,RXY")])
5349 ; alcr, alc, alcgr, alcg
5350 (define_insn "*add<mode>3_alc_cc"
5351 [(set (reg CC_REGNUM)
5353 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5354 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5355 (match_operand:GPR 2 "general_operand" "d,RT"))
5357 (set (match_operand:GPR 0 "register_operand" "=d,d")
5358 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5359 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5363 [(set_attr "op_type" "RRE,RXY")])
5365 ; alcr, alc, alcgr, alcg
5366 (define_insn "*add<mode>3_alc"
5367 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5368 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5369 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5370 (match_operand:GPR 2 "general_operand" "d,RT")))
5371 (clobber (reg:CC CC_REGNUM))]
5376 [(set_attr "op_type" "RRE,RXY")])
5378 ; slbr, slb, slbgr, slbg
5379 (define_insn "*sub<mode>3_slb_cc"
5380 [(set (reg CC_REGNUM)
5382 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5383 (match_operand:GPR 2 "general_operand" "d,RT"))
5384 (match_operand:GPR 3 "s390_slb_comparison" ""))
5386 (set (match_operand:GPR 0 "register_operand" "=d,d")
5387 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5388 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5392 [(set_attr "op_type" "RRE,RXY")
5393 (set_attr "z10prop" "z10_c,*")])
5395 ; slbr, slb, slbgr, slbg
5396 (define_insn "*sub<mode>3_slb"
5397 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5398 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5399 (match_operand:GPR 2 "general_operand" "d,RT"))
5400 (match_operand:GPR 3 "s390_slb_comparison" "")))
5401 (clobber (reg:CC CC_REGNUM))]
5406 [(set_attr "op_type" "RRE,RXY")
5407 (set_attr "z10prop" "z10_c,*")])
5409 (define_expand "add<mode>cc"
5410 [(match_operand:GPR 0 "register_operand" "")
5411 (match_operand 1 "comparison_operator" "")
5412 (match_operand:GPR 2 "register_operand" "")
5413 (match_operand:GPR 3 "const_int_operand" "")]
5415 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5416 XEXP (operands[1], 0), XEXP (operands[1], 1),
5417 operands[0], operands[2],
5418 operands[3])) FAIL; DONE;")
5421 ; scond instruction pattern(s).
5424 (define_insn_and_split "*scond<mode>"
5425 [(set (match_operand:GPR 0 "register_operand" "=&d")
5426 (match_operand:GPR 1 "s390_alc_comparison" ""))
5427 (clobber (reg:CC CC_REGNUM))]
5430 "&& reload_completed"
5431 [(set (match_dup 0) (const_int 0))
5433 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5435 (clobber (reg:CC CC_REGNUM))])]
5438 (define_insn_and_split "*scond<mode>_neg"
5439 [(set (match_operand:GPR 0 "register_operand" "=&d")
5440 (match_operand:GPR 1 "s390_slb_comparison" ""))
5441 (clobber (reg:CC CC_REGNUM))]
5444 "&& reload_completed"
5445 [(set (match_dup 0) (const_int 0))
5447 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5449 (clobber (reg:CC CC_REGNUM))])
5451 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5452 (clobber (reg:CC CC_REGNUM))])]
5456 (define_expand "cstore<mode>4"
5457 [(set (match_operand:SI 0 "register_operand" "")
5458 (match_operator:SI 1 "s390_scond_operator"
5459 [(match_operand:GPR 2 "register_operand" "")
5460 (match_operand:GPR 3 "general_operand" "")]))]
5462 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5463 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5465 (define_expand "cstorecc4"
5467 [(set (match_operand:SI 0 "register_operand" "")
5468 (match_operator:SI 1 "s390_eqne_operator"
5469 [(match_operand:CCZ1 2 "register_operand")
5470 (match_operand 3 "const0_operand")]))
5471 (clobber (reg:CC CC_REGNUM))])]
5473 "emit_insn (gen_sne (operands[0], operands[2]));
5474 if (GET_CODE (operands[1]) == EQ)
5475 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5478 (define_insn_and_split "sne"
5479 [(set (match_operand:SI 0 "register_operand" "=d")
5480 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5482 (clobber (reg:CC CC_REGNUM))]
5487 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5488 (clobber (reg:CC CC_REGNUM))])])
5492 ;; - Conditional move instructions (introduced with z196)
5495 (define_expand "mov<mode>cc"
5496 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5497 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5498 (match_operand:GPR 2 "nonimmediate_operand" "")
5499 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5501 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5502 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5504 ; locr, loc, stoc, locgr, locg, stocg
5505 (define_insn_and_split "*mov<mode>cc"
5506 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5508 (match_operator 1 "s390_comparison"
5509 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5511 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5512 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5522 "&& reload_completed
5523 && MEM_P (operands[3]) && MEM_P (operands[4])"
5526 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5531 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5535 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5538 ;;- Multiply instructions.
5542 ; muldi3 instruction pattern(s).
5545 (define_insn "*muldi3_sign"
5546 [(set (match_operand:DI 0 "register_operand" "=d,d")
5547 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5548 (match_operand:DI 1 "register_operand" "0,0")))]
5553 [(set_attr "op_type" "RRE,RXY")
5554 (set_attr "type" "imuldi")])
5556 (define_insn "muldi3"
5557 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5558 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5559 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5566 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5567 (set_attr "type" "imuldi")
5568 (set_attr "cpu_facility" "*,*,*,z10")])
5571 ; mulsi3 instruction pattern(s).
5574 (define_insn "*mulsi3_sign"
5575 [(set (match_operand:SI 0 "register_operand" "=d,d")
5576 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5577 (match_operand:SI 1 "register_operand" "0,0")))]
5582 [(set_attr "op_type" "RX,RXY")
5583 (set_attr "type" "imulhi")
5584 (set_attr "cpu_facility" "*,z10")])
5586 (define_insn "mulsi3"
5587 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5588 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5589 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5597 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5598 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5599 (set_attr "cpu_facility" "*,*,*,*,z10")])
5602 ; mulsidi3 instruction pattern(s).
5605 (define_insn "mulsidi3"
5606 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5607 (mult:DI (sign_extend:DI
5608 (match_operand:SI 1 "register_operand" "%0,0,0"))
5610 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5616 [(set_attr "op_type" "RR,RX,RXY")
5617 (set_attr "type" "imulsi")
5618 (set_attr "cpu_facility" "*,*,z10")])
5621 ; umul instruction pattern(s).
5624 ; mlr, ml, mlgr, mlg
5625 (define_insn "umul<dwh><mode>3"
5626 [(set (match_operand:DW 0 "register_operand" "=d, d")
5627 (mult:DW (zero_extend:DW
5628 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5630 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5635 [(set_attr "op_type" "RRE,RXY")
5636 (set_attr "type" "imul<dwh>")])
5639 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5642 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5643 (define_insn "mul<mode>3"
5644 [(set (match_operand:FP 0 "register_operand" "=f,f")
5645 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5646 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5649 m<xdee><bt>r\t%0,<op1>%2
5651 [(set_attr "op_type" "<RRer>,RXE")
5652 (set_attr "type" "fmul<mode>")])
5654 ; madbr, maebr, maxb, madb, maeb
5655 (define_insn "fma<mode>4"
5656 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5657 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5658 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5659 (match_operand:DSF 3 "register_operand" "0,0")))]
5664 [(set_attr "op_type" "RRE,RXE")
5665 (set_attr "type" "fmadd<mode>")])
5667 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5668 (define_insn "fms<mode>4"
5669 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5670 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5671 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5672 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5677 [(set_attr "op_type" "RRE,RXE")
5678 (set_attr "type" "fmadd<mode>")])
5681 ;;- Divide and modulo instructions.
5685 ; divmoddi4 instruction pattern(s).
5688 (define_expand "divmoddi4"
5689 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5690 (div:DI (match_operand:DI 1 "register_operand" "")
5691 (match_operand:DI 2 "general_operand" "")))
5692 (set (match_operand:DI 3 "general_operand" "")
5693 (mod:DI (match_dup 1) (match_dup 2)))])
5694 (clobber (match_dup 4))]
5697 rtx insn, div_equal, mod_equal;
5699 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5700 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5702 operands[4] = gen_reg_rtx(TImode);
5703 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5705 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5706 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5708 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5709 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5714 (define_insn "divmodtidi3"
5715 [(set (match_operand:TI 0 "register_operand" "=d,d")
5719 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5720 (match_operand:DI 2 "general_operand" "d,RT")))
5722 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5727 [(set_attr "op_type" "RRE,RXY")
5728 (set_attr "type" "idiv")])
5730 (define_insn "divmodtisi3"
5731 [(set (match_operand:TI 0 "register_operand" "=d,d")
5735 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5737 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5740 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5745 [(set_attr "op_type" "RRE,RXY")
5746 (set_attr "type" "idiv")])
5749 ; udivmoddi4 instruction pattern(s).
5752 (define_expand "udivmoddi4"
5753 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5754 (udiv:DI (match_operand:DI 1 "general_operand" "")
5755 (match_operand:DI 2 "nonimmediate_operand" "")))
5756 (set (match_operand:DI 3 "general_operand" "")
5757 (umod:DI (match_dup 1) (match_dup 2)))])
5758 (clobber (match_dup 4))]
5761 rtx insn, div_equal, mod_equal, equal;
5763 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5764 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5765 equal = gen_rtx_IOR (TImode,
5766 gen_rtx_ASHIFT (TImode,
5767 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5769 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5771 operands[4] = gen_reg_rtx(TImode);
5772 emit_clobber (operands[4]);
5773 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5774 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5776 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5777 set_unique_reg_note (insn, REG_EQUAL, equal);
5779 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5780 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5782 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5783 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5788 (define_insn "udivmodtidi3"
5789 [(set (match_operand:TI 0 "register_operand" "=d,d")
5794 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5796 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5800 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5805 [(set_attr "op_type" "RRE,RXY")
5806 (set_attr "type" "idiv")])
5809 ; divmodsi4 instruction pattern(s).
5812 (define_expand "divmodsi4"
5813 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5814 (div:SI (match_operand:SI 1 "general_operand" "")
5815 (match_operand:SI 2 "nonimmediate_operand" "")))
5816 (set (match_operand:SI 3 "general_operand" "")
5817 (mod:SI (match_dup 1) (match_dup 2)))])
5818 (clobber (match_dup 4))]
5821 rtx insn, div_equal, mod_equal, equal;
5823 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5824 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5825 equal = gen_rtx_IOR (DImode,
5826 gen_rtx_ASHIFT (DImode,
5827 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5829 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5831 operands[4] = gen_reg_rtx(DImode);
5832 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5834 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5835 set_unique_reg_note (insn, REG_EQUAL, equal);
5837 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5838 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5840 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5841 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5846 (define_insn "divmoddisi3"
5847 [(set (match_operand:DI 0 "register_operand" "=d,d")
5852 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5854 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5858 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5863 [(set_attr "op_type" "RR,RX")
5864 (set_attr "type" "idiv")])
5867 ; udivsi3 and umodsi3 instruction pattern(s).
5870 (define_expand "udivmodsi4"
5871 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5872 (udiv:SI (match_operand:SI 1 "general_operand" "")
5873 (match_operand:SI 2 "nonimmediate_operand" "")))
5874 (set (match_operand:SI 3 "general_operand" "")
5875 (umod:SI (match_dup 1) (match_dup 2)))])
5876 (clobber (match_dup 4))]
5877 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5879 rtx insn, div_equal, mod_equal, equal;
5881 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5882 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5883 equal = gen_rtx_IOR (DImode,
5884 gen_rtx_ASHIFT (DImode,
5885 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5887 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5889 operands[4] = gen_reg_rtx(DImode);
5890 emit_clobber (operands[4]);
5891 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5892 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5894 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5895 set_unique_reg_note (insn, REG_EQUAL, equal);
5897 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5898 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5900 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5901 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5906 (define_insn "udivmoddisi3"
5907 [(set (match_operand:DI 0 "register_operand" "=d,d")
5912 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5914 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5918 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5919 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5923 [(set_attr "op_type" "RRE,RXY")
5924 (set_attr "type" "idiv")])
5926 (define_expand "udivsi3"
5927 [(set (match_operand:SI 0 "register_operand" "=d")
5928 (udiv:SI (match_operand:SI 1 "general_operand" "")
5929 (match_operand:SI 2 "general_operand" "")))
5930 (clobber (match_dup 3))]
5931 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5933 rtx insn, udiv_equal, umod_equal, equal;
5935 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5936 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5937 equal = gen_rtx_IOR (DImode,
5938 gen_rtx_ASHIFT (DImode,
5939 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5941 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5943 operands[3] = gen_reg_rtx (DImode);
5945 if (CONSTANT_P (operands[2]))
5947 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5949 rtx label1 = gen_label_rtx ();
5951 operands[1] = make_safe_from (operands[1], operands[0]);
5952 emit_move_insn (operands[0], const0_rtx);
5953 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5955 emit_move_insn (operands[0], const1_rtx);
5956 emit_label (label1);
5960 operands[2] = force_reg (SImode, operands[2]);
5961 operands[2] = make_safe_from (operands[2], operands[0]);
5963 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5964 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5966 set_unique_reg_note (insn, REG_EQUAL, equal);
5968 insn = emit_move_insn (operands[0],
5969 gen_lowpart (SImode, operands[3]));
5970 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5975 rtx label1 = gen_label_rtx ();
5976 rtx label2 = gen_label_rtx ();
5977 rtx label3 = gen_label_rtx ();
5979 operands[1] = force_reg (SImode, operands[1]);
5980 operands[1] = make_safe_from (operands[1], operands[0]);
5981 operands[2] = force_reg (SImode, operands[2]);
5982 operands[2] = make_safe_from (operands[2], operands[0]);
5984 emit_move_insn (operands[0], const0_rtx);
5985 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5987 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5989 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5991 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5992 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5994 set_unique_reg_note (insn, REG_EQUAL, equal);
5996 insn = emit_move_insn (operands[0],
5997 gen_lowpart (SImode, operands[3]));
5998 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6001 emit_label (label1);
6002 emit_move_insn (operands[0], operands[1]);
6004 emit_label (label2);
6005 emit_move_insn (operands[0], const1_rtx);
6006 emit_label (label3);
6008 emit_move_insn (operands[0], operands[0]);
6012 (define_expand "umodsi3"
6013 [(set (match_operand:SI 0 "register_operand" "=d")
6014 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6015 (match_operand:SI 2 "nonimmediate_operand" "")))
6016 (clobber (match_dup 3))]
6017 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6019 rtx insn, udiv_equal, umod_equal, equal;
6021 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6022 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6023 equal = gen_rtx_IOR (DImode,
6024 gen_rtx_ASHIFT (DImode,
6025 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6027 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6029 operands[3] = gen_reg_rtx (DImode);
6031 if (CONSTANT_P (operands[2]))
6033 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6035 rtx label1 = gen_label_rtx ();
6037 operands[1] = make_safe_from (operands[1], operands[0]);
6038 emit_move_insn (operands[0], operands[1]);
6039 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6041 emit_insn (gen_abssi2 (operands[0], operands[2]));
6042 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6043 emit_label (label1);
6047 operands[2] = force_reg (SImode, operands[2]);
6048 operands[2] = make_safe_from (operands[2], operands[0]);
6050 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6051 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6053 set_unique_reg_note (insn, REG_EQUAL, equal);
6055 insn = emit_move_insn (operands[0],
6056 gen_highpart (SImode, operands[3]));
6057 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6062 rtx label1 = gen_label_rtx ();
6063 rtx label2 = gen_label_rtx ();
6064 rtx label3 = gen_label_rtx ();
6066 operands[1] = force_reg (SImode, operands[1]);
6067 operands[1] = make_safe_from (operands[1], operands[0]);
6068 operands[2] = force_reg (SImode, operands[2]);
6069 operands[2] = make_safe_from (operands[2], operands[0]);
6071 emit_move_insn(operands[0], operands[1]);
6072 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6074 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6076 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6078 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6079 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6081 set_unique_reg_note (insn, REG_EQUAL, equal);
6083 insn = emit_move_insn (operands[0],
6084 gen_highpart (SImode, operands[3]));
6085 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6088 emit_label (label1);
6089 emit_move_insn (operands[0], const0_rtx);
6091 emit_label (label2);
6092 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6093 emit_label (label3);
6099 ; div(df|sf)3 instruction pattern(s).
6102 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6103 (define_insn "div<mode>3"
6104 [(set (match_operand:FP 0 "register_operand" "=f,f")
6105 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6106 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6109 d<xde><bt>r\t%0,<op1>%2
6111 [(set_attr "op_type" "<RRer>,RXE")
6112 (set_attr "type" "fdiv<mode>")])
6116 ;;- And instructions.
6119 (define_expand "and<mode>3"
6120 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6121 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6122 (match_operand:INT 2 "general_operand" "")))
6123 (clobber (reg:CC CC_REGNUM))]
6125 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6128 ; anddi3 instruction pattern(s).
6131 (define_insn "*anddi3_cc"
6132 [(set (reg CC_REGNUM)
6134 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6135 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6137 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6138 (and:DI (match_dup 1) (match_dup 2)))]
6139 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6144 risbg\t%0,%1,%s2,128+%e2,0"
6145 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6146 (set_attr "cpu_facility" "*,z196,*,z10")
6147 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6149 (define_insn "*anddi3_cconly"
6150 [(set (reg CC_REGNUM)
6152 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6153 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6155 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6157 && s390_match_ccmode(insn, CCTmode)
6158 /* Do not steal TM patterns. */
6159 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6164 risbg\t%0,%1,%s2,128+%e2,0"
6165 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6166 (set_attr "cpu_facility" "*,z196,*,z10")
6167 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6169 (define_insn "*anddi3"
6170 [(set (match_operand:DI 0 "nonimmediate_operand"
6171 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6173 (match_operand:DI 1 "nonimmediate_operand"
6174 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6175 (match_operand:DI 2 "general_operand"
6176 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6177 (clobber (reg:CC CC_REGNUM))]
6178 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6191 risbg\t%0,%1,%s2,128+%e2,0
6194 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6195 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6196 (set_attr "z10prop" "*,
6212 [(set (match_operand:DI 0 "s_operand" "")
6213 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6214 (clobber (reg:CC CC_REGNUM))]
6217 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6218 (clobber (reg:CC CC_REGNUM))])]
6219 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6221 ;; These two are what combine generates for (ashift (zero_extract)).
6222 (define_insn "*extzv_<mode>_srl"
6223 [(set (match_operand:GPR 0 "register_operand" "=d")
6224 (and:GPR (lshiftrt:GPR
6225 (match_operand:GPR 1 "register_operand" "d")
6226 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6227 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6228 (clobber (reg:CC CC_REGNUM))]
6230 /* Note that even for the SImode pattern, the rotate is always DImode. */
6231 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6232 INTVAL (operands[3]))"
6233 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6234 [(set_attr "op_type" "RIE")
6235 (set_attr "z10prop" "z10_super_E1")])
6237 (define_insn "*extzv_<mode>_sll"
6238 [(set (match_operand:GPR 0 "register_operand" "=d")
6239 (and:GPR (ashift:GPR
6240 (match_operand:GPR 1 "register_operand" "d")
6241 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6242 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6243 (clobber (reg:CC CC_REGNUM))]
6245 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6246 INTVAL (operands[3]))"
6247 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6248 [(set_attr "op_type" "RIE")
6249 (set_attr "z10prop" "z10_super_E1")])
6253 ; andsi3 instruction pattern(s).
6256 (define_insn "*andsi3_cc"
6257 [(set (reg CC_REGNUM)
6260 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6261 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6263 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6264 (and:SI (match_dup 1) (match_dup 2)))]
6265 "s390_match_ccmode(insn, CCTmode)"
6272 risbg\t%0,%1,%t2,128+%f2,0"
6273 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6274 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6275 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6276 z10_super_E1,z10_super_E1,z10_super_E1")])
6278 (define_insn "*andsi3_cconly"
6279 [(set (reg CC_REGNUM)
6282 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6283 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6285 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6286 "s390_match_ccmode(insn, CCTmode)
6287 /* Do not steal TM patterns. */
6288 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6295 risbg\t%0,%1,%t2,128+%f2,0"
6296 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6297 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6298 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6299 z10_super_E1,z10_super_E1,z10_super_E1")])
6301 (define_insn "*andsi3_zarch"
6302 [(set (match_operand:SI 0 "nonimmediate_operand"
6303 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6304 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6305 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6306 (match_operand:SI 2 "general_operand"
6307 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6308 (clobber (reg:CC CC_REGNUM))]
6309 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6320 risbg\t%0,%1,%t2,128+%f2,0
6323 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6324 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6325 (set_attr "z10prop" "*,
6338 (define_insn "*andsi3_esa"
6339 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6340 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6341 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6342 (clobber (reg:CC CC_REGNUM))]
6343 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6349 [(set_attr "op_type" "RR,RX,SI,SS")
6350 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6354 [(set (match_operand:SI 0 "s_operand" "")
6355 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6356 (clobber (reg:CC CC_REGNUM))]
6359 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6360 (clobber (reg:CC CC_REGNUM))])]
6361 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6364 ; andhi3 instruction pattern(s).
6367 (define_insn "*andhi3_zarch"
6368 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6369 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6370 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6371 (clobber (reg:CC CC_REGNUM))]
6372 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6379 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6380 (set_attr "cpu_facility" "*,z196,*,*,*")
6381 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6384 (define_insn "*andhi3_esa"
6385 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6386 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6387 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6388 (clobber (reg:CC CC_REGNUM))]
6389 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6394 [(set_attr "op_type" "RR,SI,SS")
6395 (set_attr "z10prop" "z10_super_E1,*,*")
6399 [(set (match_operand:HI 0 "s_operand" "")
6400 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6401 (clobber (reg:CC CC_REGNUM))]
6404 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6405 (clobber (reg:CC CC_REGNUM))])]
6406 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6409 ; andqi3 instruction pattern(s).
6412 (define_insn "*andqi3_zarch"
6413 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6414 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6415 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6416 (clobber (reg:CC CC_REGNUM))]
6417 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6425 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6426 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6427 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6429 (define_insn "*andqi3_esa"
6430 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6431 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6432 (match_operand:QI 2 "general_operand" "d,n,Q")))
6433 (clobber (reg:CC CC_REGNUM))]
6434 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6439 [(set_attr "op_type" "RR,SI,SS")
6440 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6443 ; Block and (NC) patterns.
6447 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6448 (and:BLK (match_dup 0)
6449 (match_operand:BLK 1 "memory_operand" "Q")))
6450 (use (match_operand 2 "const_int_operand" "n"))
6451 (clobber (reg:CC CC_REGNUM))]
6452 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6453 "nc\t%O0(%2,%R0),%S1"
6454 [(set_attr "op_type" "SS")
6455 (set_attr "z196prop" "z196_cracked")])
6458 [(set (match_operand 0 "memory_operand" "")
6460 (match_operand 1 "memory_operand" "")))
6461 (clobber (reg:CC CC_REGNUM))]
6463 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6464 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6466 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6468 (clobber (reg:CC CC_REGNUM))])]
6470 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6471 operands[0] = adjust_address (operands[0], BLKmode, 0);
6472 operands[1] = adjust_address (operands[1], BLKmode, 0);
6477 [(set (match_operand:BLK 0 "memory_operand" "")
6478 (and:BLK (match_dup 0)
6479 (match_operand:BLK 1 "memory_operand" "")))
6480 (use (match_operand 2 "const_int_operand" ""))
6481 (clobber (reg:CC CC_REGNUM))])
6483 [(set (match_operand:BLK 3 "memory_operand" "")
6484 (and:BLK (match_dup 3)
6485 (match_operand:BLK 4 "memory_operand" "")))
6486 (use (match_operand 5 "const_int_operand" ""))
6487 (clobber (reg:CC CC_REGNUM))])]
6488 "s390_offset_p (operands[0], operands[3], operands[2])
6489 && s390_offset_p (operands[1], operands[4], operands[2])
6490 && !s390_overlap_p (operands[0], operands[1],
6491 INTVAL (operands[2]) + INTVAL (operands[5]))
6492 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6494 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6496 (clobber (reg:CC CC_REGNUM))])]
6497 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6498 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6499 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6503 ;;- Bit set (inclusive or) instructions.
6506 (define_expand "ior<mode>3"
6507 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6508 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6509 (match_operand:INT 2 "general_operand" "")))
6510 (clobber (reg:CC CC_REGNUM))]
6512 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6515 ; iordi3 instruction pattern(s).
6518 (define_insn "*iordi3_cc"
6519 [(set (reg CC_REGNUM)
6520 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6521 (match_operand:DI 2 "general_operand" " d,d,RT"))
6523 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6524 (ior:DI (match_dup 1) (match_dup 2)))]
6525 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6530 [(set_attr "op_type" "RRE,RRF,RXY")
6531 (set_attr "cpu_facility" "*,z196,*")
6532 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6534 (define_insn "*iordi3_cconly"
6535 [(set (reg CC_REGNUM)
6536 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6537 (match_operand:DI 2 "general_operand" " d,d,RT"))
6539 (clobber (match_scratch:DI 0 "=d,d,d"))]
6540 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6545 [(set_attr "op_type" "RRE,RRF,RXY")
6546 (set_attr "cpu_facility" "*,z196,*")
6547 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6549 (define_insn "*iordi3"
6550 [(set (match_operand:DI 0 "nonimmediate_operand"
6551 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6552 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6553 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6554 (match_operand:DI 2 "general_operand"
6555 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6556 (clobber (reg:CC CC_REGNUM))]
6557 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6570 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6571 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6572 (set_attr "z10prop" "z10_super_E1,
6585 [(set (match_operand:DI 0 "s_operand" "")
6586 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6587 (clobber (reg:CC CC_REGNUM))]
6590 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6591 (clobber (reg:CC CC_REGNUM))])]
6592 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6595 ; iorsi3 instruction pattern(s).
6598 (define_insn "*iorsi3_cc"
6599 [(set (reg CC_REGNUM)
6600 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6601 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6603 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6604 (ior:SI (match_dup 1) (match_dup 2)))]
6605 "s390_match_ccmode(insn, CCTmode)"
6612 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6613 (set_attr "cpu_facility" "*,*,z196,*,*")
6614 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6616 (define_insn "*iorsi3_cconly"
6617 [(set (reg CC_REGNUM)
6618 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6619 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6621 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6622 "s390_match_ccmode(insn, CCTmode)"
6629 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6630 (set_attr "cpu_facility" "*,*,z196,*,*")
6631 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6633 (define_insn "*iorsi3_zarch"
6634 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6635 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6636 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6637 (clobber (reg:CC CC_REGNUM))]
6638 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6649 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6650 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6651 (set_attr "z10prop" "z10_super_E1,
6661 (define_insn "*iorsi3_esa"
6662 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6663 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6664 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6665 (clobber (reg:CC CC_REGNUM))]
6666 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6672 [(set_attr "op_type" "RR,RX,SI,SS")
6673 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6676 [(set (match_operand:SI 0 "s_operand" "")
6677 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6678 (clobber (reg:CC CC_REGNUM))]
6681 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6682 (clobber (reg:CC CC_REGNUM))])]
6683 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6686 ; iorhi3 instruction pattern(s).
6689 (define_insn "*iorhi3_zarch"
6690 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6691 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6692 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6693 (clobber (reg:CC CC_REGNUM))]
6694 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6701 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6702 (set_attr "cpu_facility" "*,z196,*,*,*")
6703 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6705 (define_insn "*iorhi3_esa"
6706 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6707 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6708 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6709 (clobber (reg:CC CC_REGNUM))]
6710 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6715 [(set_attr "op_type" "RR,SI,SS")
6716 (set_attr "z10prop" "z10_super_E1,*,*")])
6719 [(set (match_operand:HI 0 "s_operand" "")
6720 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6721 (clobber (reg:CC CC_REGNUM))]
6724 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6725 (clobber (reg:CC CC_REGNUM))])]
6726 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6729 ; iorqi3 instruction pattern(s).
6732 (define_insn "*iorqi3_zarch"
6733 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6734 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6735 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6736 (clobber (reg:CC CC_REGNUM))]
6737 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6745 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6746 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6747 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6748 z10_super,z10_super,*")])
6750 (define_insn "*iorqi3_esa"
6751 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6752 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6753 (match_operand:QI 2 "general_operand" "d,n,Q")))
6754 (clobber (reg:CC CC_REGNUM))]
6755 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6760 [(set_attr "op_type" "RR,SI,SS")
6761 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6764 ; Block inclusive or (OC) patterns.
6768 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6769 (ior:BLK (match_dup 0)
6770 (match_operand:BLK 1 "memory_operand" "Q")))
6771 (use (match_operand 2 "const_int_operand" "n"))
6772 (clobber (reg:CC CC_REGNUM))]
6773 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6774 "oc\t%O0(%2,%R0),%S1"
6775 [(set_attr "op_type" "SS")
6776 (set_attr "z196prop" "z196_cracked")])
6779 [(set (match_operand 0 "memory_operand" "")
6781 (match_operand 1 "memory_operand" "")))
6782 (clobber (reg:CC CC_REGNUM))]
6784 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6785 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6787 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6789 (clobber (reg:CC CC_REGNUM))])]
6791 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6792 operands[0] = adjust_address (operands[0], BLKmode, 0);
6793 operands[1] = adjust_address (operands[1], BLKmode, 0);
6798 [(set (match_operand:BLK 0 "memory_operand" "")
6799 (ior:BLK (match_dup 0)
6800 (match_operand:BLK 1 "memory_operand" "")))
6801 (use (match_operand 2 "const_int_operand" ""))
6802 (clobber (reg:CC CC_REGNUM))])
6804 [(set (match_operand:BLK 3 "memory_operand" "")
6805 (ior:BLK (match_dup 3)
6806 (match_operand:BLK 4 "memory_operand" "")))
6807 (use (match_operand 5 "const_int_operand" ""))
6808 (clobber (reg:CC CC_REGNUM))])]
6809 "s390_offset_p (operands[0], operands[3], operands[2])
6810 && s390_offset_p (operands[1], operands[4], operands[2])
6811 && !s390_overlap_p (operands[0], operands[1],
6812 INTVAL (operands[2]) + INTVAL (operands[5]))
6813 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6815 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6817 (clobber (reg:CC CC_REGNUM))])]
6818 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6819 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6820 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6824 ;;- Xor instructions.
6827 (define_expand "xor<mode>3"
6828 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6829 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6830 (match_operand:INT 2 "general_operand" "")))
6831 (clobber (reg:CC CC_REGNUM))]
6833 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6836 ; xordi3 instruction pattern(s).
6839 (define_insn "*xordi3_cc"
6840 [(set (reg CC_REGNUM)
6841 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6842 (match_operand:DI 2 "general_operand" " d,d,RT"))
6844 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6845 (xor:DI (match_dup 1) (match_dup 2)))]
6846 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6851 [(set_attr "op_type" "RRE,RRF,RXY")
6852 (set_attr "cpu_facility" "*,z196,*")
6853 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6855 (define_insn "*xordi3_cconly"
6856 [(set (reg CC_REGNUM)
6857 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6858 (match_operand:DI 2 "general_operand" " d,d,RT"))
6860 (clobber (match_scratch:DI 0 "=d,d, d"))]
6861 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6866 [(set_attr "op_type" "RRE,RRF,RXY")
6867 (set_attr "cpu_facility" "*,z196,*")
6868 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6870 (define_insn "*xordi3"
6871 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6872 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6873 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6874 (clobber (reg:CC CC_REGNUM))]
6875 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6884 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6885 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6886 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6887 *,z10_super_E1,*,*")])
6890 [(set (match_operand:DI 0 "s_operand" "")
6891 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6892 (clobber (reg:CC CC_REGNUM))]
6895 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6896 (clobber (reg:CC CC_REGNUM))])]
6897 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6900 ; xorsi3 instruction pattern(s).
6903 (define_insn "*xorsi3_cc"
6904 [(set (reg CC_REGNUM)
6905 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6906 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6908 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6909 (xor:SI (match_dup 1) (match_dup 2)))]
6910 "s390_match_ccmode(insn, CCTmode)"
6917 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6918 (set_attr "cpu_facility" "*,*,z196,*,*")
6919 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6920 z10_super_E1,z10_super_E1")])
6922 (define_insn "*xorsi3_cconly"
6923 [(set (reg CC_REGNUM)
6924 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6925 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6927 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6928 "s390_match_ccmode(insn, CCTmode)"
6935 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6936 (set_attr "cpu_facility" "*,*,z196,*,*")
6937 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6938 z10_super_E1,z10_super_E1")])
6940 (define_insn "*xorsi3"
6941 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6942 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6943 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6944 (clobber (reg:CC CC_REGNUM))]
6945 "s390_logical_operator_ok_p (operands)"
6954 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6955 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6956 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6957 z10_super_E1,z10_super_E1,*,*")])
6960 [(set (match_operand:SI 0 "s_operand" "")
6961 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6962 (clobber (reg:CC CC_REGNUM))]
6965 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6966 (clobber (reg:CC CC_REGNUM))])]
6967 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6970 ; xorhi3 instruction pattern(s).
6973 (define_insn "*xorhi3"
6974 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6975 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6976 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6977 (clobber (reg:CC CC_REGNUM))]
6978 "s390_logical_operator_ok_p (operands)"
6985 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6986 (set_attr "cpu_facility" "*,*,z196,*,*")
6987 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6990 [(set (match_operand:HI 0 "s_operand" "")
6991 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6992 (clobber (reg:CC CC_REGNUM))]
6995 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6996 (clobber (reg:CC CC_REGNUM))])]
6997 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7000 ; xorqi3 instruction pattern(s).
7003 (define_insn "*xorqi3"
7004 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7005 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7006 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7007 (clobber (reg:CC CC_REGNUM))]
7008 "s390_logical_operator_ok_p (operands)"
7016 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7017 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7018 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7022 ; Block exclusive or (XC) patterns.
7026 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7027 (xor:BLK (match_dup 0)
7028 (match_operand:BLK 1 "memory_operand" "Q")))
7029 (use (match_operand 2 "const_int_operand" "n"))
7030 (clobber (reg:CC CC_REGNUM))]
7031 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7032 "xc\t%O0(%2,%R0),%S1"
7033 [(set_attr "op_type" "SS")])
7036 [(set (match_operand 0 "memory_operand" "")
7038 (match_operand 1 "memory_operand" "")))
7039 (clobber (reg:CC CC_REGNUM))]
7041 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7042 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7044 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7046 (clobber (reg:CC CC_REGNUM))])]
7048 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7049 operands[0] = adjust_address (operands[0], BLKmode, 0);
7050 operands[1] = adjust_address (operands[1], BLKmode, 0);
7055 [(set (match_operand:BLK 0 "memory_operand" "")
7056 (xor:BLK (match_dup 0)
7057 (match_operand:BLK 1 "memory_operand" "")))
7058 (use (match_operand 2 "const_int_operand" ""))
7059 (clobber (reg:CC CC_REGNUM))])
7061 [(set (match_operand:BLK 3 "memory_operand" "")
7062 (xor:BLK (match_dup 3)
7063 (match_operand:BLK 4 "memory_operand" "")))
7064 (use (match_operand 5 "const_int_operand" ""))
7065 (clobber (reg:CC CC_REGNUM))])]
7066 "s390_offset_p (operands[0], operands[3], operands[2])
7067 && s390_offset_p (operands[1], operands[4], operands[2])
7068 && !s390_overlap_p (operands[0], operands[1],
7069 INTVAL (operands[2]) + INTVAL (operands[5]))
7070 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7072 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7074 (clobber (reg:CC CC_REGNUM))])]
7075 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7076 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7077 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7080 ; Block xor (XC) patterns with src == dest.
7083 (define_insn "*xc_zero"
7084 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7086 (use (match_operand 1 "const_int_operand" "n"))
7087 (clobber (reg:CC CC_REGNUM))]
7088 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7089 "xc\t%O0(%1,%R0),%S0"
7090 [(set_attr "op_type" "SS")
7091 (set_attr "z196prop" "z196_cracked")])
7095 [(set (match_operand:BLK 0 "memory_operand" "")
7097 (use (match_operand 1 "const_int_operand" ""))
7098 (clobber (reg:CC CC_REGNUM))])
7100 [(set (match_operand:BLK 2 "memory_operand" "")
7102 (use (match_operand 3 "const_int_operand" ""))
7103 (clobber (reg:CC CC_REGNUM))])]
7104 "s390_offset_p (operands[0], operands[2], operands[1])
7105 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7107 [(set (match_dup 4) (const_int 0))
7109 (clobber (reg:CC CC_REGNUM))])]
7110 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7111 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7115 ;;- Negate instructions.
7119 ; neg(di|si)2 instruction pattern(s).
7122 (define_expand "neg<mode>2"
7124 [(set (match_operand:DSI 0 "register_operand" "=d")
7125 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7126 (clobber (reg:CC CC_REGNUM))])]
7130 (define_insn "*negdi2_sign_cc"
7131 [(set (reg CC_REGNUM)
7132 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7133 (match_operand:SI 1 "register_operand" "d") 0)
7134 (const_int 32)) (const_int 32)))
7136 (set (match_operand:DI 0 "register_operand" "=d")
7137 (neg:DI (sign_extend:DI (match_dup 1))))]
7138 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7140 [(set_attr "op_type" "RRE")
7141 (set_attr "z10prop" "z10_c")])
7143 (define_insn "*negdi2_sign"
7144 [(set (match_operand:DI 0 "register_operand" "=d")
7145 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7146 (clobber (reg:CC CC_REGNUM))]
7149 [(set_attr "op_type" "RRE")
7150 (set_attr "z10prop" "z10_c")])
7153 (define_insn "*neg<mode>2_cc"
7154 [(set (reg CC_REGNUM)
7155 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7157 (set (match_operand:GPR 0 "register_operand" "=d")
7158 (neg:GPR (match_dup 1)))]
7159 "s390_match_ccmode (insn, CCAmode)"
7161 [(set_attr "op_type" "RR<E>")
7162 (set_attr "z10prop" "z10_super_c_E1")])
7165 (define_insn "*neg<mode>2_cconly"
7166 [(set (reg CC_REGNUM)
7167 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7169 (clobber (match_scratch:GPR 0 "=d"))]
7170 "s390_match_ccmode (insn, CCAmode)"
7172 [(set_attr "op_type" "RR<E>")
7173 (set_attr "z10prop" "z10_super_c_E1")])
7176 (define_insn "*neg<mode>2"
7177 [(set (match_operand:GPR 0 "register_operand" "=d")
7178 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7179 (clobber (reg:CC CC_REGNUM))]
7182 [(set_attr "op_type" "RR<E>")
7183 (set_attr "z10prop" "z10_super_c_E1")])
7185 (define_insn_and_split "*negdi2_31"
7186 [(set (match_operand:DI 0 "register_operand" "=d")
7187 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7188 (clobber (reg:CC CC_REGNUM))]
7191 "&& reload_completed"
7193 [(set (match_dup 2) (neg:SI (match_dup 3)))
7194 (clobber (reg:CC CC_REGNUM))])
7196 [(set (reg:CCAP CC_REGNUM)
7197 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7198 (set (match_dup 4) (neg:SI (match_dup 5)))])
7200 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7202 (label_ref (match_dup 6))))
7204 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7205 (clobber (reg:CC CC_REGNUM))])
7207 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7208 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7209 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7210 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7211 operands[6] = gen_label_rtx ();")
7214 ; neg(df|sf)2 instruction pattern(s).
7217 (define_expand "neg<mode>2"
7219 [(set (match_operand:BFP 0 "register_operand" "=f")
7220 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7221 (clobber (reg:CC CC_REGNUM))])]
7225 ; lcxbr, lcdbr, lcebr
7226 (define_insn "*neg<mode>2_cc"
7227 [(set (reg CC_REGNUM)
7228 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7229 (match_operand:BFP 2 "const0_operand" "")))
7230 (set (match_operand:BFP 0 "register_operand" "=f")
7231 (neg:BFP (match_dup 1)))]
7232 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7234 [(set_attr "op_type" "RRE")
7235 (set_attr "type" "fsimp<mode>")])
7237 ; lcxbr, lcdbr, lcebr
7238 (define_insn "*neg<mode>2_cconly"
7239 [(set (reg CC_REGNUM)
7240 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7241 (match_operand:BFP 2 "const0_operand" "")))
7242 (clobber (match_scratch:BFP 0 "=f"))]
7243 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7245 [(set_attr "op_type" "RRE")
7246 (set_attr "type" "fsimp<mode>")])
7249 (define_insn "*neg<mode>2_nocc"
7250 [(set (match_operand:FP 0 "register_operand" "=f")
7251 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7254 [(set_attr "op_type" "RRE")
7255 (set_attr "type" "fsimp<mode>")])
7257 ; lcxbr, lcdbr, lcebr
7258 (define_insn "*neg<mode>2"
7259 [(set (match_operand:BFP 0 "register_operand" "=f")
7260 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7261 (clobber (reg:CC CC_REGNUM))]
7264 [(set_attr "op_type" "RRE")
7265 (set_attr "type" "fsimp<mode>")])
7269 ;;- Absolute value instructions.
7273 ; abs(di|si)2 instruction pattern(s).
7276 (define_insn "*absdi2_sign_cc"
7277 [(set (reg CC_REGNUM)
7278 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7279 (match_operand:SI 1 "register_operand" "d") 0)
7280 (const_int 32)) (const_int 32)))
7282 (set (match_operand:DI 0 "register_operand" "=d")
7283 (abs:DI (sign_extend:DI (match_dup 1))))]
7284 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7286 [(set_attr "op_type" "RRE")
7287 (set_attr "z10prop" "z10_c")])
7289 (define_insn "*absdi2_sign"
7290 [(set (match_operand:DI 0 "register_operand" "=d")
7291 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7292 (clobber (reg:CC CC_REGNUM))]
7295 [(set_attr "op_type" "RRE")
7296 (set_attr "z10prop" "z10_c")])
7299 (define_insn "*abs<mode>2_cc"
7300 [(set (reg CC_REGNUM)
7301 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7303 (set (match_operand:GPR 0 "register_operand" "=d")
7304 (abs:GPR (match_dup 1)))]
7305 "s390_match_ccmode (insn, CCAmode)"
7307 [(set_attr "op_type" "RR<E>")
7308 (set_attr "z10prop" "z10_c")])
7311 (define_insn "*abs<mode>2_cconly"
7312 [(set (reg CC_REGNUM)
7313 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7315 (clobber (match_scratch:GPR 0 "=d"))]
7316 "s390_match_ccmode (insn, CCAmode)"
7318 [(set_attr "op_type" "RR<E>")
7319 (set_attr "z10prop" "z10_c")])
7322 (define_insn "abs<mode>2"
7323 [(set (match_operand:GPR 0 "register_operand" "=d")
7324 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7325 (clobber (reg:CC CC_REGNUM))]
7328 [(set_attr "op_type" "RR<E>")
7329 (set_attr "z10prop" "z10_c")])
7332 ; abs(df|sf)2 instruction pattern(s).
7335 (define_expand "abs<mode>2"
7337 [(set (match_operand:BFP 0 "register_operand" "=f")
7338 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7339 (clobber (reg:CC CC_REGNUM))])]
7343 ; lpxbr, lpdbr, lpebr
7344 (define_insn "*abs<mode>2_cc"
7345 [(set (reg CC_REGNUM)
7346 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7347 (match_operand:BFP 2 "const0_operand" "")))
7348 (set (match_operand:BFP 0 "register_operand" "=f")
7349 (abs:BFP (match_dup 1)))]
7350 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7352 [(set_attr "op_type" "RRE")
7353 (set_attr "type" "fsimp<mode>")])
7355 ; lpxbr, lpdbr, lpebr
7356 (define_insn "*abs<mode>2_cconly"
7357 [(set (reg CC_REGNUM)
7358 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7359 (match_operand:BFP 2 "const0_operand" "")))
7360 (clobber (match_scratch:BFP 0 "=f"))]
7361 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7363 [(set_attr "op_type" "RRE")
7364 (set_attr "type" "fsimp<mode>")])
7367 (define_insn "*abs<mode>2_nocc"
7368 [(set (match_operand:FP 0 "register_operand" "=f")
7369 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7372 [(set_attr "op_type" "RRE")
7373 (set_attr "type" "fsimp<mode>")])
7375 ; lpxbr, lpdbr, lpebr
7376 (define_insn "*abs<mode>2"
7377 [(set (match_operand:BFP 0 "register_operand" "=f")
7378 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7379 (clobber (reg:CC CC_REGNUM))]
7382 [(set_attr "op_type" "RRE")
7383 (set_attr "type" "fsimp<mode>")])
7387 ;;- Negated absolute value instructions
7394 (define_insn "*negabsdi2_sign_cc"
7395 [(set (reg CC_REGNUM)
7396 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7397 (match_operand:SI 1 "register_operand" "d") 0)
7398 (const_int 32)) (const_int 32))))
7400 (set (match_operand:DI 0 "register_operand" "=d")
7401 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7402 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7404 [(set_attr "op_type" "RRE")
7405 (set_attr "z10prop" "z10_c")])
7407 (define_insn "*negabsdi2_sign"
7408 [(set (match_operand:DI 0 "register_operand" "=d")
7409 (neg:DI (abs:DI (sign_extend:DI
7410 (match_operand:SI 1 "register_operand" "d")))))
7411 (clobber (reg:CC CC_REGNUM))]
7414 [(set_attr "op_type" "RRE")
7415 (set_attr "z10prop" "z10_c")])
7418 (define_insn "*negabs<mode>2_cc"
7419 [(set (reg CC_REGNUM)
7420 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7422 (set (match_operand:GPR 0 "register_operand" "=d")
7423 (neg:GPR (abs:GPR (match_dup 1))))]
7424 "s390_match_ccmode (insn, CCAmode)"
7426 [(set_attr "op_type" "RR<E>")
7427 (set_attr "z10prop" "z10_c")])
7430 (define_insn "*negabs<mode>2_cconly"
7431 [(set (reg CC_REGNUM)
7432 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7434 (clobber (match_scratch:GPR 0 "=d"))]
7435 "s390_match_ccmode (insn, CCAmode)"
7437 [(set_attr "op_type" "RR<E>")
7438 (set_attr "z10prop" "z10_c")])
7441 (define_insn "*negabs<mode>2"
7442 [(set (match_operand:GPR 0 "register_operand" "=d")
7443 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7444 (clobber (reg:CC CC_REGNUM))]
7447 [(set_attr "op_type" "RR<E>")
7448 (set_attr "z10prop" "z10_c")])
7454 ; lnxbr, lndbr, lnebr
7455 (define_insn "*negabs<mode>2_cc"
7456 [(set (reg CC_REGNUM)
7457 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7458 (match_operand:BFP 2 "const0_operand" "")))
7459 (set (match_operand:BFP 0 "register_operand" "=f")
7460 (neg:BFP (abs:BFP (match_dup 1))))]
7461 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7463 [(set_attr "op_type" "RRE")
7464 (set_attr "type" "fsimp<mode>")])
7466 ; lnxbr, lndbr, lnebr
7467 (define_insn "*negabs<mode>2_cconly"
7468 [(set (reg CC_REGNUM)
7469 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7470 (match_operand:BFP 2 "const0_operand" "")))
7471 (clobber (match_scratch:BFP 0 "=f"))]
7472 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7474 [(set_attr "op_type" "RRE")
7475 (set_attr "type" "fsimp<mode>")])
7478 (define_insn "*negabs<mode>2_nocc"
7479 [(set (match_operand:FP 0 "register_operand" "=f")
7480 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7483 [(set_attr "op_type" "RRE")
7484 (set_attr "type" "fsimp<mode>")])
7486 ; lnxbr, lndbr, lnebr
7487 (define_insn "*negabs<mode>2"
7488 [(set (match_operand:BFP 0 "register_operand" "=f")
7489 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7490 (clobber (reg:CC CC_REGNUM))]
7493 [(set_attr "op_type" "RRE")
7494 (set_attr "type" "fsimp<mode>")])
7497 ;;- Square root instructions.
7501 ; sqrt(df|sf)2 instruction pattern(s).
7504 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7505 (define_insn "sqrt<mode>2"
7506 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7507 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7512 [(set_attr "op_type" "RRE,RXE")
7513 (set_attr "type" "fsqrt<mode>")])
7517 ;;- One complement instructions.
7521 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7524 (define_expand "one_cmpl<mode>2"
7526 [(set (match_operand:INT 0 "register_operand" "")
7527 (xor:INT (match_operand:INT 1 "register_operand" "")
7529 (clobber (reg:CC CC_REGNUM))])]
7535 ;; Find leftmost bit instructions.
7538 (define_expand "clzdi2"
7539 [(set (match_operand:DI 0 "register_operand" "=d")
7540 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7541 "TARGET_EXTIMM && TARGET_ZARCH"
7543 rtx insn, clz_equal;
7544 rtx wide_reg = gen_reg_rtx (TImode);
7545 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7547 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7549 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7551 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7552 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7557 (define_insn "clztidi2"
7558 [(set (match_operand:TI 0 "register_operand" "=d")
7562 (xor:DI (match_operand:DI 1 "register_operand" "d")
7563 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7564 (subreg:SI (clz:DI (match_dup 1)) 4))))
7567 (zero_extend:TI (clz:DI (match_dup 1)))))
7568 (clobber (reg:CC CC_REGNUM))]
7569 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7570 == (unsigned HOST_WIDE_INT) 1 << 63
7571 && TARGET_EXTIMM && TARGET_ZARCH"
7573 [(set_attr "op_type" "RRE")])
7577 ;;- Rotate instructions.
7581 ; rotl(di|si)3 instruction pattern(s).
7585 (define_insn "rotl<mode>3"
7586 [(set (match_operand:GPR 0 "register_operand" "=d")
7587 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7588 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7591 [(set_attr "op_type" "RSE")
7592 (set_attr "atype" "reg")
7593 (set_attr "z10prop" "z10_super_E1")])
7596 (define_insn "*rotl<mode>3_and"
7597 [(set (match_operand:GPR 0 "register_operand" "=d")
7598 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7599 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7600 (match_operand:SI 3 "const_int_operand" "n"))))]
7601 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7603 [(set_attr "op_type" "RSE")
7604 (set_attr "atype" "reg")
7605 (set_attr "z10prop" "z10_super_E1")])
7609 ;;- Shift instructions.
7613 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7614 ; Left shifts and logical right shifts
7616 (define_expand "<shift><mode>3"
7617 [(set (match_operand:DSI 0 "register_operand" "")
7618 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7619 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7624 (define_insn "*<shift>di3_31"
7625 [(set (match_operand:DI 0 "register_operand" "=d")
7626 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7627 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7630 [(set_attr "op_type" "RS")
7631 (set_attr "atype" "reg")
7632 (set_attr "z196prop" "z196_cracked")])
7634 ; sll, srl, sllg, srlg, sllk, srlk
7635 (define_insn "*<shift><mode>3"
7636 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7637 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7638 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7641 s<lr>l<g>\t%0,<1>%Y2
7642 s<lr>l<gk>\t%0,%1,%Y2"
7643 [(set_attr "op_type" "RS<E>,RSY")
7644 (set_attr "atype" "reg,reg")
7645 (set_attr "cpu_facility" "*,z196")
7646 (set_attr "z10prop" "z10_super_E1,*")])
7649 (define_insn "*<shift>di3_31_and"
7650 [(set (match_operand:DI 0 "register_operand" "=d")
7651 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7652 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7653 (match_operand:SI 3 "const_int_operand" "n"))))]
7654 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7656 [(set_attr "op_type" "RS")
7657 (set_attr "atype" "reg")])
7659 ; sll, srl, sllg, srlg, sllk, srlk
7660 (define_insn "*<shift><mode>3_and"
7661 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7662 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7663 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7664 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7665 "(INTVAL (operands[3]) & 63) == 63"
7667 s<lr>l<g>\t%0,<1>%Y2
7668 s<lr>l<gk>\t%0,%1,%Y2"
7669 [(set_attr "op_type" "RS<E>,RSY")
7670 (set_attr "atype" "reg,reg")
7671 (set_attr "cpu_facility" "*,z196")
7672 (set_attr "z10prop" "z10_super_E1,*")])
7675 ; ashr(di|si)3 instruction pattern(s).
7676 ; Arithmetic right shifts
7678 (define_expand "ashr<mode>3"
7680 [(set (match_operand:DSI 0 "register_operand" "")
7681 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7682 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7683 (clobber (reg:CC CC_REGNUM))])]
7687 (define_insn "*ashrdi3_cc_31"
7688 [(set (reg CC_REGNUM)
7689 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7690 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7692 (set (match_operand:DI 0 "register_operand" "=d")
7693 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7694 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7696 [(set_attr "op_type" "RS")
7697 (set_attr "atype" "reg")])
7699 (define_insn "*ashrdi3_cconly_31"
7700 [(set (reg CC_REGNUM)
7701 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7702 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7704 (clobber (match_scratch:DI 0 "=d"))]
7705 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7707 [(set_attr "op_type" "RS")
7708 (set_attr "atype" "reg")])
7710 (define_insn "*ashrdi3_31"
7711 [(set (match_operand:DI 0 "register_operand" "=d")
7712 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7713 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7714 (clobber (reg:CC CC_REGNUM))]
7717 [(set_attr "op_type" "RS")
7718 (set_attr "atype" "reg")])
7721 (define_insn "*ashr<mode>3_cc"
7722 [(set (reg CC_REGNUM)
7723 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7724 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7726 (set (match_operand:GPR 0 "register_operand" "=d,d")
7727 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7728 "s390_match_ccmode(insn, CCSmode)"
7732 [(set_attr "op_type" "RS<E>,RSY")
7733 (set_attr "atype" "reg,reg")
7734 (set_attr "cpu_facility" "*,z196")
7735 (set_attr "z10prop" "z10_super_E1,*")])
7738 (define_insn "*ashr<mode>3_cconly"
7739 [(set (reg CC_REGNUM)
7740 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7741 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7743 (clobber (match_scratch:GPR 0 "=d,d"))]
7744 "s390_match_ccmode(insn, CCSmode)"
7748 [(set_attr "op_type" "RS<E>,RSY")
7749 (set_attr "atype" "reg,reg")
7750 (set_attr "cpu_facility" "*,z196")
7751 (set_attr "z10prop" "z10_super_E1,*")])
7754 (define_insn "*ashr<mode>3"
7755 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7756 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7757 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7758 (clobber (reg:CC CC_REGNUM))]
7763 [(set_attr "op_type" "RS<E>,RSY")
7764 (set_attr "atype" "reg,reg")
7765 (set_attr "cpu_facility" "*,z196")
7766 (set_attr "z10prop" "z10_super_E1,*")])
7769 ; shift pattern with implicit ANDs
7771 (define_insn "*ashrdi3_cc_31_and"
7772 [(set (reg CC_REGNUM)
7773 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7774 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7775 (match_operand:SI 3 "const_int_operand" "n")))
7777 (set (match_operand:DI 0 "register_operand" "=d")
7778 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7779 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7780 && (INTVAL (operands[3]) & 63) == 63"
7782 [(set_attr "op_type" "RS")
7783 (set_attr "atype" "reg")])
7785 (define_insn "*ashrdi3_cconly_31_and"
7786 [(set (reg CC_REGNUM)
7787 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7788 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7789 (match_operand:SI 3 "const_int_operand" "n")))
7791 (clobber (match_scratch:DI 0 "=d"))]
7792 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7793 && (INTVAL (operands[3]) & 63) == 63"
7795 [(set_attr "op_type" "RS")
7796 (set_attr "atype" "reg")])
7798 (define_insn "*ashrdi3_31_and"
7799 [(set (match_operand:DI 0 "register_operand" "=d")
7800 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7801 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7802 (match_operand:SI 3 "const_int_operand" "n"))))
7803 (clobber (reg:CC CC_REGNUM))]
7804 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7806 [(set_attr "op_type" "RS")
7807 (set_attr "atype" "reg")])
7810 (define_insn "*ashr<mode>3_cc_and"
7811 [(set (reg CC_REGNUM)
7812 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7813 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7814 (match_operand:SI 3 "const_int_operand" "n,n")))
7816 (set (match_operand:GPR 0 "register_operand" "=d,d")
7817 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7818 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7822 [(set_attr "op_type" "RS<E>,RSY")
7823 (set_attr "atype" "reg,reg")
7824 (set_attr "cpu_facility" "*,z196")
7825 (set_attr "z10prop" "z10_super_E1,*")])
7828 (define_insn "*ashr<mode>3_cconly_and"
7829 [(set (reg CC_REGNUM)
7830 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7831 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7832 (match_operand:SI 3 "const_int_operand" "n,n")))
7834 (clobber (match_scratch:GPR 0 "=d,d"))]
7835 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7839 [(set_attr "op_type" "RS<E>,RSY")
7840 (set_attr "atype" "reg,reg")
7841 (set_attr "cpu_facility" "*,z196")
7842 (set_attr "z10prop" "z10_super_E1,*")])
7845 (define_insn "*ashr<mode>3_and"
7846 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7847 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7848 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7849 (match_operand:SI 3 "const_int_operand" "n,n"))))
7850 (clobber (reg:CC CC_REGNUM))]
7851 "(INTVAL (operands[3]) & 63) == 63"
7855 [(set_attr "op_type" "RS<E>,RSY")
7856 (set_attr "atype" "reg,reg")
7857 (set_attr "cpu_facility" "*,z196")
7858 (set_attr "z10prop" "z10_super_E1,*")])
7862 ;; Branch instruction patterns.
7865 (define_expand "cbranch<mode>4"
7867 (if_then_else (match_operator 0 "comparison_operator"
7868 [(match_operand:GPR 1 "register_operand" "")
7869 (match_operand:GPR 2 "general_operand" "")])
7870 (label_ref (match_operand 3 "" ""))
7873 "s390_emit_jump (operands[3],
7874 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7877 (define_expand "cbranch<mode>4"
7879 (if_then_else (match_operator 0 "comparison_operator"
7880 [(match_operand:FP 1 "register_operand" "")
7881 (match_operand:FP 2 "general_operand" "")])
7882 (label_ref (match_operand 3 "" ""))
7885 "s390_emit_jump (operands[3],
7886 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7889 (define_expand "cbranchcc4"
7891 (if_then_else (match_operator 0 "s390_eqne_operator"
7892 [(match_operand 1 "cc_reg_operand" "")
7893 (match_operand 2 "const0_operand" "")])
7894 (label_ref (match_operand 3 "" ""))
7897 "s390_emit_jump (operands[3],
7898 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7904 ;;- Conditional jump instructions.
7907 (define_insn "*cjump_64"
7910 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7911 (label_ref (match_operand 0 "" ""))
7915 if (get_attr_length (insn) == 4)
7918 return "jg%C1\t%l0";
7920 [(set_attr "op_type" "RI")
7921 (set_attr "type" "branch")
7922 (set (attr "length")
7923 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7924 (const_int 4) (const_int 6)))])
7926 (define_insn "*cjump_31"
7929 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7930 (label_ref (match_operand 0 "" ""))
7934 gcc_assert (get_attr_length (insn) == 4);
7937 [(set_attr "op_type" "RI")
7938 (set_attr "type" "branch")
7939 (set (attr "length")
7940 (if_then_else (not (match_test "flag_pic"))
7941 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7942 (const_int 4) (const_int 6))
7943 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7944 (const_int 4) (const_int 8))))])
7946 (define_insn "*cjump_long"
7949 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7950 (match_operand 0 "address_operand" "ZQZR")
7954 if (get_attr_op_type (insn) == OP_TYPE_RR)
7959 [(set (attr "op_type")
7960 (if_then_else (match_operand 0 "register_operand" "")
7961 (const_string "RR") (const_string "RX")))
7962 (set_attr "type" "branch")
7963 (set_attr "atype" "agen")])
7967 ;;- Negated conditional jump instructions.
7970 (define_insn "*icjump_64"
7973 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7975 (label_ref (match_operand 0 "" ""))))]
7978 if (get_attr_length (insn) == 4)
7981 return "jg%D1\t%l0";
7983 [(set_attr "op_type" "RI")
7984 (set_attr "type" "branch")
7985 (set (attr "length")
7986 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7987 (const_int 4) (const_int 6)))])
7989 (define_insn "*icjump_31"
7992 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7994 (label_ref (match_operand 0 "" ""))))]
7997 gcc_assert (get_attr_length (insn) == 4);
8000 [(set_attr "op_type" "RI")
8001 (set_attr "type" "branch")
8002 (set (attr "length")
8003 (if_then_else (not (match_test "flag_pic"))
8004 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8005 (const_int 4) (const_int 6))
8006 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8007 (const_int 4) (const_int 8))))])
8009 (define_insn "*icjump_long"
8012 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8014 (match_operand 0 "address_operand" "ZQZR")))]
8017 if (get_attr_op_type (insn) == OP_TYPE_RR)
8022 [(set (attr "op_type")
8023 (if_then_else (match_operand 0 "register_operand" "")
8024 (const_string "RR") (const_string "RX")))
8025 (set_attr "type" "branch")
8026 (set_attr "atype" "agen")])
8029 ;;- Trap instructions.
8033 [(trap_if (const_int 1) (const_int 0))]
8036 [(set_attr "op_type" "RI")
8037 (set_attr "type" "branch")])
8039 (define_expand "ctrap<mode>4"
8040 [(trap_if (match_operator 0 "comparison_operator"
8041 [(match_operand:GPR 1 "register_operand" "")
8042 (match_operand:GPR 2 "general_operand" "")])
8043 (match_operand 3 "const0_operand" ""))]
8046 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8047 operands[1], operands[2]);
8048 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8052 (define_expand "ctrap<mode>4"
8053 [(trap_if (match_operator 0 "comparison_operator"
8054 [(match_operand:FP 1 "register_operand" "")
8055 (match_operand:FP 2 "general_operand" "")])
8056 (match_operand 3 "const0_operand" ""))]
8059 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8060 operands[1], operands[2]);
8061 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8065 (define_insn "condtrap"
8066 [(trap_if (match_operator 0 "s390_comparison"
8067 [(match_operand 1 "cc_reg_operand" "c")
8072 [(set_attr "op_type" "RI")
8073 (set_attr "type" "branch")])
8075 ; crt, cgrt, cit, cgit
8076 (define_insn "*cmp_and_trap_signed_int<mode>"
8077 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8078 [(match_operand:GPR 1 "register_operand" "d,d")
8079 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8085 [(set_attr "op_type" "RRF,RIE")
8086 (set_attr "type" "branch")
8087 (set_attr "z10prop" "z10_super_c,z10_super")])
8089 ; clrt, clgrt, clfit, clgit, clt, clgt
8090 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8091 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8092 [(match_operand:GPR 1 "register_operand" "d,d, d")
8093 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8100 [(set_attr "op_type" "RRF,RIE,RSY")
8101 (set_attr "type" "branch")
8102 (set_attr "z10prop" "z10_super_c,z10_super,*")
8103 (set_attr "cpu_facility" "z10,z10,zEC12")])
8106 (define_insn "*load_and_trap<mode>"
8107 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8110 (set (match_operand:GPR 1 "register_operand" "=d")
8114 [(set_attr "op_type" "RXY")])
8118 ;;- Loop instructions.
8120 ;; This is all complicated by the fact that since this is a jump insn
8121 ;; we must handle our own output reloads.
8125 ; This splitter will be matched by combine and has to add the 2 moves
8126 ; necessary to load the compare and the increment values into a
8127 ; register pair as needed by brxle.
8129 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8132 (match_operator 6 "s390_brx_operator"
8133 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8134 (match_operand:GPR 2 "general_operand" ""))
8135 (match_operand:GPR 3 "register_operand" "")])
8136 (label_ref (match_operand 0 "" ""))
8138 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8139 (plus:GPR (match_dup 1) (match_dup 2)))
8140 (clobber (match_scratch:GPR 5 ""))]
8143 "!reload_completed && !reload_in_progress"
8144 [(set (match_dup 7) (match_dup 2)) ; the increment
8145 (set (match_dup 8) (match_dup 3)) ; the comparison value
8146 (parallel [(set (pc)
8149 [(plus:GPR (match_dup 1) (match_dup 7))
8151 (label_ref (match_dup 0))
8154 (plus:GPR (match_dup 1) (match_dup 7)))
8155 (clobber (match_dup 5))
8156 (clobber (reg:CC CC_REGNUM))])]
8158 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8159 operands[7] = gen_lowpart (<GPR:MODE>mode,
8160 gen_highpart (word_mode, dreg));
8161 operands[8] = gen_lowpart (<GPR:MODE>mode,
8162 gen_lowpart (word_mode, dreg));
8167 (define_insn_and_split "*brxg_64bit"
8170 (match_operator 5 "s390_brx_operator"
8171 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8172 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8173 (subreg:DI (match_dup 2) 8)])
8174 (label_ref (match_operand 0 "" ""))
8176 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8177 (plus:DI (match_dup 1)
8178 (subreg:DI (match_dup 2) 0)))
8179 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8180 (clobber (reg:CC CC_REGNUM))]
8183 if (which_alternative != 0)
8185 else if (get_attr_length (insn) == 6)
8186 return "brx%E5g\t%1,%2,%l0";
8188 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8190 "&& reload_completed
8191 && (!REG_P (operands[3])
8192 || !rtx_equal_p (operands[1], operands[3]))"
8193 [(set (match_dup 4) (match_dup 1))
8194 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8195 (clobber (reg:CC CC_REGNUM))])
8196 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8197 (set (match_dup 3) (match_dup 4))
8198 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8199 (label_ref (match_dup 0))
8202 [(set_attr "op_type" "RIE")
8203 (set_attr "type" "branch")
8204 (set (attr "length")
8205 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8206 (const_int 6) (const_int 16)))])
8210 (define_insn_and_split "*brx_64bit"
8213 (match_operator 5 "s390_brx_operator"
8214 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8215 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8216 (subreg:SI (match_dup 2) 12)])
8217 (label_ref (match_operand 0 "" ""))
8219 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8220 (plus:SI (match_dup 1)
8221 (subreg:SI (match_dup 2) 4)))
8222 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8223 (clobber (reg:CC CC_REGNUM))]
8226 if (which_alternative != 0)
8228 else if (get_attr_length (insn) == 6)
8229 return "brx%C5\t%1,%2,%l0";
8231 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8233 "&& reload_completed
8234 && (!REG_P (operands[3])
8235 || !rtx_equal_p (operands[1], operands[3]))"
8236 [(set (match_dup 4) (match_dup 1))
8237 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8238 (clobber (reg:CC CC_REGNUM))])
8239 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8240 (set (match_dup 3) (match_dup 4))
8241 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8242 (label_ref (match_dup 0))
8245 [(set_attr "op_type" "RSI")
8246 (set_attr "type" "branch")
8247 (set (attr "length")
8248 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8249 (const_int 6) (const_int 14)))])
8253 (define_insn_and_split "*brx_31bit"
8256 (match_operator 5 "s390_brx_operator"
8257 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8258 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8259 (subreg:SI (match_dup 2) 4)])
8260 (label_ref (match_operand 0 "" ""))
8262 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8263 (plus:SI (match_dup 1)
8264 (subreg:SI (match_dup 2) 0)))
8265 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8266 (clobber (reg:CC CC_REGNUM))]
8267 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8269 if (which_alternative != 0)
8271 else if (get_attr_length (insn) == 6)
8272 return "brx%C5\t%1,%2,%l0";
8274 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8276 "&& reload_completed
8277 && (!REG_P (operands[3])
8278 || !rtx_equal_p (operands[1], operands[3]))"
8279 [(set (match_dup 4) (match_dup 1))
8280 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8281 (clobber (reg:CC CC_REGNUM))])
8282 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8283 (set (match_dup 3) (match_dup 4))
8284 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8285 (label_ref (match_dup 0))
8288 [(set_attr "op_type" "RSI")
8289 (set_attr "type" "branch")
8290 (set (attr "length")
8291 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8292 (const_int 6) (const_int 14)))])
8297 (define_expand "doloop_end"
8298 [(use (match_operand 0 "" "")) ; loop pseudo
8299 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8300 (use (match_operand 2 "" "")) ; max iterations
8301 (use (match_operand 3 "" "")) ; loop level
8302 (use (match_operand 4 "" "")) ; label
8303 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
8306 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8307 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8308 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8309 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8310 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8311 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8318 (define_insn_and_split "doloop_si64"
8321 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8323 (label_ref (match_operand 0 "" ""))
8325 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8326 (plus:SI (match_dup 1) (const_int -1)))
8327 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8328 (clobber (reg:CC CC_REGNUM))]
8331 if (which_alternative != 0)
8333 else if (get_attr_length (insn) == 4)
8334 return "brct\t%1,%l0";
8336 return "ahi\t%1,-1\;jgne\t%l0";
8338 "&& reload_completed
8339 && (! REG_P (operands[2])
8340 || ! rtx_equal_p (operands[1], operands[2]))"
8341 [(set (match_dup 3) (match_dup 1))
8342 (parallel [(set (reg:CCAN CC_REGNUM)
8343 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8345 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8346 (set (match_dup 2) (match_dup 3))
8347 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8348 (label_ref (match_dup 0))
8351 [(set_attr "op_type" "RI")
8352 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8353 ; hurt us in the (rare) case of ahi.
8354 (set_attr "z10prop" "z10_super_E1")
8355 (set_attr "type" "branch")
8356 (set (attr "length")
8357 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8358 (const_int 4) (const_int 10)))])
8360 (define_insn_and_split "doloop_si31"
8363 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8365 (label_ref (match_operand 0 "" ""))
8367 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8368 (plus:SI (match_dup 1) (const_int -1)))
8369 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8370 (clobber (reg:CC CC_REGNUM))]
8373 if (which_alternative != 0)
8375 else if (get_attr_length (insn) == 4)
8376 return "brct\t%1,%l0";
8380 "&& reload_completed
8381 && (! REG_P (operands[2])
8382 || ! rtx_equal_p (operands[1], operands[2]))"
8383 [(set (match_dup 3) (match_dup 1))
8384 (parallel [(set (reg:CCAN CC_REGNUM)
8385 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8387 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8388 (set (match_dup 2) (match_dup 3))
8389 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8390 (label_ref (match_dup 0))
8393 [(set_attr "op_type" "RI")
8394 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8395 ; hurt us in the (rare) case of ahi.
8396 (set_attr "z10prop" "z10_super_E1")
8397 (set_attr "type" "branch")
8398 (set (attr "length")
8399 (if_then_else (not (match_test "flag_pic"))
8400 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8401 (const_int 4) (const_int 6))
8402 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8403 (const_int 4) (const_int 8))))])
8405 (define_insn "*doloop_si_long"
8408 (ne (match_operand:SI 1 "register_operand" "d")
8410 (match_operand 0 "address_operand" "ZQZR")
8412 (set (match_operand:SI 2 "register_operand" "=1")
8413 (plus:SI (match_dup 1) (const_int -1)))
8414 (clobber (match_scratch:SI 3 "=X"))
8415 (clobber (reg:CC CC_REGNUM))]
8418 if (get_attr_op_type (insn) == OP_TYPE_RR)
8419 return "bctr\t%1,%0";
8421 return "bct\t%1,%a0";
8423 [(set (attr "op_type")
8424 (if_then_else (match_operand 0 "register_operand" "")
8425 (const_string "RR") (const_string "RX")))
8426 (set_attr "type" "branch")
8427 (set_attr "atype" "agen")
8428 (set_attr "z10prop" "z10_c")
8429 (set_attr "z196prop" "z196_cracked")])
8431 (define_insn_and_split "doloop_di"
8434 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8436 (label_ref (match_operand 0 "" ""))
8438 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8439 (plus:DI (match_dup 1) (const_int -1)))
8440 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8441 (clobber (reg:CC CC_REGNUM))]
8444 if (which_alternative != 0)
8446 else if (get_attr_length (insn) == 4)
8447 return "brctg\t%1,%l0";
8449 return "aghi\t%1,-1\;jgne\t%l0";
8451 "&& reload_completed
8452 && (! REG_P (operands[2])
8453 || ! rtx_equal_p (operands[1], operands[2]))"
8454 [(set (match_dup 3) (match_dup 1))
8455 (parallel [(set (reg:CCAN CC_REGNUM)
8456 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8458 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8459 (set (match_dup 2) (match_dup 3))
8460 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8461 (label_ref (match_dup 0))
8464 [(set_attr "op_type" "RI")
8465 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8466 ; hurt us in the (rare) case of ahi.
8467 (set_attr "z10prop" "z10_super_E1")
8468 (set_attr "type" "branch")
8469 (set (attr "length")
8470 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8471 (const_int 4) (const_int 10)))])
8474 ;;- Unconditional jump instructions.
8478 ; jump instruction pattern(s).
8481 (define_expand "jump"
8482 [(match_operand 0 "" "")]
8484 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8486 (define_insn "*jump64"
8487 [(set (pc) (label_ref (match_operand 0 "" "")))]
8490 if (get_attr_length (insn) == 4)
8495 [(set_attr "op_type" "RI")
8496 (set_attr "type" "branch")
8497 (set (attr "length")
8498 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8499 (const_int 4) (const_int 6)))])
8501 (define_insn "*jump31"
8502 [(set (pc) (label_ref (match_operand 0 "" "")))]
8505 gcc_assert (get_attr_length (insn) == 4);
8508 [(set_attr "op_type" "RI")
8509 (set_attr "type" "branch")
8510 (set (attr "length")
8511 (if_then_else (not (match_test "flag_pic"))
8512 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8513 (const_int 4) (const_int 6))
8514 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8515 (const_int 4) (const_int 8))))])
8518 ; indirect-jump instruction pattern(s).
8521 (define_insn "indirect_jump"
8522 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8525 if (get_attr_op_type (insn) == OP_TYPE_RR)
8530 [(set (attr "op_type")
8531 (if_then_else (match_operand 0 "register_operand" "")
8532 (const_string "RR") (const_string "RX")))
8533 (set_attr "type" "branch")
8534 (set_attr "atype" "agen")])
8537 ; casesi instruction pattern(s).
8540 (define_insn "casesi_jump"
8541 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8542 (use (label_ref (match_operand 1 "" "")))]
8545 if (get_attr_op_type (insn) == OP_TYPE_RR)
8550 [(set (attr "op_type")
8551 (if_then_else (match_operand 0 "register_operand" "")
8552 (const_string "RR") (const_string "RX")))
8553 (set_attr "type" "branch")
8554 (set_attr "atype" "agen")])
8556 (define_expand "casesi"
8557 [(match_operand:SI 0 "general_operand" "")
8558 (match_operand:SI 1 "general_operand" "")
8559 (match_operand:SI 2 "general_operand" "")
8560 (label_ref (match_operand 3 "" ""))
8561 (label_ref (match_operand 4 "" ""))]
8564 rtx index = gen_reg_rtx (SImode);
8565 rtx base = gen_reg_rtx (Pmode);
8566 rtx target = gen_reg_rtx (Pmode);
8568 emit_move_insn (index, operands[0]);
8569 emit_insn (gen_subsi3 (index, index, operands[1]));
8570 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8573 if (Pmode != SImode)
8574 index = convert_to_mode (Pmode, index, 1);
8575 if (GET_CODE (index) != REG)
8576 index = copy_to_mode_reg (Pmode, index);
8579 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8581 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8583 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8585 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8586 emit_move_insn (target, index);
8589 target = gen_rtx_PLUS (Pmode, base, target);
8590 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8597 ;;- Jump to subroutine.
8602 ; untyped call instruction pattern(s).
8605 ;; Call subroutine returning any type.
8606 (define_expand "untyped_call"
8607 [(parallel [(call (match_operand 0 "" "")
8609 (match_operand 1 "" "")
8610 (match_operand 2 "" "")])]
8615 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8617 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8619 rtx set = XVECEXP (operands[2], 0, i);
8620 emit_move_insn (SET_DEST (set), SET_SRC (set));
8623 /* The optimizer does not know that the call sets the function value
8624 registers we stored in the result block. We avoid problems by
8625 claiming that all hard registers are used and clobbered at this
8627 emit_insn (gen_blockage ());
8632 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8633 ;; all of memory. This blocks insns from being moved across this point.
8635 (define_insn "blockage"
8636 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8639 [(set_attr "type" "none")
8640 (set_attr "length" "0")])
8646 (define_expand "sibcall"
8647 [(call (match_operand 0 "" "")
8648 (match_operand 1 "" ""))]
8651 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8655 (define_insn "*sibcall_br"
8656 [(call (mem:QI (reg SIBCALL_REGNUM))
8657 (match_operand 0 "const_int_operand" "n"))]
8658 "SIBLING_CALL_P (insn)
8659 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8661 [(set_attr "op_type" "RR")
8662 (set_attr "type" "branch")
8663 (set_attr "atype" "agen")])
8665 (define_insn "*sibcall_brc"
8666 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8667 (match_operand 1 "const_int_operand" "n"))]
8668 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8670 [(set_attr "op_type" "RI")
8671 (set_attr "type" "branch")])
8673 (define_insn "*sibcall_brcl"
8674 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8675 (match_operand 1 "const_int_operand" "n"))]
8676 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8678 [(set_attr "op_type" "RIL")
8679 (set_attr "type" "branch")])
8682 ; sibcall_value patterns
8685 (define_expand "sibcall_value"
8686 [(set (match_operand 0 "" "")
8687 (call (match_operand 1 "" "")
8688 (match_operand 2 "" "")))]
8691 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8695 (define_insn "*sibcall_value_br"
8696 [(set (match_operand 0 "" "")
8697 (call (mem:QI (reg SIBCALL_REGNUM))
8698 (match_operand 1 "const_int_operand" "n")))]
8699 "SIBLING_CALL_P (insn)
8700 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8702 [(set_attr "op_type" "RR")
8703 (set_attr "type" "branch")
8704 (set_attr "atype" "agen")])
8706 (define_insn "*sibcall_value_brc"
8707 [(set (match_operand 0 "" "")
8708 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8709 (match_operand 2 "const_int_operand" "n")))]
8710 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8712 [(set_attr "op_type" "RI")
8713 (set_attr "type" "branch")])
8715 (define_insn "*sibcall_value_brcl"
8716 [(set (match_operand 0 "" "")
8717 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8718 (match_operand 2 "const_int_operand" "n")))]
8719 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8721 [(set_attr "op_type" "RIL")
8722 (set_attr "type" "branch")])
8726 ; call instruction pattern(s).
8729 (define_expand "call"
8730 [(call (match_operand 0 "" "")
8731 (match_operand 1 "" ""))
8732 (use (match_operand 2 "" ""))]
8735 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8736 gen_rtx_REG (Pmode, RETURN_REGNUM));
8740 (define_insn "*bras"
8741 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8742 (match_operand 1 "const_int_operand" "n"))
8743 (clobber (match_operand 2 "register_operand" "=r"))]
8744 "!SIBLING_CALL_P (insn)
8745 && TARGET_SMALL_EXEC
8746 && GET_MODE (operands[2]) == Pmode"
8748 [(set_attr "op_type" "RI")
8749 (set_attr "type" "jsr")
8750 (set_attr "z196prop" "z196_cracked")])
8752 (define_insn "*brasl"
8753 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8754 (match_operand 1 "const_int_operand" "n"))
8755 (clobber (match_operand 2 "register_operand" "=r"))]
8756 "!SIBLING_CALL_P (insn)
8758 && GET_MODE (operands[2]) == Pmode"
8760 [(set_attr "op_type" "RIL")
8761 (set_attr "type" "jsr")
8762 (set_attr "z196prop" "z196_cracked")])
8764 (define_insn "*basr"
8765 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8766 (match_operand 1 "const_int_operand" "n"))
8767 (clobber (match_operand 2 "register_operand" "=r"))]
8768 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8770 if (get_attr_op_type (insn) == OP_TYPE_RR)
8771 return "basr\t%2,%0";
8773 return "bas\t%2,%a0";
8775 [(set (attr "op_type")
8776 (if_then_else (match_operand 0 "register_operand" "")
8777 (const_string "RR") (const_string "RX")))
8778 (set_attr "type" "jsr")
8779 (set_attr "atype" "agen")
8780 (set_attr "z196prop" "z196_cracked")])
8783 ; call_value instruction pattern(s).
8786 (define_expand "call_value"
8787 [(set (match_operand 0 "" "")
8788 (call (match_operand 1 "" "")
8789 (match_operand 2 "" "")))
8790 (use (match_operand 3 "" ""))]
8793 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8794 gen_rtx_REG (Pmode, RETURN_REGNUM));
8798 (define_insn "*bras_r"
8799 [(set (match_operand 0 "" "")
8800 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8801 (match_operand:SI 2 "const_int_operand" "n")))
8802 (clobber (match_operand 3 "register_operand" "=r"))]
8803 "!SIBLING_CALL_P (insn)
8804 && TARGET_SMALL_EXEC
8805 && GET_MODE (operands[3]) == Pmode"
8807 [(set_attr "op_type" "RI")
8808 (set_attr "type" "jsr")
8809 (set_attr "z196prop" "z196_cracked")])
8811 (define_insn "*brasl_r"
8812 [(set (match_operand 0 "" "")
8813 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8814 (match_operand 2 "const_int_operand" "n")))
8815 (clobber (match_operand 3 "register_operand" "=r"))]
8816 "!SIBLING_CALL_P (insn)
8818 && GET_MODE (operands[3]) == Pmode"
8820 [(set_attr "op_type" "RIL")
8821 (set_attr "type" "jsr")
8822 (set_attr "z196prop" "z196_cracked")])
8824 (define_insn "*basr_r"
8825 [(set (match_operand 0 "" "")
8826 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8827 (match_operand 2 "const_int_operand" "n")))
8828 (clobber (match_operand 3 "register_operand" "=r"))]
8829 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8831 if (get_attr_op_type (insn) == OP_TYPE_RR)
8832 return "basr\t%3,%1";
8834 return "bas\t%3,%a1";
8836 [(set (attr "op_type")
8837 (if_then_else (match_operand 1 "register_operand" "")
8838 (const_string "RR") (const_string "RX")))
8839 (set_attr "type" "jsr")
8840 (set_attr "atype" "agen")
8841 (set_attr "z196prop" "z196_cracked")])
8844 ;;- Thread-local storage support.
8847 (define_expand "get_thread_pointer<mode>"
8848 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8852 (define_expand "set_thread_pointer<mode>"
8853 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8854 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8858 (define_insn "*set_tp"
8859 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8862 [(set_attr "type" "none")
8863 (set_attr "length" "0")])
8865 (define_insn "*tls_load_64"
8866 [(set (match_operand:DI 0 "register_operand" "=d")
8867 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8868 (match_operand:DI 2 "" "")]
8872 [(set_attr "op_type" "RXE")
8873 (set_attr "z10prop" "z10_fwd_A3")])
8875 (define_insn "*tls_load_31"
8876 [(set (match_operand:SI 0 "register_operand" "=d,d")
8877 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8878 (match_operand:SI 2 "" "")]
8884 [(set_attr "op_type" "RX,RXY")
8885 (set_attr "type" "load")
8886 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8888 (define_insn "*bras_tls"
8889 [(set (match_operand 0 "" "")
8890 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8891 (match_operand 2 "const_int_operand" "n")))
8892 (clobber (match_operand 3 "register_operand" "=r"))
8893 (use (match_operand 4 "" ""))]
8894 "!SIBLING_CALL_P (insn)
8895 && TARGET_SMALL_EXEC
8896 && GET_MODE (operands[3]) == Pmode"
8898 [(set_attr "op_type" "RI")
8899 (set_attr "type" "jsr")
8900 (set_attr "z196prop" "z196_cracked")])
8902 (define_insn "*brasl_tls"
8903 [(set (match_operand 0 "" "")
8904 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8905 (match_operand 2 "const_int_operand" "n")))
8906 (clobber (match_operand 3 "register_operand" "=r"))
8907 (use (match_operand 4 "" ""))]
8908 "!SIBLING_CALL_P (insn)
8910 && GET_MODE (operands[3]) == Pmode"
8912 [(set_attr "op_type" "RIL")
8913 (set_attr "type" "jsr")
8914 (set_attr "z196prop" "z196_cracked")])
8916 (define_insn "*basr_tls"
8917 [(set (match_operand 0 "" "")
8918 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8919 (match_operand 2 "const_int_operand" "n")))
8920 (clobber (match_operand 3 "register_operand" "=r"))
8921 (use (match_operand 4 "" ""))]
8922 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8924 if (get_attr_op_type (insn) == OP_TYPE_RR)
8925 return "basr\t%3,%1%J4";
8927 return "bas\t%3,%a1%J4";
8929 [(set (attr "op_type")
8930 (if_then_else (match_operand 1 "register_operand" "")
8931 (const_string "RR") (const_string "RX")))
8932 (set_attr "type" "jsr")
8933 (set_attr "atype" "agen")
8934 (set_attr "z196prop" "z196_cracked")])
8937 ;;- Atomic operations
8941 ; memory barrier patterns.
8944 (define_expand "mem_signal_fence"
8945 [(match_operand:SI 0 "const_int_operand")] ;; model
8948 /* The s390 memory model is strong enough not to require any
8949 barrier in order to synchronize a thread with itself. */
8953 (define_expand "mem_thread_fence"
8954 [(match_operand:SI 0 "const_int_operand")] ;; model
8957 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8958 enough not to require barriers of any kind. */
8959 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
8961 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8962 MEM_VOLATILE_P (mem) = 1;
8963 emit_insn (gen_mem_thread_fence_1 (mem));
8968 ; Although bcr is superscalar on Z10, this variant will never
8969 ; become part of an execution group.
8970 (define_insn "mem_thread_fence_1"
8971 [(set (match_operand:BLK 0 "" "")
8972 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8975 [(set_attr "op_type" "RR")])
8978 ; atomic load/store operations
8981 ; Atomic loads need not examine the memory model at all.
8982 (define_expand "atomic_load<mode>"
8983 [(match_operand:DINT 0 "register_operand") ;; output
8984 (match_operand:DINT 1 "memory_operand") ;; memory
8985 (match_operand:SI 2 "const_int_operand")] ;; model
8988 if (<MODE>mode == TImode)
8989 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
8990 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8991 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
8993 emit_move_insn (operands[0], operands[1]);
8997 ; Different from movdi_31 in that we want no splitters.
8998 (define_insn "atomic_loaddi_1"
8999 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9000 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9008 [(set_attr "op_type" "RS,RSY,RS,RSY")
9009 (set_attr "type" "lm,lm,floaddf,floaddf")])
9011 (define_insn "atomic_loadti_1"
9012 [(set (match_operand:TI 0 "register_operand" "=r")
9013 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9017 [(set_attr "op_type" "RXY")
9018 (set_attr "type" "other")])
9020 ; Atomic stores must(?) enforce sequential consistency.
9021 (define_expand "atomic_store<mode>"
9022 [(match_operand:DINT 0 "memory_operand") ;; memory
9023 (match_operand:DINT 1 "register_operand") ;; input
9024 (match_operand:SI 2 "const_int_operand")] ;; model
9027 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9029 if (<MODE>mode == TImode)
9030 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9031 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9032 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9034 emit_move_insn (operands[0], operands[1]);
9035 if (model == MEMMODEL_SEQ_CST)
9036 emit_insn (gen_mem_thread_fence (operands[2]));
9040 ; Different from movdi_31 in that we want no splitters.
9041 (define_insn "atomic_storedi_1"
9042 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9043 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9051 [(set_attr "op_type" "RS,RSY,RS,RSY")
9052 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9054 (define_insn "atomic_storeti_1"
9055 [(set (match_operand:TI 0 "memory_operand" "=RT")
9056 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9060 [(set_attr "op_type" "RXY")
9061 (set_attr "type" "other")])
9064 ; compare and swap patterns.
9067 (define_expand "atomic_compare_and_swap<mode>"
9068 [(match_operand:SI 0 "register_operand") ;; bool success output
9069 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9070 (match_operand:DGPR 2 "memory_operand") ;; memory
9071 (match_operand:DGPR 3 "register_operand") ;; expected intput
9072 (match_operand:DGPR 4 "register_operand") ;; newval intput
9073 (match_operand:SI 5 "const_int_operand") ;; is_weak
9074 (match_operand:SI 6 "const_int_operand") ;; success model
9075 (match_operand:SI 7 "const_int_operand")] ;; failure model
9078 rtx cc, cmp, output = operands[1];
9080 if (!register_operand (output, <MODE>mode))
9081 output = gen_reg_rtx (<MODE>mode);
9083 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9084 (output, operands[2], operands[3], operands[4]));
9086 /* We deliberately accept non-register operands in the predicate
9087 to ensure the write back to the output operand happens *before*
9088 the store-flags code below. This makes it easier for combine
9089 to merge the store-flags code with a potential test-and-branch
9090 pattern following (immediately!) afterwards. */
9091 if (output != operands[1])
9092 emit_move_insn (operands[1], output);
9094 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9095 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9096 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9100 (define_expand "atomic_compare_and_swap<mode>"
9101 [(match_operand:SI 0 "register_operand") ;; bool success output
9102 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9103 (match_operand:HQI 2 "memory_operand") ;; memory
9104 (match_operand:HQI 3 "general_operand") ;; expected intput
9105 (match_operand:HQI 4 "general_operand") ;; newval intput
9106 (match_operand:SI 5 "const_int_operand") ;; is_weak
9107 (match_operand:SI 6 "const_int_operand") ;; success model
9108 (match_operand:SI 7 "const_int_operand")] ;; failure model
9111 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9112 operands[3], operands[4], INTVAL (operands[5]));
9116 (define_expand "atomic_compare_and_swap<mode>_internal"
9118 [(set (match_operand:DGPR 0 "register_operand")
9119 (match_operand:DGPR 1 "memory_operand"))
9121 (unspec_volatile:DGPR
9123 (match_operand:DGPR 2 "register_operand")
9124 (match_operand:DGPR 3 "register_operand")]
9126 (set (reg:CCZ1 CC_REGNUM)
9127 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9131 (define_insn "*atomic_compare_and_swap<mode>_1"
9132 [(set (match_operand:TDI 0 "register_operand" "=r")
9133 (match_operand:TDI 1 "memory_operand" "+QS"))
9135 (unspec_volatile:TDI
9137 (match_operand:TDI 2 "register_operand" "0")
9138 (match_operand:TDI 3 "register_operand" "r")]
9140 (set (reg:CCZ1 CC_REGNUM)
9141 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9143 "c<td>sg\t%0,%3,%S1"
9144 [(set_attr "op_type" "RSY")
9145 (set_attr "type" "sem")])
9148 (define_insn "*atomic_compare_and_swapdi_2"
9149 [(set (match_operand:DI 0 "register_operand" "=r,r")
9150 (match_operand:DI 1 "memory_operand" "+Q,S"))
9154 (match_operand:DI 2 "register_operand" "0,0")
9155 (match_operand:DI 3 "register_operand" "r,r")]
9157 (set (reg:CCZ1 CC_REGNUM)
9158 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9163 [(set_attr "op_type" "RS,RSY")
9164 (set_attr "type" "sem")])
9167 (define_insn "*atomic_compare_and_swapsi_3"
9168 [(set (match_operand:SI 0 "register_operand" "=r,r")
9169 (match_operand:SI 1 "memory_operand" "+Q,S"))
9173 (match_operand:SI 2 "register_operand" "0,0")
9174 (match_operand:SI 3 "register_operand" "r,r")]
9176 (set (reg:CCZ1 CC_REGNUM)
9177 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9182 [(set_attr "op_type" "RS,RSY")
9183 (set_attr "type" "sem")])
9186 ; Other atomic instruction patterns.
9189 ; z196 load and add, xor, or and and instructions
9191 (define_expand "atomic_fetch_<atomic><mode>"
9192 [(match_operand:GPR 0 "register_operand") ;; val out
9194 (match_operand:GPR 1 "memory_operand") ;; memory
9195 (match_operand:GPR 2 "register_operand")) ;; val in
9196 (match_operand:SI 3 "const_int_operand")] ;; model
9199 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9200 (operands[0], operands[1], operands[2]));
9204 ; lan, lang, lao, laog, lax, laxg, laa, laag
9205 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9206 [(set (match_operand:GPR 0 "register_operand" "=d")
9207 (match_operand:GPR 1 "memory_operand" "+QS"))
9209 (unspec_volatile:GPR
9210 [(ATOMIC_Z196:GPR (match_dup 1)
9211 (match_operand:GPR 2 "general_operand" "d"))]
9213 (clobber (reg:CC CC_REGNUM))]
9215 "la<noxa><g>\t%0,%2,%1"
9216 [(set_attr "op_type" "RSY")
9217 (set_attr "type" "sem")])
9219 ;; For SImode and larger, the optabs.c code will do just fine in
9220 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9221 ;; better by expanding our own loop.
9223 (define_expand "atomic_<atomic><mode>"
9225 (match_operand:HQI 0 "memory_operand") ;; memory
9226 (match_operand:HQI 1 "general_operand")) ;; val in
9227 (match_operand:SI 2 "const_int_operand")] ;; model
9230 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9231 operands[1], false);
9235 (define_expand "atomic_fetch_<atomic><mode>"
9236 [(match_operand:HQI 0 "register_operand") ;; val out
9238 (match_operand:HQI 1 "memory_operand") ;; memory
9239 (match_operand:HQI 2 "general_operand")) ;; val in
9240 (match_operand:SI 3 "const_int_operand")] ;; model
9243 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9244 operands[2], false);
9248 (define_expand "atomic_<atomic>_fetch<mode>"
9249 [(match_operand:HQI 0 "register_operand") ;; val out
9251 (match_operand:HQI 1 "memory_operand") ;; memory
9252 (match_operand:HQI 2 "general_operand")) ;; val in
9253 (match_operand:SI 3 "const_int_operand")] ;; model
9256 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9261 (define_expand "atomic_exchange<mode>"
9262 [(match_operand:HQI 0 "register_operand") ;; val out
9263 (match_operand:HQI 1 "memory_operand") ;; memory
9264 (match_operand:HQI 2 "general_operand") ;; val in
9265 (match_operand:SI 3 "const_int_operand")] ;; model
9268 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9269 operands[2], false);
9274 ;;- Miscellaneous instructions.
9278 ; allocate stack instruction pattern(s).
9281 (define_expand "allocate_stack"
9282 [(match_operand 0 "general_operand" "")
9283 (match_operand 1 "general_operand" "")]
9286 rtx temp = gen_reg_rtx (Pmode);
9288 emit_move_insn (temp, s390_back_chain_rtx ());
9289 anti_adjust_stack (operands[1]);
9290 emit_move_insn (s390_back_chain_rtx (), temp);
9292 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9298 ; setjmp instruction pattern.
9301 (define_expand "builtin_setjmp_receiver"
9302 [(match_operand 0 "" "")]
9305 emit_insn (s390_load_got ());
9306 emit_use (pic_offset_table_rtx);
9310 ;; These patterns say how to save and restore the stack pointer. We need not
9311 ;; save the stack pointer at function level since we are careful to
9312 ;; preserve the backchain. At block level, we have to restore the backchain
9313 ;; when we restore the stack pointer.
9315 ;; For nonlocal gotos, we must save both the stack pointer and its
9316 ;; backchain and restore both. Note that in the nonlocal case, the
9317 ;; save area is a memory location.
9319 (define_expand "save_stack_function"
9320 [(match_operand 0 "general_operand" "")
9321 (match_operand 1 "general_operand" "")]
9325 (define_expand "restore_stack_function"
9326 [(match_operand 0 "general_operand" "")
9327 (match_operand 1 "general_operand" "")]
9331 (define_expand "restore_stack_block"
9332 [(match_operand 0 "register_operand" "")
9333 (match_operand 1 "register_operand" "")]
9336 rtx temp = gen_reg_rtx (Pmode);
9338 emit_move_insn (temp, s390_back_chain_rtx ());
9339 emit_move_insn (operands[0], operands[1]);
9340 emit_move_insn (s390_back_chain_rtx (), temp);
9345 (define_expand "save_stack_nonlocal"
9346 [(match_operand 0 "memory_operand" "")
9347 (match_operand 1 "register_operand" "")]
9350 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9352 /* Copy the backchain to the first word, sp to the second and the
9353 literal pool base to the third. */
9355 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9356 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9357 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9359 if (TARGET_BACKCHAIN)
9360 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9362 emit_move_insn (save_sp, operands[1]);
9363 emit_move_insn (save_bp, base);
9368 (define_expand "restore_stack_nonlocal"
9369 [(match_operand 0 "register_operand" "")
9370 (match_operand 1 "memory_operand" "")]
9373 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9374 rtx temp = NULL_RTX;
9376 /* Restore the backchain from the first word, sp from the second and the
9377 literal pool base from the third. */
9379 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9380 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9381 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9383 if (TARGET_BACKCHAIN)
9384 temp = force_reg (Pmode, save_bc);
9386 emit_move_insn (base, save_bp);
9387 emit_move_insn (operands[0], save_sp);
9390 emit_move_insn (s390_back_chain_rtx (), temp);
9396 (define_expand "exception_receiver"
9400 s390_set_has_landing_pad_p (true);
9405 ; nop instruction pattern(s).
9412 [(set_attr "op_type" "RR")
9413 (set_attr "z10prop" "z10_fr_E1")])
9419 [(set_attr "op_type" "RR")])
9423 ; Special literal pool access instruction pattern(s).
9426 (define_insn "*pool_entry"
9427 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9428 UNSPECV_POOL_ENTRY)]
9431 enum machine_mode mode = GET_MODE (PATTERN (insn));
9432 unsigned int align = GET_MODE_BITSIZE (mode);
9433 s390_output_pool_entry (operands[0], mode, align);
9436 [(set (attr "length")
9437 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9439 (define_insn "pool_align"
9440 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9441 UNSPECV_POOL_ALIGN)]
9444 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9446 (define_insn "pool_section_start"
9447 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9450 [(set_attr "length" "0")])
9452 (define_insn "pool_section_end"
9453 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9456 [(set_attr "length" "0")])
9458 (define_insn "main_base_31_small"
9459 [(set (match_operand 0 "register_operand" "=a")
9460 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9461 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9463 [(set_attr "op_type" "RR")
9464 (set_attr "type" "la")
9465 (set_attr "z196prop" "z196_cracked")])
9467 (define_insn "main_base_31_large"
9468 [(set (match_operand 0 "register_operand" "=a")
9469 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9470 (set (pc) (label_ref (match_operand 2 "" "")))]
9471 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9473 [(set_attr "op_type" "RI")
9474 (set_attr "z196prop" "z196_cracked")])
9476 (define_insn "main_base_64"
9477 [(set (match_operand 0 "register_operand" "=a")
9478 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9479 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9481 [(set_attr "op_type" "RIL")
9482 (set_attr "type" "larl")
9483 (set_attr "z10prop" "z10_fwd_A1")])
9485 (define_insn "main_pool"
9486 [(set (match_operand 0 "register_operand" "=a")
9487 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9488 "GET_MODE (operands[0]) == Pmode"
9493 (if_then_else (match_test "TARGET_CPU_ZARCH")
9494 (const_string "larl") (const_string "la")))])
9496 (define_insn "reload_base_31"
9497 [(set (match_operand 0 "register_operand" "=a")
9498 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9499 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9500 "basr\t%0,0\;la\t%0,%1-.(%0)"
9501 [(set_attr "length" "6")
9502 (set_attr "type" "la")
9503 (set_attr "z196prop" "z196_cracked")])
9505 (define_insn "reload_base_64"
9506 [(set (match_operand 0 "register_operand" "=a")
9507 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9508 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9510 [(set_attr "op_type" "RIL")
9511 (set_attr "type" "larl")
9512 (set_attr "z10prop" "z10_fwd_A1")])
9515 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9520 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9523 ;; Insns related to generating the function prologue and epilogue.
9527 (define_expand "prologue"
9528 [(use (const_int 0))]
9530 "s390_emit_prologue (); DONE;")
9532 (define_expand "epilogue"
9533 [(use (const_int 1))]
9535 "s390_emit_epilogue (false); DONE;")
9537 (define_expand "sibcall_epilogue"
9538 [(use (const_int 0))]
9540 "s390_emit_epilogue (true); DONE;")
9542 (define_insn "*return"
9544 (use (match_operand 0 "register_operand" "a"))]
9545 "GET_MODE (operands[0]) == Pmode"
9547 [(set_attr "op_type" "RR")
9548 (set_attr "type" "jsr")
9549 (set_attr "atype" "agen")])
9552 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9553 ;; pointer. This is used for compatibility.
9555 (define_expand "ptr_extend"
9556 [(set (match_operand:DI 0 "register_operand" "=r")
9557 (match_operand:SI 1 "register_operand" "r"))]
9560 emit_insn (gen_anddi3 (operands[0],
9561 gen_lowpart (DImode, operands[1]),
9562 GEN_INT (0x7fffffff)));
9566 ;; Instruction definition to expand eh_return macro to support
9567 ;; swapping in special linkage return addresses.
9569 (define_expand "eh_return"
9570 [(use (match_operand 0 "register_operand" ""))]
9573 s390_emit_tpf_eh_return (operands[0]);
9578 ; Stack Protector Patterns
9581 (define_expand "stack_protect_set"
9582 [(set (match_operand 0 "memory_operand" "")
9583 (match_operand 1 "memory_operand" ""))]
9586 #ifdef TARGET_THREAD_SSP_OFFSET
9588 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9589 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9592 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9594 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9599 (define_insn "stack_protect_set<mode>"
9600 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9601 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9603 "mvc\t%O0(%G0,%R0),%S1"
9604 [(set_attr "op_type" "SS")])
9606 (define_expand "stack_protect_test"
9607 [(set (reg:CC CC_REGNUM)
9608 (compare (match_operand 0 "memory_operand" "")
9609 (match_operand 1 "memory_operand" "")))
9610 (match_operand 2 "" "")]
9614 #ifdef TARGET_THREAD_SSP_OFFSET
9616 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9617 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9620 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9622 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9624 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9625 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9626 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9630 (define_insn "stack_protect_test<mode>"
9631 [(set (reg:CCZ CC_REGNUM)
9632 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9633 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9635 "clc\t%O0(%G0,%R0),%S1"
9636 [(set_attr "op_type" "SS")])
9638 ; This is used in s390_emit_prologue in order to prevent insns
9639 ; adjusting the stack pointer to be moved over insns writing stack
9640 ; slots using a copy of the stack pointer in a different register.
9641 (define_insn "stack_tie"
9642 [(set (match_operand:BLK 0 "memory_operand" "+m")
9643 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9646 [(set_attr "length" "0")])
9650 ; Data prefetch patterns
9653 (define_insn "prefetch"
9654 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9655 (match_operand:SI 1 "const_int_operand" " n,n")
9656 (match_operand:SI 2 "const_int_operand" " n,n"))]
9659 switch (which_alternative)
9662 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9664 if (larl_operand (operands[0], Pmode))
9665 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9668 /* This might be reached for symbolic operands with an odd
9669 addend. We simply omit the prefetch for such rare cases. */
9674 [(set_attr "type" "load,larl")
9675 (set_attr "op_type" "RXY,RIL")
9676 (set_attr "z10prop" "z10_super")
9677 (set_attr "z196prop" "z196_alone")])
9681 ; Byte swap instructions
9684 (define_insn "bswap<mode>2"
9685 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9686 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9691 [(set_attr "type" "*,load")
9692 (set_attr "op_type" "RRE,RXY")
9693 (set_attr "z10prop" "z10_super")])
9697 ; Population count instruction
9700 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9701 ; portions and stores the result in the corresponding bytes in op0.
9702 (define_insn "*popcount<mode>"
9703 [(set (match_operand:INT 0 "register_operand" "=d")
9704 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9705 (clobber (reg:CC CC_REGNUM))]
9708 [(set_attr "op_type" "RRE")])
9710 (define_expand "popcountdi2"
9712 (parallel [(set (match_operand:DI 0 "register_operand" "")
9713 (unspec:DI [(match_operand:DI 1 "register_operand")]
9715 (clobber (reg:CC CC_REGNUM))])
9717 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9719 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9720 (clobber (reg:CC CC_REGNUM))])
9723 (ashift:DI (match_dup 0) (const_int 16)))
9725 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9726 (clobber (reg:CC CC_REGNUM))])
9728 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9730 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9731 (clobber (reg:CC CC_REGNUM))])
9733 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9734 "TARGET_Z196 && TARGET_64BIT"
9735 "operands[2] = gen_reg_rtx (DImode);")
9737 (define_expand "popcountsi2"
9739 (parallel [(set (match_operand:SI 0 "register_operand" "")
9740 (unspec:SI [(match_operand:SI 1 "register_operand")]
9742 (clobber (reg:CC CC_REGNUM))])
9745 (ashift:SI (match_dup 0) (const_int 16)))
9747 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9748 (clobber (reg:CC CC_REGNUM))])
9750 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9752 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9753 (clobber (reg:CC CC_REGNUM))])
9755 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9757 "operands[2] = gen_reg_rtx (SImode);")
9759 (define_expand "popcounthi2"
9761 (parallel [(set (match_operand:HI 0 "register_operand" "")
9762 (unspec:HI [(match_operand:HI 1 "register_operand")]
9764 (clobber (reg:CC CC_REGNUM))])
9767 (ashift:SI (match_dup 0) (const_int 8)))
9769 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9770 (clobber (reg:CC CC_REGNUM))])
9772 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9774 "operands[2] = gen_reg_rtx (SImode);")
9776 (define_expand "popcountqi2"
9778 (parallel [(set (match_operand:QI 0 "register_operand" "")
9779 (unspec:QI [(match_operand:QI 1 "register_operand")]
9781 (clobber (reg:CC CC_REGNUM))])]
9786 ;;- Copy sign instructions
9789 (define_insn "copysign<mode>3"
9790 [(set (match_operand:FP 0 "register_operand" "=f")
9791 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9792 (match_operand:FP 2 "register_operand" "f")]
9796 [(set_attr "op_type" "RRF")
9797 (set_attr "type" "fsimp<mode>")])