1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; GOT/PLT and lt-relative accesses
94 ; TLS relocation specifiers
110 ; Stack Smashing Protector
114 ; Test Data Class (TDC)
126 UNSPEC_FPINT_NEARBYINT
135 UNSPEC_VEC_SMULT_EVEN
136 UNSPEC_VEC_UMULT_EVEN
150 UNSPEC_VEC_INSERT_AND_ZERO
151 UNSPEC_VEC_LOAD_BNDRY
156 UNSPEC_VEC_PACK_SATURATE
157 UNSPEC_VEC_PACK_SATURATE_CC
158 UNSPEC_VEC_PACK_SATURATE_GENCC
159 UNSPEC_VEC_PACK_UNSIGNED_SATURATE
160 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
161 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
173 UNSPEC_VEC_ADDEC_U128
178 UNSPEC_VEC_GFMSUM_128
179 UNSPEC_VEC_GFMSUM_ACCUM
180 UNSPEC_VEC_GFMSUM_ACCUM_128
199 UNSPEC_VEC_SUBEC_U128
233 ;; UNSPEC_VOLATILE usage
236 (define_c_enum "unspecv" [
258 ; Hotpatching (unremovable NOPs)
263 ; Transactional Execution support
273 ; Set and get floating point control register
282 ; Registers with special meaning
286 ; Sibling call register.
288 ; Literal pool base register.
290 ; Return address register.
292 ; Condition code register.
294 ; Thread local storage pointer register.
298 ; Hardware register names
302 ; General purpose registers
304 ; Floating point registers.
329 ;; PFPO GPR0 argument format
334 ; PFPO operation type
335 (PFPO_CONVERT 0x1000000)
337 (PFPO_OP_TYPE_SF 0x5)
338 (PFPO_OP_TYPE_DF 0x6)
339 (PFPO_OP_TYPE_TF 0x7)
340 (PFPO_OP_TYPE_SD 0x8)
341 (PFPO_OP_TYPE_DD 0x9)
342 (PFPO_OP_TYPE_TD 0xa)
343 ; Bitposition of operand types
344 (PFPO_OP0_TYPE_SHIFT 16)
345 (PFPO_OP1_TYPE_SHIFT 8)
348 ; Immediate operands for tbegin and tbeginc
349 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
350 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
352 ;; Instruction operand type as used in the Principles of Operation.
353 ;; Used to determine defaults for length and other attribute values.
355 (define_attr "op_type"
356 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
359 ;; Instruction type attribute used for scheduling.
361 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
362 cs,vs,store,sem,idiv,
363 imulhi,imulsi,imuldi,
364 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
365 floadtf,floaddf,floadsf,fstoredf,fstoresf,
366 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
367 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
369 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
370 itoftf, itofdf, itofsf, itofdd, itoftd,
371 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
372 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
374 (cond [(eq_attr "op_type" "NN") (const_string "other")
375 (eq_attr "op_type" "SS") (const_string "cs")]
376 (const_string "integer")))
378 ;; Another attribute used for scheduling purposes:
379 ;; agen: Instruction uses the address generation unit
380 ;; reg: Instruction does not use the agen unit
382 (define_attr "atype" "agen,reg"
383 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
385 (const_string "agen")))
387 ;; Properties concerning Z10 execution grouping and value forwarding.
388 ;; z10_super: instruction is superscalar.
389 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
390 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
391 ;; target register. It can forward this value to a second instruction that reads
392 ;; the same register if that second instruction is issued in the same group.
393 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
394 ;; instruction in the S pipe writes to the register, then the T instruction
395 ;; can immediately read the new value.
396 ;; z10_fr: union of Z10_fwd and z10_rec.
397 ;; z10_c: second operand of instruction is a register and read with complemented bits.
399 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
402 (define_attr "z10prop" "none,
403 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
404 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
406 z10_fr, z10_fr_A3, z10_fr_E1,
408 (const_string "none"))
410 ;; Properties concerning Z196 decoding
411 ;; z196_alone: must group alone
412 ;; z196_end: ends a group
413 ;; z196_cracked: instruction is cracked or expanded
414 (define_attr "z196prop" "none,
415 z196_alone, z196_ends,
417 (const_string "none"))
419 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
423 (define_attr "length" ""
424 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
425 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
429 ;; Processor type. This attribute must exactly match the processor_type
430 ;; enumeration in s390.h. The current machine description does not
431 ;; distinguish between g5 and g6, but there are differences between the two
432 ;; CPUs could in theory be modeled.
434 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
435 (const (symbol_ref "s390_tune_attr")))
437 (define_attr "cpu_facility"
438 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
439 (const_string "standard"))
441 (define_attr "enabled" ""
442 (cond [(eq_attr "cpu_facility" "standard")
445 (and (eq_attr "cpu_facility" "ieee")
446 (match_test "TARGET_CPU_IEEE_FLOAT"))
449 (and (eq_attr "cpu_facility" "zarch")
450 (match_test "TARGET_ZARCH"))
453 (and (eq_attr "cpu_facility" "longdisp")
454 (match_test "TARGET_LONG_DISPLACEMENT"))
457 (and (eq_attr "cpu_facility" "extimm")
458 (match_test "TARGET_EXTIMM"))
461 (and (eq_attr "cpu_facility" "dfp")
462 (match_test "TARGET_DFP"))
465 (and (eq_attr "cpu_facility" "cpu_zarch")
466 (match_test "TARGET_CPU_ZARCH"))
469 (and (eq_attr "cpu_facility" "z10")
470 (match_test "TARGET_Z10"))
473 (and (eq_attr "cpu_facility" "z196")
474 (match_test "TARGET_Z196"))
477 (and (eq_attr "cpu_facility" "zEC12")
478 (match_test "TARGET_ZEC12"))
481 (and (eq_attr "cpu_facility" "vec")
482 (match_test "TARGET_VX"))
486 ;; Pipeline description for z900. For lack of anything better,
487 ;; this description is also used for the g5 and g6.
490 ;; Pipeline description for z990, z9-109 and z9-ec.
493 ;; Pipeline description for z10
496 ;; Pipeline description for z196
499 ;; Pipeline description for zEC12
503 (include "predicates.md")
505 ;; Constraint definitions
506 (include "constraints.md")
513 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
515 ;; These mode iterators allow floating point patterns to be generated from the
517 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
518 (SD "TARGET_HARD_DFP")])
519 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
520 (define_mode_iterator BFP [TF DF SF])
521 (define_mode_iterator DFP [TD DD])
522 (define_mode_iterator DFP_ALL [TD DD SD])
523 (define_mode_iterator DSF [DF SF])
524 (define_mode_iterator SD_SF [SF SD])
525 (define_mode_iterator DD_DF [DF DD])
526 (define_mode_iterator TD_TF [TF TD])
528 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
529 ;; from the same template.
530 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
531 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
532 (define_mode_iterator DSI [DI SI])
533 (define_mode_iterator TDI [TI DI])
535 ;; These mode iterators allow :P to be used for patterns that operate on
536 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
537 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
539 ;; These macros refer to the actual word_mode of the configuration.
540 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
541 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
542 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
544 ;; Used by the umul pattern to express modes having half the size.
545 (define_mode_attr DWH [(TI "DI") (DI "SI")])
546 (define_mode_attr dwh [(TI "di") (DI "si")])
548 ;; This mode iterator allows the QI and HI patterns to be defined from
549 ;; the same template.
550 (define_mode_iterator HQI [HI QI])
552 ;; This mode iterator allows the integer patterns to be defined from the
554 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
555 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
557 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
558 ;; the same template.
559 (define_code_iterator SHIFT [ashift lshiftrt])
561 ;; This iterator allows r[ox]sbg to be defined with the same template
562 (define_code_iterator IXOR [ior xor])
564 ;; This iterator is used to expand the patterns for the nearest
565 ;; integer functions.
566 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
567 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
568 UNSPEC_FPINT_NEARBYINT])
569 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
570 (UNSPEC_FPINT_BTRUNC "btrunc")
571 (UNSPEC_FPINT_ROUND "round")
572 (UNSPEC_FPINT_CEIL "ceil")
573 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
574 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
575 (UNSPEC_FPINT_BTRUNC "5")
576 (UNSPEC_FPINT_ROUND "1")
577 (UNSPEC_FPINT_CEIL "6")
578 (UNSPEC_FPINT_NEARBYINT "0")])
580 ;; This iterator and attribute allow to combine most atomic operations.
581 (define_code_iterator ATOMIC [and ior xor plus minus mult])
582 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
583 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
584 (plus "add") (minus "sub") (mult "nand")])
585 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
587 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
588 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
589 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
591 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
592 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
594 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
596 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
597 ;; Likewise for "<RXe>".
598 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
599 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
601 ;; The decimal floating point variants of add, sub, div and mul support 3
602 ;; fp register operands. The following attributes allow to merge the bfp and
603 ;; dfp variants in a single insn definition.
605 ;; This attribute is used to set op_type accordingly.
606 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
607 (DD "RRR") (SD "RRR")])
609 ;; This attribute is used in the operand constraint list in order to have the
610 ;; first and the second operand match for bfp modes.
611 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
613 ;; This attribute is used to merge the scalar vector instructions into
614 ;; the FP patterns. For non-supported modes (all but DF) it expands
615 ;; to constraints which are supposed to be matched by an earlier
617 (define_mode_attr v0 [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")])
618 (define_mode_attr vf [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")])
619 (define_mode_attr vd [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")])
621 ;; This attribute is used in the operand list of the instruction to have an
622 ;; additional operand for the dfp instructions.
623 (define_mode_attr op1 [(TF "") (DF "") (SF "")
624 (TD "%1,") (DD "%1,") (SD "%1,")])
627 ;; This attribute is used in the operand constraint list
628 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
629 ;; TFmode values are represented by a fp register pair. Since the
630 ;; sign bit instructions only handle single source and target fp registers
631 ;; these instructions can only be used for TFmode values if the source and
632 ;; target operand uses the same fp register.
633 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
635 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
636 ;; This is used to disable the memory alternative in TFmode patterns.
637 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
639 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
640 ;; within instruction mnemonics.
641 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
643 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
644 ;; modes and to an empty string for bfp modes.
645 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
647 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
648 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
649 ;; version only operates on one register.
650 (define_mode_attr d0 [(DI "d") (SI "0")])
652 ;; In combination with d0 this allows to combine instructions of which the 31bit
653 ;; version only operates on one register. The DImode version needs an additional
654 ;; register for the assembler output.
655 (define_mode_attr 1 [(DI "%1,") (SI "")])
657 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
658 ;; 'ashift' and "srdl" in 'lshiftrt'.
659 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
661 ;; In SHIFT templates, this attribute holds the correct standard name for the
662 ;; pattern itself and the corresponding function calls.
663 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
665 ;; This attribute handles differences in the instruction 'type' and will result
666 ;; in "RRE" for DImode and "RR" for SImode.
667 (define_mode_attr E [(DI "E") (SI "")])
669 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
670 ;; to result in "RXY" for DImode and "RX" for SImode.
671 (define_mode_attr Y [(DI "Y") (SI "")])
673 ;; This attribute handles differences in the instruction 'type' and will result
674 ;; in "RSE" for TImode and "RS" for DImode.
675 (define_mode_attr TE [(TI "E") (DI "")])
677 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
678 ;; and "lcr" in SImode.
679 (define_mode_attr g [(DI "g") (SI "")])
681 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
682 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
683 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
684 ;; variant for long displacements.
685 (define_mode_attr y [(DI "g") (SI "y")])
687 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
688 ;; and "cds" in DImode.
689 (define_mode_attr tg [(TI "g") (DI "")])
691 ;; In TDI templates, a string like "c<d>sg".
692 (define_mode_attr td [(TI "d") (DI "")])
694 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
695 ;; and "cfdbr" in SImode.
696 (define_mode_attr gf [(DI "g") (SI "f")])
698 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
699 ;; and sllk for SI. This way it is possible to merge the new z196 SI
700 ;; 3 operands shift instructions into the existing patterns.
701 (define_mode_attr gk [(DI "g") (SI "k")])
703 ;; ICM mask required to load MODE value into the lowest subreg
704 ;; of a SImode register.
705 (define_mode_attr icm_lo [(HI "3") (QI "1")])
707 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
708 ;; HImode and "llgc" in QImode.
709 (define_mode_attr hc [(HI "h") (QI "c")])
711 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
713 (define_mode_attr DBL [(DI "TI") (SI "DI")])
715 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
716 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
717 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
719 ;; Maximum unsigned integer that fits in MODE.
720 (define_mode_attr max_uint [(HI "65535") (QI "255")])
722 ;; Start and end field computations for RISBG et al.
723 (define_mode_attr bfstart [(DI "s") (SI "t")])
724 (define_mode_attr bfend [(DI "e") (SI "f")])
726 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
727 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
729 ;; Allow return and simple_return to be defined from a single template.
730 (define_code_iterator ANY_RETURN [return simple_return])
734 ; Condition code modes generated by vector fp comparisons. These will
735 ; be used also in single element mode.
736 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
737 ; Used with VFCMP to expand part of the mnemonic
738 ; For fp we have a mismatch: eq in the insn name - e in asm
739 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
740 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
743 (include "vector.md")
746 ;;- Compare instructions.
749 ; Test-under-Mask instructions
751 (define_insn "*tmqi_mem"
752 [(set (reg CC_REGNUM)
753 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
754 (match_operand:QI 1 "immediate_operand" "n,n"))
755 (match_operand:QI 2 "immediate_operand" "n,n")))]
756 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
760 [(set_attr "op_type" "SI,SIY")
761 (set_attr "z10prop" "z10_super,z10_super")])
763 (define_insn "*tmdi_reg"
764 [(set (reg CC_REGNUM)
765 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
766 (match_operand:DI 1 "immediate_operand"
767 "N0HD0,N1HD0,N2HD0,N3HD0"))
768 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
770 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
771 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
777 [(set_attr "op_type" "RI")
778 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
780 (define_insn "*tmsi_reg"
781 [(set (reg CC_REGNUM)
782 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
783 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
784 (match_operand:SI 2 "immediate_operand" "n,n")))]
785 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
786 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
790 [(set_attr "op_type" "RI")
791 (set_attr "z10prop" "z10_super,z10_super")])
793 (define_insn "*tm<mode>_full"
794 [(set (reg CC_REGNUM)
795 (compare (match_operand:HQI 0 "register_operand" "d")
796 (match_operand:HQI 1 "immediate_operand" "n")))]
797 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
799 [(set_attr "op_type" "RI")
800 (set_attr "z10prop" "z10_super")])
804 ; Load-and-Test instructions
807 ; tst(di|si) instruction pattern(s).
809 (define_insn "*tstdi_sign"
810 [(set (reg CC_REGNUM)
814 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
815 (const_int 32)) (const_int 32))
816 (match_operand:DI 1 "const0_operand" "")))
817 (set (match_operand:DI 2 "register_operand" "=d,d")
818 (sign_extend:DI (match_dup 0)))]
819 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
822 [(set_attr "op_type" "RRE,RXY")
823 (set_attr "cpu_facility" "*,z10")
824 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
827 (define_insn "*tst<mode>_extimm"
828 [(set (reg CC_REGNUM)
829 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
830 (match_operand:GPR 1 "const0_operand" "")))
831 (set (match_operand:GPR 2 "register_operand" "=d,d")
833 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
837 [(set_attr "op_type" "RR<E>,RXY")
838 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
841 (define_insn "*tst<mode>_cconly_extimm"
842 [(set (reg CC_REGNUM)
843 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
844 (match_operand:GPR 1 "const0_operand" "")))
845 (clobber (match_scratch:GPR 2 "=X,d"))]
846 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
850 [(set_attr "op_type" "RR<E>,RXY")
851 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
853 (define_insn "*tstdi"
854 [(set (reg CC_REGNUM)
855 (compare (match_operand:DI 0 "register_operand" "d")
856 (match_operand:DI 1 "const0_operand" "")))
857 (set (match_operand:DI 2 "register_operand" "=d")
859 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
861 [(set_attr "op_type" "RRE")
862 (set_attr "z10prop" "z10_fr_E1")])
864 (define_insn "*tstsi"
865 [(set (reg CC_REGNUM)
866 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
867 (match_operand:SI 1 "const0_operand" "")))
868 (set (match_operand:SI 2 "register_operand" "=d,d,d")
870 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
875 [(set_attr "op_type" "RR,RS,RSY")
876 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
878 (define_insn "*tstsi_cconly"
879 [(set (reg CC_REGNUM)
880 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
881 (match_operand:SI 1 "const0_operand" "")))
882 (clobber (match_scratch:SI 2 "=X,d,d"))]
883 "s390_match_ccmode(insn, CCSmode)"
888 [(set_attr "op_type" "RR,RS,RSY")
889 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
891 (define_insn "*tstdi_cconly_31"
892 [(set (reg CC_REGNUM)
893 (compare (match_operand:DI 0 "register_operand" "d")
894 (match_operand:DI 1 "const0_operand" "")))]
895 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
897 [(set_attr "op_type" "RS")
898 (set_attr "atype" "reg")])
901 (define_insn "*tst<mode>_cconly2"
902 [(set (reg CC_REGNUM)
903 (compare (match_operand:GPR 0 "register_operand" "d")
904 (match_operand:GPR 1 "const0_operand" "")))]
905 "s390_match_ccmode(insn, CCSmode)"
907 [(set_attr "op_type" "RR<E>")
908 (set_attr "z10prop" "z10_fr_E1")])
910 ; tst(hi|qi) instruction pattern(s).
912 (define_insn "*tst<mode>CCT"
913 [(set (reg CC_REGNUM)
914 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
915 (match_operand:HQI 1 "const0_operand" "")))
916 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
918 "s390_match_ccmode(insn, CCTmode)"
921 icmy\t%2,<icm_lo>,%S0
923 [(set_attr "op_type" "RS,RSY,RI")
924 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
926 (define_insn "*tsthiCCT_cconly"
927 [(set (reg CC_REGNUM)
928 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
929 (match_operand:HI 1 "const0_operand" "")))
930 (clobber (match_scratch:HI 2 "=d,d,X"))]
931 "s390_match_ccmode(insn, CCTmode)"
936 [(set_attr "op_type" "RS,RSY,RI")
937 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
939 (define_insn "*tstqiCCT_cconly"
940 [(set (reg CC_REGNUM)
941 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
942 (match_operand:QI 1 "const0_operand" "")))]
943 "s390_match_ccmode(insn, CCTmode)"
948 [(set_attr "op_type" "SI,SIY,RI")
949 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
951 (define_insn "*tst<mode>"
952 [(set (reg CC_REGNUM)
953 (compare (match_operand:HQI 0 "s_operand" "Q,S")
954 (match_operand:HQI 1 "const0_operand" "")))
955 (set (match_operand:HQI 2 "register_operand" "=d,d")
957 "s390_match_ccmode(insn, CCSmode)"
960 icmy\t%2,<icm_lo>,%S0"
961 [(set_attr "op_type" "RS,RSY")
962 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
964 (define_insn "*tst<mode>_cconly"
965 [(set (reg CC_REGNUM)
966 (compare (match_operand:HQI 0 "s_operand" "Q,S")
967 (match_operand:HQI 1 "const0_operand" "")))
968 (clobber (match_scratch:HQI 2 "=d,d"))]
969 "s390_match_ccmode(insn, CCSmode)"
972 icmy\t%2,<icm_lo>,%S0"
973 [(set_attr "op_type" "RS,RSY")
974 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
977 ; Compare (equality) instructions
979 (define_insn "*cmpdi_cct"
980 [(set (reg CC_REGNUM)
981 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
982 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
983 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
990 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
991 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
993 (define_insn "*cmpsi_cct"
994 [(set (reg CC_REGNUM)
995 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
996 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
997 "s390_match_ccmode (insn, CCTmode)"
1005 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1006 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1008 ; Compare (signed) instructions
1010 (define_insn "*cmpdi_ccs_sign"
1011 [(set (reg CC_REGNUM)
1012 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1014 (match_operand:DI 0 "register_operand" "d, d,d")))]
1015 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1020 [(set_attr "op_type" "RRE,RXY,RIL")
1021 (set_attr "z10prop" "z10_c,*,*")
1022 (set_attr "type" "*,*,larl")])
1026 (define_insn "*cmpsi_ccs_sign"
1027 [(set (reg CC_REGNUM)
1028 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1029 (match_operand:SI 0 "register_operand" "d,d,d")))]
1030 "s390_match_ccmode(insn, CCSRmode)"
1035 [(set_attr "op_type" "RX,RXY,RIL")
1036 (set_attr "cpu_facility" "*,*,z10")
1037 (set_attr "type" "*,*,larl")
1038 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1040 (define_insn "*cmphi_ccs_z10"
1041 [(set (reg CC_REGNUM)
1042 (compare (match_operand:HI 0 "s_operand" "Q")
1043 (match_operand:HI 1 "immediate_operand" "K")))]
1044 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1046 [(set_attr "op_type" "SIL")
1047 (set_attr "z196prop" "z196_cracked")])
1049 (define_insn "*cmpdi_ccs_signhi_rl"
1050 [(set (reg CC_REGNUM)
1051 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
1052 (match_operand:GPR 0 "register_operand" "d,d")))]
1053 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1057 [(set_attr "op_type" "RXY,RIL")
1058 (set_attr "type" "*,larl")])
1060 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1061 (define_insn "*cmp<mode>_ccs"
1062 [(set (reg CC_REGNUM)
1063 (compare (match_operand:GPR 0 "nonimmediate_operand"
1065 (match_operand:GPR 1 "general_operand"
1066 "d,K,K,Os,R,T,b")))]
1067 "s390_match_ccmode(insn, CCSmode)"
1076 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1077 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
1078 (set_attr "type" "*,*,*,*,*,*,larl")
1079 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1082 ; Compare (unsigned) instructions
1084 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1085 [(set (reg CC_REGNUM)
1086 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1087 "larl_operand" "X")))
1088 (match_operand:SI 0 "register_operand" "d")))]
1089 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1091 [(set_attr "op_type" "RIL")
1092 (set_attr "type" "larl")
1093 (set_attr "z10prop" "z10_super")])
1096 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1097 [(set (reg CC_REGNUM)
1098 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1099 "larl_operand" "X")))
1100 (match_operand:GPR 0 "register_operand" "d")))]
1101 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1103 [(set_attr "op_type" "RIL")
1104 (set_attr "type" "larl")
1105 (set_attr "z10prop" "z10_super")])
1107 (define_insn "*cmpdi_ccu_zero"
1108 [(set (reg CC_REGNUM)
1109 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1111 (match_operand:DI 0 "register_operand" "d, d,d")))]
1112 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1117 [(set_attr "op_type" "RRE,RXY,RIL")
1118 (set_attr "cpu_facility" "*,*,z10")
1119 (set_attr "type" "*,*,larl")
1120 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1122 (define_insn "*cmpdi_ccu"
1123 [(set (reg CC_REGNUM)
1124 (compare (match_operand:DI 0 "nonimmediate_operand"
1125 "d, d,d,Q, d, Q,BQ")
1126 (match_operand:DI 1 "general_operand"
1127 "d,Op,b,D,RT,BQ,Q")))]
1128 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1137 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1138 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1139 (set_attr "type" "*,*,larl,*,*,*,*")
1140 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1142 (define_insn "*cmpsi_ccu"
1143 [(set (reg CC_REGNUM)
1144 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1145 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1146 "s390_match_ccmode (insn, CCUmode)"
1156 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1157 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1158 (set_attr "type" "*,*,larl,*,*,*,*,*")
1159 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1161 (define_insn "*cmphi_ccu"
1162 [(set (reg CC_REGNUM)
1163 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1164 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1165 "s390_match_ccmode (insn, CCUmode)
1166 && !register_operand (operands[1], HImode)"
1173 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1174 (set_attr "cpu_facility" "*,*,z10,*,*")
1175 (set_attr "z10prop" "*,*,z10_super,*,*")])
1177 (define_insn "*cmpqi_ccu"
1178 [(set (reg CC_REGNUM)
1179 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1180 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1181 "s390_match_ccmode (insn, CCUmode)
1182 && !register_operand (operands[1], QImode)"
1190 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1191 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1194 ; Block compare (CLC) instruction patterns.
1197 [(set (reg CC_REGNUM)
1198 (compare (match_operand:BLK 0 "memory_operand" "Q")
1199 (match_operand:BLK 1 "memory_operand" "Q")))
1200 (use (match_operand 2 "const_int_operand" "n"))]
1201 "s390_match_ccmode (insn, CCUmode)
1202 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1203 "clc\t%O0(%2,%R0),%S1"
1204 [(set_attr "op_type" "SS")])
1207 [(set (reg CC_REGNUM)
1208 (compare (match_operand 0 "memory_operand" "")
1209 (match_operand 1 "memory_operand" "")))]
1211 && s390_match_ccmode (insn, CCUmode)
1212 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1213 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1215 [(set (match_dup 0) (match_dup 1))
1216 (use (match_dup 2))])]
1218 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1219 operands[0] = adjust_address (operands[0], BLKmode, 0);
1220 operands[1] = adjust_address (operands[1], BLKmode, 0);
1222 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1223 operands[0], operands[1]);
1224 operands[0] = SET_DEST (PATTERN (curr_insn));
1228 ; (TF|DF|SF|TD|DD|SD) instructions
1230 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1231 (define_insn "*cmp<mode>_ccs_0"
1232 [(set (reg CC_REGNUM)
1233 (compare (match_operand:FP 0 "register_operand" "f")
1234 (match_operand:FP 1 "const0_operand" "")))]
1235 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1236 "lt<xde><bt>r\t%0,%0"
1237 [(set_attr "op_type" "RRE")
1238 (set_attr "type" "fsimp<mode>")])
1240 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1241 (define_insn "*cmp<mode>_ccs"
1242 [(set (reg CC_REGNUM)
1243 (compare (match_operand:FP 0 "register_operand" "f,f")
1244 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1245 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1249 [(set_attr "op_type" "RRE,RXE")
1250 (set_attr "type" "fsimp<mode>")])
1252 ; wfcedbs, wfchdbs, wfchedbs
1253 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1254 [(set (reg:VFCMP CC_REGNUM)
1255 (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1256 (match_operand:DF 1 "register_operand" "v")))
1257 (clobber (match_scratch:V2DI 2 "=v"))]
1258 "TARGET_Z13 && TARGET_HARD_FLOAT"
1259 "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1260 [(set_attr "op_type" "VRR")])
1262 ; Compare and Branch instructions
1264 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1265 ; The following instructions do a complementary access of their second
1266 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1267 (define_insn "*cmp_and_br_signed_<mode>"
1269 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1270 [(match_operand:GPR 1 "register_operand" "d,d")
1271 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1272 (label_ref (match_operand 3 "" ""))
1274 (clobber (reg:CC CC_REGNUM))]
1275 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1277 if (get_attr_length (insn) == 6)
1278 return which_alternative ?
1279 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1281 return which_alternative ?
1282 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1284 [(set_attr "op_type" "RIE")
1285 (set_attr "type" "branch")
1286 (set_attr "z10prop" "z10_super_c,z10_super")
1287 (set (attr "length")
1288 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1289 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1290 ; 10 byte for cgr/jg
1292 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1293 ; The following instructions do a complementary access of their second
1294 ; operand (z10 only): clrj, clgrj, clr, clgr
1295 (define_insn "*cmp_and_br_unsigned_<mode>"
1297 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1298 [(match_operand:GPR 1 "register_operand" "d,d")
1299 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1300 (label_ref (match_operand 3 "" ""))
1302 (clobber (reg:CC CC_REGNUM))]
1303 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1305 if (get_attr_length (insn) == 6)
1306 return which_alternative ?
1307 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1309 return which_alternative ?
1310 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1312 [(set_attr "op_type" "RIE")
1313 (set_attr "type" "branch")
1314 (set_attr "z10prop" "z10_super_c,z10_super")
1315 (set (attr "length")
1316 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1317 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1318 ; 10 byte for clgr/jg
1320 ; And now the same two patterns as above but with a negated CC mask.
1322 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1323 ; The following instructions do a complementary access of their second
1324 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1325 (define_insn "*icmp_and_br_signed_<mode>"
1327 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1328 [(match_operand:GPR 1 "register_operand" "d,d")
1329 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1331 (label_ref (match_operand 3 "" ""))))
1332 (clobber (reg:CC CC_REGNUM))]
1333 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1335 if (get_attr_length (insn) == 6)
1336 return which_alternative ?
1337 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1339 return which_alternative ?
1340 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1342 [(set_attr "op_type" "RIE")
1343 (set_attr "type" "branch")
1344 (set_attr "z10prop" "z10_super_c,z10_super")
1345 (set (attr "length")
1346 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1347 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1348 ; 10 byte for cgr/jg
1350 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1351 ; The following instructions do a complementary access of their second
1352 ; operand (z10 only): clrj, clgrj, clr, clgr
1353 (define_insn "*icmp_and_br_unsigned_<mode>"
1355 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1356 [(match_operand:GPR 1 "register_operand" "d,d")
1357 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1359 (label_ref (match_operand 3 "" ""))))
1360 (clobber (reg:CC CC_REGNUM))]
1361 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1363 if (get_attr_length (insn) == 6)
1364 return which_alternative ?
1365 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1367 return which_alternative ?
1368 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1370 [(set_attr "op_type" "RIE")
1371 (set_attr "type" "branch")
1372 (set_attr "z10prop" "z10_super_c,z10_super")
1373 (set (attr "length")
1374 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1375 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1376 ; 10 byte for clgr/jg
1379 ;;- Move instructions.
1383 ; movti instruction pattern(s).
1386 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1387 ; for TImode (use double-int for the calculations)
1388 (define_insn "movti"
1389 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o")
1390 (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
1404 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1405 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1406 (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1409 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1410 (match_operand:TI 1 "general_operand" ""))]
1411 "TARGET_ZARCH && reload_completed
1412 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1413 [(set (match_dup 2) (match_dup 4))
1414 (set (match_dup 3) (match_dup 5))]
1416 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1417 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1418 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1419 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1423 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1424 (match_operand:TI 1 "general_operand" ""))]
1425 "TARGET_ZARCH && reload_completed
1426 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1427 [(set (match_dup 2) (match_dup 4))
1428 (set (match_dup 3) (match_dup 5))]
1430 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1431 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1432 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1433 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1436 ; Use part of the TImode target reg to perform the address
1437 ; calculation. If the TImode value is supposed to be copied into a VR
1438 ; this splitter is not necessary.
1440 [(set (match_operand:TI 0 "register_operand" "")
1441 (match_operand:TI 1 "memory_operand" ""))]
1442 "TARGET_ZARCH && reload_completed
1443 && !VECTOR_REG_P (operands[0])
1444 && !s_operand (operands[1], VOIDmode)"
1445 [(set (match_dup 0) (match_dup 1))]
1447 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1448 addr = gen_lowpart (Pmode, addr);
1449 s390_load_address (addr, XEXP (operands[1], 0));
1450 operands[1] = replace_equiv_address (operands[1], addr);
1454 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1455 ; For the higher order bits we do simply a DImode move while the
1456 ; second part is done via vec extract. Both will end up as vlgvg.
1458 [(set (match_operand:TI 0 "register_operand" "")
1459 (match_operand:TI 1 "register_operand" ""))]
1460 "TARGET_VX && reload_completed
1461 && GENERAL_REG_P (operands[0])
1462 && VECTOR_REG_P (operands[1])"
1463 [(set (match_dup 2) (match_dup 4))
1464 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1465 UNSPEC_VEC_EXTRACT))]
1467 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1468 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1469 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1470 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1474 ; Patterns used for secondary reloads
1477 ; z10 provides move instructions accepting larl memory operands.
1478 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1479 ; These patterns are also used for unaligned SI and DI accesses.
1481 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1482 [(parallel [(match_operand:ALL 0 "memory_operand" "")
1483 (match_operand:ALL 1 "register_operand" "=d")
1484 (match_operand:P 2 "register_operand" "=&a")])]
1487 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1491 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1492 [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1493 (match_operand:ALL 1 "memory_operand" "")
1494 (match_operand:P 2 "register_operand" "=a")])]
1497 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1501 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1502 [(parallel [(match_operand:P 0 "register_operand" "=d")
1503 (match_operand:P 1 "larl_operand" "")
1504 (match_operand:P 2 "register_operand" "=a")])]
1507 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1511 ; Handles loading a PLUS (load address) expression
1513 (define_expand "reload<mode>_plus"
1514 [(parallel [(match_operand:P 0 "register_operand" "=a")
1515 (match_operand:P 1 "s390_plus_operand" "")
1516 (match_operand:P 2 "register_operand" "=&a")])]
1519 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1523 ; Not all the indirect memory access instructions support the full
1524 ; format (long disp + index + base). So whenever a move from/to such
1525 ; an address is required and the instruction cannot deal with it we do
1526 ; a load address into a scratch register first and use this as the new
1528 ; This in particular is used for:
1529 ; - non-offsetable memory accesses for multiword moves
1530 ; - full vector reg moves with long displacements
1532 (define_expand "reload<mode>_la_in"
1533 [(parallel [(match_operand 0 "register_operand" "")
1534 (match_operand 1 "" "")
1535 (match_operand:P 2 "register_operand" "=&a")])]
1538 gcc_assert (MEM_P (operands[1]));
1539 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1540 operands[1] = replace_equiv_address (operands[1], operands[2]);
1541 emit_move_insn (operands[0], operands[1]);
1545 (define_expand "reload<mode>_la_out"
1546 [(parallel [(match_operand 0 "" "")
1547 (match_operand 1 "register_operand" "")
1548 (match_operand:P 2 "register_operand" "=&a")])]
1551 gcc_assert (MEM_P (operands[0]));
1552 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1553 operands[0] = replace_equiv_address (operands[0], operands[2]);
1554 emit_move_insn (operands[0], operands[1]);
1558 (define_expand "reload<mode>_PIC_addr"
1559 [(parallel [(match_operand 0 "register_operand" "=d")
1560 (match_operand 1 "larl_operand" "")
1561 (match_operand:P 2 "register_operand" "=a")])]
1564 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1565 emit_move_insn (operands[0], new_rtx);
1569 ; movdi instruction pattern(s).
1572 (define_expand "movdi"
1573 [(set (match_operand:DI 0 "general_operand" "")
1574 (match_operand:DI 1 "general_operand" ""))]
1577 /* Handle symbolic constants. */
1579 && (SYMBOLIC_CONST (operands[1])
1580 || (GET_CODE (operands[1]) == PLUS
1581 && XEXP (operands[1], 0) == pic_offset_table_rtx
1582 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1583 emit_symbolic_move (operands);
1586 (define_insn "*movdi_larl"
1587 [(set (match_operand:DI 0 "register_operand" "=d")
1588 (match_operand:DI 1 "larl_operand" "X"))]
1590 && !FP_REG_P (operands[0])"
1592 [(set_attr "op_type" "RIL")
1593 (set_attr "type" "larl")
1594 (set_attr "z10prop" "z10_super_A1")])
1596 (define_insn "*movdi_64"
1597 [(set (match_operand:DI 0 "nonimmediate_operand"
1598 "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
1599 (match_operand:DI 1 "general_operand"
1600 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
1635 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1636 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1637 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1638 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1640 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1641 z10,*,*,*,*,*,longdisp,*,longdisp,
1642 z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1643 (set_attr "z10prop" "z10_fwd_A1,
1672 [(set (match_operand:DI 0 "register_operand" "")
1673 (match_operand:DI 1 "register_operand" ""))]
1674 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1675 [(set (match_dup 2) (match_dup 3))
1676 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1677 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1678 "operands[2] = gen_lowpart (SImode, operands[0]);
1679 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1682 [(set (match_operand:DI 0 "register_operand" "")
1683 (match_operand:DI 1 "register_operand" ""))]
1684 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1685 && dead_or_set_p (insn, operands[1])"
1686 [(set (match_dup 3) (match_dup 2))
1687 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1688 (set (match_dup 4) (match_dup 2))]
1689 "operands[2] = gen_lowpart (SImode, operands[1]);
1690 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1693 [(set (match_operand:DI 0 "register_operand" "")
1694 (match_operand:DI 1 "register_operand" ""))]
1695 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1696 && !dead_or_set_p (insn, operands[1])"
1697 [(set (match_dup 3) (match_dup 2))
1698 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1699 (set (match_dup 4) (match_dup 2))
1700 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1701 "operands[2] = gen_lowpart (SImode, operands[1]);
1702 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1704 (define_insn "*movdi_31"
1705 [(set (match_operand:DI 0 "nonimmediate_operand"
1706 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1707 (match_operand:DI 1 "general_operand"
1708 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1723 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1724 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1725 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1727 ; For a load from a symbol ref we can use one of the target registers
1728 ; together with larl to load the address.
1730 [(set (match_operand:DI 0 "register_operand" "")
1731 (match_operand:DI 1 "memory_operand" ""))]
1732 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1733 && larl_operand (XEXP (operands[1], 0), SImode)"
1734 [(set (match_dup 2) (match_dup 3))
1735 (set (match_dup 0) (match_dup 1))]
1737 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1738 operands[3] = XEXP (operands[1], 0);
1739 operands[1] = replace_equiv_address (operands[1], operands[2]);
1743 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1744 (match_operand:DI 1 "general_operand" ""))]
1745 "!TARGET_ZARCH && reload_completed
1746 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1747 [(set (match_dup 2) (match_dup 4))
1748 (set (match_dup 3) (match_dup 5))]
1750 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1751 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1752 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1753 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1757 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1758 (match_operand:DI 1 "general_operand" ""))]
1759 "!TARGET_ZARCH && reload_completed
1760 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1761 [(set (match_dup 2) (match_dup 4))
1762 (set (match_dup 3) (match_dup 5))]
1764 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1765 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1766 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1767 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1771 [(set (match_operand:DI 0 "register_operand" "")
1772 (match_operand:DI 1 "memory_operand" ""))]
1773 "!TARGET_ZARCH && reload_completed
1774 && !FP_REG_P (operands[0])
1775 && !s_operand (operands[1], VOIDmode)"
1776 [(set (match_dup 0) (match_dup 1))]
1778 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1779 s390_load_address (addr, XEXP (operands[1], 0));
1780 operands[1] = replace_equiv_address (operands[1], addr);
1784 [(set (match_operand:DI 0 "register_operand" "")
1785 (mem:DI (match_operand 1 "address_operand" "")))]
1787 && !FP_REG_P (operands[0])
1788 && GET_CODE (operands[1]) == SYMBOL_REF
1789 && CONSTANT_POOL_ADDRESS_P (operands[1])
1790 && get_pool_mode (operands[1]) == DImode
1791 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1792 [(set (match_dup 0) (match_dup 2))]
1793 "operands[2] = get_pool_constant (operands[1]);")
1795 (define_insn "*la_64"
1796 [(set (match_operand:DI 0 "register_operand" "=d,d")
1797 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1802 [(set_attr "op_type" "RX,RXY")
1803 (set_attr "type" "la")
1804 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1808 [(set (match_operand:DI 0 "register_operand" "")
1809 (match_operand:QI 1 "address_operand" ""))
1810 (clobber (reg:CC CC_REGNUM))])]
1812 && preferred_la_operand_p (operands[1], const0_rtx)"
1813 [(set (match_dup 0) (match_dup 1))]
1817 [(set (match_operand:DI 0 "register_operand" "")
1818 (match_operand:DI 1 "register_operand" ""))
1821 (plus:DI (match_dup 0)
1822 (match_operand:DI 2 "nonmemory_operand" "")))
1823 (clobber (reg:CC CC_REGNUM))])]
1825 && !reg_overlap_mentioned_p (operands[0], operands[2])
1826 && preferred_la_operand_p (operands[1], operands[2])"
1827 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1831 ; movsi instruction pattern(s).
1834 (define_expand "movsi"
1835 [(set (match_operand:SI 0 "general_operand" "")
1836 (match_operand:SI 1 "general_operand" ""))]
1839 /* Handle symbolic constants. */
1841 && (SYMBOLIC_CONST (operands[1])
1842 || (GET_CODE (operands[1]) == PLUS
1843 && XEXP (operands[1], 0) == pic_offset_table_rtx
1844 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1845 emit_symbolic_move (operands);
1848 (define_insn "*movsi_larl"
1849 [(set (match_operand:SI 0 "register_operand" "=d")
1850 (match_operand:SI 1 "larl_operand" "X"))]
1851 "!TARGET_64BIT && TARGET_CPU_ZARCH
1852 && !FP_REG_P (operands[0])"
1854 [(set_attr "op_type" "RIL")
1855 (set_attr "type" "larl")
1856 (set_attr "z10prop" "z10_fwd_A1")])
1858 (define_insn "*movsi_zarch"
1859 [(set (match_operand:SI 0 "nonimmediate_operand"
1860 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
1861 (match_operand:SI 1 "general_operand"
1862 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
1895 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1896 RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1897 (set_attr "type" "*,
1921 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1922 vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1923 (set_attr "z10prop" "z10_fwd_A1,
1948 (define_insn "*movsi_esa"
1949 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
1950 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
1966 [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
1967 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
1968 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
1970 (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
1974 [(set (match_operand:SI 0 "register_operand" "")
1975 (mem:SI (match_operand 1 "address_operand" "")))]
1976 "!FP_REG_P (operands[0])
1977 && GET_CODE (operands[1]) == SYMBOL_REF
1978 && CONSTANT_POOL_ADDRESS_P (operands[1])
1979 && get_pool_mode (operands[1]) == SImode
1980 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1981 [(set (match_dup 0) (match_dup 2))]
1982 "operands[2] = get_pool_constant (operands[1]);")
1984 (define_insn "*la_31"
1985 [(set (match_operand:SI 0 "register_operand" "=d,d")
1986 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1987 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1991 [(set_attr "op_type" "RX,RXY")
1992 (set_attr "type" "la")
1993 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1997 [(set (match_operand:SI 0 "register_operand" "")
1998 (match_operand:QI 1 "address_operand" ""))
1999 (clobber (reg:CC CC_REGNUM))])]
2001 && preferred_la_operand_p (operands[1], const0_rtx)"
2002 [(set (match_dup 0) (match_dup 1))]
2006 [(set (match_operand:SI 0 "register_operand" "")
2007 (match_operand:SI 1 "register_operand" ""))
2010 (plus:SI (match_dup 0)
2011 (match_operand:SI 2 "nonmemory_operand" "")))
2012 (clobber (reg:CC CC_REGNUM))])]
2014 && !reg_overlap_mentioned_p (operands[0], operands[2])
2015 && preferred_la_operand_p (operands[1], operands[2])"
2016 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2019 (define_insn "*la_31_and"
2020 [(set (match_operand:SI 0 "register_operand" "=d,d")
2021 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
2022 (const_int 2147483647)))]
2027 [(set_attr "op_type" "RX,RXY")
2028 (set_attr "type" "la")
2029 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2031 (define_insn_and_split "*la_31_and_cc"
2032 [(set (match_operand:SI 0 "register_operand" "=d")
2033 (and:SI (match_operand:QI 1 "address_operand" "p")
2034 (const_int 2147483647)))
2035 (clobber (reg:CC CC_REGNUM))]
2038 "&& reload_completed"
2040 (and:SI (match_dup 1) (const_int 2147483647)))]
2042 [(set_attr "op_type" "RX")
2043 (set_attr "type" "la")])
2045 (define_insn "force_la_31"
2046 [(set (match_operand:SI 0 "register_operand" "=d,d")
2047 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
2048 (use (const_int 0))]
2053 [(set_attr "op_type" "RX")
2054 (set_attr "type" "la")
2055 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2058 ; movhi instruction pattern(s).
2061 (define_expand "movhi"
2062 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2063 (match_operand:HI 1 "general_operand" ""))]
2066 /* Make it explicit that loading a register from memory
2067 always sign-extends (at least) to SImode. */
2068 if (optimize && can_create_pseudo_p ()
2069 && register_operand (operands[0], VOIDmode)
2070 && GET_CODE (operands[1]) == MEM)
2072 rtx tmp = gen_reg_rtx (SImode);
2073 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2074 emit_insn (gen_rtx_SET (tmp, ext));
2075 operands[1] = gen_lowpart (HImode, tmp);
2079 (define_insn "*movhi"
2080 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
2081 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
2099 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2100 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2101 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
2102 (set_attr "z10prop" "z10_fr_E1,
2110 z10_super,*,*,*,*,*,*")])
2113 [(set (match_operand:HI 0 "register_operand" "")
2114 (mem:HI (match_operand 1 "address_operand" "")))]
2115 "GET_CODE (operands[1]) == SYMBOL_REF
2116 && CONSTANT_POOL_ADDRESS_P (operands[1])
2117 && get_pool_mode (operands[1]) == HImode
2118 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2119 [(set (match_dup 0) (match_dup 2))]
2120 "operands[2] = get_pool_constant (operands[1]);")
2123 ; movqi instruction pattern(s).
2126 (define_expand "movqi"
2127 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2128 (match_operand:QI 1 "general_operand" ""))]
2131 /* On z/Architecture, zero-extending from memory to register
2132 is just as fast as a QImode load. */
2133 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2134 && register_operand (operands[0], VOIDmode)
2135 && GET_CODE (operands[1]) == MEM)
2137 rtx tmp = gen_reg_rtx (DImode);
2138 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2139 emit_insn (gen_rtx_SET (tmp, ext));
2140 operands[1] = gen_lowpart (QImode, tmp);
2144 (define_insn "*movqi"
2145 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
2146 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
2164 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2165 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2166 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
2167 (set_attr "z10prop" "z10_fr_E1,
2178 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2179 (mem:QI (match_operand 1 "address_operand" "")))]
2180 "GET_CODE (operands[1]) == SYMBOL_REF
2181 && CONSTANT_POOL_ADDRESS_P (operands[1])
2182 && get_pool_mode (operands[1]) == QImode
2183 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2184 [(set (match_dup 0) (match_dup 2))]
2185 "operands[2] = get_pool_constant (operands[1]);")
2188 ; movstrictqi instruction pattern(s).
2191 (define_insn "*movstrictqi"
2192 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2193 (match_operand:QI 1 "memory_operand" "R,T"))]
2198 [(set_attr "op_type" "RX,RXY")
2199 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2202 ; movstricthi instruction pattern(s).
2205 (define_insn "*movstricthi"
2206 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2207 (match_operand:HI 1 "memory_operand" "Q,S"))
2208 (clobber (reg:CC CC_REGNUM))]
2213 [(set_attr "op_type" "RS,RSY")
2214 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2217 ; movstrictsi instruction pattern(s).
2220 (define_insn "movstrictsi"
2221 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2222 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2229 [(set_attr "op_type" "RR,RX,RXY,RRE")
2230 (set_attr "type" "lr,load,load,*")
2231 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2234 ; mov(tf|td) instruction pattern(s).
2237 (define_expand "mov<mode>"
2238 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2239 (match_operand:TD_TF 1 "general_operand" ""))]
2243 (define_insn "*mov<mode>_64"
2244 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2245 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2256 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2257 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2258 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2260 (define_insn "*mov<mode>_31"
2261 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2262 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2269 [(set_attr "op_type" "RRE,RRE,*,*")
2270 (set_attr "type" "fsimptf,fsimptf,*,*")
2271 (set_attr "cpu_facility" "z196,*,*,*")])
2273 ; TFmode in GPRs splitters
2276 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2277 (match_operand:TD_TF 1 "general_operand" ""))]
2278 "TARGET_ZARCH && reload_completed
2279 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2280 [(set (match_dup 2) (match_dup 4))
2281 (set (match_dup 3) (match_dup 5))]
2283 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2284 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2285 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2286 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2290 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2291 (match_operand:TD_TF 1 "general_operand" ""))]
2292 "TARGET_ZARCH && reload_completed
2293 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2294 [(set (match_dup 2) (match_dup 4))
2295 (set (match_dup 3) (match_dup 5))]
2297 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2298 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2299 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2300 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2304 [(set (match_operand:TD_TF 0 "register_operand" "")
2305 (match_operand:TD_TF 1 "memory_operand" ""))]
2306 "TARGET_ZARCH && reload_completed
2307 && GENERAL_REG_P (operands[0])
2308 && !s_operand (operands[1], VOIDmode)"
2309 [(set (match_dup 0) (match_dup 1))]
2311 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2312 addr = gen_lowpart (Pmode, addr);
2313 s390_load_address (addr, XEXP (operands[1], 0));
2314 operands[1] = replace_equiv_address (operands[1], addr);
2317 ; TFmode in BFPs splitters
2320 [(set (match_operand:TD_TF 0 "register_operand" "")
2321 (match_operand:TD_TF 1 "memory_operand" ""))]
2322 "reload_completed && offsettable_memref_p (operands[1])
2323 && FP_REG_P (operands[0])"
2324 [(set (match_dup 2) (match_dup 4))
2325 (set (match_dup 3) (match_dup 5))]
2327 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2329 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2331 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2332 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2336 [(set (match_operand:TD_TF 0 "memory_operand" "")
2337 (match_operand:TD_TF 1 "register_operand" ""))]
2338 "reload_completed && offsettable_memref_p (operands[0])
2339 && FP_REG_P (operands[1])"
2340 [(set (match_dup 2) (match_dup 4))
2341 (set (match_dup 3) (match_dup 5))]
2343 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2344 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2345 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2347 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2352 ; mov(df|dd) instruction pattern(s).
2355 (define_expand "mov<mode>"
2356 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2357 (match_operand:DD_DF 1 "general_operand" ""))]
2361 (define_insn "*mov<mode>_64dfp"
2362 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2363 "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
2364 (match_operand:DD_DF 1 "general_operand"
2365 " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
2387 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2388 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2389 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2390 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2391 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2393 (define_insn "*mov<mode>_64"
2394 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
2395 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
2413 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2414 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2415 fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2416 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2417 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
2419 (define_insn "*mov<mode>_31"
2420 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2421 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2422 (match_operand:DD_DF 1 "general_operand"
2423 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2438 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2439 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2440 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2441 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2444 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2445 (match_operand:DD_DF 1 "general_operand" ""))]
2446 "!TARGET_ZARCH && reload_completed
2447 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2448 [(set (match_dup 2) (match_dup 4))
2449 (set (match_dup 3) (match_dup 5))]
2451 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2452 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2453 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2454 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2458 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2459 (match_operand:DD_DF 1 "general_operand" ""))]
2460 "!TARGET_ZARCH && reload_completed
2461 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2462 [(set (match_dup 2) (match_dup 4))
2463 (set (match_dup 3) (match_dup 5))]
2465 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2466 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2467 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2468 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2472 [(set (match_operand:DD_DF 0 "register_operand" "")
2473 (match_operand:DD_DF 1 "memory_operand" ""))]
2474 "!TARGET_ZARCH && reload_completed
2475 && !FP_REG_P (operands[0])
2476 && !s_operand (operands[1], VOIDmode)"
2477 [(set (match_dup 0) (match_dup 1))]
2479 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2480 s390_load_address (addr, XEXP (operands[1], 0));
2481 operands[1] = replace_equiv_address (operands[1], addr);
2485 ; mov(sf|sd) instruction pattern(s).
2488 (define_insn "mov<mode>"
2489 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2490 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
2491 (match_operand:SD_SF 1 "general_operand"
2492 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
2517 [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2518 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2519 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2520 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2521 (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
2524 ; movcc instruction pattern
2527 (define_insn "movcc"
2528 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2529 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2539 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2540 (set_attr "type" "lr,*,*,load,load,store,store")
2541 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2542 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2545 ; Block move (MVC) patterns.
2549 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2550 (match_operand:BLK 1 "memory_operand" "Q"))
2551 (use (match_operand 2 "const_int_operand" "n"))]
2552 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2553 "mvc\t%O0(%2,%R0),%S1"
2554 [(set_attr "op_type" "SS")])
2556 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2557 ; order to have it implemented with mvc.
2560 [(set (match_operand:QI 0 "memory_operand" "")
2561 (match_operand:QI 1 "memory_operand" ""))]
2564 [(set (match_dup 0) (match_dup 1))
2565 (use (const_int 1))])]
2567 operands[0] = adjust_address (operands[0], BLKmode, 0);
2568 operands[1] = adjust_address (operands[1], BLKmode, 0);
2574 [(set (match_operand:BLK 0 "memory_operand" "")
2575 (match_operand:BLK 1 "memory_operand" ""))
2576 (use (match_operand 2 "const_int_operand" ""))])
2578 [(set (match_operand:BLK 3 "memory_operand" "")
2579 (match_operand:BLK 4 "memory_operand" ""))
2580 (use (match_operand 5 "const_int_operand" ""))])]
2581 "s390_offset_p (operands[0], operands[3], operands[2])
2582 && s390_offset_p (operands[1], operands[4], operands[2])
2583 && !s390_overlap_p (operands[0], operands[1],
2584 INTVAL (operands[2]) + INTVAL (operands[5]))
2585 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2587 [(set (match_dup 6) (match_dup 7))
2588 (use (match_dup 8))])]
2589 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2590 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2591 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2595 ; load_multiple pattern(s).
2597 ; ??? Due to reload problems with replacing registers inside match_parallel
2598 ; we currently support load_multiple/store_multiple only after reload.
2601 (define_expand "load_multiple"
2602 [(match_par_dup 3 [(set (match_operand 0 "" "")
2603 (match_operand 1 "" ""))
2604 (use (match_operand 2 "" ""))])]
2613 /* Support only loading a constant number of fixed-point registers from
2614 memory and only bother with this if more than two */
2615 if (GET_CODE (operands[2]) != CONST_INT
2616 || INTVAL (operands[2]) < 2
2617 || INTVAL (operands[2]) > 16
2618 || GET_CODE (operands[1]) != MEM
2619 || GET_CODE (operands[0]) != REG
2620 || REGNO (operands[0]) >= 16)
2623 count = INTVAL (operands[2]);
2624 regno = REGNO (operands[0]);
2625 mode = GET_MODE (operands[0]);
2626 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2629 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2630 if (!can_create_pseudo_p ())
2632 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2634 from = XEXP (operands[1], 0);
2637 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2638 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2639 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2641 from = XEXP (XEXP (operands[1], 0), 0);
2642 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2649 from = force_reg (Pmode, XEXP (operands[1], 0));
2653 for (i = 0; i < count; i++)
2654 XVECEXP (operands[3], 0, i)
2655 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2656 change_address (operands[1], mode,
2657 plus_constant (Pmode, from,
2658 off + i * GET_MODE_SIZE (mode))));
2661 (define_insn "*load_multiple_di"
2662 [(match_parallel 0 "load_multiple_operation"
2663 [(set (match_operand:DI 1 "register_operand" "=r")
2664 (match_operand:DI 2 "s_operand" "QS"))])]
2665 "reload_completed && TARGET_ZARCH"
2667 int words = XVECLEN (operands[0], 0);
2668 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2669 return "lmg\t%1,%0,%S2";
2671 [(set_attr "op_type" "RSY")
2672 (set_attr "type" "lm")])
2674 (define_insn "*load_multiple_si"
2675 [(match_parallel 0 "load_multiple_operation"
2676 [(set (match_operand:SI 1 "register_operand" "=r,r")
2677 (match_operand:SI 2 "s_operand" "Q,S"))])]
2680 int words = XVECLEN (operands[0], 0);
2681 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2682 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2684 [(set_attr "op_type" "RS,RSY")
2685 (set_attr "type" "lm")])
2688 ; store multiple pattern(s).
2691 (define_expand "store_multiple"
2692 [(match_par_dup 3 [(set (match_operand 0 "" "")
2693 (match_operand 1 "" ""))
2694 (use (match_operand 2 "" ""))])]
2703 /* Support only storing a constant number of fixed-point registers to
2704 memory and only bother with this if more than two. */
2705 if (GET_CODE (operands[2]) != CONST_INT
2706 || INTVAL (operands[2]) < 2
2707 || INTVAL (operands[2]) > 16
2708 || GET_CODE (operands[0]) != MEM
2709 || GET_CODE (operands[1]) != REG
2710 || REGNO (operands[1]) >= 16)
2713 count = INTVAL (operands[2]);
2714 regno = REGNO (operands[1]);
2715 mode = GET_MODE (operands[1]);
2716 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2719 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2721 if (!can_create_pseudo_p ())
2723 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2725 to = XEXP (operands[0], 0);
2728 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2729 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2730 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2732 to = XEXP (XEXP (operands[0], 0), 0);
2733 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2740 to = force_reg (Pmode, XEXP (operands[0], 0));
2744 for (i = 0; i < count; i++)
2745 XVECEXP (operands[3], 0, i)
2746 = gen_rtx_SET (change_address (operands[0], mode,
2747 plus_constant (Pmode, to,
2748 off + i * GET_MODE_SIZE (mode))),
2749 gen_rtx_REG (mode, regno + i));
2752 (define_insn "*store_multiple_di"
2753 [(match_parallel 0 "store_multiple_operation"
2754 [(set (match_operand:DI 1 "s_operand" "=QS")
2755 (match_operand:DI 2 "register_operand" "r"))])]
2756 "reload_completed && TARGET_ZARCH"
2758 int words = XVECLEN (operands[0], 0);
2759 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2760 return "stmg\t%2,%0,%S1";
2762 [(set_attr "op_type" "RSY")
2763 (set_attr "type" "stm")])
2766 (define_insn "*store_multiple_si"
2767 [(match_parallel 0 "store_multiple_operation"
2768 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2769 (match_operand:SI 2 "register_operand" "r,r"))])]
2772 int words = XVECLEN (operands[0], 0);
2773 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2774 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2776 [(set_attr "op_type" "RS,RSY")
2777 (set_attr "type" "stm")])
2780 ;; String instructions.
2783 (define_insn "*execute_rl"
2784 [(match_parallel 0 "execute_operation"
2785 [(unspec [(match_operand 1 "register_operand" "a")
2786 (match_operand 2 "" "")
2787 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2788 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2789 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2791 [(set_attr "op_type" "RIL")
2792 (set_attr "type" "cs")])
2794 (define_insn "*execute"
2795 [(match_parallel 0 "execute_operation"
2796 [(unspec [(match_operand 1 "register_operand" "a")
2797 (match_operand:BLK 2 "memory_operand" "R")
2798 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2799 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2800 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2802 [(set_attr "op_type" "RX")
2803 (set_attr "type" "cs")])
2807 ; strlenM instruction pattern(s).
2810 (define_expand "strlen<mode>"
2811 [(match_operand:P 0 "register_operand" "") ; result
2812 (match_operand:BLK 1 "memory_operand" "") ; input string
2813 (match_operand:SI 2 "immediate_operand" "") ; search character
2814 (match_operand:SI 3 "immediate_operand" "")] ; known alignment
2817 if (!TARGET_VX || operands[2] != const0_rtx)
2818 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2819 operands[2], operands[3]));
2821 s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2826 (define_expand "strlen_srst<mode>"
2827 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2830 (unspec:P [(const_int 0)
2831 (match_operand:BLK 1 "memory_operand" "")
2833 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2834 (clobber (scratch:P))
2835 (clobber (reg:CC CC_REGNUM))])
2837 [(set (match_operand:P 0 "register_operand" "")
2838 (minus:P (match_dup 4) (match_dup 5)))
2839 (clobber (reg:CC CC_REGNUM))])]
2842 operands[4] = gen_reg_rtx (Pmode);
2843 operands[5] = gen_reg_rtx (Pmode);
2844 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2845 operands[1] = replace_equiv_address (operands[1], operands[5]);
2848 (define_insn "*strlen<mode>"
2849 [(set (match_operand:P 0 "register_operand" "=a")
2850 (unspec:P [(match_operand:P 2 "general_operand" "0")
2851 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2853 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2854 (clobber (match_scratch:P 1 "=a"))
2855 (clobber (reg:CC CC_REGNUM))]
2857 "srst\t%0,%1\;jo\t.-4"
2858 [(set_attr "length" "8")
2859 (set_attr "type" "vs")])
2862 ; cmpstrM instruction pattern(s).
2865 (define_expand "cmpstrsi"
2866 [(set (reg:SI 0) (const_int 0))
2868 [(clobber (match_operand 3 "" ""))
2869 (clobber (match_dup 4))
2870 (set (reg:CCU CC_REGNUM)
2871 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2872 (match_operand:BLK 2 "memory_operand" "")))
2875 [(set (match_operand:SI 0 "register_operand" "=d")
2876 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2877 (clobber (reg:CC CC_REGNUM))])]
2880 /* As the result of CMPINT is inverted compared to what we need,
2881 we have to swap the operands. */
2882 rtx op1 = operands[2];
2883 rtx op2 = operands[1];
2884 rtx addr1 = gen_reg_rtx (Pmode);
2885 rtx addr2 = gen_reg_rtx (Pmode);
2887 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2888 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2889 operands[1] = replace_equiv_address_nv (op1, addr1);
2890 operands[2] = replace_equiv_address_nv (op2, addr2);
2891 operands[3] = addr1;
2892 operands[4] = addr2;
2895 (define_insn "*cmpstr<mode>"
2896 [(clobber (match_operand:P 0 "register_operand" "=d"))
2897 (clobber (match_operand:P 1 "register_operand" "=d"))
2898 (set (reg:CCU CC_REGNUM)
2899 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2900 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2903 "clst\t%0,%1\;jo\t.-4"
2904 [(set_attr "length" "8")
2905 (set_attr "type" "vs")])
2908 ; movstr instruction pattern.
2911 (define_expand "movstr"
2912 [(set (reg:SI 0) (const_int 0))
2914 [(clobber (match_dup 3))
2915 (set (match_operand:BLK 1 "memory_operand" "")
2916 (match_operand:BLK 2 "memory_operand" ""))
2917 (set (match_operand 0 "register_operand" "")
2918 (unspec [(match_dup 1)
2920 (reg:SI 0)] UNSPEC_MVST))
2921 (clobber (reg:CC CC_REGNUM))])]
2924 rtx addr1 = gen_reg_rtx (Pmode);
2925 rtx addr2 = gen_reg_rtx (Pmode);
2927 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2928 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2929 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2930 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2931 operands[3] = addr2;
2934 (define_insn "*movstr"
2935 [(clobber (match_operand:P 2 "register_operand" "=d"))
2936 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2937 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2938 (set (match_operand:P 0 "register_operand" "=d")
2939 (unspec [(mem:BLK (match_dup 1))
2940 (mem:BLK (match_dup 3))
2941 (reg:SI 0)] UNSPEC_MVST))
2942 (clobber (reg:CC CC_REGNUM))]
2944 "mvst\t%1,%2\;jo\t.-4"
2945 [(set_attr "length" "8")
2946 (set_attr "type" "vs")])
2950 ; movmemM instruction pattern(s).
2953 (define_expand "movmem<mode>"
2954 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2955 (match_operand:BLK 1 "memory_operand" "")) ; source
2956 (use (match_operand:GPR 2 "general_operand" "")) ; count
2957 (match_operand 3 "" "")]
2960 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2966 ; Move a block that is up to 256 bytes in length.
2967 ; The block length is taken as (operands[2] % 256) + 1.
2969 (define_expand "movmem_short"
2971 [(set (match_operand:BLK 0 "memory_operand" "")
2972 (match_operand:BLK 1 "memory_operand" ""))
2973 (use (match_operand 2 "nonmemory_operand" ""))
2974 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2975 (clobber (match_dup 3))])]
2977 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2979 (define_insn "*movmem_short"
2980 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2981 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2982 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2983 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2984 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2985 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2987 [(set_attr "type" "cs")
2988 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2991 [(set (match_operand:BLK 0 "memory_operand" "")
2992 (match_operand:BLK 1 "memory_operand" ""))
2993 (use (match_operand 2 "const_int_operand" ""))
2994 (use (match_operand 3 "immediate_operand" ""))
2995 (clobber (scratch))]
2998 [(set (match_dup 0) (match_dup 1))
2999 (use (match_dup 2))])]
3000 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3003 [(set (match_operand:BLK 0 "memory_operand" "")
3004 (match_operand:BLK 1 "memory_operand" ""))
3005 (use (match_operand 2 "register_operand" ""))
3006 (use (match_operand 3 "memory_operand" ""))
3007 (clobber (scratch))]
3010 [(unspec [(match_dup 2) (match_dup 3)
3011 (const_int 0)] UNSPEC_EXECUTE)
3012 (set (match_dup 0) (match_dup 1))
3013 (use (const_int 1))])]
3017 [(set (match_operand:BLK 0 "memory_operand" "")
3018 (match_operand:BLK 1 "memory_operand" ""))
3019 (use (match_operand 2 "register_operand" ""))
3020 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3021 (clobber (scratch))]
3022 "TARGET_Z10 && reload_completed"
3024 [(unspec [(match_dup 2) (const_int 0)
3025 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3026 (set (match_dup 0) (match_dup 1))
3027 (use (const_int 1))])]
3028 "operands[3] = gen_label_rtx ();")
3031 [(set (match_operand:BLK 0 "memory_operand" "")
3032 (match_operand:BLK 1 "memory_operand" ""))
3033 (use (match_operand 2 "register_operand" ""))
3034 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3035 (clobber (match_operand 3 "register_operand" ""))]
3036 "reload_completed && TARGET_CPU_ZARCH"
3037 [(set (match_dup 3) (label_ref (match_dup 4)))
3039 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3040 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3041 (set (match_dup 0) (match_dup 1))
3042 (use (const_int 1))])]
3043 "operands[4] = gen_label_rtx ();")
3045 ; Move a block of arbitrary length.
3047 (define_expand "movmem_long"
3049 [(clobber (match_dup 2))
3050 (clobber (match_dup 3))
3051 (set (match_operand:BLK 0 "memory_operand" "")
3052 (match_operand:BLK 1 "memory_operand" ""))
3053 (use (match_operand 2 "general_operand" ""))
3055 (clobber (reg:CC CC_REGNUM))])]
3058 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3059 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3060 rtx reg0 = gen_reg_rtx (dreg_mode);
3061 rtx reg1 = gen_reg_rtx (dreg_mode);
3062 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3063 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3064 rtx len0 = gen_lowpart (Pmode, reg0);
3065 rtx len1 = gen_lowpart (Pmode, reg1);
3067 emit_clobber (reg0);
3068 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3069 emit_move_insn (len0, operands[2]);
3071 emit_clobber (reg1);
3072 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3073 emit_move_insn (len1, operands[2]);
3075 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3076 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3081 (define_insn "*movmem_long"
3082 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3083 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3084 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3085 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3088 (clobber (reg:CC CC_REGNUM))]
3089 "TARGET_64BIT || !TARGET_ZARCH"
3090 "mvcle\t%0,%1,0\;jo\t.-4"
3091 [(set_attr "length" "8")
3092 (set_attr "type" "vs")])
3094 (define_insn "*movmem_long_31z"
3095 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3096 (clobber (match_operand:TI 1 "register_operand" "=d"))
3097 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3098 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3101 (clobber (reg:CC CC_REGNUM))]
3102 "!TARGET_64BIT && TARGET_ZARCH"
3103 "mvcle\t%0,%1,0\;jo\t.-4"
3104 [(set_attr "length" "8")
3105 (set_attr "type" "vs")])
3112 (define_expand "signbit<mode>2"
3113 [(set (reg:CCZ CC_REGNUM)
3114 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3117 (set (match_operand:SI 0 "register_operand" "=d")
3118 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3121 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3124 (define_expand "isinf<mode>2"
3125 [(set (reg:CCZ CC_REGNUM)
3126 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3129 (set (match_operand:SI 0 "register_operand" "=d")
3130 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3133 operands[2] = GEN_INT (S390_TDC_INFINITY);
3136 ; This extracts CC into a GPR properly shifted. The actual IPM
3137 ; instruction will be issued by reload. The constraint of operand 1
3138 ; forces reload to use a GPR. So reload will issue a movcc insn for
3139 ; copying CC into a GPR first.
3140 (define_insn_and_split "*cc_to_int"
3141 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3142 (unspec:SI [(match_operand 1 "register_operand" "0")]
3147 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3149 ; This insn is used to generate all variants of the Test Data Class
3150 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
3151 ; is the register to be tested and the second one is the bit mask
3152 ; specifying the required test(s).
3154 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3155 (define_insn "*TDC_insn_<mode>"
3156 [(set (reg:CCZ CC_REGNUM)
3157 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3158 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3160 "t<_d>c<xde><bt>\t%0,%1"
3161 [(set_attr "op_type" "RXE")
3162 (set_attr "type" "fsimp<mode>")])
3167 ; setmemM instruction pattern(s).
3170 (define_expand "setmem<mode>"
3171 [(set (match_operand:BLK 0 "memory_operand" "")
3172 (match_operand:QI 2 "general_operand" ""))
3173 (use (match_operand:GPR 1 "general_operand" ""))
3174 (match_operand 3 "" "")]
3176 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3178 ; Clear a block that is up to 256 bytes in length.
3179 ; The block length is taken as (operands[1] % 256) + 1.
3181 (define_expand "clrmem_short"
3183 [(set (match_operand:BLK 0 "memory_operand" "")
3185 (use (match_operand 1 "nonmemory_operand" ""))
3186 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3187 (clobber (match_dup 2))
3188 (clobber (reg:CC CC_REGNUM))])]
3190 "operands[2] = gen_rtx_SCRATCH (Pmode);")
3192 (define_insn "*clrmem_short"
3193 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3195 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3196 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3197 (clobber (match_scratch:P 3 "=X,X,X,&a"))
3198 (clobber (reg:CC CC_REGNUM))]
3199 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3201 [(set_attr "type" "cs")
3202 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3205 [(set (match_operand:BLK 0 "memory_operand" "")
3207 (use (match_operand 1 "const_int_operand" ""))
3208 (use (match_operand 2 "immediate_operand" ""))
3210 (clobber (reg:CC CC_REGNUM))]
3213 [(set (match_dup 0) (const_int 0))
3215 (clobber (reg:CC CC_REGNUM))])]
3216 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3219 [(set (match_operand:BLK 0 "memory_operand" "")
3221 (use (match_operand 1 "register_operand" ""))
3222 (use (match_operand 2 "memory_operand" ""))
3224 (clobber (reg:CC CC_REGNUM))]
3227 [(unspec [(match_dup 1) (match_dup 2)
3228 (const_int 0)] UNSPEC_EXECUTE)
3229 (set (match_dup 0) (const_int 0))
3231 (clobber (reg:CC CC_REGNUM))])]
3235 [(set (match_operand:BLK 0 "memory_operand" "")
3237 (use (match_operand 1 "register_operand" ""))
3238 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3240 (clobber (reg:CC CC_REGNUM))]
3241 "TARGET_Z10 && reload_completed"
3243 [(unspec [(match_dup 1) (const_int 0)
3244 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3245 (set (match_dup 0) (const_int 0))
3247 (clobber (reg:CC CC_REGNUM))])]
3248 "operands[3] = gen_label_rtx ();")
3251 [(set (match_operand:BLK 0 "memory_operand" "")
3253 (use (match_operand 1 "register_operand" ""))
3254 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3255 (clobber (match_operand 2 "register_operand" ""))
3256 (clobber (reg:CC CC_REGNUM))]
3257 "reload_completed && TARGET_CPU_ZARCH"
3258 [(set (match_dup 2) (label_ref (match_dup 3)))
3260 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3261 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3262 (set (match_dup 0) (const_int 0))
3264 (clobber (reg:CC CC_REGNUM))])]
3265 "operands[3] = gen_label_rtx ();")
3267 ; Initialize a block of arbitrary length with (operands[2] % 256).
3269 (define_expand "setmem_long"
3271 [(clobber (match_dup 1))
3272 (set (match_operand:BLK 0 "memory_operand" "")
3273 (match_operand 2 "shift_count_or_setmem_operand" ""))
3274 (use (match_operand 1 "general_operand" ""))
3276 (clobber (reg:CC CC_REGNUM))])]
3279 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3280 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3281 rtx reg0 = gen_reg_rtx (dreg_mode);
3282 rtx reg1 = gen_reg_rtx (dreg_mode);
3283 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3284 rtx len0 = gen_lowpart (Pmode, reg0);
3286 emit_clobber (reg0);
3287 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3288 emit_move_insn (len0, operands[1]);
3290 emit_move_insn (reg1, const0_rtx);
3292 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3297 (define_insn "*setmem_long"
3298 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3299 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3300 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3302 (use (match_operand:<DBL> 1 "register_operand" "d"))
3303 (clobber (reg:CC CC_REGNUM))]
3304 "TARGET_64BIT || !TARGET_ZARCH"
3305 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3306 [(set_attr "length" "8")
3307 (set_attr "type" "vs")])
3309 (define_insn "*setmem_long_and"
3310 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3311 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3312 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3313 (match_operand 4 "const_int_operand" "n")))
3315 (use (match_operand:<DBL> 1 "register_operand" "d"))
3316 (clobber (reg:CC CC_REGNUM))]
3317 "(TARGET_64BIT || !TARGET_ZARCH) &&
3318 (INTVAL (operands[4]) & 255) == 255"
3319 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3320 [(set_attr "length" "8")
3321 (set_attr "type" "vs")])
3323 (define_insn "*setmem_long_31z"
3324 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3325 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3326 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3328 (use (match_operand:TI 1 "register_operand" "d"))
3329 (clobber (reg:CC CC_REGNUM))]
3330 "!TARGET_64BIT && TARGET_ZARCH"
3331 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3332 [(set_attr "length" "8")
3333 (set_attr "type" "vs")])
3336 ; cmpmemM instruction pattern(s).
3339 (define_expand "cmpmemsi"
3340 [(set (match_operand:SI 0 "register_operand" "")
3341 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3342 (match_operand:BLK 2 "memory_operand" "") ) )
3343 (use (match_operand:SI 3 "general_operand" ""))
3344 (use (match_operand:SI 4 "" ""))]
3347 if (s390_expand_cmpmem (operands[0], operands[1],
3348 operands[2], operands[3]))
3354 ; Compare a block that is up to 256 bytes in length.
3355 ; The block length is taken as (operands[2] % 256) + 1.
3357 (define_expand "cmpmem_short"
3359 [(set (reg:CCU CC_REGNUM)
3360 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3361 (match_operand:BLK 1 "memory_operand" "")))
3362 (use (match_operand 2 "nonmemory_operand" ""))
3363 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3364 (clobber (match_dup 3))])]
3366 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3368 (define_insn "*cmpmem_short"
3369 [(set (reg:CCU CC_REGNUM)
3370 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3371 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3372 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3373 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3374 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3375 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3377 [(set_attr "type" "cs")
3378 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3381 [(set (reg:CCU CC_REGNUM)
3382 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3383 (match_operand:BLK 1 "memory_operand" "")))
3384 (use (match_operand 2 "const_int_operand" ""))
3385 (use (match_operand 3 "immediate_operand" ""))
3386 (clobber (scratch))]
3389 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3390 (use (match_dup 2))])]
3391 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3394 [(set (reg:CCU CC_REGNUM)
3395 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3396 (match_operand:BLK 1 "memory_operand" "")))
3397 (use (match_operand 2 "register_operand" ""))
3398 (use (match_operand 3 "memory_operand" ""))
3399 (clobber (scratch))]
3402 [(unspec [(match_dup 2) (match_dup 3)
3403 (const_int 0)] UNSPEC_EXECUTE)
3404 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3405 (use (const_int 1))])]
3409 [(set (reg:CCU CC_REGNUM)
3410 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3411 (match_operand:BLK 1 "memory_operand" "")))
3412 (use (match_operand 2 "register_operand" ""))
3413 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3414 (clobber (scratch))]
3415 "TARGET_Z10 && reload_completed"
3417 [(unspec [(match_dup 2) (const_int 0)
3418 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3419 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3420 (use (const_int 1))])]
3421 "operands[4] = gen_label_rtx ();")
3424 [(set (reg:CCU CC_REGNUM)
3425 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3426 (match_operand:BLK 1 "memory_operand" "")))
3427 (use (match_operand 2 "register_operand" ""))
3428 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3429 (clobber (match_operand 3 "register_operand" ""))]
3430 "reload_completed && TARGET_CPU_ZARCH"
3431 [(set (match_dup 3) (label_ref (match_dup 4)))
3433 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3434 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3435 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3436 (use (const_int 1))])]
3437 "operands[4] = gen_label_rtx ();")
3439 ; Compare a block of arbitrary length.
3441 (define_expand "cmpmem_long"
3443 [(clobber (match_dup 2))
3444 (clobber (match_dup 3))
3445 (set (reg:CCU CC_REGNUM)
3446 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3447 (match_operand:BLK 1 "memory_operand" "")))
3448 (use (match_operand 2 "general_operand" ""))
3449 (use (match_dup 3))])]
3452 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3453 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3454 rtx reg0 = gen_reg_rtx (dreg_mode);
3455 rtx reg1 = gen_reg_rtx (dreg_mode);
3456 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3457 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3458 rtx len0 = gen_lowpart (Pmode, reg0);
3459 rtx len1 = gen_lowpart (Pmode, reg1);
3461 emit_clobber (reg0);
3462 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3463 emit_move_insn (len0, operands[2]);
3465 emit_clobber (reg1);
3466 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3467 emit_move_insn (len1, operands[2]);
3469 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3470 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3475 (define_insn "*cmpmem_long"
3476 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3477 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3478 (set (reg:CCU CC_REGNUM)
3479 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3480 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3482 (use (match_dup 3))]
3483 "TARGET_64BIT || !TARGET_ZARCH"
3484 "clcle\t%0,%1,0\;jo\t.-4"
3485 [(set_attr "length" "8")
3486 (set_attr "type" "vs")])
3488 (define_insn "*cmpmem_long_31z"
3489 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3490 (clobber (match_operand:TI 1 "register_operand" "=d"))
3491 (set (reg:CCU CC_REGNUM)
3492 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3493 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3495 (use (match_dup 3))]
3496 "!TARGET_64BIT && TARGET_ZARCH"
3497 "clcle\t%0,%1,0\;jo\t.-4"
3498 [(set_attr "op_type" "NN")
3499 (set_attr "type" "vs")
3500 (set_attr "length" "8")])
3502 ; Convert CCUmode condition code to integer.
3503 ; Result is zero if EQ, positive if LTU, negative if GTU.
3505 (define_insn_and_split "cmpint"
3506 [(set (match_operand:SI 0 "register_operand" "=d")
3507 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3508 UNSPEC_STRCMPCC_TO_INT))
3509 (clobber (reg:CC CC_REGNUM))]
3513 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3515 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3516 (clobber (reg:CC CC_REGNUM))])])
3518 (define_insn_and_split "*cmpint_cc"
3519 [(set (reg CC_REGNUM)
3520 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3521 UNSPEC_STRCMPCC_TO_INT)
3523 (set (match_operand:SI 0 "register_operand" "=d")
3524 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3525 "s390_match_ccmode (insn, CCSmode)"
3527 "&& reload_completed"
3528 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3530 [(set (match_dup 2) (match_dup 3))
3531 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3533 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3534 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3535 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3538 (define_insn_and_split "*cmpint_sign"
3539 [(set (match_operand:DI 0 "register_operand" "=d")
3540 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3541 UNSPEC_STRCMPCC_TO_INT)))
3542 (clobber (reg:CC CC_REGNUM))]
3545 "&& reload_completed"
3546 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3548 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3549 (clobber (reg:CC CC_REGNUM))])])
3551 (define_insn_and_split "*cmpint_sign_cc"
3552 [(set (reg CC_REGNUM)
3553 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3554 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3555 UNSPEC_STRCMPCC_TO_INT) 0)
3556 (const_int 32)) (const_int 32))
3558 (set (match_operand:DI 0 "register_operand" "=d")
3559 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3560 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3562 "&& reload_completed"
3563 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3565 [(set (match_dup 2) (match_dup 3))
3566 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3568 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3569 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3570 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3575 ;;- Conversion instructions.
3578 (define_insn "*sethighpartsi"
3579 [(set (match_operand:SI 0 "register_operand" "=d,d")
3580 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3581 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3582 (clobber (reg:CC CC_REGNUM))]
3587 [(set_attr "op_type" "RS,RSY")
3588 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3590 (define_insn "*sethighpartdi_64"
3591 [(set (match_operand:DI 0 "register_operand" "=d")
3592 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3593 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3594 (clobber (reg:CC CC_REGNUM))]
3597 [(set_attr "op_type" "RSY")
3598 (set_attr "z10prop" "z10_super")])
3600 (define_insn "*sethighpartdi_31"
3601 [(set (match_operand:DI 0 "register_operand" "=d,d")
3602 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3603 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3604 (clobber (reg:CC CC_REGNUM))]
3609 [(set_attr "op_type" "RS,RSY")
3610 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3613 ; extv instruction patterns
3616 ; FIXME: This expander needs to be converted from DI to GPR as well
3617 ; after resolving some issues with it.
3619 (define_expand "extzv"
3621 [(set (match_operand:DI 0 "register_operand" "=d")
3623 (match_operand:DI 1 "register_operand" "d")
3624 (match_operand 2 "const_int_operand" "") ; size
3625 (match_operand 3 "const_int_operand" ""))) ; start
3626 (clobber (reg:CC CC_REGNUM))])]
3629 /* Starting with zEC12 there is risbgn not clobbering CC. */
3632 emit_move_insn (operands[0],
3633 gen_rtx_ZERO_EXTRACT (DImode,
3641 (define_insn "*extzv<mode>_zEC12"
3642 [(set (match_operand:GPR 0 "register_operand" "=d")
3644 (match_operand:GPR 1 "register_operand" "d")
3645 (match_operand 2 "const_int_operand" "") ; size
3646 (match_operand 3 "const_int_operand" "")))] ; start]
3648 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3649 [(set_attr "op_type" "RIE")])
3651 (define_insn "*extzv<mode>_z10"
3652 [(set (match_operand:GPR 0 "register_operand" "=d")
3654 (match_operand:GPR 1 "register_operand" "d")
3655 (match_operand 2 "const_int_operand" "") ; size
3656 (match_operand 3 "const_int_operand" ""))) ; start
3657 (clobber (reg:CC CC_REGNUM))]
3659 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3660 [(set_attr "op_type" "RIE")
3661 (set_attr "z10prop" "z10_super_E1")])
3663 (define_insn_and_split "*pre_z10_extzv<mode>"
3664 [(set (match_operand:GPR 0 "register_operand" "=d")
3665 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3666 (match_operand 2 "nonzero_shift_count_operand" "")
3668 (clobber (reg:CC CC_REGNUM))]
3671 "&& reload_completed"
3673 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3674 (clobber (reg:CC CC_REGNUM))])
3675 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3677 int bitsize = INTVAL (operands[2]);
3678 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3679 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3681 operands[1] = adjust_address (operands[1], BLKmode, 0);
3682 set_mem_size (operands[1], size);
3683 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3684 operands[3] = GEN_INT (mask);
3687 (define_insn_and_split "*pre_z10_extv<mode>"
3688 [(set (match_operand:GPR 0 "register_operand" "=d")
3689 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3690 (match_operand 2 "nonzero_shift_count_operand" "")
3692 (clobber (reg:CC CC_REGNUM))]
3695 "&& reload_completed"
3697 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3698 (clobber (reg:CC CC_REGNUM))])
3700 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3701 (clobber (reg:CC CC_REGNUM))])]
3703 int bitsize = INTVAL (operands[2]);
3704 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3705 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3707 operands[1] = adjust_address (operands[1], BLKmode, 0);
3708 set_mem_size (operands[1], size);
3709 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3710 operands[3] = GEN_INT (mask);
3714 ; insv instruction patterns
3717 (define_expand "insv"
3718 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3719 (match_operand 1 "const_int_operand" "")
3720 (match_operand 2 "const_int_operand" ""))
3721 (match_operand 3 "general_operand" ""))]
3724 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3730 ; The normal RTL expansion will never generate a zero_extract where
3731 ; the location operand isn't word mode. However, we do this in the
3732 ; back-end when generating atomic operations. See s390_two_part_insv.
3733 (define_insn "*insv<mode>_zEC12"
3734 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3735 (match_operand 1 "const_int_operand" "I") ; size
3736 (match_operand 2 "const_int_operand" "I")) ; pos
3737 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3739 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3740 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3741 [(set_attr "op_type" "RIE")])
3743 (define_insn "*insv<mode>_z10"
3744 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3745 (match_operand 1 "const_int_operand" "I") ; size
3746 (match_operand 2 "const_int_operand" "I")) ; pos
3747 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3748 (clobber (reg:CC CC_REGNUM))]
3750 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3751 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3752 [(set_attr "op_type" "RIE")
3753 (set_attr "z10prop" "z10_super_E1")])
3755 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3756 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3757 (define_insn "*insv<mode>_zEC12_noshift"
3758 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3759 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3760 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3761 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3762 (match_operand:GPR 4 "const_int_operand" ""))))]
3763 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3764 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3765 [(set_attr "op_type" "RIE")])
3767 (define_insn "*insv<mode>_z10_noshift"
3768 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3769 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3770 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3771 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3772 (match_operand:GPR 4 "const_int_operand" ""))))
3773 (clobber (reg:CC CC_REGNUM))]
3774 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3775 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3776 [(set_attr "op_type" "RIE")
3777 (set_attr "z10prop" "z10_super_E1")])
3779 ; Implement appending Y on the left of S bits of X
3780 ; x = (y << s) | (x & ((1 << s) - 1))
3781 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3782 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3783 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3784 (match_operand:GPR 2 "immediate_operand" ""))
3785 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3786 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3787 "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3788 "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3789 [(set_attr "op_type" "RIE")
3790 (set_attr "z10prop" "z10_super_E1")])
3792 (define_insn "*insv<mode>_z10_appendbitsleft"
3793 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3794 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3795 (match_operand:GPR 2 "immediate_operand" ""))
3796 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3797 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3798 (clobber (reg:CC CC_REGNUM))]
3799 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3800 "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3801 [(set_attr "op_type" "RIE")
3802 (set_attr "z10prop" "z10_super_E1")])
3804 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3805 ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3806 ; -> z = y >> d; z = risbg;
3809 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3810 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3811 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3812 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3813 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3814 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3816 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3818 (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
3819 (ashift:GPR (match_dup 3) (match_dup 4))))]
3821 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3826 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3827 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3828 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3829 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3830 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3831 (clobber (reg:CC CC_REGNUM))])]
3832 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3834 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3837 (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
3838 (ashift:GPR (match_dup 3) (match_dup 4))))
3839 (clobber (reg:CC CC_REGNUM))])]
3841 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3844 (define_insn "*r<noxa>sbg_<mode>_noshift"
3845 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3847 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3848 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3849 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3850 (clobber (reg:CC CC_REGNUM))]
3852 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3853 [(set_attr "op_type" "RIE")])
3855 (define_insn "*r<noxa>sbg_di_rotl"
3856 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3860 (match_operand:DI 1 "nonimmediate_operand" "d")
3861 (match_operand:DI 3 "const_int_operand" ""))
3862 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3863 (match_operand:DI 4 "nonimmediate_operand" "0")))
3864 (clobber (reg:CC CC_REGNUM))]
3866 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3867 [(set_attr "op_type" "RIE")])
3869 (define_insn "*r<noxa>sbg_<mode>_srl"
3870 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3874 (match_operand:GPR 1 "nonimmediate_operand" "d")
3875 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3876 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3877 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3878 (clobber (reg:CC CC_REGNUM))]
3880 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3881 INTVAL (operands[2]))"
3882 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3883 [(set_attr "op_type" "RIE")])
3885 (define_insn "*r<noxa>sbg_<mode>_sll"
3886 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3890 (match_operand:GPR 1 "nonimmediate_operand" "d")
3891 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3892 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3893 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3894 (clobber (reg:CC CC_REGNUM))]
3896 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3897 INTVAL (operands[2]))"
3898 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3899 [(set_attr "op_type" "RIE")])
3901 ;; These two are generated by combine for s.bf &= val.
3902 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3903 ;; shifts and ands, which results in some truly awful patterns
3904 ;; including subregs of operations. Rather unnecessisarily, IMO.
3907 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3908 ;; (const_int 24 [0x18])
3909 ;; (const_int 0 [0]))
3910 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3911 ;; (const_int 40 [0x28])) 4)
3912 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3914 ;; we should instead generate
3916 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3917 ;; (const_int 24 [0x18])
3918 ;; (const_int 0 [0]))
3919 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3920 ;; (const_int 40 [0x28]))
3921 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3923 ;; by noticing that we can push down the outer paradoxical subreg
3924 ;; into the operation.
3926 (define_insn "*insv_rnsbg_noshift"
3927 [(set (zero_extract:DI
3928 (match_operand:DI 0 "nonimmediate_operand" "+d")
3929 (match_operand 1 "const_int_operand" "")
3930 (match_operand 2 "const_int_operand" ""))
3933 (match_operand:DI 3 "nonimmediate_operand" "d")))
3934 (clobber (reg:CC CC_REGNUM))]
3936 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3937 "rnsbg\t%0,%3,%2,63,0"
3938 [(set_attr "op_type" "RIE")])
3940 (define_insn "*insv_rnsbg_srl"
3941 [(set (zero_extract:DI
3942 (match_operand:DI 0 "nonimmediate_operand" "+d")
3943 (match_operand 1 "const_int_operand" "")
3944 (match_operand 2 "const_int_operand" ""))
3948 (match_operand 3 "const_int_operand" ""))
3949 (match_operand:DI 4 "nonimmediate_operand" "d")))
3950 (clobber (reg:CC CC_REGNUM))]
3952 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3953 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3954 [(set_attr "op_type" "RIE")])
3956 (define_insn "*insv<mode>_mem_reg"
3957 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3958 (match_operand 1 "const_int_operand" "n,n")
3960 (match_operand:W 2 "register_operand" "d,d"))]
3961 "INTVAL (operands[1]) > 0
3962 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3963 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3965 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3967 operands[1] = GEN_INT ((1ul << size) - 1);
3968 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3969 : "stcmy\t%2,%1,%S0";
3971 [(set_attr "op_type" "RS,RSY")
3972 (set_attr "z10prop" "z10_super,z10_super")])
3974 (define_insn "*insvdi_mem_reghigh"
3975 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3976 (match_operand 1 "const_int_operand" "n")
3978 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3981 && INTVAL (operands[1]) > 0
3982 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3983 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3985 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3987 operands[1] = GEN_INT ((1ul << size) - 1);
3988 return "stcmh\t%2,%1,%S0";
3990 [(set_attr "op_type" "RSY")
3991 (set_attr "z10prop" "z10_super")])
3993 (define_insn "*insvdi_reg_imm"
3994 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3996 (match_operand 1 "const_int_operand" "n"))
3997 (match_operand:DI 2 "const_int_operand" "n"))]
3999 && INTVAL (operands[1]) >= 0
4000 && INTVAL (operands[1]) < BITS_PER_WORD
4001 && INTVAL (operands[1]) % 16 == 0"
4003 switch (BITS_PER_WORD - INTVAL (operands[1]))
4005 case 64: return "iihh\t%0,%x2"; break;
4006 case 48: return "iihl\t%0,%x2"; break;
4007 case 32: return "iilh\t%0,%x2"; break;
4008 case 16: return "iill\t%0,%x2"; break;
4009 default: gcc_unreachable();
4012 [(set_attr "op_type" "RI")
4013 (set_attr "z10prop" "z10_super_E1")])
4015 ; Update the left-most 32 bit of a DI.
4016 (define_insn "*insv_h_di_reg_extimm"
4017 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4020 (match_operand:DI 1 "const_int_operand" "n"))]
4023 [(set_attr "op_type" "RIL")
4024 (set_attr "z10prop" "z10_fwd_E1")])
4026 ; Update the right-most 32 bit of a DI.
4027 (define_insn "*insv_l_di_reg_extimm"
4028 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4031 (match_operand:DI 1 "const_int_operand" "n"))]
4034 [(set_attr "op_type" "RIL")
4035 (set_attr "z10prop" "z10_fwd_A1")])
4038 ; extendsidi2 instruction pattern(s).
4041 (define_expand "extendsidi2"
4042 [(set (match_operand:DI 0 "register_operand" "")
4043 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4048 emit_clobber (operands[0]);
4049 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4050 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4051 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4056 (define_insn "*extendsidi2"
4057 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4058 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4064 [(set_attr "op_type" "RRE,RXY,RIL")
4065 (set_attr "type" "*,*,larl")
4066 (set_attr "cpu_facility" "*,*,z10")
4067 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4070 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4073 (define_expand "extend<HQI:mode><DSI:mode>2"
4074 [(set (match_operand:DSI 0 "register_operand" "")
4075 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4078 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4080 rtx tmp = gen_reg_rtx (SImode);
4081 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4082 emit_insn (gen_extendsidi2 (operands[0], tmp));
4085 else if (!TARGET_EXTIMM)
4087 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4089 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4090 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4091 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4097 ; extendhidi2 instruction pattern(s).
4100 (define_insn "*extendhidi2_extimm"
4101 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4102 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
4103 "TARGET_ZARCH && TARGET_EXTIMM"
4108 [(set_attr "op_type" "RRE,RXY,RIL")
4109 (set_attr "type" "*,*,larl")
4110 (set_attr "cpu_facility" "extimm,extimm,z10")
4111 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4113 (define_insn "*extendhidi2"
4114 [(set (match_operand:DI 0 "register_operand" "=d")
4115 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
4118 [(set_attr "op_type" "RXY")
4119 (set_attr "z10prop" "z10_super_E1")])
4122 ; extendhisi2 instruction pattern(s).
4125 (define_insn "*extendhisi2_extimm"
4126 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4127 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4134 [(set_attr "op_type" "RRE,RX,RXY,RIL")
4135 (set_attr "type" "*,*,*,larl")
4136 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4137 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4139 (define_insn "*extendhisi2"
4140 [(set (match_operand:SI 0 "register_operand" "=d,d")
4141 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4146 [(set_attr "op_type" "RX,RXY")
4147 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4150 ; extendqi(si|di)2 instruction pattern(s).
4153 ; lbr, lgbr, lb, lgb
4154 (define_insn "*extendqi<mode>2_extimm"
4155 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4156 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
4161 [(set_attr "op_type" "RRE,RXY")
4162 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4165 (define_insn "*extendqi<mode>2"
4166 [(set (match_operand:GPR 0 "register_operand" "=d")
4167 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
4168 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4170 [(set_attr "op_type" "RXY")
4171 (set_attr "z10prop" "z10_super_E1")])
4173 (define_insn_and_split "*extendqi<mode>2_short_displ"
4174 [(set (match_operand:GPR 0 "register_operand" "=d")
4175 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4176 (clobber (reg:CC CC_REGNUM))]
4177 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4179 "&& reload_completed"
4181 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4182 (clobber (reg:CC CC_REGNUM))])
4184 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4185 (clobber (reg:CC CC_REGNUM))])]
4187 operands[1] = adjust_address (operands[1], BLKmode, 0);
4188 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4189 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4193 ; zero_extendsidi2 instruction pattern(s).
4196 (define_expand "zero_extendsidi2"
4197 [(set (match_operand:DI 0 "register_operand" "")
4198 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4203 emit_clobber (operands[0]);
4204 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4205 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4210 (define_insn "*zero_extendsidi2"
4211 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4212 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4218 [(set_attr "op_type" "RRE,RXY,RIL")
4219 (set_attr "type" "*,*,larl")
4220 (set_attr "cpu_facility" "*,*,z10")
4221 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4224 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4227 (define_insn "*llgt_sidi"
4228 [(set (match_operand:DI 0 "register_operand" "=d")
4229 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4230 (const_int 2147483647)))]
4233 [(set_attr "op_type" "RXE")
4234 (set_attr "z10prop" "z10_super_E1")])
4236 (define_insn_and_split "*llgt_sidi_split"
4237 [(set (match_operand:DI 0 "register_operand" "=d")
4238 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4239 (const_int 2147483647)))
4240 (clobber (reg:CC CC_REGNUM))]
4243 "&& reload_completed"
4245 (and:DI (subreg:DI (match_dup 1) 0)
4246 (const_int 2147483647)))]
4249 (define_insn "*llgt_sisi"
4250 [(set (match_operand:SI 0 "register_operand" "=d,d")
4251 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
4252 (const_int 2147483647)))]
4257 [(set_attr "op_type" "RRE,RXE")
4258 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4260 (define_insn "*llgt_didi"
4261 [(set (match_operand:DI 0 "register_operand" "=d,d")
4262 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4263 (const_int 2147483647)))]
4268 [(set_attr "op_type" "RRE,RXE")
4269 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4272 [(set (match_operand:DSI 0 "register_operand" "")
4273 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4274 (const_int 2147483647)))
4275 (clobber (reg:CC CC_REGNUM))]
4276 "TARGET_ZARCH && reload_completed"
4278 (and:DSI (match_dup 1)
4279 (const_int 2147483647)))]
4283 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4286 (define_expand "zero_extend<mode>di2"
4287 [(set (match_operand:DI 0 "register_operand" "")
4288 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4293 rtx tmp = gen_reg_rtx (SImode);
4294 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4295 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4298 else if (!TARGET_EXTIMM)
4300 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4301 operands[1] = gen_lowpart (DImode, operands[1]);
4302 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4303 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4308 (define_expand "zero_extend<mode>si2"
4309 [(set (match_operand:SI 0 "register_operand" "")
4310 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4315 operands[1] = gen_lowpart (SImode, operands[1]);
4316 emit_insn (gen_andsi3 (operands[0], operands[1],
4317 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4323 (define_insn "*zero_extendhi<mode>2_z10"
4324 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4325 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4331 [(set_attr "op_type" "RXY,RRE,RIL")
4332 (set_attr "type" "*,*,larl")
4333 (set_attr "cpu_facility" "*,*,z10")
4334 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4336 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4337 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4338 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4339 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4344 [(set_attr "op_type" "RRE,RXY")
4345 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4348 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4349 [(set (match_operand:GPR 0 "register_operand" "=d")
4350 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4351 "TARGET_ZARCH && !TARGET_EXTIMM"
4353 [(set_attr "op_type" "RXY")
4354 (set_attr "z10prop" "z10_fwd_A3")])
4356 (define_insn_and_split "*zero_extendhisi2_31"
4357 [(set (match_operand:SI 0 "register_operand" "=&d")
4358 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4359 (clobber (reg:CC CC_REGNUM))]
4362 "&& reload_completed"
4363 [(set (match_dup 0) (const_int 0))
4365 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4366 (clobber (reg:CC CC_REGNUM))])]
4367 "operands[2] = gen_lowpart (HImode, operands[0]);")
4369 (define_insn_and_split "*zero_extendqisi2_31"
4370 [(set (match_operand:SI 0 "register_operand" "=&d")
4371 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4374 "&& reload_completed"
4375 [(set (match_dup 0) (const_int 0))
4376 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4377 "operands[2] = gen_lowpart (QImode, operands[0]);")
4380 ; zero_extendqihi2 instruction pattern(s).
4383 (define_expand "zero_extendqihi2"
4384 [(set (match_operand:HI 0 "register_operand" "")
4385 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4386 "TARGET_ZARCH && !TARGET_EXTIMM"
4388 operands[1] = gen_lowpart (HImode, operands[1]);
4389 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4393 (define_insn "*zero_extendqihi2_64"
4394 [(set (match_operand:HI 0 "register_operand" "=d")
4395 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4396 "TARGET_ZARCH && !TARGET_EXTIMM"
4398 [(set_attr "op_type" "RXY")
4399 (set_attr "z10prop" "z10_fwd_A3")])
4401 (define_insn_and_split "*zero_extendqihi2_31"
4402 [(set (match_operand:HI 0 "register_operand" "=&d")
4403 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4406 "&& reload_completed"
4407 [(set (match_dup 0) (const_int 0))
4408 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4409 "operands[2] = gen_lowpart (QImode, operands[0]);")
4412 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4415 (define_expand "fixuns_truncdddi2"
4417 [(set (match_operand:DI 0 "register_operand" "")
4418 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4419 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4420 (clobber (reg:CC CC_REGNUM))])]
4426 rtx_code_label *label1 = gen_label_rtx ();
4427 rtx_code_label *label2 = gen_label_rtx ();
4428 rtx temp = gen_reg_rtx (TDmode);
4429 REAL_VALUE_TYPE cmp, sub;
4431 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4432 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4434 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4435 solution is doing the check and the subtraction in TD mode and using a
4436 TD -> DI convert afterwards. */
4437 emit_insn (gen_extendddtd2 (temp, operands[1]));
4438 temp = force_reg (TDmode, temp);
4439 emit_cmp_and_jump_insns (temp,
4440 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4441 LT, NULL_RTX, VOIDmode, 0, label1);
4442 emit_insn (gen_subtd3 (temp, temp,
4443 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4444 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4447 emit_label (label1);
4448 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4449 emit_label (label2);
4454 (define_expand "fixuns_trunctddi2"
4456 [(set (match_operand:DI 0 "register_operand" "")
4457 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4458 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4459 (clobber (reg:CC CC_REGNUM))])]
4465 rtx_code_label *label1 = gen_label_rtx ();
4466 rtx_code_label *label2 = gen_label_rtx ();
4467 rtx temp = gen_reg_rtx (TDmode);
4468 REAL_VALUE_TYPE cmp, sub;
4470 operands[1] = force_reg (TDmode, operands[1]);
4471 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4472 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4474 emit_cmp_and_jump_insns (operands[1],
4475 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4476 LT, NULL_RTX, VOIDmode, 0, label1);
4477 emit_insn (gen_subtd3 (temp, operands[1],
4478 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4479 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4482 emit_label (label1);
4483 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4484 emit_label (label2);
4490 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4491 ; instruction pattern(s).
4494 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4496 [(set (match_operand:GPR 0 "register_operand" "")
4497 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4498 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4499 (clobber (reg:CC CC_REGNUM))])]
4504 rtx_code_label *label1 = gen_label_rtx ();
4505 rtx_code_label *label2 = gen_label_rtx ();
4506 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4507 REAL_VALUE_TYPE cmp, sub;
4509 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4510 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4511 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4513 emit_cmp_and_jump_insns (operands[1],
4514 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4515 LT, NULL_RTX, VOIDmode, 0, label1);
4516 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4517 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4518 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4522 emit_label (label1);
4523 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4524 operands[1], GEN_INT (5)));
4525 emit_label (label2);
4530 ; fixuns_trunc(td|dd)si2 expander
4531 (define_expand "fixuns_trunc<mode>si2"
4533 [(set (match_operand:SI 0 "register_operand" "")
4534 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4535 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4536 (clobber (reg:CC CC_REGNUM))])]
4537 "TARGET_Z196 && TARGET_HARD_DFP"
4540 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4542 (define_insn "*fixuns_truncdfdi2_z13"
4543 [(set (match_operand:DI 0 "register_operand" "=d,v")
4544 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4545 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4546 (clobber (reg:CC CC_REGNUM))]
4547 "TARGET_Z13 && TARGET_HARD_FLOAT"
4550 wclgdb\t%v0,%v1,0,%h2"
4551 [(set_attr "op_type" "RRF,VRR")
4552 (set_attr "type" "ftoi")])
4554 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4555 ; clfdtr, clfxtr, clgdtr, clgxtr
4556 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4557 [(set (match_operand:GPR 0 "register_operand" "=d")
4558 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4559 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4560 (clobber (reg:CC CC_REGNUM))]
4561 "TARGET_Z196 && TARGET_HARD_FLOAT
4562 && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4563 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4564 [(set_attr "op_type" "RRF")
4565 (set_attr "type" "ftoi")])
4567 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4568 [(set (match_operand:GPR 0 "register_operand" "")
4569 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4572 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4577 (define_insn "*fix_truncdfdi2_bfp_z13"
4578 [(set (match_operand:DI 0 "register_operand" "=d,v")
4579 (fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4580 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4581 (clobber (reg:CC CC_REGNUM))]
4582 "TARGET_Z13 && TARGET_HARD_FLOAT"
4585 wcgdb\t%v0,%v1,0,%h2"
4586 [(set_attr "op_type" "RRE,VRR")
4587 (set_attr "type" "ftoi")])
4589 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4590 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4591 [(set (match_operand:GPR 0 "register_operand" "=d")
4592 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4593 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4594 (clobber (reg:CC CC_REGNUM))]
4596 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4597 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4598 [(set_attr "op_type" "RRE")
4599 (set_attr "type" "ftoi")])
4601 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4603 [(set (match_operand:GPR 0 "register_operand" "=d")
4604 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4605 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4606 (clobber (reg:CC CC_REGNUM))])]
4607 "TARGET_HARD_FLOAT")
4609 ; fix_trunc(td|dd)di2 instruction pattern(s).
4612 (define_expand "fix_trunc<mode>di2"
4613 [(set (match_operand:DI 0 "register_operand" "")
4614 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4615 "TARGET_ZARCH && TARGET_HARD_DFP"
4617 operands[1] = force_reg (<MODE>mode, operands[1]);
4618 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4624 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4625 [(set (match_operand:DI 0 "register_operand" "=d")
4626 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4627 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4628 (clobber (reg:CC CC_REGNUM))]
4629 "TARGET_ZARCH && TARGET_HARD_DFP"
4630 "cg<DFP:xde>tr\t%0,%h2,%1"
4631 [(set_attr "op_type" "RRF")
4632 (set_attr "type" "ftoidfp")])
4636 ; fix_trunctf(si|di)2 instruction pattern(s).
4639 (define_expand "fix_trunctf<mode>2"
4640 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4641 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4642 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4643 (clobber (reg:CC CC_REGNUM))])]
4649 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4652 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4653 (define_insn "floatdi<mode>2"
4654 [(set (match_operand:FP 0 "register_operand" "=f,<vf>")
4655 (float:FP (match_operand:DI 1 "register_operand" "d,<vd>")))]
4656 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4660 [(set_attr "op_type" "RRE,VRR")
4661 (set_attr "type" "itof<mode>" )
4662 (set_attr "cpu_facility" "*,vec")])
4664 ; cxfbr, cdfbr, cefbr
4665 (define_insn "floatsi<mode>2"
4666 [(set (match_operand:BFP 0 "register_operand" "=f")
4667 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4670 [(set_attr "op_type" "RRE")
4671 (set_attr "type" "itof<mode>" )])
4674 (define_insn "floatsi<mode>2"
4675 [(set (match_operand:DFP 0 "register_operand" "=f")
4676 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4677 "TARGET_Z196 && TARGET_HARD_FLOAT"
4678 "c<xde>ftr\t%0,0,%1,0"
4679 [(set_attr "op_type" "RRE")
4680 (set_attr "type" "itof<mode>" )])
4683 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4686 (define_insn "*floatunsdidf2_z13"
4687 [(set (match_operand:DF 0 "register_operand" "=f,v")
4688 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
4689 "TARGET_Z13 && TARGET_HARD_FLOAT"
4692 wcdlgb\t%v0,%v1,0,0"
4693 [(set_attr "op_type" "RRE,VRR")
4694 (set_attr "type" "itofdf")])
4696 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4697 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4698 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4699 [(set (match_operand:FP 0 "register_operand" "=f")
4700 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4701 "TARGET_Z196 && TARGET_HARD_FLOAT
4702 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4703 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4704 [(set_attr "op_type" "RRE")
4705 (set_attr "type" "itof<FP:mode>")])
4707 (define_expand "floatuns<GPR:mode><FP:mode>2"
4708 [(set (match_operand:FP 0 "register_operand" "")
4709 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4710 "TARGET_Z196 && TARGET_HARD_FLOAT")
4713 ; truncdfsf2 instruction pattern(s).
4716 (define_insn "truncdfsf2"
4717 [(set (match_operand:SF 0 "register_operand" "=f,v")
4718 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))]
4722 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4723 ; According to BFP rounding mode
4724 [(set_attr "op_type" "RRE,VRR")
4725 (set_attr "type" "ftruncdf")
4726 (set_attr "cpu_facility" "*,vec")])
4729 ; trunctf(df|sf)2 instruction pattern(s).
4733 (define_insn "trunctf<mode>2"
4734 [(set (match_operand:DSF 0 "register_operand" "=f")
4735 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4736 (clobber (match_scratch:TF 2 "=f"))]
4738 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4739 [(set_attr "length" "6")
4740 (set_attr "type" "ftrunctf")])
4743 ; trunctddd2 and truncddsd2 instruction pattern(s).
4746 (define_insn "trunctddd2"
4747 [(set (match_operand:DD 0 "register_operand" "=f")
4748 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4749 (clobber (match_scratch:TD 2 "=f"))]
4751 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4752 [(set_attr "length" "6")
4753 (set_attr "type" "ftruncdd")])
4755 (define_insn "truncddsd2"
4756 [(set (match_operand:SD 0 "register_operand" "=f")
4757 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4760 [(set_attr "op_type" "RRF")
4761 (set_attr "type" "ftruncsd")])
4763 (define_expand "trunctdsd2"
4766 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4767 (clobber (match_scratch:TD 2 ""))])
4768 (set (match_operand:SD 0 "register_operand" "")
4769 (float_truncate:SD (match_dup 3)))]
4772 operands[3] = gen_reg_rtx (DDmode);
4776 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4779 (define_insn "*extendsfdf2_z13"
4780 [(set (match_operand:DF 0 "register_operand" "=f,f,v")
4781 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
4782 "TARGET_Z13 && TARGET_HARD_FLOAT"
4787 [(set_attr "op_type" "RRE,RXE,VRR")
4788 (set_attr "type" "fsimpdf, floaddf,fsimpdf")])
4790 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4791 (define_insn "*extend<DSF:mode><BFP:mode>2"
4792 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4793 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4795 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4796 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4798 l<BFP:xde><DSF:xde>br\t%0,%1
4799 l<BFP:xde><DSF:xde>b\t%0,%1"
4800 [(set_attr "op_type" "RRE,RXE")
4801 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4803 (define_expand "extend<DSF:mode><BFP:mode>2"
4804 [(set (match_operand:BFP 0 "register_operand" "")
4805 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4807 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4810 ; extendddtd2 and extendsddd2 instruction pattern(s).
4813 (define_insn "extendddtd2"
4814 [(set (match_operand:TD 0 "register_operand" "=f")
4815 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4818 [(set_attr "op_type" "RRF")
4819 (set_attr "type" "fsimptf")])
4821 (define_insn "extendsddd2"
4822 [(set (match_operand:DD 0 "register_operand" "=f")
4823 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4826 [(set_attr "op_type" "RRF")
4827 (set_attr "type" "fsimptf")])
4829 (define_expand "extendsdtd2"
4831 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4832 (set (match_operand:TD 0 "register_operand" "")
4833 (float_extend:TD (match_dup 2)))]
4836 operands[2] = gen_reg_rtx (DDmode);
4839 ; Binary Floating Point - load fp integer
4841 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4842 ; For all of them the inexact exceptions are suppressed.
4844 ; fiebra, fidbra, fixbra
4845 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4846 [(set (match_operand:BFP 0 "register_operand" "=f")
4847 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4850 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4851 [(set_attr "op_type" "RRF")
4852 (set_attr "type" "fsimp<BFP:mode>")])
4854 ; rint is supposed to raise an inexact exception so we can use the
4855 ; older instructions.
4857 ; fiebr, fidbr, fixbr
4858 (define_insn "rint<BFP:mode>2"
4859 [(set (match_operand:BFP 0 "register_operand" "=f")
4860 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4861 UNSPEC_FPINT_RINT))]
4863 "fi<BFP:xde>br\t%0,0,%1"
4864 [(set_attr "op_type" "RRF")
4865 (set_attr "type" "fsimp<BFP:mode>")])
4868 ; Decimal Floating Point - load fp integer
4871 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4872 [(set (match_operand:DFP 0 "register_operand" "=f")
4873 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4876 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4877 [(set_attr "op_type" "RRF")
4878 (set_attr "type" "fsimp<DFP:mode>")])
4881 (define_insn "rint<DFP:mode>2"
4882 [(set (match_operand:DFP 0 "register_operand" "=f")
4883 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4884 UNSPEC_FPINT_RINT))]
4886 "fi<DFP:xde>tr\t%0,0,%1,0"
4887 [(set_attr "op_type" "RRF")
4888 (set_attr "type" "fsimp<DFP:mode>")])
4891 ; Binary <-> Decimal floating point trunc patterns
4894 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4895 [(set (reg:DFP_ALL FPR0_REGNUM)
4896 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4897 (use (reg:SI GPR0_REGNUM))
4898 (clobber (reg:CC CC_REGNUM))]
4902 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4903 [(set (reg:BFP FPR0_REGNUM)
4904 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4905 (use (reg:SI GPR0_REGNUM))
4906 (clobber (reg:CC CC_REGNUM))]
4910 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4911 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4912 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4914 [(set (reg:DFP_ALL FPR0_REGNUM)
4915 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4916 (use (reg:SI GPR0_REGNUM))
4917 (clobber (reg:CC CC_REGNUM))])
4918 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4919 (reg:DFP_ALL FPR0_REGNUM))]
4921 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4923 HOST_WIDE_INT flags;
4925 flags = (PFPO_CONVERT |
4926 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4927 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4929 operands[2] = GEN_INT (flags);
4932 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4933 [(set (reg:DFP_ALL FPR4_REGNUM)
4934 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4935 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4937 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4938 (use (reg:SI GPR0_REGNUM))
4939 (clobber (reg:CC CC_REGNUM))])
4940 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4942 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4944 HOST_WIDE_INT flags;
4946 flags = (PFPO_CONVERT |
4947 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4948 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4950 operands[2] = GEN_INT (flags);
4954 ; Binary <-> Decimal floating point extend patterns
4957 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4958 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4959 (use (reg:SI GPR0_REGNUM))
4960 (clobber (reg:CC CC_REGNUM))]
4964 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4965 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4966 (use (reg:SI GPR0_REGNUM))
4967 (clobber (reg:CC CC_REGNUM))]
4971 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4972 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4973 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4975 [(set (reg:DFP_ALL FPR0_REGNUM)
4976 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4977 (use (reg:SI GPR0_REGNUM))
4978 (clobber (reg:CC CC_REGNUM))])
4979 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4980 (reg:DFP_ALL FPR0_REGNUM))]
4982 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4984 HOST_WIDE_INT flags;
4986 flags = (PFPO_CONVERT |
4987 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4988 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4990 operands[2] = GEN_INT (flags);
4993 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4994 [(set (reg:DFP_ALL FPR4_REGNUM)
4995 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4996 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4998 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4999 (use (reg:SI GPR0_REGNUM))
5000 (clobber (reg:CC CC_REGNUM))])
5001 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5003 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5005 HOST_WIDE_INT flags;
5007 flags = (PFPO_CONVERT |
5008 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5009 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5011 operands[2] = GEN_INT (flags);
5016 ;; ARITHMETIC OPERATIONS
5018 ; arithmetic operations set the ConditionCode,
5019 ; because of unpredictable Bits in Register for Halfword and Byte
5020 ; the ConditionCode can be set wrong in operations for Halfword and Byte
5023 ;;- Add instructions.
5027 ; addti3 instruction pattern(s).
5030 (define_expand "addti3"
5032 [(set (match_operand:TI 0 "register_operand" "")
5033 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5034 (match_operand:TI 2 "general_operand" "") ) )
5035 (clobber (reg:CC CC_REGNUM))])]
5038 /* For z13 we have vaq which doesn't set CC. */
5041 emit_insn (gen_rtx_SET (operands[0],
5042 gen_rtx_PLUS (TImode,
5043 copy_to_mode_reg (TImode, operands[1]),
5044 copy_to_mode_reg (TImode, operands[2]))));
5049 (define_insn_and_split "*addti3"
5050 [(set (match_operand:TI 0 "register_operand" "=&d")
5051 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5052 (match_operand:TI 2 "general_operand" "do") ) )
5053 (clobber (reg:CC CC_REGNUM))]
5056 "&& reload_completed"
5058 [(set (reg:CCL1 CC_REGNUM)
5059 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5061 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5063 [(set (match_dup 3) (plus:DI
5064 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5065 (match_dup 4)) (match_dup 5)))
5066 (clobber (reg:CC CC_REGNUM))])]
5067 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5068 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5069 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5070 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5071 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5072 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5073 [(set_attr "op_type" "*")
5074 (set_attr "cpu_facility" "*")])
5077 ; adddi3 instruction pattern(s).
5080 (define_expand "adddi3"
5082 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5083 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5084 (match_operand:DI 2 "general_operand" "")))
5085 (clobber (reg:CC CC_REGNUM))])]
5089 (define_insn "*adddi3_sign"
5090 [(set (match_operand:DI 0 "register_operand" "=d,d")
5091 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5092 (match_operand:DI 1 "register_operand" "0,0")))
5093 (clobber (reg:CC CC_REGNUM))]
5098 [(set_attr "op_type" "RRE,RXY")
5099 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5101 (define_insn "*adddi3_zero_cc"
5102 [(set (reg CC_REGNUM)
5103 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5104 (match_operand:DI 1 "register_operand" "0,0"))
5106 (set (match_operand:DI 0 "register_operand" "=d,d")
5107 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5108 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5112 [(set_attr "op_type" "RRE,RXY")
5113 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5115 (define_insn "*adddi3_zero_cconly"
5116 [(set (reg CC_REGNUM)
5117 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5118 (match_operand:DI 1 "register_operand" "0,0"))
5120 (clobber (match_scratch:DI 0 "=d,d"))]
5121 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5125 [(set_attr "op_type" "RRE,RXY")
5126 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5128 (define_insn "*adddi3_zero"
5129 [(set (match_operand:DI 0 "register_operand" "=d,d")
5130 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5131 (match_operand:DI 1 "register_operand" "0,0")))
5132 (clobber (reg:CC CC_REGNUM))]
5137 [(set_attr "op_type" "RRE,RXY")
5138 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5140 (define_insn_and_split "*adddi3_31z"
5141 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5142 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5143 (match_operand:DI 2 "general_operand" "do") ) )
5144 (clobber (reg:CC CC_REGNUM))]
5145 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5147 "&& reload_completed"
5149 [(set (reg:CCL1 CC_REGNUM)
5150 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5152 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5154 [(set (match_dup 3) (plus:SI
5155 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5156 (match_dup 4)) (match_dup 5)))
5157 (clobber (reg:CC CC_REGNUM))])]
5158 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5159 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5160 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5161 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5162 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5163 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5165 (define_insn_and_split "*adddi3_31"
5166 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5167 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5168 (match_operand:DI 2 "general_operand" "do") ) )
5169 (clobber (reg:CC CC_REGNUM))]
5172 "&& reload_completed"
5174 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5175 (clobber (reg:CC CC_REGNUM))])
5177 [(set (reg:CCL1 CC_REGNUM)
5178 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5180 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5182 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5184 (label_ref (match_dup 9))))
5186 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5187 (clobber (reg:CC CC_REGNUM))])
5189 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5190 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5191 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5192 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5193 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5194 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5195 operands[9] = gen_label_rtx ();")
5198 ; addsi3 instruction pattern(s).
5201 (define_expand "addsi3"
5203 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5204 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5205 (match_operand:SI 2 "general_operand" "")))
5206 (clobber (reg:CC CC_REGNUM))])]
5210 (define_insn "*addsi3_sign"
5211 [(set (match_operand:SI 0 "register_operand" "=d,d")
5212 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5213 (match_operand:SI 1 "register_operand" "0,0")))
5214 (clobber (reg:CC CC_REGNUM))]
5219 [(set_attr "op_type" "RX,RXY")
5220 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5223 ; add(di|si)3 instruction pattern(s).
5226 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5227 (define_insn "*add<mode>3"
5228 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
5229 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
5230 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
5231 (clobber (reg:CC CC_REGNUM))]
5243 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5244 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
5245 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5246 z10_super_E1,z10_super_E1,z10_super_E1")])
5248 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5249 (define_insn "*add<mode>3_carry1_cc"
5250 [(set (reg CC_REGNUM)
5251 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5252 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5254 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
5255 (plus:GPR (match_dup 1) (match_dup 2)))]
5256 "s390_match_ccmode (insn, CCL1mode)"
5262 al<g>hsik\t%0,%1,%h2
5266 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5267 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5268 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5269 z10_super_E1,z10_super_E1,z10_super_E1")])
5271 ; alr, al, aly, algr, alg, alrk, algrk
5272 (define_insn "*add<mode>3_carry1_cconly"
5273 [(set (reg CC_REGNUM)
5274 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5275 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5277 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5278 "s390_match_ccmode (insn, CCL1mode)"
5284 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5285 (set_attr "cpu_facility" "*,z196,*,*")
5286 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5288 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5289 (define_insn "*add<mode>3_carry2_cc"
5290 [(set (reg CC_REGNUM)
5291 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5292 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
5294 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
5295 (plus:GPR (match_dup 1) (match_dup 2)))]
5296 "s390_match_ccmode (insn, CCL1mode)"
5302 al<g>hsik\t%0,%1,%h2
5306 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5307 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5308 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5309 z10_super_E1,z10_super_E1,z10_super_E1")])
5311 ; alr, al, aly, algr, alg, alrk, algrk
5312 (define_insn "*add<mode>3_carry2_cconly"
5313 [(set (reg CC_REGNUM)
5314 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5315 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5317 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5318 "s390_match_ccmode (insn, CCL1mode)"
5324 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5325 (set_attr "cpu_facility" "*,z196,*,*")
5326 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5328 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5329 (define_insn "*add<mode>3_cc"
5330 [(set (reg CC_REGNUM)
5331 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5332 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
5334 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
5335 (plus:GPR (match_dup 1) (match_dup 2)))]
5336 "s390_match_ccmode (insn, CCLmode)"
5342 al<g>hsik\t%0,%1,%h2
5346 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5347 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5348 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5349 *,z10_super_E1,z10_super_E1,z10_super_E1")])
5351 ; alr, al, aly, algr, alg, alrk, algrk
5352 (define_insn "*add<mode>3_cconly"
5353 [(set (reg CC_REGNUM)
5354 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5355 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5357 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5358 "s390_match_ccmode (insn, CCLmode)"
5364 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5365 (set_attr "cpu_facility" "*,z196,*,*")
5366 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5368 ; alr, al, aly, algr, alg, alrk, algrk
5369 (define_insn "*add<mode>3_cconly2"
5370 [(set (reg CC_REGNUM)
5371 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5372 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5373 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5374 "s390_match_ccmode(insn, CCLmode)"
5380 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5381 (set_attr "cpu_facility" "*,z196,*,*")
5382 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5384 ; ahi, afi, aghi, agfi, asi, agsi
5385 (define_insn "*add<mode>3_imm_cc"
5386 [(set (reg CC_REGNUM)
5387 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5388 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
5390 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
5391 (plus:GPR (match_dup 1) (match_dup 2)))]
5392 "s390_match_ccmode (insn, CCAmode)
5393 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5394 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5395 /* Avoid INT32_MIN on 32 bit. */
5396 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5402 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5403 (set_attr "cpu_facility" "*,z196,extimm,z10")
5404 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5407 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5410 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5411 ; FIXME: wfadb does not clobber cc
5412 (define_insn "add<mode>3"
5413 [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>")
5414 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>")
5415 (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))
5416 (clobber (reg:CC CC_REGNUM))]
5419 a<xde><bt>r\t%0,<op1>%2
5422 [(set_attr "op_type" "<RRer>,RXE,VRR")
5423 (set_attr "type" "fsimp<mode>")
5424 (set_attr "cpu_facility" "*,*,vec")])
5426 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5427 (define_insn "*add<mode>3_cc"
5428 [(set (reg CC_REGNUM)
5429 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5430 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5431 (match_operand:FP 3 "const0_operand" "")))
5432 (set (match_operand:FP 0 "register_operand" "=f,f")
5433 (plus:FP (match_dup 1) (match_dup 2)))]
5434 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5436 a<xde><bt>r\t%0,<op1>%2
5438 [(set_attr "op_type" "<RRer>,RXE")
5439 (set_attr "type" "fsimp<mode>")])
5441 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5442 (define_insn "*add<mode>3_cconly"
5443 [(set (reg CC_REGNUM)
5444 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5445 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5446 (match_operand:FP 3 "const0_operand" "")))
5447 (clobber (match_scratch:FP 0 "=f,f"))]
5448 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5450 a<xde><bt>r\t%0,<op1>%2
5452 [(set_attr "op_type" "<RRer>,RXE")
5453 (set_attr "type" "fsimp<mode>")])
5456 ; Pointer add instruction patterns
5459 ; This will match "*la_64"
5460 (define_expand "addptrdi3"
5461 [(set (match_operand:DI 0 "register_operand" "")
5462 (plus:DI (match_operand:DI 1 "register_operand" "")
5463 (match_operand:DI 2 "nonmemory_operand" "")))]
5466 if (GET_CODE (operands[2]) == CONST_INT)
5468 HOST_WIDE_INT c = INTVAL (operands[2]);
5470 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5471 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5473 operands[2] = force_const_mem (DImode, operands[2]);
5474 operands[2] = force_reg (DImode, operands[2]);
5476 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5477 operands[2] = force_reg (DImode, operands[2]);
5481 ; For 31 bit we have to prevent the generated pattern from matching
5482 ; normal ADDs since la only does a 31 bit add. This is supposed to
5483 ; match "force_la_31".
5484 (define_expand "addptrsi3"
5486 [(set (match_operand:SI 0 "register_operand" "")
5487 (plus:SI (match_operand:SI 1 "register_operand" "")
5488 (match_operand:SI 2 "nonmemory_operand" "")))
5489 (use (const_int 0))])]
5492 if (GET_CODE (operands[2]) == CONST_INT)
5494 HOST_WIDE_INT c = INTVAL (operands[2]);
5496 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5497 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5499 operands[2] = force_const_mem (SImode, operands[2]);
5500 operands[2] = force_reg (SImode, operands[2]);
5502 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5503 operands[2] = force_reg (SImode, operands[2]);
5508 ;;- Subtract instructions.
5512 ; subti3 instruction pattern(s).
5515 (define_expand "subti3"
5517 [(set (match_operand:TI 0 "register_operand" "")
5518 (minus:TI (match_operand:TI 1 "register_operand" "")
5519 (match_operand:TI 2 "general_operand" "") ) )
5520 (clobber (reg:CC CC_REGNUM))])]
5523 /* For z13 we have vaq which doesn't set CC. */
5526 emit_insn (gen_rtx_SET (operands[0],
5527 gen_rtx_MINUS (TImode,
5529 copy_to_mode_reg (TImode, operands[2]))));
5534 (define_insn_and_split "*subti3"
5535 [(set (match_operand:TI 0 "register_operand" "=&d")
5536 (minus:TI (match_operand:TI 1 "register_operand" "0")
5537 (match_operand:TI 2 "general_operand" "do") ) )
5538 (clobber (reg:CC CC_REGNUM))]
5541 "&& reload_completed"
5543 [(set (reg:CCL2 CC_REGNUM)
5544 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5546 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5548 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5549 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5550 (clobber (reg:CC CC_REGNUM))])]
5551 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5552 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5553 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5554 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5555 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5556 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5557 [(set_attr "op_type" "*")
5558 (set_attr "cpu_facility" "*")])
5561 ; subdi3 instruction pattern(s).
5564 (define_expand "subdi3"
5566 [(set (match_operand:DI 0 "register_operand" "")
5567 (minus:DI (match_operand:DI 1 "register_operand" "")
5568 (match_operand:DI 2 "general_operand" "")))
5569 (clobber (reg:CC CC_REGNUM))])]
5573 (define_insn "*subdi3_sign"
5574 [(set (match_operand:DI 0 "register_operand" "=d,d")
5575 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5576 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5577 (clobber (reg:CC CC_REGNUM))]
5582 [(set_attr "op_type" "RRE,RXY")
5583 (set_attr "z10prop" "z10_c,*")
5584 (set_attr "z196prop" "z196_cracked")])
5586 (define_insn "*subdi3_zero_cc"
5587 [(set (reg CC_REGNUM)
5588 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5589 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5591 (set (match_operand:DI 0 "register_operand" "=d,d")
5592 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5593 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5597 [(set_attr "op_type" "RRE,RXY")
5598 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5600 (define_insn "*subdi3_zero_cconly"
5601 [(set (reg CC_REGNUM)
5602 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5603 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5605 (clobber (match_scratch:DI 0 "=d,d"))]
5606 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5610 [(set_attr "op_type" "RRE,RXY")
5611 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5613 (define_insn "*subdi3_zero"
5614 [(set (match_operand:DI 0 "register_operand" "=d,d")
5615 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5616 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5617 (clobber (reg:CC CC_REGNUM))]
5622 [(set_attr "op_type" "RRE,RXY")
5623 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5625 (define_insn_and_split "*subdi3_31z"
5626 [(set (match_operand:DI 0 "register_operand" "=&d")
5627 (minus:DI (match_operand:DI 1 "register_operand" "0")
5628 (match_operand:DI 2 "general_operand" "do") ) )
5629 (clobber (reg:CC CC_REGNUM))]
5630 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5632 "&& reload_completed"
5634 [(set (reg:CCL2 CC_REGNUM)
5635 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5637 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5639 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5640 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5641 (clobber (reg:CC CC_REGNUM))])]
5642 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5643 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5644 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5645 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5646 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5647 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5649 (define_insn_and_split "*subdi3_31"
5650 [(set (match_operand:DI 0 "register_operand" "=&d")
5651 (minus:DI (match_operand:DI 1 "register_operand" "0")
5652 (match_operand:DI 2 "general_operand" "do") ) )
5653 (clobber (reg:CC CC_REGNUM))]
5656 "&& reload_completed"
5658 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5659 (clobber (reg:CC CC_REGNUM))])
5661 [(set (reg:CCL2 CC_REGNUM)
5662 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5664 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5666 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5668 (label_ref (match_dup 9))))
5670 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5671 (clobber (reg:CC CC_REGNUM))])
5673 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5674 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5675 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5676 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5677 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5678 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5679 operands[9] = gen_label_rtx ();")
5682 ; subsi3 instruction pattern(s).
5685 (define_expand "subsi3"
5687 [(set (match_operand:SI 0 "register_operand" "")
5688 (minus:SI (match_operand:SI 1 "register_operand" "")
5689 (match_operand:SI 2 "general_operand" "")))
5690 (clobber (reg:CC CC_REGNUM))])]
5694 (define_insn "*subsi3_sign"
5695 [(set (match_operand:SI 0 "register_operand" "=d,d")
5696 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5697 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5698 (clobber (reg:CC CC_REGNUM))]
5703 [(set_attr "op_type" "RX,RXY")
5704 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5707 ; sub(di|si)3 instruction pattern(s).
5710 ; sr, s, sy, sgr, sg, srk, sgrk
5711 (define_insn "*sub<mode>3"
5712 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5713 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5714 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5715 (clobber (reg:CC CC_REGNUM))]
5722 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5723 (set_attr "cpu_facility" "*,z196,*,*")
5724 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5726 ; slr, sl, sly, slgr, slg, slrk, slgrk
5727 (define_insn "*sub<mode>3_borrow_cc"
5728 [(set (reg CC_REGNUM)
5729 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5730 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5732 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5733 (minus:GPR (match_dup 1) (match_dup 2)))]
5734 "s390_match_ccmode (insn, CCL2mode)"
5740 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5741 (set_attr "cpu_facility" "*,z196,*,*")
5742 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5744 ; slr, sl, sly, slgr, slg, slrk, slgrk
5745 (define_insn "*sub<mode>3_borrow_cconly"
5746 [(set (reg CC_REGNUM)
5747 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5748 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5750 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5751 "s390_match_ccmode (insn, CCL2mode)"
5757 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5758 (set_attr "cpu_facility" "*,z196,*,*")
5759 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5761 ; slr, sl, sly, slgr, slg, slrk, slgrk
5762 (define_insn "*sub<mode>3_cc"
5763 [(set (reg CC_REGNUM)
5764 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5765 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5767 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5768 (minus:GPR (match_dup 1) (match_dup 2)))]
5769 "s390_match_ccmode (insn, CCLmode)"
5775 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5776 (set_attr "cpu_facility" "*,z196,*,*")
5777 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5779 ; slr, sl, sly, slgr, slg, slrk, slgrk
5780 (define_insn "*sub<mode>3_cc2"
5781 [(set (reg CC_REGNUM)
5782 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5783 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5784 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5785 (minus:GPR (match_dup 1) (match_dup 2)))]
5786 "s390_match_ccmode (insn, CCL3mode)"
5792 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5793 (set_attr "cpu_facility" "*,z196,*,*")
5794 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5796 ; slr, sl, sly, slgr, slg, slrk, slgrk
5797 (define_insn "*sub<mode>3_cconly"
5798 [(set (reg CC_REGNUM)
5799 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5800 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5802 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5803 "s390_match_ccmode (insn, CCLmode)"
5809 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5810 (set_attr "cpu_facility" "*,z196,*,*")
5811 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5814 ; slr, sl, sly, slgr, slg, slrk, slgrk
5815 (define_insn "*sub<mode>3_cconly2"
5816 [(set (reg CC_REGNUM)
5817 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5818 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5819 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5820 "s390_match_ccmode (insn, CCL3mode)"
5826 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5827 (set_attr "cpu_facility" "*,z196,*,*")
5828 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5832 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5835 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5836 (define_insn "sub<mode>3"
5837 [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>")
5838 (minus:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>")
5839 (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))
5840 (clobber (reg:CC CC_REGNUM))]
5843 s<xde><bt>r\t%0,<op1>%2
5846 [(set_attr "op_type" "<RRer>,RXE,VRR")
5847 (set_attr "type" "fsimp<mode>")
5848 (set_attr "cpu_facility" "*,*,vec")])
5850 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5851 (define_insn "*sub<mode>3_cc"
5852 [(set (reg CC_REGNUM)
5853 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5854 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5855 (match_operand:FP 3 "const0_operand" "")))
5856 (set (match_operand:FP 0 "register_operand" "=f,f")
5857 (minus:FP (match_dup 1) (match_dup 2)))]
5858 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5860 s<xde><bt>r\t%0,<op1>%2
5862 [(set_attr "op_type" "<RRer>,RXE")
5863 (set_attr "type" "fsimp<mode>")])
5865 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5866 (define_insn "*sub<mode>3_cconly"
5867 [(set (reg CC_REGNUM)
5868 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5869 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5870 (match_operand:FP 3 "const0_operand" "")))
5871 (clobber (match_scratch:FP 0 "=f,f"))]
5872 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5874 s<xde><bt>r\t%0,<op1>%2
5876 [(set_attr "op_type" "<RRer>,RXE")
5877 (set_attr "type" "fsimp<mode>")])
5881 ;;- Conditional add/subtract instructions.
5885 ; add(di|si)cc instruction pattern(s).
5888 ; the following 4 patterns are used when the result of an add with
5889 ; carry is checked for an overflow condition
5891 ; op1 + op2 + c < op1
5893 ; alcr, alc, alcgr, alcg
5894 (define_insn "*add<mode>3_alc_carry1_cc"
5895 [(set (reg CC_REGNUM)
5897 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5898 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5899 (match_operand:GPR 2 "general_operand" "d,RT"))
5901 (set (match_operand:GPR 0 "register_operand" "=d,d")
5902 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5903 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5907 [(set_attr "op_type" "RRE,RXY")
5908 (set_attr "z196prop" "z196_alone,z196_alone")])
5910 ; alcr, alc, alcgr, alcg
5911 (define_insn "*add<mode>3_alc_carry1_cconly"
5912 [(set (reg CC_REGNUM)
5914 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5915 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5916 (match_operand:GPR 2 "general_operand" "d,RT"))
5918 (clobber (match_scratch:GPR 0 "=d,d"))]
5919 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5923 [(set_attr "op_type" "RRE,RXY")
5924 (set_attr "z196prop" "z196_alone,z196_alone")])
5926 ; op1 + op2 + c < op2
5928 ; alcr, alc, alcgr, alcg
5929 (define_insn "*add<mode>3_alc_carry2_cc"
5930 [(set (reg CC_REGNUM)
5932 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5933 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5934 (match_operand:GPR 2 "general_operand" "d,RT"))
5936 (set (match_operand:GPR 0 "register_operand" "=d,d")
5937 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5938 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5942 [(set_attr "op_type" "RRE,RXY")])
5944 ; alcr, alc, alcgr, alcg
5945 (define_insn "*add<mode>3_alc_carry2_cconly"
5946 [(set (reg CC_REGNUM)
5948 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5949 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5950 (match_operand:GPR 2 "general_operand" "d,RT"))
5952 (clobber (match_scratch:GPR 0 "=d,d"))]
5953 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5957 [(set_attr "op_type" "RRE,RXY")])
5959 ; alcr, alc, alcgr, alcg
5960 (define_insn "*add<mode>3_alc_cc"
5961 [(set (reg CC_REGNUM)
5963 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5964 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5965 (match_operand:GPR 2 "general_operand" "d,RT"))
5967 (set (match_operand:GPR 0 "register_operand" "=d,d")
5968 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5969 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5973 [(set_attr "op_type" "RRE,RXY")])
5975 ; alcr, alc, alcgr, alcg
5976 (define_insn "*add<mode>3_alc"
5977 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5978 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5979 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5980 (match_operand:GPR 2 "general_operand" "d,RT")))
5981 (clobber (reg:CC CC_REGNUM))]
5986 [(set_attr "op_type" "RRE,RXY")])
5988 ; slbr, slb, slbgr, slbg
5989 (define_insn "*sub<mode>3_slb_cc"
5990 [(set (reg CC_REGNUM)
5992 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5993 (match_operand:GPR 2 "general_operand" "d,RT"))
5994 (match_operand:GPR 3 "s390_slb_comparison" ""))
5996 (set (match_operand:GPR 0 "register_operand" "=d,d")
5997 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5998 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6002 [(set_attr "op_type" "RRE,RXY")
6003 (set_attr "z10prop" "z10_c,*")])
6005 ; slbr, slb, slbgr, slbg
6006 (define_insn "*sub<mode>3_slb"
6007 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6008 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6009 (match_operand:GPR 2 "general_operand" "d,RT"))
6010 (match_operand:GPR 3 "s390_slb_comparison" "")))
6011 (clobber (reg:CC CC_REGNUM))]
6016 [(set_attr "op_type" "RRE,RXY")
6017 (set_attr "z10prop" "z10_c,*")])
6019 (define_expand "add<mode>cc"
6020 [(match_operand:GPR 0 "register_operand" "")
6021 (match_operand 1 "comparison_operator" "")
6022 (match_operand:GPR 2 "register_operand" "")
6023 (match_operand:GPR 3 "const_int_operand" "")]
6025 "if (!s390_expand_addcc (GET_CODE (operands[1]),
6026 XEXP (operands[1], 0), XEXP (operands[1], 1),
6027 operands[0], operands[2],
6028 operands[3])) FAIL; DONE;")
6031 ; scond instruction pattern(s).
6034 (define_insn_and_split "*scond<mode>"
6035 [(set (match_operand:GPR 0 "register_operand" "=&d")
6036 (match_operand:GPR 1 "s390_alc_comparison" ""))
6037 (clobber (reg:CC CC_REGNUM))]
6040 "&& reload_completed"
6041 [(set (match_dup 0) (const_int 0))
6043 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6045 (clobber (reg:CC CC_REGNUM))])]
6048 (define_insn_and_split "*scond<mode>_neg"
6049 [(set (match_operand:GPR 0 "register_operand" "=&d")
6050 (match_operand:GPR 1 "s390_slb_comparison" ""))
6051 (clobber (reg:CC CC_REGNUM))]
6054 "&& reload_completed"
6055 [(set (match_dup 0) (const_int 0))
6057 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6059 (clobber (reg:CC CC_REGNUM))])
6061 [(set (match_dup 0) (neg:GPR (match_dup 0)))
6062 (clobber (reg:CC CC_REGNUM))])]
6066 (define_expand "cstore<mode>4"
6067 [(set (match_operand:SI 0 "register_operand" "")
6068 (match_operator:SI 1 "s390_scond_operator"
6069 [(match_operand:GPR 2 "register_operand" "")
6070 (match_operand:GPR 3 "general_operand" "")]))]
6072 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6073 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6075 (define_expand "cstorecc4"
6077 [(set (match_operand:SI 0 "register_operand" "")
6078 (match_operator:SI 1 "s390_eqne_operator"
6079 [(match_operand:CCZ1 2 "register_operand")
6080 (match_operand 3 "const0_operand")]))
6081 (clobber (reg:CC CC_REGNUM))])]
6083 "emit_insn (gen_sne (operands[0], operands[2]));
6084 if (GET_CODE (operands[1]) == EQ)
6085 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6088 (define_insn_and_split "sne"
6089 [(set (match_operand:SI 0 "register_operand" "=d")
6090 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6092 (clobber (reg:CC CC_REGNUM))]
6097 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6098 (clobber (reg:CC CC_REGNUM))])])
6102 ;; - Conditional move instructions (introduced with z196)
6105 (define_expand "mov<mode>cc"
6106 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6107 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6108 (match_operand:GPR 2 "nonimmediate_operand" "")
6109 (match_operand:GPR 3 "nonimmediate_operand" "")))]
6111 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6112 XEXP (operands[1], 0), XEXP (operands[1], 1));")
6114 ; locr, loc, stoc, locgr, locg, stocg
6115 (define_insn_and_split "*mov<mode>cc"
6116 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
6118 (match_operator 1 "s390_comparison"
6119 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
6120 (match_operand 5 "const_int_operand" "")])
6121 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
6122 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
6132 "&& reload_completed
6133 && MEM_P (operands[3]) && MEM_P (operands[4])"
6136 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6141 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6145 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
6148 ;;- Multiply instructions.
6152 ; muldi3 instruction pattern(s).
6155 (define_insn "*muldi3_sign"
6156 [(set (match_operand:DI 0 "register_operand" "=d,d")
6157 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
6158 (match_operand:DI 1 "register_operand" "0,0")))]
6163 [(set_attr "op_type" "RRE,RXY")
6164 (set_attr "type" "imuldi")])
6166 (define_insn "muldi3"
6167 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6168 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6169 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
6176 [(set_attr "op_type" "RRE,RI,RXY,RIL")
6177 (set_attr "type" "imuldi")
6178 (set_attr "cpu_facility" "*,*,*,z10")])
6181 ; mulsi3 instruction pattern(s).
6184 (define_insn "*mulsi3_sign"
6185 [(set (match_operand:SI 0 "register_operand" "=d,d")
6186 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6187 (match_operand:SI 1 "register_operand" "0,0")))]
6192 [(set_attr "op_type" "RX,RXY")
6193 (set_attr "type" "imulhi")
6194 (set_attr "cpu_facility" "*,z10")])
6196 (define_insn "mulsi3"
6197 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6198 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6199 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6207 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
6208 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
6209 (set_attr "cpu_facility" "*,*,*,*,z10")])
6212 ; mulsidi3 instruction pattern(s).
6215 (define_insn "mulsidi3"
6216 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6217 (mult:DI (sign_extend:DI
6218 (match_operand:SI 1 "register_operand" "%0,0,0"))
6220 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6226 [(set_attr "op_type" "RR,RX,RXY")
6227 (set_attr "type" "imulsi")
6228 (set_attr "cpu_facility" "*,*,z10")])
6231 ; umul instruction pattern(s).
6234 ; mlr, ml, mlgr, mlg
6235 (define_insn "umul<dwh><mode>3"
6236 [(set (match_operand:DW 0 "register_operand" "=d, d")
6237 (mult:DW (zero_extend:DW
6238 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
6240 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
6245 [(set_attr "op_type" "RRE,RXY")
6246 (set_attr "type" "imul<dwh>")])
6249 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6252 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6253 (define_insn "mul<mode>3"
6254 [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>")
6255 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>")
6256 (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))]
6259 m<xdee><bt>r\t%0,<op1>%2
6262 [(set_attr "op_type" "<RRer>,RXE,VRR")
6263 (set_attr "type" "fmul<mode>")
6264 (set_attr "cpu_facility" "*,*,vec")])
6266 ; madbr, maebr, maxb, madb, maeb
6267 (define_insn "fma<mode>4"
6268 [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>")
6269 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
6270 (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>")
6271 (match_operand:DSF 3 "register_operand" "0,0,<v0>")))]
6276 wfmadb\t%v0,%v1,%v2,%v3"
6277 [(set_attr "op_type" "RRE,RXE,VRR")
6278 (set_attr "type" "fmadd<mode>")
6279 (set_attr "cpu_facility" "*,*,vec")])
6281 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6282 (define_insn "fms<mode>4"
6283 [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>")
6284 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
6285 (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>")
6286 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,<v0>"))))]
6291 wfmsdb\t%v0,%v1,%v2,%v3"
6292 [(set_attr "op_type" "RRE,RXE,VRR")
6293 (set_attr "type" "fmadd<mode>")
6294 (set_attr "cpu_facility" "*,*,vec")])
6297 ;;- Divide and modulo instructions.
6301 ; divmoddi4 instruction pattern(s).
6304 (define_expand "divmoddi4"
6305 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6306 (div:DI (match_operand:DI 1 "register_operand" "")
6307 (match_operand:DI 2 "general_operand" "")))
6308 (set (match_operand:DI 3 "general_operand" "")
6309 (mod:DI (match_dup 1) (match_dup 2)))])
6310 (clobber (match_dup 4))]
6313 rtx insn, div_equal, mod_equal;
6315 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6316 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6318 operands[4] = gen_reg_rtx(TImode);
6319 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6321 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6322 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6324 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6325 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6330 (define_insn "divmodtidi3"
6331 [(set (match_operand:TI 0 "register_operand" "=d,d")
6335 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6336 (match_operand:DI 2 "general_operand" "d,RT")))
6338 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6343 [(set_attr "op_type" "RRE,RXY")
6344 (set_attr "type" "idiv")])
6346 (define_insn "divmodtisi3"
6347 [(set (match_operand:TI 0 "register_operand" "=d,d")
6351 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6353 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
6356 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6361 [(set_attr "op_type" "RRE,RXY")
6362 (set_attr "type" "idiv")])
6365 ; udivmoddi4 instruction pattern(s).
6368 (define_expand "udivmoddi4"
6369 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6370 (udiv:DI (match_operand:DI 1 "general_operand" "")
6371 (match_operand:DI 2 "nonimmediate_operand" "")))
6372 (set (match_operand:DI 3 "general_operand" "")
6373 (umod:DI (match_dup 1) (match_dup 2)))])
6374 (clobber (match_dup 4))]
6377 rtx insn, div_equal, mod_equal, equal;
6379 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6380 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6381 equal = gen_rtx_IOR (TImode,
6382 gen_rtx_ASHIFT (TImode,
6383 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6385 gen_rtx_ZERO_EXTEND (TImode, div_equal));
6387 operands[4] = gen_reg_rtx(TImode);
6388 emit_clobber (operands[4]);
6389 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6390 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6392 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6393 set_unique_reg_note (insn, REG_EQUAL, equal);
6395 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6396 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6398 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6399 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6404 (define_insn "udivmodtidi3"
6405 [(set (match_operand:TI 0 "register_operand" "=d,d")
6410 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6412 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6416 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6421 [(set_attr "op_type" "RRE,RXY")
6422 (set_attr "type" "idiv")])
6425 ; divmodsi4 instruction pattern(s).
6428 (define_expand "divmodsi4"
6429 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6430 (div:SI (match_operand:SI 1 "general_operand" "")
6431 (match_operand:SI 2 "nonimmediate_operand" "")))
6432 (set (match_operand:SI 3 "general_operand" "")
6433 (mod:SI (match_dup 1) (match_dup 2)))])
6434 (clobber (match_dup 4))]
6437 rtx insn, div_equal, mod_equal, equal;
6439 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6440 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6441 equal = gen_rtx_IOR (DImode,
6442 gen_rtx_ASHIFT (DImode,
6443 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6445 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6447 operands[4] = gen_reg_rtx(DImode);
6448 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6450 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6451 set_unique_reg_note (insn, REG_EQUAL, equal);
6453 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6454 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6456 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6457 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6462 (define_insn "divmoddisi3"
6463 [(set (match_operand:DI 0 "register_operand" "=d,d")
6468 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6470 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6474 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6479 [(set_attr "op_type" "RR,RX")
6480 (set_attr "type" "idiv")])
6483 ; udivsi3 and umodsi3 instruction pattern(s).
6486 (define_expand "udivmodsi4"
6487 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6488 (udiv:SI (match_operand:SI 1 "general_operand" "")
6489 (match_operand:SI 2 "nonimmediate_operand" "")))
6490 (set (match_operand:SI 3 "general_operand" "")
6491 (umod:SI (match_dup 1) (match_dup 2)))])
6492 (clobber (match_dup 4))]
6493 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6495 rtx insn, div_equal, mod_equal, equal;
6497 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6498 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6499 equal = gen_rtx_IOR (DImode,
6500 gen_rtx_ASHIFT (DImode,
6501 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6503 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6505 operands[4] = gen_reg_rtx(DImode);
6506 emit_clobber (operands[4]);
6507 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6508 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6510 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6511 set_unique_reg_note (insn, REG_EQUAL, equal);
6513 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6514 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6516 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6517 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6522 (define_insn "udivmoddisi3"
6523 [(set (match_operand:DI 0 "register_operand" "=d,d")
6528 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6530 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6534 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6535 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6539 [(set_attr "op_type" "RRE,RXY")
6540 (set_attr "type" "idiv")])
6542 (define_expand "udivsi3"
6543 [(set (match_operand:SI 0 "register_operand" "=d")
6544 (udiv:SI (match_operand:SI 1 "general_operand" "")
6545 (match_operand:SI 2 "general_operand" "")))
6546 (clobber (match_dup 3))]
6547 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6549 rtx insn, udiv_equal, umod_equal, equal;
6551 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6552 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6553 equal = gen_rtx_IOR (DImode,
6554 gen_rtx_ASHIFT (DImode,
6555 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6557 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6559 operands[3] = gen_reg_rtx (DImode);
6561 if (CONSTANT_P (operands[2]))
6563 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6565 rtx_code_label *label1 = gen_label_rtx ();
6567 operands[1] = make_safe_from (operands[1], operands[0]);
6568 emit_move_insn (operands[0], const0_rtx);
6569 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6571 emit_move_insn (operands[0], const1_rtx);
6572 emit_label (label1);
6576 operands[2] = force_reg (SImode, operands[2]);
6577 operands[2] = make_safe_from (operands[2], operands[0]);
6579 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6580 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6582 set_unique_reg_note (insn, REG_EQUAL, equal);
6584 insn = emit_move_insn (operands[0],
6585 gen_lowpart (SImode, operands[3]));
6586 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6591 rtx_code_label *label1 = gen_label_rtx ();
6592 rtx_code_label *label2 = gen_label_rtx ();
6593 rtx_code_label *label3 = gen_label_rtx ();
6595 operands[1] = force_reg (SImode, operands[1]);
6596 operands[1] = make_safe_from (operands[1], operands[0]);
6597 operands[2] = force_reg (SImode, operands[2]);
6598 operands[2] = make_safe_from (operands[2], operands[0]);
6600 emit_move_insn (operands[0], const0_rtx);
6601 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6603 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6605 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6607 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6608 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6610 set_unique_reg_note (insn, REG_EQUAL, equal);
6612 insn = emit_move_insn (operands[0],
6613 gen_lowpart (SImode, operands[3]));
6614 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6617 emit_label (label1);
6618 emit_move_insn (operands[0], operands[1]);
6620 emit_label (label2);
6621 emit_move_insn (operands[0], const1_rtx);
6622 emit_label (label3);
6624 emit_move_insn (operands[0], operands[0]);
6628 (define_expand "umodsi3"
6629 [(set (match_operand:SI 0 "register_operand" "=d")
6630 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6631 (match_operand:SI 2 "nonimmediate_operand" "")))
6632 (clobber (match_dup 3))]
6633 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6635 rtx insn, udiv_equal, umod_equal, equal;
6637 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6638 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6639 equal = gen_rtx_IOR (DImode,
6640 gen_rtx_ASHIFT (DImode,
6641 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6643 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6645 operands[3] = gen_reg_rtx (DImode);
6647 if (CONSTANT_P (operands[2]))
6649 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6651 rtx_code_label *label1 = gen_label_rtx ();
6653 operands[1] = make_safe_from (operands[1], operands[0]);
6654 emit_move_insn (operands[0], operands[1]);
6655 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6657 emit_insn (gen_abssi2 (operands[0], operands[2]));
6658 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6659 emit_label (label1);
6663 operands[2] = force_reg (SImode, operands[2]);
6664 operands[2] = make_safe_from (operands[2], operands[0]);
6666 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6667 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6669 set_unique_reg_note (insn, REG_EQUAL, equal);
6671 insn = emit_move_insn (operands[0],
6672 gen_highpart (SImode, operands[3]));
6673 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6678 rtx_code_label *label1 = gen_label_rtx ();
6679 rtx_code_label *label2 = gen_label_rtx ();
6680 rtx_code_label *label3 = gen_label_rtx ();
6682 operands[1] = force_reg (SImode, operands[1]);
6683 operands[1] = make_safe_from (operands[1], operands[0]);
6684 operands[2] = force_reg (SImode, operands[2]);
6685 operands[2] = make_safe_from (operands[2], operands[0]);
6687 emit_move_insn(operands[0], operands[1]);
6688 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6690 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6692 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6694 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6695 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6697 set_unique_reg_note (insn, REG_EQUAL, equal);
6699 insn = emit_move_insn (operands[0],
6700 gen_highpart (SImode, operands[3]));
6701 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6704 emit_label (label1);
6705 emit_move_insn (operands[0], const0_rtx);
6707 emit_label (label2);
6708 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6709 emit_label (label3);
6715 ; div(df|sf)3 instruction pattern(s).
6718 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6719 (define_insn "div<mode>3"
6720 [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>")
6721 (div:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>")
6722 (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))]
6725 d<xde><bt>r\t%0,<op1>%2
6728 [(set_attr "op_type" "<RRer>,RXE,VRR")
6729 (set_attr "type" "fdiv<mode>")
6730 (set_attr "cpu_facility" "*,*,vec")])
6734 ;;- And instructions.
6737 (define_expand "and<mode>3"
6738 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6739 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6740 (match_operand:INT 2 "general_operand" "")))
6741 (clobber (reg:CC CC_REGNUM))]
6743 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6746 ; anddi3 instruction pattern(s).
6749 (define_insn "*anddi3_cc"
6750 [(set (reg CC_REGNUM)
6752 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6753 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6755 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6756 (and:DI (match_dup 1) (match_dup 2)))]
6757 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6762 risbg\t%0,%1,%s2,128+%e2,0"
6763 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6764 (set_attr "cpu_facility" "*,z196,*,z10")
6765 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6767 (define_insn "*anddi3_cconly"
6768 [(set (reg CC_REGNUM)
6770 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6771 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6773 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6775 && s390_match_ccmode(insn, CCTmode)
6776 /* Do not steal TM patterns. */
6777 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6782 risbg\t%0,%1,%s2,128+%e2,0"
6783 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6784 (set_attr "cpu_facility" "*,z196,*,z10")
6785 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6787 (define_insn "*anddi3"
6788 [(set (match_operand:DI 0 "nonimmediate_operand"
6789 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6791 (match_operand:DI 1 "nonimmediate_operand"
6792 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6793 (match_operand:DI 2 "general_operand"
6794 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6795 (clobber (reg:CC CC_REGNUM))]
6796 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6809 risbg\t%0,%1,%s2,128+%e2,0
6812 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6813 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6814 (set_attr "z10prop" "*,
6830 [(set (match_operand:DI 0 "s_operand" "")
6831 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6832 (clobber (reg:CC CC_REGNUM))]
6835 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6836 (clobber (reg:CC CC_REGNUM))])]
6837 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6839 ;; These two are what combine generates for (ashift (zero_extract)).
6840 (define_insn "*extzv_<mode>_srl"
6841 [(set (match_operand:GPR 0 "register_operand" "=d")
6842 (and:GPR (lshiftrt:GPR
6843 (match_operand:GPR 1 "register_operand" "d")
6844 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6845 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6846 (clobber (reg:CC CC_REGNUM))]
6848 /* Note that even for the SImode pattern, the rotate is always DImode. */
6849 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6850 INTVAL (operands[3]))"
6851 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6852 [(set_attr "op_type" "RIE")
6853 (set_attr "z10prop" "z10_super_E1")])
6855 (define_insn "*extzv_<mode>_sll"
6856 [(set (match_operand:GPR 0 "register_operand" "=d")
6857 (and:GPR (ashift:GPR
6858 (match_operand:GPR 1 "register_operand" "d")
6859 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6860 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6861 (clobber (reg:CC CC_REGNUM))]
6863 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6864 INTVAL (operands[3]))"
6865 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6866 [(set_attr "op_type" "RIE")
6867 (set_attr "z10prop" "z10_super_E1")])
6871 ; andsi3 instruction pattern(s).
6874 (define_insn "*andsi3_cc"
6875 [(set (reg CC_REGNUM)
6878 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6879 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6881 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6882 (and:SI (match_dup 1) (match_dup 2)))]
6883 "s390_match_ccmode(insn, CCTmode)"
6890 risbg\t%0,%1,%t2,128+%f2,0"
6891 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6892 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6893 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6894 z10_super_E1,z10_super_E1,z10_super_E1")])
6896 (define_insn "*andsi3_cconly"
6897 [(set (reg CC_REGNUM)
6900 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6901 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6903 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6904 "s390_match_ccmode(insn, CCTmode)
6905 /* Do not steal TM patterns. */
6906 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6913 risbg\t%0,%1,%t2,128+%f2,0"
6914 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6915 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6916 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6917 z10_super_E1,z10_super_E1,z10_super_E1")])
6919 (define_insn "*andsi3_zarch"
6920 [(set (match_operand:SI 0 "nonimmediate_operand"
6921 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6922 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6923 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6924 (match_operand:SI 2 "general_operand"
6925 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6926 (clobber (reg:CC CC_REGNUM))]
6927 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6938 risbg\t%0,%1,%t2,128+%f2,0
6941 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6942 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6943 (set_attr "z10prop" "*,
6956 (define_insn "*andsi3_esa"
6957 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6958 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6959 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6960 (clobber (reg:CC CC_REGNUM))]
6961 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6967 [(set_attr "op_type" "RR,RX,SI,SS")
6968 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6972 [(set (match_operand:SI 0 "s_operand" "")
6973 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6974 (clobber (reg:CC CC_REGNUM))]
6977 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6978 (clobber (reg:CC CC_REGNUM))])]
6979 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6982 ; andhi3 instruction pattern(s).
6985 (define_insn "*andhi3_zarch"
6986 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6987 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6988 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6989 (clobber (reg:CC CC_REGNUM))]
6990 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6997 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6998 (set_attr "cpu_facility" "*,z196,*,*,*")
6999 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7002 (define_insn "*andhi3_esa"
7003 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7004 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7005 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7006 (clobber (reg:CC CC_REGNUM))]
7007 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7012 [(set_attr "op_type" "RR,SI,SS")
7013 (set_attr "z10prop" "z10_super_E1,*,*")
7017 [(set (match_operand:HI 0 "s_operand" "")
7018 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7019 (clobber (reg:CC CC_REGNUM))]
7022 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7023 (clobber (reg:CC CC_REGNUM))])]
7024 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7027 ; andqi3 instruction pattern(s).
7030 (define_insn "*andqi3_zarch"
7031 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7032 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7033 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7034 (clobber (reg:CC CC_REGNUM))]
7035 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7043 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7044 (set_attr "cpu_facility" "*,z196,*,*,*,*")
7045 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7047 (define_insn "*andqi3_esa"
7048 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7049 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7050 (match_operand:QI 2 "general_operand" "d,n,Q")))
7051 (clobber (reg:CC CC_REGNUM))]
7052 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7057 [(set_attr "op_type" "RR,SI,SS")
7058 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7061 ; Block and (NC) patterns.
7065 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7066 (and:BLK (match_dup 0)
7067 (match_operand:BLK 1 "memory_operand" "Q")))
7068 (use (match_operand 2 "const_int_operand" "n"))
7069 (clobber (reg:CC CC_REGNUM))]
7070 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7071 "nc\t%O0(%2,%R0),%S1"
7072 [(set_attr "op_type" "SS")
7073 (set_attr "z196prop" "z196_cracked")])
7076 [(set (match_operand 0 "memory_operand" "")
7078 (match_operand 1 "memory_operand" "")))
7079 (clobber (reg:CC CC_REGNUM))]
7081 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7082 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7084 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7086 (clobber (reg:CC CC_REGNUM))])]
7088 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7089 operands[0] = adjust_address (operands[0], BLKmode, 0);
7090 operands[1] = adjust_address (operands[1], BLKmode, 0);
7095 [(set (match_operand:BLK 0 "memory_operand" "")
7096 (and:BLK (match_dup 0)
7097 (match_operand:BLK 1 "memory_operand" "")))
7098 (use (match_operand 2 "const_int_operand" ""))
7099 (clobber (reg:CC CC_REGNUM))])
7101 [(set (match_operand:BLK 3 "memory_operand" "")
7102 (and:BLK (match_dup 3)
7103 (match_operand:BLK 4 "memory_operand" "")))
7104 (use (match_operand 5 "const_int_operand" ""))
7105 (clobber (reg:CC CC_REGNUM))])]
7106 "s390_offset_p (operands[0], operands[3], operands[2])
7107 && s390_offset_p (operands[1], operands[4], operands[2])
7108 && !s390_overlap_p (operands[0], operands[1],
7109 INTVAL (operands[2]) + INTVAL (operands[5]))
7110 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7112 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7114 (clobber (reg:CC CC_REGNUM))])]
7115 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7116 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7117 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7121 ;;- Bit set (inclusive or) instructions.
7124 (define_expand "ior<mode>3"
7125 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7126 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7127 (match_operand:INT 2 "general_operand" "")))
7128 (clobber (reg:CC CC_REGNUM))]
7130 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7133 ; iordi3 instruction pattern(s).
7136 (define_insn "*iordi3_cc"
7137 [(set (reg CC_REGNUM)
7138 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7139 (match_operand:DI 2 "general_operand" " d,d,RT"))
7141 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7142 (ior:DI (match_dup 1) (match_dup 2)))]
7143 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7148 [(set_attr "op_type" "RRE,RRF,RXY")
7149 (set_attr "cpu_facility" "*,z196,*")
7150 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7152 (define_insn "*iordi3_cconly"
7153 [(set (reg CC_REGNUM)
7154 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7155 (match_operand:DI 2 "general_operand" " d,d,RT"))
7157 (clobber (match_scratch:DI 0 "=d,d,d"))]
7158 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7163 [(set_attr "op_type" "RRE,RRF,RXY")
7164 (set_attr "cpu_facility" "*,z196,*")
7165 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7167 (define_insn "*iordi3"
7168 [(set (match_operand:DI 0 "nonimmediate_operand"
7169 "=d, d, d, d, d, d,d,d, d, AQ,Q")
7170 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7171 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
7172 (match_operand:DI 2 "general_operand"
7173 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7174 (clobber (reg:CC CC_REGNUM))]
7175 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7188 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7189 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7190 (set_attr "z10prop" "z10_super_E1,
7203 [(set (match_operand:DI 0 "s_operand" "")
7204 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7205 (clobber (reg:CC CC_REGNUM))]
7208 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7209 (clobber (reg:CC CC_REGNUM))])]
7210 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7213 ; iorsi3 instruction pattern(s).
7216 (define_insn "*iorsi3_cc"
7217 [(set (reg CC_REGNUM)
7218 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7219 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7221 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7222 (ior:SI (match_dup 1) (match_dup 2)))]
7223 "s390_match_ccmode(insn, CCTmode)"
7230 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7231 (set_attr "cpu_facility" "*,*,z196,*,*")
7232 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7234 (define_insn "*iorsi3_cconly"
7235 [(set (reg CC_REGNUM)
7236 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7237 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7239 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7240 "s390_match_ccmode(insn, CCTmode)"
7247 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7248 (set_attr "cpu_facility" "*,*,z196,*,*")
7249 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7251 (define_insn "*iorsi3_zarch"
7252 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
7253 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
7254 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7255 (clobber (reg:CC CC_REGNUM))]
7256 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7267 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7268 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
7269 (set_attr "z10prop" "z10_super_E1,
7279 (define_insn "*iorsi3_esa"
7280 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7281 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7282 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7283 (clobber (reg:CC CC_REGNUM))]
7284 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7290 [(set_attr "op_type" "RR,RX,SI,SS")
7291 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7294 [(set (match_operand:SI 0 "s_operand" "")
7295 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7296 (clobber (reg:CC CC_REGNUM))]
7299 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7300 (clobber (reg:CC CC_REGNUM))])]
7301 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7304 ; iorhi3 instruction pattern(s).
7307 (define_insn "*iorhi3_zarch"
7308 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7309 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7310 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
7311 (clobber (reg:CC CC_REGNUM))]
7312 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7319 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7320 (set_attr "cpu_facility" "*,z196,*,*,*")
7321 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7323 (define_insn "*iorhi3_esa"
7324 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7325 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7326 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7327 (clobber (reg:CC CC_REGNUM))]
7328 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7333 [(set_attr "op_type" "RR,SI,SS")
7334 (set_attr "z10prop" "z10_super_E1,*,*")])
7337 [(set (match_operand:HI 0 "s_operand" "")
7338 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7339 (clobber (reg:CC CC_REGNUM))]
7342 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7343 (clobber (reg:CC CC_REGNUM))])]
7344 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7347 ; iorqi3 instruction pattern(s).
7350 (define_insn "*iorqi3_zarch"
7351 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7352 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7353 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7354 (clobber (reg:CC CC_REGNUM))]
7355 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7363 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7364 (set_attr "cpu_facility" "*,z196,*,*,*,*")
7365 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7366 z10_super,z10_super,*")])
7368 (define_insn "*iorqi3_esa"
7369 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7370 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7371 (match_operand:QI 2 "general_operand" "d,n,Q")))
7372 (clobber (reg:CC CC_REGNUM))]
7373 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7378 [(set_attr "op_type" "RR,SI,SS")
7379 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7382 ; Block inclusive or (OC) patterns.
7386 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7387 (ior:BLK (match_dup 0)
7388 (match_operand:BLK 1 "memory_operand" "Q")))
7389 (use (match_operand 2 "const_int_operand" "n"))
7390 (clobber (reg:CC CC_REGNUM))]
7391 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7392 "oc\t%O0(%2,%R0),%S1"
7393 [(set_attr "op_type" "SS")
7394 (set_attr "z196prop" "z196_cracked")])
7397 [(set (match_operand 0 "memory_operand" "")
7399 (match_operand 1 "memory_operand" "")))
7400 (clobber (reg:CC CC_REGNUM))]
7402 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7403 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7405 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7407 (clobber (reg:CC CC_REGNUM))])]
7409 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7410 operands[0] = adjust_address (operands[0], BLKmode, 0);
7411 operands[1] = adjust_address (operands[1], BLKmode, 0);
7416 [(set (match_operand:BLK 0 "memory_operand" "")
7417 (ior:BLK (match_dup 0)
7418 (match_operand:BLK 1 "memory_operand" "")))
7419 (use (match_operand 2 "const_int_operand" ""))
7420 (clobber (reg:CC CC_REGNUM))])
7422 [(set (match_operand:BLK 3 "memory_operand" "")
7423 (ior:BLK (match_dup 3)
7424 (match_operand:BLK 4 "memory_operand" "")))
7425 (use (match_operand 5 "const_int_operand" ""))
7426 (clobber (reg:CC CC_REGNUM))])]
7427 "s390_offset_p (operands[0], operands[3], operands[2])
7428 && s390_offset_p (operands[1], operands[4], operands[2])
7429 && !s390_overlap_p (operands[0], operands[1],
7430 INTVAL (operands[2]) + INTVAL (operands[5]))
7431 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7433 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7435 (clobber (reg:CC CC_REGNUM))])]
7436 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7437 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7438 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7442 ;;- Xor instructions.
7445 (define_expand "xor<mode>3"
7446 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7447 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7448 (match_operand:INT 2 "general_operand" "")))
7449 (clobber (reg:CC CC_REGNUM))]
7451 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7453 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7454 ; simplifications. So its better to have something matching.
7456 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7457 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7460 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7461 (clobber (reg:CC CC_REGNUM))])]
7463 operands[2] = constm1_rtx;
7464 if (!s390_logical_operator_ok_p (operands))
7469 ; xordi3 instruction pattern(s).
7472 (define_insn "*xordi3_cc"
7473 [(set (reg CC_REGNUM)
7474 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7475 (match_operand:DI 2 "general_operand" " d,d,RT"))
7477 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7478 (xor:DI (match_dup 1) (match_dup 2)))]
7479 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7484 [(set_attr "op_type" "RRE,RRF,RXY")
7485 (set_attr "cpu_facility" "*,z196,*")
7486 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7488 (define_insn "*xordi3_cconly"
7489 [(set (reg CC_REGNUM)
7490 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7491 (match_operand:DI 2 "general_operand" " d,d,RT"))
7493 (clobber (match_scratch:DI 0 "=d,d, d"))]
7494 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7499 [(set_attr "op_type" "RRE,RRF,RXY")
7500 (set_attr "cpu_facility" "*,z196,*")
7501 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7503 (define_insn "*xordi3"
7504 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
7505 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
7506 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7507 (clobber (reg:CC CC_REGNUM))]
7508 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7517 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7518 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7519 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7520 *,z10_super_E1,*,*")])
7523 [(set (match_operand:DI 0 "s_operand" "")
7524 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7525 (clobber (reg:CC CC_REGNUM))]
7528 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7529 (clobber (reg:CC CC_REGNUM))])]
7530 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7533 ; xorsi3 instruction pattern(s).
7536 (define_insn "*xorsi3_cc"
7537 [(set (reg CC_REGNUM)
7538 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7539 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7541 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7542 (xor:SI (match_dup 1) (match_dup 2)))]
7543 "s390_match_ccmode(insn, CCTmode)"
7550 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7551 (set_attr "cpu_facility" "*,*,z196,*,*")
7552 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7553 z10_super_E1,z10_super_E1")])
7555 (define_insn "*xorsi3_cconly"
7556 [(set (reg CC_REGNUM)
7557 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7558 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7560 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7561 "s390_match_ccmode(insn, CCTmode)"
7568 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7569 (set_attr "cpu_facility" "*,*,z196,*,*")
7570 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7571 z10_super_E1,z10_super_E1")])
7573 (define_insn "*xorsi3"
7574 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7575 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7576 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7577 (clobber (reg:CC CC_REGNUM))]
7578 "s390_logical_operator_ok_p (operands)"
7587 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7588 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7589 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7590 z10_super_E1,z10_super_E1,*,*")])
7593 [(set (match_operand:SI 0 "s_operand" "")
7594 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7595 (clobber (reg:CC CC_REGNUM))]
7598 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7599 (clobber (reg:CC CC_REGNUM))])]
7600 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7603 ; xorhi3 instruction pattern(s).
7606 (define_insn "*xorhi3"
7607 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7608 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7609 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7610 (clobber (reg:CC CC_REGNUM))]
7611 "s390_logical_operator_ok_p (operands)"
7618 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7619 (set_attr "cpu_facility" "*,*,z196,*,*")
7620 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7623 [(set (match_operand:HI 0 "s_operand" "")
7624 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7625 (clobber (reg:CC CC_REGNUM))]
7628 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7629 (clobber (reg:CC CC_REGNUM))])]
7630 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7633 ; xorqi3 instruction pattern(s).
7636 (define_insn "*xorqi3"
7637 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7638 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7639 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7640 (clobber (reg:CC CC_REGNUM))]
7641 "s390_logical_operator_ok_p (operands)"
7649 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7650 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7651 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7655 ; Block exclusive or (XC) patterns.
7659 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7660 (xor:BLK (match_dup 0)
7661 (match_operand:BLK 1 "memory_operand" "Q")))
7662 (use (match_operand 2 "const_int_operand" "n"))
7663 (clobber (reg:CC CC_REGNUM))]
7664 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7665 "xc\t%O0(%2,%R0),%S1"
7666 [(set_attr "op_type" "SS")])
7669 [(set (match_operand 0 "memory_operand" "")
7671 (match_operand 1 "memory_operand" "")))
7672 (clobber (reg:CC CC_REGNUM))]
7674 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7675 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7677 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7679 (clobber (reg:CC CC_REGNUM))])]
7681 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7682 operands[0] = adjust_address (operands[0], BLKmode, 0);
7683 operands[1] = adjust_address (operands[1], BLKmode, 0);
7688 [(set (match_operand:BLK 0 "memory_operand" "")
7689 (xor:BLK (match_dup 0)
7690 (match_operand:BLK 1 "memory_operand" "")))
7691 (use (match_operand 2 "const_int_operand" ""))
7692 (clobber (reg:CC CC_REGNUM))])
7694 [(set (match_operand:BLK 3 "memory_operand" "")
7695 (xor:BLK (match_dup 3)
7696 (match_operand:BLK 4 "memory_operand" "")))
7697 (use (match_operand 5 "const_int_operand" ""))
7698 (clobber (reg:CC CC_REGNUM))])]
7699 "s390_offset_p (operands[0], operands[3], operands[2])
7700 && s390_offset_p (operands[1], operands[4], operands[2])
7701 && !s390_overlap_p (operands[0], operands[1],
7702 INTVAL (operands[2]) + INTVAL (operands[5]))
7703 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7705 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7707 (clobber (reg:CC CC_REGNUM))])]
7708 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7709 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7710 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7713 ; Block xor (XC) patterns with src == dest.
7716 (define_insn "*xc_zero"
7717 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7719 (use (match_operand 1 "const_int_operand" "n"))
7720 (clobber (reg:CC CC_REGNUM))]
7721 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7722 "xc\t%O0(%1,%R0),%S0"
7723 [(set_attr "op_type" "SS")
7724 (set_attr "z196prop" "z196_cracked")])
7728 [(set (match_operand:BLK 0 "memory_operand" "")
7730 (use (match_operand 1 "const_int_operand" ""))
7731 (clobber (reg:CC CC_REGNUM))])
7733 [(set (match_operand:BLK 2 "memory_operand" "")
7735 (use (match_operand 3 "const_int_operand" ""))
7736 (clobber (reg:CC CC_REGNUM))])]
7737 "s390_offset_p (operands[0], operands[2], operands[1])
7738 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7740 [(set (match_dup 4) (const_int 0))
7742 (clobber (reg:CC CC_REGNUM))])]
7743 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7744 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7748 ;;- Negate instructions.
7752 ; neg(di|si)2 instruction pattern(s).
7755 (define_expand "neg<mode>2"
7757 [(set (match_operand:DSI 0 "register_operand" "=d")
7758 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7759 (clobber (reg:CC CC_REGNUM))])]
7763 (define_insn "*negdi2_sign_cc"
7764 [(set (reg CC_REGNUM)
7765 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7766 (match_operand:SI 1 "register_operand" "d") 0)
7767 (const_int 32)) (const_int 32)))
7769 (set (match_operand:DI 0 "register_operand" "=d")
7770 (neg:DI (sign_extend:DI (match_dup 1))))]
7771 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7773 [(set_attr "op_type" "RRE")
7774 (set_attr "z10prop" "z10_c")])
7776 (define_insn "*negdi2_sign"
7777 [(set (match_operand:DI 0 "register_operand" "=d")
7778 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7779 (clobber (reg:CC CC_REGNUM))]
7782 [(set_attr "op_type" "RRE")
7783 (set_attr "z10prop" "z10_c")])
7786 (define_insn "*neg<mode>2_cc"
7787 [(set (reg CC_REGNUM)
7788 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7790 (set (match_operand:GPR 0 "register_operand" "=d")
7791 (neg:GPR (match_dup 1)))]
7792 "s390_match_ccmode (insn, CCAmode)"
7794 [(set_attr "op_type" "RR<E>")
7795 (set_attr "z10prop" "z10_super_c_E1")])
7798 (define_insn "*neg<mode>2_cconly"
7799 [(set (reg CC_REGNUM)
7800 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7802 (clobber (match_scratch:GPR 0 "=d"))]
7803 "s390_match_ccmode (insn, CCAmode)"
7805 [(set_attr "op_type" "RR<E>")
7806 (set_attr "z10prop" "z10_super_c_E1")])
7809 (define_insn "*neg<mode>2"
7810 [(set (match_operand:GPR 0 "register_operand" "=d")
7811 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7812 (clobber (reg:CC CC_REGNUM))]
7815 [(set_attr "op_type" "RR<E>")
7816 (set_attr "z10prop" "z10_super_c_E1")])
7818 (define_insn "*negdi2_31"
7819 [(set (match_operand:DI 0 "register_operand" "=d")
7820 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7821 (clobber (reg:CC CC_REGNUM))]
7825 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7827 ; Doing the twos complement separately on the SImode parts does an
7828 ; unwanted +1 on the high part which needs to be subtracted afterwards
7829 ; ... unless the +1 on the low part created an overflow.
7832 [(set (match_operand:DI 0 "register_operand" "")
7833 (neg:DI (match_operand:DI 1 "register_operand" "")))
7834 (clobber (reg:CC CC_REGNUM))]
7836 && (REGNO (operands[0]) == REGNO (operands[1])
7837 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7838 && reload_completed"
7840 [(set (match_dup 2) (neg:SI (match_dup 3)))
7841 (clobber (reg:CC CC_REGNUM))])
7843 [(set (reg:CCAP CC_REGNUM)
7844 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7845 (set (match_dup 4) (neg:SI (match_dup 5)))])
7847 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7849 (label_ref (match_dup 6))))
7851 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7852 (clobber (reg:CC CC_REGNUM))])
7854 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7855 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7856 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7857 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7858 operands[6] = gen_label_rtx ();")
7860 ; Like above but first make a copy of the low part of the src operand
7861 ; since it might overlap with the high part of the destination.
7864 [(set (match_operand:DI 0 "register_operand" "")
7865 (neg:DI (match_operand:DI 1 "register_operand" "")))
7866 (clobber (reg:CC CC_REGNUM))]
7868 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7869 && reload_completed"
7870 [; Make a backup of op5 first
7871 (set (match_dup 4) (match_dup 5))
7872 ; Setting op2 here might clobber op5
7874 [(set (match_dup 2) (neg:SI (match_dup 3)))
7875 (clobber (reg:CC CC_REGNUM))])
7877 [(set (reg:CCAP CC_REGNUM)
7878 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7879 (set (match_dup 4) (neg:SI (match_dup 4)))])
7881 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7883 (label_ref (match_dup 6))))
7885 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7886 (clobber (reg:CC CC_REGNUM))])
7888 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7889 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7890 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7891 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7892 operands[6] = gen_label_rtx ();")
7895 ; neg(df|sf)2 instruction pattern(s).
7898 (define_expand "neg<mode>2"
7900 [(set (match_operand:BFP 0 "register_operand" "=f")
7901 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7902 (clobber (reg:CC CC_REGNUM))])]
7906 ; lcxbr, lcdbr, lcebr
7907 (define_insn "*neg<mode>2_cc"
7908 [(set (reg CC_REGNUM)
7909 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7910 (match_operand:BFP 2 "const0_operand" "")))
7911 (set (match_operand:BFP 0 "register_operand" "=f")
7912 (neg:BFP (match_dup 1)))]
7913 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7915 [(set_attr "op_type" "RRE")
7916 (set_attr "type" "fsimp<mode>")])
7918 ; lcxbr, lcdbr, lcebr
7919 (define_insn "*neg<mode>2_cconly"
7920 [(set (reg CC_REGNUM)
7921 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7922 (match_operand:BFP 2 "const0_operand" "")))
7923 (clobber (match_scratch:BFP 0 "=f"))]
7924 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7926 [(set_attr "op_type" "RRE")
7927 (set_attr "type" "fsimp<mode>")])
7930 (define_insn "*neg<mode>2_nocc"
7931 [(set (match_operand:FP 0 "register_operand" "=f")
7932 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7935 [(set_attr "op_type" "RRE")
7936 (set_attr "type" "fsimp<mode>")])
7938 ; lcxbr, lcdbr, lcebr
7939 ; FIXME: wflcdb does not clobber cc
7940 (define_insn "*neg<mode>2"
7941 [(set (match_operand:BFP 0 "register_operand" "=f,<vf>")
7942 (neg:BFP (match_operand:BFP 1 "register_operand" "f,<vf>")))
7943 (clobber (reg:CC CC_REGNUM))]
7948 [(set_attr "op_type" "RRE,VRR")
7949 (set_attr "cpu_facility" "*,vec")
7950 (set_attr "type" "fsimp<mode>,*")])
7954 ;;- Absolute value instructions.
7958 ; abs(di|si)2 instruction pattern(s).
7961 (define_insn "*absdi2_sign_cc"
7962 [(set (reg CC_REGNUM)
7963 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7964 (match_operand:SI 1 "register_operand" "d") 0)
7965 (const_int 32)) (const_int 32)))
7967 (set (match_operand:DI 0 "register_operand" "=d")
7968 (abs:DI (sign_extend:DI (match_dup 1))))]
7969 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7971 [(set_attr "op_type" "RRE")
7972 (set_attr "z10prop" "z10_c")])
7974 (define_insn "*absdi2_sign"
7975 [(set (match_operand:DI 0 "register_operand" "=d")
7976 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7977 (clobber (reg:CC CC_REGNUM))]
7980 [(set_attr "op_type" "RRE")
7981 (set_attr "z10prop" "z10_c")])
7984 (define_insn "*abs<mode>2_cc"
7985 [(set (reg CC_REGNUM)
7986 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7988 (set (match_operand:GPR 0 "register_operand" "=d")
7989 (abs:GPR (match_dup 1)))]
7990 "s390_match_ccmode (insn, CCAmode)"
7992 [(set_attr "op_type" "RR<E>")
7993 (set_attr "z10prop" "z10_c")])
7996 (define_insn "*abs<mode>2_cconly"
7997 [(set (reg CC_REGNUM)
7998 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8000 (clobber (match_scratch:GPR 0 "=d"))]
8001 "s390_match_ccmode (insn, CCAmode)"
8003 [(set_attr "op_type" "RR<E>")
8004 (set_attr "z10prop" "z10_c")])
8007 (define_insn "abs<mode>2"
8008 [(set (match_operand:GPR 0 "register_operand" "=d")
8009 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8010 (clobber (reg:CC CC_REGNUM))]
8013 [(set_attr "op_type" "RR<E>")
8014 (set_attr "z10prop" "z10_c")])
8017 ; abs(df|sf)2 instruction pattern(s).
8020 (define_expand "abs<mode>2"
8022 [(set (match_operand:BFP 0 "register_operand" "=f")
8023 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8024 (clobber (reg:CC CC_REGNUM))])]
8028 ; lpxbr, lpdbr, lpebr
8029 (define_insn "*abs<mode>2_cc"
8030 [(set (reg CC_REGNUM)
8031 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8032 (match_operand:BFP 2 "const0_operand" "")))
8033 (set (match_operand:BFP 0 "register_operand" "=f")
8034 (abs:BFP (match_dup 1)))]
8035 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8037 [(set_attr "op_type" "RRE")
8038 (set_attr "type" "fsimp<mode>")])
8040 ; lpxbr, lpdbr, lpebr
8041 (define_insn "*abs<mode>2_cconly"
8042 [(set (reg CC_REGNUM)
8043 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8044 (match_operand:BFP 2 "const0_operand" "")))
8045 (clobber (match_scratch:BFP 0 "=f"))]
8046 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8048 [(set_attr "op_type" "RRE")
8049 (set_attr "type" "fsimp<mode>")])
8052 (define_insn "*abs<mode>2_nocc"
8053 [(set (match_operand:FP 0 "register_operand" "=f")
8054 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8057 [(set_attr "op_type" "RRE")
8058 (set_attr "type" "fsimp<mode>")])
8060 ; lpxbr, lpdbr, lpebr
8061 ; FIXME: wflpdb does not clobber cc
8062 (define_insn "*abs<mode>2"
8063 [(set (match_operand:BFP 0 "register_operand" "=f,<vf>")
8064 (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>")))
8065 (clobber (reg:CC CC_REGNUM))]
8070 [(set_attr "op_type" "RRE,VRR")
8071 (set_attr "cpu_facility" "*,vec")
8072 (set_attr "type" "fsimp<mode>,*")])
8076 ;;- Negated absolute value instructions
8083 (define_insn "*negabsdi2_sign_cc"
8084 [(set (reg CC_REGNUM)
8085 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8086 (match_operand:SI 1 "register_operand" "d") 0)
8087 (const_int 32)) (const_int 32))))
8089 (set (match_operand:DI 0 "register_operand" "=d")
8090 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8091 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8093 [(set_attr "op_type" "RRE")
8094 (set_attr "z10prop" "z10_c")])
8096 (define_insn "*negabsdi2_sign"
8097 [(set (match_operand:DI 0 "register_operand" "=d")
8098 (neg:DI (abs:DI (sign_extend:DI
8099 (match_operand:SI 1 "register_operand" "d")))))
8100 (clobber (reg:CC CC_REGNUM))]
8103 [(set_attr "op_type" "RRE")
8104 (set_attr "z10prop" "z10_c")])
8107 (define_insn "*negabs<mode>2_cc"
8108 [(set (reg CC_REGNUM)
8109 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8111 (set (match_operand:GPR 0 "register_operand" "=d")
8112 (neg:GPR (abs:GPR (match_dup 1))))]
8113 "s390_match_ccmode (insn, CCAmode)"
8115 [(set_attr "op_type" "RR<E>")
8116 (set_attr "z10prop" "z10_c")])
8119 (define_insn "*negabs<mode>2_cconly"
8120 [(set (reg CC_REGNUM)
8121 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8123 (clobber (match_scratch:GPR 0 "=d"))]
8124 "s390_match_ccmode (insn, CCAmode)"
8126 [(set_attr "op_type" "RR<E>")
8127 (set_attr "z10prop" "z10_c")])
8130 (define_insn "*negabs<mode>2"
8131 [(set (match_operand:GPR 0 "register_operand" "=d")
8132 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8133 (clobber (reg:CC CC_REGNUM))]
8136 [(set_attr "op_type" "RR<E>")
8137 (set_attr "z10prop" "z10_c")])
8143 ; lnxbr, lndbr, lnebr
8144 (define_insn "*negabs<mode>2_cc"
8145 [(set (reg CC_REGNUM)
8146 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8147 (match_operand:BFP 2 "const0_operand" "")))
8148 (set (match_operand:BFP 0 "register_operand" "=f")
8149 (neg:BFP (abs:BFP (match_dup 1))))]
8150 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8152 [(set_attr "op_type" "RRE")
8153 (set_attr "type" "fsimp<mode>")])
8155 ; lnxbr, lndbr, lnebr
8156 (define_insn "*negabs<mode>2_cconly"
8157 [(set (reg CC_REGNUM)
8158 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8159 (match_operand:BFP 2 "const0_operand" "")))
8160 (clobber (match_scratch:BFP 0 "=f"))]
8161 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8163 [(set_attr "op_type" "RRE")
8164 (set_attr "type" "fsimp<mode>")])
8167 (define_insn "*negabs<mode>2_nocc"
8168 [(set (match_operand:FP 0 "register_operand" "=f")
8169 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8172 [(set_attr "op_type" "RRE")
8173 (set_attr "type" "fsimp<mode>")])
8175 ; lnxbr, lndbr, lnebr
8176 ; FIXME: wflndb does not clobber cc
8177 (define_insn "*negabs<mode>2"
8178 [(set (match_operand:BFP 0 "register_operand" "=f,<vf>")
8179 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>"))))
8180 (clobber (reg:CC CC_REGNUM))]
8185 [(set_attr "op_type" "RRE,VRR")
8186 (set_attr "cpu_facility" "*,vec")
8187 (set_attr "type" "fsimp<mode>,*")])
8190 ;;- Square root instructions.
8194 ; sqrt(df|sf)2 instruction pattern(s).
8197 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8198 (define_insn "sqrt<mode>2"
8199 [(set (match_operand:BFP 0 "register_operand" "=f, f,<vf>")
8200 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>,<vf>")))]
8206 [(set_attr "op_type" "RRE,RXE,VRR")
8207 (set_attr "type" "fsqrt<mode>")
8208 (set_attr "cpu_facility" "*,*,vec")])
8212 ;;- One complement instructions.
8216 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8219 (define_expand "one_cmpl<mode>2"
8221 [(set (match_operand:INT 0 "register_operand" "")
8222 (xor:INT (match_operand:INT 1 "register_operand" "")
8224 (clobber (reg:CC CC_REGNUM))])]
8230 ;; Find leftmost bit instructions.
8233 (define_expand "clzdi2"
8234 [(set (match_operand:DI 0 "register_operand" "=d")
8235 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8236 "TARGET_EXTIMM && TARGET_ZARCH"
8238 rtx insn, clz_equal;
8239 rtx wide_reg = gen_reg_rtx (TImode);
8240 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8242 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8244 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8246 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8247 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8252 (define_insn "clztidi2"
8253 [(set (match_operand:TI 0 "register_operand" "=d")
8257 (xor:DI (match_operand:DI 1 "register_operand" "d")
8258 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8259 (subreg:SI (clz:DI (match_dup 1)) 4))))
8262 (zero_extend:TI (clz:DI (match_dup 1)))))
8263 (clobber (reg:CC CC_REGNUM))]
8264 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8265 == (unsigned HOST_WIDE_INT) 1 << 63
8266 && TARGET_EXTIMM && TARGET_ZARCH"
8268 [(set_attr "op_type" "RRE")])
8272 ;;- Rotate instructions.
8276 ; rotl(di|si)3 instruction pattern(s).
8280 (define_insn "rotl<mode>3"
8281 [(set (match_operand:GPR 0 "register_operand" "=d")
8282 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8283 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8286 [(set_attr "op_type" "RSE")
8287 (set_attr "atype" "reg")
8288 (set_attr "z10prop" "z10_super_E1")])
8291 (define_insn "*rotl<mode>3_and"
8292 [(set (match_operand:GPR 0 "register_operand" "=d")
8293 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8294 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8295 (match_operand:SI 3 "const_int_operand" "n"))))]
8296 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8298 [(set_attr "op_type" "RSE")
8299 (set_attr "atype" "reg")
8300 (set_attr "z10prop" "z10_super_E1")])
8304 ;;- Shift instructions.
8308 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8309 ; Left shifts and logical right shifts
8311 (define_expand "<shift><mode>3"
8312 [(set (match_operand:DSI 0 "register_operand" "")
8313 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8314 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
8319 (define_insn "*<shift>di3_31"
8320 [(set (match_operand:DI 0 "register_operand" "=d")
8321 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8322 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8325 [(set_attr "op_type" "RS")
8326 (set_attr "atype" "reg")
8327 (set_attr "z196prop" "z196_cracked")])
8329 ; sll, srl, sllg, srlg, sllk, srlk
8330 (define_insn "*<shift><mode>3"
8331 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8332 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8333 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
8336 s<lr>l<g>\t%0,<1>%Y2
8337 s<lr>l<gk>\t%0,%1,%Y2"
8338 [(set_attr "op_type" "RS<E>,RSY")
8339 (set_attr "atype" "reg,reg")
8340 (set_attr "cpu_facility" "*,z196")
8341 (set_attr "z10prop" "z10_super_E1,*")])
8344 (define_insn "*<shift>di3_31_and"
8345 [(set (match_operand:DI 0 "register_operand" "=d")
8346 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8347 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8348 (match_operand:SI 3 "const_int_operand" "n"))))]
8349 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8351 [(set_attr "op_type" "RS")
8352 (set_attr "atype" "reg")])
8354 ; sll, srl, sllg, srlg, sllk, srlk
8355 (define_insn "*<shift><mode>3_and"
8356 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8357 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8358 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8359 (match_operand:SI 3 "const_int_operand" "n,n"))))]
8360 "(INTVAL (operands[3]) & 63) == 63"
8362 s<lr>l<g>\t%0,<1>%Y2
8363 s<lr>l<gk>\t%0,%1,%Y2"
8364 [(set_attr "op_type" "RS<E>,RSY")
8365 (set_attr "atype" "reg,reg")
8366 (set_attr "cpu_facility" "*,z196")
8367 (set_attr "z10prop" "z10_super_E1,*")])
8370 ; ashr(di|si)3 instruction pattern(s).
8371 ; Arithmetic right shifts
8373 (define_expand "ashr<mode>3"
8375 [(set (match_operand:DSI 0 "register_operand" "")
8376 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8377 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
8378 (clobber (reg:CC CC_REGNUM))])]
8382 (define_insn "*ashrdi3_cc_31"
8383 [(set (reg CC_REGNUM)
8384 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8385 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8387 (set (match_operand:DI 0 "register_operand" "=d")
8388 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8389 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8391 [(set_attr "op_type" "RS")
8392 (set_attr "atype" "reg")])
8394 (define_insn "*ashrdi3_cconly_31"
8395 [(set (reg CC_REGNUM)
8396 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8397 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8399 (clobber (match_scratch:DI 0 "=d"))]
8400 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8402 [(set_attr "op_type" "RS")
8403 (set_attr "atype" "reg")])
8405 (define_insn "*ashrdi3_31"
8406 [(set (match_operand:DI 0 "register_operand" "=d")
8407 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8408 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
8409 (clobber (reg:CC CC_REGNUM))]
8412 [(set_attr "op_type" "RS")
8413 (set_attr "atype" "reg")])
8416 (define_insn "*ashr<mode>3_cc"
8417 [(set (reg CC_REGNUM)
8418 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8419 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8421 (set (match_operand:GPR 0 "register_operand" "=d,d")
8422 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
8423 "s390_match_ccmode(insn, CCSmode)"
8427 [(set_attr "op_type" "RS<E>,RSY")
8428 (set_attr "atype" "reg,reg")
8429 (set_attr "cpu_facility" "*,z196")
8430 (set_attr "z10prop" "z10_super_E1,*")])
8433 (define_insn "*ashr<mode>3_cconly"
8434 [(set (reg CC_REGNUM)
8435 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8436 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8438 (clobber (match_scratch:GPR 0 "=d,d"))]
8439 "s390_match_ccmode(insn, CCSmode)"
8443 [(set_attr "op_type" "RS<E>,RSY")
8444 (set_attr "atype" "reg,reg")
8445 (set_attr "cpu_facility" "*,z196")
8446 (set_attr "z10prop" "z10_super_E1,*")])
8449 (define_insn "*ashr<mode>3"
8450 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8451 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8452 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8453 (clobber (reg:CC CC_REGNUM))]
8458 [(set_attr "op_type" "RS<E>,RSY")
8459 (set_attr "atype" "reg,reg")
8460 (set_attr "cpu_facility" "*,z196")
8461 (set_attr "z10prop" "z10_super_E1,*")])
8464 ; shift pattern with implicit ANDs
8466 (define_insn "*ashrdi3_cc_31_and"
8467 [(set (reg CC_REGNUM)
8468 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8469 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8470 (match_operand:SI 3 "const_int_operand" "n")))
8472 (set (match_operand:DI 0 "register_operand" "=d")
8473 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8474 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8475 && (INTVAL (operands[3]) & 63) == 63"
8477 [(set_attr "op_type" "RS")
8478 (set_attr "atype" "reg")])
8480 (define_insn "*ashrdi3_cconly_31_and"
8481 [(set (reg CC_REGNUM)
8482 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8483 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8484 (match_operand:SI 3 "const_int_operand" "n")))
8486 (clobber (match_scratch:DI 0 "=d"))]
8487 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8488 && (INTVAL (operands[3]) & 63) == 63"
8490 [(set_attr "op_type" "RS")
8491 (set_attr "atype" "reg")])
8493 (define_insn "*ashrdi3_31_and"
8494 [(set (match_operand:DI 0 "register_operand" "=d")
8495 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8496 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8497 (match_operand:SI 3 "const_int_operand" "n"))))
8498 (clobber (reg:CC CC_REGNUM))]
8499 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8501 [(set_attr "op_type" "RS")
8502 (set_attr "atype" "reg")])
8505 (define_insn "*ashr<mode>3_cc_and"
8506 [(set (reg CC_REGNUM)
8507 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8508 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8509 (match_operand:SI 3 "const_int_operand" "n,n")))
8511 (set (match_operand:GPR 0 "register_operand" "=d,d")
8512 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8513 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8517 [(set_attr "op_type" "RS<E>,RSY")
8518 (set_attr "atype" "reg,reg")
8519 (set_attr "cpu_facility" "*,z196")
8520 (set_attr "z10prop" "z10_super_E1,*")])
8523 (define_insn "*ashr<mode>3_cconly_and"
8524 [(set (reg CC_REGNUM)
8525 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8526 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8527 (match_operand:SI 3 "const_int_operand" "n,n")))
8529 (clobber (match_scratch:GPR 0 "=d,d"))]
8530 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8534 [(set_attr "op_type" "RS<E>,RSY")
8535 (set_attr "atype" "reg,reg")
8536 (set_attr "cpu_facility" "*,z196")
8537 (set_attr "z10prop" "z10_super_E1,*")])
8540 (define_insn "*ashr<mode>3_and"
8541 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8542 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8543 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8544 (match_operand:SI 3 "const_int_operand" "n,n"))))
8545 (clobber (reg:CC CC_REGNUM))]
8546 "(INTVAL (operands[3]) & 63) == 63"
8550 [(set_attr "op_type" "RS<E>,RSY")
8551 (set_attr "atype" "reg,reg")
8552 (set_attr "cpu_facility" "*,z196")
8553 (set_attr "z10prop" "z10_super_E1,*")])
8557 ;; Branch instruction patterns.
8560 (define_expand "cbranch<mode>4"
8562 (if_then_else (match_operator 0 "comparison_operator"
8563 [(match_operand:GPR 1 "register_operand" "")
8564 (match_operand:GPR 2 "general_operand" "")])
8565 (label_ref (match_operand 3 "" ""))
8568 "s390_emit_jump (operands[3],
8569 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8572 (define_expand "cbranch<mode>4"
8574 (if_then_else (match_operator 0 "comparison_operator"
8575 [(match_operand:FP 1 "register_operand" "")
8576 (match_operand:FP 2 "general_operand" "")])
8577 (label_ref (match_operand 3 "" ""))
8580 "s390_emit_jump (operands[3],
8581 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8584 (define_expand "cbranchcc4"
8586 (if_then_else (match_operator 0 "s390_comparison"
8587 [(match_operand 1 "cc_reg_operand" "")
8588 (match_operand 2 "const_int_operand" "")])
8589 (label_ref (match_operand 3 "" ""))
8596 ;;- Conditional jump instructions.
8599 (define_insn "*cjump_64"
8602 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8603 (match_operand 2 "const_int_operand" "")])
8604 (label_ref (match_operand 0 "" ""))
8608 if (get_attr_length (insn) == 4)
8611 return "jg%C1\t%l0";
8613 [(set_attr "op_type" "RI")
8614 (set_attr "type" "branch")
8615 (set (attr "length")
8616 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8617 (const_int 4) (const_int 6)))])
8619 (define_insn "*cjump_31"
8622 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8623 (match_operand 2 "const_int_operand" "")])
8624 (label_ref (match_operand 0 "" ""))
8628 gcc_assert (get_attr_length (insn) == 4);
8631 [(set_attr "op_type" "RI")
8632 (set_attr "type" "branch")
8633 (set (attr "length")
8634 (if_then_else (not (match_test "flag_pic"))
8635 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8636 (const_int 4) (const_int 6))
8637 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8638 (const_int 4) (const_int 8))))])
8640 (define_insn "*cjump_long"
8643 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8644 (match_operand 0 "address_operand" "ZQZR")
8648 if (get_attr_op_type (insn) == OP_TYPE_RR)
8653 [(set (attr "op_type")
8654 (if_then_else (match_operand 0 "register_operand" "")
8655 (const_string "RR") (const_string "RX")))
8656 (set_attr "type" "branch")
8657 (set_attr "atype" "agen")])
8659 ;; A conditional return instruction.
8660 (define_insn "*c<code>"
8663 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8666 "s390_can_use_<code>_insn ()"
8668 [(set_attr "op_type" "RR")
8669 (set_attr "type" "jsr")
8670 (set_attr "atype" "agen")])
8673 ;;- Negated conditional jump instructions.
8676 (define_insn "*icjump_64"
8679 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8681 (label_ref (match_operand 0 "" ""))))]
8684 if (get_attr_length (insn) == 4)
8687 return "jg%D1\t%l0";
8689 [(set_attr "op_type" "RI")
8690 (set_attr "type" "branch")
8691 (set (attr "length")
8692 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8693 (const_int 4) (const_int 6)))])
8695 (define_insn "*icjump_31"
8698 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8700 (label_ref (match_operand 0 "" ""))))]
8703 gcc_assert (get_attr_length (insn) == 4);
8706 [(set_attr "op_type" "RI")
8707 (set_attr "type" "branch")
8708 (set (attr "length")
8709 (if_then_else (not (match_test "flag_pic"))
8710 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8711 (const_int 4) (const_int 6))
8712 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8713 (const_int 4) (const_int 8))))])
8715 (define_insn "*icjump_long"
8718 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8720 (match_operand 0 "address_operand" "ZQZR")))]
8723 if (get_attr_op_type (insn) == OP_TYPE_RR)
8728 [(set (attr "op_type")
8729 (if_then_else (match_operand 0 "register_operand" "")
8730 (const_string "RR") (const_string "RX")))
8731 (set_attr "type" "branch")
8732 (set_attr "atype" "agen")])
8735 ;;- Trap instructions.
8739 [(trap_if (const_int 1) (const_int 0))]
8742 [(set_attr "op_type" "RI")
8743 (set_attr "type" "branch")])
8745 (define_expand "ctrap<mode>4"
8746 [(trap_if (match_operator 0 "comparison_operator"
8747 [(match_operand:GPR 1 "register_operand" "")
8748 (match_operand:GPR 2 "general_operand" "")])
8749 (match_operand 3 "const0_operand" ""))]
8752 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8753 operands[1], operands[2]);
8754 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8758 (define_expand "ctrap<mode>4"
8759 [(trap_if (match_operator 0 "comparison_operator"
8760 [(match_operand:FP 1 "register_operand" "")
8761 (match_operand:FP 2 "general_operand" "")])
8762 (match_operand 3 "const0_operand" ""))]
8765 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8766 operands[1], operands[2]);
8767 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8771 (define_insn "condtrap"
8772 [(trap_if (match_operator 0 "s390_comparison"
8773 [(match_operand 1 "cc_reg_operand" "c")
8778 [(set_attr "op_type" "RI")
8779 (set_attr "type" "branch")])
8781 ; crt, cgrt, cit, cgit
8782 (define_insn "*cmp_and_trap_signed_int<mode>"
8783 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8784 [(match_operand:GPR 1 "register_operand" "d,d")
8785 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8791 [(set_attr "op_type" "RRF,RIE")
8792 (set_attr "type" "branch")
8793 (set_attr "z10prop" "z10_super_c,z10_super")])
8795 ; clrt, clgrt, clfit, clgit, clt, clgt
8796 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8797 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8798 [(match_operand:GPR 1 "register_operand" "d,d, d")
8799 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8806 [(set_attr "op_type" "RRF,RIE,RSY")
8807 (set_attr "type" "branch")
8808 (set_attr "z10prop" "z10_super_c,z10_super,*")
8809 (set_attr "cpu_facility" "z10,z10,zEC12")])
8812 (define_insn "*load_and_trap<mode>"
8813 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8816 (set (match_operand:GPR 1 "register_operand" "=d")
8820 [(set_attr "op_type" "RXY")])
8824 ;;- Loop instructions.
8826 ;; This is all complicated by the fact that since this is a jump insn
8827 ;; we must handle our own output reloads.
8831 ; This splitter will be matched by combine and has to add the 2 moves
8832 ; necessary to load the compare and the increment values into a
8833 ; register pair as needed by brxle.
8835 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8838 (match_operator 6 "s390_brx_operator"
8839 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8840 (match_operand:GPR 2 "general_operand" ""))
8841 (match_operand:GPR 3 "register_operand" "")])
8842 (label_ref (match_operand 0 "" ""))
8844 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8845 (plus:GPR (match_dup 1) (match_dup 2)))
8846 (clobber (match_scratch:GPR 5 ""))]
8849 "!reload_completed && !reload_in_progress"
8850 [(set (match_dup 7) (match_dup 2)) ; the increment
8851 (set (match_dup 8) (match_dup 3)) ; the comparison value
8852 (parallel [(set (pc)
8855 [(plus:GPR (match_dup 1) (match_dup 7))
8857 (label_ref (match_dup 0))
8860 (plus:GPR (match_dup 1) (match_dup 7)))
8861 (clobber (match_dup 5))
8862 (clobber (reg:CC CC_REGNUM))])]
8864 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8865 operands[7] = gen_lowpart (<GPR:MODE>mode,
8866 gen_highpart (word_mode, dreg));
8867 operands[8] = gen_lowpart (<GPR:MODE>mode,
8868 gen_lowpart (word_mode, dreg));
8873 (define_insn_and_split "*brxg_64bit"
8876 (match_operator 5 "s390_brx_operator"
8877 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8878 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8879 (subreg:DI (match_dup 2) 8)])
8880 (label_ref (match_operand 0 "" ""))
8882 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8883 (plus:DI (match_dup 1)
8884 (subreg:DI (match_dup 2) 0)))
8885 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8886 (clobber (reg:CC CC_REGNUM))]
8889 if (which_alternative != 0)
8891 else if (get_attr_length (insn) == 6)
8892 return "brx%E5g\t%1,%2,%l0";
8894 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8896 "&& reload_completed
8897 && (!REG_P (operands[3])
8898 || !rtx_equal_p (operands[1], operands[3]))"
8899 [(set (match_dup 4) (match_dup 1))
8900 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8901 (clobber (reg:CC CC_REGNUM))])
8902 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8903 (set (match_dup 3) (match_dup 4))
8904 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8905 (label_ref (match_dup 0))
8908 [(set_attr "op_type" "RIE")
8909 (set_attr "type" "branch")
8910 (set (attr "length")
8911 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8912 (const_int 6) (const_int 16)))])
8916 (define_insn_and_split "*brx_64bit"
8919 (match_operator 5 "s390_brx_operator"
8920 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8921 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8922 (subreg:SI (match_dup 2) 12)])
8923 (label_ref (match_operand 0 "" ""))
8925 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8926 (plus:SI (match_dup 1)
8927 (subreg:SI (match_dup 2) 4)))
8928 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8929 (clobber (reg:CC CC_REGNUM))]
8932 if (which_alternative != 0)
8934 else if (get_attr_length (insn) == 6)
8935 return "brx%C5\t%1,%2,%l0";
8937 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8939 "&& reload_completed
8940 && (!REG_P (operands[3])
8941 || !rtx_equal_p (operands[1], operands[3]))"
8942 [(set (match_dup 4) (match_dup 1))
8943 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8944 (clobber (reg:CC CC_REGNUM))])
8945 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8946 (set (match_dup 3) (match_dup 4))
8947 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8948 (label_ref (match_dup 0))
8951 [(set_attr "op_type" "RSI")
8952 (set_attr "type" "branch")
8953 (set (attr "length")
8954 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8955 (const_int 6) (const_int 14)))])
8959 (define_insn_and_split "*brx_31bit"
8962 (match_operator 5 "s390_brx_operator"
8963 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8964 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8965 (subreg:SI (match_dup 2) 4)])
8966 (label_ref (match_operand 0 "" ""))
8968 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8969 (plus:SI (match_dup 1)
8970 (subreg:SI (match_dup 2) 0)))
8971 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8972 (clobber (reg:CC CC_REGNUM))]
8973 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8975 if (which_alternative != 0)
8977 else if (get_attr_length (insn) == 6)
8978 return "brx%C5\t%1,%2,%l0";
8980 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8982 "&& reload_completed
8983 && (!REG_P (operands[3])
8984 || !rtx_equal_p (operands[1], operands[3]))"
8985 [(set (match_dup 4) (match_dup 1))
8986 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8987 (clobber (reg:CC CC_REGNUM))])
8988 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8989 (set (match_dup 3) (match_dup 4))
8990 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8991 (label_ref (match_dup 0))
8994 [(set_attr "op_type" "RSI")
8995 (set_attr "type" "branch")
8996 (set (attr "length")
8997 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8998 (const_int 6) (const_int 14)))])
9003 (define_expand "doloop_end"
9004 [(use (match_operand 0 "" "")) ; loop pseudo
9005 (use (match_operand 1 "" ""))] ; label
9008 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9009 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9010 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9011 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9012 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9013 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9020 (define_insn_and_split "doloop_si64"
9023 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9025 (label_ref (match_operand 0 "" ""))
9027 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9028 (plus:SI (match_dup 1) (const_int -1)))
9029 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9030 (clobber (reg:CC CC_REGNUM))]
9033 if (which_alternative != 0)
9035 else if (get_attr_length (insn) == 4)
9036 return "brct\t%1,%l0";
9038 return "ahi\t%1,-1\;jgne\t%l0";
9040 "&& reload_completed
9041 && (! REG_P (operands[2])
9042 || ! rtx_equal_p (operands[1], operands[2]))"
9043 [(set (match_dup 3) (match_dup 1))
9044 (parallel [(set (reg:CCAN CC_REGNUM)
9045 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9047 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9048 (set (match_dup 2) (match_dup 3))
9049 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9050 (label_ref (match_dup 0))
9053 [(set_attr "op_type" "RI")
9054 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9055 ; hurt us in the (rare) case of ahi.
9056 (set_attr "z10prop" "z10_super_E1")
9057 (set_attr "type" "branch")
9058 (set (attr "length")
9059 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9060 (const_int 4) (const_int 10)))])
9062 (define_insn_and_split "doloop_si31"
9065 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9067 (label_ref (match_operand 0 "" ""))
9069 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9070 (plus:SI (match_dup 1) (const_int -1)))
9071 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9072 (clobber (reg:CC CC_REGNUM))]
9075 if (which_alternative != 0)
9077 else if (get_attr_length (insn) == 4)
9078 return "brct\t%1,%l0";
9082 "&& reload_completed
9083 && (! REG_P (operands[2])
9084 || ! rtx_equal_p (operands[1], operands[2]))"
9085 [(set (match_dup 3) (match_dup 1))
9086 (parallel [(set (reg:CCAN CC_REGNUM)
9087 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9089 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9090 (set (match_dup 2) (match_dup 3))
9091 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9092 (label_ref (match_dup 0))
9095 [(set_attr "op_type" "RI")
9096 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9097 ; hurt us in the (rare) case of ahi.
9098 (set_attr "z10prop" "z10_super_E1")
9099 (set_attr "type" "branch")
9100 (set (attr "length")
9101 (if_then_else (not (match_test "flag_pic"))
9102 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9103 (const_int 4) (const_int 6))
9104 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9105 (const_int 4) (const_int 8))))])
9107 (define_insn "*doloop_si_long"
9110 (ne (match_operand:SI 1 "register_operand" "d")
9112 (match_operand 0 "address_operand" "ZQZR")
9114 (set (match_operand:SI 2 "register_operand" "=1")
9115 (plus:SI (match_dup 1) (const_int -1)))
9116 (clobber (match_scratch:SI 3 "=X"))
9117 (clobber (reg:CC CC_REGNUM))]
9120 if (get_attr_op_type (insn) == OP_TYPE_RR)
9121 return "bctr\t%1,%0";
9123 return "bct\t%1,%a0";
9125 [(set (attr "op_type")
9126 (if_then_else (match_operand 0 "register_operand" "")
9127 (const_string "RR") (const_string "RX")))
9128 (set_attr "type" "branch")
9129 (set_attr "atype" "agen")
9130 (set_attr "z10prop" "z10_c")
9131 (set_attr "z196prop" "z196_cracked")])
9133 (define_insn_and_split "doloop_di"
9136 (ne (match_operand:DI 1 "register_operand" "d,d,d")
9138 (label_ref (match_operand 0 "" ""))
9140 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9141 (plus:DI (match_dup 1) (const_int -1)))
9142 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9143 (clobber (reg:CC CC_REGNUM))]
9146 if (which_alternative != 0)
9148 else if (get_attr_length (insn) == 4)
9149 return "brctg\t%1,%l0";
9151 return "aghi\t%1,-1\;jgne\t%l0";
9153 "&& reload_completed
9154 && (! REG_P (operands[2])
9155 || ! rtx_equal_p (operands[1], operands[2]))"
9156 [(set (match_dup 3) (match_dup 1))
9157 (parallel [(set (reg:CCAN CC_REGNUM)
9158 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9160 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9161 (set (match_dup 2) (match_dup 3))
9162 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9163 (label_ref (match_dup 0))
9166 [(set_attr "op_type" "RI")
9167 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9168 ; hurt us in the (rare) case of ahi.
9169 (set_attr "z10prop" "z10_super_E1")
9170 (set_attr "type" "branch")
9171 (set (attr "length")
9172 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9173 (const_int 4) (const_int 10)))])
9176 ;;- Unconditional jump instructions.
9180 ; jump instruction pattern(s).
9183 (define_expand "jump"
9184 [(match_operand 0 "" "")]
9186 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9188 (define_insn "*jump64"
9189 [(set (pc) (label_ref (match_operand 0 "" "")))]
9192 if (get_attr_length (insn) == 4)
9197 [(set_attr "op_type" "RI")
9198 (set_attr "type" "branch")
9199 (set (attr "length")
9200 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9201 (const_int 4) (const_int 6)))])
9203 (define_insn "*jump31"
9204 [(set (pc) (label_ref (match_operand 0 "" "")))]
9207 gcc_assert (get_attr_length (insn) == 4);
9210 [(set_attr "op_type" "RI")
9211 (set_attr "type" "branch")
9212 (set (attr "length")
9213 (if_then_else (not (match_test "flag_pic"))
9214 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9215 (const_int 4) (const_int 6))
9216 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9217 (const_int 4) (const_int 8))))])
9220 ; indirect-jump instruction pattern(s).
9223 (define_insn "indirect_jump"
9224 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
9227 if (get_attr_op_type (insn) == OP_TYPE_RR)
9232 [(set (attr "op_type")
9233 (if_then_else (match_operand 0 "register_operand" "")
9234 (const_string "RR") (const_string "RX")))
9235 (set_attr "type" "branch")
9236 (set_attr "atype" "agen")])
9239 ; casesi instruction pattern(s).
9242 (define_insn "casesi_jump"
9243 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
9244 (use (label_ref (match_operand 1 "" "")))]
9247 if (get_attr_op_type (insn) == OP_TYPE_RR)
9252 [(set (attr "op_type")
9253 (if_then_else (match_operand 0 "register_operand" "")
9254 (const_string "RR") (const_string "RX")))
9255 (set_attr "type" "branch")
9256 (set_attr "atype" "agen")])
9258 (define_expand "casesi"
9259 [(match_operand:SI 0 "general_operand" "")
9260 (match_operand:SI 1 "general_operand" "")
9261 (match_operand:SI 2 "general_operand" "")
9262 (label_ref (match_operand 3 "" ""))
9263 (label_ref (match_operand 4 "" ""))]
9266 rtx index = gen_reg_rtx (SImode);
9267 rtx base = gen_reg_rtx (Pmode);
9268 rtx target = gen_reg_rtx (Pmode);
9270 emit_move_insn (index, operands[0]);
9271 emit_insn (gen_subsi3 (index, index, operands[1]));
9272 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9275 if (Pmode != SImode)
9276 index = convert_to_mode (Pmode, index, 1);
9277 if (GET_CODE (index) != REG)
9278 index = copy_to_mode_reg (Pmode, index);
9281 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9283 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9285 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9287 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9288 emit_move_insn (target, index);
9291 target = gen_rtx_PLUS (Pmode, base, target);
9292 emit_jump_insn (gen_casesi_jump (target, operands[3]));
9299 ;;- Jump to subroutine.
9304 ; untyped call instruction pattern(s).
9307 ;; Call subroutine returning any type.
9308 (define_expand "untyped_call"
9309 [(parallel [(call (match_operand 0 "" "")
9311 (match_operand 1 "" "")
9312 (match_operand 2 "" "")])]
9317 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9319 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9321 rtx set = XVECEXP (operands[2], 0, i);
9322 emit_move_insn (SET_DEST (set), SET_SRC (set));
9325 /* The optimizer does not know that the call sets the function value
9326 registers we stored in the result block. We avoid problems by
9327 claiming that all hard registers are used and clobbered at this
9329 emit_insn (gen_blockage ());
9334 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9335 ;; all of memory. This blocks insns from being moved across this point.
9337 (define_insn "blockage"
9338 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9341 [(set_attr "type" "none")
9342 (set_attr "length" "0")])
9348 (define_expand "sibcall"
9349 [(call (match_operand 0 "" "")
9350 (match_operand 1 "" ""))]
9353 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9357 (define_insn "*sibcall_br"
9358 [(call (mem:QI (reg SIBCALL_REGNUM))
9359 (match_operand 0 "const_int_operand" "n"))]
9360 "SIBLING_CALL_P (insn)
9361 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9363 [(set_attr "op_type" "RR")
9364 (set_attr "type" "branch")
9365 (set_attr "atype" "agen")])
9367 (define_insn "*sibcall_brc"
9368 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9369 (match_operand 1 "const_int_operand" "n"))]
9370 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9372 [(set_attr "op_type" "RI")
9373 (set_attr "type" "branch")])
9375 (define_insn "*sibcall_brcl"
9376 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9377 (match_operand 1 "const_int_operand" "n"))]
9378 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9380 [(set_attr "op_type" "RIL")
9381 (set_attr "type" "branch")])
9384 ; sibcall_value patterns
9387 (define_expand "sibcall_value"
9388 [(set (match_operand 0 "" "")
9389 (call (match_operand 1 "" "")
9390 (match_operand 2 "" "")))]
9393 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9397 (define_insn "*sibcall_value_br"
9398 [(set (match_operand 0 "" "")
9399 (call (mem:QI (reg SIBCALL_REGNUM))
9400 (match_operand 1 "const_int_operand" "n")))]
9401 "SIBLING_CALL_P (insn)
9402 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9404 [(set_attr "op_type" "RR")
9405 (set_attr "type" "branch")
9406 (set_attr "atype" "agen")])
9408 (define_insn "*sibcall_value_brc"
9409 [(set (match_operand 0 "" "")
9410 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9411 (match_operand 2 "const_int_operand" "n")))]
9412 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9414 [(set_attr "op_type" "RI")
9415 (set_attr "type" "branch")])
9417 (define_insn "*sibcall_value_brcl"
9418 [(set (match_operand 0 "" "")
9419 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9420 (match_operand 2 "const_int_operand" "n")))]
9421 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9423 [(set_attr "op_type" "RIL")
9424 (set_attr "type" "branch")])
9428 ; call instruction pattern(s).
9431 (define_expand "call"
9432 [(call (match_operand 0 "" "")
9433 (match_operand 1 "" ""))
9434 (use (match_operand 2 "" ""))]
9437 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9438 gen_rtx_REG (Pmode, RETURN_REGNUM));
9442 (define_insn "*bras"
9443 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9444 (match_operand 1 "const_int_operand" "n"))
9445 (clobber (match_operand 2 "register_operand" "=r"))]
9446 "!SIBLING_CALL_P (insn)
9447 && TARGET_SMALL_EXEC
9448 && GET_MODE (operands[2]) == Pmode"
9450 [(set_attr "op_type" "RI")
9451 (set_attr "type" "jsr")
9452 (set_attr "z196prop" "z196_cracked")])
9454 (define_insn "*brasl"
9455 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9456 (match_operand 1 "const_int_operand" "n"))
9457 (clobber (match_operand 2 "register_operand" "=r"))]
9458 "!SIBLING_CALL_P (insn)
9460 && GET_MODE (operands[2]) == Pmode"
9462 [(set_attr "op_type" "RIL")
9463 (set_attr "type" "jsr")
9464 (set_attr "z196prop" "z196_cracked")])
9466 (define_insn "*basr"
9467 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9468 (match_operand 1 "const_int_operand" "n"))
9469 (clobber (match_operand 2 "register_operand" "=r"))]
9470 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9472 if (get_attr_op_type (insn) == OP_TYPE_RR)
9473 return "basr\t%2,%0";
9475 return "bas\t%2,%a0";
9477 [(set (attr "op_type")
9478 (if_then_else (match_operand 0 "register_operand" "")
9479 (const_string "RR") (const_string "RX")))
9480 (set_attr "type" "jsr")
9481 (set_attr "atype" "agen")
9482 (set_attr "z196prop" "z196_cracked")])
9485 ; call_value instruction pattern(s).
9488 (define_expand "call_value"
9489 [(set (match_operand 0 "" "")
9490 (call (match_operand 1 "" "")
9491 (match_operand 2 "" "")))
9492 (use (match_operand 3 "" ""))]
9495 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9496 gen_rtx_REG (Pmode, RETURN_REGNUM));
9500 (define_insn "*bras_r"
9501 [(set (match_operand 0 "" "")
9502 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9503 (match_operand:SI 2 "const_int_operand" "n")))
9504 (clobber (match_operand 3 "register_operand" "=r"))]
9505 "!SIBLING_CALL_P (insn)
9506 && TARGET_SMALL_EXEC
9507 && GET_MODE (operands[3]) == Pmode"
9509 [(set_attr "op_type" "RI")
9510 (set_attr "type" "jsr")
9511 (set_attr "z196prop" "z196_cracked")])
9513 (define_insn "*brasl_r"
9514 [(set (match_operand 0 "" "")
9515 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9516 (match_operand 2 "const_int_operand" "n")))
9517 (clobber (match_operand 3 "register_operand" "=r"))]
9518 "!SIBLING_CALL_P (insn)
9520 && GET_MODE (operands[3]) == Pmode"
9522 [(set_attr "op_type" "RIL")
9523 (set_attr "type" "jsr")
9524 (set_attr "z196prop" "z196_cracked")])
9526 (define_insn "*basr_r"
9527 [(set (match_operand 0 "" "")
9528 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9529 (match_operand 2 "const_int_operand" "n")))
9530 (clobber (match_operand 3 "register_operand" "=r"))]
9531 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9533 if (get_attr_op_type (insn) == OP_TYPE_RR)
9534 return "basr\t%3,%1";
9536 return "bas\t%3,%a1";
9538 [(set (attr "op_type")
9539 (if_then_else (match_operand 1 "register_operand" "")
9540 (const_string "RR") (const_string "RX")))
9541 (set_attr "type" "jsr")
9542 (set_attr "atype" "agen")
9543 (set_attr "z196prop" "z196_cracked")])
9546 ;;- Thread-local storage support.
9549 (define_expand "get_thread_pointer<mode>"
9550 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9554 (define_expand "set_thread_pointer<mode>"
9555 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9556 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9560 (define_insn "*set_tp"
9561 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9564 [(set_attr "type" "none")
9565 (set_attr "length" "0")])
9567 (define_insn "*tls_load_64"
9568 [(set (match_operand:DI 0 "register_operand" "=d")
9569 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9570 (match_operand:DI 2 "" "")]
9574 [(set_attr "op_type" "RXE")
9575 (set_attr "z10prop" "z10_fwd_A3")])
9577 (define_insn "*tls_load_31"
9578 [(set (match_operand:SI 0 "register_operand" "=d,d")
9579 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9580 (match_operand:SI 2 "" "")]
9586 [(set_attr "op_type" "RX,RXY")
9587 (set_attr "type" "load")
9588 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9590 (define_insn "*bras_tls"
9591 [(set (match_operand 0 "" "")
9592 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9593 (match_operand 2 "const_int_operand" "n")))
9594 (clobber (match_operand 3 "register_operand" "=r"))
9595 (use (match_operand 4 "" ""))]
9596 "!SIBLING_CALL_P (insn)
9597 && TARGET_SMALL_EXEC
9598 && GET_MODE (operands[3]) == Pmode"
9600 [(set_attr "op_type" "RI")
9601 (set_attr "type" "jsr")
9602 (set_attr "z196prop" "z196_cracked")])
9604 (define_insn "*brasl_tls"
9605 [(set (match_operand 0 "" "")
9606 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9607 (match_operand 2 "const_int_operand" "n")))
9608 (clobber (match_operand 3 "register_operand" "=r"))
9609 (use (match_operand 4 "" ""))]
9610 "!SIBLING_CALL_P (insn)
9612 && GET_MODE (operands[3]) == Pmode"
9614 [(set_attr "op_type" "RIL")
9615 (set_attr "type" "jsr")
9616 (set_attr "z196prop" "z196_cracked")])
9618 (define_insn "*basr_tls"
9619 [(set (match_operand 0 "" "")
9620 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9621 (match_operand 2 "const_int_operand" "n")))
9622 (clobber (match_operand 3 "register_operand" "=r"))
9623 (use (match_operand 4 "" ""))]
9624 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9626 if (get_attr_op_type (insn) == OP_TYPE_RR)
9627 return "basr\t%3,%1%J4";
9629 return "bas\t%3,%a1%J4";
9631 [(set (attr "op_type")
9632 (if_then_else (match_operand 1 "register_operand" "")
9633 (const_string "RR") (const_string "RX")))
9634 (set_attr "type" "jsr")
9635 (set_attr "atype" "agen")
9636 (set_attr "z196prop" "z196_cracked")])
9639 ;;- Atomic operations
9643 ; memory barrier patterns.
9646 (define_expand "mem_signal_fence"
9647 [(match_operand:SI 0 "const_int_operand")] ;; model
9650 /* The s390 memory model is strong enough not to require any
9651 barrier in order to synchronize a thread with itself. */
9655 (define_expand "mem_thread_fence"
9656 [(match_operand:SI 0 "const_int_operand")] ;; model
9659 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9660 enough not to require barriers of any kind. */
9661 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9663 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9664 MEM_VOLATILE_P (mem) = 1;
9665 emit_insn (gen_mem_thread_fence_1 (mem));
9670 ; Although bcr is superscalar on Z10, this variant will never
9671 ; become part of an execution group.
9672 ; With z196 we can make use of the fast-BCR-serialization facility.
9673 ; This allows for a slightly faster sync which is sufficient for our
9675 (define_insn "mem_thread_fence_1"
9676 [(set (match_operand:BLK 0 "" "")
9677 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9685 [(set_attr "op_type" "RR")
9686 (set_attr "mnemonic" "bcr_flush")
9687 (set_attr "z196prop" "z196_alone")])
9690 ; atomic load/store operations
9693 ; Atomic loads need not examine the memory model at all.
9694 (define_expand "atomic_load<mode>"
9695 [(match_operand:DINT 0 "register_operand") ;; output
9696 (match_operand:DINT 1 "memory_operand") ;; memory
9697 (match_operand:SI 2 "const_int_operand")] ;; model
9700 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9703 if (<MODE>mode == TImode)
9704 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9705 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9706 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9708 emit_move_insn (operands[0], operands[1]);
9712 ; Different from movdi_31 in that we want no splitters.
9713 (define_insn "atomic_loaddi_1"
9714 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9715 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9723 [(set_attr "op_type" "RS,RSY,RS,RSY")
9724 (set_attr "type" "lm,lm,floaddf,floaddf")])
9726 (define_insn "atomic_loadti_1"
9727 [(set (match_operand:TI 0 "register_operand" "=r")
9728 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9732 [(set_attr "op_type" "RXY")
9733 (set_attr "type" "other")])
9735 ; Atomic stores must(?) enforce sequential consistency.
9736 (define_expand "atomic_store<mode>"
9737 [(match_operand:DINT 0 "memory_operand") ;; memory
9738 (match_operand:DINT 1 "register_operand") ;; input
9739 (match_operand:SI 2 "const_int_operand")] ;; model
9742 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9744 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9747 if (<MODE>mode == TImode)
9748 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9749 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9750 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9752 emit_move_insn (operands[0], operands[1]);
9753 if (is_mm_seq_cst (model))
9754 emit_insn (gen_mem_thread_fence (operands[2]));
9758 ; Different from movdi_31 in that we want no splitters.
9759 (define_insn "atomic_storedi_1"
9760 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9761 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9769 [(set_attr "op_type" "RS,RSY,RS,RSY")
9770 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9772 (define_insn "atomic_storeti_1"
9773 [(set (match_operand:TI 0 "memory_operand" "=RT")
9774 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9778 [(set_attr "op_type" "RXY")
9779 (set_attr "type" "other")])
9782 ; compare and swap patterns.
9785 (define_expand "atomic_compare_and_swap<mode>"
9786 [(match_operand:SI 0 "register_operand") ;; bool success output
9787 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9788 (match_operand:DGPR 2 "memory_operand") ;; memory
9789 (match_operand:DGPR 3 "register_operand") ;; expected intput
9790 (match_operand:DGPR 4 "register_operand") ;; newval intput
9791 (match_operand:SI 5 "const_int_operand") ;; is_weak
9792 (match_operand:SI 6 "const_int_operand") ;; success model
9793 (match_operand:SI 7 "const_int_operand")] ;; failure model
9796 rtx cc, cmp, output = operands[1];
9798 if (!register_operand (output, <MODE>mode))
9799 output = gen_reg_rtx (<MODE>mode);
9801 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9804 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9805 (output, operands[2], operands[3], operands[4]));
9807 /* We deliberately accept non-register operands in the predicate
9808 to ensure the write back to the output operand happens *before*
9809 the store-flags code below. This makes it easier for combine
9810 to merge the store-flags code with a potential test-and-branch
9811 pattern following (immediately!) afterwards. */
9812 if (output != operands[1])
9813 emit_move_insn (operands[1], output);
9815 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9816 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9817 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9821 (define_expand "atomic_compare_and_swap<mode>"
9822 [(match_operand:SI 0 "register_operand") ;; bool success output
9823 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9824 (match_operand:HQI 2 "memory_operand") ;; memory
9825 (match_operand:HQI 3 "general_operand") ;; expected intput
9826 (match_operand:HQI 4 "general_operand") ;; newval intput
9827 (match_operand:SI 5 "const_int_operand") ;; is_weak
9828 (match_operand:SI 6 "const_int_operand") ;; success model
9829 (match_operand:SI 7 "const_int_operand")] ;; failure model
9832 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9833 operands[3], operands[4], INTVAL (operands[5]));
9837 (define_expand "atomic_compare_and_swap<mode>_internal"
9839 [(set (match_operand:DGPR 0 "register_operand")
9840 (match_operand:DGPR 1 "memory_operand"))
9842 (unspec_volatile:DGPR
9844 (match_operand:DGPR 2 "register_operand")
9845 (match_operand:DGPR 3 "register_operand")]
9847 (set (reg:CCZ1 CC_REGNUM)
9848 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9852 (define_insn "*atomic_compare_and_swap<mode>_1"
9853 [(set (match_operand:TDI 0 "register_operand" "=r")
9854 (match_operand:TDI 1 "memory_operand" "+QS"))
9856 (unspec_volatile:TDI
9858 (match_operand:TDI 2 "register_operand" "0")
9859 (match_operand:TDI 3 "register_operand" "r")]
9861 (set (reg:CCZ1 CC_REGNUM)
9862 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9864 "c<td>sg\t%0,%3,%S1"
9865 [(set_attr "op_type" "RSY")
9866 (set_attr "type" "sem")])
9869 (define_insn "*atomic_compare_and_swapdi_2"
9870 [(set (match_operand:DI 0 "register_operand" "=r,r")
9871 (match_operand:DI 1 "memory_operand" "+Q,S"))
9875 (match_operand:DI 2 "register_operand" "0,0")
9876 (match_operand:DI 3 "register_operand" "r,r")]
9878 (set (reg:CCZ1 CC_REGNUM)
9879 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9884 [(set_attr "op_type" "RS,RSY")
9885 (set_attr "type" "sem")])
9888 (define_insn "*atomic_compare_and_swapsi_3"
9889 [(set (match_operand:SI 0 "register_operand" "=r,r")
9890 (match_operand:SI 1 "memory_operand" "+Q,S"))
9894 (match_operand:SI 2 "register_operand" "0,0")
9895 (match_operand:SI 3 "register_operand" "r,r")]
9897 (set (reg:CCZ1 CC_REGNUM)
9898 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9903 [(set_attr "op_type" "RS,RSY")
9904 (set_attr "type" "sem")])
9907 ; Other atomic instruction patterns.
9910 ; z196 load and add, xor, or and and instructions
9912 (define_expand "atomic_fetch_<atomic><mode>"
9913 [(match_operand:GPR 0 "register_operand") ;; val out
9915 (match_operand:GPR 1 "memory_operand") ;; memory
9916 (match_operand:GPR 2 "register_operand")) ;; val in
9917 (match_operand:SI 3 "const_int_operand")] ;; model
9920 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9923 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9924 (operands[0], operands[1], operands[2]));
9928 ; lan, lang, lao, laog, lax, laxg, laa, laag
9929 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9930 [(set (match_operand:GPR 0 "register_operand" "=d")
9931 (match_operand:GPR 1 "memory_operand" "+QS"))
9933 (unspec_volatile:GPR
9934 [(ATOMIC_Z196:GPR (match_dup 1)
9935 (match_operand:GPR 2 "general_operand" "d"))]
9937 (clobber (reg:CC CC_REGNUM))]
9939 "la<noxa><g>\t%0,%2,%1"
9940 [(set_attr "op_type" "RSY")
9941 (set_attr "type" "sem")])
9943 ;; For SImode and larger, the optabs.c code will do just fine in
9944 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9945 ;; better by expanding our own loop.
9947 (define_expand "atomic_<atomic><mode>"
9949 (match_operand:HQI 0 "memory_operand") ;; memory
9950 (match_operand:HQI 1 "general_operand")) ;; val in
9951 (match_operand:SI 2 "const_int_operand")] ;; model
9954 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9955 operands[1], false);
9959 (define_expand "atomic_fetch_<atomic><mode>"
9960 [(match_operand:HQI 0 "register_operand") ;; val out
9962 (match_operand:HQI 1 "memory_operand") ;; memory
9963 (match_operand:HQI 2 "general_operand")) ;; val in
9964 (match_operand:SI 3 "const_int_operand")] ;; model
9967 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9968 operands[2], false);
9972 (define_expand "atomic_<atomic>_fetch<mode>"
9973 [(match_operand:HQI 0 "register_operand") ;; val out
9975 (match_operand:HQI 1 "memory_operand") ;; memory
9976 (match_operand:HQI 2 "general_operand")) ;; val in
9977 (match_operand:SI 3 "const_int_operand")] ;; model
9980 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9985 (define_expand "atomic_exchange<mode>"
9986 [(match_operand:HQI 0 "register_operand") ;; val out
9987 (match_operand:HQI 1 "memory_operand") ;; memory
9988 (match_operand:HQI 2 "general_operand") ;; val in
9989 (match_operand:SI 3 "const_int_operand")] ;; model
9992 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9993 operands[2], false);
9998 ;;- Miscellaneous instructions.
10002 ; allocate stack instruction pattern(s).
10005 (define_expand "allocate_stack"
10006 [(match_operand 0 "general_operand" "")
10007 (match_operand 1 "general_operand" "")]
10010 rtx temp = gen_reg_rtx (Pmode);
10012 emit_move_insn (temp, s390_back_chain_rtx ());
10013 anti_adjust_stack (operands[1]);
10014 emit_move_insn (s390_back_chain_rtx (), temp);
10016 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10022 ; setjmp instruction pattern.
10025 (define_expand "builtin_setjmp_receiver"
10026 [(match_operand 0 "" "")]
10029 emit_insn (s390_load_got ());
10030 emit_use (pic_offset_table_rtx);
10034 ;; These patterns say how to save and restore the stack pointer. We need not
10035 ;; save the stack pointer at function level since we are careful to
10036 ;; preserve the backchain. At block level, we have to restore the backchain
10037 ;; when we restore the stack pointer.
10039 ;; For nonlocal gotos, we must save both the stack pointer and its
10040 ;; backchain and restore both. Note that in the nonlocal case, the
10041 ;; save area is a memory location.
10043 (define_expand "save_stack_function"
10044 [(match_operand 0 "general_operand" "")
10045 (match_operand 1 "general_operand" "")]
10049 (define_expand "restore_stack_function"
10050 [(match_operand 0 "general_operand" "")
10051 (match_operand 1 "general_operand" "")]
10055 (define_expand "restore_stack_block"
10056 [(match_operand 0 "register_operand" "")
10057 (match_operand 1 "register_operand" "")]
10060 rtx temp = gen_reg_rtx (Pmode);
10062 emit_move_insn (temp, s390_back_chain_rtx ());
10063 emit_move_insn (operands[0], operands[1]);
10064 emit_move_insn (s390_back_chain_rtx (), temp);
10069 (define_expand "save_stack_nonlocal"
10070 [(match_operand 0 "memory_operand" "")
10071 (match_operand 1 "register_operand" "")]
10074 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10076 /* Copy the backchain to the first word, sp to the second and the
10077 literal pool base to the third. */
10079 rtx save_bc = adjust_address (operands[0], Pmode, 0);
10080 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10081 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10083 if (TARGET_BACKCHAIN)
10084 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10086 emit_move_insn (save_sp, operands[1]);
10087 emit_move_insn (save_bp, base);
10092 (define_expand "restore_stack_nonlocal"
10093 [(match_operand 0 "register_operand" "")
10094 (match_operand 1 "memory_operand" "")]
10097 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10098 rtx temp = NULL_RTX;
10100 /* Restore the backchain from the first word, sp from the second and the
10101 literal pool base from the third. */
10103 rtx save_bc = adjust_address (operands[1], Pmode, 0);
10104 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10105 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10107 if (TARGET_BACKCHAIN)
10108 temp = force_reg (Pmode, save_bc);
10110 emit_move_insn (base, save_bp);
10111 emit_move_insn (operands[0], save_sp);
10114 emit_move_insn (s390_back_chain_rtx (), temp);
10120 (define_expand "exception_receiver"
10124 s390_set_has_landing_pad_p (true);
10129 ; nop instruction pattern(s).
10136 [(set_attr "op_type" "RR")
10137 (set_attr "z10prop" "z10_fr_E1")])
10139 (define_insn "nop1"
10143 [(set_attr "op_type" "RR")])
10145 ;;- Undeletable nops (used for hotpatching)
10147 (define_insn "nop_2_byte"
10148 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10151 [(set_attr "op_type" "RR")])
10153 (define_insn "nop_4_byte"
10154 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10157 [(set_attr "op_type" "RX")])
10159 (define_insn "nop_6_byte"
10160 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10163 [(set_attr "op_type" "RIL")])
10167 ; Special literal pool access instruction pattern(s).
10170 (define_insn "*pool_entry"
10171 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10172 UNSPECV_POOL_ENTRY)]
10175 machine_mode mode = GET_MODE (PATTERN (insn));
10176 unsigned int align = GET_MODE_BITSIZE (mode);
10177 s390_output_pool_entry (operands[0], mode, align);
10180 [(set (attr "length")
10181 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10183 (define_insn "pool_align"
10184 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10185 UNSPECV_POOL_ALIGN)]
10188 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10190 (define_insn "pool_section_start"
10191 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10193 ".section\t.rodata"
10194 [(set_attr "length" "0")])
10196 (define_insn "pool_section_end"
10197 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10200 [(set_attr "length" "0")])
10202 (define_insn "main_base_31_small"
10203 [(set (match_operand 0 "register_operand" "=a")
10204 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10205 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10207 [(set_attr "op_type" "RR")
10208 (set_attr "type" "la")
10209 (set_attr "z196prop" "z196_cracked")])
10211 (define_insn "main_base_31_large"
10212 [(set (match_operand 0 "register_operand" "=a")
10213 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10214 (set (pc) (label_ref (match_operand 2 "" "")))]
10215 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10217 [(set_attr "op_type" "RI")
10218 (set_attr "z196prop" "z196_cracked")])
10220 (define_insn "main_base_64"
10221 [(set (match_operand 0 "register_operand" "=a")
10222 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10223 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10225 [(set_attr "op_type" "RIL")
10226 (set_attr "type" "larl")
10227 (set_attr "z10prop" "z10_fwd_A1")])
10229 (define_insn "main_pool"
10230 [(set (match_operand 0 "register_operand" "=a")
10231 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10232 "GET_MODE (operands[0]) == Pmode"
10234 gcc_unreachable ();
10236 [(set (attr "type")
10237 (if_then_else (match_test "TARGET_CPU_ZARCH")
10238 (const_string "larl") (const_string "la")))])
10240 (define_insn "reload_base_31"
10241 [(set (match_operand 0 "register_operand" "=a")
10242 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10243 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10244 "basr\t%0,0\;la\t%0,%1-.(%0)"
10245 [(set_attr "length" "6")
10246 (set_attr "type" "la")
10247 (set_attr "z196prop" "z196_cracked")])
10249 (define_insn "reload_base_64"
10250 [(set (match_operand 0 "register_operand" "=a")
10251 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10252 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10254 [(set_attr "op_type" "RIL")
10255 (set_attr "type" "larl")
10256 (set_attr "z10prop" "z10_fwd_A1")])
10258 (define_insn "pool"
10259 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10262 gcc_unreachable ();
10264 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10267 ;; Insns related to generating the function prologue and epilogue.
10271 (define_expand "prologue"
10272 [(use (const_int 0))]
10274 "s390_emit_prologue (); DONE;")
10276 (define_expand "epilogue"
10277 [(use (const_int 1))]
10279 "s390_emit_epilogue (false); DONE;")
10281 (define_expand "sibcall_epilogue"
10282 [(use (const_int 0))]
10284 "s390_emit_epilogue (true); DONE;")
10286 ;; A direct return instruction, without using an epilogue.
10287 (define_insn "<code>"
10289 "s390_can_use_<code>_insn ()"
10291 [(set_attr "op_type" "RR")
10292 (set_attr "type" "jsr")
10293 (set_attr "atype" "agen")])
10295 (define_insn "*return"
10297 (use (match_operand 0 "register_operand" "a"))]
10298 "GET_MODE (operands[0]) == Pmode"
10300 [(set_attr "op_type" "RR")
10301 (set_attr "type" "jsr")
10302 (set_attr "atype" "agen")])
10305 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10306 ;; pointer. This is used for compatibility.
10308 (define_expand "ptr_extend"
10309 [(set (match_operand:DI 0 "register_operand" "=r")
10310 (match_operand:SI 1 "register_operand" "r"))]
10313 emit_insn (gen_anddi3 (operands[0],
10314 gen_lowpart (DImode, operands[1]),
10315 GEN_INT (0x7fffffff)));
10319 ;; Instruction definition to expand eh_return macro to support
10320 ;; swapping in special linkage return addresses.
10322 (define_expand "eh_return"
10323 [(use (match_operand 0 "register_operand" ""))]
10326 s390_emit_tpf_eh_return (operands[0]);
10331 ; Stack Protector Patterns
10334 (define_expand "stack_protect_set"
10335 [(set (match_operand 0 "memory_operand" "")
10336 (match_operand 1 "memory_operand" ""))]
10339 #ifdef TARGET_THREAD_SSP_OFFSET
10341 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10342 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10345 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10347 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10352 (define_insn "stack_protect_set<mode>"
10353 [(set (match_operand:DSI 0 "memory_operand" "=Q")
10354 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10356 "mvc\t%O0(%G0,%R0),%S1"
10357 [(set_attr "op_type" "SS")])
10359 (define_expand "stack_protect_test"
10360 [(set (reg:CC CC_REGNUM)
10361 (compare (match_operand 0 "memory_operand" "")
10362 (match_operand 1 "memory_operand" "")))
10363 (match_operand 2 "" "")]
10367 #ifdef TARGET_THREAD_SSP_OFFSET
10369 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10370 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10373 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10375 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10377 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10378 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10379 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10383 (define_insn "stack_protect_test<mode>"
10384 [(set (reg:CCZ CC_REGNUM)
10385 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10386 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10388 "clc\t%O0(%G0,%R0),%S1"
10389 [(set_attr "op_type" "SS")])
10391 ; This is used in s390_emit_prologue in order to prevent insns
10392 ; adjusting the stack pointer to be moved over insns writing stack
10393 ; slots using a copy of the stack pointer in a different register.
10394 (define_insn "stack_tie"
10395 [(set (match_operand:BLK 0 "memory_operand" "+m")
10396 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10399 [(set_attr "length" "0")])
10403 ; Data prefetch patterns
10406 (define_insn "prefetch"
10407 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
10408 (match_operand:SI 1 "const_int_operand" " n,n")
10409 (match_operand:SI 2 "const_int_operand" " n,n"))]
10412 switch (which_alternative)
10415 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10417 if (larl_operand (operands[0], Pmode))
10418 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10421 /* This might be reached for symbolic operands with an odd
10422 addend. We simply omit the prefetch for such rare cases. */
10427 [(set_attr "type" "load,larl")
10428 (set_attr "op_type" "RXY,RIL")
10429 (set_attr "z10prop" "z10_super")
10430 (set_attr "z196prop" "z196_alone")])
10434 ; Byte swap instructions
10437 (define_insn "bswap<mode>2"
10438 [(set (match_operand:GPR 0 "register_operand" "=d, d")
10439 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
10444 [(set_attr "type" "*,load")
10445 (set_attr "op_type" "RRE,RXY")
10446 (set_attr "z10prop" "z10_super")])
10450 ; Population count instruction
10453 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10454 ; portions and stores the result in the corresponding bytes in op0.
10455 (define_insn "*popcount<mode>"
10456 [(set (match_operand:INT 0 "register_operand" "=d")
10457 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10458 (clobber (reg:CC CC_REGNUM))]
10461 [(set_attr "op_type" "RRE")])
10463 (define_expand "popcountdi2"
10465 (parallel [(set (match_operand:DI 0 "register_operand" "")
10466 (unspec:DI [(match_operand:DI 1 "register_operand")]
10468 (clobber (reg:CC CC_REGNUM))])
10469 ; sllg op2, op0, 32
10470 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10472 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10473 (clobber (reg:CC CC_REGNUM))])
10474 ; sllg op2, op0, 16
10476 (ashift:DI (match_dup 0) (const_int 16)))
10478 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10479 (clobber (reg:CC CC_REGNUM))])
10481 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10483 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10484 (clobber (reg:CC CC_REGNUM))])
10485 ; srlg op0, op0, 56
10486 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10487 "TARGET_Z196 && TARGET_64BIT"
10488 "operands[2] = gen_reg_rtx (DImode);")
10490 (define_expand "popcountsi2"
10492 (parallel [(set (match_operand:SI 0 "register_operand" "")
10493 (unspec:SI [(match_operand:SI 1 "register_operand")]
10495 (clobber (reg:CC CC_REGNUM))])
10496 ; sllk op2, op0, 16
10498 (ashift:SI (match_dup 0) (const_int 16)))
10500 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10501 (clobber (reg:CC CC_REGNUM))])
10503 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10505 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10506 (clobber (reg:CC CC_REGNUM))])
10508 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10510 "operands[2] = gen_reg_rtx (SImode);")
10512 (define_expand "popcounthi2"
10514 (parallel [(set (match_operand:HI 0 "register_operand" "")
10515 (unspec:HI [(match_operand:HI 1 "register_operand")]
10517 (clobber (reg:CC CC_REGNUM))])
10520 (ashift:SI (match_dup 0) (const_int 8)))
10522 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10523 (clobber (reg:CC CC_REGNUM))])
10525 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10527 "operands[2] = gen_reg_rtx (SImode);")
10529 (define_expand "popcountqi2"
10531 (parallel [(set (match_operand:QI 0 "register_operand" "")
10532 (unspec:QI [(match_operand:QI 1 "register_operand")]
10534 (clobber (reg:CC CC_REGNUM))])]
10539 ;;- Copy sign instructions
10542 (define_insn "copysign<mode>3"
10543 [(set (match_operand:FP 0 "register_operand" "=f")
10544 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10545 (match_operand:FP 2 "register_operand" "f")]
10549 [(set_attr "op_type" "RRF")
10550 (set_attr "type" "fsimp<mode>")])
10554 ;;- Transactional execution instructions
10557 ; This splitter helps combine to make use of CC directly when
10558 ; comparing the integer result of a tbegin builtin with a constant.
10559 ; The unspec is already removed by canonicalize_comparison. So this
10560 ; splitters only job is to turn the PARALLEL into separate insns
10561 ; again. Unfortunately this only works with the very first cc/int
10562 ; compare since combine is not able to deal with data flow across
10563 ; basic block boundaries.
10565 ; It needs to be an insn pattern as well since combine does not apply
10566 ; the splitter directly. Combine would only use it if it actually
10567 ; would reduce the number of instructions.
10568 (define_insn_and_split "*ccraw_to_int"
10571 (match_operator 0 "s390_eqne_operator"
10572 [(reg:CCRAW CC_REGNUM)
10573 (match_operand 1 "const_int_operand" "")])
10574 (label_ref (match_operand 2 "" ""))
10576 (set (match_operand:SI 3 "register_operand" "=d")
10577 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10581 [(set (match_dup 3)
10582 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10584 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10585 (label_ref (match_dup 2))
10589 ; Non-constrained transaction begin
10591 (define_expand "tbegin"
10592 [(match_operand:SI 0 "register_operand" "")
10593 (match_operand:BLK 1 "memory_operand" "")]
10596 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10600 (define_expand "tbegin_nofloat"
10601 [(match_operand:SI 0 "register_operand" "")
10602 (match_operand:BLK 1 "memory_operand" "")]
10605 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10609 (define_expand "tbegin_retry"
10610 [(match_operand:SI 0 "register_operand" "")
10611 (match_operand:BLK 1 "memory_operand" "")
10612 (match_operand:SI 2 "general_operand" "")]
10615 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10619 (define_expand "tbegin_retry_nofloat"
10620 [(match_operand:SI 0 "register_operand" "")
10621 (match_operand:BLK 1 "memory_operand" "")
10622 (match_operand:SI 2 "general_operand" "")]
10625 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10629 (define_insn "tbegin_1"
10630 [(set (reg:CCRAW CC_REGNUM)
10631 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10633 (set (match_operand:BLK 1 "memory_operand" "=Q")
10634 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10635 (clobber (reg:DF 16))
10636 (clobber (reg:DF 17))
10637 (clobber (reg:DF 18))
10638 (clobber (reg:DF 19))
10639 (clobber (reg:DF 20))
10640 (clobber (reg:DF 21))
10641 (clobber (reg:DF 22))
10642 (clobber (reg:DF 23))
10643 (clobber (reg:DF 24))
10644 (clobber (reg:DF 25))
10645 (clobber (reg:DF 26))
10646 (clobber (reg:DF 27))
10647 (clobber (reg:DF 28))
10648 (clobber (reg:DF 29))
10649 (clobber (reg:DF 30))
10650 (clobber (reg:DF 31))]
10651 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10652 ; not supposed to be used for immediates (see genpreds.c).
10653 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10655 [(set_attr "op_type" "SIL")])
10657 ; Same as above but without the FPR clobbers
10658 (define_insn "tbegin_nofloat_1"
10659 [(set (reg:CCRAW CC_REGNUM)
10660 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10662 (set (match_operand:BLK 1 "memory_operand" "=Q")
10663 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10664 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10666 [(set_attr "op_type" "SIL")])
10669 ; Constrained transaction begin
10671 (define_expand "tbeginc"
10672 [(set (reg:CCRAW CC_REGNUM)
10673 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10678 (define_insn "*tbeginc_1"
10679 [(set (reg:CCRAW CC_REGNUM)
10680 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10682 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10684 [(set_attr "op_type" "SIL")])
10688 (define_expand "tend"
10689 [(set (reg:CCRAW CC_REGNUM)
10690 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10691 (set (match_operand:SI 0 "register_operand" "")
10692 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10696 (define_insn "*tend_1"
10697 [(set (reg:CCRAW CC_REGNUM)
10698 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10701 [(set_attr "op_type" "S")])
10703 ; Transaction abort
10705 (define_expand "tabort"
10706 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10708 "TARGET_HTM && operands != NULL"
10710 if (CONST_INT_P (operands[0])
10711 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10713 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10714 ". Values in range 0 through 255 are reserved.",
10715 INTVAL (operands[0]));
10720 (define_insn "*tabort_1"
10721 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10723 "TARGET_HTM && operands != NULL"
10725 [(set_attr "op_type" "S")])
10727 ; Transaction extract nesting depth
10729 (define_insn "etnd"
10730 [(set (match_operand:SI 0 "register_operand" "=d")
10731 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10734 [(set_attr "op_type" "RRE")])
10736 ; Non-transactional store
10738 (define_insn "ntstg"
10739 [(set (match_operand:DI 0 "memory_operand" "=RT")
10740 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10744 [(set_attr "op_type" "RXY")])
10746 ; Transaction perform processor assist
10748 (define_expand "tx_assist"
10749 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10750 (reg:SI GPR0_REGNUM)
10756 (define_insn "*ppa"
10757 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10758 (match_operand:SI 1 "register_operand" "d")
10759 (match_operand 2 "const_int_operand" "I")]
10761 "TARGET_HTM && INTVAL (operands[2]) < 16"
10763 [(set_attr "op_type" "RRF")])
10766 ; Set and get floating point control register
10768 (define_insn "sfpc"
10769 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10771 "TARGET_HARD_FLOAT"
10774 (define_insn "efpc"
10775 [(set (match_operand:SI 0 "register_operand" "=d")
10776 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10777 "TARGET_HARD_FLOAT"
10781 ; Load count to block boundary
10783 (define_insn "lcbb"
10784 [(set (match_operand:SI 0 "register_operand" "=d")
10785 (unspec:SI [(match_operand:SI 1 "address_operand" "ZQZR")
10786 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
10787 (clobber (reg:CC CC_REGNUM))]
10790 [(set_attr "op_type" "VRX")])