gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com).
   5 ;; This file is part of GNU CC.
   6
   7 ;; GNU CC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11
  12 ;; GNU CC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GNU CC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22 ;;
  23 ;; Special constraints for s/390 machine description:
  24 ;;
  25 ;;    a -- Any address register from 1 to 15.
  26 ;;    d -- Any register from 0 to 15.
  27 ;;    I -- An 8-bit constant (0..255).
  28 ;;    J -- A 12-bit constant (0..4095).
  29 ;;    K -- A 16-bit constant (-32768..32767).
  30 ;;    Q -- A memory reference without index-register.
  31 ;;    S -- Valid operand for the LARL instruction.
  32 ;;
  33 ;; Special formats used for outputting 390 instructions.
  34 ;;
  35 ;;   %b -- Print a constant byte integer.               xy
  36 ;;   %h -- Print a signed 16-bit.                       wxyz
  37 ;;   %N -- Print next register (second word of a DImode reg) or next word.
  38 ;;   %M -- Print next register (second word of a TImode reg) or next word.
  39 ;;   %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
  40 ;;   %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
  41 ;;
  42 ;; We have a special constraint for pattern matching.
  43 ;;
  44 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  45 ;;
  46
  47
  48 ;; Define an insn type attribute.  This is used in function unit delay
  49 ;; computations.
  50
  51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
  52   (const_string "integer"))
  53
  54 ;; Insn are devide in two classes:
  55 ;;   mem: Insn accessing memory
  56 ;;   reg: Insn operands all in registers
  57
  58 (define_attr "atype" "reg,mem"
  59   (const_string "reg"))
  60
  61 ;; Generic pipeline function unit.
  62
  63 (define_function_unit "integer" 1 0
  64   (eq_attr "type" "none") 0 0)
  65
  66 (define_function_unit "integer" 1 0
  67   (eq_attr "type" "integer") 1 1)
  68
  69 (define_function_unit "integer" 1 0
  70   (eq_attr "type" "load") 1 1)
  71
  72 (define_function_unit "integer" 1 0
  73   (eq_attr "type" "la") 1 1)
  74
  75 (define_function_unit "integer" 1 0
  76   (eq_attr "type" "lr") 1 1)
  77
  78 (define_function_unit "integer" 1 0
  79   (eq_attr "type" "store") 1 1)
  80
  81 (define_function_unit "integer" 1 0
  82   (eq_attr "type" "lm") 2 2)
  83
  84 (define_function_unit "integer" 1 0
  85   (eq_attr "type" "stm") 2 2)
  86
  87 (define_function_unit "integer" 1 0
  88   (eq_attr "type" "cs") 5 5)
  89
  90 (define_function_unit "integer" 1 0
  91   (eq_attr "type" "vs") 30 30)
  92
  93 (define_function_unit "integer" 1 0
  94   (eq_attr "type" "jsr") 5 5)
  95
  96 (define_function_unit "integer" 1 0
  97   (eq_attr "type" "imul") 7 7)
  98
  99 (define_function_unit "integer" 1 0
 100   (eq_attr "type" "fmul") 6 6)
 101
 102 (define_function_unit "integer" 1 0
 103   (eq_attr "type" "idiv") 33 33)
 104
 105 (define_function_unit "integer" 1 0
 106   (eq_attr "type" "fdiv") 33 33)
 107
 108 (define_function_unit "integer" 1 0
 109   (eq_attr "type" "o2") 2 2)
 110
 111 (define_function_unit "integer" 1 0
 112   (eq_attr "type" "o3") 3 3)
 113
 114 (define_function_unit "integer" 1 0
 115   (eq_attr "type" "other") 5 5)
 116
 117 ;; Operand type. Used to default length attribute values
 118
 119 (define_attr "op_type"
 120   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
 121   (const_string "RX"))
 122
 123 ;; Length in bytes.
 124
 125 (define_attr "length" ""
 126 (cond [ (eq_attr "op_type" "E")    (const_int 2)
 127          (eq_attr "op_type" "RR")  (const_int 2)
 128          (eq_attr "op_type" "RX")  (const_int 4)
 129          (eq_attr "op_type" "RI")  (const_int 4)
 130          (eq_attr "op_type" "RRE") (const_int 4)
 131          (eq_attr "op_type" "RS")  (const_int 4)
 132          (eq_attr "op_type" "RSI") (const_int 4)
 133          (eq_attr "op_type" "RX")  (const_int 4)
 134          (eq_attr "op_type" "S")   (const_int 4)
 135          (eq_attr "op_type" "SI")  (const_int 4)
 136          (eq_attr "op_type" "SS")  (const_int 6)
 137          (eq_attr "op_type" "SSE") (const_int 6)
 138          (eq_attr "op_type" "RXE") (const_int 6)
 139          (eq_attr "op_type" "RSE") (const_int 6)
 140          (eq_attr "op_type" "RIL") (const_int 6)]
 141          (const_int 4)))
 142
 143 ;; Define attributes for `asm' insns.
 144
 145 (define_asm_attributes [(set_attr "type" "other")
 146                         (set_attr "op_type" "NN")])
 147
 148 ;;
 149 ;;  Condition Codes
 150 ;;
 151 ;
 152 ;   CCL:  Zero     Nonzero   Zero      Nonzero      (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
 153 ;   CCA:  Zero     <Zero     >Zero     Overflow     (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
 154 ;   CCU:  Equal    ULess     UGreater  --           (CL, CLR, CLI, CLM)
 155 ;   CCS:  Equal    SLess     SGreater  --           (C, CR, CH, CHI, ICM)
 156 ;   CCT:  Zero     Mixed     Mixed     Ones         (TM, TMH, TML)
 157
 158 ;   CCZ  -> CCL / CCZ1
 159 ;   CCZ1 -> CCA/CCU/CCS/CCT
 160 ;   CCS  -> CCA
 161
 162 ;   String:    CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
 163 ;   Clobber:   CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
 164
 165
 166 ;;
 167 ;;- Compare instructions.
 168 ;;
 169
 170 (define_expand "cmpdi"
 171   [(set (reg:CC 33)
 172         (compare:CC (match_operand:DI 0 "register_operand" "")
 173                     (match_operand:DI 1 "general_operand" "")))]
 174   "TARGET_64BIT"
 175   "
 176 {
 177   s390_compare_op0 = operands[0];
 178   s390_compare_op1 = operands[1];
 179   DONE;
 180 }")
 181
 182 (define_expand "cmpsi"
 183   [(set (reg:CC 33)
 184         (compare:CC (match_operand:SI 0 "register_operand" "")
 185                     (match_operand:SI 1 "general_operand" "")))]
 186   ""
 187   "
 188 {
 189   s390_compare_op0 = operands[0];
 190   s390_compare_op1 = operands[1];
 191   DONE;
 192 }")
 193
 194 ;(define_expand "cmphi"
 195 ;  [(set (reg:CC 33)
 196 ;        (compare:CC (match_operand:HI 0 "register_operand" "")
 197 ;                    (match_operand:HI 1 "general_operand" "")))]
 198 ;  ""
 199 ;  "
 200 ;{
 201 ;  s390_compare_op0 = operands[0];
 202 ;  s390_compare_op1 = operands[1];
 203 ;  DONE;
 204 ;}")
 205
 206 ;(define_expand "cmpqi"
 207 ;  [(set (reg:CC 33)
 208 ;        (compare:CC (match_operand:QI 0 "register_operand" "")
 209 ;                    (match_operand:QI 1 "general_operand" "")))]
 210 ;  ""
 211 ;  "
 212 ;{
 213 ;  s390_compare_op0 = operands[0];
 214 ;  s390_compare_op1 = operands[1];
 215 ;  DONE;
 216 ;}")
 217
 218 (define_expand "cmpdf"
 219   [(set (reg:CC 33)
 220         (compare:CC (match_operand:DF 0 "register_operand" "")
 221                     (match_operand:DF 1 "general_operand" "")))]
 222   "TARGET_HARD_FLOAT"
 223   "
 224 {
 225   s390_compare_op0 = operands[0];
 226   s390_compare_op1 = operands[1];
 227   DONE;
 228 }")
 229
 230 (define_expand "cmpsf"
 231   [(set (reg:CC 33)
 232         (compare:CC (match_operand:SF 0 "register_operand" "")
 233                     (match_operand:SF 1 "general_operand" "")))]
 234   "TARGET_HARD_FLOAT"
 235   "
 236 {
 237   s390_compare_op0 = operands[0];
 238   s390_compare_op1 = operands[1];
 239   DONE;
 240 }")
 241
 242
 243 ; DI instructions
 244
 245 (define_insn "*cmpdi_tm2"
 246   [(set (reg 33)
 247         (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
 248                                   (match_operand:DI 1 "const_int_operand" "n")
 249                                   (match_operand:DI 2 "const_int_operand" "n"))
 250                  (const_int 0)))]
 251   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
 252    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 253    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
 254    && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
 255       == INTVAL (operands[2]) >> 4"
 256   "*
 257 {
 258   int part = INTVAL (operands[2]) >> 4;
 259   int block = (1 << INTVAL (operands[1])) - 1;
 260   int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
 261
 262   operands[2] = GEN_INT (block << shift);
 263
 264   switch (part)
 265     {
 266       case 0: return \"tmhh\\t%0,%x2\";
 267       case 1: return \"tmhl\\t%0,%x2\";
 268       case 2: return \"tmlh\\t%0,%x2\";
 269       case 3: return \"tmll\\t%0,%x2\";
 270       default: abort ();
 271     }
 272 }"
 273   [(set_attr "op_type" "RI")])
 274
 275 (define_insn "*cmpdi_tm_reg"
 276   [(set (reg 33)
 277         (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
 278                          (match_operand:DI 1 "immediate_operand" "n"))
 279                  (const_int 0)))]
 280   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
 281    && s390_single_hi (operands[1], DImode, 0) >= 0"
 282   "*
 283 {
 284   int part = s390_single_hi (operands[1], DImode, 0);
 285   operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
 286
 287   switch (part)
 288     {
 289       case 0: return \"tmhh\\t%0,%x1\";
 290       case 1: return \"tmhl\\t%0,%x1\";
 291       case 2: return \"tmlh\\t%0,%x1\";
 292       case 3: return \"tmll\\t%0,%x1\";
 293       default: abort ();
 294     }
 295 }"
 296   [(set_attr "op_type" "RI")])
 297
 298 (define_insn "*cmpdi_tm_mem"
 299   [(set (reg 33)
 300         (compare (and:DI (match_operand:DI 0 "s_operand" "%Qo")
 301                          (match_operand:DI 1 "immediate_operand" "n"))
 302                  (const_int 0)))]
 303   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
 304    && s390_single_qi (operands[1], DImode, 0) >= 0"
 305   "*
 306 {
 307   int part = s390_single_qi (operands[1], DImode, 0);
 308   operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
 309
 310   operands[0] = gen_rtx_MEM (QImode,
 311                              plus_constant (XEXP (operands[0], 0), part));
 312   return \"tm\\t%0,%b1\";
 313 }"
 314   [(set_attr "op_type" "SI")
 315    (set_attr "atype"   "mem")])
 316
 317 (define_insn "*ltgr"
 318   [(set (reg 33)
 319         (compare (match_operand:DI 0 "register_operand" "d")
 320                  (match_operand:DI 1 "const0_operand" "")))
 321    (set (match_operand:DI 2 "register_operand" "=d")
 322         (match_dup 0))]
 323   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 324   "ltgr\\t%2,%0"
 325   [(set_attr "op_type" "RRE")])
 326
 327 (define_insn "*cmpdi_ccs_0_64"
 328   [(set (reg 33)
 329         (compare (match_operand:DI 0 "register_operand" "d")
 330                  (match_operand:DI 1 "const0_operand" "")))]
 331   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 332   "ltgr\\t%0,%0"
 333   [(set_attr "op_type" "RRE")])
 334
 335 (define_insn "*cmpdi_ccs_0_31"
 336   [(set (reg 33)
 337         (compare (match_operand:DI 0 "register_operand" "d")
 338                  (match_operand:DI 1 "const0_operand" "")))]
 339   "s390_match_ccmode(insn, CCSmode)"
 340   "srda\\t%0,0"
 341   [(set_attr "op_type" "RS")])
 342
 343 (define_insn "*cmpdi_ccs"
 344   [(set (reg 33)
 345         (compare (match_operand:DI 0 "register_operand" "d,d,d")
 346                  (match_operand:DI 1 "general_operand" "d,K,m")))]
 347   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 348   "@
 349    cgr\\t%0,%1
 350    cghi\\t%0,%c1
 351    cg\\t%0,%1"
 352   [(set_attr "op_type" "RRE,RI,RXE")
 353    (set_attr "atype"    "reg,reg,mem")])
 354
 355 (define_insn "*cmpdi_ccu"
 356   [(set (reg 33)
 357         (compare (match_operand:DI 0 "register_operand" "d,d")
 358                  (match_operand:DI 1 "general_operand" "d,m")))]
 359   "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
 360   "@
 361    clgr\\t%0,%1
 362    clg\\t%0,%1"
 363   [(set_attr "op_type" "RRE,RXE")
 364    (set_attr "atype"   "reg,mem")])
 365
 366 (define_insn "*cmpdi_ccu_mem"
 367   [(set (reg 33)
 368         (compare (match_operand:DI 0 "s_imm_operand" "oQ")
 369                  (match_operand:DI 1 "s_imm_operand" "oQ")))]
 370   "s390_match_ccmode(insn, CCUmode)"
 371   "clc\\t%O0(8,%R0),%1"
 372   [(set_attr "op_type" "SS")
 373    (set_attr "atype"   "mem")])
 374
 375 ; SI instructions
 376
 377 (define_insn "*cmpsi_tm2"
 378   [(set (reg 33)
 379         (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
 380                                   (match_operand:SI 1 "const_int_operand" "n")
 381                                   (match_operand:SI 2 "const_int_operand" "n"))
 382                  (const_int 0)))]
 383   "s390_match_ccmode(insn, CCTmode)
 384    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 385    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
 386    && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
 387       == INTVAL (operands[2]) >> 4"
 388   "*
 389 {
 390   int part = INTVAL (operands[2]) >> 4;
 391   int block = (1 << INTVAL (operands[1])) - 1;
 392   int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
 393
 394   operands[2] = GEN_INT (block << shift);
 395
 396   switch (part)
 397     {
 398       case 0: return \"tmh\\t%0,%x2\";
 399       case 1: return \"tml\\t%0,%x2\";
 400       default: abort ();
 401     }
 402 }"
 403   [(set_attr "op_type" "RI")])
 404
 405 (define_insn "*cmpsi_tm_reg"
 406   [(set (reg 33)
 407         (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
 408                          (match_operand:SI 1 "immediate_operand" "n"))
 409                  (const_int 0)))]
 410   "s390_match_ccmode(insn, CCTmode)
 411    && s390_single_hi (operands[1], SImode, 0) >= 0"
 412   "*
 413 {
 414   int part = s390_single_hi (operands[1], SImode, 0);
 415   operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
 416
 417   switch (part)
 418     {
 419       case 0: return \"tmh\\t%0,%x1\";
 420       case 1: return \"tml\\t%0,%x1\";
 421       default: abort ();
 422     }
 423 }"
 424   [(set_attr "op_type" "RI")])
 425
 426 (define_insn "*cmpsi_tm_mem"
 427   [(set (reg 33)
 428         (compare (and:SI (match_operand:SI 0 "s_operand" "%Qo")
 429                          (match_operand:SI 1 "immediate_operand" "n"))
 430                  (const_int 0)))]
 431   "s390_match_ccmode(insn, CCTmode)
 432    && s390_single_qi (operands[1], SImode, 0) >= 0"
 433   "*
 434 {
 435   int part = s390_single_qi (operands[1], SImode, 0);
 436   operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
 437
 438   operands[0] = gen_rtx_MEM (QImode,
 439                              plus_constant (XEXP (operands[0], 0), part));
 440   return \"tm\\t%0,%b1\";
 441 }"
 442   [(set_attr "op_type" "SI")
 443    (set_attr "atype"   "mem")])
 444
 445 (define_insn "*ltr"
 446   [(set (reg 33)
 447         (compare (match_operand:SI 0 "register_operand" "d")
 448                  (match_operand:SI 1 "const0_operand" "")))
 449    (set (match_operand:SI 2 "register_operand" "=d")
 450         (match_dup 0))]
 451   "s390_match_ccmode(insn, CCSmode)"
 452   "ltr\\t%2,%0"
 453   [(set_attr "op_type" "RR")])
 454
 455 (define_insn "*icm15"
 456   [(set (reg 33)
 457         (compare (match_operand:SI 0 "s_operand" "Qo")
 458                  (match_operand:SI 1 "const0_operand" "")))
 459    (set (match_operand:SI 2 "register_operand" "=d")
 460         (match_dup 0))]
 461   "s390_match_ccmode(insn, CCSmode)"
 462   "icm\\t%2,15,%0"
 463   [(set_attr "op_type" "RS")
 464    (set_attr "atype"   "mem")])
 465
 466 (define_insn "*icm15_cconly"
 467   [(set (reg 33)
 468         (compare (match_operand:SI 0 "s_operand" "Qo")
 469                  (match_operand:SI 1 "const0_operand" "")))
 470    (clobber (match_scratch:SI 2 "=d"))]
 471   "s390_match_ccmode(insn, CCSmode)"
 472   "icm\\t%2,15,%0"
 473   [(set_attr "op_type" "RS")
 474    (set_attr "atype"   "mem")])
 475
 476 (define_insn "*cmpsi_ccs_0"
 477   [(set (reg 33)
 478         (compare (match_operand:SI 0 "register_operand" "d")
 479                  (match_operand:SI 1 "const0_operand" "")))]
 480   "s390_match_ccmode(insn, CCSmode)"
 481   "ltr\\t%0,%0"
 482   [(set_attr "op_type" "RR")])
 483
 484 (define_insn "*cmpsidi_ccs"
 485   [(set (reg 33)
 486         (compare (match_operand:SI 0 "register_operand" "d")
 487                  (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
 488   "s390_match_ccmode(insn, CCSmode)"
 489   "ch\\t%0,%1"
 490   [(set_attr "op_type" "RR")
 491    (set_attr "atype"   "mem")])
 492
 493 (define_insn "*cmpsi_ccs"
 494   [(set (reg 33)
 495         (compare (match_operand:SI 0 "register_operand" "d,d,d")
 496                  (match_operand:SI 1 "general_operand" "d,K,m")))]
 497   "s390_match_ccmode(insn, CCSmode)"
 498   "@
 499    cr\\t%0,%1
 500    chi\\t%0,%c1
 501    c\\t%0,%1"
 502   [(set_attr "op_type" "RR,RI,RX")
 503    (set_attr "atype"   "reg,reg,mem")])
 504
 505 (define_insn "*cmpsi_ccu"
 506   [(set (reg 33)
 507         (compare (match_operand:SI 0 "register_operand" "d,d")
 508                  (match_operand:SI 1 "general_operand" "d,m")))]
 509   "s390_match_ccmode(insn, CCUmode)"
 510   "@
 511    clr\\t%0,%1
 512    cl\\t%0,%1"
 513   [(set_attr "op_type" "RR,RX")
 514    (set_attr "atype"   "reg,mem")])
 515
 516 (define_insn "*cmpsi_ccu_mem"
 517   [(set (reg 33)
 518         (compare (match_operand:SI 0 "s_imm_operand" "oQ")
 519                  (match_operand:SI 1 "s_imm_operand" "oQ")))]
 520   "s390_match_ccmode(insn, CCUmode)"
 521   "clc\\t%O0(4,%R0),%1"
 522    [(set_attr "op_type" "SS")
 523     (set_attr "atype"   "mem")])
 524
 525
 526 ; HI instructions
 527
 528 (define_insn "*cmphi_tm_sub"
 529   [(set (reg 33)
 530         (compare (and:SI (subreg:SI (match_operand:HI 0 "s_operand" "%Qo") 0)
 531                          (match_operand:SI 1 "immediate_operand" "n"))
 532                  (const_int 0)))]
 533   "s390_match_ccmode(insn, CCTmode)
 534    && s390_single_qi (operands[1], HImode, 0) >= 0"
 535   "*
 536 {
 537   int part = s390_single_qi (operands[1], HImode, 0);
 538   operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
 539
 540   operands[0] = gen_rtx_MEM (QImode,
 541                              plus_constant (XEXP (operands[0], 0), part));
 542   return \"tm\\t%0,%b1\";
 543 }"
 544   [(set_attr "op_type" "SI")
 545    (set_attr "atype"   "mem")])
 546
 547 (define_insn "*icm3"
 548   [(set (reg 33)
 549         (compare (match_operand:HI 0 "s_operand" "Qo")
 550                  (match_operand:HI 1 "const0_operand" "")))
 551    (set (match_operand:HI 2 "register_operand" "=d")
 552         (match_dup 0))]
 553   "s390_match_ccmode(insn, CCSmode)"
 554   "icm\\t%2,3,%0"
 555   [(set_attr "op_type" "RS")
 556    (set_attr "atype"   "mem")])
 557
 558 (define_insn "*cmphi_cct_0"
 559   [(set (reg 33)
 560         (compare (match_operand:HI 0 "register_operand" "d")
 561                  (match_operand:HI 1 "const0_operand"   "")))]
 562   "s390_match_ccmode(insn, CCTmode)"
 563   "tml\\t%0,65535"
 564   [(set_attr "op_type" "RX")])
 565
 566 (define_insn "*cmphi_ccs_0"
 567   [(set (reg 33)
 568         (compare (match_operand:HI 0 "s_operand" "Qo")
 569                  (match_operand:HI 1 "const0_operand" "")))
 570    (clobber (match_scratch:HI 2 "=d"))]
 571   "s390_match_ccmode(insn, CCSmode)"
 572   "icm\\t%2,3,%0"
 573   [(set_attr "op_type" "RS")
 574    (set_attr "atype"   "mem")])
 575
 576 (define_insn "*cmphi_ccu"
 577   [(set (reg 33)
 578         (compare (match_operand:HI 0 "register_operand" "d")
 579                  (match_operand:HI 1 "s_imm_operand" "Qo")))]
 580   "s390_match_ccmode(insn, CCUmode)"
 581   "clm\\t%0,3,%1"
 582   [(set_attr "op_type" "RS")
 583    (set_attr "atype"   "mem")])
 584
 585 (define_insn "*cmphi_ccu_mem"
 586   [(set (reg 33)
 587         (compare (match_operand:HI 0 "s_imm_operand" "oQ")
 588                  (match_operand:HI 1 "s_imm_operand" "oQ")))]
 589   "s390_match_ccmode(insn, CCUmode)"
 590   "clc\\t%O0(2,%R0),%1"
 591   [(set_attr "op_type" "SS")
 592    (set_attr "atype"   "mem")])
 593
 594
 595 ; QI instructions
 596
 597 (define_insn "*cmpqi_tm2"
 598   [(set (reg 33)
 599         (compare (zero_extract:SI (match_operand:QI 0 "s_operand" "Qo")
 600                                   (match_operand:SI 1 "const_int_operand" "n")
 601                                   (match_operand:SI 2 "const_int_operand" "n"))
 602                  (const_int 0)))]
 603   "s390_match_ccmode(insn, CCTmode)
 604    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 605    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
 606   "*
 607 {
 608   int block = (1 << INTVAL (operands[1])) - 1;
 609   int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
 610
 611   operands[2] = GEN_INT (block << shift);
 612   return \"tm\\t%0,%b2\";
 613 }"
 614   [(set_attr "op_type" "SI")
 615    (set_attr "atype"   "mem")])
 616
 617 (define_insn "*cmpqi_tm"
 618   [(set (reg 33)
 619         (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,Q")
 620                          (match_operand:QI 1 "immediate_operand" "n,n"))
 621                  (const_int 0)))]
 622   "s390_match_ccmode(insn, CCTmode)"
 623   "@
 624    tml\\t%0,%b1
 625    tm\\t%0,%b1"
 626   [(set_attr "op_type" "RI,SI")
 627    (set_attr "atype"   "reg,mem")])
 628
 629 (define_insn "*cmpqi_tm_sub"
 630   [(set (reg 33)
 631         (compare (and:SI (subreg:SI (match_operand:QI 0 "s_operand" "%Qo") 0)
 632                          (match_operand:SI 1 "immediate_operand" "n"))
 633                  (const_int 0)))]
 634   "s390_match_ccmode(insn, CCTmode)"
 635   "tm\\t%0,%b1"
 636   [(set_attr "op_type" "SI")
 637    (set_attr "atype"   "mem")])
 638
 639 (define_insn "*icm1"
 640   [(set (reg 33)
 641         (compare (match_operand:QI 0 "s_operand" "Qo")
 642                  (match_operand:QI 1 "const0_operand" "")))
 643    (set (match_operand:QI 2 "register_operand" "=d")
 644         (match_dup 0))]
 645   "s390_match_ccmode(insn, CCSmode)"
 646   "icm\\t%2,1,%0"
 647   [(set_attr "op_type" "RS")
 648    (set_attr "atype"   "mem")])
 649
 650 (define_insn "*tm_0"
 651   [(set (reg 33)
 652         (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
 653                                          (match_operand:QI 1 "immediate_operand" "")))
 654                  (const_int 0)))]
 655   "s390_match_ccmode(insn, CCTmode) &&
 656    INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
 657   "tm\\t%0,%1"
 658   [(set_attr "op_type" "RI")
 659    (set_attr "atype"   "mem")])
 660
 661 (define_insn "*cmpqi_cct_0"
 662   [(set (reg 33)
 663         (compare (match_operand:QI 0 "register_operand" "d")
 664                  (match_operand:QI 1 "const0_operand"   "")))]
 665   "s390_match_ccmode(insn, CCTmode)"
 666   "tml\\t%0,255"
 667   [(set_attr "op_type" "RI")])
 668
 669 (define_insn "*cmpqi_ccs_0"
 670   [(set (reg 33)
 671         (compare (match_operand:QI 0 "s_operand" "Qo")
 672                  (match_operand:QI 1 "const0_operand" "")))
 673    (clobber (match_scratch:QI 2 "=d"))]
 674   "s390_match_ccmode(insn, CCSmode)"
 675   "icm\\t%2,1,%0"
 676   [(set_attr "op_type" "RS")
 677    (set_attr "atype"   "mem")])
 678
 679 (define_insn "*cmpqi_ccu_0"
 680   [(set (reg 33)
 681         (compare (match_operand:QI 0 "s_operand"      "Qo")
 682                  (match_operand:QI 1 "const0_operand" "")))]
 683   "s390_match_ccmode(insn, CCUmode)"
 684   "cli\\t%0,0"
 685   [(set_attr "op_type" "SI")
 686    (set_attr "atype"   "mem")])
 687
 688 (define_insn "*cmpqi_ccu"
 689   [(set (reg 33)
 690         (compare (match_operand:QI 0 "register_operand" "d")
 691                  (match_operand:QI 1 "s_imm_operand" "Qo")))]
 692   "s390_match_ccmode(insn, CCUmode)"
 693   "clm\\t%0,1,%1"
 694   [(set_attr "op_type" "RS")
 695    (set_attr "atype"   "mem")])
 696
 697 (define_insn "*cmpqi_ccu_immed"
 698   [(set (reg 33)
 699         (compare (match_operand:QI 0 "s_operand" "Qo")
 700                  (match_operand:QI 1 "const_int_operand" "n")))]
 701   "s390_match_ccmode(insn, CCUmode) &&
 702    INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
 703   "cli\\t%0,%1"
 704   [(set_attr "op_type" "SI")
 705    (set_attr "atype"   "mem")])
 706
 707 (define_insn "*cmpqi_ccu_mem"
 708   [(set (reg 33)
 709         (compare (match_operand:QI 0 "s_imm_operand" "oQ")
 710                  (match_operand:QI 1 "s_imm_operand" "oQ")))]
 711   "s390_match_ccmode(insn, CCUmode)"
 712   "clc\\t%O0(1,%R0),%1"
 713   [(set_attr "op_type" "SS")
 714    (set_attr "atype"   "mem")])
 715
 716
 717 ; DF instructions
 718
 719 (define_insn "*cmpdf_ccs_0"
 720   [(set (reg 33)
 721         (compare (match_operand:DF 0 "register_operand" "f")
 722                  (match_operand:DF 1 "const0_operand" "")))]
 723   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 724   "ltdbr\\t%0,%0"
 725    [(set_attr "op_type" "RR")])
 726
 727 (define_insn "*cmpdf_ccs_0_ibm"
 728   [(set (reg 33)
 729         (compare (match_operand:DF 0 "register_operand" "f")
 730                  (match_operand:DF 1 "const0_operand" "")))]
 731   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 732   "ltdr\\t%0,%0"
 733    [(set_attr "op_type" "RR")])
 734
 735 (define_insn "*cmpdf_ccs"
 736   [(set (reg 33)
 737         (compare (match_operand:DF 0 "register_operand" "f,f")
 738                  (match_operand:DF 1 "general_operand" "f,m")))]
 739   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 740   "@
 741    cdbr\\t%0,%1
 742    cdb\\t%0,%1"
 743    [(set_attr "op_type" "RR,RX")
 744     (set_attr "atype"   "reg,mem")])
 745
 746 (define_insn "*cmpdf_ccs_ibm"
 747   [(set (reg 33)
 748         (compare (match_operand:DF 0 "register_operand" "f,f")
 749                  (match_operand:DF 1 "general_operand" "f,m")))]
 750   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 751   "@
 752    cdr\\t%0,%1
 753    cd\\t%0,%1"
 754    [(set_attr "op_type" "RR,RX")
 755     (set_attr "atype"   "reg,mem")])
 756
 757
 758 ; SF instructions
 759
 760 (define_insn "*cmpsf_ccs_0"
 761   [(set (reg 33)
 762         (compare (match_operand:SF 0 "register_operand" "f")
 763                  (match_operand:SF 1 "const0_operand" "")))]
 764   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 765   "ltebr\\t%0,%0"
 766    [(set_attr "op_type" "RR")])
 767
 768 (define_insn "*cmpsf_ccs_0_ibm"
 769   [(set (reg 33)
 770         (compare (match_operand:SF 0 "register_operand" "f")
 771                  (match_operand:SF 1 "const0_operand" "")))]
 772   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 773   "lter\\t%0,%0"
 774    [(set_attr "op_type" "RR")])
 775
 776 (define_insn "*cmpsf_ccs"
 777   [(set (reg 33)
 778         (compare (match_operand:SF 0 "register_operand" "f,f")
 779                  (match_operand:SF 1 "general_operand" "f,m")))]
 780   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 781   "@
 782    cebr\\t%0,%1
 783    ceb\\t%0,%1"
 784   [(set_attr "op_type" "RR,RX")
 785    (set_attr "atype"   "reg,mem")])
 786
 787 (define_insn "*cmpsf_ccs"
 788   [(set (reg 33)
 789         (compare (match_operand:SF 0 "register_operand" "f,f")
 790                  (match_operand:SF 1 "general_operand" "f,m")))]
 791   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 792   "@
 793    cer\\t%0,%1
 794    ce\\t%0,%1"
 795   [(set_attr "op_type" "RR,RX")
 796    (set_attr "atype"   "reg,mem")])
 797
 798
 799 ;;
 800 ;;- Move instructions.
 801 ;;
 802
 803 ;
 804 ; movti instruction pattern(s).
 805 ;
 806
 807 (define_insn "*movti_ss"
 808   [(set (match_operand:TI 0 "s_operand" "=Qo")
 809         (match_operand:TI 1 "s_imm_operand" "Qo"))]
 810   ""
 811   "mvc\\t%O0(16,%R0),%1"
 812   [(set_attr "op_type" "SS")
 813    (set_attr "atype"   "mem")])
 814
 815 (define_insn "movti"
 816   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m")
 817         (match_operand:TI 1 "general_operand" "Q,d,dKm,d"))]
 818   "TARGET_64BIT"
 819   "@
 820    lmg\\t%0,%N0,%1
 821    stmg\\t%1,%N1,%0
 822    #
 823    #"
 824   [(set_attr "op_type" "RSE,RSE,NN,NN")
 825    (set_attr "atype"   "mem")])
 826
 827 (define_split
 828   [(set (match_operand:TI 0 "nonimmediate_operand" "")
 829         (match_operand:TI 1 "general_operand" ""))]
 830   "TARGET_64BIT && reload_completed
 831    && !s_operand (operands[0], VOIDmode)
 832    && !s_operand (operands[1], VOIDmode)
 833    && (register_operand (operands[0], VOIDmode)
 834        || register_operand (operands[1], VOIDmode))
 835    && (!register_operand (operands[0], VOIDmode)
 836        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
 837                                     operands[1])
 838        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
 839                                     operands[1]))"
 840   [(set (match_dup 2) (match_dup 4))
 841    (set (match_dup 3) (match_dup 5))]
 842   "
 843 {
 844   if (!register_operand (operands[0], VOIDmode)
 845       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
 846                                    operands[1]))
 847     {
 848       operands[2] = operand_subword (operands[0], 0, 0, TImode);
 849       operands[3] = operand_subword (operands[0], 1, 0, TImode);
 850       operands[4] = operand_subword (operands[1], 0, 0, TImode);
 851       operands[5] = operand_subword (operands[1], 1, 0, TImode);
 852     }
 853   else
 854     {
 855       operands[2] = operand_subword (operands[0], 1, 0, TImode);
 856       operands[3] = operand_subword (operands[0], 0, 0, TImode);
 857       operands[4] = operand_subword (operands[1], 1, 0, TImode);
 858       operands[5] = operand_subword (operands[1], 0, 0, TImode);
 859     }
 860 }")
 861
 862 (define_split
 863   [(set (match_operand:TI 0 "register_operand" "")
 864         (match_operand:TI 1 "memory_operand" ""))]
 865   "TARGET_64BIT && reload_completed
 866    && !s_operand (operands[1], VOIDmode)"
 867   [(set (match_dup 2) (match_dup 3))
 868    (set (match_dup 0) (mem:TI (match_dup 2)))]
 869   "operands[2] = operand_subword (operands[0], 0, 0, TImode);
 870    operands[3] = XEXP (operands[1], 0);")
 871
 872 ;
 873 ; movdi instruction pattern(s).
 874 ;
 875
 876 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
 877 ;; move to get the address of the symbolic object from the GOT.
 878
 879 (define_expand "movdi"
 880   [(set (match_operand:DI 0 "general_operand" "")
 881         (match_operand:DI 1 "general_operand" ""))]
 882   ""
 883   "
 884 {
 885   /* Handle PIC symbolic constants.  */
 886   if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
 887     emit_pic_move (operands, DImode);
 888
 889   /* During and after reload, we need to force constants
 890      to the literal pool ourselves, if necessary.  */
 891   if ((reload_in_progress || reload_completed)
 892       && CONSTANT_P (operands[1])
 893       && (!legitimate_reload_constant_p (operands[1])
 894           || fp_operand (operands[0], VOIDmode)))
 895     operands[1] = force_const_mem (DImode, operands[1]);
 896 }")
 897
 898 (define_insn "*movdi_lhi"
 899   [(set (match_operand:DI 0 "register_operand" "=d")
 900         (match_operand:DI 1 "immediate_operand" "K"))]
 901   "TARGET_64BIT
 902    && GET_CODE (operands[1]) == CONST_INT
 903    && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
 904    && !fp_operand (operands[0], VOIDmode)"
 905   "lghi\\t%0,%h1"
 906   [(set_attr "op_type" "RI")
 907    (set_attr "atype"   "reg")])
 908
 909 (define_insn "*movdi_lli"
 910   [(set (match_operand:DI 0 "register_operand" "=d")
 911         (match_operand:DI 1 "immediate_operand" "n"))]
 912   "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
 913    && !fp_operand (operands[0], VOIDmode)"
 914   "*
 915 {
 916   int part = s390_single_hi (operands[1], DImode, 0);
 917   operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
 918
 919   switch (part)
 920     {
 921       case 0: return \"llihh\\t%0,%x1\";
 922       case 1: return \"llihl\\t%0,%x1\";
 923       case 2: return \"llilh\\t%0,%x1\";
 924       case 3: return \"llill\\t%0,%x1\";
 925       default: abort ();
 926     }
 927 }"
 928   [(set_attr "op_type" "RI")
 929    (set_attr "atype"   "reg")])
 930
 931 (define_insn "*movdi_larl"
 932   [(set (match_operand:DI 0 "register_operand" "=d")
 933         (match_operand:DI 1 "larl_operand" "X"))]
 934   "TARGET_64BIT
 935    && !fp_operand (operands[0], VOIDmode)"
 936   "larl\\t%0,%1"
 937    [(set_attr "op_type" "RIL")
 938     (set_attr "atype"   "reg")
 939     (set_attr "type"    "la")])
 940
 941 (define_insn "*movdi_ss"
 942   [(set (match_operand:DI 0 "s_operand" "=Qo")
 943         (match_operand:DI 1 "s_imm_operand" "Qo"))]
 944   ""
 945   "mvc\\t%O0(8,%R0),%1"
 946   [(set_attr "op_type" "SS")
 947    (set_attr "atype"   "mem")])
 948
 949 (define_insn "*movdi_64"
 950   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,f,f,m")
 951         (match_operand:DI 1 "general_operand" "d,m,d,f,m,f"))]
 952   "TARGET_64BIT"
 953   "@
 954    lgr\\t%0,%1
 955    lg\\t%0,%1
 956    stg\\t%1,%0
 957    ldr\\t%0,%1
 958    ld\\t%0,%1
 959    std\\t%1,%0"
 960   [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX")
 961    (set_attr "atype"   "reg,mem,mem,reg,mem,mem")])
 962
 963 (define_insn "*movdi_31"
 964   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,f,f,m")
 965         (match_operand:DI 1 "general_operand" "Q,d,dKm,d,f,m,f"))]
 966   "!TARGET_64BIT"
 967   "@
 968    lm\\t%0,%N0,%1
 969    stm\\t%1,%N1,%0
 970    #
 971    #
 972    ldr\\t%0,%1
 973    ld\\t%0,%1
 974    std\\t%1,%0"
 975   [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX")
 976    (set_attr "atype"   "mem,mem,*,*,reg,mem,mem")])
 977
 978 (define_split
 979   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 980         (match_operand:DI 1 "general_operand" ""))]
 981   "!TARGET_64BIT && reload_completed
 982    && !fp_operand (operands[0], VOIDmode)
 983    && !fp_operand (operands[1], VOIDmode)
 984    && !s_operand (operands[0], VOIDmode)
 985    && !s_operand (operands[1], VOIDmode)
 986    && (register_operand (operands[0], VOIDmode)
 987        || register_operand (operands[1], VOIDmode))
 988    && (!register_operand (operands[0], VOIDmode)
 989        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
 990                                     operands[1])
 991        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
 992                                     operands[1]))"
 993   [(set (match_dup 2) (match_dup 4))
 994    (set (match_dup 3) (match_dup 5))]
 995   "
 996 {
 997   if (!register_operand (operands[0], VOIDmode)
 998       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
 999                                    operands[1]))
1000     {
1001       operands[2] = operand_subword (operands[0], 0, 0, DImode);
1002       operands[3] = operand_subword (operands[0], 1, 0, DImode);
1003       operands[4] = operand_subword (operands[1], 0, 0, DImode);
1004       operands[5] = operand_subword (operands[1], 1, 0, DImode);
1005     }
1006   else
1007     {
1008       operands[2] = operand_subword (operands[0], 1, 0, DImode);
1009       operands[3] = operand_subword (operands[0], 0, 0, DImode);
1010       operands[4] = operand_subword (operands[1], 1, 0, DImode);
1011       operands[5] = operand_subword (operands[1], 0, 0, DImode);
1012     }
1013 }")
1014
1015 (define_split
1016   [(set (match_operand:DI 0 "register_operand" "")
1017         (match_operand:DI 1 "memory_operand" ""))]
1018   "!TARGET_64BIT && reload_completed
1019    && !fp_operand (operands[0], VOIDmode)
1020    && !fp_operand (operands[1], VOIDmode)
1021    && !s_operand (operands[1], VOIDmode)"
1022   [(set (match_dup 2) (match_dup 3))
1023    (set (match_dup 0) (mem:DI (match_dup 2)))]
1024   "operands[2] = operand_subword (operands[0], 1, 0, DImode);
1025    operands[3] = XEXP (operands[1], 0);")
1026
1027 ;
1028 ; movsi instruction pattern(s).
1029 ;
1030
1031 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1032 ;; move to get the address of the symbolic object from the GOT.
1033
1034 (define_expand "movsi"
1035   [(set (match_operand:SI 0 "general_operand" "")
1036         (match_operand:SI 1 "general_operand" ""))]
1037   ""
1038   "
1039 {
1040   /* Handle PIC symbolic constants.  */
1041   if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1042     emit_pic_move (operands, SImode);
1043
1044   /* expr.c tries to load an effective address using
1045      force_reg.  This fails because we don't have a
1046      generic load_address pattern.  Convert the move
1047      to a proper arithmetic operation instead, unless
1048      it is guaranteed to be OK.  */
1049   if (GET_CODE (operands[1]) == PLUS
1050       && !legitimate_la_operand_p (operands[1]))
1051     {
1052       operands[1] = force_operand (operands[1], operands[0]);
1053       if (operands[1] == operands[0])
1054         DONE;
1055     }
1056
1057   /* During and after reload, we need to force constants
1058      to the literal pool ourselves, if necessary.  */
1059   if ((reload_in_progress || reload_completed)
1060       && CONSTANT_P (operands[1])
1061       && (!legitimate_reload_constant_p (operands[1])
1062           || fp_operand (operands[0], VOIDmode)))
1063     operands[1] = force_const_mem (SImode, operands[1]);
1064 }")
1065
1066 (define_insn "*movsi_lhi"
1067   [(set (match_operand:SI 0 "register_operand" "=d")
1068         (match_operand:SI 1 "immediate_operand" "K"))]
1069   "GET_CODE (operands[1]) == CONST_INT
1070    && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1071    && !fp_operand (operands[0], VOIDmode)"
1072   "lhi\\t%0,%h1"
1073   [(set_attr "op_type" "RI")])
1074
1075 (define_insn "*movsi_lli"
1076   [(set (match_operand:SI 0 "register_operand" "=d")
1077         (match_operand:SI 1 "immediate_operand" "n"))]
1078   "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1079    && !fp_operand (operands[0], VOIDmode)"
1080   "*
1081 {
1082   int part = s390_single_hi (operands[1], SImode, 0);
1083   operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1084
1085   switch (part)
1086     {
1087       case 0: return \"llilh\\t%0,%x1\";
1088       case 1: return \"llill\\t%0,%x1\";
1089       default: abort ();
1090     }
1091 }"
1092   [(set_attr "op_type" "RI")])
1093
1094 (define_insn "*movsi_ss"
1095   [(set (match_operand:SI 0 "s_operand" "=Qo")
1096         (match_operand:SI 1 "s_imm_operand" "Qo"))]
1097   ""
1098   "mvc\\t%O0(4,%R0),%1"
1099   [(set_attr "op_type" "SS")
1100    (set_attr "atype"   "mem")])
1101
1102 (define_insn "*movsi"
1103   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,f,f,m")
1104         (match_operand:SI 1 "general_operand" "d,m,d,f,m,f"))]
1105   ""
1106   "@
1107    lr\\t%0,%1
1108    l\\t%0,%1
1109    st\\t%1,%0
1110    ler\\t%0,%1
1111    le\\t%0,%1
1112    ste\\t%1,%0"
1113   [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1114    (set_attr "atype"   "reg,mem,mem,reg,mem,mem")])
1115
1116
1117 ;
1118 ; movhi instruction pattern(s).
1119 ;
1120
1121 (define_insn "movhi"
1122   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m")
1123         (match_operand:HI 1 "general_operand" "d,n,m,d"))]
1124   ""
1125   "@
1126    lr\\t%0,%1
1127    lhi\\t%0,%h1
1128    lh\\t%0,%1
1129    sth\\t%1,%0"
1130   [(set_attr "op_type" "RR,RI,RX,RX")
1131    (set_attr "atype"   "reg,reg,mem,mem")])
1132
1133
1134 ;
1135 ; movqi instruction pattern(s).
1136 ;
1137
1138 (define_insn "movqi_64"
1139   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1140         (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1141   "TARGET_64BIT"
1142   "@
1143    lr\\t%0,%1
1144    lhi\\t%0,%b1
1145    llgc\\t%0,%1
1146    stc\\t%1,%0
1147    mvi\\t%0,%b1"
1148   [(set_attr "op_type" "RR,RI,RXE,RX,SI")
1149    (set_attr "atype"   "reg,reg,mem,mem,mem")])
1150
1151
1152 (define_insn "movqi"
1153   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1154         (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1155   ""
1156   "@
1157    lr\\t%0,%1
1158    lhi\\t%0,%b1
1159    ic\\t%0,%1
1160    stc\\t%1,%0
1161    mvi\\t%0,%b1"
1162   [(set_attr "op_type" "RR,RI,RX,RX,SI")
1163    (set_attr "atype"   "reg,reg,mem,mem,mem")])
1164
1165
1166 ;
1167 ; moveqstrictqi instruction pattern(s).
1168 ;
1169
1170 (define_insn "*movstrictqi"
1171   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1172                          (match_operand:QI 1 "memory_operand" "m"))]
1173   ""
1174   "ic\\t%0,%1"
1175   [(set_attr "op_type"  "RX")
1176    (set_attr "atype"    "mem")])
1177
1178 ;
1179 ; movstricthi instruction pattern(s).
1180 ;
1181
1182 (define_insn "*movstricthi"
1183   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1184                          (match_operand:HI 1 "s_imm_operand" "Qo"))
1185    (clobber (reg:CC 33))]
1186   ""
1187   "icm\\t%0,3,%1"
1188   [(set_attr "op_type" "RS")
1189    (set_attr "atype"   "mem")])
1190
1191
1192 ;
1193 ; movstrictsi instruction pattern(s).
1194 ;
1195
1196 (define_insn "movestrictsi"
1197   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1198                          (match_operand:SI 1 "general_operand" "d,m"))]
1199   "TARGET_64BIT"
1200   "@
1201    lr\\t%0,%1
1202    l\\t%0,%1"
1203   [(set_attr "op_type" "RR,RS")
1204    (set_attr "atype"   "reg,mem")])
1205
1206
1207 ;
1208 ; movdf instruction pattern(s).
1209 ;
1210
1211 (define_expand "movdf"
1212   [(set (match_operand:DF 0 "nonimmediate_operand" "")
1213         (match_operand:DF 1 "general_operand"  ""))]
1214   ""
1215   "
1216 {
1217   /* During and after reload, we need to force constants
1218      to the literal pool ourselves, if necessary.  */
1219   if ((reload_in_progress || reload_completed)
1220       && CONSTANT_P (operands[1]))
1221     operands[1] = force_const_mem (DFmode, operands[1]);
1222 }")
1223
1224 (define_insn "*movdf_ss"
1225   [(set (match_operand:DF 0 "s_operand" "=Qo")
1226         (match_operand:DF 1 "s_imm_operand" "Qo"))]
1227   ""
1228   "mvc\\t%O0(8,%R0),%1"
1229   [(set_attr "op_type" "SS")
1230    (set_attr "atype"   "mem")])
1231
1232 (define_insn "*movdf_64"
1233   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1234         (match_operand:DF 1 "general_operand" "f,m,f,d,m,d"))]
1235   "TARGET_64BIT"
1236   "@
1237    ldr\\t%0,%1
1238    ld\\t%0,%1
1239    std\\t%1,%0
1240    lgr\\t%0,%1
1241    lg\\t%0,%1
1242    stg\\t%1,%0"
1243   [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE")
1244    (set_attr "atype"   "reg,mem,mem,reg,mem,mem")])
1245
1246 (define_insn "*movdf_31"
1247   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m")
1248         (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d"))]
1249   "!TARGET_64BIT"
1250   "@
1251    ldr\\t%0,%1
1252    ld\\t%0,%1
1253    std\\t%1,%0
1254    lm\\t%0,%N0,%1
1255    stm\\t%1,%N1,%0
1256    #
1257    #"
1258   [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN")
1259    (set_attr "atype"   "reg,mem,mem,mem,mem,*,*")])
1260
1261 (define_split
1262   [(set (match_operand:DF 0 "nonimmediate_operand" "")
1263         (match_operand:DF 1 "general_operand" ""))]
1264   "!TARGET_64BIT && reload_completed
1265    && !fp_operand (operands[0], VOIDmode)
1266    && !fp_operand (operands[1], VOIDmode)
1267    && !s_operand (operands[0], VOIDmode)
1268    && !s_operand (operands[1], VOIDmode)
1269    && (register_operand (operands[0], VOIDmode)
1270        || register_operand (operands[1], VOIDmode))
1271    && (!register_operand (operands[0], VOIDmode)
1272        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1273                                     operands[1])
1274        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1275                                     operands[1]))"
1276   [(set (match_dup 2) (match_dup 4))
1277    (set (match_dup 3) (match_dup 5))]
1278   "
1279 {
1280   if (!register_operand (operands[0], VOIDmode)
1281       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1282                                    operands[1]))
1283     {
1284       operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1285       operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1286       operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1287       operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1288     }
1289   else
1290     {
1291       operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1292       operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1293       operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1294       operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1295     }
1296 }")
1297
1298 (define_split
1299   [(set (match_operand:DF 0 "register_operand" "")
1300         (match_operand:DF 1 "memory_operand" ""))]
1301   "!TARGET_64BIT && reload_completed
1302    && !fp_operand (operands[0], VOIDmode)
1303    && !fp_operand (operands[1], VOIDmode)
1304    && !s_operand (operands[1], VOIDmode)"
1305   [(set (match_dup 2) (match_dup 3))
1306    (set (match_dup 0) (mem:DI (match_dup 2)))]
1307   "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1308    operands[3] = XEXP (operands[1], 0);")
1309
1310 ;
1311 ; movsf instruction pattern(s).
1312 ;
1313
1314 (define_expand "movsf"
1315   [(set (match_operand:SF 0 "nonimmediate_operand" "")
1316         (match_operand:SF 1 "general_operand"  ""))]
1317   ""
1318   "
1319 {
1320   /* During and after reload, we need to force constants
1321      to the literal pool ourselves, if necessary.  */
1322   if ((reload_in_progress || reload_completed)
1323       && CONSTANT_P (operands[1]))
1324     operands[1] = force_const_mem (SFmode, operands[1]);
1325 }")
1326
1327 (define_insn "*movsf_ss"
1328   [(set (match_operand:SF 0 "s_operand" "=Qo")
1329         (match_operand:SF 1 "s_imm_operand" "Qo"))]
1330   ""
1331   "mvc\\t%O0(4,%R0),%1"
1332   [(set_attr "op_type" "SS")
1333    (set_attr "atype"   "mem")])
1334
1335 (define_insn "*movsf"
1336   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1337         (match_operand:SF 1 "general_operand" "f,m,f,d,m,d"))]
1338   ""
1339   "@
1340    ler\\t%0,%1
1341    le\\t%0,%1
1342    ste\\t%1,%0
1343    lr\\t%0,%1
1344    l\\t%0,%1
1345    st\\t%1,%0"
1346   [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1347    (set_attr "atype"   "reg,mem,mem,reg,mem,mem")])
1348
1349 ;
1350 ; load_multiple pattern(s).
1351 ;
1352
1353 (define_expand "load_multiple"
1354   [(match_par_dup 3 [(set (match_operand 0 "" "")
1355                           (match_operand 1 "" ""))
1356                      (use (match_operand 2 "" ""))])]
1357   ""
1358   "
1359 {
1360   int regno;
1361   int count;
1362   rtx from;
1363   int i, off;
1364
1365   /* Support only loading a constant number of fixed-point registers from
1366      memory and only bother with this if more than two */
1367   if (GET_CODE (operands[2]) != CONST_INT
1368       || INTVAL (operands[2]) < 2
1369       || INTVAL (operands[2]) > 16
1370       || GET_CODE (operands[1]) != MEM
1371       || GET_CODE (operands[0]) != REG
1372       || REGNO (operands[0]) >= 16)
1373     FAIL;
1374
1375   count = INTVAL (operands[2]);
1376   regno = REGNO (operands[0]);
1377
1378   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1379   if (no_new_pseudos)
1380     {
1381       if (GET_CODE (XEXP (operands[1], 0)) == REG)
1382         {
1383           from = XEXP (operands[1], 0);
1384           off = 0;
1385         }
1386       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1387                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1388                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1389         {
1390           from = XEXP (XEXP (operands[1], 0), 0);
1391           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1392         }
1393       else
1394         FAIL;
1395
1396       if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1397         FAIL;
1398     }
1399   else
1400     {
1401       from = force_reg (Pmode, XEXP (operands[1], 0));
1402       off = 0;
1403     }
1404
1405   for (i = 0; i < count; i++)
1406     XVECEXP (operands[3], 0, i)
1407       = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1408                      change_address (operands[1], Pmode,
1409                                      plus_constant (from,
1410                                                     off + i * UNITS_PER_WORD)));
1411 }")
1412
1413 (define_insn "*load_multiple_di"
1414   [(match_parallel 0 "load_multiple_operation"
1415                    [(set (match_operand:DI 1 "register_operand" "=r")
1416                          (match_operand:DI 2 "s_operand" "oQ"))])]
1417   ""
1418   "*
1419 {
1420   int words = XVECLEN (operands[0], 0);
1421
1422   if (XVECLEN (operands[0], 0) == 1)
1423     return \"lg\\t%1,0(%2)\";
1424
1425   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1426     return \"lmg\\t%1,%0,%2\";
1427 }"
1428    [(set_attr "op_type" "RXE")
1429     (set_attr "atype"   "mem")
1430     (set_attr "type"    "lm")])
1431
1432 (define_insn "*load_multiple_si"
1433   [(match_parallel 0 "load_multiple_operation"
1434                    [(set (match_operand:SI 1 "register_operand" "=r")
1435                          (match_operand:SI 2 "s_operand" "oQ"))])]
1436   ""
1437   "*
1438 {
1439   int words = XVECLEN (operands[0], 0);
1440
1441   if (XVECLEN (operands[0], 0) == 1)
1442     return \"l\\t%1,0(%2)\";
1443
1444   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1445     return \"lm\\t%1,%0,%2\";
1446 }"
1447    [(set_attr "op_type" "RXE")
1448     (set_attr "atype"   "mem")
1449     (set_attr "type"    "lm")])
1450
1451 ;
1452 ; store multiple pattern(s).
1453 ;
1454
1455 (define_expand "store_multiple"
1456   [(match_par_dup 3 [(set (match_operand 0 "" "")
1457                           (match_operand 1 "" ""))
1458                      (use (match_operand 2 "" ""))])]
1459   ""
1460   "
1461 {
1462   int regno;
1463   int count;
1464   rtx to;
1465   int i, off;
1466
1467   /* Support only storing a constant number of fixed-point registers to
1468      memory and only bother with this if more than two.  */
1469   if (GET_CODE (operands[2]) != CONST_INT
1470       || INTVAL (operands[2]) < 2
1471       || INTVAL (operands[2]) > 16
1472       || GET_CODE (operands[0]) != MEM
1473       || GET_CODE (operands[1]) != REG
1474       || REGNO (operands[1]) >= 16)
1475     FAIL;
1476
1477   count = INTVAL (operands[2]);
1478   regno = REGNO (operands[1]);
1479
1480   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1481
1482   if (no_new_pseudos)
1483     {
1484       if (GET_CODE (XEXP (operands[0], 0)) == REG)
1485         {
1486           to = XEXP (operands[0], 0);
1487           off = 0;
1488         }
1489       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1490                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1491                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1492         {
1493           to = XEXP (XEXP (operands[0], 0), 0);
1494           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1495         }
1496       else
1497         FAIL;
1498
1499       if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1500         FAIL;
1501     }
1502   else
1503     {
1504       to = force_reg (Pmode, XEXP (operands[0], 0));
1505       off = 0;
1506     }
1507
1508   for (i = 0; i < count; i++)
1509     XVECEXP (operands[3], 0, i)
1510       = gen_rtx_SET (VOIDmode,
1511                      change_address (operands[0], Pmode,
1512                                      plus_constant (to,
1513                                                     off + i * UNITS_PER_WORD)),
1514                      gen_rtx_REG (Pmode, regno + i));
1515 }")
1516
1517 (define_insn "*store_multiple_di"
1518   [(match_parallel 0 "store_multiple_operation"
1519                    [(set (match_operand:DI 1 "s_operand" "=oQ")
1520                          (match_operand:DI 2 "register_operand" "r"))])]
1521   ""
1522   "*
1523 {
1524   int words = XVECLEN (operands[0], 0);
1525
1526   if (XVECLEN (operands[0], 0) == 1)
1527     return \"stg\\t%1,0(%2)\";
1528
1529   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1530     return \"stmg\\t%2,%0,%1\";
1531 }"
1532    [(set_attr "op_type" "RXE")
1533     (set_attr "atype"   "mem")
1534     (set_attr "type"    "stm")])
1535
1536
1537 (define_insn "*store_multiple_si"
1538   [(match_parallel 0 "store_multiple_operation"
1539                    [(set (match_operand:SI 1 "s_operand" "=oQ")
1540                          (match_operand:SI 2 "register_operand" "r"))])]
1541   ""
1542   "*
1543 {
1544   int words = XVECLEN (operands[0], 0);
1545
1546   if (XVECLEN (operands[0], 0) == 1)
1547     return \"st\\t%1,0(%2)\";
1548
1549   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1550     return \"stm\\t%2,%0,%1\";
1551 }"
1552    [(set_attr "op_type" "RXE")
1553     (set_attr "atype"   "mem")
1554     (set_attr "type"    "stm")])
1555
1556 ;;
1557 ;; String instructions.
1558 ;;
1559
1560 ;
1561 ; movstrdi instruction pattern(s).
1562 ;
1563
1564 (define_expand "movstrdi"
1565    [(set (match_operand:BLK 0 "general_operand" "")
1566          (match_operand:BLK 1 "general_operand" ""))
1567     (use (match_operand:DI 2 "general_operand" ""))
1568     (match_operand 3 "" "")]
1569     "TARGET_64BIT"
1570     "
1571 {
1572   rtx addr0, addr1;
1573
1574   addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1575   addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1576
1577   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1578     {
1579       operands[0] = change_address (operands[0], VOIDmode, addr0);
1580       operands[1] = change_address (operands[1], VOIDmode, addr1);
1581       operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1582
1583       emit_insn (gen_movstrsico (operands[0], operands[1], operands[2]));
1584       DONE;
1585     }
1586   else
1587     {
1588       if (TARGET_MVCLE)
1589         {
1590           /* implementation suggested by  Richard Henderson <rth@cygnus.com> */
1591           rtx reg0 = gen_reg_rtx (TImode);
1592           rtx reg1 = gen_reg_rtx (TImode);
1593           rtx len = operands[2];
1594
1595           if (! CONSTANT_P (len))
1596             len = force_reg (DImode, len);
1597
1598           /* Load up the address+length pairs.  */
1599
1600           emit_move_insn (gen_highpart (DImode, reg0), addr0);
1601           emit_move_insn (gen_lowpart (DImode, reg0), len);
1602
1603           emit_move_insn (gen_highpart (DImode, reg1), addr1);
1604           emit_move_insn (gen_lowpart (DImode, reg1), len);
1605
1606           /* MOVE */
1607           emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
1608           DONE;
1609         }
1610       else
1611         {
1612           rtx label = gen_label_rtx ();
1613           rtx reg0, reg1, len;
1614
1615           reg0 = gen_reg_rtx (DImode);
1616           reg1 = gen_reg_rtx (DImode);
1617           len = gen_reg_rtx (DImode);
1618
1619           emit_move_insn (len, operands[2]);
1620           emit_insn (gen_cmpdi (len, const0_rtx));
1621           emit_jump_insn (gen_beq (label));
1622           emit_move_insn (reg0, addr0);
1623           emit_move_insn (reg1, addr1);
1624           emit_insn (gen_adddi3 (len, len, constm1_rtx));
1625           emit_insn (gen_movstrdix_64 (reg0, reg1, reg0, reg1, len));
1626           emit_label (label);
1627           DONE;
1628        }
1629     }
1630 }")
1631
1632 ;
1633 ; movstrsi instruction pattern(s).
1634 ;
1635
1636 (define_expand "movstrsi"
1637    [(set (match_operand:BLK 0 "general_operand" "")
1638          (match_operand:BLK 1 "general_operand" ""))
1639     (use (match_operand:SI 2 "general_operand" ""))
1640     (match_operand 3 "" "")]
1641     ""
1642     "
1643 {
1644   rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1645   rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1646
1647   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1648     {
1649       operands[0] = change_address (operands[0], VOIDmode, addr0);
1650       operands[1] = change_address (operands[1], VOIDmode, addr1);
1651       operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1652
1653       emit_insn (gen_movstrsico (operands[0], operands[1], operands[2]));
1654       DONE;
1655     }
1656   else
1657     {
1658       if (TARGET_64BIT)
1659         FAIL;
1660
1661       if (TARGET_MVCLE)
1662         {
1663           /* implementation suggested by  Richard Henderson <rth@cygnus.com> */
1664           rtx reg0 = gen_reg_rtx (DImode);
1665           rtx reg1 = gen_reg_rtx (DImode);
1666           rtx len = operands[2];
1667
1668
1669           if (! CONSTANT_P (len))
1670             len = force_reg (SImode, len);
1671
1672           /* Load up the address+length pairs.  */
1673
1674           emit_move_insn (gen_highpart (SImode, reg0), addr0);
1675           emit_move_insn (gen_lowpart (SImode, reg0), len);
1676
1677           emit_move_insn (gen_highpart (SImode, reg1), addr1);
1678           emit_move_insn (gen_lowpart (SImode, reg1), len);
1679
1680           /* MOVE */
1681           emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
1682           DONE;
1683         }
1684       else
1685         {
1686           rtx label = gen_label_rtx ();
1687           rtx reg0, reg1, len;
1688
1689           reg0 = gen_reg_rtx (SImode);
1690           reg1 = gen_reg_rtx (SImode);
1691           len = gen_reg_rtx (SImode);
1692
1693           emit_move_insn (len, operands[2]);
1694           emit_insn (gen_cmpsi (len, const0_rtx));
1695           emit_jump_insn (gen_beq (label));
1696           emit_move_insn (reg0, addr0);
1697           emit_move_insn (reg1, addr1);
1698           emit_insn (gen_addsi3 (len, len, constm1_rtx));
1699           emit_insn (gen_movstrsix_31 (reg0, reg1, reg0, reg1, len));
1700           emit_label (label);
1701           DONE;
1702        }
1703     }
1704 }")
1705
1706 ; Move a block that is less than 256 bytes in length.
1707
1708 (define_insn "movstrsico"
1709   [(set (match_operand:BLK 0 "s_operand" "=oQ")
1710         (match_operand:BLK 1 "s_operand" "oQ"))
1711    (use (match_operand 2 "const_int_operand" "I"))]
1712   "((unsigned) INTVAL (operands[2]) < 256)"
1713   "mvc\\t%O0(%c2+1,%R0),%1"
1714   [(set_attr "op_type" "SS")
1715    (set_attr "atype" "mem")])
1716
1717 ; Move a block that is more than 256 bytes in lenght or length in register
1718
1719 (define_insn "movstrdix_64"
1720   [(clobber (match_operand:DI 0 "register_operand" "=a"))
1721    (clobber (match_operand:DI 1 "register_operand" "=a"))
1722    (set (mem:BLK (match_operand:DI 2 "register_operand" "0"))
1723         (mem:BLK (match_operand:DI 3 "register_operand" "1")))
1724    (use (match_operand:DI 4 "register_operand" "a"))
1725    (clobber (match_scratch:DI 5 "=&a"))
1726    (clobber (reg:CC 33))]
1727   ""
1728   "*
1729 {
1730   rtx xop[4];
1731   xop[0] = gen_label_rtx ();
1732   xop[1] = gen_label_rtx ();
1733   xop[2] = gen_label_rtx ();
1734   xop[3] = operands[5];
1735   output_asm_insn (\"srag\\t%5,%4,8\", operands);
1736   output_asm_insn (\"jz\\t%l1\", xop);
1737   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1738                              CODE_LABEL_NUMBER (xop[0]));
1739   output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1740   output_asm_insn (\"la\\t%0,256(%0)\", operands);
1741   output_asm_insn (\"la\\t%1,256(%1)\", operands);
1742   output_asm_insn (\"brct\\t%3,%l0\", xop);
1743   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1744                              CODE_LABEL_NUMBER (xop[1]));
1745   output_asm_insn (\"bras\\t%3,%l2\", xop);
1746   output_asm_insn (\"mvc\\t0(1,%0),0(%1)\", operands);
1747   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1748                              CODE_LABEL_NUMBER (xop[2]));
1749   return \"ex\\t%4,0(%5)\";
1750 }"
1751   [(set_attr "op_type" "NN")
1752    (set_attr "atype"   "mem")
1753    (set_attr "length" "44")])
1754
1755 (define_insn "movstrsix_31"
1756   [(clobber (match_operand:SI 0 "register_operand" "=a"))
1757    (clobber (match_operand:SI 1 "register_operand" "=a"))
1758    (set (mem:BLK (match_operand:SI 2 "register_operand" "0"))
1759         (mem:BLK (match_operand:SI 3 "register_operand" "1")))
1760    (use (match_operand:SI 4 "register_operand" "a"))
1761    (clobber (match_scratch:SI 5 "=&a"))
1762    (clobber (reg:CC 33))]
1763   ""
1764   "*
1765 {
1766   rtx xop[4];
1767   xop[0] = gen_label_rtx ();
1768   xop[1] = gen_label_rtx ();
1769   xop[2] = gen_label_rtx ();
1770   xop[3] = operands[5];
1771   output_asm_insn (\"lr\\t%5,%4\", operands);
1772   output_asm_insn (\"sra\\t%5,8\", operands);
1773   output_asm_insn (\"jz\\t%l1\", xop);
1774   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1775                              CODE_LABEL_NUMBER (xop[0]));
1776   output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1777   output_asm_insn (\"la\\t%0,256(%0)\", operands);
1778   output_asm_insn (\"la\\t%1,256(%1)\", operands);
1779   output_asm_insn (\"brct\\t%3,%l0\", xop);
1780   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1781                              CODE_LABEL_NUMBER (xop[1]));
1782   output_asm_insn (\"bras\\t%3,%l2\", xop);
1783   output_asm_insn (\"mvc\\t0(1,%0),0(%1)\", operands);
1784   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1785                              CODE_LABEL_NUMBER (xop[2]));
1786   return \"ex\\t%4,0(%5)\";
1787 }"
1788    [(set_attr "op_type" "NN")
1789     (set_attr "length" "42")
1790     (set_attr "atype" "mem")])
1791
1792 ; Move a block that is larger than 255 bytes in length.
1793
1794 (define_insn "movstrdi_64"
1795   [(clobber (match_operand:TI 0 "register_operand" "=d"))
1796    (clobber (match_operand:TI 1 "register_operand" "=d"))
1797    (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1798         (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1799    (clobber (reg:CC 33))]
1800   ""
1801   "mvcle\\t%0,%1,0\;jo\\t.-4"
1802   [(set_attr "op_type" "NN")
1803    (set_attr "atype"   "mem")
1804    (set_attr "length"  "8")])
1805
1806 (define_insn "movstrsi_31"
1807   [(clobber (match_operand:DI 0 "register_operand" "=d"))
1808    (clobber (match_operand:DI 1 "register_operand" "=d"))
1809    (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1810         (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1811    (clobber (reg:CC 33))]
1812   ""
1813   "mvcle\\t%0,%1,0\;jo\\t.-4"
1814    [(set_attr "op_type" "NN")
1815     (set_attr "atype" "mem")
1816     (set_attr "length"  "8")])
1817
1818 ;
1819 ; clrstrdi instruction pattern(s).
1820 ;
1821
1822 (define_expand "clrstrdi"
1823   [(set (match_operand:BLK 0 "general_operand" "")
1824         (const_int 0))
1825    (use (match_operand:DI 1 "general_operand" ""))
1826    (match_operand 2 "" "")]
1827   "TARGET_64BIT"
1828   "
1829 {
1830    rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1831
1832    operands[0] = change_address (operands[0], VOIDmode, addr);
1833
1834    if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1835      {
1836         emit_insn (gen_clrstrsico (operands[0], operands[1]));
1837         DONE;
1838      }
1839    else
1840      {
1841       rtx reg0 = gen_reg_rtx (TImode);
1842       rtx reg1 = gen_reg_rtx (TImode);
1843       rtx len = operands[1];
1844
1845       if (! CONSTANT_P (len))
1846           len = force_reg (DImode, len);
1847
1848       /* Load up the address+length pairs.  */
1849
1850       emit_move_insn (gen_highpart (DImode, reg0), addr);
1851       emit_move_insn (gen_lowpart (DImode, reg0), len);
1852
1853       emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
1854
1855       /* Clear! */
1856       emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0, reg1));
1857       DONE;
1858      }
1859 }")
1860
1861 ;
1862 ; clrstrsi instruction pattern(s).
1863 ;
1864
1865 (define_expand "clrstrsi"
1866   [(set (match_operand:BLK 0 "general_operand" "")
1867         (const_int 0))
1868    (use (match_operand:SI 1 "general_operand" ""))
1869    (match_operand 2 "" "")]
1870    "!TARGET_64BIT"
1871    "
1872 {
1873    rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1874
1875    operands[0] = change_address (operands[0], VOIDmode, addr);
1876
1877    if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1878      {
1879         emit_insn (gen_clrstrsico (operands[0], operands[1]));
1880         DONE;
1881      }
1882    else
1883      {
1884       rtx reg0 = gen_reg_rtx (DImode);
1885       rtx reg1 = gen_reg_rtx (DImode);
1886       rtx len = operands[1];
1887
1888       if (! CONSTANT_P (len))
1889           len = force_reg (SImode, len);
1890
1891       /* Load up the address+length pairs.  */
1892
1893       emit_move_insn (gen_highpart (SImode, reg0), addr);
1894       emit_move_insn (gen_lowpart (SImode, reg0), len);
1895
1896       emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
1897
1898       /* CLear! */
1899       emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0, reg1));
1900       DONE;
1901      }
1902 }")
1903
1904 ; Clear memory with length less than 256 bytes
1905
1906 (define_insn "clrstrsico"
1907   [(set (match_operand:BLK 0 "s_operand" "=Qo")
1908         (const_int 0))
1909    (use (match_operand 1 "immediate_operand" "I"))
1910    (clobber (reg:CC 33))]
1911   ""
1912   "xc\\t%O0(%1,%R0),%0"
1913   [(set_attr "op_type" "RS")
1914    (set_attr "type"    "cs")
1915    (set_attr "atype"   "mem")])
1916
1917 ; Clear memory with length greater 256 bytes or lenght not constant
1918
1919 (define_insn "clrstrsi_64"
1920   [(clobber (match_operand:TI 0 "register_operand" "=d"))
1921    (clobber (match_operand:TI 1 "register_operand" "=d"))
1922    (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1923         (const_int 0))
1924    (use (match_operand:TI 3 "register_operand" "1"))
1925    (clobber (reg:CC 33))]
1926   "TARGET_64BIT"
1927   "mvcle\\t%0,%1,0\;jo\\t.-4"
1928   [(set_attr "op_type" "NN")
1929    (set_attr "atype"   "mem")
1930    (set_attr "type"    "vs")
1931    (set_attr "length"  "8")])
1932
1933 (define_insn "clrstrsi_31"
1934   [(clobber (match_operand:DI 0 "register_operand" "=d"))
1935    (clobber (match_operand:DI 1 "register_operand" "=d"))
1936    (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1937         (const_int 0))
1938    (use (match_operand:DI 3 "register_operand" "1"))
1939    (clobber (reg:CC 33))]
1940   "!TARGET_64BIT"
1941   "mvcle\\t%0,%1,0\;jo\\t.-4"
1942   [(set_attr "op_type" "NN")
1943    (set_attr "atype"   "mem")
1944    (set_attr "type"    "vs")
1945    (set_attr "length"  "8")])
1946
1947 ;
1948 ; cmpstrdi instruction pattern(s).
1949 ;
1950
1951 (define_expand "cmpstrdi"
1952    [(set (match_operand:DI 0 "register_operand" "")
1953          (compare:DI (match_operand:BLK 1 "s_operand" "")
1954                   (match_operand:BLK 2 "s_operand" "") ) )
1955              (use (match_operand:DI 3  "general_operand" ""))
1956              (use (match_operand:DI 4  "" ""))]
1957    "TARGET_64BIT"
1958    "
1959 {
1960   rtx addr0, addr1;
1961
1962   /* for pre/post increment */
1963   operands[1] = protect_from_queue (operands[1], 0);
1964   operands[2] = protect_from_queue (operands[2], 0);
1965   operands[3] = protect_from_queue (operands[3], 0);
1966
1967   addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1968   addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1969
1970   if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1971     {
1972       if (INTVAL (operands[3]) == 0) {
1973         emit_move_insn (operands[0], operands[3]);
1974         DONE;
1975       }
1976
1977       operands[1] = change_address (operands[1], VOIDmode, addr0);
1978       operands[2] = change_address (operands[2], VOIDmode, addr1);
1979
1980       emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1981       emit_insn (gen_cmpint_di (operands[0]));
1982       DONE;
1983     }
1984   else
1985     {
1986       /* implementation suggested by  Richard Henderson <rth@cygnus.com> */
1987       rtx reg0 = gen_reg_rtx (TImode);
1988       rtx reg1 = gen_reg_rtx (TImode);
1989       rtx len = operands[3];
1990
1991       if (! CONSTANT_P (len))
1992           len = force_reg (DImode, len);
1993
1994       /* Load up the address+length pairs.  */
1995       emit_move_insn (gen_highpart (DImode, reg0), addr0);
1996       emit_move_insn (gen_lowpart (DImode, reg0), len);
1997
1998       emit_move_insn (gen_highpart (DImode, reg1), addr1);
1999       emit_move_insn (gen_lowpart (DImode, reg1), len);
2000
2001       /* Compare! */
2002       emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2003       emit_insn (gen_cmpint_di (operands[0]));
2004       DONE;
2005     }
2006 }")
2007
2008 ;
2009 ; cmpstrsi instruction pattern(s).
2010 ;
2011
2012 (define_expand "cmpstrsi"
2013    [(set (match_operand:SI 0 "register_operand" "")
2014          (compare:SI (match_operand:BLK 1 "s_operand" "")
2015                   (match_operand:BLK 2 "s_operand" "") ) )
2016              (use (match_operand:SI 3  "general_operand" ""))
2017              (use (match_operand:SI 4  "" ""))]
2018    ""
2019    "
2020 {
2021   rtx addr0, addr1;
2022
2023   /* for pre/post increment */
2024   operands[1] = protect_from_queue (operands[1], 0);
2025   operands[2] = protect_from_queue (operands[2], 0);
2026   operands[3] = protect_from_queue (operands[3], 0);
2027
2028   addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2029   addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2030
2031   if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2032     {
2033       if (INTVAL (operands[3]) == 0) {
2034         emit_move_insn (operands[0], operands[3]);
2035         DONE;
2036       }
2037
2038       operands[1] = change_address (operands[1], VOIDmode, addr0);
2039       operands[2] = change_address (operands[2], VOIDmode, addr1);
2040
2041       emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2042       emit_insn (gen_cmpint_si (operands[0]));
2043       DONE;
2044     }
2045   else
2046     {
2047       /* implementation suggested by  Richard Henderson <rth@cygnus.com> */
2048       rtx reg0, reg1;
2049       rtx len = operands[3];
2050
2051       if (TARGET_64BIT)
2052         {
2053           reg0 = gen_reg_rtx (TImode);
2054           reg1 = gen_reg_rtx (TImode);
2055         }
2056       else
2057         {
2058           reg0 = gen_reg_rtx (DImode);
2059           reg1 = gen_reg_rtx (DImode);
2060         }
2061
2062       if (! CONSTANT_P (len))
2063           len = force_reg (Pmode, len);
2064
2065       /* Load up the address+length pairs.  */
2066       emit_move_insn (gen_highpart (Pmode, reg0), addr0);
2067       emit_move_insn (gen_lowpart (Pmode, reg0), len);
2068
2069       emit_move_insn (gen_highpart (Pmode, reg1), addr1);
2070       emit_move_insn (gen_lowpart (Pmode, reg1), len);
2071
2072       /* Compare! */
2073       if (TARGET_64BIT)
2074           emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2075       else
2076           emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
2077
2078       emit_insn (gen_cmpint_si (operands[0]));
2079       DONE;
2080     }
2081 }")
2082
2083 ; Compare a block that is less than 256 bytes in length.
2084
2085 (define_insn "cmpstr_const"
2086   [(set (reg:CCS 33)
2087         (compare:CCS (match_operand:BLK 0 "s_operand" "oQ")
2088                      (match_operand:BLK 1 "s_operand" "oQ")))
2089    (use (match_operand 2 "immediate_operand" "I"))]
2090   "(unsigned) INTVAL (operands[2]) < 256"
2091   "clc\\t%O0(%c2,%R0),%1"
2092   [(set_attr "op_type" "SS")
2093    (set_attr "atype"   "mem")
2094    (set_attr "type"    "cs")])
2095
2096 ; Compare a block that is larger than 255 bytes in length.
2097
2098 (define_insn "cmpstr_64"
2099   [(clobber (match_operand:TI 0 "register_operand" "=d"))
2100    (clobber (match_operand:TI 1 "register_operand" "=d"))
2101    (set (reg:CCS 33)
2102         (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2103                      (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))]
2104   "TARGET_64BIT"
2105   "clcl\\t%0,%1"
2106   [(set_attr "op_type" "RR")
2107    (set_attr "atype"   "mem")
2108    (set_attr "type"    "vs")])
2109
2110 (define_insn "cmpstr_31"
2111   [(clobber (match_operand:DI 0 "register_operand" "=d"))
2112    (clobber (match_operand:DI 1 "register_operand" "=d"))
2113    (set (reg:CCS 33)
2114         (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2115                      (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))]
2116   "!TARGET_64BIT"
2117   "clcl\\t%0,%1"
2118   [(set_attr "op_type" "RR")
2119    (set_attr "atype"   "mem")
2120    (set_attr "type"    "vs")])
2121
2122 ; Convert condition code to integer in range (-1, 0, 1)
2123
2124 (define_insn "cmpint_si"
2125   [(set (match_operand:SI 0 "register_operand" "=d")
2126         (compare:SI (reg:CCS 33) (const_int 0)))]
2127   ""
2128   "*
2129 {
2130    output_asm_insn (\"lhi\\t%0,1\", operands);
2131    output_asm_insn (\"jh\\t.+12\", operands);
2132    output_asm_insn (\"jl\\t.+6\", operands);
2133    output_asm_insn (\"sr\\t%0,%0\", operands);
2134    return \"lcr\\t%0,%0\";
2135 }"
2136   [(set_attr "op_type" "NN")
2137    (set_attr "length"  "16")
2138    (set_attr "atype"   "reg")
2139    (set_attr "type"    "other")])
2140
2141 (define_insn "cmpint_di"
2142   [(set (match_operand:DI 0 "register_operand" "=d")
2143         (compare:DI (reg:CCS 33) (const_int 0)))]
2144   "TARGET_64BIT"
2145   "*
2146 {
2147    output_asm_insn (\"lghi\\t%0,1\", operands);
2148    output_asm_insn (\"jh\\t.+12\", operands);
2149    output_asm_insn (\"jl\\t.+6\", operands);
2150    output_asm_insn (\"sgr\\t%0,%0\", operands);
2151    return \"lcgr\\t%0,%0\";
2152 }"
2153   [(set_attr "op_type" "NN")
2154    (set_attr "length"  "22")
2155    (set_attr "atype"   "reg")
2156    (set_attr "type"    "other")])
2157
2158
2159 ;;
2160 ;;- Conversion instructions.
2161 ;;
2162
2163 (define_insn "*sethighqisi"
2164   [(set (match_operand:SI 0 "register_operand" "=d")
2165         (unspec:SI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2166    (clobber (reg:CC 33))]
2167   ""
2168   "icm\\t%0,8,%1"
2169   [(set_attr "op_type" "RS")
2170    (set_attr "atype"   "mem")])
2171
2172 (define_insn "*sethighhisi"
2173   [(set (match_operand:SI 0 "register_operand" "=d")
2174         (unspec:SI [(match_operand:HI 1 "s_operand" "Qo")] 10))
2175    (clobber (reg:CC 33))]
2176   ""
2177   "icm\\t%0,12,%1"
2178   [(set_attr "op_type" "RS")
2179    (set_attr "atype"   "mem")])
2180
2181 (define_insn "*sethighqidi_64"
2182   [(set (match_operand:DI 0 "register_operand" "=d")
2183         (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2184    (clobber (reg:CC 33))]
2185   "TARGET_64BIT"
2186   "icmh\\t%0,8,%1"
2187   [(set_attr "op_type" "RSE")
2188    (set_attr "atype"   "mem")])
2189
2190 (define_insn "*sethighqidi_31"
2191   [(set (match_operand:DI 0 "register_operand" "=d")
2192         (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2193    (clobber (reg:CC 33))]
2194   "!TARGET_64BIT"
2195   "icm\\t%0,8,%1"
2196   [(set_attr "op_type" "RS")
2197    (set_attr "atype"   "mem")])
2198
2199 (define_split
2200   [(set (match_operand:SI 0 "register_operand" "")
2201         (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2202                          (match_operand 2 "const_int_operand" "")
2203                          (const_int 0)))]
2204   "!TARGET_64BIT && !reload_completed
2205    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2206   [(parallel
2207     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2208      (clobber (reg:CC 33))])
2209     (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2210   "
2211 {
2212   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2213   operands[1] = change_address (operands[1], QImode, 0);
2214 }")
2215
2216 (define_split
2217   [(set (match_operand:SI 0 "register_operand" "")
2218         (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2219                          (match_operand 2 "const_int_operand" "")
2220                          (const_int 0)))]
2221   "!TARGET_64BIT && !reload_completed
2222    && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2223   [(parallel
2224     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2225      (clobber (reg:CC 33))])
2226     (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2227   "
2228 {
2229   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2230   operands[1] = change_address (operands[1], HImode, 0);
2231 }")
2232
2233 ;
2234 ; extendsidi2 instruction pattern(s).
2235 ;
2236
2237 (define_expand "extendsidi2"
2238   [(set (match_operand:DI 0 "register_operand" "")
2239         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2240   ""
2241   "
2242 {
2243   if (!TARGET_64BIT)
2244     {
2245       rtx insns, subword;
2246
2247       operands[1] = force_reg (SImode, operands[1]);
2248       subword = operand_subword (operands[0], 0, 1, DImode);
2249
2250       start_sequence ();
2251       emit_move_insn (subword, operands[1]);
2252       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2253       insns = get_insns ();
2254       end_sequence ();
2255
2256       emit_no_conflict_block (insns, operands[0], operands[1], 0,
2257                               gen_rtx_SIGN_EXTEND (DImode, operands[1]));
2258
2259       /* Avoid having the REG_RETVAL destroyed by someone attaching
2260          other REG_EQUAL notes.  */
2261       emit_move_insn (operands[0], operands[0]);
2262       DONE;
2263     }
2264 }
2265 ")
2266
2267 (define_insn "*extendsidi2"
2268   [(set (match_operand:DI 0 "register_operand" "=d,d")
2269         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2270   "TARGET_64BIT"
2271   "@
2272    lgfr\\t%0,%1
2273    lgf\\t%0,%1"
2274   [(set_attr "op_type" "RRE,RXE")
2275    (set_attr "atype"   "reg,mem")])
2276
2277 ;
2278 ; extendhidi2 instruction pattern(s).
2279 ;
2280
2281 (define_expand "extendhidi2"
2282   [(set (match_operand:DI 0 "register_operand" "")
2283         (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2284   ""
2285   "
2286 {
2287   if (!TARGET_64BIT)
2288     {
2289       rtx tmp = gen_reg_rtx (SImode);
2290       emit_insn (gen_extendhisi2 (tmp, operands[1]));
2291       emit_insn (gen_extendsidi2 (operands[0], tmp));
2292       DONE;
2293     }
2294   else
2295     {
2296       operands[1] = gen_lowpart (DImode, operands[1]);
2297       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2298       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2299       DONE;
2300     }
2301 }
2302 ")
2303
2304 (define_insn "*extendhidi2"
2305   [(set (match_operand:DI 0 "register_operand" "=d")
2306         (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2307   "TARGET_64BIT"
2308   "lgh\\t%0,%1"
2309   [(set_attr "op_type" "RXE")
2310    (set_attr "atype"   "mem")])
2311
2312 ;
2313 ; extendqidi2 instruction pattern(s).
2314 ;
2315
2316 (define_expand "extendqidi2"
2317   [(set (match_operand:DI 0 "register_operand" "")
2318         (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2319   ""
2320   "
2321 {
2322   if (!TARGET_64BIT)
2323     {
2324       rtx tmp = gen_reg_rtx (SImode);
2325       emit_insn (gen_extendqisi2 (tmp, operands[1]));
2326       emit_insn (gen_extendsidi2 (operands[0], tmp));
2327       DONE;
2328     }
2329   else
2330     {
2331       operands[1] = gen_lowpart (DImode, operands[1]);
2332       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2333       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2334       DONE;
2335     }
2336 }
2337 ")
2338
2339 (define_split
2340   [(set (match_operand:DI 0 "register_operand" "")
2341         (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2342   "TARGET_64BIT && !reload_completed"
2343   [(parallel
2344     [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2345      (clobber (reg:CC 33))])
2346    (parallel
2347     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2348      (clobber (reg:CC 33))])]
2349   "")
2350
2351 ;
2352 ; extendhisi2 instruction pattern(s).
2353 ;
2354
2355 (define_expand "extendhisi2"
2356   [(set (match_operand:SI 0 "register_operand" "")
2357         (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2358   ""
2359   "
2360 {
2361   operands[1] = gen_lowpart (SImode, operands[1]);
2362   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2363   emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2364   DONE;
2365 }
2366 ")
2367
2368 (define_insn "*extendhisi2"
2369   [(set (match_operand:SI 0 "register_operand" "=d")
2370         (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2371   ""
2372   "lh\\t%0,%1"
2373   [(set_attr "op_type" "RX")
2374    (set_attr "atype"   "mem")])
2375
2376 ;
2377 ; extendqisi2 instruction pattern(s).
2378 ;
2379
2380 (define_expand "extendqisi2"
2381   [(set (match_operand:SI 0 "register_operand" "")
2382         (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2383   ""
2384   "
2385 {
2386   operands[1] = gen_lowpart (SImode, operands[1]);
2387   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2388   emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2389   DONE;
2390 }
2391 ")
2392
2393 (define_split
2394   [(set (match_operand:SI 0 "register_operand" "")
2395         (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2396   "!reload_completed"
2397   [(parallel
2398     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2399      (clobber (reg:CC 33))])
2400    (parallel
2401     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2402      (clobber (reg:CC 33))])]
2403   "")
2404
2405 ;
2406 ; extendqihi2 instruction pattern(s).
2407 ;
2408
2409
2410 ;
2411 ; zero_extendsidi2 instruction pattern(s).
2412 ;
2413
2414 (define_expand "zero_extendsidi2"
2415   [(set (match_operand:DI 0 "register_operand" "")
2416         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2417   ""
2418   "
2419 {
2420   if (!TARGET_64BIT)
2421     {
2422       rtx insns, subword;
2423
2424       operands[1] = force_reg (SImode, operands[1]);
2425       subword = operand_subword (operands[0], 0, 1, DImode);
2426
2427       start_sequence ();
2428       emit_move_insn (subword, operands[1]);
2429       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (32)));
2430       insns = get_insns ();
2431       end_sequence ();
2432
2433       emit_no_conflict_block (insns, operands[0], operands[1], 0,
2434                               gen_rtx_ZERO_EXTEND (DImode, operands[1]));
2435
2436       /* Avoid having the REG_RETVAL destroyed by someone attaching
2437          other REG_EQUAL notes.  */
2438       emit_move_insn (operands[0], operands[0]);
2439       DONE;
2440     }
2441 }
2442 ")
2443
2444 (define_insn "*zero_extendsidi2"
2445   [(set (match_operand:DI 0 "register_operand" "=d,d")
2446         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2447   "TARGET_64BIT"
2448   "@
2449    llgfr\\t%0,%1
2450    llgf\\t%0,%1"
2451   [(set_attr "op_type" "RRE,RXE")
2452    (set_attr "atype"   "reg,mem")])
2453
2454 ;
2455 ; zero_extendhidi2 instruction pattern(s).
2456 ;
2457
2458 (define_expand "zero_extendhidi2"
2459   [(set (match_operand:DI 0 "register_operand" "")
2460         (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2461   ""
2462   "
2463 {
2464   if (!TARGET_64BIT)
2465     {
2466       rtx tmp = gen_reg_rtx (SImode);
2467       emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2468       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2469       DONE;
2470     }
2471   else
2472     {
2473       operands[1] = gen_lowpart (DImode, operands[1]);
2474       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2475       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2476       DONE;
2477     }
2478 }
2479 ")
2480
2481 (define_insn "*zero_extendhidi2"
2482   [(set (match_operand:DI 0 "register_operand" "=d")
2483         (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2484   "TARGET_64BIT"
2485   "llgh\\t%0,%1"
2486   [(set_attr "op_type" "RXE")
2487    (set_attr "atype"   "mem")])
2488
2489 ;
2490 ; zero_extendqidi2 instruction pattern(s)
2491 ;
2492
2493 (define_expand "zero_extendqidi2"
2494   [(set (match_operand:DI 0 "register_operand" "")
2495         (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2496   ""
2497   "
2498 {
2499   if (!TARGET_64BIT)
2500     {
2501       rtx tmp = gen_reg_rtx (SImode);
2502       emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2503       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2504       DONE;
2505     }
2506   else
2507     {
2508       operands[1] = gen_lowpart (DImode, operands[1]);
2509       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2510       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2511       DONE;
2512     }
2513 }
2514 ")
2515
2516 (define_insn "*zero_extendqidi2"
2517   [(set (match_operand:DI 0 "register_operand" "=d")
2518         (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2519   "TARGET_64BIT"
2520   "llgc\\t%0,%1"
2521   [(set_attr "op_type" "RXE")
2522    (set_attr "atype"   "mem")])
2523
2524 ;
2525 ; zero_extendhisi2 instruction pattern(s).
2526 ;
2527
2528 (define_expand "zero_extendhisi2"
2529   [(set (match_operand:SI 0 "register_operand" "")
2530         (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2531   ""
2532   "
2533 {
2534   operands[1] = gen_lowpart (SImode, operands[1]);
2535   emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2536   DONE;
2537 }
2538 ")
2539
2540 (define_insn "*zero_extendhisi2_64"
2541   [(set (match_operand:SI 0 "register_operand" "=d")
2542         (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2543   "TARGET_64BIT"
2544   "llgh\\t%0,%1"
2545   [(set_attr "op_type" "RXE")
2546    (set_attr "atype"   "mem")])
2547
2548 ;
2549 ; zero_extendqisi2 instruction pattern(s).
2550 ;
2551
2552 (define_expand "zero_extendqisi2"
2553   [(set (match_operand:SI 0 "register_operand" "")
2554         (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2555   ""
2556   "
2557 {
2558   operands[1] = gen_lowpart (SImode, operands[1]);
2559   emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2560   DONE;
2561 }
2562 ")
2563
2564 (define_insn "*zero_extendqisi2_64"
2565   [(set (match_operand:SI 0 "register_operand" "=d")
2566         (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2567   "TARGET_64BIT"
2568   "llgc\\t%0,%1"
2569   [(set_attr "op_type" "RXE")
2570    (set_attr "atype"   "mem")])
2571
2572 ;
2573 ; zero_extendqihi2 instruction pattern(s).
2574 ;
2575
2576 (define_expand "zero_extendqihi2"
2577   [(set (match_operand:HI 0 "register_operand" "")
2578         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2579   "TARGET_64BIT"
2580   "
2581 {
2582   operands[1] = gen_lowpart (HImode, operands[1]);
2583   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2584   DONE;
2585 }
2586 ")
2587
2588 (define_insn "*zero_extendqihi2_64"
2589   [(set (match_operand:HI 0 "register_operand" "=d")
2590         (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2591    (clobber (reg:CC 33))]
2592   "TARGET_64BIT"
2593   "llgc\\t%0,%1"
2594   [(set_attr "op_type" "RXE")
2595    (set_attr "atype"   "mem")])
2596
2597 ;
2598 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2599 ;
2600
2601 (define_expand "fixuns_truncdfdi2"
2602   [(set (match_operand:DI 0 "register_operand" "")
2603         (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2604   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2605   "
2606 {
2607   rtx label1 = gen_label_rtx ();
2608   rtx label2 = gen_label_rtx ();
2609   rtx temp = gen_reg_rtx (DFmode);
2610   operands[1] = force_reg (DFmode, operands[1]);
2611
2612   emit_insn (gen_cmpdf (operands[1],
2613         CONST_DOUBLE_FROM_REAL_VALUE (
2614           REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2615   emit_jump_insn (gen_blt (label1));
2616   emit_insn (gen_subdf3 (temp, operands[1],
2617         CONST_DOUBLE_FROM_REAL_VALUE (
2618           REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2619   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2620   emit_jump (label2);
2621
2622   emit_label (label1);
2623   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2624   emit_label (label2);
2625   DONE;
2626 }")
2627
2628 (define_expand "fix_truncdfdi2"
2629   [(set (match_operand:DI 0 "register_operand" "")
2630         (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2631   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2632   "
2633 {
2634   operands[1] = force_reg (DFmode, operands[1]);
2635   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2636   DONE;
2637 }")
2638
2639 (define_insn "fix_truncdfdi2_ieee"
2640   [(set (match_operand:DI 0 "register_operand" "=d")
2641         (fix:DI (match_operand:DF 1 "register_operand" "f")))
2642    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2643    (clobber (reg:CC 33))]
2644   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2645   "cgdbr\\t%0,%h2,%1"
2646   [(set_attr "op_type" "RRE")
2647    (set_attr "type"    "other")])
2648
2649 ;
2650 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2651 ;
2652
2653 (define_expand "fixuns_truncdfsi2"
2654   [(set (match_operand:SI 0 "register_operand" "")
2655         (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2656   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2657   "
2658 {
2659   rtx label1 = gen_label_rtx ();
2660   rtx label2 = gen_label_rtx ();
2661   rtx temp = gen_reg_rtx (DFmode);
2662
2663   operands[1] = force_reg (DFmode,operands[1]);
2664   emit_insn (gen_cmpdf (operands[1],
2665         CONST_DOUBLE_FROM_REAL_VALUE (
2666           REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2667   emit_jump_insn (gen_blt (label1));
2668   emit_insn (gen_subdf3 (temp, operands[1],
2669         CONST_DOUBLE_FROM_REAL_VALUE (
2670           REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2671   emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2672   emit_jump (label2);
2673
2674   emit_label (label1);
2675   emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2676   emit_label (label2);
2677   DONE;
2678 }")
2679
2680 (define_expand "fix_truncdfsi2"
2681   [(set (match_operand:SI 0 "register_operand" "")
2682         (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2683   "TARGET_HARD_FLOAT"
2684   "
2685 {
2686   if (TARGET_IBM_FLOAT)
2687     {
2688       /* This is the algorithm from POP chapter A.5.7.2.  */
2689
2690       rtx temp   = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2691       rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2692       rtx two32  = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2693
2694       operands[1] = force_reg (DFmode, operands[1]);
2695       emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2696                                          two31r, two32, temp));
2697     }
2698   else
2699     {
2700       operands[1] = force_reg (DFmode, operands[1]);
2701       emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2702     }
2703
2704   DONE;
2705 }")
2706
2707 (define_insn "fix_truncdfsi2_ieee"
2708   [(set (match_operand:SI 0 "register_operand" "=d")
2709         (fix:SI (match_operand:DF 1 "register_operand" "f")))
2710     (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2711     (clobber (reg:CC 33))]
2712   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2713   "cfdbr\\t%0,%h2,%1"
2714    [(set_attr "op_type" "RRE")
2715     (set_attr "type"    "other" )])
2716
2717 (define_insn "fix_truncdfsi2_ibm"
2718   [(set (match_operand:SI 0 "register_operand" "=d")
2719         (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2720    (use (match_operand:DI 2 "immediate_operand" "m"))
2721    (use (match_operand:DI 3 "immediate_operand" "m"))
2722    (use (match_operand:BLK 4 "memory_operand" "m"))
2723    (clobber (reg:CC 33))]
2724   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2725   "*
2726 {
2727    output_asm_insn (\"sd\\t%1,%2\", operands);
2728    output_asm_insn (\"aw\\t%1,%3\", operands);
2729    output_asm_insn (\"std\\t%1,%4\", operands);
2730    output_asm_insn (\"xi\\t%N4,128\", operands);
2731    return \"l\\t%0,%N4\";
2732 }"
2733   [(set_attr "op_type" "NN")
2734    (set_attr "type"    "other")
2735    (set_attr "length"  "20")])
2736
2737 ;
2738 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2739 ;
2740
2741 (define_expand "fixuns_truncsfdi2"
2742   [(set (match_operand:DI 0 "register_operand" "")
2743         (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2744   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2745   "
2746 {
2747   rtx label1 = gen_label_rtx ();
2748   rtx label2 = gen_label_rtx ();
2749   rtx temp = gen_reg_rtx (SFmode);
2750
2751   operands[1] = force_reg (SFmode, operands[1]);
2752   emit_insn (gen_cmpsf (operands[1],
2753         CONST_DOUBLE_FROM_REAL_VALUE (
2754           REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2755   emit_jump_insn (gen_blt (label1));
2756
2757   emit_insn (gen_subsf3 (temp, operands[1],
2758         CONST_DOUBLE_FROM_REAL_VALUE (
2759           REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2760   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2761   emit_jump (label2);
2762
2763   emit_label (label1);
2764   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2765   emit_label (label2);
2766   DONE;
2767 }")
2768
2769 (define_expand "fix_truncsfdi2"
2770   [(set (match_operand:DI 0 "register_operand" "")
2771         (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2772   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2773   "
2774 {
2775   operands[1] = force_reg (SFmode, operands[1]);
2776   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2777   DONE;
2778 }")
2779
2780 (define_insn "fix_truncsfdi2_ieee"
2781   [(set (match_operand:DI 0 "register_operand" "=d")
2782         (fix:DI (match_operand:SF 1 "register_operand"  "f")))
2783    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2784    (clobber (reg:CC 33))]
2785   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2786   "cgebr\\t%0,%h2,%1"
2787   [(set_attr "op_type" "RRE")
2788    (set_attr "type"    "other")])
2789
2790 ;
2791 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2792 ;
2793
2794 (define_expand "fixuns_truncsfsi2"
2795   [(set (match_operand:SI 0 "register_operand" "")
2796         (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2797   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2798   "
2799 {
2800   rtx label1 = gen_label_rtx ();
2801   rtx label2 = gen_label_rtx ();
2802   rtx temp = gen_reg_rtx (SFmode);
2803
2804   operands[1] = force_reg (SFmode, operands[1]);
2805   emit_insn (gen_cmpsf (operands[1],
2806         CONST_DOUBLE_FROM_REAL_VALUE (
2807           REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2808   emit_jump_insn (gen_blt (label1));
2809   emit_insn (gen_subsf3 (temp, operands[1],
2810         CONST_DOUBLE_FROM_REAL_VALUE (
2811           REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2812   emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2813   emit_jump (label2);
2814
2815   emit_label (label1);
2816   emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2817   emit_label (label2);
2818   DONE;
2819 }")
2820
2821 (define_expand "fix_truncsfsi2"
2822   [(set (match_operand:SI 0 "register_operand" "")
2823         (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2824   "TARGET_HARD_FLOAT"
2825   "
2826 {
2827   if (TARGET_IBM_FLOAT)
2828     {
2829       /* Convert to DFmode and then use the POP algorithm.  */
2830       rtx temp = gen_reg_rtx (DFmode);
2831       emit_insn (gen_extendsfdf2 (temp, operands[1]));
2832       emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2833     }
2834   else
2835     {
2836       operands[1] = force_reg (SFmode, operands[1]);
2837       emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2838     }
2839
2840   DONE;
2841 }")
2842
2843 (define_insn "fix_truncsfsi2_ieee"
2844   [(set (match_operand:SI 0 "register_operand" "=d")
2845         (fix:SI (match_operand:SF 1 "register_operand" "f")))
2846     (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2847     (clobber (reg:CC 33))]
2848   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2849   "cfebr\\t%0,%h2,%1"
2850   [(set_attr "op_type" "RRE")
2851    (set_attr "type"    "other")])
2852
2853 ;
2854 ; floatdidf2 instruction pattern(s).
2855 ;
2856
2857 (define_insn "floatdidf2"
2858   [(set (match_operand:DF 0 "register_operand" "=f")
2859         (float:DF (match_operand:DI 1 "register_operand" "d")))
2860    (clobber (reg:CC 33))]
2861   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2862   "cdgbr\\t%0,%1"
2863   [(set_attr "op_type" "RRE")
2864    (set_attr "type"    "other" )])
2865
2866 ;
2867 ; floatdisf2 instruction pattern(s).
2868 ;
2869
2870 (define_insn "floatdisf2"
2871   [(set (match_operand:SF 0 "register_operand" "=f")
2872         (float:SF (match_operand:DI 1 "register_operand" "d")))
2873    (clobber (reg:CC 33))]
2874   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2875   "cegbr\\t%0,%1"
2876   [(set_attr "op_type" "RRE")
2877    (set_attr "type"    "other" )])
2878
2879 ;
2880 ; floatsidf2 instruction pattern(s).
2881 ;
2882
2883 (define_expand "floatsidf2"
2884   [(parallel
2885     [(set (match_operand:DF 0 "register_operand" "")
2886           (float:DF (match_operand:SI 1 "register_operand" "")))
2887      (clobber (reg:CC 33))])]
2888   "TARGET_HARD_FLOAT"
2889   "
2890 {
2891   if (TARGET_IBM_FLOAT)
2892     {
2893       /* This is the algorithm from POP chapter A.5.7.1.  */
2894
2895       rtx temp  = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2896       rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2897
2898       emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2899       DONE;
2900     }
2901 }")
2902
2903 (define_insn "floatsidf2_ieee"
2904   [(set (match_operand:DF 0 "register_operand" "=f")
2905         (float:DF (match_operand:SI 1 "register_operand"  "d")))
2906    (clobber (reg:CC 33))]
2907   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2908   "cdfbr\\t%0,%1"
2909   [(set_attr "op_type" "RRE")
2910    (set_attr "type"   "other" )])
2911
2912 (define_insn "floatsidf2_ibm"
2913   [(set (match_operand:DF 0 "register_operand" "=f")
2914         (float:DF (match_operand:SI 1 "register_operand" "d")))
2915    (use (match_operand:DI 2 "immediate_operand" "m"))
2916    (use (match_operand:BLK 3 "memory_operand" "m"))
2917    (clobber (reg:CC 33))]
2918   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2919   "*
2920 {
2921    output_asm_insn (\"st\\t%1,%N3\", operands);
2922    output_asm_insn (\"xi\\t%N3,128\", operands);
2923    output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2924    output_asm_insn (\"ld\\t%0,%3\", operands);
2925    return \"sd\\t%0,%2\";
2926 }"
2927   [(set_attr "op_type" "NN")
2928    (set_attr "type"    "other" )
2929    (set_attr "length"  "20")])
2930
2931 ;
2932 ; floatsisf2 instruction pattern(s).
2933 ;
2934
2935 (define_expand "floatsisf2"
2936   [(parallel
2937     [(set (match_operand:SF 0 "register_operand" "")
2938           (float:SF (match_operand:SI 1 "register_operand" "")))
2939      (clobber (reg:CC 33))])]
2940   "TARGET_HARD_FLOAT"
2941   "
2942 {
2943   if (TARGET_IBM_FLOAT)
2944     {
2945       /* Use the POP algorithm to convert to DFmode and then truncate.  */
2946       rtx temp = gen_reg_rtx (DFmode);
2947       emit_insn (gen_floatsidf2 (temp, operands[1]));
2948       emit_insn (gen_truncdfsf2 (operands[0], temp));
2949       DONE;
2950     }
2951 }")
2952
2953 (define_insn "floatsisf2_ieee"
2954   [(set (match_operand:SF 0 "register_operand" "=f")
2955         (float:SF (match_operand:SI 1 "register_operand" "d")))
2956    (clobber (reg:CC 33))]
2957   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2958   "cefbr\\t%0,%1"
2959   [(set_attr "op_type" "RRE")
2960    (set_attr "type"    "other" )])
2961
2962 ;
2963 ; truncdfsf2 instruction pattern(s).
2964 ;
2965
2966 (define_expand "truncdfsf2"
2967   [(set (match_operand:SF 0 "register_operand" "")
2968         (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2969   "TARGET_HARD_FLOAT"
2970   "")
2971
2972 (define_insn "truncdfsf2_ieee"
2973   [(set (match_operand:SF 0 "register_operand" "=f")
2974         (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2975   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2976   "ledbr\\t%0,%1"
2977   [(set_attr "op_type"  "RR")])
2978
2979 (define_insn "truncdfsf2_ibm"
2980   [(set (match_operand:SF 0 "register_operand" "=f,f")
2981         (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2982   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2983   "@
2984    lrer\\t%0,%1
2985    le\\t%0,%1"
2986   [(set_attr "op_type"  "RR,RX")
2987    (set_attr "atype"    "reg,mem")])
2988
2989 ;
2990 ; extendsfdf2 instruction pattern(s).
2991 ;
2992
2993 (define_expand "extendsfdf2"
2994   [(set (match_operand:DF 0 "register_operand" "")
2995         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2996   "TARGET_HARD_FLOAT"
2997   "
2998 {
2999   if (TARGET_IBM_FLOAT)
3000     {
3001       emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3002       DONE;
3003     }
3004 }")
3005
3006 (define_insn "extendsfdf2_ieee"
3007   [(set (match_operand:DF 0 "register_operand" "=f,f")
3008         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,m")))]
3009   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3010   "@
3011    ldebr\\t%0,%1
3012    ldeb\\t%0,%1"
3013   [(set_attr "op_type"  "RRE,RXE")])
3014
3015 (define_insn "extendsfdf2_ibm"
3016   [(set (match_operand:DF 0 "register_operand" "=f,f")
3017         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
3018    (clobber (reg:CC 33))]
3019   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3020   "@
3021    sdr\\t%0,%0\;ler\\t%0,%1
3022    sdr\\t%0,%0\;le\\t%0,%1"
3023   [(set_attr "op_type"  "RRE,RXE")
3024    (set_attr "atype"    "reg,mem")
3025    (set_attr "type"     "o2,o2")])
3026
3027
3028 ;;
3029 ;; ARITHMETRIC OPERATIONS
3030 ;;
3031 ;  arithmetric operations set the ConditionCode,
3032 ;  because of unpredictable Bits in Register for Halfword and Byte
3033 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
3034
3035 ;;
3036 ;;- Add instructions.
3037 ;;
3038
3039 ;
3040 ; adddi3 instruction pattern(s).
3041 ;
3042
3043 (define_insn "addaddr_esame"
3044   [(set (match_operand:DI 0 "register_operand" "=a,a")
3045         (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
3046                  (match_operand:DI 2 "nonmemory_operand" "J,a")))]
3047   "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3048      (REGNO (operands[1]) == BASE_REGISTER)) &&
3049         (GET_CODE (operands[2]) == REG ||
3050          CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3051   "@
3052    la\\t%0,%c2(,%1)
3053    la\\t%0,0(%1,%2)"
3054   [(set_attr "op_type" "RX")
3055    (set_attr "atype"   "mem")
3056    (set_attr "type"    "la")])
3057
3058 (define_insn "adddi3_64"
3059   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3060         (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3061                  (match_operand:DI 2 "general_operand" "d,K,m") ) )
3062    (clobber (reg:CC 33))]
3063   "TARGET_64BIT"
3064   "@
3065    agr\\t%0,%2
3066    aghi\\t%0,%h2
3067    ag\\t%0,%2"
3068   [(set_attr "op_type"  "RRE,RI,RXE")
3069    (set_attr "atype"    "reg,reg,mem")])
3070
3071 ;
3072 ; For weakness of reload, need (set (reg x) (plus (reg y) (reg x)))
3073 ;
3074
3075 (define_insn "adddi3_inv_64"
3076   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3077         (plus:DI (match_operand:DI 1 "general_operand" "%d,K,m")
3078                  (match_operand:DI 2 "register_operand" "0,0,0") ) )
3079    (clobber (reg:CC 33))]
3080   "TARGET_64BIT"
3081   "@
3082    agr\\t%0,%1
3083    aghi\\t%0,%h1
3084    ag\\t%0,%1"
3085   [(set_attr "op_type" "RRE,RI,RXE")
3086    (set_attr "atype"   "reg,reg,mem")])
3087
3088 (define_insn "adddi3_31"
3089   [(set (match_operand:DI 0 "register_operand" "=d,d")
3090         (plus:DI (match_operand:DI 1 "register_operand" "0,0")
3091                  (match_operand:DI 2 "general_operand" "d,m") ) )
3092    (clobber (reg:CC 33))]
3093   "!TARGET_64BIT"
3094   "*
3095 {
3096    switch (which_alternative)
3097      {
3098      case 0: /* d <- d */
3099        output_asm_insn (\"ar\\t%0,%2\", operands);
3100        output_asm_insn (\"alr\\t%N0,%N2\", operands);
3101        break;
3102
3103      case 1: /* d <- m */
3104        output_asm_insn (\"a\\t%0,%2\", operands);
3105        output_asm_insn (\"al\\t%N0,%N2\", operands);
3106        break;
3107
3108      default:
3109        abort ();
3110      }
3111
3112    output_asm_insn (\"brc\\t12,.+8\", operands);
3113    return \"ahi\\t%0,1\";
3114 }"
3115   [(set_attr "op_type" "NN,NN")
3116    (set_attr "atype"   "reg,mem")
3117    (set_attr "type"    "o2,o2")
3118    (set_attr "length"  "12,16")])
3119
3120 (define_expand "adddi3"
3121   [(set (match_operand:DI 0 "register_operand" "")
3122         (plus:DI (match_operand:DI 1 "register_operand" "")
3123                  (match_operand:DI 2 "general_operand" "")))]
3124   ""
3125   "
3126 {
3127   if (TARGET_64BIT)
3128     emit_insn(gen_adddi3_64 (operands[0],operands[1],operands[2]));
3129   else
3130     emit_insn(gen_adddi3_31 (operands[0],operands[1],operands[2]));
3131   DONE;
3132 }")
3133
3134 (define_insn "reload_load_address"
3135   [(set (match_operand:DI 0 "register_operand" "=a")
3136         (match_operand:QI 1 "address_operand" "p"))]
3137   "TARGET_64BIT"
3138   "la\\t%0,%a1"
3139   [(set_attr "op_type" "RX")
3140    (set_attr "atype"   "mem")
3141    (set_attr "type"    "la")])
3142
3143 (define_insn "*reload_load_address_reg_0"
3144   [(set (match_operand:DI 0 "register_operand" "=d")
3145         (plus:DI (match_operand:DI 1 "register_operand" "%0")
3146                  (match_operand:DI 2 "register_operand" "d")))]
3147   "TARGET_64BIT"
3148   "brxlg\\t%0,%2,.+6"
3149   [(set_attr "op_type" "RIE")
3150    (set_attr "atype"   "reg")])
3151
3152 (define_insn "*reload_la_64"
3153   [(set (match_operand:DI 0 "register_operand" "=d")
3154         (plus:DI (match_operand:DI 1 "general_operand" "g")
3155                  (match_operand:DI 2 "general_operand" "g")))]
3156   "TARGET_64BIT && reload_in_progress"
3157   "#")
3158
3159 (define_split
3160   [(set (match_operand:DI 0 "register_operand" "")
3161         (plus:DI (match_operand:DI 1 "general_operand" "")
3162                  (match_operand:DI 2 "register_operand" "")))]
3163   "TARGET_64BIT && reload_completed
3164    && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
3165    && !rtx_equal_p (operands[0], operands[1])
3166    && !rtx_equal_p (operands[0], operands[2])"
3167   [(set (match_dup 0) (match_dup 1))
3168    (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3169   "
3170 {
3171   if (CONSTANT_P (operands[1])
3172       && !legitimate_reload_constant_p (operands[1]))
3173     operands[1] = force_const_mem (DImode, operands[1]);
3174 }")
3175
3176
3177 (define_split
3178   [(set (match_operand:DI 0 "register_operand" "")
3179         (plus:DI (match_operand:DI 1 "register_operand" "")
3180                  (match_operand:DI 2 "general_operand" "")))]
3181   "TARGET_64BIT && reload_completed
3182    && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
3183    && !rtx_equal_p (operands[0], operands[1])
3184    && !rtx_equal_p (operands[0], operands[2])"
3185   [(set (match_dup 0) (match_dup 2))
3186    (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))]
3187   "
3188 {
3189   if (CONSTANT_P (operands[2])
3190       && !legitimate_reload_constant_p (operands[2]))
3191     operands[2] = force_const_mem (DImode, operands[2]);
3192 }")
3193
3194 ;
3195 ; addsi3 instruction pattern(s).
3196 ;
3197
3198 (define_insn "*la_ccclobber"
3199   [(set (match_operand:SI 0 "register_operand" "=a")
3200         (match_operand:QI 1 "address_operand"  "p"))
3201    (clobber (reg:CC 33))]
3202   "legitimate_la_operand_p (operands[1])"
3203   "la\\t%0,%a1"
3204    [(set_attr "op_type"  "RX")
3205     (set_attr "atype"    "mem")
3206     (set_attr "type"     "la")])
3207
3208 (define_insn "*addaddr_ccclobber"
3209   [(set (match_operand:SI 0 "register_operand" "=d,d")
3210         (plus:SI (match_operand:SI 1 "register_operand" "%a,a")
3211                  (match_operand:SI 2 "nonmemory_operand" "J,a")))
3212    (clobber (reg:CC 33))]
3213   "(((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3214      (REGNO (operands[1]) == FRAME_POINTER_REGNUM ) ||
3215      (REGNO (operands[1]) == BASE_REGISTER)) &&
3216         (GET_CODE (operands[2]) == REG ||
3217          CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3218   "@
3219    la\\t%0,%c2(,%1)
3220    la\\t%0,0(%1,%2)"
3221   [(set_attr "op_type"  "RX")
3222    (set_attr "atype"    "mem")
3223    (set_attr "type"     "la")])
3224
3225 (define_insn "*addsi3_cc"
3226   [(set (reg 33)
3227         (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3228                           (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3229                  (const_int 0)))
3230    (set (match_operand:SI 0 "register_operand" "=d,d")
3231         (plus:SI (match_dup 1) (match_dup 2)))]
3232   "s390_match_ccmode(insn, CCLmode)"
3233   "@
3234    alr\\t%0,%2
3235    al\\t%0,%2"
3236   [(set_attr "op_type"  "RR,RX")
3237    (set_attr "atype"    "reg,mem")])
3238
3239 (define_insn "*addsi3_cconly"
3240   [(set (reg 33)
3241         (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3242                           (match_operand:SI 2 "general_operand" "d,m"))
3243                  (const_int 0)))
3244    (clobber (match_scratch:SI 0 "=d,d"))]
3245   "s390_match_ccmode(insn, CCLmode)"
3246   "@
3247    alr\\t%0,%2
3248    al\\t%0,%2"
3249   [(set_attr "op_type"  "RR,RX")
3250    (set_attr "atype"    "reg,mem")])
3251
3252 (define_insn "*addsi3_cconly2"
3253   [(set (reg 33)
3254         (compare (match_operand:SI 1 "register_operand" "%0,0")
3255                  (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3256    (clobber (match_scratch:SI 0 "=d,d"))]
3257   "s390_match_ccmode(insn, CCLmode)"
3258   "@
3259    alr\\t%0,%2
3260    al\\t%0,%2"
3261   [(set_attr "op_type"  "RR,RX")
3262    (set_attr "atype"    "reg,mem")])
3263
3264 (define_insn "addsi3"
3265   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3266         (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3267                  (match_operand:SI 2 "general_operand" "d,K,m")))
3268    (clobber (reg:CC 33))]
3269   ""
3270   "@
3271    ar\\t%0,%2
3272    ahi\\t%0,%h2
3273    a\\t%0,%2"
3274   [(set_attr "op_type"  "RR,RI,RX")
3275    (set_attr "atype"    "reg,reg,mem")])
3276
3277 (define_insn "*la"
3278   [(set (match_operand:SI 0 "register_operand" "=a")
3279         (match_operand:QI 1 "address_operand" "p"))]
3280   "reload_in_progress || reload_completed
3281    || legitimate_la_operand_p (operands[1])"
3282   "la\\t%0,%a1"
3283   [(set_attr "op_type"  "RX")
3284    (set_attr "atype"    "mem")
3285    (set_attr "type"     "la")])
3286
3287 (define_insn "*do_la_reg_0"
3288   [(set (match_operand:SI 0 "register_operand" "=d")
3289         (plus:SI (match_operand:SI 1 "register_operand" "%0")
3290                  (match_operand:SI 2 "register_operand" "d")))]
3291   "reload_in_progress || reload_completed"
3292   "brxle\\t%0,%2,.+4"
3293   [(set_attr "op_type" "RSI")
3294    (set_attr "atype"   "reg")])
3295
3296 (define_insn "*reload_la_31"
3297   [(set (match_operand:SI 0 "register_operand" "=d")
3298         (plus:SI (match_operand:SI 1 "general_operand" "g")
3299                  (match_operand:SI 2 "general_operand" "g")))]
3300   "reload_in_progress"
3301   "#")
3302
3303 (define_split
3304   [(set (match_operand:SI 0 "register_operand" "")
3305         (plus:SI (match_operand:SI 1 "general_operand" "")
3306                  (match_operand:SI 2 "register_operand" "")))]
3307   "reload_completed
3308    && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3309    && !rtx_equal_p (operands[0], operands[1])
3310    && !rtx_equal_p (operands[0], operands[2])"
3311   [(set (match_dup 0) (match_dup 1))
3312    (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3313   "
3314 {
3315   if (CONSTANT_P (operands[1])
3316       && !legitimate_reload_constant_p (operands[1]))
3317     operands[1] = force_const_mem (SImode, operands[1]);
3318 }")
3319
3320 (define_split
3321   [(set (match_operand:SI 0 "register_operand" "")
3322         (plus:SI (match_operand:SI 1 "register_operand" "")
3323                  (match_operand:SI 2 "general_operand" "")))]
3324   "reload_completed
3325    && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3326    && !rtx_equal_p (operands[0], operands[1])
3327    && !rtx_equal_p (operands[0], operands[2])"
3328   [(set (match_dup 0) (match_dup 2))
3329    (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
3330   "
3331 {
3332   if (CONSTANT_P (operands[2])
3333       && !legitimate_reload_constant_p (operands[2]))
3334     operands[2] = force_const_mem (SImode, operands[2]);
3335 }")
3336
3337
3338 ;
3339 ; addhi3 instruction pattern(s).
3340 ;
3341
3342 (define_insn "addhi3"
3343   [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3344         (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
3345                  (match_operand:HI 2 "general_operand" "d,K,m")))
3346    (clobber (reg:CC 33))]
3347   ""
3348   "@
3349    ar\\t%0,%2
3350    ahi\\t%0,%h2
3351    ah\\t%0,%2"
3352   [(set_attr "op_type"  "RR,RI,RX")
3353    (set_attr "atype"    "reg,reg,mem")])
3354
3355
3356 ;
3357 ; addqi3 instruction pattern(s).
3358 ;
3359
3360 (define_insn "addqi3"
3361   [(set (match_operand:QI 0 "register_operand" "=d,d")
3362         (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
3363                  (match_operand:QI 2 "general_operand" "a,n")))
3364    (clobber (reg:CC 33))]
3365   ""
3366   "@
3367    ar\\t%0,%2
3368    ahi\\t%0,%h2"
3369   [(set_attr "op_type"  "RX,RX")
3370    (set_attr "atype"    "reg,mem")])
3371
3372
3373 ;
3374 ; adddf3 instruction pattern(s).
3375 ;
3376
3377 (define_expand "adddf3"
3378   [(parallel
3379     [(set (match_operand:DF 0 "register_operand" "=f,f")
3380           (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3381                    (match_operand:DF 2 "general_operand" "f,m")))
3382      (clobber (reg:CC 33))])]
3383   "TARGET_HARD_FLOAT"
3384   "")
3385
3386 (define_insn "*adddf3"
3387   [(set (match_operand:DF 0 "register_operand" "=f,f")
3388         (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3389                  (match_operand:DF 2 "general_operand" "f,m")))
3390    (clobber (reg:CC 33))]
3391   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3392   "@
3393    adbr\\t%0,%2
3394    adb\\t%0,%2"
3395   [(set_attr "op_type"  "RR,RX")
3396    (set_attr "atype"    "reg,mem")])
3397
3398 (define_insn "*adddf3_ibm"
3399   [(set (match_operand:DF 0 "register_operand" "=f,f")
3400         (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3401                  (match_operand:DF 2 "general_operand" "f,m")))
3402    (clobber (reg:CC 33))]
3403   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3404   "@
3405    adr\\t%0,%2
3406    ad\\t%0,%2"
3407   [(set_attr "op_type"  "RR,RX")
3408    (set_attr "atype"    "reg,mem")])
3409
3410 ;
3411 ; addsf3 instruction pattern(s).
3412 ;
3413
3414 (define_expand "addsf3"
3415   [(parallel
3416     [(set (match_operand:SF 0 "register_operand" "=f,f")
3417           (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3418                    (match_operand:SF 2 "general_operand" "f,m")))
3419      (clobber (reg:CC 33))])]
3420   "TARGET_HARD_FLOAT"
3421   "")
3422
3423 (define_insn "*addsf3"
3424   [(set (match_operand:SF 0 "register_operand" "=f,f")
3425         (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3426                  (match_operand:SF 2 "general_operand" "f,m")))
3427    (clobber (reg:CC 33))]
3428   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3429   "@
3430    aebr\\t%0,%2
3431    aeb\\t%0,%2"
3432   [(set_attr "op_type"  "RR,RX")
3433    (set_attr "atype"    "reg,mem")])
3434
3435 (define_insn "*addsf3"
3436   [(set (match_operand:SF 0 "register_operand" "=f,f")
3437         (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3438                  (match_operand:SF 2 "general_operand" "f,m")))
3439    (clobber (reg:CC 33))]
3440   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3441   "@
3442    aer\\t%0,%2
3443    ae\\t%0,%2"
3444   [(set_attr "op_type"  "RR,RX")
3445    (set_attr "atype"    "reg,mem")])
3446
3447
3448 ;;
3449 ;;- Subtract instructions.
3450 ;;
3451
3452 ;
3453 ; subdi3 instruction pattern(s).
3454 ;
3455
3456 (define_insn "*subdi3_64"
3457   [(set (match_operand:DI 0 "register_operand" "=d,d")
3458         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3459                   (match_operand:DI 2 "general_operand" "d,m") ) )
3460    (clobber (reg:CC 33))]
3461   "TARGET_64BIT"
3462   "@
3463    sgr\\t%0,%2
3464    sg\\t%0,%2"
3465   [(set_attr "op_type"  "RRE,RRE")
3466    (set_attr "atype"    "reg,mem")])
3467
3468 (define_insn "subdi3"
3469   [(set (match_operand:DI 0 "register_operand" "=d,d")
3470         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3471                   (match_operand:DI 2 "general_operand" "d,m")))
3472    (clobber (reg:CC 33))]
3473   ""
3474   "*
3475 {
3476    switch (which_alternative)
3477      {
3478      case 0: /* d <- d */
3479        output_asm_insn (\"sr\\t%0,%2\", operands);
3480        output_asm_insn (\"slr\\t%N0,%N2\", operands);
3481        break;
3482      case 1: /* d <- m */
3483        output_asm_insn (\"s\\t%0,%2\", operands);
3484        output_asm_insn (\"sl\\t%N0,%N2\", operands);
3485        break;
3486
3487      default:
3488        abort ();
3489      }
3490
3491    output_asm_insn (\"brc\\t11,.+8\", operands);
3492    return \"ahi\\t%0,-1\";
3493 }"
3494   [(set_attr "op_type"  "NN,NN")
3495    (set_attr "atype"    "reg,mem")
3496    (set_attr "type"     "other,other")
3497    (set_attr "length"   "12,16")])
3498
3499 ;
3500 ; subsi3 instruction pattern(s).
3501 ;
3502
3503 (define_insn "*subsi3_cc"
3504   [(set (reg 33)
3505         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3506                            (match_operand:SI 2 "general_operand" "d,m"))
3507                  (const_int 0)))
3508    (set (match_operand:SI 0 "register_operand" "=d,d")
3509         (minus:SI (match_dup 1) (match_dup 2)))]
3510   "s390_match_ccmode(insn, CCLmode)"
3511   "@
3512    slr\\t%0,%2
3513    sl\\t%0,%2"
3514   [(set_attr "op_type"  "RR,RX")
3515    (set_attr "atype"    "reg,mem")])
3516
3517 (define_insn "*subsi3_cconly"
3518   [(set (reg 33)
3519         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3520                            (match_operand:SI 2 "general_operand" "d,m"))
3521                  (const_int 0)))
3522    (clobber (match_scratch:SI 0 "=d,d"))]
3523   "s390_match_ccmode(insn, CCLmode)"
3524   "@
3525    slr\\t%0,%2
3526    sl\\t%0,%2"
3527   [(set_attr "op_type"  "RR,RX")
3528    (set_attr "atype"    "reg,mem")])
3529
3530 (define_insn "subsi3"
3531   [(set (match_operand:SI 0 "register_operand" "=d,d")
3532         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3533                   (match_operand:SI 2 "general_operand" "d,m")))
3534    (clobber (reg:CC 33))]
3535   ""
3536   "@
3537    sr\\t%0,%2
3538    s\\t%0,%2"
3539   [(set_attr "op_type"  "RR,RX")
3540    (set_attr "atype"    "reg,mem")])
3541
3542 ;
3543 ; subhi3 instruction pattern(s).
3544 ;
3545
3546 (define_insn "subhi3"
3547   [(set (match_operand:HI 0 "register_operand" "=d,d")
3548         (minus:HI (match_operand:HI 1 "register_operand" "0,0")
3549                   (match_operand:HI 2 "general_operand" "d,m")))
3550    (clobber (reg:CC 33))]
3551   ""
3552   "@
3553    sr\\t%0,%2
3554    sh\\t%0,%2"
3555   [(set_attr "op_type"  "RR,RX")
3556    (set_attr "atype"    "reg,mem")])
3557
3558 ;
3559 ; subqi3 instruction pattern(s).
3560 ;
3561
3562 (define_insn "subqi3"
3563   [(set (match_operand:QI 0 "register_operand" "=d")
3564         (minus:QI (match_operand:QI 1 "register_operand" "0")
3565                   (match_operand:QI 2 "register_operand" "d")))
3566    (clobber (reg:CC 33))]
3567   ""
3568   "sr\\t%0,%2"
3569    [(set_attr "op_type"  "RR")])
3570
3571 ;
3572 ; subdf3 instruction pattern(s).
3573 ;
3574
3575 (define_expand "subdf3"
3576   [(parallel
3577     [(set (match_operand:DF 0 "register_operand" "=f,f")
3578           (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3579                     (match_operand:DF 2 "general_operand" "f,m")))
3580      (clobber (reg:CC 33))])]
3581   "TARGET_HARD_FLOAT"
3582   "")
3583
3584 (define_insn "*subdf3"
3585   [(set (match_operand:DF 0 "register_operand" "=f,f")
3586         (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3587                   (match_operand:DF 2 "general_operand" "f,m")))
3588    (clobber (reg:CC 33))]
3589   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3590   "@
3591    sdbr\\t%0,%2
3592    sdb\\t%0,%2"
3593   [(set_attr "op_type"  "RR,RX")
3594    (set_attr "atype"    "reg,mem")])
3595
3596 (define_insn "*subdf3_ibm"
3597   [(set (match_operand:DF 0 "register_operand" "=f,f")
3598         (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3599                   (match_operand:DF 2 "general_operand" "f,m")))
3600    (clobber (reg:CC 33))]
3601   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3602   "@
3603    sdr\\t%0,%2
3604    sd\\t%0,%2"
3605   [(set_attr "op_type"  "RR,RX")
3606    (set_attr "atype"    "reg,mem")])
3607
3608 ;
3609 ; subsf3 instruction pattern(s).
3610 ;
3611
3612 (define_expand "subsf3"
3613   [(parallel
3614     [(set (match_operand:SF 0 "register_operand" "=f,f")
3615           (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3616                     (match_operand:SF 2 "general_operand" "f,m")))
3617      (clobber (reg:CC 33))])]
3618   "TARGET_HARD_FLOAT"
3619   "")
3620
3621 (define_insn "*subsf3"
3622   [(set (match_operand:SF 0 "register_operand" "=f,f")
3623         (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3624                   (match_operand:SF 2 "general_operand" "f,m")))
3625    (clobber (reg:CC 33))]
3626   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3627   "@
3628    sebr\\t%0,%2
3629    seb\\t%0,%2"
3630   [(set_attr "op_type"  "RR,RX")
3631    (set_attr "atype"    "reg,mem")])
3632
3633 (define_insn "*subsf3_ibm"
3634   [(set (match_operand:SF 0 "register_operand" "=f,f")
3635         (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3636                   (match_operand:SF 2 "general_operand" "f,m")))
3637    (clobber (reg:CC 33))]
3638   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3639   "@
3640    ser\\t%0,%2
3641    se\\t%0,%2"
3642   [(set_attr "op_type"  "RR,RX")
3643    (set_attr "atype"    "reg,mem")])
3644
3645
3646 ;;
3647 ;;- Multiply instructions.
3648 ;;
3649
3650 ;
3651 ; muldi3 instruction pattern(s).
3652 ;
3653
3654 (define_insn "muldi3"
3655   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3656         (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3657                  (match_operand:DI 2 "general_operand" "d,K,m")))
3658    (clobber (reg:CC 33))]
3659   "TARGET_64BIT"
3660   "@
3661    msgr\\t%0,%2
3662    mghi\\t%0,%h2
3663    msg\\t%0,%2"
3664   [(set_attr "op_type"  "RRE,RI,RX")
3665    (set_attr "atype"    "reg,reg,mem")
3666    (set_attr "type"     "imul")])
3667
3668 ;
3669 ; mulsi3 instruction pattern(s).
3670 ;
3671
3672 (define_insn "mulsi3"
3673   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3674         (mult:SI  (match_operand:SI 1 "register_operand" "%0,0,0")
3675                   (match_operand:SI 2 "general_operand" "d,K,m")))
3676    (clobber (reg:CC 33))]
3677   ""
3678   "@
3679    msr\\t%0,%2
3680    mhi\\t%0,%h2
3681    ms\\t%0,%2"
3682   [(set_attr "op_type"  "RRE,RI,RX")
3683    (set_attr "atype"    "reg,reg,mem")
3684    (set_attr "type"     "imul")])
3685
3686 ;
3687 ; mulsidi3 instruction pattern(s).
3688 ;
3689
3690 (define_expand "mulsidi3"
3691   [(set (match_operand:DI 0 "register_operand" "")
3692         (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3693                  (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3694   "!TARGET_64BIT"
3695   "
3696 {
3697   rtx insn;
3698
3699   emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
3700   emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3701   insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3702
3703   REG_NOTES (insn) =
3704         gen_rtx_EXPR_LIST (REG_EQUAL,
3705                            gen_rtx_MULT (DImode,
3706                                 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3707                                 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3708                            REG_NOTES (insn));
3709   DONE;
3710 }")
3711
3712 (define_insn "mulsi_6432"
3713    [(set (match_operand:DI 0 "register_operand" "=d,d")
3714          (mult:DI (sign_extend:DI
3715                     (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3716                   (sign_extend:DI
3717                     (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3718     (clobber (reg:CC 33))]
3719    "!TARGET_64BIT"
3720    "@
3721     mr\\t%0,%2
3722     m\\t%0,%2"
3723   [(set_attr "op_type"  "RR,RX")
3724    (set_attr "atype"    "reg,mem")
3725    (set_attr "type"     "imul")])
3726
3727 ;
3728 ; muldf3 instruction pattern(s).
3729 ;
3730
3731 (define_expand "muldf3"
3732   [(parallel
3733     [(set (match_operand:DF 0 "register_operand" "=f,f")
3734           (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3735                    (match_operand:DF 2 "general_operand" "f,m")))
3736      (clobber (reg:CC 33))])]
3737   "TARGET_HARD_FLOAT"
3738   "")
3739
3740 (define_insn "*muldf3"
3741   [(set (match_operand:DF 0 "register_operand" "=f,f")
3742         (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3743                  (match_operand:DF 2 "general_operand" "f,m")))
3744    (clobber (reg:CC 33))]
3745   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3746   "@
3747    mdbr\\t%0,%2
3748    mdb\\t%0,%2"
3749   [(set_attr "op_type"  "RR,RX")
3750    (set_attr "type"     "fmul")
3751    (set_attr "atype"    "reg,mem")])
3752
3753 (define_insn "*muldf3_ibm"
3754   [(set (match_operand:DF 0 "register_operand" "=f,f")
3755         (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3756                  (match_operand:DF 2 "general_operand" "f,m")))
3757    (clobber (reg:CC 33))]
3758   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3759   "@
3760    mdr\\t%0,%2
3761    md\\t%0,%2"
3762   [(set_attr "op_type"  "RR,RX")
3763    (set_attr "type"    "fmul")
3764    (set_attr "atype"    "reg,mem")])
3765
3766 ;
3767 ; mulsf3 instruction pattern(s).
3768 ;
3769
3770 (define_expand "mulsf3"
3771   [(parallel
3772     [(set (match_operand:SF 0 "register_operand" "=f,f")
3773           (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3774                    (match_operand:SF 2 "general_operand" "f,m")))
3775      (clobber (reg:CC 33))])]
3776   "TARGET_HARD_FLOAT"
3777   "")
3778
3779 (define_insn "*mulsf3"
3780   [(set (match_operand:SF 0 "register_operand" "=f,f")
3781         (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3782                  (match_operand:SF 2 "general_operand" "f,m")))
3783    (clobber (reg:CC 33))]
3784   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3785   "@
3786    meebr\\t%0,%2
3787    meeb\\t%0,%2"
3788   [(set_attr "op_type"  "RR,RX")
3789    (set_attr "type"     "fmul")
3790    (set_attr "atype"    "reg,mem")])
3791
3792 (define_insn "*mulsf3_ibm"
3793   [(set (match_operand:SF 0 "register_operand" "=f,f")
3794         (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3795                  (match_operand:SF 2 "general_operand" "f,m")))
3796    (clobber (reg:CC 33))]
3797   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3798   "@
3799    mer\\t%0,%2
3800    me\\t%0,%2"
3801   [(set_attr "op_type"  "RR,RX")
3802    (set_attr "type"     "fmul")
3803    (set_attr "atype"    "reg,mem")])
3804
3805
3806 ;;
3807 ;;- Divide and modulo instructions.
3808 ;;
3809
3810 ;
3811 ; divmoddi4 instruction pattern(s).
3812 ;
3813
3814 (define_expand "divmoddi4"
3815   [(parallel [(set (match_operand:DI 0 "general_operand" "")
3816                    (div:DI (match_operand:DI 1 "general_operand" "")
3817                            (match_operand:DI 2 "general_operand" "")))
3818               (set (match_operand:DI 3 "general_operand" "")
3819                    (mod:DI (match_dup 1) (match_dup 2)))])
3820    (clobber (match_dup 4))]
3821   "TARGET_64BIT"
3822   "
3823 {
3824   rtx insn, div_equal, mod_equal, equal;
3825
3826   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3827   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3828   equal = gen_rtx_IOR (TImode,
3829                        gen_rtx_ZERO_EXTEND (TImode, div_equal),
3830                        gen_rtx_ASHIFT (TImode,
3831                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3832                                        GEN_INT (64)));
3833
3834   operands[4] = gen_reg_rtx(TImode);
3835   emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3836   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3837   insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3838   REG_NOTES (insn) =
3839         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3840
3841   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3842   REG_NOTES (insn) =
3843         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3844
3845   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3846   REG_NOTES (insn) =
3847         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3848
3849   DONE;
3850 }")
3851
3852 (define_insn "divmodtidi3"
3853   [(set (match_operand:TI 0 "register_operand" "=d,d")
3854         (ior:TI
3855           (zero_extend:TI
3856             (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3857                     (match_operand:DI 2 "general_operand" "d,m")))
3858           (ashift:TI
3859             (zero_extend:TI
3860               (mod:DI (truncate:DI (match_dup 1))
3861                       (match_dup 2)))
3862             (const_int 64))))]
3863   "TARGET_64BIT"
3864   "@
3865    dsgr\\t%0,%2
3866    dsg\\t%0,%2"
3867   [(set_attr "op_type"  "RRE,RXE")
3868    (set_attr "type"     "idiv")
3869    (set_attr "atype"    "reg,mem")])
3870
3871 (define_insn "divmodtisi3"
3872   [(set (match_operand:TI 0 "register_operand" "=d,d")
3873         (ior:TI
3874           (zero_extend:TI
3875             (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3876                     (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3877           (ashift:TI
3878             (zero_extend:TI
3879               (mod:DI (truncate:DI (match_dup 1))
3880                       (sign_extend:DI (match_dup 2))))
3881             (const_int 64))))]
3882   "TARGET_64BIT"
3883   "@
3884    dsgfr\\t%0,%2
3885    dsgf\\t%0,%2"
3886   [(set_attr "op_type"  "RRE,RXE")
3887    (set_attr "type"     "idiv")
3888    (set_attr "atype"    "reg,mem")])
3889
3890 ;
3891 ; udivmoddi4 instruction pattern(s).
3892 ;
3893
3894 (define_expand "udivmoddi4"
3895   [(parallel [(set (match_operand:DI 0 "general_operand" "")
3896                    (udiv:DI (match_operand:DI 1 "general_operand" "")
3897                             (match_operand:DI 2 "nonimmediate_operand" "")))
3898               (set (match_operand:DI 3 "general_operand" "")
3899                    (umod:DI (match_dup 1) (match_dup 2)))])
3900    (clobber (match_dup 4))]
3901   "TARGET_64BIT"
3902   "
3903 {
3904   rtx insn, div_equal, mod_equal, equal;
3905
3906   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3907   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3908   equal = gen_rtx_IOR (TImode,
3909                        gen_rtx_ZERO_EXTEND (TImode, div_equal),
3910                        gen_rtx_ASHIFT (TImode,
3911                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3912                                        GEN_INT (64)));
3913
3914   operands[4] = gen_reg_rtx(TImode);
3915   emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3916   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3917   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3918   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3919   REG_NOTES (insn) =
3920         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3921
3922   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3923   REG_NOTES (insn) =
3924         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3925
3926   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3927   REG_NOTES (insn) =
3928         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3929
3930   DONE;
3931 }")
3932
3933 (define_insn "udivmodtidi3"
3934   [(set (match_operand:TI 0 "register_operand" "=d,d")
3935         (ior:TI (zero_extend:TI
3936                   (truncate:DI
3937                     (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3938                              (zero_extend:TI
3939                                (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3940                 (ashift:TI
3941                   (zero_extend:TI
3942                     (truncate:DI
3943                       (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3944                   (const_int 64))))]
3945   "TARGET_64BIT"
3946   "@
3947    dlgr\\t%0,%2
3948    dlg\\t%0,%2"
3949   [(set_attr "op_type"  "RRE,RXE")
3950    (set_attr "type"     "idiv")
3951    (set_attr "atype"    "reg,mem")])
3952
3953 ;
3954 ; divmodsi4 instruction pattern(s).
3955 ;
3956
3957 (define_expand "divmodsi4"
3958   [(parallel [(set (match_operand:SI 0 "general_operand" "")
3959                    (div:SI (match_operand:SI 1 "general_operand" "")
3960                            (match_operand:SI 2 "nonimmediate_operand" "")))
3961               (set (match_operand:SI 3 "general_operand" "")
3962                    (mod:SI (match_dup 1) (match_dup 2)))])
3963    (clobber (match_dup 4))]
3964   "!TARGET_64BIT"
3965   "
3966 {
3967   rtx insn, div_equal, mod_equal, equal;
3968
3969   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3970   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3971   equal = gen_rtx_IOR (DImode,
3972                        gen_rtx_ZERO_EXTEND (DImode, div_equal),
3973                        gen_rtx_ASHIFT (DImode,
3974                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3975                                        GEN_INT (32)));
3976
3977   operands[4] = gen_reg_rtx(DImode);
3978   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3979   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3980   REG_NOTES (insn) =
3981         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3982
3983   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3984   REG_NOTES (insn) =
3985         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3986
3987   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3988   REG_NOTES (insn) =
3989         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3990
3991   DONE;
3992 }")
3993
3994 (define_insn "divmoddisi3"
3995   [(set (match_operand:DI 0 "register_operand" "=d,d")
3996         (ior:DI (zero_extend:DI
3997                   (truncate:SI
3998                     (div:DI (match_operand:DI 1 "register_operand" "0,0")
3999                             (sign_extend:DI
4000                               (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4001                 (ashift:DI
4002                   (zero_extend:DI
4003                     (truncate:SI
4004                       (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4005                   (const_int 32))))]
4006   "!TARGET_64BIT"
4007   "@
4008    dr\\t%0,%2
4009    d\\t%0,%2"
4010   [(set_attr "op_type"  "RR,RX")
4011    (set_attr "type"     "idiv")
4012    (set_attr "atype"    "reg,mem")])
4013
4014 ;
4015 ; udivsi3 and umodsi3 instruction pattern(s).
4016 ;
4017
4018
4019 (define_expand "udivsi3"
4020   [(set (match_operand:SI 0 "register_operand" "=d")
4021         (udiv:SI (match_operand:SI 1 "general_operand" "")
4022                  (match_operand:SI 2 "general_operand" "")))
4023    (clobber (match_dup 3))]
4024   "!TARGET_64BIT"
4025   "
4026 {
4027   rtx insn, udiv_equal, umod_equal, equal;
4028
4029   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4030   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4031   equal = gen_rtx_IOR (DImode,
4032                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4033                        gen_rtx_ASHIFT (DImode,
4034                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4035                                        GEN_INT (32)));
4036
4037   operands[3] = gen_reg_rtx (DImode);
4038
4039   if (CONSTANT_P (operands[2]))
4040     {
4041       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4042         {
4043           rtx label1 = gen_label_rtx ();
4044
4045           operands[1] = make_safe_from (operands[1], operands[0]);
4046           emit_move_insn (operands[0], const0_rtx);
4047           emit_insn (gen_cmpsi (operands[1], operands[2]));
4048           emit_jump_insn (gen_bltu (label1));
4049           emit_move_insn (operands[0], const1_rtx);
4050           emit_label (label1);
4051         }
4052       else
4053         {
4054           operands[2] = force_reg (SImode, operands[2]);
4055           operands[2] = make_safe_from (operands[2], operands[0]);
4056
4057           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4058           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4059                                              operands[2]));
4060           REG_NOTES (insn) =
4061             gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4062
4063           insn = emit_move_insn (operands[0],
4064                                  gen_lowpart (SImode, operands[3]));
4065           REG_NOTES (insn) =
4066             gen_rtx_EXPR_LIST (REG_EQUAL,
4067                                udiv_equal, REG_NOTES (insn));
4068         }
4069     }
4070   else
4071     {
4072       rtx label1 = gen_label_rtx ();
4073       rtx label2 = gen_label_rtx ();
4074       rtx label3 = gen_label_rtx ();
4075
4076       operands[1] = force_reg (SImode, operands[1]);
4077       operands[1] = make_safe_from (operands[1], operands[0]);
4078       operands[2] = force_reg (SImode, operands[2]);
4079       operands[2] = make_safe_from (operands[2], operands[0]);
4080
4081       emit_move_insn (operands[0], const0_rtx);
4082       emit_insn (gen_cmpsi (operands[2], operands[1]));
4083       emit_jump_insn (gen_bgtu (label3));
4084       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4085       emit_jump_insn (gen_blt (label2));
4086       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4087       emit_jump_insn (gen_beq (label1));
4088       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4089       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4090                                          operands[2]));
4091       REG_NOTES (insn) =
4092       gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4093
4094       insn = emit_move_insn (operands[0],
4095                              gen_lowpart (SImode, operands[3]));
4096       REG_NOTES (insn) =
4097       gen_rtx_EXPR_LIST (REG_EQUAL,
4098                                udiv_equal, REG_NOTES (insn));
4099       emit_jump (label3);
4100       emit_label (label1);
4101       emit_move_insn (operands[0], operands[1]);
4102       emit_jump (label3);
4103       emit_label (label2);
4104       emit_move_insn (operands[0], const1_rtx);
4105       emit_label (label3);
4106     }
4107   emit_move_insn (operands[0], operands[0]);
4108   DONE;
4109 }")
4110
4111 (define_expand "umodsi3"
4112   [(set (match_operand:SI 0 "register_operand" "=d")
4113         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4114                  (match_operand:SI 2 "nonimmediate_operand" "")))
4115    (clobber (match_dup 3))]
4116   "!TARGET_64BIT"
4117   "
4118 {
4119   rtx insn, udiv_equal, umod_equal, equal;
4120
4121   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4122   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4123   equal = gen_rtx_IOR (DImode,
4124                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4125                        gen_rtx_ASHIFT (DImode,
4126                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4127                                        GEN_INT (32)));
4128
4129   operands[3] = gen_reg_rtx (DImode);
4130
4131   if (CONSTANT_P (operands[2]))
4132     {
4133       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4134         {
4135           rtx label1 = gen_label_rtx ();
4136
4137           operands[1] = make_safe_from (operands[1], operands[0]);
4138           emit_move_insn (operands[0], operands[1]);
4139           emit_insn (gen_cmpsi (operands[0], operands[2]));
4140           emit_jump_insn (gen_bltu (label1));
4141           emit_insn (gen_abssi2 (operands[0], operands[2]));
4142           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4143           emit_label (label1);
4144         }
4145       else
4146         {
4147           operands[2] = force_reg (SImode, operands[2]);
4148           operands[2] = make_safe_from (operands[2], operands[0]);
4149
4150           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4151           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4152                                              operands[2]));
4153           REG_NOTES (insn) =
4154             gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4155
4156           insn = emit_move_insn (operands[0],
4157                                  gen_highpart (SImode, operands[3]));
4158           REG_NOTES (insn) =
4159             gen_rtx_EXPR_LIST (REG_EQUAL,
4160                                umod_equal, REG_NOTES (insn));
4161         }
4162     }
4163   else
4164     {
4165       rtx label1 = gen_label_rtx ();
4166       rtx label2 = gen_label_rtx ();
4167       rtx label3 = gen_label_rtx ();
4168
4169       operands[1] = force_reg (SImode, operands[1]);
4170       operands[1] = make_safe_from (operands[1], operands[0]);
4171       operands[2] = force_reg (SImode, operands[2]);
4172       operands[2] = make_safe_from (operands[2], operands[0]);
4173
4174       emit_move_insn(operands[0], operands[1]);
4175       emit_insn (gen_cmpsi (operands[2], operands[1]));
4176       emit_jump_insn (gen_bgtu (label3));
4177       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4178       emit_jump_insn (gen_blt (label2));
4179       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4180       emit_jump_insn (gen_beq (label1));
4181       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4182       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4183                                          operands[2]));
4184       REG_NOTES (insn) =
4185       gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4186
4187       insn = emit_move_insn (operands[0],
4188                              gen_highpart (SImode, operands[3]));
4189       REG_NOTES (insn) =
4190       gen_rtx_EXPR_LIST (REG_EQUAL,
4191                          umod_equal, REG_NOTES (insn));
4192       emit_jump (label3);
4193       emit_label (label1);
4194       emit_move_insn (operands[0], const0_rtx);
4195       emit_jump (label3);
4196       emit_label (label2);
4197       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4198       emit_label (label3);
4199     }
4200   DONE;
4201 }")
4202
4203 ;
4204 ; divdf3 instruction pattern(s).
4205 ;
4206
4207 (define_expand "divdf3"
4208   [(parallel
4209     [(set (match_operand:DF 0 "register_operand" "=f,f")
4210           (div:DF (match_operand:DF 1 "register_operand" "0,0")
4211                   (match_operand:DF 2 "general_operand" "f,m")))
4212      (clobber (reg:CC 33))])]
4213   "TARGET_HARD_FLOAT"
4214   "")
4215
4216 (define_insn "*divdf3"
4217   [(set (match_operand:DF 0 "register_operand" "=f,f")
4218         (div:DF (match_operand:DF 1 "register_operand" "0,0")
4219                 (match_operand:DF 2 "general_operand" "f,m")))
4220    (clobber (reg:CC 33))]
4221   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4222   "@
4223    ddbr\\t%0,%2
4224    ddb\\t%0,%2"
4225   [(set_attr "op_type"  "RR,RX")
4226    (set_attr "type"     "fdiv")
4227    (set_attr "atype"    "reg,mem")])
4228
4229 (define_insn "*divdf3_ibm"
4230   [(set (match_operand:DF 0 "register_operand" "=f,f")
4231         (div:DF (match_operand:DF 1 "register_operand" "0,0")
4232                 (match_operand:DF 2 "general_operand" "f,m")))
4233    (clobber (reg:CC 33))]
4234   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4235   "@
4236    ddr\\t%0,%2
4237    dd\\t%0,%2"
4238   [(set_attr "op_type"  "RR,RX")
4239    (set_attr "type"     "fdiv")
4240    (set_attr "atype"    "reg,mem")])
4241
4242 ;
4243 ; divsf3 instruction pattern(s).
4244 ;
4245
4246 (define_expand "divsf3"
4247   [(parallel
4248     [(set (match_operand:SF 0 "register_operand" "=f,f")
4249           (div:SF (match_operand:SF 1 "register_operand" "0,0")
4250                   (match_operand:SF 2 "general_operand" "f,m")))
4251      (clobber (reg:CC 33))])]
4252   "TARGET_HARD_FLOAT"
4253   "")
4254
4255 (define_insn "*divsf3"
4256   [(set (match_operand:SF 0 "register_operand" "=f,f")
4257         (div:SF (match_operand:SF 1 "register_operand" "0,0")
4258                 (match_operand:SF 2 "general_operand" "f,m")))
4259    (clobber (reg:CC 33))]
4260   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4261   "@
4262    debr\\t%0,%2
4263    deb\\t%0,%2"
4264   [(set_attr "op_type"  "RR,RX")
4265    (set_attr "type"     "fdiv")
4266    (set_attr "atype"    "reg,mem")])
4267
4268 (define_insn "*divsf3"
4269   [(set (match_operand:SF 0 "register_operand" "=f,f")
4270         (div:SF (match_operand:SF 1 "register_operand" "0,0")
4271                 (match_operand:SF 2 "general_operand" "f,m")))
4272    (clobber (reg:CC 33))]
4273   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4274   "@
4275    der\\t%0,%2
4276    de\\t%0,%2"
4277   [(set_attr "op_type"  "RR,RX")
4278    (set_attr "type"     "fdiv")
4279    (set_attr "atype"    "reg,mem")])
4280
4281
4282 ;;
4283 ;;- And instructions.
4284 ;;
4285
4286 ;
4287 ; anddi3 instruction pattern(s).
4288 ;
4289
4290 (define_insn "*anddi3_cc"
4291   [(set (reg 33)
4292         (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4293                          (match_operand:DI 2 "general_operand" "d,m"))
4294                  (const_int 0)))
4295    (set (match_operand:DI 0 "register_operand" "=d,d")
4296         (and:DI (match_dup 1) (match_dup 2)))]
4297   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4298   "@
4299    ngr\\t%0,%2
4300    ng\\t%0,%2"
4301   [(set_attr "op_type"  "RRE,RXE")
4302    (set_attr "atype"    "reg,mem")])
4303
4304 (define_insn "*anddi3_cconly"
4305   [(set (reg 33)
4306         (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4307                          (match_operand:DI 2 "general_operand" "d,m"))
4308                  (const_int 0)))
4309    (clobber (match_scratch:DI 0 "=d,d"))]
4310   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4311   "@
4312    ngr\\t%0,%2
4313    ng\\t%0,%2"
4314   [(set_attr "op_type"  "RRE,RXE")
4315    (set_attr "atype"    "reg,mem")])
4316
4317 (define_insn "*anddi3_ni"
4318   [(set (match_operand:DI 0 "register_operand" "=d")
4319         (and:DI (match_operand:DI 1 "register_operand" "%0")
4320                 (match_operand:DI 2 "immediate_operand" "n")))
4321    (clobber (reg:CC 33))]
4322   "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4323   "*
4324 {
4325   int part = s390_single_hi (operands[2], DImode, -1);
4326   operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4327
4328   switch (part)
4329     {
4330       case 0: return \"nihh\\t%0,%x2\";
4331       case 1: return \"nihl\\t%0,%x2\";
4332       case 2: return \"nilh\\t%0,%x2\";
4333       case 3: return \"nill\\t%0,%x2\";
4334       default: abort ();
4335     }
4336 }"
4337   [(set_attr "op_type"  "RI")
4338    (set_attr "atype"    "reg")])
4339
4340 (define_insn "anddi3"
4341   [(set (match_operand:DI 0 "register_operand" "=d,d")
4342         (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4343                 (match_operand:DI 2 "general_operand" "d,m")))
4344    (clobber (reg:CC 33))]
4345   "TARGET_64BIT"
4346   "@
4347    ngr\\t%0,%2
4348    ng\\t%0,%2"
4349   [(set_attr "op_type"  "RRE,RXE")
4350    (set_attr "atype"    "reg,mem")])
4351
4352 (define_insn "*anddi3_ss"
4353   [(set (match_operand:DI 0 "s_operand" "=Qo")
4354         (and:DI (match_dup 0)
4355                 (match_operand:DI 1 "s_imm_operand" "Qo")))
4356    (clobber (reg:CC 33))]
4357   ""
4358   "nc\\t%O0(8,%R0),%1"
4359   [(set_attr "op_type"  "SS")
4360    (set_attr "atype"    "mem")])
4361
4362 (define_insn "*anddi3_ss_inv"
4363   [(set (match_operand:DI 0 "s_operand" "=Qo")
4364         (and:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4365                 (match_dup 0)))
4366    (clobber (reg:CC 33))]
4367   ""
4368   "nc\\t%O0(8,%R0),%1"
4369   [(set_attr "op_type"  "SS")
4370    (set_attr "atype"    "mem")])
4371
4372 ;
4373 ; andsi3 instruction pattern(s).
4374 ;
4375
4376 (define_insn "*andsi3_cc"
4377   [(set (reg 33)
4378         (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4379                          (match_operand:SI 2 "general_operand" "d,m"))
4380                  (const_int 0)))
4381    (set (match_operand:SI 0 "register_operand" "=d,d")
4382         (and:SI (match_dup 1) (match_dup 2)))]
4383   "s390_match_ccmode(insn, CCTmode)"
4384   "@
4385    nr\\t%0,%2
4386    n\\t%0,%2"
4387   [(set_attr "op_type"  "RR,RX")
4388    (set_attr "atype"    "reg,mem")])
4389
4390 (define_insn "*andsi3_cconly"
4391   [(set (reg 33)
4392         (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4393                          (match_operand:SI 2 "general_operand" "d,m"))
4394                  (const_int 0)))
4395    (clobber (match_scratch:SI 0 "=d,d"))]
4396   "s390_match_ccmode(insn, CCTmode)"
4397   "@
4398    nr\\t%0,%2
4399    n\\t%0,%2"
4400   [(set_attr "op_type"  "RR,RX")
4401    (set_attr "atype"    "reg,mem")])
4402
4403 (define_insn "*andsi3_ni"
4404   [(set (match_operand:SI 0 "register_operand" "=d")
4405         (and:SI (match_operand:SI 1 "register_operand" "%0")
4406                 (match_operand:SI 2 "immediate_operand" "n")))
4407    (clobber (reg:CC 33))]
4408   "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4409   "*
4410 {
4411   int part = s390_single_hi (operands[2], SImode, -1);
4412   operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4413
4414   switch (part)
4415     {
4416       case 0: return \"nilh\\t%0,%x2\";
4417       case 1: return \"nill\\t%0,%x2\";
4418       default: abort ();
4419     }
4420 }"
4421   [(set_attr "op_type"  "RI")
4422    (set_attr "atype"    "reg")])
4423
4424 (define_insn "andsi3"
4425   [(set (match_operand:SI 0 "register_operand" "=d,d")
4426         (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4427                 (match_operand:SI 2 "general_operand" "d,m")))
4428    (clobber (reg:CC 33))]
4429   ""
4430   "@
4431    nr\\t%0,%2
4432    n\\t%0,%2"
4433   [(set_attr "op_type"  "RR,RX")
4434    (set_attr "atype"    "reg,mem")])
4435
4436 (define_insn "*andsi3_ss"
4437   [(set (match_operand:SI 0 "s_operand" "=Qo")
4438         (and:SI (match_dup 0)
4439                 (match_operand:SI 1 "s_imm_operand" "Qo")))
4440    (clobber (reg:CC 33))]
4441   ""
4442   "nc\\t%O0(4,%R0),%1"
4443   [(set_attr "op_type"  "SS")
4444    (set_attr "atype"    "mem")])
4445
4446 (define_insn "*andsi3_ss_inv"
4447   [(set (match_operand:SI 0 "s_operand" "=Qo")
4448         (and:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4449                 (match_dup 0)))
4450    (clobber (reg:CC 33))]
4451   ""
4452   "nc\\t%O0(4,%R0),%1"
4453   [(set_attr "op_type"  "SS")
4454    (set_attr "atype"    "mem")])
4455
4456 ;
4457 ; andhi3 instruction pattern(s).
4458 ;
4459
4460 (define_insn "*andhi3_ni"
4461   [(set (match_operand:HI 0 "register_operand" "=d,d")
4462         (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4463                 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4464    (clobber (reg:CC 33))]
4465   "TARGET_64BIT"
4466   "@
4467    nr\\t%0,%2
4468    nill\\t%0,%x2"
4469   [(set_attr "op_type"  "RR,RI")
4470    (set_attr "atype"    "reg")])
4471
4472 (define_insn "andhi3"
4473   [(set (match_operand:HI 0 "register_operand" "=d")
4474         (and:HI (match_operand:HI 1 "register_operand" "%0")
4475                 (match_operand:HI 2 "nonmemory_operand" "d")))
4476    (clobber (reg:CC 33))]
4477   ""
4478   "nr\\t%0,%2"
4479   [(set_attr "op_type"  "RR")
4480    (set_attr "atype"    "reg")])
4481
4482 (define_insn "*andhi3_ss"
4483   [(set (match_operand:HI 0 "s_operand" "=Qo")
4484         (and:HI (match_dup 0)
4485                 (match_operand:HI 1 "s_imm_operand" "Qo")))
4486    (clobber (reg:CC 33))]
4487   ""
4488   "nc\\t%O0(2,%R0),%1"
4489   [(set_attr "op_type"  "SS")
4490    (set_attr "atype"    "mem")])
4491
4492 (define_insn "*andhi3_ss_inv"
4493   [(set (match_operand:HI 0 "s_operand" "=Qo")
4494         (and:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4495                 (match_dup 0)))
4496    (clobber (reg:CC 33))]
4497   ""
4498   "nc\\t%O0(2,%R0),%1"
4499   [(set_attr "op_type"  "SS")
4500    (set_attr "atype"    "mem")])
4501
4502 ;
4503 ; andqi3 instruction pattern(s).
4504 ;
4505
4506 (define_insn "*andqi3_ni"
4507   [(set (match_operand:QI 0 "register_operand" "=d,d")
4508         (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4509                 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4510    (clobber (reg:CC 33))]
4511   "TARGET_64BIT"
4512   "@
4513    nr\\t%0,%2
4514    nill\\t%0,%b2"
4515   [(set_attr "op_type"  "RR,RI")
4516    (set_attr "atype"    "reg")])
4517
4518 (define_insn "andqi3"
4519   [(set (match_operand:QI 0 "register_operand" "=d")
4520         (and:QI (match_operand:QI 1 "register_operand" "%0")
4521                 (match_operand:QI 2 "nonmemory_operand" "d")))
4522    (clobber (reg:CC 33))]
4523   ""
4524   "nr\\t%0,%2"
4525   [(set_attr "op_type"  "RR")
4526    (set_attr "atype"    "reg")])
4527
4528 (define_insn "*andqi3_ss"
4529   [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4530         (and:QI (match_dup 0)
4531                 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4532    (clobber (reg:CC 33))]
4533   ""
4534   "@
4535    ni\\t%0,%b1
4536    nc\\t%O0(1,%R0),%1"
4537   [(set_attr "op_type"  "SI,SS")
4538    (set_attr "atype"    "mem")])
4539
4540 (define_insn "*andqi3_ss_inv"
4541   [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4542         (and:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4543                 (match_dup 0)))
4544    (clobber (reg:CC 33))]
4545   ""
4546   "@
4547    ni\\t%0,%b1
4548    nc\\t%O0(1,%R0),%1"
4549   [(set_attr "op_type"  "SI,SS")
4550    (set_attr "atype"    "mem")])
4551
4552
4553 ;;
4554 ;;- Bit set (inclusive or) instructions.
4555 ;;
4556
4557 ;
4558 ; iordi3 instruction pattern(s).
4559 ;
4560
4561 (define_insn "*iordi3_cc"
4562   [(set (reg 33)
4563         (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4564                          (match_operand:DI 2 "general_operand" "d,m"))
4565                  (const_int 0)))
4566    (set (match_operand:DI 0 "register_operand" "=d,d")
4567         (ior:DI (match_dup 1) (match_dup 2)))]
4568   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4569   "@
4570    ogr\\t%0,%2
4571    og\\t%0,%2"
4572   [(set_attr "op_type"  "RRE,RXE")
4573    (set_attr "atype"    "reg,mem")])
4574
4575 (define_insn "*iordi3_cconly"
4576   [(set (reg 33)
4577         (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4578                          (match_operand:DI 2 "general_operand" "d,m"))
4579                  (const_int 0)))
4580    (clobber (match_scratch:DI 0 "=d,d"))]
4581   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4582   "@
4583    ogr\\t%0,%2
4584    og\\t%0,%2"
4585   [(set_attr "op_type"  "RRE,RXE")
4586    (set_attr "atype"    "reg,mem")])
4587
4588 (define_insn "*iordi3_oi"
4589   [(set (match_operand:DI 0 "register_operand" "=d")
4590         (ior:DI (match_operand:DI 1 "register_operand" "%0")
4591                 (match_operand:DI 2 "immediate_operand" "n")))
4592    (clobber (reg:CC 33))]
4593   "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4594   "*
4595 {
4596   int part = s390_single_hi (operands[2], DImode, 0);
4597   operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4598
4599   switch (part)
4600     {
4601       case 0: return \"oihh\\t%0,%x2\";
4602       case 1: return \"oihl\\t%0,%x2\";
4603       case 2: return \"oilh\\t%0,%x2\";
4604       case 3: return \"oill\\t%0,%x2\";
4605       default: abort ();
4606     }
4607 }"
4608   [(set_attr "op_type"  "RI")
4609    (set_attr "atype"    "reg")])
4610
4611 (define_insn "iordi3"
4612   [(set (match_operand:DI 0 "register_operand" "=d,d")
4613         (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4614                 (match_operand:DI 2 "general_operand" "d,m")))
4615    (clobber (reg:CC 33))]
4616   "TARGET_64BIT"
4617   "@
4618    ogr\\t%0,%2
4619    og\\t%0,%2"
4620   [(set_attr "op_type"  "RRE,RXE")
4621    (set_attr "atype"    "reg,mem")])
4622
4623 (define_insn "*iordi3_ss"
4624   [(set (match_operand:DI 0 "s_operand" "=Qo")
4625         (ior:DI (match_dup 0)
4626                 (match_operand:DI 1 "s_imm_operand" "Qo")))
4627    (clobber (reg:CC 33))]
4628   ""
4629   "oc\\t%O0(8,%R0),%1"
4630   [(set_attr "op_type"  "SS")
4631    (set_attr "atype"    "mem")])
4632
4633 (define_insn "*iordi3_ss_inv"
4634   [(set (match_operand:DI 0 "s_operand" "=Qo")
4635         (ior:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4636                 (match_dup 0)))
4637    (clobber (reg:CC 33))]
4638   ""
4639   "oc\\t%O0(8,%R0),%1"
4640   [(set_attr "op_type"  "SS")
4641    (set_attr "atype"    "mem")])
4642
4643 ;
4644 ; iorsi3 instruction pattern(s).
4645 ;
4646
4647 (define_insn "*iorsi3_cc"
4648   [(set (reg 33)
4649         (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4650                          (match_operand:SI 2 "general_operand" "d,m"))
4651                  (const_int 0)))
4652    (set (match_operand:SI 0 "register_operand" "=d,d")
4653         (ior:SI (match_dup 1) (match_dup 2)))]
4654   "s390_match_ccmode(insn, CCTmode)"
4655   "@
4656    or\\t%0,%2
4657    o\\t%0,%2"
4658   [(set_attr "op_type"  "RR,RX")
4659    (set_attr "atype"    "reg,mem")])
4660
4661 (define_insn "*iorsi3_cconly"
4662   [(set (reg 33)
4663         (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4664                          (match_operand:SI 2 "general_operand" "d,m"))
4665                  (const_int 0)))
4666    (clobber (match_scratch:SI 0 "=d,d"))]
4667   "s390_match_ccmode(insn, CCTmode)"
4668   "@
4669    or\\t%0,%2
4670    o\\t%0,%2"
4671   [(set_attr "op_type"  "RR,RX")
4672    (set_attr "atype"    "reg,mem")])
4673
4674 (define_insn "*iorsi3_oi"
4675   [(set (match_operand:SI 0 "register_operand" "=d")
4676         (ior:SI (match_operand:SI 1 "register_operand" "%0")
4677                 (match_operand:SI 2 "immediate_operand" "n")))
4678    (clobber (reg:CC 33))]
4679   "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4680   "*
4681 {
4682   int part = s390_single_hi (operands[2], SImode, 0);
4683   operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4684
4685   switch (part)
4686     {
4687       case 0: return \"oilh\\t%0,%x2\";
4688       case 1: return \"oill\\t%0,%x2\";
4689       default: abort ();
4690     }
4691 }"
4692   [(set_attr "op_type"  "RI")
4693    (set_attr "atype"    "reg")])
4694
4695 (define_insn "iorsi3"
4696   [(set (match_operand:SI 0 "register_operand" "=d,d")
4697         (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4698                 (match_operand:SI 2 "general_operand" "d,m")))
4699    (clobber (reg:CC 33))]
4700   ""
4701   "@
4702    or\\t%0,%2
4703    o\\t%0,%2"
4704   [(set_attr "op_type"  "RR,RX")
4705    (set_attr "atype"    "reg,mem")])
4706
4707 (define_insn "*iorsi3_ss"
4708   [(set (match_operand:SI 0 "s_operand" "=Qo")
4709         (ior:SI (match_dup 0)
4710                 (match_operand:SI 1 "s_imm_operand" "Qo")))
4711    (clobber (reg:CC 33))]
4712   ""
4713   "oc\\t%O0(4,%R0),%1"
4714   [(set_attr "op_type"  "SS")
4715    (set_attr "atype"    "mem")])
4716
4717 (define_insn "*iorsi3_ss_inv"
4718   [(set (match_operand:SI 0 "s_operand" "=Qo")
4719         (ior:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4720                 (match_dup 0)))
4721    (clobber (reg:CC 33))]
4722   ""
4723   "oc\\t%O0(4,%R0),%1"
4724   [(set_attr "op_type"  "SS")
4725    (set_attr "atype"    "mem")])
4726
4727 ;
4728 ; iorhi3 instruction pattern(s).
4729 ;
4730
4731 (define_insn "*iorhi3_oi"
4732   [(set (match_operand:HI 0 "register_operand" "=d,d")
4733         (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4734                 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4735    (clobber (reg:CC 33))]
4736   "TARGET_64BIT"
4737   "@
4738    or\\t%0,%2
4739    oill\\t%0,%x2"
4740   [(set_attr "op_type"  "RR,RI")
4741    (set_attr "atype"    "reg")])
4742
4743 (define_insn "iorhi3"
4744   [(set (match_operand:HI 0 "register_operand" "=d")
4745         (ior:HI (match_operand:HI 1 "register_operand" "%0")
4746                 (match_operand:HI 2 "nonmemory_operand" "d")))
4747    (clobber (reg:CC 33))]
4748   ""
4749   "or\\t%0,%2"
4750   [(set_attr "op_type"  "RR")
4751    (set_attr "atype"    "reg")])
4752
4753 (define_insn "*iorhi3_ss"
4754   [(set (match_operand:HI 0 "s_operand" "=Qo")
4755         (ior:HI (match_dup 0)
4756                 (match_operand:HI 1 "s_imm_operand" "Qo")))
4757    (clobber (reg:CC 33))]
4758   ""
4759   "oc\\t%O0(2,%R0),%1"
4760   [(set_attr "op_type"  "SS")
4761    (set_attr "atype"    "mem")])
4762
4763 (define_insn "*iorhi3_ss_inv"
4764   [(set (match_operand:HI 0 "s_operand" "=Qo")
4765         (ior:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4766                 (match_dup 0)))
4767    (clobber (reg:CC 33))]
4768   ""
4769   "oc\\t%O0(2,%R0),%1"
4770   [(set_attr "op_type"  "SS")
4771    (set_attr "atype"    "mem")])
4772
4773 ;
4774 ; iorqi3 instruction pattern(s).
4775 ;
4776
4777 (define_insn "*iorqi3_oi"
4778   [(set (match_operand:QI 0 "register_operand" "=d,d")
4779         (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4780                 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4781    (clobber (reg:CC 33))]
4782   "TARGET_64BIT"
4783   "@
4784    or\\t%0,%2
4785    oill\\t%0,%b2"
4786   [(set_attr "op_type"  "RR,RI")
4787    (set_attr "atype"    "reg")])
4788
4789 (define_insn "iorqi3"
4790   [(set (match_operand:QI 0 "register_operand" "=d")
4791         (ior:QI (match_operand:QI 1 "register_operand" "%0")
4792                 (match_operand:QI 2 "nonmemory_operand" "d")))
4793    (clobber (reg:CC 33))]
4794   ""
4795   "or\\t%0,%2"
4796   [(set_attr "op_type"  "RR")
4797    (set_attr "atype"    "reg")])
4798
4799 (define_insn "*iorqi3_ss"
4800   [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4801         (ior:QI (match_dup 0)
4802                 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4803    (clobber (reg:CC 33))]
4804   ""
4805   "@
4806    oi\\t%0,%b1
4807    oc\\t%O0(1,%R0),%1"
4808   [(set_attr "op_type"  "SI,SS")
4809    (set_attr "atype"    "reg,mem")])
4810
4811 (define_insn "*iorqi3_ss_inv"
4812   [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4813         (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4814                 (match_dup 0)))
4815    (clobber (reg:CC 33))]
4816   ""
4817   "@
4818    oi\\t%0,%b1
4819    oc\\t%O0(1,%R0),%1"
4820   [(set_attr "op_type"  "SI,SS")
4821    (set_attr "atype"    "reg,mem")])
4822
4823
4824 ;;
4825 ;;- Xor instructions.
4826 ;;
4827
4828 ;
4829 ; xordi3 instruction pattern(s).
4830 ;
4831
4832 (define_insn "*xordi3_cc"
4833   [(set (reg 33)
4834         (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4835                          (match_operand:DI 2 "general_operand" "d,m"))
4836                  (const_int 0)))
4837    (set (match_operand:DI 0 "register_operand" "=d,d")
4838         (xor:DI (match_dup 1) (match_dup 2)))]
4839   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4840   "@
4841    xgr\\t%0,%2
4842    xg\\t%0,%2"
4843   [(set_attr "op_type"  "RRE,RXE")
4844    (set_attr "atype"    "reg,mem")])
4845
4846 (define_insn "*xordi3_cconly"
4847   [(set (reg 33)
4848         (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4849                          (match_operand:DI 2 "general_operand" "d,m"))
4850                  (const_int 0)))
4851    (clobber (match_scratch:DI 0 "=d,d"))]
4852   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4853   "@
4854    xgr\\t%0,%2
4855    xr\\t%0,%2"
4856   [(set_attr "op_type"  "RRE,RXE")
4857    (set_attr "atype"    "reg,mem")])
4858
4859 (define_insn "xordi3"
4860   [(set (match_operand:DI 0 "register_operand" "=d,d")
4861         (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4862                 (match_operand:DI 2 "general_operand" "d,m")))
4863    (clobber (reg:CC 33))]
4864   "TARGET_64BIT"
4865   "@
4866    xgr\\t%0,%2
4867    xg\\t%0,%2"
4868   [(set_attr "op_type"  "RRE,RXE")
4869    (set_attr "atype"    "reg,mem")])
4870
4871 (define_insn "*xordi3_ss"
4872   [(set (match_operand:DI 0 "s_operand" "=Qo")
4873         (xor:DI (match_dup 0)
4874                 (match_operand:DI 1 "s_imm_operand" "Qo")))
4875    (clobber (reg:CC 33))]
4876   ""
4877   "xc\\t%O0(8,%R0),%1"
4878   [(set_attr "op_type"  "SS")
4879    (set_attr "atype"    "mem")])
4880
4881 (define_insn "*xordi3_ss_inv"
4882   [(set (match_operand:DI 0 "s_operand" "=Qo")
4883         (xor:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4884                 (match_dup 0)))
4885    (clobber (reg:CC 33))]
4886   ""
4887   "xc\\t%O0(8,%R0),%1"
4888   [(set_attr "op_type"  "SS")
4889    (set_attr "atype"    "mem")])
4890
4891 ;
4892 ; xorsi3 instruction pattern(s).
4893 ;
4894
4895 (define_insn "*xorsi3_cc"
4896   [(set (reg 33)
4897         (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4898                          (match_operand:SI 2 "general_operand" "d,m"))
4899                  (const_int 0)))
4900    (set (match_operand:SI 0 "register_operand" "=d,d")
4901         (xor:SI (match_dup 1) (match_dup 2)))]
4902   "s390_match_ccmode(insn, CCTmode)"
4903   "@
4904    xr\\t%0,%2
4905    x\\t%0,%2"
4906   [(set_attr "op_type"  "RR,RX")
4907    (set_attr "atype"    "reg,mem")])
4908
4909 (define_insn "*xorsi3_cconly"
4910   [(set (reg 33)
4911         (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4912                          (match_operand:SI 2 "general_operand" "d,m"))
4913                  (const_int 0)))
4914    (clobber (match_scratch:SI 0 "=d,d"))]
4915   "s390_match_ccmode(insn, CCTmode)"
4916   "@
4917    xr\\t%0,%2
4918    x\\t%0,%2"
4919   [(set_attr "op_type"  "RR,RX")
4920    (set_attr "atype"    "reg,mem")])
4921
4922 (define_insn "xorsi3"
4923   [(set (match_operand:SI 0 "register_operand" "=d,d")
4924         (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4925                 (match_operand:SI 2 "general_operand" "d,m")))
4926    (clobber (reg:CC 33))]
4927   ""
4928   "@
4929    xr\\t%0,%2
4930    x\\t%0,%2"
4931   [(set_attr "op_type"  "RR,RX")
4932    (set_attr "atype"    "reg,mem")])
4933
4934 (define_insn "*xorsi3_ss"
4935   [(set (match_operand:SI 0 "s_operand" "=Qo")
4936         (xor:SI (match_dup 0)
4937                 (match_operand:SI 1 "s_imm_operand" "Qo")))
4938    (clobber (reg:CC 33))]
4939   ""
4940   "xc\\t%O0(4,%R0),%1"
4941   [(set_attr "op_type"  "SS")
4942    (set_attr "atype"    "mem")])
4943
4944 (define_insn "*xorsi3_ss_inv"
4945   [(set (match_operand:SI 0 "s_operand" "=Qo")
4946         (xor:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4947                 (match_dup 0)))
4948    (clobber (reg:CC 33))]
4949   ""
4950   "xc\\t%O0(4,%R0),%1"
4951   [(set_attr "op_type"  "SS")
4952    (set_attr "atype"    "mem")])
4953
4954 ;
4955 ; xorhi3 instruction pattern(s).
4956 ;
4957
4958 (define_insn "xorhi3"
4959   [(set (match_operand:HI 0 "register_operand" "=d")
4960         (xor:HI (match_operand:HI 1 "register_operand" "%0")
4961                 (match_operand:HI 2 "nonmemory_operand" "d")))
4962    (clobber (reg:CC 33))]
4963   ""
4964   "xr\\t%0,%2"
4965   [(set_attr "op_type"  "RR")
4966    (set_attr "atype"    "reg")])
4967
4968 (define_insn "*xorhi3_ss"
4969   [(set (match_operand:HI 0 "s_operand" "=Qo")
4970         (xor:HI (match_dup 0)
4971                 (match_operand:HI 1 "s_imm_operand" "Qo")))
4972    (clobber (reg:CC 33))]
4973   ""
4974   "xc\\t%O0(2,%R0),%1"
4975   [(set_attr "op_type"  "SS")
4976    (set_attr "atype"    "mem")])
4977
4978 (define_insn "*xorhi3_ss_inv"
4979   [(set (match_operand:HI 0 "s_operand" "=Qo")
4980         (xor:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4981                 (match_dup 0)))
4982    (clobber (reg:CC 33))]
4983   ""
4984   "xc\\t%O0(2,%R0),%1"
4985   [(set_attr "op_type"  "SS")
4986    (set_attr "atype"    "mem")])
4987
4988 ;
4989 ; xorqi3 instruction pattern(s).
4990 ;
4991
4992 (define_insn "xorqi3"
4993   [(set (match_operand:QI 0 "register_operand" "=d")
4994         (xor:QI (match_operand:QI 1 "register_operand" "%0")
4995                 (match_operand:QI 2 "nonmemory_operand" "d")))
4996    (clobber (reg:CC 33))]
4997   ""
4998   "xr\\t%0,%2"
4999   [(set_attr "op_type"  "RR")
5000    (set_attr "atype"    "reg")])
5001
5002 (define_insn "*xorqi3_ss"
5003   [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
5004         (xor:QI (match_dup 0)
5005                 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
5006    (clobber (reg:CC 33))]
5007   ""
5008   "@
5009    xi\\t%0,%b1
5010    xc\\t%O0(1,%R0),%1"
5011   [(set_attr "op_type"  "SI,SS")
5012    (set_attr "atype"    "mem")])
5013
5014 (define_insn "*xorqi3_ss_inv"
5015   [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
5016         (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
5017                 (match_dup 0)))
5018    (clobber (reg:CC 33))]
5019   ""
5020   "@
5021    xi\\t%0,%b1
5022    xc\\t%O0(1,%R0),%1"
5023   [(set_attr "op_type"  "SI,SS")
5024    (set_attr "atype"    "mem")])
5025
5026
5027 ;;
5028 ;;- Negate instructions.
5029 ;;
5030
5031 ;
5032 ; negdi2 instruction pattern(s).
5033 ;
5034
5035 (define_expand "negdi2"
5036   [(parallel
5037     [(set (match_operand:DI 0 "register_operand" "=d")
5038           (neg:DI (match_operand:DI 1 "register_operand" "d")))
5039      (clobber (reg:CC 33))])]
5040   ""
5041   "")
5042
5043 (define_insn "*negdi2_64"
5044   [(set (match_operand:DI 0 "register_operand" "=d")
5045         (neg:DI (match_operand:DI 1 "register_operand" "d")))
5046    (clobber (reg:CC 33))]
5047   "TARGET_64BIT"
5048   "lcgr\\t%0,%1"
5049   [(set_attr "op_type"  "RR")])
5050
5051 (define_insn "*negdi2_31"
5052   [(set (match_operand:DI 0 "register_operand" "=d")
5053         (neg:DI (match_operand:DI 1 "register_operand" "d")))
5054    (clobber (reg:CC 33))]
5055   "!TARGET_64BIT"
5056   "*
5057 {
5058   rtx xop[1];
5059   xop[0] = gen_label_rtx ();
5060   output_asm_insn (\"lcr\\t%0,%1\", operands);
5061   output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5062   output_asm_insn (\"je\\t%l0\", xop);
5063   output_asm_insn (\"bctr\\t%0,0\", operands);
5064   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5065                              CODE_LABEL_NUMBER (xop[0]));
5066   return \"\";
5067 }"
5068   [(set_attr "op_type"  "NN")
5069    (set_attr "type"     "other")
5070    (set_attr "length"   "10")])
5071
5072 ;
5073 ; negsi2 instruction pattern(s).
5074 ;
5075
5076 (define_insn "negsi2"
5077   [(set (match_operand:SI 0 "register_operand" "=d")
5078         (neg:SI (match_operand:SI 1 "register_operand" "d")))
5079    (clobber (reg:CC 33))]
5080   ""
5081   "lcr\\t%0,%1"
5082   [(set_attr "op_type"  "RR")])
5083
5084 ;
5085 ; negdf2 instruction pattern(s).
5086 ;
5087
5088 (define_expand "negdf2"
5089   [(parallel
5090     [(set (match_operand:DF 0 "register_operand" "=f")
5091           (neg:DF (match_operand:DF 1 "register_operand" "f")))
5092      (clobber (reg:CC 33))])]
5093   "TARGET_HARD_FLOAT"
5094   "")
5095
5096 (define_insn "*negdf2"
5097   [(set (match_operand:DF 0 "register_operand" "=f")
5098         (neg:DF (match_operand:DF 1 "register_operand" "f")))
5099    (clobber (reg:CC 33))]
5100   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5101   "lcdbr\\t%0,%1"
5102   [(set_attr "op_type"  "RR")])
5103
5104 (define_insn "*negdf2_ibm"
5105   [(set (match_operand:DF 0 "register_operand" "=f")
5106         (neg:DF (match_operand:DF 1 "register_operand" "f")))
5107    (clobber (reg:CC 33))]
5108   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5109   "lcdr\\t%0,%1"
5110   [(set_attr "op_type"  "RR")])
5111
5112 ;
5113 ; negsf2 instruction pattern(s).
5114 ;
5115
5116 (define_expand "negsf2"
5117   [(parallel
5118     [(set (match_operand:SF 0 "register_operand" "=f")
5119           (neg:SF (match_operand:SF 1 "register_operand" "f")))
5120      (clobber (reg:CC 33))])]
5121   "TARGET_HARD_FLOAT"
5122   "")
5123
5124 (define_insn "*negsf2"
5125   [(set (match_operand:SF 0 "register_operand" "=f")
5126         (neg:SF (match_operand:SF 1 "register_operand" "f")))
5127    (clobber (reg:CC 33))]
5128   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5129   "lcebr\\t%0,%1"
5130   [(set_attr "op_type"  "RR")])
5131
5132 (define_insn "*negsf2"
5133   [(set (match_operand:SF 0 "register_operand" "=f")
5134         (neg:SF (match_operand:SF 1 "register_operand" "f")))
5135    (clobber (reg:CC 33))]
5136   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5137   "lcer\\t%0,%1"
5138   [(set_attr "op_type"  "RR")])
5139
5140
5141 ;;
5142 ;;- Absolute value instructions.
5143 ;;
5144
5145 ;
5146 ; absdi2 instruction pattern(s).
5147 ;
5148
5149 (define_insn "absdi2"
5150   [(set (match_operand:DI 0 "register_operand" "=d")
5151         (abs:DI (match_operand:DI 1 "register_operand" "d")))
5152    (clobber (reg:CC 33))]
5153   "TARGET_64BIT"
5154   "lpgr\\t%0,%1"
5155   [(set_attr "op_type"  "RRE")])
5156
5157 ;
5158 ; abssi2 instruction pattern(s).
5159 ;
5160
5161 (define_insn "abssi2"
5162   [(set (match_operand:SI 0 "register_operand" "=d")
5163         (abs:SI (match_operand:SI 1 "register_operand" "d")))
5164    (clobber (reg:CC 33))]
5165   ""
5166   "lpr\\t%0,%1"
5167   [(set_attr "op_type"  "RR")])
5168
5169 ;
5170 ; absdf2 instruction pattern(s).
5171 ;
5172
5173 (define_expand "absdf2"
5174   [(parallel
5175     [(set (match_operand:DF 0 "register_operand" "=f")
5176           (abs:DF (match_operand:DF 1 "register_operand" "f")))
5177      (clobber (reg:CC 33))])]
5178   "TARGET_HARD_FLOAT"
5179   "")
5180
5181 (define_insn "*absdf2"
5182   [(set (match_operand:DF 0 "register_operand" "=f")
5183         (abs:DF (match_operand:DF 1 "register_operand" "f")))
5184    (clobber (reg:CC 33))]
5185   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5186   "lpdbr\\t%0,%1"
5187   [(set_attr "op_type"  "RR")])
5188
5189 (define_insn "*absdf2_ibm"
5190   [(set (match_operand:DF 0 "register_operand" "=f")
5191         (abs:DF (match_operand:DF 1 "register_operand" "f")))
5192    (clobber (reg:CC 33))]
5193   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5194   "lpdr\\t%0,%1"
5195   [(set_attr "op_type"  "RR")])
5196
5197 ;
5198 ; abssf2 instruction pattern(s).
5199 ;
5200
5201 (define_expand "abssf2"
5202   [(parallel
5203     [(set (match_operand:SF 0 "register_operand" "=f")
5204           (abs:SF (match_operand:SF 1 "register_operand" "f")))
5205      (clobber (reg:CC 33))])]
5206   "TARGET_HARD_FLOAT"
5207   "")
5208
5209 (define_insn "*abssf2"
5210   [(set (match_operand:SF 0 "register_operand" "=f")
5211         (abs:SF (match_operand:SF 1 "register_operand" "f")))
5212    (clobber (reg:CC 33))]
5213   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5214   "lpebr\\t%0,%1"
5215   [(set_attr "op_type"  "RR")])
5216
5217 (define_insn "*abssf2_ibm"
5218   [(set (match_operand:SF 0 "register_operand" "=f")
5219         (abs:SF (match_operand:SF 1 "register_operand" "f")))
5220    (clobber (reg:CC 33))]
5221   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5222   "lper\\t%0,%1"
5223   [(set_attr "op_type"  "RR")])
5224
5225 ;;
5226 ;;- Square root instructions.
5227 ;;
5228
5229 ;
5230 ; sqrtdf2 instruction pattern(s).
5231 ;
5232
5233 (define_insn "sqrtdf2"
5234   [(set (match_operand:DF 0 "register_operand" "=f,f")
5235         (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5236   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5237   "@
5238    sqdbr\\t%0,%1
5239    sqdb\\t%0,%1"
5240   [(set_attr "op_type"  "RRE,RSE")])
5241
5242 ;
5243 ; sqrtsf2 instruction pattern(s).
5244 ;
5245
5246 (define_insn "sqrtsf2"
5247   [(set (match_operand:SF 0 "register_operand" "=f,f")
5248         (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5249   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5250   "@
5251    sqebr\\t%0,%1
5252    sqeb\\t%0,%1"
5253   [(set_attr "op_type"  "RRE,RSE")])
5254
5255 ;;
5256 ;;- One complement instructions.
5257 ;;
5258
5259 ;
5260 ; one_cmpldi2 instruction pattern(s).
5261 ;
5262
5263 (define_expand "one_cmpldi2"
5264   [(parallel
5265     [(set (match_operand:DI 0 "register_operand" "")
5266           (xor:DI (match_operand:DI 1 "register_operand" "")
5267                   (const_int -1)))
5268      (clobber (reg:CC 33))])]
5269   "TARGET_64BIT"
5270   "")
5271
5272 ;
5273 ; one_cmplsi2 instruction pattern(s).
5274 ;
5275
5276 (define_expand "one_cmplsi2"
5277   [(parallel
5278     [(set (match_operand:SI 0 "register_operand" "")
5279           (xor:SI (match_operand:SI 1 "register_operand" "")
5280                   (const_int -1)))
5281      (clobber (reg:CC 33))])]
5282   ""
5283   "")
5284
5285 ;
5286 ; one_cmplhi2 instruction pattern(s).
5287 ;
5288
5289 (define_expand "one_cmplhi2"
5290   [(parallel
5291     [(set (match_operand:HI 0 "register_operand" "")
5292           (xor:HI (match_operand:HI 1 "register_operand" "")
5293                   (const_int -1)))
5294      (clobber (reg:CC 33))])]
5295   ""
5296   "")
5297
5298 ;
5299 ; one_cmplqi2 instruction pattern(s).
5300 ;
5301
5302 (define_expand "one_cmplqi2"
5303   [(parallel
5304     [(set (match_operand:QI 0 "register_operand" "")
5305           (xor:QI (match_operand:QI 1 "register_operand" "")
5306                   (const_int -1)))
5307      (clobber (reg:CC 33))])]
5308   ""
5309   "")
5310
5311
5312 ;;
5313 ;;- Rotate instructions.
5314 ;;
5315
5316 ;
5317 ; rotldi3 instruction pattern(s).
5318 ;
5319
5320 (define_insn "rotldi3"
5321   [(set (match_operand:DI 0 "register_operand" "=d,d")
5322         (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5323                    (match_operand:DI 2 "nonmemory_operand" "J,a")))
5324    (clobber (reg:CC 33))]
5325   "TARGET_64BIT"
5326   "@
5327    rllg\\t%0,%1,%c2
5328    rllg\\t%0,%1,0(%2)"
5329   [(set_attr "op_type"  "RSE")])
5330
5331 ;
5332 ; rotlsi3 instruction pattern(s).
5333 ;
5334
5335 (define_insn "rotlsi3"
5336   [(set (match_operand:SI 0 "register_operand" "=d,d")
5337         (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5338                    (match_operand:SI 2 "nonmemory_operand" "J,a")))
5339    (clobber (reg:CC 33))]
5340   "TARGET_64BIT"
5341   "@
5342    rll\\t%0,%1,%c2
5343    rll\\t%0,%1,0(%2)"
5344   [(set_attr "op_type"  "RSE")])
5345
5346
5347 ;;
5348 ;;- Arithmetic shift instructions.
5349 ;;
5350 ;;  for left shifts always setal shifts are used (ANSI-C)
5351
5352 ;
5353 ; ashldi3 instruction pattern(s).
5354 ;
5355
5356 (define_expand "ashldi3"
5357   [(parallel
5358     [(set (match_operand:DI 0 "register_operand" "")
5359           (ashift:DI (match_operand:DI 1 "register_operand" "")
5360                      (match_operand:SI 2 "nonmemory_operand" "")))
5361      (clobber (reg:CC 33))])]
5362   ""
5363   "")
5364
5365 (define_insn "*ashldi3_31"
5366   [(set (match_operand:DI 0 "register_operand" "=d,d")
5367         (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5368                    (match_operand:SI 2 "nonmemory_operand" "J,a")))
5369    (clobber (reg:CC 33))]
5370   "!TARGET_64BIT"
5371   "@
5372    sldl\\t%0,%c2
5373    sldl\\t%0,0(%2)"
5374   [(set_attr "op_type"  "RS")])
5375
5376 (define_insn "*ashldi3_64"
5377   [(set            (match_operand:DI 0 "register_operand" "=d,d")
5378         (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5379                    (match_operand:SI 2 "nonmemory_operand" "J,a")))
5380    (clobber (reg:CC 33))]
5381   "TARGET_64BIT"
5382   "@
5383    sllg\\t%0,%1,%2
5384    sllg\\t%0,%1,0(%2)"
5385   [(set_attr "op_type"  "RSE")])
5386
5387 ;
5388 ; ashrdi3 instruction pattern(s).
5389 ;
5390
5391 (define_expand "ashrdi3"
5392   [(parallel
5393     [(set (match_operand:DI 0 "register_operand" "")
5394           (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5395                        (match_operand:SI 2 "nonmemory_operand" "")))
5396      (clobber (reg:CC 33))])]
5397   ""
5398   "")
5399
5400 (define_insn "*ashrdi3_31"
5401   [(set (match_operand:DI 0 "register_operand" "=d,d")
5402         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5403                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5404    (clobber (reg:CC 33))]
5405   "!TARGET_64BIT"
5406   "@
5407    srda\\t%0,%c2
5408    srda\\t%0,0(%2)"
5409   [(set_attr "op_type"  "RS")])
5410
5411 (define_insn "*ashrdi3_64"
5412   [(set (match_operand:DI 0 "register_operand" "=d,d")
5413         (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5414                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5415    (clobber (reg:CC 33))]
5416   "TARGET_64BIT"
5417   "@
5418    srag\\t%0,%1,%c2
5419    srag\\t%0,%1,0(%2)"
5420   [(set_attr "op_type"  "RSE")])
5421
5422 ;
5423 ; ashlsi3 instruction pattern(s).
5424 ;
5425 ; all 32 bits has to be shifted (testcase co750c)
5426
5427 (define_insn "ashlsi3"
5428   [(set (match_operand:SI 0 "register_operand" "=d,d")
5429         (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5430                    (match_operand:SI 2 "nonmemory_operand" "J,a")))
5431    (clobber (reg:CC 33))]
5432   ""
5433   "@
5434    sll\\t%0,%c2
5435    sll\\t%0,0(%2)"
5436   [(set_attr "op_type"  "RS")])
5437
5438 ;
5439 ; ashrsi3 instruction pattern(s).
5440 ;
5441
5442 (define_insn "ashrsi3"
5443   [(set (match_operand:SI 0 "register_operand" "=d,d")
5444         (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5445                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5446    (clobber (reg:CC 33))]
5447   ""
5448   "@
5449    sra\\t%0,%c2
5450    sra\\t%0,0(%2)"
5451   [(set_attr "op_type"  "RS")])
5452
5453
5454 ;;
5455 ;;- logical shift instructions.
5456 ;;
5457
5458 ;
5459 ; lshrdi3 instruction pattern(s).
5460 ;
5461
5462 (define_expand "lshrdi3"
5463   [(parallel
5464     [(set (match_operand:DI 0 "register_operand" "")
5465           (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5466                        (match_operand:SI 2 "nonmemory_operand" "")))
5467      (clobber (reg:CC 33))])]
5468   ""
5469   "")
5470
5471 (define_insn "*lshrdi3_31"
5472   [(set (match_operand:DI 0 "register_operand" "=d,d")
5473         (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5474                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5475    (clobber (reg:CC 33))]
5476   "!TARGET_64BIT"
5477   "@
5478    srdl\\t%0,%c2
5479    srdl\\t%0,0(%2)"
5480    [(set_attr "op_type"  "RS,RS")])
5481
5482 (define_insn "*lshrdi3_64"
5483   [(set (match_operand:DI 0 "register_operand" "=d,d")
5484         (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5485                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5486    (clobber (reg:CC 33))]
5487   "TARGET_64BIT"
5488   "@
5489    srlg\\t%0,%1,%c2
5490    srlg\\t%0,%1,0(%2)"
5491   [(set_attr "op_type"  "RS,RS")])
5492
5493 ;
5494 ; lshrsi3 instruction pattern(s).
5495 ;
5496
5497 (define_insn "lshrsi3"
5498   [(set (match_operand:SI 0 "register_operand" "=d,d")
5499         (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5500                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5501    (clobber (reg:CC 33))]
5502   ""
5503   "@
5504    srl\\t%0,%c2
5505    srl\\t%0,0(%2)"
5506   [(set_attr "op_type"  "RS")])
5507
5508
5509 ;;
5510 ;; Branch instruction patterns.
5511 ;;
5512
5513 (define_expand "beq"
5514   [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5515    (set (pc)
5516         (if_then_else (eq (reg:CCZ 33) (const_int 0))
5517                       (label_ref (match_operand 0 "" ""))
5518                       (pc)))]
5519   ""
5520   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5521
5522 (define_expand "bne"
5523   [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5524    (set (pc)
5525         (if_then_else (ne (reg:CCZ 33) (const_int 0))
5526                       (label_ref (match_operand 0 "" ""))
5527                       (pc)))]
5528   ""
5529   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5530
5531 (define_expand "bgt"
5532   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5533    (set (pc)
5534         (if_then_else (gt (reg:CCS 33) (const_int 0))
5535                       (label_ref (match_operand 0 "" ""))
5536                       (pc)))]
5537   ""
5538   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5539
5540 (define_expand "bgtu"
5541   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5542    (set (pc)
5543         (if_then_else (gtu (reg:CCU 33) (const_int 0))
5544                       (label_ref (match_operand 0 "" ""))
5545                       (pc)))]
5546   ""
5547   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5548
5549 (define_expand "blt"
5550   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5551    (set (pc)
5552         (if_then_else (lt (reg:CCS 33) (const_int 0))
5553                       (label_ref (match_operand 0 "" ""))
5554                       (pc)))]
5555   ""
5556   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5557
5558 (define_expand "bltu"
5559   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5560    (set (pc)
5561         (if_then_else (ltu (reg:CCU 33) (const_int 0))
5562                       (label_ref (match_operand 0 "" ""))
5563                       (pc)))]
5564   ""
5565   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5566
5567 (define_expand "bge"
5568   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5569    (set (pc)
5570         (if_then_else (ge (reg:CCS 33) (const_int 0))
5571                       (label_ref (match_operand 0 "" ""))
5572                       (pc)))]
5573   ""
5574   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5575
5576 (define_expand "bgeu"
5577   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5578    (set (pc)
5579         (if_then_else (geu (reg:CCU 33) (const_int 0))
5580                       (label_ref (match_operand 0 "" ""))
5581                       (pc)))]
5582   ""
5583   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5584
5585 (define_expand "ble"
5586   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5587    (set (pc)
5588         (if_then_else (le (reg:CCS 33) (const_int 0))
5589                       (label_ref (match_operand 0 "" ""))
5590                       (pc)))]
5591   ""
5592   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5593
5594 (define_expand "bleu"
5595   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5596    (set (pc)
5597         (if_then_else (leu (reg:CCU 33) (const_int 0))
5598                       (label_ref (match_operand 0 "" ""))
5599                       (pc)))]
5600   ""
5601   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5602
5603 (define_expand "bunordered"
5604   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5605    (set (pc)
5606         (if_then_else (unordered (reg:CCS 33) (const_int 0))
5607                       (label_ref (match_operand 0 "" ""))
5608                       (pc)))]
5609   ""
5610   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5611
5612 (define_expand "bordered"
5613   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5614    (set (pc)
5615         (if_then_else (ordered (reg:CCS 33) (const_int 0))
5616                       (label_ref (match_operand 0 "" ""))
5617                       (pc)))]
5618   ""
5619   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5620
5621 (define_expand "buneq"
5622   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5623    (set (pc)
5624         (if_then_else (uneq (reg:CCS 33) (const_int 0))
5625                       (label_ref (match_operand 0 "" ""))
5626                       (pc)))]
5627   ""
5628   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5629
5630 (define_expand "bungt"
5631   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5632    (set (pc)
5633         (if_then_else (ungt (reg:CCS 33) (const_int 0))
5634                       (label_ref (match_operand 0 "" ""))
5635                       (pc)))]
5636   ""
5637   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5638
5639 (define_expand "bunlt"
5640   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5641    (set (pc)
5642         (if_then_else (unlt (reg:CCS 33) (const_int 0))
5643                       (label_ref (match_operand 0 "" ""))
5644                       (pc)))]
5645   ""
5646   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5647
5648 (define_expand "bunge"
5649   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5650    (set (pc)
5651         (if_then_else (unge (reg:CCS 33) (const_int 0))
5652                       (label_ref (match_operand 0 "" ""))
5653                       (pc)))]
5654   ""
5655   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5656
5657 (define_expand "bunle"
5658   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5659    (set (pc)
5660         (if_then_else (unle (reg:CCS 33) (const_int 0))
5661                       (label_ref (match_operand 0 "" ""))
5662                       (pc)))]
5663   ""
5664   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5665
5666 (define_expand "bltgt"
5667   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5668    (set (pc)
5669         (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5670                       (label_ref (match_operand 0 "" ""))
5671                       (pc)))]
5672   ""
5673   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5674
5675
5676 ;;
5677 ;;- Conditional jump instructions.
5678 ;;
5679
5680 (define_insn "cjump"
5681  [(set (pc)
5682        (if_then_else
5683          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5684          (label_ref (match_operand 0 "" ""))
5685          (pc)))]
5686   ""
5687   "*
5688 {
5689   if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5690      return \"j%C1\\t%l0\";
5691   else
5692      return \"jg%C1\\t%l0\";
5693 }"
5694   [(set_attr "op_type" "RI")
5695    (set (attr "length") (if_then_else
5696       (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5697       (const_int 4) (const_int 6)))])
5698
5699 (define_insn "*cjump_long"
5700  [(set (pc)
5701        (if_then_else
5702          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5703          (match_operand 0 "address_operand" "p")
5704          (pc)))]
5705   ""
5706   "*
5707 {
5708   if (get_attr_op_type (insn) == OP_TYPE_RR)
5709     return \"b%C1r\\t%0\";
5710   else
5711     return \"b%C1\\t%a0\";
5712 }"
5713   [(set (attr "op_type")
5714         (if_then_else (match_operand 0 "register_operand" "")
5715                       (const_string "RR") (const_string "RX")))
5716    (set_attr "atype" "mem")])
5717
5718
5719 ;;
5720 ;;- Negated conditional jump instructions.
5721 ;;
5722
5723 (define_insn "icjump"
5724  [(set (pc)
5725        (if_then_else
5726          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5727          (pc)
5728          (label_ref (match_operand 0 "" ""))))]
5729   ""
5730   "*
5731 {
5732   if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5733      return \"j%D1\\t%l0\";
5734   else
5735      return \"jg%D1\\t%l0\";
5736 }"
5737   [(set_attr "op_type" "RI")
5738    (set (attr "length") (if_then_else
5739      (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5740      (const_int 4) (const_int 6)))])
5741
5742 (define_insn "*icjump_long"
5743  [(set (pc)
5744        (if_then_else
5745          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5746          (pc)
5747          (match_operand 0 "address_operand" "p")))]
5748   ""
5749   "*
5750 {
5751   if (get_attr_op_type (insn) == OP_TYPE_RR)
5752     return \"b%D1r\\t%0\";
5753   else
5754     return \"b%D1\\t%a0\";
5755 }"
5756   [(set (attr "op_type")
5757         (if_then_else (match_operand 0 "register_operand" "")
5758                       (const_string "RR") (const_string "RX")))
5759    (set_attr "atype" "mem")])
5760
5761
5762 ;;
5763 ;;- Subtract one and jump if not zero.
5764 ;;
5765
5766 ;(define_expand "decrement_and_branch_on_count"
5767 ;  [(use (match_operand 0 "register_operand" ""))
5768 ;   (use (label_ref (match_operand 1 "" "")))]
5769 ;  ""
5770 ;  "
5771 ;{
5772 ;/*  if (TARGET_64BIT)
5773 ;    emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5774 ;  else */
5775 ;    emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5776 ;  DONE;
5777 ;}")
5778 ;
5779 ;(define_insn "brctsi"
5780 ;  [(set (pc)
5781 ;        (if_then_else
5782 ;           (ne (match_operand:SI 0 "register_operand" "+a")
5783 ;               (const_int 1))
5784 ;           (label_ref (match_operand 1 "" ""))
5785 ;           (pc)))
5786 ;   (set (match_dup 0)
5787 ;        (plus:SI (match_dup 0) (const_int -1)))]
5788 ;  ""
5789 ;  "brct\\t%0,%l1"
5790 ;   [(set_attr "op_type" "RI")
5791 ;    (set_attr "type"    "branch")]
5792 ;)
5793 ;
5794 ;(define_insn "ibrctsi"
5795 ;  [(set (pc)
5796 ;        (if_then_else
5797 ;          (eq (match_operand:SI 0 "register_operand" "+a")
5798 ;              (const_int 1))
5799 ;          (pc)
5800 ;          (label_ref (match_operand 1 "" ""))))
5801 ;   (set (match_dup 0)
5802 ;        (plus:SI (match_dup 0) (const_int -1)))]
5803 ;  ""
5804 ;  "brct\\t%0,%l1"
5805 ;   [(set_attr "op_type" "RI")
5806 ;    (set_attr "type"    "branch")]
5807 ;)
5808
5809
5810 ;;
5811 ;;- Unconditional jump instructions.
5812 ;;
5813
5814 ;
5815 ; jump instruction pattern(s).
5816 ;
5817
5818 (define_insn "jump"
5819   [(set (pc) (label_ref (match_operand 0 "" "")))]
5820   ""
5821   "*
5822 {
5823   if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5824      return \"j\\t%l0\";
5825   else
5826      return \"jg\\t%l0\";
5827 }"
5828   [(set_attr "op_type" "RI")
5829    (set (attr "length") (if_then_else
5830      (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5831      (const_int 4) (const_int 6)))])
5832
5833 ;
5834 ; indirect-jump instruction pattern(s).
5835 ;
5836
5837 (define_insn "indirect_jump"
5838  [(set (pc) (match_operand 0 "address_operand" "p"))]
5839   ""
5840   "*
5841 {
5842   if (get_attr_op_type (insn) == OP_TYPE_RR)
5843     return \"br\\t%0\";
5844   else
5845     return \"b\\t%a0\";
5846 }"
5847   [(set (attr "op_type")
5848         (if_then_else (match_operand 0 "register_operand" "")
5849                       (const_string "RR") (const_string "RX")))
5850    (set_attr "atype" "mem")])
5851
5852 ;
5853 ; casesi instruction pattern(s).
5854 ;
5855
5856 (define_insn "casesi_jump"
5857  [(set (pc) (match_operand 0 "address_operand" "p"))
5858    (use (label_ref (match_operand 1 "" "")))]
5859   ""
5860   "*
5861 {
5862   if (get_attr_op_type (insn) == OP_TYPE_RR)
5863     return \"br\\t%0\";
5864   else
5865     return \"b\\t%a0\";
5866 }"
5867   [(set (attr "op_type")
5868         (if_then_else (match_operand 0 "register_operand" "")
5869                       (const_string "RR") (const_string "RX")))
5870    (set_attr "atype" "mem")])
5871
5872 (define_expand "casesi"
5873   [(match_operand:SI 0 "general_operand" "")
5874    (match_operand:SI 1 "general_operand" "")
5875    (match_operand:SI 2 "general_operand" "")
5876    (label_ref (match_operand 3 "" ""))
5877    (label_ref (match_operand 4 "" ""))]
5878   ""
5879   "
5880 {
5881    rtx index  = gen_reg_rtx (SImode);
5882    rtx base   = gen_reg_rtx (Pmode);
5883    rtx target = gen_reg_rtx (Pmode);
5884
5885    emit_move_insn (index, operands[0]);
5886    emit_insn (gen_subsi3 (index, index, operands[1]));
5887    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
5888                             operands[4]);
5889
5890    if (Pmode != SImode)
5891      index = convert_to_mode (Pmode, index, 1);
5892    if (GET_CODE (index) != REG)
5893      index = copy_to_mode_reg (Pmode, index);
5894
5895    if (TARGET_64BIT)
5896        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
5897    else
5898        emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
5899
5900    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
5901
5902    index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
5903    emit_move_insn (target, index);
5904
5905    if (flag_pic)
5906      target = gen_rtx_PLUS (Pmode, base, target);
5907    emit_jump_insn (gen_casesi_jump (target, operands[3]));
5908
5909    DONE;
5910 }")
5911
5912
5913 ;;
5914 ;;- Jump to subroutine.
5915 ;;
5916 ;;
5917
5918 ;
5919 ; untyped call instruction pattern(s).
5920 ;
5921
5922 ;; Call subroutine returning any type.
5923 (define_expand "untyped_call"
5924   [(parallel [(call (match_operand 0 "" "")
5925                     (const_int 0))
5926               (match_operand 1 "" "")
5927               (match_operand 2 "" "")])]
5928   ""
5929   "
5930 {
5931   int i;
5932
5933   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
5934
5935   for (i = 0; i < XVECLEN (operands[2], 0); i++)
5936     {
5937       rtx set = XVECEXP (operands[2], 0, i);
5938       emit_move_insn (SET_DEST (set), SET_SRC (set));
5939     }
5940
5941   /* The optimizer does not know that the call sets the function value
5942      registers we stored in the result block.  We avoid problems by
5943      claiming that all hard registers are used and clobbered at this
5944      point.  */
5945   emit_insn (gen_blockage ());
5946
5947   DONE;
5948 }")
5949
5950 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5951 ;; all of memory.  This blocks insns from being moved across this point.
5952
5953 (define_insn "blockage"
5954   [(unspec_volatile [(const_int 0)] 0)]
5955   ""
5956   ""
5957   [(set_attr "type"    "none")])
5958
5959
5960
5961 ;
5962 ; call instruction pattern(s).
5963 ;
5964
5965 (define_expand "call"
5966   [(parallel [(call (match_operand 0 "" "")
5967                     (match_operand 1 "" ""))
5968               (clobber (match_operand 2 "" ""))])]
5969   ""
5970   "
5971 {
5972   /* Abuse operand 2 to hold the return register.  */
5973   operands[2] = gen_rtx_REG (Pmode, RETURN_REGNUM);
5974
5975   /* In 31-bit, we must load the GOT register even if the
5976      compiler doesn't know about it, because the PLT glue
5977      code uses it.  In 64-bit, this is not necessary.  */
5978   if (flag_pic && !TARGET_64BIT)
5979     current_function_uses_pic_offset_table = 1;
5980
5981   /* Direct function calls need special treatment.  */
5982   if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5983     {
5984       rtx sym = XEXP (operands[0], 0);
5985
5986       /* When calling a global routine in PIC mode, we must
5987          replace the symbol itself with the PLT stub.  */
5988       if (flag_pic && !SYMBOL_REF_FLAG(sym))
5989         {
5990           sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5991           sym = gen_rtx_CONST (Pmode, sym);
5992         }
5993
5994       /* Unless we can use the bras(l) insn, force the
5995          routine address into a register.  */
5996       if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
5997         {
5998           rtx target = gen_reg_rtx (Pmode);
5999           emit_move_insn (target, sym);
6000           sym = target;
6001         }
6002
6003       operands[0] = gen_rtx_MEM (QImode, sym);
6004     }
6005 }")
6006
6007 (define_insn "brasl"
6008   [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6009          (match_operand:SI 1 "const_int_operand" "n"))
6010    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6011   "TARGET_64BIT"
6012   "brasl\\t%2,%0"
6013   [(set_attr "op_type" "RIL")
6014    (set_attr "type"    "jsr")])
6015
6016 (define_insn "bras"
6017   [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6018          (match_operand:SI 1 "const_int_operand" "n"))
6019    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6020   "TARGET_SMALL_EXEC"
6021   "bras\\t%2,%0"
6022   [(set_attr "op_type" "RI")
6023    (set_attr "type"    "jsr")])
6024
6025 (define_insn "basr_64"
6026   [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6027          (match_operand:SI 1 "const_int_operand" "n"))
6028    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6029   "TARGET_64BIT"
6030   "basr\\t%2,%0"
6031   [(set_attr "op_type" "RR")
6032    (set_attr "type"    "jsr")
6033    (set_attr "atype"   "mem")])
6034
6035 (define_insn "basr_31"
6036   [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6037          (match_operand:SI 1 "const_int_operand" "n"))
6038    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6039   "!TARGET_64BIT"
6040   "basr\\t%2,%0"
6041   [(set_attr "op_type" "RR")
6042    (set_attr "type"    "jsr")
6043    (set_attr "atype"    "mem")])
6044
6045 (define_insn "bas_64"
6046   [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6047          (match_operand:SI 1 "const_int_operand" "n"))
6048    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6049   "TARGET_64BIT"
6050   "bas\\t%2,%a0"
6051   [(set_attr "op_type" "RX")
6052    (set_attr "type"    "jsr")
6053    (set_attr "atype"   "mem")])
6054
6055 (define_insn "bas_31"
6056   [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6057          (match_operand:SI 1 "const_int_operand" "n"))
6058    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6059   "!TARGET_64BIT"
6060   "bas\\t%2,%a0"
6061   [(set_attr "op_type" "RX")
6062    (set_attr "type"    "jsr")
6063    (set_attr "atype"   "mem")])
6064
6065
6066 ;
6067 ; call_value instruction pattern(s).
6068 ;
6069
6070 (define_expand "call_value"
6071   [(parallel [(set (match_operand 0 "" "")
6072                    (call (match_operand 1 "" "")
6073                          (match_operand 2 "" "")))
6074               (clobber (match_operand 3 "" ""))])]
6075   ""
6076   "
6077 {
6078   /* Abuse operand 3 to hold the return register.  */
6079   operands[3] = gen_rtx_REG (Pmode, RETURN_REGNUM);
6080
6081   /* In 31-bit, we must load the GOT register even if the
6082      compiler doesn't know about it, because the PLT glue
6083      code uses it.  In 64-bit, this is not necessary.  */
6084   if (flag_pic && !TARGET_64BIT)
6085     current_function_uses_pic_offset_table = 1;
6086
6087   /* Direct function calls need special treatment.  */
6088   if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6089     {
6090       rtx sym = XEXP (operands[1], 0);
6091
6092       /* When calling a global routine in PIC mode, we must
6093          replace the symbol itself with the PLT stub.  */
6094       if (flag_pic && !SYMBOL_REF_FLAG(sym))
6095         {
6096           sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6097           sym = gen_rtx_CONST (Pmode, sym);
6098         }
6099
6100       /* Unless we can use the bras(l) insn, force the
6101          routine address into a register.  */
6102       if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6103         {
6104           rtx target = gen_reg_rtx (Pmode);
6105           emit_move_insn (target, sym);
6106           sym = target;
6107         }
6108
6109       operands[1] = gen_rtx_MEM (QImode, sym);
6110     }
6111 }")
6112
6113 (define_insn "brasl_r"
6114   [(set (match_operand 0 "register_operand" "=df")
6115         (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6116               (match_operand:SI 2 "const_int_operand" "n")))
6117    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6118   "TARGET_64BIT"
6119   "brasl\\t%3,%1"
6120   [(set_attr "op_type" "RIL")
6121    (set_attr "type"    "jsr")])
6122
6123 (define_insn "bras_r"
6124   [(set (match_operand 0 "register_operand" "=df")
6125         (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6126               (match_operand:SI 2 "const_int_operand" "n")))
6127    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6128   "TARGET_SMALL_EXEC"
6129   "bras\\t%3,%1"
6130   [(set_attr "op_type" "RI")
6131    (set_attr "type"    "jsr")])
6132
6133 (define_insn "basr_r_64"
6134   [(set (match_operand 0 "register_operand" "=df")
6135         (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6136               (match_operand:SI 2 "const_int_operand" "n")))
6137    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6138   "TARGET_64BIT"
6139   "basr\\t%3,%1"
6140   [(set_attr "op_type" "RR")
6141    (set_attr "type"    "jsr")])
6142
6143 (define_insn "basr_r_31"
6144   [(set (match_operand 0 "register_operand" "=df")
6145         (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6146               (match_operand:SI 2 "const_int_operand" "n")))
6147    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6148   "!TARGET_64BIT"
6149   "basr\\t%3,%1"
6150   [(set_attr "op_type" "RR")
6151    (set_attr "type"    "jsr")
6152    (set_attr "atype"   "mem")])
6153
6154 (define_insn "bas_r_64"
6155   [(set (match_operand 0 "register_operand" "=df")
6156         (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6157               (match_operand:SI 2 "const_int_operand" "n")))
6158    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6159   "TARGET_64BIT"
6160   "bas\\t%3,%a1"
6161   [(set_attr "op_type" "RX")
6162    (set_attr "type"    "jsr")
6163    (set_attr "atype"   "mem")])
6164
6165 (define_insn "bas_r_31"
6166   [(set (match_operand 0 "register_operand" "=df")
6167         (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6168               (match_operand:SI 2 "const_int_operand" "n")))
6169    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6170   "!TARGET_64BIT"
6171   "bas\\t%3,%a1"
6172    [(set_attr "op_type" "RX")
6173     (set_attr "type"    "jsr")
6174     (set_attr "atype"   "mem")])
6175
6176
6177 ;;
6178 ;;- Miscellaneous instructions.
6179 ;;
6180
6181 ;
6182 ; allocate stack instruction pattern(s).
6183 ;
6184
6185 (define_expand "allocate_stack"
6186   [(set (reg 15)
6187         (plus (reg 15) (match_operand 1 "general_operand" "")))
6188    (set (match_operand 0 "general_operand" "")
6189         (reg 15))]
6190  ""
6191  "
6192 {
6193     rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6194     rtx chain = gen_rtx (MEM, Pmode, stack);
6195     rtx temp = gen_reg_rtx (Pmode);
6196
6197     emit_move_insn (temp, chain);
6198
6199     if (TARGET_64BIT)
6200       emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6201     else
6202       emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6203
6204     emit_move_insn (chain, temp);
6205
6206     emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6207     DONE;
6208 }")
6209
6210
6211 ;
6212 ; setjmp/longjmp instruction pattern(s).
6213 ;
6214
6215 (define_expand "builtin_setjmp_setup"
6216   [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6217   ""
6218   "
6219 {
6220   rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6221   rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6222
6223   emit_move_insn (base, basereg);
6224   DONE;
6225 }")
6226
6227 (define_expand "builtin_setjmp_receiver"
6228   [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6229   "flag_pic"
6230   "
6231 {
6232   rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6233   rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6234   SYMBOL_REF_FLAG (got) = 1;
6235
6236   emit_move_insn (gotreg, got);
6237   emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6238   DONE;
6239 }")
6240
6241 (define_expand "builtin_longjmp"
6242   [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6243   ""
6244   "
6245 {
6246   /* The elements of the buffer are, in order:  */
6247   rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6248   rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6249   rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6250   rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6251   rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6252   rtx jmp = gen_rtx_REG (Pmode, 14);
6253
6254   emit_move_insn (jmp, lab);
6255   emit_move_insn (basereg, base);
6256   emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6257   emit_move_insn (hard_frame_pointer_rtx, fp);
6258
6259   emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6260   emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6261   emit_insn (gen_rtx_USE (VOIDmode, basereg));
6262   emit_indirect_jump (jmp);
6263   DONE;
6264 }")
6265
6266
6267 ;; These patterns say how to save and restore the stack pointer.  We need not
6268 ;; save the stack pointer at function level since we are careful to
6269 ;; preserve the backchain.  At block level, we have to restore the backchain
6270 ;; when we restore the stack pointer.
6271 ;;
6272 ;; For nonlocal gotos, we must save both the stack pointer and its
6273 ;; backchain and restore both.  Note that in the nonlocal case, the
6274 ;; save area is a memory location.
6275
6276 (define_expand "save_stack_function"
6277   [(match_operand 0 "general_operand" "")
6278    (match_operand 1 "general_operand" "")]
6279   ""
6280   "DONE;")
6281
6282 (define_expand "restore_stack_function"
6283   [(match_operand 0 "general_operand" "")
6284    (match_operand 1 "general_operand" "")]
6285   ""
6286   "DONE;")
6287
6288 (define_expand "restore_stack_block"
6289   [(use (match_operand 0 "register_operand" ""))
6290    (set (match_dup 2) (match_dup 3))
6291    (set (match_dup 0) (match_operand 1 "register_operand" ""))
6292    (set (match_dup 3) (match_dup 2))]
6293   ""
6294   "
6295 {
6296   operands[2] = gen_reg_rtx (Pmode);
6297   operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6298 }")
6299
6300 (define_expand "save_stack_nonlocal"
6301   [(match_operand 0 "memory_operand" "")
6302    (match_operand 1 "register_operand" "")]
6303   ""
6304   "
6305 {
6306   rtx temp = gen_reg_rtx (Pmode);
6307
6308   /* Copy the backchain to the first word, sp to the second.  */
6309   emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6310   emit_move_insn (operand_subword (operands[0], 0, 0,
6311                  TARGET_64BIT ? TImode : DImode),
6312                  temp);
6313   emit_move_insn (operand_subword (operands[0], 1, 0,
6314                  TARGET_64BIT ? TImode : DImode),
6315                  operands[1]);
6316   DONE;
6317 }")
6318
6319 (define_expand "restore_stack_nonlocal"
6320   [(match_operand 0 "register_operand" "")
6321    (match_operand 1 "memory_operand" "")]
6322   ""
6323   "
6324 {
6325   rtx temp = gen_reg_rtx (Pmode);
6326
6327   /* Restore the backchain from the first word, sp from the second.  */
6328   emit_move_insn (temp,
6329                  operand_subword (operands[1], 0, 0,
6330                  TARGET_64BIT ? TImode : DImode));
6331   emit_move_insn (operands[0],
6332                  operand_subword (operands[1], 1, 0,
6333                  TARGET_64BIT ? TImode : DImode));
6334   emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6335   DONE;
6336 }")
6337
6338
6339 ;
6340 ; nop instruction pattern(s).
6341 ;
6342
6343 (define_insn "nop"
6344   [(const_int 0)]
6345   ""
6346   "lr\\t0,0"
6347   [(set_attr "op_type" "RR")])
6348
6349
6350 ;
6351 ; Special literal pool access instruction pattern(s).
6352 ;
6353
6354 (define_insn "reload_base"
6355   [(parallel [(set (reg 13) (pc))
6356               (use (label_ref (match_operand 0 "" "")))])]
6357   ""
6358   "*
6359 {
6360   if (TARGET_64BIT)
6361     return \"larl\\t13,%y0\";
6362   else
6363     return \"basr\\t13,0\;ahi\\t13,%Y0\";
6364 }"
6365   [(set_attr "op_type" "NN")
6366    (set_attr "type"    "la")
6367    (set_attr "length"  "8")])
6368
6369 (define_insn "ltorg"
6370   [(parallel [(set (reg 13) (pc))
6371               (use (match_operand:SI 0 "const_int_operand" ""))])]
6372   ""
6373   "*
6374 {
6375    s390_dump_literal_pool (insn, operands[0]);
6376    return \"0:\";
6377 }"
6378   [(set_attr "op_type" "NN")
6379    (set_attr "type"    "other")
6380    (set_attr "length"  "4096")])
6381
6382 ;;
6383 ;; Insns related to generating the function prologue and epilogue.
6384 ;;
6385
6386
6387 (define_expand "prologue"
6388   [(use (const_int 0))]
6389   ""
6390   "
6391 {
6392       s390_emit_prologue ();
6393       DONE;
6394 }")
6395
6396 (define_expand "epilogue"
6397   [(use (const_int 1))]
6398   ""
6399   "
6400 {
6401       s390_emit_epilogue ();
6402       DONE;
6403 }")
6404
6405
6406 (define_insn "*return_si"
6407   [(return)
6408    (use (match_operand:SI 0 "register_operand" "a"))]
6409   "!TARGET_64BIT"
6410   "br\\t%0"
6411   [(set_attr "op_type" "RR")
6412    (set_attr "type"    "jsr")
6413    (set_attr "atype"   "mem")])
6414
6415 (define_insn "*return_di"
6416   [(return)
6417    (use (match_operand:DI 0 "register_operand" "a"))]
6418   "TARGET_64BIT"
6419   "br\\t%0"
6420   [(set_attr "op_type" "RR")
6421    (set_attr "type"    "jsr")
6422    (set_attr "atype"   "mem")])
6423
6424
6425 (define_insn "lit"
6426   [(set (reg 13) (pc))
6427    (unspec_volatile [(const_int 0)] 200)]
6428   ""
6429   "*
6430 {
6431    s390_output_constant_pool (asm_out_file);
6432    return \"\";
6433 }"
6434   [(set_attr "op_type" "NN")
6435    (set_attr "type"    "integer")])
6436
6437
6438 ;;
6439 ;; Peephole optimization patterns.
6440 ;;
6441
6442 (define_peephole
6443   [(set (match_operand:SI 0 "memory_operand" "m")
6444         (match_operand:SI 1 "register_operand" "d"))
6445    (set (match_dup 1)
6446         (match_dup 0))]
6447  ""
6448  "st\\t%1,%0")
6449
6450 (define_peephole
6451   [(set (match_operand:SI 0 "memory_operand" "m")
6452         (match_operand:SI 1 "register_operand" "d"))
6453    (set (match_dup 0)
6454         (match_dup 1))]
6455  ""
6456  "st\\t%1,%0")
6457
6458 (define_peephole
6459   [(set (match_operand:SI 0 "register_operand" "")
6460         (match_operand:SI 1 "register_operand" ""))
6461    (parallel
6462     [(set (match_dup 0)
6463           (plus:SI (match_dup 0)
6464                    (match_operand:SI 2 "immediate_operand" "")))
6465      (clobber (reg:CC 33))])]
6466  "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6467    REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6468    REGNO (operands[0]) == BASE_REGISTER ||
6469    REGNO (operands[1]) == BASE_REGISTER) &&
6470   INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6471  "la\\t%0,%c2(%1)")
6472
6473 ;
6474 ; peepholes for fast char instructions
6475 ;
6476
6477 ;(define_peephole
6478 ;  [(set (match_operand:QI 0 "register_operand" "d")
6479 ;        (match_operand:QI 1 "s_operand" "Q"))
6480 ;  (set  (match_operand:SI 2 "register_operand" "0")
6481 ;        (zero_extend:SI (match_dup 0)))]
6482 ; "REGNO(operands[0]) == REGNO(operands[2])"
6483 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6484
6485 ;(define_peephole
6486 ;  [(set (match_operand:QI 0 "register_operand" "d")
6487 ;        (match_operand:QI 1 "s_operand" "Q"))
6488 ;   (set (match_operand:SI 2 "register_operand" "0")
6489 ;        (sign_extend:SI (match_dup 0)))]
6490 ; "REGNO(operands[0]) == REGNO(operands[2])"
6491 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6492
6493 (define_peephole
6494   [(set (match_operand:QI 0 "register_operand" "d")
6495         (match_operand:QI 1 "immediate_operand" "J"))
6496    (set (match_operand:SI 2 "register_operand" "0" )
6497         (sign_extend:SI (match_dup 0) ) )]
6498  "REGNO(operands[0]) == REGNO(operands[2])"
6499  "lhi\\t%0,%h1")
6500
6501 ;
6502 ; peepholes for fast short instructions
6503 ;
6504
6505 ;(define_peephole
6506 ;  [(set (match_operand:HI 0 "register_operand" "d")
6507 ;        (match_operand:HI 1 "s_operand" "Q"))
6508 ;   (set (match_operand:SI 2 "register_operand" "0" )
6509 ;        (zero_extend:SI (match_dup 0)))]
6510 ; "REGNO(operands[0]) == REGNO(operands[2])"
6511 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6512
6513 (define_peephole
6514   [(set (match_operand:HI 0 "register_operand" "d")
6515         (match_operand:HI 1 "memory_operand" "m"))
6516    (set (match_operand:SI 2 "register_operand" "0" )
6517         (sign_extend:SI (match_dup 0)))]
6518  "REGNO(operands[0]) == REGNO(operands[2])"
6519  "lh\\t%0,%1")
6520
6521 (define_peephole
6522   [(set (match_operand:HI 0 "register_operand" "d")
6523         (match_operand:HI 1 "immediate_operand" "K"))
6524    (set (match_operand:SI 2 "register_operand" "0" )
6525         (sign_extend:SI (match_dup 0) ) )]
6526  "REGNO(operands[0]) == REGNO(operands[2])"
6527  "lhi\\t%0,%h1")
6528
6529 ;
6530 ; peepholes for divide instructions
6531 ;
6532
6533 (define_peephole
6534   [(set (match_operand:DI 0 "register_operand" "d")
6535         (match_operand:DI 1 "memory_operand" "m"))
6536    (set (match_dup 0)
6537         (lshiftrt:DI (match_dup 0)
6538         (match_operand:SI 2 "immediate_operand" "J")))
6539    (set (match_dup 0)
6540         (div:SI (match_dup 0)
6541         (match_operand:SI 3 "nonimmediate_operand" "g")))
6542    (set (match_dup 1)
6543         (match_dup 0))]
6544   ""
6545   "*
6546 {
6547    output_asm_insn (\"l\\t%0,%1\", operands);
6548    output_asm_insn (\"srdl\\t%0,%b2\", operands);
6549
6550    if (REG_P (operands[3]))
6551      output_asm_insn (\"dr\\t%0,%3\", operands);
6552    else
6553      output_asm_insn (\"d\\t%0,%3\", operands);
6554
6555    return \"st\\t%N0,%N1\";
6556 }")
6557
6558 (define_peephole
6559   [(set (match_operand:DI 0 "register_operand" "d")
6560         (match_operand:DI 1 "memory_operand" "m"))
6561    (set (match_dup 0)
6562         (lshiftrt:DI (match_dup 0)
6563         (match_operand:SI 2 "immediate_operand" "J")))
6564    (set (match_dup 0)
6565         (mod:SI (match_dup 0)
6566         (match_operand:SI 3 "nonimmediate_operand" "g")))
6567    (set (match_dup 1)
6568         (match_dup 0))]
6569   ""
6570   "*
6571 {
6572    output_asm_insn (\"l\\t%0,%1\", operands);
6573    output_asm_insn (\"srdl\\t%0,%b2\", operands);
6574
6575    if (REG_P (operands[3]))
6576      output_asm_insn (\"dr\\t%0,%3\", operands);
6577    else
6578      output_asm_insn (\"d\\t%0,%3\", operands);
6579
6580    return \"st\\t%0,%1\";
6581 }")
6582