gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999-2015 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com) and
   5 ;;                 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify it under
  10 ;; the terms of the GNU General Public License as published by the Free
  11 ;; Software Foundation; either version 3, or (at your option) any later
  12 ;; version.
  13
  14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 ;; for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;;
  24 ;; See constraints.md for a description of constraints specific to s390.
  25 ;;
  26
  27 ;; Special formats used for outputting 390 instructions.
  28 ;;
  29 ;;     %C: print opcode suffix for branch condition.
  30 ;;     %D: print opcode suffix for inverse branch condition.
  31 ;;     %J: print tls_load/tls_gdcall/tls_ldcall suffix
  32 ;;     %G: print the size of the operand in bytes.
  33 ;;     %O: print only the displacement of a memory reference.
  34 ;;     %R: print only the base register of a memory reference.
  35 ;;     %S: print S-type memory reference (base+displacement).
  36 ;;     %N: print the second word of a DImode operand.
  37 ;;     %M: print the second word of a TImode operand.
  38 ;;     %Y: print shift count operand.
  39 ;;
  40 ;;     %b: print integer X as if it's an unsigned byte.
  41 ;;     %c: print integer X as if it's an signed byte.
  42 ;;     %x: print integer X as if it's an unsigned halfword.
  43 ;;     %h: print integer X as if it's a signed halfword.
  44 ;;     %i: print the first nonzero HImode part of X.
  45 ;;     %j: print the first HImode part unequal to -1 of X.
  46 ;;     %k: print the first nonzero SImode part of X.
  47 ;;     %m: print the first SImode part unequal to -1 of X.
  48 ;;     %o: print integer X as if it's an unsigned 32bit word.
  49 ;;
  50 ;; We have a special constraint for pattern matching.
  51 ;;
  52 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  53 ;;
  54
  55 ;;
  56 ;; UNSPEC usage
  57 ;;
  58
  59 (define_c_enum "unspec" [
  60    ; Miscellaneous
  61    UNSPEC_ROUND
  62    UNSPEC_ICM
  63    UNSPEC_TIE
  64
  65    ; Convert CC into a str comparison result and copy it into an
  66    ; integer register
  67    ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
  68    UNSPEC_STRCMPCC_TO_INT
  69
  70    ; Copy CC as is into the lower 2 bits of an integer register
  71    UNSPEC_CC_TO_INT
  72
  73    ; GOT/PLT and lt-relative accesses
  74    UNSPEC_LTREL_OFFSET
  75    UNSPEC_LTREL_BASE
  76    UNSPEC_POOL_OFFSET
  77    UNSPEC_GOTENT
  78    UNSPEC_GOT
  79    UNSPEC_GOTOFF
  80    UNSPEC_PLT
  81    UNSPEC_PLTOFF
  82
  83    ; Literal pool
  84    UNSPEC_RELOAD_BASE
  85    UNSPEC_MAIN_BASE
  86    UNSPEC_LTREF
  87    UNSPEC_INSN
  88    UNSPEC_EXECUTE
  89
  90    ; Atomic Support
  91    UNSPEC_MB
  92    UNSPEC_MOVA
  93
  94    ; TLS relocation specifiers
  95    UNSPEC_TLSGD
  96    UNSPEC_TLSLDM
  97    UNSPEC_NTPOFF
  98    UNSPEC_DTPOFF
  99    UNSPEC_GOTNTPOFF
 100    UNSPEC_INDNTPOFF
 101
 102    ; TLS support
 103    UNSPEC_TLSLDM_NTPOFF
 104    UNSPEC_TLS_LOAD
 105
 106    ; String Functions
 107    UNSPEC_SRST
 108    UNSPEC_MVST
 109
 110    ; Stack Smashing Protector
 111    UNSPEC_SP_SET
 112    UNSPEC_SP_TEST
 113
 114    ; Test Data Class (TDC)
 115    UNSPEC_TDC_INSN
 116
 117    ; Population Count
 118    UNSPEC_POPCNT
 119    UNSPEC_COPYSIGN
 120
 121    ; Load FP Integer
 122    UNSPEC_FPINT_FLOOR
 123    UNSPEC_FPINT_BTRUNC
 124    UNSPEC_FPINT_ROUND
 125    UNSPEC_FPINT_CEIL
 126    UNSPEC_FPINT_NEARBYINT
 127    UNSPEC_FPINT_RINT
 128
 129    UNSPEC_LCBB
 130
 131    ; Vector
 132    UNSPEC_VEC_SMULT_HI
 133    UNSPEC_VEC_UMULT_HI
 134    UNSPEC_VEC_SMULT_LO
 135    UNSPEC_VEC_SMULT_EVEN
 136    UNSPEC_VEC_UMULT_EVEN
 137    UNSPEC_VEC_SMULT_ODD
 138    UNSPEC_VEC_UMULT_ODD
 139
 140    UNSPEC_VEC_VMAL
 141    UNSPEC_VEC_VMAH
 142    UNSPEC_VEC_VMALH
 143    UNSPEC_VEC_VMAE
 144    UNSPEC_VEC_VMALE
 145    UNSPEC_VEC_VMAO
 146    UNSPEC_VEC_VMALO
 147
 148    UNSPEC_VEC_GATHER
 149    UNSPEC_VEC_EXTRACT
 150    UNSPEC_VEC_INSERT_AND_ZERO
 151    UNSPEC_VEC_LOAD_BNDRY
 152    UNSPEC_VEC_LOAD_LEN
 153    UNSPEC_VEC_MERGEH
 154    UNSPEC_VEC_MERGEL
 155    UNSPEC_VEC_PACK
 156    UNSPEC_VEC_PACK_SATURATE
 157    UNSPEC_VEC_PACK_SATURATE_CC
 158    UNSPEC_VEC_PACK_SATURATE_GENCC
 159    UNSPEC_VEC_PACK_UNSIGNED_SATURATE
 160    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
 161    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
 162    UNSPEC_VEC_PERM
 163    UNSPEC_VEC_PERMI
 164    UNSPEC_VEC_EXTEND
 165    UNSPEC_VEC_STORE_LEN
 166    UNSPEC_VEC_UNPACKH
 167    UNSPEC_VEC_UNPACKH_L
 168    UNSPEC_VEC_UNPACKL
 169    UNSPEC_VEC_UNPACKL_L
 170    UNSPEC_VEC_ADDC
 171    UNSPEC_VEC_ADDC_U128
 172    UNSPEC_VEC_ADDE_U128
 173    UNSPEC_VEC_ADDEC_U128
 174    UNSPEC_VEC_AVG
 175    UNSPEC_VEC_AVGU
 176    UNSPEC_VEC_CHECKSUM
 177    UNSPEC_VEC_GFMSUM
 178    UNSPEC_VEC_GFMSUM_128
 179    UNSPEC_VEC_GFMSUM_ACCUM
 180    UNSPEC_VEC_GFMSUM_ACCUM_128
 181    UNSPEC_VEC_SET
 182
 183    UNSPEC_VEC_VSUMG
 184    UNSPEC_VEC_VSUMQ
 185    UNSPEC_VEC_VSUM
 186    UNSPEC_VEC_RL_MASK
 187    UNSPEC_VEC_SLL
 188    UNSPEC_VEC_SLB
 189    UNSPEC_VEC_SLDB
 190    UNSPEC_VEC_SRAL
 191    UNSPEC_VEC_SRAB
 192    UNSPEC_VEC_SRL
 193    UNSPEC_VEC_SRLB
 194
 195    UNSPEC_VEC_SUB_U128
 196    UNSPEC_VEC_SUBC
 197    UNSPEC_VEC_SUBC_U128
 198    UNSPEC_VEC_SUBE_U128
 199    UNSPEC_VEC_SUBEC_U128
 200
 201    UNSPEC_VEC_TEST_MASK
 202
 203    UNSPEC_VEC_VFAE
 204    UNSPEC_VEC_VFAECC
 205
 206    UNSPEC_VEC_VFEE
 207    UNSPEC_VEC_VFEECC
 208    UNSPEC_VEC_VFENE
 209    UNSPEC_VEC_VFENECC
 210
 211    UNSPEC_VEC_VISTR
 212    UNSPEC_VEC_VISTRCC
 213
 214    UNSPEC_VEC_VSTRC
 215    UNSPEC_VEC_VSTRCCC
 216
 217    UNSPEC_VEC_VCDGB
 218    UNSPEC_VEC_VCDLGB
 219
 220    UNSPEC_VEC_VCGDB
 221    UNSPEC_VEC_VCLGDB
 222
 223    UNSPEC_VEC_VFIDB
 224
 225    UNSPEC_VEC_VLDEB
 226    UNSPEC_VEC_VLEDB
 227
 228    UNSPEC_VEC_VFTCIDB
 229    UNSPEC_VEC_VFTCIDBCC
 230 ])
 231
 232 ;;
 233 ;; UNSPEC_VOLATILE usage
 234 ;;
 235
 236 (define_c_enum "unspecv" [
 237    ; Blockage
 238    UNSPECV_BLOCKAGE
 239
 240    ; TPF Support
 241    UNSPECV_TPF_PROLOGUE
 242    UNSPECV_TPF_EPILOGUE
 243
 244    ; Literal pool
 245    UNSPECV_POOL
 246    UNSPECV_POOL_SECTION
 247    UNSPECV_POOL_ALIGN
 248    UNSPECV_POOL_ENTRY
 249    UNSPECV_MAIN_POOL
 250
 251    ; TLS support
 252    UNSPECV_SET_TP
 253
 254    ; Atomic Support
 255    UNSPECV_CAS
 256    UNSPECV_ATOMIC_OP
 257
 258    ; Hotpatching (unremovable NOPs)
 259    UNSPECV_NOP_2_BYTE
 260    UNSPECV_NOP_4_BYTE
 261    UNSPECV_NOP_6_BYTE
 262
 263    ; Transactional Execution support
 264    UNSPECV_TBEGIN
 265    UNSPECV_TBEGIN_TDB
 266    UNSPECV_TBEGINC
 267    UNSPECV_TEND
 268    UNSPECV_TABORT
 269    UNSPECV_ETND
 270    UNSPECV_NTSTG
 271    UNSPECV_PPA
 272
 273    ; Set and get floating point control register
 274    UNSPECV_SFPC
 275    UNSPECV_EFPC
 276   ])
 277
 278 ;;
 279 ;; Registers
 280 ;;
 281
 282 ; Registers with special meaning
 283
 284 (define_constants
 285   [
 286    ; Sibling call register.
 287    (SIBCALL_REGNUM               1)
 288    ; Literal pool base register.
 289    (BASE_REGNUM                 13)
 290    ; Return address register.
 291    (RETURN_REGNUM               14)
 292    ; Condition code register.
 293    (CC_REGNUM                   33)
 294    ; Thread local storage pointer register.
 295    (TP_REGNUM                   36)
 296   ])
 297
 298 ; Hardware register names
 299
 300 (define_constants
 301   [
 302    ; General purpose registers
 303    (GPR0_REGNUM                  0)
 304    (GPR1_REGNUM                  1)
 305    ; Floating point registers.
 306    (FPR0_REGNUM                 16)
 307    (FPR1_REGNUM                 20)
 308    (FPR2_REGNUM                 17)
 309    (FPR3_REGNUM                 21)
 310    (FPR4_REGNUM                 18)
 311    (FPR5_REGNUM                 22)
 312    (FPR6_REGNUM                 19)
 313    (FPR7_REGNUM                 23)
 314    (FPR8_REGNUM                 24)
 315    (FPR9_REGNUM                 28)
 316    (FPR10_REGNUM                25)
 317    (FPR11_REGNUM                29)
 318    (FPR12_REGNUM                26)
 319    (FPR13_REGNUM                30)
 320    (FPR14_REGNUM                27)
 321    (FPR15_REGNUM                31)
 322    (VR0_REGNUM                  16)
 323    (VR16_REGNUM                 38)
 324    (VR23_REGNUM                 45)
 325    (VR24_REGNUM                 46)
 326    (VR31_REGNUM                 53)
 327   ])
 328
 329 ;;
 330 ;; PFPO GPR0 argument format
 331 ;;
 332
 333 (define_constants
 334   [
 335    ; PFPO operation type
 336    (PFPO_CONVERT          0x1000000)
 337    ; PFPO operand types
 338    (PFPO_OP_TYPE_SF             0x5)
 339    (PFPO_OP_TYPE_DF             0x6)
 340    (PFPO_OP_TYPE_TF             0x7)
 341    (PFPO_OP_TYPE_SD             0x8)
 342    (PFPO_OP_TYPE_DD             0x9)
 343    (PFPO_OP_TYPE_TD             0xa)
 344    ; Bitposition of operand types
 345    (PFPO_OP0_TYPE_SHIFT          16)
 346    (PFPO_OP1_TYPE_SHIFT           8)
 347   ])
 348
 349 ; Immediate operands for tbegin and tbeginc
 350 (define_constants [(TBEGIN_MASK  65292)]) ; 0xff0c
 351 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
 352
 353 ;; Instruction operand type as used in the Principles of Operation.
 354 ;; Used to determine defaults for length and other attribute values.
 355
 356 (define_attr "op_type"
 357   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
 358   (const_string "NN"))
 359
 360 ;; Instruction type attribute used for scheduling.
 361
 362 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
 363                      cs,vs,store,sem,idiv,
 364                      imulhi,imulsi,imuldi,
 365                      branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
 366                      floadtf,floaddf,floadsf,fstoredf,fstoresf,
 367                      fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
 368                      ftoi,fsqrttf,fsqrtdf,fsqrtsf,
 369                      fmadddf,fmaddsf,
 370                      ftrunctf,ftruncdf, ftruncsd, ftruncdd,
 371                      itoftf, itofdf, itofsf, itofdd, itoftd,
 372                      fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
 373                      fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
 374                      ftoidfp, other"
 375   (cond [(eq_attr "op_type" "NN")  (const_string "other")
 376          (eq_attr "op_type" "SS")  (const_string "cs")]
 377     (const_string "integer")))
 378
 379 ;; Another attribute used for scheduling purposes:
 380 ;;   agen: Instruction uses the address generation unit
 381 ;;   reg: Instruction does not use the agen unit
 382
 383 (define_attr "atype" "agen,reg"
 384   (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
 385                 (const_string "reg")
 386                 (const_string "agen")))
 387
 388 ;; Properties concerning Z10 execution grouping and value forwarding.
 389 ;; z10_super: instruction is superscalar.
 390 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
 391 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
 392 ;;   target register.  It can forward this value to a second instruction that reads
 393 ;;   the same register if that second instruction is issued in the same group.
 394 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
 395 ;;   instruction in the S pipe writes to the register, then the T instruction
 396 ;;   can immediately read the new value.
 397 ;; z10_fr: union of Z10_fwd and z10_rec.
 398 ;; z10_c: second operand of instruction is a register and read with complemented bits.
 399 ;;
 400 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
 401
 402
 403 (define_attr "z10prop" "none,
 404                         z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
 405                         z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
 406                         z10_rec,
 407                         z10_fr, z10_fr_A3, z10_fr_E1,
 408                         z10_c"
 409              (const_string "none"))
 410
 411 ;; Properties concerning Z196 decoding
 412 ;; z196_alone: must group alone
 413 ;; z196_end: ends a group
 414 ;; z196_cracked: instruction is cracked or expanded
 415 (define_attr "z196prop" "none,
 416                          z196_alone, z196_ends,
 417                          z196_cracked"
 418              (const_string "none"))
 419
 420 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
 421
 422 ;; Length in bytes.
 423
 424 (define_attr "length" ""
 425   (cond [(eq_attr "op_type" "E,RR")                           (const_int 2)
 426          (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR")  (const_int 4)]
 427     (const_int 6)))
 428
 429
 430 ;; Processor type.  This attribute must exactly match the processor_type
 431 ;; enumeration in s390.h.  The current machine description does not
 432 ;; distinguish between g5 and g6, but there are differences between the two
 433 ;; CPUs could in theory be modeled.
 434
 435 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
 436   (const (symbol_ref "s390_tune_attr")))
 437
 438 (define_attr "cpu_facility"
 439   "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
 440   (const_string "standard"))
 441
 442 (define_attr "enabled" ""
 443   (cond [(eq_attr "cpu_facility" "standard")
 444          (const_int 1)
 445
 446          (and (eq_attr "cpu_facility" "ieee")
 447               (match_test "TARGET_CPU_IEEE_FLOAT"))
 448          (const_int 1)
 449
 450          (and (eq_attr "cpu_facility" "zarch")
 451               (match_test "TARGET_ZARCH"))
 452          (const_int 1)
 453
 454          (and (eq_attr "cpu_facility" "longdisp")
 455               (match_test "TARGET_LONG_DISPLACEMENT"))
 456          (const_int 1)
 457
 458          (and (eq_attr "cpu_facility" "extimm")
 459               (match_test "TARGET_EXTIMM"))
 460          (const_int 1)
 461
 462          (and (eq_attr "cpu_facility" "dfp")
 463               (match_test "TARGET_DFP"))
 464          (const_int 1)
 465
 466          (and (eq_attr "cpu_facility" "cpu_zarch")
 467               (match_test "TARGET_CPU_ZARCH"))
 468          (const_int 1)
 469
 470          (and (eq_attr "cpu_facility" "z10")
 471               (match_test "TARGET_Z10"))
 472          (const_int 1)
 473
 474          (and (eq_attr "cpu_facility" "z196")
 475               (match_test "TARGET_Z196"))
 476          (const_int 1)
 477
 478          (and (eq_attr "cpu_facility" "zEC12")
 479               (match_test "TARGET_ZEC12"))
 480          (const_int 1)
 481
 482          (and (eq_attr "cpu_facility" "vec")
 483               (match_test "TARGET_VX"))
 484          (const_int 1)]
 485         (const_int 0)))
 486
 487 ;; Pipeline description for z900.  For lack of anything better,
 488 ;; this description is also used for the g5 and g6.
 489 (include "2064.md")
 490
 491 ;; Pipeline description for z990, z9-109 and z9-ec.
 492 (include "2084.md")
 493
 494 ;; Pipeline description for z10
 495 (include "2097.md")
 496
 497 ;; Pipeline description for z196
 498 (include "2817.md")
 499
 500 ;; Pipeline description for zEC12
 501 (include "2827.md")
 502
 503 ;; Predicates
 504 (include "predicates.md")
 505
 506 ;; Constraint definitions
 507 (include "constraints.md")
 508
 509 ;; Other includes
 510 (include "tpf.md")
 511
 512 ;; Iterators
 513
 514 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
 515
 516 ;; These mode iterators allow floating point patterns to be generated from the
 517 ;; same template.
 518 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
 519                               (SD "TARGET_HARD_DFP")])
 520 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
 521 (define_mode_iterator BFP [TF DF SF])
 522 (define_mode_iterator DFP [TD DD])
 523 (define_mode_iterator DFP_ALL [TD DD SD])
 524 (define_mode_iterator DSF [DF SF])
 525 (define_mode_iterator SD_SF [SF SD])
 526 (define_mode_iterator DD_DF [DF DD])
 527 (define_mode_iterator TD_TF [TF TD])
 528
 529 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
 530 ;; from the same template.
 531 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
 532 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
 533 (define_mode_iterator DSI [DI SI])
 534 (define_mode_iterator TDI [TI DI])
 535
 536 ;; These mode iterators allow :P to be used for patterns that operate on
 537 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 538 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
 539
 540 ;; These macros refer to the actual word_mode of the configuration.
 541 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
 542 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
 543 (define_mode_iterator W  [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
 544
 545 ;; Used by the umul pattern to express modes having half the size.
 546 (define_mode_attr DWH [(TI "DI") (DI "SI")])
 547 (define_mode_attr dwh [(TI "di") (DI "si")])
 548
 549 ;; This mode iterator allows the QI and HI patterns to be defined from
 550 ;; the same template.
 551 (define_mode_iterator HQI [HI QI])
 552
 553 ;; This mode iterator allows the integer patterns to be defined from the
 554 ;; same template.
 555 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
 556 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
 557
 558 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
 559 ;; the same template.
 560 (define_code_iterator SHIFT [ashift lshiftrt])
 561
 562 ;; This iterator allows r[ox]sbg to be defined with the same template
 563 (define_code_iterator IXOR [ior xor])
 564
 565 ;; This iterator is used to expand the patterns for the nearest
 566 ;; integer functions.
 567 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
 568                             UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
 569                             UNSPEC_FPINT_NEARBYINT])
 570 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
 571                              (UNSPEC_FPINT_BTRUNC "btrunc")
 572                              (UNSPEC_FPINT_ROUND "round")
 573                              (UNSPEC_FPINT_CEIL "ceil")
 574                              (UNSPEC_FPINT_NEARBYINT "nearbyint")])
 575 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
 576                                      (UNSPEC_FPINT_BTRUNC "5")
 577                                      (UNSPEC_FPINT_ROUND "1")
 578                                      (UNSPEC_FPINT_CEIL "6")
 579                                      (UNSPEC_FPINT_NEARBYINT "0")])
 580
 581 ;; This iterator and attribute allow to combine most atomic operations.
 582 (define_code_iterator ATOMIC [and ior xor plus minus mult])
 583 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
 584 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
 585                           (plus "add") (minus "sub") (mult "nand")])
 586 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
 587
 588 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
 589 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
 590 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
 591
 592 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
 593 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
 594 ;; SDmode.
 595 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
 596
 597 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
 598 ;; Likewise for "<RXe>".
 599 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
 600 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 601
 602 ;; The decimal floating point variants of add, sub, div and mul support 3
 603 ;; fp register operands.  The following attributes allow to merge the bfp and
 604 ;; dfp variants in a single insn definition.
 605
 606 ;; This attribute is used to set op_type accordingly.
 607 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
 608                         (DD "RRR") (SD "RRR")])
 609
 610 ;; This attribute is used in the operand constraint list in order to have the
 611 ;; first and the second operand match for bfp modes.
 612 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
 613
 614 ;; This attribute is used to merge the scalar vector instructions into
 615 ;; the FP patterns.  For non-supported modes (all but DF) it expands
 616 ;; to constraints which are supposed to be matched by an earlier
 617 ;; variant.
 618 (define_mode_attr v0      [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")])
 619 (define_mode_attr vf      [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")])
 620 (define_mode_attr vd      [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")])
 621
 622 ;; This attribute is used in the operand list of the instruction to have an
 623 ;; additional operand for the dfp instructions.
 624 (define_mode_attr op1 [(TF "") (DF "") (SF "")
 625                        (TD "%1,") (DD "%1,") (SD "%1,")])
 626
 627
 628 ;; This attribute is used in the operand constraint list
 629 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
 630 ;; TFmode values are represented by a fp register pair.  Since the
 631 ;; sign bit instructions only handle single source and target fp registers
 632 ;; these instructions can only be used for TFmode values if the source and
 633 ;; target operand uses the same fp register.
 634 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 635
 636 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
 637 ;; This is used to disable the memory alternative in TFmode patterns.
 638 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
 639
 640 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 641 ;; within instruction mnemonics.
 642 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 643
 644 ;; This attribute is used within instruction mnemonics.  It evaluates to d for dfp
 645 ;; modes and to an empty string for bfp modes.
 646 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
 647
 648 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
 649 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
 650 ;; version only operates on one register.
 651 (define_mode_attr d0 [(DI "d") (SI "0")])
 652
 653 ;; In combination with d0 this allows to combine instructions of which the 31bit
 654 ;; version only operates on one register. The DImode version needs an additional
 655 ;; register for the assembler output.
 656 (define_mode_attr 1 [(DI "%1,") (SI "")])
 657
 658 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
 659 ;; 'ashift' and "srdl" in 'lshiftrt'.
 660 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
 661
 662 ;; In SHIFT templates, this attribute holds the correct standard name for the
 663 ;; pattern itself and the corresponding function calls.
 664 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
 665
 666 ;; This attribute handles differences in the instruction 'type' and will result
 667 ;; in "RRE" for DImode and "RR" for SImode.
 668 (define_mode_attr E [(DI "E") (SI "")])
 669
 670 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
 671 ;; to result in "RXY" for DImode and "RX" for SImode.
 672 (define_mode_attr Y [(DI "Y") (SI "")])
 673
 674 ;; This attribute handles differences in the instruction 'type' and will result
 675 ;; in "RSE" for TImode and "RS" for DImode.
 676 (define_mode_attr TE [(TI "E") (DI "")])
 677
 678 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
 679 ;; and "lcr" in SImode.
 680 (define_mode_attr g [(DI "g") (SI "")])
 681
 682 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
 683 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
 684 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
 685 ;; variant for long displacements.
 686 (define_mode_attr y [(DI "g") (SI "y")])
 687
 688 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
 689 ;; and "cds" in DImode.
 690 (define_mode_attr tg [(TI "g") (DI "")])
 691
 692 ;; In TDI templates, a string like "c<d>sg".
 693 (define_mode_attr td [(TI "d") (DI "")])
 694
 695 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
 696 ;; and "cfdbr" in SImode.
 697 (define_mode_attr gf [(DI "g") (SI "f")])
 698
 699 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
 700 ;; and sllk for SI.  This way it is possible to merge the new z196 SI
 701 ;; 3 operands shift instructions into the existing patterns.
 702 (define_mode_attr gk [(DI "g") (SI "k")])
 703
 704 ;; ICM mask required to load MODE value into the lowest subreg
 705 ;; of a SImode register.
 706 (define_mode_attr icm_lo [(HI "3") (QI "1")])
 707
 708 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
 709 ;; HImode and "llgc" in QImode.
 710 (define_mode_attr hc [(HI "h") (QI "c")])
 711
 712 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
 713 ;; in SImode.
 714 (define_mode_attr DBL [(DI "TI") (SI "DI")])
 715
 716 ;; This attribute expands to DF for TFmode and to DD for TDmode .  It is
 717 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
 718 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
 719
 720 ;; Maximum unsigned integer that fits in MODE.
 721 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 722
 723 ;; Start and end field computations for RISBG et al.
 724 (define_mode_attr bfstart [(DI "s") (SI "t")])
 725 (define_mode_attr bfend   [(DI "e") (SI "f")])
 726
 727 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
 728 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
 729
 730 ;; Allow return and simple_return to be defined from a single template.
 731 (define_code_iterator ANY_RETURN [return simple_return])
 732
 733
 734
 735 ; Condition code modes generated by vector fp comparisons.  These will
 736 ; be used also in single element mode.
 737 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
 738 ; Used with VFCMP to expand part of the mnemonic
 739 ; For fp we have a mismatch: eq in the insn name - e in asm
 740 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
 741 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
 742
 743
 744 (include "vector.md")
 745
 746 ;;
 747 ;;- Compare instructions.
 748 ;;
 749
 750 ; Test-under-Mask instructions
 751
 752 (define_insn "*tmqi_mem"
 753   [(set (reg CC_REGNUM)
 754         (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
 755                          (match_operand:QI 1 "immediate_operand" "n,n"))
 756                  (match_operand:QI 2 "immediate_operand" "n,n")))]
 757   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
 758   "@
 759    tm\t%S0,%b1
 760    tmy\t%S0,%b1"
 761   [(set_attr "op_type" "SI,SIY")
 762    (set_attr "z10prop" "z10_super,z10_super")])
 763
 764 (define_insn "*tmdi_reg"
 765   [(set (reg CC_REGNUM)
 766         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
 767                          (match_operand:DI 1 "immediate_operand"
 768                                              "N0HD0,N1HD0,N2HD0,N3HD0"))
 769                  (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
 770   "TARGET_ZARCH
 771    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 772    && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
 773   "@
 774    tmhh\t%0,%i1
 775    tmhl\t%0,%i1
 776    tmlh\t%0,%i1
 777    tmll\t%0,%i1"
 778   [(set_attr "op_type" "RI")
 779    (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
 780
 781 (define_insn "*tmsi_reg"
 782   [(set (reg CC_REGNUM)
 783         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
 784                          (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
 785                  (match_operand:SI 2 "immediate_operand" "n,n")))]
 786   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 787    && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
 788   "@
 789    tmh\t%0,%i1
 790    tml\t%0,%i1"
 791   [(set_attr "op_type" "RI")
 792    (set_attr "z10prop" "z10_super,z10_super")])
 793
 794 (define_insn "*tm<mode>_full"
 795   [(set (reg CC_REGNUM)
 796         (compare (match_operand:HQI 0 "register_operand" "d")
 797                  (match_operand:HQI 1 "immediate_operand" "n")))]
 798   "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
 799   "tml\t%0,<max_uint>"
 800   [(set_attr "op_type" "RI")
 801    (set_attr "z10prop" "z10_super")])
 802
 803
 804 ;
 805 ; Load-and-Test instructions
 806 ;
 807
 808 ; tst(di|si) instruction pattern(s).
 809
 810 (define_insn "*tstdi_sign"
 811   [(set (reg CC_REGNUM)
 812         (compare
 813           (ashiftrt:DI
 814             (ashift:DI
 815               (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
 816               (const_int 32)) (const_int 32))
 817           (match_operand:DI 1 "const0_operand" "")))
 818    (set (match_operand:DI 2 "register_operand" "=d,d")
 819         (sign_extend:DI (match_dup 0)))]
 820   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
 821   "ltgfr\t%2,%0
 822    ltgf\t%2,%0"
 823   [(set_attr "op_type"      "RRE,RXY")
 824    (set_attr "cpu_facility" "*,z10")
 825    (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
 826
 827 ; ltr, lt, ltgr, ltg
 828 (define_insn "*tst<mode>_extimm"
 829   [(set (reg CC_REGNUM)
 830         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 831                  (match_operand:GPR 1 "const0_operand" "")))
 832    (set (match_operand:GPR 2 "register_operand" "=d,d")
 833         (match_dup 0))]
 834   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 835   "@
 836    lt<g>r\t%2,%0
 837    lt<g>\t%2,%0"
 838   [(set_attr "op_type" "RR<E>,RXY")
 839    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
 840
 841 ; ltr, lt, ltgr, ltg
 842 (define_insn "*tst<mode>_cconly_extimm"
 843   [(set (reg CC_REGNUM)
 844         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 845                  (match_operand:GPR 1 "const0_operand" "")))
 846    (clobber (match_scratch:GPR 2 "=X,d"))]
 847   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 848   "@
 849    lt<g>r\t%0,%0
 850    lt<g>\t%2,%0"
 851   [(set_attr "op_type" "RR<E>,RXY")
 852    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
 853
 854 (define_insn "*tstdi"
 855   [(set (reg CC_REGNUM)
 856         (compare (match_operand:DI 0 "register_operand" "d")
 857                  (match_operand:DI 1 "const0_operand" "")))
 858    (set (match_operand:DI 2 "register_operand" "=d")
 859         (match_dup 0))]
 860   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
 861   "ltgr\t%2,%0"
 862   [(set_attr "op_type" "RRE")
 863    (set_attr "z10prop" "z10_fr_E1")])
 864
 865 (define_insn "*tstsi"
 866   [(set (reg CC_REGNUM)
 867         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 868                  (match_operand:SI 1 "const0_operand" "")))
 869    (set (match_operand:SI 2 "register_operand" "=d,d,d")
 870         (match_dup 0))]
 871   "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
 872   "@
 873    ltr\t%2,%0
 874    icm\t%2,15,%S0
 875    icmy\t%2,15,%S0"
 876   [(set_attr "op_type" "RR,RS,RSY")
 877    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 878
 879 (define_insn "*tstsi_cconly"
 880   [(set (reg CC_REGNUM)
 881         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 882                  (match_operand:SI 1 "const0_operand" "")))
 883    (clobber (match_scratch:SI 2 "=X,d,d"))]
 884   "s390_match_ccmode(insn, CCSmode)"
 885   "@
 886    ltr\t%0,%0
 887    icm\t%2,15,%S0
 888    icmy\t%2,15,%S0"
 889   [(set_attr "op_type" "RR,RS,RSY")
 890    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 891
 892 (define_insn "*tstdi_cconly_31"
 893   [(set (reg CC_REGNUM)
 894         (compare (match_operand:DI 0 "register_operand" "d")
 895                  (match_operand:DI 1 "const0_operand" "")))]
 896   "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
 897   "srda\t%0,0"
 898   [(set_attr "op_type" "RS")
 899    (set_attr "atype"   "reg")])
 900
 901 ; ltr, ltgr
 902 (define_insn "*tst<mode>_cconly2"
 903   [(set (reg CC_REGNUM)
 904         (compare (match_operand:GPR 0 "register_operand" "d")
 905                  (match_operand:GPR 1 "const0_operand" "")))]
 906   "s390_match_ccmode(insn, CCSmode)"
 907   "lt<g>r\t%0,%0"
 908   [(set_attr "op_type" "RR<E>")
 909    (set_attr "z10prop" "z10_fr_E1")])
 910
 911 ; tst(hi|qi) instruction pattern(s).
 912
 913 (define_insn "*tst<mode>CCT"
 914   [(set (reg CC_REGNUM)
 915         (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
 916                  (match_operand:HQI 1 "const0_operand" "")))
 917    (set (match_operand:HQI 2 "register_operand" "=d,d,0")
 918         (match_dup 0))]
 919   "s390_match_ccmode(insn, CCTmode)"
 920   "@
 921    icm\t%2,<icm_lo>,%S0
 922    icmy\t%2,<icm_lo>,%S0
 923    tml\t%0,<max_uint>"
 924   [(set_attr "op_type" "RS,RSY,RI")
 925    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 926
 927 (define_insn "*tsthiCCT_cconly"
 928   [(set (reg CC_REGNUM)
 929         (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
 930                  (match_operand:HI 1 "const0_operand" "")))
 931    (clobber (match_scratch:HI 2 "=d,d,X"))]
 932   "s390_match_ccmode(insn, CCTmode)"
 933   "@
 934    icm\t%2,3,%S0
 935    icmy\t%2,3,%S0
 936    tml\t%0,65535"
 937   [(set_attr "op_type" "RS,RSY,RI")
 938    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 939
 940 (define_insn "*tstqiCCT_cconly"
 941   [(set (reg CC_REGNUM)
 942         (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
 943                  (match_operand:QI 1 "const0_operand" "")))]
 944   "s390_match_ccmode(insn, CCTmode)"
 945   "@
 946    cli\t%S0,0
 947    cliy\t%S0,0
 948    tml\t%0,255"
 949   [(set_attr "op_type" "SI,SIY,RI")
 950    (set_attr "z10prop" "z10_super,z10_super,z10_super")])
 951
 952 (define_insn "*tst<mode>"
 953   [(set (reg CC_REGNUM)
 954         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 955                  (match_operand:HQI 1 "const0_operand" "")))
 956    (set (match_operand:HQI 2 "register_operand" "=d,d")
 957         (match_dup 0))]
 958   "s390_match_ccmode(insn, CCSmode)"
 959   "@
 960    icm\t%2,<icm_lo>,%S0
 961    icmy\t%2,<icm_lo>,%S0"
 962   [(set_attr "op_type" "RS,RSY")
 963    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 964
 965 (define_insn "*tst<mode>_cconly"
 966   [(set (reg CC_REGNUM)
 967         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 968                  (match_operand:HQI 1 "const0_operand" "")))
 969    (clobber (match_scratch:HQI 2 "=d,d"))]
 970   "s390_match_ccmode(insn, CCSmode)"
 971   "@
 972    icm\t%2,<icm_lo>,%S0
 973    icmy\t%2,<icm_lo>,%S0"
 974   [(set_attr "op_type" "RS,RSY")
 975    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 976
 977
 978 ; Compare (equality) instructions
 979
 980 (define_insn "*cmpdi_cct"
 981   [(set (reg CC_REGNUM)
 982         (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
 983                  (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
 984   "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
 985   "@
 986    cgr\t%0,%1
 987    cghi\t%0,%h1
 988    cgfi\t%0,%1
 989    cg\t%0,%1
 990    #"
 991   [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
 992    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
 993
 994 (define_insn "*cmpsi_cct"
 995   [(set (reg CC_REGNUM)
 996         (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
 997                  (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
 998   "s390_match_ccmode (insn, CCTmode)"
 999   "@
1000    cr\t%0,%1
1001    chi\t%0,%h1
1002    cfi\t%0,%1
1003    c\t%0,%1
1004    cy\t%0,%1
1005    #"
1006   [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1007    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1008
1009 ; Compare (signed) instructions
1010
1011 (define_insn "*cmpdi_ccs_sign"
1012   [(set (reg CC_REGNUM)
1013         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1014                                                      "d,RT,b"))
1015                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1016   "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1017   "@
1018    cgfr\t%0,%1
1019    cgf\t%0,%1
1020    cgfrl\t%0,%1"
1021   [(set_attr "op_type"      "RRE,RXY,RIL")
1022    (set_attr "z10prop" "z10_c,*,*")
1023    (set_attr "type"         "*,*,larl")])
1024
1025
1026
1027 (define_insn "*cmpsi_ccs_sign"
1028   [(set (reg CC_REGNUM)
1029         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1030                  (match_operand:SI 0 "register_operand" "d,d,d")))]
1031   "s390_match_ccmode(insn, CCSRmode)"
1032   "@
1033    ch\t%0,%1
1034    chy\t%0,%1
1035    chrl\t%0,%1"
1036   [(set_attr "op_type"      "RX,RXY,RIL")
1037    (set_attr "cpu_facility" "*,*,z10")
1038    (set_attr "type"         "*,*,larl")
1039    (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1040
1041 (define_insn "*cmphi_ccs_z10"
1042   [(set (reg CC_REGNUM)
1043         (compare (match_operand:HI 0 "s_operand"         "Q")
1044                  (match_operand:HI 1 "immediate_operand" "K")))]
1045   "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1046   "chhsi\t%0,%1"
1047   [(set_attr "op_type" "SIL")
1048    (set_attr "z196prop" "z196_cracked")])
1049
1050 (define_insn "*cmpdi_ccs_signhi_rl"
1051   [(set (reg CC_REGNUM)
1052         (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
1053                  (match_operand:GPR 0 "register_operand"  "d,d")))]
1054   "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1055   "@
1056    cgh\t%0,%1
1057    cghrl\t%0,%1"
1058   [(set_attr "op_type" "RXY,RIL")
1059    (set_attr "type"    "*,larl")])
1060
1061 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1062 (define_insn "*cmp<mode>_ccs"
1063   [(set (reg CC_REGNUM)
1064         (compare (match_operand:GPR 0 "nonimmediate_operand"
1065                                       "d,d,Q, d,d,d,d")
1066                  (match_operand:GPR 1 "general_operand"
1067                                       "d,K,K,Os,R,T,b")))]
1068   "s390_match_ccmode(insn, CCSmode)"
1069   "@
1070    c<g>r\t%0,%1
1071    c<g>hi\t%0,%h1
1072    c<g>hsi\t%0,%h1
1073    c<g>fi\t%0,%1
1074    c<g>\t%0,%1
1075    c<y>\t%0,%1
1076    c<g>rl\t%0,%1"
1077   [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1078    (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
1079    (set_attr "type" "*,*,*,*,*,*,larl")
1080    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1081
1082
1083 ; Compare (unsigned) instructions
1084
1085 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1086   [(set (reg CC_REGNUM)
1087         (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1088                                           "larl_operand" "X")))
1089                  (match_operand:SI 0 "register_operand" "d")))]
1090   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1091   "clhrl\t%0,%1"
1092   [(set_attr "op_type" "RIL")
1093    (set_attr "type"    "larl")
1094    (set_attr "z10prop" "z10_super")])
1095
1096 ; clhrl, clghrl
1097 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1098   [(set (reg CC_REGNUM)
1099         (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1100                                           "larl_operand" "X")))
1101                  (match_operand:GPR 0 "register_operand" "d")))]
1102   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1103   "cl<g>hrl\t%0,%1"
1104   [(set_attr "op_type" "RIL")
1105    (set_attr "type"    "larl")
1106    (set_attr "z10prop" "z10_super")])
1107
1108 (define_insn "*cmpdi_ccu_zero"
1109   [(set (reg CC_REGNUM)
1110         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1111                                                         "d,RT,b"))
1112                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1113   "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1114   "@
1115    clgfr\t%0,%1
1116    clgf\t%0,%1
1117    clgfrl\t%0,%1"
1118   [(set_attr "op_type"      "RRE,RXY,RIL")
1119    (set_attr "cpu_facility" "*,*,z10")
1120    (set_attr "type"         "*,*,larl")
1121    (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1122
1123 (define_insn "*cmpdi_ccu"
1124   [(set (reg CC_REGNUM)
1125         (compare (match_operand:DI 0 "nonimmediate_operand"
1126                                      "d, d,d,Q, d, Q,BQ")
1127                  (match_operand:DI 1 "general_operand"
1128                                      "d,Op,b,D,RT,BQ,Q")))]
1129   "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1130   "@
1131    clgr\t%0,%1
1132    clgfi\t%0,%1
1133    clgrl\t%0,%1
1134    clghsi\t%0,%x1
1135    clg\t%0,%1
1136    #
1137    #"
1138   [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1139    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1140    (set_attr "type"         "*,*,larl,*,*,*,*")
1141    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1142
1143 (define_insn "*cmpsi_ccu"
1144   [(set (reg CC_REGNUM)
1145         (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1146                  (match_operand:SI 1 "general_operand"      "d,Os,b,D,R,T,BQ, Q")))]
1147   "s390_match_ccmode (insn, CCUmode)"
1148   "@
1149    clr\t%0,%1
1150    clfi\t%0,%o1
1151    clrl\t%0,%1
1152    clfhsi\t%0,%x1
1153    cl\t%0,%1
1154    cly\t%0,%1
1155    #
1156    #"
1157   [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1158    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1159    (set_attr "type"         "*,*,larl,*,*,*,*,*")
1160    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1161
1162 (define_insn "*cmphi_ccu"
1163   [(set (reg CC_REGNUM)
1164         (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1165                  (match_operand:HI 1 "general_operand"      "Q,S,D,BQ,Q")))]
1166   "s390_match_ccmode (insn, CCUmode)
1167    && !register_operand (operands[1], HImode)"
1168   "@
1169    clm\t%0,3,%S1
1170    clmy\t%0,3,%S1
1171    clhhsi\t%0,%1
1172    #
1173    #"
1174   [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1175    (set_attr "cpu_facility" "*,*,z10,*,*")
1176    (set_attr "z10prop" "*,*,z10_super,*,*")])
1177
1178 (define_insn "*cmpqi_ccu"
1179   [(set (reg CC_REGNUM)
1180         (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1181                  (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1182   "s390_match_ccmode (insn, CCUmode)
1183    && !register_operand (operands[1], QImode)"
1184   "@
1185    clm\t%0,1,%S1
1186    clmy\t%0,1,%S1
1187    cli\t%S0,%b1
1188    cliy\t%S0,%b1
1189    #
1190    #"
1191   [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1192    (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1193
1194
1195 ; Block compare (CLC) instruction patterns.
1196
1197 (define_insn "*clc"
1198   [(set (reg CC_REGNUM)
1199         (compare (match_operand:BLK 0 "memory_operand" "Q")
1200                  (match_operand:BLK 1 "memory_operand" "Q")))
1201    (use (match_operand 2 "const_int_operand" "n"))]
1202   "s390_match_ccmode (insn, CCUmode)
1203    && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1204   "clc\t%O0(%2,%R0),%S1"
1205   [(set_attr "op_type" "SS")])
1206
1207 (define_split
1208   [(set (reg CC_REGNUM)
1209         (compare (match_operand 0 "memory_operand" "")
1210                  (match_operand 1 "memory_operand" "")))]
1211   "reload_completed
1212    && s390_match_ccmode (insn, CCUmode)
1213    && GET_MODE (operands[0]) == GET_MODE (operands[1])
1214    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1215   [(parallel
1216     [(set (match_dup 0) (match_dup 1))
1217      (use (match_dup 2))])]
1218 {
1219   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1220   operands[0] = adjust_address (operands[0], BLKmode, 0);
1221   operands[1] = adjust_address (operands[1], BLKmode, 0);
1222
1223   operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1224                                  operands[0], operands[1]);
1225   operands[0] = SET_DEST (PATTERN (curr_insn));
1226 })
1227
1228
1229 ; (TF|DF|SF|TD|DD|SD) instructions
1230
1231 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1232 (define_insn "*cmp<mode>_ccs_0"
1233   [(set (reg CC_REGNUM)
1234         (compare (match_operand:FP 0 "register_operand" "f")
1235                  (match_operand:FP 1 "const0_operand"   "")))]
1236   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1237   "lt<xde><bt>r\t%0,%0"
1238    [(set_attr "op_type" "RRE")
1239     (set_attr "type"  "fsimp<mode>")])
1240
1241 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1242 (define_insn "*cmp<mode>_ccs"
1243   [(set (reg CC_REGNUM)
1244         (compare (match_operand:FP 0 "register_operand" "f,f")
1245                  (match_operand:FP 1 "general_operand"  "f,<Rf>")))]
1246   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1247   "@
1248    c<xde><bt>r\t%0,%1
1249    c<xde>b\t%0,%1"
1250    [(set_attr "op_type" "RRE,RXE")
1251     (set_attr "type"  "fsimp<mode>")])
1252
1253 ; wfcedbs, wfchdbs, wfchedbs
1254 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1255   [(set (reg:VFCMP CC_REGNUM)
1256         (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1257                        (match_operand:DF 1 "register_operand" "v")))
1258    (clobber (match_scratch:V2DI 2 "=v"))]
1259   "TARGET_Z13 && TARGET_HARD_FLOAT"
1260   "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1261   [(set_attr "op_type" "VRR")])
1262
1263 ; Compare and Branch instructions
1264
1265 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1266 ; The following instructions do a complementary access of their second
1267 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1268 (define_insn "*cmp_and_br_signed_<mode>"
1269   [(set (pc)
1270         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1271                         [(match_operand:GPR 1 "register_operand"  "d,d")
1272                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1273                       (label_ref (match_operand 3 "" ""))
1274                       (pc)))
1275    (clobber (reg:CC CC_REGNUM))]
1276   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1277 {
1278   if (get_attr_length (insn) == 6)
1279     return which_alternative ?
1280       "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1281   else
1282     return which_alternative ?
1283       "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1284 }
1285   [(set_attr "op_type" "RIE")
1286    (set_attr "type"    "branch")
1287    (set_attr "z10prop" "z10_super_c,z10_super")
1288    (set (attr "length")
1289         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1290                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1291                                                        ; 10 byte for cgr/jg
1292
1293 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1294 ; The following instructions do a complementary access of their second
1295 ; operand (z10 only): clrj, clgrj, clr, clgr
1296 (define_insn "*cmp_and_br_unsigned_<mode>"
1297   [(set (pc)
1298         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1299                         [(match_operand:GPR 1 "register_operand"  "d,d")
1300                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1301                       (label_ref (match_operand 3 "" ""))
1302                       (pc)))
1303    (clobber (reg:CC CC_REGNUM))]
1304   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1305 {
1306   if (get_attr_length (insn) == 6)
1307     return which_alternative ?
1308       "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1309   else
1310     return which_alternative ?
1311       "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1312 }
1313   [(set_attr "op_type" "RIE")
1314    (set_attr "type"    "branch")
1315    (set_attr "z10prop" "z10_super_c,z10_super")
1316    (set (attr "length")
1317         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1318                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1319                                                        ; 10 byte for clgr/jg
1320
1321 ; And now the same two patterns as above but with a negated CC mask.
1322
1323 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1324 ; The following instructions do a complementary access of their second
1325 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1326 (define_insn "*icmp_and_br_signed_<mode>"
1327   [(set (pc)
1328         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1329                         [(match_operand:GPR 1 "register_operand"  "d,d")
1330                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1331                       (pc)
1332                       (label_ref (match_operand 3 "" ""))))
1333    (clobber (reg:CC CC_REGNUM))]
1334   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1335 {
1336   if (get_attr_length (insn) == 6)
1337     return which_alternative ?
1338       "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1339   else
1340     return which_alternative ?
1341       "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1342 }
1343   [(set_attr "op_type" "RIE")
1344    (set_attr "type"    "branch")
1345    (set_attr "z10prop" "z10_super_c,z10_super")
1346    (set (attr "length")
1347         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1348                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1349                                                        ; 10 byte for cgr/jg
1350
1351 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1352 ; The following instructions do a complementary access of their second
1353 ; operand (z10 only): clrj, clgrj, clr, clgr
1354 (define_insn "*icmp_and_br_unsigned_<mode>"
1355   [(set (pc)
1356         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1357                         [(match_operand:GPR 1 "register_operand"  "d,d")
1358                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1359                       (pc)
1360                       (label_ref (match_operand 3 "" ""))))
1361    (clobber (reg:CC CC_REGNUM))]
1362   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1363 {
1364   if (get_attr_length (insn) == 6)
1365     return which_alternative ?
1366       "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1367   else
1368     return which_alternative ?
1369       "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1370 }
1371   [(set_attr "op_type" "RIE")
1372    (set_attr "type"    "branch")
1373    (set_attr "z10prop" "z10_super_c,z10_super")
1374    (set (attr "length")
1375         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1376                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1377                                                        ; 10 byte for clgr/jg
1378
1379 ;;
1380 ;;- Move instructions.
1381 ;;
1382
1383 ;
1384 ; movti instruction pattern(s).
1385 ;
1386
1387 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1388 ; for TImode (use double-int for the calculations)
1389 (define_insn "movti"
1390   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v,  v,  v,v,d, v,QR,   d,o")
1391         (match_operand:TI 1 "general_operand"      "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
1392   "TARGET_ZARCH"
1393   "@
1394    lmg\t%0,%N0,%S1
1395    stmg\t%1,%N1,%S0
1396    vlr\t%v0,%v1
1397    vzero\t%v0
1398    vone\t%v0
1399    vlvgp\t%v0,%1,%N1
1400    #
1401    vl\t%v0,%1
1402    vst\t%v1,%0
1403    #
1404    #"
1405   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1406    (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1407    (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1408
1409 (define_split
1410   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1411         (match_operand:TI 1 "general_operand" ""))]
1412   "TARGET_ZARCH && reload_completed
1413    && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1414   [(set (match_dup 2) (match_dup 4))
1415    (set (match_dup 3) (match_dup 5))]
1416 {
1417   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1418   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1419   operands[4] = operand_subword (operands[1], 0, 0, TImode);
1420   operands[5] = operand_subword (operands[1], 1, 0, TImode);
1421 })
1422
1423 (define_split
1424   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1425         (match_operand:TI 1 "general_operand" ""))]
1426   "TARGET_ZARCH && reload_completed
1427    && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1428   [(set (match_dup 2) (match_dup 4))
1429    (set (match_dup 3) (match_dup 5))]
1430 {
1431   operands[2] = operand_subword (operands[0], 1, 0, TImode);
1432   operands[3] = operand_subword (operands[0], 0, 0, TImode);
1433   operands[4] = operand_subword (operands[1], 1, 0, TImode);
1434   operands[5] = operand_subword (operands[1], 0, 0, TImode);
1435 })
1436
1437 ; Use part of the TImode target reg to perform the address
1438 ; calculation.  If the TImode value is supposed to be copied into a VR
1439 ; this splitter is not necessary.
1440 (define_split
1441   [(set (match_operand:TI 0 "register_operand" "")
1442         (match_operand:TI 1 "memory_operand" ""))]
1443   "TARGET_ZARCH && reload_completed
1444    && !VECTOR_REG_P (operands[0])
1445    && !s_operand (operands[1], VOIDmode)"
1446   [(set (match_dup 0) (match_dup 1))]
1447 {
1448   rtx addr = operand_subword (operands[0], 1, 0, TImode);
1449   addr = gen_lowpart (Pmode, addr);
1450   s390_load_address (addr, XEXP (operands[1], 0));
1451   operands[1] = replace_equiv_address (operands[1], addr);
1452 })
1453
1454
1455 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1456 ; For the higher order bits we do simply a DImode move while the
1457 ; second part is done via vec extract.  Both will end up as vlgvg.
1458 (define_split
1459   [(set (match_operand:TI 0 "register_operand" "")
1460         (match_operand:TI 1 "register_operand" ""))]
1461   "TARGET_VX && reload_completed
1462    && GENERAL_REG_P (operands[0])
1463    && VECTOR_REG_P (operands[1])"
1464   [(set (match_dup 2) (match_dup 4))
1465    (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1466                                  UNSPEC_VEC_EXTRACT))]
1467 {
1468   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1469   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1470   operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1471   operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1472 })
1473
1474 ;
1475 ; Patterns used for secondary reloads
1476 ;
1477
1478 ; z10 provides move instructions accepting larl memory operands.
1479 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1480 ; These patterns are also used for unaligned SI and DI accesses.
1481
1482 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1483   [(parallel [(match_operand:ALL 0 "memory_operand"   "")
1484               (match_operand:ALL 1 "register_operand" "=d")
1485               (match_operand:P   2 "register_operand" "=&a")])]
1486   "TARGET_Z10"
1487 {
1488   s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1489   DONE;
1490 })
1491
1492 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1493   [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1494               (match_operand:ALL 1 "memory_operand"   "")
1495               (match_operand:P   2 "register_operand" "=a")])]
1496   "TARGET_Z10"
1497 {
1498   s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1499   DONE;
1500 })
1501
1502 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1503   [(parallel [(match_operand:P 0 "register_operand" "=d")
1504               (match_operand:P 1 "larl_operand"     "")
1505               (match_operand:P 2 "register_operand" "=a")])]
1506   "TARGET_Z10"
1507 {
1508   s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1509   DONE;
1510 })
1511
1512 ; Handles loading a PLUS (load address) expression
1513
1514 (define_expand "reload<mode>_plus"
1515   [(parallel [(match_operand:P 0 "register_operand"  "=a")
1516               (match_operand:P 1 "s390_plus_operand" "")
1517               (match_operand:P 2 "register_operand"  "=&a")])]
1518   ""
1519 {
1520   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1521   DONE;
1522 })
1523
1524 ; Not all the indirect memory access instructions support the full
1525 ; format (long disp + index + base).  So whenever a move from/to such
1526 ; an address is required and the instruction cannot deal with it we do
1527 ; a load address into a scratch register first and use this as the new
1528 ; base register.
1529 ; This in particular is used for:
1530 ; - non-offsetable memory accesses for multiword moves
1531 ; - full vector reg moves with long displacements
1532
1533 (define_expand "reload<mode>_la_in"
1534   [(parallel [(match_operand 0   "register_operand" "")
1535               (match_operand 1   "" "")
1536               (match_operand:P 2 "register_operand" "=&a")])]
1537   ""
1538 {
1539   gcc_assert (MEM_P (operands[1]));
1540   s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1541   operands[1] = replace_equiv_address (operands[1], operands[2]);
1542   emit_move_insn (operands[0], operands[1]);
1543   DONE;
1544 })
1545
1546 (define_expand "reload<mode>_la_out"
1547   [(parallel [(match_operand   0 "" "")
1548               (match_operand   1 "register_operand" "")
1549               (match_operand:P 2 "register_operand" "=&a")])]
1550   ""
1551 {
1552   gcc_assert (MEM_P (operands[0]));
1553   s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1554   operands[0] = replace_equiv_address (operands[0], operands[2]);
1555   emit_move_insn (operands[0], operands[1]);
1556   DONE;
1557 })
1558
1559 (define_expand "reload<mode>_PIC_addr"
1560   [(parallel [(match_operand   0 "register_operand" "=d")
1561               (match_operand   1 "larl_operand"     "")
1562               (match_operand:P 2 "register_operand" "=a")])]
1563   ""
1564 {
1565   rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1566   emit_move_insn (operands[0], new_rtx);
1567 })
1568
1569 ;
1570 ; movdi instruction pattern(s).
1571 ;
1572
1573 (define_expand "movdi"
1574   [(set (match_operand:DI 0 "general_operand" "")
1575         (match_operand:DI 1 "general_operand" ""))]
1576   ""
1577 {
1578   /* Handle symbolic constants.  */
1579   if (TARGET_64BIT
1580       && (SYMBOLIC_CONST (operands[1])
1581           || (GET_CODE (operands[1]) == PLUS
1582               && XEXP (operands[1], 0) == pic_offset_table_rtx
1583               && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1584     emit_symbolic_move (operands);
1585 })
1586
1587 (define_insn "*movdi_larl"
1588   [(set (match_operand:DI 0 "register_operand" "=d")
1589         (match_operand:DI 1 "larl_operand" "X"))]
1590   "TARGET_64BIT
1591    && !FP_REG_P (operands[0])"
1592   "larl\t%0,%1"
1593    [(set_attr "op_type" "RIL")
1594     (set_attr "type"    "larl")
1595     (set_attr "z10prop" "z10_super_A1")])
1596
1597 (define_insn "*movdi_64"
1598   [(set (match_operand:DI 0 "nonimmediate_operand"
1599          "=d,    d,    d,    d,    d, d,    d,    d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
1600         (match_operand:DI 1 "general_operand"
1601          " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f,  R,  T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
1602   "TARGET_ZARCH"
1603   "@
1604    lghi\t%0,%h1
1605    llihh\t%0,%i1
1606    llihl\t%0,%i1
1607    llilh\t%0,%i1
1608    llill\t%0,%i1
1609    lgfi\t%0,%1
1610    llihf\t%0,%k1
1611    llilf\t%0,%k1
1612    ldgr\t%0,%1
1613    lgdr\t%0,%1
1614    lay\t%0,%a1
1615    lgrl\t%0,%1
1616    lgr\t%0,%1
1617    lg\t%0,%1
1618    stg\t%1,%0
1619    ldr\t%0,%1
1620    ld\t%0,%1
1621    ldy\t%0,%1
1622    std\t%1,%0
1623    stdy\t%1,%0
1624    stgrl\t%1,%0
1625    mvghi\t%0,%1
1626    #
1627    #
1628    stam\t%1,%N1,%S0
1629    lam\t%0,%N0,%S1
1630    vleig\t%v0,%h1,0
1631    vlr\t%v0,%v1
1632    vlvgg\t%v0,%1,0
1633    vlgvg\t%0,%v1,0
1634    vleg\t%v0,%1,0
1635    vsteg\t%v1,%0,0"
1636   [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1637                         RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1638    (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1639                      floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1640                      *,*,*,*,*,*,*")
1641    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1642                              z10,*,*,*,*,*,longdisp,*,longdisp,
1643                              z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1644    (set_attr "z10prop" "z10_fwd_A1,
1645                         z10_fwd_E1,
1646                         z10_fwd_E1,
1647                         z10_fwd_E1,
1648                         z10_fwd_E1,
1649                         z10_fwd_A1,
1650                         z10_fwd_E1,
1651                         z10_fwd_E1,
1652                         *,
1653                         *,
1654                         z10_fwd_A1,
1655                         z10_fwd_A3,
1656                         z10_fr_E1,
1657                         z10_fwd_A3,
1658                         z10_rec,
1659                         *,
1660                         *,
1661                         *,
1662                         *,
1663                         *,
1664                         z10_rec,
1665                         z10_super,
1666                         *,
1667                         *,
1668                         *,
1669                         *,*,*,*,*,*,*")
1670 ])
1671
1672 (define_split
1673   [(set (match_operand:DI 0 "register_operand" "")
1674         (match_operand:DI 1 "register_operand" ""))]
1675   "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1676   [(set (match_dup 2) (match_dup 3))
1677    (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1678    (set (strict_low_part (match_dup 2)) (match_dup 4))]
1679   "operands[2] = gen_lowpart (SImode, operands[0]);
1680    s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1681
1682 (define_split
1683   [(set (match_operand:DI 0 "register_operand" "")
1684         (match_operand:DI 1 "register_operand" ""))]
1685   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1686    && dead_or_set_p (insn, operands[1])"
1687   [(set (match_dup 3) (match_dup 2))
1688    (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1689    (set (match_dup 4) (match_dup 2))]
1690   "operands[2] = gen_lowpart (SImode, operands[1]);
1691    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1692
1693 (define_split
1694   [(set (match_operand:DI 0 "register_operand" "")
1695         (match_operand:DI 1 "register_operand" ""))]
1696   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1697    && !dead_or_set_p (insn, operands[1])"
1698   [(set (match_dup 3) (match_dup 2))
1699    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1700    (set (match_dup 4) (match_dup 2))
1701    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1702   "operands[2] = gen_lowpart (SImode, operands[1]);
1703    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1704
1705 (define_insn "*movdi_31"
1706   [(set (match_operand:DI 0 "nonimmediate_operand"
1707                             "=d,d,Q,S,d   ,o,!*f,!*f,!*f,!R,!T,d")
1708         (match_operand:DI 1 "general_operand"
1709                             " Q,S,d,d,dPRT,d, *f,  R,  T,*f,*f,b"))]
1710   "!TARGET_ZARCH"
1711   "@
1712    lm\t%0,%N0,%S1
1713    lmy\t%0,%N0,%S1
1714    stm\t%1,%N1,%S0
1715    stmy\t%1,%N1,%S0
1716    #
1717    #
1718    ldr\t%0,%1
1719    ld\t%0,%1
1720    ldy\t%0,%1
1721    std\t%1,%0
1722    stdy\t%1,%0
1723    #"
1724   [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1725    (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1726    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1727
1728 ; For a load from a symbol ref we can use one of the target registers
1729 ; together with larl to load the address.
1730 (define_split
1731   [(set (match_operand:DI 0 "register_operand" "")
1732         (match_operand:DI 1 "memory_operand" ""))]
1733   "!TARGET_ZARCH && reload_completed && TARGET_Z10
1734    && larl_operand (XEXP (operands[1], 0), SImode)"
1735   [(set (match_dup 2) (match_dup 3))
1736    (set (match_dup 0) (match_dup 1))]
1737 {
1738   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1739   operands[3] = XEXP (operands[1], 0);
1740   operands[1] = replace_equiv_address (operands[1], operands[2]);
1741 })
1742
1743 (define_split
1744   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1745         (match_operand:DI 1 "general_operand" ""))]
1746   "!TARGET_ZARCH && reload_completed
1747    && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1748   [(set (match_dup 2) (match_dup 4))
1749    (set (match_dup 3) (match_dup 5))]
1750 {
1751   operands[2] = operand_subword (operands[0], 0, 0, DImode);
1752   operands[3] = operand_subword (operands[0], 1, 0, DImode);
1753   operands[4] = operand_subword (operands[1], 0, 0, DImode);
1754   operands[5] = operand_subword (operands[1], 1, 0, DImode);
1755 })
1756
1757 (define_split
1758   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1759         (match_operand:DI 1 "general_operand" ""))]
1760   "!TARGET_ZARCH && reload_completed
1761    && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1762   [(set (match_dup 2) (match_dup 4))
1763    (set (match_dup 3) (match_dup 5))]
1764 {
1765   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1766   operands[3] = operand_subword (operands[0], 0, 0, DImode);
1767   operands[4] = operand_subword (operands[1], 1, 0, DImode);
1768   operands[5] = operand_subword (operands[1], 0, 0, DImode);
1769 })
1770
1771 (define_split
1772   [(set (match_operand:DI 0 "register_operand" "")
1773         (match_operand:DI 1 "memory_operand" ""))]
1774   "!TARGET_ZARCH && reload_completed
1775    && !FP_REG_P (operands[0])
1776    && !s_operand (operands[1], VOIDmode)"
1777   [(set (match_dup 0) (match_dup 1))]
1778 {
1779   rtx addr = operand_subword (operands[0], 1, 0, DImode);
1780   s390_load_address (addr, XEXP (operands[1], 0));
1781   operands[1] = replace_equiv_address (operands[1], addr);
1782 })
1783
1784 (define_peephole2
1785   [(set (match_operand:DI 0 "register_operand" "")
1786         (mem:DI (match_operand 1 "address_operand" "")))]
1787   "TARGET_ZARCH
1788    && !FP_REG_P (operands[0])
1789    && GET_CODE (operands[1]) == SYMBOL_REF
1790    && CONSTANT_POOL_ADDRESS_P (operands[1])
1791    && get_pool_mode (operands[1]) == DImode
1792    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1793   [(set (match_dup 0) (match_dup 2))]
1794   "operands[2] = get_pool_constant (operands[1]);")
1795
1796 (define_insn "*la_64"
1797   [(set (match_operand:DI 0 "register_operand" "=d,d")
1798         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1799   "TARGET_64BIT"
1800   "@
1801    la\t%0,%a1
1802    lay\t%0,%a1"
1803   [(set_attr "op_type" "RX,RXY")
1804    (set_attr "type"    "la")
1805    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1806
1807 (define_peephole2
1808   [(parallel
1809     [(set (match_operand:DI 0 "register_operand" "")
1810           (match_operand:QI 1 "address_operand" ""))
1811      (clobber (reg:CC CC_REGNUM))])]
1812   "TARGET_64BIT
1813    && preferred_la_operand_p (operands[1], const0_rtx)"
1814   [(set (match_dup 0) (match_dup 1))]
1815   "")
1816
1817 (define_peephole2
1818   [(set (match_operand:DI 0 "register_operand" "")
1819         (match_operand:DI 1 "register_operand" ""))
1820    (parallel
1821     [(set (match_dup 0)
1822           (plus:DI (match_dup 0)
1823                    (match_operand:DI 2 "nonmemory_operand" "")))
1824      (clobber (reg:CC CC_REGNUM))])]
1825   "TARGET_64BIT
1826    && !reg_overlap_mentioned_p (operands[0], operands[2])
1827    && preferred_la_operand_p (operands[1], operands[2])"
1828   [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1829   "")
1830
1831 ;
1832 ; movsi instruction pattern(s).
1833 ;
1834
1835 (define_expand "movsi"
1836   [(set (match_operand:SI 0 "general_operand" "")
1837         (match_operand:SI 1 "general_operand" ""))]
1838   ""
1839 {
1840   /* Handle symbolic constants.  */
1841   if (!TARGET_64BIT
1842       && (SYMBOLIC_CONST (operands[1])
1843           || (GET_CODE (operands[1]) == PLUS
1844               && XEXP (operands[1], 0) == pic_offset_table_rtx
1845               && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1846     emit_symbolic_move (operands);
1847 })
1848
1849 (define_insn "*movsi_larl"
1850   [(set (match_operand:SI 0 "register_operand" "=d")
1851         (match_operand:SI 1 "larl_operand" "X"))]
1852   "!TARGET_64BIT && TARGET_CPU_ZARCH
1853    && !FP_REG_P (operands[0])"
1854   "larl\t%0,%1"
1855    [(set_attr "op_type" "RIL")
1856     (set_attr "type"    "larl")
1857     (set_attr "z10prop" "z10_fwd_A1")])
1858
1859 (define_insn "*movsi_zarch"
1860   [(set (match_operand:SI 0 "nonimmediate_operand"
1861          "=d,    d,    d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
1862         (match_operand:SI 1 "general_operand"
1863          " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f,  R,  R,  T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
1864   "TARGET_ZARCH"
1865   "@
1866    lhi\t%0,%h1
1867    llilh\t%0,%i1
1868    llill\t%0,%i1
1869    iilf\t%0,%o1
1870    lay\t%0,%a1
1871    lrl\t%0,%1
1872    lr\t%0,%1
1873    l\t%0,%1
1874    ly\t%0,%1
1875    st\t%1,%0
1876    sty\t%1,%0
1877    lder\t%0,%1
1878    ler\t%0,%1
1879    lde\t%0,%1
1880    le\t%0,%1
1881    ley\t%0,%1
1882    ste\t%1,%0
1883    stey\t%1,%0
1884    ear\t%0,%1
1885    sar\t%0,%1
1886    stam\t%1,%1,%S0
1887    strl\t%1,%0
1888    mvhi\t%0,%1
1889    lam\t%0,%0,%S1
1890    vleif\t%v0,%h1,0
1891    vlr\t%v0,%v1
1892    vlvgf\t%v0,%1,0
1893    vlgvf\t%0,%v1,0
1894    vlef\t%v0,%1,0
1895    vstef\t%v1,%0,0"
1896   [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1897                         RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1898    (set_attr "type" "*,
1899                      *,
1900                      *,
1901                      *,
1902                      la,
1903                      larl,
1904                      lr,
1905                      load,
1906                      load,
1907                      store,
1908                      store,
1909                      floadsf,
1910                      floadsf,
1911                      floadsf,
1912                      floadsf,
1913                      floadsf,
1914                      fstoresf,
1915                      fstoresf,
1916                      *,
1917                      *,
1918                      *,
1919                      larl,
1920                      *,
1921                      *,*,*,*,*,*,*")
1922    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1923                              vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1924    (set_attr "z10prop" "z10_fwd_A1,
1925                         z10_fwd_E1,
1926                         z10_fwd_E1,
1927                         z10_fwd_A1,
1928                         z10_fwd_A1,
1929                         z10_fwd_A3,
1930                         z10_fr_E1,
1931                         z10_fwd_A3,
1932                         z10_fwd_A3,
1933                         z10_rec,
1934                         z10_rec,
1935                         *,
1936                         *,
1937                         *,
1938                         *,
1939                         *,
1940                         *,
1941                         *,
1942                         z10_super_E1,
1943                         z10_super,
1944                         *,
1945                         z10_rec,
1946                         z10_super,
1947                         *,*,*,*,*,*,*")])
1948
1949 (define_insn "*movsi_esa"
1950   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
1951         (match_operand:SI 1 "general_operand"       "K,d,R,d, *f, *f,  R,  R,*f,t,d,t,Q"))]
1952   "!TARGET_ZARCH"
1953   "@
1954    lhi\t%0,%h1
1955    lr\t%0,%1
1956    l\t%0,%1
1957    st\t%1,%0
1958    lder\t%0,%1
1959    ler\t%0,%1
1960    lde\t%0,%1
1961    le\t%0,%1
1962    ste\t%1,%0
1963    ear\t%0,%1
1964    sar\t%0,%1
1965    stam\t%1,%1,%S0
1966    lam\t%0,%0,%S1"
1967   [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
1968    (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
1969    (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
1970                         z10_super,*,*")
1971    (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
1972 ])
1973
1974 (define_peephole2
1975   [(set (match_operand:SI 0 "register_operand" "")
1976         (mem:SI (match_operand 1 "address_operand" "")))]
1977   "!FP_REG_P (operands[0])
1978    && GET_CODE (operands[1]) == SYMBOL_REF
1979    && CONSTANT_POOL_ADDRESS_P (operands[1])
1980    && get_pool_mode (operands[1]) == SImode
1981    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1982   [(set (match_dup 0) (match_dup 2))]
1983   "operands[2] = get_pool_constant (operands[1]);")
1984
1985 (define_insn "*la_31"
1986   [(set (match_operand:SI 0 "register_operand" "=d,d")
1987         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1988   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1989   "@
1990    la\t%0,%a1
1991    lay\t%0,%a1"
1992   [(set_attr "op_type"  "RX,RXY")
1993    (set_attr "type"     "la")
1994    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1995
1996 (define_peephole2
1997   [(parallel
1998     [(set (match_operand:SI 0 "register_operand" "")
1999           (match_operand:QI 1 "address_operand" ""))
2000      (clobber (reg:CC CC_REGNUM))])]
2001   "!TARGET_64BIT
2002    && preferred_la_operand_p (operands[1], const0_rtx)"
2003   [(set (match_dup 0) (match_dup 1))]
2004   "")
2005
2006 (define_peephole2
2007   [(set (match_operand:SI 0 "register_operand" "")
2008         (match_operand:SI 1 "register_operand" ""))
2009    (parallel
2010     [(set (match_dup 0)
2011           (plus:SI (match_dup 0)
2012                    (match_operand:SI 2 "nonmemory_operand" "")))
2013      (clobber (reg:CC CC_REGNUM))])]
2014   "!TARGET_64BIT
2015    && !reg_overlap_mentioned_p (operands[0], operands[2])
2016    && preferred_la_operand_p (operands[1], operands[2])"
2017   [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2018   "")
2019
2020 (define_insn "*la_31_and"
2021   [(set (match_operand:SI 0 "register_operand" "=d,d")
2022         (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
2023                 (const_int 2147483647)))]
2024   "!TARGET_64BIT"
2025   "@
2026    la\t%0,%a1
2027    lay\t%0,%a1"
2028   [(set_attr "op_type"  "RX,RXY")
2029    (set_attr "type"     "la")
2030    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2031
2032 (define_insn_and_split "*la_31_and_cc"
2033   [(set (match_operand:SI 0 "register_operand" "=d")
2034         (and:SI (match_operand:QI 1 "address_operand" "p")
2035                 (const_int 2147483647)))
2036    (clobber (reg:CC CC_REGNUM))]
2037   "!TARGET_64BIT"
2038   "#"
2039   "&& reload_completed"
2040   [(set (match_dup 0)
2041         (and:SI (match_dup 1) (const_int 2147483647)))]
2042   ""
2043   [(set_attr "op_type"  "RX")
2044    (set_attr "type"     "la")])
2045
2046 (define_insn "force_la_31"
2047   [(set (match_operand:SI 0 "register_operand" "=d,d")
2048         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
2049    (use (const_int 0))]
2050   "!TARGET_64BIT"
2051   "@
2052    la\t%0,%a1
2053    lay\t%0,%a1"
2054   [(set_attr "op_type"  "RX")
2055    (set_attr "type"     "la")
2056    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2057
2058 ;
2059 ; movhi instruction pattern(s).
2060 ;
2061
2062 (define_expand "movhi"
2063   [(set (match_operand:HI 0 "nonimmediate_operand" "")
2064         (match_operand:HI 1 "general_operand" ""))]
2065   ""
2066 {
2067   /* Make it explicit that loading a register from memory
2068      always sign-extends (at least) to SImode.  */
2069   if (optimize && can_create_pseudo_p ()
2070       && register_operand (operands[0], VOIDmode)
2071       && GET_CODE (operands[1]) == MEM)
2072     {
2073       rtx tmp = gen_reg_rtx (SImode);
2074       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2075       emit_insn (gen_rtx_SET (tmp, ext));
2076       operands[1] = gen_lowpart (HImode, tmp);
2077     }
2078 })
2079
2080 (define_insn "*movhi"
2081   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
2082         (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
2083   ""
2084   "@
2085    lr\t%0,%1
2086    lhi\t%0,%h1
2087    lh\t%0,%1
2088    lhy\t%0,%1
2089    lhrl\t%0,%1
2090    sth\t%1,%0
2091    sthy\t%1,%0
2092    sthrl\t%1,%0
2093    mvhhi\t%0,%1
2094    vleih\t%v0,%h1,0
2095    vlr\t%v0,%v1
2096    vlvgh\t%v0,%1,0
2097    vlgvh\t%0,%v1,0
2098    vleh\t%v0,%1,0
2099    vsteh\t%v1,%0,0"
2100   [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2101    (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2102    (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
2103    (set_attr "z10prop" "z10_fr_E1,
2104                        z10_fwd_A1,
2105                        z10_super_E1,
2106                        z10_super_E1,
2107                        z10_super_E1,
2108                        z10_rec,
2109                        z10_rec,
2110                        z10_rec,
2111                        z10_super,*,*,*,*,*,*")])
2112
2113 (define_peephole2
2114   [(set (match_operand:HI 0 "register_operand" "")
2115         (mem:HI (match_operand 1 "address_operand" "")))]
2116   "GET_CODE (operands[1]) == SYMBOL_REF
2117    && CONSTANT_POOL_ADDRESS_P (operands[1])
2118    && get_pool_mode (operands[1]) == HImode
2119    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2120   [(set (match_dup 0) (match_dup 2))]
2121   "operands[2] = get_pool_constant (operands[1]);")
2122
2123 ;
2124 ; movqi instruction pattern(s).
2125 ;
2126
2127 (define_expand "movqi"
2128   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2129         (match_operand:QI 1 "general_operand" ""))]
2130   ""
2131 {
2132   /* On z/Architecture, zero-extending from memory to register
2133      is just as fast as a QImode load.  */
2134   if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2135       && register_operand (operands[0], VOIDmode)
2136       && GET_CODE (operands[1]) == MEM)
2137     {
2138       rtx tmp = gen_reg_rtx (DImode);
2139       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2140       emit_insn (gen_rtx_SET (tmp, ext));
2141       operands[1] = gen_lowpart (QImode, tmp);
2142     }
2143 })
2144
2145 (define_insn "*movqi"
2146   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
2147         (match_operand:QI 1 "general_operand"      " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
2148   ""
2149   "@
2150    lr\t%0,%1
2151    lhi\t%0,%b1
2152    ic\t%0,%1
2153    icy\t%0,%1
2154    stc\t%1,%0
2155    stcy\t%1,%0
2156    mvi\t%S0,%b1
2157    mviy\t%S0,%b1
2158    #
2159    vleib\t%v0,%b1,0
2160    vlr\t%v0,%v1
2161    vlvgb\t%v0,%1,0
2162    vlgvb\t%0,%v1,0
2163    vleb\t%v0,%1,0
2164    vsteb\t%v1,%0,0"
2165   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2166    (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2167    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
2168    (set_attr "z10prop" "z10_fr_E1,
2169                         z10_fwd_A1,
2170                         z10_super_E1,
2171                         z10_super_E1,
2172                         z10_rec,
2173                         z10_rec,
2174                         z10_super,
2175                         z10_super,
2176                         *,*,*,*,*,*,*")])
2177
2178 (define_peephole2
2179   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2180         (mem:QI (match_operand 1 "address_operand" "")))]
2181   "GET_CODE (operands[1]) == SYMBOL_REF
2182    && CONSTANT_POOL_ADDRESS_P (operands[1])
2183    && get_pool_mode (operands[1]) == QImode
2184    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2185   [(set (match_dup 0) (match_dup 2))]
2186   "operands[2] = get_pool_constant (operands[1]);")
2187
2188 ;
2189 ; movstrictqi instruction pattern(s).
2190 ;
2191
2192 (define_insn "*movstrictqi"
2193   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2194                          (match_operand:QI 1 "memory_operand" "R,T"))]
2195   ""
2196   "@
2197    ic\t%0,%1
2198    icy\t%0,%1"
2199   [(set_attr "op_type"  "RX,RXY")
2200    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2201
2202 ;
2203 ; movstricthi instruction pattern(s).
2204 ;
2205
2206 (define_insn "*movstricthi"
2207   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2208                          (match_operand:HI 1 "memory_operand" "Q,S"))
2209    (clobber (reg:CC CC_REGNUM))]
2210   ""
2211   "@
2212    icm\t%0,3,%S1
2213    icmy\t%0,3,%S1"
2214   [(set_attr "op_type" "RS,RSY")
2215    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2216
2217 ;
2218 ; movstrictsi instruction pattern(s).
2219 ;
2220
2221 (define_insn "movstrictsi"
2222   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2223                          (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2224   "TARGET_ZARCH"
2225   "@
2226    lr\t%0,%1
2227    l\t%0,%1
2228    ly\t%0,%1
2229    ear\t%0,%1"
2230   [(set_attr "op_type" "RR,RX,RXY,RRE")
2231    (set_attr "type" "lr,load,load,*")
2232    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2233
2234 ;
2235 ; mov(tf|td) instruction pattern(s).
2236 ;
2237
2238 (define_expand "mov<mode>"
2239   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2240         (match_operand:TD_TF 1 "general_operand"      ""))]
2241   ""
2242   "")
2243
2244 (define_insn "*mov<mode>_64"
2245   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS,  d,o")
2246         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dRT,d"))]
2247   "TARGET_ZARCH"
2248   "@
2249    lzxr\t%0
2250    lxr\t%0,%1
2251    #
2252    #
2253    lmg\t%0,%N0,%S1
2254    stmg\t%1,%N1,%S0
2255    #
2256    #"
2257   [(set_attr "op_type"      "RRE,RRE,*,*,RSY,RSY,*,*")
2258    (set_attr "type"         "fsimptf,fsimptf,*,*,lm,stm,*,*")
2259    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2260
2261 (define_insn "*mov<mode>_31"
2262   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2263         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
2264   "!TARGET_ZARCH"
2265   "@
2266    lzxr\t%0
2267    lxr\t%0,%1
2268    #
2269    #"
2270   [(set_attr "op_type"      "RRE,RRE,*,*")
2271    (set_attr "type"         "fsimptf,fsimptf,*,*")
2272    (set_attr "cpu_facility" "z196,*,*,*")])
2273
2274 ; TFmode in GPRs splitters
2275
2276 (define_split
2277   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2278         (match_operand:TD_TF 1 "general_operand"      ""))]
2279   "TARGET_ZARCH && reload_completed
2280    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2281   [(set (match_dup 2) (match_dup 4))
2282    (set (match_dup 3) (match_dup 5))]
2283 {
2284   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2285   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2286   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2287   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2288 })
2289
2290 (define_split
2291   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2292         (match_operand:TD_TF 1 "general_operand"      ""))]
2293   "TARGET_ZARCH && reload_completed
2294    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2295   [(set (match_dup 2) (match_dup 4))
2296    (set (match_dup 3) (match_dup 5))]
2297 {
2298   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2299   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2300   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2301   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2302 })
2303
2304 (define_split
2305   [(set (match_operand:TD_TF 0 "register_operand" "")
2306         (match_operand:TD_TF 1 "memory_operand"   ""))]
2307   "TARGET_ZARCH && reload_completed
2308    && GENERAL_REG_P (operands[0])
2309    && !s_operand (operands[1], VOIDmode)"
2310   [(set (match_dup 0) (match_dup 1))]
2311 {
2312   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2313   addr = gen_lowpart (Pmode, addr);
2314   s390_load_address (addr, XEXP (operands[1], 0));
2315   operands[1] = replace_equiv_address (operands[1], addr);
2316 })
2317
2318 ; TFmode in BFPs splitters
2319
2320 (define_split
2321   [(set (match_operand:TD_TF 0 "register_operand" "")
2322         (match_operand:TD_TF 1 "memory_operand" ""))]
2323   "reload_completed && offsettable_memref_p (operands[1])
2324    && FP_REG_P (operands[0])"
2325   [(set (match_dup 2) (match_dup 4))
2326    (set (match_dup 3) (match_dup 5))]
2327 {
2328   operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2329                                      <MODE>mode, 0);
2330   operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2331                                      <MODE>mode, 8);
2332   operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2333   operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2334 })
2335
2336 (define_split
2337   [(set (match_operand:TD_TF 0 "memory_operand" "")
2338         (match_operand:TD_TF 1 "register_operand" ""))]
2339   "reload_completed && offsettable_memref_p (operands[0])
2340    && FP_REG_P (operands[1])"
2341   [(set (match_dup 2) (match_dup 4))
2342    (set (match_dup 3) (match_dup 5))]
2343 {
2344   operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2345   operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2346   operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2347                                      <MODE>mode, 0);
2348   operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2349                                      <MODE>mode, 8);
2350 })
2351
2352 ;
2353 ; mov(df|dd) instruction pattern(s).
2354 ;
2355
2356 (define_expand "mov<mode>"
2357   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2358         (match_operand:DD_DF 1 "general_operand"  ""))]
2359   ""
2360   "")
2361
2362 (define_insn "*mov<mode>_64dfp"
2363   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2364                                "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
2365         (match_operand:DD_DF 1 "general_operand"
2366                                " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
2367   "TARGET_DFP"
2368   "@
2369    lzdr\t%0
2370    ldr\t%0,%1
2371    ldgr\t%0,%1
2372    lgdr\t%0,%1
2373    ld\t%0,%1
2374    ldy\t%0,%1
2375    std\t%1,%0
2376    stdy\t%1,%0
2377    lghi\t%0,0
2378    lgr\t%0,%1
2379    lgrl\t%0,%1
2380    lg\t%0,%1
2381    stgrl\t%1,%0
2382    stg\t%1,%0
2383    vlr\t%v0,%v1
2384    vlvgg\t%v0,%1,0
2385    vlgvg\t%0,%v1,0
2386    vleg\t%0,%1,0
2387    vsteg\t%1,%0,0"
2388   [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2389    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2390                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2391    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2392    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2393
2394 (define_insn "*mov<mode>_64"
2395   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
2396         (match_operand:DD_DF 1 "general_operand"      " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
2397   "TARGET_ZARCH"
2398   "@
2399    lzdr\t%0
2400    ldr\t%0,%1
2401    ld\t%0,%1
2402    ldy\t%0,%1
2403    std\t%1,%0
2404    stdy\t%1,%0
2405    lghi\t%0,0
2406    lgr\t%0,%1
2407    lgrl\t%0,%1
2408    lg\t%0,%1
2409    stgrl\t%1,%0
2410    stg\t%1,%0
2411    vlr\t%v0,%v1
2412    vleg\t%v0,%1,0
2413    vsteg\t%v1,%0,0"
2414   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2415    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2416                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2417    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2418    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
2419
2420 (define_insn "*mov<mode>_31"
2421   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2422                                "=f,f,f,f,R,T,d,d,Q,S,   d,o")
2423         (match_operand:DD_DF 1 "general_operand"
2424                                " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2425   "!TARGET_ZARCH"
2426   "@
2427    lzdr\t%0
2428    ldr\t%0,%1
2429    ld\t%0,%1
2430    ldy\t%0,%1
2431    std\t%1,%0
2432    stdy\t%1,%0
2433    lm\t%0,%N0,%S1
2434    lmy\t%0,%N0,%S1
2435    stm\t%1,%N1,%S0
2436    stmy\t%1,%N1,%S0
2437    #
2438    #"
2439   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2440    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2441                         fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2442    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2443
2444 (define_split
2445   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2446         (match_operand:DD_DF 1 "general_operand" ""))]
2447   "!TARGET_ZARCH && reload_completed
2448    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2449   [(set (match_dup 2) (match_dup 4))
2450    (set (match_dup 3) (match_dup 5))]
2451 {
2452   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2453   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2454   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2455   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2456 })
2457
2458 (define_split
2459   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2460         (match_operand:DD_DF 1 "general_operand" ""))]
2461   "!TARGET_ZARCH && reload_completed
2462    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2463   [(set (match_dup 2) (match_dup 4))
2464    (set (match_dup 3) (match_dup 5))]
2465 {
2466   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2467   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2468   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2469   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2470 })
2471
2472 (define_split
2473   [(set (match_operand:DD_DF 0 "register_operand" "")
2474         (match_operand:DD_DF 1 "memory_operand" ""))]
2475   "!TARGET_ZARCH && reload_completed
2476    && !FP_REG_P (operands[0])
2477    && !s_operand (operands[1], VOIDmode)"
2478   [(set (match_dup 0) (match_dup 1))]
2479 {
2480   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2481   s390_load_address (addr, XEXP (operands[1], 0));
2482   operands[1] = replace_equiv_address (operands[1], addr);
2483 })
2484
2485 ;
2486 ; mov(sf|sd) instruction pattern(s).
2487 ;
2488
2489 (define_insn "mov<mode>"
2490   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2491                                "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
2492         (match_operand:SD_SF 1 "general_operand"
2493                                " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
2494   ""
2495   "@
2496    lzer\t%0
2497    lder\t%0,%1
2498    ler\t%0,%1
2499    lde\t%0,%1
2500    le\t%0,%1
2501    ley\t%0,%1
2502    ste\t%1,%0
2503    stey\t%1,%0
2504    lhi\t%0,0
2505    lr\t%0,%1
2506    lrl\t%0,%1
2507    l\t%0,%1
2508    ly\t%0,%1
2509    strl\t%1,%0
2510    st\t%1,%0
2511    sty\t%1,%0
2512    vlr\t%v0,%v1
2513    vleif\t%v0,0
2514    vlvgf\t%v0,%1,0
2515    vlgvf\t%0,%v1,0
2516    vleg\t%0,%1,0
2517    vsteg\t%1,%0,0"
2518   [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2519    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2520                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2521    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2522    (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
2523
2524 ;
2525 ; movcc instruction pattern
2526 ;
2527
2528 (define_insn "movcc"
2529   [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2530         (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2531   ""
2532   "@
2533    lr\t%0,%1
2534    tmh\t%1,12288
2535    ipm\t%0
2536    l\t%0,%1
2537    ly\t%0,%1
2538    st\t%1,%0
2539    sty\t%1,%0"
2540   [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2541    (set_attr "type" "lr,*,*,load,load,store,store")
2542    (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2543    (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2544
2545 ;
2546 ; Block move (MVC) patterns.
2547 ;
2548
2549 (define_insn "*mvc"
2550   [(set (match_operand:BLK 0 "memory_operand" "=Q")
2551         (match_operand:BLK 1 "memory_operand" "Q"))
2552    (use (match_operand 2 "const_int_operand" "n"))]
2553   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2554   "mvc\t%O0(%2,%R0),%S1"
2555   [(set_attr "op_type" "SS")])
2556
2557 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2558 ; order to have it implemented with mvc.
2559
2560 (define_split
2561   [(set (match_operand:QI 0 "memory_operand" "")
2562         (match_operand:QI 1 "memory_operand" ""))]
2563   "reload_completed"
2564   [(parallel
2565     [(set (match_dup 0) (match_dup 1))
2566      (use (const_int 1))])]
2567 {
2568   operands[0] = adjust_address (operands[0], BLKmode, 0);
2569   operands[1] = adjust_address (operands[1], BLKmode, 0);
2570 })
2571
2572
2573 (define_peephole2
2574   [(parallel
2575     [(set (match_operand:BLK 0 "memory_operand" "")
2576           (match_operand:BLK 1 "memory_operand" ""))
2577      (use (match_operand 2 "const_int_operand" ""))])
2578    (parallel
2579     [(set (match_operand:BLK 3 "memory_operand" "")
2580           (match_operand:BLK 4 "memory_operand" ""))
2581      (use (match_operand 5 "const_int_operand" ""))])]
2582   "s390_offset_p (operands[0], operands[3], operands[2])
2583    && s390_offset_p (operands[1], operands[4], operands[2])
2584    && !s390_overlap_p (operands[0], operands[1],
2585                        INTVAL (operands[2]) + INTVAL (operands[5]))
2586    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2587   [(parallel
2588     [(set (match_dup 6) (match_dup 7))
2589      (use (match_dup 8))])]
2590   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2591    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2592    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2593
2594
2595 ;
2596 ; load_multiple pattern(s).
2597 ;
2598 ; ??? Due to reload problems with replacing registers inside match_parallel
2599 ; we currently support load_multiple/store_multiple only after reload.
2600 ;
2601
2602 (define_expand "load_multiple"
2603   [(match_par_dup 3 [(set (match_operand 0 "" "")
2604                           (match_operand 1 "" ""))
2605                      (use (match_operand 2 "" ""))])]
2606   "reload_completed"
2607 {
2608   machine_mode mode;
2609   int regno;
2610   int count;
2611   rtx from;
2612   int i, off;
2613
2614   /* Support only loading a constant number of fixed-point registers from
2615      memory and only bother with this if more than two */
2616   if (GET_CODE (operands[2]) != CONST_INT
2617       || INTVAL (operands[2]) < 2
2618       || INTVAL (operands[2]) > 16
2619       || GET_CODE (operands[1]) != MEM
2620       || GET_CODE (operands[0]) != REG
2621       || REGNO (operands[0]) >= 16)
2622     FAIL;
2623
2624   count = INTVAL (operands[2]);
2625   regno = REGNO (operands[0]);
2626   mode = GET_MODE (operands[0]);
2627   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2628     FAIL;
2629
2630   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2631   if (!can_create_pseudo_p ())
2632     {
2633       if (GET_CODE (XEXP (operands[1], 0)) == REG)
2634         {
2635           from = XEXP (operands[1], 0);
2636           off = 0;
2637         }
2638       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2639                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2640                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2641         {
2642           from = XEXP (XEXP (operands[1], 0), 0);
2643           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2644         }
2645       else
2646         FAIL;
2647     }
2648   else
2649     {
2650       from = force_reg (Pmode, XEXP (operands[1], 0));
2651       off = 0;
2652     }
2653
2654   for (i = 0; i < count; i++)
2655     XVECEXP (operands[3], 0, i)
2656       = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2657                      change_address (operands[1], mode,
2658                        plus_constant (Pmode, from,
2659                                       off + i * GET_MODE_SIZE (mode))));
2660 })
2661
2662 (define_insn "*load_multiple_di"
2663   [(match_parallel 0 "load_multiple_operation"
2664                    [(set (match_operand:DI 1 "register_operand" "=r")
2665                          (match_operand:DI 2 "s_operand" "QS"))])]
2666   "reload_completed && TARGET_ZARCH"
2667 {
2668   int words = XVECLEN (operands[0], 0);
2669   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2670   return "lmg\t%1,%0,%S2";
2671 }
2672    [(set_attr "op_type" "RSY")
2673     (set_attr "type"    "lm")])
2674
2675 (define_insn "*load_multiple_si"
2676   [(match_parallel 0 "load_multiple_operation"
2677                    [(set (match_operand:SI 1 "register_operand" "=r,r")
2678                          (match_operand:SI 2 "s_operand" "Q,S"))])]
2679   "reload_completed"
2680 {
2681   int words = XVECLEN (operands[0], 0);
2682   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2683   return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2684 }
2685    [(set_attr "op_type" "RS,RSY")
2686     (set_attr "type"    "lm")])
2687
2688 ;
2689 ; store multiple pattern(s).
2690 ;
2691
2692 (define_expand "store_multiple"
2693   [(match_par_dup 3 [(set (match_operand 0 "" "")
2694                           (match_operand 1 "" ""))
2695                      (use (match_operand 2 "" ""))])]
2696   "reload_completed"
2697 {
2698   machine_mode mode;
2699   int regno;
2700   int count;
2701   rtx to;
2702   int i, off;
2703
2704   /* Support only storing a constant number of fixed-point registers to
2705      memory and only bother with this if more than two.  */
2706   if (GET_CODE (operands[2]) != CONST_INT
2707       || INTVAL (operands[2]) < 2
2708       || INTVAL (operands[2]) > 16
2709       || GET_CODE (operands[0]) != MEM
2710       || GET_CODE (operands[1]) != REG
2711       || REGNO (operands[1]) >= 16)
2712     FAIL;
2713
2714   count = INTVAL (operands[2]);
2715   regno = REGNO (operands[1]);
2716   mode = GET_MODE (operands[1]);
2717   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2718     FAIL;
2719
2720   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2721
2722   if (!can_create_pseudo_p ())
2723     {
2724       if (GET_CODE (XEXP (operands[0], 0)) == REG)
2725         {
2726           to = XEXP (operands[0], 0);
2727           off = 0;
2728         }
2729       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2730                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2731                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2732         {
2733           to = XEXP (XEXP (operands[0], 0), 0);
2734           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2735         }
2736       else
2737         FAIL;
2738     }
2739   else
2740     {
2741       to = force_reg (Pmode, XEXP (operands[0], 0));
2742       off = 0;
2743     }
2744
2745   for (i = 0; i < count; i++)
2746     XVECEXP (operands[3], 0, i)
2747       = gen_rtx_SET (change_address (operands[0], mode,
2748                        plus_constant (Pmode, to,
2749                                       off + i * GET_MODE_SIZE (mode))),
2750                      gen_rtx_REG (mode, regno + i));
2751 })
2752
2753 (define_insn "*store_multiple_di"
2754   [(match_parallel 0 "store_multiple_operation"
2755                    [(set (match_operand:DI 1 "s_operand" "=QS")
2756                          (match_operand:DI 2 "register_operand" "r"))])]
2757   "reload_completed && TARGET_ZARCH"
2758 {
2759   int words = XVECLEN (operands[0], 0);
2760   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2761   return "stmg\t%2,%0,%S1";
2762 }
2763    [(set_attr "op_type" "RSY")
2764     (set_attr "type"    "stm")])
2765
2766
2767 (define_insn "*store_multiple_si"
2768   [(match_parallel 0 "store_multiple_operation"
2769                    [(set (match_operand:SI 1 "s_operand" "=Q,S")
2770                          (match_operand:SI 2 "register_operand" "r,r"))])]
2771   "reload_completed"
2772 {
2773   int words = XVECLEN (operands[0], 0);
2774   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2775   return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2776 }
2777    [(set_attr "op_type" "RS,RSY")
2778     (set_attr "type"    "stm")])
2779
2780 ;;
2781 ;; String instructions.
2782 ;;
2783
2784 (define_insn "*execute_rl"
2785   [(match_parallel 0 "execute_operation"
2786     [(unspec [(match_operand 1    "register_operand" "a")
2787               (match_operand 2    "" "")
2788               (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2789   "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2790    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2791   "exrl\t%1,%3"
2792   [(set_attr "op_type" "RIL")
2793    (set_attr "type"    "cs")])
2794
2795 (define_insn "*execute"
2796   [(match_parallel 0 "execute_operation"
2797     [(unspec [(match_operand 1 "register_operand" "a")
2798               (match_operand:BLK 2 "memory_operand" "R")
2799               (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2800   "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2801    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2802   "ex\t%1,%2"
2803   [(set_attr "op_type" "RX")
2804    (set_attr "type" "cs")])
2805
2806
2807 ;
2808 ; strlenM instruction pattern(s).
2809 ;
2810
2811 (define_expand "strlen<mode>"
2812   [(match_operand:P   0 "register_operand" "")  ; result
2813    (match_operand:BLK 1 "memory_operand" "")    ; input string
2814    (match_operand:SI  2 "immediate_operand" "") ; search character
2815    (match_operand:SI  3 "immediate_operand" "")] ; known alignment
2816   ""
2817 {
2818   if (!TARGET_VX || operands[2] != const0_rtx)
2819     emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2820                                       operands[2], operands[3]));
2821   else
2822     s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2823
2824   DONE;
2825 })
2826
2827 (define_expand "strlen_srst<mode>"
2828   [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2829    (parallel
2830     [(set (match_dup 4)
2831           (unspec:P [(const_int 0)
2832                       (match_operand:BLK 1 "memory_operand" "")
2833                       (reg:SI 0)
2834                       (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2835      (clobber (scratch:P))
2836      (clobber (reg:CC CC_REGNUM))])
2837    (parallel
2838     [(set (match_operand:P 0 "register_operand" "")
2839           (minus:P (match_dup 4) (match_dup 5)))
2840      (clobber (reg:CC CC_REGNUM))])]
2841   ""
2842 {
2843   operands[4] = gen_reg_rtx (Pmode);
2844   operands[5] = gen_reg_rtx (Pmode);
2845   emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2846   operands[1] = replace_equiv_address (operands[1], operands[5]);
2847 })
2848
2849 (define_insn "*strlen<mode>"
2850   [(set (match_operand:P 0 "register_operand" "=a")
2851         (unspec:P [(match_operand:P 2 "general_operand" "0")
2852                     (mem:BLK (match_operand:P 3 "register_operand" "1"))
2853                     (reg:SI 0)
2854                     (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2855    (clobber (match_scratch:P 1 "=a"))
2856    (clobber (reg:CC CC_REGNUM))]
2857   ""
2858   "srst\t%0,%1\;jo\t.-4"
2859   [(set_attr "length" "8")
2860    (set_attr "type" "vs")])
2861
2862 ;
2863 ; cmpstrM instruction pattern(s).
2864 ;
2865
2866 (define_expand "cmpstrsi"
2867   [(set (reg:SI 0) (const_int 0))
2868    (parallel
2869     [(clobber (match_operand 3 "" ""))
2870      (clobber (match_dup 4))
2871      (set (reg:CCU CC_REGNUM)
2872           (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2873                        (match_operand:BLK 2 "memory_operand" "")))
2874      (use (reg:SI 0))])
2875    (parallel
2876     [(set (match_operand:SI 0 "register_operand" "=d")
2877           (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2878      (clobber (reg:CC CC_REGNUM))])]
2879   ""
2880 {
2881   /* As the result of CMPINT is inverted compared to what we need,
2882      we have to swap the operands.  */
2883   rtx op1 = operands[2];
2884   rtx op2 = operands[1];
2885   rtx addr1 = gen_reg_rtx (Pmode);
2886   rtx addr2 = gen_reg_rtx (Pmode);
2887
2888   emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2889   emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2890   operands[1] = replace_equiv_address_nv (op1, addr1);
2891   operands[2] = replace_equiv_address_nv (op2, addr2);
2892   operands[3] = addr1;
2893   operands[4] = addr2;
2894 })
2895
2896 (define_insn "*cmpstr<mode>"
2897   [(clobber (match_operand:P 0 "register_operand" "=d"))
2898    (clobber (match_operand:P 1 "register_operand" "=d"))
2899    (set (reg:CCU CC_REGNUM)
2900         (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2901                      (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2902    (use (reg:SI 0))]
2903   ""
2904   "clst\t%0,%1\;jo\t.-4"
2905   [(set_attr "length" "8")
2906    (set_attr "type" "vs")])
2907
2908 ;
2909 ; movstr instruction pattern.
2910 ;
2911
2912 (define_expand "movstr"
2913   [(match_operand 0 "register_operand" "")
2914    (match_operand 1 "memory_operand" "")
2915    (match_operand 2 "memory_operand" "")]
2916   ""
2917 {
2918   if (TARGET_64BIT)
2919     emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
2920   else
2921     emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
2922   DONE;
2923 })
2924
2925 (define_expand "movstr<P:mode>"
2926   [(set (reg:SI 0) (const_int 0))
2927    (parallel
2928     [(clobber (match_dup 3))
2929      (set (match_operand:BLK 1 "memory_operand" "")
2930           (match_operand:BLK 2 "memory_operand" ""))
2931      (set (match_operand:P 0 "register_operand" "")
2932           (unspec:P [(match_dup 1)
2933                    (match_dup 2)
2934                    (reg:SI 0)] UNSPEC_MVST))
2935      (clobber (reg:CC CC_REGNUM))])]
2936   ""
2937 {
2938   rtx addr1 = gen_reg_rtx (Pmode);
2939   rtx addr2 = gen_reg_rtx (Pmode);
2940
2941   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2942   emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2943   operands[1] = replace_equiv_address_nv (operands[1], addr1);
2944   operands[2] = replace_equiv_address_nv (operands[2], addr2);
2945   operands[3] = addr2;
2946 })
2947
2948 (define_insn "*movstr"
2949   [(clobber (match_operand:P 2 "register_operand" "=d"))
2950    (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2951         (mem:BLK (match_operand:P 3 "register_operand" "2")))
2952    (set (match_operand:P 0 "register_operand" "=d")
2953         (unspec:P [(mem:BLK (match_dup 1))
2954                  (mem:BLK (match_dup 3))
2955                  (reg:SI 0)] UNSPEC_MVST))
2956    (clobber (reg:CC CC_REGNUM))]
2957   ""
2958   "mvst\t%1,%2\;jo\t.-4"
2959   [(set_attr "length" "8")
2960    (set_attr "type" "vs")])
2961
2962
2963 ;
2964 ; movmemM instruction pattern(s).
2965 ;
2966
2967 (define_expand "movmem<mode>"
2968   [(set (match_operand:BLK 0 "memory_operand" "")   ; destination
2969         (match_operand:BLK 1 "memory_operand" ""))  ; source
2970    (use (match_operand:GPR 2 "general_operand" "")) ; count
2971    (match_operand 3 "" "")]
2972   ""
2973 {
2974   if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2975     DONE;
2976   else
2977     FAIL;
2978 })
2979
2980 ; Move a block that is up to 256 bytes in length.
2981 ; The block length is taken as (operands[2] % 256) + 1.
2982
2983 (define_expand "movmem_short"
2984   [(parallel
2985     [(set (match_operand:BLK 0 "memory_operand" "")
2986           (match_operand:BLK 1 "memory_operand" ""))
2987      (use (match_operand 2 "nonmemory_operand" ""))
2988      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2989      (clobber (match_dup 3))])]
2990   ""
2991   "operands[3] = gen_rtx_SCRATCH (Pmode);")
2992
2993 (define_insn "*movmem_short"
2994   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2995         (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2996    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2997    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2998    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2999   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3000   "#"
3001   [(set_attr "type"         "cs")
3002    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3003
3004 (define_split
3005   [(set (match_operand:BLK 0 "memory_operand" "")
3006         (match_operand:BLK 1 "memory_operand" ""))
3007    (use (match_operand 2 "const_int_operand" ""))
3008    (use (match_operand 3 "immediate_operand" ""))
3009    (clobber (scratch))]
3010   "reload_completed"
3011   [(parallel
3012     [(set (match_dup 0) (match_dup 1))
3013      (use (match_dup 2))])]
3014   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3015
3016 (define_split
3017   [(set (match_operand:BLK 0 "memory_operand" "")
3018         (match_operand:BLK 1 "memory_operand" ""))
3019    (use (match_operand 2 "register_operand" ""))
3020    (use (match_operand 3 "memory_operand" ""))
3021    (clobber (scratch))]
3022   "reload_completed"
3023   [(parallel
3024     [(unspec [(match_dup 2) (match_dup 3)
3025               (const_int 0)] UNSPEC_EXECUTE)
3026      (set (match_dup 0) (match_dup 1))
3027      (use (const_int 1))])]
3028   "")
3029
3030 (define_split
3031   [(set (match_operand:BLK 0 "memory_operand" "")
3032         (match_operand:BLK 1 "memory_operand" ""))
3033    (use (match_operand 2 "register_operand" ""))
3034    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3035    (clobber (scratch))]
3036   "TARGET_Z10 && reload_completed"
3037   [(parallel
3038     [(unspec [(match_dup 2) (const_int 0)
3039               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3040      (set (match_dup 0) (match_dup 1))
3041      (use (const_int 1))])]
3042   "operands[3] = gen_label_rtx ();")
3043
3044 (define_split
3045   [(set (match_operand:BLK 0 "memory_operand" "")
3046         (match_operand:BLK 1 "memory_operand" ""))
3047    (use (match_operand 2 "register_operand" ""))
3048    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3049    (clobber (match_operand 3 "register_operand" ""))]
3050   "reload_completed && TARGET_CPU_ZARCH"
3051   [(set (match_dup 3) (label_ref (match_dup 4)))
3052    (parallel
3053     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3054               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3055      (set (match_dup 0) (match_dup 1))
3056      (use (const_int 1))])]
3057   "operands[4] = gen_label_rtx ();")
3058
3059 ; Move a block of arbitrary length.
3060
3061 (define_expand "movmem_long"
3062   [(parallel
3063     [(clobber (match_dup 2))
3064      (clobber (match_dup 3))
3065      (set (match_operand:BLK 0 "memory_operand" "")
3066           (match_operand:BLK 1 "memory_operand" ""))
3067      (use (match_operand 2 "general_operand" ""))
3068      (use (match_dup 3))
3069      (clobber (reg:CC CC_REGNUM))])]
3070   ""
3071 {
3072   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3073   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3074   rtx reg0 = gen_reg_rtx (dreg_mode);
3075   rtx reg1 = gen_reg_rtx (dreg_mode);
3076   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3077   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3078   rtx len0 = gen_lowpart (Pmode, reg0);
3079   rtx len1 = gen_lowpart (Pmode, reg1);
3080
3081   emit_clobber (reg0);
3082   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3083   emit_move_insn (len0, operands[2]);
3084
3085   emit_clobber (reg1);
3086   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3087   emit_move_insn (len1, operands[2]);
3088
3089   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3090   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3091   operands[2] = reg0;
3092   operands[3] = reg1;
3093 })
3094
3095 (define_insn "*movmem_long"
3096   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3097    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3098    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3099         (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3100    (use (match_dup 2))
3101    (use (match_dup 3))
3102    (clobber (reg:CC CC_REGNUM))]
3103   "TARGET_64BIT || !TARGET_ZARCH"
3104   "mvcle\t%0,%1,0\;jo\t.-4"
3105   [(set_attr "length" "8")
3106    (set_attr "type" "vs")])
3107
3108 (define_insn "*movmem_long_31z"
3109   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3110    (clobber (match_operand:TI 1 "register_operand" "=d"))
3111    (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3112         (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3113    (use (match_dup 2))
3114    (use (match_dup 3))
3115    (clobber (reg:CC CC_REGNUM))]
3116   "!TARGET_64BIT && TARGET_ZARCH"
3117   "mvcle\t%0,%1,0\;jo\t.-4"
3118   [(set_attr "length" "8")
3119    (set_attr "type" "vs")])
3120
3121
3122 ;
3123 ; Test data class.
3124 ;
3125
3126 (define_expand "signbit<mode>2"
3127   [(set (reg:CCZ CC_REGNUM)
3128         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3129                      (match_dup 2)]
3130                      UNSPEC_TDC_INSN))
3131    (set (match_operand:SI 0 "register_operand" "=d")
3132         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3133   "TARGET_HARD_FLOAT"
3134 {
3135   operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3136 })
3137
3138 (define_expand "isinf<mode>2"
3139   [(set (reg:CCZ CC_REGNUM)
3140         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3141                      (match_dup 2)]
3142                      UNSPEC_TDC_INSN))
3143    (set (match_operand:SI 0 "register_operand" "=d")
3144         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3145   "TARGET_HARD_FLOAT"
3146 {
3147   operands[2] = GEN_INT (S390_TDC_INFINITY);
3148 })
3149
3150 ; This extracts CC into a GPR properly shifted.  The actual IPM
3151 ; instruction will be issued by reload.  The constraint of operand 1
3152 ; forces reload to use a GPR.  So reload will issue a movcc insn for
3153 ; copying CC into a GPR first.
3154 (define_insn_and_split "*cc_to_int"
3155   [(set (match_operand:SI 0 "nonimmediate_operand"     "=d")
3156         (unspec:SI [(match_operand 1 "register_operand" "0")]
3157                    UNSPEC_CC_TO_INT))]
3158   "operands != NULL"
3159   "#"
3160   "reload_completed"
3161   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3162
3163 ; This insn is used to generate all variants of the Test Data Class
3164 ; instruction, namely tcxb, tcdb, and tceb.  The insn's first operand
3165 ; is the register to be tested and the second one is the bit mask
3166 ; specifying the required test(s).
3167 ;
3168 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3169 (define_insn "*TDC_insn_<mode>"
3170   [(set (reg:CCZ CC_REGNUM)
3171         (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3172                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3173   "TARGET_HARD_FLOAT"
3174   "t<_d>c<xde><bt>\t%0,%1"
3175    [(set_attr "op_type" "RXE")
3176     (set_attr "type"  "fsimp<mode>")])
3177
3178
3179
3180 ;
3181 ; setmemM instruction pattern(s).
3182 ;
3183
3184 (define_expand "setmem<mode>"
3185   [(set (match_operand:BLK 0 "memory_operand" "")
3186         (match_operand:QI 2 "general_operand" ""))
3187    (use (match_operand:GPR 1 "general_operand" ""))
3188    (match_operand 3 "" "")]
3189   ""
3190   "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3191
3192 ; Clear a block that is up to 256 bytes in length.
3193 ; The block length is taken as (operands[1] % 256) + 1.
3194
3195 (define_expand "clrmem_short"
3196   [(parallel
3197     [(set (match_operand:BLK 0 "memory_operand" "")
3198           (const_int 0))
3199      (use (match_operand 1 "nonmemory_operand" ""))
3200      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3201      (clobber (match_dup 2))
3202      (clobber (reg:CC CC_REGNUM))])]
3203   ""
3204   "operands[2] = gen_rtx_SCRATCH (Pmode);")
3205
3206 (define_insn "*clrmem_short"
3207   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3208         (const_int 0))
3209    (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3210    (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3211    (clobber (match_scratch:P 3 "=X,X,X,&a"))
3212    (clobber (reg:CC CC_REGNUM))]
3213   "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3214   "#"
3215   [(set_attr "type" "cs")
3216    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3217
3218 (define_split
3219   [(set (match_operand:BLK 0 "memory_operand" "")
3220         (const_int 0))
3221    (use (match_operand 1 "const_int_operand" ""))
3222    (use (match_operand 2 "immediate_operand" ""))
3223    (clobber (scratch))
3224    (clobber (reg:CC CC_REGNUM))]
3225   "reload_completed"
3226   [(parallel
3227     [(set (match_dup 0) (const_int 0))
3228      (use (match_dup 1))
3229      (clobber (reg:CC CC_REGNUM))])]
3230   "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3231
3232 (define_split
3233   [(set (match_operand:BLK 0 "memory_operand" "")
3234         (const_int 0))
3235    (use (match_operand 1 "register_operand" ""))
3236    (use (match_operand 2 "memory_operand" ""))
3237    (clobber (scratch))
3238    (clobber (reg:CC CC_REGNUM))]
3239   "reload_completed"
3240   [(parallel
3241     [(unspec [(match_dup 1) (match_dup 2)
3242               (const_int 0)] UNSPEC_EXECUTE)
3243      (set (match_dup 0) (const_int 0))
3244      (use (const_int 1))
3245      (clobber (reg:CC CC_REGNUM))])]
3246   "")
3247
3248 (define_split
3249   [(set (match_operand:BLK 0 "memory_operand" "")
3250         (const_int 0))
3251    (use (match_operand 1 "register_operand" ""))
3252    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3253    (clobber (scratch))
3254    (clobber (reg:CC CC_REGNUM))]
3255   "TARGET_Z10 && reload_completed"
3256   [(parallel
3257     [(unspec [(match_dup 1) (const_int 0)
3258               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3259      (set (match_dup 0) (const_int 0))
3260      (use (const_int 1))
3261      (clobber (reg:CC CC_REGNUM))])]
3262   "operands[3] = gen_label_rtx ();")
3263
3264 (define_split
3265   [(set (match_operand:BLK 0 "memory_operand" "")
3266         (const_int 0))
3267    (use (match_operand 1 "register_operand" ""))
3268    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3269    (clobber (match_operand 2 "register_operand" ""))
3270    (clobber (reg:CC CC_REGNUM))]
3271   "reload_completed && TARGET_CPU_ZARCH"
3272   [(set (match_dup 2) (label_ref (match_dup 3)))
3273    (parallel
3274     [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3275               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3276      (set (match_dup 0) (const_int 0))
3277      (use (const_int 1))
3278      (clobber (reg:CC CC_REGNUM))])]
3279   "operands[3] = gen_label_rtx ();")
3280
3281 ; Initialize a block of arbitrary length with (operands[2] % 256).
3282
3283 (define_expand "setmem_long"
3284   [(parallel
3285     [(clobber (match_dup 1))
3286      (set (match_operand:BLK 0 "memory_operand" "")
3287           (match_operand 2 "shift_count_or_setmem_operand" ""))
3288      (use (match_operand 1 "general_operand" ""))
3289      (use (match_dup 3))
3290      (clobber (reg:CC CC_REGNUM))])]
3291   ""
3292 {
3293   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3294   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3295   rtx reg0 = gen_reg_rtx (dreg_mode);
3296   rtx reg1 = gen_reg_rtx (dreg_mode);
3297   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3298   rtx len0 = gen_lowpart (Pmode, reg0);
3299
3300   emit_clobber (reg0);
3301   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3302   emit_move_insn (len0, operands[1]);
3303
3304   emit_move_insn (reg1, const0_rtx);
3305
3306   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3307   operands[1] = reg0;
3308   operands[3] = reg1;
3309 })
3310
3311 (define_insn "*setmem_long"
3312   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3313    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3314         (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3315    (use (match_dup 3))
3316    (use (match_operand:<DBL> 1 "register_operand" "d"))
3317    (clobber (reg:CC CC_REGNUM))]
3318   "TARGET_64BIT || !TARGET_ZARCH"
3319   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3320   [(set_attr "length" "8")
3321    (set_attr "type" "vs")])
3322
3323 (define_insn "*setmem_long_and"
3324   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3325    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3326         (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3327              (match_operand 4 "const_int_operand"             "n")))
3328    (use (match_dup 3))
3329    (use (match_operand:<DBL> 1 "register_operand" "d"))
3330    (clobber (reg:CC CC_REGNUM))]
3331   "(TARGET_64BIT || !TARGET_ZARCH) &&
3332    (INTVAL (operands[4]) & 255) == 255"
3333   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3334   [(set_attr "length" "8")
3335    (set_attr "type" "vs")])
3336
3337 (define_insn "*setmem_long_31z"
3338   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3339    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3340         (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3341    (use (match_dup 3))
3342    (use (match_operand:TI 1 "register_operand" "d"))
3343    (clobber (reg:CC CC_REGNUM))]
3344   "!TARGET_64BIT && TARGET_ZARCH"
3345   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3346   [(set_attr "length" "8")
3347    (set_attr "type" "vs")])
3348
3349 ;
3350 ; cmpmemM instruction pattern(s).
3351 ;
3352
3353 (define_expand "cmpmemsi"
3354   [(set (match_operand:SI 0 "register_operand" "")
3355         (compare:SI (match_operand:BLK 1 "memory_operand" "")
3356                     (match_operand:BLK 2 "memory_operand" "") ) )
3357    (use (match_operand:SI 3 "general_operand" ""))
3358    (use (match_operand:SI 4 "" ""))]
3359   ""
3360 {
3361   if (s390_expand_cmpmem (operands[0], operands[1],
3362                           operands[2], operands[3]))
3363     DONE;
3364   else
3365     FAIL;
3366 })
3367
3368 ; Compare a block that is up to 256 bytes in length.
3369 ; The block length is taken as (operands[2] % 256) + 1.
3370
3371 (define_expand "cmpmem_short"
3372   [(parallel
3373     [(set (reg:CCU CC_REGNUM)
3374           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3375                        (match_operand:BLK 1 "memory_operand" "")))
3376      (use (match_operand 2 "nonmemory_operand" ""))
3377      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3378      (clobber (match_dup 3))])]
3379   ""
3380   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3381
3382 (define_insn "*cmpmem_short"
3383   [(set (reg:CCU CC_REGNUM)
3384         (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3385                      (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3386    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3387    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3388    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3389   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3390   "#"
3391   [(set_attr "type" "cs")
3392    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3393
3394 (define_split
3395   [(set (reg:CCU CC_REGNUM)
3396         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3397                      (match_operand:BLK 1 "memory_operand" "")))
3398    (use (match_operand 2 "const_int_operand" ""))
3399    (use (match_operand 3 "immediate_operand" ""))
3400    (clobber (scratch))]
3401   "reload_completed"
3402   [(parallel
3403     [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3404      (use (match_dup 2))])]
3405   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3406
3407 (define_split
3408   [(set (reg:CCU CC_REGNUM)
3409         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3410                      (match_operand:BLK 1 "memory_operand" "")))
3411    (use (match_operand 2 "register_operand" ""))
3412    (use (match_operand 3 "memory_operand" ""))
3413    (clobber (scratch))]
3414   "reload_completed"
3415   [(parallel
3416     [(unspec [(match_dup 2) (match_dup 3)
3417               (const_int 0)] UNSPEC_EXECUTE)
3418      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3419      (use (const_int 1))])]
3420   "")
3421
3422 (define_split
3423   [(set (reg:CCU CC_REGNUM)
3424         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3425                      (match_operand:BLK 1 "memory_operand" "")))
3426    (use (match_operand 2 "register_operand" ""))
3427    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3428    (clobber (scratch))]
3429   "TARGET_Z10 && reload_completed"
3430   [(parallel
3431     [(unspec [(match_dup 2) (const_int 0)
3432               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3433      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3434      (use (const_int 1))])]
3435   "operands[4] = gen_label_rtx ();")
3436
3437 (define_split
3438   [(set (reg:CCU CC_REGNUM)
3439         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3440                      (match_operand:BLK 1 "memory_operand" "")))
3441    (use (match_operand 2 "register_operand" ""))
3442    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3443    (clobber (match_operand 3 "register_operand" ""))]
3444   "reload_completed && TARGET_CPU_ZARCH"
3445   [(set (match_dup 3) (label_ref (match_dup 4)))
3446    (parallel
3447     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3448               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3449      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3450      (use (const_int 1))])]
3451   "operands[4] = gen_label_rtx ();")
3452
3453 ; Compare a block of arbitrary length.
3454
3455 (define_expand "cmpmem_long"
3456   [(parallel
3457     [(clobber (match_dup 2))
3458      (clobber (match_dup 3))
3459      (set (reg:CCU CC_REGNUM)
3460           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3461                        (match_operand:BLK 1 "memory_operand" "")))
3462      (use (match_operand 2 "general_operand" ""))
3463      (use (match_dup 3))])]
3464   ""
3465 {
3466   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3467   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3468   rtx reg0 = gen_reg_rtx (dreg_mode);
3469   rtx reg1 = gen_reg_rtx (dreg_mode);
3470   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3471   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3472   rtx len0 = gen_lowpart (Pmode, reg0);
3473   rtx len1 = gen_lowpart (Pmode, reg1);
3474
3475   emit_clobber (reg0);
3476   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3477   emit_move_insn (len0, operands[2]);
3478
3479   emit_clobber (reg1);
3480   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3481   emit_move_insn (len1, operands[2]);
3482
3483   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3484   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3485   operands[2] = reg0;
3486   operands[3] = reg1;
3487 })
3488
3489 (define_insn "*cmpmem_long"
3490   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3491    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3492    (set (reg:CCU CC_REGNUM)
3493         (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3494                      (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3495    (use (match_dup 2))
3496    (use (match_dup 3))]
3497   "TARGET_64BIT || !TARGET_ZARCH"
3498   "clcle\t%0,%1,0\;jo\t.-4"
3499   [(set_attr "length" "8")
3500    (set_attr "type" "vs")])
3501
3502 (define_insn "*cmpmem_long_31z"
3503   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3504    (clobber (match_operand:TI 1 "register_operand" "=d"))
3505    (set (reg:CCU CC_REGNUM)
3506         (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3507                      (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3508    (use (match_dup 2))
3509    (use (match_dup 3))]
3510   "!TARGET_64BIT && TARGET_ZARCH"
3511   "clcle\t%0,%1,0\;jo\t.-4"
3512   [(set_attr "op_type" "NN")
3513    (set_attr "type"    "vs")
3514    (set_attr "length"  "8")])
3515
3516 ; Convert CCUmode condition code to integer.
3517 ; Result is zero if EQ, positive if LTU, negative if GTU.
3518
3519 (define_insn_and_split "cmpint"
3520   [(set (match_operand:SI 0 "register_operand" "=d")
3521         (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3522                    UNSPEC_STRCMPCC_TO_INT))
3523    (clobber (reg:CC CC_REGNUM))]
3524   ""
3525   "#"
3526   "reload_completed"
3527   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3528    (parallel
3529     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3530      (clobber (reg:CC CC_REGNUM))])])
3531
3532 (define_insn_and_split "*cmpint_cc"
3533   [(set (reg CC_REGNUM)
3534         (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3535                             UNSPEC_STRCMPCC_TO_INT)
3536                  (const_int 0)))
3537    (set (match_operand:SI 0 "register_operand" "=d")
3538         (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3539   "s390_match_ccmode (insn, CCSmode)"
3540   "#"
3541   "&& reload_completed"
3542   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3543    (parallel
3544     [(set (match_dup 2) (match_dup 3))
3545      (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3546 {
3547   rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3548   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3549   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3550 })
3551
3552 (define_insn_and_split "*cmpint_sign"
3553   [(set (match_operand:DI 0 "register_operand" "=d")
3554         (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3555                                    UNSPEC_STRCMPCC_TO_INT)))
3556    (clobber (reg:CC CC_REGNUM))]
3557   "TARGET_ZARCH"
3558   "#"
3559   "&& reload_completed"
3560   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3561    (parallel
3562     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3563      (clobber (reg:CC CC_REGNUM))])])
3564
3565 (define_insn_and_split "*cmpint_sign_cc"
3566   [(set (reg CC_REGNUM)
3567         (compare (ashiftrt:DI (ashift:DI (subreg:DI
3568                    (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3569                               UNSPEC_STRCMPCC_TO_INT) 0)
3570                    (const_int 32)) (const_int 32))
3571                  (const_int 0)))
3572    (set (match_operand:DI 0 "register_operand" "=d")
3573         (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3574   "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3575   "#"
3576   "&& reload_completed"
3577   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3578    (parallel
3579     [(set (match_dup 2) (match_dup 3))
3580      (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3581 {
3582   rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3583   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3584   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3585 })
3586
3587
3588 ;;
3589 ;;- Conversion instructions.
3590 ;;
3591
3592 (define_insn "*sethighpartsi"
3593   [(set (match_operand:SI 0 "register_operand" "=d,d")
3594         (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3595                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3596    (clobber (reg:CC CC_REGNUM))]
3597   ""
3598   "@
3599    icm\t%0,%2,%S1
3600    icmy\t%0,%2,%S1"
3601   [(set_attr "op_type" "RS,RSY")
3602    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3603
3604 (define_insn "*sethighpartdi_64"
3605   [(set (match_operand:DI 0 "register_operand" "=d")
3606         (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3607                     (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3608    (clobber (reg:CC CC_REGNUM))]
3609   "TARGET_ZARCH"
3610   "icmh\t%0,%2,%S1"
3611   [(set_attr "op_type" "RSY")
3612    (set_attr "z10prop" "z10_super")])
3613
3614 (define_insn "*sethighpartdi_31"
3615   [(set (match_operand:DI 0 "register_operand" "=d,d")
3616         (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3617                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3618    (clobber (reg:CC CC_REGNUM))]
3619   "!TARGET_ZARCH"
3620   "@
3621    icm\t%0,%2,%S1
3622    icmy\t%0,%2,%S1"
3623   [(set_attr "op_type" "RS,RSY")
3624    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3625
3626 ;
3627 ; extv instruction patterns
3628 ;
3629
3630 ; FIXME: This expander needs to be converted from DI to GPR as well
3631 ; after resolving some issues with it.
3632
3633 (define_expand "extzv"
3634   [(parallel
3635     [(set (match_operand:DI 0 "register_operand" "=d")
3636         (zero_extract:DI
3637          (match_operand:DI 1 "register_operand" "d")
3638          (match_operand 2 "const_int_operand" "")   ; size
3639          (match_operand 3 "const_int_operand" ""))) ; start
3640      (clobber (reg:CC CC_REGNUM))])]
3641   "TARGET_Z10"
3642 {
3643   /* Starting with zEC12 there is risbgn not clobbering CC.  */
3644   if (TARGET_ZEC12)
3645     {
3646       emit_move_insn (operands[0],
3647                     gen_rtx_ZERO_EXTRACT (DImode,
3648                                           operands[1],
3649                                           operands[2],
3650                                           operands[3]));
3651       DONE;
3652     }
3653 })
3654
3655 (define_insn "*extzv<mode>_zEC12"
3656   [(set (match_operand:GPR 0 "register_operand" "=d")
3657       (zero_extract:GPR
3658         (match_operand:GPR 1 "register_operand" "d")
3659         (match_operand 2 "const_int_operand" "")   ; size
3660         (match_operand 3 "const_int_operand" "")))] ; start]
3661   "TARGET_ZEC12"
3662   "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3663   [(set_attr "op_type" "RIE")])
3664
3665 (define_insn "*extzv<mode>_z10"
3666   [(set (match_operand:GPR 0 "register_operand" "=d")
3667       (zero_extract:GPR
3668        (match_operand:GPR 1 "register_operand" "d")
3669        (match_operand 2 "const_int_operand" "")   ; size
3670        (match_operand 3 "const_int_operand" ""))) ; start
3671    (clobber (reg:CC CC_REGNUM))]
3672   "TARGET_Z10"
3673   "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3674   [(set_attr "op_type" "RIE")
3675    (set_attr "z10prop" "z10_super_E1")])
3676
3677 (define_insn_and_split "*pre_z10_extzv<mode>"
3678   [(set (match_operand:GPR 0 "register_operand" "=d")
3679         (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3680                           (match_operand 2 "nonzero_shift_count_operand" "")
3681                           (const_int 0)))
3682    (clobber (reg:CC CC_REGNUM))]
3683   "!TARGET_Z10"
3684   "#"
3685   "&& reload_completed"
3686   [(parallel
3687     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3688      (clobber (reg:CC CC_REGNUM))])
3689    (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3690 {
3691   int bitsize = INTVAL (operands[2]);
3692   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3693   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3694
3695   operands[1] = adjust_address (operands[1], BLKmode, 0);
3696   set_mem_size (operands[1], size);
3697   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3698   operands[3] = GEN_INT (mask);
3699 })
3700
3701 (define_insn_and_split "*pre_z10_extv<mode>"
3702   [(set (match_operand:GPR 0 "register_operand" "=d")
3703         (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3704                           (match_operand 2 "nonzero_shift_count_operand" "")
3705                           (const_int 0)))
3706    (clobber (reg:CC CC_REGNUM))]
3707   ""
3708   "#"
3709   "&& reload_completed"
3710   [(parallel
3711     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3712      (clobber (reg:CC CC_REGNUM))])
3713    (parallel
3714     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3715      (clobber (reg:CC CC_REGNUM))])]
3716 {
3717   int bitsize = INTVAL (operands[2]);
3718   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3719   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3720
3721   operands[1] = adjust_address (operands[1], BLKmode, 0);
3722   set_mem_size (operands[1], size);
3723   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3724   operands[3] = GEN_INT (mask);
3725 })
3726
3727 ;
3728 ; insv instruction patterns
3729 ;
3730
3731 (define_expand "insv"
3732   [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3733                       (match_operand 1 "const_int_operand" "")
3734                       (match_operand 2 "const_int_operand" ""))
3735         (match_operand 3 "general_operand" ""))]
3736   ""
3737 {
3738   if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3739     DONE;
3740   FAIL;
3741 })
3742
3743
3744 ; The normal RTL expansion will never generate a zero_extract where
3745 ; the location operand isn't word mode.  However, we do this in the
3746 ; back-end when generating atomic operations. See s390_two_part_insv.
3747 (define_insn "*insv<mode>_zEC12"
3748   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3749                           (match_operand 1 "const_int_operand"    "I")  ; size
3750                           (match_operand 2 "const_int_operand"    "I")) ; pos
3751         (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3752   "TARGET_ZEC12
3753    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3754   "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3755   [(set_attr "op_type" "RIE")])
3756
3757 (define_insn "*insv<mode>_z10"
3758   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3759                           (match_operand 1 "const_int_operand"    "I")  ; size
3760                           (match_operand 2 "const_int_operand"    "I")) ; pos
3761         (match_operand:GPR 3 "nonimmediate_operand" "d"))
3762    (clobber (reg:CC CC_REGNUM))]
3763   "TARGET_Z10
3764    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3765   "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3766   [(set_attr "op_type" "RIE")
3767    (set_attr "z10prop" "z10_super_E1")])
3768
3769 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3770 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3771 (define_insn "*insv<mode>_zEC12_noshift"
3772   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3773         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3774                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3775                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3776                           (match_operand:GPR 4 "const_int_operand" ""))))]
3777   "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3778   "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3779   [(set_attr "op_type" "RIE")])
3780
3781 (define_insn "*insv<mode>_z10_noshift"
3782   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3783         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3784                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3785                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3786                           (match_operand:GPR 4 "const_int_operand" ""))))
3787    (clobber (reg:CC CC_REGNUM))]
3788   "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3789   "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3790   [(set_attr "op_type" "RIE")
3791    (set_attr "z10prop" "z10_super_E1")])
3792
3793 ; Implement appending Y on the left of S bits of X
3794 ; x = (y << s) | (x & ((1 << s) - 1))
3795 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3796   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3797         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3798                           (match_operand:GPR 2 "immediate_operand" ""))
3799                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3800                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3801   "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3802   "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3803   [(set_attr "op_type" "RIE")
3804    (set_attr "z10prop" "z10_super_E1")])
3805
3806 (define_insn "*insv<mode>_z10_appendbitsleft"
3807   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3808         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3809                           (match_operand:GPR 2 "immediate_operand" ""))
3810                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3811                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3812    (clobber (reg:CC CC_REGNUM))]
3813   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3814   "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3815   [(set_attr "op_type" "RIE")
3816    (set_attr "z10prop" "z10_super_E1")])
3817
3818 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3819 ;  -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3820 ;  -> z = y >> d; z = risbg;
3821
3822 (define_split
3823   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3824         (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3825                                (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3826                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3827                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3828   "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3829   [(set (match_dup 0)
3830         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3831    (set (match_dup 0)
3832         (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
3833                  (ashift:GPR (match_dup 3) (match_dup 4))))]
3834 {
3835   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3836 })
3837
3838 (define_split
3839   [(parallel
3840     [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3841           (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3842                                  (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3843                    (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3844                                (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3845      (clobber (reg:CC CC_REGNUM))])]
3846   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3847   [(set (match_dup 0)
3848         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3849    (parallel
3850     [(set (match_dup 0)
3851           (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
3852                    (ashift:GPR (match_dup 3) (match_dup 4))))
3853      (clobber (reg:CC CC_REGNUM))])]
3854 {
3855   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3856 })
3857
3858 (define_insn "*r<noxa>sbg_<mode>_noshift"
3859   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3860         (IXOR:GPR
3861           (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3862                    (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3863           (match_operand:GPR 3 "nonimmediate_operand" "0")))
3864    (clobber (reg:CC CC_REGNUM))]
3865   "TARGET_Z10"
3866   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3867   [(set_attr "op_type" "RIE")])
3868
3869 (define_insn "*r<noxa>sbg_di_rotl"
3870   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3871         (IXOR:DI
3872           (and:DI
3873             (rotate:DI
3874               (match_operand:DI 1 "nonimmediate_operand" "d")
3875               (match_operand:DI 3 "const_int_operand" ""))
3876             (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3877           (match_operand:DI 4 "nonimmediate_operand" "0")))
3878    (clobber (reg:CC CC_REGNUM))]
3879   "TARGET_Z10"
3880   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3881   [(set_attr "op_type" "RIE")])
3882
3883 (define_insn "*r<noxa>sbg_<mode>_srl"
3884   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3885         (IXOR:GPR
3886           (and:GPR
3887             (lshiftrt:GPR
3888               (match_operand:GPR 1 "nonimmediate_operand" "d")
3889               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3890             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3891           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3892    (clobber (reg:CC CC_REGNUM))]
3893   "TARGET_Z10
3894    && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3895                            INTVAL (operands[2]))"
3896   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3897   [(set_attr "op_type" "RIE")])
3898
3899 (define_insn "*r<noxa>sbg_<mode>_sll"
3900   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3901         (IXOR:GPR
3902           (and:GPR
3903             (ashift:GPR
3904               (match_operand:GPR 1 "nonimmediate_operand" "d")
3905               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3906             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3907           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3908    (clobber (reg:CC CC_REGNUM))]
3909   "TARGET_Z10
3910    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3911                            INTVAL (operands[2]))"
3912   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3913   [(set_attr "op_type" "RIE")])
3914
3915 ;; These two are generated by combine for s.bf &= val.
3916 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3917 ;; shifts and ands, which results in some truly awful patterns
3918 ;; including subregs of operations.  Rather unnecessisarily, IMO.
3919 ;; Instead of
3920 ;;
3921 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3922 ;;        (const_int 24 [0x18])
3923 ;;        (const_int 0 [0]))
3924 ;;    (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3925 ;;                    (const_int 40 [0x28])) 4)
3926 ;;            (reg:SI 4 %r4 [ y+4 ])) 0))
3927 ;;
3928 ;; we should instead generate
3929 ;;
3930 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3931 ;;        (const_int 24 [0x18])
3932 ;;        (const_int 0 [0]))
3933 ;;    (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3934 ;;                    (const_int 40 [0x28]))
3935 ;;            (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3936 ;;
3937 ;; by noticing that we can push down the outer paradoxical subreg
3938 ;; into the operation.
3939
3940 (define_insn "*insv_rnsbg_noshift"
3941   [(set (zero_extract:DI
3942           (match_operand:DI 0 "nonimmediate_operand" "+d")
3943           (match_operand 1 "const_int_operand" "")
3944           (match_operand 2 "const_int_operand" ""))
3945         (and:DI
3946           (match_dup 0)
3947           (match_operand:DI 3 "nonimmediate_operand" "d")))
3948    (clobber (reg:CC CC_REGNUM))]
3949   "TARGET_Z10
3950    && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3951   "rnsbg\t%0,%3,%2,63,0"
3952   [(set_attr "op_type" "RIE")])
3953
3954 (define_insn "*insv_rnsbg_srl"
3955   [(set (zero_extract:DI
3956           (match_operand:DI 0 "nonimmediate_operand" "+d")
3957           (match_operand 1 "const_int_operand" "")
3958           (match_operand 2 "const_int_operand" ""))
3959         (and:DI
3960           (lshiftrt:DI
3961             (match_dup 0)
3962             (match_operand 3 "const_int_operand" ""))
3963           (match_operand:DI 4 "nonimmediate_operand" "d")))
3964    (clobber (reg:CC CC_REGNUM))]
3965   "TARGET_Z10
3966    && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3967   "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3968   [(set_attr "op_type" "RIE")])
3969
3970 (define_insn "*insv<mode>_mem_reg"
3971   [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3972                         (match_operand 1 "const_int_operand" "n,n")
3973                         (const_int 0))
3974         (match_operand:W 2 "register_operand" "d,d"))]
3975   "INTVAL (operands[1]) > 0
3976    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3977    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3978 {
3979     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3980
3981     operands[1] = GEN_INT ((1ul << size) - 1);
3982     return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3983                                     : "stcmy\t%2,%1,%S0";
3984 }
3985   [(set_attr "op_type" "RS,RSY")
3986    (set_attr "z10prop" "z10_super,z10_super")])
3987
3988 (define_insn "*insvdi_mem_reghigh"
3989   [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3990                          (match_operand 1 "const_int_operand" "n")
3991                          (const_int 0))
3992         (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3993                      (const_int 32)))]
3994   "TARGET_ZARCH
3995    && INTVAL (operands[1]) > 0
3996    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3997    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3998 {
3999     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4000
4001     operands[1] = GEN_INT ((1ul << size) - 1);
4002     return "stcmh\t%2,%1,%S0";
4003 }
4004 [(set_attr "op_type" "RSY")
4005  (set_attr "z10prop" "z10_super")])
4006
4007 (define_insn "*insvdi_reg_imm"
4008   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4009                          (const_int 16)
4010                          (match_operand 1 "const_int_operand" "n"))
4011         (match_operand:DI 2 "const_int_operand" "n"))]
4012   "TARGET_ZARCH
4013    && INTVAL (operands[1]) >= 0
4014    && INTVAL (operands[1]) < BITS_PER_WORD
4015    && INTVAL (operands[1]) % 16 == 0"
4016 {
4017   switch (BITS_PER_WORD - INTVAL (operands[1]))
4018     {
4019       case 64: return "iihh\t%0,%x2"; break;
4020       case 48: return "iihl\t%0,%x2"; break;
4021       case 32: return "iilh\t%0,%x2"; break;
4022       case 16: return "iill\t%0,%x2"; break;
4023       default: gcc_unreachable();
4024     }
4025 }
4026   [(set_attr "op_type" "RI")
4027    (set_attr "z10prop" "z10_super_E1")])
4028
4029 ; Update the left-most 32 bit of a DI.
4030 (define_insn "*insv_h_di_reg_extimm"
4031   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4032                          (const_int 32)
4033                          (const_int 0))
4034         (match_operand:DI 1 "const_int_operand" "n"))]
4035   "TARGET_EXTIMM"
4036   "iihf\t%0,%o1"
4037   [(set_attr "op_type" "RIL")
4038    (set_attr "z10prop" "z10_fwd_E1")])
4039
4040 ; Update the right-most 32 bit of a DI.
4041 (define_insn "*insv_l_di_reg_extimm"
4042   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4043                          (const_int 32)
4044                          (const_int 32))
4045         (match_operand:DI 1 "const_int_operand" "n"))]
4046   "TARGET_EXTIMM"
4047   "iilf\t%0,%o1"
4048   [(set_attr "op_type" "RIL")
4049    (set_attr "z10prop" "z10_fwd_A1")])
4050
4051 ;
4052 ; extendsidi2 instruction pattern(s).
4053 ;
4054
4055 (define_expand "extendsidi2"
4056   [(set (match_operand:DI 0 "register_operand" "")
4057         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4058   ""
4059 {
4060   if (!TARGET_ZARCH)
4061     {
4062       emit_clobber (operands[0]);
4063       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4064       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4065       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4066       DONE;
4067     }
4068 })
4069
4070 (define_insn "*extendsidi2"
4071   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4072         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4073   "TARGET_ZARCH"
4074   "@
4075    lgfr\t%0,%1
4076    lgf\t%0,%1
4077    lgfrl\t%0,%1"
4078   [(set_attr "op_type"      "RRE,RXY,RIL")
4079    (set_attr "type"         "*,*,larl")
4080    (set_attr "cpu_facility" "*,*,z10")
4081    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4082
4083 ;
4084 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4085 ;
4086
4087 (define_expand "extend<HQI:mode><DSI:mode>2"
4088   [(set (match_operand:DSI 0 "register_operand" "")
4089         (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4090   ""
4091 {
4092   if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4093     {
4094       rtx tmp = gen_reg_rtx (SImode);
4095       emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4096       emit_insn (gen_extendsidi2 (operands[0], tmp));
4097       DONE;
4098     }
4099   else if (!TARGET_EXTIMM)
4100     {
4101       rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4102
4103       operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4104       emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4105       emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4106       DONE;
4107     }
4108 })
4109
4110 ;
4111 ; extendhidi2 instruction pattern(s).
4112 ;
4113
4114 (define_insn "*extendhidi2_extimm"
4115   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4116         (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
4117   "TARGET_ZARCH && TARGET_EXTIMM"
4118   "@
4119    lghr\t%0,%1
4120    lgh\t%0,%1
4121    lghrl\t%0,%1"
4122   [(set_attr "op_type"      "RRE,RXY,RIL")
4123    (set_attr "type"         "*,*,larl")
4124    (set_attr "cpu_facility" "extimm,extimm,z10")
4125    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4126
4127 (define_insn "*extendhidi2"
4128   [(set (match_operand:DI 0 "register_operand" "=d")
4129         (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
4130   "TARGET_ZARCH"
4131   "lgh\t%0,%1"
4132   [(set_attr "op_type" "RXY")
4133    (set_attr "z10prop" "z10_super_E1")])
4134
4135 ;
4136 ; extendhisi2 instruction pattern(s).
4137 ;
4138
4139 (define_insn "*extendhisi2_extimm"
4140   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4141         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4142   "TARGET_EXTIMM"
4143   "@
4144    lhr\t%0,%1
4145    lh\t%0,%1
4146    lhy\t%0,%1
4147    lhrl\t%0,%1"
4148   [(set_attr "op_type"      "RRE,RX,RXY,RIL")
4149    (set_attr "type"         "*,*,*,larl")
4150    (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4151    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4152
4153 (define_insn "*extendhisi2"
4154   [(set (match_operand:SI 0 "register_operand" "=d,d")
4155         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4156   "!TARGET_EXTIMM"
4157   "@
4158    lh\t%0,%1
4159    lhy\t%0,%1"
4160   [(set_attr "op_type" "RX,RXY")
4161    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4162
4163 ;
4164 ; extendqi(si|di)2 instruction pattern(s).
4165 ;
4166
4167 ; lbr, lgbr, lb, lgb
4168 (define_insn "*extendqi<mode>2_extimm"
4169   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4170         (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
4171   "TARGET_EXTIMM"
4172   "@
4173    l<g>br\t%0,%1
4174    l<g>b\t%0,%1"
4175   [(set_attr "op_type" "RRE,RXY")
4176    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4177
4178 ; lb, lgb
4179 (define_insn "*extendqi<mode>2"
4180   [(set (match_operand:GPR 0 "register_operand" "=d")
4181         (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
4182   "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4183   "l<g>b\t%0,%1"
4184   [(set_attr "op_type" "RXY")
4185    (set_attr "z10prop" "z10_super_E1")])
4186
4187 (define_insn_and_split "*extendqi<mode>2_short_displ"
4188   [(set (match_operand:GPR 0 "register_operand" "=d")
4189         (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4190    (clobber (reg:CC CC_REGNUM))]
4191   "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4192   "#"
4193   "&& reload_completed"
4194   [(parallel
4195     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4196      (clobber (reg:CC CC_REGNUM))])
4197    (parallel
4198     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4199      (clobber (reg:CC CC_REGNUM))])]
4200 {
4201   operands[1] = adjust_address (operands[1], BLKmode, 0);
4202   set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4203   operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4204 })
4205
4206 ;
4207 ; zero_extendsidi2 instruction pattern(s).
4208 ;
4209
4210 (define_expand "zero_extendsidi2"
4211   [(set (match_operand:DI 0 "register_operand" "")
4212         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4213   ""
4214 {
4215   if (!TARGET_ZARCH)
4216     {
4217       emit_clobber (operands[0]);
4218       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4219       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4220       DONE;
4221     }
4222 })
4223
4224 (define_insn "*zero_extendsidi2"
4225   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4226         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4227   "TARGET_ZARCH"
4228   "@
4229    llgfr\t%0,%1
4230    llgf\t%0,%1
4231    llgfrl\t%0,%1"
4232   [(set_attr "op_type"      "RRE,RXY,RIL")
4233    (set_attr "type"         "*,*,larl")
4234    (set_attr "cpu_facility" "*,*,z10")
4235    (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4236
4237 ;
4238 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4239 ;
4240
4241 (define_insn "*llgt_sidi"
4242   [(set (match_operand:DI 0 "register_operand" "=d")
4243         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4244                 (const_int 2147483647)))]
4245   "TARGET_ZARCH"
4246   "llgt\t%0,%1"
4247   [(set_attr "op_type"  "RXE")
4248    (set_attr "z10prop" "z10_super_E1")])
4249
4250 (define_insn_and_split "*llgt_sidi_split"
4251   [(set (match_operand:DI 0 "register_operand" "=d")
4252         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4253                 (const_int 2147483647)))
4254    (clobber (reg:CC CC_REGNUM))]
4255   "TARGET_ZARCH"
4256   "#"
4257   "&& reload_completed"
4258   [(set (match_dup 0)
4259         (and:DI (subreg:DI (match_dup 1) 0)
4260                 (const_int 2147483647)))]
4261   "")
4262
4263 (define_insn "*llgt_sisi"
4264   [(set (match_operand:SI 0 "register_operand" "=d,d")
4265         (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
4266                 (const_int 2147483647)))]
4267   "TARGET_ZARCH"
4268   "@
4269    llgtr\t%0,%1
4270    llgt\t%0,%1"
4271   [(set_attr "op_type"  "RRE,RXE")
4272    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4273
4274 (define_insn "*llgt_didi"
4275   [(set (match_operand:DI 0 "register_operand" "=d,d")
4276         (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4277                 (const_int 2147483647)))]
4278   "TARGET_ZARCH"
4279   "@
4280    llgtr\t%0,%1
4281    llgt\t%0,%N1"
4282   [(set_attr "op_type"  "RRE,RXE")
4283    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4284
4285 (define_split
4286   [(set (match_operand:DSI 0 "register_operand" "")
4287         (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4288                  (const_int 2147483647)))
4289    (clobber (reg:CC CC_REGNUM))]
4290   "TARGET_ZARCH && reload_completed"
4291   [(set (match_dup 0)
4292         (and:DSI (match_dup 1)
4293                  (const_int 2147483647)))]
4294   "")
4295
4296 ;
4297 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4298 ;
4299
4300 (define_expand "zero_extend<mode>di2"
4301   [(set (match_operand:DI 0 "register_operand" "")
4302         (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4303   ""
4304 {
4305   if (!TARGET_ZARCH)
4306     {
4307       rtx tmp = gen_reg_rtx (SImode);
4308       emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4309       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4310       DONE;
4311     }
4312   else if (!TARGET_EXTIMM)
4313     {
4314       rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4315       operands[1] = gen_lowpart (DImode, operands[1]);
4316       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4317       emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4318       DONE;
4319     }
4320 })
4321
4322 (define_expand "zero_extend<mode>si2"
4323   [(set (match_operand:SI 0 "register_operand" "")
4324         (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4325   ""
4326 {
4327   if (!TARGET_EXTIMM)
4328     {
4329       operands[1] = gen_lowpart (SImode, operands[1]);
4330       emit_insn (gen_andsi3 (operands[0], operands[1],
4331                              GEN_INT ((1 << <HQI:bitsize>) - 1)));
4332       DONE;
4333     }
4334 })
4335
4336 ; llhrl, llghrl
4337 (define_insn "*zero_extendhi<mode>2_z10"
4338   [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4339         (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4340   "TARGET_Z10"
4341   "@
4342    ll<g>hr\t%0,%1
4343    ll<g>h\t%0,%1
4344    ll<g>hrl\t%0,%1"
4345   [(set_attr "op_type"      "RXY,RRE,RIL")
4346    (set_attr "type"         "*,*,larl")
4347    (set_attr "cpu_facility" "*,*,z10")
4348    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4349
4350 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4351 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4352   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4353         (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4354   "TARGET_EXTIMM"
4355   "@
4356    ll<g><hc>r\t%0,%1
4357    ll<g><hc>\t%0,%1"
4358   [(set_attr "op_type" "RRE,RXY")
4359    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4360
4361 ; llgh, llgc
4362 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4363   [(set (match_operand:GPR 0 "register_operand" "=d")
4364         (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4365   "TARGET_ZARCH && !TARGET_EXTIMM"
4366   "llg<hc>\t%0,%1"
4367   [(set_attr "op_type" "RXY")
4368    (set_attr "z10prop" "z10_fwd_A3")])
4369
4370 (define_insn_and_split "*zero_extendhisi2_31"
4371   [(set (match_operand:SI 0 "register_operand" "=&d")
4372         (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4373    (clobber (reg:CC CC_REGNUM))]
4374   "!TARGET_ZARCH"
4375   "#"
4376   "&& reload_completed"
4377   [(set (match_dup 0) (const_int 0))
4378    (parallel
4379     [(set (strict_low_part (match_dup 2)) (match_dup 1))
4380      (clobber (reg:CC CC_REGNUM))])]
4381   "operands[2] = gen_lowpart (HImode, operands[0]);")
4382
4383 (define_insn_and_split "*zero_extendqisi2_31"
4384   [(set (match_operand:SI 0 "register_operand" "=&d")
4385         (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4386   "!TARGET_ZARCH"
4387   "#"
4388   "&& reload_completed"
4389   [(set (match_dup 0) (const_int 0))
4390    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4391   "operands[2] = gen_lowpart (QImode, operands[0]);")
4392
4393 ;
4394 ; zero_extendqihi2 instruction pattern(s).
4395 ;
4396
4397 (define_expand "zero_extendqihi2"
4398   [(set (match_operand:HI 0 "register_operand" "")
4399         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4400   "TARGET_ZARCH && !TARGET_EXTIMM"
4401 {
4402   operands[1] = gen_lowpart (HImode, operands[1]);
4403   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4404   DONE;
4405 })
4406
4407 (define_insn "*zero_extendqihi2_64"
4408   [(set (match_operand:HI 0 "register_operand" "=d")
4409         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4410   "TARGET_ZARCH && !TARGET_EXTIMM"
4411   "llgc\t%0,%1"
4412   [(set_attr "op_type" "RXY")
4413    (set_attr "z10prop" "z10_fwd_A3")])
4414
4415 (define_insn_and_split "*zero_extendqihi2_31"
4416   [(set (match_operand:HI 0 "register_operand" "=&d")
4417         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4418   "!TARGET_ZARCH"
4419   "#"
4420   "&& reload_completed"
4421   [(set (match_dup 0) (const_int 0))
4422    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4423   "operands[2] = gen_lowpart (QImode, operands[0]);")
4424
4425 ;
4426 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4427 ;
4428
4429 (define_expand "fixuns_truncdddi2"
4430   [(parallel
4431     [(set (match_operand:DI 0 "register_operand" "")
4432           (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4433      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4434      (clobber (reg:CC CC_REGNUM))])]
4435
4436   "TARGET_HARD_DFP"
4437 {
4438   if (!TARGET_Z196)
4439     {
4440       rtx_code_label *label1 = gen_label_rtx ();
4441       rtx_code_label *label2 = gen_label_rtx ();
4442       rtx temp = gen_reg_rtx (TDmode);
4443       REAL_VALUE_TYPE cmp, sub;
4444
4445       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4446       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4447
4448       /* 2^63 can't be represented as 64bit DFP number with full precision.  The
4449          solution is doing the check and the subtraction in TD mode and using a
4450          TD -> DI convert afterwards.  */
4451       emit_insn (gen_extendddtd2 (temp, operands[1]));
4452       temp = force_reg (TDmode, temp);
4453       emit_cmp_and_jump_insns (temp,
4454             const_double_from_real_value (cmp, TDmode),
4455             LT, NULL_RTX, VOIDmode, 0, label1);
4456       emit_insn (gen_subtd3 (temp, temp,
4457             const_double_from_real_value (sub, TDmode)));
4458       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4459       emit_jump (label2);
4460
4461       emit_label (label1);
4462       emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4463       emit_label (label2);
4464       DONE;
4465     }
4466 })
4467
4468 (define_expand "fixuns_trunctddi2"
4469   [(parallel
4470     [(set (match_operand:DI 0 "register_operand" "")
4471           (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4472      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4473      (clobber (reg:CC CC_REGNUM))])]
4474
4475   "TARGET_HARD_DFP"
4476 {
4477   if (!TARGET_Z196)
4478     {
4479       rtx_code_label *label1 = gen_label_rtx ();
4480       rtx_code_label *label2 = gen_label_rtx ();
4481       rtx temp = gen_reg_rtx (TDmode);
4482       REAL_VALUE_TYPE cmp, sub;
4483
4484       operands[1] = force_reg (TDmode, operands[1]);
4485       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4486       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4487
4488       emit_cmp_and_jump_insns (operands[1],
4489             const_double_from_real_value (cmp, TDmode),
4490             LT, NULL_RTX, VOIDmode, 0, label1);
4491       emit_insn (gen_subtd3 (temp, operands[1],
4492             const_double_from_real_value (sub, TDmode)));
4493       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4494       emit_jump (label2);
4495
4496       emit_label (label1);
4497       emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4498       emit_label (label2);
4499       DONE;
4500     }
4501 })
4502
4503 ;
4504 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4505 ; instruction pattern(s).
4506 ;
4507
4508 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4509   [(parallel
4510     [(set (match_operand:GPR 0 "register_operand" "")
4511           (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4512      (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4513      (clobber (reg:CC CC_REGNUM))])]
4514   "TARGET_HARD_FLOAT"
4515 {
4516   if (!TARGET_Z196)
4517     {
4518       rtx_code_label *label1 = gen_label_rtx ();
4519       rtx_code_label *label2 = gen_label_rtx ();
4520       rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4521       REAL_VALUE_TYPE cmp, sub;
4522
4523       operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4524       real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4525       real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4526
4527       emit_cmp_and_jump_insns (operands[1],
4528             const_double_from_real_value (cmp, <BFP:MODE>mode),
4529             LT, NULL_RTX, VOIDmode, 0, label1);
4530       emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4531             const_double_from_real_value (sub, <BFP:MODE>mode)));
4532       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4533             GEN_INT (7)));
4534       emit_jump (label2);
4535
4536       emit_label (label1);
4537       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4538             operands[1], GEN_INT (5)));
4539       emit_label (label2);
4540       DONE;
4541     }
4542 })
4543
4544 ; fixuns_trunc(td|dd)si2 expander
4545 (define_expand "fixuns_trunc<mode>si2"
4546   [(parallel
4547     [(set (match_operand:SI 0 "register_operand" "")
4548           (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4549      (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4550      (clobber (reg:CC CC_REGNUM))])]
4551   "TARGET_Z196 && TARGET_HARD_DFP"
4552   "")
4553
4554 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4555
4556 (define_insn "*fixuns_truncdfdi2_z13"
4557   [(set (match_operand:DI                  0 "register_operand" "=d,v")
4558         (unsigned_fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4559    (unspec:DI [(match_operand:DI           2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4560    (clobber (reg:CC CC_REGNUM))]
4561    "TARGET_Z13 && TARGET_HARD_FLOAT"
4562    "@
4563     clgdbr\t%0,%h2,%1,0
4564     wclgdb\t%v0,%v1,0,%h2"
4565    [(set_attr "op_type" "RRF,VRR")
4566     (set_attr "type"    "ftoi")])
4567
4568 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4569 ;         clfdtr, clfxtr,         clgdtr, clgxtr
4570 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4571   [(set (match_operand:GPR                  0 "register_operand" "=d")
4572         (unsigned_fix:GPR (match_operand:FP 1 "register_operand"  "f")))
4573    (unspec:GPR [(match_operand:GPR          2 "immediate_operand" "K")] UNSPEC_ROUND)
4574    (clobber (reg:CC CC_REGNUM))]
4575    "TARGET_Z196 && TARGET_HARD_FLOAT
4576     && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4577    "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4578    [(set_attr "op_type" "RRF")
4579     (set_attr "type"    "ftoi")])
4580
4581 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4582   [(set (match_operand:GPR 0 "register_operand" "")
4583         (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4584   "TARGET_HARD_FLOAT"
4585 {
4586   emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4587              GEN_INT (5)));
4588   DONE;
4589 })
4590
4591 (define_insn "*fix_truncdfdi2_bfp_z13"
4592   [(set (match_operand:DI         0 "register_operand" "=d,v")
4593         (fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4594    (unspec:DI [(match_operand:DI  2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4595    (clobber (reg:CC CC_REGNUM))]
4596   "TARGET_Z13 && TARGET_HARD_FLOAT"
4597   "@
4598    cgdbr\t%0,%h2,%1
4599    wcgdb\t%v0,%v1,0,%h2"
4600   [(set_attr "op_type" "RRE,VRR")
4601    (set_attr "type"    "ftoi")])
4602
4603 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4604 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4605   [(set (match_operand:GPR          0 "register_operand" "=d")
4606         (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4607    (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4608    (clobber (reg:CC CC_REGNUM))]
4609   "TARGET_HARD_FLOAT
4610     && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4611   "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4612   [(set_attr "op_type" "RRE")
4613    (set_attr "type"    "ftoi")])
4614
4615 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4616   [(parallel
4617     [(set (match_operand:GPR          0 "register_operand" "=d")
4618           (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4619      (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4620      (clobber (reg:CC CC_REGNUM))])]
4621   "TARGET_HARD_FLOAT")
4622 ;
4623 ; fix_trunc(td|dd)di2 instruction pattern(s).
4624 ;
4625
4626 (define_expand "fix_trunc<mode>di2"
4627   [(set (match_operand:DI 0 "register_operand" "")
4628         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4629   "TARGET_ZARCH && TARGET_HARD_DFP"
4630 {
4631   operands[1] = force_reg (<MODE>mode, operands[1]);
4632   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4633       GEN_INT (9)));
4634   DONE;
4635 })
4636
4637 ; cgxtr, cgdtr
4638 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4639   [(set (match_operand:DI 0 "register_operand" "=d")
4640         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4641    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4642    (clobber (reg:CC CC_REGNUM))]
4643   "TARGET_ZARCH && TARGET_HARD_DFP"
4644   "cg<DFP:xde>tr\t%0,%h2,%1"
4645   [(set_attr "op_type" "RRF")
4646    (set_attr "type"    "ftoidfp")])
4647
4648
4649 ;
4650 ; fix_trunctf(si|di)2 instruction pattern(s).
4651 ;
4652
4653 (define_expand "fix_trunctf<mode>2"
4654   [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4655                    (fix:GPR (match_operand:TF 1 "register_operand" "")))
4656               (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4657               (clobber (reg:CC CC_REGNUM))])]
4658   "TARGET_HARD_FLOAT"
4659   "")
4660
4661
4662 ;
4663 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4664 ;
4665
4666 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4667 (define_insn "floatdi<mode>2"
4668   [(set (match_operand:FP           0 "register_operand" "=f,<vf>")
4669         (float:FP (match_operand:DI 1 "register_operand"  "d,<vd>")))]
4670   "TARGET_ZARCH && TARGET_HARD_FLOAT"
4671   "@
4672    c<xde>g<bt>r\t%0,%1
4673    wcdgb\t%v0,%v1,0,0"
4674   [(set_attr "op_type"      "RRE,VRR")
4675    (set_attr "type"         "itof<mode>" )
4676    (set_attr "cpu_facility" "*,vec")])
4677
4678 ; cxfbr, cdfbr, cefbr
4679 (define_insn "floatsi<mode>2"
4680   [(set (match_operand:BFP 0 "register_operand" "=f")
4681         (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4682   "TARGET_HARD_FLOAT"
4683   "c<xde>fbr\t%0,%1"
4684   [(set_attr "op_type" "RRE")
4685    (set_attr "type"   "itof<mode>" )])
4686
4687 ; cxftr, cdftr
4688 (define_insn "floatsi<mode>2"
4689   [(set (match_operand:DFP 0 "register_operand" "=f")
4690         (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4691   "TARGET_Z196 && TARGET_HARD_FLOAT"
4692   "c<xde>ftr\t%0,0,%1,0"
4693   [(set_attr "op_type" "RRE")
4694    (set_attr "type"   "itof<mode>" )])
4695
4696 ;
4697 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4698 ;
4699
4700 (define_insn "*floatunsdidf2_z13"
4701   [(set (match_operand:DF                    0 "register_operand" "=f,v")
4702         (unsigned_float:DF (match_operand:DI 1 "register_operand"  "d,v")))]
4703   "TARGET_Z13 && TARGET_HARD_FLOAT"
4704   "@
4705    cdlgbr\t%0,0,%1,0
4706    wcdlgb\t%v0,%v1,0,0"
4707   [(set_attr "op_type" "RRE,VRR")
4708    (set_attr "type"    "itofdf")])
4709
4710 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4711 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4712 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4713   [(set (match_operand:FP                     0 "register_operand" "=f")
4714         (unsigned_float:FP (match_operand:GPR 1 "register_operand"  "d")))]
4715   "TARGET_Z196 && TARGET_HARD_FLOAT
4716    && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4717   "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4718   [(set_attr "op_type" "RRE")
4719    (set_attr "type"    "itof<FP:mode>")])
4720
4721 (define_expand "floatuns<GPR:mode><FP:mode>2"
4722   [(set (match_operand:FP                     0 "register_operand" "")
4723         (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4724   "TARGET_Z196 && TARGET_HARD_FLOAT")
4725
4726 ;
4727 ; truncdfsf2 instruction pattern(s).
4728 ;
4729
4730 (define_insn "truncdfsf2"
4731   [(set (match_operand:SF                    0 "register_operand" "=f,v")
4732         (float_truncate:SF (match_operand:DF 1 "register_operand"  "f,v")))]
4733   "TARGET_HARD_FLOAT"
4734   "@
4735    ledbr\t%0,%1
4736    wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4737                        ; According to BFP rounding mode
4738   [(set_attr "op_type"      "RRE,VRR")
4739    (set_attr "type"         "ftruncdf")
4740    (set_attr "cpu_facility" "*,vec")])
4741
4742 ;
4743 ; trunctf(df|sf)2 instruction pattern(s).
4744 ;
4745
4746 ; ldxbr, lexbr
4747 (define_insn "trunctf<mode>2"
4748   [(set (match_operand:DSF 0 "register_operand" "=f")
4749         (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4750    (clobber (match_scratch:TF 2 "=f"))]
4751   "TARGET_HARD_FLOAT"
4752   "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4753   [(set_attr "length" "6")
4754    (set_attr "type"   "ftrunctf")])
4755
4756 ;
4757 ; trunctddd2 and truncddsd2 instruction pattern(s).
4758 ;
4759
4760 (define_insn "trunctddd2"
4761   [(set (match_operand:DD 0 "register_operand" "=f")
4762         (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4763    (clobber (match_scratch:TD 2 "=f"))]
4764   "TARGET_HARD_DFP"
4765   "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4766   [(set_attr "length"  "6")
4767    (set_attr "type"    "ftruncdd")])
4768
4769 (define_insn "truncddsd2"
4770   [(set (match_operand:SD 0 "register_operand" "=f")
4771         (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4772   "TARGET_HARD_DFP"
4773   "ledtr\t%0,0,%1,0"
4774   [(set_attr "op_type" "RRF")
4775    (set_attr "type"    "ftruncsd")])
4776
4777 (define_expand "trunctdsd2"
4778   [(parallel
4779     [(set (match_dup 3)
4780           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4781      (clobber (match_scratch:TD 2 ""))])
4782    (set (match_operand:SD 0 "register_operand" "")
4783         (float_truncate:SD (match_dup 3)))]
4784   "TARGET_HARD_DFP"
4785 {
4786   operands[3] = gen_reg_rtx (DDmode);
4787 })
4788
4789 ;
4790 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4791 ;
4792
4793 (define_insn "*extendsfdf2_z13"
4794   [(set (match_operand:DF                  0 "register_operand"     "=f,f,v")
4795         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R,v")))]
4796   "TARGET_Z13 && TARGET_HARD_FLOAT"
4797   "@
4798    ldebr\t%0,%1
4799    ldeb\t%0,%1
4800    wldeb\t%v0,%v1"
4801   [(set_attr "op_type" "RRE,RXE,VRR")
4802    (set_attr "type"    "fsimpdf, floaddf,fsimpdf")])
4803
4804 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4805 (define_insn "*extend<DSF:mode><BFP:mode>2"
4806   [(set (match_operand:BFP                   0 "register_operand"     "=f,f")
4807         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand"  "f,R")))]
4808   "TARGET_HARD_FLOAT
4809    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4810    && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4811   "@
4812    l<BFP:xde><DSF:xde>br\t%0,%1
4813    l<BFP:xde><DSF:xde>b\t%0,%1"
4814   [(set_attr "op_type" "RRE,RXE")
4815    (set_attr "type"    "fsimp<BFP:mode>, fload<BFP:mode>")])
4816
4817 (define_expand "extend<DSF:mode><BFP:mode>2"
4818   [(set (match_operand:BFP                   0 "register_operand"     "")
4819         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4820   "TARGET_HARD_FLOAT
4821    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4822
4823 ;
4824 ; extendddtd2 and extendsddd2 instruction pattern(s).
4825 ;
4826
4827 (define_insn "extendddtd2"
4828   [(set (match_operand:TD 0 "register_operand" "=f")
4829         (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4830   "TARGET_HARD_DFP"
4831   "lxdtr\t%0,%1,0"
4832   [(set_attr "op_type" "RRF")
4833    (set_attr "type"    "fsimptf")])
4834
4835 (define_insn "extendsddd2"
4836   [(set (match_operand:DD 0 "register_operand" "=f")
4837         (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4838   "TARGET_HARD_DFP"
4839   "ldetr\t%0,%1,0"
4840   [(set_attr "op_type" "RRF")
4841    (set_attr "type"    "fsimptf")])
4842
4843 (define_expand "extendsdtd2"
4844   [(set (match_dup 2)
4845         (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4846    (set (match_operand:TD 0 "register_operand" "")
4847         (float_extend:TD (match_dup 2)))]
4848   "TARGET_HARD_DFP"
4849 {
4850   operands[2] = gen_reg_rtx (DDmode);
4851 })
4852
4853 ; Binary Floating Point - load fp integer
4854
4855 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4856 ; For all of them the inexact exceptions are suppressed.
4857
4858 ; fiebra, fidbra, fixbra
4859 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4860   [(set (match_operand:BFP 0 "register_operand" "=f")
4861         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4862                     FPINT))]
4863   "TARGET_Z196"
4864   "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4865   [(set_attr "op_type"   "RRF")
4866    (set_attr "type"      "fsimp<BFP:mode>")])
4867
4868 ; rint is supposed to raise an inexact exception so we can use the
4869 ; older instructions.
4870
4871 ; fiebr, fidbr, fixbr
4872 (define_insn "rint<BFP:mode>2"
4873   [(set (match_operand:BFP 0 "register_operand" "=f")
4874         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4875                     UNSPEC_FPINT_RINT))]
4876   ""
4877   "fi<BFP:xde>br\t%0,0,%1"
4878   [(set_attr "op_type"   "RRF")
4879    (set_attr "type"      "fsimp<BFP:mode>")])
4880
4881
4882 ; Decimal Floating Point - load fp integer
4883
4884 ; fidtr, fixtr
4885 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4886   [(set (match_operand:DFP 0 "register_operand" "=f")
4887         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4888                     FPINT))]
4889   "TARGET_HARD_DFP"
4890   "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4891   [(set_attr "op_type"   "RRF")
4892    (set_attr "type"      "fsimp<DFP:mode>")])
4893
4894 ; fidtr, fixtr
4895 (define_insn "rint<DFP:mode>2"
4896   [(set (match_operand:DFP 0 "register_operand" "=f")
4897         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4898                     UNSPEC_FPINT_RINT))]
4899   "TARGET_HARD_DFP"
4900   "fi<DFP:xde>tr\t%0,0,%1,0"
4901   [(set_attr "op_type"   "RRF")
4902    (set_attr "type"      "fsimp<DFP:mode>")])
4903
4904 ;
4905 ; Binary <-> Decimal floating point trunc patterns
4906 ;
4907
4908 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4909   [(set (reg:DFP_ALL FPR0_REGNUM)
4910         (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4911    (use (reg:SI GPR0_REGNUM))
4912    (clobber (reg:CC CC_REGNUM))
4913    (clobber (reg:SI GPR1_REGNUM))]
4914   "TARGET_HARD_DFP"
4915   "pfpo")
4916
4917 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4918   [(set (reg:BFP FPR0_REGNUM)
4919         (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4920    (use (reg:SI GPR0_REGNUM))
4921    (clobber (reg:CC CC_REGNUM))
4922    (clobber (reg:SI GPR1_REGNUM))]
4923   "TARGET_HARD_DFP"
4924   "pfpo")
4925
4926 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4927   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4928    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4929    (parallel
4930     [(set (reg:DFP_ALL FPR0_REGNUM)
4931           (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4932      (use (reg:SI GPR0_REGNUM))
4933      (clobber (reg:CC CC_REGNUM))
4934      (clobber (reg:SI GPR1_REGNUM))])
4935    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4936         (reg:DFP_ALL FPR0_REGNUM))]
4937   "TARGET_HARD_DFP
4938    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4939 {
4940   HOST_WIDE_INT flags;
4941
4942   flags = (PFPO_CONVERT |
4943            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4944            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4945
4946   operands[2] = GEN_INT (flags);
4947 })
4948
4949 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4950   [(set (reg:DFP_ALL FPR4_REGNUM)
4951         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4952    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4953    (parallel
4954     [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4955      (use (reg:SI GPR0_REGNUM))
4956      (clobber (reg:CC CC_REGNUM))
4957      (clobber (reg:SI GPR1_REGNUM))])
4958    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4959   "TARGET_HARD_DFP
4960    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4961 {
4962   HOST_WIDE_INT flags;
4963
4964   flags = (PFPO_CONVERT |
4965            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4966            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4967
4968   operands[2] = GEN_INT (flags);
4969 })
4970
4971 ;
4972 ; Binary <-> Decimal floating point extend patterns
4973 ;
4974
4975 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4976   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4977    (use (reg:SI GPR0_REGNUM))
4978    (clobber (reg:CC CC_REGNUM))
4979    (clobber (reg:SI GPR1_REGNUM))]
4980   "TARGET_HARD_DFP"
4981   "pfpo")
4982
4983 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4984   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4985    (use (reg:SI GPR0_REGNUM))
4986    (clobber (reg:CC CC_REGNUM))
4987    (clobber (reg:SI GPR1_REGNUM))]
4988   "TARGET_HARD_DFP"
4989   "pfpo")
4990
4991 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4992   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4993    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4994    (parallel
4995     [(set (reg:DFP_ALL FPR0_REGNUM)
4996           (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4997      (use (reg:SI GPR0_REGNUM))
4998      (clobber (reg:CC CC_REGNUM))
4999      (clobber (reg:SI GPR1_REGNUM))])
5000    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5001         (reg:DFP_ALL FPR0_REGNUM))]
5002   "TARGET_HARD_DFP
5003    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5004 {
5005   HOST_WIDE_INT flags;
5006
5007   flags = (PFPO_CONVERT |
5008            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5009            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5010
5011   operands[2] = GEN_INT (flags);
5012 })
5013
5014 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5015   [(set (reg:DFP_ALL FPR4_REGNUM)
5016         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5017    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5018    (parallel
5019     [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5020      (use (reg:SI GPR0_REGNUM))
5021      (clobber (reg:CC CC_REGNUM))
5022      (clobber (reg:SI GPR1_REGNUM))])
5023    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5024   "TARGET_HARD_DFP
5025    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5026 {
5027   HOST_WIDE_INT flags;
5028
5029   flags = (PFPO_CONVERT |
5030            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5031            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5032
5033   operands[2] = GEN_INT (flags);
5034 })
5035
5036
5037 ;;
5038 ;; ARITHMETIC OPERATIONS
5039 ;;
5040 ;  arithmetic operations set the ConditionCode,
5041 ;  because of unpredictable Bits in Register for Halfword and Byte
5042 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
5043
5044 ;;
5045 ;;- Add instructions.
5046 ;;
5047
5048 ;
5049 ; addti3 instruction pattern(s).
5050 ;
5051
5052 (define_expand "addti3"
5053   [(parallel
5054     [(set (match_operand:TI          0 "register_operand"     "")
5055           (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5056                    (match_operand:TI 2 "general_operand"      "") ) )
5057      (clobber (reg:CC CC_REGNUM))])]
5058   "TARGET_ZARCH"
5059 {
5060   /* For z13 we have vaq which doesn't set CC.  */
5061   if (TARGET_VX)
5062     {
5063       emit_insn (gen_rtx_SET (operands[0],
5064                               gen_rtx_PLUS (TImode,
5065                                             copy_to_mode_reg (TImode, operands[1]),
5066                                             copy_to_mode_reg (TImode, operands[2]))));
5067       DONE;
5068     }
5069 })
5070
5071 (define_insn_and_split "*addti3"
5072   [(set (match_operand:TI          0 "register_operand"    "=&d")
5073         (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5074                  (match_operand:TI 2 "general_operand"      "do") ) )
5075    (clobber (reg:CC CC_REGNUM))]
5076   "TARGET_ZARCH"
5077   "#"
5078   "&& reload_completed"
5079   [(parallel
5080     [(set (reg:CCL1 CC_REGNUM)
5081           (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5082                         (match_dup 7)))
5083      (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5084    (parallel
5085     [(set (match_dup 3) (plus:DI
5086                           (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5087                                    (match_dup 4)) (match_dup 5)))
5088      (clobber (reg:CC CC_REGNUM))])]
5089   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5090    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5091    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5092    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5093    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5094    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5095   [(set_attr "op_type"  "*")
5096    (set_attr "cpu_facility" "*")])
5097
5098 ;
5099 ; adddi3 instruction pattern(s).
5100 ;
5101
5102 (define_expand "adddi3"
5103   [(parallel
5104     [(set (match_operand:DI 0 "nonimmediate_operand" "")
5105           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5106                    (match_operand:DI 2 "general_operand" "")))
5107      (clobber (reg:CC CC_REGNUM))])]
5108   ""
5109   "")
5110
5111 (define_insn "*adddi3_sign"
5112   [(set (match_operand:DI 0 "register_operand" "=d,d")
5113         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5114                  (match_operand:DI 1 "register_operand" "0,0")))
5115    (clobber (reg:CC CC_REGNUM))]
5116   "TARGET_ZARCH"
5117   "@
5118    agfr\t%0,%2
5119    agf\t%0,%2"
5120   [(set_attr "op_type"  "RRE,RXY")
5121    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5122
5123 (define_insn "*adddi3_zero_cc"
5124   [(set (reg CC_REGNUM)
5125         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5126                           (match_operand:DI 1 "register_operand" "0,0"))
5127                  (const_int 0)))
5128    (set (match_operand:DI 0 "register_operand" "=d,d")
5129         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5130   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5131   "@
5132    algfr\t%0,%2
5133    algf\t%0,%2"
5134   [(set_attr "op_type"  "RRE,RXY")
5135    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5136
5137 (define_insn "*adddi3_zero_cconly"
5138   [(set (reg CC_REGNUM)
5139         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5140                           (match_operand:DI 1 "register_operand" "0,0"))
5141                  (const_int 0)))
5142    (clobber (match_scratch:DI 0 "=d,d"))]
5143   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5144   "@
5145    algfr\t%0,%2
5146    algf\t%0,%2"
5147   [(set_attr "op_type"  "RRE,RXY")
5148    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5149
5150 (define_insn "*adddi3_zero"
5151   [(set (match_operand:DI 0 "register_operand" "=d,d")
5152         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5153                  (match_operand:DI 1 "register_operand" "0,0")))
5154    (clobber (reg:CC CC_REGNUM))]
5155   "TARGET_ZARCH"
5156   "@
5157    algfr\t%0,%2
5158    algf\t%0,%2"
5159   [(set_attr "op_type"  "RRE,RXY")
5160    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5161
5162 (define_insn_and_split "*adddi3_31z"
5163   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5164         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5165                  (match_operand:DI 2 "general_operand" "do") ) )
5166    (clobber (reg:CC CC_REGNUM))]
5167   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5168   "#"
5169   "&& reload_completed"
5170   [(parallel
5171     [(set (reg:CCL1 CC_REGNUM)
5172           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5173                         (match_dup 7)))
5174      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5175    (parallel
5176     [(set (match_dup 3) (plus:SI
5177                           (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5178                                    (match_dup 4)) (match_dup 5)))
5179      (clobber (reg:CC CC_REGNUM))])]
5180   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5181    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5182    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5183    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5184    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5185    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5186
5187 (define_insn_and_split "*adddi3_31"
5188   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5189         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5190                  (match_operand:DI 2 "general_operand" "do") ) )
5191    (clobber (reg:CC CC_REGNUM))]
5192   "!TARGET_CPU_ZARCH"
5193   "#"
5194   "&& reload_completed"
5195   [(parallel
5196     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5197      (clobber (reg:CC CC_REGNUM))])
5198    (parallel
5199     [(set (reg:CCL1 CC_REGNUM)
5200           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5201                         (match_dup 7)))
5202      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5203    (set (pc)
5204         (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5205                       (pc)
5206                       (label_ref (match_dup 9))))
5207    (parallel
5208     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5209      (clobber (reg:CC CC_REGNUM))])
5210    (match_dup 9)]
5211   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5212    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5213    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5214    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5215    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5216    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5217    operands[9] = gen_label_rtx ();")
5218
5219 ;
5220 ; addsi3 instruction pattern(s).
5221 ;
5222
5223 (define_expand "addsi3"
5224   [(parallel
5225     [(set (match_operand:SI 0 "nonimmediate_operand" "")
5226           (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5227                    (match_operand:SI 2 "general_operand" "")))
5228      (clobber (reg:CC CC_REGNUM))])]
5229   ""
5230   "")
5231
5232 (define_insn "*addsi3_sign"
5233   [(set (match_operand:SI 0 "register_operand" "=d,d")
5234         (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5235                  (match_operand:SI 1 "register_operand" "0,0")))
5236    (clobber (reg:CC CC_REGNUM))]
5237   ""
5238   "@
5239    ah\t%0,%2
5240    ahy\t%0,%2"
5241   [(set_attr "op_type"  "RX,RXY")
5242    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5243
5244 ;
5245 ; add(di|si)3 instruction pattern(s).
5246 ;
5247
5248 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5249 (define_insn "*add<mode>3"
5250   [(set (match_operand:GPR 0 "nonimmediate_operand"           "=d,d,d,d, d, d,d,d,QS")
5251         (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
5252                   (match_operand:GPR 2 "general_operand"      " d,d,K,K,Op,On,R,T, C") ) )
5253    (clobber (reg:CC CC_REGNUM))]
5254   ""
5255   "@
5256    a<g>r\t%0,%2
5257    a<g>rk\t%0,%1,%2
5258    a<g>hi\t%0,%h2
5259    a<g>hik\t%0,%1,%h2
5260    al<g>fi\t%0,%2
5261    sl<g>fi\t%0,%n2
5262    a<g>\t%0,%2
5263    a<y>\t%0,%2
5264    a<g>si\t%0,%c2"
5265   [(set_attr "op_type"  "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5266    (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
5267    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5268                         z10_super_E1,z10_super_E1,z10_super_E1")])
5269
5270 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5271 (define_insn "*add<mode>3_carry1_cc"
5272   [(set (reg CC_REGNUM)
5273         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5274                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5275                  (match_dup 1)))
5276    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,d")
5277         (plus:GPR (match_dup 1) (match_dup 2)))]
5278   "s390_match_ccmode (insn, CCL1mode)"
5279   "@
5280    al<g>r\t%0,%2
5281    al<g>rk\t%0,%1,%2
5282    al<g>fi\t%0,%2
5283    sl<g>fi\t%0,%n2
5284    al<g>hsik\t%0,%1,%h2
5285    al<g>\t%0,%2
5286    al<y>\t%0,%2
5287    al<g>si\t%0,%c2"
5288   [(set_attr "op_type"      "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5289    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5290    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5291                         z10_super_E1,z10_super_E1,z10_super_E1")])
5292
5293 ; alr, al, aly, algr, alg, alrk, algrk
5294 (define_insn "*add<mode>3_carry1_cconly"
5295   [(set (reg CC_REGNUM)
5296         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5297                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5298                  (match_dup 1)))
5299    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5300   "s390_match_ccmode (insn, CCL1mode)"
5301   "@
5302    al<g>r\t%0,%2
5303    al<g>rk\t%0,%1,%2
5304    al<g>\t%0,%2
5305    al<y>\t%0,%2"
5306   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5307    (set_attr "cpu_facility" "*,z196,*,*")
5308    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5309
5310 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5311 (define_insn "*add<mode>3_carry2_cc"
5312   [(set (reg CC_REGNUM)
5313         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5314                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5315                  (match_dup 2)))
5316    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5317         (plus:GPR (match_dup 1) (match_dup 2)))]
5318   "s390_match_ccmode (insn, CCL1mode)"
5319   "@
5320    al<g>r\t%0,%2
5321    al<g>rk\t%0,%1,%2
5322    al<g>fi\t%0,%2
5323    sl<g>fi\t%0,%n2
5324    al<g>hsik\t%0,%1,%h2
5325    al<g>\t%0,%2
5326    al<y>\t%0,%2
5327    al<g>si\t%0,%c2"
5328   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5329    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5330    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5331                         z10_super_E1,z10_super_E1,z10_super_E1")])
5332
5333 ; alr, al, aly, algr, alg, alrk, algrk
5334 (define_insn "*add<mode>3_carry2_cconly"
5335   [(set (reg CC_REGNUM)
5336         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5337                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5338                  (match_dup 2)))
5339    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5340   "s390_match_ccmode (insn, CCL1mode)"
5341   "@
5342    al<g>r\t%0,%2
5343    al<g>rk\t%0,%1,%2
5344    al<g>\t%0,%2
5345    al<y>\t%0,%2"
5346   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5347    (set_attr "cpu_facility" "*,z196,*,*")
5348    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5349
5350 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5351 (define_insn "*add<mode>3_cc"
5352   [(set (reg CC_REGNUM)
5353         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5354                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5355                  (const_int 0)))
5356    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5357         (plus:GPR (match_dup 1) (match_dup 2)))]
5358   "s390_match_ccmode (insn, CCLmode)"
5359   "@
5360    al<g>r\t%0,%2
5361    al<g>rk\t%0,%1,%2
5362    al<g>fi\t%0,%2
5363    sl<g>fi\t%0,%n2
5364    al<g>hsik\t%0,%1,%h2
5365    al<g>\t%0,%2
5366    al<y>\t%0,%2
5367    al<g>si\t%0,%c2"
5368   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5369    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5370    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5371                         *,z10_super_E1,z10_super_E1,z10_super_E1")])
5372
5373 ; alr, al, aly, algr, alg, alrk, algrk
5374 (define_insn "*add<mode>3_cconly"
5375   [(set (reg CC_REGNUM)
5376         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5377                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5378                  (const_int 0)))
5379    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5380   "s390_match_ccmode (insn, CCLmode)"
5381   "@
5382    al<g>r\t%0,%2
5383    al<g>rk\t%0,%1,%2
5384    al<g>\t%0,%2
5385    al<y>\t%0,%2"
5386   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5387    (set_attr "cpu_facility" "*,z196,*,*")
5388    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5389
5390 ; alr, al, aly, algr, alg, alrk, algrk
5391 (define_insn "*add<mode>3_cconly2"
5392   [(set (reg CC_REGNUM)
5393         (compare (match_operand:GPR 1 "nonimmediate_operand"    "%0,d,0,0")
5394                  (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5395    (clobber (match_scratch:GPR 0                                "=d,d,d,d"))]
5396   "s390_match_ccmode(insn, CCLmode)"
5397   "@
5398    al<g>r\t%0,%2
5399    al<g>rk\t%0,%1,%2
5400    al<g>\t%0,%2
5401    al<y>\t%0,%2"
5402   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5403    (set_attr "cpu_facility" "*,z196,*,*")
5404    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5405
5406 ; ahi, afi, aghi, agfi, asi, agsi
5407 (define_insn "*add<mode>3_imm_cc"
5408   [(set (reg CC_REGNUM)
5409         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5410                            (match_operand:GPR 2 "const_int_operand"    " K, K,Os, C"))
5411                  (const_int 0)))
5412    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d, d,d,QS")
5413         (plus:GPR (match_dup 1) (match_dup 2)))]
5414   "s390_match_ccmode (insn, CCAmode)
5415    && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5416        || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5417            /* Avoid INT32_MIN on 32 bit.  */
5418            && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5419   "@
5420    a<g>hi\t%0,%h2
5421    a<g>hik\t%0,%1,%h2
5422    a<g>fi\t%0,%2
5423    a<g>si\t%0,%c2"
5424   [(set_attr "op_type"      "RI,RIE,RIL,SIY")
5425    (set_attr "cpu_facility" "*,z196,extimm,z10")
5426    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5427
5428 ;
5429 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5430 ;
5431
5432 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5433 ; FIXME: wfadb does not clobber cc
5434 (define_insn "add<mode>3"
5435   [(set (match_operand:FP 0 "register_operand"                 "=f,   f,<vf>")
5436         (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
5437                  (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))
5438    (clobber (reg:CC CC_REGNUM))]
5439   "TARGET_HARD_FLOAT"
5440   "@
5441    a<xde><bt>r\t%0,<op1>%2
5442    a<xde>b\t%0,%2
5443    wfadb\t%v0,%v1,%v2"
5444   [(set_attr "op_type"      "<RRer>,RXE,VRR")
5445    (set_attr "type"         "fsimp<mode>")
5446    (set_attr "cpu_facility" "*,*,vec")])
5447
5448 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5449 (define_insn "*add<mode>3_cc"
5450   [(set (reg CC_REGNUM)
5451         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5452                           (match_operand:FP 2 "general_operand"      " f,<Rf>"))
5453                  (match_operand:FP 3 "const0_operand" "")))
5454    (set (match_operand:FP 0 "register_operand" "=f,f")
5455         (plus:FP (match_dup 1) (match_dup 2)))]
5456   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5457   "@
5458    a<xde><bt>r\t%0,<op1>%2
5459    a<xde>b\t%0,%2"
5460   [(set_attr "op_type"  "<RRer>,RXE")
5461    (set_attr "type"     "fsimp<mode>")])
5462
5463 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5464 (define_insn "*add<mode>3_cconly"
5465   [(set (reg CC_REGNUM)
5466         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5467                            (match_operand:FP 2 "general_operand"      " f,<Rf>"))
5468                  (match_operand:FP 3 "const0_operand" "")))
5469    (clobber (match_scratch:FP 0 "=f,f"))]
5470   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5471   "@
5472    a<xde><bt>r\t%0,<op1>%2
5473    a<xde>b\t%0,%2"
5474   [(set_attr "op_type"  "<RRer>,RXE")
5475    (set_attr "type"     "fsimp<mode>")])
5476
5477 ;
5478 ; Pointer add instruction patterns
5479 ;
5480
5481 ; This will match "*la_64"
5482 (define_expand "addptrdi3"
5483   [(set (match_operand:DI 0 "register_operand" "")
5484         (plus:DI (match_operand:DI 1 "register_operand" "")
5485                  (match_operand:DI 2 "nonmemory_operand" "")))]
5486   "TARGET_64BIT"
5487 {
5488   if (GET_CODE (operands[2]) == CONST_INT)
5489     {
5490       HOST_WIDE_INT c = INTVAL (operands[2]);
5491
5492       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5493           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5494         {
5495           operands[2] = force_const_mem (DImode, operands[2]);
5496           operands[2] = force_reg (DImode, operands[2]);
5497         }
5498       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5499         operands[2] = force_reg (DImode, operands[2]);
5500     }
5501 })
5502
5503 ; For 31 bit we have to prevent the generated pattern from matching
5504 ; normal ADDs since la only does a 31 bit add.  This is supposed to
5505 ; match "force_la_31".
5506 (define_expand "addptrsi3"
5507   [(parallel
5508     [(set (match_operand:SI 0 "register_operand" "")
5509           (plus:SI (match_operand:SI 1 "register_operand" "")
5510                    (match_operand:SI 2 "nonmemory_operand" "")))
5511                    (use (const_int 0))])]
5512   "!TARGET_64BIT"
5513 {
5514   if (GET_CODE (operands[2]) == CONST_INT)
5515     {
5516       HOST_WIDE_INT c = INTVAL (operands[2]);
5517
5518       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5519           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5520         {
5521           operands[2] = force_const_mem (SImode, operands[2]);
5522           operands[2] = force_reg (SImode, operands[2]);
5523         }
5524       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5525         operands[2] = force_reg (SImode, operands[2]);
5526     }
5527 })
5528
5529 ;;
5530 ;;- Subtract instructions.
5531 ;;
5532
5533 ;
5534 ; subti3 instruction pattern(s).
5535 ;
5536
5537 (define_expand "subti3"
5538   [(parallel
5539     [(set (match_operand:TI           0 "register_operand" "")
5540           (minus:TI (match_operand:TI 1 "register_operand" "")
5541                     (match_operand:TI 2 "general_operand"  "") ) )
5542      (clobber (reg:CC CC_REGNUM))])]
5543   "TARGET_ZARCH"
5544 {
5545   /* For z13 we have vaq which doesn't set CC.  */
5546   if (TARGET_VX)
5547     {
5548       emit_insn (gen_rtx_SET (operands[0],
5549                               gen_rtx_MINUS (TImode,
5550                                             operands[1],
5551                                             copy_to_mode_reg (TImode, operands[2]))));
5552       DONE;
5553     }
5554 })
5555
5556 (define_insn_and_split "*subti3"
5557   [(set (match_operand:TI           0 "register_operand" "=&d")
5558         (minus:TI (match_operand:TI 1 "register_operand"   "0")
5559                   (match_operand:TI 2 "general_operand"   "do") ) )
5560    (clobber (reg:CC CC_REGNUM))]
5561   "TARGET_ZARCH"
5562   "#"
5563   "&& reload_completed"
5564   [(parallel
5565     [(set (reg:CCL2 CC_REGNUM)
5566           (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5567                         (match_dup 7)))
5568      (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5569    (parallel
5570     [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5571                                   (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5572      (clobber (reg:CC CC_REGNUM))])]
5573   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5574    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5575    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5576    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5577    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5578    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5579   [(set_attr "op_type"      "*")
5580    (set_attr "cpu_facility" "*")])
5581
5582 ;
5583 ; subdi3 instruction pattern(s).
5584 ;
5585
5586 (define_expand "subdi3"
5587   [(parallel
5588     [(set (match_operand:DI 0 "register_operand" "")
5589           (minus:DI (match_operand:DI 1 "register_operand" "")
5590                     (match_operand:DI 2 "general_operand" "")))
5591      (clobber (reg:CC CC_REGNUM))])]
5592   ""
5593   "")
5594
5595 (define_insn "*subdi3_sign"
5596   [(set (match_operand:DI 0 "register_operand" "=d,d")
5597         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5598                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5599    (clobber (reg:CC CC_REGNUM))]
5600   "TARGET_ZARCH"
5601   "@
5602    sgfr\t%0,%2
5603    sgf\t%0,%2"
5604   [(set_attr "op_type"  "RRE,RXY")
5605    (set_attr "z10prop" "z10_c,*")
5606    (set_attr "z196prop" "z196_cracked")])
5607
5608 (define_insn "*subdi3_zero_cc"
5609   [(set (reg CC_REGNUM)
5610         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5611                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5612                  (const_int 0)))
5613    (set (match_operand:DI 0 "register_operand" "=d,d")
5614         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5615   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5616   "@
5617    slgfr\t%0,%2
5618    slgf\t%0,%2"
5619   [(set_attr "op_type"  "RRE,RXY")
5620    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5621
5622 (define_insn "*subdi3_zero_cconly"
5623   [(set (reg CC_REGNUM)
5624         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5625                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5626                  (const_int 0)))
5627    (clobber (match_scratch:DI 0 "=d,d"))]
5628   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5629   "@
5630    slgfr\t%0,%2
5631    slgf\t%0,%2"
5632   [(set_attr "op_type"  "RRE,RXY")
5633    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5634
5635 (define_insn "*subdi3_zero"
5636   [(set (match_operand:DI 0 "register_operand" "=d,d")
5637         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5638                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5639    (clobber (reg:CC CC_REGNUM))]
5640   "TARGET_ZARCH"
5641   "@
5642    slgfr\t%0,%2
5643    slgf\t%0,%2"
5644   [(set_attr "op_type"  "RRE,RXY")
5645    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5646
5647 (define_insn_and_split "*subdi3_31z"
5648   [(set (match_operand:DI 0 "register_operand" "=&d")
5649         (minus:DI (match_operand:DI 1 "register_operand" "0")
5650                   (match_operand:DI 2 "general_operand" "do") ) )
5651    (clobber (reg:CC CC_REGNUM))]
5652   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5653   "#"
5654   "&& reload_completed"
5655   [(parallel
5656     [(set (reg:CCL2 CC_REGNUM)
5657           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5658                         (match_dup 7)))
5659      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5660    (parallel
5661     [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5662                                   (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5663      (clobber (reg:CC CC_REGNUM))])]
5664   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5665    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5666    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5667    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5668    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5669    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5670
5671 (define_insn_and_split "*subdi3_31"
5672   [(set (match_operand:DI 0 "register_operand" "=&d")
5673         (minus:DI (match_operand:DI 1 "register_operand" "0")
5674                   (match_operand:DI 2 "general_operand" "do") ) )
5675    (clobber (reg:CC CC_REGNUM))]
5676   "!TARGET_CPU_ZARCH"
5677   "#"
5678   "&& reload_completed"
5679   [(parallel
5680     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5681      (clobber (reg:CC CC_REGNUM))])
5682    (parallel
5683     [(set (reg:CCL2 CC_REGNUM)
5684           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5685                         (match_dup 7)))
5686      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5687    (set (pc)
5688         (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5689                       (pc)
5690                       (label_ref (match_dup 9))))
5691    (parallel
5692     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5693      (clobber (reg:CC CC_REGNUM))])
5694    (match_dup 9)]
5695   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5696    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5697    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5698    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5699    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5700    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5701    operands[9] = gen_label_rtx ();")
5702
5703 ;
5704 ; subsi3 instruction pattern(s).
5705 ;
5706
5707 (define_expand "subsi3"
5708   [(parallel
5709     [(set (match_operand:SI 0 "register_operand" "")
5710           (minus:SI (match_operand:SI 1 "register_operand" "")
5711                     (match_operand:SI 2 "general_operand" "")))
5712      (clobber (reg:CC CC_REGNUM))])]
5713   ""
5714   "")
5715
5716 (define_insn "*subsi3_sign"
5717   [(set (match_operand:SI 0 "register_operand" "=d,d")
5718         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5719                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5720    (clobber (reg:CC CC_REGNUM))]
5721   ""
5722   "@
5723    sh\t%0,%2
5724    shy\t%0,%2"
5725   [(set_attr "op_type"  "RX,RXY")
5726    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5727
5728 ;
5729 ; sub(di|si)3 instruction pattern(s).
5730 ;
5731
5732 ; sr, s, sy, sgr, sg, srk, sgrk
5733 (define_insn "*sub<mode>3"
5734   [(set (match_operand:GPR 0 "register_operand"           "=d,d,d,d")
5735         (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5736                    (match_operand:GPR 2 "general_operand"  "d,d,R,T") ) )
5737    (clobber (reg:CC CC_REGNUM))]
5738   ""
5739   "@
5740    s<g>r\t%0,%2
5741    s<g>rk\t%0,%1,%2
5742    s<g>\t%0,%2
5743    s<y>\t%0,%2"
5744   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5745    (set_attr "cpu_facility" "*,z196,*,*")
5746    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5747
5748 ; slr, sl, sly, slgr, slg, slrk, slgrk
5749 (define_insn "*sub<mode>3_borrow_cc"
5750   [(set (reg CC_REGNUM)
5751         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5752                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5753                  (match_dup 1)))
5754    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5755         (minus:GPR (match_dup 1) (match_dup 2)))]
5756   "s390_match_ccmode (insn, CCL2mode)"
5757   "@
5758    sl<g>r\t%0,%2
5759    sl<g>rk\t%0,%1,%2
5760    sl<g>\t%0,%2
5761    sl<y>\t%0,%2"
5762   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5763    (set_attr "cpu_facility" "*,z196,*,*")
5764    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5765
5766 ; slr, sl, sly, slgr, slg, slrk, slgrk
5767 (define_insn "*sub<mode>3_borrow_cconly"
5768   [(set (reg CC_REGNUM)
5769         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5770                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5771                  (match_dup 1)))
5772    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5773   "s390_match_ccmode (insn, CCL2mode)"
5774   "@
5775    sl<g>r\t%0,%2
5776    sl<g>rk\t%0,%1,%2
5777    sl<g>\t%0,%2
5778    sl<y>\t%0,%2"
5779   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5780    (set_attr "cpu_facility" "*,z196,*,*")
5781    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5782
5783 ; slr, sl, sly, slgr, slg, slrk, slgrk
5784 (define_insn "*sub<mode>3_cc"
5785   [(set (reg CC_REGNUM)
5786         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5787                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5788                  (const_int 0)))
5789    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5790         (minus:GPR (match_dup 1) (match_dup 2)))]
5791   "s390_match_ccmode (insn, CCLmode)"
5792   "@
5793    sl<g>r\t%0,%2
5794    sl<g>rk\t%0,%1,%2
5795    sl<g>\t%0,%2
5796    sl<y>\t%0,%2"
5797   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5798    (set_attr "cpu_facility" "*,z196,*,*")
5799    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5800
5801 ; slr, sl, sly, slgr, slg, slrk, slgrk
5802 (define_insn "*sub<mode>3_cc2"
5803   [(set (reg CC_REGNUM)
5804         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5805                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5806    (set (match_operand:GPR 0 "register_operand"         "=d,d,d,d")
5807         (minus:GPR (match_dup 1) (match_dup 2)))]
5808   "s390_match_ccmode (insn, CCL3mode)"
5809   "@
5810    sl<g>r\t%0,%2
5811    sl<g>rk\t%0,%1,%2
5812    sl<g>\t%0,%2
5813    sl<y>\t%0,%2"
5814   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5815    (set_attr "cpu_facility" "*,z196,*,*")
5816    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5817
5818 ; slr, sl, sly, slgr, slg, slrk, slgrk
5819 (define_insn "*sub<mode>3_cconly"
5820   [(set (reg CC_REGNUM)
5821         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5822                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5823                  (const_int 0)))
5824    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5825   "s390_match_ccmode (insn, CCLmode)"
5826   "@
5827    sl<g>r\t%0,%2
5828    sl<g>rk\t%0,%1,%2
5829    sl<g>\t%0,%2
5830    sl<y>\t%0,%2"
5831   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5832    (set_attr "cpu_facility" "*,z196,*,*")
5833    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5834
5835
5836 ; slr, sl, sly, slgr, slg, slrk, slgrk
5837 (define_insn "*sub<mode>3_cconly2"
5838   [(set (reg CC_REGNUM)
5839         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5840                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5841    (clobber (match_scratch:GPR 0                        "=d,d,d,d"))]
5842   "s390_match_ccmode (insn, CCL3mode)"
5843   "@
5844    sl<g>r\t%0,%2
5845    sl<g>rk\t%0,%1,%2
5846    sl<g>\t%0,%2
5847    sl<y>\t%0,%2"
5848   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5849    (set_attr "cpu_facility" "*,z196,*,*")
5850    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5851
5852
5853 ;
5854 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5855 ;
5856
5857 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5858 (define_insn "sub<mode>3"
5859   [(set (match_operand:FP           0 "register_operand"   "=f,   f,<vf>")
5860         (minus:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
5861                   (match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))
5862    (clobber (reg:CC CC_REGNUM))]
5863   "TARGET_HARD_FLOAT"
5864   "@
5865    s<xde><bt>r\t%0,<op1>%2
5866    s<xde>b\t%0,%2
5867    wfsdb\t%v0,%v1,%v2"
5868   [(set_attr "op_type"      "<RRer>,RXE,VRR")
5869    (set_attr "type"         "fsimp<mode>")
5870    (set_attr "cpu_facility" "*,*,vec")])
5871
5872 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5873 (define_insn "*sub<mode>3_cc"
5874   [(set (reg CC_REGNUM)
5875         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5876                            (match_operand:FP 2 "general_operand"      "f,<Rf>"))
5877                  (match_operand:FP 3 "const0_operand" "")))
5878    (set (match_operand:FP 0 "register_operand" "=f,f")
5879         (minus:FP (match_dup 1) (match_dup 2)))]
5880   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5881   "@
5882    s<xde><bt>r\t%0,<op1>%2
5883    s<xde>b\t%0,%2"
5884   [(set_attr "op_type"  "<RRer>,RXE")
5885    (set_attr "type"     "fsimp<mode>")])
5886
5887 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5888 (define_insn "*sub<mode>3_cconly"
5889   [(set (reg CC_REGNUM)
5890         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5891                            (match_operand:FP 2 "general_operand"      "f,<Rf>"))
5892                  (match_operand:FP 3 "const0_operand" "")))
5893    (clobber (match_scratch:FP 0 "=f,f"))]
5894   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5895   "@
5896    s<xde><bt>r\t%0,<op1>%2
5897    s<xde>b\t%0,%2"
5898   [(set_attr "op_type"  "<RRer>,RXE")
5899    (set_attr "type"     "fsimp<mode>")])
5900
5901
5902 ;;
5903 ;;- Conditional add/subtract instructions.
5904 ;;
5905
5906 ;
5907 ; add(di|si)cc instruction pattern(s).
5908 ;
5909
5910 ; the following 4 patterns are used when the result of an add with
5911 ; carry is checked for an overflow condition
5912
5913 ; op1 + op2 + c < op1
5914
5915 ; alcr, alc, alcgr, alcg
5916 (define_insn "*add<mode>3_alc_carry1_cc"
5917   [(set (reg CC_REGNUM)
5918         (compare
5919           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5920                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5921                     (match_operand:GPR 2 "general_operand" "d,RT"))
5922           (match_dup 1)))
5923    (set (match_operand:GPR 0 "register_operand" "=d,d")
5924         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5925   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5926   "@
5927    alc<g>r\t%0,%2
5928    alc<g>\t%0,%2"
5929   [(set_attr "op_type"  "RRE,RXY")
5930    (set_attr "z196prop" "z196_alone,z196_alone")])
5931
5932 ; alcr, alc, alcgr, alcg
5933 (define_insn "*add<mode>3_alc_carry1_cconly"
5934   [(set (reg CC_REGNUM)
5935         (compare
5936           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5937                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5938                     (match_operand:GPR 2 "general_operand" "d,RT"))
5939           (match_dup 1)))
5940    (clobber (match_scratch:GPR 0 "=d,d"))]
5941   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5942   "@
5943    alc<g>r\t%0,%2
5944    alc<g>\t%0,%2"
5945   [(set_attr "op_type"  "RRE,RXY")
5946    (set_attr "z196prop" "z196_alone,z196_alone")])
5947
5948 ; op1 + op2 + c < op2
5949
5950 ; alcr, alc, alcgr, alcg
5951 (define_insn "*add<mode>3_alc_carry2_cc"
5952   [(set (reg CC_REGNUM)
5953         (compare
5954           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5955                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5956                     (match_operand:GPR 2 "general_operand" "d,RT"))
5957           (match_dup 2)))
5958    (set (match_operand:GPR 0 "register_operand" "=d,d")
5959         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5960   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5961   "@
5962    alc<g>r\t%0,%2
5963    alc<g>\t%0,%2"
5964   [(set_attr "op_type"  "RRE,RXY")])
5965
5966 ; alcr, alc, alcgr, alcg
5967 (define_insn "*add<mode>3_alc_carry2_cconly"
5968   [(set (reg CC_REGNUM)
5969         (compare
5970           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5971                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5972                     (match_operand:GPR 2 "general_operand" "d,RT"))
5973           (match_dup 2)))
5974    (clobber (match_scratch:GPR 0 "=d,d"))]
5975   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5976   "@
5977    alc<g>r\t%0,%2
5978    alc<g>\t%0,%2"
5979   [(set_attr "op_type"  "RRE,RXY")])
5980
5981 ; alcr, alc, alcgr, alcg
5982 (define_insn "*add<mode>3_alc_cc"
5983   [(set (reg CC_REGNUM)
5984         (compare
5985           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5986                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5987                     (match_operand:GPR 2 "general_operand" "d,RT"))
5988           (const_int 0)))
5989    (set (match_operand:GPR 0 "register_operand" "=d,d")
5990         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5991   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5992   "@
5993    alc<g>r\t%0,%2
5994    alc<g>\t%0,%2"
5995   [(set_attr "op_type"  "RRE,RXY")])
5996
5997 ; alcr, alc, alcgr, alcg
5998 (define_insn "*add<mode>3_alc"
5999   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6000         (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6001                             (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6002                   (match_operand:GPR 2 "general_operand" "d,RT")))
6003    (clobber (reg:CC CC_REGNUM))]
6004   "TARGET_CPU_ZARCH"
6005   "@
6006    alc<g>r\t%0,%2
6007    alc<g>\t%0,%2"
6008   [(set_attr "op_type"  "RRE,RXY")])
6009
6010 ; slbr, slb, slbgr, slbg
6011 (define_insn "*sub<mode>3_slb_cc"
6012   [(set (reg CC_REGNUM)
6013         (compare
6014           (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6015                                 (match_operand:GPR 2 "general_operand" "d,RT"))
6016                      (match_operand:GPR 3 "s390_slb_comparison" ""))
6017           (const_int 0)))
6018    (set (match_operand:GPR 0 "register_operand" "=d,d")
6019         (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6020   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6021   "@
6022    slb<g>r\t%0,%2
6023    slb<g>\t%0,%2"
6024   [(set_attr "op_type"  "RRE,RXY")
6025    (set_attr "z10prop" "z10_c,*")])
6026
6027 ; slbr, slb, slbgr, slbg
6028 (define_insn "*sub<mode>3_slb"
6029   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6030         (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6031                               (match_operand:GPR 2 "general_operand" "d,RT"))
6032                    (match_operand:GPR 3 "s390_slb_comparison" "")))
6033    (clobber (reg:CC CC_REGNUM))]
6034   "TARGET_CPU_ZARCH"
6035   "@
6036    slb<g>r\t%0,%2
6037    slb<g>\t%0,%2"
6038   [(set_attr "op_type"  "RRE,RXY")
6039    (set_attr "z10prop" "z10_c,*")])
6040
6041 (define_expand "add<mode>cc"
6042   [(match_operand:GPR 0 "register_operand" "")
6043    (match_operand 1 "comparison_operator" "")
6044    (match_operand:GPR 2 "register_operand" "")
6045    (match_operand:GPR 3 "const_int_operand" "")]
6046   "TARGET_CPU_ZARCH"
6047   "if (!s390_expand_addcc (GET_CODE (operands[1]),
6048                            XEXP (operands[1], 0), XEXP (operands[1], 1),
6049                            operands[0], operands[2],
6050                            operands[3])) FAIL; DONE;")
6051
6052 ;
6053 ; scond instruction pattern(s).
6054 ;
6055
6056 (define_insn_and_split "*scond<mode>"
6057   [(set (match_operand:GPR 0 "register_operand" "=&d")
6058         (match_operand:GPR 1 "s390_alc_comparison" ""))
6059    (clobber (reg:CC CC_REGNUM))]
6060   "TARGET_CPU_ZARCH"
6061   "#"
6062   "&& reload_completed"
6063   [(set (match_dup 0) (const_int 0))
6064    (parallel
6065     [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6066                                   (match_dup 0)))
6067      (clobber (reg:CC CC_REGNUM))])]
6068   "")
6069
6070 (define_insn_and_split "*scond<mode>_neg"
6071   [(set (match_operand:GPR 0 "register_operand" "=&d")
6072         (match_operand:GPR 1 "s390_slb_comparison" ""))
6073    (clobber (reg:CC CC_REGNUM))]
6074   "TARGET_CPU_ZARCH"
6075   "#"
6076   "&& reload_completed"
6077   [(set (match_dup 0) (const_int 0))
6078    (parallel
6079     [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6080                                    (match_dup 1)))
6081      (clobber (reg:CC CC_REGNUM))])
6082    (parallel
6083     [(set (match_dup 0) (neg:GPR (match_dup 0)))
6084      (clobber (reg:CC CC_REGNUM))])]
6085   "")
6086
6087
6088 (define_expand "cstore<mode>4"
6089   [(set (match_operand:SI 0 "register_operand" "")
6090         (match_operator:SI 1 "s390_scond_operator"
6091          [(match_operand:GPR 2 "register_operand" "")
6092           (match_operand:GPR 3 "general_operand" "")]))]
6093   "TARGET_CPU_ZARCH"
6094   "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6095                            operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6096
6097 (define_expand "cstorecc4"
6098   [(parallel
6099     [(set (match_operand:SI 0 "register_operand" "")
6100           (match_operator:SI 1 "s390_eqne_operator"
6101            [(match_operand:CCZ1 2 "register_operand")
6102             (match_operand 3 "const0_operand")]))
6103      (clobber (reg:CC CC_REGNUM))])]
6104   ""
6105   "emit_insn (gen_sne (operands[0], operands[2]));
6106    if (GET_CODE (operands[1]) == EQ)
6107      emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6108    DONE;")
6109
6110 (define_insn_and_split "sne"
6111   [(set (match_operand:SI 0 "register_operand" "=d")
6112         (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6113                (const_int 0)))
6114    (clobber (reg:CC CC_REGNUM))]
6115   ""
6116   "#"
6117   "reload_completed"
6118   [(parallel
6119     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6120      (clobber (reg:CC CC_REGNUM))])])
6121
6122
6123 ;;
6124 ;; - Conditional move instructions (introduced with z196)
6125 ;;
6126
6127 (define_expand "mov<mode>cc"
6128   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6129         (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6130                           (match_operand:GPR 2 "nonimmediate_operand" "")
6131                           (match_operand:GPR 3 "nonimmediate_operand" "")))]
6132   "TARGET_Z196"
6133 {
6134   /* Emit the comparison insn in case we do not already have a comparison result.  */
6135   if (!s390_comparison (operands[1], VOIDmode))
6136     operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6137                                      XEXP (operands[1], 0),
6138                                      XEXP (operands[1], 1));
6139 })
6140
6141 ; locr, loc, stoc, locgr, locg, stocg
6142 (define_insn_and_split "*mov<mode>cc"
6143   [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d, d, d,QS,QS,&d")
6144         (if_then_else:GPR
6145           (match_operator 1 "s390_comparison"
6146             [(match_operand 2 "cc_reg_operand"        " c,c, c, c, c, c, c")
6147              (match_operand 5 "const_int_operand"     "")])
6148           (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
6149           (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
6150   "TARGET_Z196"
6151   "@
6152    loc<g>r%C1\t%0,%3
6153    loc<g>r%D1\t%0,%4
6154    loc<g>%C1\t%0,%3
6155    loc<g>%D1\t%0,%4
6156    stoc<g>%C1\t%3,%0
6157    stoc<g>%D1\t%4,%0
6158    #"
6159   "&& reload_completed
6160    && MEM_P (operands[3]) && MEM_P (operands[4])"
6161   [(set (match_dup 0)
6162         (if_then_else:GPR
6163          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6164          (match_dup 3)
6165          (match_dup 0)))
6166    (set (match_dup 0)
6167         (if_then_else:GPR
6168          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6169          (match_dup 0)
6170          (match_dup 4)))]
6171   ""
6172   [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
6173
6174 ;;
6175 ;;- Multiply instructions.
6176 ;;
6177
6178 ;
6179 ; muldi3 instruction pattern(s).
6180 ;
6181
6182 (define_insn "*muldi3_sign"
6183   [(set (match_operand:DI 0 "register_operand" "=d,d")
6184         (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
6185                  (match_operand:DI 1 "register_operand" "0,0")))]
6186   "TARGET_ZARCH"
6187   "@
6188    msgfr\t%0,%2
6189    msgf\t%0,%2"
6190   [(set_attr "op_type"      "RRE,RXY")
6191    (set_attr "type"         "imuldi")])
6192
6193 (define_insn "muldi3"
6194   [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6195         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6196                  (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
6197   "TARGET_ZARCH"
6198   "@
6199    msgr\t%0,%2
6200    mghi\t%0,%h2
6201    msg\t%0,%2
6202    msgfi\t%0,%2"
6203   [(set_attr "op_type"      "RRE,RI,RXY,RIL")
6204    (set_attr "type"         "imuldi")
6205    (set_attr "cpu_facility" "*,*,*,z10")])
6206
6207 ;
6208 ; mulsi3 instruction pattern(s).
6209 ;
6210
6211 (define_insn "*mulsi3_sign"
6212   [(set (match_operand:SI 0 "register_operand" "=d,d")
6213         (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6214                  (match_operand:SI 1 "register_operand" "0,0")))]
6215   ""
6216   "@
6217    mh\t%0,%2
6218    mhy\t%0,%2"
6219   [(set_attr "op_type"      "RX,RXY")
6220    (set_attr "type"         "imulhi")
6221    (set_attr "cpu_facility" "*,z10")])
6222
6223 (define_insn "mulsi3"
6224   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6225         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6226                   (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6227   ""
6228   "@
6229    msr\t%0,%2
6230    mhi\t%0,%h2
6231    ms\t%0,%2
6232    msy\t%0,%2
6233    msfi\t%0,%2"
6234   [(set_attr "op_type"      "RRE,RI,RX,RXY,RIL")
6235    (set_attr "type"         "imulsi,imulhi,imulsi,imulsi,imulsi")
6236    (set_attr "cpu_facility" "*,*,*,*,z10")])
6237
6238 ;
6239 ; mulsidi3 instruction pattern(s).
6240 ;
6241
6242 (define_insn "mulsidi3"
6243   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6244         (mult:DI (sign_extend:DI
6245                    (match_operand:SI 1 "register_operand" "%0,0,0"))
6246                  (sign_extend:DI
6247                    (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6248   "!TARGET_ZARCH"
6249   "@
6250    mr\t%0,%2
6251    m\t%0,%2
6252    mfy\t%0,%2"
6253   [(set_attr "op_type"      "RR,RX,RXY")
6254    (set_attr "type"         "imulsi")
6255    (set_attr "cpu_facility" "*,*,z10")])
6256
6257 ;
6258 ; umul instruction pattern(s).
6259 ;
6260
6261 ; mlr, ml, mlgr, mlg
6262 (define_insn "umul<dwh><mode>3"
6263   [(set (match_operand:DW 0 "register_operand"                   "=d, d")
6264         (mult:DW (zero_extend:DW
6265                    (match_operand:<DWH> 1 "register_operand"     "%0, 0"))
6266                  (zero_extend:DW
6267                    (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
6268   "TARGET_CPU_ZARCH"
6269   "@
6270    ml<tg>r\t%0,%2
6271    ml<tg>\t%0,%2"
6272   [(set_attr "op_type"  "RRE,RXY")
6273    (set_attr "type"     "imul<dwh>")])
6274
6275 ;
6276 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6277 ;
6278
6279 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6280 (define_insn "mul<mode>3"
6281   [(set (match_operand:FP          0 "register_operand"        "=f,   f,<vf>")
6282         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
6283                  (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))]
6284   "TARGET_HARD_FLOAT"
6285   "@
6286    m<xdee><bt>r\t%0,<op1>%2
6287    m<xdee>b\t%0,%2
6288    wfmdb\t%v0,%v1,%v2"
6289   [(set_attr "op_type"      "<RRer>,RXE,VRR")
6290    (set_attr "type"         "fmul<mode>")
6291    (set_attr "cpu_facility" "*,*,vec")])
6292
6293 ; madbr, maebr, maxb, madb, maeb
6294 (define_insn "fma<mode>4"
6295   [(set (match_operand:DSF          0 "register_operand"     "=f,f,<vf>")
6296         (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
6297                  (match_operand:DSF 2 "nonimmediate_operand"  "f,R,<vf>")
6298                  (match_operand:DSF 3 "register_operand"      "0,0,<v0>")))]
6299   "TARGET_HARD_FLOAT"
6300   "@
6301    ma<xde>br\t%0,%1,%2
6302    ma<xde>b\t%0,%1,%2
6303    wfmadb\t%v0,%v1,%v2,%v3"
6304   [(set_attr "op_type"      "RRE,RXE,VRR")
6305    (set_attr "type"         "fmadd<mode>")
6306    (set_attr "cpu_facility" "*,*,vec")])
6307
6308 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6309 (define_insn "fms<mode>4"
6310   [(set (match_operand:DSF                   0 "register_operand"     "=f,f,<vf>")
6311         (fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,<vf>")
6312                  (match_operand:DSF          2 "nonimmediate_operand"  "f,R,<vf>")
6313                  (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,<v0>"))))]
6314   "TARGET_HARD_FLOAT"
6315   "@
6316    ms<xde>br\t%0,%1,%2
6317    ms<xde>b\t%0,%1,%2
6318    wfmsdb\t%v0,%v1,%v2,%v3"
6319   [(set_attr "op_type"      "RRE,RXE,VRR")
6320    (set_attr "type"         "fmadd<mode>")
6321    (set_attr "cpu_facility" "*,*,vec")])
6322
6323 ;;
6324 ;;- Divide and modulo instructions.
6325 ;;
6326
6327 ;
6328 ; divmoddi4 instruction pattern(s).
6329 ;
6330
6331 (define_expand "divmoddi4"
6332   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6333                    (div:DI (match_operand:DI 1 "register_operand" "")
6334                            (match_operand:DI 2 "general_operand" "")))
6335               (set (match_operand:DI 3 "general_operand" "")
6336                    (mod:DI (match_dup 1) (match_dup 2)))])
6337    (clobber (match_dup 4))]
6338   "TARGET_ZARCH"
6339 {
6340   rtx insn, div_equal, mod_equal;
6341
6342   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6343   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6344
6345   operands[4] = gen_reg_rtx(TImode);
6346   emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6347
6348   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6349   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6350
6351   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6352   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6353
6354   DONE;
6355 })
6356
6357 (define_insn "divmodtidi3"
6358   [(set (match_operand:TI 0 "register_operand" "=d,d")
6359         (ior:TI
6360           (ashift:TI
6361             (zero_extend:TI
6362               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6363                       (match_operand:DI 2 "general_operand" "d,RT")))
6364             (const_int 64))
6365           (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6366   "TARGET_ZARCH"
6367   "@
6368    dsgr\t%0,%2
6369    dsg\t%0,%2"
6370   [(set_attr "op_type"  "RRE,RXY")
6371    (set_attr "type"     "idiv")])
6372
6373 (define_insn "divmodtisi3"
6374   [(set (match_operand:TI 0 "register_operand" "=d,d")
6375         (ior:TI
6376           (ashift:TI
6377             (zero_extend:TI
6378               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6379                       (sign_extend:DI
6380                         (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
6381             (const_int 64))
6382           (zero_extend:TI
6383             (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6384   "TARGET_ZARCH"
6385   "@
6386    dsgfr\t%0,%2
6387    dsgf\t%0,%2"
6388   [(set_attr "op_type"  "RRE,RXY")
6389    (set_attr "type"     "idiv")])
6390
6391 ;
6392 ; udivmoddi4 instruction pattern(s).
6393 ;
6394
6395 (define_expand "udivmoddi4"
6396   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6397                    (udiv:DI (match_operand:DI 1 "general_operand" "")
6398                             (match_operand:DI 2 "nonimmediate_operand" "")))
6399               (set (match_operand:DI 3 "general_operand" "")
6400                    (umod:DI (match_dup 1) (match_dup 2)))])
6401    (clobber (match_dup 4))]
6402   "TARGET_ZARCH"
6403 {
6404   rtx insn, div_equal, mod_equal, equal;
6405
6406   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6407   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6408   equal = gen_rtx_IOR (TImode,
6409                        gen_rtx_ASHIFT (TImode,
6410                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6411                                        GEN_INT (64)),
6412                        gen_rtx_ZERO_EXTEND (TImode, div_equal));
6413
6414   operands[4] = gen_reg_rtx(TImode);
6415   emit_clobber (operands[4]);
6416   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6417   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6418
6419   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6420   set_unique_reg_note (insn, REG_EQUAL, equal);
6421
6422   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6423   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6424
6425   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6426   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6427
6428   DONE;
6429 })
6430
6431 (define_insn "udivmodtidi3"
6432   [(set (match_operand:TI 0 "register_operand" "=d,d")
6433         (ior:TI
6434           (ashift:TI
6435             (zero_extend:TI
6436               (truncate:DI
6437                 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6438                          (zero_extend:TI
6439                            (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6440             (const_int 64))
6441           (zero_extend:TI
6442             (truncate:DI
6443               (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6444   "TARGET_ZARCH"
6445   "@
6446    dlgr\t%0,%2
6447    dlg\t%0,%2"
6448   [(set_attr "op_type"  "RRE,RXY")
6449    (set_attr "type"     "idiv")])
6450
6451 ;
6452 ; divmodsi4 instruction pattern(s).
6453 ;
6454
6455 (define_expand "divmodsi4"
6456   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6457                    (div:SI (match_operand:SI 1 "general_operand" "")
6458                            (match_operand:SI 2 "nonimmediate_operand" "")))
6459               (set (match_operand:SI 3 "general_operand" "")
6460                    (mod:SI (match_dup 1) (match_dup 2)))])
6461    (clobber (match_dup 4))]
6462   "!TARGET_ZARCH"
6463 {
6464   rtx insn, div_equal, mod_equal, equal;
6465
6466   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6467   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6468   equal = gen_rtx_IOR (DImode,
6469                        gen_rtx_ASHIFT (DImode,
6470                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6471                                        GEN_INT (32)),
6472                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6473
6474   operands[4] = gen_reg_rtx(DImode);
6475   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6476
6477   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6478   set_unique_reg_note (insn, REG_EQUAL, equal);
6479
6480   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6481   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6482
6483   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6484   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6485
6486   DONE;
6487 })
6488
6489 (define_insn "divmoddisi3"
6490   [(set (match_operand:DI 0 "register_operand" "=d,d")
6491         (ior:DI
6492           (ashift:DI
6493             (zero_extend:DI
6494               (truncate:SI
6495                 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6496                         (sign_extend:DI
6497                           (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6498             (const_int 32))
6499           (zero_extend:DI
6500             (truncate:SI
6501               (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6502   "!TARGET_ZARCH"
6503   "@
6504    dr\t%0,%2
6505    d\t%0,%2"
6506   [(set_attr "op_type"  "RR,RX")
6507    (set_attr "type"     "idiv")])
6508
6509 ;
6510 ; udivsi3 and umodsi3 instruction pattern(s).
6511 ;
6512
6513 (define_expand "udivmodsi4"
6514   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6515                    (udiv:SI (match_operand:SI 1 "general_operand" "")
6516                             (match_operand:SI 2 "nonimmediate_operand" "")))
6517               (set (match_operand:SI 3 "general_operand" "")
6518                    (umod:SI (match_dup 1) (match_dup 2)))])
6519    (clobber (match_dup 4))]
6520   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6521 {
6522   rtx insn, div_equal, mod_equal, equal;
6523
6524   div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6525   mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6526   equal = gen_rtx_IOR (DImode,
6527                        gen_rtx_ASHIFT (DImode,
6528                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6529                                        GEN_INT (32)),
6530                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6531
6532   operands[4] = gen_reg_rtx(DImode);
6533   emit_clobber (operands[4]);
6534   emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6535   emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6536
6537   insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6538   set_unique_reg_note (insn, REG_EQUAL, equal);
6539
6540   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6541   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6542
6543   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6544   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6545
6546   DONE;
6547 })
6548
6549 (define_insn "udivmoddisi3"
6550   [(set (match_operand:DI 0 "register_operand" "=d,d")
6551         (ior:DI
6552           (ashift:DI
6553             (zero_extend:DI
6554               (truncate:SI
6555                 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6556                          (zero_extend:DI
6557                            (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6558             (const_int 32))
6559           (zero_extend:DI
6560             (truncate:SI
6561               (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6562   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6563   "@
6564    dlr\t%0,%2
6565    dl\t%0,%2"
6566   [(set_attr "op_type"  "RRE,RXY")
6567    (set_attr "type"     "idiv")])
6568
6569 (define_expand "udivsi3"
6570   [(set (match_operand:SI 0 "register_operand" "=d")
6571         (udiv:SI (match_operand:SI 1 "general_operand" "")
6572                  (match_operand:SI 2 "general_operand" "")))
6573    (clobber (match_dup 3))]
6574   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6575 {
6576   rtx insn, udiv_equal, umod_equal, equal;
6577
6578   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6579   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6580   equal = gen_rtx_IOR (DImode,
6581                        gen_rtx_ASHIFT (DImode,
6582                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6583                                        GEN_INT (32)),
6584                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6585
6586   operands[3] = gen_reg_rtx (DImode);
6587
6588   if (CONSTANT_P (operands[2]))
6589     {
6590       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6591         {
6592           rtx_code_label *label1 = gen_label_rtx ();
6593
6594           operands[1] = make_safe_from (operands[1], operands[0]);
6595           emit_move_insn (operands[0], const0_rtx);
6596           emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6597                                    SImode, 1, label1);
6598           emit_move_insn (operands[0], const1_rtx);
6599           emit_label (label1);
6600         }
6601       else
6602         {
6603           operands[2] = force_reg (SImode, operands[2]);
6604           operands[2] = make_safe_from (operands[2], operands[0]);
6605
6606           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6607           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6608                                              operands[2]));
6609           set_unique_reg_note (insn, REG_EQUAL, equal);
6610
6611           insn = emit_move_insn (operands[0],
6612                                  gen_lowpart (SImode, operands[3]));
6613           set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6614         }
6615     }
6616   else
6617     {
6618       rtx_code_label *label1 = gen_label_rtx ();
6619       rtx_code_label *label2 = gen_label_rtx ();
6620       rtx_code_label *label3 = gen_label_rtx ();
6621
6622       operands[1] = force_reg (SImode, operands[1]);
6623       operands[1] = make_safe_from (operands[1], operands[0]);
6624       operands[2] = force_reg (SImode, operands[2]);
6625       operands[2] = make_safe_from (operands[2], operands[0]);
6626
6627       emit_move_insn (operands[0], const0_rtx);
6628       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6629                                SImode, 1, label3);
6630       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6631                                SImode, 0, label2);
6632       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6633                                SImode, 0, label1);
6634       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6635       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6636                                          operands[2]));
6637       set_unique_reg_note (insn, REG_EQUAL, equal);
6638
6639       insn = emit_move_insn (operands[0],
6640                              gen_lowpart (SImode, operands[3]));
6641       set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6642
6643       emit_jump (label3);
6644       emit_label (label1);
6645       emit_move_insn (operands[0], operands[1]);
6646       emit_jump (label3);
6647       emit_label (label2);
6648       emit_move_insn (operands[0], const1_rtx);
6649       emit_label (label3);
6650     }
6651   emit_move_insn (operands[0], operands[0]);
6652   DONE;
6653 })
6654
6655 (define_expand "umodsi3"
6656   [(set (match_operand:SI 0 "register_operand" "=d")
6657         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6658                  (match_operand:SI 2 "nonimmediate_operand" "")))
6659    (clobber (match_dup 3))]
6660   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6661 {
6662   rtx insn, udiv_equal, umod_equal, equal;
6663
6664   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6665   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6666   equal = gen_rtx_IOR (DImode,
6667                        gen_rtx_ASHIFT (DImode,
6668                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6669                                        GEN_INT (32)),
6670                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6671
6672   operands[3] = gen_reg_rtx (DImode);
6673
6674   if (CONSTANT_P (operands[2]))
6675     {
6676       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6677         {
6678           rtx_code_label *label1 = gen_label_rtx ();
6679
6680           operands[1] = make_safe_from (operands[1], operands[0]);
6681           emit_move_insn (operands[0], operands[1]);
6682           emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6683                                    SImode, 1, label1);
6684           emit_insn (gen_abssi2 (operands[0], operands[2]));
6685           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6686           emit_label (label1);
6687         }
6688       else
6689         {
6690           operands[2] = force_reg (SImode, operands[2]);
6691           operands[2] = make_safe_from (operands[2], operands[0]);
6692
6693           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6694           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6695                                              operands[2]));
6696           set_unique_reg_note (insn, REG_EQUAL, equal);
6697
6698           insn = emit_move_insn (operands[0],
6699                                  gen_highpart (SImode, operands[3]));
6700           set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6701         }
6702     }
6703   else
6704     {
6705       rtx_code_label *label1 = gen_label_rtx ();
6706       rtx_code_label *label2 = gen_label_rtx ();
6707       rtx_code_label *label3 = gen_label_rtx ();
6708
6709       operands[1] = force_reg (SImode, operands[1]);
6710       operands[1] = make_safe_from (operands[1], operands[0]);
6711       operands[2] = force_reg (SImode, operands[2]);
6712       operands[2] = make_safe_from (operands[2], operands[0]);
6713
6714       emit_move_insn(operands[0], operands[1]);
6715       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6716                                SImode, 1, label3);
6717       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6718                                SImode, 0, label2);
6719       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6720                                SImode, 0, label1);
6721       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6722       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6723                                          operands[2]));
6724       set_unique_reg_note (insn, REG_EQUAL, equal);
6725
6726       insn = emit_move_insn (operands[0],
6727                              gen_highpart (SImode, operands[3]));
6728       set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6729
6730       emit_jump (label3);
6731       emit_label (label1);
6732       emit_move_insn (operands[0], const0_rtx);
6733       emit_jump (label3);
6734       emit_label (label2);
6735       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6736       emit_label (label3);
6737     }
6738   DONE;
6739 })
6740
6741 ;
6742 ; div(df|sf)3 instruction pattern(s).
6743 ;
6744
6745 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6746 (define_insn "div<mode>3"
6747   [(set (match_operand:FP         0 "register_operand"   "=f,   f,<vf>")
6748         (div:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
6749                 (match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))]
6750   "TARGET_HARD_FLOAT"
6751   "@
6752    d<xde><bt>r\t%0,<op1>%2
6753    d<xde>b\t%0,%2
6754    wfddb\t%v0,%v1,%v2"
6755   [(set_attr "op_type"      "<RRer>,RXE,VRR")
6756    (set_attr "type"         "fdiv<mode>")
6757    (set_attr "cpu_facility" "*,*,vec")])
6758
6759
6760 ;;
6761 ;;- And instructions.
6762 ;;
6763
6764 (define_expand "and<mode>3"
6765   [(set (match_operand:INT 0 "nonimmediate_operand" "")
6766         (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6767                  (match_operand:INT 2 "general_operand" "")))
6768    (clobber (reg:CC CC_REGNUM))]
6769   ""
6770   "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6771
6772 ;
6773 ; anddi3 instruction pattern(s).
6774 ;
6775
6776 (define_insn "*anddi3_cc"
6777   [(set (reg CC_REGNUM)
6778         (compare
6779           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6780                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6781           (const_int 0)))
6782    (set (match_operand:DI 0 "register_operand"               "=d,d, d,    d")
6783         (and:DI (match_dup 1) (match_dup 2)))]
6784   "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6785   "@
6786    ngr\t%0,%2
6787    ngrk\t%0,%1,%2
6788    ng\t%0,%2
6789    risbg\t%0,%1,%s2,128+%e2,0"
6790   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6791    (set_attr "cpu_facility" "*,z196,*,z10")
6792    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6793
6794 (define_insn "*anddi3_cconly"
6795   [(set (reg CC_REGNUM)
6796         (compare
6797           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6798                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6799                  (const_int 0)))
6800    (clobber (match_scratch:DI 0                              "=d,d, d,    d"))]
6801   "TARGET_ZARCH
6802    && s390_match_ccmode(insn, CCTmode)
6803    /* Do not steal TM patterns.  */
6804    && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6805   "@
6806    ngr\t%0,%2
6807    ngrk\t%0,%1,%2
6808    ng\t%0,%2
6809    risbg\t%0,%1,%s2,128+%e2,0"
6810   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6811    (set_attr "cpu_facility" "*,z196,*,z10")
6812    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6813
6814 (define_insn "*anddi3"
6815   [(set (match_operand:DI 0 "nonimmediate_operand"
6816             "=d,d,    d,    d,    d,    d,    d,    d,d,d, d,    d,   AQ,Q")
6817         (and:DI
6818           (match_operand:DI 1 "nonimmediate_operand"
6819             "%d,o,    0,    0,    0,    0,    0,    0,0,d, 0,    d,    0,0")
6820           (match_operand:DI 2 "general_operand"
6821             "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6822    (clobber (reg:CC CC_REGNUM))]
6823   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6824   "@
6825    #
6826    #
6827    nihh\t%0,%j2
6828    nihl\t%0,%j2
6829    nilh\t%0,%j2
6830    nill\t%0,%j2
6831    nihf\t%0,%m2
6832    nilf\t%0,%m2
6833    ngr\t%0,%2
6834    ngrk\t%0,%1,%2
6835    ng\t%0,%2
6836    risbg\t%0,%1,%s2,128+%e2,0
6837    #
6838    #"
6839   [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6840    (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6841    (set_attr "z10prop" "*,
6842                         *,
6843                         z10_super_E1,
6844                         z10_super_E1,
6845                         z10_super_E1,
6846                         z10_super_E1,
6847                         z10_super_E1,
6848                         z10_super_E1,
6849                         z10_super_E1,
6850                         *,
6851                         z10_super_E1,
6852                         z10_super_E1,
6853                         *,
6854                         *")])
6855
6856 (define_split
6857   [(set (match_operand:DI 0 "s_operand" "")
6858         (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6859    (clobber (reg:CC CC_REGNUM))]
6860   "reload_completed"
6861   [(parallel
6862     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6863      (clobber (reg:CC CC_REGNUM))])]
6864   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6865
6866 ;; These two are what combine generates for (ashift (zero_extract)).
6867 (define_insn "*extzv_<mode>_srl"
6868   [(set (match_operand:GPR 0 "register_operand" "=d")
6869         (and:GPR (lshiftrt:GPR
6870                    (match_operand:GPR 1 "register_operand" "d")
6871                    (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6872                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6873    (clobber (reg:CC CC_REGNUM))]
6874   "TARGET_Z10
6875    /* Note that even for the SImode pattern, the rotate is always DImode.  */
6876    && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6877                            INTVAL (operands[3]))"
6878   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6879   [(set_attr "op_type" "RIE")
6880    (set_attr "z10prop" "z10_super_E1")])
6881
6882 (define_insn "*extzv_<mode>_sll"
6883   [(set (match_operand:GPR 0 "register_operand" "=d")
6884         (and:GPR (ashift:GPR
6885                   (match_operand:GPR 1 "register_operand" "d")
6886                   (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6887                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6888    (clobber (reg:CC CC_REGNUM))]
6889   "TARGET_Z10
6890    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6891                            INTVAL (operands[3]))"
6892   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6893   [(set_attr "op_type" "RIE")
6894    (set_attr "z10prop" "z10_super_E1")])
6895
6896
6897 ;
6898 ; andsi3 instruction pattern(s).
6899 ;
6900
6901 (define_insn "*andsi3_cc"
6902   [(set (reg CC_REGNUM)
6903         (compare
6904           (and:SI
6905             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6906             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6907           (const_int 0)))
6908    (set (match_operand:SI 0 "register_operand"         "=d,d,d,d,d,    d")
6909         (and:SI (match_dup 1) (match_dup 2)))]
6910   "s390_match_ccmode(insn, CCTmode)"
6911   "@
6912    nilf\t%0,%o2
6913    nr\t%0,%2
6914    nrk\t%0,%1,%2
6915    n\t%0,%2
6916    ny\t%0,%2
6917    risbg\t%0,%1,%t2,128+%f2,0"
6918   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6919    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6920    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6921                         z10_super_E1,z10_super_E1,z10_super_E1")])
6922
6923 (define_insn "*andsi3_cconly"
6924   [(set (reg CC_REGNUM)
6925         (compare
6926           (and:SI
6927             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6928             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6929           (const_int 0)))
6930    (clobber (match_scratch:SI 0                        "=d,d,d,d,d,    d"))]
6931   "s390_match_ccmode(insn, CCTmode)
6932    /* Do not steal TM patterns.  */
6933    && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6934   "@
6935    nilf\t%0,%o2
6936    nr\t%0,%2
6937    nrk\t%0,%1,%2
6938    n\t%0,%2
6939    ny\t%0,%2
6940    risbg\t%0,%1,%t2,128+%f2,0"
6941   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6942    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6943    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6944                         z10_super_E1,z10_super_E1,z10_super_E1")])
6945
6946 (define_insn "*andsi3_zarch"
6947   [(set (match_operand:SI 0 "nonimmediate_operand"
6948                             "=d,d,    d,    d, d,d,d,d,d,    d,   AQ,Q")
6949         (and:SI (match_operand:SI 1 "nonimmediate_operand"
6950                             "%d,o,    0,    0, 0,0,d,0,0,    d,    0,0")
6951                 (match_operand:SI 2 "general_operand"
6952                             " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6953    (clobber (reg:CC CC_REGNUM))]
6954   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6955   "@
6956    #
6957    #
6958    nilh\t%0,%j2
6959    nill\t%0,%j2
6960    nilf\t%0,%o2
6961    nr\t%0,%2
6962    nrk\t%0,%1,%2
6963    n\t%0,%2
6964    ny\t%0,%2
6965    risbg\t%0,%1,%t2,128+%f2,0
6966    #
6967    #"
6968   [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6969    (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6970    (set_attr "z10prop" "*,
6971                         *,
6972                         z10_super_E1,
6973                         z10_super_E1,
6974                         z10_super_E1,
6975                         z10_super_E1,
6976                         *,
6977                         z10_super_E1,
6978                         z10_super_E1,
6979                         z10_super_E1,
6980                         *,
6981                         *")])
6982
6983 (define_insn "*andsi3_esa"
6984   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,   AQ,Q")
6985         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,    0,0")
6986                 (match_operand:SI 2 "general_operand"      " d,R,NxQSF,Q")))
6987    (clobber (reg:CC CC_REGNUM))]
6988   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6989   "@
6990    nr\t%0,%2
6991    n\t%0,%2
6992    #
6993    #"
6994   [(set_attr "op_type"  "RR,RX,SI,SS")
6995    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6996
6997
6998 (define_split
6999   [(set (match_operand:SI 0 "s_operand" "")
7000         (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7001    (clobber (reg:CC CC_REGNUM))]
7002   "reload_completed"
7003   [(parallel
7004     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7005      (clobber (reg:CC CC_REGNUM))])]
7006   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7007
7008 ;
7009 ; andhi3 instruction pattern(s).
7010 ;
7011
7012 (define_insn "*andhi3_zarch"
7013   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7014         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7015                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQHF,Q")))
7016    (clobber (reg:CC CC_REGNUM))]
7017   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7018   "@
7019    nr\t%0,%2
7020    nrk\t%0,%1,%2
7021    nill\t%0,%x2
7022    #
7023    #"
7024   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7025    (set_attr "cpu_facility" "*,z196,*,*,*")
7026    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7027 ])
7028
7029 (define_insn "*andhi3_esa"
7030   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7031         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7032                 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7033    (clobber (reg:CC CC_REGNUM))]
7034   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7035   "@
7036    nr\t%0,%2
7037    #
7038    #"
7039   [(set_attr "op_type"  "RR,SI,SS")
7040    (set_attr "z10prop" "z10_super_E1,*,*")
7041 ])
7042
7043 (define_split
7044   [(set (match_operand:HI 0 "s_operand" "")
7045         (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7046    (clobber (reg:CC CC_REGNUM))]
7047   "reload_completed"
7048   [(parallel
7049     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7050      (clobber (reg:CC CC_REGNUM))])]
7051   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7052
7053 ;
7054 ; andqi3 instruction pattern(s).
7055 ;
7056
7057 (define_insn "*andqi3_zarch"
7058   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7059         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7060                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7061    (clobber (reg:CC CC_REGNUM))]
7062   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7063   "@
7064    nr\t%0,%2
7065    nrk\t%0,%1,%2
7066    nill\t%0,%b2
7067    ni\t%S0,%b2
7068    niy\t%S0,%b2
7069    #"
7070   [(set_attr "op_type"  "RR,RRF,RI,SI,SIY,SS")
7071    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7072    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7073
7074 (define_insn "*andqi3_esa"
7075   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7076         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7077                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7078    (clobber (reg:CC CC_REGNUM))]
7079   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7080   "@
7081    nr\t%0,%2
7082    ni\t%S0,%b2
7083    #"
7084   [(set_attr "op_type"  "RR,SI,SS")
7085    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7086
7087 ;
7088 ; Block and (NC) patterns.
7089 ;
7090
7091 (define_insn "*nc"
7092   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7093         (and:BLK (match_dup 0)
7094                  (match_operand:BLK 1 "memory_operand" "Q")))
7095    (use (match_operand 2 "const_int_operand" "n"))
7096    (clobber (reg:CC CC_REGNUM))]
7097   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7098   "nc\t%O0(%2,%R0),%S1"
7099   [(set_attr "op_type" "SS")
7100    (set_attr "z196prop" "z196_cracked")])
7101
7102 (define_split
7103   [(set (match_operand 0 "memory_operand" "")
7104         (and (match_dup 0)
7105              (match_operand 1 "memory_operand" "")))
7106    (clobber (reg:CC CC_REGNUM))]
7107   "reload_completed
7108    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7109    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7110   [(parallel
7111     [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7112      (use (match_dup 2))
7113      (clobber (reg:CC CC_REGNUM))])]
7114 {
7115   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7116   operands[0] = adjust_address (operands[0], BLKmode, 0);
7117   operands[1] = adjust_address (operands[1], BLKmode, 0);
7118 })
7119
7120 (define_peephole2
7121   [(parallel
7122     [(set (match_operand:BLK 0 "memory_operand" "")
7123           (and:BLK (match_dup 0)
7124                    (match_operand:BLK 1 "memory_operand" "")))
7125      (use (match_operand 2 "const_int_operand" ""))
7126      (clobber (reg:CC CC_REGNUM))])
7127    (parallel
7128     [(set (match_operand:BLK 3 "memory_operand" "")
7129           (and:BLK (match_dup 3)
7130                    (match_operand:BLK 4 "memory_operand" "")))
7131      (use (match_operand 5 "const_int_operand" ""))
7132      (clobber (reg:CC CC_REGNUM))])]
7133   "s390_offset_p (operands[0], operands[3], operands[2])
7134    && s390_offset_p (operands[1], operands[4], operands[2])
7135    && !s390_overlap_p (operands[0], operands[1],
7136                        INTVAL (operands[2]) + INTVAL (operands[5]))
7137    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7138   [(parallel
7139     [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7140      (use (match_dup 8))
7141      (clobber (reg:CC CC_REGNUM))])]
7142   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7143    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7144    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7145
7146
7147 ;;
7148 ;;- Bit set (inclusive or) instructions.
7149 ;;
7150
7151 (define_expand "ior<mode>3"
7152   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7153         (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7154                  (match_operand:INT 2 "general_operand" "")))
7155    (clobber (reg:CC CC_REGNUM))]
7156   ""
7157   "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7158
7159 ;
7160 ; iordi3 instruction pattern(s).
7161 ;
7162
7163 (define_insn "*iordi3_cc"
7164   [(set (reg CC_REGNUM)
7165         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7166                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7167                  (const_int 0)))
7168    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7169         (ior:DI (match_dup 1) (match_dup 2)))]
7170   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7171   "@
7172    ogr\t%0,%2
7173    ogrk\t%0,%1,%2
7174    og\t%0,%2"
7175   [(set_attr "op_type"  "RRE,RRF,RXY")
7176    (set_attr "cpu_facility" "*,z196,*")
7177    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7178
7179 (define_insn "*iordi3_cconly"
7180   [(set (reg CC_REGNUM)
7181         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7182                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7183                  (const_int 0)))
7184    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7185   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7186   "@
7187    ogr\t%0,%2
7188    ogrk\t%0,%1,%2
7189    og\t%0,%2"
7190   [(set_attr "op_type"  "RRE,RRF,RXY")
7191    (set_attr "cpu_facility" "*,z196,*")
7192    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7193
7194 (define_insn "*iordi3"
7195   [(set (match_operand:DI 0 "nonimmediate_operand"
7196                                "=d,    d,    d,    d,    d,    d,d,d, d,   AQ,Q")
7197         (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7198                             "   %0,    0,    0,    0,    0,    0,0,d, 0,    0,0")
7199                 (match_operand:DI 2 "general_operand"
7200                             "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7201    (clobber (reg:CC CC_REGNUM))]
7202   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7203   "@
7204    oihh\t%0,%i2
7205    oihl\t%0,%i2
7206    oilh\t%0,%i2
7207    oill\t%0,%i2
7208    oihf\t%0,%k2
7209    oilf\t%0,%k2
7210    ogr\t%0,%2
7211    ogrk\t%0,%1,%2
7212    og\t%0,%2
7213    #
7214    #"
7215   [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7216    (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7217    (set_attr "z10prop" "z10_super_E1,
7218                         z10_super_E1,
7219                         z10_super_E1,
7220                         z10_super_E1,
7221                         z10_super_E1,
7222                         z10_super_E1,
7223                         z10_super_E1,
7224                         *,
7225                         z10_super_E1,
7226                         *,
7227                         *")])
7228
7229 (define_split
7230   [(set (match_operand:DI 0 "s_operand" "")
7231         (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7232    (clobber (reg:CC CC_REGNUM))]
7233   "reload_completed"
7234   [(parallel
7235     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7236      (clobber (reg:CC CC_REGNUM))])]
7237   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7238
7239 ;
7240 ; iorsi3 instruction pattern(s).
7241 ;
7242
7243 (define_insn "*iorsi3_cc"
7244   [(set (reg CC_REGNUM)
7245         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7246                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7247                  (const_int 0)))
7248    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7249         (ior:SI (match_dup 1) (match_dup 2)))]
7250   "s390_match_ccmode(insn, CCTmode)"
7251   "@
7252    oilf\t%0,%o2
7253    or\t%0,%2
7254    ork\t%0,%1,%2
7255    o\t%0,%2
7256    oy\t%0,%2"
7257   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7258    (set_attr "cpu_facility" "*,*,z196,*,*")
7259    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7260
7261 (define_insn "*iorsi3_cconly"
7262   [(set (reg CC_REGNUM)
7263         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7264                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7265                  (const_int 0)))
7266    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7267   "s390_match_ccmode(insn, CCTmode)"
7268   "@
7269    oilf\t%0,%o2
7270    or\t%0,%2
7271    ork\t%0,%1,%2
7272    o\t%0,%2
7273    oy\t%0,%2"
7274   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7275    (set_attr "cpu_facility" "*,*,z196,*,*")
7276    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7277
7278 (define_insn "*iorsi3_zarch"
7279   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,    d, d,d,d,d,d,   AQ,Q")
7280         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,    0, 0,0,d,0,0,    0,0")
7281                 (match_operand:SI 2 "general_operand"   "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7282    (clobber (reg:CC CC_REGNUM))]
7283   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7284   "@
7285    oilh\t%0,%i2
7286    oill\t%0,%i2
7287    oilf\t%0,%o2
7288    or\t%0,%2
7289    ork\t%0,%1,%2
7290    o\t%0,%2
7291    oy\t%0,%2
7292    #
7293    #"
7294   [(set_attr "op_type"  "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7295    (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
7296    (set_attr "z10prop" "z10_super_E1,
7297                         z10_super_E1,
7298                         z10_super_E1,
7299                         z10_super_E1,
7300                         *,
7301                         z10_super_E1,
7302                         z10_super_E1,
7303                         *,
7304                         *")])
7305
7306 (define_insn "*iorsi3_esa"
7307   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7308         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7309                 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7310    (clobber (reg:CC CC_REGNUM))]
7311   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7312   "@
7313    or\t%0,%2
7314    o\t%0,%2
7315    #
7316    #"
7317   [(set_attr "op_type"  "RR,RX,SI,SS")
7318    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7319
7320 (define_split
7321   [(set (match_operand:SI 0 "s_operand" "")
7322         (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7323    (clobber (reg:CC CC_REGNUM))]
7324   "reload_completed"
7325   [(parallel
7326     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7327      (clobber (reg:CC CC_REGNUM))])]
7328   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7329
7330 ;
7331 ; iorhi3 instruction pattern(s).
7332 ;
7333
7334 (define_insn "*iorhi3_zarch"
7335   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7336         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7337                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQH0,Q")))
7338    (clobber (reg:CC CC_REGNUM))]
7339   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7340   "@
7341    or\t%0,%2
7342    ork\t%0,%1,%2
7343    oill\t%0,%x2
7344    #
7345    #"
7346   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7347    (set_attr "cpu_facility" "*,z196,*,*,*")
7348    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7349
7350 (define_insn "*iorhi3_esa"
7351   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7352         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7353                 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7354    (clobber (reg:CC CC_REGNUM))]
7355   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7356   "@
7357    or\t%0,%2
7358    #
7359    #"
7360   [(set_attr "op_type"  "RR,SI,SS")
7361    (set_attr "z10prop" "z10_super_E1,*,*")])
7362
7363 (define_split
7364   [(set (match_operand:HI 0 "s_operand" "")
7365         (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7366    (clobber (reg:CC CC_REGNUM))]
7367   "reload_completed"
7368   [(parallel
7369     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7370      (clobber (reg:CC CC_REGNUM))])]
7371   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7372
7373 ;
7374 ; iorqi3 instruction pattern(s).
7375 ;
7376
7377 (define_insn "*iorqi3_zarch"
7378   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7379         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7380                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7381    (clobber (reg:CC CC_REGNUM))]
7382   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7383   "@
7384    or\t%0,%2
7385    ork\t%0,%1,%2
7386    oill\t%0,%b2
7387    oi\t%S0,%b2
7388    oiy\t%S0,%b2
7389    #"
7390   [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7391    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7392    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7393                         z10_super,z10_super,*")])
7394
7395 (define_insn "*iorqi3_esa"
7396   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7397         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7398                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7399    (clobber (reg:CC CC_REGNUM))]
7400   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7401   "@
7402    or\t%0,%2
7403    oi\t%S0,%b2
7404    #"
7405   [(set_attr "op_type"  "RR,SI,SS")
7406    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7407
7408 ;
7409 ; Block inclusive or (OC) patterns.
7410 ;
7411
7412 (define_insn "*oc"
7413   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7414         (ior:BLK (match_dup 0)
7415                  (match_operand:BLK 1 "memory_operand" "Q")))
7416    (use (match_operand 2 "const_int_operand" "n"))
7417    (clobber (reg:CC CC_REGNUM))]
7418   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7419   "oc\t%O0(%2,%R0),%S1"
7420   [(set_attr "op_type" "SS")
7421    (set_attr "z196prop" "z196_cracked")])
7422
7423 (define_split
7424   [(set (match_operand 0 "memory_operand" "")
7425         (ior (match_dup 0)
7426              (match_operand 1 "memory_operand" "")))
7427    (clobber (reg:CC CC_REGNUM))]
7428   "reload_completed
7429    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7430    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7431   [(parallel
7432     [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7433      (use (match_dup 2))
7434      (clobber (reg:CC CC_REGNUM))])]
7435 {
7436   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7437   operands[0] = adjust_address (operands[0], BLKmode, 0);
7438   operands[1] = adjust_address (operands[1], BLKmode, 0);
7439 })
7440
7441 (define_peephole2
7442   [(parallel
7443     [(set (match_operand:BLK 0 "memory_operand" "")
7444           (ior:BLK (match_dup 0)
7445                    (match_operand:BLK 1 "memory_operand" "")))
7446      (use (match_operand 2 "const_int_operand" ""))
7447      (clobber (reg:CC CC_REGNUM))])
7448    (parallel
7449     [(set (match_operand:BLK 3 "memory_operand" "")
7450           (ior:BLK (match_dup 3)
7451                    (match_operand:BLK 4 "memory_operand" "")))
7452      (use (match_operand 5 "const_int_operand" ""))
7453      (clobber (reg:CC CC_REGNUM))])]
7454   "s390_offset_p (operands[0], operands[3], operands[2])
7455    && s390_offset_p (operands[1], operands[4], operands[2])
7456    && !s390_overlap_p (operands[0], operands[1],
7457                        INTVAL (operands[2]) + INTVAL (operands[5]))
7458    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7459   [(parallel
7460     [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7461      (use (match_dup 8))
7462      (clobber (reg:CC CC_REGNUM))])]
7463   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7464    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7465    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7466
7467
7468 ;;
7469 ;;- Xor instructions.
7470 ;;
7471
7472 (define_expand "xor<mode>3"
7473   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7474         (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7475                  (match_operand:INT 2 "general_operand" "")))
7476    (clobber (reg:CC CC_REGNUM))]
7477   ""
7478   "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7479
7480 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7481 ; simplifications.  So its better to have something matching.
7482 (define_split
7483   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7484         (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7485   ""
7486   [(parallel
7487     [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7488      (clobber (reg:CC CC_REGNUM))])]
7489 {
7490   operands[2] = constm1_rtx;
7491   if (!s390_logical_operator_ok_p (operands))
7492     FAIL;
7493 })
7494
7495 ;
7496 ; xordi3 instruction pattern(s).
7497 ;
7498
7499 (define_insn "*xordi3_cc"
7500   [(set (reg CC_REGNUM)
7501         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7502                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7503                  (const_int 0)))
7504    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7505         (xor:DI (match_dup 1) (match_dup 2)))]
7506   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7507   "@
7508    xgr\t%0,%2
7509    xgrk\t%0,%1,%2
7510    xg\t%0,%2"
7511   [(set_attr "op_type" "RRE,RRF,RXY")
7512    (set_attr "cpu_facility" "*,z196,*")
7513    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7514
7515 (define_insn "*xordi3_cconly"
7516   [(set (reg CC_REGNUM)
7517         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7518                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7519                  (const_int 0)))
7520    (clobber (match_scratch:DI 0                                     "=d,d, d"))]
7521   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7522   "@
7523    xgr\t%0,%2
7524    xgrk\t%0,%1,%2
7525    xg\t%0,%2"
7526   [(set_attr "op_type" "RRE,RRF,RXY")
7527    (set_attr "cpu_facility" "*,z196,*")
7528    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7529
7530 (define_insn "*xordi3"
7531   [(set (match_operand:DI 0 "nonimmediate_operand"         "=d,    d,d,d, d,   AQ,Q")
7532         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,    0,0,d, 0,    0,0")
7533                 (match_operand:DI 2 "general_operand"   "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7534    (clobber (reg:CC CC_REGNUM))]
7535   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7536   "@
7537    xihf\t%0,%k2
7538    xilf\t%0,%k2
7539    xgr\t%0,%2
7540    xgrk\t%0,%1,%2
7541    xg\t%0,%2
7542    #
7543    #"
7544   [(set_attr "op_type"  "RIL,RIL,RRE,RRF,RXY,SI,SS")
7545    (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7546    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7547                         *,z10_super_E1,*,*")])
7548
7549 (define_split
7550   [(set (match_operand:DI 0 "s_operand" "")
7551         (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7552    (clobber (reg:CC CC_REGNUM))]
7553   "reload_completed"
7554   [(parallel
7555     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7556      (clobber (reg:CC CC_REGNUM))])]
7557   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7558
7559 ;
7560 ; xorsi3 instruction pattern(s).
7561 ;
7562
7563 (define_insn "*xorsi3_cc"
7564   [(set (reg CC_REGNUM)
7565         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7566                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7567                  (const_int 0)))
7568    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7569         (xor:SI (match_dup 1) (match_dup 2)))]
7570   "s390_match_ccmode(insn, CCTmode)"
7571   "@
7572    xilf\t%0,%o2
7573    xr\t%0,%2
7574    xrk\t%0,%1,%2
7575    x\t%0,%2
7576    xy\t%0,%2"
7577   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7578    (set_attr "cpu_facility" "*,*,z196,*,*")
7579    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7580                         z10_super_E1,z10_super_E1")])
7581
7582 (define_insn "*xorsi3_cconly"
7583   [(set (reg CC_REGNUM)
7584         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7585                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7586                  (const_int 0)))
7587    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7588   "s390_match_ccmode(insn, CCTmode)"
7589   "@
7590    xilf\t%0,%o2
7591    xr\t%0,%2
7592    xrk\t%0,%1,%2
7593    x\t%0,%2
7594    xy\t%0,%2"
7595   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7596    (set_attr "cpu_facility" "*,*,z196,*,*")
7597    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7598                         z10_super_E1,z10_super_E1")])
7599
7600 (define_insn "*xorsi3"
7601   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,d,d,d,   AQ,Q")
7602         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    0,0")
7603                 (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxQS0,Q")))
7604    (clobber (reg:CC CC_REGNUM))]
7605   "s390_logical_operator_ok_p (operands)"
7606   "@
7607    xilf\t%0,%o2
7608    xr\t%0,%2
7609    xrk\t%0,%1,%2
7610    x\t%0,%2
7611    xy\t%0,%2
7612    #
7613    #"
7614   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,SI,SS")
7615    (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7616    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7617                         z10_super_E1,z10_super_E1,*,*")])
7618
7619 (define_split
7620   [(set (match_operand:SI 0 "s_operand" "")
7621         (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7622    (clobber (reg:CC CC_REGNUM))]
7623   "reload_completed"
7624   [(parallel
7625     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7626      (clobber (reg:CC CC_REGNUM))])]
7627   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7628
7629 ;
7630 ; xorhi3 instruction pattern(s).
7631 ;
7632
7633 (define_insn "*xorhi3"
7634   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7635         (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d,    0,0")
7636                 (match_operand:HI 2 "general_operand"      "Os,d,d,NxQH0,Q")))
7637    (clobber (reg:CC CC_REGNUM))]
7638   "s390_logical_operator_ok_p (operands)"
7639   "@
7640    xilf\t%0,%x2
7641    xr\t%0,%2
7642    xrk\t%0,%1,%2
7643    #
7644    #"
7645   [(set_attr "op_type"  "RIL,RR,RRF,SI,SS")
7646    (set_attr "cpu_facility" "*,*,z196,*,*")
7647    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7648
7649 (define_split
7650   [(set (match_operand:HI 0 "s_operand" "")
7651         (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7652    (clobber (reg:CC CC_REGNUM))]
7653   "reload_completed"
7654   [(parallel
7655     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7656      (clobber (reg:CC CC_REGNUM))])]
7657   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7658
7659 ;
7660 ; xorqi3 instruction pattern(s).
7661 ;
7662
7663 (define_insn "*xorqi3"
7664   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7665         (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7666                 (match_operand:QI 2 "general_operand"      "Os,d,d,n,n,Q")))
7667    (clobber (reg:CC CC_REGNUM))]
7668   "s390_logical_operator_ok_p (operands)"
7669   "@
7670    xilf\t%0,%b2
7671    xr\t%0,%2
7672    xrk\t%0,%1,%2
7673    xi\t%S0,%b2
7674    xiy\t%S0,%b2
7675    #"
7676   [(set_attr "op_type"  "RIL,RR,RRF,SI,SIY,SS")
7677    (set_attr "cpu_facility" "*,*,z196,*,*,*")
7678    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7679
7680
7681 ;
7682 ; Block exclusive or (XC) patterns.
7683 ;
7684
7685 (define_insn "*xc"
7686   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7687         (xor:BLK (match_dup 0)
7688                  (match_operand:BLK 1 "memory_operand" "Q")))
7689    (use (match_operand 2 "const_int_operand" "n"))
7690    (clobber (reg:CC CC_REGNUM))]
7691   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7692   "xc\t%O0(%2,%R0),%S1"
7693   [(set_attr "op_type" "SS")])
7694
7695 (define_split
7696   [(set (match_operand 0 "memory_operand" "")
7697         (xor (match_dup 0)
7698              (match_operand 1 "memory_operand" "")))
7699    (clobber (reg:CC CC_REGNUM))]
7700   "reload_completed
7701    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7702    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7703   [(parallel
7704     [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7705      (use (match_dup 2))
7706      (clobber (reg:CC CC_REGNUM))])]
7707 {
7708   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7709   operands[0] = adjust_address (operands[0], BLKmode, 0);
7710   operands[1] = adjust_address (operands[1], BLKmode, 0);
7711 })
7712
7713 (define_peephole2
7714   [(parallel
7715     [(set (match_operand:BLK 0 "memory_operand" "")
7716           (xor:BLK (match_dup 0)
7717                    (match_operand:BLK 1 "memory_operand" "")))
7718      (use (match_operand 2 "const_int_operand" ""))
7719      (clobber (reg:CC CC_REGNUM))])
7720    (parallel
7721     [(set (match_operand:BLK 3 "memory_operand" "")
7722           (xor:BLK (match_dup 3)
7723                    (match_operand:BLK 4 "memory_operand" "")))
7724      (use (match_operand 5 "const_int_operand" ""))
7725      (clobber (reg:CC CC_REGNUM))])]
7726   "s390_offset_p (operands[0], operands[3], operands[2])
7727    && s390_offset_p (operands[1], operands[4], operands[2])
7728    && !s390_overlap_p (operands[0], operands[1],
7729                        INTVAL (operands[2]) + INTVAL (operands[5]))
7730    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7731   [(parallel
7732     [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7733      (use (match_dup 8))
7734      (clobber (reg:CC CC_REGNUM))])]
7735   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7736    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7737    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7738
7739 ;
7740 ; Block xor (XC) patterns with src == dest.
7741 ;
7742
7743 (define_insn "*xc_zero"
7744   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7745         (const_int 0))
7746    (use (match_operand 1 "const_int_operand" "n"))
7747    (clobber (reg:CC CC_REGNUM))]
7748   "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7749   "xc\t%O0(%1,%R0),%S0"
7750   [(set_attr "op_type" "SS")
7751    (set_attr "z196prop" "z196_cracked")])
7752
7753 (define_peephole2
7754   [(parallel
7755     [(set (match_operand:BLK 0 "memory_operand" "")
7756           (const_int 0))
7757      (use (match_operand 1 "const_int_operand" ""))
7758      (clobber (reg:CC CC_REGNUM))])
7759    (parallel
7760     [(set (match_operand:BLK 2 "memory_operand" "")
7761           (const_int 0))
7762      (use (match_operand 3 "const_int_operand" ""))
7763      (clobber (reg:CC CC_REGNUM))])]
7764   "s390_offset_p (operands[0], operands[2], operands[1])
7765    && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7766   [(parallel
7767     [(set (match_dup 4) (const_int 0))
7768      (use (match_dup 5))
7769      (clobber (reg:CC CC_REGNUM))])]
7770   "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7771    operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7772
7773
7774 ;;
7775 ;;- Negate instructions.
7776 ;;
7777
7778 ;
7779 ; neg(di|si)2 instruction pattern(s).
7780 ;
7781
7782 (define_expand "neg<mode>2"
7783   [(parallel
7784     [(set (match_operand:DSI 0 "register_operand" "=d")
7785           (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7786      (clobber (reg:CC CC_REGNUM))])]
7787   ""
7788   "")
7789
7790 (define_insn "*negdi2_sign_cc"
7791   [(set (reg CC_REGNUM)
7792         (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7793                            (match_operand:SI 1 "register_operand" "d") 0)
7794                            (const_int 32)) (const_int 32)))
7795                  (const_int 0)))
7796    (set (match_operand:DI 0 "register_operand" "=d")
7797         (neg:DI (sign_extend:DI (match_dup 1))))]
7798   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7799   "lcgfr\t%0,%1"
7800   [(set_attr "op_type"  "RRE")
7801    (set_attr "z10prop" "z10_c")])
7802
7803 (define_insn "*negdi2_sign"
7804   [(set (match_operand:DI 0 "register_operand" "=d")
7805         (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7806    (clobber (reg:CC CC_REGNUM))]
7807   "TARGET_ZARCH"
7808   "lcgfr\t%0,%1"
7809   [(set_attr "op_type"  "RRE")
7810    (set_attr "z10prop" "z10_c")])
7811
7812 ; lcr, lcgr
7813 (define_insn "*neg<mode>2_cc"
7814   [(set (reg CC_REGNUM)
7815         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7816                  (const_int 0)))
7817    (set (match_operand:GPR 0 "register_operand" "=d")
7818         (neg:GPR (match_dup 1)))]
7819   "s390_match_ccmode (insn, CCAmode)"
7820   "lc<g>r\t%0,%1"
7821   [(set_attr "op_type"  "RR<E>")
7822    (set_attr "z10prop" "z10_super_c_E1")])
7823
7824 ; lcr, lcgr
7825 (define_insn "*neg<mode>2_cconly"
7826   [(set (reg CC_REGNUM)
7827         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7828                  (const_int 0)))
7829    (clobber (match_scratch:GPR 0 "=d"))]
7830   "s390_match_ccmode (insn, CCAmode)"
7831   "lc<g>r\t%0,%1"
7832   [(set_attr "op_type"  "RR<E>")
7833    (set_attr "z10prop" "z10_super_c_E1")])
7834
7835 ; lcr, lcgr
7836 (define_insn "*neg<mode>2"
7837   [(set (match_operand:GPR 0 "register_operand" "=d")
7838         (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7839    (clobber (reg:CC CC_REGNUM))]
7840   ""
7841   "lc<g>r\t%0,%1"
7842   [(set_attr "op_type"  "RR<E>")
7843    (set_attr "z10prop" "z10_super_c_E1")])
7844
7845 (define_insn "*negdi2_31"
7846   [(set (match_operand:DI 0 "register_operand" "=d")
7847         (neg:DI (match_operand:DI 1 "register_operand" "d")))
7848    (clobber (reg:CC CC_REGNUM))]
7849   "!TARGET_ZARCH"
7850   "#")
7851
7852 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7853
7854 ; Doing the twos complement separately on the SImode parts does an
7855 ; unwanted +1 on the high part which needs to be subtracted afterwards
7856 ; ... unless the +1 on the low part created an overflow.
7857
7858 (define_split
7859   [(set (match_operand:DI 0 "register_operand" "")
7860         (neg:DI (match_operand:DI 1 "register_operand" "")))
7861    (clobber (reg:CC CC_REGNUM))]
7862   "!TARGET_ZARCH
7863    && (REGNO (operands[0]) == REGNO (operands[1])
7864       || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7865    && reload_completed"
7866   [(parallel
7867     [(set (match_dup 2) (neg:SI (match_dup 3)))
7868      (clobber (reg:CC CC_REGNUM))])
7869    (parallel
7870     [(set (reg:CCAP CC_REGNUM)
7871           (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7872      (set (match_dup 4) (neg:SI (match_dup 5)))])
7873    (set (pc)
7874         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7875                       (pc)
7876                       (label_ref (match_dup 6))))
7877    (parallel
7878     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7879      (clobber (reg:CC CC_REGNUM))])
7880    (match_dup 6)]
7881   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7882    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7883    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7884    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7885    operands[6] = gen_label_rtx ();")
7886
7887 ; Like above but first make a copy of the low part of the src operand
7888 ; since it might overlap with the high part of the destination.
7889
7890 (define_split
7891   [(set (match_operand:DI 0 "register_operand" "")
7892         (neg:DI (match_operand:DI 1 "register_operand" "")))
7893    (clobber (reg:CC CC_REGNUM))]
7894   "!TARGET_ZARCH
7895    && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7896    && reload_completed"
7897   [; Make a backup of op5 first
7898    (set (match_dup 4) (match_dup 5))
7899    ; Setting op2 here might clobber op5
7900    (parallel
7901     [(set (match_dup 2) (neg:SI (match_dup 3)))
7902      (clobber (reg:CC CC_REGNUM))])
7903    (parallel
7904     [(set (reg:CCAP CC_REGNUM)
7905           (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7906      (set (match_dup 4) (neg:SI (match_dup 4)))])
7907    (set (pc)
7908         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7909                       (pc)
7910                       (label_ref (match_dup 6))))
7911    (parallel
7912     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7913      (clobber (reg:CC CC_REGNUM))])
7914    (match_dup 6)]
7915   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7916    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7917    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7918    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7919    operands[6] = gen_label_rtx ();")
7920
7921 ;
7922 ; neg(df|sf)2 instruction pattern(s).
7923 ;
7924
7925 (define_expand "neg<mode>2"
7926   [(parallel
7927     [(set (match_operand:BFP 0 "register_operand" "=f")
7928           (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7929      (clobber (reg:CC CC_REGNUM))])]
7930   "TARGET_HARD_FLOAT"
7931   "")
7932
7933 ; lcxbr, lcdbr, lcebr
7934 (define_insn "*neg<mode>2_cc"
7935   [(set (reg CC_REGNUM)
7936         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7937                  (match_operand:BFP 2 "const0_operand" "")))
7938    (set (match_operand:BFP 0 "register_operand" "=f")
7939         (neg:BFP (match_dup 1)))]
7940   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7941   "lc<xde>br\t%0,%1"
7942   [(set_attr "op_type"  "RRE")
7943    (set_attr "type"     "fsimp<mode>")])
7944
7945 ; lcxbr, lcdbr, lcebr
7946 (define_insn "*neg<mode>2_cconly"
7947   [(set (reg CC_REGNUM)
7948         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7949                  (match_operand:BFP 2 "const0_operand" "")))
7950    (clobber (match_scratch:BFP 0 "=f"))]
7951   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7952   "lc<xde>br\t%0,%1"
7953   [(set_attr "op_type"  "RRE")
7954    (set_attr "type"     "fsimp<mode>")])
7955
7956 ; lcdfr
7957 (define_insn "*neg<mode>2_nocc"
7958   [(set (match_operand:FP 0 "register_operand"         "=f")
7959         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7960   "TARGET_DFP"
7961   "lcdfr\t%0,%1"
7962   [(set_attr "op_type"  "RRE")
7963    (set_attr "type"     "fsimp<mode>")])
7964
7965 ; lcxbr, lcdbr, lcebr
7966 ; FIXME: wflcdb does not clobber cc
7967 (define_insn "*neg<mode>2"
7968   [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
7969         (neg:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
7970    (clobber (reg:CC CC_REGNUM))]
7971   "TARGET_HARD_FLOAT"
7972   "@
7973    lc<xde>br\t%0,%1
7974    wflcdb\t%0,%1"
7975   [(set_attr "op_type"      "RRE,VRR")
7976    (set_attr "cpu_facility" "*,vec")
7977    (set_attr "type"         "fsimp<mode>,*")])
7978
7979
7980 ;;
7981 ;;- Absolute value instructions.
7982 ;;
7983
7984 ;
7985 ; abs(di|si)2 instruction pattern(s).
7986 ;
7987
7988 (define_insn "*absdi2_sign_cc"
7989   [(set (reg CC_REGNUM)
7990         (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7991                            (match_operand:SI 1 "register_operand" "d") 0)
7992                            (const_int 32)) (const_int 32)))
7993                  (const_int 0)))
7994    (set (match_operand:DI 0 "register_operand" "=d")
7995         (abs:DI (sign_extend:DI (match_dup 1))))]
7996   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7997   "lpgfr\t%0,%1"
7998   [(set_attr "op_type"  "RRE")
7999    (set_attr "z10prop" "z10_c")])
8000
8001 (define_insn "*absdi2_sign"
8002   [(set (match_operand:DI 0 "register_operand" "=d")
8003         (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8004    (clobber (reg:CC CC_REGNUM))]
8005   "TARGET_ZARCH"
8006   "lpgfr\t%0,%1"
8007   [(set_attr "op_type"  "RRE")
8008    (set_attr "z10prop" "z10_c")])
8009
8010 ; lpr, lpgr
8011 (define_insn "*abs<mode>2_cc"
8012   [(set (reg CC_REGNUM)
8013         (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8014                  (const_int 0)))
8015    (set (match_operand:GPR 0 "register_operand" "=d")
8016         (abs:GPR (match_dup 1)))]
8017   "s390_match_ccmode (insn, CCAmode)"
8018   "lp<g>r\t%0,%1"
8019   [(set_attr "op_type"  "RR<E>")
8020    (set_attr "z10prop" "z10_c")])
8021
8022 ; lpr, lpgr
8023 (define_insn "*abs<mode>2_cconly"
8024   [(set (reg CC_REGNUM)
8025         (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8026                  (const_int 0)))
8027    (clobber (match_scratch:GPR 0 "=d"))]
8028   "s390_match_ccmode (insn, CCAmode)"
8029   "lp<g>r\t%0,%1"
8030   [(set_attr "op_type"  "RR<E>")
8031    (set_attr "z10prop" "z10_c")])
8032
8033 ; lpr, lpgr
8034 (define_insn "abs<mode>2"
8035   [(set (match_operand:GPR 0 "register_operand" "=d")
8036         (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8037    (clobber (reg:CC CC_REGNUM))]
8038   ""
8039   "lp<g>r\t%0,%1"
8040   [(set_attr "op_type"  "RR<E>")
8041    (set_attr "z10prop" "z10_c")])
8042
8043 ;
8044 ; abs(df|sf)2 instruction pattern(s).
8045 ;
8046
8047 (define_expand "abs<mode>2"
8048   [(parallel
8049     [(set (match_operand:BFP 0 "register_operand" "=f")
8050           (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8051      (clobber (reg:CC CC_REGNUM))])]
8052   "TARGET_HARD_FLOAT"
8053   "")
8054
8055 ; lpxbr, lpdbr, lpebr
8056 (define_insn "*abs<mode>2_cc"
8057   [(set (reg CC_REGNUM)
8058         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8059                  (match_operand:BFP 2 "const0_operand" "")))
8060    (set (match_operand:BFP 0 "register_operand" "=f")
8061         (abs:BFP (match_dup 1)))]
8062   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8063   "lp<xde>br\t%0,%1"
8064   [(set_attr "op_type"  "RRE")
8065    (set_attr "type"     "fsimp<mode>")])
8066
8067 ; lpxbr, lpdbr, lpebr
8068 (define_insn "*abs<mode>2_cconly"
8069   [(set (reg CC_REGNUM)
8070         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8071                  (match_operand:BFP 2 "const0_operand" "")))
8072    (clobber (match_scratch:BFP 0 "=f"))]
8073   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8074   "lp<xde>br\t%0,%1"
8075   [(set_attr "op_type"  "RRE")
8076    (set_attr "type"     "fsimp<mode>")])
8077
8078 ; lpdfr
8079 (define_insn "*abs<mode>2_nocc"
8080   [(set (match_operand:FP 0 "register_operand"         "=f")
8081         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8082   "TARGET_DFP"
8083   "lpdfr\t%0,%1"
8084   [(set_attr "op_type"  "RRE")
8085    (set_attr "type"     "fsimp<mode>")])
8086
8087 ; lpxbr, lpdbr, lpebr
8088 ; FIXME: wflpdb does not clobber cc
8089 (define_insn "*abs<mode>2"
8090   [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
8091         (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
8092    (clobber (reg:CC CC_REGNUM))]
8093   "TARGET_HARD_FLOAT"
8094   "@
8095     lp<xde>br\t%0,%1
8096     wflpdb\t%0,%1"
8097   [(set_attr "op_type"      "RRE,VRR")
8098    (set_attr "cpu_facility" "*,vec")
8099    (set_attr "type"         "fsimp<mode>,*")])
8100
8101
8102 ;;
8103 ;;- Negated absolute value instructions
8104 ;;
8105
8106 ;
8107 ; Integer
8108 ;
8109
8110 (define_insn "*negabsdi2_sign_cc"
8111   [(set (reg CC_REGNUM)
8112         (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8113                            (match_operand:SI 1 "register_operand" "d") 0)
8114                            (const_int 32)) (const_int 32))))
8115                  (const_int 0)))
8116    (set (match_operand:DI 0 "register_operand" "=d")
8117         (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8118   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8119   "lngfr\t%0,%1"
8120   [(set_attr "op_type"  "RRE")
8121    (set_attr "z10prop" "z10_c")])
8122
8123 (define_insn "*negabsdi2_sign"
8124   [(set (match_operand:DI 0 "register_operand" "=d")
8125         (neg:DI (abs:DI (sign_extend:DI
8126                           (match_operand:SI 1 "register_operand" "d")))))
8127    (clobber (reg:CC CC_REGNUM))]
8128   "TARGET_ZARCH"
8129   "lngfr\t%0,%1"
8130   [(set_attr "op_type" "RRE")
8131    (set_attr "z10prop" "z10_c")])
8132
8133 ; lnr, lngr
8134 (define_insn "*negabs<mode>2_cc"
8135   [(set (reg CC_REGNUM)
8136         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8137                  (const_int 0)))
8138    (set (match_operand:GPR 0 "register_operand" "=d")
8139         (neg:GPR (abs:GPR (match_dup 1))))]
8140   "s390_match_ccmode (insn, CCAmode)"
8141   "ln<g>r\t%0,%1"
8142   [(set_attr "op_type"  "RR<E>")
8143    (set_attr "z10prop" "z10_c")])
8144
8145 ; lnr, lngr
8146 (define_insn "*negabs<mode>2_cconly"
8147   [(set (reg CC_REGNUM)
8148         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8149                  (const_int 0)))
8150    (clobber (match_scratch:GPR 0 "=d"))]
8151   "s390_match_ccmode (insn, CCAmode)"
8152   "ln<g>r\t%0,%1"
8153   [(set_attr "op_type"  "RR<E>")
8154    (set_attr "z10prop" "z10_c")])
8155
8156 ; lnr, lngr
8157 (define_insn "*negabs<mode>2"
8158   [(set (match_operand:GPR 0 "register_operand" "=d")
8159         (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8160    (clobber (reg:CC CC_REGNUM))]
8161   ""
8162   "ln<g>r\t%0,%1"
8163   [(set_attr "op_type" "RR<E>")
8164    (set_attr "z10prop" "z10_c")])
8165
8166 ;
8167 ; Floating point
8168 ;
8169
8170 ; lnxbr, lndbr, lnebr
8171 (define_insn "*negabs<mode>2_cc"
8172   [(set (reg CC_REGNUM)
8173         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8174                  (match_operand:BFP 2 "const0_operand" "")))
8175    (set (match_operand:BFP 0 "register_operand" "=f")
8176         (neg:BFP (abs:BFP (match_dup 1))))]
8177   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8178   "ln<xde>br\t%0,%1"
8179   [(set_attr "op_type"  "RRE")
8180    (set_attr "type"     "fsimp<mode>")])
8181
8182 ; lnxbr, lndbr, lnebr
8183 (define_insn "*negabs<mode>2_cconly"
8184   [(set (reg CC_REGNUM)
8185         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8186                  (match_operand:BFP 2 "const0_operand" "")))
8187    (clobber (match_scratch:BFP 0 "=f"))]
8188   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8189   "ln<xde>br\t%0,%1"
8190   [(set_attr "op_type"  "RRE")
8191    (set_attr "type"     "fsimp<mode>")])
8192
8193 ; lndfr
8194 (define_insn "*negabs<mode>2_nocc"
8195   [(set (match_operand:FP 0 "register_operand"                  "=f")
8196         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8197   "TARGET_DFP"
8198   "lndfr\t%0,%1"
8199   [(set_attr "op_type"  "RRE")
8200    (set_attr "type"     "fsimp<mode>")])
8201
8202 ; lnxbr, lndbr, lnebr
8203 ; FIXME: wflndb does not clobber cc
8204 (define_insn "*negabs<mode>2"
8205   [(set (match_operand:BFP                   0 "register_operand" "=f,<vf>")
8206         (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>"))))
8207    (clobber (reg:CC CC_REGNUM))]
8208   "TARGET_HARD_FLOAT"
8209   "@
8210    ln<xde>br\t%0,%1
8211    wflndb\t%0,%1"
8212   [(set_attr "op_type"      "RRE,VRR")
8213    (set_attr "cpu_facility" "*,vec")
8214    (set_attr "type"         "fsimp<mode>,*")])
8215
8216 ;;
8217 ;;- Square root instructions.
8218 ;;
8219
8220 ;
8221 ; sqrt(df|sf)2 instruction pattern(s).
8222 ;
8223
8224 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8225 (define_insn "sqrt<mode>2"
8226   [(set (match_operand:BFP           0 "register_operand" "=f,   f,<vf>")
8227         (sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,<Rf>,<vf>")))]
8228   "TARGET_HARD_FLOAT"
8229   "@
8230    sq<xde>br\t%0,%1
8231    sq<xde>b\t%0,%1
8232    wfsqdb\t%v0,%v1"
8233   [(set_attr "op_type"      "RRE,RXE,VRR")
8234    (set_attr "type"         "fsqrt<mode>")
8235    (set_attr "cpu_facility" "*,*,vec")])
8236
8237
8238 ;;
8239 ;;- One complement instructions.
8240 ;;
8241
8242 ;
8243 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8244 ;
8245
8246 (define_expand "one_cmpl<mode>2"
8247   [(parallel
8248     [(set (match_operand:INT 0 "register_operand" "")
8249           (xor:INT (match_operand:INT 1 "register_operand" "")
8250                    (const_int -1)))
8251      (clobber (reg:CC CC_REGNUM))])]
8252   ""
8253   "")
8254
8255
8256 ;;
8257 ;; Find leftmost bit instructions.
8258 ;;
8259
8260 (define_expand "clzdi2"
8261   [(set (match_operand:DI 0 "register_operand" "=d")
8262         (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8263   "TARGET_EXTIMM && TARGET_ZARCH"
8264 {
8265   rtx insn, clz_equal;
8266   rtx wide_reg = gen_reg_rtx (TImode);
8267   rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8268
8269   clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8270
8271   emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8272
8273   insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8274   set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8275
8276   DONE;
8277 })
8278
8279 (define_insn "clztidi2"
8280   [(set (match_operand:TI 0 "register_operand" "=d")
8281         (ior:TI
8282           (ashift:TI
8283             (zero_extend:TI
8284               (xor:DI (match_operand:DI 1 "register_operand" "d")
8285                       (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8286                                 (subreg:SI (clz:DI (match_dup 1)) 4))))
8287
8288             (const_int 64))
8289           (zero_extend:TI (clz:DI (match_dup 1)))))
8290    (clobber (reg:CC CC_REGNUM))]
8291   "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8292    == (unsigned HOST_WIDE_INT) 1 << 63
8293    && TARGET_EXTIMM && TARGET_ZARCH"
8294   "flogr\t%0,%1"
8295   [(set_attr "op_type"  "RRE")])
8296
8297
8298 ;;
8299 ;;- Rotate instructions.
8300 ;;
8301
8302 ;
8303 ; rotl(di|si)3 instruction pattern(s).
8304 ;
8305
8306 ; rll, rllg
8307 (define_insn "rotl<mode>3"
8308   [(set (match_operand:GPR 0 "register_operand" "=d")
8309         (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8310                     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8311   "TARGET_CPU_ZARCH"
8312   "rll<g>\t%0,%1,%Y2"
8313   [(set_attr "op_type"  "RSE")
8314    (set_attr "atype"    "reg")
8315    (set_attr "z10prop" "z10_super_E1")])
8316
8317 ; rll, rllg
8318 (define_insn "*rotl<mode>3_and"
8319   [(set (match_operand:GPR 0 "register_operand" "=d")
8320         (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8321                     (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8322                             (match_operand:SI 3 "const_int_operand"   "n"))))]
8323   "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8324   "rll<g>\t%0,%1,%Y2"
8325   [(set_attr "op_type"  "RSE")
8326    (set_attr "atype"    "reg")
8327    (set_attr "z10prop" "z10_super_E1")])
8328
8329
8330 ;;
8331 ;;- Shift instructions.
8332 ;;
8333
8334 ;
8335 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8336 ; Left shifts and logical right shifts
8337
8338 (define_expand "<shift><mode>3"
8339   [(set (match_operand:DSI 0 "register_operand" "")
8340         (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8341                    (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
8342   ""
8343   "")
8344
8345 ; sldl, srdl
8346 (define_insn "*<shift>di3_31"
8347   [(set (match_operand:DI 0 "register_operand" "=d")
8348         (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8349                   (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8350   "!TARGET_ZARCH"
8351   "s<lr>dl\t%0,%Y2"
8352   [(set_attr "op_type"  "RS")
8353    (set_attr "atype"    "reg")
8354    (set_attr "z196prop" "z196_cracked")])
8355
8356 ; sll, srl, sllg, srlg, sllk, srlk
8357 (define_insn "*<shift><mode>3"
8358   [(set (match_operand:GPR 0 "register_operand"                          "=d,d")
8359         (SHIFT:GPR (match_operand:GPR 1 "register_operand"             "<d0>,d")
8360                    (match_operand:SI 2 "shift_count_or_setmem_operand"    "Y,Y")))]
8361   ""
8362   "@
8363    s<lr>l<g>\t%0,<1>%Y2
8364    s<lr>l<gk>\t%0,%1,%Y2"
8365   [(set_attr "op_type"  "RS<E>,RSY")
8366    (set_attr "atype"    "reg,reg")
8367    (set_attr "cpu_facility" "*,z196")
8368    (set_attr "z10prop" "z10_super_E1,*")])
8369
8370 ; sldl, srdl
8371 (define_insn "*<shift>di3_31_and"
8372   [(set (match_operand:DI 0 "register_operand" "=d")
8373         (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8374                   (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8375                           (match_operand:SI 3 "const_int_operand"   "n"))))]
8376   "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8377   "s<lr>dl\t%0,%Y2"
8378   [(set_attr "op_type"  "RS")
8379    (set_attr "atype"    "reg")])
8380
8381 ; sll, srl, sllg, srlg, sllk, srlk
8382 (define_insn "*<shift><mode>3_and"
8383   [(set (match_operand:GPR 0 "register_operand"                                 "=d,d")
8384         (SHIFT:GPR (match_operand:GPR 1 "register_operand"                    "<d0>,d")
8385                    (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand"   "Y,Y")
8386                            (match_operand:SI 3 "const_int_operand"               "n,n"))))]
8387   "(INTVAL (operands[3]) & 63) == 63"
8388   "@
8389    s<lr>l<g>\t%0,<1>%Y2
8390    s<lr>l<gk>\t%0,%1,%Y2"
8391   [(set_attr "op_type"  "RS<E>,RSY")
8392    (set_attr "atype"    "reg,reg")
8393    (set_attr "cpu_facility" "*,z196")
8394    (set_attr "z10prop" "z10_super_E1,*")])
8395
8396 ;
8397 ; ashr(di|si)3 instruction pattern(s).
8398 ; Arithmetic right shifts
8399
8400 (define_expand "ashr<mode>3"
8401   [(parallel
8402     [(set (match_operand:DSI 0 "register_operand" "")
8403           (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8404                         (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
8405      (clobber (reg:CC CC_REGNUM))])]
8406   ""
8407   "")
8408
8409 (define_insn "*ashrdi3_cc_31"
8410   [(set (reg CC_REGNUM)
8411         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8412                               (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8413                  (const_int 0)))
8414    (set (match_operand:DI 0 "register_operand" "=d")
8415         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8416   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8417   "srda\t%0,%Y2"
8418   [(set_attr "op_type"  "RS")
8419    (set_attr "atype"    "reg")])
8420
8421 (define_insn "*ashrdi3_cconly_31"
8422   [(set (reg CC_REGNUM)
8423         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8424                               (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8425                  (const_int 0)))
8426    (clobber (match_scratch:DI 0 "=d"))]
8427   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8428   "srda\t%0,%Y2"
8429   [(set_attr "op_type"  "RS")
8430    (set_attr "atype"    "reg")])
8431
8432 (define_insn "*ashrdi3_31"
8433   [(set (match_operand:DI 0 "register_operand" "=d")
8434         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8435                      (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
8436    (clobber (reg:CC CC_REGNUM))]
8437   "!TARGET_ZARCH"
8438   "srda\t%0,%Y2"
8439   [(set_attr "op_type"  "RS")
8440    (set_attr "atype"    "reg")])
8441
8442 ; sra, srag, srak
8443 (define_insn "*ashr<mode>3_cc"
8444   [(set (reg CC_REGNUM)
8445         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8446                                (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8447                  (const_int 0)))
8448    (set (match_operand:GPR 0 "register_operand"                                   "=d,d")
8449         (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
8450   "s390_match_ccmode(insn, CCSmode)"
8451   "@
8452    sra<g>\t%0,<1>%Y2
8453    sra<gk>\t%0,%1,%Y2"
8454   [(set_attr "op_type"  "RS<E>,RSY")
8455    (set_attr "atype"    "reg,reg")
8456    (set_attr "cpu_facility" "*,z196")
8457    (set_attr "z10prop" "z10_super_E1,*")])
8458
8459 ; sra, srag, srak
8460 (define_insn "*ashr<mode>3_cconly"
8461   [(set (reg CC_REGNUM)
8462         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8463                                (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8464                  (const_int 0)))
8465    (clobber (match_scratch:GPR 0                                                  "=d,d"))]
8466   "s390_match_ccmode(insn, CCSmode)"
8467   "@
8468    sra<g>\t%0,<1>%Y2
8469    sra<gk>\t%0,%1,%Y2"
8470   [(set_attr "op_type"  "RS<E>,RSY")
8471    (set_attr "atype"    "reg,reg")
8472    (set_attr "cpu_facility" "*,z196")
8473    (set_attr "z10prop" "z10_super_E1,*")])
8474
8475 ; sra, srag
8476 (define_insn "*ashr<mode>3"
8477   [(set (match_operand:GPR 0 "register_operand"                          "=d,d")
8478         (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8479                       (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8480    (clobber (reg:CC CC_REGNUM))]
8481   ""
8482   "@
8483    sra<g>\t%0,<1>%Y2
8484    sra<gk>\t%0,%1,%Y2"
8485   [(set_attr "op_type"  "RS<E>,RSY")
8486    (set_attr "atype"    "reg,reg")
8487    (set_attr "cpu_facility" "*,z196")
8488    (set_attr "z10prop" "z10_super_E1,*")])
8489
8490
8491 ; shift pattern with implicit ANDs
8492
8493 (define_insn "*ashrdi3_cc_31_and"
8494   [(set (reg CC_REGNUM)
8495         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8496                               (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8497                                       (match_operand:SI 3 "const_int_operand"   "n")))
8498                  (const_int 0)))
8499    (set (match_operand:DI 0 "register_operand" "=d")
8500         (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8501   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8502    && (INTVAL (operands[3]) & 63) == 63"
8503   "srda\t%0,%Y2"
8504   [(set_attr "op_type"  "RS")
8505    (set_attr "atype"    "reg")])
8506
8507 (define_insn "*ashrdi3_cconly_31_and"
8508   [(set (reg CC_REGNUM)
8509         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8510                               (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8511                                       (match_operand:SI 3 "const_int_operand"   "n")))
8512                  (const_int 0)))
8513    (clobber (match_scratch:DI 0 "=d"))]
8514   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8515    && (INTVAL (operands[3]) & 63) == 63"
8516   "srda\t%0,%Y2"
8517   [(set_attr "op_type"  "RS")
8518    (set_attr "atype"    "reg")])
8519
8520 (define_insn "*ashrdi3_31_and"
8521   [(set (match_operand:DI 0 "register_operand" "=d")
8522         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8523                      (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8524                              (match_operand:SI 3 "const_int_operand"   "n"))))
8525    (clobber (reg:CC CC_REGNUM))]
8526   "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8527   "srda\t%0,%Y2"
8528   [(set_attr "op_type"  "RS")
8529    (set_attr "atype"    "reg")])
8530
8531 ; sra, srag, srak
8532 (define_insn "*ashr<mode>3_cc_and"
8533   [(set (reg CC_REGNUM)
8534         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8535                                (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8536                                        (match_operand:SI 3 "const_int_operand"             "n,n")))
8537                  (const_int 0)))
8538    (set (match_operand:GPR 0 "register_operand"                                           "=d,d")
8539         (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8540   "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8541   "@
8542    sra<g>\t%0,<1>%Y2
8543    sra<gk>\t%0,%1,%Y2"
8544   [(set_attr "op_type"  "RS<E>,RSY")
8545    (set_attr "atype"    "reg,reg")
8546    (set_attr "cpu_facility" "*,z196")
8547    (set_attr "z10prop" "z10_super_E1,*")])
8548
8549 ; sra, srag, srak
8550 (define_insn "*ashr<mode>3_cconly_and"
8551   [(set (reg CC_REGNUM)
8552         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8553                                (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8554                                        (match_operand:SI 3 "const_int_operand"             "n,n")))
8555                  (const_int 0)))
8556    (clobber (match_scratch:GPR 0                                                          "=d,d"))]
8557   "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8558   "@
8559    sra<g>\t%0,<1>%Y2
8560    sra<gk>\t%0,%1,%Y2"
8561   [(set_attr "op_type"  "RS<E>,RSY")
8562    (set_attr "atype"    "reg,reg")
8563    (set_attr "cpu_facility" "*,z196")
8564    (set_attr "z10prop" "z10_super_E1,*")])
8565
8566 ; sra, srag, srak
8567 (define_insn "*ashr<mode>3_and"
8568   [(set (match_operand:GPR 0 "register_operand"                                  "=d,d")
8569         (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8570                       (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8571                               (match_operand:SI 3 "const_int_operand"             "n,n"))))
8572    (clobber (reg:CC CC_REGNUM))]
8573   "(INTVAL (operands[3]) & 63) == 63"
8574   "@
8575    sra<g>\t%0,<1>%Y2
8576    sra<gk>\t%0,%1,%Y2"
8577   [(set_attr "op_type"  "RS<E>,RSY")
8578    (set_attr "atype"    "reg,reg")
8579    (set_attr "cpu_facility" "*,z196")
8580    (set_attr "z10prop" "z10_super_E1,*")])
8581
8582
8583 ;;
8584 ;; Branch instruction patterns.
8585 ;;
8586
8587 (define_expand "cbranch<mode>4"
8588   [(set (pc)
8589         (if_then_else (match_operator 0 "comparison_operator"
8590                        [(match_operand:GPR 1 "register_operand" "")
8591                         (match_operand:GPR 2 "general_operand" "")])
8592                       (label_ref (match_operand 3 "" ""))
8593                       (pc)))]
8594   ""
8595   "s390_emit_jump (operands[3],
8596     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8597    DONE;")
8598
8599 (define_expand "cbranch<mode>4"
8600   [(set (pc)
8601         (if_then_else (match_operator 0 "comparison_operator"
8602                        [(match_operand:FP 1 "register_operand" "")
8603                         (match_operand:FP 2 "general_operand" "")])
8604                       (label_ref (match_operand 3 "" ""))
8605                       (pc)))]
8606   "TARGET_HARD_FLOAT"
8607   "s390_emit_jump (operands[3],
8608     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8609    DONE;")
8610
8611 (define_expand "cbranchcc4"
8612   [(set (pc)
8613         (if_then_else (match_operator 0 "s390_comparison"
8614                        [(match_operand 1 "cc_reg_operand" "")
8615                         (match_operand 2 "const_int_operand" "")])
8616                       (label_ref (match_operand 3 "" ""))
8617                       (pc)))]
8618   ""
8619   "")
8620
8621
8622 ;;
8623 ;;- Conditional jump instructions.
8624 ;;
8625
8626 (define_insn "*cjump_64"
8627   [(set (pc)
8628         (if_then_else
8629           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8630                                                (match_operand 2 "const_int_operand" "")])
8631           (label_ref (match_operand 0 "" ""))
8632           (pc)))]
8633   "TARGET_CPU_ZARCH"
8634 {
8635   if (get_attr_length (insn) == 4)
8636     return "j%C1\t%l0";
8637   else
8638     return "jg%C1\t%l0";
8639 }
8640   [(set_attr "op_type" "RI")
8641    (set_attr "type"    "branch")
8642    (set (attr "length")
8643         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8644                       (const_int 4) (const_int 6)))])
8645
8646 (define_insn "*cjump_31"
8647   [(set (pc)
8648         (if_then_else
8649           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8650                                                (match_operand 2 "const_int_operand" "")])
8651           (label_ref (match_operand 0 "" ""))
8652           (pc)))]
8653   "!TARGET_CPU_ZARCH"
8654 {
8655   gcc_assert (get_attr_length (insn) == 4);
8656   return "j%C1\t%l0";
8657 }
8658   [(set_attr "op_type" "RI")
8659    (set_attr "type"    "branch")
8660    (set (attr "length")
8661         (if_then_else (not (match_test "flag_pic"))
8662           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8663                         (const_int 4) (const_int 6))
8664           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8665                         (const_int 4) (const_int 8))))])
8666
8667 (define_insn "*cjump_long"
8668   [(set (pc)
8669         (if_then_else
8670           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8671           (match_operand 0 "address_operand" "ZQZR")
8672           (pc)))]
8673   ""
8674 {
8675   if (get_attr_op_type (insn) == OP_TYPE_RR)
8676     return "b%C1r\t%0";
8677   else
8678     return "b%C1\t%a0";
8679 }
8680   [(set (attr "op_type")
8681         (if_then_else (match_operand 0 "register_operand" "")
8682                       (const_string "RR") (const_string "RX")))
8683    (set_attr "type"  "branch")
8684    (set_attr "atype" "agen")])
8685
8686 ;; A conditional return instruction.
8687 (define_insn "*c<code>"
8688   [(set (pc)
8689         (if_then_else
8690           (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8691           (ANY_RETURN)
8692           (pc)))]
8693   "s390_can_use_<code>_insn ()"
8694   "b%C0r\t%%r14"
8695   [(set_attr "op_type" "RR")
8696    (set_attr "type"  "jsr")
8697    (set_attr "atype" "agen")])
8698
8699 ;;
8700 ;;- Negated conditional jump instructions.
8701 ;;
8702
8703 (define_insn "*icjump_64"
8704   [(set (pc)
8705         (if_then_else
8706           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8707           (pc)
8708           (label_ref (match_operand 0 "" ""))))]
8709   "TARGET_CPU_ZARCH"
8710 {
8711   if (get_attr_length (insn) == 4)
8712     return "j%D1\t%l0";
8713   else
8714     return "jg%D1\t%l0";
8715 }
8716   [(set_attr "op_type" "RI")
8717    (set_attr "type"    "branch")
8718    (set (attr "length")
8719         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8720                       (const_int 4) (const_int 6)))])
8721
8722 (define_insn "*icjump_31"
8723   [(set (pc)
8724         (if_then_else
8725           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8726           (pc)
8727           (label_ref (match_operand 0 "" ""))))]
8728   "!TARGET_CPU_ZARCH"
8729 {
8730   gcc_assert (get_attr_length (insn) == 4);
8731   return "j%D1\t%l0";
8732 }
8733   [(set_attr "op_type" "RI")
8734    (set_attr "type"    "branch")
8735    (set (attr "length")
8736         (if_then_else (not (match_test "flag_pic"))
8737           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8738                         (const_int 4) (const_int 6))
8739           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8740                         (const_int 4) (const_int 8))))])
8741
8742 (define_insn "*icjump_long"
8743   [(set (pc)
8744         (if_then_else
8745           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8746           (pc)
8747           (match_operand 0 "address_operand" "ZQZR")))]
8748   ""
8749 {
8750   if (get_attr_op_type (insn) == OP_TYPE_RR)
8751     return "b%D1r\t%0";
8752   else
8753     return "b%D1\t%a0";
8754 }
8755   [(set (attr "op_type")
8756         (if_then_else (match_operand 0 "register_operand" "")
8757                       (const_string "RR") (const_string "RX")))
8758    (set_attr "type"  "branch")
8759    (set_attr "atype" "agen")])
8760
8761 ;;
8762 ;;- Trap instructions.
8763 ;;
8764
8765 (define_insn "trap"
8766   [(trap_if (const_int 1) (const_int 0))]
8767   ""
8768   "j\t.+2"
8769   [(set_attr "op_type" "RI")
8770    (set_attr "type"  "branch")])
8771
8772 (define_expand "ctrap<mode>4"
8773   [(trap_if (match_operator 0 "comparison_operator"
8774              [(match_operand:GPR 1 "register_operand" "")
8775               (match_operand:GPR 2 "general_operand" "")])
8776              (match_operand 3 "const0_operand" ""))]
8777   ""
8778   {
8779     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8780                                   operands[1], operands[2]);
8781     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8782     DONE;
8783   })
8784
8785 (define_expand "ctrap<mode>4"
8786   [(trap_if (match_operator 0 "comparison_operator"
8787              [(match_operand:FP 1 "register_operand" "")
8788               (match_operand:FP 2 "general_operand" "")])
8789              (match_operand 3 "const0_operand" ""))]
8790   ""
8791   {
8792     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8793                                   operands[1], operands[2]);
8794     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8795     DONE;
8796   })
8797
8798 (define_insn "condtrap"
8799   [(trap_if (match_operator 0 "s390_comparison"
8800              [(match_operand 1 "cc_reg_operand" "c")
8801               (const_int 0)])
8802             (const_int 0))]
8803   ""
8804   "j%C0\t.+2";
8805   [(set_attr "op_type" "RI")
8806    (set_attr "type"  "branch")])
8807
8808 ; crt, cgrt, cit, cgit
8809 (define_insn "*cmp_and_trap_signed_int<mode>"
8810   [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8811                [(match_operand:GPR 1 "register_operand"  "d,d")
8812                 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8813             (const_int 0))]
8814   "TARGET_Z10"
8815   "@
8816    c<g>rt%C0\t%1,%2
8817    c<g>it%C0\t%1,%h2"
8818   [(set_attr "op_type" "RRF,RIE")
8819    (set_attr "type"    "branch")
8820    (set_attr "z10prop" "z10_super_c,z10_super")])
8821
8822 ; clrt, clgrt, clfit, clgit, clt, clgt
8823 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8824   [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8825                [(match_operand:GPR 1 "register_operand" "d,d, d")
8826                 (match_operand:GPR 2 "general_operand"  "d,D,RT")])
8827             (const_int 0))]
8828   "TARGET_Z10"
8829   "@
8830    cl<g>rt%C0\t%1,%2
8831    cl<gf>it%C0\t%1,%x2
8832    cl<g>t%C0\t%1,%2"
8833   [(set_attr "op_type"      "RRF,RIE,RSY")
8834    (set_attr "type"         "branch")
8835    (set_attr "z10prop"      "z10_super_c,z10_super,*")
8836    (set_attr "cpu_facility" "z10,z10,zEC12")])
8837
8838 ; lat, lgat
8839 (define_insn "*load_and_trap<mode>"
8840   [(trap_if (eq (match_operand:GPR 0 "memory_operand"  "RT")
8841                 (const_int 0))
8842             (const_int 0))
8843    (set (match_operand:GPR 1 "register_operand" "=d")
8844         (match_dup 0))]
8845   "TARGET_ZEC12"
8846   "l<g>at\t%1,%0"
8847   [(set_attr "op_type" "RXY")])
8848
8849
8850 ;;
8851 ;;- Loop instructions.
8852 ;;
8853 ;;  This is all complicated by the fact that since this is a jump insn
8854 ;;  we must handle our own output reloads.
8855
8856 ;; branch on index
8857
8858 ; This splitter will be matched by combine and has to add the 2 moves
8859 ; necessary to load the compare and the increment values into a
8860 ; register pair as needed by brxle.
8861
8862 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8863   [(set (pc)
8864         (if_then_else
8865          (match_operator 6 "s390_brx_operator"
8866             [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8867                        (match_operand:GPR 2 "general_operand"  ""))
8868              (match_operand:GPR 3 "register_operand" "")])
8869          (label_ref (match_operand 0 "" ""))
8870          (pc)))
8871    (set (match_operand:GPR 4 "nonimmediate_operand" "")
8872         (plus:GPR (match_dup 1) (match_dup 2)))
8873    (clobber (match_scratch:GPR 5 ""))]
8874   "TARGET_CPU_ZARCH"
8875   "#"
8876   "!reload_completed && !reload_in_progress"
8877   [(set (match_dup 7) (match_dup 2)) ; the increment
8878    (set (match_dup 8) (match_dup 3)) ; the comparison value
8879    (parallel [(set (pc)
8880                    (if_then_else
8881                     (match_op_dup 6
8882                        [(plus:GPR (match_dup 1) (match_dup 7))
8883                         (match_dup 8)])
8884                     (label_ref (match_dup 0))
8885                     (pc)))
8886               (set (match_dup 4)
8887                    (plus:GPR (match_dup 1) (match_dup 7)))
8888               (clobber (match_dup 5))
8889               (clobber (reg:CC CC_REGNUM))])]
8890   {
8891     rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8892     operands[7] = gen_lowpart (<GPR:MODE>mode,
8893                                gen_highpart (word_mode, dreg));
8894     operands[8] = gen_lowpart (<GPR:MODE>mode,
8895                                gen_lowpart (word_mode, dreg));
8896   })
8897
8898 ; brxlg, brxhg
8899
8900 (define_insn_and_split "*brxg_64bit"
8901   [(set (pc)
8902         (if_then_else
8903           (match_operator 5 "s390_brx_operator"
8904              [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8905                        (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8906               (subreg:DI (match_dup 2) 8)])
8907           (label_ref (match_operand 0 "" ""))
8908           (pc)))
8909    (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8910         (plus:DI (match_dup 1)
8911                  (subreg:DI (match_dup 2) 0)))
8912    (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8913    (clobber (reg:CC CC_REGNUM))]
8914   "TARGET_ZARCH"
8915 {
8916   if (which_alternative != 0)
8917     return "#";
8918   else if (get_attr_length (insn) == 6)
8919     return "brx%E5g\t%1,%2,%l0";
8920   else
8921     return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8922 }
8923   "&& reload_completed
8924    && (!REG_P (operands[3])
8925        || !rtx_equal_p (operands[1], operands[3]))"
8926   [(set (match_dup 4) (match_dup 1))
8927    (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8928               (clobber (reg:CC CC_REGNUM))])
8929    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8930    (set (match_dup 3) (match_dup 4))
8931    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8932                            (label_ref (match_dup 0))
8933                            (pc)))]
8934   ""
8935   [(set_attr "op_type"  "RIE")
8936    (set_attr "type"  "branch")
8937    (set (attr "length")
8938         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8939                       (const_int 6) (const_int 16)))])
8940
8941 ; brxle, brxh
8942
8943 (define_insn_and_split "*brx_64bit"
8944   [(set (pc)
8945         (if_then_else
8946           (match_operator 5 "s390_brx_operator"
8947              [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8948                        (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8949               (subreg:SI (match_dup 2) 12)])
8950           (label_ref (match_operand 0 "" ""))
8951           (pc)))
8952    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8953         (plus:SI (match_dup 1)
8954                  (subreg:SI (match_dup 2) 4)))
8955    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8956    (clobber (reg:CC CC_REGNUM))]
8957   "TARGET_ZARCH"
8958 {
8959   if (which_alternative != 0)
8960     return "#";
8961   else if (get_attr_length (insn) == 6)
8962     return "brx%C5\t%1,%2,%l0";
8963   else
8964     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8965 }
8966   "&& reload_completed
8967    && (!REG_P (operands[3])
8968        || !rtx_equal_p (operands[1], operands[3]))"
8969   [(set (match_dup 4) (match_dup 1))
8970    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8971               (clobber (reg:CC CC_REGNUM))])
8972    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8973    (set (match_dup 3) (match_dup 4))
8974    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8975                            (label_ref (match_dup 0))
8976                            (pc)))]
8977   ""
8978   [(set_attr "op_type"  "RSI")
8979    (set_attr "type"  "branch")
8980    (set (attr "length")
8981         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8982                       (const_int 6) (const_int 14)))])
8983
8984 ; brxle, brxh
8985
8986 (define_insn_and_split "*brx_31bit"
8987   [(set (pc)
8988         (if_then_else
8989           (match_operator 5 "s390_brx_operator"
8990             [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8991                       (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8992              (subreg:SI (match_dup 2) 4)])
8993           (label_ref (match_operand 0 "" ""))
8994           (pc)))
8995    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8996         (plus:SI (match_dup 1)
8997                  (subreg:SI (match_dup 2) 0)))
8998    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8999    (clobber (reg:CC CC_REGNUM))]
9000   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9001 {
9002   if (which_alternative != 0)
9003     return "#";
9004   else if (get_attr_length (insn) == 6)
9005     return "brx%C5\t%1,%2,%l0";
9006   else
9007     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9008 }
9009   "&& reload_completed
9010    && (!REG_P (operands[3])
9011        || !rtx_equal_p (operands[1], operands[3]))"
9012   [(set (match_dup 4) (match_dup 1))
9013    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9014               (clobber (reg:CC CC_REGNUM))])
9015    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9016    (set (match_dup 3) (match_dup 4))
9017    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9018                            (label_ref (match_dup 0))
9019                            (pc)))]
9020   ""
9021   [(set_attr "op_type"  "RSI")
9022    (set_attr "type"  "branch")
9023    (set (attr "length")
9024         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9025                       (const_int 6) (const_int 14)))])
9026
9027
9028 ;; branch on count
9029
9030 (define_expand "doloop_end"
9031   [(use (match_operand 0 "" ""))        ; loop pseudo
9032    (use (match_operand 1 "" ""))]       ; label
9033   ""
9034 {
9035   if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9036     emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9037   else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9038     emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9039   else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9040     emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9041   else
9042     FAIL;
9043
9044   DONE;
9045 })
9046
9047 (define_insn_and_split "doloop_si64"
9048   [(set (pc)
9049         (if_then_else
9050           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9051               (const_int 1))
9052           (label_ref (match_operand 0 "" ""))
9053           (pc)))
9054    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9055         (plus:SI (match_dup 1) (const_int -1)))
9056    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9057    (clobber (reg:CC CC_REGNUM))]
9058   "TARGET_CPU_ZARCH"
9059 {
9060   if (which_alternative != 0)
9061     return "#";
9062   else if (get_attr_length (insn) == 4)
9063     return "brct\t%1,%l0";
9064   else
9065     return "ahi\t%1,-1\;jgne\t%l0";
9066 }
9067   "&& reload_completed
9068    && (! REG_P (operands[2])
9069        || ! rtx_equal_p (operands[1], operands[2]))"
9070   [(set (match_dup 3) (match_dup 1))
9071    (parallel [(set (reg:CCAN CC_REGNUM)
9072                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9073                                  (const_int 0)))
9074               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9075    (set (match_dup 2) (match_dup 3))
9076    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9077                            (label_ref (match_dup 0))
9078                            (pc)))]
9079   ""
9080   [(set_attr "op_type"  "RI")
9081    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9082    ; hurt us in the (rare) case of ahi.
9083    (set_attr "z10prop"  "z10_super_E1")
9084    (set_attr "type"  "branch")
9085    (set (attr "length")
9086         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9087                       (const_int 4) (const_int 10)))])
9088
9089 (define_insn_and_split "doloop_si31"
9090   [(set (pc)
9091         (if_then_else
9092           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9093               (const_int 1))
9094           (label_ref (match_operand 0 "" ""))
9095           (pc)))
9096    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9097         (plus:SI (match_dup 1) (const_int -1)))
9098    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9099    (clobber (reg:CC CC_REGNUM))]
9100   "!TARGET_CPU_ZARCH"
9101 {
9102   if (which_alternative != 0)
9103     return "#";
9104   else if (get_attr_length (insn) == 4)
9105     return "brct\t%1,%l0";
9106   else
9107     gcc_unreachable ();
9108 }
9109   "&& reload_completed
9110    && (! REG_P (operands[2])
9111        || ! rtx_equal_p (operands[1], operands[2]))"
9112   [(set (match_dup 3) (match_dup 1))
9113    (parallel [(set (reg:CCAN CC_REGNUM)
9114                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9115                                  (const_int 0)))
9116               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9117    (set (match_dup 2) (match_dup 3))
9118    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9119                            (label_ref (match_dup 0))
9120                            (pc)))]
9121   ""
9122   [(set_attr "op_type"  "RI")
9123    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9124    ; hurt us in the (rare) case of ahi.
9125    (set_attr "z10prop"  "z10_super_E1")
9126    (set_attr "type"  "branch")
9127    (set (attr "length")
9128         (if_then_else (not (match_test "flag_pic"))
9129           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9130                         (const_int 4) (const_int 6))
9131           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9132                         (const_int 4) (const_int 8))))])
9133
9134 (define_insn "*doloop_si_long"
9135   [(set (pc)
9136         (if_then_else
9137           (ne (match_operand:SI 1 "register_operand" "d")
9138               (const_int 1))
9139           (match_operand 0 "address_operand" "ZQZR")
9140           (pc)))
9141    (set (match_operand:SI 2 "register_operand" "=1")
9142         (plus:SI (match_dup 1) (const_int -1)))
9143    (clobber (match_scratch:SI 3 "=X"))
9144    (clobber (reg:CC CC_REGNUM))]
9145   "!TARGET_CPU_ZARCH"
9146 {
9147   if (get_attr_op_type (insn) == OP_TYPE_RR)
9148     return "bctr\t%1,%0";
9149   else
9150     return "bct\t%1,%a0";
9151 }
9152   [(set (attr "op_type")
9153         (if_then_else (match_operand 0 "register_operand" "")
9154                       (const_string "RR") (const_string "RX")))
9155    (set_attr "type"  "branch")
9156    (set_attr "atype" "agen")
9157    (set_attr "z10prop"  "z10_c")
9158    (set_attr "z196prop" "z196_cracked")])
9159
9160 (define_insn_and_split "doloop_di"
9161   [(set (pc)
9162         (if_then_else
9163           (ne (match_operand:DI 1 "register_operand" "d,d,d")
9164               (const_int 1))
9165           (label_ref (match_operand 0 "" ""))
9166           (pc)))
9167    (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9168         (plus:DI (match_dup 1) (const_int -1)))
9169    (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9170    (clobber (reg:CC CC_REGNUM))]
9171   "TARGET_ZARCH"
9172 {
9173   if (which_alternative != 0)
9174     return "#";
9175   else if (get_attr_length (insn) == 4)
9176     return "brctg\t%1,%l0";
9177   else
9178     return "aghi\t%1,-1\;jgne\t%l0";
9179 }
9180   "&& reload_completed
9181    && (! REG_P (operands[2])
9182        || ! rtx_equal_p (operands[1], operands[2]))"
9183   [(set (match_dup 3) (match_dup 1))
9184    (parallel [(set (reg:CCAN CC_REGNUM)
9185                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9186                                  (const_int 0)))
9187               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9188    (set (match_dup 2) (match_dup 3))
9189    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9190                            (label_ref (match_dup 0))
9191                            (pc)))]
9192   ""
9193   [(set_attr "op_type"  "RI")
9194    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9195    ; hurt us in the (rare) case of ahi.
9196    (set_attr "z10prop"  "z10_super_E1")
9197    (set_attr "type"  "branch")
9198    (set (attr "length")
9199         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9200                       (const_int 4) (const_int 10)))])
9201
9202 ;;
9203 ;;- Unconditional jump instructions.
9204 ;;
9205
9206 ;
9207 ; jump instruction pattern(s).
9208 ;
9209
9210 (define_expand "jump"
9211   [(match_operand 0 "" "")]
9212   ""
9213   "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9214
9215 (define_insn "*jump64"
9216   [(set (pc) (label_ref (match_operand 0 "" "")))]
9217   "TARGET_CPU_ZARCH"
9218 {
9219   if (get_attr_length (insn) == 4)
9220     return "j\t%l0";
9221   else
9222     return "jg\t%l0";
9223 }
9224   [(set_attr "op_type" "RI")
9225    (set_attr "type"  "branch")
9226    (set (attr "length")
9227         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9228                       (const_int 4) (const_int 6)))])
9229
9230 (define_insn "*jump31"
9231   [(set (pc) (label_ref (match_operand 0 "" "")))]
9232   "!TARGET_CPU_ZARCH"
9233 {
9234   gcc_assert (get_attr_length (insn) == 4);
9235   return "j\t%l0";
9236 }
9237   [(set_attr "op_type" "RI")
9238    (set_attr "type"  "branch")
9239    (set (attr "length")
9240         (if_then_else (not (match_test "flag_pic"))
9241           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9242                         (const_int 4) (const_int 6))
9243           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9244                         (const_int 4) (const_int 8))))])
9245
9246 ;
9247 ; indirect-jump instruction pattern(s).
9248 ;
9249
9250 (define_insn "indirect_jump"
9251  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
9252   ""
9253 {
9254   if (get_attr_op_type (insn) == OP_TYPE_RR)
9255     return "br\t%0";
9256   else
9257     return "b\t%a0";
9258 }
9259   [(set (attr "op_type")
9260         (if_then_else (match_operand 0 "register_operand" "")
9261                       (const_string "RR") (const_string "RX")))
9262    (set_attr "type"  "branch")
9263    (set_attr "atype" "agen")])
9264
9265 ;
9266 ; casesi instruction pattern(s).
9267 ;
9268
9269 (define_insn "casesi_jump"
9270  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
9271    (use (label_ref (match_operand 1 "" "")))]
9272   ""
9273 {
9274   if (get_attr_op_type (insn) == OP_TYPE_RR)
9275     return "br\t%0";
9276   else
9277     return "b\t%a0";
9278 }
9279   [(set (attr "op_type")
9280         (if_then_else (match_operand 0 "register_operand" "")
9281                       (const_string "RR") (const_string "RX")))
9282    (set_attr "type"  "branch")
9283    (set_attr "atype" "agen")])
9284
9285 (define_expand "casesi"
9286   [(match_operand:SI 0 "general_operand" "")
9287    (match_operand:SI 1 "general_operand" "")
9288    (match_operand:SI 2 "general_operand" "")
9289    (label_ref (match_operand 3 "" ""))
9290    (label_ref (match_operand 4 "" ""))]
9291   ""
9292 {
9293    rtx index  = gen_reg_rtx (SImode);
9294    rtx base   = gen_reg_rtx (Pmode);
9295    rtx target = gen_reg_rtx (Pmode);
9296
9297    emit_move_insn (index, operands[0]);
9298    emit_insn (gen_subsi3 (index, index, operands[1]));
9299    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9300                             operands[4]);
9301
9302    if (Pmode != SImode)
9303      index = convert_to_mode (Pmode, index, 1);
9304    if (GET_CODE (index) != REG)
9305      index = copy_to_mode_reg (Pmode, index);
9306
9307    if (TARGET_64BIT)
9308        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9309    else
9310        emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9311
9312    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9313
9314    index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9315    emit_move_insn (target, index);
9316
9317    if (flag_pic)
9318      target = gen_rtx_PLUS (Pmode, base, target);
9319    emit_jump_insn (gen_casesi_jump (target, operands[3]));
9320
9321    DONE;
9322 })
9323
9324
9325 ;;
9326 ;;- Jump to subroutine.
9327 ;;
9328 ;;
9329
9330 ;
9331 ; untyped call instruction pattern(s).
9332 ;
9333
9334 ;; Call subroutine returning any type.
9335 (define_expand "untyped_call"
9336   [(parallel [(call (match_operand 0 "" "")
9337                     (const_int 0))
9338               (match_operand 1 "" "")
9339               (match_operand 2 "" "")])]
9340   ""
9341 {
9342   int i;
9343
9344   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9345
9346   for (i = 0; i < XVECLEN (operands[2], 0); i++)
9347     {
9348       rtx set = XVECEXP (operands[2], 0, i);
9349       emit_move_insn (SET_DEST (set), SET_SRC (set));
9350     }
9351
9352   /* The optimizer does not know that the call sets the function value
9353      registers we stored in the result block.  We avoid problems by
9354      claiming that all hard registers are used and clobbered at this
9355      point.  */
9356   emit_insn (gen_blockage ());
9357
9358   DONE;
9359 })
9360
9361 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9362 ;; all of memory.  This blocks insns from being moved across this point.
9363
9364 (define_insn "blockage"
9365   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9366   ""
9367   ""
9368   [(set_attr "type"    "none")
9369    (set_attr "length"  "0")])
9370
9371 ;
9372 ; sibcall patterns
9373 ;
9374
9375 (define_expand "sibcall"
9376   [(call (match_operand 0 "" "")
9377          (match_operand 1 "" ""))]
9378   ""
9379 {
9380   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9381   DONE;
9382 })
9383
9384 (define_insn "*sibcall_br"
9385   [(call (mem:QI (reg SIBCALL_REGNUM))
9386          (match_operand 0 "const_int_operand" "n"))]
9387   "SIBLING_CALL_P (insn)
9388    && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9389   "br\t%%r1"
9390   [(set_attr "op_type" "RR")
9391    (set_attr "type"  "branch")
9392    (set_attr "atype" "agen")])
9393
9394 (define_insn "*sibcall_brc"
9395   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9396          (match_operand 1 "const_int_operand" "n"))]
9397   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9398   "j\t%0"
9399   [(set_attr "op_type" "RI")
9400    (set_attr "type"    "branch")])
9401
9402 (define_insn "*sibcall_brcl"
9403   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9404          (match_operand 1 "const_int_operand" "n"))]
9405   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9406   "jg\t%0"
9407   [(set_attr "op_type" "RIL")
9408    (set_attr "type"    "branch")])
9409
9410 ;
9411 ; sibcall_value patterns
9412 ;
9413
9414 (define_expand "sibcall_value"
9415   [(set (match_operand 0 "" "")
9416         (call (match_operand 1 "" "")
9417               (match_operand 2 "" "")))]
9418   ""
9419 {
9420   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9421   DONE;
9422 })
9423
9424 (define_insn "*sibcall_value_br"
9425   [(set (match_operand 0 "" "")
9426         (call (mem:QI (reg SIBCALL_REGNUM))
9427               (match_operand 1 "const_int_operand" "n")))]
9428   "SIBLING_CALL_P (insn)
9429    && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9430   "br\t%%r1"
9431   [(set_attr "op_type" "RR")
9432    (set_attr "type"  "branch")
9433    (set_attr "atype" "agen")])
9434
9435 (define_insn "*sibcall_value_brc"
9436   [(set (match_operand 0 "" "")
9437         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9438               (match_operand 2 "const_int_operand" "n")))]
9439   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9440   "j\t%1"
9441   [(set_attr "op_type" "RI")
9442    (set_attr "type"    "branch")])
9443
9444 (define_insn "*sibcall_value_brcl"
9445   [(set (match_operand 0 "" "")
9446         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9447               (match_operand 2 "const_int_operand" "n")))]
9448   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9449   "jg\t%1"
9450   [(set_attr "op_type" "RIL")
9451    (set_attr "type"    "branch")])
9452
9453
9454 ;
9455 ; call instruction pattern(s).
9456 ;
9457
9458 (define_expand "call"
9459   [(call (match_operand 0 "" "")
9460          (match_operand 1 "" ""))
9461    (use (match_operand 2 "" ""))]
9462   ""
9463 {
9464   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9465                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9466   DONE;
9467 })
9468
9469 (define_insn "*bras"
9470   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9471          (match_operand 1 "const_int_operand" "n"))
9472    (clobber (match_operand 2 "register_operand" "=r"))]
9473   "!SIBLING_CALL_P (insn)
9474    && TARGET_SMALL_EXEC
9475    && GET_MODE (operands[2]) == Pmode"
9476   "bras\t%2,%0"
9477   [(set_attr "op_type" "RI")
9478    (set_attr "type"    "jsr")
9479    (set_attr "z196prop" "z196_cracked")])
9480
9481 (define_insn "*brasl"
9482   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9483          (match_operand 1 "const_int_operand" "n"))
9484    (clobber (match_operand 2 "register_operand" "=r"))]
9485   "!SIBLING_CALL_P (insn)
9486    && TARGET_CPU_ZARCH
9487    && GET_MODE (operands[2]) == Pmode"
9488   "brasl\t%2,%0"
9489   [(set_attr "op_type" "RIL")
9490    (set_attr "type"    "jsr")
9491    (set_attr "z196prop" "z196_cracked")])
9492
9493 (define_insn "*basr"
9494   [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9495          (match_operand 1 "const_int_operand" "n"))
9496    (clobber (match_operand 2 "register_operand" "=r"))]
9497   "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9498 {
9499   if (get_attr_op_type (insn) == OP_TYPE_RR)
9500     return "basr\t%2,%0";
9501   else
9502     return "bas\t%2,%a0";
9503 }
9504   [(set (attr "op_type")
9505         (if_then_else (match_operand 0 "register_operand" "")
9506                       (const_string "RR") (const_string "RX")))
9507    (set_attr "type"  "jsr")
9508    (set_attr "atype" "agen")
9509    (set_attr "z196prop" "z196_cracked")])
9510
9511 ;
9512 ; call_value instruction pattern(s).
9513 ;
9514
9515 (define_expand "call_value"
9516   [(set (match_operand 0 "" "")
9517         (call (match_operand 1 "" "")
9518               (match_operand 2 "" "")))
9519    (use (match_operand 3 "" ""))]
9520   ""
9521 {
9522   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9523                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9524   DONE;
9525 })
9526
9527 (define_insn "*bras_r"
9528   [(set (match_operand 0 "" "")
9529         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9530               (match_operand:SI 2 "const_int_operand" "n")))
9531    (clobber (match_operand 3 "register_operand" "=r"))]
9532   "!SIBLING_CALL_P (insn)
9533    && TARGET_SMALL_EXEC
9534    && GET_MODE (operands[3]) == Pmode"
9535   "bras\t%3,%1"
9536   [(set_attr "op_type" "RI")
9537    (set_attr "type"    "jsr")
9538    (set_attr "z196prop" "z196_cracked")])
9539
9540 (define_insn "*brasl_r"
9541   [(set (match_operand 0 "" "")
9542         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9543               (match_operand 2 "const_int_operand" "n")))
9544    (clobber (match_operand 3 "register_operand" "=r"))]
9545   "!SIBLING_CALL_P (insn)
9546    && TARGET_CPU_ZARCH
9547    && GET_MODE (operands[3]) == Pmode"
9548   "brasl\t%3,%1"
9549   [(set_attr "op_type" "RIL")
9550    (set_attr "type"    "jsr")
9551    (set_attr "z196prop" "z196_cracked")])
9552
9553 (define_insn "*basr_r"
9554   [(set (match_operand 0 "" "")
9555         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9556               (match_operand 2 "const_int_operand" "n")))
9557    (clobber (match_operand 3 "register_operand" "=r"))]
9558   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9559 {
9560   if (get_attr_op_type (insn) == OP_TYPE_RR)
9561     return "basr\t%3,%1";
9562   else
9563     return "bas\t%3,%a1";
9564 }
9565   [(set (attr "op_type")
9566         (if_then_else (match_operand 1 "register_operand" "")
9567                       (const_string "RR") (const_string "RX")))
9568    (set_attr "type"  "jsr")
9569    (set_attr "atype" "agen")
9570    (set_attr "z196prop" "z196_cracked")])
9571
9572 ;;
9573 ;;- Thread-local storage support.
9574 ;;
9575
9576 (define_expand "get_thread_pointer<mode>"
9577   [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9578   ""
9579   "")
9580
9581 (define_expand "set_thread_pointer<mode>"
9582   [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9583    (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9584   ""
9585   "")
9586
9587 (define_insn "*set_tp"
9588   [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9589   ""
9590   ""
9591   [(set_attr "type" "none")
9592    (set_attr "length" "0")])
9593
9594 (define_insn "*tls_load_64"
9595   [(set (match_operand:DI 0 "register_operand" "=d")
9596         (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9597                     (match_operand:DI 2 "" "")]
9598                    UNSPEC_TLS_LOAD))]
9599   "TARGET_64BIT"
9600   "lg\t%0,%1%J2"
9601   [(set_attr "op_type" "RXE")
9602    (set_attr "z10prop" "z10_fwd_A3")])
9603
9604 (define_insn "*tls_load_31"
9605   [(set (match_operand:SI 0 "register_operand" "=d,d")
9606         (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9607                     (match_operand:SI 2 "" "")]
9608                    UNSPEC_TLS_LOAD))]
9609   "!TARGET_64BIT"
9610   "@
9611    l\t%0,%1%J2
9612    ly\t%0,%1%J2"
9613   [(set_attr "op_type" "RX,RXY")
9614    (set_attr "type" "load")
9615    (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9616
9617 (define_insn "*bras_tls"
9618   [(set (match_operand 0 "" "")
9619         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9620               (match_operand 2 "const_int_operand" "n")))
9621    (clobber (match_operand 3 "register_operand" "=r"))
9622    (use (match_operand 4 "" ""))]
9623   "!SIBLING_CALL_P (insn)
9624    && TARGET_SMALL_EXEC
9625    && GET_MODE (operands[3]) == Pmode"
9626   "bras\t%3,%1%J4"
9627   [(set_attr "op_type" "RI")
9628    (set_attr "type"    "jsr")
9629    (set_attr "z196prop" "z196_cracked")])
9630
9631 (define_insn "*brasl_tls"
9632   [(set (match_operand 0 "" "")
9633         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9634               (match_operand 2 "const_int_operand" "n")))
9635    (clobber (match_operand 3 "register_operand" "=r"))
9636    (use (match_operand 4 "" ""))]
9637   "!SIBLING_CALL_P (insn)
9638    && TARGET_CPU_ZARCH
9639    && GET_MODE (operands[3]) == Pmode"
9640   "brasl\t%3,%1%J4"
9641   [(set_attr "op_type" "RIL")
9642    (set_attr "type"    "jsr")
9643    (set_attr "z196prop" "z196_cracked")])
9644
9645 (define_insn "*basr_tls"
9646   [(set (match_operand 0 "" "")
9647         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9648               (match_operand 2 "const_int_operand" "n")))
9649    (clobber (match_operand 3 "register_operand" "=r"))
9650    (use (match_operand 4 "" ""))]
9651   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9652 {
9653   if (get_attr_op_type (insn) == OP_TYPE_RR)
9654     return "basr\t%3,%1%J4";
9655   else
9656     return "bas\t%3,%a1%J4";
9657 }
9658   [(set (attr "op_type")
9659         (if_then_else (match_operand 1 "register_operand" "")
9660                       (const_string "RR") (const_string "RX")))
9661    (set_attr "type"  "jsr")
9662    (set_attr "atype" "agen")
9663    (set_attr "z196prop" "z196_cracked")])
9664
9665 ;;
9666 ;;- Atomic operations
9667 ;;
9668
9669 ;
9670 ; memory barrier patterns.
9671 ;
9672
9673 (define_expand "mem_signal_fence"
9674   [(match_operand:SI 0 "const_int_operand")]            ;; model
9675   ""
9676 {
9677   /* The s390 memory model is strong enough not to require any
9678      barrier in order to synchronize a thread with itself.  */
9679   DONE;
9680 })
9681
9682 (define_expand "mem_thread_fence"
9683   [(match_operand:SI 0 "const_int_operand")]            ;; model
9684   ""
9685 {
9686   /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9687      enough not to require barriers of any kind.  */
9688   if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9689     {
9690       rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9691       MEM_VOLATILE_P (mem) = 1;
9692       emit_insn (gen_mem_thread_fence_1 (mem));
9693     }
9694   DONE;
9695 })
9696
9697 ; Although bcr is superscalar on Z10, this variant will never
9698 ; become part of an execution group.
9699 ; With z196 we can make use of the fast-BCR-serialization facility.
9700 ; This allows for a slightly faster sync which is sufficient for our
9701 ; purposes.
9702 (define_insn "mem_thread_fence_1"
9703   [(set (match_operand:BLK 0 "" "")
9704         (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9705   ""
9706 {
9707   if (TARGET_Z196)
9708     return "bcr\t14,0";
9709   else
9710     return "bcr\t15,0";
9711 }
9712   [(set_attr "op_type" "RR")
9713    (set_attr "mnemonic" "bcr_flush")
9714    (set_attr "z196prop" "z196_alone")])
9715
9716 ;
9717 ; atomic load/store operations
9718 ;
9719
9720 ; Atomic loads need not examine the memory model at all.
9721 (define_expand "atomic_load<mode>"
9722   [(match_operand:DINT 0 "register_operand")    ;; output
9723    (match_operand:DINT 1 "memory_operand")      ;; memory
9724    (match_operand:SI 2 "const_int_operand")]    ;; model
9725   ""
9726 {
9727   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9728     FAIL;
9729
9730   if (<MODE>mode == TImode)
9731     emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9732   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9733     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9734   else
9735     emit_move_insn (operands[0], operands[1]);
9736   DONE;
9737 })
9738
9739 ; Different from movdi_31 in that we want no splitters.
9740 (define_insn "atomic_loaddi_1"
9741   [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9742         (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9743                    UNSPEC_MOVA))]
9744   "!TARGET_ZARCH"
9745   "@
9746    lm\t%0,%M0,%S1
9747    lmy\t%0,%M0,%S1
9748    ld\t%0,%1
9749    ldy\t%0,%1"
9750   [(set_attr "op_type" "RS,RSY,RS,RSY")
9751    (set_attr "type" "lm,lm,floaddf,floaddf")])
9752
9753 (define_insn "atomic_loadti_1"
9754   [(set (match_operand:TI 0 "register_operand" "=r")
9755         (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9756                    UNSPEC_MOVA))]
9757   "TARGET_ZARCH"
9758   "lpq\t%0,%1"
9759   [(set_attr "op_type" "RXY")
9760    (set_attr "type" "other")])
9761
9762 ; Atomic stores must(?) enforce sequential consistency.
9763 (define_expand "atomic_store<mode>"
9764   [(match_operand:DINT 0 "memory_operand")      ;; memory
9765    (match_operand:DINT 1 "register_operand")    ;; input
9766    (match_operand:SI 2 "const_int_operand")]    ;; model
9767   ""
9768 {
9769   enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9770
9771   if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9772     FAIL;
9773
9774   if (<MODE>mode == TImode)
9775     emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9776   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9777     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9778   else
9779     emit_move_insn (operands[0], operands[1]);
9780   if (is_mm_seq_cst (model))
9781     emit_insn (gen_mem_thread_fence (operands[2]));
9782   DONE;
9783 })
9784
9785 ; Different from movdi_31 in that we want no splitters.
9786 (define_insn "atomic_storedi_1"
9787   [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9788         (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9789                    UNSPEC_MOVA))]
9790   "!TARGET_ZARCH"
9791   "@
9792    stm\t%1,%N1,%S0
9793    stmy\t%1,%N1,%S0
9794    std %1,%0
9795    stdy %1,%0"
9796   [(set_attr "op_type" "RS,RSY,RS,RSY")
9797    (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9798
9799 (define_insn "atomic_storeti_1"
9800   [(set (match_operand:TI 0 "memory_operand" "=RT")
9801         (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9802                    UNSPEC_MOVA))]
9803   "TARGET_ZARCH"
9804   "stpq\t%1,%0"
9805   [(set_attr "op_type" "RXY")
9806    (set_attr "type" "other")])
9807
9808 ;
9809 ; compare and swap patterns.
9810 ;
9811
9812 (define_expand "atomic_compare_and_swap<mode>"
9813   [(match_operand:SI 0 "register_operand")      ;; bool success output
9814    (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9815    (match_operand:DGPR 2 "memory_operand")      ;; memory
9816    (match_operand:DGPR 3 "register_operand")    ;; expected intput
9817    (match_operand:DGPR 4 "register_operand")    ;; newval intput
9818    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9819    (match_operand:SI 6 "const_int_operand")     ;; success model
9820    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9821   ""
9822 {
9823   rtx cc, cmp, output = operands[1];
9824
9825   if (!register_operand (output, <MODE>mode))
9826     output = gen_reg_rtx (<MODE>mode);
9827
9828   if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9829     FAIL;
9830
9831   emit_insn (gen_atomic_compare_and_swap<mode>_internal
9832              (output, operands[2], operands[3], operands[4]));
9833
9834   /* We deliberately accept non-register operands in the predicate
9835      to ensure the write back to the output operand happens *before*
9836      the store-flags code below.  This makes it easier for combine
9837      to merge the store-flags code with a potential test-and-branch
9838      pattern following (immediately!) afterwards.  */
9839   if (output != operands[1])
9840     emit_move_insn (operands[1], output);
9841
9842   cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9843   cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9844   emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9845   DONE;
9846 })
9847
9848 (define_expand "atomic_compare_and_swap<mode>"
9849   [(match_operand:SI 0 "register_operand")      ;; bool success output
9850    (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9851    (match_operand:HQI 2 "memory_operand")       ;; memory
9852    (match_operand:HQI 3 "general_operand")      ;; expected intput
9853    (match_operand:HQI 4 "general_operand")      ;; newval intput
9854    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9855    (match_operand:SI 6 "const_int_operand")     ;; success model
9856    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9857   ""
9858 {
9859   s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9860                       operands[3], operands[4], INTVAL (operands[5]));
9861   DONE;
9862 })
9863
9864 (define_expand "atomic_compare_and_swap<mode>_internal"
9865   [(parallel
9866      [(set (match_operand:DGPR 0 "register_operand")
9867            (match_operand:DGPR 1 "memory_operand"))
9868       (set (match_dup 1)
9869            (unspec_volatile:DGPR
9870              [(match_dup 1)
9871               (match_operand:DGPR 2 "register_operand")
9872               (match_operand:DGPR 3 "register_operand")]
9873              UNSPECV_CAS))
9874       (set (reg:CCZ1 CC_REGNUM)
9875            (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9876   "")
9877
9878 ; cdsg, csg
9879 (define_insn "*atomic_compare_and_swap<mode>_1"
9880   [(set (match_operand:TDI 0 "register_operand" "=r")
9881         (match_operand:TDI 1 "memory_operand" "+QS"))
9882    (set (match_dup 1)
9883         (unspec_volatile:TDI
9884           [(match_dup 1)
9885            (match_operand:TDI 2 "register_operand" "0")
9886            (match_operand:TDI 3 "register_operand" "r")]
9887           UNSPECV_CAS))
9888    (set (reg:CCZ1 CC_REGNUM)
9889         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9890   "TARGET_ZARCH"
9891   "c<td>sg\t%0,%3,%S1"
9892   [(set_attr "op_type" "RSY")
9893    (set_attr "type"   "sem")])
9894
9895 ; cds, cdsy
9896 (define_insn "*atomic_compare_and_swapdi_2"
9897   [(set (match_operand:DI 0 "register_operand" "=r,r")
9898         (match_operand:DI 1 "memory_operand" "+Q,S"))
9899    (set (match_dup 1)
9900         (unspec_volatile:DI
9901           [(match_dup 1)
9902            (match_operand:DI 2 "register_operand" "0,0")
9903            (match_operand:DI 3 "register_operand" "r,r")]
9904           UNSPECV_CAS))
9905    (set (reg:CCZ1 CC_REGNUM)
9906         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9907   "!TARGET_ZARCH"
9908   "@
9909    cds\t%0,%3,%S1
9910    cdsy\t%0,%3,%S1"
9911   [(set_attr "op_type" "RS,RSY")
9912    (set_attr "type" "sem")])
9913
9914 ; cs, csy
9915 (define_insn "*atomic_compare_and_swapsi_3"
9916   [(set (match_operand:SI 0 "register_operand" "=r,r")
9917         (match_operand:SI 1 "memory_operand" "+Q,S"))
9918    (set (match_dup 1)
9919         (unspec_volatile:SI
9920           [(match_dup 1)
9921            (match_operand:SI 2 "register_operand" "0,0")
9922            (match_operand:SI 3 "register_operand" "r,r")]
9923           UNSPECV_CAS))
9924    (set (reg:CCZ1 CC_REGNUM)
9925         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9926   ""
9927   "@
9928    cs\t%0,%3,%S1
9929    csy\t%0,%3,%S1"
9930   [(set_attr "op_type" "RS,RSY")
9931    (set_attr "type"   "sem")])
9932
9933 ;
9934 ; Other atomic instruction patterns.
9935 ;
9936
9937 ; z196 load and add, xor, or and and instructions
9938
9939 (define_expand "atomic_fetch_<atomic><mode>"
9940   [(match_operand:GPR 0 "register_operand")             ;; val out
9941    (ATOMIC_Z196:GPR
9942      (match_operand:GPR 1 "memory_operand")             ;; memory
9943      (match_operand:GPR 2 "register_operand"))          ;; val in
9944    (match_operand:SI 3 "const_int_operand")]            ;; model
9945   "TARGET_Z196"
9946 {
9947   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9948     FAIL;
9949
9950   emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9951              (operands[0], operands[1], operands[2]));
9952   DONE;
9953 })
9954
9955 ; lan, lang, lao, laog, lax, laxg, laa, laag
9956 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9957   [(set (match_operand:GPR 0 "register_operand" "=d")
9958         (match_operand:GPR 1 "memory_operand" "+QS"))
9959    (set (match_dup 1)
9960         (unspec_volatile:GPR
9961          [(ATOMIC_Z196:GPR (match_dup 1)
9962                            (match_operand:GPR 2 "general_operand" "d"))]
9963          UNSPECV_ATOMIC_OP))
9964    (clobber (reg:CC CC_REGNUM))]
9965   "TARGET_Z196"
9966   "la<noxa><g>\t%0,%2,%1"
9967   [(set_attr "op_type" "RSY")
9968    (set_attr "type" "sem")])
9969
9970 ;; For SImode and larger, the optabs.c code will do just fine in
9971 ;; expanding a compare-and-swap loop.  For QI/HImode, we can do
9972 ;; better by expanding our own loop.
9973
9974 (define_expand "atomic_<atomic><mode>"
9975   [(ATOMIC:HQI
9976      (match_operand:HQI 0 "memory_operand")             ;; memory
9977      (match_operand:HQI 1 "general_operand"))           ;; val in
9978    (match_operand:SI 2 "const_int_operand")]            ;; model
9979   ""
9980 {
9981   s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9982                        operands[1], false);
9983   DONE;
9984 })
9985
9986 (define_expand "atomic_fetch_<atomic><mode>"
9987   [(match_operand:HQI 0 "register_operand")             ;; val out
9988    (ATOMIC:HQI
9989      (match_operand:HQI 1 "memory_operand")             ;; memory
9990      (match_operand:HQI 2 "general_operand"))           ;; val in
9991    (match_operand:SI 3 "const_int_operand")]            ;; model
9992   ""
9993 {
9994   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9995                       operands[2], false);
9996   DONE;
9997 })
9998
9999 (define_expand "atomic_<atomic>_fetch<mode>"
10000   [(match_operand:HQI 0 "register_operand")             ;; val out
10001    (ATOMIC:HQI
10002      (match_operand:HQI 1 "memory_operand")             ;; memory
10003      (match_operand:HQI 2 "general_operand"))           ;; val in
10004    (match_operand:SI 3 "const_int_operand")]            ;; model
10005   ""
10006 {
10007   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10008                       operands[2], true);
10009   DONE;
10010 })
10011
10012 (define_expand "atomic_exchange<mode>"
10013   [(match_operand:HQI 0 "register_operand")             ;; val out
10014    (match_operand:HQI 1 "memory_operand")               ;; memory
10015    (match_operand:HQI 2 "general_operand")              ;; val in
10016    (match_operand:SI 3 "const_int_operand")]            ;; model
10017   ""
10018 {
10019   s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10020                       operands[2], false);
10021   DONE;
10022 })
10023
10024 ;;
10025 ;;- Miscellaneous instructions.
10026 ;;
10027
10028 ;
10029 ; allocate stack instruction pattern(s).
10030 ;
10031
10032 (define_expand "allocate_stack"
10033   [(match_operand 0 "general_operand" "")
10034    (match_operand 1 "general_operand" "")]
10035  "TARGET_BACKCHAIN"
10036 {
10037   rtx temp = gen_reg_rtx (Pmode);
10038
10039   emit_move_insn (temp, s390_back_chain_rtx ());
10040   anti_adjust_stack (operands[1]);
10041   emit_move_insn (s390_back_chain_rtx (), temp);
10042
10043   emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10044   DONE;
10045 })
10046
10047
10048 ;
10049 ; setjmp instruction pattern.
10050 ;
10051
10052 (define_expand "builtin_setjmp_receiver"
10053   [(match_operand 0 "" "")]
10054   "flag_pic"
10055 {
10056   emit_insn (s390_load_got ());
10057   emit_use (pic_offset_table_rtx);
10058   DONE;
10059 })
10060
10061 ;; These patterns say how to save and restore the stack pointer.  We need not
10062 ;; save the stack pointer at function level since we are careful to
10063 ;; preserve the backchain.  At block level, we have to restore the backchain
10064 ;; when we restore the stack pointer.
10065 ;;
10066 ;; For nonlocal gotos, we must save both the stack pointer and its
10067 ;; backchain and restore both.  Note that in the nonlocal case, the
10068 ;; save area is a memory location.
10069
10070 (define_expand "save_stack_function"
10071   [(match_operand 0 "general_operand" "")
10072    (match_operand 1 "general_operand" "")]
10073   ""
10074   "DONE;")
10075
10076 (define_expand "restore_stack_function"
10077   [(match_operand 0 "general_operand" "")
10078    (match_operand 1 "general_operand" "")]
10079   ""
10080   "DONE;")
10081
10082 (define_expand "restore_stack_block"
10083   [(match_operand 0 "register_operand" "")
10084    (match_operand 1 "register_operand" "")]
10085   "TARGET_BACKCHAIN"
10086 {
10087   rtx temp = gen_reg_rtx (Pmode);
10088
10089   emit_move_insn (temp, s390_back_chain_rtx ());
10090   emit_move_insn (operands[0], operands[1]);
10091   emit_move_insn (s390_back_chain_rtx (), temp);
10092
10093   DONE;
10094 })
10095
10096 (define_expand "save_stack_nonlocal"
10097   [(match_operand 0 "memory_operand" "")
10098    (match_operand 1 "register_operand" "")]
10099   ""
10100 {
10101   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10102
10103   /* Copy the backchain to the first word, sp to the second and the
10104      literal pool base to the third.  */
10105
10106   rtx save_bc = adjust_address (operands[0], Pmode, 0);
10107   rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10108   rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10109
10110   if (TARGET_BACKCHAIN)
10111     emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10112
10113   emit_move_insn (save_sp, operands[1]);
10114   emit_move_insn (save_bp, base);
10115
10116   DONE;
10117 })
10118
10119 (define_expand "restore_stack_nonlocal"
10120   [(match_operand 0 "register_operand" "")
10121    (match_operand 1 "memory_operand" "")]
10122   ""
10123 {
10124   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10125   rtx temp = NULL_RTX;
10126
10127   /* Restore the backchain from the first word, sp from the second and the
10128      literal pool base from the third.  */
10129
10130   rtx save_bc = adjust_address (operands[1], Pmode, 0);
10131   rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10132   rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10133
10134   if (TARGET_BACKCHAIN)
10135     temp = force_reg (Pmode, save_bc);
10136
10137   emit_move_insn (base, save_bp);
10138   emit_move_insn (operands[0], save_sp);
10139
10140   if (temp)
10141     emit_move_insn (s390_back_chain_rtx (), temp);
10142
10143   emit_use (base);
10144   DONE;
10145 })
10146
10147 (define_expand "exception_receiver"
10148   [(const_int 0)]
10149   ""
10150 {
10151   s390_set_has_landing_pad_p (true);
10152   DONE;
10153 })
10154
10155 ;
10156 ; nop instruction pattern(s).
10157 ;
10158
10159 (define_insn "nop"
10160   [(const_int 0)]
10161   ""
10162   "lr\t0,0"
10163   [(set_attr "op_type" "RR")
10164    (set_attr "z10prop"  "z10_fr_E1")])
10165
10166 (define_insn "nop1"
10167   [(const_int 1)]
10168   ""
10169   "lr\t1,1"
10170   [(set_attr "op_type" "RR")])
10171
10172 ;;- Undeletable nops (used for hotpatching)
10173
10174 (define_insn "nop_2_byte"
10175   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10176   ""
10177   "nopr\t%%r7"
10178   [(set_attr "op_type" "RR")])
10179
10180 (define_insn "nop_4_byte"
10181   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10182   ""
10183   "nop\t0"
10184   [(set_attr "op_type" "RX")])
10185
10186 (define_insn "nop_6_byte"
10187   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10188   "TARGET_CPU_ZARCH"
10189   "brcl\t0, 0"
10190   [(set_attr "op_type" "RIL")])
10191
10192
10193 ;
10194 ; Special literal pool access instruction pattern(s).
10195 ;
10196
10197 (define_insn "*pool_entry"
10198   [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10199                     UNSPECV_POOL_ENTRY)]
10200   ""
10201 {
10202   machine_mode mode = GET_MODE (PATTERN (insn));
10203   unsigned int align = GET_MODE_BITSIZE (mode);
10204   s390_output_pool_entry (operands[0], mode, align);
10205   return "";
10206 }
10207   [(set (attr "length")
10208         (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10209
10210 (define_insn "pool_align"
10211   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10212                     UNSPECV_POOL_ALIGN)]
10213   ""
10214   ".align\t%0"
10215   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10216
10217 (define_insn "pool_section_start"
10218   [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10219   ""
10220   ".section\t.rodata"
10221   [(set_attr "length" "0")])
10222
10223 (define_insn "pool_section_end"
10224   [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10225   ""
10226   ".previous"
10227   [(set_attr "length" "0")])
10228
10229 (define_insn "main_base_31_small"
10230   [(set (match_operand 0 "register_operand" "=a")
10231         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10232   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10233   "basr\t%0,0"
10234   [(set_attr "op_type" "RR")
10235    (set_attr "type"    "la")
10236    (set_attr "z196prop" "z196_cracked")])
10237
10238 (define_insn "main_base_31_large"
10239   [(set (match_operand 0 "register_operand" "=a")
10240         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10241    (set (pc) (label_ref (match_operand 2 "" "")))]
10242   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10243   "bras\t%0,%2"
10244   [(set_attr "op_type" "RI")
10245    (set_attr "z196prop" "z196_cracked")])
10246
10247 (define_insn "main_base_64"
10248   [(set (match_operand 0 "register_operand" "=a")
10249         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10250   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10251   "larl\t%0,%1"
10252   [(set_attr "op_type" "RIL")
10253    (set_attr "type"    "larl")
10254    (set_attr "z10prop" "z10_fwd_A1")])
10255
10256 (define_insn "main_pool"
10257   [(set (match_operand 0 "register_operand" "=a")
10258         (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10259   "GET_MODE (operands[0]) == Pmode"
10260 {
10261   gcc_unreachable ();
10262 }
10263   [(set (attr "type")
10264         (if_then_else (match_test "TARGET_CPU_ZARCH")
10265                       (const_string "larl") (const_string "la")))])
10266
10267 (define_insn "reload_base_31"
10268   [(set (match_operand 0 "register_operand" "=a")
10269         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10270   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10271   "basr\t%0,0\;la\t%0,%1-.(%0)"
10272   [(set_attr "length" "6")
10273    (set_attr "type" "la")
10274    (set_attr "z196prop" "z196_cracked")])
10275
10276 (define_insn "reload_base_64"
10277   [(set (match_operand 0 "register_operand" "=a")
10278         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10279   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10280   "larl\t%0,%1"
10281   [(set_attr "op_type" "RIL")
10282    (set_attr "type"    "larl")
10283    (set_attr "z10prop" "z10_fwd_A1")])
10284
10285 (define_insn "pool"
10286   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10287   ""
10288 {
10289   gcc_unreachable ();
10290 }
10291   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10292
10293 ;;
10294 ;; Insns related to generating the function prologue and epilogue.
10295 ;;
10296
10297
10298 (define_expand "prologue"
10299   [(use (const_int 0))]
10300   ""
10301   "s390_emit_prologue (); DONE;")
10302
10303 (define_expand "epilogue"
10304   [(use (const_int 1))]
10305   ""
10306   "s390_emit_epilogue (false); DONE;")
10307
10308 (define_expand "sibcall_epilogue"
10309   [(use (const_int 0))]
10310   ""
10311   "s390_emit_epilogue (true); DONE;")
10312
10313 ;; A direct return instruction, without using an epilogue.
10314 (define_insn "<code>"
10315   [(ANY_RETURN)]
10316   "s390_can_use_<code>_insn ()"
10317   "br\t%%r14"
10318   [(set_attr "op_type" "RR")
10319    (set_attr "type"    "jsr")
10320    (set_attr "atype"   "agen")])
10321
10322 (define_insn "*return"
10323   [(return)
10324    (use (match_operand 0 "register_operand" "a"))]
10325   "GET_MODE (operands[0]) == Pmode"
10326   "br\t%0"
10327   [(set_attr "op_type" "RR")
10328    (set_attr "type"    "jsr")
10329    (set_attr "atype"   "agen")])
10330
10331
10332 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10333 ;; pointer. This is used for compatibility.
10334
10335 (define_expand "ptr_extend"
10336   [(set (match_operand:DI 0 "register_operand" "=r")
10337         (match_operand:SI 1 "register_operand" "r"))]
10338   "TARGET_64BIT"
10339 {
10340   emit_insn (gen_anddi3 (operands[0],
10341                          gen_lowpart (DImode, operands[1]),
10342                          GEN_INT (0x7fffffff)));
10343   DONE;
10344 })
10345
10346 ;; Instruction definition to expand eh_return macro to support
10347 ;; swapping in special linkage return addresses.
10348
10349 (define_expand "eh_return"
10350   [(use (match_operand 0 "register_operand" ""))]
10351   "TARGET_TPF"
10352 {
10353   s390_emit_tpf_eh_return (operands[0]);
10354   DONE;
10355 })
10356
10357 ;
10358 ; Stack Protector Patterns
10359 ;
10360
10361 (define_expand "stack_protect_set"
10362   [(set (match_operand 0 "memory_operand" "")
10363         (match_operand 1 "memory_operand" ""))]
10364   ""
10365 {
10366 #ifdef TARGET_THREAD_SSP_OFFSET
10367   operands[1]
10368     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10369                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10370 #endif
10371   if (TARGET_64BIT)
10372     emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10373   else
10374     emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10375
10376   DONE;
10377 })
10378
10379 (define_insn "stack_protect_set<mode>"
10380   [(set (match_operand:DSI 0 "memory_operand" "=Q")
10381         (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10382   ""
10383   "mvc\t%O0(%G0,%R0),%S1"
10384   [(set_attr "op_type" "SS")])
10385
10386 (define_expand "stack_protect_test"
10387   [(set (reg:CC CC_REGNUM)
10388         (compare (match_operand 0 "memory_operand" "")
10389                  (match_operand 1 "memory_operand" "")))
10390    (match_operand 2 "" "")]
10391   ""
10392 {
10393   rtx cc_reg, test;
10394 #ifdef TARGET_THREAD_SSP_OFFSET
10395   operands[1]
10396     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10397                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10398 #endif
10399   if (TARGET_64BIT)
10400     emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10401   else
10402     emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10403
10404   cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10405   test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10406   emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10407   DONE;
10408 })
10409
10410 (define_insn "stack_protect_test<mode>"
10411   [(set (reg:CCZ CC_REGNUM)
10412         (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10413                      (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10414   ""
10415   "clc\t%O0(%G0,%R0),%S1"
10416   [(set_attr "op_type" "SS")])
10417
10418 ; This is used in s390_emit_prologue in order to prevent insns
10419 ; adjusting the stack pointer to be moved over insns writing stack
10420 ; slots using a copy of the stack pointer in a different register.
10421 (define_insn "stack_tie"
10422   [(set (match_operand:BLK 0 "memory_operand" "+m")
10423         (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10424   ""
10425   ""
10426   [(set_attr "length" "0")])
10427
10428
10429 ;
10430 ; Data prefetch patterns
10431 ;
10432
10433 (define_insn "prefetch"
10434   [(prefetch (match_operand 0    "address_operand"   "ZQZRZSZT,X")
10435              (match_operand:SI 1 "const_int_operand" "       n,n")
10436              (match_operand:SI 2 "const_int_operand" "       n,n"))]
10437   "TARGET_Z10"
10438 {
10439   switch (which_alternative)
10440     {
10441       case 0:
10442         return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10443       case 1:
10444         if (larl_operand (operands[0], Pmode))
10445           return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10446       default:
10447
10448         /* This might be reached for symbolic operands with an odd
10449            addend.  We simply omit the prefetch for such rare cases.  */
10450
10451         return "";
10452      }
10453 }
10454   [(set_attr "type" "load,larl")
10455    (set_attr "op_type" "RXY,RIL")
10456    (set_attr "z10prop" "z10_super")
10457    (set_attr "z196prop" "z196_alone")])
10458
10459
10460 ;
10461 ; Byte swap instructions
10462 ;
10463
10464 ; FIXME: There is also mvcin but we cannot use it since src and target
10465 ; may overlap.
10466 (define_insn "bswap<mode>2"
10467   [(set (match_operand:GPR 0            "nonimmediate_operand" "=d, d,RT")
10468         (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))]
10469   "TARGET_CPU_ZARCH"
10470   "@
10471    lrv<g>r\t%0,%1
10472    lrv<g>\t%0,%1
10473    strv<g>\t%1,%0"
10474   [(set_attr "type" "*,load,store")
10475    (set_attr "op_type" "RRE,RXY,RXY")
10476    (set_attr "z10prop" "z10_super")])
10477
10478 (define_insn "bswaphi2"
10479   [(set (match_operand:HI 0           "nonimmediate_operand" "=d, d,RT")
10480         (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))]
10481   "TARGET_CPU_ZARCH"
10482   "@
10483    #
10484    lrvh\t%0,%1
10485    strvh\t%1,%0"
10486   [(set_attr "type" "*,load,store")
10487    (set_attr "op_type" "RRE,RXY,RXY")
10488    (set_attr "z10prop" "z10_super")])
10489
10490 (define_split
10491   [(set (match_operand:HI 0           "register_operand" "")
10492         (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10493   "TARGET_CPU_ZARCH"
10494   [(set (match_dup 2) (bswap:SI (match_dup 3)))
10495    (set (match_dup 2) (lshiftrt:SI (match_dup 2)
10496                                    (const_int 16)))
10497    (set (match_dup 0) (subreg:HI (match_dup 2) 2))]
10498 {
10499   operands[2] = gen_reg_rtx (SImode);
10500   operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10501 })
10502
10503
10504 ;
10505 ; Population count instruction
10506 ;
10507
10508 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10509 ; portions and stores the result in the corresponding bytes in op0.
10510 (define_insn "*popcount<mode>"
10511   [(set (match_operand:INT 0 "register_operand" "=d")
10512         (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10513    (clobber (reg:CC CC_REGNUM))]
10514   "TARGET_Z196"
10515   "popcnt\t%0,%1"
10516   [(set_attr "op_type" "RRE")])
10517
10518 (define_expand "popcountdi2"
10519   [; popcnt op0, op1
10520    (parallel [(set (match_operand:DI 0 "register_operand" "")
10521                    (unspec:DI [(match_operand:DI 1 "register_operand")]
10522                               UNSPEC_POPCNT))
10523               (clobber (reg:CC CC_REGNUM))])
10524    ; sllg op2, op0, 32
10525    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10526    ; agr op0, op2
10527    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10528               (clobber (reg:CC CC_REGNUM))])
10529    ; sllg op2, op0, 16
10530    (set (match_dup 2)
10531         (ashift:DI (match_dup 0) (const_int 16)))
10532    ; agr op0, op2
10533    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10534               (clobber (reg:CC CC_REGNUM))])
10535    ; sllg op2, op0, 8
10536    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10537    ; agr op0, op2
10538    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10539               (clobber (reg:CC CC_REGNUM))])
10540    ; srlg op0, op0, 56
10541    (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10542   "TARGET_Z196 && TARGET_64BIT"
10543   "operands[2] = gen_reg_rtx (DImode);")
10544
10545 (define_expand "popcountsi2"
10546   [; popcnt op0, op1
10547    (parallel [(set (match_operand:SI 0 "register_operand" "")
10548                    (unspec:SI [(match_operand:SI 1 "register_operand")]
10549                               UNSPEC_POPCNT))
10550               (clobber (reg:CC CC_REGNUM))])
10551    ; sllk op2, op0, 16
10552    (set (match_dup 2)
10553         (ashift:SI (match_dup 0) (const_int 16)))
10554    ; ar op0, op2
10555    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10556               (clobber (reg:CC CC_REGNUM))])
10557    ; sllk op2, op0, 8
10558    (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10559    ; ar op0, op2
10560    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10561               (clobber (reg:CC CC_REGNUM))])
10562    ; srl op0, op0, 24
10563    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10564   "TARGET_Z196"
10565   "operands[2] = gen_reg_rtx (SImode);")
10566
10567 (define_expand "popcounthi2"
10568   [; popcnt op0, op1
10569    (parallel [(set (match_operand:HI 0 "register_operand" "")
10570                    (unspec:HI [(match_operand:HI 1 "register_operand")]
10571                               UNSPEC_POPCNT))
10572               (clobber (reg:CC CC_REGNUM))])
10573    ; sllk op2, op0, 8
10574    (set (match_dup 2)
10575         (ashift:SI (match_dup 0) (const_int 8)))
10576    ; ar op0, op2
10577    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10578               (clobber (reg:CC CC_REGNUM))])
10579    ; srl op0, op0, 8
10580    (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10581   "TARGET_Z196"
10582   "operands[2] = gen_reg_rtx (SImode);")
10583
10584 (define_expand "popcountqi2"
10585   [; popcnt op0, op1
10586    (parallel [(set (match_operand:QI 0 "register_operand" "")
10587                    (unspec:QI [(match_operand:QI 1 "register_operand")]
10588                               UNSPEC_POPCNT))
10589               (clobber (reg:CC CC_REGNUM))])]
10590   "TARGET_Z196"
10591   "")
10592
10593 ;;
10594 ;;- Copy sign instructions
10595 ;;
10596
10597 (define_insn "copysign<mode>3"
10598   [(set (match_operand:FP 0 "register_operand" "=f")
10599       (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10600                   (match_operand:FP 2 "register_operand" "f")]
10601                   UNSPEC_COPYSIGN))]
10602   "TARGET_Z196"
10603   "cpsdr\t%0,%2,%1"
10604   [(set_attr "op_type"  "RRF")
10605    (set_attr "type"     "fsimp<mode>")])
10606
10607
10608 ;;
10609 ;;- Transactional execution instructions
10610 ;;
10611
10612 ; This splitter helps combine to make use of CC directly when
10613 ; comparing the integer result of a tbegin builtin with a constant.
10614 ; The unspec is already removed by canonicalize_comparison. So this
10615 ; splitters only job is to turn the PARALLEL into separate insns
10616 ; again.  Unfortunately this only works with the very first cc/int
10617 ; compare since combine is not able to deal with data flow across
10618 ; basic block boundaries.
10619
10620 ; It needs to be an insn pattern as well since combine does not apply
10621 ; the splitter directly.  Combine would only use it if it actually
10622 ; would reduce the number of instructions.
10623 (define_insn_and_split "*ccraw_to_int"
10624   [(set (pc)
10625         (if_then_else
10626          (match_operator 0 "s390_eqne_operator"
10627                          [(reg:CCRAW CC_REGNUM)
10628                           (match_operand 1 "const_int_operand" "")])
10629          (label_ref (match_operand 2 "" ""))
10630          (pc)))
10631    (set (match_operand:SI 3 "register_operand" "=d")
10632         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10633   ""
10634   "#"
10635   ""
10636   [(set (match_dup 3)
10637         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10638    (set (pc)
10639         (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10640                       (label_ref (match_dup 2))
10641                       (pc)))]
10642   "")
10643
10644 ; Non-constrained transaction begin
10645
10646 (define_expand "tbegin"
10647   [(match_operand:SI 0 "register_operand" "")
10648    (match_operand:BLK 1 "memory_operand" "")]
10649   "TARGET_HTM"
10650 {
10651   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10652   DONE;
10653 })
10654
10655 (define_expand "tbegin_nofloat"
10656   [(match_operand:SI 0 "register_operand" "")
10657    (match_operand:BLK 1 "memory_operand" "")]
10658   "TARGET_HTM"
10659 {
10660   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10661   DONE;
10662 })
10663
10664 (define_expand "tbegin_retry"
10665   [(match_operand:SI 0 "register_operand" "")
10666    (match_operand:BLK 1 "memory_operand" "")
10667    (match_operand:SI 2 "general_operand" "")]
10668   "TARGET_HTM"
10669 {
10670   s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10671   DONE;
10672 })
10673
10674 (define_expand "tbegin_retry_nofloat"
10675   [(match_operand:SI 0 "register_operand" "")
10676    (match_operand:BLK 1 "memory_operand" "")
10677    (match_operand:SI 2 "general_operand" "")]
10678   "TARGET_HTM"
10679 {
10680   s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10681   DONE;
10682 })
10683
10684 ; Clobber VRs since they don't get restored
10685 (define_insn "tbegin_1_z13"
10686   [(set (reg:CCRAW CC_REGNUM)
10687         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10688                                UNSPECV_TBEGIN))
10689    (set (match_operand:BLK 1 "memory_operand" "=Q")
10690         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10691    (clobber (reg:TI 16)) (clobber (reg:TI 38))
10692    (clobber (reg:TI 17)) (clobber (reg:TI 39))
10693    (clobber (reg:TI 18)) (clobber (reg:TI 40))
10694    (clobber (reg:TI 19)) (clobber (reg:TI 41))
10695    (clobber (reg:TI 20)) (clobber (reg:TI 42))
10696    (clobber (reg:TI 21)) (clobber (reg:TI 43))
10697    (clobber (reg:TI 22)) (clobber (reg:TI 44))
10698    (clobber (reg:TI 23)) (clobber (reg:TI 45))
10699    (clobber (reg:TI 24)) (clobber (reg:TI 46))
10700    (clobber (reg:TI 25)) (clobber (reg:TI 47))
10701    (clobber (reg:TI 26)) (clobber (reg:TI 48))
10702    (clobber (reg:TI 27)) (clobber (reg:TI 49))
10703    (clobber (reg:TI 28)) (clobber (reg:TI 50))
10704    (clobber (reg:TI 29)) (clobber (reg:TI 51))
10705    (clobber (reg:TI 30)) (clobber (reg:TI 52))
10706    (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10707 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10708 ; not supposed to be used for immediates (see genpreds.c).
10709   "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10710   "tbegin\t%1,%x0"
10711   [(set_attr "op_type" "SIL")])
10712
10713 (define_insn "tbegin_1"
10714   [(set (reg:CCRAW CC_REGNUM)
10715         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10716                                UNSPECV_TBEGIN))
10717    (set (match_operand:BLK 1 "memory_operand" "=Q")
10718         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10719    (clobber (reg:DF 16))
10720    (clobber (reg:DF 17))
10721    (clobber (reg:DF 18))
10722    (clobber (reg:DF 19))
10723    (clobber (reg:DF 20))
10724    (clobber (reg:DF 21))
10725    (clobber (reg:DF 22))
10726    (clobber (reg:DF 23))
10727    (clobber (reg:DF 24))
10728    (clobber (reg:DF 25))
10729    (clobber (reg:DF 26))
10730    (clobber (reg:DF 27))
10731    (clobber (reg:DF 28))
10732    (clobber (reg:DF 29))
10733    (clobber (reg:DF 30))
10734    (clobber (reg:DF 31))]
10735 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10736 ; not supposed to be used for immediates (see genpreds.c).
10737   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10738   "tbegin\t%1,%x0"
10739   [(set_attr "op_type" "SIL")])
10740
10741 ; Same as above but without the FPR clobbers
10742 (define_insn "tbegin_nofloat_1"
10743   [(set (reg:CCRAW CC_REGNUM)
10744         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10745                                UNSPECV_TBEGIN))
10746    (set (match_operand:BLK 1 "memory_operand" "=Q")
10747         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10748   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10749   "tbegin\t%1,%x0"
10750   [(set_attr "op_type" "SIL")])
10751
10752
10753 ; Constrained transaction begin
10754
10755 (define_expand "tbeginc"
10756   [(set (reg:CCRAW CC_REGNUM)
10757         (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10758                                UNSPECV_TBEGINC))]
10759   "TARGET_HTM"
10760   "")
10761
10762 (define_insn "*tbeginc_1"
10763   [(set (reg:CCRAW CC_REGNUM)
10764         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10765                                UNSPECV_TBEGINC))]
10766   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10767   "tbeginc\t0,%x0"
10768   [(set_attr "op_type" "SIL")])
10769
10770 ; Transaction end
10771
10772 (define_expand "tend"
10773   [(set (reg:CCRAW CC_REGNUM)
10774         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10775    (set (match_operand:SI 0 "register_operand" "")
10776         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10777   "TARGET_HTM"
10778   "")
10779
10780 (define_insn "*tend_1"
10781   [(set (reg:CCRAW CC_REGNUM)
10782         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10783   "TARGET_HTM"
10784   "tend"
10785   [(set_attr "op_type" "S")])
10786
10787 ; Transaction abort
10788
10789 (define_expand "tabort"
10790   [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10791                     UNSPECV_TABORT)]
10792   "TARGET_HTM && operands != NULL"
10793 {
10794   if (CONST_INT_P (operands[0])
10795       && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10796     {
10797       error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10798              ".  Values in range 0 through 255 are reserved.",
10799              INTVAL (operands[0]));
10800       FAIL;
10801     }
10802 })
10803
10804 (define_insn "*tabort_1"
10805   [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10806                     UNSPECV_TABORT)]
10807   "TARGET_HTM && operands != NULL"
10808   "tabort\t%Y0"
10809   [(set_attr "op_type" "S")])
10810
10811 ; Transaction extract nesting depth
10812
10813 (define_insn "etnd"
10814   [(set (match_operand:SI 0 "register_operand" "=d")
10815         (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10816   "TARGET_HTM"
10817   "etnd\t%0"
10818   [(set_attr "op_type" "RRE")])
10819
10820 ; Non-transactional store
10821
10822 (define_insn "ntstg"
10823   [(set (match_operand:DI 0 "memory_operand" "=RT")
10824         (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10825                             UNSPECV_NTSTG))]
10826   "TARGET_HTM"
10827   "ntstg\t%1,%0"
10828   [(set_attr "op_type" "RXY")])
10829
10830 ; Transaction perform processor assist
10831
10832 (define_expand "tx_assist"
10833   [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10834                      (reg:SI GPR0_REGNUM)
10835                      (const_int 1)]
10836                     UNSPECV_PPA)]
10837   "TARGET_HTM"
10838   "")
10839
10840 (define_insn "*ppa"
10841   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10842                      (match_operand:SI 1 "register_operand" "d")
10843                      (match_operand 2 "const_int_operand" "I")]
10844                     UNSPECV_PPA)]
10845   "TARGET_HTM && INTVAL (operands[2]) < 16"
10846   "ppa\t%0,%1,%2"
10847   [(set_attr "op_type" "RRF")])
10848
10849
10850 ; Set and get floating point control register
10851
10852 (define_insn "sfpc"
10853   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10854                     UNSPECV_SFPC)]
10855   "TARGET_HARD_FLOAT"
10856   "sfpc\t%0")
10857
10858 (define_insn "efpc"
10859   [(set (match_operand:SI 0 "register_operand" "=d")
10860         (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10861   "TARGET_HARD_FLOAT"
10862   "efpc\t%0")
10863
10864
10865 ; Load count to block boundary
10866
10867 (define_insn "lcbb"
10868   [(set (match_operand:SI             0 "register_operand"  "=d")
10869         (unspec:SI [(match_operand:SI 1 "address_operand" "ZQZR")
10870                     (match_operand:SI 2 "immediate_operand"  "C")] UNSPEC_LCBB))
10871    (clobber (reg:CC CC_REGNUM))]
10872   "TARGET_Z13"
10873   "lcbb\t%0,%1,%b2"
10874   [(set_attr "op_type" "VRX")])