1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; GOT/PLT and lt-relative accesses
94 ; TLS relocation specifiers
110 ; Stack Smashing Protector
114 ; Test Data Class (TDC)
126 UNSPEC_FPINT_NEARBYINT
131 ;; UNSPEC_VOLATILE usage
134 (define_c_enum "unspecv" [
156 ; Hotpatching (unremovable NOPs)
161 ; Transactional Execution support
171 ; Set and get floating point control register
180 ; Registers with special meaning
184 ; Sibling call register.
186 ; Literal pool base register.
188 ; Return address register.
190 ; Condition code register.
192 ; Thread local storage pointer register.
196 ; Hardware register names
200 ; General purpose registers
202 ; Floating point registers.
222 ;; PFPO GPR0 argument format
227 ; PFPO operation type
228 (PFPO_CONVERT 0x1000000)
230 (PFPO_OP_TYPE_SF 0x5)
231 (PFPO_OP_TYPE_DF 0x6)
232 (PFPO_OP_TYPE_TF 0x7)
233 (PFPO_OP_TYPE_SD 0x8)
234 (PFPO_OP_TYPE_DD 0x9)
235 (PFPO_OP_TYPE_TD 0xa)
236 ; Bitposition of operand types
237 (PFPO_OP0_TYPE_SHIFT 16)
238 (PFPO_OP1_TYPE_SHIFT 8)
241 ; Immediate operands for tbegin and tbeginc
242 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
243 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
245 ;; Instruction operand type as used in the Principles of Operation.
246 ;; Used to determine defaults for length and other attribute values.
248 (define_attr "op_type"
249 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
252 ;; Instruction type attribute used for scheduling.
254 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
255 cs,vs,store,sem,idiv,
256 imulhi,imulsi,imuldi,
257 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
258 floadtf,floaddf,floadsf,fstoredf,fstoresf,
259 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
260 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
262 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
263 itoftf, itofdf, itofsf, itofdd, itoftd,
264 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
265 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
267 (cond [(eq_attr "op_type" "NN") (const_string "other")
268 (eq_attr "op_type" "SS") (const_string "cs")]
269 (const_string "integer")))
271 ;; Another attribute used for scheduling purposes:
272 ;; agen: Instruction uses the address generation unit
273 ;; reg: Instruction does not use the agen unit
275 (define_attr "atype" "agen,reg"
276 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
278 (const_string "agen")))
280 ;; Properties concerning Z10 execution grouping and value forwarding.
281 ;; z10_super: instruction is superscalar.
282 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
283 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
284 ;; target register. It can forward this value to a second instruction that reads
285 ;; the same register if that second instruction is issued in the same group.
286 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
287 ;; instruction in the S pipe writes to the register, then the T instruction
288 ;; can immediately read the new value.
289 ;; z10_fr: union of Z10_fwd and z10_rec.
290 ;; z10_c: second operand of instruction is a register and read with complemented bits.
292 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
295 (define_attr "z10prop" "none,
296 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
297 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
299 z10_fr, z10_fr_A3, z10_fr_E1,
301 (const_string "none"))
303 ;; Properties concerning Z196 decoding
304 ;; z196_alone: must group alone
305 ;; z196_end: ends a group
306 ;; z196_cracked: instruction is cracked or expanded
307 (define_attr "z196prop" "none,
308 z196_alone, z196_ends,
310 (const_string "none"))
312 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
316 (define_attr "length" ""
317 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
318 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
322 ;; Processor type. This attribute must exactly match the processor_type
323 ;; enumeration in s390.h. The current machine description does not
324 ;; distinguish between g5 and g6, but there are differences between the two
325 ;; CPUs could in theory be modeled.
327 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
328 (const (symbol_ref "s390_tune_attr")))
330 (define_attr "cpu_facility"
331 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
332 (const_string "standard"))
334 (define_attr "enabled" ""
335 (cond [(eq_attr "cpu_facility" "standard")
338 (and (eq_attr "cpu_facility" "ieee")
339 (match_test "TARGET_CPU_IEEE_FLOAT"))
342 (and (eq_attr "cpu_facility" "zarch")
343 (match_test "TARGET_ZARCH"))
346 (and (eq_attr "cpu_facility" "longdisp")
347 (match_test "TARGET_LONG_DISPLACEMENT"))
350 (and (eq_attr "cpu_facility" "extimm")
351 (match_test "TARGET_EXTIMM"))
354 (and (eq_attr "cpu_facility" "dfp")
355 (match_test "TARGET_DFP"))
358 (and (eq_attr "cpu_facility" "cpu_zarch")
359 (match_test "TARGET_CPU_ZARCH"))
362 (and (eq_attr "cpu_facility" "z10")
363 (match_test "TARGET_Z10"))
366 (and (eq_attr "cpu_facility" "z196")
367 (match_test "TARGET_Z196"))
370 (and (eq_attr "cpu_facility" "zEC12")
371 (match_test "TARGET_ZEC12"))
374 (and (eq_attr "cpu_facility" "vec")
375 (match_test "TARGET_VX"))
379 ;; Pipeline description for z900. For lack of anything better,
380 ;; this description is also used for the g5 and g6.
383 ;; Pipeline description for z990, z9-109 and z9-ec.
386 ;; Pipeline description for z10
389 ;; Pipeline description for z196
392 ;; Pipeline description for zEC12
396 (include "predicates.md")
398 ;; Constraint definitions
399 (include "constraints.md")
406 ;; These mode iterators allow floating point patterns to be generated from the
408 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
409 (SD "TARGET_HARD_DFP")])
410 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
411 (define_mode_iterator FPALL [TF DF SF TD DD SD])
412 (define_mode_iterator BFP [TF DF SF])
413 (define_mode_iterator DFP [TD DD])
414 (define_mode_iterator DFP_ALL [TD DD SD])
415 (define_mode_iterator DSF [DF SF])
416 (define_mode_iterator SD_SF [SF SD])
417 (define_mode_iterator DD_DF [DF DD])
418 (define_mode_iterator TD_TF [TF TD])
420 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
421 ;; from the same template.
422 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
423 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
424 (define_mode_iterator DSI [DI SI])
425 (define_mode_iterator TDI [TI DI])
427 ;; These mode iterators allow :P to be used for patterns that operate on
428 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
429 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
431 ;; These macros refer to the actual word_mode of the configuration.
432 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
433 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
434 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
436 ;; Used by the umul pattern to express modes having half the size.
437 (define_mode_attr DWH [(TI "DI") (DI "SI")])
438 (define_mode_attr dwh [(TI "di") (DI "si")])
440 ;; This mode iterator allows the QI and HI patterns to be defined from
441 ;; the same template.
442 (define_mode_iterator HQI [HI QI])
444 ;; This mode iterator allows the integer patterns to be defined from the
446 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
447 (define_mode_iterator INTALL [TI DI SI HI QI])
448 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
450 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
451 ;; the same template.
452 (define_code_iterator SHIFT [ashift lshiftrt])
454 ;; This iterator allows r[ox]sbg to be defined with the same template
455 (define_code_iterator IXOR [ior xor])
457 ;; This iterator is used to expand the patterns for the nearest
458 ;; integer functions.
459 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
460 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
461 UNSPEC_FPINT_NEARBYINT])
462 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
463 (UNSPEC_FPINT_BTRUNC "btrunc")
464 (UNSPEC_FPINT_ROUND "round")
465 (UNSPEC_FPINT_CEIL "ceil")
466 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
467 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
468 (UNSPEC_FPINT_BTRUNC "5")
469 (UNSPEC_FPINT_ROUND "1")
470 (UNSPEC_FPINT_CEIL "6")
471 (UNSPEC_FPINT_NEARBYINT "0")])
473 ;; This iterator and attribute allow to combine most atomic operations.
474 (define_code_iterator ATOMIC [and ior xor plus minus mult])
475 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
476 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
477 (plus "add") (minus "sub") (mult "nand")])
478 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
480 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
481 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
482 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
484 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
485 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
487 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
489 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
490 ;; Likewise for "<RXe>".
491 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
492 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
494 ;; The decimal floating point variants of add, sub, div and mul support 3
495 ;; fp register operands. The following attributes allow to merge the bfp and
496 ;; dfp variants in a single insn definition.
498 ;; This attribute is used to set op_type accordingly.
499 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
500 (DD "RRR") (SD "RRR")])
502 ;; This attribute is used in the operand constraint list in order to have the
503 ;; first and the second operand match for bfp modes.
504 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
506 ;; This attribute is used in the operand list of the instruction to have an
507 ;; additional operand for the dfp instructions.
508 (define_mode_attr op1 [(TF "") (DF "") (SF "")
509 (TD "%1,") (DD "%1,") (SD "%1,")])
512 ;; This attribute is used in the operand constraint list
513 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
514 ;; TFmode values are represented by a fp register pair. Since the
515 ;; sign bit instructions only handle single source and target fp registers
516 ;; these instructions can only be used for TFmode values if the source and
517 ;; target operand uses the same fp register.
518 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
520 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
521 ;; This is used to disable the memory alternative in TFmode patterns.
522 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
524 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
525 ;; within instruction mnemonics.
526 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
528 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
529 ;; modes and to an empty string for bfp modes.
530 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
532 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
533 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
534 ;; version only operates on one register.
535 (define_mode_attr d0 [(DI "d") (SI "0")])
537 ;; In combination with d0 this allows to combine instructions of which the 31bit
538 ;; version only operates on one register. The DImode version needs an additional
539 ;; register for the assembler output.
540 (define_mode_attr 1 [(DI "%1,") (SI "")])
542 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
543 ;; 'ashift' and "srdl" in 'lshiftrt'.
544 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
546 ;; In SHIFT templates, this attribute holds the correct standard name for the
547 ;; pattern itself and the corresponding function calls.
548 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
550 ;; This attribute handles differences in the instruction 'type' and will result
551 ;; in "RRE" for DImode and "RR" for SImode.
552 (define_mode_attr E [(DI "E") (SI "")])
554 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
555 ;; to result in "RXY" for DImode and "RX" for SImode.
556 (define_mode_attr Y [(DI "Y") (SI "")])
558 ;; This attribute handles differences in the instruction 'type' and will result
559 ;; in "RSE" for TImode and "RS" for DImode.
560 (define_mode_attr TE [(TI "E") (DI "")])
562 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
563 ;; and "lcr" in SImode.
564 (define_mode_attr g [(DI "g") (SI "")])
566 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
567 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
568 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
569 ;; variant for long displacements.
570 (define_mode_attr y [(DI "g") (SI "y")])
572 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
573 ;; and "cds" in DImode.
574 (define_mode_attr tg [(TI "g") (DI "")])
576 ;; In TDI templates, a string like "c<d>sg".
577 (define_mode_attr td [(TI "d") (DI "")])
579 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
580 ;; and "cfdbr" in SImode.
581 (define_mode_attr gf [(DI "g") (SI "f")])
583 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
584 ;; and sllk for SI. This way it is possible to merge the new z196 SI
585 ;; 3 operands shift instructions into the existing patterns.
586 (define_mode_attr gk [(DI "g") (SI "k")])
588 ;; ICM mask required to load MODE value into the lowest subreg
589 ;; of a SImode register.
590 (define_mode_attr icm_lo [(HI "3") (QI "1")])
592 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
593 ;; HImode and "llgc" in QImode.
594 (define_mode_attr hc [(HI "h") (QI "c")])
596 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
598 (define_mode_attr DBL [(DI "TI") (SI "DI")])
600 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
601 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
602 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
604 ;; Maximum unsigned integer that fits in MODE.
605 (define_mode_attr max_uint [(HI "65535") (QI "255")])
607 ;; Start and end field computations for RISBG et al.
608 (define_mode_attr bfstart [(DI "s") (SI "t")])
609 (define_mode_attr bfend [(DI "e") (SI "f")])
611 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
612 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
614 ;; Allow return and simple_return to be defined from a single template.
615 (define_code_iterator ANY_RETURN [return simple_return])
618 ;;- Compare instructions.
621 ; Test-under-Mask instructions
623 (define_insn "*tmqi_mem"
624 [(set (reg CC_REGNUM)
625 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
626 (match_operand:QI 1 "immediate_operand" "n,n"))
627 (match_operand:QI 2 "immediate_operand" "n,n")))]
628 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
632 [(set_attr "op_type" "SI,SIY")
633 (set_attr "z10prop" "z10_super,z10_super")])
635 (define_insn "*tmdi_reg"
636 [(set (reg CC_REGNUM)
637 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
638 (match_operand:DI 1 "immediate_operand"
639 "N0HD0,N1HD0,N2HD0,N3HD0"))
640 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
642 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
643 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
649 [(set_attr "op_type" "RI")
650 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
652 (define_insn "*tmsi_reg"
653 [(set (reg CC_REGNUM)
654 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
655 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
656 (match_operand:SI 2 "immediate_operand" "n,n")))]
657 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
658 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
662 [(set_attr "op_type" "RI")
663 (set_attr "z10prop" "z10_super,z10_super")])
665 (define_insn "*tm<mode>_full"
666 [(set (reg CC_REGNUM)
667 (compare (match_operand:HQI 0 "register_operand" "d")
668 (match_operand:HQI 1 "immediate_operand" "n")))]
669 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
671 [(set_attr "op_type" "RI")
672 (set_attr "z10prop" "z10_super")])
676 ; Load-and-Test instructions
679 ; tst(di|si) instruction pattern(s).
681 (define_insn "*tstdi_sign"
682 [(set (reg CC_REGNUM)
686 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
687 (const_int 32)) (const_int 32))
688 (match_operand:DI 1 "const0_operand" "")))
689 (set (match_operand:DI 2 "register_operand" "=d,d")
690 (sign_extend:DI (match_dup 0)))]
691 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
694 [(set_attr "op_type" "RRE,RXY")
695 (set_attr "cpu_facility" "*,z10")
696 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
699 (define_insn "*tst<mode>_extimm"
700 [(set (reg CC_REGNUM)
701 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
702 (match_operand:GPR 1 "const0_operand" "")))
703 (set (match_operand:GPR 2 "register_operand" "=d,d")
705 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
709 [(set_attr "op_type" "RR<E>,RXY")
710 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
713 (define_insn "*tst<mode>_cconly_extimm"
714 [(set (reg CC_REGNUM)
715 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
716 (match_operand:GPR 1 "const0_operand" "")))
717 (clobber (match_scratch:GPR 2 "=X,d"))]
718 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
722 [(set_attr "op_type" "RR<E>,RXY")
723 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
725 (define_insn "*tstdi"
726 [(set (reg CC_REGNUM)
727 (compare (match_operand:DI 0 "register_operand" "d")
728 (match_operand:DI 1 "const0_operand" "")))
729 (set (match_operand:DI 2 "register_operand" "=d")
731 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
733 [(set_attr "op_type" "RRE")
734 (set_attr "z10prop" "z10_fr_E1")])
736 (define_insn "*tstsi"
737 [(set (reg CC_REGNUM)
738 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
739 (match_operand:SI 1 "const0_operand" "")))
740 (set (match_operand:SI 2 "register_operand" "=d,d,d")
742 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
747 [(set_attr "op_type" "RR,RS,RSY")
748 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
750 (define_insn "*tstsi_cconly"
751 [(set (reg CC_REGNUM)
752 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
753 (match_operand:SI 1 "const0_operand" "")))
754 (clobber (match_scratch:SI 2 "=X,d,d"))]
755 "s390_match_ccmode(insn, CCSmode)"
760 [(set_attr "op_type" "RR,RS,RSY")
761 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
763 (define_insn "*tstdi_cconly_31"
764 [(set (reg CC_REGNUM)
765 (compare (match_operand:DI 0 "register_operand" "d")
766 (match_operand:DI 1 "const0_operand" "")))]
767 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
769 [(set_attr "op_type" "RS")
770 (set_attr "atype" "reg")])
773 (define_insn "*tst<mode>_cconly2"
774 [(set (reg CC_REGNUM)
775 (compare (match_operand:GPR 0 "register_operand" "d")
776 (match_operand:GPR 1 "const0_operand" "")))]
777 "s390_match_ccmode(insn, CCSmode)"
779 [(set_attr "op_type" "RR<E>")
780 (set_attr "z10prop" "z10_fr_E1")])
782 ; tst(hi|qi) instruction pattern(s).
784 (define_insn "*tst<mode>CCT"
785 [(set (reg CC_REGNUM)
786 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
787 (match_operand:HQI 1 "const0_operand" "")))
788 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
790 "s390_match_ccmode(insn, CCTmode)"
793 icmy\t%2,<icm_lo>,%S0
795 [(set_attr "op_type" "RS,RSY,RI")
796 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
798 (define_insn "*tsthiCCT_cconly"
799 [(set (reg CC_REGNUM)
800 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
801 (match_operand:HI 1 "const0_operand" "")))
802 (clobber (match_scratch:HI 2 "=d,d,X"))]
803 "s390_match_ccmode(insn, CCTmode)"
808 [(set_attr "op_type" "RS,RSY,RI")
809 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
811 (define_insn "*tstqiCCT_cconly"
812 [(set (reg CC_REGNUM)
813 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
814 (match_operand:QI 1 "const0_operand" "")))]
815 "s390_match_ccmode(insn, CCTmode)"
820 [(set_attr "op_type" "SI,SIY,RI")
821 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
823 (define_insn "*tst<mode>"
824 [(set (reg CC_REGNUM)
825 (compare (match_operand:HQI 0 "s_operand" "Q,S")
826 (match_operand:HQI 1 "const0_operand" "")))
827 (set (match_operand:HQI 2 "register_operand" "=d,d")
829 "s390_match_ccmode(insn, CCSmode)"
832 icmy\t%2,<icm_lo>,%S0"
833 [(set_attr "op_type" "RS,RSY")
834 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
836 (define_insn "*tst<mode>_cconly"
837 [(set (reg CC_REGNUM)
838 (compare (match_operand:HQI 0 "s_operand" "Q,S")
839 (match_operand:HQI 1 "const0_operand" "")))
840 (clobber (match_scratch:HQI 2 "=d,d"))]
841 "s390_match_ccmode(insn, CCSmode)"
844 icmy\t%2,<icm_lo>,%S0"
845 [(set_attr "op_type" "RS,RSY")
846 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
849 ; Compare (equality) instructions
851 (define_insn "*cmpdi_cct"
852 [(set (reg CC_REGNUM)
853 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
854 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
855 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
862 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
863 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
865 (define_insn "*cmpsi_cct"
866 [(set (reg CC_REGNUM)
867 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
868 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
869 "s390_match_ccmode (insn, CCTmode)"
877 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
878 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
880 ; Compare (signed) instructions
882 (define_insn "*cmpdi_ccs_sign"
883 [(set (reg CC_REGNUM)
884 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
886 (match_operand:DI 0 "register_operand" "d, d,d")))]
887 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
892 [(set_attr "op_type" "RRE,RXY,RIL")
893 (set_attr "z10prop" "z10_c,*,*")
894 (set_attr "type" "*,*,larl")])
898 (define_insn "*cmpsi_ccs_sign"
899 [(set (reg CC_REGNUM)
900 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
901 (match_operand:SI 0 "register_operand" "d,d,d")))]
902 "s390_match_ccmode(insn, CCSRmode)"
907 [(set_attr "op_type" "RX,RXY,RIL")
908 (set_attr "cpu_facility" "*,*,z10")
909 (set_attr "type" "*,*,larl")
910 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
912 (define_insn "*cmphi_ccs_z10"
913 [(set (reg CC_REGNUM)
914 (compare (match_operand:HI 0 "s_operand" "Q")
915 (match_operand:HI 1 "immediate_operand" "K")))]
916 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
918 [(set_attr "op_type" "SIL")
919 (set_attr "z196prop" "z196_cracked")])
921 (define_insn "*cmpdi_ccs_signhi_rl"
922 [(set (reg CC_REGNUM)
923 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
924 (match_operand:GPR 0 "register_operand" "d,d")))]
925 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
929 [(set_attr "op_type" "RXY,RIL")
930 (set_attr "type" "*,larl")])
932 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
933 (define_insn "*cmp<mode>_ccs"
934 [(set (reg CC_REGNUM)
935 (compare (match_operand:GPR 0 "nonimmediate_operand"
937 (match_operand:GPR 1 "general_operand"
939 "s390_match_ccmode(insn, CCSmode)"
948 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
949 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
950 (set_attr "type" "*,*,*,*,*,*,larl")
951 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
954 ; Compare (unsigned) instructions
956 (define_insn "*cmpsi_ccu_zerohi_rlsi"
957 [(set (reg CC_REGNUM)
958 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
959 "larl_operand" "X")))
960 (match_operand:SI 0 "register_operand" "d")))]
961 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
963 [(set_attr "op_type" "RIL")
964 (set_attr "type" "larl")
965 (set_attr "z10prop" "z10_super")])
968 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
969 [(set (reg CC_REGNUM)
970 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
971 "larl_operand" "X")))
972 (match_operand:GPR 0 "register_operand" "d")))]
973 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
975 [(set_attr "op_type" "RIL")
976 (set_attr "type" "larl")
977 (set_attr "z10prop" "z10_super")])
979 (define_insn "*cmpdi_ccu_zero"
980 [(set (reg CC_REGNUM)
981 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
983 (match_operand:DI 0 "register_operand" "d, d,d")))]
984 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
989 [(set_attr "op_type" "RRE,RXY,RIL")
990 (set_attr "cpu_facility" "*,*,z10")
991 (set_attr "type" "*,*,larl")
992 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
994 (define_insn "*cmpdi_ccu"
995 [(set (reg CC_REGNUM)
996 (compare (match_operand:DI 0 "nonimmediate_operand"
998 (match_operand:DI 1 "general_operand"
999 "d,Op,b,D,RT,BQ,Q")))]
1000 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1009 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1010 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1011 (set_attr "type" "*,*,larl,*,*,*,*")
1012 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1014 (define_insn "*cmpsi_ccu"
1015 [(set (reg CC_REGNUM)
1016 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1017 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1018 "s390_match_ccmode (insn, CCUmode)"
1028 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1029 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1030 (set_attr "type" "*,*,larl,*,*,*,*,*")
1031 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1033 (define_insn "*cmphi_ccu"
1034 [(set (reg CC_REGNUM)
1035 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1036 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1037 "s390_match_ccmode (insn, CCUmode)
1038 && !register_operand (operands[1], HImode)"
1045 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1046 (set_attr "cpu_facility" "*,*,z10,*,*")
1047 (set_attr "z10prop" "*,*,z10_super,*,*")])
1049 (define_insn "*cmpqi_ccu"
1050 [(set (reg CC_REGNUM)
1051 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1052 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1053 "s390_match_ccmode (insn, CCUmode)
1054 && !register_operand (operands[1], QImode)"
1062 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1063 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1066 ; Block compare (CLC) instruction patterns.
1069 [(set (reg CC_REGNUM)
1070 (compare (match_operand:BLK 0 "memory_operand" "Q")
1071 (match_operand:BLK 1 "memory_operand" "Q")))
1072 (use (match_operand 2 "const_int_operand" "n"))]
1073 "s390_match_ccmode (insn, CCUmode)
1074 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1075 "clc\t%O0(%2,%R0),%S1"
1076 [(set_attr "op_type" "SS")])
1079 [(set (reg CC_REGNUM)
1080 (compare (match_operand 0 "memory_operand" "")
1081 (match_operand 1 "memory_operand" "")))]
1083 && s390_match_ccmode (insn, CCUmode)
1084 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1085 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1087 [(set (match_dup 0) (match_dup 1))
1088 (use (match_dup 2))])]
1090 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1091 operands[0] = adjust_address (operands[0], BLKmode, 0);
1092 operands[1] = adjust_address (operands[1], BLKmode, 0);
1094 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1095 operands[0], operands[1]);
1096 operands[0] = SET_DEST (PATTERN (curr_insn));
1100 ; (TF|DF|SF|TD|DD|SD) instructions
1102 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1103 (define_insn "*cmp<mode>_ccs_0"
1104 [(set (reg CC_REGNUM)
1105 (compare (match_operand:FP 0 "register_operand" "f")
1106 (match_operand:FP 1 "const0_operand" "")))]
1107 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1108 "lt<xde><bt>r\t%0,%0"
1109 [(set_attr "op_type" "RRE")
1110 (set_attr "type" "fsimp<mode>")])
1112 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1113 (define_insn "*cmp<mode>_ccs"
1114 [(set (reg CC_REGNUM)
1115 (compare (match_operand:FP 0 "register_operand" "f,f")
1116 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1117 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1121 [(set_attr "op_type" "RRE,RXE")
1122 (set_attr "type" "fsimp<mode>")])
1125 ; Compare and Branch instructions
1127 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1128 ; The following instructions do a complementary access of their second
1129 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1130 (define_insn "*cmp_and_br_signed_<mode>"
1132 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1133 [(match_operand:GPR 1 "register_operand" "d,d")
1134 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1135 (label_ref (match_operand 3 "" ""))
1137 (clobber (reg:CC CC_REGNUM))]
1138 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1140 if (get_attr_length (insn) == 6)
1141 return which_alternative ?
1142 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1144 return which_alternative ?
1145 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1147 [(set_attr "op_type" "RIE")
1148 (set_attr "type" "branch")
1149 (set_attr "z10prop" "z10_super_c,z10_super")
1150 (set (attr "length")
1151 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1152 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1153 ; 10 byte for cgr/jg
1155 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1156 ; The following instructions do a complementary access of their second
1157 ; operand (z10 only): clrj, clgrj, clr, clgr
1158 (define_insn "*cmp_and_br_unsigned_<mode>"
1160 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1161 [(match_operand:GPR 1 "register_operand" "d,d")
1162 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1163 (label_ref (match_operand 3 "" ""))
1165 (clobber (reg:CC CC_REGNUM))]
1166 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1168 if (get_attr_length (insn) == 6)
1169 return which_alternative ?
1170 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1172 return which_alternative ?
1173 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1175 [(set_attr "op_type" "RIE")
1176 (set_attr "type" "branch")
1177 (set_attr "z10prop" "z10_super_c,z10_super")
1178 (set (attr "length")
1179 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1180 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1181 ; 10 byte for clgr/jg
1183 ; And now the same two patterns as above but with a negated CC mask.
1185 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1186 ; The following instructions do a complementary access of their second
1187 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1188 (define_insn "*icmp_and_br_signed_<mode>"
1190 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1191 [(match_operand:GPR 1 "register_operand" "d,d")
1192 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1194 (label_ref (match_operand 3 "" ""))))
1195 (clobber (reg:CC CC_REGNUM))]
1196 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1198 if (get_attr_length (insn) == 6)
1199 return which_alternative ?
1200 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1202 return which_alternative ?
1203 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1205 [(set_attr "op_type" "RIE")
1206 (set_attr "type" "branch")
1207 (set_attr "z10prop" "z10_super_c,z10_super")
1208 (set (attr "length")
1209 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1210 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1211 ; 10 byte for cgr/jg
1213 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1214 ; The following instructions do a complementary access of their second
1215 ; operand (z10 only): clrj, clgrj, clr, clgr
1216 (define_insn "*icmp_and_br_unsigned_<mode>"
1218 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1219 [(match_operand:GPR 1 "register_operand" "d,d")
1220 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1222 (label_ref (match_operand 3 "" ""))))
1223 (clobber (reg:CC CC_REGNUM))]
1224 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1226 if (get_attr_length (insn) == 6)
1227 return which_alternative ?
1228 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1230 return which_alternative ?
1231 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1233 [(set_attr "op_type" "RIE")
1234 (set_attr "type" "branch")
1235 (set_attr "z10prop" "z10_super_c,z10_super")
1236 (set (attr "length")
1237 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1238 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1239 ; 10 byte for clgr/jg
1242 ;;- Move instructions.
1246 ; movti instruction pattern(s).
1249 (define_insn "movti"
1250 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1251 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1258 [(set_attr "op_type" "RSY,RSY,*,*")
1259 (set_attr "type" "lm,stm,*,*")])
1262 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1263 (match_operand:TI 1 "general_operand" ""))]
1264 "TARGET_ZARCH && reload_completed
1265 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1266 [(set (match_dup 2) (match_dup 4))
1267 (set (match_dup 3) (match_dup 5))]
1269 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1270 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1271 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1272 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1276 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1277 (match_operand:TI 1 "general_operand" ""))]
1278 "TARGET_ZARCH && reload_completed
1279 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1280 [(set (match_dup 2) (match_dup 4))
1281 (set (match_dup 3) (match_dup 5))]
1283 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1284 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1285 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1286 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1290 [(set (match_operand:TI 0 "register_operand" "")
1291 (match_operand:TI 1 "memory_operand" ""))]
1292 "TARGET_ZARCH && reload_completed
1293 && !s_operand (operands[1], VOIDmode)"
1294 [(set (match_dup 0) (match_dup 1))]
1296 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1297 addr = gen_lowpart (Pmode, addr);
1298 s390_load_address (addr, XEXP (operands[1], 0));
1299 operands[1] = replace_equiv_address (operands[1], addr);
1304 ; Patterns used for secondary reloads
1307 ; z10 provides move instructions accepting larl memory operands.
1308 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1309 ; These patterns are also used for unaligned SI and DI accesses.
1311 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1312 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1313 (match_operand:INTALL 1 "register_operand" "=d")
1314 (match_operand:P 2 "register_operand" "=&a")])]
1317 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1321 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1322 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1323 (match_operand:INTALL 1 "memory_operand" "")
1324 (match_operand:P 2 "register_operand" "=a")])]
1327 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1331 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1332 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1333 (match_operand:FPALL 1 "register_operand" "=d")
1334 (match_operand:P 2 "register_operand" "=&a")])]
1337 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1341 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1342 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1343 (match_operand:FPALL 1 "memory_operand" "")
1344 (match_operand:P 2 "register_operand" "=a")])]
1347 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1351 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1352 [(parallel [(match_operand:P 0 "register_operand" "=d")
1353 (match_operand:P 1 "larl_operand" "")
1354 (match_operand:P 2 "register_operand" "=a")])]
1357 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1361 ; Handles loading a PLUS (load address) expression
1363 (define_expand "reload<mode>_plus"
1364 [(parallel [(match_operand:P 0 "register_operand" "=a")
1365 (match_operand:P 1 "s390_plus_operand" "")
1366 (match_operand:P 2 "register_operand" "=&a")])]
1369 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1373 ; Handles assessing a non-offsetable memory address
1375 (define_expand "reload<mode>_nonoffmem_in"
1376 [(parallel [(match_operand 0 "register_operand" "")
1377 (match_operand 1 "" "")
1378 (match_operand:P 2 "register_operand" "=&a")])]
1381 gcc_assert (MEM_P (operands[1]));
1382 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1383 operands[1] = replace_equiv_address (operands[1], operands[2]);
1384 emit_move_insn (operands[0], operands[1]);
1388 (define_expand "reload<mode>_nonoffmem_out"
1389 [(parallel [(match_operand 0 "" "")
1390 (match_operand 1 "register_operand" "")
1391 (match_operand:P 2 "register_operand" "=&a")])]
1394 gcc_assert (MEM_P (operands[0]));
1395 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1396 operands[0] = replace_equiv_address (operands[0], operands[2]);
1397 emit_move_insn (operands[0], operands[1]);
1401 (define_expand "reload<mode>_PIC_addr"
1402 [(parallel [(match_operand 0 "register_operand" "=d")
1403 (match_operand 1 "larl_operand" "")
1404 (match_operand:P 2 "register_operand" "=a")])]
1407 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1408 emit_move_insn (operands[0], new_rtx);
1412 ; movdi instruction pattern(s).
1415 (define_expand "movdi"
1416 [(set (match_operand:DI 0 "general_operand" "")
1417 (match_operand:DI 1 "general_operand" ""))]
1420 /* Handle symbolic constants. */
1422 && (SYMBOLIC_CONST (operands[1])
1423 || (GET_CODE (operands[1]) == PLUS
1424 && XEXP (operands[1], 0) == pic_offset_table_rtx
1425 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1426 emit_symbolic_move (operands);
1429 (define_insn "*movdi_larl"
1430 [(set (match_operand:DI 0 "register_operand" "=d")
1431 (match_operand:DI 1 "larl_operand" "X"))]
1433 && !FP_REG_P (operands[0])"
1435 [(set_attr "op_type" "RIL")
1436 (set_attr "type" "larl")
1437 (set_attr "z10prop" "z10_super_A1")])
1439 (define_insn "*movdi_64"
1440 [(set (match_operand:DI 0 "nonimmediate_operand"
1441 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1442 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1443 (match_operand:DI 1 "general_operand"
1444 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1445 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1474 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1475 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1476 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1477 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1479 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1480 z10,*,*,*,*,*,longdisp,*,longdisp,
1482 (set_attr "z10prop" "z10_fwd_A1,
1511 [(set (match_operand:DI 0 "register_operand" "")
1512 (match_operand:DI 1 "register_operand" ""))]
1513 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1514 [(set (match_dup 2) (match_dup 3))
1515 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1516 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1517 "operands[2] = gen_lowpart (SImode, operands[0]);
1518 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1521 [(set (match_operand:DI 0 "register_operand" "")
1522 (match_operand:DI 1 "register_operand" ""))]
1523 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1524 && dead_or_set_p (insn, operands[1])"
1525 [(set (match_dup 3) (match_dup 2))
1526 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1527 (set (match_dup 4) (match_dup 2))]
1528 "operands[2] = gen_lowpart (SImode, operands[1]);
1529 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1532 [(set (match_operand:DI 0 "register_operand" "")
1533 (match_operand:DI 1 "register_operand" ""))]
1534 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1535 && !dead_or_set_p (insn, operands[1])"
1536 [(set (match_dup 3) (match_dup 2))
1537 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1538 (set (match_dup 4) (match_dup 2))
1539 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1540 "operands[2] = gen_lowpart (SImode, operands[1]);
1541 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1543 (define_insn "*movdi_31"
1544 [(set (match_operand:DI 0 "nonimmediate_operand"
1545 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1546 (match_operand:DI 1 "general_operand"
1547 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1562 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1563 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1564 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1566 ; For a load from a symbol ref we can use one of the target registers
1567 ; together with larl to load the address.
1569 [(set (match_operand:DI 0 "register_operand" "")
1570 (match_operand:DI 1 "memory_operand" ""))]
1571 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1572 && larl_operand (XEXP (operands[1], 0), SImode)"
1573 [(set (match_dup 2) (match_dup 3))
1574 (set (match_dup 0) (match_dup 1))]
1576 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1577 operands[3] = XEXP (operands[1], 0);
1578 operands[1] = replace_equiv_address (operands[1], operands[2]);
1582 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1583 (match_operand:DI 1 "general_operand" ""))]
1584 "!TARGET_ZARCH && reload_completed
1585 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1586 [(set (match_dup 2) (match_dup 4))
1587 (set (match_dup 3) (match_dup 5))]
1589 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1590 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1591 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1592 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1596 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1597 (match_operand:DI 1 "general_operand" ""))]
1598 "!TARGET_ZARCH && reload_completed
1599 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1600 [(set (match_dup 2) (match_dup 4))
1601 (set (match_dup 3) (match_dup 5))]
1603 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1604 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1605 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1606 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1610 [(set (match_operand:DI 0 "register_operand" "")
1611 (match_operand:DI 1 "memory_operand" ""))]
1612 "!TARGET_ZARCH && reload_completed
1613 && !FP_REG_P (operands[0])
1614 && !s_operand (operands[1], VOIDmode)"
1615 [(set (match_dup 0) (match_dup 1))]
1617 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1618 s390_load_address (addr, XEXP (operands[1], 0));
1619 operands[1] = replace_equiv_address (operands[1], addr);
1623 [(set (match_operand:DI 0 "register_operand" "")
1624 (mem:DI (match_operand 1 "address_operand" "")))]
1626 && !FP_REG_P (operands[0])
1627 && GET_CODE (operands[1]) == SYMBOL_REF
1628 && CONSTANT_POOL_ADDRESS_P (operands[1])
1629 && get_pool_mode (operands[1]) == DImode
1630 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1631 [(set (match_dup 0) (match_dup 2))]
1632 "operands[2] = get_pool_constant (operands[1]);")
1634 (define_insn "*la_64"
1635 [(set (match_operand:DI 0 "register_operand" "=d,d")
1636 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1641 [(set_attr "op_type" "RX,RXY")
1642 (set_attr "type" "la")
1643 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1647 [(set (match_operand:DI 0 "register_operand" "")
1648 (match_operand:QI 1 "address_operand" ""))
1649 (clobber (reg:CC CC_REGNUM))])]
1651 && preferred_la_operand_p (operands[1], const0_rtx)"
1652 [(set (match_dup 0) (match_dup 1))]
1656 [(set (match_operand:DI 0 "register_operand" "")
1657 (match_operand:DI 1 "register_operand" ""))
1660 (plus:DI (match_dup 0)
1661 (match_operand:DI 2 "nonmemory_operand" "")))
1662 (clobber (reg:CC CC_REGNUM))])]
1664 && !reg_overlap_mentioned_p (operands[0], operands[2])
1665 && preferred_la_operand_p (operands[1], operands[2])"
1666 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1670 ; movsi instruction pattern(s).
1673 (define_expand "movsi"
1674 [(set (match_operand:SI 0 "general_operand" "")
1675 (match_operand:SI 1 "general_operand" ""))]
1678 /* Handle symbolic constants. */
1680 && (SYMBOLIC_CONST (operands[1])
1681 || (GET_CODE (operands[1]) == PLUS
1682 && XEXP (operands[1], 0) == pic_offset_table_rtx
1683 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1684 emit_symbolic_move (operands);
1687 (define_insn "*movsi_larl"
1688 [(set (match_operand:SI 0 "register_operand" "=d")
1689 (match_operand:SI 1 "larl_operand" "X"))]
1690 "!TARGET_64BIT && TARGET_CPU_ZARCH
1691 && !FP_REG_P (operands[0])"
1693 [(set_attr "op_type" "RIL")
1694 (set_attr "type" "larl")
1695 (set_attr "z10prop" "z10_fwd_A1")])
1697 (define_insn "*movsi_zarch"
1698 [(set (match_operand:SI 0 "nonimmediate_operand"
1699 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1700 (match_operand:SI 1 "general_operand"
1701 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1726 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1727 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1728 (set_attr "type" "*,
1750 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1751 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1752 (set_attr "z10prop" "z10_fwd_A1,
1775 (define_insn "*movsi_esa"
1776 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1777 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1791 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1792 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1793 (set_attr "z10prop" "z10_fwd_A1,
1807 [(set (match_operand:SI 0 "register_operand" "")
1808 (mem:SI (match_operand 1 "address_operand" "")))]
1809 "!FP_REG_P (operands[0])
1810 && GET_CODE (operands[1]) == SYMBOL_REF
1811 && CONSTANT_POOL_ADDRESS_P (operands[1])
1812 && get_pool_mode (operands[1]) == SImode
1813 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1814 [(set (match_dup 0) (match_dup 2))]
1815 "operands[2] = get_pool_constant (operands[1]);")
1817 (define_insn "*la_31"
1818 [(set (match_operand:SI 0 "register_operand" "=d,d")
1819 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1820 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1824 [(set_attr "op_type" "RX,RXY")
1825 (set_attr "type" "la")
1826 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1830 [(set (match_operand:SI 0 "register_operand" "")
1831 (match_operand:QI 1 "address_operand" ""))
1832 (clobber (reg:CC CC_REGNUM))])]
1834 && preferred_la_operand_p (operands[1], const0_rtx)"
1835 [(set (match_dup 0) (match_dup 1))]
1839 [(set (match_operand:SI 0 "register_operand" "")
1840 (match_operand:SI 1 "register_operand" ""))
1843 (plus:SI (match_dup 0)
1844 (match_operand:SI 2 "nonmemory_operand" "")))
1845 (clobber (reg:CC CC_REGNUM))])]
1847 && !reg_overlap_mentioned_p (operands[0], operands[2])
1848 && preferred_la_operand_p (operands[1], operands[2])"
1849 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1852 (define_insn "*la_31_and"
1853 [(set (match_operand:SI 0 "register_operand" "=d,d")
1854 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1855 (const_int 2147483647)))]
1860 [(set_attr "op_type" "RX,RXY")
1861 (set_attr "type" "la")
1862 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1864 (define_insn_and_split "*la_31_and_cc"
1865 [(set (match_operand:SI 0 "register_operand" "=d")
1866 (and:SI (match_operand:QI 1 "address_operand" "p")
1867 (const_int 2147483647)))
1868 (clobber (reg:CC CC_REGNUM))]
1871 "&& reload_completed"
1873 (and:SI (match_dup 1) (const_int 2147483647)))]
1875 [(set_attr "op_type" "RX")
1876 (set_attr "type" "la")])
1878 (define_insn "force_la_31"
1879 [(set (match_operand:SI 0 "register_operand" "=d,d")
1880 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1881 (use (const_int 0))]
1886 [(set_attr "op_type" "RX")
1887 (set_attr "type" "la")
1888 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1891 ; movhi instruction pattern(s).
1894 (define_expand "movhi"
1895 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1896 (match_operand:HI 1 "general_operand" ""))]
1899 /* Make it explicit that loading a register from memory
1900 always sign-extends (at least) to SImode. */
1901 if (optimize && can_create_pseudo_p ()
1902 && register_operand (operands[0], VOIDmode)
1903 && GET_CODE (operands[1]) == MEM)
1905 rtx tmp = gen_reg_rtx (SImode);
1906 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1907 emit_insn (gen_rtx_SET (tmp, ext));
1908 operands[1] = gen_lowpart (HImode, tmp);
1912 (define_insn "*movhi"
1913 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1914 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1926 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1927 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1928 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1929 (set_attr "z10prop" "z10_fr_E1,
1940 [(set (match_operand:HI 0 "register_operand" "")
1941 (mem:HI (match_operand 1 "address_operand" "")))]
1942 "GET_CODE (operands[1]) == SYMBOL_REF
1943 && CONSTANT_POOL_ADDRESS_P (operands[1])
1944 && get_pool_mode (operands[1]) == HImode
1945 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1946 [(set (match_dup 0) (match_dup 2))]
1947 "operands[2] = get_pool_constant (operands[1]);")
1950 ; movqi instruction pattern(s).
1953 (define_expand "movqi"
1954 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1955 (match_operand:QI 1 "general_operand" ""))]
1958 /* On z/Architecture, zero-extending from memory to register
1959 is just as fast as a QImode load. */
1960 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1961 && register_operand (operands[0], VOIDmode)
1962 && GET_CODE (operands[1]) == MEM)
1964 rtx tmp = gen_reg_rtx (DImode);
1965 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1966 emit_insn (gen_rtx_SET (tmp, ext));
1967 operands[1] = gen_lowpart (QImode, tmp);
1971 (define_insn "*movqi"
1972 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1973 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1985 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1986 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1987 (set_attr "z10prop" "z10_fr_E1,
1998 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1999 (mem:QI (match_operand 1 "address_operand" "")))]
2000 "GET_CODE (operands[1]) == SYMBOL_REF
2001 && CONSTANT_POOL_ADDRESS_P (operands[1])
2002 && get_pool_mode (operands[1]) == QImode
2003 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2004 [(set (match_dup 0) (match_dup 2))]
2005 "operands[2] = get_pool_constant (operands[1]);")
2008 ; movstrictqi instruction pattern(s).
2011 (define_insn "*movstrictqi"
2012 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2013 (match_operand:QI 1 "memory_operand" "R,T"))]
2018 [(set_attr "op_type" "RX,RXY")
2019 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2022 ; movstricthi instruction pattern(s).
2025 (define_insn "*movstricthi"
2026 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2027 (match_operand:HI 1 "memory_operand" "Q,S"))
2028 (clobber (reg:CC CC_REGNUM))]
2033 [(set_attr "op_type" "RS,RSY")
2034 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2037 ; movstrictsi instruction pattern(s).
2040 (define_insn "movstrictsi"
2041 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2042 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2049 [(set_attr "op_type" "RR,RX,RXY,RRE")
2050 (set_attr "type" "lr,load,load,*")
2051 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2054 ; mov(tf|td) instruction pattern(s).
2057 (define_expand "mov<mode>"
2058 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2059 (match_operand:TD_TF 1 "general_operand" ""))]
2063 (define_insn "*mov<mode>_64"
2064 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2065 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2076 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2077 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2078 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2080 (define_insn "*mov<mode>_31"
2081 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2082 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2089 [(set_attr "op_type" "RRE,RRE,*,*")
2090 (set_attr "type" "fsimptf,fsimptf,*,*")
2091 (set_attr "cpu_facility" "z196,*,*,*")])
2093 ; TFmode in GPRs splitters
2096 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2097 (match_operand:TD_TF 1 "general_operand" ""))]
2098 "TARGET_ZARCH && reload_completed
2099 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2100 [(set (match_dup 2) (match_dup 4))
2101 (set (match_dup 3) (match_dup 5))]
2103 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2104 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2105 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2106 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2110 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2111 (match_operand:TD_TF 1 "general_operand" ""))]
2112 "TARGET_ZARCH && reload_completed
2113 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2114 [(set (match_dup 2) (match_dup 4))
2115 (set (match_dup 3) (match_dup 5))]
2117 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2118 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2119 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2120 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2124 [(set (match_operand:TD_TF 0 "register_operand" "")
2125 (match_operand:TD_TF 1 "memory_operand" ""))]
2126 "TARGET_ZARCH && reload_completed
2127 && !FP_REG_P (operands[0])
2128 && !s_operand (operands[1], VOIDmode)"
2129 [(set (match_dup 0) (match_dup 1))]
2131 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2132 addr = gen_lowpart (Pmode, addr);
2133 s390_load_address (addr, XEXP (operands[1], 0));
2134 operands[1] = replace_equiv_address (operands[1], addr);
2137 ; TFmode in BFPs splitters
2140 [(set (match_operand:TD_TF 0 "register_operand" "")
2141 (match_operand:TD_TF 1 "memory_operand" ""))]
2142 "reload_completed && offsettable_memref_p (operands[1])
2143 && FP_REG_P (operands[0])"
2144 [(set (match_dup 2) (match_dup 4))
2145 (set (match_dup 3) (match_dup 5))]
2147 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2149 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2151 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2152 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2156 [(set (match_operand:TD_TF 0 "memory_operand" "")
2157 (match_operand:TD_TF 1 "register_operand" ""))]
2158 "reload_completed && offsettable_memref_p (operands[0])
2159 && FP_REG_P (operands[1])"
2160 [(set (match_dup 2) (match_dup 4))
2161 (set (match_dup 3) (match_dup 5))]
2163 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2164 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2165 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2167 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2172 ; mov(df|dd) instruction pattern(s).
2175 (define_expand "mov<mode>"
2176 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2177 (match_operand:DD_DF 1 "general_operand" ""))]
2181 (define_insn "*mov<mode>_64dfp"
2182 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2183 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2184 (match_operand:DD_DF 1 "general_operand"
2185 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2200 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2201 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2202 fstoredf,fstoredf,*,lr,load,store")
2203 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2204 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2206 (define_insn "*mov<mode>_64"
2207 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2208 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2221 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2222 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2223 fstore<mode>,fstore<mode>,*,lr,load,store")
2224 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2225 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2227 (define_insn "*mov<mode>_31"
2228 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2229 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2230 (match_operand:DD_DF 1 "general_operand"
2231 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2246 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2247 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2248 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2249 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2252 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2253 (match_operand:DD_DF 1 "general_operand" ""))]
2254 "!TARGET_ZARCH && reload_completed
2255 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2256 [(set (match_dup 2) (match_dup 4))
2257 (set (match_dup 3) (match_dup 5))]
2259 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2260 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2261 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2262 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2266 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2267 (match_operand:DD_DF 1 "general_operand" ""))]
2268 "!TARGET_ZARCH && reload_completed
2269 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2270 [(set (match_dup 2) (match_dup 4))
2271 (set (match_dup 3) (match_dup 5))]
2273 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2274 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2275 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2276 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2280 [(set (match_operand:DD_DF 0 "register_operand" "")
2281 (match_operand:DD_DF 1 "memory_operand" ""))]
2282 "!TARGET_ZARCH && reload_completed
2283 && !FP_REG_P (operands[0])
2284 && !s_operand (operands[1], VOIDmode)"
2285 [(set (match_dup 0) (match_dup 1))]
2287 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2288 s390_load_address (addr, XEXP (operands[1], 0));
2289 operands[1] = replace_equiv_address (operands[1], addr);
2293 ; mov(sf|sd) instruction pattern(s).
2296 (define_insn "mov<mode>"
2297 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2298 "=f,f,f,f,R,T,d,d,d,d,R,T")
2299 (match_operand:SD_SF 1 "general_operand"
2300 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2315 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2316 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2317 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2318 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2319 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2322 ; movcc instruction pattern
2325 (define_insn "movcc"
2326 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2327 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2337 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2338 (set_attr "type" "lr,*,*,load,load,store,store")
2339 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2340 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2343 ; Block move (MVC) patterns.
2347 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2348 (match_operand:BLK 1 "memory_operand" "Q"))
2349 (use (match_operand 2 "const_int_operand" "n"))]
2350 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2351 "mvc\t%O0(%2,%R0),%S1"
2352 [(set_attr "op_type" "SS")])
2354 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2355 ; order to have it implemented with mvc.
2358 [(set (match_operand:QI 0 "memory_operand" "")
2359 (match_operand:QI 1 "memory_operand" ""))]
2362 [(set (match_dup 0) (match_dup 1))
2363 (use (const_int 1))])]
2365 operands[0] = adjust_address (operands[0], BLKmode, 0);
2366 operands[1] = adjust_address (operands[1], BLKmode, 0);
2372 [(set (match_operand:BLK 0 "memory_operand" "")
2373 (match_operand:BLK 1 "memory_operand" ""))
2374 (use (match_operand 2 "const_int_operand" ""))])
2376 [(set (match_operand:BLK 3 "memory_operand" "")
2377 (match_operand:BLK 4 "memory_operand" ""))
2378 (use (match_operand 5 "const_int_operand" ""))])]
2379 "s390_offset_p (operands[0], operands[3], operands[2])
2380 && s390_offset_p (operands[1], operands[4], operands[2])
2381 && !s390_overlap_p (operands[0], operands[1],
2382 INTVAL (operands[2]) + INTVAL (operands[5]))
2383 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2385 [(set (match_dup 6) (match_dup 7))
2386 (use (match_dup 8))])]
2387 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2388 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2389 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2393 ; load_multiple pattern(s).
2395 ; ??? Due to reload problems with replacing registers inside match_parallel
2396 ; we currently support load_multiple/store_multiple only after reload.
2399 (define_expand "load_multiple"
2400 [(match_par_dup 3 [(set (match_operand 0 "" "")
2401 (match_operand 1 "" ""))
2402 (use (match_operand 2 "" ""))])]
2411 /* Support only loading a constant number of fixed-point registers from
2412 memory and only bother with this if more than two */
2413 if (GET_CODE (operands[2]) != CONST_INT
2414 || INTVAL (operands[2]) < 2
2415 || INTVAL (operands[2]) > 16
2416 || GET_CODE (operands[1]) != MEM
2417 || GET_CODE (operands[0]) != REG
2418 || REGNO (operands[0]) >= 16)
2421 count = INTVAL (operands[2]);
2422 regno = REGNO (operands[0]);
2423 mode = GET_MODE (operands[0]);
2424 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2427 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2428 if (!can_create_pseudo_p ())
2430 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2432 from = XEXP (operands[1], 0);
2435 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2436 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2437 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2439 from = XEXP (XEXP (operands[1], 0), 0);
2440 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2447 from = force_reg (Pmode, XEXP (operands[1], 0));
2451 for (i = 0; i < count; i++)
2452 XVECEXP (operands[3], 0, i)
2453 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2454 change_address (operands[1], mode,
2455 plus_constant (Pmode, from,
2456 off + i * GET_MODE_SIZE (mode))));
2459 (define_insn "*load_multiple_di"
2460 [(match_parallel 0 "load_multiple_operation"
2461 [(set (match_operand:DI 1 "register_operand" "=r")
2462 (match_operand:DI 2 "s_operand" "QS"))])]
2463 "reload_completed && TARGET_ZARCH"
2465 int words = XVECLEN (operands[0], 0);
2466 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2467 return "lmg\t%1,%0,%S2";
2469 [(set_attr "op_type" "RSY")
2470 (set_attr "type" "lm")])
2472 (define_insn "*load_multiple_si"
2473 [(match_parallel 0 "load_multiple_operation"
2474 [(set (match_operand:SI 1 "register_operand" "=r,r")
2475 (match_operand:SI 2 "s_operand" "Q,S"))])]
2478 int words = XVECLEN (operands[0], 0);
2479 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2480 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2482 [(set_attr "op_type" "RS,RSY")
2483 (set_attr "type" "lm")])
2486 ; store multiple pattern(s).
2489 (define_expand "store_multiple"
2490 [(match_par_dup 3 [(set (match_operand 0 "" "")
2491 (match_operand 1 "" ""))
2492 (use (match_operand 2 "" ""))])]
2501 /* Support only storing a constant number of fixed-point registers to
2502 memory and only bother with this if more than two. */
2503 if (GET_CODE (operands[2]) != CONST_INT
2504 || INTVAL (operands[2]) < 2
2505 || INTVAL (operands[2]) > 16
2506 || GET_CODE (operands[0]) != MEM
2507 || GET_CODE (operands[1]) != REG
2508 || REGNO (operands[1]) >= 16)
2511 count = INTVAL (operands[2]);
2512 regno = REGNO (operands[1]);
2513 mode = GET_MODE (operands[1]);
2514 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2517 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2519 if (!can_create_pseudo_p ())
2521 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2523 to = XEXP (operands[0], 0);
2526 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2527 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2528 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2530 to = XEXP (XEXP (operands[0], 0), 0);
2531 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2538 to = force_reg (Pmode, XEXP (operands[0], 0));
2542 for (i = 0; i < count; i++)
2543 XVECEXP (operands[3], 0, i)
2544 = gen_rtx_SET (change_address (operands[0], mode,
2545 plus_constant (Pmode, to,
2546 off + i * GET_MODE_SIZE (mode))),
2547 gen_rtx_REG (mode, regno + i));
2550 (define_insn "*store_multiple_di"
2551 [(match_parallel 0 "store_multiple_operation"
2552 [(set (match_operand:DI 1 "s_operand" "=QS")
2553 (match_operand:DI 2 "register_operand" "r"))])]
2554 "reload_completed && TARGET_ZARCH"
2556 int words = XVECLEN (operands[0], 0);
2557 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2558 return "stmg\t%2,%0,%S1";
2560 [(set_attr "op_type" "RSY")
2561 (set_attr "type" "stm")])
2564 (define_insn "*store_multiple_si"
2565 [(match_parallel 0 "store_multiple_operation"
2566 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2567 (match_operand:SI 2 "register_operand" "r,r"))])]
2570 int words = XVECLEN (operands[0], 0);
2571 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2572 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2574 [(set_attr "op_type" "RS,RSY")
2575 (set_attr "type" "stm")])
2578 ;; String instructions.
2581 (define_insn "*execute_rl"
2582 [(match_parallel 0 "execute_operation"
2583 [(unspec [(match_operand 1 "register_operand" "a")
2584 (match_operand 2 "" "")
2585 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2586 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2587 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2589 [(set_attr "op_type" "RIL")
2590 (set_attr "type" "cs")])
2592 (define_insn "*execute"
2593 [(match_parallel 0 "execute_operation"
2594 [(unspec [(match_operand 1 "register_operand" "a")
2595 (match_operand:BLK 2 "memory_operand" "R")
2596 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2597 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2598 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2600 [(set_attr "op_type" "RX")
2601 (set_attr "type" "cs")])
2605 ; strlenM instruction pattern(s).
2608 (define_expand "strlen<mode>"
2609 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2612 (unspec:P [(const_int 0)
2613 (match_operand:BLK 1 "memory_operand" "")
2615 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2616 (clobber (scratch:P))
2617 (clobber (reg:CC CC_REGNUM))])
2619 [(set (match_operand:P 0 "register_operand" "")
2620 (minus:P (match_dup 4) (match_dup 5)))
2621 (clobber (reg:CC CC_REGNUM))])]
2624 operands[4] = gen_reg_rtx (Pmode);
2625 operands[5] = gen_reg_rtx (Pmode);
2626 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2627 operands[1] = replace_equiv_address (operands[1], operands[5]);
2630 (define_insn "*strlen<mode>"
2631 [(set (match_operand:P 0 "register_operand" "=a")
2632 (unspec:P [(match_operand:P 2 "general_operand" "0")
2633 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2635 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2636 (clobber (match_scratch:P 1 "=a"))
2637 (clobber (reg:CC CC_REGNUM))]
2639 "srst\t%0,%1\;jo\t.-4"
2640 [(set_attr "length" "8")
2641 (set_attr "type" "vs")])
2644 ; cmpstrM instruction pattern(s).
2647 (define_expand "cmpstrsi"
2648 [(set (reg:SI 0) (const_int 0))
2650 [(clobber (match_operand 3 "" ""))
2651 (clobber (match_dup 4))
2652 (set (reg:CCU CC_REGNUM)
2653 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2654 (match_operand:BLK 2 "memory_operand" "")))
2657 [(set (match_operand:SI 0 "register_operand" "=d")
2658 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2659 (clobber (reg:CC CC_REGNUM))])]
2662 /* As the result of CMPINT is inverted compared to what we need,
2663 we have to swap the operands. */
2664 rtx op1 = operands[2];
2665 rtx op2 = operands[1];
2666 rtx addr1 = gen_reg_rtx (Pmode);
2667 rtx addr2 = gen_reg_rtx (Pmode);
2669 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2670 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2671 operands[1] = replace_equiv_address_nv (op1, addr1);
2672 operands[2] = replace_equiv_address_nv (op2, addr2);
2673 operands[3] = addr1;
2674 operands[4] = addr2;
2677 (define_insn "*cmpstr<mode>"
2678 [(clobber (match_operand:P 0 "register_operand" "=d"))
2679 (clobber (match_operand:P 1 "register_operand" "=d"))
2680 (set (reg:CCU CC_REGNUM)
2681 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2682 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2685 "clst\t%0,%1\;jo\t.-4"
2686 [(set_attr "length" "8")
2687 (set_attr "type" "vs")])
2690 ; movstr instruction pattern.
2693 (define_expand "movstr"
2694 [(set (reg:SI 0) (const_int 0))
2696 [(clobber (match_dup 3))
2697 (set (match_operand:BLK 1 "memory_operand" "")
2698 (match_operand:BLK 2 "memory_operand" ""))
2699 (set (match_operand 0 "register_operand" "")
2700 (unspec [(match_dup 1)
2702 (reg:SI 0)] UNSPEC_MVST))
2703 (clobber (reg:CC CC_REGNUM))])]
2706 rtx addr1 = gen_reg_rtx (Pmode);
2707 rtx addr2 = gen_reg_rtx (Pmode);
2709 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2710 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2711 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2712 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2713 operands[3] = addr2;
2716 (define_insn "*movstr"
2717 [(clobber (match_operand:P 2 "register_operand" "=d"))
2718 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2719 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2720 (set (match_operand:P 0 "register_operand" "=d")
2721 (unspec [(mem:BLK (match_dup 1))
2722 (mem:BLK (match_dup 3))
2723 (reg:SI 0)] UNSPEC_MVST))
2724 (clobber (reg:CC CC_REGNUM))]
2726 "mvst\t%1,%2\;jo\t.-4"
2727 [(set_attr "length" "8")
2728 (set_attr "type" "vs")])
2732 ; movmemM instruction pattern(s).
2735 (define_expand "movmem<mode>"
2736 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2737 (match_operand:BLK 1 "memory_operand" "")) ; source
2738 (use (match_operand:GPR 2 "general_operand" "")) ; count
2739 (match_operand 3 "" "")]
2742 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2748 ; Move a block that is up to 256 bytes in length.
2749 ; The block length is taken as (operands[2] % 256) + 1.
2751 (define_expand "movmem_short"
2753 [(set (match_operand:BLK 0 "memory_operand" "")
2754 (match_operand:BLK 1 "memory_operand" ""))
2755 (use (match_operand 2 "nonmemory_operand" ""))
2756 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2757 (clobber (match_dup 3))])]
2759 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2761 (define_insn "*movmem_short"
2762 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2763 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2764 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2765 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2766 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2767 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2769 [(set_attr "type" "cs")
2770 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2773 [(set (match_operand:BLK 0 "memory_operand" "")
2774 (match_operand:BLK 1 "memory_operand" ""))
2775 (use (match_operand 2 "const_int_operand" ""))
2776 (use (match_operand 3 "immediate_operand" ""))
2777 (clobber (scratch))]
2780 [(set (match_dup 0) (match_dup 1))
2781 (use (match_dup 2))])]
2782 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2785 [(set (match_operand:BLK 0 "memory_operand" "")
2786 (match_operand:BLK 1 "memory_operand" ""))
2787 (use (match_operand 2 "register_operand" ""))
2788 (use (match_operand 3 "memory_operand" ""))
2789 (clobber (scratch))]
2792 [(unspec [(match_dup 2) (match_dup 3)
2793 (const_int 0)] UNSPEC_EXECUTE)
2794 (set (match_dup 0) (match_dup 1))
2795 (use (const_int 1))])]
2799 [(set (match_operand:BLK 0 "memory_operand" "")
2800 (match_operand:BLK 1 "memory_operand" ""))
2801 (use (match_operand 2 "register_operand" ""))
2802 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2803 (clobber (scratch))]
2804 "TARGET_Z10 && reload_completed"
2806 [(unspec [(match_dup 2) (const_int 0)
2807 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2808 (set (match_dup 0) (match_dup 1))
2809 (use (const_int 1))])]
2810 "operands[3] = gen_label_rtx ();")
2813 [(set (match_operand:BLK 0 "memory_operand" "")
2814 (match_operand:BLK 1 "memory_operand" ""))
2815 (use (match_operand 2 "register_operand" ""))
2816 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2817 (clobber (match_operand 3 "register_operand" ""))]
2818 "reload_completed && TARGET_CPU_ZARCH"
2819 [(set (match_dup 3) (label_ref (match_dup 4)))
2821 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2822 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2823 (set (match_dup 0) (match_dup 1))
2824 (use (const_int 1))])]
2825 "operands[4] = gen_label_rtx ();")
2827 ; Move a block of arbitrary length.
2829 (define_expand "movmem_long"
2831 [(clobber (match_dup 2))
2832 (clobber (match_dup 3))
2833 (set (match_operand:BLK 0 "memory_operand" "")
2834 (match_operand:BLK 1 "memory_operand" ""))
2835 (use (match_operand 2 "general_operand" ""))
2837 (clobber (reg:CC CC_REGNUM))])]
2840 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2841 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2842 rtx reg0 = gen_reg_rtx (dreg_mode);
2843 rtx reg1 = gen_reg_rtx (dreg_mode);
2844 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2845 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2846 rtx len0 = gen_lowpart (Pmode, reg0);
2847 rtx len1 = gen_lowpart (Pmode, reg1);
2849 emit_clobber (reg0);
2850 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2851 emit_move_insn (len0, operands[2]);
2853 emit_clobber (reg1);
2854 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2855 emit_move_insn (len1, operands[2]);
2857 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2858 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2863 (define_insn "*movmem_long"
2864 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2865 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2866 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2867 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2870 (clobber (reg:CC CC_REGNUM))]
2871 "TARGET_64BIT || !TARGET_ZARCH"
2872 "mvcle\t%0,%1,0\;jo\t.-4"
2873 [(set_attr "length" "8")
2874 (set_attr "type" "vs")])
2876 (define_insn "*movmem_long_31z"
2877 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2878 (clobber (match_operand:TI 1 "register_operand" "=d"))
2879 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2880 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2883 (clobber (reg:CC CC_REGNUM))]
2884 "!TARGET_64BIT && TARGET_ZARCH"
2885 "mvcle\t%0,%1,0\;jo\t.-4"
2886 [(set_attr "length" "8")
2887 (set_attr "type" "vs")])
2894 (define_expand "signbit<mode>2"
2895 [(set (reg:CCZ CC_REGNUM)
2896 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2899 (set (match_operand:SI 0 "register_operand" "=d")
2900 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2903 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2906 (define_expand "isinf<mode>2"
2907 [(set (reg:CCZ CC_REGNUM)
2908 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2911 (set (match_operand:SI 0 "register_operand" "=d")
2912 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2915 operands[2] = GEN_INT (S390_TDC_INFINITY);
2918 (define_insn_and_split "*cc_to_int"
2919 [(set (match_operand:SI 0 "register_operand" "=d")
2920 (unspec:SI [(match_operand 1 "register_operand" "0")]
2925 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2927 ; This insn is used to generate all variants of the Test Data Class
2928 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2929 ; is the register to be tested and the second one is the bit mask
2930 ; specifying the required test(s).
2932 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2933 (define_insn "*TDC_insn_<mode>"
2934 [(set (reg:CCZ CC_REGNUM)
2935 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2936 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2938 "t<_d>c<xde><bt>\t%0,%1"
2939 [(set_attr "op_type" "RXE")
2940 (set_attr "type" "fsimp<mode>")])
2945 ; setmemM instruction pattern(s).
2948 (define_expand "setmem<mode>"
2949 [(set (match_operand:BLK 0 "memory_operand" "")
2950 (match_operand:QI 2 "general_operand" ""))
2951 (use (match_operand:GPR 1 "general_operand" ""))
2952 (match_operand 3 "" "")]
2954 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2956 ; Clear a block that is up to 256 bytes in length.
2957 ; The block length is taken as (operands[1] % 256) + 1.
2959 (define_expand "clrmem_short"
2961 [(set (match_operand:BLK 0 "memory_operand" "")
2963 (use (match_operand 1 "nonmemory_operand" ""))
2964 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2965 (clobber (match_dup 2))
2966 (clobber (reg:CC CC_REGNUM))])]
2968 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2970 (define_insn "*clrmem_short"
2971 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2973 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2974 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2975 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2976 (clobber (reg:CC CC_REGNUM))]
2977 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2979 [(set_attr "type" "cs")
2980 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2983 [(set (match_operand:BLK 0 "memory_operand" "")
2985 (use (match_operand 1 "const_int_operand" ""))
2986 (use (match_operand 2 "immediate_operand" ""))
2988 (clobber (reg:CC CC_REGNUM))]
2991 [(set (match_dup 0) (const_int 0))
2993 (clobber (reg:CC CC_REGNUM))])]
2994 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2997 [(set (match_operand:BLK 0 "memory_operand" "")
2999 (use (match_operand 1 "register_operand" ""))
3000 (use (match_operand 2 "memory_operand" ""))
3002 (clobber (reg:CC CC_REGNUM))]
3005 [(unspec [(match_dup 1) (match_dup 2)
3006 (const_int 0)] UNSPEC_EXECUTE)
3007 (set (match_dup 0) (const_int 0))
3009 (clobber (reg:CC CC_REGNUM))])]
3013 [(set (match_operand:BLK 0 "memory_operand" "")
3015 (use (match_operand 1 "register_operand" ""))
3016 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3018 (clobber (reg:CC CC_REGNUM))]
3019 "TARGET_Z10 && reload_completed"
3021 [(unspec [(match_dup 1) (const_int 0)
3022 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3023 (set (match_dup 0) (const_int 0))
3025 (clobber (reg:CC CC_REGNUM))])]
3026 "operands[3] = gen_label_rtx ();")
3029 [(set (match_operand:BLK 0 "memory_operand" "")
3031 (use (match_operand 1 "register_operand" ""))
3032 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3033 (clobber (match_operand 2 "register_operand" ""))
3034 (clobber (reg:CC CC_REGNUM))]
3035 "reload_completed && TARGET_CPU_ZARCH"
3036 [(set (match_dup 2) (label_ref (match_dup 3)))
3038 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3039 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3040 (set (match_dup 0) (const_int 0))
3042 (clobber (reg:CC CC_REGNUM))])]
3043 "operands[3] = gen_label_rtx ();")
3045 ; Initialize a block of arbitrary length with (operands[2] % 256).
3047 (define_expand "setmem_long"
3049 [(clobber (match_dup 1))
3050 (set (match_operand:BLK 0 "memory_operand" "")
3051 (match_operand 2 "shift_count_or_setmem_operand" ""))
3052 (use (match_operand 1 "general_operand" ""))
3054 (clobber (reg:CC CC_REGNUM))])]
3057 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3058 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3059 rtx reg0 = gen_reg_rtx (dreg_mode);
3060 rtx reg1 = gen_reg_rtx (dreg_mode);
3061 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3062 rtx len0 = gen_lowpart (Pmode, reg0);
3064 emit_clobber (reg0);
3065 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3066 emit_move_insn (len0, operands[1]);
3068 emit_move_insn (reg1, const0_rtx);
3070 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3075 (define_insn "*setmem_long"
3076 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3077 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3078 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3080 (use (match_operand:<DBL> 1 "register_operand" "d"))
3081 (clobber (reg:CC CC_REGNUM))]
3082 "TARGET_64BIT || !TARGET_ZARCH"
3083 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3084 [(set_attr "length" "8")
3085 (set_attr "type" "vs")])
3087 (define_insn "*setmem_long_and"
3088 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3089 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3090 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3091 (match_operand 4 "const_int_operand" "n")))
3093 (use (match_operand:<DBL> 1 "register_operand" "d"))
3094 (clobber (reg:CC CC_REGNUM))]
3095 "(TARGET_64BIT || !TARGET_ZARCH) &&
3096 (INTVAL (operands[4]) & 255) == 255"
3097 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3098 [(set_attr "length" "8")
3099 (set_attr "type" "vs")])
3101 (define_insn "*setmem_long_31z"
3102 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3103 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3104 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3106 (use (match_operand:TI 1 "register_operand" "d"))
3107 (clobber (reg:CC CC_REGNUM))]
3108 "!TARGET_64BIT && TARGET_ZARCH"
3109 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3110 [(set_attr "length" "8")
3111 (set_attr "type" "vs")])
3114 ; cmpmemM instruction pattern(s).
3117 (define_expand "cmpmemsi"
3118 [(set (match_operand:SI 0 "register_operand" "")
3119 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3120 (match_operand:BLK 2 "memory_operand" "") ) )
3121 (use (match_operand:SI 3 "general_operand" ""))
3122 (use (match_operand:SI 4 "" ""))]
3125 if (s390_expand_cmpmem (operands[0], operands[1],
3126 operands[2], operands[3]))
3132 ; Compare a block that is up to 256 bytes in length.
3133 ; The block length is taken as (operands[2] % 256) + 1.
3135 (define_expand "cmpmem_short"
3137 [(set (reg:CCU CC_REGNUM)
3138 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3139 (match_operand:BLK 1 "memory_operand" "")))
3140 (use (match_operand 2 "nonmemory_operand" ""))
3141 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3142 (clobber (match_dup 3))])]
3144 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3146 (define_insn "*cmpmem_short"
3147 [(set (reg:CCU CC_REGNUM)
3148 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3149 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3150 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3151 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3152 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3153 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3155 [(set_attr "type" "cs")
3156 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3159 [(set (reg:CCU CC_REGNUM)
3160 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3161 (match_operand:BLK 1 "memory_operand" "")))
3162 (use (match_operand 2 "const_int_operand" ""))
3163 (use (match_operand 3 "immediate_operand" ""))
3164 (clobber (scratch))]
3167 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3168 (use (match_dup 2))])]
3169 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3172 [(set (reg:CCU CC_REGNUM)
3173 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3174 (match_operand:BLK 1 "memory_operand" "")))
3175 (use (match_operand 2 "register_operand" ""))
3176 (use (match_operand 3 "memory_operand" ""))
3177 (clobber (scratch))]
3180 [(unspec [(match_dup 2) (match_dup 3)
3181 (const_int 0)] UNSPEC_EXECUTE)
3182 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3183 (use (const_int 1))])]
3187 [(set (reg:CCU CC_REGNUM)
3188 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3189 (match_operand:BLK 1 "memory_operand" "")))
3190 (use (match_operand 2 "register_operand" ""))
3191 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3192 (clobber (scratch))]
3193 "TARGET_Z10 && reload_completed"
3195 [(unspec [(match_dup 2) (const_int 0)
3196 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3197 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3198 (use (const_int 1))])]
3199 "operands[4] = gen_label_rtx ();")
3202 [(set (reg:CCU CC_REGNUM)
3203 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3204 (match_operand:BLK 1 "memory_operand" "")))
3205 (use (match_operand 2 "register_operand" ""))
3206 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3207 (clobber (match_operand 3 "register_operand" ""))]
3208 "reload_completed && TARGET_CPU_ZARCH"
3209 [(set (match_dup 3) (label_ref (match_dup 4)))
3211 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3212 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3213 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3214 (use (const_int 1))])]
3215 "operands[4] = gen_label_rtx ();")
3217 ; Compare a block of arbitrary length.
3219 (define_expand "cmpmem_long"
3221 [(clobber (match_dup 2))
3222 (clobber (match_dup 3))
3223 (set (reg:CCU CC_REGNUM)
3224 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3225 (match_operand:BLK 1 "memory_operand" "")))
3226 (use (match_operand 2 "general_operand" ""))
3227 (use (match_dup 3))])]
3230 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3231 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3232 rtx reg0 = gen_reg_rtx (dreg_mode);
3233 rtx reg1 = gen_reg_rtx (dreg_mode);
3234 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3235 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3236 rtx len0 = gen_lowpart (Pmode, reg0);
3237 rtx len1 = gen_lowpart (Pmode, reg1);
3239 emit_clobber (reg0);
3240 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3241 emit_move_insn (len0, operands[2]);
3243 emit_clobber (reg1);
3244 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3245 emit_move_insn (len1, operands[2]);
3247 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3248 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3253 (define_insn "*cmpmem_long"
3254 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3255 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3256 (set (reg:CCU CC_REGNUM)
3257 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3258 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3260 (use (match_dup 3))]
3261 "TARGET_64BIT || !TARGET_ZARCH"
3262 "clcle\t%0,%1,0\;jo\t.-4"
3263 [(set_attr "length" "8")
3264 (set_attr "type" "vs")])
3266 (define_insn "*cmpmem_long_31z"
3267 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3268 (clobber (match_operand:TI 1 "register_operand" "=d"))
3269 (set (reg:CCU CC_REGNUM)
3270 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3271 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3273 (use (match_dup 3))]
3274 "!TARGET_64BIT && TARGET_ZARCH"
3275 "clcle\t%0,%1,0\;jo\t.-4"
3276 [(set_attr "op_type" "NN")
3277 (set_attr "type" "vs")
3278 (set_attr "length" "8")])
3280 ; Convert CCUmode condition code to integer.
3281 ; Result is zero if EQ, positive if LTU, negative if GTU.
3283 (define_insn_and_split "cmpint"
3284 [(set (match_operand:SI 0 "register_operand" "=d")
3285 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3286 UNSPEC_STRCMPCC_TO_INT))
3287 (clobber (reg:CC CC_REGNUM))]
3291 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3293 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3294 (clobber (reg:CC CC_REGNUM))])])
3296 (define_insn_and_split "*cmpint_cc"
3297 [(set (reg CC_REGNUM)
3298 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3299 UNSPEC_STRCMPCC_TO_INT)
3301 (set (match_operand:SI 0 "register_operand" "=d")
3302 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3303 "s390_match_ccmode (insn, CCSmode)"
3305 "&& reload_completed"
3306 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3308 [(set (match_dup 2) (match_dup 3))
3309 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3311 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3312 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3313 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3316 (define_insn_and_split "*cmpint_sign"
3317 [(set (match_operand:DI 0 "register_operand" "=d")
3318 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3319 UNSPEC_STRCMPCC_TO_INT)))
3320 (clobber (reg:CC CC_REGNUM))]
3323 "&& reload_completed"
3324 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3326 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3327 (clobber (reg:CC CC_REGNUM))])])
3329 (define_insn_and_split "*cmpint_sign_cc"
3330 [(set (reg CC_REGNUM)
3331 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3332 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3333 UNSPEC_STRCMPCC_TO_INT) 0)
3334 (const_int 32)) (const_int 32))
3336 (set (match_operand:DI 0 "register_operand" "=d")
3337 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3338 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3340 "&& reload_completed"
3341 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3343 [(set (match_dup 2) (match_dup 3))
3344 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3346 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3347 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3348 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3353 ;;- Conversion instructions.
3356 (define_insn "*sethighpartsi"
3357 [(set (match_operand:SI 0 "register_operand" "=d,d")
3358 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3359 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3360 (clobber (reg:CC CC_REGNUM))]
3365 [(set_attr "op_type" "RS,RSY")
3366 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3368 (define_insn "*sethighpartdi_64"
3369 [(set (match_operand:DI 0 "register_operand" "=d")
3370 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3371 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3372 (clobber (reg:CC CC_REGNUM))]
3375 [(set_attr "op_type" "RSY")
3376 (set_attr "z10prop" "z10_super")])
3378 (define_insn "*sethighpartdi_31"
3379 [(set (match_operand:DI 0 "register_operand" "=d,d")
3380 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3381 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3382 (clobber (reg:CC CC_REGNUM))]
3387 [(set_attr "op_type" "RS,RSY")
3388 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3391 ; extv instruction patterns
3394 ; FIXME: This expander needs to be converted from DI to GPR as well
3395 ; after resolving some issues with it.
3397 (define_expand "extzv"
3399 [(set (match_operand:DI 0 "register_operand" "=d")
3401 (match_operand:DI 1 "register_operand" "d")
3402 (match_operand 2 "const_int_operand" "") ; size
3403 (match_operand 3 "const_int_operand" ""))) ; start
3404 (clobber (reg:CC CC_REGNUM))])]
3407 /* Starting with zEC12 there is risbgn not clobbering CC. */
3410 emit_move_insn (operands[0],
3411 gen_rtx_ZERO_EXTRACT (DImode,
3419 (define_insn "*extzv<mode>_zEC12"
3420 [(set (match_operand:GPR 0 "register_operand" "=d")
3422 (match_operand:GPR 1 "register_operand" "d")
3423 (match_operand 2 "const_int_operand" "") ; size
3424 (match_operand 3 "const_int_operand" "")))] ; start]
3426 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3427 [(set_attr "op_type" "RIE")])
3429 (define_insn "*extzv<mode>_z10"
3430 [(set (match_operand:GPR 0 "register_operand" "=d")
3432 (match_operand:GPR 1 "register_operand" "d")
3433 (match_operand 2 "const_int_operand" "") ; size
3434 (match_operand 3 "const_int_operand" ""))) ; start
3435 (clobber (reg:CC CC_REGNUM))]
3437 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3438 [(set_attr "op_type" "RIE")
3439 (set_attr "z10prop" "z10_super_E1")])
3441 (define_insn_and_split "*pre_z10_extzv<mode>"
3442 [(set (match_operand:GPR 0 "register_operand" "=d")
3443 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3444 (match_operand 2 "nonzero_shift_count_operand" "")
3446 (clobber (reg:CC CC_REGNUM))]
3449 "&& reload_completed"
3451 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3452 (clobber (reg:CC CC_REGNUM))])
3453 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3455 int bitsize = INTVAL (operands[2]);
3456 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3457 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3459 operands[1] = adjust_address (operands[1], BLKmode, 0);
3460 set_mem_size (operands[1], size);
3461 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3462 operands[3] = GEN_INT (mask);
3465 (define_insn_and_split "*pre_z10_extv<mode>"
3466 [(set (match_operand:GPR 0 "register_operand" "=d")
3467 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3468 (match_operand 2 "nonzero_shift_count_operand" "")
3470 (clobber (reg:CC CC_REGNUM))]
3473 "&& reload_completed"
3475 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3476 (clobber (reg:CC CC_REGNUM))])
3478 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3479 (clobber (reg:CC CC_REGNUM))])]
3481 int bitsize = INTVAL (operands[2]);
3482 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3483 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3485 operands[1] = adjust_address (operands[1], BLKmode, 0);
3486 set_mem_size (operands[1], size);
3487 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3488 operands[3] = GEN_INT (mask);
3492 ; insv instruction patterns
3495 (define_expand "insv"
3496 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3497 (match_operand 1 "const_int_operand" "")
3498 (match_operand 2 "const_int_operand" ""))
3499 (match_operand 3 "general_operand" ""))]
3502 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3508 ; The normal RTL expansion will never generate a zero_extract where
3509 ; the location operand isn't word mode. However, we do this in the
3510 ; back-end when generating atomic operations. See s390_two_part_insv.
3511 (define_insn "*insv<mode>_zEC12"
3512 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3513 (match_operand 1 "const_int_operand" "I") ; size
3514 (match_operand 2 "const_int_operand" "I")) ; pos
3515 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3517 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3518 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3519 [(set_attr "op_type" "RIE")])
3521 (define_insn "*insv<mode>_z10"
3522 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3523 (match_operand 1 "const_int_operand" "I") ; size
3524 (match_operand 2 "const_int_operand" "I")) ; pos
3525 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3526 (clobber (reg:CC CC_REGNUM))]
3528 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3529 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3530 [(set_attr "op_type" "RIE")
3531 (set_attr "z10prop" "z10_super_E1")])
3533 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3534 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3535 (define_insn "*insv<mode>_zEC12_noshift"
3536 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3537 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3538 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3539 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3540 (match_operand:GPR 4 "const_int_operand" ""))))]
3541 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3542 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3543 [(set_attr "op_type" "RIE")])
3545 (define_insn "*insv<mode>_z10_noshift"
3546 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3547 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3548 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3549 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3550 (match_operand:GPR 4 "const_int_operand" ""))))
3551 (clobber (reg:CC CC_REGNUM))]
3552 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3553 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3554 [(set_attr "op_type" "RIE")
3555 (set_attr "z10prop" "z10_super_E1")])
3557 (define_insn "*r<noxa>sbg_<mode>_noshift"
3558 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3560 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3561 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3562 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3563 (clobber (reg:CC CC_REGNUM))]
3565 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3566 [(set_attr "op_type" "RIE")])
3568 (define_insn "*r<noxa>sbg_di_rotl"
3569 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3573 (match_operand:DI 1 "nonimmediate_operand" "d")
3574 (match_operand:DI 3 "const_int_operand" ""))
3575 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3576 (match_operand:DI 4 "nonimmediate_operand" "0")))
3577 (clobber (reg:CC CC_REGNUM))]
3579 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3580 [(set_attr "op_type" "RIE")])
3582 (define_insn "*r<noxa>sbg_<mode>_srl"
3583 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3587 (match_operand:GPR 1 "nonimmediate_operand" "d")
3588 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3589 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3590 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3591 (clobber (reg:CC CC_REGNUM))]
3593 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3594 INTVAL (operands[2]))"
3595 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3596 [(set_attr "op_type" "RIE")])
3598 (define_insn "*r<noxa>sbg_<mode>_sll"
3599 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3603 (match_operand:GPR 1 "nonimmediate_operand" "d")
3604 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3605 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3606 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3607 (clobber (reg:CC CC_REGNUM))]
3609 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3610 INTVAL (operands[2]))"
3611 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3612 [(set_attr "op_type" "RIE")])
3614 ;; These two are generated by combine for s.bf &= val.
3615 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3616 ;; shifts and ands, which results in some truly awful patterns
3617 ;; including subregs of operations. Rather unnecessisarily, IMO.
3620 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3621 ;; (const_int 24 [0x18])
3622 ;; (const_int 0 [0]))
3623 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3624 ;; (const_int 40 [0x28])) 4)
3625 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3627 ;; we should instead generate
3629 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3630 ;; (const_int 24 [0x18])
3631 ;; (const_int 0 [0]))
3632 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3633 ;; (const_int 40 [0x28]))
3634 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3636 ;; by noticing that we can push down the outer paradoxical subreg
3637 ;; into the operation.
3639 (define_insn "*insv_rnsbg_noshift"
3640 [(set (zero_extract:DI
3641 (match_operand:DI 0 "nonimmediate_operand" "+d")
3642 (match_operand 1 "const_int_operand" "")
3643 (match_operand 2 "const_int_operand" ""))
3646 (match_operand:DI 3 "nonimmediate_operand" "d")))
3647 (clobber (reg:CC CC_REGNUM))]
3649 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3650 "rnsbg\t%0,%3,%2,63,0"
3651 [(set_attr "op_type" "RIE")])
3653 (define_insn "*insv_rnsbg_srl"
3654 [(set (zero_extract:DI
3655 (match_operand:DI 0 "nonimmediate_operand" "+d")
3656 (match_operand 1 "const_int_operand" "")
3657 (match_operand 2 "const_int_operand" ""))
3661 (match_operand 3 "const_int_operand" ""))
3662 (match_operand:DI 4 "nonimmediate_operand" "d")))
3663 (clobber (reg:CC CC_REGNUM))]
3665 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3666 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3667 [(set_attr "op_type" "RIE")])
3669 (define_insn "*insv<mode>_mem_reg"
3670 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3671 (match_operand 1 "const_int_operand" "n,n")
3673 (match_operand:W 2 "register_operand" "d,d"))]
3674 "INTVAL (operands[1]) > 0
3675 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3676 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3678 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3680 operands[1] = GEN_INT ((1ul << size) - 1);
3681 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3682 : "stcmy\t%2,%1,%S0";
3684 [(set_attr "op_type" "RS,RSY")
3685 (set_attr "z10prop" "z10_super,z10_super")])
3687 (define_insn "*insvdi_mem_reghigh"
3688 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3689 (match_operand 1 "const_int_operand" "n")
3691 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3694 && INTVAL (operands[1]) > 0
3695 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3696 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3698 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3700 operands[1] = GEN_INT ((1ul << size) - 1);
3701 return "stcmh\t%2,%1,%S0";
3703 [(set_attr "op_type" "RSY")
3704 (set_attr "z10prop" "z10_super")])
3706 (define_insn "*insvdi_reg_imm"
3707 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3709 (match_operand 1 "const_int_operand" "n"))
3710 (match_operand:DI 2 "const_int_operand" "n"))]
3712 && INTVAL (operands[1]) >= 0
3713 && INTVAL (operands[1]) < BITS_PER_WORD
3714 && INTVAL (operands[1]) % 16 == 0"
3716 switch (BITS_PER_WORD - INTVAL (operands[1]))
3718 case 64: return "iihh\t%0,%x2"; break;
3719 case 48: return "iihl\t%0,%x2"; break;
3720 case 32: return "iilh\t%0,%x2"; break;
3721 case 16: return "iill\t%0,%x2"; break;
3722 default: gcc_unreachable();
3725 [(set_attr "op_type" "RI")
3726 (set_attr "z10prop" "z10_super_E1")])
3728 ; Update the left-most 32 bit of a DI.
3729 (define_insn "*insv_h_di_reg_extimm"
3730 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3733 (match_operand:DI 1 "const_int_operand" "n"))]
3736 [(set_attr "op_type" "RIL")
3737 (set_attr "z10prop" "z10_fwd_E1")])
3739 ; Update the right-most 32 bit of a DI.
3740 (define_insn "*insv_l_di_reg_extimm"
3741 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3744 (match_operand:DI 1 "const_int_operand" "n"))]
3747 [(set_attr "op_type" "RIL")
3748 (set_attr "z10prop" "z10_fwd_A1")])
3751 ; extendsidi2 instruction pattern(s).
3754 (define_expand "extendsidi2"
3755 [(set (match_operand:DI 0 "register_operand" "")
3756 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3761 emit_clobber (operands[0]);
3762 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3763 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3764 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3769 (define_insn "*extendsidi2"
3770 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3771 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3777 [(set_attr "op_type" "RRE,RXY,RIL")
3778 (set_attr "type" "*,*,larl")
3779 (set_attr "cpu_facility" "*,*,z10")
3780 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3783 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3786 (define_expand "extend<HQI:mode><DSI:mode>2"
3787 [(set (match_operand:DSI 0 "register_operand" "")
3788 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3791 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3793 rtx tmp = gen_reg_rtx (SImode);
3794 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3795 emit_insn (gen_extendsidi2 (operands[0], tmp));
3798 else if (!TARGET_EXTIMM)
3800 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3802 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3803 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3804 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3810 ; extendhidi2 instruction pattern(s).
3813 (define_insn "*extendhidi2_extimm"
3814 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3815 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3816 "TARGET_ZARCH && TARGET_EXTIMM"
3821 [(set_attr "op_type" "RRE,RXY,RIL")
3822 (set_attr "type" "*,*,larl")
3823 (set_attr "cpu_facility" "extimm,extimm,z10")
3824 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3826 (define_insn "*extendhidi2"
3827 [(set (match_operand:DI 0 "register_operand" "=d")
3828 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3831 [(set_attr "op_type" "RXY")
3832 (set_attr "z10prop" "z10_super_E1")])
3835 ; extendhisi2 instruction pattern(s).
3838 (define_insn "*extendhisi2_extimm"
3839 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3840 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3847 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3848 (set_attr "type" "*,*,*,larl")
3849 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3850 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3852 (define_insn "*extendhisi2"
3853 [(set (match_operand:SI 0 "register_operand" "=d,d")
3854 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3859 [(set_attr "op_type" "RX,RXY")
3860 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3863 ; extendqi(si|di)2 instruction pattern(s).
3866 ; lbr, lgbr, lb, lgb
3867 (define_insn "*extendqi<mode>2_extimm"
3868 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3869 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3874 [(set_attr "op_type" "RRE,RXY")
3875 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3878 (define_insn "*extendqi<mode>2"
3879 [(set (match_operand:GPR 0 "register_operand" "=d")
3880 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3881 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3883 [(set_attr "op_type" "RXY")
3884 (set_attr "z10prop" "z10_super_E1")])
3886 (define_insn_and_split "*extendqi<mode>2_short_displ"
3887 [(set (match_operand:GPR 0 "register_operand" "=d")
3888 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3889 (clobber (reg:CC CC_REGNUM))]
3890 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3892 "&& reload_completed"
3894 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3895 (clobber (reg:CC CC_REGNUM))])
3897 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3898 (clobber (reg:CC CC_REGNUM))])]
3900 operands[1] = adjust_address (operands[1], BLKmode, 0);
3901 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3902 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3906 ; zero_extendsidi2 instruction pattern(s).
3909 (define_expand "zero_extendsidi2"
3910 [(set (match_operand:DI 0 "register_operand" "")
3911 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3916 emit_clobber (operands[0]);
3917 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3918 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3923 (define_insn "*zero_extendsidi2"
3924 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3925 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3931 [(set_attr "op_type" "RRE,RXY,RIL")
3932 (set_attr "type" "*,*,larl")
3933 (set_attr "cpu_facility" "*,*,z10")
3934 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3937 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3940 (define_insn "*llgt_sidi"
3941 [(set (match_operand:DI 0 "register_operand" "=d")
3942 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3943 (const_int 2147483647)))]
3946 [(set_attr "op_type" "RXE")
3947 (set_attr "z10prop" "z10_super_E1")])
3949 (define_insn_and_split "*llgt_sidi_split"
3950 [(set (match_operand:DI 0 "register_operand" "=d")
3951 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3952 (const_int 2147483647)))
3953 (clobber (reg:CC CC_REGNUM))]
3956 "&& reload_completed"
3958 (and:DI (subreg:DI (match_dup 1) 0)
3959 (const_int 2147483647)))]
3962 (define_insn "*llgt_sisi"
3963 [(set (match_operand:SI 0 "register_operand" "=d,d")
3964 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3965 (const_int 2147483647)))]
3970 [(set_attr "op_type" "RRE,RXE")
3971 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3973 (define_insn "*llgt_didi"
3974 [(set (match_operand:DI 0 "register_operand" "=d,d")
3975 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3976 (const_int 2147483647)))]
3981 [(set_attr "op_type" "RRE,RXE")
3982 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3985 [(set (match_operand:DSI 0 "register_operand" "")
3986 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3987 (const_int 2147483647)))
3988 (clobber (reg:CC CC_REGNUM))]
3989 "TARGET_ZARCH && reload_completed"
3991 (and:DSI (match_dup 1)
3992 (const_int 2147483647)))]
3996 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3999 (define_expand "zero_extend<mode>di2"
4000 [(set (match_operand:DI 0 "register_operand" "")
4001 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4006 rtx tmp = gen_reg_rtx (SImode);
4007 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4008 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4011 else if (!TARGET_EXTIMM)
4013 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4014 operands[1] = gen_lowpart (DImode, operands[1]);
4015 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4016 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4021 (define_expand "zero_extend<mode>si2"
4022 [(set (match_operand:SI 0 "register_operand" "")
4023 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4028 operands[1] = gen_lowpart (SImode, operands[1]);
4029 emit_insn (gen_andsi3 (operands[0], operands[1],
4030 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4036 (define_insn "*zero_extendhi<mode>2_z10"
4037 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4038 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4044 [(set_attr "op_type" "RXY,RRE,RIL")
4045 (set_attr "type" "*,*,larl")
4046 (set_attr "cpu_facility" "*,*,z10")
4047 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4049 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4050 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4051 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4052 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4057 [(set_attr "op_type" "RRE,RXY")
4058 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4061 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4062 [(set (match_operand:GPR 0 "register_operand" "=d")
4063 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4064 "TARGET_ZARCH && !TARGET_EXTIMM"
4066 [(set_attr "op_type" "RXY")
4067 (set_attr "z10prop" "z10_fwd_A3")])
4069 (define_insn_and_split "*zero_extendhisi2_31"
4070 [(set (match_operand:SI 0 "register_operand" "=&d")
4071 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4072 (clobber (reg:CC CC_REGNUM))]
4075 "&& reload_completed"
4076 [(set (match_dup 0) (const_int 0))
4078 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4079 (clobber (reg:CC CC_REGNUM))])]
4080 "operands[2] = gen_lowpart (HImode, operands[0]);")
4082 (define_insn_and_split "*zero_extendqisi2_31"
4083 [(set (match_operand:SI 0 "register_operand" "=&d")
4084 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4087 "&& reload_completed"
4088 [(set (match_dup 0) (const_int 0))
4089 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4090 "operands[2] = gen_lowpart (QImode, operands[0]);")
4093 ; zero_extendqihi2 instruction pattern(s).
4096 (define_expand "zero_extendqihi2"
4097 [(set (match_operand:HI 0 "register_operand" "")
4098 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4099 "TARGET_ZARCH && !TARGET_EXTIMM"
4101 operands[1] = gen_lowpart (HImode, operands[1]);
4102 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4106 (define_insn "*zero_extendqihi2_64"
4107 [(set (match_operand:HI 0 "register_operand" "=d")
4108 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4109 "TARGET_ZARCH && !TARGET_EXTIMM"
4111 [(set_attr "op_type" "RXY")
4112 (set_attr "z10prop" "z10_fwd_A3")])
4114 (define_insn_and_split "*zero_extendqihi2_31"
4115 [(set (match_operand:HI 0 "register_operand" "=&d")
4116 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4119 "&& reload_completed"
4120 [(set (match_dup 0) (const_int 0))
4121 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4122 "operands[2] = gen_lowpart (QImode, operands[0]);")
4125 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4128 (define_expand "fixuns_truncdddi2"
4130 [(set (match_operand:DI 0 "register_operand" "")
4131 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4132 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4133 (clobber (reg:CC CC_REGNUM))])]
4139 rtx_code_label *label1 = gen_label_rtx ();
4140 rtx_code_label *label2 = gen_label_rtx ();
4141 rtx temp = gen_reg_rtx (TDmode);
4142 REAL_VALUE_TYPE cmp, sub;
4144 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4145 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4147 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4148 solution is doing the check and the subtraction in TD mode and using a
4149 TD -> DI convert afterwards. */
4150 emit_insn (gen_extendddtd2 (temp, operands[1]));
4151 temp = force_reg (TDmode, temp);
4152 emit_cmp_and_jump_insns (temp,
4153 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4154 LT, NULL_RTX, VOIDmode, 0, label1);
4155 emit_insn (gen_subtd3 (temp, temp,
4156 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4157 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4160 emit_label (label1);
4161 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4162 emit_label (label2);
4167 (define_expand "fixuns_trunctddi2"
4169 [(set (match_operand:DI 0 "register_operand" "")
4170 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4171 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4172 (clobber (reg:CC CC_REGNUM))])]
4178 rtx_code_label *label1 = gen_label_rtx ();
4179 rtx_code_label *label2 = gen_label_rtx ();
4180 rtx temp = gen_reg_rtx (TDmode);
4181 REAL_VALUE_TYPE cmp, sub;
4183 operands[1] = force_reg (TDmode, operands[1]);
4184 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4185 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4187 emit_cmp_and_jump_insns (operands[1],
4188 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4189 LT, NULL_RTX, VOIDmode, 0, label1);
4190 emit_insn (gen_subtd3 (temp, operands[1],
4191 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4192 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4195 emit_label (label1);
4196 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4197 emit_label (label2);
4203 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4204 ; instruction pattern(s).
4207 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4209 [(set (match_operand:GPR 0 "register_operand" "")
4210 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4211 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4212 (clobber (reg:CC CC_REGNUM))])]
4217 rtx_code_label *label1 = gen_label_rtx ();
4218 rtx_code_label *label2 = gen_label_rtx ();
4219 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4220 REAL_VALUE_TYPE cmp, sub;
4222 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4223 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4224 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4226 emit_cmp_and_jump_insns (operands[1],
4227 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4228 LT, NULL_RTX, VOIDmode, 0, label1);
4229 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4230 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4231 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4235 emit_label (label1);
4236 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4237 operands[1], GEN_INT (5)));
4238 emit_label (label2);
4243 ; fixuns_trunc(td|dd)si2 expander
4244 (define_expand "fixuns_trunc<mode>si2"
4246 [(set (match_operand:SI 0 "register_operand" "")
4247 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4248 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4249 (clobber (reg:CC CC_REGNUM))])]
4250 "TARGET_Z196 && TARGET_HARD_DFP"
4253 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4255 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4256 ; clfdtr, clfxtr, clgdtr, clgxtr
4257 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4258 [(set (match_operand:GPR 0 "register_operand" "=r")
4259 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4260 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4261 (clobber (reg:CC CC_REGNUM))]
4263 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4264 [(set_attr "op_type" "RRF")
4265 (set_attr "type" "ftoi")])
4267 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4268 [(set (match_operand:GPR 0 "register_operand" "")
4269 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4272 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4277 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4278 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4279 [(set (match_operand:GPR 0 "register_operand" "=d")
4280 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4281 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4282 (clobber (reg:CC CC_REGNUM))]
4284 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4285 [(set_attr "op_type" "RRE")
4286 (set_attr "type" "ftoi")])
4290 ; fix_trunc(td|dd)di2 instruction pattern(s).
4293 (define_expand "fix_trunc<mode>di2"
4294 [(set (match_operand:DI 0 "register_operand" "")
4295 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4296 "TARGET_ZARCH && TARGET_HARD_DFP"
4298 operands[1] = force_reg (<MODE>mode, operands[1]);
4299 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4305 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4306 [(set (match_operand:DI 0 "register_operand" "=d")
4307 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4308 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4309 (clobber (reg:CC CC_REGNUM))]
4310 "TARGET_ZARCH && TARGET_HARD_DFP"
4311 "cg<DFP:xde>tr\t%0,%h2,%1"
4312 [(set_attr "op_type" "RRF")
4313 (set_attr "type" "ftoidfp")])
4317 ; fix_trunctf(si|di)2 instruction pattern(s).
4320 (define_expand "fix_trunctf<mode>2"
4321 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4322 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4323 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4324 (clobber (reg:CC CC_REGNUM))])]
4330 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4333 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4334 (define_insn "floatdi<mode>2"
4335 [(set (match_operand:FP 0 "register_operand" "=f")
4336 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4337 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4338 "c<xde>g<bt>r\t%0,%1"
4339 [(set_attr "op_type" "RRE")
4340 (set_attr "type" "itof<mode>" )])
4342 ; cxfbr, cdfbr, cefbr
4343 (define_insn "floatsi<mode>2"
4344 [(set (match_operand:BFP 0 "register_operand" "=f")
4345 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4348 [(set_attr "op_type" "RRE")
4349 (set_attr "type" "itof<mode>" )])
4352 (define_insn "floatsi<mode>2"
4353 [(set (match_operand:DFP 0 "register_operand" "=f")
4354 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4355 "TARGET_Z196 && TARGET_HARD_FLOAT"
4356 "c<xde>ftr\t%0,0,%1,0"
4357 [(set_attr "op_type" "RRE")
4358 (set_attr "type" "itof<mode>" )])
4361 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4364 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4365 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4366 (define_insn "floatuns<GPR:mode><FP:mode>2"
4367 [(set (match_operand:FP 0 "register_operand" "=f")
4368 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4369 "TARGET_Z196 && TARGET_HARD_FLOAT"
4370 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4371 [(set_attr "op_type" "RRE")
4372 (set_attr "type" "itof<FP:mode>" )])
4375 ; truncdfsf2 instruction pattern(s).
4378 (define_insn "truncdfsf2"
4379 [(set (match_operand:SF 0 "register_operand" "=f")
4380 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4383 [(set_attr "op_type" "RRE")
4384 (set_attr "type" "ftruncdf")])
4387 ; trunctf(df|sf)2 instruction pattern(s).
4391 (define_insn "trunctf<mode>2"
4392 [(set (match_operand:DSF 0 "register_operand" "=f")
4393 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4394 (clobber (match_scratch:TF 2 "=f"))]
4396 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4397 [(set_attr "length" "6")
4398 (set_attr "type" "ftrunctf")])
4401 ; trunctddd2 and truncddsd2 instruction pattern(s).
4404 (define_insn "trunctddd2"
4405 [(set (match_operand:DD 0 "register_operand" "=f")
4406 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4407 (clobber (match_scratch:TD 2 "=f"))]
4409 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4410 [(set_attr "length" "6")
4411 (set_attr "type" "ftruncdd")])
4413 (define_insn "truncddsd2"
4414 [(set (match_operand:SD 0 "register_operand" "=f")
4415 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4418 [(set_attr "op_type" "RRF")
4419 (set_attr "type" "ftruncsd")])
4421 (define_expand "trunctdsd2"
4424 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4425 (clobber (match_scratch:TD 2 ""))])
4426 (set (match_operand:SD 0 "register_operand" "")
4427 (float_truncate:SD (match_dup 3)))]
4430 operands[3] = gen_reg_rtx (DDmode);
4434 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4437 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4438 (define_insn "extend<DSF:mode><BFP:mode>2"
4439 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4440 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4442 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4444 l<BFP:xde><DSF:xde>br\t%0,%1
4445 l<BFP:xde><DSF:xde>b\t%0,%1"
4446 [(set_attr "op_type" "RRE,RXE")
4447 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4450 ; extendddtd2 and extendsddd2 instruction pattern(s).
4453 (define_insn "extendddtd2"
4454 [(set (match_operand:TD 0 "register_operand" "=f")
4455 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4458 [(set_attr "op_type" "RRF")
4459 (set_attr "type" "fsimptf")])
4461 (define_insn "extendsddd2"
4462 [(set (match_operand:DD 0 "register_operand" "=f")
4463 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4466 [(set_attr "op_type" "RRF")
4467 (set_attr "type" "fsimptf")])
4469 (define_expand "extendsdtd2"
4471 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4472 (set (match_operand:TD 0 "register_operand" "")
4473 (float_extend:TD (match_dup 2)))]
4476 operands[2] = gen_reg_rtx (DDmode);
4479 ; Binary Floating Point - load fp integer
4481 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4482 ; For all of them the inexact exceptions are suppressed.
4484 ; fiebra, fidbra, fixbra
4485 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4486 [(set (match_operand:BFP 0 "register_operand" "=f")
4487 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4490 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4491 [(set_attr "op_type" "RRF")
4492 (set_attr "type" "fsimp<BFP:mode>")])
4494 ; rint is supposed to raise an inexact exception so we can use the
4495 ; older instructions.
4497 ; fiebr, fidbr, fixbr
4498 (define_insn "rint<BFP:mode>2"
4499 [(set (match_operand:BFP 0 "register_operand" "=f")
4500 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4501 UNSPEC_FPINT_RINT))]
4503 "fi<BFP:xde>br\t%0,0,%1"
4504 [(set_attr "op_type" "RRF")
4505 (set_attr "type" "fsimp<BFP:mode>")])
4508 ; Decimal Floating Point - load fp integer
4511 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4512 [(set (match_operand:DFP 0 "register_operand" "=f")
4513 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4516 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4517 [(set_attr "op_type" "RRF")
4518 (set_attr "type" "fsimp<DFP:mode>")])
4521 (define_insn "rint<DFP:mode>2"
4522 [(set (match_operand:DFP 0 "register_operand" "=f")
4523 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4524 UNSPEC_FPINT_RINT))]
4526 "fi<DFP:xde>tr\t%0,0,%1,0"
4527 [(set_attr "op_type" "RRF")
4528 (set_attr "type" "fsimp<DFP:mode>")])
4531 ; Binary <-> Decimal floating point trunc patterns
4534 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4535 [(set (reg:DFP_ALL FPR0_REGNUM)
4536 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4537 (use (reg:SI GPR0_REGNUM))
4538 (clobber (reg:CC CC_REGNUM))]
4542 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4543 [(set (reg:BFP FPR0_REGNUM)
4544 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4545 (use (reg:SI GPR0_REGNUM))
4546 (clobber (reg:CC CC_REGNUM))]
4550 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4551 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4552 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4554 [(set (reg:DFP_ALL FPR0_REGNUM)
4555 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4556 (use (reg:SI GPR0_REGNUM))
4557 (clobber (reg:CC CC_REGNUM))])
4558 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4559 (reg:DFP_ALL FPR0_REGNUM))]
4561 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4563 HOST_WIDE_INT flags;
4565 flags = (PFPO_CONVERT |
4566 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4567 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4569 operands[2] = GEN_INT (flags);
4572 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4573 [(set (reg:DFP_ALL FPR4_REGNUM)
4574 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4575 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4577 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4578 (use (reg:SI GPR0_REGNUM))
4579 (clobber (reg:CC CC_REGNUM))])
4580 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4582 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4584 HOST_WIDE_INT flags;
4586 flags = (PFPO_CONVERT |
4587 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4588 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4590 operands[2] = GEN_INT (flags);
4594 ; Binary <-> Decimal floating point extend patterns
4597 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4598 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4599 (use (reg:SI GPR0_REGNUM))
4600 (clobber (reg:CC CC_REGNUM))]
4604 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4605 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4606 (use (reg:SI GPR0_REGNUM))
4607 (clobber (reg:CC CC_REGNUM))]
4611 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4612 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4613 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4615 [(set (reg:DFP_ALL FPR0_REGNUM)
4616 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4617 (use (reg:SI GPR0_REGNUM))
4618 (clobber (reg:CC CC_REGNUM))])
4619 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4620 (reg:DFP_ALL FPR0_REGNUM))]
4622 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4624 HOST_WIDE_INT flags;
4626 flags = (PFPO_CONVERT |
4627 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4628 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4630 operands[2] = GEN_INT (flags);
4633 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4634 [(set (reg:DFP_ALL FPR4_REGNUM)
4635 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4636 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4638 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4639 (use (reg:SI GPR0_REGNUM))
4640 (clobber (reg:CC CC_REGNUM))])
4641 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4643 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4645 HOST_WIDE_INT flags;
4647 flags = (PFPO_CONVERT |
4648 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4649 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4651 operands[2] = GEN_INT (flags);
4656 ;; ARITHMETIC OPERATIONS
4658 ; arithmetic operations set the ConditionCode,
4659 ; because of unpredictable Bits in Register for Halfword and Byte
4660 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4663 ;;- Add instructions.
4667 ; addti3 instruction pattern(s).
4670 (define_insn_and_split "addti3"
4671 [(set (match_operand:TI 0 "register_operand" "=&d")
4672 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4673 (match_operand:TI 2 "general_operand" "do") ) )
4674 (clobber (reg:CC CC_REGNUM))]
4677 "&& reload_completed"
4679 [(set (reg:CCL1 CC_REGNUM)
4680 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4682 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4684 [(set (match_dup 3) (plus:DI
4685 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4686 (match_dup 4)) (match_dup 5)))
4687 (clobber (reg:CC CC_REGNUM))])]
4688 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4689 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4690 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4691 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4692 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4693 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4696 ; adddi3 instruction pattern(s).
4699 (define_expand "adddi3"
4701 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4702 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4703 (match_operand:DI 2 "general_operand" "")))
4704 (clobber (reg:CC CC_REGNUM))])]
4708 (define_insn "*adddi3_sign"
4709 [(set (match_operand:DI 0 "register_operand" "=d,d")
4710 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4711 (match_operand:DI 1 "register_operand" "0,0")))
4712 (clobber (reg:CC CC_REGNUM))]
4717 [(set_attr "op_type" "RRE,RXY")
4718 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4720 (define_insn "*adddi3_zero_cc"
4721 [(set (reg CC_REGNUM)
4722 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4723 (match_operand:DI 1 "register_operand" "0,0"))
4725 (set (match_operand:DI 0 "register_operand" "=d,d")
4726 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4727 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4731 [(set_attr "op_type" "RRE,RXY")
4732 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4734 (define_insn "*adddi3_zero_cconly"
4735 [(set (reg CC_REGNUM)
4736 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4737 (match_operand:DI 1 "register_operand" "0,0"))
4739 (clobber (match_scratch:DI 0 "=d,d"))]
4740 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4744 [(set_attr "op_type" "RRE,RXY")
4745 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4747 (define_insn "*adddi3_zero"
4748 [(set (match_operand:DI 0 "register_operand" "=d,d")
4749 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4750 (match_operand:DI 1 "register_operand" "0,0")))
4751 (clobber (reg:CC CC_REGNUM))]
4756 [(set_attr "op_type" "RRE,RXY")
4757 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4759 (define_insn_and_split "*adddi3_31z"
4760 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4761 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4762 (match_operand:DI 2 "general_operand" "do") ) )
4763 (clobber (reg:CC CC_REGNUM))]
4764 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4766 "&& reload_completed"
4768 [(set (reg:CCL1 CC_REGNUM)
4769 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4771 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4773 [(set (match_dup 3) (plus:SI
4774 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4775 (match_dup 4)) (match_dup 5)))
4776 (clobber (reg:CC CC_REGNUM))])]
4777 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4778 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4779 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4780 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4781 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4782 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4784 (define_insn_and_split "*adddi3_31"
4785 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4786 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4787 (match_operand:DI 2 "general_operand" "do") ) )
4788 (clobber (reg:CC CC_REGNUM))]
4791 "&& reload_completed"
4793 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4794 (clobber (reg:CC CC_REGNUM))])
4796 [(set (reg:CCL1 CC_REGNUM)
4797 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4799 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4801 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4803 (label_ref (match_dup 9))))
4805 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4806 (clobber (reg:CC CC_REGNUM))])
4808 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4809 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4810 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4811 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4812 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4813 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4814 operands[9] = gen_label_rtx ();")
4817 ; addsi3 instruction pattern(s).
4820 (define_expand "addsi3"
4822 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4823 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4824 (match_operand:SI 2 "general_operand" "")))
4825 (clobber (reg:CC CC_REGNUM))])]
4829 (define_insn "*addsi3_sign"
4830 [(set (match_operand:SI 0 "register_operand" "=d,d")
4831 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4832 (match_operand:SI 1 "register_operand" "0,0")))
4833 (clobber (reg:CC CC_REGNUM))]
4838 [(set_attr "op_type" "RX,RXY")
4839 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4842 ; add(di|si)3 instruction pattern(s).
4845 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4846 (define_insn "*add<mode>3"
4847 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4848 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4849 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4850 (clobber (reg:CC CC_REGNUM))]
4862 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4863 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4864 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4865 z10_super_E1,z10_super_E1,z10_super_E1")])
4867 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4868 (define_insn "*add<mode>3_carry1_cc"
4869 [(set (reg CC_REGNUM)
4870 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4871 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4873 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4874 (plus:GPR (match_dup 1) (match_dup 2)))]
4875 "s390_match_ccmode (insn, CCL1mode)"
4881 al<g>hsik\t%0,%1,%h2
4885 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4886 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4887 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4888 z10_super_E1,z10_super_E1,z10_super_E1")])
4890 ; alr, al, aly, algr, alg, alrk, algrk
4891 (define_insn "*add<mode>3_carry1_cconly"
4892 [(set (reg CC_REGNUM)
4893 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4894 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4896 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4897 "s390_match_ccmode (insn, CCL1mode)"
4903 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4904 (set_attr "cpu_facility" "*,z196,*,*")
4905 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4907 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4908 (define_insn "*add<mode>3_carry2_cc"
4909 [(set (reg CC_REGNUM)
4910 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4911 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4913 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4914 (plus:GPR (match_dup 1) (match_dup 2)))]
4915 "s390_match_ccmode (insn, CCL1mode)"
4921 al<g>hsik\t%0,%1,%h2
4925 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4926 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4927 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4928 z10_super_E1,z10_super_E1,z10_super_E1")])
4930 ; alr, al, aly, algr, alg, alrk, algrk
4931 (define_insn "*add<mode>3_carry2_cconly"
4932 [(set (reg CC_REGNUM)
4933 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4934 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4936 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4937 "s390_match_ccmode (insn, CCL1mode)"
4943 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4944 (set_attr "cpu_facility" "*,z196,*,*")
4945 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4947 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4948 (define_insn "*add<mode>3_cc"
4949 [(set (reg CC_REGNUM)
4950 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4951 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4953 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4954 (plus:GPR (match_dup 1) (match_dup 2)))]
4955 "s390_match_ccmode (insn, CCLmode)"
4961 al<g>hsik\t%0,%1,%h2
4965 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4966 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4967 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4968 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4970 ; alr, al, aly, algr, alg, alrk, algrk
4971 (define_insn "*add<mode>3_cconly"
4972 [(set (reg CC_REGNUM)
4973 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4974 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4976 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4977 "s390_match_ccmode (insn, CCLmode)"
4983 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4984 (set_attr "cpu_facility" "*,z196,*,*")
4985 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4987 ; alr, al, aly, algr, alg, alrk, algrk
4988 (define_insn "*add<mode>3_cconly2"
4989 [(set (reg CC_REGNUM)
4990 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4991 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4992 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4993 "s390_match_ccmode(insn, CCLmode)"
4999 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5000 (set_attr "cpu_facility" "*,z196,*,*")
5001 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5003 ; ahi, afi, aghi, agfi, asi, agsi
5004 (define_insn "*add<mode>3_imm_cc"
5005 [(set (reg CC_REGNUM)
5006 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5007 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
5009 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
5010 (plus:GPR (match_dup 1) (match_dup 2)))]
5011 "s390_match_ccmode (insn, CCAmode)
5012 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5013 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5014 /* Avoid INT32_MIN on 32 bit. */
5015 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5021 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5022 (set_attr "cpu_facility" "*,z196,extimm,z10")
5023 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5026 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5029 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5030 (define_insn "add<mode>3"
5031 [(set (match_operand:FP 0 "register_operand" "=f, f")
5032 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5033 (match_operand:FP 2 "general_operand" " f,<Rf>")))
5034 (clobber (reg:CC CC_REGNUM))]
5037 a<xde><bt>r\t%0,<op1>%2
5039 [(set_attr "op_type" "<RRer>,RXE")
5040 (set_attr "type" "fsimp<mode>")])
5042 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5043 (define_insn "*add<mode>3_cc"
5044 [(set (reg CC_REGNUM)
5045 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5046 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5047 (match_operand:FP 3 "const0_operand" "")))
5048 (set (match_operand:FP 0 "register_operand" "=f,f")
5049 (plus:FP (match_dup 1) (match_dup 2)))]
5050 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5052 a<xde><bt>r\t%0,<op1>%2
5054 [(set_attr "op_type" "<RRer>,RXE")
5055 (set_attr "type" "fsimp<mode>")])
5057 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5058 (define_insn "*add<mode>3_cconly"
5059 [(set (reg CC_REGNUM)
5060 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5061 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5062 (match_operand:FP 3 "const0_operand" "")))
5063 (clobber (match_scratch:FP 0 "=f,f"))]
5064 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5066 a<xde><bt>r\t%0,<op1>%2
5068 [(set_attr "op_type" "<RRer>,RXE")
5069 (set_attr "type" "fsimp<mode>")])
5072 ; Pointer add instruction patterns
5075 ; This will match "*la_64"
5076 (define_expand "addptrdi3"
5077 [(set (match_operand:DI 0 "register_operand" "")
5078 (plus:DI (match_operand:DI 1 "register_operand" "")
5079 (match_operand:DI 2 "nonmemory_operand" "")))]
5082 if (GET_CODE (operands[2]) == CONST_INT)
5084 HOST_WIDE_INT c = INTVAL (operands[2]);
5086 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5087 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5089 operands[2] = force_const_mem (DImode, operands[2]);
5090 operands[2] = force_reg (DImode, operands[2]);
5092 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5093 operands[2] = force_reg (DImode, operands[2]);
5097 ; For 31 bit we have to prevent the generated pattern from matching
5098 ; normal ADDs since la only does a 31 bit add. This is supposed to
5099 ; match "force_la_31".
5100 (define_expand "addptrsi3"
5102 [(set (match_operand:SI 0 "register_operand" "")
5103 (plus:SI (match_operand:SI 1 "register_operand" "")
5104 (match_operand:SI 2 "nonmemory_operand" "")))
5105 (use (const_int 0))])]
5108 if (GET_CODE (operands[2]) == CONST_INT)
5110 HOST_WIDE_INT c = INTVAL (operands[2]);
5112 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5113 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5115 operands[2] = force_const_mem (SImode, operands[2]);
5116 operands[2] = force_reg (SImode, operands[2]);
5118 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5119 operands[2] = force_reg (SImode, operands[2]);
5124 ;;- Subtract instructions.
5128 ; subti3 instruction pattern(s).
5131 (define_insn_and_split "subti3"
5132 [(set (match_operand:TI 0 "register_operand" "=&d")
5133 (minus:TI (match_operand:TI 1 "register_operand" "0")
5134 (match_operand:TI 2 "general_operand" "do") ) )
5135 (clobber (reg:CC CC_REGNUM))]
5138 "&& reload_completed"
5140 [(set (reg:CCL2 CC_REGNUM)
5141 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5143 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5145 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5146 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5147 (clobber (reg:CC CC_REGNUM))])]
5148 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5149 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5150 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5151 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5152 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5153 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
5156 ; subdi3 instruction pattern(s).
5159 (define_expand "subdi3"
5161 [(set (match_operand:DI 0 "register_operand" "")
5162 (minus:DI (match_operand:DI 1 "register_operand" "")
5163 (match_operand:DI 2 "general_operand" "")))
5164 (clobber (reg:CC CC_REGNUM))])]
5168 (define_insn "*subdi3_sign"
5169 [(set (match_operand:DI 0 "register_operand" "=d,d")
5170 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5171 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5172 (clobber (reg:CC CC_REGNUM))]
5177 [(set_attr "op_type" "RRE,RXY")
5178 (set_attr "z10prop" "z10_c,*")
5179 (set_attr "z196prop" "z196_cracked")])
5181 (define_insn "*subdi3_zero_cc"
5182 [(set (reg CC_REGNUM)
5183 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5184 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5186 (set (match_operand:DI 0 "register_operand" "=d,d")
5187 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5188 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5192 [(set_attr "op_type" "RRE,RXY")
5193 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5195 (define_insn "*subdi3_zero_cconly"
5196 [(set (reg CC_REGNUM)
5197 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5198 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5200 (clobber (match_scratch:DI 0 "=d,d"))]
5201 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5205 [(set_attr "op_type" "RRE,RXY")
5206 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5208 (define_insn "*subdi3_zero"
5209 [(set (match_operand:DI 0 "register_operand" "=d,d")
5210 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5211 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5212 (clobber (reg:CC CC_REGNUM))]
5217 [(set_attr "op_type" "RRE,RXY")
5218 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5220 (define_insn_and_split "*subdi3_31z"
5221 [(set (match_operand:DI 0 "register_operand" "=&d")
5222 (minus:DI (match_operand:DI 1 "register_operand" "0")
5223 (match_operand:DI 2 "general_operand" "do") ) )
5224 (clobber (reg:CC CC_REGNUM))]
5225 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5227 "&& reload_completed"
5229 [(set (reg:CCL2 CC_REGNUM)
5230 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5232 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5234 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5235 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5236 (clobber (reg:CC CC_REGNUM))])]
5237 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5238 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5239 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5240 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5241 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5242 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5244 (define_insn_and_split "*subdi3_31"
5245 [(set (match_operand:DI 0 "register_operand" "=&d")
5246 (minus:DI (match_operand:DI 1 "register_operand" "0")
5247 (match_operand:DI 2 "general_operand" "do") ) )
5248 (clobber (reg:CC CC_REGNUM))]
5251 "&& reload_completed"
5253 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5254 (clobber (reg:CC CC_REGNUM))])
5256 [(set (reg:CCL2 CC_REGNUM)
5257 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5259 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5261 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5263 (label_ref (match_dup 9))))
5265 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5266 (clobber (reg:CC CC_REGNUM))])
5268 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5269 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5270 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5271 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5272 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5273 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5274 operands[9] = gen_label_rtx ();")
5277 ; subsi3 instruction pattern(s).
5280 (define_expand "subsi3"
5282 [(set (match_operand:SI 0 "register_operand" "")
5283 (minus:SI (match_operand:SI 1 "register_operand" "")
5284 (match_operand:SI 2 "general_operand" "")))
5285 (clobber (reg:CC CC_REGNUM))])]
5289 (define_insn "*subsi3_sign"
5290 [(set (match_operand:SI 0 "register_operand" "=d,d")
5291 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5292 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5293 (clobber (reg:CC CC_REGNUM))]
5298 [(set_attr "op_type" "RX,RXY")
5299 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5302 ; sub(di|si)3 instruction pattern(s).
5305 ; sr, s, sy, sgr, sg, srk, sgrk
5306 (define_insn "*sub<mode>3"
5307 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5308 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5309 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5310 (clobber (reg:CC CC_REGNUM))]
5317 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5318 (set_attr "cpu_facility" "*,z196,*,*")
5319 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5321 ; slr, sl, sly, slgr, slg, slrk, slgrk
5322 (define_insn "*sub<mode>3_borrow_cc"
5323 [(set (reg CC_REGNUM)
5324 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5325 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5327 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5328 (minus:GPR (match_dup 1) (match_dup 2)))]
5329 "s390_match_ccmode (insn, CCL2mode)"
5335 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5336 (set_attr "cpu_facility" "*,z196,*,*")
5337 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5339 ; slr, sl, sly, slgr, slg, slrk, slgrk
5340 (define_insn "*sub<mode>3_borrow_cconly"
5341 [(set (reg CC_REGNUM)
5342 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5343 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5345 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5346 "s390_match_ccmode (insn, CCL2mode)"
5352 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5353 (set_attr "cpu_facility" "*,z196,*,*")
5354 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5356 ; slr, sl, sly, slgr, slg, slrk, slgrk
5357 (define_insn "*sub<mode>3_cc"
5358 [(set (reg CC_REGNUM)
5359 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5360 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5362 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5363 (minus:GPR (match_dup 1) (match_dup 2)))]
5364 "s390_match_ccmode (insn, CCLmode)"
5370 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5371 (set_attr "cpu_facility" "*,z196,*,*")
5372 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5374 ; slr, sl, sly, slgr, slg, slrk, slgrk
5375 (define_insn "*sub<mode>3_cc2"
5376 [(set (reg CC_REGNUM)
5377 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5378 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5379 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5380 (minus:GPR (match_dup 1) (match_dup 2)))]
5381 "s390_match_ccmode (insn, CCL3mode)"
5387 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5388 (set_attr "cpu_facility" "*,z196,*,*")
5389 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5391 ; slr, sl, sly, slgr, slg, slrk, slgrk
5392 (define_insn "*sub<mode>3_cconly"
5393 [(set (reg CC_REGNUM)
5394 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5395 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5397 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5398 "s390_match_ccmode (insn, CCLmode)"
5404 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5405 (set_attr "cpu_facility" "*,z196,*,*")
5406 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5409 ; slr, sl, sly, slgr, slg, slrk, slgrk
5410 (define_insn "*sub<mode>3_cconly2"
5411 [(set (reg CC_REGNUM)
5412 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5413 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5414 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5415 "s390_match_ccmode (insn, CCL3mode)"
5421 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5422 (set_attr "cpu_facility" "*,z196,*,*")
5423 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5427 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5430 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5431 (define_insn "sub<mode>3"
5432 [(set (match_operand:FP 0 "register_operand" "=f, f")
5433 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5434 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5435 (clobber (reg:CC CC_REGNUM))]
5438 s<xde><bt>r\t%0,<op1>%2
5440 [(set_attr "op_type" "<RRer>,RXE")
5441 (set_attr "type" "fsimp<mode>")])
5443 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5444 (define_insn "*sub<mode>3_cc"
5445 [(set (reg CC_REGNUM)
5446 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5447 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5448 (match_operand:FP 3 "const0_operand" "")))
5449 (set (match_operand:FP 0 "register_operand" "=f,f")
5450 (minus:FP (match_dup 1) (match_dup 2)))]
5451 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5453 s<xde><bt>r\t%0,<op1>%2
5455 [(set_attr "op_type" "<RRer>,RXE")
5456 (set_attr "type" "fsimp<mode>")])
5458 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5459 (define_insn "*sub<mode>3_cconly"
5460 [(set (reg CC_REGNUM)
5461 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5462 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5463 (match_operand:FP 3 "const0_operand" "")))
5464 (clobber (match_scratch:FP 0 "=f,f"))]
5465 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5467 s<xde><bt>r\t%0,<op1>%2
5469 [(set_attr "op_type" "<RRer>,RXE")
5470 (set_attr "type" "fsimp<mode>")])
5474 ;;- Conditional add/subtract instructions.
5478 ; add(di|si)cc instruction pattern(s).
5481 ; the following 4 patterns are used when the result of an add with
5482 ; carry is checked for an overflow condition
5484 ; op1 + op2 + c < op1
5486 ; alcr, alc, alcgr, alcg
5487 (define_insn "*add<mode>3_alc_carry1_cc"
5488 [(set (reg CC_REGNUM)
5490 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5491 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5492 (match_operand:GPR 2 "general_operand" "d,RT"))
5494 (set (match_operand:GPR 0 "register_operand" "=d,d")
5495 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5496 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5500 [(set_attr "op_type" "RRE,RXY")
5501 (set_attr "z196prop" "z196_alone,z196_alone")])
5503 ; alcr, alc, alcgr, alcg
5504 (define_insn "*add<mode>3_alc_carry1_cconly"
5505 [(set (reg CC_REGNUM)
5507 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5508 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5509 (match_operand:GPR 2 "general_operand" "d,RT"))
5511 (clobber (match_scratch:GPR 0 "=d,d"))]
5512 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5516 [(set_attr "op_type" "RRE,RXY")
5517 (set_attr "z196prop" "z196_alone,z196_alone")])
5519 ; op1 + op2 + c < op2
5521 ; alcr, alc, alcgr, alcg
5522 (define_insn "*add<mode>3_alc_carry2_cc"
5523 [(set (reg CC_REGNUM)
5525 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5526 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5527 (match_operand:GPR 2 "general_operand" "d,RT"))
5529 (set (match_operand:GPR 0 "register_operand" "=d,d")
5530 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5531 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5535 [(set_attr "op_type" "RRE,RXY")])
5537 ; alcr, alc, alcgr, alcg
5538 (define_insn "*add<mode>3_alc_carry2_cconly"
5539 [(set (reg CC_REGNUM)
5541 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5542 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5543 (match_operand:GPR 2 "general_operand" "d,RT"))
5545 (clobber (match_scratch:GPR 0 "=d,d"))]
5546 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5550 [(set_attr "op_type" "RRE,RXY")])
5552 ; alcr, alc, alcgr, alcg
5553 (define_insn "*add<mode>3_alc_cc"
5554 [(set (reg CC_REGNUM)
5556 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5557 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5558 (match_operand:GPR 2 "general_operand" "d,RT"))
5560 (set (match_operand:GPR 0 "register_operand" "=d,d")
5561 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5562 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5566 [(set_attr "op_type" "RRE,RXY")])
5568 ; alcr, alc, alcgr, alcg
5569 (define_insn "*add<mode>3_alc"
5570 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5571 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5572 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5573 (match_operand:GPR 2 "general_operand" "d,RT")))
5574 (clobber (reg:CC CC_REGNUM))]
5579 [(set_attr "op_type" "RRE,RXY")])
5581 ; slbr, slb, slbgr, slbg
5582 (define_insn "*sub<mode>3_slb_cc"
5583 [(set (reg CC_REGNUM)
5585 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5586 (match_operand:GPR 2 "general_operand" "d,RT"))
5587 (match_operand:GPR 3 "s390_slb_comparison" ""))
5589 (set (match_operand:GPR 0 "register_operand" "=d,d")
5590 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5591 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5595 [(set_attr "op_type" "RRE,RXY")
5596 (set_attr "z10prop" "z10_c,*")])
5598 ; slbr, slb, slbgr, slbg
5599 (define_insn "*sub<mode>3_slb"
5600 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5601 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5602 (match_operand:GPR 2 "general_operand" "d,RT"))
5603 (match_operand:GPR 3 "s390_slb_comparison" "")))
5604 (clobber (reg:CC CC_REGNUM))]
5609 [(set_attr "op_type" "RRE,RXY")
5610 (set_attr "z10prop" "z10_c,*")])
5612 (define_expand "add<mode>cc"
5613 [(match_operand:GPR 0 "register_operand" "")
5614 (match_operand 1 "comparison_operator" "")
5615 (match_operand:GPR 2 "register_operand" "")
5616 (match_operand:GPR 3 "const_int_operand" "")]
5618 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5619 XEXP (operands[1], 0), XEXP (operands[1], 1),
5620 operands[0], operands[2],
5621 operands[3])) FAIL; DONE;")
5624 ; scond instruction pattern(s).
5627 (define_insn_and_split "*scond<mode>"
5628 [(set (match_operand:GPR 0 "register_operand" "=&d")
5629 (match_operand:GPR 1 "s390_alc_comparison" ""))
5630 (clobber (reg:CC CC_REGNUM))]
5633 "&& reload_completed"
5634 [(set (match_dup 0) (const_int 0))
5636 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5638 (clobber (reg:CC CC_REGNUM))])]
5641 (define_insn_and_split "*scond<mode>_neg"
5642 [(set (match_operand:GPR 0 "register_operand" "=&d")
5643 (match_operand:GPR 1 "s390_slb_comparison" ""))
5644 (clobber (reg:CC CC_REGNUM))]
5647 "&& reload_completed"
5648 [(set (match_dup 0) (const_int 0))
5650 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5652 (clobber (reg:CC CC_REGNUM))])
5654 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5655 (clobber (reg:CC CC_REGNUM))])]
5659 (define_expand "cstore<mode>4"
5660 [(set (match_operand:SI 0 "register_operand" "")
5661 (match_operator:SI 1 "s390_scond_operator"
5662 [(match_operand:GPR 2 "register_operand" "")
5663 (match_operand:GPR 3 "general_operand" "")]))]
5665 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5666 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5668 (define_expand "cstorecc4"
5670 [(set (match_operand:SI 0 "register_operand" "")
5671 (match_operator:SI 1 "s390_eqne_operator"
5672 [(match_operand:CCZ1 2 "register_operand")
5673 (match_operand 3 "const0_operand")]))
5674 (clobber (reg:CC CC_REGNUM))])]
5676 "emit_insn (gen_sne (operands[0], operands[2]));
5677 if (GET_CODE (operands[1]) == EQ)
5678 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5681 (define_insn_and_split "sne"
5682 [(set (match_operand:SI 0 "register_operand" "=d")
5683 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5685 (clobber (reg:CC CC_REGNUM))]
5690 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5691 (clobber (reg:CC CC_REGNUM))])])
5695 ;; - Conditional move instructions (introduced with z196)
5698 (define_expand "mov<mode>cc"
5699 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5700 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5701 (match_operand:GPR 2 "nonimmediate_operand" "")
5702 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5704 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5705 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5707 ; locr, loc, stoc, locgr, locg, stocg
5708 (define_insn_and_split "*mov<mode>cc"
5709 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5711 (match_operator 1 "s390_comparison"
5712 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5713 (match_operand 5 "const_int_operand" "")])
5714 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5715 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5725 "&& reload_completed
5726 && MEM_P (operands[3]) && MEM_P (operands[4])"
5729 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5734 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5738 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5741 ;;- Multiply instructions.
5745 ; muldi3 instruction pattern(s).
5748 (define_insn "*muldi3_sign"
5749 [(set (match_operand:DI 0 "register_operand" "=d,d")
5750 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5751 (match_operand:DI 1 "register_operand" "0,0")))]
5756 [(set_attr "op_type" "RRE,RXY")
5757 (set_attr "type" "imuldi")])
5759 (define_insn "muldi3"
5760 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5761 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5762 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5769 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5770 (set_attr "type" "imuldi")
5771 (set_attr "cpu_facility" "*,*,*,z10")])
5774 ; mulsi3 instruction pattern(s).
5777 (define_insn "*mulsi3_sign"
5778 [(set (match_operand:SI 0 "register_operand" "=d,d")
5779 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5780 (match_operand:SI 1 "register_operand" "0,0")))]
5785 [(set_attr "op_type" "RX,RXY")
5786 (set_attr "type" "imulhi")
5787 (set_attr "cpu_facility" "*,z10")])
5789 (define_insn "mulsi3"
5790 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5791 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5792 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5800 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5801 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5802 (set_attr "cpu_facility" "*,*,*,*,z10")])
5805 ; mulsidi3 instruction pattern(s).
5808 (define_insn "mulsidi3"
5809 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5810 (mult:DI (sign_extend:DI
5811 (match_operand:SI 1 "register_operand" "%0,0,0"))
5813 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5819 [(set_attr "op_type" "RR,RX,RXY")
5820 (set_attr "type" "imulsi")
5821 (set_attr "cpu_facility" "*,*,z10")])
5824 ; umul instruction pattern(s).
5827 ; mlr, ml, mlgr, mlg
5828 (define_insn "umul<dwh><mode>3"
5829 [(set (match_operand:DW 0 "register_operand" "=d, d")
5830 (mult:DW (zero_extend:DW
5831 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5833 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5838 [(set_attr "op_type" "RRE,RXY")
5839 (set_attr "type" "imul<dwh>")])
5842 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5845 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5846 (define_insn "mul<mode>3"
5847 [(set (match_operand:FP 0 "register_operand" "=f,f")
5848 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5849 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5852 m<xdee><bt>r\t%0,<op1>%2
5854 [(set_attr "op_type" "<RRer>,RXE")
5855 (set_attr "type" "fmul<mode>")])
5857 ; madbr, maebr, maxb, madb, maeb
5858 (define_insn "fma<mode>4"
5859 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5860 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5861 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5862 (match_operand:DSF 3 "register_operand" "0,0")))]
5867 [(set_attr "op_type" "RRE,RXE")
5868 (set_attr "type" "fmadd<mode>")])
5870 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5871 (define_insn "fms<mode>4"
5872 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5873 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5874 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5875 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5880 [(set_attr "op_type" "RRE,RXE")
5881 (set_attr "type" "fmadd<mode>")])
5884 ;;- Divide and modulo instructions.
5888 ; divmoddi4 instruction pattern(s).
5891 (define_expand "divmoddi4"
5892 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5893 (div:DI (match_operand:DI 1 "register_operand" "")
5894 (match_operand:DI 2 "general_operand" "")))
5895 (set (match_operand:DI 3 "general_operand" "")
5896 (mod:DI (match_dup 1) (match_dup 2)))])
5897 (clobber (match_dup 4))]
5900 rtx insn, div_equal, mod_equal;
5902 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5903 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5905 operands[4] = gen_reg_rtx(TImode);
5906 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5908 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5909 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5911 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5912 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5917 (define_insn "divmodtidi3"
5918 [(set (match_operand:TI 0 "register_operand" "=d,d")
5922 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5923 (match_operand:DI 2 "general_operand" "d,RT")))
5925 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5930 [(set_attr "op_type" "RRE,RXY")
5931 (set_attr "type" "idiv")])
5933 (define_insn "divmodtisi3"
5934 [(set (match_operand:TI 0 "register_operand" "=d,d")
5938 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5940 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5943 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5948 [(set_attr "op_type" "RRE,RXY")
5949 (set_attr "type" "idiv")])
5952 ; udivmoddi4 instruction pattern(s).
5955 (define_expand "udivmoddi4"
5956 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5957 (udiv:DI (match_operand:DI 1 "general_operand" "")
5958 (match_operand:DI 2 "nonimmediate_operand" "")))
5959 (set (match_operand:DI 3 "general_operand" "")
5960 (umod:DI (match_dup 1) (match_dup 2)))])
5961 (clobber (match_dup 4))]
5964 rtx insn, div_equal, mod_equal, equal;
5966 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5967 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5968 equal = gen_rtx_IOR (TImode,
5969 gen_rtx_ASHIFT (TImode,
5970 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5972 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5974 operands[4] = gen_reg_rtx(TImode);
5975 emit_clobber (operands[4]);
5976 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5977 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5979 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5980 set_unique_reg_note (insn, REG_EQUAL, equal);
5982 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5983 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5985 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5986 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5991 (define_insn "udivmodtidi3"
5992 [(set (match_operand:TI 0 "register_operand" "=d,d")
5997 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5999 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6003 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6008 [(set_attr "op_type" "RRE,RXY")
6009 (set_attr "type" "idiv")])
6012 ; divmodsi4 instruction pattern(s).
6015 (define_expand "divmodsi4"
6016 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6017 (div:SI (match_operand:SI 1 "general_operand" "")
6018 (match_operand:SI 2 "nonimmediate_operand" "")))
6019 (set (match_operand:SI 3 "general_operand" "")
6020 (mod:SI (match_dup 1) (match_dup 2)))])
6021 (clobber (match_dup 4))]
6024 rtx insn, div_equal, mod_equal, equal;
6026 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6027 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6028 equal = gen_rtx_IOR (DImode,
6029 gen_rtx_ASHIFT (DImode,
6030 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6032 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6034 operands[4] = gen_reg_rtx(DImode);
6035 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6037 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6038 set_unique_reg_note (insn, REG_EQUAL, equal);
6040 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6041 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6043 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6044 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6049 (define_insn "divmoddisi3"
6050 [(set (match_operand:DI 0 "register_operand" "=d,d")
6055 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6057 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6061 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6066 [(set_attr "op_type" "RR,RX")
6067 (set_attr "type" "idiv")])
6070 ; udivsi3 and umodsi3 instruction pattern(s).
6073 (define_expand "udivmodsi4"
6074 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6075 (udiv:SI (match_operand:SI 1 "general_operand" "")
6076 (match_operand:SI 2 "nonimmediate_operand" "")))
6077 (set (match_operand:SI 3 "general_operand" "")
6078 (umod:SI (match_dup 1) (match_dup 2)))])
6079 (clobber (match_dup 4))]
6080 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6082 rtx insn, div_equal, mod_equal, equal;
6084 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6085 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6086 equal = gen_rtx_IOR (DImode,
6087 gen_rtx_ASHIFT (DImode,
6088 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6090 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6092 operands[4] = gen_reg_rtx(DImode);
6093 emit_clobber (operands[4]);
6094 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6095 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6097 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6098 set_unique_reg_note (insn, REG_EQUAL, equal);
6100 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6101 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6103 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6104 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6109 (define_insn "udivmoddisi3"
6110 [(set (match_operand:DI 0 "register_operand" "=d,d")
6115 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6117 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6121 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6122 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6126 [(set_attr "op_type" "RRE,RXY")
6127 (set_attr "type" "idiv")])
6129 (define_expand "udivsi3"
6130 [(set (match_operand:SI 0 "register_operand" "=d")
6131 (udiv:SI (match_operand:SI 1 "general_operand" "")
6132 (match_operand:SI 2 "general_operand" "")))
6133 (clobber (match_dup 3))]
6134 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6136 rtx insn, udiv_equal, umod_equal, equal;
6138 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6139 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6140 equal = gen_rtx_IOR (DImode,
6141 gen_rtx_ASHIFT (DImode,
6142 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6144 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6146 operands[3] = gen_reg_rtx (DImode);
6148 if (CONSTANT_P (operands[2]))
6150 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6152 rtx_code_label *label1 = gen_label_rtx ();
6154 operands[1] = make_safe_from (operands[1], operands[0]);
6155 emit_move_insn (operands[0], const0_rtx);
6156 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6158 emit_move_insn (operands[0], const1_rtx);
6159 emit_label (label1);
6163 operands[2] = force_reg (SImode, operands[2]);
6164 operands[2] = make_safe_from (operands[2], operands[0]);
6166 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6167 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6169 set_unique_reg_note (insn, REG_EQUAL, equal);
6171 insn = emit_move_insn (operands[0],
6172 gen_lowpart (SImode, operands[3]));
6173 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6178 rtx_code_label *label1 = gen_label_rtx ();
6179 rtx_code_label *label2 = gen_label_rtx ();
6180 rtx_code_label *label3 = gen_label_rtx ();
6182 operands[1] = force_reg (SImode, operands[1]);
6183 operands[1] = make_safe_from (operands[1], operands[0]);
6184 operands[2] = force_reg (SImode, operands[2]);
6185 operands[2] = make_safe_from (operands[2], operands[0]);
6187 emit_move_insn (operands[0], const0_rtx);
6188 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6190 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6192 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6194 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6195 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6197 set_unique_reg_note (insn, REG_EQUAL, equal);
6199 insn = emit_move_insn (operands[0],
6200 gen_lowpart (SImode, operands[3]));
6201 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6204 emit_label (label1);
6205 emit_move_insn (operands[0], operands[1]);
6207 emit_label (label2);
6208 emit_move_insn (operands[0], const1_rtx);
6209 emit_label (label3);
6211 emit_move_insn (operands[0], operands[0]);
6215 (define_expand "umodsi3"
6216 [(set (match_operand:SI 0 "register_operand" "=d")
6217 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6218 (match_operand:SI 2 "nonimmediate_operand" "")))
6219 (clobber (match_dup 3))]
6220 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6222 rtx insn, udiv_equal, umod_equal, equal;
6224 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6225 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6226 equal = gen_rtx_IOR (DImode,
6227 gen_rtx_ASHIFT (DImode,
6228 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6230 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6232 operands[3] = gen_reg_rtx (DImode);
6234 if (CONSTANT_P (operands[2]))
6236 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6238 rtx_code_label *label1 = gen_label_rtx ();
6240 operands[1] = make_safe_from (operands[1], operands[0]);
6241 emit_move_insn (operands[0], operands[1]);
6242 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6244 emit_insn (gen_abssi2 (operands[0], operands[2]));
6245 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6246 emit_label (label1);
6250 operands[2] = force_reg (SImode, operands[2]);
6251 operands[2] = make_safe_from (operands[2], operands[0]);
6253 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6254 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6256 set_unique_reg_note (insn, REG_EQUAL, equal);
6258 insn = emit_move_insn (operands[0],
6259 gen_highpart (SImode, operands[3]));
6260 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6265 rtx_code_label *label1 = gen_label_rtx ();
6266 rtx_code_label *label2 = gen_label_rtx ();
6267 rtx_code_label *label3 = gen_label_rtx ();
6269 operands[1] = force_reg (SImode, operands[1]);
6270 operands[1] = make_safe_from (operands[1], operands[0]);
6271 operands[2] = force_reg (SImode, operands[2]);
6272 operands[2] = make_safe_from (operands[2], operands[0]);
6274 emit_move_insn(operands[0], operands[1]);
6275 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6277 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6279 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6281 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6282 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6284 set_unique_reg_note (insn, REG_EQUAL, equal);
6286 insn = emit_move_insn (operands[0],
6287 gen_highpart (SImode, operands[3]));
6288 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6291 emit_label (label1);
6292 emit_move_insn (operands[0], const0_rtx);
6294 emit_label (label2);
6295 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6296 emit_label (label3);
6302 ; div(df|sf)3 instruction pattern(s).
6305 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6306 (define_insn "div<mode>3"
6307 [(set (match_operand:FP 0 "register_operand" "=f,f")
6308 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6309 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6312 d<xde><bt>r\t%0,<op1>%2
6314 [(set_attr "op_type" "<RRer>,RXE")
6315 (set_attr "type" "fdiv<mode>")])
6319 ;;- And instructions.
6322 (define_expand "and<mode>3"
6323 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6324 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6325 (match_operand:INT 2 "general_operand" "")))
6326 (clobber (reg:CC CC_REGNUM))]
6328 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6331 ; anddi3 instruction pattern(s).
6334 (define_insn "*anddi3_cc"
6335 [(set (reg CC_REGNUM)
6337 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6338 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6340 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6341 (and:DI (match_dup 1) (match_dup 2)))]
6342 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6347 risbg\t%0,%1,%s2,128+%e2,0"
6348 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6349 (set_attr "cpu_facility" "*,z196,*,z10")
6350 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6352 (define_insn "*anddi3_cconly"
6353 [(set (reg CC_REGNUM)
6355 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6356 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6358 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6360 && s390_match_ccmode(insn, CCTmode)
6361 /* Do not steal TM patterns. */
6362 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6367 risbg\t%0,%1,%s2,128+%e2,0"
6368 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6369 (set_attr "cpu_facility" "*,z196,*,z10")
6370 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6372 (define_insn "*anddi3"
6373 [(set (match_operand:DI 0 "nonimmediate_operand"
6374 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6376 (match_operand:DI 1 "nonimmediate_operand"
6377 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6378 (match_operand:DI 2 "general_operand"
6379 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6380 (clobber (reg:CC CC_REGNUM))]
6381 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6394 risbg\t%0,%1,%s2,128+%e2,0
6397 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6398 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6399 (set_attr "z10prop" "*,
6415 [(set (match_operand:DI 0 "s_operand" "")
6416 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6417 (clobber (reg:CC CC_REGNUM))]
6420 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6421 (clobber (reg:CC CC_REGNUM))])]
6422 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6424 ;; These two are what combine generates for (ashift (zero_extract)).
6425 (define_insn "*extzv_<mode>_srl"
6426 [(set (match_operand:GPR 0 "register_operand" "=d")
6427 (and:GPR (lshiftrt:GPR
6428 (match_operand:GPR 1 "register_operand" "d")
6429 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6430 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6431 (clobber (reg:CC CC_REGNUM))]
6433 /* Note that even for the SImode pattern, the rotate is always DImode. */
6434 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6435 INTVAL (operands[3]))"
6436 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6437 [(set_attr "op_type" "RIE")
6438 (set_attr "z10prop" "z10_super_E1")])
6440 (define_insn "*extzv_<mode>_sll"
6441 [(set (match_operand:GPR 0 "register_operand" "=d")
6442 (and:GPR (ashift:GPR
6443 (match_operand:GPR 1 "register_operand" "d")
6444 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6445 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6446 (clobber (reg:CC CC_REGNUM))]
6448 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6449 INTVAL (operands[3]))"
6450 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6451 [(set_attr "op_type" "RIE")
6452 (set_attr "z10prop" "z10_super_E1")])
6456 ; andsi3 instruction pattern(s).
6459 (define_insn "*andsi3_cc"
6460 [(set (reg CC_REGNUM)
6463 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6464 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6466 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6467 (and:SI (match_dup 1) (match_dup 2)))]
6468 "s390_match_ccmode(insn, CCTmode)"
6475 risbg\t%0,%1,%t2,128+%f2,0"
6476 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6477 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6478 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6479 z10_super_E1,z10_super_E1,z10_super_E1")])
6481 (define_insn "*andsi3_cconly"
6482 [(set (reg CC_REGNUM)
6485 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6486 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6488 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6489 "s390_match_ccmode(insn, CCTmode)
6490 /* Do not steal TM patterns. */
6491 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6498 risbg\t%0,%1,%t2,128+%f2,0"
6499 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6500 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6501 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6502 z10_super_E1,z10_super_E1,z10_super_E1")])
6504 (define_insn "*andsi3_zarch"
6505 [(set (match_operand:SI 0 "nonimmediate_operand"
6506 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6507 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6508 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6509 (match_operand:SI 2 "general_operand"
6510 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6511 (clobber (reg:CC CC_REGNUM))]
6512 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6523 risbg\t%0,%1,%t2,128+%f2,0
6526 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6527 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6528 (set_attr "z10prop" "*,
6541 (define_insn "*andsi3_esa"
6542 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6543 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6544 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6545 (clobber (reg:CC CC_REGNUM))]
6546 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6552 [(set_attr "op_type" "RR,RX,SI,SS")
6553 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6557 [(set (match_operand:SI 0 "s_operand" "")
6558 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6559 (clobber (reg:CC CC_REGNUM))]
6562 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6563 (clobber (reg:CC CC_REGNUM))])]
6564 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6567 ; andhi3 instruction pattern(s).
6570 (define_insn "*andhi3_zarch"
6571 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6572 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6573 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6574 (clobber (reg:CC CC_REGNUM))]
6575 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6582 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6583 (set_attr "cpu_facility" "*,z196,*,*,*")
6584 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6587 (define_insn "*andhi3_esa"
6588 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6589 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6590 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6591 (clobber (reg:CC CC_REGNUM))]
6592 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6597 [(set_attr "op_type" "RR,SI,SS")
6598 (set_attr "z10prop" "z10_super_E1,*,*")
6602 [(set (match_operand:HI 0 "s_operand" "")
6603 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6604 (clobber (reg:CC CC_REGNUM))]
6607 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6608 (clobber (reg:CC CC_REGNUM))])]
6609 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6612 ; andqi3 instruction pattern(s).
6615 (define_insn "*andqi3_zarch"
6616 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6617 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6618 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6619 (clobber (reg:CC CC_REGNUM))]
6620 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6628 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6629 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6630 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6632 (define_insn "*andqi3_esa"
6633 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6634 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6635 (match_operand:QI 2 "general_operand" "d,n,Q")))
6636 (clobber (reg:CC CC_REGNUM))]
6637 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6642 [(set_attr "op_type" "RR,SI,SS")
6643 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6646 ; Block and (NC) patterns.
6650 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6651 (and:BLK (match_dup 0)
6652 (match_operand:BLK 1 "memory_operand" "Q")))
6653 (use (match_operand 2 "const_int_operand" "n"))
6654 (clobber (reg:CC CC_REGNUM))]
6655 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6656 "nc\t%O0(%2,%R0),%S1"
6657 [(set_attr "op_type" "SS")
6658 (set_attr "z196prop" "z196_cracked")])
6661 [(set (match_operand 0 "memory_operand" "")
6663 (match_operand 1 "memory_operand" "")))
6664 (clobber (reg:CC CC_REGNUM))]
6666 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6667 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6669 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6671 (clobber (reg:CC CC_REGNUM))])]
6673 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6674 operands[0] = adjust_address (operands[0], BLKmode, 0);
6675 operands[1] = adjust_address (operands[1], BLKmode, 0);
6680 [(set (match_operand:BLK 0 "memory_operand" "")
6681 (and:BLK (match_dup 0)
6682 (match_operand:BLK 1 "memory_operand" "")))
6683 (use (match_operand 2 "const_int_operand" ""))
6684 (clobber (reg:CC CC_REGNUM))])
6686 [(set (match_operand:BLK 3 "memory_operand" "")
6687 (and:BLK (match_dup 3)
6688 (match_operand:BLK 4 "memory_operand" "")))
6689 (use (match_operand 5 "const_int_operand" ""))
6690 (clobber (reg:CC CC_REGNUM))])]
6691 "s390_offset_p (operands[0], operands[3], operands[2])
6692 && s390_offset_p (operands[1], operands[4], operands[2])
6693 && !s390_overlap_p (operands[0], operands[1],
6694 INTVAL (operands[2]) + INTVAL (operands[5]))
6695 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6697 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6699 (clobber (reg:CC CC_REGNUM))])]
6700 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6701 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6702 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6706 ;;- Bit set (inclusive or) instructions.
6709 (define_expand "ior<mode>3"
6710 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6711 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6712 (match_operand:INT 2 "general_operand" "")))
6713 (clobber (reg:CC CC_REGNUM))]
6715 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6718 ; iordi3 instruction pattern(s).
6721 (define_insn "*iordi3_cc"
6722 [(set (reg CC_REGNUM)
6723 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6724 (match_operand:DI 2 "general_operand" " d,d,RT"))
6726 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6727 (ior:DI (match_dup 1) (match_dup 2)))]
6728 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6733 [(set_attr "op_type" "RRE,RRF,RXY")
6734 (set_attr "cpu_facility" "*,z196,*")
6735 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6737 (define_insn "*iordi3_cconly"
6738 [(set (reg CC_REGNUM)
6739 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6740 (match_operand:DI 2 "general_operand" " d,d,RT"))
6742 (clobber (match_scratch:DI 0 "=d,d,d"))]
6743 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6748 [(set_attr "op_type" "RRE,RRF,RXY")
6749 (set_attr "cpu_facility" "*,z196,*")
6750 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6752 (define_insn "*iordi3"
6753 [(set (match_operand:DI 0 "nonimmediate_operand"
6754 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6755 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6756 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6757 (match_operand:DI 2 "general_operand"
6758 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6759 (clobber (reg:CC CC_REGNUM))]
6760 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6773 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6774 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6775 (set_attr "z10prop" "z10_super_E1,
6788 [(set (match_operand:DI 0 "s_operand" "")
6789 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6790 (clobber (reg:CC CC_REGNUM))]
6793 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6794 (clobber (reg:CC CC_REGNUM))])]
6795 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6798 ; iorsi3 instruction pattern(s).
6801 (define_insn "*iorsi3_cc"
6802 [(set (reg CC_REGNUM)
6803 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6804 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6806 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6807 (ior:SI (match_dup 1) (match_dup 2)))]
6808 "s390_match_ccmode(insn, CCTmode)"
6815 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6816 (set_attr "cpu_facility" "*,*,z196,*,*")
6817 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6819 (define_insn "*iorsi3_cconly"
6820 [(set (reg CC_REGNUM)
6821 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6822 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6824 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6825 "s390_match_ccmode(insn, CCTmode)"
6832 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6833 (set_attr "cpu_facility" "*,*,z196,*,*")
6834 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6836 (define_insn "*iorsi3_zarch"
6837 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6838 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6839 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6840 (clobber (reg:CC CC_REGNUM))]
6841 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6852 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6853 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6854 (set_attr "z10prop" "z10_super_E1,
6864 (define_insn "*iorsi3_esa"
6865 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6866 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6867 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6868 (clobber (reg:CC CC_REGNUM))]
6869 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6875 [(set_attr "op_type" "RR,RX,SI,SS")
6876 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6879 [(set (match_operand:SI 0 "s_operand" "")
6880 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6881 (clobber (reg:CC CC_REGNUM))]
6884 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6885 (clobber (reg:CC CC_REGNUM))])]
6886 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6889 ; iorhi3 instruction pattern(s).
6892 (define_insn "*iorhi3_zarch"
6893 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6894 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6895 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6896 (clobber (reg:CC CC_REGNUM))]
6897 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6904 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6905 (set_attr "cpu_facility" "*,z196,*,*,*")
6906 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6908 (define_insn "*iorhi3_esa"
6909 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6910 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6911 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6912 (clobber (reg:CC CC_REGNUM))]
6913 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6918 [(set_attr "op_type" "RR,SI,SS")
6919 (set_attr "z10prop" "z10_super_E1,*,*")])
6922 [(set (match_operand:HI 0 "s_operand" "")
6923 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6924 (clobber (reg:CC CC_REGNUM))]
6927 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6928 (clobber (reg:CC CC_REGNUM))])]
6929 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6932 ; iorqi3 instruction pattern(s).
6935 (define_insn "*iorqi3_zarch"
6936 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6937 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6938 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6939 (clobber (reg:CC CC_REGNUM))]
6940 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6948 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6949 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6950 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6951 z10_super,z10_super,*")])
6953 (define_insn "*iorqi3_esa"
6954 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6955 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6956 (match_operand:QI 2 "general_operand" "d,n,Q")))
6957 (clobber (reg:CC CC_REGNUM))]
6958 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6963 [(set_attr "op_type" "RR,SI,SS")
6964 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6967 ; Block inclusive or (OC) patterns.
6971 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6972 (ior:BLK (match_dup 0)
6973 (match_operand:BLK 1 "memory_operand" "Q")))
6974 (use (match_operand 2 "const_int_operand" "n"))
6975 (clobber (reg:CC CC_REGNUM))]
6976 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6977 "oc\t%O0(%2,%R0),%S1"
6978 [(set_attr "op_type" "SS")
6979 (set_attr "z196prop" "z196_cracked")])
6982 [(set (match_operand 0 "memory_operand" "")
6984 (match_operand 1 "memory_operand" "")))
6985 (clobber (reg:CC CC_REGNUM))]
6987 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6988 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6990 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6992 (clobber (reg:CC CC_REGNUM))])]
6994 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6995 operands[0] = adjust_address (operands[0], BLKmode, 0);
6996 operands[1] = adjust_address (operands[1], BLKmode, 0);
7001 [(set (match_operand:BLK 0 "memory_operand" "")
7002 (ior:BLK (match_dup 0)
7003 (match_operand:BLK 1 "memory_operand" "")))
7004 (use (match_operand 2 "const_int_operand" ""))
7005 (clobber (reg:CC CC_REGNUM))])
7007 [(set (match_operand:BLK 3 "memory_operand" "")
7008 (ior:BLK (match_dup 3)
7009 (match_operand:BLK 4 "memory_operand" "")))
7010 (use (match_operand 5 "const_int_operand" ""))
7011 (clobber (reg:CC CC_REGNUM))])]
7012 "s390_offset_p (operands[0], operands[3], operands[2])
7013 && s390_offset_p (operands[1], operands[4], operands[2])
7014 && !s390_overlap_p (operands[0], operands[1],
7015 INTVAL (operands[2]) + INTVAL (operands[5]))
7016 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7018 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7020 (clobber (reg:CC CC_REGNUM))])]
7021 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7022 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7023 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7027 ;;- Xor instructions.
7030 (define_expand "xor<mode>3"
7031 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7032 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7033 (match_operand:INT 2 "general_operand" "")))
7034 (clobber (reg:CC CC_REGNUM))]
7036 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7038 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7039 ; simplifications. So its better to have something matching.
7041 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7042 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7045 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7046 (clobber (reg:CC CC_REGNUM))])]
7048 operands[2] = constm1_rtx;
7049 if (!s390_logical_operator_ok_p (operands))
7054 ; xordi3 instruction pattern(s).
7057 (define_insn "*xordi3_cc"
7058 [(set (reg CC_REGNUM)
7059 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7060 (match_operand:DI 2 "general_operand" " d,d,RT"))
7062 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7063 (xor:DI (match_dup 1) (match_dup 2)))]
7064 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7069 [(set_attr "op_type" "RRE,RRF,RXY")
7070 (set_attr "cpu_facility" "*,z196,*")
7071 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7073 (define_insn "*xordi3_cconly"
7074 [(set (reg CC_REGNUM)
7075 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7076 (match_operand:DI 2 "general_operand" " d,d,RT"))
7078 (clobber (match_scratch:DI 0 "=d,d, d"))]
7079 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7084 [(set_attr "op_type" "RRE,RRF,RXY")
7085 (set_attr "cpu_facility" "*,z196,*")
7086 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7088 (define_insn "*xordi3"
7089 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
7090 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
7091 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7092 (clobber (reg:CC CC_REGNUM))]
7093 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7102 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7103 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7104 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7105 *,z10_super_E1,*,*")])
7108 [(set (match_operand:DI 0 "s_operand" "")
7109 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7110 (clobber (reg:CC CC_REGNUM))]
7113 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7114 (clobber (reg:CC CC_REGNUM))])]
7115 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7118 ; xorsi3 instruction pattern(s).
7121 (define_insn "*xorsi3_cc"
7122 [(set (reg CC_REGNUM)
7123 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7124 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7126 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7127 (xor:SI (match_dup 1) (match_dup 2)))]
7128 "s390_match_ccmode(insn, CCTmode)"
7135 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7136 (set_attr "cpu_facility" "*,*,z196,*,*")
7137 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7138 z10_super_E1,z10_super_E1")])
7140 (define_insn "*xorsi3_cconly"
7141 [(set (reg CC_REGNUM)
7142 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7143 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7145 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7146 "s390_match_ccmode(insn, CCTmode)"
7153 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7154 (set_attr "cpu_facility" "*,*,z196,*,*")
7155 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7156 z10_super_E1,z10_super_E1")])
7158 (define_insn "*xorsi3"
7159 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7160 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7161 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7162 (clobber (reg:CC CC_REGNUM))]
7163 "s390_logical_operator_ok_p (operands)"
7172 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7173 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7174 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7175 z10_super_E1,z10_super_E1,*,*")])
7178 [(set (match_operand:SI 0 "s_operand" "")
7179 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7180 (clobber (reg:CC CC_REGNUM))]
7183 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7184 (clobber (reg:CC CC_REGNUM))])]
7185 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7188 ; xorhi3 instruction pattern(s).
7191 (define_insn "*xorhi3"
7192 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7193 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7194 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7195 (clobber (reg:CC CC_REGNUM))]
7196 "s390_logical_operator_ok_p (operands)"
7203 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7204 (set_attr "cpu_facility" "*,*,z196,*,*")
7205 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7208 [(set (match_operand:HI 0 "s_operand" "")
7209 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7210 (clobber (reg:CC CC_REGNUM))]
7213 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7214 (clobber (reg:CC CC_REGNUM))])]
7215 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7218 ; xorqi3 instruction pattern(s).
7221 (define_insn "*xorqi3"
7222 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7223 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7224 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7225 (clobber (reg:CC CC_REGNUM))]
7226 "s390_logical_operator_ok_p (operands)"
7234 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7235 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7236 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7240 ; Block exclusive or (XC) patterns.
7244 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7245 (xor:BLK (match_dup 0)
7246 (match_operand:BLK 1 "memory_operand" "Q")))
7247 (use (match_operand 2 "const_int_operand" "n"))
7248 (clobber (reg:CC CC_REGNUM))]
7249 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7250 "xc\t%O0(%2,%R0),%S1"
7251 [(set_attr "op_type" "SS")])
7254 [(set (match_operand 0 "memory_operand" "")
7256 (match_operand 1 "memory_operand" "")))
7257 (clobber (reg:CC CC_REGNUM))]
7259 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7260 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7262 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7264 (clobber (reg:CC CC_REGNUM))])]
7266 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7267 operands[0] = adjust_address (operands[0], BLKmode, 0);
7268 operands[1] = adjust_address (operands[1], BLKmode, 0);
7273 [(set (match_operand:BLK 0 "memory_operand" "")
7274 (xor:BLK (match_dup 0)
7275 (match_operand:BLK 1 "memory_operand" "")))
7276 (use (match_operand 2 "const_int_operand" ""))
7277 (clobber (reg:CC CC_REGNUM))])
7279 [(set (match_operand:BLK 3 "memory_operand" "")
7280 (xor:BLK (match_dup 3)
7281 (match_operand:BLK 4 "memory_operand" "")))
7282 (use (match_operand 5 "const_int_operand" ""))
7283 (clobber (reg:CC CC_REGNUM))])]
7284 "s390_offset_p (operands[0], operands[3], operands[2])
7285 && s390_offset_p (operands[1], operands[4], operands[2])
7286 && !s390_overlap_p (operands[0], operands[1],
7287 INTVAL (operands[2]) + INTVAL (operands[5]))
7288 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7290 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7292 (clobber (reg:CC CC_REGNUM))])]
7293 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7294 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7295 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7298 ; Block xor (XC) patterns with src == dest.
7301 (define_insn "*xc_zero"
7302 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7304 (use (match_operand 1 "const_int_operand" "n"))
7305 (clobber (reg:CC CC_REGNUM))]
7306 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7307 "xc\t%O0(%1,%R0),%S0"
7308 [(set_attr "op_type" "SS")
7309 (set_attr "z196prop" "z196_cracked")])
7313 [(set (match_operand:BLK 0 "memory_operand" "")
7315 (use (match_operand 1 "const_int_operand" ""))
7316 (clobber (reg:CC CC_REGNUM))])
7318 [(set (match_operand:BLK 2 "memory_operand" "")
7320 (use (match_operand 3 "const_int_operand" ""))
7321 (clobber (reg:CC CC_REGNUM))])]
7322 "s390_offset_p (operands[0], operands[2], operands[1])
7323 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7325 [(set (match_dup 4) (const_int 0))
7327 (clobber (reg:CC CC_REGNUM))])]
7328 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7329 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7333 ;;- Negate instructions.
7337 ; neg(di|si)2 instruction pattern(s).
7340 (define_expand "neg<mode>2"
7342 [(set (match_operand:DSI 0 "register_operand" "=d")
7343 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7344 (clobber (reg:CC CC_REGNUM))])]
7348 (define_insn "*negdi2_sign_cc"
7349 [(set (reg CC_REGNUM)
7350 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7351 (match_operand:SI 1 "register_operand" "d") 0)
7352 (const_int 32)) (const_int 32)))
7354 (set (match_operand:DI 0 "register_operand" "=d")
7355 (neg:DI (sign_extend:DI (match_dup 1))))]
7356 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7358 [(set_attr "op_type" "RRE")
7359 (set_attr "z10prop" "z10_c")])
7361 (define_insn "*negdi2_sign"
7362 [(set (match_operand:DI 0 "register_operand" "=d")
7363 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7364 (clobber (reg:CC CC_REGNUM))]
7367 [(set_attr "op_type" "RRE")
7368 (set_attr "z10prop" "z10_c")])
7371 (define_insn "*neg<mode>2_cc"
7372 [(set (reg CC_REGNUM)
7373 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7375 (set (match_operand:GPR 0 "register_operand" "=d")
7376 (neg:GPR (match_dup 1)))]
7377 "s390_match_ccmode (insn, CCAmode)"
7379 [(set_attr "op_type" "RR<E>")
7380 (set_attr "z10prop" "z10_super_c_E1")])
7383 (define_insn "*neg<mode>2_cconly"
7384 [(set (reg CC_REGNUM)
7385 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7387 (clobber (match_scratch:GPR 0 "=d"))]
7388 "s390_match_ccmode (insn, CCAmode)"
7390 [(set_attr "op_type" "RR<E>")
7391 (set_attr "z10prop" "z10_super_c_E1")])
7394 (define_insn "*neg<mode>2"
7395 [(set (match_operand:GPR 0 "register_operand" "=d")
7396 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7397 (clobber (reg:CC CC_REGNUM))]
7400 [(set_attr "op_type" "RR<E>")
7401 (set_attr "z10prop" "z10_super_c_E1")])
7403 (define_insn "*negdi2_31"
7404 [(set (match_operand:DI 0 "register_operand" "=d")
7405 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7406 (clobber (reg:CC CC_REGNUM))]
7410 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7412 ; Doing the twos complement separately on the SImode parts does an
7413 ; unwanted +1 on the high part which needs to be subtracted afterwards
7414 ; ... unless the +1 on the low part created an overflow.
7417 [(set (match_operand:DI 0 "register_operand" "")
7418 (neg:DI (match_operand:DI 1 "register_operand" "")))
7419 (clobber (reg:CC CC_REGNUM))]
7421 && (REGNO (operands[0]) == REGNO (operands[1])
7422 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7423 && reload_completed"
7425 [(set (match_dup 2) (neg:SI (match_dup 3)))
7426 (clobber (reg:CC CC_REGNUM))])
7428 [(set (reg:CCAP CC_REGNUM)
7429 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7430 (set (match_dup 4) (neg:SI (match_dup 5)))])
7432 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7434 (label_ref (match_dup 6))))
7436 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7437 (clobber (reg:CC CC_REGNUM))])
7439 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7440 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7441 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7442 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7443 operands[6] = gen_label_rtx ();")
7445 ; Like above but first make a copy of the low part of the src operand
7446 ; since it might overlap with the high part of the destination.
7449 [(set (match_operand:DI 0 "register_operand" "")
7450 (neg:DI (match_operand:DI 1 "register_operand" "")))
7451 (clobber (reg:CC CC_REGNUM))]
7453 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7454 && reload_completed"
7455 [; Make a backup of op5 first
7456 (set (match_dup 4) (match_dup 5))
7457 ; Setting op2 here might clobber op5
7459 [(set (match_dup 2) (neg:SI (match_dup 3)))
7460 (clobber (reg:CC CC_REGNUM))])
7462 [(set (reg:CCAP CC_REGNUM)
7463 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7464 (set (match_dup 4) (neg:SI (match_dup 4)))])
7466 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7468 (label_ref (match_dup 6))))
7470 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7471 (clobber (reg:CC CC_REGNUM))])
7473 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7474 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7475 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7476 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7477 operands[6] = gen_label_rtx ();")
7480 ; neg(df|sf)2 instruction pattern(s).
7483 (define_expand "neg<mode>2"
7485 [(set (match_operand:BFP 0 "register_operand" "=f")
7486 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7487 (clobber (reg:CC CC_REGNUM))])]
7491 ; lcxbr, lcdbr, lcebr
7492 (define_insn "*neg<mode>2_cc"
7493 [(set (reg CC_REGNUM)
7494 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7495 (match_operand:BFP 2 "const0_operand" "")))
7496 (set (match_operand:BFP 0 "register_operand" "=f")
7497 (neg:BFP (match_dup 1)))]
7498 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7500 [(set_attr "op_type" "RRE")
7501 (set_attr "type" "fsimp<mode>")])
7503 ; lcxbr, lcdbr, lcebr
7504 (define_insn "*neg<mode>2_cconly"
7505 [(set (reg CC_REGNUM)
7506 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7507 (match_operand:BFP 2 "const0_operand" "")))
7508 (clobber (match_scratch:BFP 0 "=f"))]
7509 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7511 [(set_attr "op_type" "RRE")
7512 (set_attr "type" "fsimp<mode>")])
7515 (define_insn "*neg<mode>2_nocc"
7516 [(set (match_operand:FP 0 "register_operand" "=f")
7517 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7520 [(set_attr "op_type" "RRE")
7521 (set_attr "type" "fsimp<mode>")])
7523 ; lcxbr, lcdbr, lcebr
7524 (define_insn "*neg<mode>2"
7525 [(set (match_operand:BFP 0 "register_operand" "=f")
7526 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7527 (clobber (reg:CC CC_REGNUM))]
7530 [(set_attr "op_type" "RRE")
7531 (set_attr "type" "fsimp<mode>")])
7535 ;;- Absolute value instructions.
7539 ; abs(di|si)2 instruction pattern(s).
7542 (define_insn "*absdi2_sign_cc"
7543 [(set (reg CC_REGNUM)
7544 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7545 (match_operand:SI 1 "register_operand" "d") 0)
7546 (const_int 32)) (const_int 32)))
7548 (set (match_operand:DI 0 "register_operand" "=d")
7549 (abs:DI (sign_extend:DI (match_dup 1))))]
7550 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7552 [(set_attr "op_type" "RRE")
7553 (set_attr "z10prop" "z10_c")])
7555 (define_insn "*absdi2_sign"
7556 [(set (match_operand:DI 0 "register_operand" "=d")
7557 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7558 (clobber (reg:CC CC_REGNUM))]
7561 [(set_attr "op_type" "RRE")
7562 (set_attr "z10prop" "z10_c")])
7565 (define_insn "*abs<mode>2_cc"
7566 [(set (reg CC_REGNUM)
7567 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7569 (set (match_operand:GPR 0 "register_operand" "=d")
7570 (abs:GPR (match_dup 1)))]
7571 "s390_match_ccmode (insn, CCAmode)"
7573 [(set_attr "op_type" "RR<E>")
7574 (set_attr "z10prop" "z10_c")])
7577 (define_insn "*abs<mode>2_cconly"
7578 [(set (reg CC_REGNUM)
7579 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7581 (clobber (match_scratch:GPR 0 "=d"))]
7582 "s390_match_ccmode (insn, CCAmode)"
7584 [(set_attr "op_type" "RR<E>")
7585 (set_attr "z10prop" "z10_c")])
7588 (define_insn "abs<mode>2"
7589 [(set (match_operand:GPR 0 "register_operand" "=d")
7590 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7591 (clobber (reg:CC CC_REGNUM))]
7594 [(set_attr "op_type" "RR<E>")
7595 (set_attr "z10prop" "z10_c")])
7598 ; abs(df|sf)2 instruction pattern(s).
7601 (define_expand "abs<mode>2"
7603 [(set (match_operand:BFP 0 "register_operand" "=f")
7604 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7605 (clobber (reg:CC CC_REGNUM))])]
7609 ; lpxbr, lpdbr, lpebr
7610 (define_insn "*abs<mode>2_cc"
7611 [(set (reg CC_REGNUM)
7612 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7613 (match_operand:BFP 2 "const0_operand" "")))
7614 (set (match_operand:BFP 0 "register_operand" "=f")
7615 (abs:BFP (match_dup 1)))]
7616 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7618 [(set_attr "op_type" "RRE")
7619 (set_attr "type" "fsimp<mode>")])
7621 ; lpxbr, lpdbr, lpebr
7622 (define_insn "*abs<mode>2_cconly"
7623 [(set (reg CC_REGNUM)
7624 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7625 (match_operand:BFP 2 "const0_operand" "")))
7626 (clobber (match_scratch:BFP 0 "=f"))]
7627 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7629 [(set_attr "op_type" "RRE")
7630 (set_attr "type" "fsimp<mode>")])
7633 (define_insn "*abs<mode>2_nocc"
7634 [(set (match_operand:FP 0 "register_operand" "=f")
7635 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7638 [(set_attr "op_type" "RRE")
7639 (set_attr "type" "fsimp<mode>")])
7641 ; lpxbr, lpdbr, lpebr
7642 (define_insn "*abs<mode>2"
7643 [(set (match_operand:BFP 0 "register_operand" "=f")
7644 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7645 (clobber (reg:CC CC_REGNUM))]
7648 [(set_attr "op_type" "RRE")
7649 (set_attr "type" "fsimp<mode>")])
7653 ;;- Negated absolute value instructions
7660 (define_insn "*negabsdi2_sign_cc"
7661 [(set (reg CC_REGNUM)
7662 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7663 (match_operand:SI 1 "register_operand" "d") 0)
7664 (const_int 32)) (const_int 32))))
7666 (set (match_operand:DI 0 "register_operand" "=d")
7667 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7668 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7670 [(set_attr "op_type" "RRE")
7671 (set_attr "z10prop" "z10_c")])
7673 (define_insn "*negabsdi2_sign"
7674 [(set (match_operand:DI 0 "register_operand" "=d")
7675 (neg:DI (abs:DI (sign_extend:DI
7676 (match_operand:SI 1 "register_operand" "d")))))
7677 (clobber (reg:CC CC_REGNUM))]
7680 [(set_attr "op_type" "RRE")
7681 (set_attr "z10prop" "z10_c")])
7684 (define_insn "*negabs<mode>2_cc"
7685 [(set (reg CC_REGNUM)
7686 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7688 (set (match_operand:GPR 0 "register_operand" "=d")
7689 (neg:GPR (abs:GPR (match_dup 1))))]
7690 "s390_match_ccmode (insn, CCAmode)"
7692 [(set_attr "op_type" "RR<E>")
7693 (set_attr "z10prop" "z10_c")])
7696 (define_insn "*negabs<mode>2_cconly"
7697 [(set (reg CC_REGNUM)
7698 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7700 (clobber (match_scratch:GPR 0 "=d"))]
7701 "s390_match_ccmode (insn, CCAmode)"
7703 [(set_attr "op_type" "RR<E>")
7704 (set_attr "z10prop" "z10_c")])
7707 (define_insn "*negabs<mode>2"
7708 [(set (match_operand:GPR 0 "register_operand" "=d")
7709 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7710 (clobber (reg:CC CC_REGNUM))]
7713 [(set_attr "op_type" "RR<E>")
7714 (set_attr "z10prop" "z10_c")])
7720 ; lnxbr, lndbr, lnebr
7721 (define_insn "*negabs<mode>2_cc"
7722 [(set (reg CC_REGNUM)
7723 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7724 (match_operand:BFP 2 "const0_operand" "")))
7725 (set (match_operand:BFP 0 "register_operand" "=f")
7726 (neg:BFP (abs:BFP (match_dup 1))))]
7727 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7729 [(set_attr "op_type" "RRE")
7730 (set_attr "type" "fsimp<mode>")])
7732 ; lnxbr, lndbr, lnebr
7733 (define_insn "*negabs<mode>2_cconly"
7734 [(set (reg CC_REGNUM)
7735 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7736 (match_operand:BFP 2 "const0_operand" "")))
7737 (clobber (match_scratch:BFP 0 "=f"))]
7738 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7740 [(set_attr "op_type" "RRE")
7741 (set_attr "type" "fsimp<mode>")])
7744 (define_insn "*negabs<mode>2_nocc"
7745 [(set (match_operand:FP 0 "register_operand" "=f")
7746 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7749 [(set_attr "op_type" "RRE")
7750 (set_attr "type" "fsimp<mode>")])
7752 ; lnxbr, lndbr, lnebr
7753 (define_insn "*negabs<mode>2"
7754 [(set (match_operand:BFP 0 "register_operand" "=f")
7755 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7756 (clobber (reg:CC CC_REGNUM))]
7759 [(set_attr "op_type" "RRE")
7760 (set_attr "type" "fsimp<mode>")])
7763 ;;- Square root instructions.
7767 ; sqrt(df|sf)2 instruction pattern(s).
7770 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7771 (define_insn "sqrt<mode>2"
7772 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7773 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7778 [(set_attr "op_type" "RRE,RXE")
7779 (set_attr "type" "fsqrt<mode>")])
7783 ;;- One complement instructions.
7787 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7790 (define_expand "one_cmpl<mode>2"
7792 [(set (match_operand:INT 0 "register_operand" "")
7793 (xor:INT (match_operand:INT 1 "register_operand" "")
7795 (clobber (reg:CC CC_REGNUM))])]
7801 ;; Find leftmost bit instructions.
7804 (define_expand "clzdi2"
7805 [(set (match_operand:DI 0 "register_operand" "=d")
7806 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7807 "TARGET_EXTIMM && TARGET_ZARCH"
7809 rtx insn, clz_equal;
7810 rtx wide_reg = gen_reg_rtx (TImode);
7811 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7813 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7815 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7817 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7818 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7823 (define_insn "clztidi2"
7824 [(set (match_operand:TI 0 "register_operand" "=d")
7828 (xor:DI (match_operand:DI 1 "register_operand" "d")
7829 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7830 (subreg:SI (clz:DI (match_dup 1)) 4))))
7833 (zero_extend:TI (clz:DI (match_dup 1)))))
7834 (clobber (reg:CC CC_REGNUM))]
7835 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7836 == (unsigned HOST_WIDE_INT) 1 << 63
7837 && TARGET_EXTIMM && TARGET_ZARCH"
7839 [(set_attr "op_type" "RRE")])
7843 ;;- Rotate instructions.
7847 ; rotl(di|si)3 instruction pattern(s).
7851 (define_insn "rotl<mode>3"
7852 [(set (match_operand:GPR 0 "register_operand" "=d")
7853 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7854 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7857 [(set_attr "op_type" "RSE")
7858 (set_attr "atype" "reg")
7859 (set_attr "z10prop" "z10_super_E1")])
7862 (define_insn "*rotl<mode>3_and"
7863 [(set (match_operand:GPR 0 "register_operand" "=d")
7864 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7865 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7866 (match_operand:SI 3 "const_int_operand" "n"))))]
7867 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7869 [(set_attr "op_type" "RSE")
7870 (set_attr "atype" "reg")
7871 (set_attr "z10prop" "z10_super_E1")])
7875 ;;- Shift instructions.
7879 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7880 ; Left shifts and logical right shifts
7882 (define_expand "<shift><mode>3"
7883 [(set (match_operand:DSI 0 "register_operand" "")
7884 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7885 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7890 (define_insn "*<shift>di3_31"
7891 [(set (match_operand:DI 0 "register_operand" "=d")
7892 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7893 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7896 [(set_attr "op_type" "RS")
7897 (set_attr "atype" "reg")
7898 (set_attr "z196prop" "z196_cracked")])
7900 ; sll, srl, sllg, srlg, sllk, srlk
7901 (define_insn "*<shift><mode>3"
7902 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7903 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7904 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7907 s<lr>l<g>\t%0,<1>%Y2
7908 s<lr>l<gk>\t%0,%1,%Y2"
7909 [(set_attr "op_type" "RS<E>,RSY")
7910 (set_attr "atype" "reg,reg")
7911 (set_attr "cpu_facility" "*,z196")
7912 (set_attr "z10prop" "z10_super_E1,*")])
7915 (define_insn "*<shift>di3_31_and"
7916 [(set (match_operand:DI 0 "register_operand" "=d")
7917 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7918 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7919 (match_operand:SI 3 "const_int_operand" "n"))))]
7920 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7922 [(set_attr "op_type" "RS")
7923 (set_attr "atype" "reg")])
7925 ; sll, srl, sllg, srlg, sllk, srlk
7926 (define_insn "*<shift><mode>3_and"
7927 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7928 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7929 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7930 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7931 "(INTVAL (operands[3]) & 63) == 63"
7933 s<lr>l<g>\t%0,<1>%Y2
7934 s<lr>l<gk>\t%0,%1,%Y2"
7935 [(set_attr "op_type" "RS<E>,RSY")
7936 (set_attr "atype" "reg,reg")
7937 (set_attr "cpu_facility" "*,z196")
7938 (set_attr "z10prop" "z10_super_E1,*")])
7941 ; ashr(di|si)3 instruction pattern(s).
7942 ; Arithmetic right shifts
7944 (define_expand "ashr<mode>3"
7946 [(set (match_operand:DSI 0 "register_operand" "")
7947 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7948 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7949 (clobber (reg:CC CC_REGNUM))])]
7953 (define_insn "*ashrdi3_cc_31"
7954 [(set (reg CC_REGNUM)
7955 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7956 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7958 (set (match_operand:DI 0 "register_operand" "=d")
7959 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7960 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7962 [(set_attr "op_type" "RS")
7963 (set_attr "atype" "reg")])
7965 (define_insn "*ashrdi3_cconly_31"
7966 [(set (reg CC_REGNUM)
7967 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7968 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7970 (clobber (match_scratch:DI 0 "=d"))]
7971 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7973 [(set_attr "op_type" "RS")
7974 (set_attr "atype" "reg")])
7976 (define_insn "*ashrdi3_31"
7977 [(set (match_operand:DI 0 "register_operand" "=d")
7978 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7979 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7980 (clobber (reg:CC CC_REGNUM))]
7983 [(set_attr "op_type" "RS")
7984 (set_attr "atype" "reg")])
7987 (define_insn "*ashr<mode>3_cc"
7988 [(set (reg CC_REGNUM)
7989 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7990 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7992 (set (match_operand:GPR 0 "register_operand" "=d,d")
7993 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7994 "s390_match_ccmode(insn, CCSmode)"
7998 [(set_attr "op_type" "RS<E>,RSY")
7999 (set_attr "atype" "reg,reg")
8000 (set_attr "cpu_facility" "*,z196")
8001 (set_attr "z10prop" "z10_super_E1,*")])
8004 (define_insn "*ashr<mode>3_cconly"
8005 [(set (reg CC_REGNUM)
8006 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8007 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8009 (clobber (match_scratch:GPR 0 "=d,d"))]
8010 "s390_match_ccmode(insn, CCSmode)"
8014 [(set_attr "op_type" "RS<E>,RSY")
8015 (set_attr "atype" "reg,reg")
8016 (set_attr "cpu_facility" "*,z196")
8017 (set_attr "z10prop" "z10_super_E1,*")])
8020 (define_insn "*ashr<mode>3"
8021 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8022 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8023 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8024 (clobber (reg:CC CC_REGNUM))]
8029 [(set_attr "op_type" "RS<E>,RSY")
8030 (set_attr "atype" "reg,reg")
8031 (set_attr "cpu_facility" "*,z196")
8032 (set_attr "z10prop" "z10_super_E1,*")])
8035 ; shift pattern with implicit ANDs
8037 (define_insn "*ashrdi3_cc_31_and"
8038 [(set (reg CC_REGNUM)
8039 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8040 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8041 (match_operand:SI 3 "const_int_operand" "n")))
8043 (set (match_operand:DI 0 "register_operand" "=d")
8044 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8045 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8046 && (INTVAL (operands[3]) & 63) == 63"
8048 [(set_attr "op_type" "RS")
8049 (set_attr "atype" "reg")])
8051 (define_insn "*ashrdi3_cconly_31_and"
8052 [(set (reg CC_REGNUM)
8053 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8054 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8055 (match_operand:SI 3 "const_int_operand" "n")))
8057 (clobber (match_scratch:DI 0 "=d"))]
8058 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8059 && (INTVAL (operands[3]) & 63) == 63"
8061 [(set_attr "op_type" "RS")
8062 (set_attr "atype" "reg")])
8064 (define_insn "*ashrdi3_31_and"
8065 [(set (match_operand:DI 0 "register_operand" "=d")
8066 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8067 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8068 (match_operand:SI 3 "const_int_operand" "n"))))
8069 (clobber (reg:CC CC_REGNUM))]
8070 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8072 [(set_attr "op_type" "RS")
8073 (set_attr "atype" "reg")])
8076 (define_insn "*ashr<mode>3_cc_and"
8077 [(set (reg CC_REGNUM)
8078 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8079 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8080 (match_operand:SI 3 "const_int_operand" "n,n")))
8082 (set (match_operand:GPR 0 "register_operand" "=d,d")
8083 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8084 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8088 [(set_attr "op_type" "RS<E>,RSY")
8089 (set_attr "atype" "reg,reg")
8090 (set_attr "cpu_facility" "*,z196")
8091 (set_attr "z10prop" "z10_super_E1,*")])
8094 (define_insn "*ashr<mode>3_cconly_and"
8095 [(set (reg CC_REGNUM)
8096 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8097 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8098 (match_operand:SI 3 "const_int_operand" "n,n")))
8100 (clobber (match_scratch:GPR 0 "=d,d"))]
8101 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8105 [(set_attr "op_type" "RS<E>,RSY")
8106 (set_attr "atype" "reg,reg")
8107 (set_attr "cpu_facility" "*,z196")
8108 (set_attr "z10prop" "z10_super_E1,*")])
8111 (define_insn "*ashr<mode>3_and"
8112 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8113 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8114 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8115 (match_operand:SI 3 "const_int_operand" "n,n"))))
8116 (clobber (reg:CC CC_REGNUM))]
8117 "(INTVAL (operands[3]) & 63) == 63"
8121 [(set_attr "op_type" "RS<E>,RSY")
8122 (set_attr "atype" "reg,reg")
8123 (set_attr "cpu_facility" "*,z196")
8124 (set_attr "z10prop" "z10_super_E1,*")])
8128 ;; Branch instruction patterns.
8131 (define_expand "cbranch<mode>4"
8133 (if_then_else (match_operator 0 "comparison_operator"
8134 [(match_operand:GPR 1 "register_operand" "")
8135 (match_operand:GPR 2 "general_operand" "")])
8136 (label_ref (match_operand 3 "" ""))
8139 "s390_emit_jump (operands[3],
8140 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8143 (define_expand "cbranch<mode>4"
8145 (if_then_else (match_operator 0 "comparison_operator"
8146 [(match_operand:FP 1 "register_operand" "")
8147 (match_operand:FP 2 "general_operand" "")])
8148 (label_ref (match_operand 3 "" ""))
8151 "s390_emit_jump (operands[3],
8152 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8155 (define_expand "cbranchcc4"
8157 (if_then_else (match_operator 0 "s390_comparison"
8158 [(match_operand 1 "cc_reg_operand" "")
8159 (match_operand 2 "const_int_operand" "")])
8160 (label_ref (match_operand 3 "" ""))
8167 ;;- Conditional jump instructions.
8170 (define_insn "*cjump_64"
8173 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8174 (match_operand 2 "const_int_operand" "")])
8175 (label_ref (match_operand 0 "" ""))
8179 if (get_attr_length (insn) == 4)
8182 return "jg%C1\t%l0";
8184 [(set_attr "op_type" "RI")
8185 (set_attr "type" "branch")
8186 (set (attr "length")
8187 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8188 (const_int 4) (const_int 6)))])
8190 (define_insn "*cjump_31"
8193 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8194 (match_operand 2 "const_int_operand" "")])
8195 (label_ref (match_operand 0 "" ""))
8199 gcc_assert (get_attr_length (insn) == 4);
8202 [(set_attr "op_type" "RI")
8203 (set_attr "type" "branch")
8204 (set (attr "length")
8205 (if_then_else (not (match_test "flag_pic"))
8206 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8207 (const_int 4) (const_int 6))
8208 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8209 (const_int 4) (const_int 8))))])
8211 (define_insn "*cjump_long"
8214 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8215 (match_operand 0 "address_operand" "ZQZR")
8219 if (get_attr_op_type (insn) == OP_TYPE_RR)
8224 [(set (attr "op_type")
8225 (if_then_else (match_operand 0 "register_operand" "")
8226 (const_string "RR") (const_string "RX")))
8227 (set_attr "type" "branch")
8228 (set_attr "atype" "agen")])
8230 ;; A conditional return instruction.
8231 (define_insn "*c<code>"
8234 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8237 "s390_can_use_<code>_insn ()"
8239 [(set_attr "op_type" "RR")
8240 (set_attr "type" "jsr")
8241 (set_attr "atype" "agen")])
8244 ;;- Negated conditional jump instructions.
8247 (define_insn "*icjump_64"
8250 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8252 (label_ref (match_operand 0 "" ""))))]
8255 if (get_attr_length (insn) == 4)
8258 return "jg%D1\t%l0";
8260 [(set_attr "op_type" "RI")
8261 (set_attr "type" "branch")
8262 (set (attr "length")
8263 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8264 (const_int 4) (const_int 6)))])
8266 (define_insn "*icjump_31"
8269 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8271 (label_ref (match_operand 0 "" ""))))]
8274 gcc_assert (get_attr_length (insn) == 4);
8277 [(set_attr "op_type" "RI")
8278 (set_attr "type" "branch")
8279 (set (attr "length")
8280 (if_then_else (not (match_test "flag_pic"))
8281 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8282 (const_int 4) (const_int 6))
8283 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8284 (const_int 4) (const_int 8))))])
8286 (define_insn "*icjump_long"
8289 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8291 (match_operand 0 "address_operand" "ZQZR")))]
8294 if (get_attr_op_type (insn) == OP_TYPE_RR)
8299 [(set (attr "op_type")
8300 (if_then_else (match_operand 0 "register_operand" "")
8301 (const_string "RR") (const_string "RX")))
8302 (set_attr "type" "branch")
8303 (set_attr "atype" "agen")])
8306 ;;- Trap instructions.
8310 [(trap_if (const_int 1) (const_int 0))]
8313 [(set_attr "op_type" "RI")
8314 (set_attr "type" "branch")])
8316 (define_expand "ctrap<mode>4"
8317 [(trap_if (match_operator 0 "comparison_operator"
8318 [(match_operand:GPR 1 "register_operand" "")
8319 (match_operand:GPR 2 "general_operand" "")])
8320 (match_operand 3 "const0_operand" ""))]
8323 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8324 operands[1], operands[2]);
8325 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8329 (define_expand "ctrap<mode>4"
8330 [(trap_if (match_operator 0 "comparison_operator"
8331 [(match_operand:FP 1 "register_operand" "")
8332 (match_operand:FP 2 "general_operand" "")])
8333 (match_operand 3 "const0_operand" ""))]
8336 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8337 operands[1], operands[2]);
8338 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8342 (define_insn "condtrap"
8343 [(trap_if (match_operator 0 "s390_comparison"
8344 [(match_operand 1 "cc_reg_operand" "c")
8349 [(set_attr "op_type" "RI")
8350 (set_attr "type" "branch")])
8352 ; crt, cgrt, cit, cgit
8353 (define_insn "*cmp_and_trap_signed_int<mode>"
8354 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8355 [(match_operand:GPR 1 "register_operand" "d,d")
8356 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8362 [(set_attr "op_type" "RRF,RIE")
8363 (set_attr "type" "branch")
8364 (set_attr "z10prop" "z10_super_c,z10_super")])
8366 ; clrt, clgrt, clfit, clgit, clt, clgt
8367 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8368 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8369 [(match_operand:GPR 1 "register_operand" "d,d, d")
8370 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8377 [(set_attr "op_type" "RRF,RIE,RSY")
8378 (set_attr "type" "branch")
8379 (set_attr "z10prop" "z10_super_c,z10_super,*")
8380 (set_attr "cpu_facility" "z10,z10,zEC12")])
8383 (define_insn "*load_and_trap<mode>"
8384 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8387 (set (match_operand:GPR 1 "register_operand" "=d")
8391 [(set_attr "op_type" "RXY")])
8395 ;;- Loop instructions.
8397 ;; This is all complicated by the fact that since this is a jump insn
8398 ;; we must handle our own output reloads.
8402 ; This splitter will be matched by combine and has to add the 2 moves
8403 ; necessary to load the compare and the increment values into a
8404 ; register pair as needed by brxle.
8406 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8409 (match_operator 6 "s390_brx_operator"
8410 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8411 (match_operand:GPR 2 "general_operand" ""))
8412 (match_operand:GPR 3 "register_operand" "")])
8413 (label_ref (match_operand 0 "" ""))
8415 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8416 (plus:GPR (match_dup 1) (match_dup 2)))
8417 (clobber (match_scratch:GPR 5 ""))]
8420 "!reload_completed && !reload_in_progress"
8421 [(set (match_dup 7) (match_dup 2)) ; the increment
8422 (set (match_dup 8) (match_dup 3)) ; the comparison value
8423 (parallel [(set (pc)
8426 [(plus:GPR (match_dup 1) (match_dup 7))
8428 (label_ref (match_dup 0))
8431 (plus:GPR (match_dup 1) (match_dup 7)))
8432 (clobber (match_dup 5))
8433 (clobber (reg:CC CC_REGNUM))])]
8435 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8436 operands[7] = gen_lowpart (<GPR:MODE>mode,
8437 gen_highpart (word_mode, dreg));
8438 operands[8] = gen_lowpart (<GPR:MODE>mode,
8439 gen_lowpart (word_mode, dreg));
8444 (define_insn_and_split "*brxg_64bit"
8447 (match_operator 5 "s390_brx_operator"
8448 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8449 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8450 (subreg:DI (match_dup 2) 8)])
8451 (label_ref (match_operand 0 "" ""))
8453 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8454 (plus:DI (match_dup 1)
8455 (subreg:DI (match_dup 2) 0)))
8456 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8457 (clobber (reg:CC CC_REGNUM))]
8460 if (which_alternative != 0)
8462 else if (get_attr_length (insn) == 6)
8463 return "brx%E5g\t%1,%2,%l0";
8465 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8467 "&& reload_completed
8468 && (!REG_P (operands[3])
8469 || !rtx_equal_p (operands[1], operands[3]))"
8470 [(set (match_dup 4) (match_dup 1))
8471 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8472 (clobber (reg:CC CC_REGNUM))])
8473 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8474 (set (match_dup 3) (match_dup 4))
8475 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8476 (label_ref (match_dup 0))
8479 [(set_attr "op_type" "RIE")
8480 (set_attr "type" "branch")
8481 (set (attr "length")
8482 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8483 (const_int 6) (const_int 16)))])
8487 (define_insn_and_split "*brx_64bit"
8490 (match_operator 5 "s390_brx_operator"
8491 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8492 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8493 (subreg:SI (match_dup 2) 12)])
8494 (label_ref (match_operand 0 "" ""))
8496 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8497 (plus:SI (match_dup 1)
8498 (subreg:SI (match_dup 2) 4)))
8499 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8500 (clobber (reg:CC CC_REGNUM))]
8503 if (which_alternative != 0)
8505 else if (get_attr_length (insn) == 6)
8506 return "brx%C5\t%1,%2,%l0";
8508 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8510 "&& reload_completed
8511 && (!REG_P (operands[3])
8512 || !rtx_equal_p (operands[1], operands[3]))"
8513 [(set (match_dup 4) (match_dup 1))
8514 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8515 (clobber (reg:CC CC_REGNUM))])
8516 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8517 (set (match_dup 3) (match_dup 4))
8518 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8519 (label_ref (match_dup 0))
8522 [(set_attr "op_type" "RSI")
8523 (set_attr "type" "branch")
8524 (set (attr "length")
8525 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8526 (const_int 6) (const_int 14)))])
8530 (define_insn_and_split "*brx_31bit"
8533 (match_operator 5 "s390_brx_operator"
8534 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8535 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8536 (subreg:SI (match_dup 2) 4)])
8537 (label_ref (match_operand 0 "" ""))
8539 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8540 (plus:SI (match_dup 1)
8541 (subreg:SI (match_dup 2) 0)))
8542 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8543 (clobber (reg:CC CC_REGNUM))]
8544 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8546 if (which_alternative != 0)
8548 else if (get_attr_length (insn) == 6)
8549 return "brx%C5\t%1,%2,%l0";
8551 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8553 "&& reload_completed
8554 && (!REG_P (operands[3])
8555 || !rtx_equal_p (operands[1], operands[3]))"
8556 [(set (match_dup 4) (match_dup 1))
8557 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8558 (clobber (reg:CC CC_REGNUM))])
8559 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8560 (set (match_dup 3) (match_dup 4))
8561 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8562 (label_ref (match_dup 0))
8565 [(set_attr "op_type" "RSI")
8566 (set_attr "type" "branch")
8567 (set (attr "length")
8568 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8569 (const_int 6) (const_int 14)))])
8574 (define_expand "doloop_end"
8575 [(use (match_operand 0 "" "")) ; loop pseudo
8576 (use (match_operand 1 "" ""))] ; label
8579 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8580 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8581 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8582 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8583 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8584 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8591 (define_insn_and_split "doloop_si64"
8594 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8596 (label_ref (match_operand 0 "" ""))
8598 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8599 (plus:SI (match_dup 1) (const_int -1)))
8600 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8601 (clobber (reg:CC CC_REGNUM))]
8604 if (which_alternative != 0)
8606 else if (get_attr_length (insn) == 4)
8607 return "brct\t%1,%l0";
8609 return "ahi\t%1,-1\;jgne\t%l0";
8611 "&& reload_completed
8612 && (! REG_P (operands[2])
8613 || ! rtx_equal_p (operands[1], operands[2]))"
8614 [(set (match_dup 3) (match_dup 1))
8615 (parallel [(set (reg:CCAN CC_REGNUM)
8616 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8618 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8619 (set (match_dup 2) (match_dup 3))
8620 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8621 (label_ref (match_dup 0))
8624 [(set_attr "op_type" "RI")
8625 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8626 ; hurt us in the (rare) case of ahi.
8627 (set_attr "z10prop" "z10_super_E1")
8628 (set_attr "type" "branch")
8629 (set (attr "length")
8630 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8631 (const_int 4) (const_int 10)))])
8633 (define_insn_and_split "doloop_si31"
8636 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8638 (label_ref (match_operand 0 "" ""))
8640 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8641 (plus:SI (match_dup 1) (const_int -1)))
8642 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8643 (clobber (reg:CC CC_REGNUM))]
8646 if (which_alternative != 0)
8648 else if (get_attr_length (insn) == 4)
8649 return "brct\t%1,%l0";
8653 "&& reload_completed
8654 && (! REG_P (operands[2])
8655 || ! rtx_equal_p (operands[1], operands[2]))"
8656 [(set (match_dup 3) (match_dup 1))
8657 (parallel [(set (reg:CCAN CC_REGNUM)
8658 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8660 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8661 (set (match_dup 2) (match_dup 3))
8662 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8663 (label_ref (match_dup 0))
8666 [(set_attr "op_type" "RI")
8667 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8668 ; hurt us in the (rare) case of ahi.
8669 (set_attr "z10prop" "z10_super_E1")
8670 (set_attr "type" "branch")
8671 (set (attr "length")
8672 (if_then_else (not (match_test "flag_pic"))
8673 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8674 (const_int 4) (const_int 6))
8675 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8676 (const_int 4) (const_int 8))))])
8678 (define_insn "*doloop_si_long"
8681 (ne (match_operand:SI 1 "register_operand" "d")
8683 (match_operand 0 "address_operand" "ZQZR")
8685 (set (match_operand:SI 2 "register_operand" "=1")
8686 (plus:SI (match_dup 1) (const_int -1)))
8687 (clobber (match_scratch:SI 3 "=X"))
8688 (clobber (reg:CC CC_REGNUM))]
8691 if (get_attr_op_type (insn) == OP_TYPE_RR)
8692 return "bctr\t%1,%0";
8694 return "bct\t%1,%a0";
8696 [(set (attr "op_type")
8697 (if_then_else (match_operand 0 "register_operand" "")
8698 (const_string "RR") (const_string "RX")))
8699 (set_attr "type" "branch")
8700 (set_attr "atype" "agen")
8701 (set_attr "z10prop" "z10_c")
8702 (set_attr "z196prop" "z196_cracked")])
8704 (define_insn_and_split "doloop_di"
8707 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8709 (label_ref (match_operand 0 "" ""))
8711 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8712 (plus:DI (match_dup 1) (const_int -1)))
8713 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8714 (clobber (reg:CC CC_REGNUM))]
8717 if (which_alternative != 0)
8719 else if (get_attr_length (insn) == 4)
8720 return "brctg\t%1,%l0";
8722 return "aghi\t%1,-1\;jgne\t%l0";
8724 "&& reload_completed
8725 && (! REG_P (operands[2])
8726 || ! rtx_equal_p (operands[1], operands[2]))"
8727 [(set (match_dup 3) (match_dup 1))
8728 (parallel [(set (reg:CCAN CC_REGNUM)
8729 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8731 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8732 (set (match_dup 2) (match_dup 3))
8733 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8734 (label_ref (match_dup 0))
8737 [(set_attr "op_type" "RI")
8738 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8739 ; hurt us in the (rare) case of ahi.
8740 (set_attr "z10prop" "z10_super_E1")
8741 (set_attr "type" "branch")
8742 (set (attr "length")
8743 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8744 (const_int 4) (const_int 10)))])
8747 ;;- Unconditional jump instructions.
8751 ; jump instruction pattern(s).
8754 (define_expand "jump"
8755 [(match_operand 0 "" "")]
8757 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8759 (define_insn "*jump64"
8760 [(set (pc) (label_ref (match_operand 0 "" "")))]
8763 if (get_attr_length (insn) == 4)
8768 [(set_attr "op_type" "RI")
8769 (set_attr "type" "branch")
8770 (set (attr "length")
8771 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8772 (const_int 4) (const_int 6)))])
8774 (define_insn "*jump31"
8775 [(set (pc) (label_ref (match_operand 0 "" "")))]
8778 gcc_assert (get_attr_length (insn) == 4);
8781 [(set_attr "op_type" "RI")
8782 (set_attr "type" "branch")
8783 (set (attr "length")
8784 (if_then_else (not (match_test "flag_pic"))
8785 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8786 (const_int 4) (const_int 6))
8787 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8788 (const_int 4) (const_int 8))))])
8791 ; indirect-jump instruction pattern(s).
8794 (define_insn "indirect_jump"
8795 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8798 if (get_attr_op_type (insn) == OP_TYPE_RR)
8803 [(set (attr "op_type")
8804 (if_then_else (match_operand 0 "register_operand" "")
8805 (const_string "RR") (const_string "RX")))
8806 (set_attr "type" "branch")
8807 (set_attr "atype" "agen")])
8810 ; casesi instruction pattern(s).
8813 (define_insn "casesi_jump"
8814 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8815 (use (label_ref (match_operand 1 "" "")))]
8818 if (get_attr_op_type (insn) == OP_TYPE_RR)
8823 [(set (attr "op_type")
8824 (if_then_else (match_operand 0 "register_operand" "")
8825 (const_string "RR") (const_string "RX")))
8826 (set_attr "type" "branch")
8827 (set_attr "atype" "agen")])
8829 (define_expand "casesi"
8830 [(match_operand:SI 0 "general_operand" "")
8831 (match_operand:SI 1 "general_operand" "")
8832 (match_operand:SI 2 "general_operand" "")
8833 (label_ref (match_operand 3 "" ""))
8834 (label_ref (match_operand 4 "" ""))]
8837 rtx index = gen_reg_rtx (SImode);
8838 rtx base = gen_reg_rtx (Pmode);
8839 rtx target = gen_reg_rtx (Pmode);
8841 emit_move_insn (index, operands[0]);
8842 emit_insn (gen_subsi3 (index, index, operands[1]));
8843 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8846 if (Pmode != SImode)
8847 index = convert_to_mode (Pmode, index, 1);
8848 if (GET_CODE (index) != REG)
8849 index = copy_to_mode_reg (Pmode, index);
8852 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8854 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8856 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8858 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8859 emit_move_insn (target, index);
8862 target = gen_rtx_PLUS (Pmode, base, target);
8863 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8870 ;;- Jump to subroutine.
8875 ; untyped call instruction pattern(s).
8878 ;; Call subroutine returning any type.
8879 (define_expand "untyped_call"
8880 [(parallel [(call (match_operand 0 "" "")
8882 (match_operand 1 "" "")
8883 (match_operand 2 "" "")])]
8888 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8890 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8892 rtx set = XVECEXP (operands[2], 0, i);
8893 emit_move_insn (SET_DEST (set), SET_SRC (set));
8896 /* The optimizer does not know that the call sets the function value
8897 registers we stored in the result block. We avoid problems by
8898 claiming that all hard registers are used and clobbered at this
8900 emit_insn (gen_blockage ());
8905 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8906 ;; all of memory. This blocks insns from being moved across this point.
8908 (define_insn "blockage"
8909 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8912 [(set_attr "type" "none")
8913 (set_attr "length" "0")])
8919 (define_expand "sibcall"
8920 [(call (match_operand 0 "" "")
8921 (match_operand 1 "" ""))]
8924 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8928 (define_insn "*sibcall_br"
8929 [(call (mem:QI (reg SIBCALL_REGNUM))
8930 (match_operand 0 "const_int_operand" "n"))]
8931 "SIBLING_CALL_P (insn)
8932 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8934 [(set_attr "op_type" "RR")
8935 (set_attr "type" "branch")
8936 (set_attr "atype" "agen")])
8938 (define_insn "*sibcall_brc"
8939 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8940 (match_operand 1 "const_int_operand" "n"))]
8941 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8943 [(set_attr "op_type" "RI")
8944 (set_attr "type" "branch")])
8946 (define_insn "*sibcall_brcl"
8947 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8948 (match_operand 1 "const_int_operand" "n"))]
8949 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8951 [(set_attr "op_type" "RIL")
8952 (set_attr "type" "branch")])
8955 ; sibcall_value patterns
8958 (define_expand "sibcall_value"
8959 [(set (match_operand 0 "" "")
8960 (call (match_operand 1 "" "")
8961 (match_operand 2 "" "")))]
8964 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8968 (define_insn "*sibcall_value_br"
8969 [(set (match_operand 0 "" "")
8970 (call (mem:QI (reg SIBCALL_REGNUM))
8971 (match_operand 1 "const_int_operand" "n")))]
8972 "SIBLING_CALL_P (insn)
8973 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8975 [(set_attr "op_type" "RR")
8976 (set_attr "type" "branch")
8977 (set_attr "atype" "agen")])
8979 (define_insn "*sibcall_value_brc"
8980 [(set (match_operand 0 "" "")
8981 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8982 (match_operand 2 "const_int_operand" "n")))]
8983 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8985 [(set_attr "op_type" "RI")
8986 (set_attr "type" "branch")])
8988 (define_insn "*sibcall_value_brcl"
8989 [(set (match_operand 0 "" "")
8990 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8991 (match_operand 2 "const_int_operand" "n")))]
8992 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8994 [(set_attr "op_type" "RIL")
8995 (set_attr "type" "branch")])
8999 ; call instruction pattern(s).
9002 (define_expand "call"
9003 [(call (match_operand 0 "" "")
9004 (match_operand 1 "" ""))
9005 (use (match_operand 2 "" ""))]
9008 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9009 gen_rtx_REG (Pmode, RETURN_REGNUM));
9013 (define_insn "*bras"
9014 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9015 (match_operand 1 "const_int_operand" "n"))
9016 (clobber (match_operand 2 "register_operand" "=r"))]
9017 "!SIBLING_CALL_P (insn)
9018 && TARGET_SMALL_EXEC
9019 && GET_MODE (operands[2]) == Pmode"
9021 [(set_attr "op_type" "RI")
9022 (set_attr "type" "jsr")
9023 (set_attr "z196prop" "z196_cracked")])
9025 (define_insn "*brasl"
9026 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9027 (match_operand 1 "const_int_operand" "n"))
9028 (clobber (match_operand 2 "register_operand" "=r"))]
9029 "!SIBLING_CALL_P (insn)
9031 && GET_MODE (operands[2]) == Pmode"
9033 [(set_attr "op_type" "RIL")
9034 (set_attr "type" "jsr")
9035 (set_attr "z196prop" "z196_cracked")])
9037 (define_insn "*basr"
9038 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9039 (match_operand 1 "const_int_operand" "n"))
9040 (clobber (match_operand 2 "register_operand" "=r"))]
9041 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9043 if (get_attr_op_type (insn) == OP_TYPE_RR)
9044 return "basr\t%2,%0";
9046 return "bas\t%2,%a0";
9048 [(set (attr "op_type")
9049 (if_then_else (match_operand 0 "register_operand" "")
9050 (const_string "RR") (const_string "RX")))
9051 (set_attr "type" "jsr")
9052 (set_attr "atype" "agen")
9053 (set_attr "z196prop" "z196_cracked")])
9056 ; call_value instruction pattern(s).
9059 (define_expand "call_value"
9060 [(set (match_operand 0 "" "")
9061 (call (match_operand 1 "" "")
9062 (match_operand 2 "" "")))
9063 (use (match_operand 3 "" ""))]
9066 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9067 gen_rtx_REG (Pmode, RETURN_REGNUM));
9071 (define_insn "*bras_r"
9072 [(set (match_operand 0 "" "")
9073 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9074 (match_operand:SI 2 "const_int_operand" "n")))
9075 (clobber (match_operand 3 "register_operand" "=r"))]
9076 "!SIBLING_CALL_P (insn)
9077 && TARGET_SMALL_EXEC
9078 && GET_MODE (operands[3]) == Pmode"
9080 [(set_attr "op_type" "RI")
9081 (set_attr "type" "jsr")
9082 (set_attr "z196prop" "z196_cracked")])
9084 (define_insn "*brasl_r"
9085 [(set (match_operand 0 "" "")
9086 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9087 (match_operand 2 "const_int_operand" "n")))
9088 (clobber (match_operand 3 "register_operand" "=r"))]
9089 "!SIBLING_CALL_P (insn)
9091 && GET_MODE (operands[3]) == Pmode"
9093 [(set_attr "op_type" "RIL")
9094 (set_attr "type" "jsr")
9095 (set_attr "z196prop" "z196_cracked")])
9097 (define_insn "*basr_r"
9098 [(set (match_operand 0 "" "")
9099 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9100 (match_operand 2 "const_int_operand" "n")))
9101 (clobber (match_operand 3 "register_operand" "=r"))]
9102 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9104 if (get_attr_op_type (insn) == OP_TYPE_RR)
9105 return "basr\t%3,%1";
9107 return "bas\t%3,%a1";
9109 [(set (attr "op_type")
9110 (if_then_else (match_operand 1 "register_operand" "")
9111 (const_string "RR") (const_string "RX")))
9112 (set_attr "type" "jsr")
9113 (set_attr "atype" "agen")
9114 (set_attr "z196prop" "z196_cracked")])
9117 ;;- Thread-local storage support.
9120 (define_expand "get_thread_pointer<mode>"
9121 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9125 (define_expand "set_thread_pointer<mode>"
9126 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9127 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9131 (define_insn "*set_tp"
9132 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9135 [(set_attr "type" "none")
9136 (set_attr "length" "0")])
9138 (define_insn "*tls_load_64"
9139 [(set (match_operand:DI 0 "register_operand" "=d")
9140 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9141 (match_operand:DI 2 "" "")]
9145 [(set_attr "op_type" "RXE")
9146 (set_attr "z10prop" "z10_fwd_A3")])
9148 (define_insn "*tls_load_31"
9149 [(set (match_operand:SI 0 "register_operand" "=d,d")
9150 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9151 (match_operand:SI 2 "" "")]
9157 [(set_attr "op_type" "RX,RXY")
9158 (set_attr "type" "load")
9159 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9161 (define_insn "*bras_tls"
9162 [(set (match_operand 0 "" "")
9163 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9164 (match_operand 2 "const_int_operand" "n")))
9165 (clobber (match_operand 3 "register_operand" "=r"))
9166 (use (match_operand 4 "" ""))]
9167 "!SIBLING_CALL_P (insn)
9168 && TARGET_SMALL_EXEC
9169 && GET_MODE (operands[3]) == Pmode"
9171 [(set_attr "op_type" "RI")
9172 (set_attr "type" "jsr")
9173 (set_attr "z196prop" "z196_cracked")])
9175 (define_insn "*brasl_tls"
9176 [(set (match_operand 0 "" "")
9177 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9178 (match_operand 2 "const_int_operand" "n")))
9179 (clobber (match_operand 3 "register_operand" "=r"))
9180 (use (match_operand 4 "" ""))]
9181 "!SIBLING_CALL_P (insn)
9183 && GET_MODE (operands[3]) == Pmode"
9185 [(set_attr "op_type" "RIL")
9186 (set_attr "type" "jsr")
9187 (set_attr "z196prop" "z196_cracked")])
9189 (define_insn "*basr_tls"
9190 [(set (match_operand 0 "" "")
9191 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9192 (match_operand 2 "const_int_operand" "n")))
9193 (clobber (match_operand 3 "register_operand" "=r"))
9194 (use (match_operand 4 "" ""))]
9195 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9197 if (get_attr_op_type (insn) == OP_TYPE_RR)
9198 return "basr\t%3,%1%J4";
9200 return "bas\t%3,%a1%J4";
9202 [(set (attr "op_type")
9203 (if_then_else (match_operand 1 "register_operand" "")
9204 (const_string "RR") (const_string "RX")))
9205 (set_attr "type" "jsr")
9206 (set_attr "atype" "agen")
9207 (set_attr "z196prop" "z196_cracked")])
9210 ;;- Atomic operations
9214 ; memory barrier patterns.
9217 (define_expand "mem_signal_fence"
9218 [(match_operand:SI 0 "const_int_operand")] ;; model
9221 /* The s390 memory model is strong enough not to require any
9222 barrier in order to synchronize a thread with itself. */
9226 (define_expand "mem_thread_fence"
9227 [(match_operand:SI 0 "const_int_operand")] ;; model
9230 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9231 enough not to require barriers of any kind. */
9232 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9234 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9235 MEM_VOLATILE_P (mem) = 1;
9236 emit_insn (gen_mem_thread_fence_1 (mem));
9241 ; Although bcr is superscalar on Z10, this variant will never
9242 ; become part of an execution group.
9243 ; With z196 we can make use of the fast-BCR-serialization facility.
9244 ; This allows for a slightly faster sync which is sufficient for our
9246 (define_insn "mem_thread_fence_1"
9247 [(set (match_operand:BLK 0 "" "")
9248 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9256 [(set_attr "op_type" "RR")
9257 (set_attr "mnemonic" "bcr_flush")
9258 (set_attr "z196prop" "z196_alone")])
9261 ; atomic load/store operations
9264 ; Atomic loads need not examine the memory model at all.
9265 (define_expand "atomic_load<mode>"
9266 [(match_operand:DINT 0 "register_operand") ;; output
9267 (match_operand:DINT 1 "memory_operand") ;; memory
9268 (match_operand:SI 2 "const_int_operand")] ;; model
9271 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9274 if (<MODE>mode == TImode)
9275 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9276 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9277 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9279 emit_move_insn (operands[0], operands[1]);
9283 ; Different from movdi_31 in that we want no splitters.
9284 (define_insn "atomic_loaddi_1"
9285 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9286 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9294 [(set_attr "op_type" "RS,RSY,RS,RSY")
9295 (set_attr "type" "lm,lm,floaddf,floaddf")])
9297 (define_insn "atomic_loadti_1"
9298 [(set (match_operand:TI 0 "register_operand" "=r")
9299 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9303 [(set_attr "op_type" "RXY")
9304 (set_attr "type" "other")])
9306 ; Atomic stores must(?) enforce sequential consistency.
9307 (define_expand "atomic_store<mode>"
9308 [(match_operand:DINT 0 "memory_operand") ;; memory
9309 (match_operand:DINT 1 "register_operand") ;; input
9310 (match_operand:SI 2 "const_int_operand")] ;; model
9313 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9315 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9318 if (<MODE>mode == TImode)
9319 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9320 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9321 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9323 emit_move_insn (operands[0], operands[1]);
9324 if (is_mm_seq_cst (model))
9325 emit_insn (gen_mem_thread_fence (operands[2]));
9329 ; Different from movdi_31 in that we want no splitters.
9330 (define_insn "atomic_storedi_1"
9331 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9332 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9340 [(set_attr "op_type" "RS,RSY,RS,RSY")
9341 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9343 (define_insn "atomic_storeti_1"
9344 [(set (match_operand:TI 0 "memory_operand" "=RT")
9345 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9349 [(set_attr "op_type" "RXY")
9350 (set_attr "type" "other")])
9353 ; compare and swap patterns.
9356 (define_expand "atomic_compare_and_swap<mode>"
9357 [(match_operand:SI 0 "register_operand") ;; bool success output
9358 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9359 (match_operand:DGPR 2 "memory_operand") ;; memory
9360 (match_operand:DGPR 3 "register_operand") ;; expected intput
9361 (match_operand:DGPR 4 "register_operand") ;; newval intput
9362 (match_operand:SI 5 "const_int_operand") ;; is_weak
9363 (match_operand:SI 6 "const_int_operand") ;; success model
9364 (match_operand:SI 7 "const_int_operand")] ;; failure model
9367 rtx cc, cmp, output = operands[1];
9369 if (!register_operand (output, <MODE>mode))
9370 output = gen_reg_rtx (<MODE>mode);
9372 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9375 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9376 (output, operands[2], operands[3], operands[4]));
9378 /* We deliberately accept non-register operands in the predicate
9379 to ensure the write back to the output operand happens *before*
9380 the store-flags code below. This makes it easier for combine
9381 to merge the store-flags code with a potential test-and-branch
9382 pattern following (immediately!) afterwards. */
9383 if (output != operands[1])
9384 emit_move_insn (operands[1], output);
9386 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9387 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9388 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9392 (define_expand "atomic_compare_and_swap<mode>"
9393 [(match_operand:SI 0 "register_operand") ;; bool success output
9394 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9395 (match_operand:HQI 2 "memory_operand") ;; memory
9396 (match_operand:HQI 3 "general_operand") ;; expected intput
9397 (match_operand:HQI 4 "general_operand") ;; newval intput
9398 (match_operand:SI 5 "const_int_operand") ;; is_weak
9399 (match_operand:SI 6 "const_int_operand") ;; success model
9400 (match_operand:SI 7 "const_int_operand")] ;; failure model
9403 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9404 operands[3], operands[4], INTVAL (operands[5]));
9408 (define_expand "atomic_compare_and_swap<mode>_internal"
9410 [(set (match_operand:DGPR 0 "register_operand")
9411 (match_operand:DGPR 1 "memory_operand"))
9413 (unspec_volatile:DGPR
9415 (match_operand:DGPR 2 "register_operand")
9416 (match_operand:DGPR 3 "register_operand")]
9418 (set (reg:CCZ1 CC_REGNUM)
9419 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9423 (define_insn "*atomic_compare_and_swap<mode>_1"
9424 [(set (match_operand:TDI 0 "register_operand" "=r")
9425 (match_operand:TDI 1 "memory_operand" "+QS"))
9427 (unspec_volatile:TDI
9429 (match_operand:TDI 2 "register_operand" "0")
9430 (match_operand:TDI 3 "register_operand" "r")]
9432 (set (reg:CCZ1 CC_REGNUM)
9433 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9435 "c<td>sg\t%0,%3,%S1"
9436 [(set_attr "op_type" "RSY")
9437 (set_attr "type" "sem")])
9440 (define_insn "*atomic_compare_and_swapdi_2"
9441 [(set (match_operand:DI 0 "register_operand" "=r,r")
9442 (match_operand:DI 1 "memory_operand" "+Q,S"))
9446 (match_operand:DI 2 "register_operand" "0,0")
9447 (match_operand:DI 3 "register_operand" "r,r")]
9449 (set (reg:CCZ1 CC_REGNUM)
9450 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9455 [(set_attr "op_type" "RS,RSY")
9456 (set_attr "type" "sem")])
9459 (define_insn "*atomic_compare_and_swapsi_3"
9460 [(set (match_operand:SI 0 "register_operand" "=r,r")
9461 (match_operand:SI 1 "memory_operand" "+Q,S"))
9465 (match_operand:SI 2 "register_operand" "0,0")
9466 (match_operand:SI 3 "register_operand" "r,r")]
9468 (set (reg:CCZ1 CC_REGNUM)
9469 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9474 [(set_attr "op_type" "RS,RSY")
9475 (set_attr "type" "sem")])
9478 ; Other atomic instruction patterns.
9481 ; z196 load and add, xor, or and and instructions
9483 (define_expand "atomic_fetch_<atomic><mode>"
9484 [(match_operand:GPR 0 "register_operand") ;; val out
9486 (match_operand:GPR 1 "memory_operand") ;; memory
9487 (match_operand:GPR 2 "register_operand")) ;; val in
9488 (match_operand:SI 3 "const_int_operand")] ;; model
9491 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9494 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9495 (operands[0], operands[1], operands[2]));
9499 ; lan, lang, lao, laog, lax, laxg, laa, laag
9500 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9501 [(set (match_operand:GPR 0 "register_operand" "=d")
9502 (match_operand:GPR 1 "memory_operand" "+QS"))
9504 (unspec_volatile:GPR
9505 [(ATOMIC_Z196:GPR (match_dup 1)
9506 (match_operand:GPR 2 "general_operand" "d"))]
9508 (clobber (reg:CC CC_REGNUM))]
9510 "la<noxa><g>\t%0,%2,%1"
9511 [(set_attr "op_type" "RSY")
9512 (set_attr "type" "sem")])
9514 ;; For SImode and larger, the optabs.c code will do just fine in
9515 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9516 ;; better by expanding our own loop.
9518 (define_expand "atomic_<atomic><mode>"
9520 (match_operand:HQI 0 "memory_operand") ;; memory
9521 (match_operand:HQI 1 "general_operand")) ;; val in
9522 (match_operand:SI 2 "const_int_operand")] ;; model
9525 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9526 operands[1], false);
9530 (define_expand "atomic_fetch_<atomic><mode>"
9531 [(match_operand:HQI 0 "register_operand") ;; val out
9533 (match_operand:HQI 1 "memory_operand") ;; memory
9534 (match_operand:HQI 2 "general_operand")) ;; val in
9535 (match_operand:SI 3 "const_int_operand")] ;; model
9538 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9539 operands[2], false);
9543 (define_expand "atomic_<atomic>_fetch<mode>"
9544 [(match_operand:HQI 0 "register_operand") ;; val out
9546 (match_operand:HQI 1 "memory_operand") ;; memory
9547 (match_operand:HQI 2 "general_operand")) ;; val in
9548 (match_operand:SI 3 "const_int_operand")] ;; model
9551 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9556 (define_expand "atomic_exchange<mode>"
9557 [(match_operand:HQI 0 "register_operand") ;; val out
9558 (match_operand:HQI 1 "memory_operand") ;; memory
9559 (match_operand:HQI 2 "general_operand") ;; val in
9560 (match_operand:SI 3 "const_int_operand")] ;; model
9563 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9564 operands[2], false);
9569 ;;- Miscellaneous instructions.
9573 ; allocate stack instruction pattern(s).
9576 (define_expand "allocate_stack"
9577 [(match_operand 0 "general_operand" "")
9578 (match_operand 1 "general_operand" "")]
9581 rtx temp = gen_reg_rtx (Pmode);
9583 emit_move_insn (temp, s390_back_chain_rtx ());
9584 anti_adjust_stack (operands[1]);
9585 emit_move_insn (s390_back_chain_rtx (), temp);
9587 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9593 ; setjmp instruction pattern.
9596 (define_expand "builtin_setjmp_receiver"
9597 [(match_operand 0 "" "")]
9600 emit_insn (s390_load_got ());
9601 emit_use (pic_offset_table_rtx);
9605 ;; These patterns say how to save and restore the stack pointer. We need not
9606 ;; save the stack pointer at function level since we are careful to
9607 ;; preserve the backchain. At block level, we have to restore the backchain
9608 ;; when we restore the stack pointer.
9610 ;; For nonlocal gotos, we must save both the stack pointer and its
9611 ;; backchain and restore both. Note that in the nonlocal case, the
9612 ;; save area is a memory location.
9614 (define_expand "save_stack_function"
9615 [(match_operand 0 "general_operand" "")
9616 (match_operand 1 "general_operand" "")]
9620 (define_expand "restore_stack_function"
9621 [(match_operand 0 "general_operand" "")
9622 (match_operand 1 "general_operand" "")]
9626 (define_expand "restore_stack_block"
9627 [(match_operand 0 "register_operand" "")
9628 (match_operand 1 "register_operand" "")]
9631 rtx temp = gen_reg_rtx (Pmode);
9633 emit_move_insn (temp, s390_back_chain_rtx ());
9634 emit_move_insn (operands[0], operands[1]);
9635 emit_move_insn (s390_back_chain_rtx (), temp);
9640 (define_expand "save_stack_nonlocal"
9641 [(match_operand 0 "memory_operand" "")
9642 (match_operand 1 "register_operand" "")]
9645 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9647 /* Copy the backchain to the first word, sp to the second and the
9648 literal pool base to the third. */
9650 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9651 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9652 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9654 if (TARGET_BACKCHAIN)
9655 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9657 emit_move_insn (save_sp, operands[1]);
9658 emit_move_insn (save_bp, base);
9663 (define_expand "restore_stack_nonlocal"
9664 [(match_operand 0 "register_operand" "")
9665 (match_operand 1 "memory_operand" "")]
9668 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9669 rtx temp = NULL_RTX;
9671 /* Restore the backchain from the first word, sp from the second and the
9672 literal pool base from the third. */
9674 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9675 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9676 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9678 if (TARGET_BACKCHAIN)
9679 temp = force_reg (Pmode, save_bc);
9681 emit_move_insn (base, save_bp);
9682 emit_move_insn (operands[0], save_sp);
9685 emit_move_insn (s390_back_chain_rtx (), temp);
9691 (define_expand "exception_receiver"
9695 s390_set_has_landing_pad_p (true);
9700 ; nop instruction pattern(s).
9707 [(set_attr "op_type" "RR")
9708 (set_attr "z10prop" "z10_fr_E1")])
9714 [(set_attr "op_type" "RR")])
9716 ;;- Undeletable nops (used for hotpatching)
9718 (define_insn "nop_2_byte"
9719 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
9722 [(set_attr "op_type" "RR")])
9724 (define_insn "nop_4_byte"
9725 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
9728 [(set_attr "op_type" "RX")])
9730 (define_insn "nop_6_byte"
9731 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
9734 [(set_attr "op_type" "RIL")])
9738 ; Special literal pool access instruction pattern(s).
9741 (define_insn "*pool_entry"
9742 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9743 UNSPECV_POOL_ENTRY)]
9746 machine_mode mode = GET_MODE (PATTERN (insn));
9747 unsigned int align = GET_MODE_BITSIZE (mode);
9748 s390_output_pool_entry (operands[0], mode, align);
9751 [(set (attr "length")
9752 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9754 (define_insn "pool_align"
9755 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9756 UNSPECV_POOL_ALIGN)]
9759 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9761 (define_insn "pool_section_start"
9762 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9765 [(set_attr "length" "0")])
9767 (define_insn "pool_section_end"
9768 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9771 [(set_attr "length" "0")])
9773 (define_insn "main_base_31_small"
9774 [(set (match_operand 0 "register_operand" "=a")
9775 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9776 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9778 [(set_attr "op_type" "RR")
9779 (set_attr "type" "la")
9780 (set_attr "z196prop" "z196_cracked")])
9782 (define_insn "main_base_31_large"
9783 [(set (match_operand 0 "register_operand" "=a")
9784 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9785 (set (pc) (label_ref (match_operand 2 "" "")))]
9786 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9788 [(set_attr "op_type" "RI")
9789 (set_attr "z196prop" "z196_cracked")])
9791 (define_insn "main_base_64"
9792 [(set (match_operand 0 "register_operand" "=a")
9793 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9794 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9796 [(set_attr "op_type" "RIL")
9797 (set_attr "type" "larl")
9798 (set_attr "z10prop" "z10_fwd_A1")])
9800 (define_insn "main_pool"
9801 [(set (match_operand 0 "register_operand" "=a")
9802 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9803 "GET_MODE (operands[0]) == Pmode"
9808 (if_then_else (match_test "TARGET_CPU_ZARCH")
9809 (const_string "larl") (const_string "la")))])
9811 (define_insn "reload_base_31"
9812 [(set (match_operand 0 "register_operand" "=a")
9813 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9814 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9815 "basr\t%0,0\;la\t%0,%1-.(%0)"
9816 [(set_attr "length" "6")
9817 (set_attr "type" "la")
9818 (set_attr "z196prop" "z196_cracked")])
9820 (define_insn "reload_base_64"
9821 [(set (match_operand 0 "register_operand" "=a")
9822 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9823 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9825 [(set_attr "op_type" "RIL")
9826 (set_attr "type" "larl")
9827 (set_attr "z10prop" "z10_fwd_A1")])
9830 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9835 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9838 ;; Insns related to generating the function prologue and epilogue.
9842 (define_expand "prologue"
9843 [(use (const_int 0))]
9845 "s390_emit_prologue (); DONE;")
9847 (define_expand "epilogue"
9848 [(use (const_int 1))]
9850 "s390_emit_epilogue (false); DONE;")
9852 (define_expand "sibcall_epilogue"
9853 [(use (const_int 0))]
9855 "s390_emit_epilogue (true); DONE;")
9857 ;; A direct return instruction, without using an epilogue.
9858 (define_insn "<code>"
9860 "s390_can_use_<code>_insn ()"
9862 [(set_attr "op_type" "RR")
9863 (set_attr "type" "jsr")
9864 (set_attr "atype" "agen")])
9866 (define_insn "*return"
9868 (use (match_operand 0 "register_operand" "a"))]
9869 "GET_MODE (operands[0]) == Pmode"
9871 [(set_attr "op_type" "RR")
9872 (set_attr "type" "jsr")
9873 (set_attr "atype" "agen")])
9876 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9877 ;; pointer. This is used for compatibility.
9879 (define_expand "ptr_extend"
9880 [(set (match_operand:DI 0 "register_operand" "=r")
9881 (match_operand:SI 1 "register_operand" "r"))]
9884 emit_insn (gen_anddi3 (operands[0],
9885 gen_lowpart (DImode, operands[1]),
9886 GEN_INT (0x7fffffff)));
9890 ;; Instruction definition to expand eh_return macro to support
9891 ;; swapping in special linkage return addresses.
9893 (define_expand "eh_return"
9894 [(use (match_operand 0 "register_operand" ""))]
9897 s390_emit_tpf_eh_return (operands[0]);
9902 ; Stack Protector Patterns
9905 (define_expand "stack_protect_set"
9906 [(set (match_operand 0 "memory_operand" "")
9907 (match_operand 1 "memory_operand" ""))]
9910 #ifdef TARGET_THREAD_SSP_OFFSET
9912 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9913 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9916 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9918 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9923 (define_insn "stack_protect_set<mode>"
9924 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9925 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9927 "mvc\t%O0(%G0,%R0),%S1"
9928 [(set_attr "op_type" "SS")])
9930 (define_expand "stack_protect_test"
9931 [(set (reg:CC CC_REGNUM)
9932 (compare (match_operand 0 "memory_operand" "")
9933 (match_operand 1 "memory_operand" "")))
9934 (match_operand 2 "" "")]
9938 #ifdef TARGET_THREAD_SSP_OFFSET
9940 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9941 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9944 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9946 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9948 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9949 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9950 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9954 (define_insn "stack_protect_test<mode>"
9955 [(set (reg:CCZ CC_REGNUM)
9956 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9957 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9959 "clc\t%O0(%G0,%R0),%S1"
9960 [(set_attr "op_type" "SS")])
9962 ; This is used in s390_emit_prologue in order to prevent insns
9963 ; adjusting the stack pointer to be moved over insns writing stack
9964 ; slots using a copy of the stack pointer in a different register.
9965 (define_insn "stack_tie"
9966 [(set (match_operand:BLK 0 "memory_operand" "+m")
9967 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9970 [(set_attr "length" "0")])
9974 ; Data prefetch patterns
9977 (define_insn "prefetch"
9978 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9979 (match_operand:SI 1 "const_int_operand" " n,n")
9980 (match_operand:SI 2 "const_int_operand" " n,n"))]
9983 switch (which_alternative)
9986 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9988 if (larl_operand (operands[0], Pmode))
9989 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9992 /* This might be reached for symbolic operands with an odd
9993 addend. We simply omit the prefetch for such rare cases. */
9998 [(set_attr "type" "load,larl")
9999 (set_attr "op_type" "RXY,RIL")
10000 (set_attr "z10prop" "z10_super")
10001 (set_attr "z196prop" "z196_alone")])
10005 ; Byte swap instructions
10008 (define_insn "bswap<mode>2"
10009 [(set (match_operand:GPR 0 "register_operand" "=d, d")
10010 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
10015 [(set_attr "type" "*,load")
10016 (set_attr "op_type" "RRE,RXY")
10017 (set_attr "z10prop" "z10_super")])
10021 ; Population count instruction
10024 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10025 ; portions and stores the result in the corresponding bytes in op0.
10026 (define_insn "*popcount<mode>"
10027 [(set (match_operand:INT 0 "register_operand" "=d")
10028 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10029 (clobber (reg:CC CC_REGNUM))]
10032 [(set_attr "op_type" "RRE")])
10034 (define_expand "popcountdi2"
10036 (parallel [(set (match_operand:DI 0 "register_operand" "")
10037 (unspec:DI [(match_operand:DI 1 "register_operand")]
10039 (clobber (reg:CC CC_REGNUM))])
10040 ; sllg op2, op0, 32
10041 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10043 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10044 (clobber (reg:CC CC_REGNUM))])
10045 ; sllg op2, op0, 16
10047 (ashift:DI (match_dup 0) (const_int 16)))
10049 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10050 (clobber (reg:CC CC_REGNUM))])
10052 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10054 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10055 (clobber (reg:CC CC_REGNUM))])
10056 ; srlg op0, op0, 56
10057 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10058 "TARGET_Z196 && TARGET_64BIT"
10059 "operands[2] = gen_reg_rtx (DImode);")
10061 (define_expand "popcountsi2"
10063 (parallel [(set (match_operand:SI 0 "register_operand" "")
10064 (unspec:SI [(match_operand:SI 1 "register_operand")]
10066 (clobber (reg:CC CC_REGNUM))])
10067 ; sllk op2, op0, 16
10069 (ashift:SI (match_dup 0) (const_int 16)))
10071 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10072 (clobber (reg:CC CC_REGNUM))])
10074 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10076 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10077 (clobber (reg:CC CC_REGNUM))])
10079 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10081 "operands[2] = gen_reg_rtx (SImode);")
10083 (define_expand "popcounthi2"
10085 (parallel [(set (match_operand:HI 0 "register_operand" "")
10086 (unspec:HI [(match_operand:HI 1 "register_operand")]
10088 (clobber (reg:CC CC_REGNUM))])
10091 (ashift:SI (match_dup 0) (const_int 8)))
10093 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10094 (clobber (reg:CC CC_REGNUM))])
10096 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10098 "operands[2] = gen_reg_rtx (SImode);")
10100 (define_expand "popcountqi2"
10102 (parallel [(set (match_operand:QI 0 "register_operand" "")
10103 (unspec:QI [(match_operand:QI 1 "register_operand")]
10105 (clobber (reg:CC CC_REGNUM))])]
10110 ;;- Copy sign instructions
10113 (define_insn "copysign<mode>3"
10114 [(set (match_operand:FP 0 "register_operand" "=f")
10115 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10116 (match_operand:FP 2 "register_operand" "f")]
10120 [(set_attr "op_type" "RRF")
10121 (set_attr "type" "fsimp<mode>")])
10125 ;;- Transactional execution instructions
10128 ; This splitter helps combine to make use of CC directly when
10129 ; comparing the integer result of a tbegin builtin with a constant.
10130 ; The unspec is already removed by canonicalize_comparison. So this
10131 ; splitters only job is to turn the PARALLEL into separate insns
10132 ; again. Unfortunately this only works with the very first cc/int
10133 ; compare since combine is not able to deal with data flow across
10134 ; basic block boundaries.
10136 ; It needs to be an insn pattern as well since combine does not apply
10137 ; the splitter directly. Combine would only use it if it actually
10138 ; would reduce the number of instructions.
10139 (define_insn_and_split "*ccraw_to_int"
10142 (match_operator 0 "s390_eqne_operator"
10143 [(reg:CCRAW CC_REGNUM)
10144 (match_operand 1 "const_int_operand" "")])
10145 (label_ref (match_operand 2 "" ""))
10147 (set (match_operand:SI 3 "register_operand" "=d")
10148 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10152 [(set (match_dup 3)
10153 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10155 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10156 (label_ref (match_dup 2))
10160 ; Non-constrained transaction begin
10162 (define_expand "tbegin"
10163 [(match_operand:SI 0 "register_operand" "")
10164 (match_operand:BLK 1 "memory_operand" "")]
10167 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10171 (define_expand "tbegin_nofloat"
10172 [(match_operand:SI 0 "register_operand" "")
10173 (match_operand:BLK 1 "memory_operand" "")]
10176 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10180 (define_expand "tbegin_retry"
10181 [(match_operand:SI 0 "register_operand" "")
10182 (match_operand:BLK 1 "memory_operand" "")
10183 (match_operand:SI 2 "general_operand" "")]
10186 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10190 (define_expand "tbegin_retry_nofloat"
10191 [(match_operand:SI 0 "register_operand" "")
10192 (match_operand:BLK 1 "memory_operand" "")
10193 (match_operand:SI 2 "general_operand" "")]
10196 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10200 (define_insn "tbegin_1"
10201 [(set (reg:CCRAW CC_REGNUM)
10202 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10204 (set (match_operand:BLK 1 "memory_operand" "=Q")
10205 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10206 (clobber (reg:DF 16))
10207 (clobber (reg:DF 17))
10208 (clobber (reg:DF 18))
10209 (clobber (reg:DF 19))
10210 (clobber (reg:DF 20))
10211 (clobber (reg:DF 21))
10212 (clobber (reg:DF 22))
10213 (clobber (reg:DF 23))
10214 (clobber (reg:DF 24))
10215 (clobber (reg:DF 25))
10216 (clobber (reg:DF 26))
10217 (clobber (reg:DF 27))
10218 (clobber (reg:DF 28))
10219 (clobber (reg:DF 29))
10220 (clobber (reg:DF 30))
10221 (clobber (reg:DF 31))]
10222 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10223 ; not supposed to be used for immediates (see genpreds.c).
10224 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10226 [(set_attr "op_type" "SIL")])
10228 ; Same as above but without the FPR clobbers
10229 (define_insn "tbegin_nofloat_1"
10230 [(set (reg:CCRAW CC_REGNUM)
10231 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10233 (set (match_operand:BLK 1 "memory_operand" "=Q")
10234 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10235 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10237 [(set_attr "op_type" "SIL")])
10240 ; Constrained transaction begin
10242 (define_expand "tbeginc"
10243 [(set (reg:CCRAW CC_REGNUM)
10244 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10249 (define_insn "*tbeginc_1"
10250 [(set (reg:CCRAW CC_REGNUM)
10251 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10253 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10255 [(set_attr "op_type" "SIL")])
10259 (define_expand "tend"
10260 [(set (reg:CCRAW CC_REGNUM)
10261 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10262 (set (match_operand:SI 0 "register_operand" "")
10263 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10267 (define_insn "*tend_1"
10268 [(set (reg:CCRAW CC_REGNUM)
10269 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10272 [(set_attr "op_type" "S")])
10274 ; Transaction abort
10276 (define_expand "tabort"
10277 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10279 "TARGET_HTM && operands != NULL"
10281 if (CONST_INT_P (operands[0])
10282 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10284 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10285 ". Values in range 0 through 255 are reserved.",
10286 INTVAL (operands[0]));
10291 (define_insn "*tabort_1"
10292 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10294 "TARGET_HTM && operands != NULL"
10296 [(set_attr "op_type" "S")])
10298 ; Transaction extract nesting depth
10300 (define_insn "etnd"
10301 [(set (match_operand:SI 0 "register_operand" "=d")
10302 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10305 [(set_attr "op_type" "RRE")])
10307 ; Non-transactional store
10309 (define_insn "ntstg"
10310 [(set (match_operand:DI 0 "memory_operand" "=RT")
10311 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10315 [(set_attr "op_type" "RXY")])
10317 ; Transaction perform processor assist
10319 (define_expand "tx_assist"
10320 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10321 (reg:SI GPR0_REGNUM)
10327 (define_insn "*ppa"
10328 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10329 (match_operand:SI 1 "register_operand" "d")
10330 (match_operand 2 "const_int_operand" "I")]
10332 "TARGET_HTM && INTVAL (operands[2]) < 16"
10334 [(set_attr "op_type" "RRF")])
10337 ; Set and get floating point control register
10339 (define_insn "s390_sfpc"
10340 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10342 "TARGET_HARD_FLOAT"
10345 (define_insn "s390_efpc"
10346 [(set (match_operand:SI 0 "register_operand" "=d")
10347 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10348 "TARGET_HARD_FLOAT"