1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
60 (define_c_enum "unspec" [
68 ; GOT/PLT and lt-relative accesses
89 ; TLS relocation specifiers
105 ; Stack Smashing Protector
109 ; Test Data Class (TDC)
118 ;; UNSPEC_VOLATILE usage
121 (define_c_enum "unspecv" [
148 ; Registers with special meaning
152 ; Sibling call register.
154 ; Literal pool base register.
156 ; Return address register.
158 ; Condition code register.
160 ; Thread local storage pointer register.
164 ; Hardware register names
168 ; General purpose registers
170 ; Floating point registers.
176 ;; PFPO GPR0 argument format
181 ; PFPO operation type
182 (PFPO_CONVERT 0x1000000)
184 (PFPO_OP_TYPE_SF 0x5)
185 (PFPO_OP_TYPE_DF 0x6)
186 (PFPO_OP_TYPE_TF 0x7)
187 (PFPO_OP_TYPE_SD 0x8)
188 (PFPO_OP_TYPE_DD 0x9)
189 (PFPO_OP_TYPE_TD 0xa)
190 ; Bitposition of operand types
191 (PFPO_OP0_TYPE_SHIFT 16)
192 (PFPO_OP1_TYPE_SHIFT 8)
196 ;; Instruction operand type as used in the Principles of Operation.
197 ;; Used to determine defaults for length and other attribute values.
199 (define_attr "op_type"
200 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
203 ;; Instruction type attribute used for scheduling.
205 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
206 cs,vs,store,sem,idiv,
207 imulhi,imulsi,imuldi,
208 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
209 floadtf,floaddf,floadsf,fstoredf,fstoresf,
210 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
211 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
213 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
214 itoftf, itofdf, itofsf, itofdd, itoftd,
215 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
216 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
218 (cond [(eq_attr "op_type" "NN") (const_string "other")
219 (eq_attr "op_type" "SS") (const_string "cs")]
220 (const_string "integer")))
222 ;; Another attribute used for scheduling purposes:
223 ;; agen: Instruction uses the address generation unit
224 ;; reg: Instruction does not use the agen unit
226 (define_attr "atype" "agen,reg"
227 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
229 (const_string "agen")))
231 ;; Properties concerning Z10 execution grouping and value forwarding.
232 ;; z10_super: instruction is superscalar.
233 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
234 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
235 ;; target register. It can forward this value to a second instruction that reads
236 ;; the same register if that second instruction is issued in the same group.
237 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
238 ;; instruction in the S pipe writes to the register, then the T instruction
239 ;; can immediately read the new value.
240 ;; z10_fr: union of Z10_fwd and z10_rec.
241 ;; z10_c: second operand of instruction is a register and read with complemented bits.
243 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
246 (define_attr "z10prop" "none,
247 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
248 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
250 z10_fr, z10_fr_A3, z10_fr_E1,
252 (const_string "none"))
254 ;; Properties concerning Z196 decoding
255 ;; z196_alone: must group alone
256 ;; z196_end: ends a group
257 ;; z196_cracked: instruction is cracked or expanded
258 (define_attr "z196prop" "none,
259 z196_alone, z196_ends,
261 (const_string "none"))
263 (define_attr "mnemonic" "unknown" (const_string "unknown"))
267 (define_attr "length" ""
268 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
269 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
273 ;; Processor type. This attribute must exactly match the processor_type
274 ;; enumeration in s390.h. The current machine description does not
275 ;; distinguish between g5 and g6, but there are differences between the two
276 ;; CPUs could in theory be modeled.
278 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
279 (const (symbol_ref "s390_tune_attr")))
281 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196,zEC12"
282 (const_string "standard"))
284 (define_attr "enabled" ""
285 (cond [(eq_attr "cpu_facility" "standard")
288 (and (eq_attr "cpu_facility" "ieee")
289 (match_test "TARGET_CPU_IEEE_FLOAT"))
292 (and (eq_attr "cpu_facility" "zarch")
293 (match_test "TARGET_ZARCH"))
296 (and (eq_attr "cpu_facility" "longdisp")
297 (match_test "TARGET_LONG_DISPLACEMENT"))
300 (and (eq_attr "cpu_facility" "extimm")
301 (match_test "TARGET_EXTIMM"))
304 (and (eq_attr "cpu_facility" "dfp")
305 (match_test "TARGET_DFP"))
308 (and (eq_attr "cpu_facility" "z10")
309 (match_test "TARGET_Z10"))
312 (and (eq_attr "cpu_facility" "z196")
313 (match_test "TARGET_Z196"))
316 (and (eq_attr "cpu_facility" "zEC12")
317 (match_test "TARGET_ZEC12"))
321 ;; Pipeline description for z900. For lack of anything better,
322 ;; this description is also used for the g5 and g6.
325 ;; Pipeline description for z990, z9-109 and z9-ec.
328 ;; Pipeline description for z10
331 ;; Pipeline description for z196
334 ;; Pipeline description for zEC12
338 (include "predicates.md")
340 ;; Constraint definitions
341 (include "constraints.md")
348 ;; These mode iterators allow floating point patterns to be generated from the
350 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
351 (SD "TARGET_HARD_DFP")])
352 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
353 (define_mode_iterator FPALL [TF DF SF TD DD SD])
354 (define_mode_iterator BFP [TF DF SF])
355 (define_mode_iterator DFP [TD DD])
356 (define_mode_iterator DFP_ALL [TD DD SD])
357 (define_mode_iterator DSF [DF SF])
358 (define_mode_iterator SD_SF [SF SD])
359 (define_mode_iterator DD_DF [DF DD])
360 (define_mode_iterator TD_TF [TF TD])
362 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
363 ;; from the same template.
364 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
365 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
366 (define_mode_iterator DSI [DI SI])
367 (define_mode_iterator TDI [TI DI])
369 ;; These mode iterators allow :P to be used for patterns that operate on
370 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
371 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
373 ;; These macros refer to the actual word_mode of the configuration.
374 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
375 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
376 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
378 ;; Used by the umul pattern to express modes having half the size.
379 (define_mode_attr DWH [(TI "DI") (DI "SI")])
380 (define_mode_attr dwh [(TI "di") (DI "si")])
382 ;; This mode iterator allows the QI and HI patterns to be defined from
383 ;; the same template.
384 (define_mode_iterator HQI [HI QI])
386 ;; This mode iterator allows the integer patterns to be defined from the
388 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
389 (define_mode_iterator INTALL [TI DI SI HI QI])
390 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
392 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
393 ;; the same template.
394 (define_code_iterator SHIFT [ashift lshiftrt])
396 ;; This iterator allow r[ox]sbg to be defined with the same template
397 (define_code_iterator IXOR [ior xor])
399 ;; This iterator and attribute allow to combine most atomic operations.
400 (define_code_iterator ATOMIC [and ior xor plus minus mult])
401 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
402 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
403 (plus "add") (minus "sub") (mult "nand")])
404 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
406 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
407 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
408 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
410 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
411 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
413 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
415 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
416 ;; Likewise for "<RXe>".
417 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
418 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
420 ;; The decimal floating point variants of add, sub, div and mul support 3
421 ;; fp register operands. The following attributes allow to merge the bfp and
422 ;; dfp variants in a single insn definition.
424 ;; This attribute is used to set op_type accordingly.
425 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
426 (DD "RRR") (SD "RRR")])
428 ;; This attribute is used in the operand constraint list in order to have the
429 ;; first and the second operand match for bfp modes.
430 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
432 ;; This attribute is used in the operand list of the instruction to have an
433 ;; additional operand for the dfp instructions.
434 (define_mode_attr op1 [(TF "") (DF "") (SF "")
435 (TD "%1,") (DD "%1,") (SD "%1,")])
438 ;; This attribute is used in the operand constraint list
439 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
440 ;; TFmode values are represented by a fp register pair. Since the
441 ;; sign bit instructions only handle single source and target fp registers
442 ;; these instructions can only be used for TFmode values if the source and
443 ;; target operand uses the same fp register.
444 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
446 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
447 ;; This is used to disable the memory alternative in TFmode patterns.
448 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
450 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
451 ;; within instruction mnemonics.
452 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
454 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
455 ;; modes and to an empty string for bfp modes.
456 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
458 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
459 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
460 ;; version only operates on one register.
461 (define_mode_attr d0 [(DI "d") (SI "0")])
463 ;; In combination with d0 this allows to combine instructions of which the 31bit
464 ;; version only operates on one register. The DImode version needs an additional
465 ;; register for the assembler output.
466 (define_mode_attr 1 [(DI "%1,") (SI "")])
468 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
469 ;; 'ashift' and "srdl" in 'lshiftrt'.
470 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
472 ;; In SHIFT templates, this attribute holds the correct standard name for the
473 ;; pattern itself and the corresponding function calls.
474 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
476 ;; This attribute handles differences in the instruction 'type' and will result
477 ;; in "RRE" for DImode and "RR" for SImode.
478 (define_mode_attr E [(DI "E") (SI "")])
480 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
481 ;; to result in "RXY" for DImode and "RX" for SImode.
482 (define_mode_attr Y [(DI "Y") (SI "")])
484 ;; This attribute handles differences in the instruction 'type' and will result
485 ;; in "RSE" for TImode and "RS" for DImode.
486 (define_mode_attr TE [(TI "E") (DI "")])
488 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
489 ;; and "lcr" in SImode.
490 (define_mode_attr g [(DI "g") (SI "")])
492 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
493 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
494 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
495 ;; variant for long displacements.
496 (define_mode_attr y [(DI "g") (SI "y")])
498 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
499 ;; and "cds" in DImode.
500 (define_mode_attr tg [(TI "g") (DI "")])
502 ;; In TDI templates, a string like "c<d>sg".
503 (define_mode_attr td [(TI "d") (DI "")])
505 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
506 ;; and "cfdbr" in SImode.
507 (define_mode_attr gf [(DI "g") (SI "f")])
509 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
510 ;; and sllk for SI. This way it is possible to merge the new z196 SI
511 ;; 3 operands shift instructions into the existing patterns.
512 (define_mode_attr gk [(DI "g") (SI "k")])
514 ;; ICM mask required to load MODE value into the lowest subreg
515 ;; of a SImode register.
516 (define_mode_attr icm_lo [(HI "3") (QI "1")])
518 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
519 ;; HImode and "llgc" in QImode.
520 (define_mode_attr hc [(HI "h") (QI "c")])
522 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
524 (define_mode_attr DBL [(DI "TI") (SI "DI")])
526 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
527 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
528 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
530 ;; Maximum unsigned integer that fits in MODE.
531 (define_mode_attr max_uint [(HI "65535") (QI "255")])
533 ;; Start and end field computations for RISBG et al.
534 (define_mode_attr bfstart [(DI "s") (SI "t")])
535 (define_mode_attr bfend [(DI "e") (SI "f")])
537 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
538 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
541 ;;- Compare instructions.
544 ; Test-under-Mask instructions
546 (define_insn "*tmqi_mem"
547 [(set (reg CC_REGNUM)
548 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
549 (match_operand:QI 1 "immediate_operand" "n,n"))
550 (match_operand:QI 2 "immediate_operand" "n,n")))]
551 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
555 [(set_attr "op_type" "SI,SIY")
556 (set_attr "z10prop" "z10_super,z10_super")])
558 (define_insn "*tmdi_reg"
559 [(set (reg CC_REGNUM)
560 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
561 (match_operand:DI 1 "immediate_operand"
562 "N0HD0,N1HD0,N2HD0,N3HD0"))
563 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
565 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
566 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
572 [(set_attr "op_type" "RI")
573 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
575 (define_insn "*tmsi_reg"
576 [(set (reg CC_REGNUM)
577 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
578 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
579 (match_operand:SI 2 "immediate_operand" "n,n")))]
580 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
581 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
585 [(set_attr "op_type" "RI")
586 (set_attr "z10prop" "z10_super,z10_super")])
588 (define_insn "*tm<mode>_full"
589 [(set (reg CC_REGNUM)
590 (compare (match_operand:HQI 0 "register_operand" "d")
591 (match_operand:HQI 1 "immediate_operand" "n")))]
592 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
594 [(set_attr "op_type" "RI")
595 (set_attr "z10prop" "z10_super")])
599 ; Load-and-Test instructions
602 ; tst(di|si) instruction pattern(s).
604 (define_insn "*tstdi_sign"
605 [(set (reg CC_REGNUM)
609 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
610 (const_int 32)) (const_int 32))
611 (match_operand:DI 1 "const0_operand" "")))
612 (set (match_operand:DI 2 "register_operand" "=d,d")
613 (sign_extend:DI (match_dup 0)))]
614 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
617 [(set_attr "op_type" "RRE,RXY")
618 (set_attr "cpu_facility" "*,z10")
619 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
622 (define_insn "*tst<mode>_extimm"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
625 (match_operand:GPR 1 "const0_operand" "")))
626 (set (match_operand:GPR 2 "register_operand" "=d,d")
628 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
632 [(set_attr "op_type" "RR<E>,RXY")
633 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
636 (define_insn "*tst<mode>_cconly_extimm"
637 [(set (reg CC_REGNUM)
638 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
639 (match_operand:GPR 1 "const0_operand" "")))
640 (clobber (match_scratch:GPR 2 "=X,d"))]
641 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
645 [(set_attr "op_type" "RR<E>,RXY")
646 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
648 (define_insn "*tstdi"
649 [(set (reg CC_REGNUM)
650 (compare (match_operand:DI 0 "register_operand" "d")
651 (match_operand:DI 1 "const0_operand" "")))
652 (set (match_operand:DI 2 "register_operand" "=d")
654 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
656 [(set_attr "op_type" "RRE")
657 (set_attr "z10prop" "z10_fr_E1")])
659 (define_insn "*tstsi"
660 [(set (reg CC_REGNUM)
661 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
662 (match_operand:SI 1 "const0_operand" "")))
663 (set (match_operand:SI 2 "register_operand" "=d,d,d")
665 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
670 [(set_attr "op_type" "RR,RS,RSY")
671 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
673 (define_insn "*tstsi_cconly"
674 [(set (reg CC_REGNUM)
675 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
676 (match_operand:SI 1 "const0_operand" "")))
677 (clobber (match_scratch:SI 2 "=X,d,d"))]
678 "s390_match_ccmode(insn, CCSmode)"
683 [(set_attr "op_type" "RR,RS,RSY")
684 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
686 (define_insn "*tstdi_cconly_31"
687 [(set (reg CC_REGNUM)
688 (compare (match_operand:DI 0 "register_operand" "d")
689 (match_operand:DI 1 "const0_operand" "")))]
690 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
692 [(set_attr "op_type" "RS")
693 (set_attr "atype" "reg")])
696 (define_insn "*tst<mode>_cconly2"
697 [(set (reg CC_REGNUM)
698 (compare (match_operand:GPR 0 "register_operand" "d")
699 (match_operand:GPR 1 "const0_operand" "")))]
700 "s390_match_ccmode(insn, CCSmode)"
702 [(set_attr "op_type" "RR<E>")
703 (set_attr "z10prop" "z10_fr_E1")])
705 ; tst(hi|qi) instruction pattern(s).
707 (define_insn "*tst<mode>CCT"
708 [(set (reg CC_REGNUM)
709 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
710 (match_operand:HQI 1 "const0_operand" "")))
711 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
713 "s390_match_ccmode(insn, CCTmode)"
716 icmy\t%2,<icm_lo>,%S0
718 [(set_attr "op_type" "RS,RSY,RI")
719 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
721 (define_insn "*tsthiCCT_cconly"
722 [(set (reg CC_REGNUM)
723 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
724 (match_operand:HI 1 "const0_operand" "")))
725 (clobber (match_scratch:HI 2 "=d,d,X"))]
726 "s390_match_ccmode(insn, CCTmode)"
731 [(set_attr "op_type" "RS,RSY,RI")
732 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
734 (define_insn "*tstqiCCT_cconly"
735 [(set (reg CC_REGNUM)
736 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
737 (match_operand:QI 1 "const0_operand" "")))]
738 "s390_match_ccmode(insn, CCTmode)"
743 [(set_attr "op_type" "SI,SIY,RI")
744 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
746 (define_insn "*tst<mode>"
747 [(set (reg CC_REGNUM)
748 (compare (match_operand:HQI 0 "s_operand" "Q,S")
749 (match_operand:HQI 1 "const0_operand" "")))
750 (set (match_operand:HQI 2 "register_operand" "=d,d")
752 "s390_match_ccmode(insn, CCSmode)"
755 icmy\t%2,<icm_lo>,%S0"
756 [(set_attr "op_type" "RS,RSY")
757 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
759 (define_insn "*tst<mode>_cconly"
760 [(set (reg CC_REGNUM)
761 (compare (match_operand:HQI 0 "s_operand" "Q,S")
762 (match_operand:HQI 1 "const0_operand" "")))
763 (clobber (match_scratch:HQI 2 "=d,d"))]
764 "s390_match_ccmode(insn, CCSmode)"
767 icmy\t%2,<icm_lo>,%S0"
768 [(set_attr "op_type" "RS,RSY")
769 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
772 ; Compare (equality) instructions
774 (define_insn "*cmpdi_cct"
775 [(set (reg CC_REGNUM)
776 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
777 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
778 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
785 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
786 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
788 (define_insn "*cmpsi_cct"
789 [(set (reg CC_REGNUM)
790 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
791 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
792 "s390_match_ccmode (insn, CCTmode)"
800 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
801 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
803 ; Compare (signed) instructions
805 (define_insn "*cmpdi_ccs_sign"
806 [(set (reg CC_REGNUM)
807 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
809 (match_operand:DI 0 "register_operand" "d, d,d")))]
810 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
815 [(set_attr "op_type" "RRE,RXY,RIL")
816 (set_attr "z10prop" "z10_c,*,*")
817 (set_attr "type" "*,*,larl")])
821 (define_insn "*cmpsi_ccs_sign"
822 [(set (reg CC_REGNUM)
823 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
824 (match_operand:SI 0 "register_operand" "d,d,d")))]
825 "s390_match_ccmode(insn, CCSRmode)"
830 [(set_attr "op_type" "RX,RXY,RIL")
831 (set_attr "cpu_facility" "*,*,z10")
832 (set_attr "type" "*,*,larl")
833 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
835 (define_insn "*cmphi_ccs_z10"
836 [(set (reg CC_REGNUM)
837 (compare (match_operand:HI 0 "s_operand" "Q")
838 (match_operand:HI 1 "immediate_operand" "K")))]
839 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
841 [(set_attr "op_type" "SIL")
842 (set_attr "z196prop" "z196_cracked")])
844 (define_insn "*cmpdi_ccs_signhi_rl"
845 [(set (reg CC_REGNUM)
846 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
847 (match_operand:GPR 0 "register_operand" "d,d")))]
848 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
852 [(set_attr "op_type" "RXY,RIL")
853 (set_attr "type" "*,larl")])
855 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
856 (define_insn "*cmp<mode>_ccs"
857 [(set (reg CC_REGNUM)
858 (compare (match_operand:GPR 0 "nonimmediate_operand"
860 (match_operand:GPR 1 "general_operand"
862 "s390_match_ccmode(insn, CCSmode)"
871 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
872 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
873 (set_attr "type" "*,*,*,*,*,*,larl")
874 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
877 ; Compare (unsigned) instructions
879 (define_insn "*cmpsi_ccu_zerohi_rlsi"
880 [(set (reg CC_REGNUM)
881 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
882 "larl_operand" "X")))
883 (match_operand:SI 0 "register_operand" "d")))]
884 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
886 [(set_attr "op_type" "RIL")
887 (set_attr "type" "larl")
888 (set_attr "z10prop" "z10_super")])
891 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
892 [(set (reg CC_REGNUM)
893 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
894 "larl_operand" "X")))
895 (match_operand:GPR 0 "register_operand" "d")))]
896 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
898 [(set_attr "op_type" "RIL")
899 (set_attr "type" "larl")
900 (set_attr "z10prop" "z10_super")])
902 (define_insn "*cmpdi_ccu_zero"
903 [(set (reg CC_REGNUM)
904 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
906 (match_operand:DI 0 "register_operand" "d, d,d")))]
907 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
912 [(set_attr "op_type" "RRE,RXY,RIL")
913 (set_attr "cpu_facility" "*,*,z10")
914 (set_attr "type" "*,*,larl")
915 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
917 (define_insn "*cmpdi_ccu"
918 [(set (reg CC_REGNUM)
919 (compare (match_operand:DI 0 "nonimmediate_operand"
921 (match_operand:DI 1 "general_operand"
922 "d,Op,b,D,RT,BQ,Q")))]
923 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
932 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
933 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
934 (set_attr "type" "*,*,larl,*,*,*,*")
935 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
937 (define_insn "*cmpsi_ccu"
938 [(set (reg CC_REGNUM)
939 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
940 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
941 "s390_match_ccmode (insn, CCUmode)"
951 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
952 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
953 (set_attr "type" "*,*,larl,*,*,*,*,*")
954 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
956 (define_insn "*cmphi_ccu"
957 [(set (reg CC_REGNUM)
958 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
959 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
960 "s390_match_ccmode (insn, CCUmode)
961 && !register_operand (operands[1], HImode)"
968 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
969 (set_attr "cpu_facility" "*,*,z10,*,*")
970 (set_attr "z10prop" "*,*,z10_super,*,*")])
972 (define_insn "*cmpqi_ccu"
973 [(set (reg CC_REGNUM)
974 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
975 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
976 "s390_match_ccmode (insn, CCUmode)
977 && !register_operand (operands[1], QImode)"
985 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
986 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
989 ; Block compare (CLC) instruction patterns.
992 [(set (reg CC_REGNUM)
993 (compare (match_operand:BLK 0 "memory_operand" "Q")
994 (match_operand:BLK 1 "memory_operand" "Q")))
995 (use (match_operand 2 "const_int_operand" "n"))]
996 "s390_match_ccmode (insn, CCUmode)
997 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
998 "clc\t%O0(%2,%R0),%S1"
999 [(set_attr "op_type" "SS")])
1002 [(set (reg CC_REGNUM)
1003 (compare (match_operand 0 "memory_operand" "")
1004 (match_operand 1 "memory_operand" "")))]
1006 && s390_match_ccmode (insn, CCUmode)
1007 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1008 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1010 [(set (match_dup 0) (match_dup 1))
1011 (use (match_dup 2))])]
1013 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1014 operands[0] = adjust_address (operands[0], BLKmode, 0);
1015 operands[1] = adjust_address (operands[1], BLKmode, 0);
1017 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1018 operands[0], operands[1]);
1019 operands[0] = SET_DEST (PATTERN (curr_insn));
1023 ; (TF|DF|SF|TD|DD|SD) instructions
1025 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1026 (define_insn "*cmp<mode>_ccs_0"
1027 [(set (reg CC_REGNUM)
1028 (compare (match_operand:FP 0 "register_operand" "f")
1029 (match_operand:FP 1 "const0_operand" "")))]
1030 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1031 "lt<xde><bt>r\t%0,%0"
1032 [(set_attr "op_type" "RRE")
1033 (set_attr "type" "fsimp<mode>")])
1035 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1036 (define_insn "*cmp<mode>_ccs"
1037 [(set (reg CC_REGNUM)
1038 (compare (match_operand:FP 0 "register_operand" "f,f")
1039 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1040 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1044 [(set_attr "op_type" "RRE,RXE")
1045 (set_attr "type" "fsimp<mode>")])
1048 ; Compare and Branch instructions
1050 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1051 ; The following instructions do a complementary access of their second
1052 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1053 (define_insn "*cmp_and_br_signed_<mode>"
1055 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1056 [(match_operand:GPR 1 "register_operand" "d,d")
1057 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1058 (label_ref (match_operand 3 "" ""))
1060 (clobber (reg:CC CC_REGNUM))]
1061 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1063 if (get_attr_length (insn) == 6)
1064 return which_alternative ?
1065 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1067 return which_alternative ?
1068 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1070 [(set_attr "op_type" "RIE")
1071 (set_attr "type" "branch")
1072 (set_attr "z10prop" "z10_super_c,z10_super")
1073 (set (attr "length")
1074 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1075 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1076 ; 10 byte for cgr/jg
1078 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1079 ; The following instructions do a complementary access of their second
1080 ; operand (z10 only): clrj, clgrj, clr, clgr
1081 (define_insn "*cmp_and_br_unsigned_<mode>"
1083 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1084 [(match_operand:GPR 1 "register_operand" "d,d")
1085 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1086 (label_ref (match_operand 3 "" ""))
1088 (clobber (reg:CC CC_REGNUM))]
1089 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1091 if (get_attr_length (insn) == 6)
1092 return which_alternative ?
1093 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1095 return which_alternative ?
1096 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1098 [(set_attr "op_type" "RIE")
1099 (set_attr "type" "branch")
1100 (set_attr "z10prop" "z10_super_c,z10_super")
1101 (set (attr "length")
1102 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1103 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1104 ; 10 byte for clgr/jg
1106 ; And now the same two patterns as above but with a negated CC mask.
1108 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1109 ; The following instructions do a complementary access of their second
1110 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1111 (define_insn "*icmp_and_br_signed_<mode>"
1113 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1114 [(match_operand:GPR 1 "register_operand" "d,d")
1115 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1117 (label_ref (match_operand 3 "" ""))))
1118 (clobber (reg:CC CC_REGNUM))]
1119 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1121 if (get_attr_length (insn) == 6)
1122 return which_alternative ?
1123 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1125 return which_alternative ?
1126 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1128 [(set_attr "op_type" "RIE")
1129 (set_attr "type" "branch")
1130 (set_attr "z10prop" "z10_super_c,z10_super")
1131 (set (attr "length")
1132 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1133 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1134 ; 10 byte for cgr/jg
1136 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1137 ; The following instructions do a complementary access of their second
1138 ; operand (z10 only): clrj, clgrj, clr, clgr
1139 (define_insn "*icmp_and_br_unsigned_<mode>"
1141 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1142 [(match_operand:GPR 1 "register_operand" "d,d")
1143 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1145 (label_ref (match_operand 3 "" ""))))
1146 (clobber (reg:CC CC_REGNUM))]
1147 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1149 if (get_attr_length (insn) == 6)
1150 return which_alternative ?
1151 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1153 return which_alternative ?
1154 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1156 [(set_attr "op_type" "RIE")
1157 (set_attr "type" "branch")
1158 (set_attr "z10prop" "z10_super_c,z10_super")
1159 (set (attr "length")
1160 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1161 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1162 ; 10 byte for clgr/jg
1165 ;;- Move instructions.
1169 ; movti instruction pattern(s).
1172 (define_insn "movti"
1173 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1174 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1181 [(set_attr "op_type" "RSY,RSY,*,*")
1182 (set_attr "type" "lm,stm,*,*")])
1185 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1186 (match_operand:TI 1 "general_operand" ""))]
1187 "TARGET_ZARCH && reload_completed
1188 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1189 [(set (match_dup 2) (match_dup 4))
1190 (set (match_dup 3) (match_dup 5))]
1192 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1193 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1194 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1195 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1199 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1200 (match_operand:TI 1 "general_operand" ""))]
1201 "TARGET_ZARCH && reload_completed
1202 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1203 [(set (match_dup 2) (match_dup 4))
1204 (set (match_dup 3) (match_dup 5))]
1206 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1207 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1208 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1209 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1213 [(set (match_operand:TI 0 "register_operand" "")
1214 (match_operand:TI 1 "memory_operand" ""))]
1215 "TARGET_ZARCH && reload_completed
1216 && !s_operand (operands[1], VOIDmode)"
1217 [(set (match_dup 0) (match_dup 1))]
1219 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1220 addr = gen_lowpart (Pmode, addr);
1221 s390_load_address (addr, XEXP (operands[1], 0));
1222 operands[1] = replace_equiv_address (operands[1], addr);
1227 ; Patterns used for secondary reloads
1230 ; z10 provides move instructions accepting larl memory operands.
1231 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1232 ; These patterns are also used for unaligned SI and DI accesses.
1234 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1235 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1236 (match_operand:INTALL 1 "register_operand" "=d")
1237 (match_operand:P 2 "register_operand" "=&a")])]
1240 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1244 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1245 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1246 (match_operand:INTALL 1 "memory_operand" "")
1247 (match_operand:P 2 "register_operand" "=a")])]
1250 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1254 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1255 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1256 (match_operand:FPALL 1 "register_operand" "=d")
1257 (match_operand:P 2 "register_operand" "=&a")])]
1260 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1264 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1265 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1266 (match_operand:FPALL 1 "memory_operand" "")
1267 (match_operand:P 2 "register_operand" "=a")])]
1270 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1274 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1275 [(parallel [(match_operand:P 0 "register_operand" "=d")
1276 (match_operand:P 1 "larl_operand" "")
1277 (match_operand:P 2 "register_operand" "=a")])]
1280 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1284 ; Handles loading a PLUS (load address) expression
1286 (define_expand "reload<mode>_plus"
1287 [(parallel [(match_operand:P 0 "register_operand" "=a")
1288 (match_operand:P 1 "s390_plus_operand" "")
1289 (match_operand:P 2 "register_operand" "=&a")])]
1292 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1296 ; Handles assessing a non-offsetable memory address
1298 (define_expand "reload<mode>_nonoffmem_in"
1299 [(parallel [(match_operand 0 "register_operand" "")
1300 (match_operand 1 "" "")
1301 (match_operand:P 2 "register_operand" "=&a")])]
1304 gcc_assert (MEM_P (operands[1]));
1305 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1306 operands[1] = replace_equiv_address (operands[1], operands[2]);
1307 emit_move_insn (operands[0], operands[1]);
1311 (define_expand "reload<mode>_nonoffmem_out"
1312 [(parallel [(match_operand 0 "" "")
1313 (match_operand 1 "register_operand" "")
1314 (match_operand:P 2 "register_operand" "=&a")])]
1317 gcc_assert (MEM_P (operands[0]));
1318 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1319 operands[0] = replace_equiv_address (operands[0], operands[2]);
1320 emit_move_insn (operands[0], operands[1]);
1324 (define_expand "reload<mode>_PIC_addr"
1325 [(parallel [(match_operand 0 "register_operand" "=d")
1326 (match_operand 1 "larl_operand" "")
1327 (match_operand:P 2 "register_operand" "=a")])]
1330 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1331 emit_move_insn (operands[0], new_rtx);
1335 ; movdi instruction pattern(s).
1338 (define_expand "movdi"
1339 [(set (match_operand:DI 0 "general_operand" "")
1340 (match_operand:DI 1 "general_operand" ""))]
1343 /* Handle symbolic constants. */
1345 && (SYMBOLIC_CONST (operands[1])
1346 || (GET_CODE (operands[1]) == PLUS
1347 && XEXP (operands[1], 0) == pic_offset_table_rtx
1348 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1349 emit_symbolic_move (operands);
1352 (define_insn "*movdi_larl"
1353 [(set (match_operand:DI 0 "register_operand" "=d")
1354 (match_operand:DI 1 "larl_operand" "X"))]
1356 && !FP_REG_P (operands[0])"
1358 [(set_attr "op_type" "RIL")
1359 (set_attr "type" "larl")
1360 (set_attr "z10prop" "z10_super_A1")])
1362 (define_insn "*movdi_64"
1363 [(set (match_operand:DI 0 "nonimmediate_operand"
1364 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1365 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1366 (match_operand:DI 1 "general_operand"
1367 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1368 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1397 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1398 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1399 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1400 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1402 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1403 z10,*,*,*,*,*,longdisp,*,longdisp,
1405 (set_attr "z10prop" "z10_fwd_A1,
1434 [(set (match_operand:DI 0 "register_operand" "")
1435 (match_operand:DI 1 "register_operand" ""))]
1436 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1437 [(set (match_dup 2) (match_dup 3))
1438 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1439 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1440 "operands[2] = gen_lowpart (SImode, operands[0]);
1441 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1444 [(set (match_operand:DI 0 "register_operand" "")
1445 (match_operand:DI 1 "register_operand" ""))]
1446 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1447 && dead_or_set_p (insn, operands[1])"
1448 [(set (match_dup 3) (match_dup 2))
1449 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1450 (set (match_dup 4) (match_dup 2))]
1451 "operands[2] = gen_lowpart (SImode, operands[1]);
1452 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1455 [(set (match_operand:DI 0 "register_operand" "")
1456 (match_operand:DI 1 "register_operand" ""))]
1457 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1458 && !dead_or_set_p (insn, operands[1])"
1459 [(set (match_dup 3) (match_dup 2))
1460 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1461 (set (match_dup 4) (match_dup 2))
1462 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1463 "operands[2] = gen_lowpart (SImode, operands[1]);
1464 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1466 (define_insn "*movdi_31"
1467 [(set (match_operand:DI 0 "nonimmediate_operand"
1468 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1469 (match_operand:DI 1 "general_operand"
1470 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1485 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1486 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1487 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1489 ; For a load from a symbol ref we can use one of the target registers
1490 ; together with larl to load the address.
1492 [(set (match_operand:DI 0 "register_operand" "")
1493 (match_operand:DI 1 "memory_operand" ""))]
1494 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1495 && larl_operand (XEXP (operands[1], 0), SImode)"
1496 [(set (match_dup 2) (match_dup 3))
1497 (set (match_dup 0) (match_dup 1))]
1499 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1500 operands[3] = XEXP (operands[1], 0);
1501 operands[1] = replace_equiv_address (operands[1], operands[2]);
1505 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1506 (match_operand:DI 1 "general_operand" ""))]
1507 "!TARGET_ZARCH && reload_completed
1508 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1509 [(set (match_dup 2) (match_dup 4))
1510 (set (match_dup 3) (match_dup 5))]
1512 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1513 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1514 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1515 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1519 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1520 (match_operand:DI 1 "general_operand" ""))]
1521 "!TARGET_ZARCH && reload_completed
1522 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1523 [(set (match_dup 2) (match_dup 4))
1524 (set (match_dup 3) (match_dup 5))]
1526 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1527 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1528 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1529 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1533 [(set (match_operand:DI 0 "register_operand" "")
1534 (match_operand:DI 1 "memory_operand" ""))]
1535 "!TARGET_ZARCH && reload_completed
1536 && !FP_REG_P (operands[0])
1537 && !s_operand (operands[1], VOIDmode)"
1538 [(set (match_dup 0) (match_dup 1))]
1540 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1541 s390_load_address (addr, XEXP (operands[1], 0));
1542 operands[1] = replace_equiv_address (operands[1], addr);
1546 [(set (match_operand:DI 0 "register_operand" "")
1547 (mem:DI (match_operand 1 "address_operand" "")))]
1549 && !FP_REG_P (operands[0])
1550 && GET_CODE (operands[1]) == SYMBOL_REF
1551 && CONSTANT_POOL_ADDRESS_P (operands[1])
1552 && get_pool_mode (operands[1]) == DImode
1553 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1554 [(set (match_dup 0) (match_dup 2))]
1555 "operands[2] = get_pool_constant (operands[1]);")
1557 (define_insn "*la_64"
1558 [(set (match_operand:DI 0 "register_operand" "=d,d")
1559 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1564 [(set_attr "op_type" "RX,RXY")
1565 (set_attr "type" "la")
1566 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1570 [(set (match_operand:DI 0 "register_operand" "")
1571 (match_operand:QI 1 "address_operand" ""))
1572 (clobber (reg:CC CC_REGNUM))])]
1574 && preferred_la_operand_p (operands[1], const0_rtx)"
1575 [(set (match_dup 0) (match_dup 1))]
1579 [(set (match_operand:DI 0 "register_operand" "")
1580 (match_operand:DI 1 "register_operand" ""))
1583 (plus:DI (match_dup 0)
1584 (match_operand:DI 2 "nonmemory_operand" "")))
1585 (clobber (reg:CC CC_REGNUM))])]
1587 && !reg_overlap_mentioned_p (operands[0], operands[2])
1588 && preferred_la_operand_p (operands[1], operands[2])"
1589 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1593 ; movsi instruction pattern(s).
1596 (define_expand "movsi"
1597 [(set (match_operand:SI 0 "general_operand" "")
1598 (match_operand:SI 1 "general_operand" ""))]
1601 /* Handle symbolic constants. */
1603 && (SYMBOLIC_CONST (operands[1])
1604 || (GET_CODE (operands[1]) == PLUS
1605 && XEXP (operands[1], 0) == pic_offset_table_rtx
1606 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1607 emit_symbolic_move (operands);
1610 (define_insn "*movsi_larl"
1611 [(set (match_operand:SI 0 "register_operand" "=d")
1612 (match_operand:SI 1 "larl_operand" "X"))]
1613 "!TARGET_64BIT && TARGET_CPU_ZARCH
1614 && !FP_REG_P (operands[0])"
1616 [(set_attr "op_type" "RIL")
1617 (set_attr "type" "larl")
1618 (set_attr "z10prop" "z10_fwd_A1")])
1620 (define_insn "*movsi_zarch"
1621 [(set (match_operand:SI 0 "nonimmediate_operand"
1622 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1623 (match_operand:SI 1 "general_operand"
1624 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1649 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1650 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1651 (set_attr "type" "*,
1673 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1674 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1675 (set_attr "z10prop" "z10_fwd_A1,
1698 (define_insn "*movsi_esa"
1699 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1700 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1714 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1715 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1716 (set_attr "z10prop" "z10_fwd_A1,
1730 [(set (match_operand:SI 0 "register_operand" "")
1731 (mem:SI (match_operand 1 "address_operand" "")))]
1732 "!FP_REG_P (operands[0])
1733 && GET_CODE (operands[1]) == SYMBOL_REF
1734 && CONSTANT_POOL_ADDRESS_P (operands[1])
1735 && get_pool_mode (operands[1]) == SImode
1736 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1737 [(set (match_dup 0) (match_dup 2))]
1738 "operands[2] = get_pool_constant (operands[1]);")
1740 (define_insn "*la_31"
1741 [(set (match_operand:SI 0 "register_operand" "=d,d")
1742 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1743 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1747 [(set_attr "op_type" "RX,RXY")
1748 (set_attr "type" "la")
1749 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1753 [(set (match_operand:SI 0 "register_operand" "")
1754 (match_operand:QI 1 "address_operand" ""))
1755 (clobber (reg:CC CC_REGNUM))])]
1757 && preferred_la_operand_p (operands[1], const0_rtx)"
1758 [(set (match_dup 0) (match_dup 1))]
1762 [(set (match_operand:SI 0 "register_operand" "")
1763 (match_operand:SI 1 "register_operand" ""))
1766 (plus:SI (match_dup 0)
1767 (match_operand:SI 2 "nonmemory_operand" "")))
1768 (clobber (reg:CC CC_REGNUM))])]
1770 && !reg_overlap_mentioned_p (operands[0], operands[2])
1771 && preferred_la_operand_p (operands[1], operands[2])"
1772 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1775 (define_insn "*la_31_and"
1776 [(set (match_operand:SI 0 "register_operand" "=d,d")
1777 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1778 (const_int 2147483647)))]
1783 [(set_attr "op_type" "RX,RXY")
1784 (set_attr "type" "la")
1785 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1787 (define_insn_and_split "*la_31_and_cc"
1788 [(set (match_operand:SI 0 "register_operand" "=d")
1789 (and:SI (match_operand:QI 1 "address_operand" "p")
1790 (const_int 2147483647)))
1791 (clobber (reg:CC CC_REGNUM))]
1794 "&& reload_completed"
1796 (and:SI (match_dup 1) (const_int 2147483647)))]
1798 [(set_attr "op_type" "RX")
1799 (set_attr "type" "la")])
1801 (define_insn "force_la_31"
1802 [(set (match_operand:SI 0 "register_operand" "=d,d")
1803 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1804 (use (const_int 0))]
1809 [(set_attr "op_type" "RX")
1810 (set_attr "type" "la")
1811 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1814 ; movhi instruction pattern(s).
1817 (define_expand "movhi"
1818 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1819 (match_operand:HI 1 "general_operand" ""))]
1822 /* Make it explicit that loading a register from memory
1823 always sign-extends (at least) to SImode. */
1824 if (optimize && can_create_pseudo_p ()
1825 && register_operand (operands[0], VOIDmode)
1826 && GET_CODE (operands[1]) == MEM)
1828 rtx tmp = gen_reg_rtx (SImode);
1829 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1830 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1831 operands[1] = gen_lowpart (HImode, tmp);
1835 (define_insn "*movhi"
1836 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1837 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1849 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1850 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1851 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1852 (set_attr "z10prop" "z10_fr_E1,
1863 [(set (match_operand:HI 0 "register_operand" "")
1864 (mem:HI (match_operand 1 "address_operand" "")))]
1865 "GET_CODE (operands[1]) == SYMBOL_REF
1866 && CONSTANT_POOL_ADDRESS_P (operands[1])
1867 && get_pool_mode (operands[1]) == HImode
1868 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1869 [(set (match_dup 0) (match_dup 2))]
1870 "operands[2] = get_pool_constant (operands[1]);")
1873 ; movqi instruction pattern(s).
1876 (define_expand "movqi"
1877 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1878 (match_operand:QI 1 "general_operand" ""))]
1881 /* On z/Architecture, zero-extending from memory to register
1882 is just as fast as a QImode load. */
1883 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1884 && register_operand (operands[0], VOIDmode)
1885 && GET_CODE (operands[1]) == MEM)
1887 rtx tmp = gen_reg_rtx (DImode);
1888 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1889 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1890 operands[1] = gen_lowpart (QImode, tmp);
1894 (define_insn "*movqi"
1895 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1896 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1908 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1909 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1910 (set_attr "z10prop" "z10_fr_E1,
1921 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1922 (mem:QI (match_operand 1 "address_operand" "")))]
1923 "GET_CODE (operands[1]) == SYMBOL_REF
1924 && CONSTANT_POOL_ADDRESS_P (operands[1])
1925 && get_pool_mode (operands[1]) == QImode
1926 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1927 [(set (match_dup 0) (match_dup 2))]
1928 "operands[2] = get_pool_constant (operands[1]);")
1931 ; movstrictqi instruction pattern(s).
1934 (define_insn "*movstrictqi"
1935 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1936 (match_operand:QI 1 "memory_operand" "R,T"))]
1941 [(set_attr "op_type" "RX,RXY")
1942 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1945 ; movstricthi instruction pattern(s).
1948 (define_insn "*movstricthi"
1949 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1950 (match_operand:HI 1 "memory_operand" "Q,S"))
1951 (clobber (reg:CC CC_REGNUM))]
1956 [(set_attr "op_type" "RS,RSY")
1957 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1960 ; movstrictsi instruction pattern(s).
1963 (define_insn "movstrictsi"
1964 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1965 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1972 [(set_attr "op_type" "RR,RX,RXY,RRE")
1973 (set_attr "type" "lr,load,load,*")
1974 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1977 ; mov(tf|td) instruction pattern(s).
1980 (define_expand "mov<mode>"
1981 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1982 (match_operand:TD_TF 1 "general_operand" ""))]
1986 (define_insn "*mov<mode>_64"
1987 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1988 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1999 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2000 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2001 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2003 (define_insn "*mov<mode>_31"
2004 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2005 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2012 [(set_attr "op_type" "RRE,RRE,*,*")
2013 (set_attr "type" "fsimptf,fsimptf,*,*")
2014 (set_attr "cpu_facility" "z196,*,*,*")])
2016 ; TFmode in GPRs splitters
2019 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2020 (match_operand:TD_TF 1 "general_operand" ""))]
2021 "TARGET_ZARCH && reload_completed
2022 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2023 [(set (match_dup 2) (match_dup 4))
2024 (set (match_dup 3) (match_dup 5))]
2026 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2027 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2028 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2029 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2033 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2034 (match_operand:TD_TF 1 "general_operand" ""))]
2035 "TARGET_ZARCH && reload_completed
2036 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2037 [(set (match_dup 2) (match_dup 4))
2038 (set (match_dup 3) (match_dup 5))]
2040 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2041 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2042 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2043 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2047 [(set (match_operand:TD_TF 0 "register_operand" "")
2048 (match_operand:TD_TF 1 "memory_operand" ""))]
2049 "TARGET_ZARCH && reload_completed
2050 && !FP_REG_P (operands[0])
2051 && !s_operand (operands[1], VOIDmode)"
2052 [(set (match_dup 0) (match_dup 1))]
2054 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2055 addr = gen_lowpart (Pmode, addr);
2056 s390_load_address (addr, XEXP (operands[1], 0));
2057 operands[1] = replace_equiv_address (operands[1], addr);
2060 ; TFmode in BFPs splitters
2063 [(set (match_operand:TD_TF 0 "register_operand" "")
2064 (match_operand:TD_TF 1 "memory_operand" ""))]
2065 "reload_completed && offsettable_memref_p (operands[1])
2066 && FP_REG_P (operands[0])"
2067 [(set (match_dup 2) (match_dup 4))
2068 (set (match_dup 3) (match_dup 5))]
2070 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2072 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2074 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2075 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2079 [(set (match_operand:TD_TF 0 "memory_operand" "")
2080 (match_operand:TD_TF 1 "register_operand" ""))]
2081 "reload_completed && offsettable_memref_p (operands[0])
2082 && FP_REG_P (operands[1])"
2083 [(set (match_dup 2) (match_dup 4))
2084 (set (match_dup 3) (match_dup 5))]
2086 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2087 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2088 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2090 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2095 ; mov(df|dd) instruction pattern(s).
2098 (define_expand "mov<mode>"
2099 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2100 (match_operand:DD_DF 1 "general_operand" ""))]
2104 (define_insn "*mov<mode>_64dfp"
2105 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2106 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2107 (match_operand:DD_DF 1 "general_operand"
2108 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2123 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2124 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2125 fstoredf,fstoredf,*,lr,load,store")
2126 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2127 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2129 (define_insn "*mov<mode>_64"
2130 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2131 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2144 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2145 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2146 fstore<mode>,fstore<mode>,*,lr,load,store")
2147 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2148 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2150 (define_insn "*mov<mode>_31"
2151 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2152 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2153 (match_operand:DD_DF 1 "general_operand"
2154 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2169 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2170 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2171 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2172 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2175 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2176 (match_operand:DD_DF 1 "general_operand" ""))]
2177 "!TARGET_ZARCH && reload_completed
2178 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2179 [(set (match_dup 2) (match_dup 4))
2180 (set (match_dup 3) (match_dup 5))]
2182 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2183 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2184 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2185 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2189 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2190 (match_operand:DD_DF 1 "general_operand" ""))]
2191 "!TARGET_ZARCH && reload_completed
2192 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2193 [(set (match_dup 2) (match_dup 4))
2194 (set (match_dup 3) (match_dup 5))]
2196 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2197 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2198 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2199 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2203 [(set (match_operand:DD_DF 0 "register_operand" "")
2204 (match_operand:DD_DF 1 "memory_operand" ""))]
2205 "!TARGET_ZARCH && reload_completed
2206 && !FP_REG_P (operands[0])
2207 && !s_operand (operands[1], VOIDmode)"
2208 [(set (match_dup 0) (match_dup 1))]
2210 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2211 s390_load_address (addr, XEXP (operands[1], 0));
2212 operands[1] = replace_equiv_address (operands[1], addr);
2216 ; mov(sf|sd) instruction pattern(s).
2219 (define_insn "mov<mode>"
2220 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2221 "=f,f,f,f,R,T,d,d,d,d,R,T")
2222 (match_operand:SD_SF 1 "general_operand"
2223 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2238 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2239 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2240 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2241 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2242 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2245 ; movcc instruction pattern
2248 (define_insn "movcc"
2249 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2250 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2260 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2261 (set_attr "type" "lr,*,*,store,store,load,load")
2262 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2263 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2266 ; Block move (MVC) patterns.
2270 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2271 (match_operand:BLK 1 "memory_operand" "Q"))
2272 (use (match_operand 2 "const_int_operand" "n"))]
2273 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2274 "mvc\t%O0(%2,%R0),%S1"
2275 [(set_attr "op_type" "SS")])
2277 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2278 ; order to have it implemented with mvc.
2281 [(set (match_operand:QI 0 "memory_operand" "")
2282 (match_operand:QI 1 "memory_operand" ""))]
2285 [(set (match_dup 0) (match_dup 1))
2286 (use (const_int 1))])]
2288 operands[0] = adjust_address (operands[0], BLKmode, 0);
2289 operands[1] = adjust_address (operands[1], BLKmode, 0);
2295 [(set (match_operand:BLK 0 "memory_operand" "")
2296 (match_operand:BLK 1 "memory_operand" ""))
2297 (use (match_operand 2 "const_int_operand" ""))])
2299 [(set (match_operand:BLK 3 "memory_operand" "")
2300 (match_operand:BLK 4 "memory_operand" ""))
2301 (use (match_operand 5 "const_int_operand" ""))])]
2302 "s390_offset_p (operands[0], operands[3], operands[2])
2303 && s390_offset_p (operands[1], operands[4], operands[2])
2304 && !s390_overlap_p (operands[0], operands[1],
2305 INTVAL (operands[2]) + INTVAL (operands[5]))
2306 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2308 [(set (match_dup 6) (match_dup 7))
2309 (use (match_dup 8))])]
2310 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2311 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2312 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2316 ; load_multiple pattern(s).
2318 ; ??? Due to reload problems with replacing registers inside match_parallel
2319 ; we currently support load_multiple/store_multiple only after reload.
2322 (define_expand "load_multiple"
2323 [(match_par_dup 3 [(set (match_operand 0 "" "")
2324 (match_operand 1 "" ""))
2325 (use (match_operand 2 "" ""))])]
2328 enum machine_mode mode;
2334 /* Support only loading a constant number of fixed-point registers from
2335 memory and only bother with this if more than two */
2336 if (GET_CODE (operands[2]) != CONST_INT
2337 || INTVAL (operands[2]) < 2
2338 || INTVAL (operands[2]) > 16
2339 || GET_CODE (operands[1]) != MEM
2340 || GET_CODE (operands[0]) != REG
2341 || REGNO (operands[0]) >= 16)
2344 count = INTVAL (operands[2]);
2345 regno = REGNO (operands[0]);
2346 mode = GET_MODE (operands[0]);
2347 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2350 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2351 if (!can_create_pseudo_p ())
2353 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2355 from = XEXP (operands[1], 0);
2358 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2359 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2360 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2362 from = XEXP (XEXP (operands[1], 0), 0);
2363 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2370 from = force_reg (Pmode, XEXP (operands[1], 0));
2374 for (i = 0; i < count; i++)
2375 XVECEXP (operands[3], 0, i)
2376 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2377 change_address (operands[1], mode,
2378 plus_constant (Pmode, from,
2379 off + i * GET_MODE_SIZE (mode))));
2382 (define_insn "*load_multiple_di"
2383 [(match_parallel 0 "load_multiple_operation"
2384 [(set (match_operand:DI 1 "register_operand" "=r")
2385 (match_operand:DI 2 "s_operand" "QS"))])]
2386 "reload_completed && TARGET_ZARCH"
2388 int words = XVECLEN (operands[0], 0);
2389 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2390 return "lmg\t%1,%0,%S2";
2392 [(set_attr "op_type" "RSY")
2393 (set_attr "type" "lm")])
2395 (define_insn "*load_multiple_si"
2396 [(match_parallel 0 "load_multiple_operation"
2397 [(set (match_operand:SI 1 "register_operand" "=r,r")
2398 (match_operand:SI 2 "s_operand" "Q,S"))])]
2401 int words = XVECLEN (operands[0], 0);
2402 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2403 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2405 [(set_attr "op_type" "RS,RSY")
2406 (set_attr "type" "lm")])
2409 ; store multiple pattern(s).
2412 (define_expand "store_multiple"
2413 [(match_par_dup 3 [(set (match_operand 0 "" "")
2414 (match_operand 1 "" ""))
2415 (use (match_operand 2 "" ""))])]
2418 enum machine_mode mode;
2424 /* Support only storing a constant number of fixed-point registers to
2425 memory and only bother with this if more than two. */
2426 if (GET_CODE (operands[2]) != CONST_INT
2427 || INTVAL (operands[2]) < 2
2428 || INTVAL (operands[2]) > 16
2429 || GET_CODE (operands[0]) != MEM
2430 || GET_CODE (operands[1]) != REG
2431 || REGNO (operands[1]) >= 16)
2434 count = INTVAL (operands[2]);
2435 regno = REGNO (operands[1]);
2436 mode = GET_MODE (operands[1]);
2437 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2440 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2442 if (!can_create_pseudo_p ())
2444 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2446 to = XEXP (operands[0], 0);
2449 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2450 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2451 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2453 to = XEXP (XEXP (operands[0], 0), 0);
2454 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2461 to = force_reg (Pmode, XEXP (operands[0], 0));
2465 for (i = 0; i < count; i++)
2466 XVECEXP (operands[3], 0, i)
2467 = gen_rtx_SET (VOIDmode,
2468 change_address (operands[0], mode,
2469 plus_constant (Pmode, to,
2470 off + i * GET_MODE_SIZE (mode))),
2471 gen_rtx_REG (mode, regno + i));
2474 (define_insn "*store_multiple_di"
2475 [(match_parallel 0 "store_multiple_operation"
2476 [(set (match_operand:DI 1 "s_operand" "=QS")
2477 (match_operand:DI 2 "register_operand" "r"))])]
2478 "reload_completed && TARGET_ZARCH"
2480 int words = XVECLEN (operands[0], 0);
2481 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2482 return "stmg\t%2,%0,%S1";
2484 [(set_attr "op_type" "RSY")
2485 (set_attr "type" "stm")])
2488 (define_insn "*store_multiple_si"
2489 [(match_parallel 0 "store_multiple_operation"
2490 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2491 (match_operand:SI 2 "register_operand" "r,r"))])]
2494 int words = XVECLEN (operands[0], 0);
2495 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2496 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2498 [(set_attr "op_type" "RS,RSY")
2499 (set_attr "type" "stm")])
2502 ;; String instructions.
2505 (define_insn "*execute_rl"
2506 [(match_parallel 0 "execute_operation"
2507 [(unspec [(match_operand 1 "register_operand" "a")
2508 (match_operand 2 "" "")
2509 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2510 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2511 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2513 [(set_attr "op_type" "RIL")
2514 (set_attr "type" "cs")])
2516 (define_insn "*execute"
2517 [(match_parallel 0 "execute_operation"
2518 [(unspec [(match_operand 1 "register_operand" "a")
2519 (match_operand:BLK 2 "memory_operand" "R")
2520 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2521 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2522 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2524 [(set_attr "op_type" "RX")
2525 (set_attr "type" "cs")])
2529 ; strlenM instruction pattern(s).
2532 (define_expand "strlen<mode>"
2533 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2536 (unspec:P [(const_int 0)
2537 (match_operand:BLK 1 "memory_operand" "")
2539 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2540 (clobber (scratch:P))
2541 (clobber (reg:CC CC_REGNUM))])
2543 [(set (match_operand:P 0 "register_operand" "")
2544 (minus:P (match_dup 4) (match_dup 5)))
2545 (clobber (reg:CC CC_REGNUM))])]
2548 operands[4] = gen_reg_rtx (Pmode);
2549 operands[5] = gen_reg_rtx (Pmode);
2550 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2551 operands[1] = replace_equiv_address (operands[1], operands[5]);
2554 (define_insn "*strlen<mode>"
2555 [(set (match_operand:P 0 "register_operand" "=a")
2556 (unspec:P [(match_operand:P 2 "general_operand" "0")
2557 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2559 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2560 (clobber (match_scratch:P 1 "=a"))
2561 (clobber (reg:CC CC_REGNUM))]
2563 "srst\t%0,%1\;jo\t.-4"
2564 [(set_attr "length" "8")
2565 (set_attr "type" "vs")])
2568 ; cmpstrM instruction pattern(s).
2571 (define_expand "cmpstrsi"
2572 [(set (reg:SI 0) (const_int 0))
2574 [(clobber (match_operand 3 "" ""))
2575 (clobber (match_dup 4))
2576 (set (reg:CCU CC_REGNUM)
2577 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2578 (match_operand:BLK 2 "memory_operand" "")))
2581 [(set (match_operand:SI 0 "register_operand" "=d")
2582 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2583 (clobber (reg:CC CC_REGNUM))])]
2586 /* As the result of CMPINT is inverted compared to what we need,
2587 we have to swap the operands. */
2588 rtx op1 = operands[2];
2589 rtx op2 = operands[1];
2590 rtx addr1 = gen_reg_rtx (Pmode);
2591 rtx addr2 = gen_reg_rtx (Pmode);
2593 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2594 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2595 operands[1] = replace_equiv_address_nv (op1, addr1);
2596 operands[2] = replace_equiv_address_nv (op2, addr2);
2597 operands[3] = addr1;
2598 operands[4] = addr2;
2601 (define_insn "*cmpstr<mode>"
2602 [(clobber (match_operand:P 0 "register_operand" "=d"))
2603 (clobber (match_operand:P 1 "register_operand" "=d"))
2604 (set (reg:CCU CC_REGNUM)
2605 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2606 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2609 "clst\t%0,%1\;jo\t.-4"
2610 [(set_attr "length" "8")
2611 (set_attr "type" "vs")])
2614 ; movstr instruction pattern.
2617 (define_expand "movstr"
2618 [(set (reg:SI 0) (const_int 0))
2620 [(clobber (match_dup 3))
2621 (set (match_operand:BLK 1 "memory_operand" "")
2622 (match_operand:BLK 2 "memory_operand" ""))
2623 (set (match_operand 0 "register_operand" "")
2624 (unspec [(match_dup 1)
2626 (reg:SI 0)] UNSPEC_MVST))
2627 (clobber (reg:CC CC_REGNUM))])]
2630 rtx addr1 = gen_reg_rtx (Pmode);
2631 rtx addr2 = gen_reg_rtx (Pmode);
2633 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2634 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2635 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2636 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2637 operands[3] = addr2;
2640 (define_insn "*movstr"
2641 [(clobber (match_operand:P 2 "register_operand" "=d"))
2642 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2643 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2644 (set (match_operand:P 0 "register_operand" "=d")
2645 (unspec [(mem:BLK (match_dup 1))
2646 (mem:BLK (match_dup 3))
2647 (reg:SI 0)] UNSPEC_MVST))
2648 (clobber (reg:CC CC_REGNUM))]
2650 "mvst\t%1,%2\;jo\t.-4"
2651 [(set_attr "length" "8")
2652 (set_attr "type" "vs")])
2656 ; movmemM instruction pattern(s).
2659 (define_expand "movmem<mode>"
2660 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2661 (match_operand:BLK 1 "memory_operand" "")) ; source
2662 (use (match_operand:GPR 2 "general_operand" "")) ; count
2663 (match_operand 3 "" "")]
2666 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2672 ; Move a block that is up to 256 bytes in length.
2673 ; The block length is taken as (operands[2] % 256) + 1.
2675 (define_expand "movmem_short"
2677 [(set (match_operand:BLK 0 "memory_operand" "")
2678 (match_operand:BLK 1 "memory_operand" ""))
2679 (use (match_operand 2 "nonmemory_operand" ""))
2680 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2681 (clobber (match_dup 3))])]
2683 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2685 (define_insn "*movmem_short"
2686 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2687 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2688 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2689 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2690 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2691 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2693 [(set_attr "type" "cs")
2694 (set_attr "cpu_facility" "*,*,z10,*")])
2697 [(set (match_operand:BLK 0 "memory_operand" "")
2698 (match_operand:BLK 1 "memory_operand" ""))
2699 (use (match_operand 2 "const_int_operand" ""))
2700 (use (match_operand 3 "immediate_operand" ""))
2701 (clobber (scratch))]
2704 [(set (match_dup 0) (match_dup 1))
2705 (use (match_dup 2))])]
2706 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2709 [(set (match_operand:BLK 0 "memory_operand" "")
2710 (match_operand:BLK 1 "memory_operand" ""))
2711 (use (match_operand 2 "register_operand" ""))
2712 (use (match_operand 3 "memory_operand" ""))
2713 (clobber (scratch))]
2716 [(unspec [(match_dup 2) (match_dup 3)
2717 (const_int 0)] UNSPEC_EXECUTE)
2718 (set (match_dup 0) (match_dup 1))
2719 (use (const_int 1))])]
2723 [(set (match_operand:BLK 0 "memory_operand" "")
2724 (match_operand:BLK 1 "memory_operand" ""))
2725 (use (match_operand 2 "register_operand" ""))
2726 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2727 (clobber (scratch))]
2728 "TARGET_Z10 && reload_completed"
2730 [(unspec [(match_dup 2) (const_int 0)
2731 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2732 (set (match_dup 0) (match_dup 1))
2733 (use (const_int 1))])]
2734 "operands[3] = gen_label_rtx ();")
2737 [(set (match_operand:BLK 0 "memory_operand" "")
2738 (match_operand:BLK 1 "memory_operand" ""))
2739 (use (match_operand 2 "register_operand" ""))
2740 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2741 (clobber (match_operand 3 "register_operand" ""))]
2742 "reload_completed && TARGET_CPU_ZARCH"
2743 [(set (match_dup 3) (label_ref (match_dup 4)))
2745 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2746 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2747 (set (match_dup 0) (match_dup 1))
2748 (use (const_int 1))])]
2749 "operands[4] = gen_label_rtx ();")
2751 ; Move a block of arbitrary length.
2753 (define_expand "movmem_long"
2755 [(clobber (match_dup 2))
2756 (clobber (match_dup 3))
2757 (set (match_operand:BLK 0 "memory_operand" "")
2758 (match_operand:BLK 1 "memory_operand" ""))
2759 (use (match_operand 2 "general_operand" ""))
2761 (clobber (reg:CC CC_REGNUM))])]
2764 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2765 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2766 rtx reg0 = gen_reg_rtx (dreg_mode);
2767 rtx reg1 = gen_reg_rtx (dreg_mode);
2768 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2769 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2770 rtx len0 = gen_lowpart (Pmode, reg0);
2771 rtx len1 = gen_lowpart (Pmode, reg1);
2773 emit_clobber (reg0);
2774 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2775 emit_move_insn (len0, operands[2]);
2777 emit_clobber (reg1);
2778 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2779 emit_move_insn (len1, operands[2]);
2781 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2782 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2787 (define_insn "*movmem_long"
2788 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2789 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2790 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2791 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2794 (clobber (reg:CC CC_REGNUM))]
2795 "TARGET_64BIT || !TARGET_ZARCH"
2796 "mvcle\t%0,%1,0\;jo\t.-4"
2797 [(set_attr "length" "8")
2798 (set_attr "type" "vs")])
2800 (define_insn "*movmem_long_31z"
2801 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2802 (clobber (match_operand:TI 1 "register_operand" "=d"))
2803 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2804 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2807 (clobber (reg:CC CC_REGNUM))]
2808 "!TARGET_64BIT && TARGET_ZARCH"
2809 "mvcle\t%0,%1,0\;jo\t.-4"
2810 [(set_attr "length" "8")
2811 (set_attr "type" "vs")])
2818 (define_expand "signbit<mode>2"
2819 [(set (reg:CCZ CC_REGNUM)
2820 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2823 (set (match_operand:SI 0 "register_operand" "=d")
2824 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2827 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2830 (define_expand "isinf<mode>2"
2831 [(set (reg:CCZ CC_REGNUM)
2832 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2835 (set (match_operand:SI 0 "register_operand" "=d")
2836 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2839 operands[2] = GEN_INT (S390_TDC_INFINITY);
2842 ; This insn is used to generate all variants of the Test Data Class
2843 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2844 ; is the register to be tested and the second one is the bit mask
2845 ; specifying the required test(s).
2847 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2848 (define_insn "*TDC_insn_<mode>"
2849 [(set (reg:CCZ CC_REGNUM)
2850 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2851 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2853 "t<_d>c<xde><bt>\t%0,%1"
2854 [(set_attr "op_type" "RXE")
2855 (set_attr "type" "fsimp<mode>")])
2857 (define_insn_and_split "*ccz_to_int"
2858 [(set (match_operand:SI 0 "register_operand" "=d")
2859 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2860 UNSPEC_CCZ_TO_INT))]
2864 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2868 ; setmemM instruction pattern(s).
2871 (define_expand "setmem<mode>"
2872 [(set (match_operand:BLK 0 "memory_operand" "")
2873 (match_operand:QI 2 "general_operand" ""))
2874 (use (match_operand:GPR 1 "general_operand" ""))
2875 (match_operand 3 "" "")]
2877 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2879 ; Clear a block that is up to 256 bytes in length.
2880 ; The block length is taken as (operands[1] % 256) + 1.
2882 (define_expand "clrmem_short"
2884 [(set (match_operand:BLK 0 "memory_operand" "")
2886 (use (match_operand 1 "nonmemory_operand" ""))
2887 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2888 (clobber (match_dup 2))
2889 (clobber (reg:CC CC_REGNUM))])]
2891 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2893 (define_insn "*clrmem_short"
2894 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2896 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2897 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2898 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2899 (clobber (reg:CC CC_REGNUM))]
2900 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2902 [(set_attr "type" "cs")
2903 (set_attr "cpu_facility" "*,*,z10,*")])
2906 [(set (match_operand:BLK 0 "memory_operand" "")
2908 (use (match_operand 1 "const_int_operand" ""))
2909 (use (match_operand 2 "immediate_operand" ""))
2911 (clobber (reg:CC CC_REGNUM))]
2914 [(set (match_dup 0) (const_int 0))
2916 (clobber (reg:CC CC_REGNUM))])]
2917 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2920 [(set (match_operand:BLK 0 "memory_operand" "")
2922 (use (match_operand 1 "register_operand" ""))
2923 (use (match_operand 2 "memory_operand" ""))
2925 (clobber (reg:CC CC_REGNUM))]
2928 [(unspec [(match_dup 1) (match_dup 2)
2929 (const_int 0)] UNSPEC_EXECUTE)
2930 (set (match_dup 0) (const_int 0))
2932 (clobber (reg:CC CC_REGNUM))])]
2936 [(set (match_operand:BLK 0 "memory_operand" "")
2938 (use (match_operand 1 "register_operand" ""))
2939 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2941 (clobber (reg:CC CC_REGNUM))]
2942 "TARGET_Z10 && reload_completed"
2944 [(unspec [(match_dup 1) (const_int 0)
2945 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2946 (set (match_dup 0) (const_int 0))
2948 (clobber (reg:CC CC_REGNUM))])]
2949 "operands[3] = gen_label_rtx ();")
2952 [(set (match_operand:BLK 0 "memory_operand" "")
2954 (use (match_operand 1 "register_operand" ""))
2955 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2956 (clobber (match_operand 2 "register_operand" ""))
2957 (clobber (reg:CC CC_REGNUM))]
2958 "reload_completed && TARGET_CPU_ZARCH"
2959 [(set (match_dup 2) (label_ref (match_dup 3)))
2961 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2962 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2963 (set (match_dup 0) (const_int 0))
2965 (clobber (reg:CC CC_REGNUM))])]
2966 "operands[3] = gen_label_rtx ();")
2968 ; Initialize a block of arbitrary length with (operands[2] % 256).
2970 (define_expand "setmem_long"
2972 [(clobber (match_dup 1))
2973 (set (match_operand:BLK 0 "memory_operand" "")
2974 (match_operand 2 "shift_count_or_setmem_operand" ""))
2975 (use (match_operand 1 "general_operand" ""))
2977 (clobber (reg:CC CC_REGNUM))])]
2980 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2981 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2982 rtx reg0 = gen_reg_rtx (dreg_mode);
2983 rtx reg1 = gen_reg_rtx (dreg_mode);
2984 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2985 rtx len0 = gen_lowpart (Pmode, reg0);
2987 emit_clobber (reg0);
2988 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2989 emit_move_insn (len0, operands[1]);
2991 emit_move_insn (reg1, const0_rtx);
2993 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2998 (define_insn "*setmem_long"
2999 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3000 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3001 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3003 (use (match_operand:<DBL> 1 "register_operand" "d"))
3004 (clobber (reg:CC CC_REGNUM))]
3005 "TARGET_64BIT || !TARGET_ZARCH"
3006 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3007 [(set_attr "length" "8")
3008 (set_attr "type" "vs")])
3010 (define_insn "*setmem_long_and"
3011 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3012 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3013 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3014 (match_operand 4 "const_int_operand" "n")))
3016 (use (match_operand:<DBL> 1 "register_operand" "d"))
3017 (clobber (reg:CC CC_REGNUM))]
3018 "(TARGET_64BIT || !TARGET_ZARCH) &&
3019 (INTVAL (operands[4]) & 255) == 255"
3020 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3021 [(set_attr "length" "8")
3022 (set_attr "type" "vs")])
3024 (define_insn "*setmem_long_31z"
3025 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3026 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3027 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3029 (use (match_operand:TI 1 "register_operand" "d"))
3030 (clobber (reg:CC CC_REGNUM))]
3031 "!TARGET_64BIT && TARGET_ZARCH"
3032 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3033 [(set_attr "length" "8")
3034 (set_attr "type" "vs")])
3037 ; cmpmemM instruction pattern(s).
3040 (define_expand "cmpmemsi"
3041 [(set (match_operand:SI 0 "register_operand" "")
3042 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3043 (match_operand:BLK 2 "memory_operand" "") ) )
3044 (use (match_operand:SI 3 "general_operand" ""))
3045 (use (match_operand:SI 4 "" ""))]
3048 if (s390_expand_cmpmem (operands[0], operands[1],
3049 operands[2], operands[3]))
3055 ; Compare a block that is up to 256 bytes in length.
3056 ; The block length is taken as (operands[2] % 256) + 1.
3058 (define_expand "cmpmem_short"
3060 [(set (reg:CCU CC_REGNUM)
3061 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3062 (match_operand:BLK 1 "memory_operand" "")))
3063 (use (match_operand 2 "nonmemory_operand" ""))
3064 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3065 (clobber (match_dup 3))])]
3067 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3069 (define_insn "*cmpmem_short"
3070 [(set (reg:CCU CC_REGNUM)
3071 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3072 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3073 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3074 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3075 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3076 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3078 [(set_attr "type" "cs")
3079 (set_attr "cpu_facility" "*,*,z10,*")])
3082 [(set (reg:CCU CC_REGNUM)
3083 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3084 (match_operand:BLK 1 "memory_operand" "")))
3085 (use (match_operand 2 "const_int_operand" ""))
3086 (use (match_operand 3 "immediate_operand" ""))
3087 (clobber (scratch))]
3090 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3091 (use (match_dup 2))])]
3092 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3095 [(set (reg:CCU CC_REGNUM)
3096 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3097 (match_operand:BLK 1 "memory_operand" "")))
3098 (use (match_operand 2 "register_operand" ""))
3099 (use (match_operand 3 "memory_operand" ""))
3100 (clobber (scratch))]
3103 [(unspec [(match_dup 2) (match_dup 3)
3104 (const_int 0)] UNSPEC_EXECUTE)
3105 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3106 (use (const_int 1))])]
3110 [(set (reg:CCU CC_REGNUM)
3111 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3112 (match_operand:BLK 1 "memory_operand" "")))
3113 (use (match_operand 2 "register_operand" ""))
3114 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3115 (clobber (scratch))]
3116 "TARGET_Z10 && reload_completed"
3118 [(unspec [(match_dup 2) (const_int 0)
3119 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3120 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3121 (use (const_int 1))])]
3122 "operands[4] = gen_label_rtx ();")
3125 [(set (reg:CCU CC_REGNUM)
3126 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3127 (match_operand:BLK 1 "memory_operand" "")))
3128 (use (match_operand 2 "register_operand" ""))
3129 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3130 (clobber (match_operand 3 "register_operand" ""))]
3131 "reload_completed && TARGET_CPU_ZARCH"
3132 [(set (match_dup 3) (label_ref (match_dup 4)))
3134 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3135 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3136 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3137 (use (const_int 1))])]
3138 "operands[4] = gen_label_rtx ();")
3140 ; Compare a block of arbitrary length.
3142 (define_expand "cmpmem_long"
3144 [(clobber (match_dup 2))
3145 (clobber (match_dup 3))
3146 (set (reg:CCU CC_REGNUM)
3147 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3148 (match_operand:BLK 1 "memory_operand" "")))
3149 (use (match_operand 2 "general_operand" ""))
3150 (use (match_dup 3))])]
3153 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3154 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3155 rtx reg0 = gen_reg_rtx (dreg_mode);
3156 rtx reg1 = gen_reg_rtx (dreg_mode);
3157 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3158 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3159 rtx len0 = gen_lowpart (Pmode, reg0);
3160 rtx len1 = gen_lowpart (Pmode, reg1);
3162 emit_clobber (reg0);
3163 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3164 emit_move_insn (len0, operands[2]);
3166 emit_clobber (reg1);
3167 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3168 emit_move_insn (len1, operands[2]);
3170 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3171 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3176 (define_insn "*cmpmem_long"
3177 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3178 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3179 (set (reg:CCU CC_REGNUM)
3180 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3181 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3183 (use (match_dup 3))]
3184 "TARGET_64BIT || !TARGET_ZARCH"
3185 "clcle\t%0,%1,0\;jo\t.-4"
3186 [(set_attr "length" "8")
3187 (set_attr "type" "vs")])
3189 (define_insn "*cmpmem_long_31z"
3190 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3191 (clobber (match_operand:TI 1 "register_operand" "=d"))
3192 (set (reg:CCU CC_REGNUM)
3193 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3194 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3196 (use (match_dup 3))]
3197 "!TARGET_64BIT && TARGET_ZARCH"
3198 "clcle\t%0,%1,0\;jo\t.-4"
3199 [(set_attr "op_type" "NN")
3200 (set_attr "type" "vs")
3201 (set_attr "length" "8")])
3203 ; Convert CCUmode condition code to integer.
3204 ; Result is zero if EQ, positive if LTU, negative if GTU.
3206 (define_insn_and_split "cmpint"
3207 [(set (match_operand:SI 0 "register_operand" "=d")
3208 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3210 (clobber (reg:CC CC_REGNUM))]
3214 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3216 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3217 (clobber (reg:CC CC_REGNUM))])])
3219 (define_insn_and_split "*cmpint_cc"
3220 [(set (reg CC_REGNUM)
3221 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3224 (set (match_operand:SI 0 "register_operand" "=d")
3225 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3226 "s390_match_ccmode (insn, CCSmode)"
3228 "&& reload_completed"
3229 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3231 [(set (match_dup 2) (match_dup 3))
3232 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3234 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3235 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3236 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3239 (define_insn_and_split "*cmpint_sign"
3240 [(set (match_operand:DI 0 "register_operand" "=d")
3241 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3242 UNSPEC_CCU_TO_INT)))
3243 (clobber (reg:CC CC_REGNUM))]
3246 "&& reload_completed"
3247 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3249 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3250 (clobber (reg:CC CC_REGNUM))])])
3252 (define_insn_and_split "*cmpint_sign_cc"
3253 [(set (reg CC_REGNUM)
3254 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3255 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3256 UNSPEC_CCU_TO_INT) 0)
3257 (const_int 32)) (const_int 32))
3259 (set (match_operand:DI 0 "register_operand" "=d")
3260 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3261 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3263 "&& reload_completed"
3264 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3266 [(set (match_dup 2) (match_dup 3))
3267 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3269 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3270 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3271 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3276 ;;- Conversion instructions.
3279 (define_insn "*sethighpartsi"
3280 [(set (match_operand:SI 0 "register_operand" "=d,d")
3281 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3282 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3283 (clobber (reg:CC CC_REGNUM))]
3288 [(set_attr "op_type" "RS,RSY")
3289 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3291 (define_insn "*sethighpartdi_64"
3292 [(set (match_operand:DI 0 "register_operand" "=d")
3293 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3294 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3295 (clobber (reg:CC CC_REGNUM))]
3298 [(set_attr "op_type" "RSY")
3299 (set_attr "z10prop" "z10_super")])
3301 (define_insn "*sethighpartdi_31"
3302 [(set (match_operand:DI 0 "register_operand" "=d,d")
3303 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3304 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3305 (clobber (reg:CC CC_REGNUM))]
3310 [(set_attr "op_type" "RS,RSY")
3311 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3314 ; extv instruction patterns
3317 ; FIXME: This expander needs to be converted from DI to GPR as well
3318 ; after resolving some issues with it.
3320 (define_expand "extzv"
3322 [(set (match_operand:DI 0 "register_operand" "=d")
3324 (match_operand:DI 1 "register_operand" "d")
3325 (match_operand 2 "const_int_operand" "") ; size
3326 (match_operand 3 "const_int_operand" ""))) ; start
3327 (clobber (reg:CC CC_REGNUM))])]
3330 /* Starting with zEC12 there is risbgn not clobbering CC. */
3333 emit_move_insn (operands[0],
3334 gen_rtx_ZERO_EXTRACT (DImode,
3342 (define_insn "*extzv<mode>_zEC12"
3343 [(set (match_operand:GPR 0 "register_operand" "=d")
3345 (match_operand:GPR 1 "register_operand" "d")
3346 (match_operand 2 "const_int_operand" "") ; size
3347 (match_operand 3 "const_int_operand" "")))] ; start]
3349 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3350 [(set_attr "op_type" "RIE")])
3352 (define_insn "*extzv<mode>_z10"
3353 [(set (match_operand:GPR 0 "register_operand" "=d")
3355 (match_operand:GPR 1 "register_operand" "d")
3356 (match_operand 2 "const_int_operand" "") ; size
3357 (match_operand 3 "const_int_operand" ""))) ; start
3358 (clobber (reg:CC CC_REGNUM))]
3360 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3361 [(set_attr "op_type" "RIE")
3362 (set_attr "z10prop" "z10_super_E1")])
3364 (define_insn_and_split "*pre_z10_extzv<mode>"
3365 [(set (match_operand:GPR 0 "register_operand" "=d")
3366 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3367 (match_operand 2 "nonzero_shift_count_operand" "")
3369 (clobber (reg:CC CC_REGNUM))]
3372 "&& reload_completed"
3374 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3375 (clobber (reg:CC CC_REGNUM))])
3376 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3378 int bitsize = INTVAL (operands[2]);
3379 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3380 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3382 operands[1] = adjust_address (operands[1], BLKmode, 0);
3383 set_mem_size (operands[1], size);
3384 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3385 operands[3] = GEN_INT (mask);
3388 (define_insn_and_split "*pre_z10_extv<mode>"
3389 [(set (match_operand:GPR 0 "register_operand" "=d")
3390 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3391 (match_operand 2 "nonzero_shift_count_operand" "")
3393 (clobber (reg:CC CC_REGNUM))]
3396 "&& reload_completed"
3398 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3399 (clobber (reg:CC CC_REGNUM))])
3401 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3402 (clobber (reg:CC CC_REGNUM))])]
3404 int bitsize = INTVAL (operands[2]);
3405 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3406 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3408 operands[1] = adjust_address (operands[1], BLKmode, 0);
3409 set_mem_size (operands[1], size);
3410 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3411 operands[3] = GEN_INT (mask);
3415 ; insv instruction patterns
3418 (define_expand "insv"
3419 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3420 (match_operand 1 "const_int_operand" "")
3421 (match_operand 2 "const_int_operand" ""))
3422 (match_operand 3 "general_operand" ""))]
3425 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3431 ; The normal RTL expansion will never generate a zero_extract where
3432 ; the location operand isn't word mode. However, we do this in the
3433 ; back-end when generating atomic operations. See s390_two_part_insv.
3434 (define_insn "*insv<mode>_zEC12"
3435 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3436 (match_operand 1 "const_int_operand" "I") ; size
3437 (match_operand 2 "const_int_operand" "I")) ; pos
3438 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3440 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3441 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3442 [(set_attr "op_type" "RIE")])
3444 (define_insn "*insv<mode>_z10"
3445 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3446 (match_operand 1 "const_int_operand" "I") ; size
3447 (match_operand 2 "const_int_operand" "I")) ; pos
3448 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3449 (clobber (reg:CC CC_REGNUM))]
3451 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3452 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3453 [(set_attr "op_type" "RIE")
3454 (set_attr "z10prop" "z10_super_E1")])
3456 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3457 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3458 (define_insn "*insv<mode>_zEC12_noshift"
3459 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3460 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3461 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3462 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3463 (match_operand:GPR 4 "const_int_operand" ""))))]
3464 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3465 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3466 [(set_attr "op_type" "RIE")])
3468 (define_insn "*insv<mode>_z10_noshift"
3469 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3470 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3471 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3472 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3473 (match_operand:GPR 4 "const_int_operand" ""))))
3474 (clobber (reg:CC CC_REGNUM))]
3475 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3476 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3477 [(set_attr "op_type" "RIE")
3478 (set_attr "z10prop" "z10_super_E1")])
3480 (define_insn "*r<noxa>sbg_<mode>_noshift"
3481 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3483 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3484 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3485 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3486 (clobber (reg:CC CC_REGNUM))]
3488 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3489 [(set_attr "op_type" "RIE")])
3491 (define_insn "*r<noxa>sbg_di_rotl"
3492 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3496 (match_operand:DI 1 "nonimmediate_operand" "d")
3497 (match_operand:DI 3 "const_int_operand" ""))
3498 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3499 (match_operand:DI 4 "nonimmediate_operand" "0")))
3500 (clobber (reg:CC CC_REGNUM))]
3502 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3503 [(set_attr "op_type" "RIE")])
3505 (define_insn "*r<noxa>sbg_<mode>_srl"
3506 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3510 (match_operand:GPR 1 "nonimmediate_operand" "d")
3511 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3512 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3513 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3514 (clobber (reg:CC CC_REGNUM))]
3516 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3517 INTVAL (operands[2]))"
3518 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3519 [(set_attr "op_type" "RIE")])
3521 (define_insn "*r<noxa>sbg_<mode>_sll"
3522 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3526 (match_operand:GPR 1 "nonimmediate_operand" "d")
3527 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3528 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3529 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3530 (clobber (reg:CC CC_REGNUM))]
3532 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3533 INTVAL (operands[2]))"
3534 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3535 [(set_attr "op_type" "RIE")])
3537 (define_insn "*insv<mode>_mem_reg"
3538 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3539 (match_operand 1 "const_int_operand" "n,n")
3541 (match_operand:W 2 "register_operand" "d,d"))]
3542 "INTVAL (operands[1]) > 0
3543 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3544 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3546 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3548 operands[1] = GEN_INT ((1ul << size) - 1);
3549 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3550 : "stcmy\t%2,%1,%S0";
3552 [(set_attr "op_type" "RS,RSY")
3553 (set_attr "z10prop" "z10_super,z10_super")])
3555 (define_insn "*insvdi_mem_reghigh"
3556 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3557 (match_operand 1 "const_int_operand" "n")
3559 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3562 && INTVAL (operands[1]) > 0
3563 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3564 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3566 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3568 operands[1] = GEN_INT ((1ul << size) - 1);
3569 return "stcmh\t%2,%1,%S0";
3571 [(set_attr "op_type" "RSY")
3572 (set_attr "z10prop" "z10_super")])
3574 (define_insn "*insvdi_reg_imm"
3575 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3577 (match_operand 1 "const_int_operand" "n"))
3578 (match_operand:DI 2 "const_int_operand" "n"))]
3580 && INTVAL (operands[1]) >= 0
3581 && INTVAL (operands[1]) < BITS_PER_WORD
3582 && INTVAL (operands[1]) % 16 == 0"
3584 switch (BITS_PER_WORD - INTVAL (operands[1]))
3586 case 64: return "iihh\t%0,%x2"; break;
3587 case 48: return "iihl\t%0,%x2"; break;
3588 case 32: return "iilh\t%0,%x2"; break;
3589 case 16: return "iill\t%0,%x2"; break;
3590 default: gcc_unreachable();
3593 [(set_attr "op_type" "RI")
3594 (set_attr "z10prop" "z10_super_E1")])
3596 ; Update the left-most 32 bit of a DI.
3597 (define_insn "*insv_h_di_reg_extimm"
3598 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3601 (match_operand:DI 1 "const_int_operand" "n"))]
3604 [(set_attr "op_type" "RIL")
3605 (set_attr "z10prop" "z10_fwd_E1")])
3607 ; Update the right-most 32 bit of a DI.
3608 (define_insn "*insv_l_di_reg_extimm"
3609 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3612 (match_operand:DI 1 "const_int_operand" "n"))]
3615 [(set_attr "op_type" "RIL")
3616 (set_attr "z10prop" "z10_fwd_A1")])
3619 ; extendsidi2 instruction pattern(s).
3622 (define_expand "extendsidi2"
3623 [(set (match_operand:DI 0 "register_operand" "")
3624 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3629 emit_clobber (operands[0]);
3630 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3631 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3632 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3637 (define_insn "*extendsidi2"
3638 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3639 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3645 [(set_attr "op_type" "RRE,RXY,RIL")
3646 (set_attr "type" "*,*,larl")
3647 (set_attr "cpu_facility" "*,*,z10")
3648 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3651 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3654 (define_expand "extend<HQI:mode><DSI:mode>2"
3655 [(set (match_operand:DSI 0 "register_operand" "")
3656 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3659 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3661 rtx tmp = gen_reg_rtx (SImode);
3662 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3663 emit_insn (gen_extendsidi2 (operands[0], tmp));
3666 else if (!TARGET_EXTIMM)
3668 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3670 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3671 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3672 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3678 ; extendhidi2 instruction pattern(s).
3681 (define_insn "*extendhidi2_extimm"
3682 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3683 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3684 "TARGET_ZARCH && TARGET_EXTIMM"
3689 [(set_attr "op_type" "RRE,RXY,RIL")
3690 (set_attr "type" "*,*,larl")
3691 (set_attr "cpu_facility" "extimm,extimm,z10")
3692 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3694 (define_insn "*extendhidi2"
3695 [(set (match_operand:DI 0 "register_operand" "=d")
3696 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3699 [(set_attr "op_type" "RXY")
3700 (set_attr "z10prop" "z10_super_E1")])
3703 ; extendhisi2 instruction pattern(s).
3706 (define_insn "*extendhisi2_extimm"
3707 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3708 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3715 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3716 (set_attr "type" "*,*,*,larl")
3717 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3718 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3720 (define_insn "*extendhisi2"
3721 [(set (match_operand:SI 0 "register_operand" "=d,d")
3722 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3727 [(set_attr "op_type" "RX,RXY")
3728 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3731 ; extendqi(si|di)2 instruction pattern(s).
3734 ; lbr, lgbr, lb, lgb
3735 (define_insn "*extendqi<mode>2_extimm"
3736 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3737 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3742 [(set_attr "op_type" "RRE,RXY")
3743 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3746 (define_insn "*extendqi<mode>2"
3747 [(set (match_operand:GPR 0 "register_operand" "=d")
3748 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3749 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3751 [(set_attr "op_type" "RXY")
3752 (set_attr "z10prop" "z10_super_E1")])
3754 (define_insn_and_split "*extendqi<mode>2_short_displ"
3755 [(set (match_operand:GPR 0 "register_operand" "=d")
3756 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3757 (clobber (reg:CC CC_REGNUM))]
3758 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3760 "&& reload_completed"
3762 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3763 (clobber (reg:CC CC_REGNUM))])
3765 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3766 (clobber (reg:CC CC_REGNUM))])]
3768 operands[1] = adjust_address (operands[1], BLKmode, 0);
3769 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3770 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3774 ; zero_extendsidi2 instruction pattern(s).
3777 (define_expand "zero_extendsidi2"
3778 [(set (match_operand:DI 0 "register_operand" "")
3779 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3784 emit_clobber (operands[0]);
3785 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3786 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3791 (define_insn "*zero_extendsidi2"
3792 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3793 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3799 [(set_attr "op_type" "RRE,RXY,RIL")
3800 (set_attr "type" "*,*,larl")
3801 (set_attr "cpu_facility" "*,*,z10")
3802 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3805 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3808 (define_insn "*llgt_sidi"
3809 [(set (match_operand:DI 0 "register_operand" "=d")
3810 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3811 (const_int 2147483647)))]
3814 [(set_attr "op_type" "RXE")
3815 (set_attr "z10prop" "z10_super_E1")])
3817 (define_insn_and_split "*llgt_sidi_split"
3818 [(set (match_operand:DI 0 "register_operand" "=d")
3819 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3820 (const_int 2147483647)))
3821 (clobber (reg:CC CC_REGNUM))]
3824 "&& reload_completed"
3826 (and:DI (subreg:DI (match_dup 1) 0)
3827 (const_int 2147483647)))]
3830 (define_insn "*llgt_sisi"
3831 [(set (match_operand:SI 0 "register_operand" "=d,d")
3832 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3833 (const_int 2147483647)))]
3838 [(set_attr "op_type" "RRE,RXE")
3839 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3841 (define_insn "*llgt_didi"
3842 [(set (match_operand:DI 0 "register_operand" "=d,d")
3843 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3844 (const_int 2147483647)))]
3849 [(set_attr "op_type" "RRE,RXE")
3850 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3853 [(set (match_operand:DSI 0 "register_operand" "")
3854 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3855 (const_int 2147483647)))
3856 (clobber (reg:CC CC_REGNUM))]
3857 "TARGET_ZARCH && reload_completed"
3859 (and:DSI (match_dup 1)
3860 (const_int 2147483647)))]
3864 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3867 (define_expand "zero_extend<mode>di2"
3868 [(set (match_operand:DI 0 "register_operand" "")
3869 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3874 rtx tmp = gen_reg_rtx (SImode);
3875 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3876 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3879 else if (!TARGET_EXTIMM)
3881 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
3882 operands[1] = gen_lowpart (DImode, operands[1]);
3883 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3884 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3889 (define_expand "zero_extend<mode>si2"
3890 [(set (match_operand:SI 0 "register_operand" "")
3891 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3896 operands[1] = gen_lowpart (SImode, operands[1]);
3897 emit_insn (gen_andsi3 (operands[0], operands[1],
3898 GEN_INT ((1 << <HQI:bitsize>) - 1)));
3904 (define_insn "*zero_extendhi<mode>2_z10"
3905 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3906 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3912 [(set_attr "op_type" "RXY,RRE,RIL")
3913 (set_attr "type" "*,*,larl")
3914 (set_attr "cpu_facility" "*,*,z10")
3915 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3917 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3918 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3919 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3920 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3925 [(set_attr "op_type" "RRE,RXY")
3926 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3929 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3930 [(set (match_operand:GPR 0 "register_operand" "=d")
3931 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3932 "TARGET_ZARCH && !TARGET_EXTIMM"
3934 [(set_attr "op_type" "RXY")
3935 (set_attr "z10prop" "z10_fwd_A3")])
3937 (define_insn_and_split "*zero_extendhisi2_31"
3938 [(set (match_operand:SI 0 "register_operand" "=&d")
3939 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3940 (clobber (reg:CC CC_REGNUM))]
3943 "&& reload_completed"
3944 [(set (match_dup 0) (const_int 0))
3946 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3947 (clobber (reg:CC CC_REGNUM))])]
3948 "operands[2] = gen_lowpart (HImode, operands[0]);")
3950 (define_insn_and_split "*zero_extendqisi2_31"
3951 [(set (match_operand:SI 0 "register_operand" "=&d")
3952 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3955 "&& reload_completed"
3956 [(set (match_dup 0) (const_int 0))
3957 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3958 "operands[2] = gen_lowpart (QImode, operands[0]);")
3961 ; zero_extendqihi2 instruction pattern(s).
3964 (define_expand "zero_extendqihi2"
3965 [(set (match_operand:HI 0 "register_operand" "")
3966 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3967 "TARGET_ZARCH && !TARGET_EXTIMM"
3969 operands[1] = gen_lowpart (HImode, operands[1]);
3970 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3974 (define_insn "*zero_extendqihi2_64"
3975 [(set (match_operand:HI 0 "register_operand" "=d")
3976 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3977 "TARGET_ZARCH && !TARGET_EXTIMM"
3979 [(set_attr "op_type" "RXY")
3980 (set_attr "z10prop" "z10_fwd_A3")])
3982 (define_insn_and_split "*zero_extendqihi2_31"
3983 [(set (match_operand:HI 0 "register_operand" "=&d")
3984 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3987 "&& reload_completed"
3988 [(set (match_dup 0) (const_int 0))
3989 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3990 "operands[2] = gen_lowpart (QImode, operands[0]);")
3993 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3996 (define_expand "fixuns_truncdddi2"
3998 [(set (match_operand:DI 0 "register_operand" "")
3999 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4000 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4001 (clobber (reg:CC CC_REGNUM))])]
4007 rtx label1 = gen_label_rtx ();
4008 rtx label2 = gen_label_rtx ();
4009 rtx temp = gen_reg_rtx (TDmode);
4010 REAL_VALUE_TYPE cmp, sub;
4012 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4013 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4015 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4016 solution is doing the check and the subtraction in TD mode and using a
4017 TD -> DI convert afterwards. */
4018 emit_insn (gen_extendddtd2 (temp, operands[1]));
4019 temp = force_reg (TDmode, temp);
4020 emit_cmp_and_jump_insns (temp,
4021 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4022 LT, NULL_RTX, VOIDmode, 0, label1);
4023 emit_insn (gen_subtd3 (temp, temp,
4024 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4025 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4028 emit_label (label1);
4029 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4030 emit_label (label2);
4035 (define_expand "fixuns_trunctddi2"
4037 [(set (match_operand:DI 0 "register_operand" "")
4038 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4039 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4040 (clobber (reg:CC CC_REGNUM))])]
4046 rtx label1 = gen_label_rtx ();
4047 rtx label2 = gen_label_rtx ();
4048 rtx temp = gen_reg_rtx (TDmode);
4049 REAL_VALUE_TYPE cmp, sub;
4051 operands[1] = force_reg (TDmode, operands[1]);
4052 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4053 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4055 emit_cmp_and_jump_insns (operands[1],
4056 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4057 LT, NULL_RTX, VOIDmode, 0, label1);
4058 emit_insn (gen_subtd3 (temp, operands[1],
4059 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4060 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4063 emit_label (label1);
4064 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4065 emit_label (label2);
4071 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4072 ; instruction pattern(s).
4075 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4077 [(set (match_operand:GPR 0 "register_operand" "")
4078 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4079 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4080 (clobber (reg:CC CC_REGNUM))])]
4085 rtx label1 = gen_label_rtx ();
4086 rtx label2 = gen_label_rtx ();
4087 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4088 REAL_VALUE_TYPE cmp, sub;
4090 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4091 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4092 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4094 emit_cmp_and_jump_insns (operands[1],
4095 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4096 LT, NULL_RTX, VOIDmode, 0, label1);
4097 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4098 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4099 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4103 emit_label (label1);
4104 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4105 operands[1], GEN_INT (5)));
4106 emit_label (label2);
4111 ; fixuns_trunc(td|dd)si2 expander
4112 (define_expand "fixuns_trunc<mode>si2"
4114 [(set (match_operand:SI 0 "register_operand" "")
4115 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4116 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4117 (clobber (reg:CC CC_REGNUM))])]
4118 "TARGET_Z196 && TARGET_HARD_DFP"
4121 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4123 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4124 ; clfdtr, clfxtr, clgdtr, clgxtr
4125 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4126 [(set (match_operand:GPR 0 "register_operand" "=r")
4127 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4128 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4129 (clobber (reg:CC CC_REGNUM))]
4131 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4132 [(set_attr "op_type" "RRF")
4133 (set_attr "type" "ftoi")])
4135 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4136 [(set (match_operand:GPR 0 "register_operand" "")
4137 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4140 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4145 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4146 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4147 [(set (match_operand:GPR 0 "register_operand" "=d")
4148 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4149 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4150 (clobber (reg:CC CC_REGNUM))]
4152 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4153 [(set_attr "op_type" "RRE")
4154 (set_attr "type" "ftoi")])
4158 ; fix_trunc(td|dd)di2 instruction pattern(s).
4161 (define_expand "fix_trunc<mode>di2"
4162 [(set (match_operand:DI 0 "register_operand" "")
4163 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4164 "TARGET_ZARCH && TARGET_HARD_DFP"
4166 operands[1] = force_reg (<MODE>mode, operands[1]);
4167 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4173 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4174 [(set (match_operand:DI 0 "register_operand" "=d")
4175 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4176 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4177 (clobber (reg:CC CC_REGNUM))]
4178 "TARGET_ZARCH && TARGET_HARD_DFP"
4179 "cg<DFP:xde>tr\t%0,%h2,%1"
4180 [(set_attr "op_type" "RRF")
4181 (set_attr "type" "ftoidfp")])
4185 ; fix_trunctf(si|di)2 instruction pattern(s).
4188 (define_expand "fix_trunctf<mode>2"
4189 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4190 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4191 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4192 (clobber (reg:CC CC_REGNUM))])]
4198 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4201 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4202 (define_insn "floatdi<mode>2"
4203 [(set (match_operand:FP 0 "register_operand" "=f")
4204 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4205 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4206 "c<xde>g<bt>r\t%0,%1"
4207 [(set_attr "op_type" "RRE")
4208 (set_attr "type" "itof<mode>" )])
4210 ; cxfbr, cdfbr, cefbr
4211 (define_insn "floatsi<mode>2"
4212 [(set (match_operand:BFP 0 "register_operand" "=f")
4213 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4216 [(set_attr "op_type" "RRE")
4217 (set_attr "type" "itof<mode>" )])
4220 (define_insn "floatsi<mode>2"
4221 [(set (match_operand:DFP 0 "register_operand" "=f")
4222 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4223 "TARGET_Z196 && TARGET_HARD_FLOAT"
4224 "c<xde>ftr\t%0,0,%1,0"
4225 [(set_attr "op_type" "RRE")
4226 (set_attr "type" "itof<mode>" )])
4229 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4232 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4233 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4234 (define_insn "floatuns<GPR:mode><FP:mode>2"
4235 [(set (match_operand:FP 0 "register_operand" "=f")
4236 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4237 "TARGET_Z196 && TARGET_HARD_FLOAT"
4238 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4239 [(set_attr "op_type" "RRE")
4240 (set_attr "type" "itof<FP:mode>" )])
4243 ; truncdfsf2 instruction pattern(s).
4246 (define_insn "truncdfsf2"
4247 [(set (match_operand:SF 0 "register_operand" "=f")
4248 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4251 [(set_attr "op_type" "RRE")
4252 (set_attr "type" "ftruncdf")])
4255 ; trunctf(df|sf)2 instruction pattern(s).
4259 (define_insn "trunctf<mode>2"
4260 [(set (match_operand:DSF 0 "register_operand" "=f")
4261 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4262 (clobber (match_scratch:TF 2 "=f"))]
4264 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4265 [(set_attr "length" "6")
4266 (set_attr "type" "ftrunctf")])
4269 ; trunctddd2 and truncddsd2 instruction pattern(s).
4272 (define_insn "trunctddd2"
4273 [(set (match_operand:DD 0 "register_operand" "=f")
4274 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4275 (clobber (match_scratch:TD 2 "=f"))]
4277 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4278 [(set_attr "length" "6")
4279 (set_attr "type" "ftruncdd")])
4281 (define_insn "truncddsd2"
4282 [(set (match_operand:SD 0 "register_operand" "=f")
4283 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4286 [(set_attr "op_type" "RRF")
4287 (set_attr "type" "ftruncsd")])
4290 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4293 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4294 (define_insn "extend<DSF:mode><BFP:mode>2"
4295 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4296 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4298 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4300 l<BFP:xde><DSF:xde>br\t%0,%1
4301 l<BFP:xde><DSF:xde>b\t%0,%1"
4302 [(set_attr "op_type" "RRE,RXE")
4303 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4306 ; extendddtd2 and extendsddd2 instruction pattern(s).
4309 (define_insn "extendddtd2"
4310 [(set (match_operand:TD 0 "register_operand" "=f")
4311 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4314 [(set_attr "op_type" "RRF")
4315 (set_attr "type" "fsimptf")])
4317 (define_insn "extendsddd2"
4318 [(set (match_operand:DD 0 "register_operand" "=f")
4319 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4322 [(set_attr "op_type" "RRF")
4323 (set_attr "type" "fsimptf")])
4325 ; Binary <-> Decimal floating point trunc patterns
4328 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4329 [(set (reg:DFP_ALL FPR0_REGNUM)
4330 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4331 (use (reg:SI GPR0_REGNUM))
4332 (clobber (reg:CC CC_REGNUM))]
4336 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4337 [(set (reg:BFP FPR0_REGNUM)
4338 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4339 (use (reg:SI GPR0_REGNUM))
4340 (clobber (reg:CC CC_REGNUM))]
4344 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4345 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4346 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4348 [(set (reg:DFP_ALL FPR0_REGNUM)
4349 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4350 (use (reg:SI GPR0_REGNUM))
4351 (clobber (reg:CC CC_REGNUM))])
4352 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4353 (reg:DFP_ALL FPR0_REGNUM))]
4355 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4357 HOST_WIDE_INT flags;
4359 flags = (PFPO_CONVERT |
4360 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4361 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4363 operands[2] = GEN_INT (flags);
4366 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4367 [(set (reg:DFP_ALL FPR2_REGNUM)
4368 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4369 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4371 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4372 (use (reg:SI GPR0_REGNUM))
4373 (clobber (reg:CC CC_REGNUM))])
4374 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4376 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4378 HOST_WIDE_INT flags;
4380 flags = (PFPO_CONVERT |
4381 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4382 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4384 operands[2] = GEN_INT (flags);
4388 ; Binary <-> Decimal floating point extend patterns
4391 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4392 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4393 (use (reg:SI GPR0_REGNUM))
4394 (clobber (reg:CC CC_REGNUM))]
4398 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4399 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4400 (use (reg:SI GPR0_REGNUM))
4401 (clobber (reg:CC CC_REGNUM))]
4405 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4406 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4407 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4409 [(set (reg:DFP_ALL FPR0_REGNUM)
4410 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4411 (use (reg:SI GPR0_REGNUM))
4412 (clobber (reg:CC CC_REGNUM))])
4413 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4414 (reg:DFP_ALL FPR0_REGNUM))]
4416 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4418 HOST_WIDE_INT flags;
4420 flags = (PFPO_CONVERT |
4421 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4422 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4424 operands[2] = GEN_INT (flags);
4427 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4428 [(set (reg:DFP_ALL FPR2_REGNUM)
4429 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4430 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4432 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4433 (use (reg:SI GPR0_REGNUM))
4434 (clobber (reg:CC CC_REGNUM))])
4435 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4437 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4439 HOST_WIDE_INT flags;
4441 flags = (PFPO_CONVERT |
4442 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4443 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4445 operands[2] = GEN_INT (flags);
4450 ;; ARITHMETIC OPERATIONS
4452 ; arithmetic operations set the ConditionCode,
4453 ; because of unpredictable Bits in Register for Halfword and Byte
4454 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4457 ;;- Add instructions.
4461 ; addti3 instruction pattern(s).
4464 (define_insn_and_split "addti3"
4465 [(set (match_operand:TI 0 "register_operand" "=&d")
4466 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4467 (match_operand:TI 2 "general_operand" "do") ) )
4468 (clobber (reg:CC CC_REGNUM))]
4471 "&& reload_completed"
4473 [(set (reg:CCL1 CC_REGNUM)
4474 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4476 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4478 [(set (match_dup 3) (plus:DI
4479 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4480 (match_dup 4)) (match_dup 5)))
4481 (clobber (reg:CC CC_REGNUM))])]
4482 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4483 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4484 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4485 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4486 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4487 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4490 ; adddi3 instruction pattern(s).
4493 (define_expand "adddi3"
4495 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4496 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4497 (match_operand:DI 2 "general_operand" "")))
4498 (clobber (reg:CC CC_REGNUM))])]
4502 (define_insn "*adddi3_sign"
4503 [(set (match_operand:DI 0 "register_operand" "=d,d")
4504 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4505 (match_operand:DI 1 "register_operand" "0,0")))
4506 (clobber (reg:CC CC_REGNUM))]
4511 [(set_attr "op_type" "RRE,RXY")
4512 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4514 (define_insn "*adddi3_zero_cc"
4515 [(set (reg CC_REGNUM)
4516 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4517 (match_operand:DI 1 "register_operand" "0,0"))
4519 (set (match_operand:DI 0 "register_operand" "=d,d")
4520 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4521 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4525 [(set_attr "op_type" "RRE,RXY")
4526 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4528 (define_insn "*adddi3_zero_cconly"
4529 [(set (reg CC_REGNUM)
4530 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4531 (match_operand:DI 1 "register_operand" "0,0"))
4533 (clobber (match_scratch:DI 0 "=d,d"))]
4534 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4538 [(set_attr "op_type" "RRE,RXY")
4539 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4541 (define_insn "*adddi3_zero"
4542 [(set (match_operand:DI 0 "register_operand" "=d,d")
4543 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4544 (match_operand:DI 1 "register_operand" "0,0")))
4545 (clobber (reg:CC CC_REGNUM))]
4550 [(set_attr "op_type" "RRE,RXY")
4551 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4553 (define_insn_and_split "*adddi3_31z"
4554 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4555 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4556 (match_operand:DI 2 "general_operand" "do") ) )
4557 (clobber (reg:CC CC_REGNUM))]
4558 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4560 "&& reload_completed"
4562 [(set (reg:CCL1 CC_REGNUM)
4563 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4565 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4567 [(set (match_dup 3) (plus:SI
4568 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4569 (match_dup 4)) (match_dup 5)))
4570 (clobber (reg:CC CC_REGNUM))])]
4571 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4572 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4573 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4574 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4575 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4576 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4578 (define_insn_and_split "*adddi3_31"
4579 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4580 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4581 (match_operand:DI 2 "general_operand" "do") ) )
4582 (clobber (reg:CC CC_REGNUM))]
4585 "&& reload_completed"
4587 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4588 (clobber (reg:CC CC_REGNUM))])
4590 [(set (reg:CCL1 CC_REGNUM)
4591 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4593 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4595 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4597 (label_ref (match_dup 9))))
4599 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4600 (clobber (reg:CC CC_REGNUM))])
4602 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4603 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4604 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4605 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4606 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4607 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4608 operands[9] = gen_label_rtx ();")
4611 ; addsi3 instruction pattern(s).
4614 (define_expand "addsi3"
4616 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4617 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4618 (match_operand:SI 2 "general_operand" "")))
4619 (clobber (reg:CC CC_REGNUM))])]
4623 (define_insn "*addsi3_sign"
4624 [(set (match_operand:SI 0 "register_operand" "=d,d")
4625 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4626 (match_operand:SI 1 "register_operand" "0,0")))
4627 (clobber (reg:CC CC_REGNUM))]
4632 [(set_attr "op_type" "RX,RXY")
4633 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4636 ; add(di|si)3 instruction pattern(s).
4639 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4640 (define_insn "*add<mode>3"
4641 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4642 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4643 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4644 (clobber (reg:CC CC_REGNUM))]
4656 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4657 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4658 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4659 z10_super_E1,z10_super_E1,z10_super_E1")])
4661 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4662 (define_insn "*add<mode>3_carry1_cc"
4663 [(set (reg CC_REGNUM)
4664 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4665 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4667 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4668 (plus:GPR (match_dup 1) (match_dup 2)))]
4669 "s390_match_ccmode (insn, CCL1mode)"
4675 al<g>hsik\t%0,%1,%h2
4679 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4680 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4681 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4682 z10_super_E1,z10_super_E1,z10_super_E1")])
4684 ; alr, al, aly, algr, alg, alrk, algrk
4685 (define_insn "*add<mode>3_carry1_cconly"
4686 [(set (reg CC_REGNUM)
4687 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4688 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4690 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4691 "s390_match_ccmode (insn, CCL1mode)"
4697 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4698 (set_attr "cpu_facility" "*,z196,*,*")
4699 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4701 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4702 (define_insn "*add<mode>3_carry2_cc"
4703 [(set (reg CC_REGNUM)
4704 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4705 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4707 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4708 (plus:GPR (match_dup 1) (match_dup 2)))]
4709 "s390_match_ccmode (insn, CCL1mode)"
4715 al<g>hsik\t%0,%1,%h2
4719 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4720 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4721 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4722 z10_super_E1,z10_super_E1,z10_super_E1")])
4724 ; alr, al, aly, algr, alg, alrk, algrk
4725 (define_insn "*add<mode>3_carry2_cconly"
4726 [(set (reg CC_REGNUM)
4727 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4728 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4730 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4731 "s390_match_ccmode (insn, CCL1mode)"
4737 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4738 (set_attr "cpu_facility" "*,z196,*,*")
4739 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4741 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4742 (define_insn "*add<mode>3_cc"
4743 [(set (reg CC_REGNUM)
4744 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4745 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4747 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4748 (plus:GPR (match_dup 1) (match_dup 2)))]
4749 "s390_match_ccmode (insn, CCLmode)"
4755 al<g>hsik\t%0,%1,%h2
4759 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4760 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4761 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4762 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4764 ; alr, al, aly, algr, alg, alrk, algrk
4765 (define_insn "*add<mode>3_cconly"
4766 [(set (reg CC_REGNUM)
4767 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4768 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4770 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4771 "s390_match_ccmode (insn, CCLmode)"
4777 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4778 (set_attr "cpu_facility" "*,z196,*,*")
4779 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4781 ; alr, al, aly, algr, alg, alrk, algrk
4782 (define_insn "*add<mode>3_cconly2"
4783 [(set (reg CC_REGNUM)
4784 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4785 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4786 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4787 "s390_match_ccmode(insn, CCLmode)"
4793 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4794 (set_attr "cpu_facility" "*,z196,*,*")
4795 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4797 ; ahi, afi, aghi, agfi, asi, agsi
4798 (define_insn "*add<mode>3_imm_cc"
4799 [(set (reg CC_REGNUM)
4800 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4801 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4803 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4804 (plus:GPR (match_dup 1) (match_dup 2)))]
4805 "s390_match_ccmode (insn, CCAmode)
4806 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4807 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4808 /* Avoid INT32_MIN on 32 bit. */
4809 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
4815 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4816 (set_attr "cpu_facility" "*,z196,extimm,z10")
4817 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4820 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4823 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4824 (define_insn "add<mode>3"
4825 [(set (match_operand:FP 0 "register_operand" "=f, f")
4826 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4827 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4828 (clobber (reg:CC CC_REGNUM))]
4831 a<xde><bt>r\t%0,<op1>%2
4833 [(set_attr "op_type" "<RRer>,RXE")
4834 (set_attr "type" "fsimp<mode>")])
4836 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4837 (define_insn "*add<mode>3_cc"
4838 [(set (reg CC_REGNUM)
4839 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4840 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4841 (match_operand:FP 3 "const0_operand" "")))
4842 (set (match_operand:FP 0 "register_operand" "=f,f")
4843 (plus:FP (match_dup 1) (match_dup 2)))]
4844 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4846 a<xde><bt>r\t%0,<op1>%2
4848 [(set_attr "op_type" "<RRer>,RXE")
4849 (set_attr "type" "fsimp<mode>")])
4851 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4852 (define_insn "*add<mode>3_cconly"
4853 [(set (reg CC_REGNUM)
4854 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4855 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4856 (match_operand:FP 3 "const0_operand" "")))
4857 (clobber (match_scratch:FP 0 "=f,f"))]
4858 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4860 a<xde><bt>r\t%0,<op1>%2
4862 [(set_attr "op_type" "<RRer>,RXE")
4863 (set_attr "type" "fsimp<mode>")])
4867 ;;- Subtract instructions.
4871 ; subti3 instruction pattern(s).
4874 (define_insn_and_split "subti3"
4875 [(set (match_operand:TI 0 "register_operand" "=&d")
4876 (minus:TI (match_operand:TI 1 "register_operand" "0")
4877 (match_operand:TI 2 "general_operand" "do") ) )
4878 (clobber (reg:CC CC_REGNUM))]
4881 "&& reload_completed"
4883 [(set (reg:CCL2 CC_REGNUM)
4884 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4886 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4888 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4889 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4890 (clobber (reg:CC CC_REGNUM))])]
4891 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4892 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4893 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4894 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4895 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4896 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4899 ; subdi3 instruction pattern(s).
4902 (define_expand "subdi3"
4904 [(set (match_operand:DI 0 "register_operand" "")
4905 (minus:DI (match_operand:DI 1 "register_operand" "")
4906 (match_operand:DI 2 "general_operand" "")))
4907 (clobber (reg:CC CC_REGNUM))])]
4911 (define_insn "*subdi3_sign"
4912 [(set (match_operand:DI 0 "register_operand" "=d,d")
4913 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4914 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4915 (clobber (reg:CC CC_REGNUM))]
4920 [(set_attr "op_type" "RRE,RXY")
4921 (set_attr "z10prop" "z10_c,*")
4922 (set_attr "z196prop" "z196_cracked")])
4924 (define_insn "*subdi3_zero_cc"
4925 [(set (reg CC_REGNUM)
4926 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4927 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4929 (set (match_operand:DI 0 "register_operand" "=d,d")
4930 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4931 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4935 [(set_attr "op_type" "RRE,RXY")
4936 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4938 (define_insn "*subdi3_zero_cconly"
4939 [(set (reg CC_REGNUM)
4940 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4941 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4943 (clobber (match_scratch:DI 0 "=d,d"))]
4944 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4948 [(set_attr "op_type" "RRE,RXY")
4949 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4951 (define_insn "*subdi3_zero"
4952 [(set (match_operand:DI 0 "register_operand" "=d,d")
4953 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4954 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4955 (clobber (reg:CC CC_REGNUM))]
4960 [(set_attr "op_type" "RRE,RXY")
4961 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4963 (define_insn_and_split "*subdi3_31z"
4964 [(set (match_operand:DI 0 "register_operand" "=&d")
4965 (minus:DI (match_operand:DI 1 "register_operand" "0")
4966 (match_operand:DI 2 "general_operand" "do") ) )
4967 (clobber (reg:CC CC_REGNUM))]
4968 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4970 "&& reload_completed"
4972 [(set (reg:CCL2 CC_REGNUM)
4973 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4975 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4977 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4978 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4979 (clobber (reg:CC CC_REGNUM))])]
4980 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4981 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4982 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4983 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4984 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4985 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4987 (define_insn_and_split "*subdi3_31"
4988 [(set (match_operand:DI 0 "register_operand" "=&d")
4989 (minus:DI (match_operand:DI 1 "register_operand" "0")
4990 (match_operand:DI 2 "general_operand" "do") ) )
4991 (clobber (reg:CC CC_REGNUM))]
4994 "&& reload_completed"
4996 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4997 (clobber (reg:CC CC_REGNUM))])
4999 [(set (reg:CCL2 CC_REGNUM)
5000 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5002 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5004 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5006 (label_ref (match_dup 9))))
5008 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5009 (clobber (reg:CC CC_REGNUM))])
5011 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5012 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5013 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5014 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5015 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5016 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5017 operands[9] = gen_label_rtx ();")
5020 ; subsi3 instruction pattern(s).
5023 (define_expand "subsi3"
5025 [(set (match_operand:SI 0 "register_operand" "")
5026 (minus:SI (match_operand:SI 1 "register_operand" "")
5027 (match_operand:SI 2 "general_operand" "")))
5028 (clobber (reg:CC CC_REGNUM))])]
5032 (define_insn "*subsi3_sign"
5033 [(set (match_operand:SI 0 "register_operand" "=d,d")
5034 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5035 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5036 (clobber (reg:CC CC_REGNUM))]
5041 [(set_attr "op_type" "RX,RXY")
5042 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5045 ; sub(di|si)3 instruction pattern(s).
5048 ; sr, s, sy, sgr, sg, srk, sgrk
5049 (define_insn "*sub<mode>3"
5050 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5051 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5052 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5053 (clobber (reg:CC CC_REGNUM))]
5060 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5061 (set_attr "cpu_facility" "*,z196,*,*")
5062 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5064 ; slr, sl, sly, slgr, slg, slrk, slgrk
5065 (define_insn "*sub<mode>3_borrow_cc"
5066 [(set (reg CC_REGNUM)
5067 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5068 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5070 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5071 (minus:GPR (match_dup 1) (match_dup 2)))]
5072 "s390_match_ccmode (insn, CCL2mode)"
5078 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5079 (set_attr "cpu_facility" "*,z196,*,*")
5080 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5082 ; slr, sl, sly, slgr, slg, slrk, slgrk
5083 (define_insn "*sub<mode>3_borrow_cconly"
5084 [(set (reg CC_REGNUM)
5085 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5086 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5088 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5089 "s390_match_ccmode (insn, CCL2mode)"
5095 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5096 (set_attr "cpu_facility" "*,z196,*,*")
5097 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5099 ; slr, sl, sly, slgr, slg, slrk, slgrk
5100 (define_insn "*sub<mode>3_cc"
5101 [(set (reg CC_REGNUM)
5102 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5103 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5105 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5106 (minus:GPR (match_dup 1) (match_dup 2)))]
5107 "s390_match_ccmode (insn, CCLmode)"
5113 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5114 (set_attr "cpu_facility" "*,z196,*,*")
5115 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5117 ; slr, sl, sly, slgr, slg, slrk, slgrk
5118 (define_insn "*sub<mode>3_cc2"
5119 [(set (reg CC_REGNUM)
5120 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5121 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5122 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5123 (minus:GPR (match_dup 1) (match_dup 2)))]
5124 "s390_match_ccmode (insn, CCL3mode)"
5130 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5131 (set_attr "cpu_facility" "*,z196,*,*")
5132 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5134 ; slr, sl, sly, slgr, slg, slrk, slgrk
5135 (define_insn "*sub<mode>3_cconly"
5136 [(set (reg CC_REGNUM)
5137 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5138 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5140 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5141 "s390_match_ccmode (insn, CCLmode)"
5147 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5148 (set_attr "cpu_facility" "*,z196,*,*")
5149 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5152 ; slr, sl, sly, slgr, slg, slrk, slgrk
5153 (define_insn "*sub<mode>3_cconly2"
5154 [(set (reg CC_REGNUM)
5155 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5156 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5157 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5158 "s390_match_ccmode (insn, CCL3mode)"
5164 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5165 (set_attr "cpu_facility" "*,z196,*,*")
5166 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5170 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5173 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5174 (define_insn "sub<mode>3"
5175 [(set (match_operand:FP 0 "register_operand" "=f, f")
5176 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5177 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5178 (clobber (reg:CC CC_REGNUM))]
5181 s<xde><bt>r\t%0,<op1>%2
5183 [(set_attr "op_type" "<RRer>,RXE")
5184 (set_attr "type" "fsimp<mode>")])
5186 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5187 (define_insn "*sub<mode>3_cc"
5188 [(set (reg CC_REGNUM)
5189 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5190 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5191 (match_operand:FP 3 "const0_operand" "")))
5192 (set (match_operand:FP 0 "register_operand" "=f,f")
5193 (minus:FP (match_dup 1) (match_dup 2)))]
5194 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5196 s<xde><bt>r\t%0,<op1>%2
5198 [(set_attr "op_type" "<RRer>,RXE")
5199 (set_attr "type" "fsimp<mode>")])
5201 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5202 (define_insn "*sub<mode>3_cconly"
5203 [(set (reg CC_REGNUM)
5204 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5205 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5206 (match_operand:FP 3 "const0_operand" "")))
5207 (clobber (match_scratch:FP 0 "=f,f"))]
5208 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5210 s<xde><bt>r\t%0,<op1>%2
5212 [(set_attr "op_type" "<RRer>,RXE")
5213 (set_attr "type" "fsimp<mode>")])
5217 ;;- Conditional add/subtract instructions.
5221 ; add(di|si)cc instruction pattern(s).
5224 ; the following 4 patterns are used when the result of an add with
5225 ; carry is checked for an overflow condition
5227 ; op1 + op2 + c < op1
5229 ; alcr, alc, alcgr, alcg
5230 (define_insn "*add<mode>3_alc_carry1_cc"
5231 [(set (reg CC_REGNUM)
5233 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5234 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5235 (match_operand:GPR 2 "general_operand" "d,RT"))
5237 (set (match_operand:GPR 0 "register_operand" "=d,d")
5238 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5239 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5243 [(set_attr "op_type" "RRE,RXY")
5244 (set_attr "z196prop" "z196_alone,z196_alone")])
5246 ; alcr, alc, alcgr, alcg
5247 (define_insn "*add<mode>3_alc_carry1_cconly"
5248 [(set (reg CC_REGNUM)
5250 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5251 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5252 (match_operand:GPR 2 "general_operand" "d,RT"))
5254 (clobber (match_scratch:GPR 0 "=d,d"))]
5255 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5259 [(set_attr "op_type" "RRE,RXY")
5260 (set_attr "z196prop" "z196_alone,z196_alone")])
5262 ; op1 + op2 + c < op2
5264 ; alcr, alc, alcgr, alcg
5265 (define_insn "*add<mode>3_alc_carry2_cc"
5266 [(set (reg CC_REGNUM)
5268 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5269 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5270 (match_operand:GPR 2 "general_operand" "d,RT"))
5272 (set (match_operand:GPR 0 "register_operand" "=d,d")
5273 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5274 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5278 [(set_attr "op_type" "RRE,RXY")])
5280 ; alcr, alc, alcgr, alcg
5281 (define_insn "*add<mode>3_alc_carry2_cconly"
5282 [(set (reg CC_REGNUM)
5284 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5285 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5286 (match_operand:GPR 2 "general_operand" "d,RT"))
5288 (clobber (match_scratch:GPR 0 "=d,d"))]
5289 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5293 [(set_attr "op_type" "RRE,RXY")])
5295 ; alcr, alc, alcgr, alcg
5296 (define_insn "*add<mode>3_alc_cc"
5297 [(set (reg CC_REGNUM)
5299 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5300 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5301 (match_operand:GPR 2 "general_operand" "d,RT"))
5303 (set (match_operand:GPR 0 "register_operand" "=d,d")
5304 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5305 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5309 [(set_attr "op_type" "RRE,RXY")])
5311 ; alcr, alc, alcgr, alcg
5312 (define_insn "*add<mode>3_alc"
5313 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5314 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5315 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5316 (match_operand:GPR 2 "general_operand" "d,RT")))
5317 (clobber (reg:CC CC_REGNUM))]
5322 [(set_attr "op_type" "RRE,RXY")])
5324 ; slbr, slb, slbgr, slbg
5325 (define_insn "*sub<mode>3_slb_cc"
5326 [(set (reg CC_REGNUM)
5328 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5329 (match_operand:GPR 2 "general_operand" "d,RT"))
5330 (match_operand:GPR 3 "s390_slb_comparison" ""))
5332 (set (match_operand:GPR 0 "register_operand" "=d,d")
5333 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5334 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5338 [(set_attr "op_type" "RRE,RXY")
5339 (set_attr "z10prop" "z10_c,*")])
5341 ; slbr, slb, slbgr, slbg
5342 (define_insn "*sub<mode>3_slb"
5343 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5344 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5345 (match_operand:GPR 2 "general_operand" "d,RT"))
5346 (match_operand:GPR 3 "s390_slb_comparison" "")))
5347 (clobber (reg:CC CC_REGNUM))]
5352 [(set_attr "op_type" "RRE,RXY")
5353 (set_attr "z10prop" "z10_c,*")])
5355 (define_expand "add<mode>cc"
5356 [(match_operand:GPR 0 "register_operand" "")
5357 (match_operand 1 "comparison_operator" "")
5358 (match_operand:GPR 2 "register_operand" "")
5359 (match_operand:GPR 3 "const_int_operand" "")]
5361 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5362 XEXP (operands[1], 0), XEXP (operands[1], 1),
5363 operands[0], operands[2],
5364 operands[3])) FAIL; DONE;")
5367 ; scond instruction pattern(s).
5370 (define_insn_and_split "*scond<mode>"
5371 [(set (match_operand:GPR 0 "register_operand" "=&d")
5372 (match_operand:GPR 1 "s390_alc_comparison" ""))
5373 (clobber (reg:CC CC_REGNUM))]
5376 "&& reload_completed"
5377 [(set (match_dup 0) (const_int 0))
5379 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5381 (clobber (reg:CC CC_REGNUM))])]
5384 (define_insn_and_split "*scond<mode>_neg"
5385 [(set (match_operand:GPR 0 "register_operand" "=&d")
5386 (match_operand:GPR 1 "s390_slb_comparison" ""))
5387 (clobber (reg:CC CC_REGNUM))]
5390 "&& reload_completed"
5391 [(set (match_dup 0) (const_int 0))
5393 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5395 (clobber (reg:CC CC_REGNUM))])
5397 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5398 (clobber (reg:CC CC_REGNUM))])]
5402 (define_expand "cstore<mode>4"
5403 [(set (match_operand:SI 0 "register_operand" "")
5404 (match_operator:SI 1 "s390_scond_operator"
5405 [(match_operand:GPR 2 "register_operand" "")
5406 (match_operand:GPR 3 "general_operand" "")]))]
5408 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5409 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5411 (define_expand "cstorecc4"
5413 [(set (match_operand:SI 0 "register_operand" "")
5414 (match_operator:SI 1 "s390_eqne_operator"
5415 [(match_operand:CCZ1 2 "register_operand")
5416 (match_operand 3 "const0_operand")]))
5417 (clobber (reg:CC CC_REGNUM))])]
5419 "emit_insn (gen_sne (operands[0], operands[2]));
5420 if (GET_CODE (operands[1]) == EQ)
5421 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5424 (define_insn_and_split "sne"
5425 [(set (match_operand:SI 0 "register_operand" "=d")
5426 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5428 (clobber (reg:CC CC_REGNUM))]
5433 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5434 (clobber (reg:CC CC_REGNUM))])])
5438 ;; - Conditional move instructions (introduced with z196)
5441 (define_expand "mov<mode>cc"
5442 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5443 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5444 (match_operand:GPR 2 "nonimmediate_operand" "")
5445 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5447 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5448 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5450 ; locr, loc, stoc, locgr, locg, stocg
5451 (define_insn_and_split "*mov<mode>cc"
5452 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5454 (match_operator 1 "s390_comparison"
5455 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5457 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5458 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5468 "&& reload_completed
5469 && MEM_P (operands[3]) && MEM_P (operands[4])"
5472 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5477 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5481 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5484 ;;- Multiply instructions.
5488 ; muldi3 instruction pattern(s).
5491 (define_insn "*muldi3_sign"
5492 [(set (match_operand:DI 0 "register_operand" "=d,d")
5493 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5494 (match_operand:DI 1 "register_operand" "0,0")))]
5499 [(set_attr "op_type" "RRE,RXY")
5500 (set_attr "type" "imuldi")])
5502 (define_insn "muldi3"
5503 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5504 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5505 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5512 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5513 (set_attr "type" "imuldi")
5514 (set_attr "cpu_facility" "*,*,*,z10")])
5517 ; mulsi3 instruction pattern(s).
5520 (define_insn "*mulsi3_sign"
5521 [(set (match_operand:SI 0 "register_operand" "=d,d")
5522 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5523 (match_operand:SI 1 "register_operand" "0,0")))]
5528 [(set_attr "op_type" "RX,RXY")
5529 (set_attr "type" "imulhi")
5530 (set_attr "cpu_facility" "*,z10")])
5532 (define_insn "mulsi3"
5533 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5534 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5535 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5543 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5544 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5545 (set_attr "cpu_facility" "*,*,*,*,z10")])
5548 ; mulsidi3 instruction pattern(s).
5551 (define_insn "mulsidi3"
5552 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5553 (mult:DI (sign_extend:DI
5554 (match_operand:SI 1 "register_operand" "%0,0,0"))
5556 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5562 [(set_attr "op_type" "RR,RX,RXY")
5563 (set_attr "type" "imulsi")
5564 (set_attr "cpu_facility" "*,*,z10")])
5567 ; umul instruction pattern(s).
5570 ; mlr, ml, mlgr, mlg
5571 (define_insn "umul<dwh><mode>3"
5572 [(set (match_operand:DW 0 "register_operand" "=d, d")
5573 (mult:DW (zero_extend:DW
5574 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5576 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5581 [(set_attr "op_type" "RRE,RXY")
5582 (set_attr "type" "imul<dwh>")])
5585 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5588 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5589 (define_insn "mul<mode>3"
5590 [(set (match_operand:FP 0 "register_operand" "=f,f")
5591 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5592 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5595 m<xdee><bt>r\t%0,<op1>%2
5597 [(set_attr "op_type" "<RRer>,RXE")
5598 (set_attr "type" "fmul<mode>")])
5600 ; madbr, maebr, maxb, madb, maeb
5601 (define_insn "fma<mode>4"
5602 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5603 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5604 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5605 (match_operand:DSF 3 "register_operand" "0,0")))]
5610 [(set_attr "op_type" "RRE,RXE")
5611 (set_attr "type" "fmadd<mode>")])
5613 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5614 (define_insn "fms<mode>4"
5615 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5616 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5617 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5618 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5623 [(set_attr "op_type" "RRE,RXE")
5624 (set_attr "type" "fmadd<mode>")])
5627 ;;- Divide and modulo instructions.
5631 ; divmoddi4 instruction pattern(s).
5634 (define_expand "divmoddi4"
5635 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5636 (div:DI (match_operand:DI 1 "register_operand" "")
5637 (match_operand:DI 2 "general_operand" "")))
5638 (set (match_operand:DI 3 "general_operand" "")
5639 (mod:DI (match_dup 1) (match_dup 2)))])
5640 (clobber (match_dup 4))]
5643 rtx insn, div_equal, mod_equal;
5645 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5646 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5648 operands[4] = gen_reg_rtx(TImode);
5649 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5651 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5652 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5654 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5655 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5660 (define_insn "divmodtidi3"
5661 [(set (match_operand:TI 0 "register_operand" "=d,d")
5665 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5666 (match_operand:DI 2 "general_operand" "d,RT")))
5668 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5673 [(set_attr "op_type" "RRE,RXY")
5674 (set_attr "type" "idiv")])
5676 (define_insn "divmodtisi3"
5677 [(set (match_operand:TI 0 "register_operand" "=d,d")
5681 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5683 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5686 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5691 [(set_attr "op_type" "RRE,RXY")
5692 (set_attr "type" "idiv")])
5695 ; udivmoddi4 instruction pattern(s).
5698 (define_expand "udivmoddi4"
5699 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5700 (udiv:DI (match_operand:DI 1 "general_operand" "")
5701 (match_operand:DI 2 "nonimmediate_operand" "")))
5702 (set (match_operand:DI 3 "general_operand" "")
5703 (umod:DI (match_dup 1) (match_dup 2)))])
5704 (clobber (match_dup 4))]
5707 rtx insn, div_equal, mod_equal, equal;
5709 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5710 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5711 equal = gen_rtx_IOR (TImode,
5712 gen_rtx_ASHIFT (TImode,
5713 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5715 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5717 operands[4] = gen_reg_rtx(TImode);
5718 emit_clobber (operands[4]);
5719 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5720 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5722 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5723 set_unique_reg_note (insn, REG_EQUAL, equal);
5725 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5726 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5728 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5729 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5734 (define_insn "udivmodtidi3"
5735 [(set (match_operand:TI 0 "register_operand" "=d,d")
5740 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5742 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5746 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5751 [(set_attr "op_type" "RRE,RXY")
5752 (set_attr "type" "idiv")])
5755 ; divmodsi4 instruction pattern(s).
5758 (define_expand "divmodsi4"
5759 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5760 (div:SI (match_operand:SI 1 "general_operand" "")
5761 (match_operand:SI 2 "nonimmediate_operand" "")))
5762 (set (match_operand:SI 3 "general_operand" "")
5763 (mod:SI (match_dup 1) (match_dup 2)))])
5764 (clobber (match_dup 4))]
5767 rtx insn, div_equal, mod_equal, equal;
5769 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5770 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5771 equal = gen_rtx_IOR (DImode,
5772 gen_rtx_ASHIFT (DImode,
5773 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5775 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5777 operands[4] = gen_reg_rtx(DImode);
5778 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5780 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5781 set_unique_reg_note (insn, REG_EQUAL, equal);
5783 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5784 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5786 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5787 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5792 (define_insn "divmoddisi3"
5793 [(set (match_operand:DI 0 "register_operand" "=d,d")
5798 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5800 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5804 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5809 [(set_attr "op_type" "RR,RX")
5810 (set_attr "type" "idiv")])
5813 ; udivsi3 and umodsi3 instruction pattern(s).
5816 (define_expand "udivmodsi4"
5817 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5818 (udiv:SI (match_operand:SI 1 "general_operand" "")
5819 (match_operand:SI 2 "nonimmediate_operand" "")))
5820 (set (match_operand:SI 3 "general_operand" "")
5821 (umod:SI (match_dup 1) (match_dup 2)))])
5822 (clobber (match_dup 4))]
5823 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5825 rtx insn, div_equal, mod_equal, equal;
5827 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5828 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5829 equal = gen_rtx_IOR (DImode,
5830 gen_rtx_ASHIFT (DImode,
5831 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5833 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5835 operands[4] = gen_reg_rtx(DImode);
5836 emit_clobber (operands[4]);
5837 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5838 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5840 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5841 set_unique_reg_note (insn, REG_EQUAL, equal);
5843 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5844 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5846 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5847 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5852 (define_insn "udivmoddisi3"
5853 [(set (match_operand:DI 0 "register_operand" "=d,d")
5858 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5860 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5864 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5865 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5869 [(set_attr "op_type" "RRE,RXY")
5870 (set_attr "type" "idiv")])
5872 (define_expand "udivsi3"
5873 [(set (match_operand:SI 0 "register_operand" "=d")
5874 (udiv:SI (match_operand:SI 1 "general_operand" "")
5875 (match_operand:SI 2 "general_operand" "")))
5876 (clobber (match_dup 3))]
5877 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5879 rtx insn, udiv_equal, umod_equal, equal;
5881 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5882 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5883 equal = gen_rtx_IOR (DImode,
5884 gen_rtx_ASHIFT (DImode,
5885 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5887 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5889 operands[3] = gen_reg_rtx (DImode);
5891 if (CONSTANT_P (operands[2]))
5893 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5895 rtx label1 = gen_label_rtx ();
5897 operands[1] = make_safe_from (operands[1], operands[0]);
5898 emit_move_insn (operands[0], const0_rtx);
5899 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5901 emit_move_insn (operands[0], const1_rtx);
5902 emit_label (label1);
5906 operands[2] = force_reg (SImode, operands[2]);
5907 operands[2] = make_safe_from (operands[2], operands[0]);
5909 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5910 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5912 set_unique_reg_note (insn, REG_EQUAL, equal);
5914 insn = emit_move_insn (operands[0],
5915 gen_lowpart (SImode, operands[3]));
5916 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5921 rtx label1 = gen_label_rtx ();
5922 rtx label2 = gen_label_rtx ();
5923 rtx label3 = gen_label_rtx ();
5925 operands[1] = force_reg (SImode, operands[1]);
5926 operands[1] = make_safe_from (operands[1], operands[0]);
5927 operands[2] = force_reg (SImode, operands[2]);
5928 operands[2] = make_safe_from (operands[2], operands[0]);
5930 emit_move_insn (operands[0], const0_rtx);
5931 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5933 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5935 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5937 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5938 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5940 set_unique_reg_note (insn, REG_EQUAL, equal);
5942 insn = emit_move_insn (operands[0],
5943 gen_lowpart (SImode, operands[3]));
5944 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5947 emit_label (label1);
5948 emit_move_insn (operands[0], operands[1]);
5950 emit_label (label2);
5951 emit_move_insn (operands[0], const1_rtx);
5952 emit_label (label3);
5954 emit_move_insn (operands[0], operands[0]);
5958 (define_expand "umodsi3"
5959 [(set (match_operand:SI 0 "register_operand" "=d")
5960 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5961 (match_operand:SI 2 "nonimmediate_operand" "")))
5962 (clobber (match_dup 3))]
5963 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5965 rtx insn, udiv_equal, umod_equal, equal;
5967 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5968 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5969 equal = gen_rtx_IOR (DImode,
5970 gen_rtx_ASHIFT (DImode,
5971 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5973 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5975 operands[3] = gen_reg_rtx (DImode);
5977 if (CONSTANT_P (operands[2]))
5979 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5981 rtx label1 = gen_label_rtx ();
5983 operands[1] = make_safe_from (operands[1], operands[0]);
5984 emit_move_insn (operands[0], operands[1]);
5985 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5987 emit_insn (gen_abssi2 (operands[0], operands[2]));
5988 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5989 emit_label (label1);
5993 operands[2] = force_reg (SImode, operands[2]);
5994 operands[2] = make_safe_from (operands[2], operands[0]);
5996 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5997 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5999 set_unique_reg_note (insn, REG_EQUAL, equal);
6001 insn = emit_move_insn (operands[0],
6002 gen_highpart (SImode, operands[3]));
6003 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6008 rtx label1 = gen_label_rtx ();
6009 rtx label2 = gen_label_rtx ();
6010 rtx label3 = gen_label_rtx ();
6012 operands[1] = force_reg (SImode, operands[1]);
6013 operands[1] = make_safe_from (operands[1], operands[0]);
6014 operands[2] = force_reg (SImode, operands[2]);
6015 operands[2] = make_safe_from (operands[2], operands[0]);
6017 emit_move_insn(operands[0], operands[1]);
6018 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6020 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6022 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6024 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6025 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6027 set_unique_reg_note (insn, REG_EQUAL, equal);
6029 insn = emit_move_insn (operands[0],
6030 gen_highpart (SImode, operands[3]));
6031 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6034 emit_label (label1);
6035 emit_move_insn (operands[0], const0_rtx);
6037 emit_label (label2);
6038 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6039 emit_label (label3);
6045 ; div(df|sf)3 instruction pattern(s).
6048 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6049 (define_insn "div<mode>3"
6050 [(set (match_operand:FP 0 "register_operand" "=f,f")
6051 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6052 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6055 d<xde><bt>r\t%0,<op1>%2
6057 [(set_attr "op_type" "<RRer>,RXE")
6058 (set_attr "type" "fdiv<mode>")])
6062 ;;- And instructions.
6065 (define_expand "and<mode>3"
6066 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6067 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6068 (match_operand:INT 2 "general_operand" "")))
6069 (clobber (reg:CC CC_REGNUM))]
6071 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6074 ; anddi3 instruction pattern(s).
6077 (define_insn "*anddi3_cc"
6078 [(set (reg CC_REGNUM)
6080 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6081 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6083 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6084 (and:DI (match_dup 1) (match_dup 2)))]
6085 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6090 risbg\t%0,%1,%s2,128+%e2,0"
6091 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6092 (set_attr "cpu_facility" "*,z196,*,z10")
6093 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6095 (define_insn "*anddi3_cconly"
6096 [(set (reg CC_REGNUM)
6098 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6099 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6101 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6103 && s390_match_ccmode(insn, CCTmode)
6104 /* Do not steal TM patterns. */
6105 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6110 risbg\t%0,%1,%s2,128+%e2,0"
6111 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6112 (set_attr "cpu_facility" "*,z196,*,z10")
6113 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6115 (define_insn "*anddi3"
6116 [(set (match_operand:DI 0 "nonimmediate_operand"
6117 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6119 (match_operand:DI 1 "nonimmediate_operand"
6120 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6121 (match_operand:DI 2 "general_operand"
6122 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6123 (clobber (reg:CC CC_REGNUM))]
6124 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6137 risbg\t%0,%1,%s2,128+%e2,0
6140 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6141 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6142 (set_attr "z10prop" "*,
6158 [(set (match_operand:DI 0 "s_operand" "")
6159 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6160 (clobber (reg:CC CC_REGNUM))]
6163 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6164 (clobber (reg:CC CC_REGNUM))])]
6165 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6167 ;; These two are what combine generates for (ashift (zero_extract)).
6168 (define_insn "*extzv_<mode>_srl"
6169 [(set (match_operand:GPR 0 "register_operand" "=d")
6170 (and:GPR (lshiftrt:GPR
6171 (match_operand:GPR 1 "register_operand" "d")
6172 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6173 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6174 (clobber (reg:CC CC_REGNUM))]
6176 /* Note that even for the SImode pattern, the rotate is always DImode. */
6177 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6178 INTVAL (operands[3]))"
6179 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6180 [(set_attr "op_type" "RIE")
6181 (set_attr "z10prop" "z10_super_E1")])
6183 (define_insn "*extzv_<mode>_sll"
6184 [(set (match_operand:GPR 0 "register_operand" "=d")
6185 (and:GPR (ashift:GPR
6186 (match_operand:GPR 1 "register_operand" "d")
6187 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6188 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6189 (clobber (reg:CC CC_REGNUM))]
6191 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6192 INTVAL (operands[3]))"
6193 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6194 [(set_attr "op_type" "RIE")
6195 (set_attr "z10prop" "z10_super_E1")])
6199 ; andsi3 instruction pattern(s).
6202 (define_insn "*andsi3_cc"
6203 [(set (reg CC_REGNUM)
6206 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6207 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6209 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6210 (and:SI (match_dup 1) (match_dup 2)))]
6211 "s390_match_ccmode(insn, CCTmode)"
6218 risbg\t%0,%1,%t2,128+%f2,0"
6219 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6220 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6221 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6222 z10_super_E1,z10_super_E1,z10_super_E1")])
6224 (define_insn "*andsi3_cconly"
6225 [(set (reg CC_REGNUM)
6228 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6229 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6231 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6232 "s390_match_ccmode(insn, CCTmode)
6233 /* Do not steal TM patterns. */
6234 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6241 risbg\t%0,%1,%t2,128+%f2,0"
6242 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6243 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6244 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6245 z10_super_E1,z10_super_E1,z10_super_E1")])
6247 (define_insn "*andsi3_zarch"
6248 [(set (match_operand:SI 0 "nonimmediate_operand"
6249 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6250 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6251 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6252 (match_operand:SI 2 "general_operand"
6253 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6254 (clobber (reg:CC CC_REGNUM))]
6255 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6266 risbg\t%0,%1,%t2,128+%f2,0
6269 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6270 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6271 (set_attr "z10prop" "*,
6284 (define_insn "*andsi3_esa"
6285 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6286 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6287 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6288 (clobber (reg:CC CC_REGNUM))]
6289 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6295 [(set_attr "op_type" "RR,RX,SI,SS")
6296 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6300 [(set (match_operand:SI 0 "s_operand" "")
6301 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6302 (clobber (reg:CC CC_REGNUM))]
6305 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6306 (clobber (reg:CC CC_REGNUM))])]
6307 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6310 ; andhi3 instruction pattern(s).
6313 (define_insn "*andhi3_zarch"
6314 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6315 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6316 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6317 (clobber (reg:CC CC_REGNUM))]
6318 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6325 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6326 (set_attr "cpu_facility" "*,z196,*,*,*")
6327 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6330 (define_insn "*andhi3_esa"
6331 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6332 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6333 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6334 (clobber (reg:CC CC_REGNUM))]
6335 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6340 [(set_attr "op_type" "RR,SI,SS")
6341 (set_attr "z10prop" "z10_super_E1,*,*")
6345 [(set (match_operand:HI 0 "s_operand" "")
6346 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6347 (clobber (reg:CC CC_REGNUM))]
6350 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6351 (clobber (reg:CC CC_REGNUM))])]
6352 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6355 ; andqi3 instruction pattern(s).
6358 (define_insn "*andqi3_zarch"
6359 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6360 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6361 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6362 (clobber (reg:CC CC_REGNUM))]
6363 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6371 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6372 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6373 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6375 (define_insn "*andqi3_esa"
6376 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6377 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6378 (match_operand:QI 2 "general_operand" "d,n,Q")))
6379 (clobber (reg:CC CC_REGNUM))]
6380 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6385 [(set_attr "op_type" "RR,SI,SS")
6386 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6389 ; Block and (NC) patterns.
6393 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6394 (and:BLK (match_dup 0)
6395 (match_operand:BLK 1 "memory_operand" "Q")))
6396 (use (match_operand 2 "const_int_operand" "n"))
6397 (clobber (reg:CC CC_REGNUM))]
6398 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6399 "nc\t%O0(%2,%R0),%S1"
6400 [(set_attr "op_type" "SS")
6401 (set_attr "z196prop" "z196_cracked")])
6404 [(set (match_operand 0 "memory_operand" "")
6406 (match_operand 1 "memory_operand" "")))
6407 (clobber (reg:CC CC_REGNUM))]
6409 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6410 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6412 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6414 (clobber (reg:CC CC_REGNUM))])]
6416 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6417 operands[0] = adjust_address (operands[0], BLKmode, 0);
6418 operands[1] = adjust_address (operands[1], BLKmode, 0);
6423 [(set (match_operand:BLK 0 "memory_operand" "")
6424 (and:BLK (match_dup 0)
6425 (match_operand:BLK 1 "memory_operand" "")))
6426 (use (match_operand 2 "const_int_operand" ""))
6427 (clobber (reg:CC CC_REGNUM))])
6429 [(set (match_operand:BLK 3 "memory_operand" "")
6430 (and:BLK (match_dup 3)
6431 (match_operand:BLK 4 "memory_operand" "")))
6432 (use (match_operand 5 "const_int_operand" ""))
6433 (clobber (reg:CC CC_REGNUM))])]
6434 "s390_offset_p (operands[0], operands[3], operands[2])
6435 && s390_offset_p (operands[1], operands[4], operands[2])
6436 && !s390_overlap_p (operands[0], operands[1],
6437 INTVAL (operands[2]) + INTVAL (operands[5]))
6438 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6440 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6442 (clobber (reg:CC CC_REGNUM))])]
6443 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6444 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6445 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6449 ;;- Bit set (inclusive or) instructions.
6452 (define_expand "ior<mode>3"
6453 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6454 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6455 (match_operand:INT 2 "general_operand" "")))
6456 (clobber (reg:CC CC_REGNUM))]
6458 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6461 ; iordi3 instruction pattern(s).
6464 (define_insn "*iordi3_cc"
6465 [(set (reg CC_REGNUM)
6466 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6467 (match_operand:DI 2 "general_operand" " d,d,RT"))
6469 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6470 (ior:DI (match_dup 1) (match_dup 2)))]
6471 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6476 [(set_attr "op_type" "RRE,RRF,RXY")
6477 (set_attr "cpu_facility" "*,z196,*")
6478 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6480 (define_insn "*iordi3_cconly"
6481 [(set (reg CC_REGNUM)
6482 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6483 (match_operand:DI 2 "general_operand" " d,d,RT"))
6485 (clobber (match_scratch:DI 0 "=d,d,d"))]
6486 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6491 [(set_attr "op_type" "RRE,RRF,RXY")
6492 (set_attr "cpu_facility" "*,z196,*")
6493 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6495 (define_insn "*iordi3"
6496 [(set (match_operand:DI 0 "nonimmediate_operand"
6497 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6498 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6499 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6500 (match_operand:DI 2 "general_operand"
6501 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6502 (clobber (reg:CC CC_REGNUM))]
6503 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6516 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6517 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6518 (set_attr "z10prop" "z10_super_E1,
6531 [(set (match_operand:DI 0 "s_operand" "")
6532 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6533 (clobber (reg:CC CC_REGNUM))]
6536 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6537 (clobber (reg:CC CC_REGNUM))])]
6538 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6541 ; iorsi3 instruction pattern(s).
6544 (define_insn "*iorsi3_cc"
6545 [(set (reg CC_REGNUM)
6546 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6547 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6549 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6550 (ior:SI (match_dup 1) (match_dup 2)))]
6551 "s390_match_ccmode(insn, CCTmode)"
6558 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6559 (set_attr "cpu_facility" "*,*,z196,*,*")
6560 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6562 (define_insn "*iorsi3_cconly"
6563 [(set (reg CC_REGNUM)
6564 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6565 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6567 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6568 "s390_match_ccmode(insn, CCTmode)"
6575 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6576 (set_attr "cpu_facility" "*,*,z196,*,*")
6577 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6579 (define_insn "*iorsi3_zarch"
6580 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6581 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6582 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6583 (clobber (reg:CC CC_REGNUM))]
6584 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6595 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6596 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6597 (set_attr "z10prop" "z10_super_E1,
6607 (define_insn "*iorsi3_esa"
6608 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6609 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6610 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6611 (clobber (reg:CC CC_REGNUM))]
6612 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6618 [(set_attr "op_type" "RR,RX,SI,SS")
6619 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6622 [(set (match_operand:SI 0 "s_operand" "")
6623 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6624 (clobber (reg:CC CC_REGNUM))]
6627 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6628 (clobber (reg:CC CC_REGNUM))])]
6629 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6632 ; iorhi3 instruction pattern(s).
6635 (define_insn "*iorhi3_zarch"
6636 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6637 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6638 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6639 (clobber (reg:CC CC_REGNUM))]
6640 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6647 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6648 (set_attr "cpu_facility" "*,z196,*,*,*")
6649 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6651 (define_insn "*iorhi3_esa"
6652 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6653 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6654 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6655 (clobber (reg:CC CC_REGNUM))]
6656 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6661 [(set_attr "op_type" "RR,SI,SS")
6662 (set_attr "z10prop" "z10_super_E1,*,*")])
6665 [(set (match_operand:HI 0 "s_operand" "")
6666 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6667 (clobber (reg:CC CC_REGNUM))]
6670 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6671 (clobber (reg:CC CC_REGNUM))])]
6672 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6675 ; iorqi3 instruction pattern(s).
6678 (define_insn "*iorqi3_zarch"
6679 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6680 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6681 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6682 (clobber (reg:CC CC_REGNUM))]
6683 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6691 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6692 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6693 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6694 z10_super,z10_super,*")])
6696 (define_insn "*iorqi3_esa"
6697 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6698 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6699 (match_operand:QI 2 "general_operand" "d,n,Q")))
6700 (clobber (reg:CC CC_REGNUM))]
6701 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6706 [(set_attr "op_type" "RR,SI,SS")
6707 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6710 ; Block inclusive or (OC) patterns.
6714 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6715 (ior:BLK (match_dup 0)
6716 (match_operand:BLK 1 "memory_operand" "Q")))
6717 (use (match_operand 2 "const_int_operand" "n"))
6718 (clobber (reg:CC CC_REGNUM))]
6719 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6720 "oc\t%O0(%2,%R0),%S1"
6721 [(set_attr "op_type" "SS")
6722 (set_attr "z196prop" "z196_cracked")])
6725 [(set (match_operand 0 "memory_operand" "")
6727 (match_operand 1 "memory_operand" "")))
6728 (clobber (reg:CC CC_REGNUM))]
6730 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6731 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6733 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6735 (clobber (reg:CC CC_REGNUM))])]
6737 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6738 operands[0] = adjust_address (operands[0], BLKmode, 0);
6739 operands[1] = adjust_address (operands[1], BLKmode, 0);
6744 [(set (match_operand:BLK 0 "memory_operand" "")
6745 (ior:BLK (match_dup 0)
6746 (match_operand:BLK 1 "memory_operand" "")))
6747 (use (match_operand 2 "const_int_operand" ""))
6748 (clobber (reg:CC CC_REGNUM))])
6750 [(set (match_operand:BLK 3 "memory_operand" "")
6751 (ior:BLK (match_dup 3)
6752 (match_operand:BLK 4 "memory_operand" "")))
6753 (use (match_operand 5 "const_int_operand" ""))
6754 (clobber (reg:CC CC_REGNUM))])]
6755 "s390_offset_p (operands[0], operands[3], operands[2])
6756 && s390_offset_p (operands[1], operands[4], operands[2])
6757 && !s390_overlap_p (operands[0], operands[1],
6758 INTVAL (operands[2]) + INTVAL (operands[5]))
6759 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6761 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6763 (clobber (reg:CC CC_REGNUM))])]
6764 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6765 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6766 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6770 ;;- Xor instructions.
6773 (define_expand "xor<mode>3"
6774 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6775 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6776 (match_operand:INT 2 "general_operand" "")))
6777 (clobber (reg:CC CC_REGNUM))]
6779 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6782 ; xordi3 instruction pattern(s).
6785 (define_insn "*xordi3_cc"
6786 [(set (reg CC_REGNUM)
6787 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6788 (match_operand:DI 2 "general_operand" " d,d,RT"))
6790 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6791 (xor:DI (match_dup 1) (match_dup 2)))]
6792 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6797 [(set_attr "op_type" "RRE,RRF,RXY")
6798 (set_attr "cpu_facility" "*,z196,*")
6799 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6801 (define_insn "*xordi3_cconly"
6802 [(set (reg CC_REGNUM)
6803 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6804 (match_operand:DI 2 "general_operand" " d,d,RT"))
6806 (clobber (match_scratch:DI 0 "=d,d, d"))]
6807 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6812 [(set_attr "op_type" "RRE,RRF,RXY")
6813 (set_attr "cpu_facility" "*,z196,*")
6814 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6816 (define_insn "*xordi3"
6817 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6818 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6819 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6820 (clobber (reg:CC CC_REGNUM))]
6821 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6830 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6831 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6832 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6833 *,z10_super_E1,*,*")])
6836 [(set (match_operand:DI 0 "s_operand" "")
6837 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6838 (clobber (reg:CC CC_REGNUM))]
6841 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6842 (clobber (reg:CC CC_REGNUM))])]
6843 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6846 ; xorsi3 instruction pattern(s).
6849 (define_insn "*xorsi3_cc"
6850 [(set (reg CC_REGNUM)
6851 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6852 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6854 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6855 (xor:SI (match_dup 1) (match_dup 2)))]
6856 "s390_match_ccmode(insn, CCTmode)"
6863 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6864 (set_attr "cpu_facility" "*,*,z196,*,*")
6865 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6866 z10_super_E1,z10_super_E1")])
6868 (define_insn "*xorsi3_cconly"
6869 [(set (reg CC_REGNUM)
6870 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6871 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6873 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6874 "s390_match_ccmode(insn, CCTmode)"
6881 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6882 (set_attr "cpu_facility" "*,*,z196,*,*")
6883 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6884 z10_super_E1,z10_super_E1")])
6886 (define_insn "*xorsi3"
6887 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6888 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6889 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6890 (clobber (reg:CC CC_REGNUM))]
6891 "s390_logical_operator_ok_p (operands)"
6900 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6901 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6902 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6903 z10_super_E1,z10_super_E1,*,*")])
6906 [(set (match_operand:SI 0 "s_operand" "")
6907 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6908 (clobber (reg:CC CC_REGNUM))]
6911 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6912 (clobber (reg:CC CC_REGNUM))])]
6913 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6916 ; xorhi3 instruction pattern(s).
6919 (define_insn "*xorhi3"
6920 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6921 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6922 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6923 (clobber (reg:CC CC_REGNUM))]
6924 "s390_logical_operator_ok_p (operands)"
6931 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6932 (set_attr "cpu_facility" "*,*,z196,*,*")
6933 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6936 [(set (match_operand:HI 0 "s_operand" "")
6937 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6938 (clobber (reg:CC CC_REGNUM))]
6941 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6942 (clobber (reg:CC CC_REGNUM))])]
6943 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6946 ; xorqi3 instruction pattern(s).
6949 (define_insn "*xorqi3"
6950 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6951 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
6952 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
6953 (clobber (reg:CC CC_REGNUM))]
6954 "s390_logical_operator_ok_p (operands)"
6962 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
6963 (set_attr "cpu_facility" "*,*,z196,*,*,*")
6964 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
6968 ; Block exclusive or (XC) patterns.
6972 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6973 (xor:BLK (match_dup 0)
6974 (match_operand:BLK 1 "memory_operand" "Q")))
6975 (use (match_operand 2 "const_int_operand" "n"))
6976 (clobber (reg:CC CC_REGNUM))]
6977 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6978 "xc\t%O0(%2,%R0),%S1"
6979 [(set_attr "op_type" "SS")])
6982 [(set (match_operand 0 "memory_operand" "")
6984 (match_operand 1 "memory_operand" "")))
6985 (clobber (reg:CC CC_REGNUM))]
6987 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6988 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6990 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6992 (clobber (reg:CC CC_REGNUM))])]
6994 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6995 operands[0] = adjust_address (operands[0], BLKmode, 0);
6996 operands[1] = adjust_address (operands[1], BLKmode, 0);
7001 [(set (match_operand:BLK 0 "memory_operand" "")
7002 (xor:BLK (match_dup 0)
7003 (match_operand:BLK 1 "memory_operand" "")))
7004 (use (match_operand 2 "const_int_operand" ""))
7005 (clobber (reg:CC CC_REGNUM))])
7007 [(set (match_operand:BLK 3 "memory_operand" "")
7008 (xor:BLK (match_dup 3)
7009 (match_operand:BLK 4 "memory_operand" "")))
7010 (use (match_operand 5 "const_int_operand" ""))
7011 (clobber (reg:CC CC_REGNUM))])]
7012 "s390_offset_p (operands[0], operands[3], operands[2])
7013 && s390_offset_p (operands[1], operands[4], operands[2])
7014 && !s390_overlap_p (operands[0], operands[1],
7015 INTVAL (operands[2]) + INTVAL (operands[5]))
7016 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7018 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7020 (clobber (reg:CC CC_REGNUM))])]
7021 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7022 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7023 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7026 ; Block xor (XC) patterns with src == dest.
7029 (define_insn "*xc_zero"
7030 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7032 (use (match_operand 1 "const_int_operand" "n"))
7033 (clobber (reg:CC CC_REGNUM))]
7034 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7035 "xc\t%O0(%1,%R0),%S0"
7036 [(set_attr "op_type" "SS")
7037 (set_attr "z196prop" "z196_cracked")])
7041 [(set (match_operand:BLK 0 "memory_operand" "")
7043 (use (match_operand 1 "const_int_operand" ""))
7044 (clobber (reg:CC CC_REGNUM))])
7046 [(set (match_operand:BLK 2 "memory_operand" "")
7048 (use (match_operand 3 "const_int_operand" ""))
7049 (clobber (reg:CC CC_REGNUM))])]
7050 "s390_offset_p (operands[0], operands[2], operands[1])
7051 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7053 [(set (match_dup 4) (const_int 0))
7055 (clobber (reg:CC CC_REGNUM))])]
7056 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7057 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7061 ;;- Negate instructions.
7065 ; neg(di|si)2 instruction pattern(s).
7068 (define_expand "neg<mode>2"
7070 [(set (match_operand:DSI 0 "register_operand" "=d")
7071 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7072 (clobber (reg:CC CC_REGNUM))])]
7076 (define_insn "*negdi2_sign_cc"
7077 [(set (reg CC_REGNUM)
7078 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7079 (match_operand:SI 1 "register_operand" "d") 0)
7080 (const_int 32)) (const_int 32)))
7082 (set (match_operand:DI 0 "register_operand" "=d")
7083 (neg:DI (sign_extend:DI (match_dup 1))))]
7084 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7086 [(set_attr "op_type" "RRE")
7087 (set_attr "z10prop" "z10_c")])
7089 (define_insn "*negdi2_sign"
7090 [(set (match_operand:DI 0 "register_operand" "=d")
7091 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7092 (clobber (reg:CC CC_REGNUM))]
7095 [(set_attr "op_type" "RRE")
7096 (set_attr "z10prop" "z10_c")])
7099 (define_insn "*neg<mode>2_cc"
7100 [(set (reg CC_REGNUM)
7101 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7103 (set (match_operand:GPR 0 "register_operand" "=d")
7104 (neg:GPR (match_dup 1)))]
7105 "s390_match_ccmode (insn, CCAmode)"
7107 [(set_attr "op_type" "RR<E>")
7108 (set_attr "z10prop" "z10_super_c_E1")])
7111 (define_insn "*neg<mode>2_cconly"
7112 [(set (reg CC_REGNUM)
7113 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7115 (clobber (match_scratch:GPR 0 "=d"))]
7116 "s390_match_ccmode (insn, CCAmode)"
7118 [(set_attr "op_type" "RR<E>")
7119 (set_attr "z10prop" "z10_super_c_E1")])
7122 (define_insn "*neg<mode>2"
7123 [(set (match_operand:GPR 0 "register_operand" "=d")
7124 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7125 (clobber (reg:CC CC_REGNUM))]
7128 [(set_attr "op_type" "RR<E>")
7129 (set_attr "z10prop" "z10_super_c_E1")])
7131 (define_insn_and_split "*negdi2_31"
7132 [(set (match_operand:DI 0 "register_operand" "=d")
7133 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7134 (clobber (reg:CC CC_REGNUM))]
7137 "&& reload_completed"
7139 [(set (match_dup 2) (neg:SI (match_dup 3)))
7140 (clobber (reg:CC CC_REGNUM))])
7142 [(set (reg:CCAP CC_REGNUM)
7143 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7144 (set (match_dup 4) (neg:SI (match_dup 5)))])
7146 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7148 (label_ref (match_dup 6))))
7150 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7151 (clobber (reg:CC CC_REGNUM))])
7153 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7154 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7155 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7156 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7157 operands[6] = gen_label_rtx ();")
7160 ; neg(df|sf)2 instruction pattern(s).
7163 (define_expand "neg<mode>2"
7165 [(set (match_operand:BFP 0 "register_operand" "=f")
7166 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7167 (clobber (reg:CC CC_REGNUM))])]
7171 ; lcxbr, lcdbr, lcebr
7172 (define_insn "*neg<mode>2_cc"
7173 [(set (reg CC_REGNUM)
7174 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7175 (match_operand:BFP 2 "const0_operand" "")))
7176 (set (match_operand:BFP 0 "register_operand" "=f")
7177 (neg:BFP (match_dup 1)))]
7178 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7180 [(set_attr "op_type" "RRE")
7181 (set_attr "type" "fsimp<mode>")])
7183 ; lcxbr, lcdbr, lcebr
7184 (define_insn "*neg<mode>2_cconly"
7185 [(set (reg CC_REGNUM)
7186 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7187 (match_operand:BFP 2 "const0_operand" "")))
7188 (clobber (match_scratch:BFP 0 "=f"))]
7189 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7191 [(set_attr "op_type" "RRE")
7192 (set_attr "type" "fsimp<mode>")])
7195 (define_insn "*neg<mode>2_nocc"
7196 [(set (match_operand:FP 0 "register_operand" "=f")
7197 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7200 [(set_attr "op_type" "RRE")
7201 (set_attr "type" "fsimp<mode>")])
7203 ; lcxbr, lcdbr, lcebr
7204 (define_insn "*neg<mode>2"
7205 [(set (match_operand:BFP 0 "register_operand" "=f")
7206 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7207 (clobber (reg:CC CC_REGNUM))]
7210 [(set_attr "op_type" "RRE")
7211 (set_attr "type" "fsimp<mode>")])
7215 ;;- Absolute value instructions.
7219 ; abs(di|si)2 instruction pattern(s).
7222 (define_insn "*absdi2_sign_cc"
7223 [(set (reg CC_REGNUM)
7224 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7225 (match_operand:SI 1 "register_operand" "d") 0)
7226 (const_int 32)) (const_int 32)))
7228 (set (match_operand:DI 0 "register_operand" "=d")
7229 (abs:DI (sign_extend:DI (match_dup 1))))]
7230 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7232 [(set_attr "op_type" "RRE")
7233 (set_attr "z10prop" "z10_c")])
7235 (define_insn "*absdi2_sign"
7236 [(set (match_operand:DI 0 "register_operand" "=d")
7237 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7238 (clobber (reg:CC CC_REGNUM))]
7241 [(set_attr "op_type" "RRE")
7242 (set_attr "z10prop" "z10_c")])
7245 (define_insn "*abs<mode>2_cc"
7246 [(set (reg CC_REGNUM)
7247 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7249 (set (match_operand:GPR 0 "register_operand" "=d")
7250 (abs:GPR (match_dup 1)))]
7251 "s390_match_ccmode (insn, CCAmode)"
7253 [(set_attr "op_type" "RR<E>")
7254 (set_attr "z10prop" "z10_c")])
7257 (define_insn "*abs<mode>2_cconly"
7258 [(set (reg CC_REGNUM)
7259 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7261 (clobber (match_scratch:GPR 0 "=d"))]
7262 "s390_match_ccmode (insn, CCAmode)"
7264 [(set_attr "op_type" "RR<E>")
7265 (set_attr "z10prop" "z10_c")])
7268 (define_insn "abs<mode>2"
7269 [(set (match_operand:GPR 0 "register_operand" "=d")
7270 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7271 (clobber (reg:CC CC_REGNUM))]
7274 [(set_attr "op_type" "RR<E>")
7275 (set_attr "z10prop" "z10_c")])
7278 ; abs(df|sf)2 instruction pattern(s).
7281 (define_expand "abs<mode>2"
7283 [(set (match_operand:BFP 0 "register_operand" "=f")
7284 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7285 (clobber (reg:CC CC_REGNUM))])]
7289 ; lpxbr, lpdbr, lpebr
7290 (define_insn "*abs<mode>2_cc"
7291 [(set (reg CC_REGNUM)
7292 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7293 (match_operand:BFP 2 "const0_operand" "")))
7294 (set (match_operand:BFP 0 "register_operand" "=f")
7295 (abs:BFP (match_dup 1)))]
7296 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7298 [(set_attr "op_type" "RRE")
7299 (set_attr "type" "fsimp<mode>")])
7301 ; lpxbr, lpdbr, lpebr
7302 (define_insn "*abs<mode>2_cconly"
7303 [(set (reg CC_REGNUM)
7304 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7305 (match_operand:BFP 2 "const0_operand" "")))
7306 (clobber (match_scratch:BFP 0 "=f"))]
7307 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7309 [(set_attr "op_type" "RRE")
7310 (set_attr "type" "fsimp<mode>")])
7313 (define_insn "*abs<mode>2_nocc"
7314 [(set (match_operand:FP 0 "register_operand" "=f")
7315 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7318 [(set_attr "op_type" "RRE")
7319 (set_attr "type" "fsimp<mode>")])
7321 ; lpxbr, lpdbr, lpebr
7322 (define_insn "*abs<mode>2"
7323 [(set (match_operand:BFP 0 "register_operand" "=f")
7324 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7325 (clobber (reg:CC CC_REGNUM))]
7328 [(set_attr "op_type" "RRE")
7329 (set_attr "type" "fsimp<mode>")])
7333 ;;- Negated absolute value instructions
7340 (define_insn "*negabsdi2_sign_cc"
7341 [(set (reg CC_REGNUM)
7342 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7343 (match_operand:SI 1 "register_operand" "d") 0)
7344 (const_int 32)) (const_int 32))))
7346 (set (match_operand:DI 0 "register_operand" "=d")
7347 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7348 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7350 [(set_attr "op_type" "RRE")
7351 (set_attr "z10prop" "z10_c")])
7353 (define_insn "*negabsdi2_sign"
7354 [(set (match_operand:DI 0 "register_operand" "=d")
7355 (neg:DI (abs:DI (sign_extend:DI
7356 (match_operand:SI 1 "register_operand" "d")))))
7357 (clobber (reg:CC CC_REGNUM))]
7360 [(set_attr "op_type" "RRE")
7361 (set_attr "z10prop" "z10_c")])
7364 (define_insn "*negabs<mode>2_cc"
7365 [(set (reg CC_REGNUM)
7366 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7368 (set (match_operand:GPR 0 "register_operand" "=d")
7369 (neg:GPR (abs:GPR (match_dup 1))))]
7370 "s390_match_ccmode (insn, CCAmode)"
7372 [(set_attr "op_type" "RR<E>")
7373 (set_attr "z10prop" "z10_c")])
7376 (define_insn "*negabs<mode>2_cconly"
7377 [(set (reg CC_REGNUM)
7378 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7380 (clobber (match_scratch:GPR 0 "=d"))]
7381 "s390_match_ccmode (insn, CCAmode)"
7383 [(set_attr "op_type" "RR<E>")
7384 (set_attr "z10prop" "z10_c")])
7387 (define_insn "*negabs<mode>2"
7388 [(set (match_operand:GPR 0 "register_operand" "=d")
7389 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7390 (clobber (reg:CC CC_REGNUM))]
7393 [(set_attr "op_type" "RR<E>")
7394 (set_attr "z10prop" "z10_c")])
7400 ; lnxbr, lndbr, lnebr
7401 (define_insn "*negabs<mode>2_cc"
7402 [(set (reg CC_REGNUM)
7403 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7404 (match_operand:BFP 2 "const0_operand" "")))
7405 (set (match_operand:BFP 0 "register_operand" "=f")
7406 (neg:BFP (abs:BFP (match_dup 1))))]
7407 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7409 [(set_attr "op_type" "RRE")
7410 (set_attr "type" "fsimp<mode>")])
7412 ; lnxbr, lndbr, lnebr
7413 (define_insn "*negabs<mode>2_cconly"
7414 [(set (reg CC_REGNUM)
7415 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7416 (match_operand:BFP 2 "const0_operand" "")))
7417 (clobber (match_scratch:BFP 0 "=f"))]
7418 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7420 [(set_attr "op_type" "RRE")
7421 (set_attr "type" "fsimp<mode>")])
7424 (define_insn "*negabs<mode>2_nocc"
7425 [(set (match_operand:FP 0 "register_operand" "=f")
7426 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7429 [(set_attr "op_type" "RRE")
7430 (set_attr "type" "fsimp<mode>")])
7432 ; lnxbr, lndbr, lnebr
7433 (define_insn "*negabs<mode>2"
7434 [(set (match_operand:BFP 0 "register_operand" "=f")
7435 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7436 (clobber (reg:CC CC_REGNUM))]
7439 [(set_attr "op_type" "RRE")
7440 (set_attr "type" "fsimp<mode>")])
7443 ;;- Square root instructions.
7447 ; sqrt(df|sf)2 instruction pattern(s).
7450 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7451 (define_insn "sqrt<mode>2"
7452 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7453 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7458 [(set_attr "op_type" "RRE,RXE")
7459 (set_attr "type" "fsqrt<mode>")])
7463 ;;- One complement instructions.
7467 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7470 (define_expand "one_cmpl<mode>2"
7472 [(set (match_operand:INT 0 "register_operand" "")
7473 (xor:INT (match_operand:INT 1 "register_operand" "")
7475 (clobber (reg:CC CC_REGNUM))])]
7481 ;; Find leftmost bit instructions.
7484 (define_expand "clzdi2"
7485 [(set (match_operand:DI 0 "register_operand" "=d")
7486 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7487 "TARGET_EXTIMM && TARGET_ZARCH"
7489 rtx insn, clz_equal;
7490 rtx wide_reg = gen_reg_rtx (TImode);
7491 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7493 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7495 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7497 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7498 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7503 (define_insn "clztidi2"
7504 [(set (match_operand:TI 0 "register_operand" "=d")
7508 (xor:DI (match_operand:DI 1 "register_operand" "d")
7509 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7510 (subreg:SI (clz:DI (match_dup 1)) 4))))
7513 (zero_extend:TI (clz:DI (match_dup 1)))))
7514 (clobber (reg:CC CC_REGNUM))]
7515 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7516 == (unsigned HOST_WIDE_INT) 1 << 63
7517 && TARGET_EXTIMM && TARGET_ZARCH"
7519 [(set_attr "op_type" "RRE")])
7523 ;;- Rotate instructions.
7527 ; rotl(di|si)3 instruction pattern(s).
7531 (define_insn "rotl<mode>3"
7532 [(set (match_operand:GPR 0 "register_operand" "=d")
7533 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7534 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7537 [(set_attr "op_type" "RSE")
7538 (set_attr "atype" "reg")
7539 (set_attr "z10prop" "z10_super_E1")])
7542 (define_insn "*rotl<mode>3_and"
7543 [(set (match_operand:GPR 0 "register_operand" "=d")
7544 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7545 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7546 (match_operand:SI 3 "const_int_operand" "n"))))]
7547 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7549 [(set_attr "op_type" "RSE")
7550 (set_attr "atype" "reg")
7551 (set_attr "z10prop" "z10_super_E1")])
7555 ;;- Shift instructions.
7559 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7560 ; Left shifts and logical right shifts
7562 (define_expand "<shift><mode>3"
7563 [(set (match_operand:DSI 0 "register_operand" "")
7564 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7565 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7570 (define_insn "*<shift>di3_31"
7571 [(set (match_operand:DI 0 "register_operand" "=d")
7572 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7573 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7576 [(set_attr "op_type" "RS")
7577 (set_attr "atype" "reg")
7578 (set_attr "z196prop" "z196_cracked")])
7580 ; sll, srl, sllg, srlg, sllk, srlk
7581 (define_insn "*<shift><mode>3"
7582 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7583 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7584 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7587 s<lr>l<g>\t%0,<1>%Y2
7588 s<lr>l<gk>\t%0,%1,%Y2"
7589 [(set_attr "op_type" "RS<E>,RSY")
7590 (set_attr "atype" "reg,reg")
7591 (set_attr "cpu_facility" "*,z196")
7592 (set_attr "z10prop" "z10_super_E1,*")])
7595 (define_insn "*<shift>di3_31_and"
7596 [(set (match_operand:DI 0 "register_operand" "=d")
7597 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7598 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7599 (match_operand:SI 3 "const_int_operand" "n"))))]
7600 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7602 [(set_attr "op_type" "RS")
7603 (set_attr "atype" "reg")])
7605 ; sll, srl, sllg, srlg, sllk, srlk
7606 (define_insn "*<shift><mode>3_and"
7607 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7608 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7609 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7610 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7611 "(INTVAL (operands[3]) & 63) == 63"
7613 s<lr>l<g>\t%0,<1>%Y2
7614 s<lr>l<gk>\t%0,%1,%Y2"
7615 [(set_attr "op_type" "RS<E>,RSY")
7616 (set_attr "atype" "reg,reg")
7617 (set_attr "cpu_facility" "*,z196")
7618 (set_attr "z10prop" "z10_super_E1,*")])
7621 ; ashr(di|si)3 instruction pattern(s).
7622 ; Arithmetic right shifts
7624 (define_expand "ashr<mode>3"
7626 [(set (match_operand:DSI 0 "register_operand" "")
7627 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7628 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7629 (clobber (reg:CC CC_REGNUM))])]
7633 (define_insn "*ashrdi3_cc_31"
7634 [(set (reg CC_REGNUM)
7635 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7636 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7638 (set (match_operand:DI 0 "register_operand" "=d")
7639 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7640 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7642 [(set_attr "op_type" "RS")
7643 (set_attr "atype" "reg")])
7645 (define_insn "*ashrdi3_cconly_31"
7646 [(set (reg CC_REGNUM)
7647 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7648 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7650 (clobber (match_scratch:DI 0 "=d"))]
7651 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7653 [(set_attr "op_type" "RS")
7654 (set_attr "atype" "reg")])
7656 (define_insn "*ashrdi3_31"
7657 [(set (match_operand:DI 0 "register_operand" "=d")
7658 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7659 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7660 (clobber (reg:CC CC_REGNUM))]
7663 [(set_attr "op_type" "RS")
7664 (set_attr "atype" "reg")])
7667 (define_insn "*ashr<mode>3_cc"
7668 [(set (reg CC_REGNUM)
7669 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7670 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7672 (set (match_operand:GPR 0 "register_operand" "=d,d")
7673 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7674 "s390_match_ccmode(insn, CCSmode)"
7678 [(set_attr "op_type" "RS<E>,RSY")
7679 (set_attr "atype" "reg,reg")
7680 (set_attr "cpu_facility" "*,z196")
7681 (set_attr "z10prop" "z10_super_E1,*")])
7684 (define_insn "*ashr<mode>3_cconly"
7685 [(set (reg CC_REGNUM)
7686 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7687 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7689 (clobber (match_scratch:GPR 0 "=d,d"))]
7690 "s390_match_ccmode(insn, CCSmode)"
7694 [(set_attr "op_type" "RS<E>,RSY")
7695 (set_attr "atype" "reg,reg")
7696 (set_attr "cpu_facility" "*,z196")
7697 (set_attr "z10prop" "z10_super_E1,*")])
7700 (define_insn "*ashr<mode>3"
7701 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7702 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7703 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7704 (clobber (reg:CC CC_REGNUM))]
7709 [(set_attr "op_type" "RS<E>,RSY")
7710 (set_attr "atype" "reg,reg")
7711 (set_attr "cpu_facility" "*,z196")
7712 (set_attr "z10prop" "z10_super_E1,*")])
7715 ; shift pattern with implicit ANDs
7717 (define_insn "*ashrdi3_cc_31_and"
7718 [(set (reg CC_REGNUM)
7719 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7720 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7721 (match_operand:SI 3 "const_int_operand" "n")))
7723 (set (match_operand:DI 0 "register_operand" "=d")
7724 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7725 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7726 && (INTVAL (operands[3]) & 63) == 63"
7728 [(set_attr "op_type" "RS")
7729 (set_attr "atype" "reg")])
7731 (define_insn "*ashrdi3_cconly_31_and"
7732 [(set (reg CC_REGNUM)
7733 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7734 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7735 (match_operand:SI 3 "const_int_operand" "n")))
7737 (clobber (match_scratch:DI 0 "=d"))]
7738 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7739 && (INTVAL (operands[3]) & 63) == 63"
7741 [(set_attr "op_type" "RS")
7742 (set_attr "atype" "reg")])
7744 (define_insn "*ashrdi3_31_and"
7745 [(set (match_operand:DI 0 "register_operand" "=d")
7746 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7747 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7748 (match_operand:SI 3 "const_int_operand" "n"))))
7749 (clobber (reg:CC CC_REGNUM))]
7750 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7752 [(set_attr "op_type" "RS")
7753 (set_attr "atype" "reg")])
7756 (define_insn "*ashr<mode>3_cc_and"
7757 [(set (reg CC_REGNUM)
7758 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7759 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7760 (match_operand:SI 3 "const_int_operand" "n,n")))
7762 (set (match_operand:GPR 0 "register_operand" "=d,d")
7763 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7764 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7768 [(set_attr "op_type" "RS<E>,RSY")
7769 (set_attr "atype" "reg,reg")
7770 (set_attr "cpu_facility" "*,z196")
7771 (set_attr "z10prop" "z10_super_E1,*")])
7774 (define_insn "*ashr<mode>3_cconly_and"
7775 [(set (reg CC_REGNUM)
7776 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7777 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7778 (match_operand:SI 3 "const_int_operand" "n,n")))
7780 (clobber (match_scratch:GPR 0 "=d,d"))]
7781 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7785 [(set_attr "op_type" "RS<E>,RSY")
7786 (set_attr "atype" "reg,reg")
7787 (set_attr "cpu_facility" "*,z196")
7788 (set_attr "z10prop" "z10_super_E1,*")])
7791 (define_insn "*ashr<mode>3_and"
7792 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7793 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7794 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7795 (match_operand:SI 3 "const_int_operand" "n,n"))))
7796 (clobber (reg:CC CC_REGNUM))]
7797 "(INTVAL (operands[3]) & 63) == 63"
7801 [(set_attr "op_type" "RS<E>,RSY")
7802 (set_attr "atype" "reg,reg")
7803 (set_attr "cpu_facility" "*,z196")
7804 (set_attr "z10prop" "z10_super_E1,*")])
7808 ;; Branch instruction patterns.
7811 (define_expand "cbranch<mode>4"
7813 (if_then_else (match_operator 0 "comparison_operator"
7814 [(match_operand:GPR 1 "register_operand" "")
7815 (match_operand:GPR 2 "general_operand" "")])
7816 (label_ref (match_operand 3 "" ""))
7819 "s390_emit_jump (operands[3],
7820 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7823 (define_expand "cbranch<mode>4"
7825 (if_then_else (match_operator 0 "comparison_operator"
7826 [(match_operand:FP 1 "register_operand" "")
7827 (match_operand:FP 2 "general_operand" "")])
7828 (label_ref (match_operand 3 "" ""))
7831 "s390_emit_jump (operands[3],
7832 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7835 (define_expand "cbranchcc4"
7837 (if_then_else (match_operator 0 "s390_eqne_operator"
7838 [(match_operand 1 "cc_reg_operand" "")
7839 (match_operand 2 "const0_operand" "")])
7840 (label_ref (match_operand 3 "" ""))
7843 "s390_emit_jump (operands[3],
7844 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7850 ;;- Conditional jump instructions.
7853 (define_insn "*cjump_64"
7856 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7857 (label_ref (match_operand 0 "" ""))
7861 if (get_attr_length (insn) == 4)
7864 return "jg%C1\t%l0";
7866 [(set_attr "op_type" "RI")
7867 (set_attr "type" "branch")
7868 (set (attr "length")
7869 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7870 (const_int 4) (const_int 6)))])
7872 (define_insn "*cjump_31"
7875 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7876 (label_ref (match_operand 0 "" ""))
7880 gcc_assert (get_attr_length (insn) == 4);
7883 [(set_attr "op_type" "RI")
7884 (set_attr "type" "branch")
7885 (set (attr "length")
7886 (if_then_else (not (match_test "flag_pic"))
7887 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7888 (const_int 4) (const_int 6))
7889 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7890 (const_int 4) (const_int 8))))])
7892 (define_insn "*cjump_long"
7895 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7896 (match_operand 0 "address_operand" "ZQZR")
7900 if (get_attr_op_type (insn) == OP_TYPE_RR)
7905 [(set (attr "op_type")
7906 (if_then_else (match_operand 0 "register_operand" "")
7907 (const_string "RR") (const_string "RX")))
7908 (set_attr "type" "branch")
7909 (set_attr "atype" "agen")])
7913 ;;- Negated conditional jump instructions.
7916 (define_insn "*icjump_64"
7919 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7921 (label_ref (match_operand 0 "" ""))))]
7924 if (get_attr_length (insn) == 4)
7927 return "jg%D1\t%l0";
7929 [(set_attr "op_type" "RI")
7930 (set_attr "type" "branch")
7931 (set (attr "length")
7932 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7933 (const_int 4) (const_int 6)))])
7935 (define_insn "*icjump_31"
7938 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7940 (label_ref (match_operand 0 "" ""))))]
7943 gcc_assert (get_attr_length (insn) == 4);
7946 [(set_attr "op_type" "RI")
7947 (set_attr "type" "branch")
7948 (set (attr "length")
7949 (if_then_else (not (match_test "flag_pic"))
7950 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7951 (const_int 4) (const_int 6))
7952 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7953 (const_int 4) (const_int 8))))])
7955 (define_insn "*icjump_long"
7958 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7960 (match_operand 0 "address_operand" "ZQZR")))]
7963 if (get_attr_op_type (insn) == OP_TYPE_RR)
7968 [(set (attr "op_type")
7969 (if_then_else (match_operand 0 "register_operand" "")
7970 (const_string "RR") (const_string "RX")))
7971 (set_attr "type" "branch")
7972 (set_attr "atype" "agen")])
7975 ;;- Trap instructions.
7979 [(trap_if (const_int 1) (const_int 0))]
7982 [(set_attr "op_type" "RI")
7983 (set_attr "type" "branch")])
7985 (define_expand "ctrap<mode>4"
7986 [(trap_if (match_operator 0 "comparison_operator"
7987 [(match_operand:GPR 1 "register_operand" "")
7988 (match_operand:GPR 2 "general_operand" "")])
7989 (match_operand 3 "const0_operand" ""))]
7992 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7993 operands[1], operands[2]);
7994 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7998 (define_expand "ctrap<mode>4"
7999 [(trap_if (match_operator 0 "comparison_operator"
8000 [(match_operand:FP 1 "register_operand" "")
8001 (match_operand:FP 2 "general_operand" "")])
8002 (match_operand 3 "const0_operand" ""))]
8005 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8006 operands[1], operands[2]);
8007 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8011 (define_insn "condtrap"
8012 [(trap_if (match_operator 0 "s390_comparison"
8013 [(match_operand 1 "cc_reg_operand" "c")
8018 [(set_attr "op_type" "RI")
8019 (set_attr "type" "branch")])
8021 ; crt, cgrt, cit, cgit
8022 (define_insn "*cmp_and_trap_signed_int<mode>"
8023 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8024 [(match_operand:GPR 1 "register_operand" "d,d")
8025 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8031 [(set_attr "op_type" "RRF,RIE")
8032 (set_attr "type" "branch")
8033 (set_attr "z10prop" "z10_super_c,z10_super")])
8035 ; clrt, clgrt, clfit, clgit, clt, clgt
8036 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8037 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8038 [(match_operand:GPR 1 "register_operand" "d,d, d")
8039 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8046 [(set_attr "op_type" "RRF,RIE,RSY")
8047 (set_attr "type" "branch")
8048 (set_attr "z10prop" "z10_super_c,z10_super,*")
8049 (set_attr "cpu_facility" "z10,z10,zEC12")])
8052 (define_insn "*load_and_trap<mode>"
8053 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8056 (set (match_operand:GPR 1 "register_operand" "=d")
8060 [(set_attr "op_type" "RXY")])
8064 ;;- Loop instructions.
8066 ;; This is all complicated by the fact that since this is a jump insn
8067 ;; we must handle our own output reloads.
8071 ; This splitter will be matched by combine and has to add the 2 moves
8072 ; necessary to load the compare and the increment values into a
8073 ; register pair as needed by brxle.
8075 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8078 (match_operator 6 "s390_brx_operator"
8079 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8080 (match_operand:GPR 2 "general_operand" ""))
8081 (match_operand:GPR 3 "register_operand" "")])
8082 (label_ref (match_operand 0 "" ""))
8084 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8085 (plus:GPR (match_dup 1) (match_dup 2)))
8086 (clobber (match_scratch:GPR 5 ""))]
8089 "!reload_completed && !reload_in_progress"
8090 [(set (match_dup 7) (match_dup 2)) ; the increment
8091 (set (match_dup 8) (match_dup 3)) ; the comparison value
8092 (parallel [(set (pc)
8095 [(plus:GPR (match_dup 1) (match_dup 7))
8097 (label_ref (match_dup 0))
8100 (plus:GPR (match_dup 1) (match_dup 7)))
8101 (clobber (match_dup 5))
8102 (clobber (reg:CC CC_REGNUM))])]
8104 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8105 operands[7] = gen_lowpart (<GPR:MODE>mode,
8106 gen_highpart (word_mode, dreg));
8107 operands[8] = gen_lowpart (<GPR:MODE>mode,
8108 gen_lowpart (word_mode, dreg));
8113 (define_insn_and_split "*brxg_64bit"
8116 (match_operator 5 "s390_brx_operator"
8117 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8118 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8119 (subreg:DI (match_dup 2) 8)])
8120 (label_ref (match_operand 0 "" ""))
8122 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8123 (plus:DI (match_dup 1)
8124 (subreg:DI (match_dup 2) 0)))
8125 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8126 (clobber (reg:CC CC_REGNUM))]
8129 if (which_alternative != 0)
8131 else if (get_attr_length (insn) == 6)
8132 return "brx%E5g\t%1,%2,%l0";
8134 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8136 "&& reload_completed
8137 && (!REG_P (operands[3])
8138 || !rtx_equal_p (operands[1], operands[3]))"
8139 [(set (match_dup 4) (match_dup 1))
8140 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8141 (clobber (reg:CC CC_REGNUM))])
8142 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8143 (set (match_dup 3) (match_dup 4))
8144 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8145 (label_ref (match_dup 0))
8148 [(set_attr "op_type" "RIE")
8149 (set_attr "type" "branch")
8150 (set (attr "length")
8151 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8152 (const_int 6) (const_int 16)))])
8156 (define_insn_and_split "*brx_64bit"
8159 (match_operator 5 "s390_brx_operator"
8160 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8161 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8162 (subreg:SI (match_dup 2) 12)])
8163 (label_ref (match_operand 0 "" ""))
8165 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8166 (plus:SI (match_dup 1)
8167 (subreg:SI (match_dup 2) 4)))
8168 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8169 (clobber (reg:CC CC_REGNUM))]
8172 if (which_alternative != 0)
8174 else if (get_attr_length (insn) == 6)
8175 return "brx%C5\t%1,%2,%l0";
8177 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8179 "&& reload_completed
8180 && (!REG_P (operands[3])
8181 || !rtx_equal_p (operands[1], operands[3]))"
8182 [(set (match_dup 4) (match_dup 1))
8183 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8184 (clobber (reg:CC CC_REGNUM))])
8185 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8186 (set (match_dup 3) (match_dup 4))
8187 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8188 (label_ref (match_dup 0))
8191 [(set_attr "op_type" "RSI")
8192 (set_attr "type" "branch")
8193 (set (attr "length")
8194 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8195 (const_int 6) (const_int 14)))])
8199 (define_insn_and_split "*brx_31bit"
8202 (match_operator 5 "s390_brx_operator"
8203 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8204 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8205 (subreg:SI (match_dup 2) 4)])
8206 (label_ref (match_operand 0 "" ""))
8208 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8209 (plus:SI (match_dup 1)
8210 (subreg:SI (match_dup 2) 0)))
8211 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8212 (clobber (reg:CC CC_REGNUM))]
8213 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8215 if (which_alternative != 0)
8217 else if (get_attr_length (insn) == 6)
8218 return "brx%C5\t%1,%2,%l0";
8220 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8222 "&& reload_completed
8223 && (!REG_P (operands[3])
8224 || !rtx_equal_p (operands[1], operands[3]))"
8225 [(set (match_dup 4) (match_dup 1))
8226 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8227 (clobber (reg:CC CC_REGNUM))])
8228 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8229 (set (match_dup 3) (match_dup 4))
8230 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8231 (label_ref (match_dup 0))
8234 [(set_attr "op_type" "RSI")
8235 (set_attr "type" "branch")
8236 (set (attr "length")
8237 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8238 (const_int 6) (const_int 14)))])
8243 (define_expand "doloop_end"
8244 [(use (match_operand 0 "" "")) ; loop pseudo
8245 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8246 (use (match_operand 2 "" "")) ; max iterations
8247 (use (match_operand 3 "" "")) ; loop level
8248 (use (match_operand 4 "" "")) ; label
8249 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
8252 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8253 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8254 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8255 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8256 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8257 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8264 (define_insn_and_split "doloop_si64"
8267 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8269 (label_ref (match_operand 0 "" ""))
8271 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8272 (plus:SI (match_dup 1) (const_int -1)))
8273 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8274 (clobber (reg:CC CC_REGNUM))]
8277 if (which_alternative != 0)
8279 else if (get_attr_length (insn) == 4)
8280 return "brct\t%1,%l0";
8282 return "ahi\t%1,-1\;jgne\t%l0";
8284 "&& reload_completed
8285 && (! REG_P (operands[2])
8286 || ! rtx_equal_p (operands[1], operands[2]))"
8287 [(set (match_dup 3) (match_dup 1))
8288 (parallel [(set (reg:CCAN CC_REGNUM)
8289 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8291 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8292 (set (match_dup 2) (match_dup 3))
8293 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8294 (label_ref (match_dup 0))
8297 [(set_attr "op_type" "RI")
8298 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8299 ; hurt us in the (rare) case of ahi.
8300 (set_attr "z10prop" "z10_super_E1")
8301 (set_attr "type" "branch")
8302 (set (attr "length")
8303 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8304 (const_int 4) (const_int 10)))])
8306 (define_insn_and_split "doloop_si31"
8309 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8311 (label_ref (match_operand 0 "" ""))
8313 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8314 (plus:SI (match_dup 1) (const_int -1)))
8315 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8316 (clobber (reg:CC CC_REGNUM))]
8319 if (which_alternative != 0)
8321 else if (get_attr_length (insn) == 4)
8322 return "brct\t%1,%l0";
8326 "&& reload_completed
8327 && (! REG_P (operands[2])
8328 || ! rtx_equal_p (operands[1], operands[2]))"
8329 [(set (match_dup 3) (match_dup 1))
8330 (parallel [(set (reg:CCAN CC_REGNUM)
8331 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8333 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8334 (set (match_dup 2) (match_dup 3))
8335 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8336 (label_ref (match_dup 0))
8339 [(set_attr "op_type" "RI")
8340 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8341 ; hurt us in the (rare) case of ahi.
8342 (set_attr "z10prop" "z10_super_E1")
8343 (set_attr "type" "branch")
8344 (set (attr "length")
8345 (if_then_else (not (match_test "flag_pic"))
8346 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8347 (const_int 4) (const_int 6))
8348 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8349 (const_int 4) (const_int 8))))])
8351 (define_insn "*doloop_si_long"
8354 (ne (match_operand:SI 1 "register_operand" "d")
8356 (match_operand 0 "address_operand" "ZQZR")
8358 (set (match_operand:SI 2 "register_operand" "=1")
8359 (plus:SI (match_dup 1) (const_int -1)))
8360 (clobber (match_scratch:SI 3 "=X"))
8361 (clobber (reg:CC CC_REGNUM))]
8364 if (get_attr_op_type (insn) == OP_TYPE_RR)
8365 return "bctr\t%1,%0";
8367 return "bct\t%1,%a0";
8369 [(set (attr "op_type")
8370 (if_then_else (match_operand 0 "register_operand" "")
8371 (const_string "RR") (const_string "RX")))
8372 (set_attr "type" "branch")
8373 (set_attr "atype" "agen")
8374 (set_attr "z10prop" "z10_c")
8375 (set_attr "z196prop" "z196_cracked")])
8377 (define_insn_and_split "doloop_di"
8380 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8382 (label_ref (match_operand 0 "" ""))
8384 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8385 (plus:DI (match_dup 1) (const_int -1)))
8386 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8387 (clobber (reg:CC CC_REGNUM))]
8390 if (which_alternative != 0)
8392 else if (get_attr_length (insn) == 4)
8393 return "brctg\t%1,%l0";
8395 return "aghi\t%1,-1\;jgne\t%l0";
8397 "&& reload_completed
8398 && (! REG_P (operands[2])
8399 || ! rtx_equal_p (operands[1], operands[2]))"
8400 [(set (match_dup 3) (match_dup 1))
8401 (parallel [(set (reg:CCAN CC_REGNUM)
8402 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8404 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8405 (set (match_dup 2) (match_dup 3))
8406 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8407 (label_ref (match_dup 0))
8410 [(set_attr "op_type" "RI")
8411 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8412 ; hurt us in the (rare) case of ahi.
8413 (set_attr "z10prop" "z10_super_E1")
8414 (set_attr "type" "branch")
8415 (set (attr "length")
8416 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8417 (const_int 4) (const_int 10)))])
8420 ;;- Unconditional jump instructions.
8424 ; jump instruction pattern(s).
8427 (define_expand "jump"
8428 [(match_operand 0 "" "")]
8430 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8432 (define_insn "*jump64"
8433 [(set (pc) (label_ref (match_operand 0 "" "")))]
8436 if (get_attr_length (insn) == 4)
8441 [(set_attr "op_type" "RI")
8442 (set_attr "type" "branch")
8443 (set (attr "length")
8444 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8445 (const_int 4) (const_int 6)))])
8447 (define_insn "*jump31"
8448 [(set (pc) (label_ref (match_operand 0 "" "")))]
8451 gcc_assert (get_attr_length (insn) == 4);
8454 [(set_attr "op_type" "RI")
8455 (set_attr "type" "branch")
8456 (set (attr "length")
8457 (if_then_else (not (match_test "flag_pic"))
8458 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8459 (const_int 4) (const_int 6))
8460 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8461 (const_int 4) (const_int 8))))])
8464 ; indirect-jump instruction pattern(s).
8467 (define_insn "indirect_jump"
8468 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8471 if (get_attr_op_type (insn) == OP_TYPE_RR)
8476 [(set (attr "op_type")
8477 (if_then_else (match_operand 0 "register_operand" "")
8478 (const_string "RR") (const_string "RX")))
8479 (set_attr "type" "branch")
8480 (set_attr "atype" "agen")])
8483 ; casesi instruction pattern(s).
8486 (define_insn "casesi_jump"
8487 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8488 (use (label_ref (match_operand 1 "" "")))]
8491 if (get_attr_op_type (insn) == OP_TYPE_RR)
8496 [(set (attr "op_type")
8497 (if_then_else (match_operand 0 "register_operand" "")
8498 (const_string "RR") (const_string "RX")))
8499 (set_attr "type" "branch")
8500 (set_attr "atype" "agen")])
8502 (define_expand "casesi"
8503 [(match_operand:SI 0 "general_operand" "")
8504 (match_operand:SI 1 "general_operand" "")
8505 (match_operand:SI 2 "general_operand" "")
8506 (label_ref (match_operand 3 "" ""))
8507 (label_ref (match_operand 4 "" ""))]
8510 rtx index = gen_reg_rtx (SImode);
8511 rtx base = gen_reg_rtx (Pmode);
8512 rtx target = gen_reg_rtx (Pmode);
8514 emit_move_insn (index, operands[0]);
8515 emit_insn (gen_subsi3 (index, index, operands[1]));
8516 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8519 if (Pmode != SImode)
8520 index = convert_to_mode (Pmode, index, 1);
8521 if (GET_CODE (index) != REG)
8522 index = copy_to_mode_reg (Pmode, index);
8525 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8527 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8529 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8531 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8532 emit_move_insn (target, index);
8535 target = gen_rtx_PLUS (Pmode, base, target);
8536 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8543 ;;- Jump to subroutine.
8548 ; untyped call instruction pattern(s).
8551 ;; Call subroutine returning any type.
8552 (define_expand "untyped_call"
8553 [(parallel [(call (match_operand 0 "" "")
8555 (match_operand 1 "" "")
8556 (match_operand 2 "" "")])]
8561 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8563 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8565 rtx set = XVECEXP (operands[2], 0, i);
8566 emit_move_insn (SET_DEST (set), SET_SRC (set));
8569 /* The optimizer does not know that the call sets the function value
8570 registers we stored in the result block. We avoid problems by
8571 claiming that all hard registers are used and clobbered at this
8573 emit_insn (gen_blockage ());
8578 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8579 ;; all of memory. This blocks insns from being moved across this point.
8581 (define_insn "blockage"
8582 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8585 [(set_attr "type" "none")
8586 (set_attr "length" "0")])
8592 (define_expand "sibcall"
8593 [(call (match_operand 0 "" "")
8594 (match_operand 1 "" ""))]
8597 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8601 (define_insn "*sibcall_br"
8602 [(call (mem:QI (reg SIBCALL_REGNUM))
8603 (match_operand 0 "const_int_operand" "n"))]
8604 "SIBLING_CALL_P (insn)
8605 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8607 [(set_attr "op_type" "RR")
8608 (set_attr "type" "branch")
8609 (set_attr "atype" "agen")])
8611 (define_insn "*sibcall_brc"
8612 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8613 (match_operand 1 "const_int_operand" "n"))]
8614 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8616 [(set_attr "op_type" "RI")
8617 (set_attr "type" "branch")])
8619 (define_insn "*sibcall_brcl"
8620 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8621 (match_operand 1 "const_int_operand" "n"))]
8622 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8624 [(set_attr "op_type" "RIL")
8625 (set_attr "type" "branch")])
8628 ; sibcall_value patterns
8631 (define_expand "sibcall_value"
8632 [(set (match_operand 0 "" "")
8633 (call (match_operand 1 "" "")
8634 (match_operand 2 "" "")))]
8637 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8641 (define_insn "*sibcall_value_br"
8642 [(set (match_operand 0 "" "")
8643 (call (mem:QI (reg SIBCALL_REGNUM))
8644 (match_operand 1 "const_int_operand" "n")))]
8645 "SIBLING_CALL_P (insn)
8646 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8648 [(set_attr "op_type" "RR")
8649 (set_attr "type" "branch")
8650 (set_attr "atype" "agen")])
8652 (define_insn "*sibcall_value_brc"
8653 [(set (match_operand 0 "" "")
8654 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8655 (match_operand 2 "const_int_operand" "n")))]
8656 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8658 [(set_attr "op_type" "RI")
8659 (set_attr "type" "branch")])
8661 (define_insn "*sibcall_value_brcl"
8662 [(set (match_operand 0 "" "")
8663 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8664 (match_operand 2 "const_int_operand" "n")))]
8665 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8667 [(set_attr "op_type" "RIL")
8668 (set_attr "type" "branch")])
8672 ; call instruction pattern(s).
8675 (define_expand "call"
8676 [(call (match_operand 0 "" "")
8677 (match_operand 1 "" ""))
8678 (use (match_operand 2 "" ""))]
8681 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8682 gen_rtx_REG (Pmode, RETURN_REGNUM));
8686 (define_insn "*bras"
8687 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8688 (match_operand 1 "const_int_operand" "n"))
8689 (clobber (match_operand 2 "register_operand" "=r"))]
8690 "!SIBLING_CALL_P (insn)
8691 && TARGET_SMALL_EXEC
8692 && GET_MODE (operands[2]) == Pmode"
8694 [(set_attr "op_type" "RI")
8695 (set_attr "type" "jsr")
8696 (set_attr "z196prop" "z196_cracked")])
8698 (define_insn "*brasl"
8699 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8700 (match_operand 1 "const_int_operand" "n"))
8701 (clobber (match_operand 2 "register_operand" "=r"))]
8702 "!SIBLING_CALL_P (insn)
8704 && GET_MODE (operands[2]) == Pmode"
8706 [(set_attr "op_type" "RIL")
8707 (set_attr "type" "jsr")
8708 (set_attr "z196prop" "z196_cracked")])
8710 (define_insn "*basr"
8711 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8712 (match_operand 1 "const_int_operand" "n"))
8713 (clobber (match_operand 2 "register_operand" "=r"))]
8714 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8716 if (get_attr_op_type (insn) == OP_TYPE_RR)
8717 return "basr\t%2,%0";
8719 return "bas\t%2,%a0";
8721 [(set (attr "op_type")
8722 (if_then_else (match_operand 0 "register_operand" "")
8723 (const_string "RR") (const_string "RX")))
8724 (set_attr "type" "jsr")
8725 (set_attr "atype" "agen")
8726 (set_attr "z196prop" "z196_cracked")])
8729 ; call_value instruction pattern(s).
8732 (define_expand "call_value"
8733 [(set (match_operand 0 "" "")
8734 (call (match_operand 1 "" "")
8735 (match_operand 2 "" "")))
8736 (use (match_operand 3 "" ""))]
8739 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8740 gen_rtx_REG (Pmode, RETURN_REGNUM));
8744 (define_insn "*bras_r"
8745 [(set (match_operand 0 "" "")
8746 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8747 (match_operand:SI 2 "const_int_operand" "n")))
8748 (clobber (match_operand 3 "register_operand" "=r"))]
8749 "!SIBLING_CALL_P (insn)
8750 && TARGET_SMALL_EXEC
8751 && GET_MODE (operands[3]) == Pmode"
8753 [(set_attr "op_type" "RI")
8754 (set_attr "type" "jsr")
8755 (set_attr "z196prop" "z196_cracked")])
8757 (define_insn "*brasl_r"
8758 [(set (match_operand 0 "" "")
8759 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8760 (match_operand 2 "const_int_operand" "n")))
8761 (clobber (match_operand 3 "register_operand" "=r"))]
8762 "!SIBLING_CALL_P (insn)
8764 && GET_MODE (operands[3]) == Pmode"
8766 [(set_attr "op_type" "RIL")
8767 (set_attr "type" "jsr")
8768 (set_attr "z196prop" "z196_cracked")])
8770 (define_insn "*basr_r"
8771 [(set (match_operand 0 "" "")
8772 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8773 (match_operand 2 "const_int_operand" "n")))
8774 (clobber (match_operand 3 "register_operand" "=r"))]
8775 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8777 if (get_attr_op_type (insn) == OP_TYPE_RR)
8778 return "basr\t%3,%1";
8780 return "bas\t%3,%a1";
8782 [(set (attr "op_type")
8783 (if_then_else (match_operand 1 "register_operand" "")
8784 (const_string "RR") (const_string "RX")))
8785 (set_attr "type" "jsr")
8786 (set_attr "atype" "agen")
8787 (set_attr "z196prop" "z196_cracked")])
8790 ;;- Thread-local storage support.
8793 (define_expand "get_thread_pointer<mode>"
8794 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8798 (define_expand "set_thread_pointer<mode>"
8799 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8800 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8804 (define_insn "*set_tp"
8805 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8808 [(set_attr "type" "none")
8809 (set_attr "length" "0")])
8811 (define_insn "*tls_load_64"
8812 [(set (match_operand:DI 0 "register_operand" "=d")
8813 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8814 (match_operand:DI 2 "" "")]
8818 [(set_attr "op_type" "RXE")
8819 (set_attr "z10prop" "z10_fwd_A3")])
8821 (define_insn "*tls_load_31"
8822 [(set (match_operand:SI 0 "register_operand" "=d,d")
8823 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8824 (match_operand:SI 2 "" "")]
8830 [(set_attr "op_type" "RX,RXY")
8831 (set_attr "type" "load")
8832 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8834 (define_insn "*bras_tls"
8835 [(set (match_operand 0 "" "")
8836 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8837 (match_operand 2 "const_int_operand" "n")))
8838 (clobber (match_operand 3 "register_operand" "=r"))
8839 (use (match_operand 4 "" ""))]
8840 "!SIBLING_CALL_P (insn)
8841 && TARGET_SMALL_EXEC
8842 && GET_MODE (operands[3]) == Pmode"
8844 [(set_attr "op_type" "RI")
8845 (set_attr "type" "jsr")
8846 (set_attr "z196prop" "z196_cracked")])
8848 (define_insn "*brasl_tls"
8849 [(set (match_operand 0 "" "")
8850 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8851 (match_operand 2 "const_int_operand" "n")))
8852 (clobber (match_operand 3 "register_operand" "=r"))
8853 (use (match_operand 4 "" ""))]
8854 "!SIBLING_CALL_P (insn)
8856 && GET_MODE (operands[3]) == Pmode"
8858 [(set_attr "op_type" "RIL")
8859 (set_attr "type" "jsr")
8860 (set_attr "z196prop" "z196_cracked")])
8862 (define_insn "*basr_tls"
8863 [(set (match_operand 0 "" "")
8864 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8865 (match_operand 2 "const_int_operand" "n")))
8866 (clobber (match_operand 3 "register_operand" "=r"))
8867 (use (match_operand 4 "" ""))]
8868 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8870 if (get_attr_op_type (insn) == OP_TYPE_RR)
8871 return "basr\t%3,%1%J4";
8873 return "bas\t%3,%a1%J4";
8875 [(set (attr "op_type")
8876 (if_then_else (match_operand 1 "register_operand" "")
8877 (const_string "RR") (const_string "RX")))
8878 (set_attr "type" "jsr")
8879 (set_attr "atype" "agen")
8880 (set_attr "z196prop" "z196_cracked")])
8883 ;;- Atomic operations
8887 ; memory barrier patterns.
8890 (define_expand "mem_signal_fence"
8891 [(match_operand:SI 0 "const_int_operand")] ;; model
8894 /* The s390 memory model is strong enough not to require any
8895 barrier in order to synchronize a thread with itself. */
8899 (define_expand "mem_thread_fence"
8900 [(match_operand:SI 0 "const_int_operand")] ;; model
8903 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8904 enough not to require barriers of any kind. */
8905 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
8907 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8908 MEM_VOLATILE_P (mem) = 1;
8909 emit_insn (gen_mem_thread_fence_1 (mem));
8914 ; Although bcr is superscalar on Z10, this variant will never
8915 ; become part of an execution group.
8916 (define_insn "mem_thread_fence_1"
8917 [(set (match_operand:BLK 0 "" "")
8918 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8921 [(set_attr "op_type" "RR")])
8924 ; atomic load/store operations
8927 ; Atomic loads need not examine the memory model at all.
8928 (define_expand "atomic_load<mode>"
8929 [(match_operand:DINT 0 "register_operand") ;; output
8930 (match_operand:DINT 1 "memory_operand") ;; memory
8931 (match_operand:SI 2 "const_int_operand")] ;; model
8934 if (<MODE>mode == TImode)
8935 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
8936 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8937 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
8939 emit_move_insn (operands[0], operands[1]);
8943 ; Different from movdi_31 in that we want no splitters.
8944 (define_insn "atomic_loaddi_1"
8945 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
8946 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
8954 [(set_attr "op_type" "RS,RSY,RS,RSY")
8955 (set_attr "type" "lm,lm,floaddf,floaddf")])
8957 (define_insn "atomic_loadti_1"
8958 [(set (match_operand:TI 0 "register_operand" "=r")
8959 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
8963 [(set_attr "op_type" "RXY")
8964 (set_attr "type" "other")])
8966 ; Atomic stores must(?) enforce sequential consistency.
8967 (define_expand "atomic_store<mode>"
8968 [(match_operand:DINT 0 "memory_operand") ;; memory
8969 (match_operand:DINT 1 "register_operand") ;; input
8970 (match_operand:SI 2 "const_int_operand")] ;; model
8973 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
8975 if (<MODE>mode == TImode)
8976 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
8977 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8978 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
8980 emit_move_insn (operands[0], operands[1]);
8981 if (model == MEMMODEL_SEQ_CST)
8982 emit_insn (gen_mem_thread_fence (operands[2]));
8986 ; Different from movdi_31 in that we want no splitters.
8987 (define_insn "atomic_storedi_1"
8988 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
8989 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
8997 [(set_attr "op_type" "RS,RSY,RS,RSY")
8998 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9000 (define_insn "atomic_storeti_1"
9001 [(set (match_operand:TI 0 "memory_operand" "=RT")
9002 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9006 [(set_attr "op_type" "RXY")
9007 (set_attr "type" "other")])
9010 ; compare and swap patterns.
9013 (define_expand "atomic_compare_and_swap<mode>"
9014 [(match_operand:SI 0 "register_operand") ;; bool success output
9015 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9016 (match_operand:DGPR 2 "memory_operand") ;; memory
9017 (match_operand:DGPR 3 "register_operand") ;; expected intput
9018 (match_operand:DGPR 4 "register_operand") ;; newval intput
9019 (match_operand:SI 5 "const_int_operand") ;; is_weak
9020 (match_operand:SI 6 "const_int_operand") ;; success model
9021 (match_operand:SI 7 "const_int_operand")] ;; failure model
9024 rtx cc, cmp, output = operands[1];
9026 if (!register_operand (output, <MODE>mode))
9027 output = gen_reg_rtx (<MODE>mode);
9029 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9030 (output, operands[2], operands[3], operands[4]));
9032 /* We deliberately accept non-register operands in the predicate
9033 to ensure the write back to the output operand happens *before*
9034 the store-flags code below. This makes it easier for combine
9035 to merge the store-flags code with a potential test-and-branch
9036 pattern following (immediately!) afterwards. */
9037 if (output != operands[1])
9038 emit_move_insn (operands[1], output);
9040 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9041 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9042 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9046 (define_expand "atomic_compare_and_swap<mode>"
9047 [(match_operand:SI 0 "register_operand") ;; bool success output
9048 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9049 (match_operand:HQI 2 "memory_operand") ;; memory
9050 (match_operand:HQI 3 "general_operand") ;; expected intput
9051 (match_operand:HQI 4 "general_operand") ;; newval intput
9052 (match_operand:SI 5 "const_int_operand") ;; is_weak
9053 (match_operand:SI 6 "const_int_operand") ;; success model
9054 (match_operand:SI 7 "const_int_operand")] ;; failure model
9057 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9058 operands[3], operands[4], INTVAL (operands[5]));
9062 (define_expand "atomic_compare_and_swap<mode>_internal"
9064 [(set (match_operand:DGPR 0 "register_operand")
9065 (match_operand:DGPR 1 "memory_operand"))
9067 (unspec_volatile:DGPR
9069 (match_operand:DGPR 2 "register_operand")
9070 (match_operand:DGPR 3 "register_operand")]
9072 (set (reg:CCZ1 CC_REGNUM)
9073 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9077 (define_insn "*atomic_compare_and_swap<mode>_1"
9078 [(set (match_operand:TDI 0 "register_operand" "=r")
9079 (match_operand:TDI 1 "memory_operand" "+QS"))
9081 (unspec_volatile:TDI
9083 (match_operand:TDI 2 "register_operand" "0")
9084 (match_operand:TDI 3 "register_operand" "r")]
9086 (set (reg:CCZ1 CC_REGNUM)
9087 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9089 "c<td>sg\t%0,%3,%S1"
9090 [(set_attr "op_type" "RSY")
9091 (set_attr "type" "sem")])
9094 (define_insn "*atomic_compare_and_swapdi_2"
9095 [(set (match_operand:DI 0 "register_operand" "=r,r")
9096 (match_operand:DI 1 "memory_operand" "+Q,S"))
9100 (match_operand:DI 2 "register_operand" "0,0")
9101 (match_operand:DI 3 "register_operand" "r,r")]
9103 (set (reg:CCZ1 CC_REGNUM)
9104 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9109 [(set_attr "op_type" "RS,RSY")
9110 (set_attr "type" "sem")])
9113 (define_insn "*atomic_compare_and_swapsi_3"
9114 [(set (match_operand:SI 0 "register_operand" "=r,r")
9115 (match_operand:SI 1 "memory_operand" "+Q,S"))
9119 (match_operand:SI 2 "register_operand" "0,0")
9120 (match_operand:SI 3 "register_operand" "r,r")]
9122 (set (reg:CCZ1 CC_REGNUM)
9123 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9128 [(set_attr "op_type" "RS,RSY")
9129 (set_attr "type" "sem")])
9132 ; Other atomic instruction patterns.
9135 ; z196 load and add, xor, or and and instructions
9137 (define_expand "atomic_fetch_<atomic><mode>"
9138 [(match_operand:GPR 0 "register_operand") ;; val out
9140 (match_operand:GPR 1 "memory_operand") ;; memory
9141 (match_operand:GPR 2 "register_operand")) ;; val in
9142 (match_operand:SI 3 "const_int_operand")] ;; model
9145 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9146 (operands[0], operands[1], operands[2]));
9150 ; lan, lang, lao, laog, lax, laxg, laa, laag
9151 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9152 [(set (match_operand:GPR 0 "register_operand" "=d")
9153 (match_operand:GPR 1 "memory_operand" "+QS"))
9155 (unspec_volatile:GPR
9156 [(ATOMIC_Z196:GPR (match_dup 1)
9157 (match_operand:GPR 2 "general_operand" "d"))]
9159 (clobber (reg:CC CC_REGNUM))]
9161 "la<noxa><g>\t%0,%2,%1"
9162 [(set_attr "op_type" "RSY")
9163 (set_attr "type" "sem")])
9165 ;; For SImode and larger, the optabs.c code will do just fine in
9166 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9167 ;; better by expanding our own loop.
9169 (define_expand "atomic_<atomic><mode>"
9171 (match_operand:HQI 0 "memory_operand") ;; memory
9172 (match_operand:HQI 1 "general_operand")) ;; val in
9173 (match_operand:SI 2 "const_int_operand")] ;; model
9176 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9177 operands[1], false);
9181 (define_expand "atomic_fetch_<atomic><mode>"
9182 [(match_operand:HQI 0 "register_operand") ;; val out
9184 (match_operand:HQI 1 "memory_operand") ;; memory
9185 (match_operand:HQI 2 "general_operand")) ;; val in
9186 (match_operand:SI 3 "const_int_operand")] ;; model
9189 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9190 operands[2], false);
9194 (define_expand "atomic_<atomic>_fetch<mode>"
9195 [(match_operand:HQI 0 "register_operand") ;; val out
9197 (match_operand:HQI 1 "memory_operand") ;; memory
9198 (match_operand:HQI 2 "general_operand")) ;; val in
9199 (match_operand:SI 3 "const_int_operand")] ;; model
9202 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9207 (define_expand "atomic_exchange<mode>"
9208 [(match_operand:HQI 0 "register_operand") ;; val out
9209 (match_operand:HQI 1 "memory_operand") ;; memory
9210 (match_operand:HQI 2 "general_operand") ;; val in
9211 (match_operand:SI 3 "const_int_operand")] ;; model
9214 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9215 operands[2], false);
9220 ;;- Miscellaneous instructions.
9224 ; allocate stack instruction pattern(s).
9227 (define_expand "allocate_stack"
9228 [(match_operand 0 "general_operand" "")
9229 (match_operand 1 "general_operand" "")]
9232 rtx temp = gen_reg_rtx (Pmode);
9234 emit_move_insn (temp, s390_back_chain_rtx ());
9235 anti_adjust_stack (operands[1]);
9236 emit_move_insn (s390_back_chain_rtx (), temp);
9238 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9244 ; setjmp instruction pattern.
9247 (define_expand "builtin_setjmp_receiver"
9248 [(match_operand 0 "" "")]
9251 emit_insn (s390_load_got ());
9252 emit_use (pic_offset_table_rtx);
9256 ;; These patterns say how to save and restore the stack pointer. We need not
9257 ;; save the stack pointer at function level since we are careful to
9258 ;; preserve the backchain. At block level, we have to restore the backchain
9259 ;; when we restore the stack pointer.
9261 ;; For nonlocal gotos, we must save both the stack pointer and its
9262 ;; backchain and restore both. Note that in the nonlocal case, the
9263 ;; save area is a memory location.
9265 (define_expand "save_stack_function"
9266 [(match_operand 0 "general_operand" "")
9267 (match_operand 1 "general_operand" "")]
9271 (define_expand "restore_stack_function"
9272 [(match_operand 0 "general_operand" "")
9273 (match_operand 1 "general_operand" "")]
9277 (define_expand "restore_stack_block"
9278 [(match_operand 0 "register_operand" "")
9279 (match_operand 1 "register_operand" "")]
9282 rtx temp = gen_reg_rtx (Pmode);
9284 emit_move_insn (temp, s390_back_chain_rtx ());
9285 emit_move_insn (operands[0], operands[1]);
9286 emit_move_insn (s390_back_chain_rtx (), temp);
9291 (define_expand "save_stack_nonlocal"
9292 [(match_operand 0 "memory_operand" "")
9293 (match_operand 1 "register_operand" "")]
9296 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9298 /* Copy the backchain to the first word, sp to the second and the
9299 literal pool base to the third. */
9301 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9302 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9303 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9305 if (TARGET_BACKCHAIN)
9306 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9308 emit_move_insn (save_sp, operands[1]);
9309 emit_move_insn (save_bp, base);
9314 (define_expand "restore_stack_nonlocal"
9315 [(match_operand 0 "register_operand" "")
9316 (match_operand 1 "memory_operand" "")]
9319 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9320 rtx temp = NULL_RTX;
9322 /* Restore the backchain from the first word, sp from the second and the
9323 literal pool base from the third. */
9325 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9326 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9327 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9329 if (TARGET_BACKCHAIN)
9330 temp = force_reg (Pmode, save_bc);
9332 emit_move_insn (base, save_bp);
9333 emit_move_insn (operands[0], save_sp);
9336 emit_move_insn (s390_back_chain_rtx (), temp);
9342 (define_expand "exception_receiver"
9346 s390_set_has_landing_pad_p (true);
9351 ; nop instruction pattern(s).
9358 [(set_attr "op_type" "RR")
9359 (set_attr "z10prop" "z10_fr_E1")])
9365 [(set_attr "op_type" "RR")])
9369 ; Special literal pool access instruction pattern(s).
9372 (define_insn "*pool_entry"
9373 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9374 UNSPECV_POOL_ENTRY)]
9377 enum machine_mode mode = GET_MODE (PATTERN (insn));
9378 unsigned int align = GET_MODE_BITSIZE (mode);
9379 s390_output_pool_entry (operands[0], mode, align);
9382 [(set (attr "length")
9383 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9385 (define_insn "pool_align"
9386 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9387 UNSPECV_POOL_ALIGN)]
9390 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9392 (define_insn "pool_section_start"
9393 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9396 [(set_attr "length" "0")])
9398 (define_insn "pool_section_end"
9399 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9402 [(set_attr "length" "0")])
9404 (define_insn "main_base_31_small"
9405 [(set (match_operand 0 "register_operand" "=a")
9406 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9407 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9409 [(set_attr "op_type" "RR")
9410 (set_attr "type" "la")
9411 (set_attr "z196prop" "z196_cracked")])
9413 (define_insn "main_base_31_large"
9414 [(set (match_operand 0 "register_operand" "=a")
9415 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9416 (set (pc) (label_ref (match_operand 2 "" "")))]
9417 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9419 [(set_attr "op_type" "RI")
9420 (set_attr "z196prop" "z196_cracked")])
9422 (define_insn "main_base_64"
9423 [(set (match_operand 0 "register_operand" "=a")
9424 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9425 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9427 [(set_attr "op_type" "RIL")
9428 (set_attr "type" "larl")
9429 (set_attr "z10prop" "z10_fwd_A1")])
9431 (define_insn "main_pool"
9432 [(set (match_operand 0 "register_operand" "=a")
9433 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9434 "GET_MODE (operands[0]) == Pmode"
9439 (if_then_else (match_test "TARGET_CPU_ZARCH")
9440 (const_string "larl") (const_string "la")))])
9442 (define_insn "reload_base_31"
9443 [(set (match_operand 0 "register_operand" "=a")
9444 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9445 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9446 "basr\t%0,0\;la\t%0,%1-.(%0)"
9447 [(set_attr "length" "6")
9448 (set_attr "type" "la")
9449 (set_attr "z196prop" "z196_cracked")])
9451 (define_insn "reload_base_64"
9452 [(set (match_operand 0 "register_operand" "=a")
9453 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9454 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9456 [(set_attr "op_type" "RIL")
9457 (set_attr "type" "larl")
9458 (set_attr "z10prop" "z10_fwd_A1")])
9461 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9466 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9469 ;; Insns related to generating the function prologue and epilogue.
9473 (define_expand "prologue"
9474 [(use (const_int 0))]
9476 "s390_emit_prologue (); DONE;")
9478 (define_expand "epilogue"
9479 [(use (const_int 1))]
9481 "s390_emit_epilogue (false); DONE;")
9483 (define_expand "sibcall_epilogue"
9484 [(use (const_int 0))]
9486 "s390_emit_epilogue (true); DONE;")
9488 (define_insn "*return"
9490 (use (match_operand 0 "register_operand" "a"))]
9491 "GET_MODE (operands[0]) == Pmode"
9493 [(set_attr "op_type" "RR")
9494 (set_attr "type" "jsr")
9495 (set_attr "atype" "agen")])
9498 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9499 ;; pointer. This is used for compatibility.
9501 (define_expand "ptr_extend"
9502 [(set (match_operand:DI 0 "register_operand" "=r")
9503 (match_operand:SI 1 "register_operand" "r"))]
9506 emit_insn (gen_anddi3 (operands[0],
9507 gen_lowpart (DImode, operands[1]),
9508 GEN_INT (0x7fffffff)));
9512 ;; Instruction definition to expand eh_return macro to support
9513 ;; swapping in special linkage return addresses.
9515 (define_expand "eh_return"
9516 [(use (match_operand 0 "register_operand" ""))]
9519 s390_emit_tpf_eh_return (operands[0]);
9524 ; Stack Protector Patterns
9527 (define_expand "stack_protect_set"
9528 [(set (match_operand 0 "memory_operand" "")
9529 (match_operand 1 "memory_operand" ""))]
9532 #ifdef TARGET_THREAD_SSP_OFFSET
9534 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9535 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9538 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9540 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9545 (define_insn "stack_protect_set<mode>"
9546 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9547 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9549 "mvc\t%O0(%G0,%R0),%S1"
9550 [(set_attr "op_type" "SS")])
9552 (define_expand "stack_protect_test"
9553 [(set (reg:CC CC_REGNUM)
9554 (compare (match_operand 0 "memory_operand" "")
9555 (match_operand 1 "memory_operand" "")))
9556 (match_operand 2 "" "")]
9560 #ifdef TARGET_THREAD_SSP_OFFSET
9562 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9563 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9566 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9568 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9570 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9571 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9572 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9576 (define_insn "stack_protect_test<mode>"
9577 [(set (reg:CCZ CC_REGNUM)
9578 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9579 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9581 "clc\t%O0(%G0,%R0),%S1"
9582 [(set_attr "op_type" "SS")])
9584 ; This is used in s390_emit_prologue in order to prevent insns
9585 ; adjusting the stack pointer to be moved over insns writing stack
9586 ; slots using a copy of the stack pointer in a different register.
9587 (define_insn "stack_tie"
9588 [(set (match_operand:BLK 0 "memory_operand" "+m")
9589 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9592 [(set_attr "length" "0")])
9596 ; Data prefetch patterns
9599 (define_insn "prefetch"
9600 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9601 (match_operand:SI 1 "const_int_operand" " n,n")
9602 (match_operand:SI 2 "const_int_operand" " n,n"))]
9605 switch (which_alternative)
9608 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9610 if (larl_operand (operands[0], Pmode))
9611 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9614 /* This might be reached for symbolic operands with an odd
9615 addend. We simply omit the prefetch for such rare cases. */
9620 [(set_attr "type" "load,larl")
9621 (set_attr "op_type" "RXY,RIL")
9622 (set_attr "z10prop" "z10_super")
9623 (set_attr "z196prop" "z196_alone")])
9627 ; Byte swap instructions
9630 (define_insn "bswap<mode>2"
9631 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9632 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9637 [(set_attr "type" "*,load")
9638 (set_attr "op_type" "RRE,RXY")
9639 (set_attr "z10prop" "z10_super")])
9643 ; Population count instruction
9646 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9647 ; portions and stores the result in the corresponding bytes in op0.
9648 (define_insn "*popcount<mode>"
9649 [(set (match_operand:INT 0 "register_operand" "=d")
9650 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9651 (clobber (reg:CC CC_REGNUM))]
9654 [(set_attr "op_type" "RRE")])
9656 (define_expand "popcountdi2"
9658 (parallel [(set (match_operand:DI 0 "register_operand" "")
9659 (unspec:DI [(match_operand:DI 1 "register_operand")]
9661 (clobber (reg:CC CC_REGNUM))])
9663 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9665 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9666 (clobber (reg:CC CC_REGNUM))])
9669 (ashift:DI (match_dup 0) (const_int 16)))
9671 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9672 (clobber (reg:CC CC_REGNUM))])
9674 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9676 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9677 (clobber (reg:CC CC_REGNUM))])
9679 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9680 "TARGET_Z196 && TARGET_64BIT"
9681 "operands[2] = gen_reg_rtx (DImode);")
9683 (define_expand "popcountsi2"
9685 (parallel [(set (match_operand:SI 0 "register_operand" "")
9686 (unspec:SI [(match_operand:SI 1 "register_operand")]
9688 (clobber (reg:CC CC_REGNUM))])
9691 (ashift:SI (match_dup 0) (const_int 16)))
9693 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9694 (clobber (reg:CC CC_REGNUM))])
9696 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9698 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9699 (clobber (reg:CC CC_REGNUM))])
9701 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9703 "operands[2] = gen_reg_rtx (SImode);")
9705 (define_expand "popcounthi2"
9707 (parallel [(set (match_operand:HI 0 "register_operand" "")
9708 (unspec:HI [(match_operand:HI 1 "register_operand")]
9710 (clobber (reg:CC CC_REGNUM))])
9713 (ashift:SI (match_dup 0) (const_int 8)))
9715 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9716 (clobber (reg:CC CC_REGNUM))])
9718 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9720 "operands[2] = gen_reg_rtx (SImode);")
9722 (define_expand "popcountqi2"
9724 (parallel [(set (match_operand:QI 0 "register_operand" "")
9725 (unspec:QI [(match_operand:QI 1 "register_operand")]
9727 (clobber (reg:CC CC_REGNUM))])]
9732 ;;- Copy sign instructions
9735 (define_insn "copysign<mode>3"
9736 [(set (match_operand:FP 0 "register_operand" "=f")
9737 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9738 (match_operand:FP 2 "register_operand" "f")]
9742 [(set_attr "op_type" "RRF")
9743 (set_attr "type" "fsimp<mode>")])