1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
60 (define_c_enum "unspec" [
68 ; GOT/PLT and lt-relative accesses
89 ; TLS relocation specifiers
105 ; Stack Smashing Protector
109 ; Test Data Class (TDC)
118 ;; UNSPEC_VOLATILE usage
121 (define_c_enum "unspecv" [
148 ; Registers with special meaning
152 ; Sibling call register.
154 ; Literal pool base register.
156 ; Return address register.
158 ; Condition code register.
160 ; Thread local storage pointer register.
164 ; Hardware register names
168 ; General purpose registers
170 ; Floating point registers.
176 ;; PFPO GPR0 argument format
181 ; PFPO operation type
182 (PFPO_CONVERT 0x1000000)
184 (PFPO_OP_TYPE_SF 0x5)
185 (PFPO_OP_TYPE_DF 0x6)
186 (PFPO_OP_TYPE_TF 0x7)
187 (PFPO_OP_TYPE_SD 0x8)
188 (PFPO_OP_TYPE_DD 0x9)
189 (PFPO_OP_TYPE_TD 0xa)
190 ; Bitposition of operand types
191 (PFPO_OP0_TYPE_SHIFT 16)
192 (PFPO_OP1_TYPE_SHIFT 8)
196 ;; Instruction operand type as used in the Principles of Operation.
197 ;; Used to determine defaults for length and other attribute values.
199 (define_attr "op_type"
200 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
203 ;; Instruction type attribute used for scheduling.
205 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
206 cs,vs,store,sem,idiv,
207 imulhi,imulsi,imuldi,
208 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
209 floadtf,floaddf,floadsf,fstoredf,fstoresf,
210 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
211 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
213 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
214 itoftf, itofdf, itofsf, itofdd, itoftd,
215 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
216 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
218 (cond [(eq_attr "op_type" "NN") (const_string "other")
219 (eq_attr "op_type" "SS") (const_string "cs")]
220 (const_string "integer")))
222 ;; Another attribute used for scheduling purposes:
223 ;; agen: Instruction uses the address generation unit
224 ;; reg: Instruction does not use the agen unit
226 (define_attr "atype" "agen,reg"
227 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
229 (const_string "agen")))
231 ;; Properties concerning Z10 execution grouping and value forwarding.
232 ;; z10_super: instruction is superscalar.
233 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
234 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
235 ;; target register. It can forward this value to a second instruction that reads
236 ;; the same register if that second instruction is issued in the same group.
237 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
238 ;; instruction in the S pipe writes to the register, then the T instruction
239 ;; can immediately read the new value.
240 ;; z10_fr: union of Z10_fwd and z10_rec.
241 ;; z10_c: second operand of instruction is a register and read with complemented bits.
243 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
246 (define_attr "z10prop" "none,
247 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
248 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
250 z10_fr, z10_fr_A3, z10_fr_E1,
252 (const_string "none"))
254 ;; Properties concerning Z196 decoding
255 ;; z196_alone: must group alone
256 ;; z196_end: ends a group
257 ;; z196_cracked: instruction is cracked or expanded
258 (define_attr "z196prop" "none,
259 z196_alone, z196_ends,
261 (const_string "none"))
263 (define_attr "mnemonic" "unknown" (const_string "unknown"))
267 (define_attr "length" ""
268 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
269 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
273 ;; Processor type. This attribute must exactly match the processor_type
274 ;; enumeration in s390.h. The current machine description does not
275 ;; distinguish between g5 and g6, but there are differences between the two
276 ;; CPUs could in theory be modeled.
278 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
279 (const (symbol_ref "s390_tune_attr")))
281 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196,zEC12"
282 (const_string "standard"))
284 (define_attr "enabled" ""
285 (cond [(eq_attr "cpu_facility" "standard")
288 (and (eq_attr "cpu_facility" "ieee")
289 (match_test "TARGET_CPU_IEEE_FLOAT"))
292 (and (eq_attr "cpu_facility" "zarch")
293 (match_test "TARGET_ZARCH"))
296 (and (eq_attr "cpu_facility" "longdisp")
297 (match_test "TARGET_LONG_DISPLACEMENT"))
300 (and (eq_attr "cpu_facility" "extimm")
301 (match_test "TARGET_EXTIMM"))
304 (and (eq_attr "cpu_facility" "dfp")
305 (match_test "TARGET_DFP"))
308 (and (eq_attr "cpu_facility" "z10")
309 (match_test "TARGET_Z10"))
312 (and (eq_attr "cpu_facility" "z196")
313 (match_test "TARGET_Z196"))
316 (and (eq_attr "cpu_facility" "zEC12")
317 (match_test "TARGET_ZEC12"))
321 ;; Pipeline description for z900. For lack of anything better,
322 ;; this description is also used for the g5 and g6.
325 ;; Pipeline description for z990, z9-109 and z9-ec.
328 ;; Pipeline description for z10
331 ;; Pipeline description for z196
334 ;; Pipeline description for zEC12
338 (include "predicates.md")
340 ;; Constraint definitions
341 (include "constraints.md")
348 ;; These mode iterators allow floating point patterns to be generated from the
350 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
351 (SD "TARGET_HARD_DFP")])
352 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
353 (define_mode_iterator FPALL [TF DF SF TD DD SD])
354 (define_mode_iterator BFP [TF DF SF])
355 (define_mode_iterator DFP [TD DD])
356 (define_mode_iterator DFP_ALL [TD DD SD])
357 (define_mode_iterator DSF [DF SF])
358 (define_mode_iterator SD_SF [SF SD])
359 (define_mode_iterator DD_DF [DF DD])
360 (define_mode_iterator TD_TF [TF TD])
362 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
363 ;; from the same template.
364 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
365 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
366 (define_mode_iterator DSI [DI SI])
367 (define_mode_iterator TDI [TI DI])
369 ;; These mode iterators allow :P to be used for patterns that operate on
370 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
371 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
373 ;; These macros refer to the actual word_mode of the configuration.
374 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
375 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
376 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
378 ;; Used by the umul pattern to express modes having half the size.
379 (define_mode_attr DWH [(TI "DI") (DI "SI")])
380 (define_mode_attr dwh [(TI "di") (DI "si")])
382 ;; This mode iterator allows the QI and HI patterns to be defined from
383 ;; the same template.
384 (define_mode_iterator HQI [HI QI])
386 ;; This mode iterator allows the integer patterns to be defined from the
388 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
389 (define_mode_iterator INTALL [TI DI SI HI QI])
390 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
392 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
393 ;; the same template.
394 (define_code_iterator SHIFT [ashift lshiftrt])
396 ;; This iterator allow r[ox]sbg to be defined with the same template
397 (define_code_iterator IXOR [ior xor])
399 ;; This iterator and attribute allow to combine most atomic operations.
400 (define_code_iterator ATOMIC [and ior xor plus minus mult])
401 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
402 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
403 (plus "add") (minus "sub") (mult "nand")])
404 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
406 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
407 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
408 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
410 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
411 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
413 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
415 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
416 ;; Likewise for "<RXe>".
417 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
418 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
420 ;; The decimal floating point variants of add, sub, div and mul support 3
421 ;; fp register operands. The following attributes allow to merge the bfp and
422 ;; dfp variants in a single insn definition.
424 ;; This attribute is used to set op_type accordingly.
425 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
426 (DD "RRR") (SD "RRR")])
428 ;; This attribute is used in the operand constraint list in order to have the
429 ;; first and the second operand match for bfp modes.
430 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
432 ;; This attribute is used in the operand list of the instruction to have an
433 ;; additional operand for the dfp instructions.
434 (define_mode_attr op1 [(TF "") (DF "") (SF "")
435 (TD "%1,") (DD "%1,") (SD "%1,")])
438 ;; This attribute is used in the operand constraint list
439 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
440 ;; TFmode values are represented by a fp register pair. Since the
441 ;; sign bit instructions only handle single source and target fp registers
442 ;; these instructions can only be used for TFmode values if the source and
443 ;; target operand uses the same fp register.
444 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
446 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
447 ;; This is used to disable the memory alternative in TFmode patterns.
448 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
450 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
451 ;; within instruction mnemonics.
452 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
454 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
455 ;; modes and to an empty string for bfp modes.
456 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
458 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
459 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
460 ;; version only operates on one register.
461 (define_mode_attr d0 [(DI "d") (SI "0")])
463 ;; In combination with d0 this allows to combine instructions of which the 31bit
464 ;; version only operates on one register. The DImode version needs an additional
465 ;; register for the assembler output.
466 (define_mode_attr 1 [(DI "%1,") (SI "")])
468 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
469 ;; 'ashift' and "srdl" in 'lshiftrt'.
470 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
472 ;; In SHIFT templates, this attribute holds the correct standard name for the
473 ;; pattern itself and the corresponding function calls.
474 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
476 ;; This attribute handles differences in the instruction 'type' and will result
477 ;; in "RRE" for DImode and "RR" for SImode.
478 (define_mode_attr E [(DI "E") (SI "")])
480 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
481 ;; to result in "RXY" for DImode and "RX" for SImode.
482 (define_mode_attr Y [(DI "Y") (SI "")])
484 ;; This attribute handles differences in the instruction 'type' and will result
485 ;; in "RSE" for TImode and "RS" for DImode.
486 (define_mode_attr TE [(TI "E") (DI "")])
488 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
489 ;; and "lcr" in SImode.
490 (define_mode_attr g [(DI "g") (SI "")])
492 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
493 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
494 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
495 ;; variant for long displacements.
496 (define_mode_attr y [(DI "g") (SI "y")])
498 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
499 ;; and "cds" in DImode.
500 (define_mode_attr tg [(TI "g") (DI "")])
502 ;; In TDI templates, a string like "c<d>sg".
503 (define_mode_attr td [(TI "d") (DI "")])
505 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
506 ;; and "cfdbr" in SImode.
507 (define_mode_attr gf [(DI "g") (SI "f")])
509 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
510 ;; and sllk for SI. This way it is possible to merge the new z196 SI
511 ;; 3 operands shift instructions into the existing patterns.
512 (define_mode_attr gk [(DI "g") (SI "k")])
514 ;; ICM mask required to load MODE value into the lowest subreg
515 ;; of a SImode register.
516 (define_mode_attr icm_lo [(HI "3") (QI "1")])
518 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
519 ;; HImode and "llgc" in QImode.
520 (define_mode_attr hc [(HI "h") (QI "c")])
522 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
524 (define_mode_attr DBL [(DI "TI") (SI "DI")])
526 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
527 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
528 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
530 ;; Maximum unsigned integer that fits in MODE.
531 (define_mode_attr max_uint [(HI "65535") (QI "255")])
533 ;; Start and end field computations for RISBG et al.
534 (define_mode_attr bfstart [(DI "s") (SI "t")])
535 (define_mode_attr bfend [(DI "e") (SI "f")])
537 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
538 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
541 ;;- Compare instructions.
544 ; Test-under-Mask instructions
546 (define_insn "*tmqi_mem"
547 [(set (reg CC_REGNUM)
548 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
549 (match_operand:QI 1 "immediate_operand" "n,n"))
550 (match_operand:QI 2 "immediate_operand" "n,n")))]
551 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
555 [(set_attr "op_type" "SI,SIY")
556 (set_attr "z10prop" "z10_super,z10_super")])
558 (define_insn "*tmdi_reg"
559 [(set (reg CC_REGNUM)
560 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
561 (match_operand:DI 1 "immediate_operand"
562 "N0HD0,N1HD0,N2HD0,N3HD0"))
563 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
565 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
566 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
572 [(set_attr "op_type" "RI")
573 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
575 (define_insn "*tmsi_reg"
576 [(set (reg CC_REGNUM)
577 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
578 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
579 (match_operand:SI 2 "immediate_operand" "n,n")))]
580 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
581 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
585 [(set_attr "op_type" "RI")
586 (set_attr "z10prop" "z10_super,z10_super")])
588 (define_insn "*tm<mode>_full"
589 [(set (reg CC_REGNUM)
590 (compare (match_operand:HQI 0 "register_operand" "d")
591 (match_operand:HQI 1 "immediate_operand" "n")))]
592 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
594 [(set_attr "op_type" "RI")
595 (set_attr "z10prop" "z10_super")])
599 ; Load-and-Test instructions
602 ; tst(di|si) instruction pattern(s).
604 (define_insn "*tstdi_sign"
605 [(set (reg CC_REGNUM)
609 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
610 (const_int 32)) (const_int 32))
611 (match_operand:DI 1 "const0_operand" "")))
612 (set (match_operand:DI 2 "register_operand" "=d,d")
613 (sign_extend:DI (match_dup 0)))]
614 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
617 [(set_attr "op_type" "RRE,RXY")
618 (set_attr "cpu_facility" "*,z10")
619 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
622 (define_insn "*tst<mode>_extimm"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
625 (match_operand:GPR 1 "const0_operand" "")))
626 (set (match_operand:GPR 2 "register_operand" "=d,d")
628 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
632 [(set_attr "op_type" "RR<E>,RXY")
633 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
636 (define_insn "*tst<mode>_cconly_extimm"
637 [(set (reg CC_REGNUM)
638 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
639 (match_operand:GPR 1 "const0_operand" "")))
640 (clobber (match_scratch:GPR 2 "=X,d"))]
641 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
645 [(set_attr "op_type" "RR<E>,RXY")
646 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
648 (define_insn "*tstdi"
649 [(set (reg CC_REGNUM)
650 (compare (match_operand:DI 0 "register_operand" "d")
651 (match_operand:DI 1 "const0_operand" "")))
652 (set (match_operand:DI 2 "register_operand" "=d")
654 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
656 [(set_attr "op_type" "RRE")
657 (set_attr "z10prop" "z10_fr_E1")])
659 (define_insn "*tstsi"
660 [(set (reg CC_REGNUM)
661 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
662 (match_operand:SI 1 "const0_operand" "")))
663 (set (match_operand:SI 2 "register_operand" "=d,d,d")
665 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
670 [(set_attr "op_type" "RR,RS,RSY")
671 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
673 (define_insn "*tstsi_cconly"
674 [(set (reg CC_REGNUM)
675 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
676 (match_operand:SI 1 "const0_operand" "")))
677 (clobber (match_scratch:SI 2 "=X,d,d"))]
678 "s390_match_ccmode(insn, CCSmode)"
683 [(set_attr "op_type" "RR,RS,RSY")
684 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
686 (define_insn "*tstdi_cconly_31"
687 [(set (reg CC_REGNUM)
688 (compare (match_operand:DI 0 "register_operand" "d")
689 (match_operand:DI 1 "const0_operand" "")))]
690 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
692 [(set_attr "op_type" "RS")
693 (set_attr "atype" "reg")])
696 (define_insn "*tst<mode>_cconly2"
697 [(set (reg CC_REGNUM)
698 (compare (match_operand:GPR 0 "register_operand" "d")
699 (match_operand:GPR 1 "const0_operand" "")))]
700 "s390_match_ccmode(insn, CCSmode)"
702 [(set_attr "op_type" "RR<E>")
703 (set_attr "z10prop" "z10_fr_E1")])
705 ; tst(hi|qi) instruction pattern(s).
707 (define_insn "*tst<mode>CCT"
708 [(set (reg CC_REGNUM)
709 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
710 (match_operand:HQI 1 "const0_operand" "")))
711 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
713 "s390_match_ccmode(insn, CCTmode)"
716 icmy\t%2,<icm_lo>,%S0
718 [(set_attr "op_type" "RS,RSY,RI")
719 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
721 (define_insn "*tsthiCCT_cconly"
722 [(set (reg CC_REGNUM)
723 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
724 (match_operand:HI 1 "const0_operand" "")))
725 (clobber (match_scratch:HI 2 "=d,d,X"))]
726 "s390_match_ccmode(insn, CCTmode)"
731 [(set_attr "op_type" "RS,RSY,RI")
732 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
734 (define_insn "*tstqiCCT_cconly"
735 [(set (reg CC_REGNUM)
736 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
737 (match_operand:QI 1 "const0_operand" "")))]
738 "s390_match_ccmode(insn, CCTmode)"
743 [(set_attr "op_type" "SI,SIY,RI")
744 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
746 (define_insn "*tst<mode>"
747 [(set (reg CC_REGNUM)
748 (compare (match_operand:HQI 0 "s_operand" "Q,S")
749 (match_operand:HQI 1 "const0_operand" "")))
750 (set (match_operand:HQI 2 "register_operand" "=d,d")
752 "s390_match_ccmode(insn, CCSmode)"
755 icmy\t%2,<icm_lo>,%S0"
756 [(set_attr "op_type" "RS,RSY")
757 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
759 (define_insn "*tst<mode>_cconly"
760 [(set (reg CC_REGNUM)
761 (compare (match_operand:HQI 0 "s_operand" "Q,S")
762 (match_operand:HQI 1 "const0_operand" "")))
763 (clobber (match_scratch:HQI 2 "=d,d"))]
764 "s390_match_ccmode(insn, CCSmode)"
767 icmy\t%2,<icm_lo>,%S0"
768 [(set_attr "op_type" "RS,RSY")
769 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
772 ; Compare (equality) instructions
774 (define_insn "*cmpdi_cct"
775 [(set (reg CC_REGNUM)
776 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
777 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
778 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
785 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
786 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
788 (define_insn "*cmpsi_cct"
789 [(set (reg CC_REGNUM)
790 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
791 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
792 "s390_match_ccmode (insn, CCTmode)"
800 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
801 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
803 ; Compare (signed) instructions
805 (define_insn "*cmpdi_ccs_sign"
806 [(set (reg CC_REGNUM)
807 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
809 (match_operand:DI 0 "register_operand" "d, d,d")))]
810 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
815 [(set_attr "op_type" "RRE,RXY,RIL")
816 (set_attr "z10prop" "z10_c,*,*")
817 (set_attr "type" "*,*,larl")])
821 (define_insn "*cmpsi_ccs_sign"
822 [(set (reg CC_REGNUM)
823 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
824 (match_operand:SI 0 "register_operand" "d,d,d")))]
825 "s390_match_ccmode(insn, CCSRmode)"
830 [(set_attr "op_type" "RX,RXY,RIL")
831 (set_attr "cpu_facility" "*,*,z10")
832 (set_attr "type" "*,*,larl")
833 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
835 (define_insn "*cmphi_ccs_z10"
836 [(set (reg CC_REGNUM)
837 (compare (match_operand:HI 0 "s_operand" "Q")
838 (match_operand:HI 1 "immediate_operand" "K")))]
839 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
841 [(set_attr "op_type" "SIL")
842 (set_attr "z196prop" "z196_cracked")])
844 (define_insn "*cmpdi_ccs_signhi_rl"
845 [(set (reg CC_REGNUM)
846 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
847 (match_operand:GPR 0 "register_operand" "d,d")))]
848 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
852 [(set_attr "op_type" "RXY,RIL")
853 (set_attr "type" "*,larl")])
855 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
856 (define_insn "*cmp<mode>_ccs"
857 [(set (reg CC_REGNUM)
858 (compare (match_operand:GPR 0 "nonimmediate_operand"
860 (match_operand:GPR 1 "general_operand"
862 "s390_match_ccmode(insn, CCSmode)"
871 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
872 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
873 (set_attr "type" "*,*,*,*,*,*,larl")
874 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
877 ; Compare (unsigned) instructions
879 (define_insn "*cmpsi_ccu_zerohi_rlsi"
880 [(set (reg CC_REGNUM)
881 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
882 "larl_operand" "X")))
883 (match_operand:SI 0 "register_operand" "d")))]
884 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
886 [(set_attr "op_type" "RIL")
887 (set_attr "type" "larl")
888 (set_attr "z10prop" "z10_super")])
891 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
892 [(set (reg CC_REGNUM)
893 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
894 "larl_operand" "X")))
895 (match_operand:GPR 0 "register_operand" "d")))]
896 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
898 [(set_attr "op_type" "RIL")
899 (set_attr "type" "larl")
900 (set_attr "z10prop" "z10_super")])
902 (define_insn "*cmpdi_ccu_zero"
903 [(set (reg CC_REGNUM)
904 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
906 (match_operand:DI 0 "register_operand" "d, d,d")))]
907 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
912 [(set_attr "op_type" "RRE,RXY,RIL")
913 (set_attr "cpu_facility" "*,*,z10")
914 (set_attr "type" "*,*,larl")
915 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
917 (define_insn "*cmpdi_ccu"
918 [(set (reg CC_REGNUM)
919 (compare (match_operand:DI 0 "nonimmediate_operand"
921 (match_operand:DI 1 "general_operand"
922 "d,Op,b,D,RT,BQ,Q")))]
923 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
932 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
933 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
934 (set_attr "type" "*,*,larl,*,*,*,*")
935 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
937 (define_insn "*cmpsi_ccu"
938 [(set (reg CC_REGNUM)
939 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
940 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
941 "s390_match_ccmode (insn, CCUmode)"
951 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
952 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
953 (set_attr "type" "*,*,larl,*,*,*,*,*")
954 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
956 (define_insn "*cmphi_ccu"
957 [(set (reg CC_REGNUM)
958 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
959 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
960 "s390_match_ccmode (insn, CCUmode)
961 && !register_operand (operands[1], HImode)"
968 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
969 (set_attr "cpu_facility" "*,*,z10,*,*")
970 (set_attr "z10prop" "*,*,z10_super,*,*")])
972 (define_insn "*cmpqi_ccu"
973 [(set (reg CC_REGNUM)
974 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
975 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
976 "s390_match_ccmode (insn, CCUmode)
977 && !register_operand (operands[1], QImode)"
985 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
986 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
989 ; Block compare (CLC) instruction patterns.
992 [(set (reg CC_REGNUM)
993 (compare (match_operand:BLK 0 "memory_operand" "Q")
994 (match_operand:BLK 1 "memory_operand" "Q")))
995 (use (match_operand 2 "const_int_operand" "n"))]
996 "s390_match_ccmode (insn, CCUmode)
997 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
998 "clc\t%O0(%2,%R0),%S1"
999 [(set_attr "op_type" "SS")])
1002 [(set (reg CC_REGNUM)
1003 (compare (match_operand 0 "memory_operand" "")
1004 (match_operand 1 "memory_operand" "")))]
1006 && s390_match_ccmode (insn, CCUmode)
1007 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1008 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1010 [(set (match_dup 0) (match_dup 1))
1011 (use (match_dup 2))])]
1013 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1014 operands[0] = adjust_address (operands[0], BLKmode, 0);
1015 operands[1] = adjust_address (operands[1], BLKmode, 0);
1017 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1018 operands[0], operands[1]);
1019 operands[0] = SET_DEST (PATTERN (curr_insn));
1023 ; (TF|DF|SF|TD|DD|SD) instructions
1025 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1026 (define_insn "*cmp<mode>_ccs_0"
1027 [(set (reg CC_REGNUM)
1028 (compare (match_operand:FP 0 "register_operand" "f")
1029 (match_operand:FP 1 "const0_operand" "")))]
1030 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1031 "lt<xde><bt>r\t%0,%0"
1032 [(set_attr "op_type" "RRE")
1033 (set_attr "type" "fsimp<mode>")])
1035 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1036 (define_insn "*cmp<mode>_ccs"
1037 [(set (reg CC_REGNUM)
1038 (compare (match_operand:FP 0 "register_operand" "f,f")
1039 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1040 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1044 [(set_attr "op_type" "RRE,RXE")
1045 (set_attr "type" "fsimp<mode>")])
1048 ; Compare and Branch instructions
1050 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1051 ; The following instructions do a complementary access of their second
1052 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1053 (define_insn "*cmp_and_br_signed_<mode>"
1055 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1056 [(match_operand:GPR 1 "register_operand" "d,d")
1057 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1058 (label_ref (match_operand 3 "" ""))
1060 (clobber (reg:CC CC_REGNUM))]
1061 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1063 if (get_attr_length (insn) == 6)
1064 return which_alternative ?
1065 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1067 return which_alternative ?
1068 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1070 [(set_attr "op_type" "RIE")
1071 (set_attr "type" "branch")
1072 (set_attr "z10prop" "z10_super_c,z10_super")
1073 (set (attr "length")
1074 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1075 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1076 ; 10 byte for cgr/jg
1078 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1079 ; The following instructions do a complementary access of their second
1080 ; operand (z10 only): clrj, clgrj, clr, clgr
1081 (define_insn "*cmp_and_br_unsigned_<mode>"
1083 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1084 [(match_operand:GPR 1 "register_operand" "d,d")
1085 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1086 (label_ref (match_operand 3 "" ""))
1088 (clobber (reg:CC CC_REGNUM))]
1089 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1091 if (get_attr_length (insn) == 6)
1092 return which_alternative ?
1093 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1095 return which_alternative ?
1096 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1098 [(set_attr "op_type" "RIE")
1099 (set_attr "type" "branch")
1100 (set_attr "z10prop" "z10_super_c,z10_super")
1101 (set (attr "length")
1102 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1103 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1104 ; 10 byte for clgr/jg
1106 ; And now the same two patterns as above but with a negated CC mask.
1108 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1109 ; The following instructions do a complementary access of their second
1110 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1111 (define_insn "*icmp_and_br_signed_<mode>"
1113 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1114 [(match_operand:GPR 1 "register_operand" "d,d")
1115 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1117 (label_ref (match_operand 3 "" ""))))
1118 (clobber (reg:CC CC_REGNUM))]
1119 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1121 if (get_attr_length (insn) == 6)
1122 return which_alternative ?
1123 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1125 return which_alternative ?
1126 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1128 [(set_attr "op_type" "RIE")
1129 (set_attr "type" "branch")
1130 (set_attr "z10prop" "z10_super_c,z10_super")
1131 (set (attr "length")
1132 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1133 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1134 ; 10 byte for cgr/jg
1136 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1137 ; The following instructions do a complementary access of their second
1138 ; operand (z10 only): clrj, clgrj, clr, clgr
1139 (define_insn "*icmp_and_br_unsigned_<mode>"
1141 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1142 [(match_operand:GPR 1 "register_operand" "d,d")
1143 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1145 (label_ref (match_operand 3 "" ""))))
1146 (clobber (reg:CC CC_REGNUM))]
1147 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1149 if (get_attr_length (insn) == 6)
1150 return which_alternative ?
1151 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1153 return which_alternative ?
1154 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1156 [(set_attr "op_type" "RIE")
1157 (set_attr "type" "branch")
1158 (set_attr "z10prop" "z10_super_c,z10_super")
1159 (set (attr "length")
1160 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1161 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1162 ; 10 byte for clgr/jg
1165 ;;- Move instructions.
1169 ; movti instruction pattern(s).
1172 (define_insn "movti"
1173 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1174 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1181 [(set_attr "op_type" "RSY,RSY,*,*")
1182 (set_attr "type" "lm,stm,*,*")])
1185 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1186 (match_operand:TI 1 "general_operand" ""))]
1187 "TARGET_ZARCH && reload_completed
1188 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1189 [(set (match_dup 2) (match_dup 4))
1190 (set (match_dup 3) (match_dup 5))]
1192 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1193 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1194 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1195 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1199 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1200 (match_operand:TI 1 "general_operand" ""))]
1201 "TARGET_ZARCH && reload_completed
1202 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1203 [(set (match_dup 2) (match_dup 4))
1204 (set (match_dup 3) (match_dup 5))]
1206 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1207 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1208 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1209 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1213 [(set (match_operand:TI 0 "register_operand" "")
1214 (match_operand:TI 1 "memory_operand" ""))]
1215 "TARGET_ZARCH && reload_completed
1216 && !s_operand (operands[1], VOIDmode)"
1217 [(set (match_dup 0) (match_dup 1))]
1219 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1220 addr = gen_lowpart (Pmode, addr);
1221 s390_load_address (addr, XEXP (operands[1], 0));
1222 operands[1] = replace_equiv_address (operands[1], addr);
1227 ; Patterns used for secondary reloads
1230 ; z10 provides move instructions accepting larl memory operands.
1231 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1232 ; These patterns are also used for unaligned SI and DI accesses.
1234 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1235 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1236 (match_operand:INTALL 1 "register_operand" "=d")
1237 (match_operand:P 2 "register_operand" "=&a")])]
1240 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1244 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1245 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1246 (match_operand:INTALL 1 "memory_operand" "")
1247 (match_operand:P 2 "register_operand" "=a")])]
1250 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1254 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1255 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1256 (match_operand:FPALL 1 "register_operand" "=d")
1257 (match_operand:P 2 "register_operand" "=&a")])]
1260 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1264 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1265 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1266 (match_operand:FPALL 1 "memory_operand" "")
1267 (match_operand:P 2 "register_operand" "=a")])]
1270 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1274 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1275 [(parallel [(match_operand:P 0 "register_operand" "=d")
1276 (match_operand:P 1 "larl_operand" "")
1277 (match_operand:P 2 "register_operand" "=a")])]
1280 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1284 ; Handles loading a PLUS (load address) expression
1286 (define_expand "reload<mode>_plus"
1287 [(parallel [(match_operand:P 0 "register_operand" "=a")
1288 (match_operand:P 1 "s390_plus_operand" "")
1289 (match_operand:P 2 "register_operand" "=&a")])]
1292 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1296 ; Handles assessing a non-offsetable memory address
1298 (define_expand "reload<mode>_nonoffmem_in"
1299 [(parallel [(match_operand 0 "register_operand" "")
1300 (match_operand 1 "" "")
1301 (match_operand:P 2 "register_operand" "=&a")])]
1304 gcc_assert (MEM_P (operands[1]));
1305 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1306 operands[1] = replace_equiv_address (operands[1], operands[2]);
1307 emit_move_insn (operands[0], operands[1]);
1311 (define_expand "reload<mode>_nonoffmem_out"
1312 [(parallel [(match_operand 0 "" "")
1313 (match_operand 1 "register_operand" "")
1314 (match_operand:P 2 "register_operand" "=&a")])]
1317 gcc_assert (MEM_P (operands[0]));
1318 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1319 operands[0] = replace_equiv_address (operands[0], operands[2]);
1320 emit_move_insn (operands[0], operands[1]);
1324 (define_expand "reload<mode>_PIC_addr"
1325 [(parallel [(match_operand 0 "register_operand" "=d")
1326 (match_operand 1 "larl_operand" "")
1327 (match_operand:P 2 "register_operand" "=a")])]
1330 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1331 emit_move_insn (operands[0], new_rtx);
1335 ; movdi instruction pattern(s).
1338 (define_expand "movdi"
1339 [(set (match_operand:DI 0 "general_operand" "")
1340 (match_operand:DI 1 "general_operand" ""))]
1343 /* Handle symbolic constants. */
1345 && (SYMBOLIC_CONST (operands[1])
1346 || (GET_CODE (operands[1]) == PLUS
1347 && XEXP (operands[1], 0) == pic_offset_table_rtx
1348 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1349 emit_symbolic_move (operands);
1352 (define_insn "*movdi_larl"
1353 [(set (match_operand:DI 0 "register_operand" "=d")
1354 (match_operand:DI 1 "larl_operand" "X"))]
1356 && !FP_REG_P (operands[0])"
1358 [(set_attr "op_type" "RIL")
1359 (set_attr "type" "larl")
1360 (set_attr "z10prop" "z10_super_A1")])
1362 (define_insn "*movdi_64"
1363 [(set (match_operand:DI 0 "nonimmediate_operand"
1364 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1365 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1366 (match_operand:DI 1 "general_operand"
1367 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1368 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1397 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1398 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1399 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1400 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1402 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1403 z10,*,*,*,*,*,longdisp,*,longdisp,
1405 (set_attr "z10prop" "z10_fwd_A1,
1434 [(set (match_operand:DI 0 "register_operand" "")
1435 (match_operand:DI 1 "register_operand" ""))]
1436 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1437 [(set (match_dup 2) (match_dup 3))
1438 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1439 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1440 "operands[2] = gen_lowpart (SImode, operands[0]);
1441 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1444 [(set (match_operand:DI 0 "register_operand" "")
1445 (match_operand:DI 1 "register_operand" ""))]
1446 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1447 && dead_or_set_p (insn, operands[1])"
1448 [(set (match_dup 3) (match_dup 2))
1449 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1450 (set (match_dup 4) (match_dup 2))]
1451 "operands[2] = gen_lowpart (SImode, operands[1]);
1452 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1455 [(set (match_operand:DI 0 "register_operand" "")
1456 (match_operand:DI 1 "register_operand" ""))]
1457 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1458 && !dead_or_set_p (insn, operands[1])"
1459 [(set (match_dup 3) (match_dup 2))
1460 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1461 (set (match_dup 4) (match_dup 2))
1462 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1463 "operands[2] = gen_lowpart (SImode, operands[1]);
1464 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1466 (define_insn "*movdi_31"
1467 [(set (match_operand:DI 0 "nonimmediate_operand"
1468 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1469 (match_operand:DI 1 "general_operand"
1470 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1485 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1486 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1487 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1489 ; For a load from a symbol ref we can use one of the target registers
1490 ; together with larl to load the address.
1492 [(set (match_operand:DI 0 "register_operand" "")
1493 (match_operand:DI 1 "memory_operand" ""))]
1494 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1495 && larl_operand (XEXP (operands[1], 0), SImode)"
1496 [(set (match_dup 2) (match_dup 3))
1497 (set (match_dup 0) (match_dup 1))]
1499 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1500 operands[3] = XEXP (operands[1], 0);
1501 operands[1] = replace_equiv_address (operands[1], operands[2]);
1505 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1506 (match_operand:DI 1 "general_operand" ""))]
1507 "!TARGET_ZARCH && reload_completed
1508 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1509 [(set (match_dup 2) (match_dup 4))
1510 (set (match_dup 3) (match_dup 5))]
1512 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1513 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1514 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1515 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1519 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1520 (match_operand:DI 1 "general_operand" ""))]
1521 "!TARGET_ZARCH && reload_completed
1522 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1523 [(set (match_dup 2) (match_dup 4))
1524 (set (match_dup 3) (match_dup 5))]
1526 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1527 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1528 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1529 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1533 [(set (match_operand:DI 0 "register_operand" "")
1534 (match_operand:DI 1 "memory_operand" ""))]
1535 "!TARGET_ZARCH && reload_completed
1536 && !FP_REG_P (operands[0])
1537 && !s_operand (operands[1], VOIDmode)"
1538 [(set (match_dup 0) (match_dup 1))]
1540 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1541 s390_load_address (addr, XEXP (operands[1], 0));
1542 operands[1] = replace_equiv_address (operands[1], addr);
1546 [(set (match_operand:DI 0 "register_operand" "")
1547 (mem:DI (match_operand 1 "address_operand" "")))]
1549 && !FP_REG_P (operands[0])
1550 && GET_CODE (operands[1]) == SYMBOL_REF
1551 && CONSTANT_POOL_ADDRESS_P (operands[1])
1552 && get_pool_mode (operands[1]) == DImode
1553 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1554 [(set (match_dup 0) (match_dup 2))]
1555 "operands[2] = get_pool_constant (operands[1]);")
1557 (define_insn "*la_64"
1558 [(set (match_operand:DI 0 "register_operand" "=d,d")
1559 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1564 [(set_attr "op_type" "RX,RXY")
1565 (set_attr "type" "la")
1566 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1570 [(set (match_operand:DI 0 "register_operand" "")
1571 (match_operand:QI 1 "address_operand" ""))
1572 (clobber (reg:CC CC_REGNUM))])]
1574 && preferred_la_operand_p (operands[1], const0_rtx)"
1575 [(set (match_dup 0) (match_dup 1))]
1579 [(set (match_operand:DI 0 "register_operand" "")
1580 (match_operand:DI 1 "register_operand" ""))
1583 (plus:DI (match_dup 0)
1584 (match_operand:DI 2 "nonmemory_operand" "")))
1585 (clobber (reg:CC CC_REGNUM))])]
1587 && !reg_overlap_mentioned_p (operands[0], operands[2])
1588 && preferred_la_operand_p (operands[1], operands[2])"
1589 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1593 ; movsi instruction pattern(s).
1596 (define_expand "movsi"
1597 [(set (match_operand:SI 0 "general_operand" "")
1598 (match_operand:SI 1 "general_operand" ""))]
1601 /* Handle symbolic constants. */
1603 && (SYMBOLIC_CONST (operands[1])
1604 || (GET_CODE (operands[1]) == PLUS
1605 && XEXP (operands[1], 0) == pic_offset_table_rtx
1606 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1607 emit_symbolic_move (operands);
1610 (define_insn "*movsi_larl"
1611 [(set (match_operand:SI 0 "register_operand" "=d")
1612 (match_operand:SI 1 "larl_operand" "X"))]
1613 "!TARGET_64BIT && TARGET_CPU_ZARCH
1614 && !FP_REG_P (operands[0])"
1616 [(set_attr "op_type" "RIL")
1617 (set_attr "type" "larl")
1618 (set_attr "z10prop" "z10_fwd_A1")])
1620 (define_insn "*movsi_zarch"
1621 [(set (match_operand:SI 0 "nonimmediate_operand"
1622 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1623 (match_operand:SI 1 "general_operand"
1624 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1649 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1650 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1651 (set_attr "type" "*,
1673 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1674 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1675 (set_attr "z10prop" "z10_fwd_A1,
1698 (define_insn "*movsi_esa"
1699 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1700 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1714 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1715 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1716 (set_attr "z10prop" "z10_fwd_A1,
1730 [(set (match_operand:SI 0 "register_operand" "")
1731 (mem:SI (match_operand 1 "address_operand" "")))]
1732 "!FP_REG_P (operands[0])
1733 && GET_CODE (operands[1]) == SYMBOL_REF
1734 && CONSTANT_POOL_ADDRESS_P (operands[1])
1735 && get_pool_mode (operands[1]) == SImode
1736 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1737 [(set (match_dup 0) (match_dup 2))]
1738 "operands[2] = get_pool_constant (operands[1]);")
1740 (define_insn "*la_31"
1741 [(set (match_operand:SI 0 "register_operand" "=d,d")
1742 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1743 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1747 [(set_attr "op_type" "RX,RXY")
1748 (set_attr "type" "la")
1749 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1753 [(set (match_operand:SI 0 "register_operand" "")
1754 (match_operand:QI 1 "address_operand" ""))
1755 (clobber (reg:CC CC_REGNUM))])]
1757 && preferred_la_operand_p (operands[1], const0_rtx)"
1758 [(set (match_dup 0) (match_dup 1))]
1762 [(set (match_operand:SI 0 "register_operand" "")
1763 (match_operand:SI 1 "register_operand" ""))
1766 (plus:SI (match_dup 0)
1767 (match_operand:SI 2 "nonmemory_operand" "")))
1768 (clobber (reg:CC CC_REGNUM))])]
1770 && !reg_overlap_mentioned_p (operands[0], operands[2])
1771 && preferred_la_operand_p (operands[1], operands[2])"
1772 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1775 (define_insn "*la_31_and"
1776 [(set (match_operand:SI 0 "register_operand" "=d,d")
1777 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1778 (const_int 2147483647)))]
1783 [(set_attr "op_type" "RX,RXY")
1784 (set_attr "type" "la")
1785 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1787 (define_insn_and_split "*la_31_and_cc"
1788 [(set (match_operand:SI 0 "register_operand" "=d")
1789 (and:SI (match_operand:QI 1 "address_operand" "p")
1790 (const_int 2147483647)))
1791 (clobber (reg:CC CC_REGNUM))]
1794 "&& reload_completed"
1796 (and:SI (match_dup 1) (const_int 2147483647)))]
1798 [(set_attr "op_type" "RX")
1799 (set_attr "type" "la")])
1801 (define_insn "force_la_31"
1802 [(set (match_operand:SI 0 "register_operand" "=d,d")
1803 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1804 (use (const_int 0))]
1809 [(set_attr "op_type" "RX")
1810 (set_attr "type" "la")
1811 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1814 ; movhi instruction pattern(s).
1817 (define_expand "movhi"
1818 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1819 (match_operand:HI 1 "general_operand" ""))]
1822 /* Make it explicit that loading a register from memory
1823 always sign-extends (at least) to SImode. */
1824 if (optimize && can_create_pseudo_p ()
1825 && register_operand (operands[0], VOIDmode)
1826 && GET_CODE (operands[1]) == MEM)
1828 rtx tmp = gen_reg_rtx (SImode);
1829 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1830 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1831 operands[1] = gen_lowpart (HImode, tmp);
1835 (define_insn "*movhi"
1836 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1837 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1849 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1850 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1851 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1852 (set_attr "z10prop" "z10_fr_E1,
1863 [(set (match_operand:HI 0 "register_operand" "")
1864 (mem:HI (match_operand 1 "address_operand" "")))]
1865 "GET_CODE (operands[1]) == SYMBOL_REF
1866 && CONSTANT_POOL_ADDRESS_P (operands[1])
1867 && get_pool_mode (operands[1]) == HImode
1868 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1869 [(set (match_dup 0) (match_dup 2))]
1870 "operands[2] = get_pool_constant (operands[1]);")
1873 ; movqi instruction pattern(s).
1876 (define_expand "movqi"
1877 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1878 (match_operand:QI 1 "general_operand" ""))]
1881 /* On z/Architecture, zero-extending from memory to register
1882 is just as fast as a QImode load. */
1883 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1884 && register_operand (operands[0], VOIDmode)
1885 && GET_CODE (operands[1]) == MEM)
1887 rtx tmp = gen_reg_rtx (DImode);
1888 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1889 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1890 operands[1] = gen_lowpart (QImode, tmp);
1894 (define_insn "*movqi"
1895 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1896 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1908 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1909 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1910 (set_attr "z10prop" "z10_fr_E1,
1921 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1922 (mem:QI (match_operand 1 "address_operand" "")))]
1923 "GET_CODE (operands[1]) == SYMBOL_REF
1924 && CONSTANT_POOL_ADDRESS_P (operands[1])
1925 && get_pool_mode (operands[1]) == QImode
1926 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1927 [(set (match_dup 0) (match_dup 2))]
1928 "operands[2] = get_pool_constant (operands[1]);")
1931 ; movstrictqi instruction pattern(s).
1934 (define_insn "*movstrictqi"
1935 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1936 (match_operand:QI 1 "memory_operand" "R,T"))]
1941 [(set_attr "op_type" "RX,RXY")
1942 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1945 ; movstricthi instruction pattern(s).
1948 (define_insn "*movstricthi"
1949 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1950 (match_operand:HI 1 "memory_operand" "Q,S"))
1951 (clobber (reg:CC CC_REGNUM))]
1956 [(set_attr "op_type" "RS,RSY")
1957 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1960 ; movstrictsi instruction pattern(s).
1963 (define_insn "movstrictsi"
1964 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1965 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1972 [(set_attr "op_type" "RR,RX,RXY,RRE")
1973 (set_attr "type" "lr,load,load,*")
1974 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1977 ; mov(tf|td) instruction pattern(s).
1980 (define_expand "mov<mode>"
1981 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1982 (match_operand:TD_TF 1 "general_operand" ""))]
1986 (define_insn "*mov<mode>_64"
1987 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1988 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1999 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2000 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2001 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2003 (define_insn "*mov<mode>_31"
2004 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2005 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2012 [(set_attr "op_type" "RRE,RRE,*,*")
2013 (set_attr "type" "fsimptf,fsimptf,*,*")
2014 (set_attr "cpu_facility" "z196,*,*,*")])
2016 ; TFmode in GPRs splitters
2019 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2020 (match_operand:TD_TF 1 "general_operand" ""))]
2021 "TARGET_ZARCH && reload_completed
2022 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2023 [(set (match_dup 2) (match_dup 4))
2024 (set (match_dup 3) (match_dup 5))]
2026 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2027 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2028 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2029 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2033 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2034 (match_operand:TD_TF 1 "general_operand" ""))]
2035 "TARGET_ZARCH && reload_completed
2036 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2037 [(set (match_dup 2) (match_dup 4))
2038 (set (match_dup 3) (match_dup 5))]
2040 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2041 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2042 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2043 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2047 [(set (match_operand:TD_TF 0 "register_operand" "")
2048 (match_operand:TD_TF 1 "memory_operand" ""))]
2049 "TARGET_ZARCH && reload_completed
2050 && !FP_REG_P (operands[0])
2051 && !s_operand (operands[1], VOIDmode)"
2052 [(set (match_dup 0) (match_dup 1))]
2054 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2055 addr = gen_lowpart (Pmode, addr);
2056 s390_load_address (addr, XEXP (operands[1], 0));
2057 operands[1] = replace_equiv_address (operands[1], addr);
2060 ; TFmode in BFPs splitters
2063 [(set (match_operand:TD_TF 0 "register_operand" "")
2064 (match_operand:TD_TF 1 "memory_operand" ""))]
2065 "reload_completed && offsettable_memref_p (operands[1])
2066 && FP_REG_P (operands[0])"
2067 [(set (match_dup 2) (match_dup 4))
2068 (set (match_dup 3) (match_dup 5))]
2070 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2072 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2074 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2075 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2079 [(set (match_operand:TD_TF 0 "memory_operand" "")
2080 (match_operand:TD_TF 1 "register_operand" ""))]
2081 "reload_completed && offsettable_memref_p (operands[0])
2082 && FP_REG_P (operands[1])"
2083 [(set (match_dup 2) (match_dup 4))
2084 (set (match_dup 3) (match_dup 5))]
2086 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2087 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2088 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2090 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2095 ; mov(df|dd) instruction pattern(s).
2098 (define_expand "mov<mode>"
2099 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2100 (match_operand:DD_DF 1 "general_operand" ""))]
2104 (define_insn "*mov<mode>_64dfp"
2105 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2106 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2107 (match_operand:DD_DF 1 "general_operand"
2108 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2123 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2124 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2125 fstoredf,fstoredf,*,lr,load,store")
2126 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2127 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2129 (define_insn "*mov<mode>_64"
2130 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2131 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2144 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2145 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2146 fstore<mode>,fstore<mode>,*,lr,load,store")
2147 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2148 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2150 (define_insn "*mov<mode>_31"
2151 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2152 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2153 (match_operand:DD_DF 1 "general_operand"
2154 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2169 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2170 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2171 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2172 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2175 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2176 (match_operand:DD_DF 1 "general_operand" ""))]
2177 "!TARGET_ZARCH && reload_completed
2178 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2179 [(set (match_dup 2) (match_dup 4))
2180 (set (match_dup 3) (match_dup 5))]
2182 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2183 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2184 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2185 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2189 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2190 (match_operand:DD_DF 1 "general_operand" ""))]
2191 "!TARGET_ZARCH && reload_completed
2192 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2193 [(set (match_dup 2) (match_dup 4))
2194 (set (match_dup 3) (match_dup 5))]
2196 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2197 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2198 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2199 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2203 [(set (match_operand:DD_DF 0 "register_operand" "")
2204 (match_operand:DD_DF 1 "memory_operand" ""))]
2205 "!TARGET_ZARCH && reload_completed
2206 && !FP_REG_P (operands[0])
2207 && !s_operand (operands[1], VOIDmode)"
2208 [(set (match_dup 0) (match_dup 1))]
2210 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2211 s390_load_address (addr, XEXP (operands[1], 0));
2212 operands[1] = replace_equiv_address (operands[1], addr);
2216 ; mov(sf|sd) instruction pattern(s).
2219 (define_insn "mov<mode>"
2220 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2221 "=f,f,f,f,R,T,d,d,d,d,R,T")
2222 (match_operand:SD_SF 1 "general_operand"
2223 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2238 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2239 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2240 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2241 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2242 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2245 ; movcc instruction pattern
2248 (define_insn "movcc"
2249 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2250 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2260 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2261 (set_attr "type" "lr,*,*,store,store,load,load")
2262 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2263 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2266 ; Block move (MVC) patterns.
2270 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2271 (match_operand:BLK 1 "memory_operand" "Q"))
2272 (use (match_operand 2 "const_int_operand" "n"))]
2273 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2274 "mvc\t%O0(%2,%R0),%S1"
2275 [(set_attr "op_type" "SS")])
2277 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2278 ; order to have it implemented with mvc.
2281 [(set (match_operand:QI 0 "memory_operand" "")
2282 (match_operand:QI 1 "memory_operand" ""))]
2285 [(set (match_dup 0) (match_dup 1))
2286 (use (const_int 1))])]
2288 operands[0] = adjust_address (operands[0], BLKmode, 0);
2289 operands[1] = adjust_address (operands[1], BLKmode, 0);
2295 [(set (match_operand:BLK 0 "memory_operand" "")
2296 (match_operand:BLK 1 "memory_operand" ""))
2297 (use (match_operand 2 "const_int_operand" ""))])
2299 [(set (match_operand:BLK 3 "memory_operand" "")
2300 (match_operand:BLK 4 "memory_operand" ""))
2301 (use (match_operand 5 "const_int_operand" ""))])]
2302 "s390_offset_p (operands[0], operands[3], operands[2])
2303 && s390_offset_p (operands[1], operands[4], operands[2])
2304 && !s390_overlap_p (operands[0], operands[1],
2305 INTVAL (operands[2]) + INTVAL (operands[5]))
2306 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2308 [(set (match_dup 6) (match_dup 7))
2309 (use (match_dup 8))])]
2310 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2311 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2312 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2316 ; load_multiple pattern(s).
2318 ; ??? Due to reload problems with replacing registers inside match_parallel
2319 ; we currently support load_multiple/store_multiple only after reload.
2322 (define_expand "load_multiple"
2323 [(match_par_dup 3 [(set (match_operand 0 "" "")
2324 (match_operand 1 "" ""))
2325 (use (match_operand 2 "" ""))])]
2328 enum machine_mode mode;
2334 /* Support only loading a constant number of fixed-point registers from
2335 memory and only bother with this if more than two */
2336 if (GET_CODE (operands[2]) != CONST_INT
2337 || INTVAL (operands[2]) < 2
2338 || INTVAL (operands[2]) > 16
2339 || GET_CODE (operands[1]) != MEM
2340 || GET_CODE (operands[0]) != REG
2341 || REGNO (operands[0]) >= 16)
2344 count = INTVAL (operands[2]);
2345 regno = REGNO (operands[0]);
2346 mode = GET_MODE (operands[0]);
2347 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2350 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2351 if (!can_create_pseudo_p ())
2353 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2355 from = XEXP (operands[1], 0);
2358 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2359 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2360 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2362 from = XEXP (XEXP (operands[1], 0), 0);
2363 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2370 from = force_reg (Pmode, XEXP (operands[1], 0));
2374 for (i = 0; i < count; i++)
2375 XVECEXP (operands[3], 0, i)
2376 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2377 change_address (operands[1], mode,
2378 plus_constant (Pmode, from,
2379 off + i * GET_MODE_SIZE (mode))));
2382 (define_insn "*load_multiple_di"
2383 [(match_parallel 0 "load_multiple_operation"
2384 [(set (match_operand:DI 1 "register_operand" "=r")
2385 (match_operand:DI 2 "s_operand" "QS"))])]
2386 "reload_completed && TARGET_ZARCH"
2388 int words = XVECLEN (operands[0], 0);
2389 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2390 return "lmg\t%1,%0,%S2";
2392 [(set_attr "op_type" "RSY")
2393 (set_attr "type" "lm")])
2395 (define_insn "*load_multiple_si"
2396 [(match_parallel 0 "load_multiple_operation"
2397 [(set (match_operand:SI 1 "register_operand" "=r,r")
2398 (match_operand:SI 2 "s_operand" "Q,S"))])]
2401 int words = XVECLEN (operands[0], 0);
2402 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2403 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2405 [(set_attr "op_type" "RS,RSY")
2406 (set_attr "type" "lm")])
2409 ; store multiple pattern(s).
2412 (define_expand "store_multiple"
2413 [(match_par_dup 3 [(set (match_operand 0 "" "")
2414 (match_operand 1 "" ""))
2415 (use (match_operand 2 "" ""))])]
2418 enum machine_mode mode;
2424 /* Support only storing a constant number of fixed-point registers to
2425 memory and only bother with this if more than two. */
2426 if (GET_CODE (operands[2]) != CONST_INT
2427 || INTVAL (operands[2]) < 2
2428 || INTVAL (operands[2]) > 16
2429 || GET_CODE (operands[0]) != MEM
2430 || GET_CODE (operands[1]) != REG
2431 || REGNO (operands[1]) >= 16)
2434 count = INTVAL (operands[2]);
2435 regno = REGNO (operands[1]);
2436 mode = GET_MODE (operands[1]);
2437 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2440 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2442 if (!can_create_pseudo_p ())
2444 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2446 to = XEXP (operands[0], 0);
2449 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2450 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2451 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2453 to = XEXP (XEXP (operands[0], 0), 0);
2454 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2461 to = force_reg (Pmode, XEXP (operands[0], 0));
2465 for (i = 0; i < count; i++)
2466 XVECEXP (operands[3], 0, i)
2467 = gen_rtx_SET (VOIDmode,
2468 change_address (operands[0], mode,
2469 plus_constant (Pmode, to,
2470 off + i * GET_MODE_SIZE (mode))),
2471 gen_rtx_REG (mode, regno + i));
2474 (define_insn "*store_multiple_di"
2475 [(match_parallel 0 "store_multiple_operation"
2476 [(set (match_operand:DI 1 "s_operand" "=QS")
2477 (match_operand:DI 2 "register_operand" "r"))])]
2478 "reload_completed && TARGET_ZARCH"
2480 int words = XVECLEN (operands[0], 0);
2481 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2482 return "stmg\t%2,%0,%S1";
2484 [(set_attr "op_type" "RSY")
2485 (set_attr "type" "stm")])
2488 (define_insn "*store_multiple_si"
2489 [(match_parallel 0 "store_multiple_operation"
2490 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2491 (match_operand:SI 2 "register_operand" "r,r"))])]
2494 int words = XVECLEN (operands[0], 0);
2495 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2496 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2498 [(set_attr "op_type" "RS,RSY")
2499 (set_attr "type" "stm")])
2502 ;; String instructions.
2505 (define_insn "*execute_rl"
2506 [(match_parallel 0 "execute_operation"
2507 [(unspec [(match_operand 1 "register_operand" "a")
2508 (match_operand 2 "" "")
2509 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2510 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2511 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2513 [(set_attr "op_type" "RIL")
2514 (set_attr "type" "cs")])
2516 (define_insn "*execute"
2517 [(match_parallel 0 "execute_operation"
2518 [(unspec [(match_operand 1 "register_operand" "a")
2519 (match_operand:BLK 2 "memory_operand" "R")
2520 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2521 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2522 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2524 [(set_attr "op_type" "RX")
2525 (set_attr "type" "cs")])
2529 ; strlenM instruction pattern(s).
2532 (define_expand "strlen<mode>"
2533 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2536 (unspec:P [(const_int 0)
2537 (match_operand:BLK 1 "memory_operand" "")
2539 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2540 (clobber (scratch:P))
2541 (clobber (reg:CC CC_REGNUM))])
2543 [(set (match_operand:P 0 "register_operand" "")
2544 (minus:P (match_dup 4) (match_dup 5)))
2545 (clobber (reg:CC CC_REGNUM))])]
2548 operands[4] = gen_reg_rtx (Pmode);
2549 operands[5] = gen_reg_rtx (Pmode);
2550 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2551 operands[1] = replace_equiv_address (operands[1], operands[5]);
2554 (define_insn "*strlen<mode>"
2555 [(set (match_operand:P 0 "register_operand" "=a")
2556 (unspec:P [(match_operand:P 2 "general_operand" "0")
2557 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2559 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2560 (clobber (match_scratch:P 1 "=a"))
2561 (clobber (reg:CC CC_REGNUM))]
2563 "srst\t%0,%1\;jo\t.-4"
2564 [(set_attr "length" "8")
2565 (set_attr "type" "vs")])
2568 ; cmpstrM instruction pattern(s).
2571 (define_expand "cmpstrsi"
2572 [(set (reg:SI 0) (const_int 0))
2574 [(clobber (match_operand 3 "" ""))
2575 (clobber (match_dup 4))
2576 (set (reg:CCU CC_REGNUM)
2577 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2578 (match_operand:BLK 2 "memory_operand" "")))
2581 [(set (match_operand:SI 0 "register_operand" "=d")
2582 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2583 (clobber (reg:CC CC_REGNUM))])]
2586 /* As the result of CMPINT is inverted compared to what we need,
2587 we have to swap the operands. */
2588 rtx op1 = operands[2];
2589 rtx op2 = operands[1];
2590 rtx addr1 = gen_reg_rtx (Pmode);
2591 rtx addr2 = gen_reg_rtx (Pmode);
2593 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2594 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2595 operands[1] = replace_equiv_address_nv (op1, addr1);
2596 operands[2] = replace_equiv_address_nv (op2, addr2);
2597 operands[3] = addr1;
2598 operands[4] = addr2;
2601 (define_insn "*cmpstr<mode>"
2602 [(clobber (match_operand:P 0 "register_operand" "=d"))
2603 (clobber (match_operand:P 1 "register_operand" "=d"))
2604 (set (reg:CCU CC_REGNUM)
2605 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2606 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2609 "clst\t%0,%1\;jo\t.-4"
2610 [(set_attr "length" "8")
2611 (set_attr "type" "vs")])
2614 ; movstr instruction pattern.
2617 (define_expand "movstr"
2618 [(set (reg:SI 0) (const_int 0))
2620 [(clobber (match_dup 3))
2621 (set (match_operand:BLK 1 "memory_operand" "")
2622 (match_operand:BLK 2 "memory_operand" ""))
2623 (set (match_operand 0 "register_operand" "")
2624 (unspec [(match_dup 1)
2626 (reg:SI 0)] UNSPEC_MVST))
2627 (clobber (reg:CC CC_REGNUM))])]
2630 rtx addr1 = gen_reg_rtx (Pmode);
2631 rtx addr2 = gen_reg_rtx (Pmode);
2633 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2634 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2635 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2636 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2637 operands[3] = addr2;
2640 (define_insn "*movstr"
2641 [(clobber (match_operand:P 2 "register_operand" "=d"))
2642 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2643 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2644 (set (match_operand:P 0 "register_operand" "=d")
2645 (unspec [(mem:BLK (match_dup 1))
2646 (mem:BLK (match_dup 3))
2647 (reg:SI 0)] UNSPEC_MVST))
2648 (clobber (reg:CC CC_REGNUM))]
2650 "mvst\t%1,%2\;jo\t.-4"
2651 [(set_attr "length" "8")
2652 (set_attr "type" "vs")])
2656 ; movmemM instruction pattern(s).
2659 (define_expand "movmem<mode>"
2660 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2661 (match_operand:BLK 1 "memory_operand" "")) ; source
2662 (use (match_operand:GPR 2 "general_operand" "")) ; count
2663 (match_operand 3 "" "")]
2666 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2672 ; Move a block that is up to 256 bytes in length.
2673 ; The block length is taken as (operands[2] % 256) + 1.
2675 (define_expand "movmem_short"
2677 [(set (match_operand:BLK 0 "memory_operand" "")
2678 (match_operand:BLK 1 "memory_operand" ""))
2679 (use (match_operand 2 "nonmemory_operand" ""))
2680 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2681 (clobber (match_dup 3))])]
2683 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2685 (define_insn "*movmem_short"
2686 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2687 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2688 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2689 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2690 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2691 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2693 [(set_attr "type" "cs")
2694 (set_attr "cpu_facility" "*,*,z10,*")])
2697 [(set (match_operand:BLK 0 "memory_operand" "")
2698 (match_operand:BLK 1 "memory_operand" ""))
2699 (use (match_operand 2 "const_int_operand" ""))
2700 (use (match_operand 3 "immediate_operand" ""))
2701 (clobber (scratch))]
2704 [(set (match_dup 0) (match_dup 1))
2705 (use (match_dup 2))])]
2706 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2709 [(set (match_operand:BLK 0 "memory_operand" "")
2710 (match_operand:BLK 1 "memory_operand" ""))
2711 (use (match_operand 2 "register_operand" ""))
2712 (use (match_operand 3 "memory_operand" ""))
2713 (clobber (scratch))]
2716 [(unspec [(match_dup 2) (match_dup 3)
2717 (const_int 0)] UNSPEC_EXECUTE)
2718 (set (match_dup 0) (match_dup 1))
2719 (use (const_int 1))])]
2723 [(set (match_operand:BLK 0 "memory_operand" "")
2724 (match_operand:BLK 1 "memory_operand" ""))
2725 (use (match_operand 2 "register_operand" ""))
2726 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2727 (clobber (scratch))]
2728 "TARGET_Z10 && reload_completed"
2730 [(unspec [(match_dup 2) (const_int 0)
2731 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2732 (set (match_dup 0) (match_dup 1))
2733 (use (const_int 1))])]
2734 "operands[3] = gen_label_rtx ();")
2737 [(set (match_operand:BLK 0 "memory_operand" "")
2738 (match_operand:BLK 1 "memory_operand" ""))
2739 (use (match_operand 2 "register_operand" ""))
2740 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2741 (clobber (match_operand 3 "register_operand" ""))]
2742 "reload_completed && TARGET_CPU_ZARCH"
2743 [(set (match_dup 3) (label_ref (match_dup 4)))
2745 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2746 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2747 (set (match_dup 0) (match_dup 1))
2748 (use (const_int 1))])]
2749 "operands[4] = gen_label_rtx ();")
2751 ; Move a block of arbitrary length.
2753 (define_expand "movmem_long"
2755 [(clobber (match_dup 2))
2756 (clobber (match_dup 3))
2757 (set (match_operand:BLK 0 "memory_operand" "")
2758 (match_operand:BLK 1 "memory_operand" ""))
2759 (use (match_operand 2 "general_operand" ""))
2761 (clobber (reg:CC CC_REGNUM))])]
2764 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2765 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2766 rtx reg0 = gen_reg_rtx (dreg_mode);
2767 rtx reg1 = gen_reg_rtx (dreg_mode);
2768 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2769 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2770 rtx len0 = gen_lowpart (Pmode, reg0);
2771 rtx len1 = gen_lowpart (Pmode, reg1);
2773 emit_clobber (reg0);
2774 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2775 emit_move_insn (len0, operands[2]);
2777 emit_clobber (reg1);
2778 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2779 emit_move_insn (len1, operands[2]);
2781 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2782 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2787 (define_insn "*movmem_long"
2788 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2789 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2790 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2791 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2794 (clobber (reg:CC CC_REGNUM))]
2795 "TARGET_64BIT || !TARGET_ZARCH"
2796 "mvcle\t%0,%1,0\;jo\t.-4"
2797 [(set_attr "length" "8")
2798 (set_attr "type" "vs")])
2800 (define_insn "*movmem_long_31z"
2801 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2802 (clobber (match_operand:TI 1 "register_operand" "=d"))
2803 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2804 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2807 (clobber (reg:CC CC_REGNUM))]
2808 "!TARGET_64BIT && TARGET_ZARCH"
2809 "mvcle\t%0,%1,0\;jo\t.-4"
2810 [(set_attr "length" "8")
2811 (set_attr "type" "vs")])
2818 (define_expand "signbit<mode>2"
2819 [(set (reg:CCZ CC_REGNUM)
2820 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2823 (set (match_operand:SI 0 "register_operand" "=d")
2824 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2827 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2830 (define_expand "isinf<mode>2"
2831 [(set (reg:CCZ CC_REGNUM)
2832 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2835 (set (match_operand:SI 0 "register_operand" "=d")
2836 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2839 operands[2] = GEN_INT (S390_TDC_INFINITY);
2842 ; This insn is used to generate all variants of the Test Data Class
2843 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2844 ; is the register to be tested and the second one is the bit mask
2845 ; specifying the required test(s).
2847 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2848 (define_insn "*TDC_insn_<mode>"
2849 [(set (reg:CCZ CC_REGNUM)
2850 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2851 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2853 "t<_d>c<xde><bt>\t%0,%1"
2854 [(set_attr "op_type" "RXE")
2855 (set_attr "type" "fsimp<mode>")])
2857 (define_insn_and_split "*ccz_to_int"
2858 [(set (match_operand:SI 0 "register_operand" "=d")
2859 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2860 UNSPEC_CCZ_TO_INT))]
2864 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2868 ; setmemM instruction pattern(s).
2871 (define_expand "setmem<mode>"
2872 [(set (match_operand:BLK 0 "memory_operand" "")
2873 (match_operand:QI 2 "general_operand" ""))
2874 (use (match_operand:GPR 1 "general_operand" ""))
2875 (match_operand 3 "" "")]
2877 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2879 ; Clear a block that is up to 256 bytes in length.
2880 ; The block length is taken as (operands[1] % 256) + 1.
2882 (define_expand "clrmem_short"
2884 [(set (match_operand:BLK 0 "memory_operand" "")
2886 (use (match_operand 1 "nonmemory_operand" ""))
2887 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2888 (clobber (match_dup 2))
2889 (clobber (reg:CC CC_REGNUM))])]
2891 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2893 (define_insn "*clrmem_short"
2894 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2896 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2897 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2898 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2899 (clobber (reg:CC CC_REGNUM))]
2900 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2902 [(set_attr "type" "cs")
2903 (set_attr "cpu_facility" "*,*,z10,*")])
2906 [(set (match_operand:BLK 0 "memory_operand" "")
2908 (use (match_operand 1 "const_int_operand" ""))
2909 (use (match_operand 2 "immediate_operand" ""))
2911 (clobber (reg:CC CC_REGNUM))]
2914 [(set (match_dup 0) (const_int 0))
2916 (clobber (reg:CC CC_REGNUM))])]
2917 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2920 [(set (match_operand:BLK 0 "memory_operand" "")
2922 (use (match_operand 1 "register_operand" ""))
2923 (use (match_operand 2 "memory_operand" ""))
2925 (clobber (reg:CC CC_REGNUM))]
2928 [(unspec [(match_dup 1) (match_dup 2)
2929 (const_int 0)] UNSPEC_EXECUTE)
2930 (set (match_dup 0) (const_int 0))
2932 (clobber (reg:CC CC_REGNUM))])]
2936 [(set (match_operand:BLK 0 "memory_operand" "")
2938 (use (match_operand 1 "register_operand" ""))
2939 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2941 (clobber (reg:CC CC_REGNUM))]
2942 "TARGET_Z10 && reload_completed"
2944 [(unspec [(match_dup 1) (const_int 0)
2945 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2946 (set (match_dup 0) (const_int 0))
2948 (clobber (reg:CC CC_REGNUM))])]
2949 "operands[3] = gen_label_rtx ();")
2952 [(set (match_operand:BLK 0 "memory_operand" "")
2954 (use (match_operand 1 "register_operand" ""))
2955 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2956 (clobber (match_operand 2 "register_operand" ""))
2957 (clobber (reg:CC CC_REGNUM))]
2958 "reload_completed && TARGET_CPU_ZARCH"
2959 [(set (match_dup 2) (label_ref (match_dup 3)))
2961 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2962 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2963 (set (match_dup 0) (const_int 0))
2965 (clobber (reg:CC CC_REGNUM))])]
2966 "operands[3] = gen_label_rtx ();")
2968 ; Initialize a block of arbitrary length with (operands[2] % 256).
2970 (define_expand "setmem_long"
2972 [(clobber (match_dup 1))
2973 (set (match_operand:BLK 0 "memory_operand" "")
2974 (match_operand 2 "shift_count_or_setmem_operand" ""))
2975 (use (match_operand 1 "general_operand" ""))
2977 (clobber (reg:CC CC_REGNUM))])]
2980 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2981 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2982 rtx reg0 = gen_reg_rtx (dreg_mode);
2983 rtx reg1 = gen_reg_rtx (dreg_mode);
2984 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2985 rtx len0 = gen_lowpart (Pmode, reg0);
2987 emit_clobber (reg0);
2988 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2989 emit_move_insn (len0, operands[1]);
2991 emit_move_insn (reg1, const0_rtx);
2993 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2998 (define_insn "*setmem_long"
2999 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3000 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3001 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3003 (use (match_operand:<DBL> 1 "register_operand" "d"))
3004 (clobber (reg:CC CC_REGNUM))]
3005 "TARGET_64BIT || !TARGET_ZARCH"
3006 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3007 [(set_attr "length" "8")
3008 (set_attr "type" "vs")])
3010 (define_insn "*setmem_long_and"
3011 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3012 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3013 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3014 (match_operand 4 "const_int_operand" "n")))
3016 (use (match_operand:<DBL> 1 "register_operand" "d"))
3017 (clobber (reg:CC CC_REGNUM))]
3018 "(TARGET_64BIT || !TARGET_ZARCH) &&
3019 (INTVAL (operands[4]) & 255) == 255"
3020 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3021 [(set_attr "length" "8")
3022 (set_attr "type" "vs")])
3024 (define_insn "*setmem_long_31z"
3025 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3026 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3027 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3029 (use (match_operand:TI 1 "register_operand" "d"))
3030 (clobber (reg:CC CC_REGNUM))]
3031 "!TARGET_64BIT && TARGET_ZARCH"
3032 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3033 [(set_attr "length" "8")
3034 (set_attr "type" "vs")])
3037 ; cmpmemM instruction pattern(s).
3040 (define_expand "cmpmemsi"
3041 [(set (match_operand:SI 0 "register_operand" "")
3042 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3043 (match_operand:BLK 2 "memory_operand" "") ) )
3044 (use (match_operand:SI 3 "general_operand" ""))
3045 (use (match_operand:SI 4 "" ""))]
3048 if (s390_expand_cmpmem (operands[0], operands[1],
3049 operands[2], operands[3]))
3055 ; Compare a block that is up to 256 bytes in length.
3056 ; The block length is taken as (operands[2] % 256) + 1.
3058 (define_expand "cmpmem_short"
3060 [(set (reg:CCU CC_REGNUM)
3061 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3062 (match_operand:BLK 1 "memory_operand" "")))
3063 (use (match_operand 2 "nonmemory_operand" ""))
3064 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3065 (clobber (match_dup 3))])]
3067 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3069 (define_insn "*cmpmem_short"
3070 [(set (reg:CCU CC_REGNUM)
3071 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3072 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3073 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3074 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3075 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3076 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3078 [(set_attr "type" "cs")
3079 (set_attr "cpu_facility" "*,*,z10,*")])
3082 [(set (reg:CCU CC_REGNUM)
3083 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3084 (match_operand:BLK 1 "memory_operand" "")))
3085 (use (match_operand 2 "const_int_operand" ""))
3086 (use (match_operand 3 "immediate_operand" ""))
3087 (clobber (scratch))]
3090 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3091 (use (match_dup 2))])]
3092 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3095 [(set (reg:CCU CC_REGNUM)
3096 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3097 (match_operand:BLK 1 "memory_operand" "")))
3098 (use (match_operand 2 "register_operand" ""))
3099 (use (match_operand 3 "memory_operand" ""))
3100 (clobber (scratch))]
3103 [(unspec [(match_dup 2) (match_dup 3)
3104 (const_int 0)] UNSPEC_EXECUTE)
3105 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3106 (use (const_int 1))])]
3110 [(set (reg:CCU CC_REGNUM)
3111 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3112 (match_operand:BLK 1 "memory_operand" "")))
3113 (use (match_operand 2 "register_operand" ""))
3114 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3115 (clobber (scratch))]
3116 "TARGET_Z10 && reload_completed"
3118 [(unspec [(match_dup 2) (const_int 0)
3119 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3120 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3121 (use (const_int 1))])]
3122 "operands[4] = gen_label_rtx ();")
3125 [(set (reg:CCU CC_REGNUM)
3126 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3127 (match_operand:BLK 1 "memory_operand" "")))
3128 (use (match_operand 2 "register_operand" ""))
3129 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3130 (clobber (match_operand 3 "register_operand" ""))]
3131 "reload_completed && TARGET_CPU_ZARCH"
3132 [(set (match_dup 3) (label_ref (match_dup 4)))
3134 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3135 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3136 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3137 (use (const_int 1))])]
3138 "operands[4] = gen_label_rtx ();")
3140 ; Compare a block of arbitrary length.
3142 (define_expand "cmpmem_long"
3144 [(clobber (match_dup 2))
3145 (clobber (match_dup 3))
3146 (set (reg:CCU CC_REGNUM)
3147 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3148 (match_operand:BLK 1 "memory_operand" "")))
3149 (use (match_operand 2 "general_operand" ""))
3150 (use (match_dup 3))])]
3153 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3154 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3155 rtx reg0 = gen_reg_rtx (dreg_mode);
3156 rtx reg1 = gen_reg_rtx (dreg_mode);
3157 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3158 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3159 rtx len0 = gen_lowpart (Pmode, reg0);
3160 rtx len1 = gen_lowpart (Pmode, reg1);
3162 emit_clobber (reg0);
3163 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3164 emit_move_insn (len0, operands[2]);
3166 emit_clobber (reg1);
3167 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3168 emit_move_insn (len1, operands[2]);
3170 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3171 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3176 (define_insn "*cmpmem_long"
3177 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3178 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3179 (set (reg:CCU CC_REGNUM)
3180 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3181 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3183 (use (match_dup 3))]
3184 "TARGET_64BIT || !TARGET_ZARCH"
3185 "clcle\t%0,%1,0\;jo\t.-4"
3186 [(set_attr "length" "8")
3187 (set_attr "type" "vs")])
3189 (define_insn "*cmpmem_long_31z"
3190 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3191 (clobber (match_operand:TI 1 "register_operand" "=d"))
3192 (set (reg:CCU CC_REGNUM)
3193 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3194 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3196 (use (match_dup 3))]
3197 "!TARGET_64BIT && TARGET_ZARCH"
3198 "clcle\t%0,%1,0\;jo\t.-4"
3199 [(set_attr "op_type" "NN")
3200 (set_attr "type" "vs")
3201 (set_attr "length" "8")])
3203 ; Convert CCUmode condition code to integer.
3204 ; Result is zero if EQ, positive if LTU, negative if GTU.
3206 (define_insn_and_split "cmpint"
3207 [(set (match_operand:SI 0 "register_operand" "=d")
3208 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3210 (clobber (reg:CC CC_REGNUM))]
3214 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3216 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3217 (clobber (reg:CC CC_REGNUM))])])
3219 (define_insn_and_split "*cmpint_cc"
3220 [(set (reg CC_REGNUM)
3221 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3224 (set (match_operand:SI 0 "register_operand" "=d")
3225 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3226 "s390_match_ccmode (insn, CCSmode)"
3228 "&& reload_completed"
3229 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3231 [(set (match_dup 2) (match_dup 3))
3232 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3234 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3235 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3236 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3239 (define_insn_and_split "*cmpint_sign"
3240 [(set (match_operand:DI 0 "register_operand" "=d")
3241 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3242 UNSPEC_CCU_TO_INT)))
3243 (clobber (reg:CC CC_REGNUM))]
3246 "&& reload_completed"
3247 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3249 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3250 (clobber (reg:CC CC_REGNUM))])])
3252 (define_insn_and_split "*cmpint_sign_cc"
3253 [(set (reg CC_REGNUM)
3254 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3255 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3256 UNSPEC_CCU_TO_INT) 0)
3257 (const_int 32)) (const_int 32))
3259 (set (match_operand:DI 0 "register_operand" "=d")
3260 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3261 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3263 "&& reload_completed"
3264 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3266 [(set (match_dup 2) (match_dup 3))
3267 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3269 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3270 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3271 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3276 ;;- Conversion instructions.
3279 (define_insn "*sethighpartsi"
3280 [(set (match_operand:SI 0 "register_operand" "=d,d")
3281 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3282 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3283 (clobber (reg:CC CC_REGNUM))]
3288 [(set_attr "op_type" "RS,RSY")
3289 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3291 (define_insn "*sethighpartdi_64"
3292 [(set (match_operand:DI 0 "register_operand" "=d")
3293 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3294 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3295 (clobber (reg:CC CC_REGNUM))]
3298 [(set_attr "op_type" "RSY")
3299 (set_attr "z10prop" "z10_super")])
3301 (define_insn "*sethighpartdi_31"
3302 [(set (match_operand:DI 0 "register_operand" "=d,d")
3303 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3304 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3305 (clobber (reg:CC CC_REGNUM))]
3310 [(set_attr "op_type" "RS,RSY")
3311 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3314 ; extv instruction patterns
3317 ; FIXME: This expander needs to be converted from DI to GPR as well
3318 ; after resolving some issues with it.
3320 (define_expand "extzv"
3322 [(set (match_operand:DI 0 "register_operand" "=d")
3324 (match_operand:DI 1 "register_operand" "d")
3325 (match_operand 2 "const_int_operand" "") ; size
3326 (match_operand 3 "const_int_operand" ""))) ; start
3327 (clobber (reg:CC CC_REGNUM))])]
3330 /* Starting with zEC12 there is risbgn not clobbering CC. */
3333 emit_move_insn (operands[0],
3334 gen_rtx_ZERO_EXTRACT (DImode,
3342 (define_insn "*extzv<mode>_zEC12"
3343 [(set (match_operand:GPR 0 "register_operand" "=d")
3345 (match_operand:GPR 1 "register_operand" "d")
3346 (match_operand 2 "const_int_operand" "") ; size
3347 (match_operand 3 "const_int_operand" "")))] ; start]
3349 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3350 [(set_attr "op_type" "RIE")])
3352 (define_insn "*extzv<mode>_z10"
3353 [(set (match_operand:GPR 0 "register_operand" "=d")
3355 (match_operand:GPR 1 "register_operand" "d")
3356 (match_operand 2 "const_int_operand" "") ; size
3357 (match_operand 3 "const_int_operand" ""))) ; start
3358 (clobber (reg:CC CC_REGNUM))]
3360 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3361 [(set_attr "op_type" "RIE")
3362 (set_attr "z10prop" "z10_super_E1")])
3364 (define_insn_and_split "*pre_z10_extzv<mode>"
3365 [(set (match_operand:GPR 0 "register_operand" "=d")
3366 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3367 (match_operand 2 "nonzero_shift_count_operand" "")
3369 (clobber (reg:CC CC_REGNUM))]
3372 "&& reload_completed"
3374 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3375 (clobber (reg:CC CC_REGNUM))])
3376 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3378 int bitsize = INTVAL (operands[2]);
3379 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3380 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3382 operands[1] = adjust_address (operands[1], BLKmode, 0);
3383 set_mem_size (operands[1], size);
3384 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3385 operands[3] = GEN_INT (mask);
3388 (define_insn_and_split "*pre_z10_extv<mode>"
3389 [(set (match_operand:GPR 0 "register_operand" "=d")
3390 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3391 (match_operand 2 "nonzero_shift_count_operand" "")
3393 (clobber (reg:CC CC_REGNUM))]
3396 "&& reload_completed"
3398 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3399 (clobber (reg:CC CC_REGNUM))])
3401 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3402 (clobber (reg:CC CC_REGNUM))])]
3404 int bitsize = INTVAL (operands[2]);
3405 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3406 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3408 operands[1] = adjust_address (operands[1], BLKmode, 0);
3409 set_mem_size (operands[1], size);
3410 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3411 operands[3] = GEN_INT (mask);
3415 ; insv instruction patterns
3418 (define_expand "insv"
3419 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3420 (match_operand 1 "const_int_operand" "")
3421 (match_operand 2 "const_int_operand" ""))
3422 (match_operand 3 "general_operand" ""))]
3425 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3431 ; The normal RTL expansion will never generate a zero_extract where
3432 ; the location operand isn't word mode. However, we do this in the
3433 ; back-end when generating atomic operations. See s390_two_part_insv.
3434 (define_insn "*insv<mode>_zEC12"
3435 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3436 (match_operand 1 "const_int_operand" "I") ; size
3437 (match_operand 2 "const_int_operand" "I")) ; pos
3438 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3440 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3441 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3442 [(set_attr "op_type" "RIE")])
3444 (define_insn "*insv<mode>_z10"
3445 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3446 (match_operand 1 "const_int_operand" "I") ; size
3447 (match_operand 2 "const_int_operand" "I")) ; pos
3448 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3449 (clobber (reg:CC CC_REGNUM))]
3451 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3452 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3453 [(set_attr "op_type" "RIE")
3454 (set_attr "z10prop" "z10_super_E1")])
3456 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3457 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3458 (define_insn "*insv<mode>_zEC12_noshift"
3459 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3460 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3461 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3462 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3463 (match_operand:GPR 4 "const_int_operand" ""))))]
3464 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3465 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3466 [(set_attr "op_type" "RIE")])
3468 (define_insn "*insv<mode>_z10_noshift"
3469 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3470 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3471 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3472 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3473 (match_operand:GPR 4 "const_int_operand" ""))))
3474 (clobber (reg:CC CC_REGNUM))]
3475 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3476 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3477 [(set_attr "op_type" "RIE")
3478 (set_attr "z10prop" "z10_super_E1")])
3480 (define_insn "*r<noxa>sbg_<mode>_noshift"
3481 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3483 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3484 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3485 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3486 (clobber (reg:CC CC_REGNUM))]
3488 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3489 [(set_attr "op_type" "RIE")])
3491 (define_insn "*r<noxa>sbg_di_rotl"
3492 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3496 (match_operand:DI 1 "nonimmediate_operand" "d")
3497 (match_operand:DI 3 "const_int_operand" ""))
3498 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3499 (match_operand:DI 4 "nonimmediate_operand" "0")))
3500 (clobber (reg:CC CC_REGNUM))]
3502 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3503 [(set_attr "op_type" "RIE")])
3505 (define_insn "*r<noxa>sbg_<mode>_srl"
3506 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3510 (match_operand:GPR 1 "nonimmediate_operand" "d")
3511 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3512 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3513 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3514 (clobber (reg:CC CC_REGNUM))]
3516 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3517 INTVAL (operands[2]))"
3518 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3519 [(set_attr "op_type" "RIE")])
3521 (define_insn "*r<noxa>sbg_<mode>_sll"
3522 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3526 (match_operand:GPR 1 "nonimmediate_operand" "d")
3527 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3528 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3529 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3530 (clobber (reg:CC CC_REGNUM))]
3532 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3533 INTVAL (operands[2]))"
3534 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3535 [(set_attr "op_type" "RIE")])
3537 ;; These two are generated by combine for s.bf &= val.
3538 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3539 ;; shifts and ands, which results in some truly awful patterns
3540 ;; including subregs of operations. Rather unnecessisarily, IMO.
3543 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3544 ;; (const_int 24 [0x18])
3545 ;; (const_int 0 [0]))
3546 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3547 ;; (const_int 40 [0x28])) 4)
3548 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3550 ;; we should instead generate
3552 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3553 ;; (const_int 24 [0x18])
3554 ;; (const_int 0 [0]))
3555 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3556 ;; (const_int 40 [0x28]))
3557 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3559 ;; by noticing that we can push down the outer paradoxical subreg
3560 ;; into the operation.
3562 (define_insn "*insv_rnsbg_noshift"
3563 [(set (zero_extract:DI
3564 (match_operand:DI 0 "nonimmediate_operand" "+d")
3565 (match_operand 1 "const_int_operand" "")
3566 (match_operand 2 "const_int_operand" ""))
3569 (match_operand:DI 3 "nonimmediate_operand" "d")))
3570 (clobber (reg:CC CC_REGNUM))]
3572 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3573 "rnsbg\t%0,%3,%2,63,0"
3574 [(set_attr "op_type" "RIE")])
3576 (define_insn "*insv_rnsbg_srl"
3577 [(set (zero_extract:DI
3578 (match_operand:DI 0 "nonimmediate_operand" "+d")
3579 (match_operand 1 "const_int_operand" "")
3580 (match_operand 2 "const_int_operand" ""))
3584 (match_operand 3 "const_int_operand" ""))
3585 (match_operand:DI 4 "nonimmediate_operand" "d")))
3586 (clobber (reg:CC CC_REGNUM))]
3588 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3589 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3590 [(set_attr "op_type" "RIE")])
3592 (define_insn "*insv<mode>_mem_reg"
3593 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3594 (match_operand 1 "const_int_operand" "n,n")
3596 (match_operand:W 2 "register_operand" "d,d"))]
3597 "INTVAL (operands[1]) > 0
3598 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3599 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3601 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3603 operands[1] = GEN_INT ((1ul << size) - 1);
3604 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3605 : "stcmy\t%2,%1,%S0";
3607 [(set_attr "op_type" "RS,RSY")
3608 (set_attr "z10prop" "z10_super,z10_super")])
3610 (define_insn "*insvdi_mem_reghigh"
3611 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3612 (match_operand 1 "const_int_operand" "n")
3614 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3617 && INTVAL (operands[1]) > 0
3618 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3619 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3621 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3623 operands[1] = GEN_INT ((1ul << size) - 1);
3624 return "stcmh\t%2,%1,%S0";
3626 [(set_attr "op_type" "RSY")
3627 (set_attr "z10prop" "z10_super")])
3629 (define_insn "*insvdi_reg_imm"
3630 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3632 (match_operand 1 "const_int_operand" "n"))
3633 (match_operand:DI 2 "const_int_operand" "n"))]
3635 && INTVAL (operands[1]) >= 0
3636 && INTVAL (operands[1]) < BITS_PER_WORD
3637 && INTVAL (operands[1]) % 16 == 0"
3639 switch (BITS_PER_WORD - INTVAL (operands[1]))
3641 case 64: return "iihh\t%0,%x2"; break;
3642 case 48: return "iihl\t%0,%x2"; break;
3643 case 32: return "iilh\t%0,%x2"; break;
3644 case 16: return "iill\t%0,%x2"; break;
3645 default: gcc_unreachable();
3648 [(set_attr "op_type" "RI")
3649 (set_attr "z10prop" "z10_super_E1")])
3651 ; Update the left-most 32 bit of a DI.
3652 (define_insn "*insv_h_di_reg_extimm"
3653 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3656 (match_operand:DI 1 "const_int_operand" "n"))]
3659 [(set_attr "op_type" "RIL")
3660 (set_attr "z10prop" "z10_fwd_E1")])
3662 ; Update the right-most 32 bit of a DI.
3663 (define_insn "*insv_l_di_reg_extimm"
3664 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3667 (match_operand:DI 1 "const_int_operand" "n"))]
3670 [(set_attr "op_type" "RIL")
3671 (set_attr "z10prop" "z10_fwd_A1")])
3674 ; extendsidi2 instruction pattern(s).
3677 (define_expand "extendsidi2"
3678 [(set (match_operand:DI 0 "register_operand" "")
3679 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3684 emit_clobber (operands[0]);
3685 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3686 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3687 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3692 (define_insn "*extendsidi2"
3693 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3694 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3700 [(set_attr "op_type" "RRE,RXY,RIL")
3701 (set_attr "type" "*,*,larl")
3702 (set_attr "cpu_facility" "*,*,z10")
3703 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3706 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3709 (define_expand "extend<HQI:mode><DSI:mode>2"
3710 [(set (match_operand:DSI 0 "register_operand" "")
3711 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3714 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3716 rtx tmp = gen_reg_rtx (SImode);
3717 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3718 emit_insn (gen_extendsidi2 (operands[0], tmp));
3721 else if (!TARGET_EXTIMM)
3723 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3725 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3726 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3727 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3733 ; extendhidi2 instruction pattern(s).
3736 (define_insn "*extendhidi2_extimm"
3737 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3738 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3739 "TARGET_ZARCH && TARGET_EXTIMM"
3744 [(set_attr "op_type" "RRE,RXY,RIL")
3745 (set_attr "type" "*,*,larl")
3746 (set_attr "cpu_facility" "extimm,extimm,z10")
3747 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3749 (define_insn "*extendhidi2"
3750 [(set (match_operand:DI 0 "register_operand" "=d")
3751 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3754 [(set_attr "op_type" "RXY")
3755 (set_attr "z10prop" "z10_super_E1")])
3758 ; extendhisi2 instruction pattern(s).
3761 (define_insn "*extendhisi2_extimm"
3762 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3763 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3770 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3771 (set_attr "type" "*,*,*,larl")
3772 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3773 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3775 (define_insn "*extendhisi2"
3776 [(set (match_operand:SI 0 "register_operand" "=d,d")
3777 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3782 [(set_attr "op_type" "RX,RXY")
3783 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3786 ; extendqi(si|di)2 instruction pattern(s).
3789 ; lbr, lgbr, lb, lgb
3790 (define_insn "*extendqi<mode>2_extimm"
3791 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3792 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3797 [(set_attr "op_type" "RRE,RXY")
3798 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3801 (define_insn "*extendqi<mode>2"
3802 [(set (match_operand:GPR 0 "register_operand" "=d")
3803 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3804 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3806 [(set_attr "op_type" "RXY")
3807 (set_attr "z10prop" "z10_super_E1")])
3809 (define_insn_and_split "*extendqi<mode>2_short_displ"
3810 [(set (match_operand:GPR 0 "register_operand" "=d")
3811 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3812 (clobber (reg:CC CC_REGNUM))]
3813 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3815 "&& reload_completed"
3817 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3818 (clobber (reg:CC CC_REGNUM))])
3820 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3821 (clobber (reg:CC CC_REGNUM))])]
3823 operands[1] = adjust_address (operands[1], BLKmode, 0);
3824 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3825 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3829 ; zero_extendsidi2 instruction pattern(s).
3832 (define_expand "zero_extendsidi2"
3833 [(set (match_operand:DI 0 "register_operand" "")
3834 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3839 emit_clobber (operands[0]);
3840 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3841 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3846 (define_insn "*zero_extendsidi2"
3847 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3848 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3854 [(set_attr "op_type" "RRE,RXY,RIL")
3855 (set_attr "type" "*,*,larl")
3856 (set_attr "cpu_facility" "*,*,z10")
3857 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3860 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3863 (define_insn "*llgt_sidi"
3864 [(set (match_operand:DI 0 "register_operand" "=d")
3865 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3866 (const_int 2147483647)))]
3869 [(set_attr "op_type" "RXE")
3870 (set_attr "z10prop" "z10_super_E1")])
3872 (define_insn_and_split "*llgt_sidi_split"
3873 [(set (match_operand:DI 0 "register_operand" "=d")
3874 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3875 (const_int 2147483647)))
3876 (clobber (reg:CC CC_REGNUM))]
3879 "&& reload_completed"
3881 (and:DI (subreg:DI (match_dup 1) 0)
3882 (const_int 2147483647)))]
3885 (define_insn "*llgt_sisi"
3886 [(set (match_operand:SI 0 "register_operand" "=d,d")
3887 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3888 (const_int 2147483647)))]
3893 [(set_attr "op_type" "RRE,RXE")
3894 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3896 (define_insn "*llgt_didi"
3897 [(set (match_operand:DI 0 "register_operand" "=d,d")
3898 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3899 (const_int 2147483647)))]
3904 [(set_attr "op_type" "RRE,RXE")
3905 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3908 [(set (match_operand:DSI 0 "register_operand" "")
3909 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3910 (const_int 2147483647)))
3911 (clobber (reg:CC CC_REGNUM))]
3912 "TARGET_ZARCH && reload_completed"
3914 (and:DSI (match_dup 1)
3915 (const_int 2147483647)))]
3919 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3922 (define_expand "zero_extend<mode>di2"
3923 [(set (match_operand:DI 0 "register_operand" "")
3924 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3929 rtx tmp = gen_reg_rtx (SImode);
3930 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3931 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3934 else if (!TARGET_EXTIMM)
3936 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
3937 operands[1] = gen_lowpart (DImode, operands[1]);
3938 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3939 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3944 (define_expand "zero_extend<mode>si2"
3945 [(set (match_operand:SI 0 "register_operand" "")
3946 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3951 operands[1] = gen_lowpart (SImode, operands[1]);
3952 emit_insn (gen_andsi3 (operands[0], operands[1],
3953 GEN_INT ((1 << <HQI:bitsize>) - 1)));
3959 (define_insn "*zero_extendhi<mode>2_z10"
3960 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3961 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3967 [(set_attr "op_type" "RXY,RRE,RIL")
3968 (set_attr "type" "*,*,larl")
3969 (set_attr "cpu_facility" "*,*,z10")
3970 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3972 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3973 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3974 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3975 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3980 [(set_attr "op_type" "RRE,RXY")
3981 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3984 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3985 [(set (match_operand:GPR 0 "register_operand" "=d")
3986 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3987 "TARGET_ZARCH && !TARGET_EXTIMM"
3989 [(set_attr "op_type" "RXY")
3990 (set_attr "z10prop" "z10_fwd_A3")])
3992 (define_insn_and_split "*zero_extendhisi2_31"
3993 [(set (match_operand:SI 0 "register_operand" "=&d")
3994 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3995 (clobber (reg:CC CC_REGNUM))]
3998 "&& reload_completed"
3999 [(set (match_dup 0) (const_int 0))
4001 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4002 (clobber (reg:CC CC_REGNUM))])]
4003 "operands[2] = gen_lowpart (HImode, operands[0]);")
4005 (define_insn_and_split "*zero_extendqisi2_31"
4006 [(set (match_operand:SI 0 "register_operand" "=&d")
4007 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4010 "&& reload_completed"
4011 [(set (match_dup 0) (const_int 0))
4012 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4013 "operands[2] = gen_lowpart (QImode, operands[0]);")
4016 ; zero_extendqihi2 instruction pattern(s).
4019 (define_expand "zero_extendqihi2"
4020 [(set (match_operand:HI 0 "register_operand" "")
4021 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4022 "TARGET_ZARCH && !TARGET_EXTIMM"
4024 operands[1] = gen_lowpart (HImode, operands[1]);
4025 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4029 (define_insn "*zero_extendqihi2_64"
4030 [(set (match_operand:HI 0 "register_operand" "=d")
4031 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4032 "TARGET_ZARCH && !TARGET_EXTIMM"
4034 [(set_attr "op_type" "RXY")
4035 (set_attr "z10prop" "z10_fwd_A3")])
4037 (define_insn_and_split "*zero_extendqihi2_31"
4038 [(set (match_operand:HI 0 "register_operand" "=&d")
4039 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4042 "&& reload_completed"
4043 [(set (match_dup 0) (const_int 0))
4044 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4045 "operands[2] = gen_lowpart (QImode, operands[0]);")
4048 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4051 (define_expand "fixuns_truncdddi2"
4053 [(set (match_operand:DI 0 "register_operand" "")
4054 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4055 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4056 (clobber (reg:CC CC_REGNUM))])]
4062 rtx label1 = gen_label_rtx ();
4063 rtx label2 = gen_label_rtx ();
4064 rtx temp = gen_reg_rtx (TDmode);
4065 REAL_VALUE_TYPE cmp, sub;
4067 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4068 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4070 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4071 solution is doing the check and the subtraction in TD mode and using a
4072 TD -> DI convert afterwards. */
4073 emit_insn (gen_extendddtd2 (temp, operands[1]));
4074 temp = force_reg (TDmode, temp);
4075 emit_cmp_and_jump_insns (temp,
4076 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4077 LT, NULL_RTX, VOIDmode, 0, label1);
4078 emit_insn (gen_subtd3 (temp, temp,
4079 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4080 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4083 emit_label (label1);
4084 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4085 emit_label (label2);
4090 (define_expand "fixuns_trunctddi2"
4092 [(set (match_operand:DI 0 "register_operand" "")
4093 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4094 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4095 (clobber (reg:CC CC_REGNUM))])]
4101 rtx label1 = gen_label_rtx ();
4102 rtx label2 = gen_label_rtx ();
4103 rtx temp = gen_reg_rtx (TDmode);
4104 REAL_VALUE_TYPE cmp, sub;
4106 operands[1] = force_reg (TDmode, operands[1]);
4107 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4108 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4110 emit_cmp_and_jump_insns (operands[1],
4111 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4112 LT, NULL_RTX, VOIDmode, 0, label1);
4113 emit_insn (gen_subtd3 (temp, operands[1],
4114 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4115 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4118 emit_label (label1);
4119 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4120 emit_label (label2);
4126 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4127 ; instruction pattern(s).
4130 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4132 [(set (match_operand:GPR 0 "register_operand" "")
4133 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4134 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4135 (clobber (reg:CC CC_REGNUM))])]
4140 rtx label1 = gen_label_rtx ();
4141 rtx label2 = gen_label_rtx ();
4142 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4143 REAL_VALUE_TYPE cmp, sub;
4145 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4146 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4147 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4149 emit_cmp_and_jump_insns (operands[1],
4150 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4151 LT, NULL_RTX, VOIDmode, 0, label1);
4152 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4153 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4154 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4158 emit_label (label1);
4159 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4160 operands[1], GEN_INT (5)));
4161 emit_label (label2);
4166 ; fixuns_trunc(td|dd)si2 expander
4167 (define_expand "fixuns_trunc<mode>si2"
4169 [(set (match_operand:SI 0 "register_operand" "")
4170 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4171 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4172 (clobber (reg:CC CC_REGNUM))])]
4173 "TARGET_Z196 && TARGET_HARD_DFP"
4176 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4178 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4179 ; clfdtr, clfxtr, clgdtr, clgxtr
4180 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4181 [(set (match_operand:GPR 0 "register_operand" "=r")
4182 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4183 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4184 (clobber (reg:CC CC_REGNUM))]
4186 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4187 [(set_attr "op_type" "RRF")
4188 (set_attr "type" "ftoi")])
4190 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4191 [(set (match_operand:GPR 0 "register_operand" "")
4192 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4195 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4200 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4201 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4202 [(set (match_operand:GPR 0 "register_operand" "=d")
4203 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4204 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4205 (clobber (reg:CC CC_REGNUM))]
4207 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4208 [(set_attr "op_type" "RRE")
4209 (set_attr "type" "ftoi")])
4213 ; fix_trunc(td|dd)di2 instruction pattern(s).
4216 (define_expand "fix_trunc<mode>di2"
4217 [(set (match_operand:DI 0 "register_operand" "")
4218 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4219 "TARGET_ZARCH && TARGET_HARD_DFP"
4221 operands[1] = force_reg (<MODE>mode, operands[1]);
4222 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4228 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4229 [(set (match_operand:DI 0 "register_operand" "=d")
4230 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4231 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4232 (clobber (reg:CC CC_REGNUM))]
4233 "TARGET_ZARCH && TARGET_HARD_DFP"
4234 "cg<DFP:xde>tr\t%0,%h2,%1"
4235 [(set_attr "op_type" "RRF")
4236 (set_attr "type" "ftoidfp")])
4240 ; fix_trunctf(si|di)2 instruction pattern(s).
4243 (define_expand "fix_trunctf<mode>2"
4244 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4245 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4246 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4247 (clobber (reg:CC CC_REGNUM))])]
4253 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4256 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4257 (define_insn "floatdi<mode>2"
4258 [(set (match_operand:FP 0 "register_operand" "=f")
4259 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4260 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4261 "c<xde>g<bt>r\t%0,%1"
4262 [(set_attr "op_type" "RRE")
4263 (set_attr "type" "itof<mode>" )])
4265 ; cxfbr, cdfbr, cefbr
4266 (define_insn "floatsi<mode>2"
4267 [(set (match_operand:BFP 0 "register_operand" "=f")
4268 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4271 [(set_attr "op_type" "RRE")
4272 (set_attr "type" "itof<mode>" )])
4275 (define_insn "floatsi<mode>2"
4276 [(set (match_operand:DFP 0 "register_operand" "=f")
4277 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4278 "TARGET_Z196 && TARGET_HARD_FLOAT"
4279 "c<xde>ftr\t%0,0,%1,0"
4280 [(set_attr "op_type" "RRE")
4281 (set_attr "type" "itof<mode>" )])
4284 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4287 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4288 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4289 (define_insn "floatuns<GPR:mode><FP:mode>2"
4290 [(set (match_operand:FP 0 "register_operand" "=f")
4291 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4292 "TARGET_Z196 && TARGET_HARD_FLOAT"
4293 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4294 [(set_attr "op_type" "RRE")
4295 (set_attr "type" "itof<FP:mode>" )])
4298 ; truncdfsf2 instruction pattern(s).
4301 (define_insn "truncdfsf2"
4302 [(set (match_operand:SF 0 "register_operand" "=f")
4303 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4306 [(set_attr "op_type" "RRE")
4307 (set_attr "type" "ftruncdf")])
4310 ; trunctf(df|sf)2 instruction pattern(s).
4314 (define_insn "trunctf<mode>2"
4315 [(set (match_operand:DSF 0 "register_operand" "=f")
4316 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4317 (clobber (match_scratch:TF 2 "=f"))]
4319 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4320 [(set_attr "length" "6")
4321 (set_attr "type" "ftrunctf")])
4324 ; trunctddd2 and truncddsd2 instruction pattern(s).
4327 (define_insn "trunctddd2"
4328 [(set (match_operand:DD 0 "register_operand" "=f")
4329 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4330 (clobber (match_scratch:TD 2 "=f"))]
4332 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4333 [(set_attr "length" "6")
4334 (set_attr "type" "ftruncdd")])
4336 (define_insn "truncddsd2"
4337 [(set (match_operand:SD 0 "register_operand" "=f")
4338 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4341 [(set_attr "op_type" "RRF")
4342 (set_attr "type" "ftruncsd")])
4345 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4348 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4349 (define_insn "extend<DSF:mode><BFP:mode>2"
4350 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4351 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4353 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4355 l<BFP:xde><DSF:xde>br\t%0,%1
4356 l<BFP:xde><DSF:xde>b\t%0,%1"
4357 [(set_attr "op_type" "RRE,RXE")
4358 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4361 ; extendddtd2 and extendsddd2 instruction pattern(s).
4364 (define_insn "extendddtd2"
4365 [(set (match_operand:TD 0 "register_operand" "=f")
4366 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4369 [(set_attr "op_type" "RRF")
4370 (set_attr "type" "fsimptf")])
4372 (define_insn "extendsddd2"
4373 [(set (match_operand:DD 0 "register_operand" "=f")
4374 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4377 [(set_attr "op_type" "RRF")
4378 (set_attr "type" "fsimptf")])
4380 ; Binary <-> Decimal floating point trunc patterns
4383 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4384 [(set (reg:DFP_ALL FPR0_REGNUM)
4385 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4386 (use (reg:SI GPR0_REGNUM))
4387 (clobber (reg:CC CC_REGNUM))]
4391 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4392 [(set (reg:BFP FPR0_REGNUM)
4393 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4394 (use (reg:SI GPR0_REGNUM))
4395 (clobber (reg:CC CC_REGNUM))]
4399 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4400 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4401 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4403 [(set (reg:DFP_ALL FPR0_REGNUM)
4404 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4405 (use (reg:SI GPR0_REGNUM))
4406 (clobber (reg:CC CC_REGNUM))])
4407 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4408 (reg:DFP_ALL FPR0_REGNUM))]
4410 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4412 HOST_WIDE_INT flags;
4414 flags = (PFPO_CONVERT |
4415 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4416 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4418 operands[2] = GEN_INT (flags);
4421 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4422 [(set (reg:DFP_ALL FPR2_REGNUM)
4423 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4424 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4426 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4427 (use (reg:SI GPR0_REGNUM))
4428 (clobber (reg:CC CC_REGNUM))])
4429 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4431 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4433 HOST_WIDE_INT flags;
4435 flags = (PFPO_CONVERT |
4436 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4437 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4439 operands[2] = GEN_INT (flags);
4443 ; Binary <-> Decimal floating point extend patterns
4446 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4447 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4448 (use (reg:SI GPR0_REGNUM))
4449 (clobber (reg:CC CC_REGNUM))]
4453 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4454 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4455 (use (reg:SI GPR0_REGNUM))
4456 (clobber (reg:CC CC_REGNUM))]
4460 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4461 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4462 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4464 [(set (reg:DFP_ALL FPR0_REGNUM)
4465 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4466 (use (reg:SI GPR0_REGNUM))
4467 (clobber (reg:CC CC_REGNUM))])
4468 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4469 (reg:DFP_ALL FPR0_REGNUM))]
4471 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4473 HOST_WIDE_INT flags;
4475 flags = (PFPO_CONVERT |
4476 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4477 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4479 operands[2] = GEN_INT (flags);
4482 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4483 [(set (reg:DFP_ALL FPR2_REGNUM)
4484 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4485 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4487 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4488 (use (reg:SI GPR0_REGNUM))
4489 (clobber (reg:CC CC_REGNUM))])
4490 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4492 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4494 HOST_WIDE_INT flags;
4496 flags = (PFPO_CONVERT |
4497 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4498 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4500 operands[2] = GEN_INT (flags);
4505 ;; ARITHMETIC OPERATIONS
4507 ; arithmetic operations set the ConditionCode,
4508 ; because of unpredictable Bits in Register for Halfword and Byte
4509 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4512 ;;- Add instructions.
4516 ; addti3 instruction pattern(s).
4519 (define_insn_and_split "addti3"
4520 [(set (match_operand:TI 0 "register_operand" "=&d")
4521 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4522 (match_operand:TI 2 "general_operand" "do") ) )
4523 (clobber (reg:CC CC_REGNUM))]
4526 "&& reload_completed"
4528 [(set (reg:CCL1 CC_REGNUM)
4529 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4531 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4533 [(set (match_dup 3) (plus:DI
4534 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4535 (match_dup 4)) (match_dup 5)))
4536 (clobber (reg:CC CC_REGNUM))])]
4537 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4538 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4539 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4540 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4541 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4542 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4545 ; adddi3 instruction pattern(s).
4548 (define_expand "adddi3"
4550 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4551 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4552 (match_operand:DI 2 "general_operand" "")))
4553 (clobber (reg:CC CC_REGNUM))])]
4557 (define_insn "*adddi3_sign"
4558 [(set (match_operand:DI 0 "register_operand" "=d,d")
4559 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4560 (match_operand:DI 1 "register_operand" "0,0")))
4561 (clobber (reg:CC CC_REGNUM))]
4566 [(set_attr "op_type" "RRE,RXY")
4567 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4569 (define_insn "*adddi3_zero_cc"
4570 [(set (reg CC_REGNUM)
4571 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4572 (match_operand:DI 1 "register_operand" "0,0"))
4574 (set (match_operand:DI 0 "register_operand" "=d,d")
4575 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4576 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4580 [(set_attr "op_type" "RRE,RXY")
4581 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4583 (define_insn "*adddi3_zero_cconly"
4584 [(set (reg CC_REGNUM)
4585 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4586 (match_operand:DI 1 "register_operand" "0,0"))
4588 (clobber (match_scratch:DI 0 "=d,d"))]
4589 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4593 [(set_attr "op_type" "RRE,RXY")
4594 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4596 (define_insn "*adddi3_zero"
4597 [(set (match_operand:DI 0 "register_operand" "=d,d")
4598 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4599 (match_operand:DI 1 "register_operand" "0,0")))
4600 (clobber (reg:CC CC_REGNUM))]
4605 [(set_attr "op_type" "RRE,RXY")
4606 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4608 (define_insn_and_split "*adddi3_31z"
4609 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4610 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4611 (match_operand:DI 2 "general_operand" "do") ) )
4612 (clobber (reg:CC CC_REGNUM))]
4613 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4615 "&& reload_completed"
4617 [(set (reg:CCL1 CC_REGNUM)
4618 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4620 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4622 [(set (match_dup 3) (plus:SI
4623 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4624 (match_dup 4)) (match_dup 5)))
4625 (clobber (reg:CC CC_REGNUM))])]
4626 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4627 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4628 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4629 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4630 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4631 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4633 (define_insn_and_split "*adddi3_31"
4634 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4635 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4636 (match_operand:DI 2 "general_operand" "do") ) )
4637 (clobber (reg:CC CC_REGNUM))]
4640 "&& reload_completed"
4642 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4643 (clobber (reg:CC CC_REGNUM))])
4645 [(set (reg:CCL1 CC_REGNUM)
4646 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4648 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4650 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4652 (label_ref (match_dup 9))))
4654 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4655 (clobber (reg:CC CC_REGNUM))])
4657 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4658 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4659 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4660 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4661 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4662 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4663 operands[9] = gen_label_rtx ();")
4666 ; addsi3 instruction pattern(s).
4669 (define_expand "addsi3"
4671 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4672 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4673 (match_operand:SI 2 "general_operand" "")))
4674 (clobber (reg:CC CC_REGNUM))])]
4678 (define_insn "*addsi3_sign"
4679 [(set (match_operand:SI 0 "register_operand" "=d,d")
4680 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4681 (match_operand:SI 1 "register_operand" "0,0")))
4682 (clobber (reg:CC CC_REGNUM))]
4687 [(set_attr "op_type" "RX,RXY")
4688 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4691 ; add(di|si)3 instruction pattern(s).
4694 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4695 (define_insn "*add<mode>3"
4696 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4697 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4698 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4699 (clobber (reg:CC CC_REGNUM))]
4711 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4712 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4713 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4714 z10_super_E1,z10_super_E1,z10_super_E1")])
4716 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4717 (define_insn "*add<mode>3_carry1_cc"
4718 [(set (reg CC_REGNUM)
4719 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4720 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4722 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4723 (plus:GPR (match_dup 1) (match_dup 2)))]
4724 "s390_match_ccmode (insn, CCL1mode)"
4730 al<g>hsik\t%0,%1,%h2
4734 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4735 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4736 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4737 z10_super_E1,z10_super_E1,z10_super_E1")])
4739 ; alr, al, aly, algr, alg, alrk, algrk
4740 (define_insn "*add<mode>3_carry1_cconly"
4741 [(set (reg CC_REGNUM)
4742 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4743 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4745 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4746 "s390_match_ccmode (insn, CCL1mode)"
4752 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4753 (set_attr "cpu_facility" "*,z196,*,*")
4754 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4756 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4757 (define_insn "*add<mode>3_carry2_cc"
4758 [(set (reg CC_REGNUM)
4759 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4760 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4762 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4763 (plus:GPR (match_dup 1) (match_dup 2)))]
4764 "s390_match_ccmode (insn, CCL1mode)"
4770 al<g>hsik\t%0,%1,%h2
4774 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4775 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4776 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4777 z10_super_E1,z10_super_E1,z10_super_E1")])
4779 ; alr, al, aly, algr, alg, alrk, algrk
4780 (define_insn "*add<mode>3_carry2_cconly"
4781 [(set (reg CC_REGNUM)
4782 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4783 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4785 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4786 "s390_match_ccmode (insn, CCL1mode)"
4792 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4793 (set_attr "cpu_facility" "*,z196,*,*")
4794 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4796 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4797 (define_insn "*add<mode>3_cc"
4798 [(set (reg CC_REGNUM)
4799 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4800 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4802 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4803 (plus:GPR (match_dup 1) (match_dup 2)))]
4804 "s390_match_ccmode (insn, CCLmode)"
4810 al<g>hsik\t%0,%1,%h2
4814 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4815 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4816 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4817 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4819 ; alr, al, aly, algr, alg, alrk, algrk
4820 (define_insn "*add<mode>3_cconly"
4821 [(set (reg CC_REGNUM)
4822 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4823 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4825 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4826 "s390_match_ccmode (insn, CCLmode)"
4832 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4833 (set_attr "cpu_facility" "*,z196,*,*")
4834 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4836 ; alr, al, aly, algr, alg, alrk, algrk
4837 (define_insn "*add<mode>3_cconly2"
4838 [(set (reg CC_REGNUM)
4839 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4840 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4841 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4842 "s390_match_ccmode(insn, CCLmode)"
4848 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4849 (set_attr "cpu_facility" "*,z196,*,*")
4850 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4852 ; ahi, afi, aghi, agfi, asi, agsi
4853 (define_insn "*add<mode>3_imm_cc"
4854 [(set (reg CC_REGNUM)
4855 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4856 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4858 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4859 (plus:GPR (match_dup 1) (match_dup 2)))]
4860 "s390_match_ccmode (insn, CCAmode)
4861 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4862 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4863 /* Avoid INT32_MIN on 32 bit. */
4864 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
4870 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4871 (set_attr "cpu_facility" "*,z196,extimm,z10")
4872 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4875 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4878 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4879 (define_insn "add<mode>3"
4880 [(set (match_operand:FP 0 "register_operand" "=f, f")
4881 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4882 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4883 (clobber (reg:CC CC_REGNUM))]
4886 a<xde><bt>r\t%0,<op1>%2
4888 [(set_attr "op_type" "<RRer>,RXE")
4889 (set_attr "type" "fsimp<mode>")])
4891 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4892 (define_insn "*add<mode>3_cc"
4893 [(set (reg CC_REGNUM)
4894 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4895 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4896 (match_operand:FP 3 "const0_operand" "")))
4897 (set (match_operand:FP 0 "register_operand" "=f,f")
4898 (plus:FP (match_dup 1) (match_dup 2)))]
4899 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4901 a<xde><bt>r\t%0,<op1>%2
4903 [(set_attr "op_type" "<RRer>,RXE")
4904 (set_attr "type" "fsimp<mode>")])
4906 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4907 (define_insn "*add<mode>3_cconly"
4908 [(set (reg CC_REGNUM)
4909 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4910 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4911 (match_operand:FP 3 "const0_operand" "")))
4912 (clobber (match_scratch:FP 0 "=f,f"))]
4913 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4915 a<xde><bt>r\t%0,<op1>%2
4917 [(set_attr "op_type" "<RRer>,RXE")
4918 (set_attr "type" "fsimp<mode>")])
4922 ;;- Subtract instructions.
4926 ; subti3 instruction pattern(s).
4929 (define_insn_and_split "subti3"
4930 [(set (match_operand:TI 0 "register_operand" "=&d")
4931 (minus:TI (match_operand:TI 1 "register_operand" "0")
4932 (match_operand:TI 2 "general_operand" "do") ) )
4933 (clobber (reg:CC CC_REGNUM))]
4936 "&& reload_completed"
4938 [(set (reg:CCL2 CC_REGNUM)
4939 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4941 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4943 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4944 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4945 (clobber (reg:CC CC_REGNUM))])]
4946 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4947 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4948 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4949 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4950 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4951 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4954 ; subdi3 instruction pattern(s).
4957 (define_expand "subdi3"
4959 [(set (match_operand:DI 0 "register_operand" "")
4960 (minus:DI (match_operand:DI 1 "register_operand" "")
4961 (match_operand:DI 2 "general_operand" "")))
4962 (clobber (reg:CC CC_REGNUM))])]
4966 (define_insn "*subdi3_sign"
4967 [(set (match_operand:DI 0 "register_operand" "=d,d")
4968 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4969 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4970 (clobber (reg:CC CC_REGNUM))]
4975 [(set_attr "op_type" "RRE,RXY")
4976 (set_attr "z10prop" "z10_c,*")
4977 (set_attr "z196prop" "z196_cracked")])
4979 (define_insn "*subdi3_zero_cc"
4980 [(set (reg CC_REGNUM)
4981 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4982 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4984 (set (match_operand:DI 0 "register_operand" "=d,d")
4985 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4986 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4990 [(set_attr "op_type" "RRE,RXY")
4991 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4993 (define_insn "*subdi3_zero_cconly"
4994 [(set (reg CC_REGNUM)
4995 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4996 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4998 (clobber (match_scratch:DI 0 "=d,d"))]
4999 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5003 [(set_attr "op_type" "RRE,RXY")
5004 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5006 (define_insn "*subdi3_zero"
5007 [(set (match_operand:DI 0 "register_operand" "=d,d")
5008 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5009 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5010 (clobber (reg:CC CC_REGNUM))]
5015 [(set_attr "op_type" "RRE,RXY")
5016 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5018 (define_insn_and_split "*subdi3_31z"
5019 [(set (match_operand:DI 0 "register_operand" "=&d")
5020 (minus:DI (match_operand:DI 1 "register_operand" "0")
5021 (match_operand:DI 2 "general_operand" "do") ) )
5022 (clobber (reg:CC CC_REGNUM))]
5023 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5025 "&& reload_completed"
5027 [(set (reg:CCL2 CC_REGNUM)
5028 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5030 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5032 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5033 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5034 (clobber (reg:CC CC_REGNUM))])]
5035 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5036 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5037 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5038 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5039 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5040 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5042 (define_insn_and_split "*subdi3_31"
5043 [(set (match_operand:DI 0 "register_operand" "=&d")
5044 (minus:DI (match_operand:DI 1 "register_operand" "0")
5045 (match_operand:DI 2 "general_operand" "do") ) )
5046 (clobber (reg:CC CC_REGNUM))]
5049 "&& reload_completed"
5051 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5052 (clobber (reg:CC CC_REGNUM))])
5054 [(set (reg:CCL2 CC_REGNUM)
5055 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5057 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5059 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5061 (label_ref (match_dup 9))))
5063 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5064 (clobber (reg:CC CC_REGNUM))])
5066 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5067 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5068 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5069 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5070 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5071 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5072 operands[9] = gen_label_rtx ();")
5075 ; subsi3 instruction pattern(s).
5078 (define_expand "subsi3"
5080 [(set (match_operand:SI 0 "register_operand" "")
5081 (minus:SI (match_operand:SI 1 "register_operand" "")
5082 (match_operand:SI 2 "general_operand" "")))
5083 (clobber (reg:CC CC_REGNUM))])]
5087 (define_insn "*subsi3_sign"
5088 [(set (match_operand:SI 0 "register_operand" "=d,d")
5089 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5090 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5091 (clobber (reg:CC CC_REGNUM))]
5096 [(set_attr "op_type" "RX,RXY")
5097 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5100 ; sub(di|si)3 instruction pattern(s).
5103 ; sr, s, sy, sgr, sg, srk, sgrk
5104 (define_insn "*sub<mode>3"
5105 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5106 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5107 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5108 (clobber (reg:CC CC_REGNUM))]
5115 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5116 (set_attr "cpu_facility" "*,z196,*,*")
5117 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5119 ; slr, sl, sly, slgr, slg, slrk, slgrk
5120 (define_insn "*sub<mode>3_borrow_cc"
5121 [(set (reg CC_REGNUM)
5122 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5123 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5125 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5126 (minus:GPR (match_dup 1) (match_dup 2)))]
5127 "s390_match_ccmode (insn, CCL2mode)"
5133 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5134 (set_attr "cpu_facility" "*,z196,*,*")
5135 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5137 ; slr, sl, sly, slgr, slg, slrk, slgrk
5138 (define_insn "*sub<mode>3_borrow_cconly"
5139 [(set (reg CC_REGNUM)
5140 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5141 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5143 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5144 "s390_match_ccmode (insn, CCL2mode)"
5150 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5151 (set_attr "cpu_facility" "*,z196,*,*")
5152 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5154 ; slr, sl, sly, slgr, slg, slrk, slgrk
5155 (define_insn "*sub<mode>3_cc"
5156 [(set (reg CC_REGNUM)
5157 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5158 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5160 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5161 (minus:GPR (match_dup 1) (match_dup 2)))]
5162 "s390_match_ccmode (insn, CCLmode)"
5168 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5169 (set_attr "cpu_facility" "*,z196,*,*")
5170 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5172 ; slr, sl, sly, slgr, slg, slrk, slgrk
5173 (define_insn "*sub<mode>3_cc2"
5174 [(set (reg CC_REGNUM)
5175 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5176 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5177 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5178 (minus:GPR (match_dup 1) (match_dup 2)))]
5179 "s390_match_ccmode (insn, CCL3mode)"
5185 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5186 (set_attr "cpu_facility" "*,z196,*,*")
5187 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5189 ; slr, sl, sly, slgr, slg, slrk, slgrk
5190 (define_insn "*sub<mode>3_cconly"
5191 [(set (reg CC_REGNUM)
5192 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5193 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5195 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5196 "s390_match_ccmode (insn, CCLmode)"
5202 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5203 (set_attr "cpu_facility" "*,z196,*,*")
5204 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5207 ; slr, sl, sly, slgr, slg, slrk, slgrk
5208 (define_insn "*sub<mode>3_cconly2"
5209 [(set (reg CC_REGNUM)
5210 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5211 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5212 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5213 "s390_match_ccmode (insn, CCL3mode)"
5219 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5220 (set_attr "cpu_facility" "*,z196,*,*")
5221 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5225 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5228 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5229 (define_insn "sub<mode>3"
5230 [(set (match_operand:FP 0 "register_operand" "=f, f")
5231 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5232 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5233 (clobber (reg:CC CC_REGNUM))]
5236 s<xde><bt>r\t%0,<op1>%2
5238 [(set_attr "op_type" "<RRer>,RXE")
5239 (set_attr "type" "fsimp<mode>")])
5241 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5242 (define_insn "*sub<mode>3_cc"
5243 [(set (reg CC_REGNUM)
5244 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5245 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5246 (match_operand:FP 3 "const0_operand" "")))
5247 (set (match_operand:FP 0 "register_operand" "=f,f")
5248 (minus:FP (match_dup 1) (match_dup 2)))]
5249 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5251 s<xde><bt>r\t%0,<op1>%2
5253 [(set_attr "op_type" "<RRer>,RXE")
5254 (set_attr "type" "fsimp<mode>")])
5256 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5257 (define_insn "*sub<mode>3_cconly"
5258 [(set (reg CC_REGNUM)
5259 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5260 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5261 (match_operand:FP 3 "const0_operand" "")))
5262 (clobber (match_scratch:FP 0 "=f,f"))]
5263 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5265 s<xde><bt>r\t%0,<op1>%2
5267 [(set_attr "op_type" "<RRer>,RXE")
5268 (set_attr "type" "fsimp<mode>")])
5272 ;;- Conditional add/subtract instructions.
5276 ; add(di|si)cc instruction pattern(s).
5279 ; the following 4 patterns are used when the result of an add with
5280 ; carry is checked for an overflow condition
5282 ; op1 + op2 + c < op1
5284 ; alcr, alc, alcgr, alcg
5285 (define_insn "*add<mode>3_alc_carry1_cc"
5286 [(set (reg CC_REGNUM)
5288 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5289 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5290 (match_operand:GPR 2 "general_operand" "d,RT"))
5292 (set (match_operand:GPR 0 "register_operand" "=d,d")
5293 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5294 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5298 [(set_attr "op_type" "RRE,RXY")
5299 (set_attr "z196prop" "z196_alone,z196_alone")])
5301 ; alcr, alc, alcgr, alcg
5302 (define_insn "*add<mode>3_alc_carry1_cconly"
5303 [(set (reg CC_REGNUM)
5305 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5306 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5307 (match_operand:GPR 2 "general_operand" "d,RT"))
5309 (clobber (match_scratch:GPR 0 "=d,d"))]
5310 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5314 [(set_attr "op_type" "RRE,RXY")
5315 (set_attr "z196prop" "z196_alone,z196_alone")])
5317 ; op1 + op2 + c < op2
5319 ; alcr, alc, alcgr, alcg
5320 (define_insn "*add<mode>3_alc_carry2_cc"
5321 [(set (reg CC_REGNUM)
5323 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5324 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5325 (match_operand:GPR 2 "general_operand" "d,RT"))
5327 (set (match_operand:GPR 0 "register_operand" "=d,d")
5328 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5329 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5333 [(set_attr "op_type" "RRE,RXY")])
5335 ; alcr, alc, alcgr, alcg
5336 (define_insn "*add<mode>3_alc_carry2_cconly"
5337 [(set (reg CC_REGNUM)
5339 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5340 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5341 (match_operand:GPR 2 "general_operand" "d,RT"))
5343 (clobber (match_scratch:GPR 0 "=d,d"))]
5344 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5348 [(set_attr "op_type" "RRE,RXY")])
5350 ; alcr, alc, alcgr, alcg
5351 (define_insn "*add<mode>3_alc_cc"
5352 [(set (reg CC_REGNUM)
5354 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5355 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5356 (match_operand:GPR 2 "general_operand" "d,RT"))
5358 (set (match_operand:GPR 0 "register_operand" "=d,d")
5359 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5360 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5364 [(set_attr "op_type" "RRE,RXY")])
5366 ; alcr, alc, alcgr, alcg
5367 (define_insn "*add<mode>3_alc"
5368 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5369 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5370 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5371 (match_operand:GPR 2 "general_operand" "d,RT")))
5372 (clobber (reg:CC CC_REGNUM))]
5377 [(set_attr "op_type" "RRE,RXY")])
5379 ; slbr, slb, slbgr, slbg
5380 (define_insn "*sub<mode>3_slb_cc"
5381 [(set (reg CC_REGNUM)
5383 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5384 (match_operand:GPR 2 "general_operand" "d,RT"))
5385 (match_operand:GPR 3 "s390_slb_comparison" ""))
5387 (set (match_operand:GPR 0 "register_operand" "=d,d")
5388 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5389 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5393 [(set_attr "op_type" "RRE,RXY")
5394 (set_attr "z10prop" "z10_c,*")])
5396 ; slbr, slb, slbgr, slbg
5397 (define_insn "*sub<mode>3_slb"
5398 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5399 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5400 (match_operand:GPR 2 "general_operand" "d,RT"))
5401 (match_operand:GPR 3 "s390_slb_comparison" "")))
5402 (clobber (reg:CC CC_REGNUM))]
5407 [(set_attr "op_type" "RRE,RXY")
5408 (set_attr "z10prop" "z10_c,*")])
5410 (define_expand "add<mode>cc"
5411 [(match_operand:GPR 0 "register_operand" "")
5412 (match_operand 1 "comparison_operator" "")
5413 (match_operand:GPR 2 "register_operand" "")
5414 (match_operand:GPR 3 "const_int_operand" "")]
5416 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5417 XEXP (operands[1], 0), XEXP (operands[1], 1),
5418 operands[0], operands[2],
5419 operands[3])) FAIL; DONE;")
5422 ; scond instruction pattern(s).
5425 (define_insn_and_split "*scond<mode>"
5426 [(set (match_operand:GPR 0 "register_operand" "=&d")
5427 (match_operand:GPR 1 "s390_alc_comparison" ""))
5428 (clobber (reg:CC CC_REGNUM))]
5431 "&& reload_completed"
5432 [(set (match_dup 0) (const_int 0))
5434 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5436 (clobber (reg:CC CC_REGNUM))])]
5439 (define_insn_and_split "*scond<mode>_neg"
5440 [(set (match_operand:GPR 0 "register_operand" "=&d")
5441 (match_operand:GPR 1 "s390_slb_comparison" ""))
5442 (clobber (reg:CC CC_REGNUM))]
5445 "&& reload_completed"
5446 [(set (match_dup 0) (const_int 0))
5448 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5450 (clobber (reg:CC CC_REGNUM))])
5452 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5453 (clobber (reg:CC CC_REGNUM))])]
5457 (define_expand "cstore<mode>4"
5458 [(set (match_operand:SI 0 "register_operand" "")
5459 (match_operator:SI 1 "s390_scond_operator"
5460 [(match_operand:GPR 2 "register_operand" "")
5461 (match_operand:GPR 3 "general_operand" "")]))]
5463 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5464 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5466 (define_expand "cstorecc4"
5468 [(set (match_operand:SI 0 "register_operand" "")
5469 (match_operator:SI 1 "s390_eqne_operator"
5470 [(match_operand:CCZ1 2 "register_operand")
5471 (match_operand 3 "const0_operand")]))
5472 (clobber (reg:CC CC_REGNUM))])]
5474 "emit_insn (gen_sne (operands[0], operands[2]));
5475 if (GET_CODE (operands[1]) == EQ)
5476 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5479 (define_insn_and_split "sne"
5480 [(set (match_operand:SI 0 "register_operand" "=d")
5481 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5483 (clobber (reg:CC CC_REGNUM))]
5488 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5489 (clobber (reg:CC CC_REGNUM))])])
5493 ;; - Conditional move instructions (introduced with z196)
5496 (define_expand "mov<mode>cc"
5497 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5498 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5499 (match_operand:GPR 2 "nonimmediate_operand" "")
5500 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5502 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5503 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5505 ; locr, loc, stoc, locgr, locg, stocg
5506 (define_insn_and_split "*mov<mode>cc"
5507 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5509 (match_operator 1 "s390_comparison"
5510 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5512 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5513 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5523 "&& reload_completed
5524 && MEM_P (operands[3]) && MEM_P (operands[4])"
5527 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5532 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5536 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5539 ;;- Multiply instructions.
5543 ; muldi3 instruction pattern(s).
5546 (define_insn "*muldi3_sign"
5547 [(set (match_operand:DI 0 "register_operand" "=d,d")
5548 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5549 (match_operand:DI 1 "register_operand" "0,0")))]
5554 [(set_attr "op_type" "RRE,RXY")
5555 (set_attr "type" "imuldi")])
5557 (define_insn "muldi3"
5558 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5559 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5560 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5567 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5568 (set_attr "type" "imuldi")
5569 (set_attr "cpu_facility" "*,*,*,z10")])
5572 ; mulsi3 instruction pattern(s).
5575 (define_insn "*mulsi3_sign"
5576 [(set (match_operand:SI 0 "register_operand" "=d,d")
5577 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5578 (match_operand:SI 1 "register_operand" "0,0")))]
5583 [(set_attr "op_type" "RX,RXY")
5584 (set_attr "type" "imulhi")
5585 (set_attr "cpu_facility" "*,z10")])
5587 (define_insn "mulsi3"
5588 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5589 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5590 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5598 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5599 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5600 (set_attr "cpu_facility" "*,*,*,*,z10")])
5603 ; mulsidi3 instruction pattern(s).
5606 (define_insn "mulsidi3"
5607 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5608 (mult:DI (sign_extend:DI
5609 (match_operand:SI 1 "register_operand" "%0,0,0"))
5611 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5617 [(set_attr "op_type" "RR,RX,RXY")
5618 (set_attr "type" "imulsi")
5619 (set_attr "cpu_facility" "*,*,z10")])
5622 ; umul instruction pattern(s).
5625 ; mlr, ml, mlgr, mlg
5626 (define_insn "umul<dwh><mode>3"
5627 [(set (match_operand:DW 0 "register_operand" "=d, d")
5628 (mult:DW (zero_extend:DW
5629 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5631 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5636 [(set_attr "op_type" "RRE,RXY")
5637 (set_attr "type" "imul<dwh>")])
5640 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5643 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5644 (define_insn "mul<mode>3"
5645 [(set (match_operand:FP 0 "register_operand" "=f,f")
5646 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5647 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5650 m<xdee><bt>r\t%0,<op1>%2
5652 [(set_attr "op_type" "<RRer>,RXE")
5653 (set_attr "type" "fmul<mode>")])
5655 ; madbr, maebr, maxb, madb, maeb
5656 (define_insn "fma<mode>4"
5657 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5658 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5659 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5660 (match_operand:DSF 3 "register_operand" "0,0")))]
5665 [(set_attr "op_type" "RRE,RXE")
5666 (set_attr "type" "fmadd<mode>")])
5668 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5669 (define_insn "fms<mode>4"
5670 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5671 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5672 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5673 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5678 [(set_attr "op_type" "RRE,RXE")
5679 (set_attr "type" "fmadd<mode>")])
5682 ;;- Divide and modulo instructions.
5686 ; divmoddi4 instruction pattern(s).
5689 (define_expand "divmoddi4"
5690 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5691 (div:DI (match_operand:DI 1 "register_operand" "")
5692 (match_operand:DI 2 "general_operand" "")))
5693 (set (match_operand:DI 3 "general_operand" "")
5694 (mod:DI (match_dup 1) (match_dup 2)))])
5695 (clobber (match_dup 4))]
5698 rtx insn, div_equal, mod_equal;
5700 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5701 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5703 operands[4] = gen_reg_rtx(TImode);
5704 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5706 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5707 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5709 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5710 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5715 (define_insn "divmodtidi3"
5716 [(set (match_operand:TI 0 "register_operand" "=d,d")
5720 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5721 (match_operand:DI 2 "general_operand" "d,RT")))
5723 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5728 [(set_attr "op_type" "RRE,RXY")
5729 (set_attr "type" "idiv")])
5731 (define_insn "divmodtisi3"
5732 [(set (match_operand:TI 0 "register_operand" "=d,d")
5736 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5738 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5741 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5746 [(set_attr "op_type" "RRE,RXY")
5747 (set_attr "type" "idiv")])
5750 ; udivmoddi4 instruction pattern(s).
5753 (define_expand "udivmoddi4"
5754 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5755 (udiv:DI (match_operand:DI 1 "general_operand" "")
5756 (match_operand:DI 2 "nonimmediate_operand" "")))
5757 (set (match_operand:DI 3 "general_operand" "")
5758 (umod:DI (match_dup 1) (match_dup 2)))])
5759 (clobber (match_dup 4))]
5762 rtx insn, div_equal, mod_equal, equal;
5764 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5765 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5766 equal = gen_rtx_IOR (TImode,
5767 gen_rtx_ASHIFT (TImode,
5768 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5770 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5772 operands[4] = gen_reg_rtx(TImode);
5773 emit_clobber (operands[4]);
5774 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5775 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5777 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5778 set_unique_reg_note (insn, REG_EQUAL, equal);
5780 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5781 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5783 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5784 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5789 (define_insn "udivmodtidi3"
5790 [(set (match_operand:TI 0 "register_operand" "=d,d")
5795 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5797 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5801 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5806 [(set_attr "op_type" "RRE,RXY")
5807 (set_attr "type" "idiv")])
5810 ; divmodsi4 instruction pattern(s).
5813 (define_expand "divmodsi4"
5814 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5815 (div:SI (match_operand:SI 1 "general_operand" "")
5816 (match_operand:SI 2 "nonimmediate_operand" "")))
5817 (set (match_operand:SI 3 "general_operand" "")
5818 (mod:SI (match_dup 1) (match_dup 2)))])
5819 (clobber (match_dup 4))]
5822 rtx insn, div_equal, mod_equal, equal;
5824 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5825 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5826 equal = gen_rtx_IOR (DImode,
5827 gen_rtx_ASHIFT (DImode,
5828 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5830 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5832 operands[4] = gen_reg_rtx(DImode);
5833 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5835 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5836 set_unique_reg_note (insn, REG_EQUAL, equal);
5838 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5839 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5841 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5842 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5847 (define_insn "divmoddisi3"
5848 [(set (match_operand:DI 0 "register_operand" "=d,d")
5853 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5855 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5859 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5864 [(set_attr "op_type" "RR,RX")
5865 (set_attr "type" "idiv")])
5868 ; udivsi3 and umodsi3 instruction pattern(s).
5871 (define_expand "udivmodsi4"
5872 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5873 (udiv:SI (match_operand:SI 1 "general_operand" "")
5874 (match_operand:SI 2 "nonimmediate_operand" "")))
5875 (set (match_operand:SI 3 "general_operand" "")
5876 (umod:SI (match_dup 1) (match_dup 2)))])
5877 (clobber (match_dup 4))]
5878 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5880 rtx insn, div_equal, mod_equal, equal;
5882 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5883 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5884 equal = gen_rtx_IOR (DImode,
5885 gen_rtx_ASHIFT (DImode,
5886 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5888 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5890 operands[4] = gen_reg_rtx(DImode);
5891 emit_clobber (operands[4]);
5892 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5893 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5895 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5896 set_unique_reg_note (insn, REG_EQUAL, equal);
5898 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5899 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5901 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5902 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5907 (define_insn "udivmoddisi3"
5908 [(set (match_operand:DI 0 "register_operand" "=d,d")
5913 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5915 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5919 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5920 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5924 [(set_attr "op_type" "RRE,RXY")
5925 (set_attr "type" "idiv")])
5927 (define_expand "udivsi3"
5928 [(set (match_operand:SI 0 "register_operand" "=d")
5929 (udiv:SI (match_operand:SI 1 "general_operand" "")
5930 (match_operand:SI 2 "general_operand" "")))
5931 (clobber (match_dup 3))]
5932 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5934 rtx insn, udiv_equal, umod_equal, equal;
5936 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5937 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5938 equal = gen_rtx_IOR (DImode,
5939 gen_rtx_ASHIFT (DImode,
5940 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5942 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5944 operands[3] = gen_reg_rtx (DImode);
5946 if (CONSTANT_P (operands[2]))
5948 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5950 rtx label1 = gen_label_rtx ();
5952 operands[1] = make_safe_from (operands[1], operands[0]);
5953 emit_move_insn (operands[0], const0_rtx);
5954 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5956 emit_move_insn (operands[0], const1_rtx);
5957 emit_label (label1);
5961 operands[2] = force_reg (SImode, operands[2]);
5962 operands[2] = make_safe_from (operands[2], operands[0]);
5964 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5965 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5967 set_unique_reg_note (insn, REG_EQUAL, equal);
5969 insn = emit_move_insn (operands[0],
5970 gen_lowpart (SImode, operands[3]));
5971 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5976 rtx label1 = gen_label_rtx ();
5977 rtx label2 = gen_label_rtx ();
5978 rtx label3 = gen_label_rtx ();
5980 operands[1] = force_reg (SImode, operands[1]);
5981 operands[1] = make_safe_from (operands[1], operands[0]);
5982 operands[2] = force_reg (SImode, operands[2]);
5983 operands[2] = make_safe_from (operands[2], operands[0]);
5985 emit_move_insn (operands[0], const0_rtx);
5986 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5988 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5990 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5992 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5993 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5995 set_unique_reg_note (insn, REG_EQUAL, equal);
5997 insn = emit_move_insn (operands[0],
5998 gen_lowpart (SImode, operands[3]));
5999 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6002 emit_label (label1);
6003 emit_move_insn (operands[0], operands[1]);
6005 emit_label (label2);
6006 emit_move_insn (operands[0], const1_rtx);
6007 emit_label (label3);
6009 emit_move_insn (operands[0], operands[0]);
6013 (define_expand "umodsi3"
6014 [(set (match_operand:SI 0 "register_operand" "=d")
6015 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6016 (match_operand:SI 2 "nonimmediate_operand" "")))
6017 (clobber (match_dup 3))]
6018 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6020 rtx insn, udiv_equal, umod_equal, equal;
6022 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6023 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6024 equal = gen_rtx_IOR (DImode,
6025 gen_rtx_ASHIFT (DImode,
6026 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6028 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6030 operands[3] = gen_reg_rtx (DImode);
6032 if (CONSTANT_P (operands[2]))
6034 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6036 rtx label1 = gen_label_rtx ();
6038 operands[1] = make_safe_from (operands[1], operands[0]);
6039 emit_move_insn (operands[0], operands[1]);
6040 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6042 emit_insn (gen_abssi2 (operands[0], operands[2]));
6043 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6044 emit_label (label1);
6048 operands[2] = force_reg (SImode, operands[2]);
6049 operands[2] = make_safe_from (operands[2], operands[0]);
6051 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6052 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6054 set_unique_reg_note (insn, REG_EQUAL, equal);
6056 insn = emit_move_insn (operands[0],
6057 gen_highpart (SImode, operands[3]));
6058 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6063 rtx label1 = gen_label_rtx ();
6064 rtx label2 = gen_label_rtx ();
6065 rtx label3 = gen_label_rtx ();
6067 operands[1] = force_reg (SImode, operands[1]);
6068 operands[1] = make_safe_from (operands[1], operands[0]);
6069 operands[2] = force_reg (SImode, operands[2]);
6070 operands[2] = make_safe_from (operands[2], operands[0]);
6072 emit_move_insn(operands[0], operands[1]);
6073 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6075 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6077 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6079 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6080 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6082 set_unique_reg_note (insn, REG_EQUAL, equal);
6084 insn = emit_move_insn (operands[0],
6085 gen_highpart (SImode, operands[3]));
6086 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6089 emit_label (label1);
6090 emit_move_insn (operands[0], const0_rtx);
6092 emit_label (label2);
6093 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6094 emit_label (label3);
6100 ; div(df|sf)3 instruction pattern(s).
6103 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6104 (define_insn "div<mode>3"
6105 [(set (match_operand:FP 0 "register_operand" "=f,f")
6106 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6107 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6110 d<xde><bt>r\t%0,<op1>%2
6112 [(set_attr "op_type" "<RRer>,RXE")
6113 (set_attr "type" "fdiv<mode>")])
6117 ;;- And instructions.
6120 (define_expand "and<mode>3"
6121 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6122 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6123 (match_operand:INT 2 "general_operand" "")))
6124 (clobber (reg:CC CC_REGNUM))]
6126 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6129 ; anddi3 instruction pattern(s).
6132 (define_insn "*anddi3_cc"
6133 [(set (reg CC_REGNUM)
6135 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6136 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6138 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6139 (and:DI (match_dup 1) (match_dup 2)))]
6140 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6145 risbg\t%0,%1,%s2,128+%e2,0"
6146 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6147 (set_attr "cpu_facility" "*,z196,*,z10")
6148 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6150 (define_insn "*anddi3_cconly"
6151 [(set (reg CC_REGNUM)
6153 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6154 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6156 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6158 && s390_match_ccmode(insn, CCTmode)
6159 /* Do not steal TM patterns. */
6160 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6165 risbg\t%0,%1,%s2,128+%e2,0"
6166 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6167 (set_attr "cpu_facility" "*,z196,*,z10")
6168 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6170 (define_insn "*anddi3"
6171 [(set (match_operand:DI 0 "nonimmediate_operand"
6172 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6174 (match_operand:DI 1 "nonimmediate_operand"
6175 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6176 (match_operand:DI 2 "general_operand"
6177 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6178 (clobber (reg:CC CC_REGNUM))]
6179 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6192 risbg\t%0,%1,%s2,128+%e2,0
6195 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6196 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6197 (set_attr "z10prop" "*,
6213 [(set (match_operand:DI 0 "s_operand" "")
6214 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6215 (clobber (reg:CC CC_REGNUM))]
6218 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6219 (clobber (reg:CC CC_REGNUM))])]
6220 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6222 ;; These two are what combine generates for (ashift (zero_extract)).
6223 (define_insn "*extzv_<mode>_srl"
6224 [(set (match_operand:GPR 0 "register_operand" "=d")
6225 (and:GPR (lshiftrt:GPR
6226 (match_operand:GPR 1 "register_operand" "d")
6227 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6228 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6229 (clobber (reg:CC CC_REGNUM))]
6231 /* Note that even for the SImode pattern, the rotate is always DImode. */
6232 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6233 INTVAL (operands[3]))"
6234 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6235 [(set_attr "op_type" "RIE")
6236 (set_attr "z10prop" "z10_super_E1")])
6238 (define_insn "*extzv_<mode>_sll"
6239 [(set (match_operand:GPR 0 "register_operand" "=d")
6240 (and:GPR (ashift:GPR
6241 (match_operand:GPR 1 "register_operand" "d")
6242 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6243 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6244 (clobber (reg:CC CC_REGNUM))]
6246 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6247 INTVAL (operands[3]))"
6248 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6249 [(set_attr "op_type" "RIE")
6250 (set_attr "z10prop" "z10_super_E1")])
6254 ; andsi3 instruction pattern(s).
6257 (define_insn "*andsi3_cc"
6258 [(set (reg CC_REGNUM)
6261 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6262 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6264 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6265 (and:SI (match_dup 1) (match_dup 2)))]
6266 "s390_match_ccmode(insn, CCTmode)"
6273 risbg\t%0,%1,%t2,128+%f2,0"
6274 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6275 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6276 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6277 z10_super_E1,z10_super_E1,z10_super_E1")])
6279 (define_insn "*andsi3_cconly"
6280 [(set (reg CC_REGNUM)
6283 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6284 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6286 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6287 "s390_match_ccmode(insn, CCTmode)
6288 /* Do not steal TM patterns. */
6289 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6296 risbg\t%0,%1,%t2,128+%f2,0"
6297 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6298 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6299 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6300 z10_super_E1,z10_super_E1,z10_super_E1")])
6302 (define_insn "*andsi3_zarch"
6303 [(set (match_operand:SI 0 "nonimmediate_operand"
6304 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6305 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6306 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6307 (match_operand:SI 2 "general_operand"
6308 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6309 (clobber (reg:CC CC_REGNUM))]
6310 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6321 risbg\t%0,%1,%t2,128+%f2,0
6324 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6325 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6326 (set_attr "z10prop" "*,
6339 (define_insn "*andsi3_esa"
6340 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6341 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6342 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6343 (clobber (reg:CC CC_REGNUM))]
6344 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6350 [(set_attr "op_type" "RR,RX,SI,SS")
6351 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6355 [(set (match_operand:SI 0 "s_operand" "")
6356 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6357 (clobber (reg:CC CC_REGNUM))]
6360 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6361 (clobber (reg:CC CC_REGNUM))])]
6362 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6365 ; andhi3 instruction pattern(s).
6368 (define_insn "*andhi3_zarch"
6369 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6370 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6371 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6372 (clobber (reg:CC CC_REGNUM))]
6373 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6380 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6381 (set_attr "cpu_facility" "*,z196,*,*,*")
6382 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6385 (define_insn "*andhi3_esa"
6386 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6387 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6388 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6389 (clobber (reg:CC CC_REGNUM))]
6390 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6395 [(set_attr "op_type" "RR,SI,SS")
6396 (set_attr "z10prop" "z10_super_E1,*,*")
6400 [(set (match_operand:HI 0 "s_operand" "")
6401 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6402 (clobber (reg:CC CC_REGNUM))]
6405 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6406 (clobber (reg:CC CC_REGNUM))])]
6407 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6410 ; andqi3 instruction pattern(s).
6413 (define_insn "*andqi3_zarch"
6414 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6415 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6416 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6417 (clobber (reg:CC CC_REGNUM))]
6418 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6426 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6427 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6428 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6430 (define_insn "*andqi3_esa"
6431 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6432 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6433 (match_operand:QI 2 "general_operand" "d,n,Q")))
6434 (clobber (reg:CC CC_REGNUM))]
6435 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6440 [(set_attr "op_type" "RR,SI,SS")
6441 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6444 ; Block and (NC) patterns.
6448 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6449 (and:BLK (match_dup 0)
6450 (match_operand:BLK 1 "memory_operand" "Q")))
6451 (use (match_operand 2 "const_int_operand" "n"))
6452 (clobber (reg:CC CC_REGNUM))]
6453 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6454 "nc\t%O0(%2,%R0),%S1"
6455 [(set_attr "op_type" "SS")
6456 (set_attr "z196prop" "z196_cracked")])
6459 [(set (match_operand 0 "memory_operand" "")
6461 (match_operand 1 "memory_operand" "")))
6462 (clobber (reg:CC CC_REGNUM))]
6464 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6465 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6467 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6469 (clobber (reg:CC CC_REGNUM))])]
6471 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6472 operands[0] = adjust_address (operands[0], BLKmode, 0);
6473 operands[1] = adjust_address (operands[1], BLKmode, 0);
6478 [(set (match_operand:BLK 0 "memory_operand" "")
6479 (and:BLK (match_dup 0)
6480 (match_operand:BLK 1 "memory_operand" "")))
6481 (use (match_operand 2 "const_int_operand" ""))
6482 (clobber (reg:CC CC_REGNUM))])
6484 [(set (match_operand:BLK 3 "memory_operand" "")
6485 (and:BLK (match_dup 3)
6486 (match_operand:BLK 4 "memory_operand" "")))
6487 (use (match_operand 5 "const_int_operand" ""))
6488 (clobber (reg:CC CC_REGNUM))])]
6489 "s390_offset_p (operands[0], operands[3], operands[2])
6490 && s390_offset_p (operands[1], operands[4], operands[2])
6491 && !s390_overlap_p (operands[0], operands[1],
6492 INTVAL (operands[2]) + INTVAL (operands[5]))
6493 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6495 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6497 (clobber (reg:CC CC_REGNUM))])]
6498 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6499 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6500 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6504 ;;- Bit set (inclusive or) instructions.
6507 (define_expand "ior<mode>3"
6508 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6509 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6510 (match_operand:INT 2 "general_operand" "")))
6511 (clobber (reg:CC CC_REGNUM))]
6513 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6516 ; iordi3 instruction pattern(s).
6519 (define_insn "*iordi3_cc"
6520 [(set (reg CC_REGNUM)
6521 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6522 (match_operand:DI 2 "general_operand" " d,d,RT"))
6524 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6525 (ior:DI (match_dup 1) (match_dup 2)))]
6526 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6531 [(set_attr "op_type" "RRE,RRF,RXY")
6532 (set_attr "cpu_facility" "*,z196,*")
6533 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6535 (define_insn "*iordi3_cconly"
6536 [(set (reg CC_REGNUM)
6537 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6538 (match_operand:DI 2 "general_operand" " d,d,RT"))
6540 (clobber (match_scratch:DI 0 "=d,d,d"))]
6541 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6546 [(set_attr "op_type" "RRE,RRF,RXY")
6547 (set_attr "cpu_facility" "*,z196,*")
6548 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6550 (define_insn "*iordi3"
6551 [(set (match_operand:DI 0 "nonimmediate_operand"
6552 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6553 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6554 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6555 (match_operand:DI 2 "general_operand"
6556 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6557 (clobber (reg:CC CC_REGNUM))]
6558 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6571 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6572 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6573 (set_attr "z10prop" "z10_super_E1,
6586 [(set (match_operand:DI 0 "s_operand" "")
6587 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6588 (clobber (reg:CC CC_REGNUM))]
6591 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6592 (clobber (reg:CC CC_REGNUM))])]
6593 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6596 ; iorsi3 instruction pattern(s).
6599 (define_insn "*iorsi3_cc"
6600 [(set (reg CC_REGNUM)
6601 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6602 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6604 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6605 (ior:SI (match_dup 1) (match_dup 2)))]
6606 "s390_match_ccmode(insn, CCTmode)"
6613 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6614 (set_attr "cpu_facility" "*,*,z196,*,*")
6615 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6617 (define_insn "*iorsi3_cconly"
6618 [(set (reg CC_REGNUM)
6619 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6620 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6622 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6623 "s390_match_ccmode(insn, CCTmode)"
6630 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6631 (set_attr "cpu_facility" "*,*,z196,*,*")
6632 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6634 (define_insn "*iorsi3_zarch"
6635 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6636 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6637 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6638 (clobber (reg:CC CC_REGNUM))]
6639 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6650 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6651 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6652 (set_attr "z10prop" "z10_super_E1,
6662 (define_insn "*iorsi3_esa"
6663 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6664 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6665 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6666 (clobber (reg:CC CC_REGNUM))]
6667 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6673 [(set_attr "op_type" "RR,RX,SI,SS")
6674 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6677 [(set (match_operand:SI 0 "s_operand" "")
6678 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6679 (clobber (reg:CC CC_REGNUM))]
6682 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6683 (clobber (reg:CC CC_REGNUM))])]
6684 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6687 ; iorhi3 instruction pattern(s).
6690 (define_insn "*iorhi3_zarch"
6691 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6692 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6693 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6694 (clobber (reg:CC CC_REGNUM))]
6695 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6702 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6703 (set_attr "cpu_facility" "*,z196,*,*,*")
6704 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6706 (define_insn "*iorhi3_esa"
6707 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6708 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6709 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6710 (clobber (reg:CC CC_REGNUM))]
6711 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6716 [(set_attr "op_type" "RR,SI,SS")
6717 (set_attr "z10prop" "z10_super_E1,*,*")])
6720 [(set (match_operand:HI 0 "s_operand" "")
6721 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6722 (clobber (reg:CC CC_REGNUM))]
6725 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6726 (clobber (reg:CC CC_REGNUM))])]
6727 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6730 ; iorqi3 instruction pattern(s).
6733 (define_insn "*iorqi3_zarch"
6734 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6735 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6736 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6737 (clobber (reg:CC CC_REGNUM))]
6738 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6746 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6747 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6748 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6749 z10_super,z10_super,*")])
6751 (define_insn "*iorqi3_esa"
6752 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6753 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6754 (match_operand:QI 2 "general_operand" "d,n,Q")))
6755 (clobber (reg:CC CC_REGNUM))]
6756 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6761 [(set_attr "op_type" "RR,SI,SS")
6762 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6765 ; Block inclusive or (OC) patterns.
6769 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6770 (ior:BLK (match_dup 0)
6771 (match_operand:BLK 1 "memory_operand" "Q")))
6772 (use (match_operand 2 "const_int_operand" "n"))
6773 (clobber (reg:CC CC_REGNUM))]
6774 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6775 "oc\t%O0(%2,%R0),%S1"
6776 [(set_attr "op_type" "SS")
6777 (set_attr "z196prop" "z196_cracked")])
6780 [(set (match_operand 0 "memory_operand" "")
6782 (match_operand 1 "memory_operand" "")))
6783 (clobber (reg:CC CC_REGNUM))]
6785 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6786 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6788 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6790 (clobber (reg:CC CC_REGNUM))])]
6792 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6793 operands[0] = adjust_address (operands[0], BLKmode, 0);
6794 operands[1] = adjust_address (operands[1], BLKmode, 0);
6799 [(set (match_operand:BLK 0 "memory_operand" "")
6800 (ior:BLK (match_dup 0)
6801 (match_operand:BLK 1 "memory_operand" "")))
6802 (use (match_operand 2 "const_int_operand" ""))
6803 (clobber (reg:CC CC_REGNUM))])
6805 [(set (match_operand:BLK 3 "memory_operand" "")
6806 (ior:BLK (match_dup 3)
6807 (match_operand:BLK 4 "memory_operand" "")))
6808 (use (match_operand 5 "const_int_operand" ""))
6809 (clobber (reg:CC CC_REGNUM))])]
6810 "s390_offset_p (operands[0], operands[3], operands[2])
6811 && s390_offset_p (operands[1], operands[4], operands[2])
6812 && !s390_overlap_p (operands[0], operands[1],
6813 INTVAL (operands[2]) + INTVAL (operands[5]))
6814 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6816 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6818 (clobber (reg:CC CC_REGNUM))])]
6819 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6820 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6821 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6825 ;;- Xor instructions.
6828 (define_expand "xor<mode>3"
6829 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6830 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6831 (match_operand:INT 2 "general_operand" "")))
6832 (clobber (reg:CC CC_REGNUM))]
6834 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6837 ; xordi3 instruction pattern(s).
6840 (define_insn "*xordi3_cc"
6841 [(set (reg CC_REGNUM)
6842 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6843 (match_operand:DI 2 "general_operand" " d,d,RT"))
6845 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6846 (xor:DI (match_dup 1) (match_dup 2)))]
6847 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6852 [(set_attr "op_type" "RRE,RRF,RXY")
6853 (set_attr "cpu_facility" "*,z196,*")
6854 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6856 (define_insn "*xordi3_cconly"
6857 [(set (reg CC_REGNUM)
6858 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6859 (match_operand:DI 2 "general_operand" " d,d,RT"))
6861 (clobber (match_scratch:DI 0 "=d,d, d"))]
6862 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6867 [(set_attr "op_type" "RRE,RRF,RXY")
6868 (set_attr "cpu_facility" "*,z196,*")
6869 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6871 (define_insn "*xordi3"
6872 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6873 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6874 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6875 (clobber (reg:CC CC_REGNUM))]
6876 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6885 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6886 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6887 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6888 *,z10_super_E1,*,*")])
6891 [(set (match_operand:DI 0 "s_operand" "")
6892 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6893 (clobber (reg:CC CC_REGNUM))]
6896 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6897 (clobber (reg:CC CC_REGNUM))])]
6898 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6901 ; xorsi3 instruction pattern(s).
6904 (define_insn "*xorsi3_cc"
6905 [(set (reg CC_REGNUM)
6906 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6907 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6909 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6910 (xor:SI (match_dup 1) (match_dup 2)))]
6911 "s390_match_ccmode(insn, CCTmode)"
6918 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6919 (set_attr "cpu_facility" "*,*,z196,*,*")
6920 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6921 z10_super_E1,z10_super_E1")])
6923 (define_insn "*xorsi3_cconly"
6924 [(set (reg CC_REGNUM)
6925 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6926 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6928 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6929 "s390_match_ccmode(insn, CCTmode)"
6936 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6937 (set_attr "cpu_facility" "*,*,z196,*,*")
6938 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6939 z10_super_E1,z10_super_E1")])
6941 (define_insn "*xorsi3"
6942 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6943 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6944 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6945 (clobber (reg:CC CC_REGNUM))]
6946 "s390_logical_operator_ok_p (operands)"
6955 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6956 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6957 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6958 z10_super_E1,z10_super_E1,*,*")])
6961 [(set (match_operand:SI 0 "s_operand" "")
6962 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6963 (clobber (reg:CC CC_REGNUM))]
6966 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6967 (clobber (reg:CC CC_REGNUM))])]
6968 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6971 ; xorhi3 instruction pattern(s).
6974 (define_insn "*xorhi3"
6975 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6976 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6977 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6978 (clobber (reg:CC CC_REGNUM))]
6979 "s390_logical_operator_ok_p (operands)"
6986 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6987 (set_attr "cpu_facility" "*,*,z196,*,*")
6988 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6991 [(set (match_operand:HI 0 "s_operand" "")
6992 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6993 (clobber (reg:CC CC_REGNUM))]
6996 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6997 (clobber (reg:CC CC_REGNUM))])]
6998 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7001 ; xorqi3 instruction pattern(s).
7004 (define_insn "*xorqi3"
7005 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7006 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7007 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7008 (clobber (reg:CC CC_REGNUM))]
7009 "s390_logical_operator_ok_p (operands)"
7017 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7018 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7019 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7023 ; Block exclusive or (XC) patterns.
7027 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7028 (xor:BLK (match_dup 0)
7029 (match_operand:BLK 1 "memory_operand" "Q")))
7030 (use (match_operand 2 "const_int_operand" "n"))
7031 (clobber (reg:CC CC_REGNUM))]
7032 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7033 "xc\t%O0(%2,%R0),%S1"
7034 [(set_attr "op_type" "SS")])
7037 [(set (match_operand 0 "memory_operand" "")
7039 (match_operand 1 "memory_operand" "")))
7040 (clobber (reg:CC CC_REGNUM))]
7042 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7043 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7045 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7047 (clobber (reg:CC CC_REGNUM))])]
7049 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7050 operands[0] = adjust_address (operands[0], BLKmode, 0);
7051 operands[1] = adjust_address (operands[1], BLKmode, 0);
7056 [(set (match_operand:BLK 0 "memory_operand" "")
7057 (xor:BLK (match_dup 0)
7058 (match_operand:BLK 1 "memory_operand" "")))
7059 (use (match_operand 2 "const_int_operand" ""))
7060 (clobber (reg:CC CC_REGNUM))])
7062 [(set (match_operand:BLK 3 "memory_operand" "")
7063 (xor:BLK (match_dup 3)
7064 (match_operand:BLK 4 "memory_operand" "")))
7065 (use (match_operand 5 "const_int_operand" ""))
7066 (clobber (reg:CC CC_REGNUM))])]
7067 "s390_offset_p (operands[0], operands[3], operands[2])
7068 && s390_offset_p (operands[1], operands[4], operands[2])
7069 && !s390_overlap_p (operands[0], operands[1],
7070 INTVAL (operands[2]) + INTVAL (operands[5]))
7071 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7073 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7075 (clobber (reg:CC CC_REGNUM))])]
7076 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7077 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7078 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7081 ; Block xor (XC) patterns with src == dest.
7084 (define_insn "*xc_zero"
7085 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7087 (use (match_operand 1 "const_int_operand" "n"))
7088 (clobber (reg:CC CC_REGNUM))]
7089 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7090 "xc\t%O0(%1,%R0),%S0"
7091 [(set_attr "op_type" "SS")
7092 (set_attr "z196prop" "z196_cracked")])
7096 [(set (match_operand:BLK 0 "memory_operand" "")
7098 (use (match_operand 1 "const_int_operand" ""))
7099 (clobber (reg:CC CC_REGNUM))])
7101 [(set (match_operand:BLK 2 "memory_operand" "")
7103 (use (match_operand 3 "const_int_operand" ""))
7104 (clobber (reg:CC CC_REGNUM))])]
7105 "s390_offset_p (operands[0], operands[2], operands[1])
7106 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7108 [(set (match_dup 4) (const_int 0))
7110 (clobber (reg:CC CC_REGNUM))])]
7111 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7112 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7116 ;;- Negate instructions.
7120 ; neg(di|si)2 instruction pattern(s).
7123 (define_expand "neg<mode>2"
7125 [(set (match_operand:DSI 0 "register_operand" "=d")
7126 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7127 (clobber (reg:CC CC_REGNUM))])]
7131 (define_insn "*negdi2_sign_cc"
7132 [(set (reg CC_REGNUM)
7133 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7134 (match_operand:SI 1 "register_operand" "d") 0)
7135 (const_int 32)) (const_int 32)))
7137 (set (match_operand:DI 0 "register_operand" "=d")
7138 (neg:DI (sign_extend:DI (match_dup 1))))]
7139 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7141 [(set_attr "op_type" "RRE")
7142 (set_attr "z10prop" "z10_c")])
7144 (define_insn "*negdi2_sign"
7145 [(set (match_operand:DI 0 "register_operand" "=d")
7146 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7147 (clobber (reg:CC CC_REGNUM))]
7150 [(set_attr "op_type" "RRE")
7151 (set_attr "z10prop" "z10_c")])
7154 (define_insn "*neg<mode>2_cc"
7155 [(set (reg CC_REGNUM)
7156 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7158 (set (match_operand:GPR 0 "register_operand" "=d")
7159 (neg:GPR (match_dup 1)))]
7160 "s390_match_ccmode (insn, CCAmode)"
7162 [(set_attr "op_type" "RR<E>")
7163 (set_attr "z10prop" "z10_super_c_E1")])
7166 (define_insn "*neg<mode>2_cconly"
7167 [(set (reg CC_REGNUM)
7168 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7170 (clobber (match_scratch:GPR 0 "=d"))]
7171 "s390_match_ccmode (insn, CCAmode)"
7173 [(set_attr "op_type" "RR<E>")
7174 (set_attr "z10prop" "z10_super_c_E1")])
7177 (define_insn "*neg<mode>2"
7178 [(set (match_operand:GPR 0 "register_operand" "=d")
7179 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7180 (clobber (reg:CC CC_REGNUM))]
7183 [(set_attr "op_type" "RR<E>")
7184 (set_attr "z10prop" "z10_super_c_E1")])
7186 (define_insn_and_split "*negdi2_31"
7187 [(set (match_operand:DI 0 "register_operand" "=d")
7188 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7189 (clobber (reg:CC CC_REGNUM))]
7192 "&& reload_completed"
7194 [(set (match_dup 2) (neg:SI (match_dup 3)))
7195 (clobber (reg:CC CC_REGNUM))])
7197 [(set (reg:CCAP CC_REGNUM)
7198 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7199 (set (match_dup 4) (neg:SI (match_dup 5)))])
7201 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7203 (label_ref (match_dup 6))))
7205 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7206 (clobber (reg:CC CC_REGNUM))])
7208 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7209 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7210 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7211 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7212 operands[6] = gen_label_rtx ();")
7215 ; neg(df|sf)2 instruction pattern(s).
7218 (define_expand "neg<mode>2"
7220 [(set (match_operand:BFP 0 "register_operand" "=f")
7221 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7222 (clobber (reg:CC CC_REGNUM))])]
7226 ; lcxbr, lcdbr, lcebr
7227 (define_insn "*neg<mode>2_cc"
7228 [(set (reg CC_REGNUM)
7229 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7230 (match_operand:BFP 2 "const0_operand" "")))
7231 (set (match_operand:BFP 0 "register_operand" "=f")
7232 (neg:BFP (match_dup 1)))]
7233 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7235 [(set_attr "op_type" "RRE")
7236 (set_attr "type" "fsimp<mode>")])
7238 ; lcxbr, lcdbr, lcebr
7239 (define_insn "*neg<mode>2_cconly"
7240 [(set (reg CC_REGNUM)
7241 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7242 (match_operand:BFP 2 "const0_operand" "")))
7243 (clobber (match_scratch:BFP 0 "=f"))]
7244 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7246 [(set_attr "op_type" "RRE")
7247 (set_attr "type" "fsimp<mode>")])
7250 (define_insn "*neg<mode>2_nocc"
7251 [(set (match_operand:FP 0 "register_operand" "=f")
7252 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7255 [(set_attr "op_type" "RRE")
7256 (set_attr "type" "fsimp<mode>")])
7258 ; lcxbr, lcdbr, lcebr
7259 (define_insn "*neg<mode>2"
7260 [(set (match_operand:BFP 0 "register_operand" "=f")
7261 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7262 (clobber (reg:CC CC_REGNUM))]
7265 [(set_attr "op_type" "RRE")
7266 (set_attr "type" "fsimp<mode>")])
7270 ;;- Absolute value instructions.
7274 ; abs(di|si)2 instruction pattern(s).
7277 (define_insn "*absdi2_sign_cc"
7278 [(set (reg CC_REGNUM)
7279 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7280 (match_operand:SI 1 "register_operand" "d") 0)
7281 (const_int 32)) (const_int 32)))
7283 (set (match_operand:DI 0 "register_operand" "=d")
7284 (abs:DI (sign_extend:DI (match_dup 1))))]
7285 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7287 [(set_attr "op_type" "RRE")
7288 (set_attr "z10prop" "z10_c")])
7290 (define_insn "*absdi2_sign"
7291 [(set (match_operand:DI 0 "register_operand" "=d")
7292 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7293 (clobber (reg:CC CC_REGNUM))]
7296 [(set_attr "op_type" "RRE")
7297 (set_attr "z10prop" "z10_c")])
7300 (define_insn "*abs<mode>2_cc"
7301 [(set (reg CC_REGNUM)
7302 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7304 (set (match_operand:GPR 0 "register_operand" "=d")
7305 (abs:GPR (match_dup 1)))]
7306 "s390_match_ccmode (insn, CCAmode)"
7308 [(set_attr "op_type" "RR<E>")
7309 (set_attr "z10prop" "z10_c")])
7312 (define_insn "*abs<mode>2_cconly"
7313 [(set (reg CC_REGNUM)
7314 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7316 (clobber (match_scratch:GPR 0 "=d"))]
7317 "s390_match_ccmode (insn, CCAmode)"
7319 [(set_attr "op_type" "RR<E>")
7320 (set_attr "z10prop" "z10_c")])
7323 (define_insn "abs<mode>2"
7324 [(set (match_operand:GPR 0 "register_operand" "=d")
7325 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7326 (clobber (reg:CC CC_REGNUM))]
7329 [(set_attr "op_type" "RR<E>")
7330 (set_attr "z10prop" "z10_c")])
7333 ; abs(df|sf)2 instruction pattern(s).
7336 (define_expand "abs<mode>2"
7338 [(set (match_operand:BFP 0 "register_operand" "=f")
7339 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7340 (clobber (reg:CC CC_REGNUM))])]
7344 ; lpxbr, lpdbr, lpebr
7345 (define_insn "*abs<mode>2_cc"
7346 [(set (reg CC_REGNUM)
7347 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7348 (match_operand:BFP 2 "const0_operand" "")))
7349 (set (match_operand:BFP 0 "register_operand" "=f")
7350 (abs:BFP (match_dup 1)))]
7351 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7353 [(set_attr "op_type" "RRE")
7354 (set_attr "type" "fsimp<mode>")])
7356 ; lpxbr, lpdbr, lpebr
7357 (define_insn "*abs<mode>2_cconly"
7358 [(set (reg CC_REGNUM)
7359 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7360 (match_operand:BFP 2 "const0_operand" "")))
7361 (clobber (match_scratch:BFP 0 "=f"))]
7362 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7364 [(set_attr "op_type" "RRE")
7365 (set_attr "type" "fsimp<mode>")])
7368 (define_insn "*abs<mode>2_nocc"
7369 [(set (match_operand:FP 0 "register_operand" "=f")
7370 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7373 [(set_attr "op_type" "RRE")
7374 (set_attr "type" "fsimp<mode>")])
7376 ; lpxbr, lpdbr, lpebr
7377 (define_insn "*abs<mode>2"
7378 [(set (match_operand:BFP 0 "register_operand" "=f")
7379 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7380 (clobber (reg:CC CC_REGNUM))]
7383 [(set_attr "op_type" "RRE")
7384 (set_attr "type" "fsimp<mode>")])
7388 ;;- Negated absolute value instructions
7395 (define_insn "*negabsdi2_sign_cc"
7396 [(set (reg CC_REGNUM)
7397 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7398 (match_operand:SI 1 "register_operand" "d") 0)
7399 (const_int 32)) (const_int 32))))
7401 (set (match_operand:DI 0 "register_operand" "=d")
7402 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7403 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7405 [(set_attr "op_type" "RRE")
7406 (set_attr "z10prop" "z10_c")])
7408 (define_insn "*negabsdi2_sign"
7409 [(set (match_operand:DI 0 "register_operand" "=d")
7410 (neg:DI (abs:DI (sign_extend:DI
7411 (match_operand:SI 1 "register_operand" "d")))))
7412 (clobber (reg:CC CC_REGNUM))]
7415 [(set_attr "op_type" "RRE")
7416 (set_attr "z10prop" "z10_c")])
7419 (define_insn "*negabs<mode>2_cc"
7420 [(set (reg CC_REGNUM)
7421 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7423 (set (match_operand:GPR 0 "register_operand" "=d")
7424 (neg:GPR (abs:GPR (match_dup 1))))]
7425 "s390_match_ccmode (insn, CCAmode)"
7427 [(set_attr "op_type" "RR<E>")
7428 (set_attr "z10prop" "z10_c")])
7431 (define_insn "*negabs<mode>2_cconly"
7432 [(set (reg CC_REGNUM)
7433 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7435 (clobber (match_scratch:GPR 0 "=d"))]
7436 "s390_match_ccmode (insn, CCAmode)"
7438 [(set_attr "op_type" "RR<E>")
7439 (set_attr "z10prop" "z10_c")])
7442 (define_insn "*negabs<mode>2"
7443 [(set (match_operand:GPR 0 "register_operand" "=d")
7444 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7445 (clobber (reg:CC CC_REGNUM))]
7448 [(set_attr "op_type" "RR<E>")
7449 (set_attr "z10prop" "z10_c")])
7455 ; lnxbr, lndbr, lnebr
7456 (define_insn "*negabs<mode>2_cc"
7457 [(set (reg CC_REGNUM)
7458 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7459 (match_operand:BFP 2 "const0_operand" "")))
7460 (set (match_operand:BFP 0 "register_operand" "=f")
7461 (neg:BFP (abs:BFP (match_dup 1))))]
7462 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7464 [(set_attr "op_type" "RRE")
7465 (set_attr "type" "fsimp<mode>")])
7467 ; lnxbr, lndbr, lnebr
7468 (define_insn "*negabs<mode>2_cconly"
7469 [(set (reg CC_REGNUM)
7470 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7471 (match_operand:BFP 2 "const0_operand" "")))
7472 (clobber (match_scratch:BFP 0 "=f"))]
7473 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7475 [(set_attr "op_type" "RRE")
7476 (set_attr "type" "fsimp<mode>")])
7479 (define_insn "*negabs<mode>2_nocc"
7480 [(set (match_operand:FP 0 "register_operand" "=f")
7481 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7484 [(set_attr "op_type" "RRE")
7485 (set_attr "type" "fsimp<mode>")])
7487 ; lnxbr, lndbr, lnebr
7488 (define_insn "*negabs<mode>2"
7489 [(set (match_operand:BFP 0 "register_operand" "=f")
7490 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7491 (clobber (reg:CC CC_REGNUM))]
7494 [(set_attr "op_type" "RRE")
7495 (set_attr "type" "fsimp<mode>")])
7498 ;;- Square root instructions.
7502 ; sqrt(df|sf)2 instruction pattern(s).
7505 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7506 (define_insn "sqrt<mode>2"
7507 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7508 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7513 [(set_attr "op_type" "RRE,RXE")
7514 (set_attr "type" "fsqrt<mode>")])
7518 ;;- One complement instructions.
7522 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7525 (define_expand "one_cmpl<mode>2"
7527 [(set (match_operand:INT 0 "register_operand" "")
7528 (xor:INT (match_operand:INT 1 "register_operand" "")
7530 (clobber (reg:CC CC_REGNUM))])]
7536 ;; Find leftmost bit instructions.
7539 (define_expand "clzdi2"
7540 [(set (match_operand:DI 0 "register_operand" "=d")
7541 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7542 "TARGET_EXTIMM && TARGET_ZARCH"
7544 rtx insn, clz_equal;
7545 rtx wide_reg = gen_reg_rtx (TImode);
7546 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7548 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7550 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7552 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7553 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7558 (define_insn "clztidi2"
7559 [(set (match_operand:TI 0 "register_operand" "=d")
7563 (xor:DI (match_operand:DI 1 "register_operand" "d")
7564 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7565 (subreg:SI (clz:DI (match_dup 1)) 4))))
7568 (zero_extend:TI (clz:DI (match_dup 1)))))
7569 (clobber (reg:CC CC_REGNUM))]
7570 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7571 == (unsigned HOST_WIDE_INT) 1 << 63
7572 && TARGET_EXTIMM && TARGET_ZARCH"
7574 [(set_attr "op_type" "RRE")])
7578 ;;- Rotate instructions.
7582 ; rotl(di|si)3 instruction pattern(s).
7586 (define_insn "rotl<mode>3"
7587 [(set (match_operand:GPR 0 "register_operand" "=d")
7588 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7589 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7592 [(set_attr "op_type" "RSE")
7593 (set_attr "atype" "reg")
7594 (set_attr "z10prop" "z10_super_E1")])
7597 (define_insn "*rotl<mode>3_and"
7598 [(set (match_operand:GPR 0 "register_operand" "=d")
7599 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7600 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7601 (match_operand:SI 3 "const_int_operand" "n"))))]
7602 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7604 [(set_attr "op_type" "RSE")
7605 (set_attr "atype" "reg")
7606 (set_attr "z10prop" "z10_super_E1")])
7610 ;;- Shift instructions.
7614 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7615 ; Left shifts and logical right shifts
7617 (define_expand "<shift><mode>3"
7618 [(set (match_operand:DSI 0 "register_operand" "")
7619 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7620 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7625 (define_insn "*<shift>di3_31"
7626 [(set (match_operand:DI 0 "register_operand" "=d")
7627 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7628 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7631 [(set_attr "op_type" "RS")
7632 (set_attr "atype" "reg")
7633 (set_attr "z196prop" "z196_cracked")])
7635 ; sll, srl, sllg, srlg, sllk, srlk
7636 (define_insn "*<shift><mode>3"
7637 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7638 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7639 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7642 s<lr>l<g>\t%0,<1>%Y2
7643 s<lr>l<gk>\t%0,%1,%Y2"
7644 [(set_attr "op_type" "RS<E>,RSY")
7645 (set_attr "atype" "reg,reg")
7646 (set_attr "cpu_facility" "*,z196")
7647 (set_attr "z10prop" "z10_super_E1,*")])
7650 (define_insn "*<shift>di3_31_and"
7651 [(set (match_operand:DI 0 "register_operand" "=d")
7652 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7653 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7654 (match_operand:SI 3 "const_int_operand" "n"))))]
7655 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7657 [(set_attr "op_type" "RS")
7658 (set_attr "atype" "reg")])
7660 ; sll, srl, sllg, srlg, sllk, srlk
7661 (define_insn "*<shift><mode>3_and"
7662 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7663 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7664 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7665 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7666 "(INTVAL (operands[3]) & 63) == 63"
7668 s<lr>l<g>\t%0,<1>%Y2
7669 s<lr>l<gk>\t%0,%1,%Y2"
7670 [(set_attr "op_type" "RS<E>,RSY")
7671 (set_attr "atype" "reg,reg")
7672 (set_attr "cpu_facility" "*,z196")
7673 (set_attr "z10prop" "z10_super_E1,*")])
7676 ; ashr(di|si)3 instruction pattern(s).
7677 ; Arithmetic right shifts
7679 (define_expand "ashr<mode>3"
7681 [(set (match_operand:DSI 0 "register_operand" "")
7682 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7683 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7684 (clobber (reg:CC CC_REGNUM))])]
7688 (define_insn "*ashrdi3_cc_31"
7689 [(set (reg CC_REGNUM)
7690 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7691 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7693 (set (match_operand:DI 0 "register_operand" "=d")
7694 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7695 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7697 [(set_attr "op_type" "RS")
7698 (set_attr "atype" "reg")])
7700 (define_insn "*ashrdi3_cconly_31"
7701 [(set (reg CC_REGNUM)
7702 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7703 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7705 (clobber (match_scratch:DI 0 "=d"))]
7706 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7708 [(set_attr "op_type" "RS")
7709 (set_attr "atype" "reg")])
7711 (define_insn "*ashrdi3_31"
7712 [(set (match_operand:DI 0 "register_operand" "=d")
7713 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7714 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7715 (clobber (reg:CC CC_REGNUM))]
7718 [(set_attr "op_type" "RS")
7719 (set_attr "atype" "reg")])
7722 (define_insn "*ashr<mode>3_cc"
7723 [(set (reg CC_REGNUM)
7724 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7725 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7727 (set (match_operand:GPR 0 "register_operand" "=d,d")
7728 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7729 "s390_match_ccmode(insn, CCSmode)"
7733 [(set_attr "op_type" "RS<E>,RSY")
7734 (set_attr "atype" "reg,reg")
7735 (set_attr "cpu_facility" "*,z196")
7736 (set_attr "z10prop" "z10_super_E1,*")])
7739 (define_insn "*ashr<mode>3_cconly"
7740 [(set (reg CC_REGNUM)
7741 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7742 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7744 (clobber (match_scratch:GPR 0 "=d,d"))]
7745 "s390_match_ccmode(insn, CCSmode)"
7749 [(set_attr "op_type" "RS<E>,RSY")
7750 (set_attr "atype" "reg,reg")
7751 (set_attr "cpu_facility" "*,z196")
7752 (set_attr "z10prop" "z10_super_E1,*")])
7755 (define_insn "*ashr<mode>3"
7756 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7757 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7758 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7759 (clobber (reg:CC CC_REGNUM))]
7764 [(set_attr "op_type" "RS<E>,RSY")
7765 (set_attr "atype" "reg,reg")
7766 (set_attr "cpu_facility" "*,z196")
7767 (set_attr "z10prop" "z10_super_E1,*")])
7770 ; shift pattern with implicit ANDs
7772 (define_insn "*ashrdi3_cc_31_and"
7773 [(set (reg CC_REGNUM)
7774 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7775 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7776 (match_operand:SI 3 "const_int_operand" "n")))
7778 (set (match_operand:DI 0 "register_operand" "=d")
7779 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7780 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7781 && (INTVAL (operands[3]) & 63) == 63"
7783 [(set_attr "op_type" "RS")
7784 (set_attr "atype" "reg")])
7786 (define_insn "*ashrdi3_cconly_31_and"
7787 [(set (reg CC_REGNUM)
7788 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7789 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7790 (match_operand:SI 3 "const_int_operand" "n")))
7792 (clobber (match_scratch:DI 0 "=d"))]
7793 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7794 && (INTVAL (operands[3]) & 63) == 63"
7796 [(set_attr "op_type" "RS")
7797 (set_attr "atype" "reg")])
7799 (define_insn "*ashrdi3_31_and"
7800 [(set (match_operand:DI 0 "register_operand" "=d")
7801 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7802 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7803 (match_operand:SI 3 "const_int_operand" "n"))))
7804 (clobber (reg:CC CC_REGNUM))]
7805 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7807 [(set_attr "op_type" "RS")
7808 (set_attr "atype" "reg")])
7811 (define_insn "*ashr<mode>3_cc_and"
7812 [(set (reg CC_REGNUM)
7813 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7814 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7815 (match_operand:SI 3 "const_int_operand" "n,n")))
7817 (set (match_operand:GPR 0 "register_operand" "=d,d")
7818 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7819 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7823 [(set_attr "op_type" "RS<E>,RSY")
7824 (set_attr "atype" "reg,reg")
7825 (set_attr "cpu_facility" "*,z196")
7826 (set_attr "z10prop" "z10_super_E1,*")])
7829 (define_insn "*ashr<mode>3_cconly_and"
7830 [(set (reg CC_REGNUM)
7831 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7832 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7833 (match_operand:SI 3 "const_int_operand" "n,n")))
7835 (clobber (match_scratch:GPR 0 "=d,d"))]
7836 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7840 [(set_attr "op_type" "RS<E>,RSY")
7841 (set_attr "atype" "reg,reg")
7842 (set_attr "cpu_facility" "*,z196")
7843 (set_attr "z10prop" "z10_super_E1,*")])
7846 (define_insn "*ashr<mode>3_and"
7847 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7848 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7849 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7850 (match_operand:SI 3 "const_int_operand" "n,n"))))
7851 (clobber (reg:CC CC_REGNUM))]
7852 "(INTVAL (operands[3]) & 63) == 63"
7856 [(set_attr "op_type" "RS<E>,RSY")
7857 (set_attr "atype" "reg,reg")
7858 (set_attr "cpu_facility" "*,z196")
7859 (set_attr "z10prop" "z10_super_E1,*")])
7863 ;; Branch instruction patterns.
7866 (define_expand "cbranch<mode>4"
7868 (if_then_else (match_operator 0 "comparison_operator"
7869 [(match_operand:GPR 1 "register_operand" "")
7870 (match_operand:GPR 2 "general_operand" "")])
7871 (label_ref (match_operand 3 "" ""))
7874 "s390_emit_jump (operands[3],
7875 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7878 (define_expand "cbranch<mode>4"
7880 (if_then_else (match_operator 0 "comparison_operator"
7881 [(match_operand:FP 1 "register_operand" "")
7882 (match_operand:FP 2 "general_operand" "")])
7883 (label_ref (match_operand 3 "" ""))
7886 "s390_emit_jump (operands[3],
7887 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7890 (define_expand "cbranchcc4"
7892 (if_then_else (match_operator 0 "s390_eqne_operator"
7893 [(match_operand 1 "cc_reg_operand" "")
7894 (match_operand 2 "const0_operand" "")])
7895 (label_ref (match_operand 3 "" ""))
7898 "s390_emit_jump (operands[3],
7899 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7905 ;;- Conditional jump instructions.
7908 (define_insn "*cjump_64"
7911 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7912 (label_ref (match_operand 0 "" ""))
7916 if (get_attr_length (insn) == 4)
7919 return "jg%C1\t%l0";
7921 [(set_attr "op_type" "RI")
7922 (set_attr "type" "branch")
7923 (set (attr "length")
7924 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7925 (const_int 4) (const_int 6)))])
7927 (define_insn "*cjump_31"
7930 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7931 (label_ref (match_operand 0 "" ""))
7935 gcc_assert (get_attr_length (insn) == 4);
7938 [(set_attr "op_type" "RI")
7939 (set_attr "type" "branch")
7940 (set (attr "length")
7941 (if_then_else (not (match_test "flag_pic"))
7942 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7943 (const_int 4) (const_int 6))
7944 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7945 (const_int 4) (const_int 8))))])
7947 (define_insn "*cjump_long"
7950 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7951 (match_operand 0 "address_operand" "ZQZR")
7955 if (get_attr_op_type (insn) == OP_TYPE_RR)
7960 [(set (attr "op_type")
7961 (if_then_else (match_operand 0 "register_operand" "")
7962 (const_string "RR") (const_string "RX")))
7963 (set_attr "type" "branch")
7964 (set_attr "atype" "agen")])
7968 ;;- Negated conditional jump instructions.
7971 (define_insn "*icjump_64"
7974 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7976 (label_ref (match_operand 0 "" ""))))]
7979 if (get_attr_length (insn) == 4)
7982 return "jg%D1\t%l0";
7984 [(set_attr "op_type" "RI")
7985 (set_attr "type" "branch")
7986 (set (attr "length")
7987 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7988 (const_int 4) (const_int 6)))])
7990 (define_insn "*icjump_31"
7993 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7995 (label_ref (match_operand 0 "" ""))))]
7998 gcc_assert (get_attr_length (insn) == 4);
8001 [(set_attr "op_type" "RI")
8002 (set_attr "type" "branch")
8003 (set (attr "length")
8004 (if_then_else (not (match_test "flag_pic"))
8005 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8006 (const_int 4) (const_int 6))
8007 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8008 (const_int 4) (const_int 8))))])
8010 (define_insn "*icjump_long"
8013 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8015 (match_operand 0 "address_operand" "ZQZR")))]
8018 if (get_attr_op_type (insn) == OP_TYPE_RR)
8023 [(set (attr "op_type")
8024 (if_then_else (match_operand 0 "register_operand" "")
8025 (const_string "RR") (const_string "RX")))
8026 (set_attr "type" "branch")
8027 (set_attr "atype" "agen")])
8030 ;;- Trap instructions.
8034 [(trap_if (const_int 1) (const_int 0))]
8037 [(set_attr "op_type" "RI")
8038 (set_attr "type" "branch")])
8040 (define_expand "ctrap<mode>4"
8041 [(trap_if (match_operator 0 "comparison_operator"
8042 [(match_operand:GPR 1 "register_operand" "")
8043 (match_operand:GPR 2 "general_operand" "")])
8044 (match_operand 3 "const0_operand" ""))]
8047 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8048 operands[1], operands[2]);
8049 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8053 (define_expand "ctrap<mode>4"
8054 [(trap_if (match_operator 0 "comparison_operator"
8055 [(match_operand:FP 1 "register_operand" "")
8056 (match_operand:FP 2 "general_operand" "")])
8057 (match_operand 3 "const0_operand" ""))]
8060 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8061 operands[1], operands[2]);
8062 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8066 (define_insn "condtrap"
8067 [(trap_if (match_operator 0 "s390_comparison"
8068 [(match_operand 1 "cc_reg_operand" "c")
8073 [(set_attr "op_type" "RI")
8074 (set_attr "type" "branch")])
8076 ; crt, cgrt, cit, cgit
8077 (define_insn "*cmp_and_trap_signed_int<mode>"
8078 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8079 [(match_operand:GPR 1 "register_operand" "d,d")
8080 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8086 [(set_attr "op_type" "RRF,RIE")
8087 (set_attr "type" "branch")
8088 (set_attr "z10prop" "z10_super_c,z10_super")])
8090 ; clrt, clgrt, clfit, clgit, clt, clgt
8091 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8092 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8093 [(match_operand:GPR 1 "register_operand" "d,d, d")
8094 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8101 [(set_attr "op_type" "RRF,RIE,RSY")
8102 (set_attr "type" "branch")
8103 (set_attr "z10prop" "z10_super_c,z10_super,*")
8104 (set_attr "cpu_facility" "z10,z10,zEC12")])
8107 (define_insn "*load_and_trap<mode>"
8108 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8111 (set (match_operand:GPR 1 "register_operand" "=d")
8115 [(set_attr "op_type" "RXY")])
8119 ;;- Loop instructions.
8121 ;; This is all complicated by the fact that since this is a jump insn
8122 ;; we must handle our own output reloads.
8126 ; This splitter will be matched by combine and has to add the 2 moves
8127 ; necessary to load the compare and the increment values into a
8128 ; register pair as needed by brxle.
8130 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8133 (match_operator 6 "s390_brx_operator"
8134 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8135 (match_operand:GPR 2 "general_operand" ""))
8136 (match_operand:GPR 3 "register_operand" "")])
8137 (label_ref (match_operand 0 "" ""))
8139 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8140 (plus:GPR (match_dup 1) (match_dup 2)))
8141 (clobber (match_scratch:GPR 5 ""))]
8144 "!reload_completed && !reload_in_progress"
8145 [(set (match_dup 7) (match_dup 2)) ; the increment
8146 (set (match_dup 8) (match_dup 3)) ; the comparison value
8147 (parallel [(set (pc)
8150 [(plus:GPR (match_dup 1) (match_dup 7))
8152 (label_ref (match_dup 0))
8155 (plus:GPR (match_dup 1) (match_dup 7)))
8156 (clobber (match_dup 5))
8157 (clobber (reg:CC CC_REGNUM))])]
8159 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8160 operands[7] = gen_lowpart (<GPR:MODE>mode,
8161 gen_highpart (word_mode, dreg));
8162 operands[8] = gen_lowpart (<GPR:MODE>mode,
8163 gen_lowpart (word_mode, dreg));
8168 (define_insn_and_split "*brxg_64bit"
8171 (match_operator 5 "s390_brx_operator"
8172 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8173 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8174 (subreg:DI (match_dup 2) 8)])
8175 (label_ref (match_operand 0 "" ""))
8177 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8178 (plus:DI (match_dup 1)
8179 (subreg:DI (match_dup 2) 0)))
8180 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8181 (clobber (reg:CC CC_REGNUM))]
8184 if (which_alternative != 0)
8186 else if (get_attr_length (insn) == 6)
8187 return "brx%E5g\t%1,%2,%l0";
8189 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8191 "&& reload_completed
8192 && (!REG_P (operands[3])
8193 || !rtx_equal_p (operands[1], operands[3]))"
8194 [(set (match_dup 4) (match_dup 1))
8195 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8196 (clobber (reg:CC CC_REGNUM))])
8197 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8198 (set (match_dup 3) (match_dup 4))
8199 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8200 (label_ref (match_dup 0))
8203 [(set_attr "op_type" "RIE")
8204 (set_attr "type" "branch")
8205 (set (attr "length")
8206 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8207 (const_int 6) (const_int 16)))])
8211 (define_insn_and_split "*brx_64bit"
8214 (match_operator 5 "s390_brx_operator"
8215 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8216 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8217 (subreg:SI (match_dup 2) 12)])
8218 (label_ref (match_operand 0 "" ""))
8220 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8221 (plus:SI (match_dup 1)
8222 (subreg:SI (match_dup 2) 4)))
8223 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8224 (clobber (reg:CC CC_REGNUM))]
8227 if (which_alternative != 0)
8229 else if (get_attr_length (insn) == 6)
8230 return "brx%C5\t%1,%2,%l0";
8232 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8234 "&& reload_completed
8235 && (!REG_P (operands[3])
8236 || !rtx_equal_p (operands[1], operands[3]))"
8237 [(set (match_dup 4) (match_dup 1))
8238 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8239 (clobber (reg:CC CC_REGNUM))])
8240 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8241 (set (match_dup 3) (match_dup 4))
8242 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8243 (label_ref (match_dup 0))
8246 [(set_attr "op_type" "RSI")
8247 (set_attr "type" "branch")
8248 (set (attr "length")
8249 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8250 (const_int 6) (const_int 14)))])
8254 (define_insn_and_split "*brx_31bit"
8257 (match_operator 5 "s390_brx_operator"
8258 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8259 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8260 (subreg:SI (match_dup 2) 4)])
8261 (label_ref (match_operand 0 "" ""))
8263 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8264 (plus:SI (match_dup 1)
8265 (subreg:SI (match_dup 2) 0)))
8266 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8267 (clobber (reg:CC CC_REGNUM))]
8268 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8270 if (which_alternative != 0)
8272 else if (get_attr_length (insn) == 6)
8273 return "brx%C5\t%1,%2,%l0";
8275 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8277 "&& reload_completed
8278 && (!REG_P (operands[3])
8279 || !rtx_equal_p (operands[1], operands[3]))"
8280 [(set (match_dup 4) (match_dup 1))
8281 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8282 (clobber (reg:CC CC_REGNUM))])
8283 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8284 (set (match_dup 3) (match_dup 4))
8285 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8286 (label_ref (match_dup 0))
8289 [(set_attr "op_type" "RSI")
8290 (set_attr "type" "branch")
8291 (set (attr "length")
8292 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8293 (const_int 6) (const_int 14)))])
8298 (define_expand "doloop_end"
8299 [(use (match_operand 0 "" "")) ; loop pseudo
8300 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8301 (use (match_operand 2 "" "")) ; max iterations
8302 (use (match_operand 3 "" "")) ; loop level
8303 (use (match_operand 4 "" "")) ; label
8304 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
8307 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8308 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8309 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8310 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8311 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8312 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8319 (define_insn_and_split "doloop_si64"
8322 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8324 (label_ref (match_operand 0 "" ""))
8326 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8327 (plus:SI (match_dup 1) (const_int -1)))
8328 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8329 (clobber (reg:CC CC_REGNUM))]
8332 if (which_alternative != 0)
8334 else if (get_attr_length (insn) == 4)
8335 return "brct\t%1,%l0";
8337 return "ahi\t%1,-1\;jgne\t%l0";
8339 "&& reload_completed
8340 && (! REG_P (operands[2])
8341 || ! rtx_equal_p (operands[1], operands[2]))"
8342 [(set (match_dup 3) (match_dup 1))
8343 (parallel [(set (reg:CCAN CC_REGNUM)
8344 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8346 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8347 (set (match_dup 2) (match_dup 3))
8348 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8349 (label_ref (match_dup 0))
8352 [(set_attr "op_type" "RI")
8353 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8354 ; hurt us in the (rare) case of ahi.
8355 (set_attr "z10prop" "z10_super_E1")
8356 (set_attr "type" "branch")
8357 (set (attr "length")
8358 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8359 (const_int 4) (const_int 10)))])
8361 (define_insn_and_split "doloop_si31"
8364 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8366 (label_ref (match_operand 0 "" ""))
8368 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8369 (plus:SI (match_dup 1) (const_int -1)))
8370 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8371 (clobber (reg:CC CC_REGNUM))]
8374 if (which_alternative != 0)
8376 else if (get_attr_length (insn) == 4)
8377 return "brct\t%1,%l0";
8381 "&& reload_completed
8382 && (! REG_P (operands[2])
8383 || ! rtx_equal_p (operands[1], operands[2]))"
8384 [(set (match_dup 3) (match_dup 1))
8385 (parallel [(set (reg:CCAN CC_REGNUM)
8386 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8388 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8389 (set (match_dup 2) (match_dup 3))
8390 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8391 (label_ref (match_dup 0))
8394 [(set_attr "op_type" "RI")
8395 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8396 ; hurt us in the (rare) case of ahi.
8397 (set_attr "z10prop" "z10_super_E1")
8398 (set_attr "type" "branch")
8399 (set (attr "length")
8400 (if_then_else (not (match_test "flag_pic"))
8401 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8402 (const_int 4) (const_int 6))
8403 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8404 (const_int 4) (const_int 8))))])
8406 (define_insn "*doloop_si_long"
8409 (ne (match_operand:SI 1 "register_operand" "d")
8411 (match_operand 0 "address_operand" "ZQZR")
8413 (set (match_operand:SI 2 "register_operand" "=1")
8414 (plus:SI (match_dup 1) (const_int -1)))
8415 (clobber (match_scratch:SI 3 "=X"))
8416 (clobber (reg:CC CC_REGNUM))]
8419 if (get_attr_op_type (insn) == OP_TYPE_RR)
8420 return "bctr\t%1,%0";
8422 return "bct\t%1,%a0";
8424 [(set (attr "op_type")
8425 (if_then_else (match_operand 0 "register_operand" "")
8426 (const_string "RR") (const_string "RX")))
8427 (set_attr "type" "branch")
8428 (set_attr "atype" "agen")
8429 (set_attr "z10prop" "z10_c")
8430 (set_attr "z196prop" "z196_cracked")])
8432 (define_insn_and_split "doloop_di"
8435 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8437 (label_ref (match_operand 0 "" ""))
8439 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8440 (plus:DI (match_dup 1) (const_int -1)))
8441 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8442 (clobber (reg:CC CC_REGNUM))]
8445 if (which_alternative != 0)
8447 else if (get_attr_length (insn) == 4)
8448 return "brctg\t%1,%l0";
8450 return "aghi\t%1,-1\;jgne\t%l0";
8452 "&& reload_completed
8453 && (! REG_P (operands[2])
8454 || ! rtx_equal_p (operands[1], operands[2]))"
8455 [(set (match_dup 3) (match_dup 1))
8456 (parallel [(set (reg:CCAN CC_REGNUM)
8457 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8459 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8460 (set (match_dup 2) (match_dup 3))
8461 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8462 (label_ref (match_dup 0))
8465 [(set_attr "op_type" "RI")
8466 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8467 ; hurt us in the (rare) case of ahi.
8468 (set_attr "z10prop" "z10_super_E1")
8469 (set_attr "type" "branch")
8470 (set (attr "length")
8471 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8472 (const_int 4) (const_int 10)))])
8475 ;;- Unconditional jump instructions.
8479 ; jump instruction pattern(s).
8482 (define_expand "jump"
8483 [(match_operand 0 "" "")]
8485 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8487 (define_insn "*jump64"
8488 [(set (pc) (label_ref (match_operand 0 "" "")))]
8491 if (get_attr_length (insn) == 4)
8496 [(set_attr "op_type" "RI")
8497 (set_attr "type" "branch")
8498 (set (attr "length")
8499 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8500 (const_int 4) (const_int 6)))])
8502 (define_insn "*jump31"
8503 [(set (pc) (label_ref (match_operand 0 "" "")))]
8506 gcc_assert (get_attr_length (insn) == 4);
8509 [(set_attr "op_type" "RI")
8510 (set_attr "type" "branch")
8511 (set (attr "length")
8512 (if_then_else (not (match_test "flag_pic"))
8513 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8514 (const_int 4) (const_int 6))
8515 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8516 (const_int 4) (const_int 8))))])
8519 ; indirect-jump instruction pattern(s).
8522 (define_insn "indirect_jump"
8523 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8526 if (get_attr_op_type (insn) == OP_TYPE_RR)
8531 [(set (attr "op_type")
8532 (if_then_else (match_operand 0 "register_operand" "")
8533 (const_string "RR") (const_string "RX")))
8534 (set_attr "type" "branch")
8535 (set_attr "atype" "agen")])
8538 ; casesi instruction pattern(s).
8541 (define_insn "casesi_jump"
8542 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8543 (use (label_ref (match_operand 1 "" "")))]
8546 if (get_attr_op_type (insn) == OP_TYPE_RR)
8551 [(set (attr "op_type")
8552 (if_then_else (match_operand 0 "register_operand" "")
8553 (const_string "RR") (const_string "RX")))
8554 (set_attr "type" "branch")
8555 (set_attr "atype" "agen")])
8557 (define_expand "casesi"
8558 [(match_operand:SI 0 "general_operand" "")
8559 (match_operand:SI 1 "general_operand" "")
8560 (match_operand:SI 2 "general_operand" "")
8561 (label_ref (match_operand 3 "" ""))
8562 (label_ref (match_operand 4 "" ""))]
8565 rtx index = gen_reg_rtx (SImode);
8566 rtx base = gen_reg_rtx (Pmode);
8567 rtx target = gen_reg_rtx (Pmode);
8569 emit_move_insn (index, operands[0]);
8570 emit_insn (gen_subsi3 (index, index, operands[1]));
8571 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8574 if (Pmode != SImode)
8575 index = convert_to_mode (Pmode, index, 1);
8576 if (GET_CODE (index) != REG)
8577 index = copy_to_mode_reg (Pmode, index);
8580 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8582 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8584 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8586 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8587 emit_move_insn (target, index);
8590 target = gen_rtx_PLUS (Pmode, base, target);
8591 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8598 ;;- Jump to subroutine.
8603 ; untyped call instruction pattern(s).
8606 ;; Call subroutine returning any type.
8607 (define_expand "untyped_call"
8608 [(parallel [(call (match_operand 0 "" "")
8610 (match_operand 1 "" "")
8611 (match_operand 2 "" "")])]
8616 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8618 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8620 rtx set = XVECEXP (operands[2], 0, i);
8621 emit_move_insn (SET_DEST (set), SET_SRC (set));
8624 /* The optimizer does not know that the call sets the function value
8625 registers we stored in the result block. We avoid problems by
8626 claiming that all hard registers are used and clobbered at this
8628 emit_insn (gen_blockage ());
8633 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8634 ;; all of memory. This blocks insns from being moved across this point.
8636 (define_insn "blockage"
8637 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8640 [(set_attr "type" "none")
8641 (set_attr "length" "0")])
8647 (define_expand "sibcall"
8648 [(call (match_operand 0 "" "")
8649 (match_operand 1 "" ""))]
8652 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8656 (define_insn "*sibcall_br"
8657 [(call (mem:QI (reg SIBCALL_REGNUM))
8658 (match_operand 0 "const_int_operand" "n"))]
8659 "SIBLING_CALL_P (insn)
8660 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8662 [(set_attr "op_type" "RR")
8663 (set_attr "type" "branch")
8664 (set_attr "atype" "agen")])
8666 (define_insn "*sibcall_brc"
8667 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8668 (match_operand 1 "const_int_operand" "n"))]
8669 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8671 [(set_attr "op_type" "RI")
8672 (set_attr "type" "branch")])
8674 (define_insn "*sibcall_brcl"
8675 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8676 (match_operand 1 "const_int_operand" "n"))]
8677 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8679 [(set_attr "op_type" "RIL")
8680 (set_attr "type" "branch")])
8683 ; sibcall_value patterns
8686 (define_expand "sibcall_value"
8687 [(set (match_operand 0 "" "")
8688 (call (match_operand 1 "" "")
8689 (match_operand 2 "" "")))]
8692 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8696 (define_insn "*sibcall_value_br"
8697 [(set (match_operand 0 "" "")
8698 (call (mem:QI (reg SIBCALL_REGNUM))
8699 (match_operand 1 "const_int_operand" "n")))]
8700 "SIBLING_CALL_P (insn)
8701 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8703 [(set_attr "op_type" "RR")
8704 (set_attr "type" "branch")
8705 (set_attr "atype" "agen")])
8707 (define_insn "*sibcall_value_brc"
8708 [(set (match_operand 0 "" "")
8709 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8710 (match_operand 2 "const_int_operand" "n")))]
8711 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8713 [(set_attr "op_type" "RI")
8714 (set_attr "type" "branch")])
8716 (define_insn "*sibcall_value_brcl"
8717 [(set (match_operand 0 "" "")
8718 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8719 (match_operand 2 "const_int_operand" "n")))]
8720 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8722 [(set_attr "op_type" "RIL")
8723 (set_attr "type" "branch")])
8727 ; call instruction pattern(s).
8730 (define_expand "call"
8731 [(call (match_operand 0 "" "")
8732 (match_operand 1 "" ""))
8733 (use (match_operand 2 "" ""))]
8736 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8737 gen_rtx_REG (Pmode, RETURN_REGNUM));
8741 (define_insn "*bras"
8742 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8743 (match_operand 1 "const_int_operand" "n"))
8744 (clobber (match_operand 2 "register_operand" "=r"))]
8745 "!SIBLING_CALL_P (insn)
8746 && TARGET_SMALL_EXEC
8747 && GET_MODE (operands[2]) == Pmode"
8749 [(set_attr "op_type" "RI")
8750 (set_attr "type" "jsr")
8751 (set_attr "z196prop" "z196_cracked")])
8753 (define_insn "*brasl"
8754 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8755 (match_operand 1 "const_int_operand" "n"))
8756 (clobber (match_operand 2 "register_operand" "=r"))]
8757 "!SIBLING_CALL_P (insn)
8759 && GET_MODE (operands[2]) == Pmode"
8761 [(set_attr "op_type" "RIL")
8762 (set_attr "type" "jsr")
8763 (set_attr "z196prop" "z196_cracked")])
8765 (define_insn "*basr"
8766 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8767 (match_operand 1 "const_int_operand" "n"))
8768 (clobber (match_operand 2 "register_operand" "=r"))]
8769 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8771 if (get_attr_op_type (insn) == OP_TYPE_RR)
8772 return "basr\t%2,%0";
8774 return "bas\t%2,%a0";
8776 [(set (attr "op_type")
8777 (if_then_else (match_operand 0 "register_operand" "")
8778 (const_string "RR") (const_string "RX")))
8779 (set_attr "type" "jsr")
8780 (set_attr "atype" "agen")
8781 (set_attr "z196prop" "z196_cracked")])
8784 ; call_value instruction pattern(s).
8787 (define_expand "call_value"
8788 [(set (match_operand 0 "" "")
8789 (call (match_operand 1 "" "")
8790 (match_operand 2 "" "")))
8791 (use (match_operand 3 "" ""))]
8794 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8795 gen_rtx_REG (Pmode, RETURN_REGNUM));
8799 (define_insn "*bras_r"
8800 [(set (match_operand 0 "" "")
8801 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8802 (match_operand:SI 2 "const_int_operand" "n")))
8803 (clobber (match_operand 3 "register_operand" "=r"))]
8804 "!SIBLING_CALL_P (insn)
8805 && TARGET_SMALL_EXEC
8806 && GET_MODE (operands[3]) == Pmode"
8808 [(set_attr "op_type" "RI")
8809 (set_attr "type" "jsr")
8810 (set_attr "z196prop" "z196_cracked")])
8812 (define_insn "*brasl_r"
8813 [(set (match_operand 0 "" "")
8814 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8815 (match_operand 2 "const_int_operand" "n")))
8816 (clobber (match_operand 3 "register_operand" "=r"))]
8817 "!SIBLING_CALL_P (insn)
8819 && GET_MODE (operands[3]) == Pmode"
8821 [(set_attr "op_type" "RIL")
8822 (set_attr "type" "jsr")
8823 (set_attr "z196prop" "z196_cracked")])
8825 (define_insn "*basr_r"
8826 [(set (match_operand 0 "" "")
8827 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8828 (match_operand 2 "const_int_operand" "n")))
8829 (clobber (match_operand 3 "register_operand" "=r"))]
8830 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8832 if (get_attr_op_type (insn) == OP_TYPE_RR)
8833 return "basr\t%3,%1";
8835 return "bas\t%3,%a1";
8837 [(set (attr "op_type")
8838 (if_then_else (match_operand 1 "register_operand" "")
8839 (const_string "RR") (const_string "RX")))
8840 (set_attr "type" "jsr")
8841 (set_attr "atype" "agen")
8842 (set_attr "z196prop" "z196_cracked")])
8845 ;;- Thread-local storage support.
8848 (define_expand "get_thread_pointer<mode>"
8849 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8853 (define_expand "set_thread_pointer<mode>"
8854 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8855 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8859 (define_insn "*set_tp"
8860 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8863 [(set_attr "type" "none")
8864 (set_attr "length" "0")])
8866 (define_insn "*tls_load_64"
8867 [(set (match_operand:DI 0 "register_operand" "=d")
8868 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8869 (match_operand:DI 2 "" "")]
8873 [(set_attr "op_type" "RXE")
8874 (set_attr "z10prop" "z10_fwd_A3")])
8876 (define_insn "*tls_load_31"
8877 [(set (match_operand:SI 0 "register_operand" "=d,d")
8878 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8879 (match_operand:SI 2 "" "")]
8885 [(set_attr "op_type" "RX,RXY")
8886 (set_attr "type" "load")
8887 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8889 (define_insn "*bras_tls"
8890 [(set (match_operand 0 "" "")
8891 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8892 (match_operand 2 "const_int_operand" "n")))
8893 (clobber (match_operand 3 "register_operand" "=r"))
8894 (use (match_operand 4 "" ""))]
8895 "!SIBLING_CALL_P (insn)
8896 && TARGET_SMALL_EXEC
8897 && GET_MODE (operands[3]) == Pmode"
8899 [(set_attr "op_type" "RI")
8900 (set_attr "type" "jsr")
8901 (set_attr "z196prop" "z196_cracked")])
8903 (define_insn "*brasl_tls"
8904 [(set (match_operand 0 "" "")
8905 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8906 (match_operand 2 "const_int_operand" "n")))
8907 (clobber (match_operand 3 "register_operand" "=r"))
8908 (use (match_operand 4 "" ""))]
8909 "!SIBLING_CALL_P (insn)
8911 && GET_MODE (operands[3]) == Pmode"
8913 [(set_attr "op_type" "RIL")
8914 (set_attr "type" "jsr")
8915 (set_attr "z196prop" "z196_cracked")])
8917 (define_insn "*basr_tls"
8918 [(set (match_operand 0 "" "")
8919 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8920 (match_operand 2 "const_int_operand" "n")))
8921 (clobber (match_operand 3 "register_operand" "=r"))
8922 (use (match_operand 4 "" ""))]
8923 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8925 if (get_attr_op_type (insn) == OP_TYPE_RR)
8926 return "basr\t%3,%1%J4";
8928 return "bas\t%3,%a1%J4";
8930 [(set (attr "op_type")
8931 (if_then_else (match_operand 1 "register_operand" "")
8932 (const_string "RR") (const_string "RX")))
8933 (set_attr "type" "jsr")
8934 (set_attr "atype" "agen")
8935 (set_attr "z196prop" "z196_cracked")])
8938 ;;- Atomic operations
8942 ; memory barrier patterns.
8945 (define_expand "mem_signal_fence"
8946 [(match_operand:SI 0 "const_int_operand")] ;; model
8949 /* The s390 memory model is strong enough not to require any
8950 barrier in order to synchronize a thread with itself. */
8954 (define_expand "mem_thread_fence"
8955 [(match_operand:SI 0 "const_int_operand")] ;; model
8958 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8959 enough not to require barriers of any kind. */
8960 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
8962 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8963 MEM_VOLATILE_P (mem) = 1;
8964 emit_insn (gen_mem_thread_fence_1 (mem));
8969 ; Although bcr is superscalar on Z10, this variant will never
8970 ; become part of an execution group.
8971 (define_insn "mem_thread_fence_1"
8972 [(set (match_operand:BLK 0 "" "")
8973 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8976 [(set_attr "op_type" "RR")])
8979 ; atomic load/store operations
8982 ; Atomic loads need not examine the memory model at all.
8983 (define_expand "atomic_load<mode>"
8984 [(match_operand:DINT 0 "register_operand") ;; output
8985 (match_operand:DINT 1 "memory_operand") ;; memory
8986 (match_operand:SI 2 "const_int_operand")] ;; model
8989 if (<MODE>mode == TImode)
8990 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
8991 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8992 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
8994 emit_move_insn (operands[0], operands[1]);
8998 ; Different from movdi_31 in that we want no splitters.
8999 (define_insn "atomic_loaddi_1"
9000 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9001 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9009 [(set_attr "op_type" "RS,RSY,RS,RSY")
9010 (set_attr "type" "lm,lm,floaddf,floaddf")])
9012 (define_insn "atomic_loadti_1"
9013 [(set (match_operand:TI 0 "register_operand" "=r")
9014 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9018 [(set_attr "op_type" "RXY")
9019 (set_attr "type" "other")])
9021 ; Atomic stores must(?) enforce sequential consistency.
9022 (define_expand "atomic_store<mode>"
9023 [(match_operand:DINT 0 "memory_operand") ;; memory
9024 (match_operand:DINT 1 "register_operand") ;; input
9025 (match_operand:SI 2 "const_int_operand")] ;; model
9028 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9030 if (<MODE>mode == TImode)
9031 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9032 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9033 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9035 emit_move_insn (operands[0], operands[1]);
9036 if (model == MEMMODEL_SEQ_CST)
9037 emit_insn (gen_mem_thread_fence (operands[2]));
9041 ; Different from movdi_31 in that we want no splitters.
9042 (define_insn "atomic_storedi_1"
9043 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9044 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9052 [(set_attr "op_type" "RS,RSY,RS,RSY")
9053 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9055 (define_insn "atomic_storeti_1"
9056 [(set (match_operand:TI 0 "memory_operand" "=RT")
9057 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9061 [(set_attr "op_type" "RXY")
9062 (set_attr "type" "other")])
9065 ; compare and swap patterns.
9068 (define_expand "atomic_compare_and_swap<mode>"
9069 [(match_operand:SI 0 "register_operand") ;; bool success output
9070 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9071 (match_operand:DGPR 2 "memory_operand") ;; memory
9072 (match_operand:DGPR 3 "register_operand") ;; expected intput
9073 (match_operand:DGPR 4 "register_operand") ;; newval intput
9074 (match_operand:SI 5 "const_int_operand") ;; is_weak
9075 (match_operand:SI 6 "const_int_operand") ;; success model
9076 (match_operand:SI 7 "const_int_operand")] ;; failure model
9079 rtx cc, cmp, output = operands[1];
9081 if (!register_operand (output, <MODE>mode))
9082 output = gen_reg_rtx (<MODE>mode);
9084 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9085 (output, operands[2], operands[3], operands[4]));
9087 /* We deliberately accept non-register operands in the predicate
9088 to ensure the write back to the output operand happens *before*
9089 the store-flags code below. This makes it easier for combine
9090 to merge the store-flags code with a potential test-and-branch
9091 pattern following (immediately!) afterwards. */
9092 if (output != operands[1])
9093 emit_move_insn (operands[1], output);
9095 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9096 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9097 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9101 (define_expand "atomic_compare_and_swap<mode>"
9102 [(match_operand:SI 0 "register_operand") ;; bool success output
9103 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9104 (match_operand:HQI 2 "memory_operand") ;; memory
9105 (match_operand:HQI 3 "general_operand") ;; expected intput
9106 (match_operand:HQI 4 "general_operand") ;; newval intput
9107 (match_operand:SI 5 "const_int_operand") ;; is_weak
9108 (match_operand:SI 6 "const_int_operand") ;; success model
9109 (match_operand:SI 7 "const_int_operand")] ;; failure model
9112 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9113 operands[3], operands[4], INTVAL (operands[5]));
9117 (define_expand "atomic_compare_and_swap<mode>_internal"
9119 [(set (match_operand:DGPR 0 "register_operand")
9120 (match_operand:DGPR 1 "memory_operand"))
9122 (unspec_volatile:DGPR
9124 (match_operand:DGPR 2 "register_operand")
9125 (match_operand:DGPR 3 "register_operand")]
9127 (set (reg:CCZ1 CC_REGNUM)
9128 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9132 (define_insn "*atomic_compare_and_swap<mode>_1"
9133 [(set (match_operand:TDI 0 "register_operand" "=r")
9134 (match_operand:TDI 1 "memory_operand" "+QS"))
9136 (unspec_volatile:TDI
9138 (match_operand:TDI 2 "register_operand" "0")
9139 (match_operand:TDI 3 "register_operand" "r")]
9141 (set (reg:CCZ1 CC_REGNUM)
9142 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9144 "c<td>sg\t%0,%3,%S1"
9145 [(set_attr "op_type" "RSY")
9146 (set_attr "type" "sem")])
9149 (define_insn "*atomic_compare_and_swapdi_2"
9150 [(set (match_operand:DI 0 "register_operand" "=r,r")
9151 (match_operand:DI 1 "memory_operand" "+Q,S"))
9155 (match_operand:DI 2 "register_operand" "0,0")
9156 (match_operand:DI 3 "register_operand" "r,r")]
9158 (set (reg:CCZ1 CC_REGNUM)
9159 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9164 [(set_attr "op_type" "RS,RSY")
9165 (set_attr "type" "sem")])
9168 (define_insn "*atomic_compare_and_swapsi_3"
9169 [(set (match_operand:SI 0 "register_operand" "=r,r")
9170 (match_operand:SI 1 "memory_operand" "+Q,S"))
9174 (match_operand:SI 2 "register_operand" "0,0")
9175 (match_operand:SI 3 "register_operand" "r,r")]
9177 (set (reg:CCZ1 CC_REGNUM)
9178 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9183 [(set_attr "op_type" "RS,RSY")
9184 (set_attr "type" "sem")])
9187 ; Other atomic instruction patterns.
9190 ; z196 load and add, xor, or and and instructions
9192 (define_expand "atomic_fetch_<atomic><mode>"
9193 [(match_operand:GPR 0 "register_operand") ;; val out
9195 (match_operand:GPR 1 "memory_operand") ;; memory
9196 (match_operand:GPR 2 "register_operand")) ;; val in
9197 (match_operand:SI 3 "const_int_operand")] ;; model
9200 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9201 (operands[0], operands[1], operands[2]));
9205 ; lan, lang, lao, laog, lax, laxg, laa, laag
9206 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9207 [(set (match_operand:GPR 0 "register_operand" "=d")
9208 (match_operand:GPR 1 "memory_operand" "+QS"))
9210 (unspec_volatile:GPR
9211 [(ATOMIC_Z196:GPR (match_dup 1)
9212 (match_operand:GPR 2 "general_operand" "d"))]
9214 (clobber (reg:CC CC_REGNUM))]
9216 "la<noxa><g>\t%0,%2,%1"
9217 [(set_attr "op_type" "RSY")
9218 (set_attr "type" "sem")])
9220 ;; For SImode and larger, the optabs.c code will do just fine in
9221 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9222 ;; better by expanding our own loop.
9224 (define_expand "atomic_<atomic><mode>"
9226 (match_operand:HQI 0 "memory_operand") ;; memory
9227 (match_operand:HQI 1 "general_operand")) ;; val in
9228 (match_operand:SI 2 "const_int_operand")] ;; model
9231 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9232 operands[1], false);
9236 (define_expand "atomic_fetch_<atomic><mode>"
9237 [(match_operand:HQI 0 "register_operand") ;; val out
9239 (match_operand:HQI 1 "memory_operand") ;; memory
9240 (match_operand:HQI 2 "general_operand")) ;; val in
9241 (match_operand:SI 3 "const_int_operand")] ;; model
9244 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9245 operands[2], false);
9249 (define_expand "atomic_<atomic>_fetch<mode>"
9250 [(match_operand:HQI 0 "register_operand") ;; val out
9252 (match_operand:HQI 1 "memory_operand") ;; memory
9253 (match_operand:HQI 2 "general_operand")) ;; val in
9254 (match_operand:SI 3 "const_int_operand")] ;; model
9257 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9262 (define_expand "atomic_exchange<mode>"
9263 [(match_operand:HQI 0 "register_operand") ;; val out
9264 (match_operand:HQI 1 "memory_operand") ;; memory
9265 (match_operand:HQI 2 "general_operand") ;; val in
9266 (match_operand:SI 3 "const_int_operand")] ;; model
9269 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9270 operands[2], false);
9275 ;;- Miscellaneous instructions.
9279 ; allocate stack instruction pattern(s).
9282 (define_expand "allocate_stack"
9283 [(match_operand 0 "general_operand" "")
9284 (match_operand 1 "general_operand" "")]
9287 rtx temp = gen_reg_rtx (Pmode);
9289 emit_move_insn (temp, s390_back_chain_rtx ());
9290 anti_adjust_stack (operands[1]);
9291 emit_move_insn (s390_back_chain_rtx (), temp);
9293 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9299 ; setjmp instruction pattern.
9302 (define_expand "builtin_setjmp_receiver"
9303 [(match_operand 0 "" "")]
9306 emit_insn (s390_load_got ());
9307 emit_use (pic_offset_table_rtx);
9311 ;; These patterns say how to save and restore the stack pointer. We need not
9312 ;; save the stack pointer at function level since we are careful to
9313 ;; preserve the backchain. At block level, we have to restore the backchain
9314 ;; when we restore the stack pointer.
9316 ;; For nonlocal gotos, we must save both the stack pointer and its
9317 ;; backchain and restore both. Note that in the nonlocal case, the
9318 ;; save area is a memory location.
9320 (define_expand "save_stack_function"
9321 [(match_operand 0 "general_operand" "")
9322 (match_operand 1 "general_operand" "")]
9326 (define_expand "restore_stack_function"
9327 [(match_operand 0 "general_operand" "")
9328 (match_operand 1 "general_operand" "")]
9332 (define_expand "restore_stack_block"
9333 [(match_operand 0 "register_operand" "")
9334 (match_operand 1 "register_operand" "")]
9337 rtx temp = gen_reg_rtx (Pmode);
9339 emit_move_insn (temp, s390_back_chain_rtx ());
9340 emit_move_insn (operands[0], operands[1]);
9341 emit_move_insn (s390_back_chain_rtx (), temp);
9346 (define_expand "save_stack_nonlocal"
9347 [(match_operand 0 "memory_operand" "")
9348 (match_operand 1 "register_operand" "")]
9351 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9353 /* Copy the backchain to the first word, sp to the second and the
9354 literal pool base to the third. */
9356 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9357 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9358 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9360 if (TARGET_BACKCHAIN)
9361 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9363 emit_move_insn (save_sp, operands[1]);
9364 emit_move_insn (save_bp, base);
9369 (define_expand "restore_stack_nonlocal"
9370 [(match_operand 0 "register_operand" "")
9371 (match_operand 1 "memory_operand" "")]
9374 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9375 rtx temp = NULL_RTX;
9377 /* Restore the backchain from the first word, sp from the second and the
9378 literal pool base from the third. */
9380 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9381 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9382 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9384 if (TARGET_BACKCHAIN)
9385 temp = force_reg (Pmode, save_bc);
9387 emit_move_insn (base, save_bp);
9388 emit_move_insn (operands[0], save_sp);
9391 emit_move_insn (s390_back_chain_rtx (), temp);
9397 (define_expand "exception_receiver"
9401 s390_set_has_landing_pad_p (true);
9406 ; nop instruction pattern(s).
9413 [(set_attr "op_type" "RR")
9414 (set_attr "z10prop" "z10_fr_E1")])
9420 [(set_attr "op_type" "RR")])
9424 ; Special literal pool access instruction pattern(s).
9427 (define_insn "*pool_entry"
9428 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9429 UNSPECV_POOL_ENTRY)]
9432 enum machine_mode mode = GET_MODE (PATTERN (insn));
9433 unsigned int align = GET_MODE_BITSIZE (mode);
9434 s390_output_pool_entry (operands[0], mode, align);
9437 [(set (attr "length")
9438 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9440 (define_insn "pool_align"
9441 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9442 UNSPECV_POOL_ALIGN)]
9445 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9447 (define_insn "pool_section_start"
9448 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9451 [(set_attr "length" "0")])
9453 (define_insn "pool_section_end"
9454 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9457 [(set_attr "length" "0")])
9459 (define_insn "main_base_31_small"
9460 [(set (match_operand 0 "register_operand" "=a")
9461 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9462 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9464 [(set_attr "op_type" "RR")
9465 (set_attr "type" "la")
9466 (set_attr "z196prop" "z196_cracked")])
9468 (define_insn "main_base_31_large"
9469 [(set (match_operand 0 "register_operand" "=a")
9470 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9471 (set (pc) (label_ref (match_operand 2 "" "")))]
9472 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9474 [(set_attr "op_type" "RI")
9475 (set_attr "z196prop" "z196_cracked")])
9477 (define_insn "main_base_64"
9478 [(set (match_operand 0 "register_operand" "=a")
9479 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9480 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9482 [(set_attr "op_type" "RIL")
9483 (set_attr "type" "larl")
9484 (set_attr "z10prop" "z10_fwd_A1")])
9486 (define_insn "main_pool"
9487 [(set (match_operand 0 "register_operand" "=a")
9488 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9489 "GET_MODE (operands[0]) == Pmode"
9494 (if_then_else (match_test "TARGET_CPU_ZARCH")
9495 (const_string "larl") (const_string "la")))])
9497 (define_insn "reload_base_31"
9498 [(set (match_operand 0 "register_operand" "=a")
9499 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9500 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9501 "basr\t%0,0\;la\t%0,%1-.(%0)"
9502 [(set_attr "length" "6")
9503 (set_attr "type" "la")
9504 (set_attr "z196prop" "z196_cracked")])
9506 (define_insn "reload_base_64"
9507 [(set (match_operand 0 "register_operand" "=a")
9508 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9509 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9511 [(set_attr "op_type" "RIL")
9512 (set_attr "type" "larl")
9513 (set_attr "z10prop" "z10_fwd_A1")])
9516 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9521 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9524 ;; Insns related to generating the function prologue and epilogue.
9528 (define_expand "prologue"
9529 [(use (const_int 0))]
9531 "s390_emit_prologue (); DONE;")
9533 (define_expand "epilogue"
9534 [(use (const_int 1))]
9536 "s390_emit_epilogue (false); DONE;")
9538 (define_expand "sibcall_epilogue"
9539 [(use (const_int 0))]
9541 "s390_emit_epilogue (true); DONE;")
9543 (define_insn "*return"
9545 (use (match_operand 0 "register_operand" "a"))]
9546 "GET_MODE (operands[0]) == Pmode"
9548 [(set_attr "op_type" "RR")
9549 (set_attr "type" "jsr")
9550 (set_attr "atype" "agen")])
9553 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9554 ;; pointer. This is used for compatibility.
9556 (define_expand "ptr_extend"
9557 [(set (match_operand:DI 0 "register_operand" "=r")
9558 (match_operand:SI 1 "register_operand" "r"))]
9561 emit_insn (gen_anddi3 (operands[0],
9562 gen_lowpart (DImode, operands[1]),
9563 GEN_INT (0x7fffffff)));
9567 ;; Instruction definition to expand eh_return macro to support
9568 ;; swapping in special linkage return addresses.
9570 (define_expand "eh_return"
9571 [(use (match_operand 0 "register_operand" ""))]
9574 s390_emit_tpf_eh_return (operands[0]);
9579 ; Stack Protector Patterns
9582 (define_expand "stack_protect_set"
9583 [(set (match_operand 0 "memory_operand" "")
9584 (match_operand 1 "memory_operand" ""))]
9587 #ifdef TARGET_THREAD_SSP_OFFSET
9589 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9590 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9593 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9595 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9600 (define_insn "stack_protect_set<mode>"
9601 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9602 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9604 "mvc\t%O0(%G0,%R0),%S1"
9605 [(set_attr "op_type" "SS")])
9607 (define_expand "stack_protect_test"
9608 [(set (reg:CC CC_REGNUM)
9609 (compare (match_operand 0 "memory_operand" "")
9610 (match_operand 1 "memory_operand" "")))
9611 (match_operand 2 "" "")]
9615 #ifdef TARGET_THREAD_SSP_OFFSET
9617 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9618 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9621 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9623 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9625 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9626 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9627 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9631 (define_insn "stack_protect_test<mode>"
9632 [(set (reg:CCZ CC_REGNUM)
9633 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9634 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9636 "clc\t%O0(%G0,%R0),%S1"
9637 [(set_attr "op_type" "SS")])
9639 ; This is used in s390_emit_prologue in order to prevent insns
9640 ; adjusting the stack pointer to be moved over insns writing stack
9641 ; slots using a copy of the stack pointer in a different register.
9642 (define_insn "stack_tie"
9643 [(set (match_operand:BLK 0 "memory_operand" "+m")
9644 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9647 [(set_attr "length" "0")])
9651 ; Data prefetch patterns
9654 (define_insn "prefetch"
9655 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9656 (match_operand:SI 1 "const_int_operand" " n,n")
9657 (match_operand:SI 2 "const_int_operand" " n,n"))]
9660 switch (which_alternative)
9663 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9665 if (larl_operand (operands[0], Pmode))
9666 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9669 /* This might be reached for symbolic operands with an odd
9670 addend. We simply omit the prefetch for such rare cases. */
9675 [(set_attr "type" "load,larl")
9676 (set_attr "op_type" "RXY,RIL")
9677 (set_attr "z10prop" "z10_super")
9678 (set_attr "z196prop" "z196_alone")])
9682 ; Byte swap instructions
9685 (define_insn "bswap<mode>2"
9686 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9687 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9692 [(set_attr "type" "*,load")
9693 (set_attr "op_type" "RRE,RXY")
9694 (set_attr "z10prop" "z10_super")])
9698 ; Population count instruction
9701 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9702 ; portions and stores the result in the corresponding bytes in op0.
9703 (define_insn "*popcount<mode>"
9704 [(set (match_operand:INT 0 "register_operand" "=d")
9705 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9706 (clobber (reg:CC CC_REGNUM))]
9709 [(set_attr "op_type" "RRE")])
9711 (define_expand "popcountdi2"
9713 (parallel [(set (match_operand:DI 0 "register_operand" "")
9714 (unspec:DI [(match_operand:DI 1 "register_operand")]
9716 (clobber (reg:CC CC_REGNUM))])
9718 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9720 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9721 (clobber (reg:CC CC_REGNUM))])
9724 (ashift:DI (match_dup 0) (const_int 16)))
9726 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9727 (clobber (reg:CC CC_REGNUM))])
9729 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9731 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9732 (clobber (reg:CC CC_REGNUM))])
9734 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9735 "TARGET_Z196 && TARGET_64BIT"
9736 "operands[2] = gen_reg_rtx (DImode);")
9738 (define_expand "popcountsi2"
9740 (parallel [(set (match_operand:SI 0 "register_operand" "")
9741 (unspec:SI [(match_operand:SI 1 "register_operand")]
9743 (clobber (reg:CC CC_REGNUM))])
9746 (ashift:SI (match_dup 0) (const_int 16)))
9748 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9749 (clobber (reg:CC CC_REGNUM))])
9751 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9753 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9754 (clobber (reg:CC CC_REGNUM))])
9756 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9758 "operands[2] = gen_reg_rtx (SImode);")
9760 (define_expand "popcounthi2"
9762 (parallel [(set (match_operand:HI 0 "register_operand" "")
9763 (unspec:HI [(match_operand:HI 1 "register_operand")]
9765 (clobber (reg:CC CC_REGNUM))])
9768 (ashift:SI (match_dup 0) (const_int 8)))
9770 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9771 (clobber (reg:CC CC_REGNUM))])
9773 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9775 "operands[2] = gen_reg_rtx (SImode);")
9777 (define_expand "popcountqi2"
9779 (parallel [(set (match_operand:QI 0 "register_operand" "")
9780 (unspec:QI [(match_operand:QI 1 "register_operand")]
9782 (clobber (reg:CC CC_REGNUM))])]
9787 ;;- Copy sign instructions
9790 (define_insn "copysign<mode>3"
9791 [(set (match_operand:FP 0 "register_operand" "=f")
9792 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9793 (match_operand:FP 2 "register_operand" "f")]
9797 [(set_attr "op_type" "RRF")
9798 (set_attr "type" "fsimp<mode>")])