gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999-2017 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com) and
   5 ;;                 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify it under
  10 ;; the terms of the GNU General Public License as published by the Free
  11 ;; Software Foundation; either version 3, or (at your option) any later
  12 ;; version.
  13
  14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 ;; for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;;
  24 ;; See constraints.md for a description of constraints specific to s390.
  25 ;;
  26
  27 ;; Special formats used for outputting 390 instructions.
  28 ;;
  29 ;;     %C: print opcode suffix for branch condition.
  30 ;;     %D: print opcode suffix for inverse branch condition.
  31 ;;     %J: print tls_load/tls_gdcall/tls_ldcall suffix
  32 ;;     %G: print the size of the operand in bytes.
  33 ;;     %O: print only the displacement of a memory reference.
  34 ;;     %R: print only the base register of a memory reference.
  35 ;;     %S: print S-type memory reference (base+displacement).
  36 ;;     %N: print the second word of a DImode operand.
  37 ;;     %M: print the second word of a TImode operand.
  38 ;;     %Y: print shift count operand.
  39 ;;
  40 ;;     %b: print integer X as if it's an unsigned byte.
  41 ;;     %c: print integer X as if it's an signed byte.
  42 ;;     %x: print integer X as if it's an unsigned halfword.
  43 ;;     %h: print integer X as if it's a signed halfword.
  44 ;;     %i: print the first nonzero HImode part of X.
  45 ;;     %j: print the first HImode part unequal to -1 of X.
  46 ;;     %k: print the first nonzero SImode part of X.
  47 ;;     %m: print the first SImode part unequal to -1 of X.
  48 ;;     %o: print integer X as if it's an unsigned 32bit word.
  49 ;;
  50 ;; We have a special constraint for pattern matching.
  51 ;;
  52 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  53 ;;
  54
  55 ;;
  56 ;; UNSPEC usage
  57 ;;
  58
  59 (define_c_enum "unspec" [
  60    ; Miscellaneous
  61    UNSPEC_ROUND
  62    UNSPEC_ICM
  63    UNSPEC_TIE
  64
  65    ; Convert CC into a str comparison result and copy it into an
  66    ; integer register
  67    ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
  68    UNSPEC_STRCMPCC_TO_INT
  69
  70    ; Copy CC as is into the lower 2 bits of an integer register
  71    UNSPEC_CC_TO_INT
  72
  73    ; The right hand side of an setmem
  74    UNSPEC_REPLICATE_BYTE
  75
  76    ; GOT/PLT and lt-relative accesses
  77    UNSPEC_LTREL_OFFSET
  78    UNSPEC_LTREL_BASE
  79    UNSPEC_POOL_OFFSET
  80    UNSPEC_GOTENT
  81    UNSPEC_GOT
  82    UNSPEC_GOTOFF
  83    UNSPEC_PLT
  84    UNSPEC_PLTOFF
  85
  86    ; Literal pool
  87    UNSPEC_RELOAD_BASE
  88    UNSPEC_MAIN_BASE
  89    UNSPEC_LTREF
  90    UNSPEC_INSN
  91    UNSPEC_EXECUTE
  92
  93    ; Atomic Support
  94    UNSPEC_MB
  95    UNSPEC_MOVA
  96
  97    ; TLS relocation specifiers
  98    UNSPEC_TLSGD
  99    UNSPEC_TLSLDM
 100    UNSPEC_NTPOFF
 101    UNSPEC_DTPOFF
 102    UNSPEC_GOTNTPOFF
 103    UNSPEC_INDNTPOFF
 104
 105    ; TLS support
 106    UNSPEC_TLSLDM_NTPOFF
 107    UNSPEC_TLS_LOAD
 108
 109    ; String Functions
 110    UNSPEC_SRST
 111    UNSPEC_MVST
 112
 113    ; Stack Smashing Protector
 114    UNSPEC_SP_SET
 115    UNSPEC_SP_TEST
 116
 117    ; Split stack support
 118    UNSPEC_STACK_CHECK
 119
 120    ; Test Data Class (TDC)
 121    UNSPEC_TDC_INSN
 122
 123    ; Population Count
 124    UNSPEC_POPCNT
 125    UNSPEC_COPYSIGN
 126
 127    ; Load FP Integer
 128    UNSPEC_FPINT_FLOOR
 129    UNSPEC_FPINT_BTRUNC
 130    UNSPEC_FPINT_ROUND
 131    UNSPEC_FPINT_CEIL
 132    UNSPEC_FPINT_NEARBYINT
 133    UNSPEC_FPINT_RINT
 134
 135    UNSPEC_LCBB
 136
 137    ; Vector
 138    UNSPEC_VEC_SMULT_HI
 139    UNSPEC_VEC_UMULT_HI
 140    UNSPEC_VEC_SMULT_LO
 141    UNSPEC_VEC_SMULT_EVEN
 142    UNSPEC_VEC_UMULT_EVEN
 143    UNSPEC_VEC_SMULT_ODD
 144    UNSPEC_VEC_UMULT_ODD
 145
 146    UNSPEC_VEC_VMAL
 147    UNSPEC_VEC_VMAH
 148    UNSPEC_VEC_VMALH
 149    UNSPEC_VEC_VMAE
 150    UNSPEC_VEC_VMALE
 151    UNSPEC_VEC_VMAO
 152    UNSPEC_VEC_VMALO
 153
 154    UNSPEC_VEC_GATHER
 155    UNSPEC_VEC_EXTRACT
 156    UNSPEC_VEC_INSERT_AND_ZERO
 157    UNSPEC_VEC_LOAD_BNDRY
 158    UNSPEC_VEC_LOAD_LEN
 159    UNSPEC_VEC_MERGEH
 160    UNSPEC_VEC_MERGEL
 161    UNSPEC_VEC_PACK
 162    UNSPEC_VEC_PACK_SATURATE
 163    UNSPEC_VEC_PACK_SATURATE_CC
 164    UNSPEC_VEC_PACK_SATURATE_GENCC
 165    UNSPEC_VEC_PACK_UNSIGNED_SATURATE
 166    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
 167    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
 168    UNSPEC_VEC_PERM
 169    UNSPEC_VEC_PERMI
 170    UNSPEC_VEC_EXTEND
 171    UNSPEC_VEC_STORE_LEN
 172    UNSPEC_VEC_UNPACKH
 173    UNSPEC_VEC_UNPACKH_L
 174    UNSPEC_VEC_UNPACKL
 175    UNSPEC_VEC_UNPACKL_L
 176    UNSPEC_VEC_ADDC
 177    UNSPEC_VEC_ADDE_U128
 178    UNSPEC_VEC_ADDEC_U128
 179    UNSPEC_VEC_AVG
 180    UNSPEC_VEC_AVGU
 181    UNSPEC_VEC_CHECKSUM
 182    UNSPEC_VEC_GFMSUM
 183    UNSPEC_VEC_GFMSUM_128
 184    UNSPEC_VEC_GFMSUM_ACCUM
 185    UNSPEC_VEC_GFMSUM_ACCUM_128
 186    UNSPEC_VEC_SET
 187
 188    UNSPEC_VEC_VSUMG
 189    UNSPEC_VEC_VSUMQ
 190    UNSPEC_VEC_VSUM
 191    UNSPEC_VEC_RL_MASK
 192    UNSPEC_VEC_SLL
 193    UNSPEC_VEC_SLB
 194    UNSPEC_VEC_SLDB
 195    UNSPEC_VEC_SRAL
 196    UNSPEC_VEC_SRAB
 197    UNSPEC_VEC_SRL
 198    UNSPEC_VEC_SRLB
 199
 200    UNSPEC_VEC_SUBC
 201    UNSPEC_VEC_SUBE_U128
 202    UNSPEC_VEC_SUBEC_U128
 203
 204    UNSPEC_VEC_TEST_MASK
 205
 206    UNSPEC_VEC_VFAE
 207    UNSPEC_VEC_VFAECC
 208
 209    UNSPEC_VEC_VFEE
 210    UNSPEC_VEC_VFEECC
 211    UNSPEC_VEC_VFENE
 212    UNSPEC_VEC_VFENECC
 213
 214    UNSPEC_VEC_VISTR
 215    UNSPEC_VEC_VISTRCC
 216
 217    UNSPEC_VEC_VSTRC
 218    UNSPEC_VEC_VSTRCCC
 219
 220    UNSPEC_VEC_VCDGB
 221    UNSPEC_VEC_VCDLGB
 222
 223    UNSPEC_VEC_VCGDB
 224    UNSPEC_VEC_VCLGDB
 225
 226    UNSPEC_VEC_VFIDB
 227
 228    UNSPEC_VEC_VLDEB
 229    UNSPEC_VEC_VLEDB
 230
 231    UNSPEC_VEC_VFTCIDB
 232    UNSPEC_VEC_VFTCIDBCC
 233 ])
 234
 235 ;;
 236 ;; UNSPEC_VOLATILE usage
 237 ;;
 238
 239 (define_c_enum "unspecv" [
 240    ; Blockage
 241    UNSPECV_BLOCKAGE
 242
 243    ; TPF Support
 244    UNSPECV_TPF_PROLOGUE
 245    UNSPECV_TPF_EPILOGUE
 246
 247    ; Literal pool
 248    UNSPECV_POOL
 249    UNSPECV_POOL_SECTION
 250    UNSPECV_POOL_ALIGN
 251    UNSPECV_POOL_ENTRY
 252    UNSPECV_MAIN_POOL
 253
 254    ; TLS support
 255    UNSPECV_SET_TP
 256
 257    ; Atomic Support
 258    UNSPECV_CAS
 259    UNSPECV_ATOMIC_OP
 260
 261    ; Hotpatching (unremovable NOPs)
 262    UNSPECV_NOP_2_BYTE
 263    UNSPECV_NOP_4_BYTE
 264    UNSPECV_NOP_6_BYTE
 265
 266    ; Transactional Execution support
 267    UNSPECV_TBEGIN
 268    UNSPECV_TBEGIN_TDB
 269    UNSPECV_TBEGINC
 270    UNSPECV_TEND
 271    UNSPECV_TABORT
 272    UNSPECV_ETND
 273    UNSPECV_NTSTG
 274    UNSPECV_PPA
 275
 276    ; Set and get floating point control register
 277    UNSPECV_SFPC
 278    UNSPECV_EFPC
 279
 280    ; Split stack support
 281    UNSPECV_SPLIT_STACK_CALL
 282    UNSPECV_SPLIT_STACK_DATA
 283
 284    UNSPECV_OSC_BREAK
 285   ])
 286
 287 ;;
 288 ;; Registers
 289 ;;
 290
 291 ; Registers with special meaning
 292
 293 (define_constants
 294   [
 295    ; Sibling call register.
 296    (SIBCALL_REGNUM               1)
 297    ; Literal pool base register.
 298    (BASE_REGNUM                 13)
 299    ; Return address register.
 300    (RETURN_REGNUM               14)
 301    ; Stack pointer register.
 302    (STACK_REGNUM                15)
 303    ; Condition code register.
 304    (CC_REGNUM                   33)
 305    ; Thread local storage pointer register.
 306    (TP_REGNUM                   36)
 307   ])
 308
 309 ; Hardware register names
 310
 311 (define_constants
 312   [
 313    ; General purpose registers
 314    (GPR0_REGNUM                  0)
 315    (GPR1_REGNUM                  1)
 316    (GPR2_REGNUM                  2)
 317    (GPR6_REGNUM                  6)
 318    ; Floating point registers.
 319    (FPR0_REGNUM                 16)
 320    (FPR1_REGNUM                 20)
 321    (FPR2_REGNUM                 17)
 322    (FPR3_REGNUM                 21)
 323    (FPR4_REGNUM                 18)
 324    (FPR5_REGNUM                 22)
 325    (FPR6_REGNUM                 19)
 326    (FPR7_REGNUM                 23)
 327    (FPR8_REGNUM                 24)
 328    (FPR9_REGNUM                 28)
 329    (FPR10_REGNUM                25)
 330    (FPR11_REGNUM                29)
 331    (FPR12_REGNUM                26)
 332    (FPR13_REGNUM                30)
 333    (FPR14_REGNUM                27)
 334    (FPR15_REGNUM                31)
 335    (VR0_REGNUM                  16)
 336    (VR16_REGNUM                 38)
 337    (VR23_REGNUM                 45)
 338    (VR24_REGNUM                 46)
 339    (VR31_REGNUM                 53)
 340   ])
 341
 342 ; Rounding modes for binary floating point numbers
 343 (define_constants
 344   [(BFP_RND_CURRENT                 0)
 345    (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
 346    (BFP_RND_PREP_FOR_SHORT_PREC     3)
 347    (BFP_RND_NEAREST_TIE_TO_EVEN     4)
 348    (BFP_RND_TOWARD_0                5)
 349    (BFP_RND_TOWARD_INF              6)
 350    (BFP_RND_TOWARD_MINF             7)])
 351
 352 ; Rounding modes for decimal floating point numbers
 353 ; 1-7 were introduced with the floating point extension facility
 354 ; available with z196
 355 ; With these rounding modes (1-7) a quantum exception might occur
 356 ; which is suppressed for the other modes.
 357 (define_constants
 358   [(DFP_RND_CURRENT                          0)
 359    (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
 360    (DFP_RND_CURRENT_QUANTEXC                 2)
 361    (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC     3)
 362    (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC     4)
 363    (DFP_RND_TOWARD_0_QUANTEXC                5)
 364    (DFP_RND_TOWARD_INF_QUANTEXC              6)
 365    (DFP_RND_TOWARD_MINF_QUANTEXC             7)
 366    (DFP_RND_NEAREST_TIE_TO_EVEN              8)
 367    (DFP_RND_TOWARD_0                         9)
 368    (DFP_RND_TOWARD_INF                      10)
 369    (DFP_RND_TOWARD_MINF                     11)
 370    (DFP_RND_NEAREST_TIE_AWAY_FROM_0         12)
 371    (DFP_RND_NEAREST_TIE_TO_0                13)
 372    (DFP_RND_AWAY_FROM_0                     14)
 373    (DFP_RND_PREP_FOR_SHORT_PREC             15)])
 374
 375 ;;
 376 ;; PFPO GPR0 argument format
 377 ;;
 378
 379 (define_constants
 380   [
 381    ; PFPO operation type
 382    (PFPO_CONVERT          0x1000000)
 383    ; PFPO operand types
 384    (PFPO_OP_TYPE_SF             0x5)
 385    (PFPO_OP_TYPE_DF             0x6)
 386    (PFPO_OP_TYPE_TF             0x7)
 387    (PFPO_OP_TYPE_SD             0x8)
 388    (PFPO_OP_TYPE_DD             0x9)
 389    (PFPO_OP_TYPE_TD             0xa)
 390    ; Bitposition of operand types
 391    (PFPO_OP0_TYPE_SHIFT          16)
 392    (PFPO_OP1_TYPE_SHIFT           8)
 393   ])
 394
 395 ; Immediate operands for tbegin and tbeginc
 396 (define_constants [(TBEGIN_MASK  65292)]) ; 0xff0c
 397 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
 398
 399 ;; Instruction operand type as used in the Principles of Operation.
 400 ;; Used to determine defaults for length and other attribute values.
 401
 402 (define_attr "op_type"
 403   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
 404   (const_string "NN"))
 405
 406 ;; Instruction type attribute used for scheduling.
 407
 408 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
 409                      cs,vs,store,sem,idiv,
 410                      imulhi,imulsi,imuldi,
 411                      branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
 412                      floadtf,floaddf,floadsf,fstoredf,fstoresf,
 413                      fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
 414                      ftoi,fsqrttf,fsqrtdf,fsqrtsf,
 415                      fmadddf,fmaddsf,
 416                      ftrunctf,ftruncdf, ftruncsd, ftruncdd,
 417                      itoftf, itofdf, itofsf, itofdd, itoftd,
 418                      fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
 419                      fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
 420                      ftoidfp, other"
 421   (cond [(eq_attr "op_type" "NN")  (const_string "other")
 422          (eq_attr "op_type" "SS")  (const_string "cs")]
 423     (const_string "integer")))
 424
 425 ;; Another attribute used for scheduling purposes:
 426 ;;   agen: Instruction uses the address generation unit
 427 ;;   reg: Instruction does not use the agen unit
 428
 429 (define_attr "atype" "agen,reg"
 430   (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
 431                 (const_string "reg")
 432                 (const_string "agen")))
 433
 434 ;; Properties concerning Z10 execution grouping and value forwarding.
 435 ;; z10_super: instruction is superscalar.
 436 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
 437 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
 438 ;;   target register.  It can forward this value to a second instruction that reads
 439 ;;   the same register if that second instruction is issued in the same group.
 440 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
 441 ;;   instruction in the S pipe writes to the register, then the T instruction
 442 ;;   can immediately read the new value.
 443 ;; z10_fr: union of Z10_fwd and z10_rec.
 444 ;; z10_c: second operand of instruction is a register and read with complemented bits.
 445 ;;
 446 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
 447
 448
 449 (define_attr "z10prop" "none,
 450                         z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
 451                         z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
 452                         z10_rec,
 453                         z10_fr, z10_fr_A3, z10_fr_E1,
 454                         z10_c"
 455              (const_string "none"))
 456
 457 ;; Properties concerning Z196 decoding
 458 ;; z196_alone: must group alone
 459 ;; z196_end: ends a group
 460 ;; z196_cracked: instruction is cracked or expanded
 461 (define_attr "z196prop" "none,
 462                          z196_alone, z196_ends,
 463                          z196_cracked"
 464              (const_string "none"))
 465
 466 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
 467
 468 ;; Length in bytes.
 469
 470 (define_attr "length" ""
 471   (cond [(eq_attr "op_type" "E,RR")                       (const_int 2)
 472          (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF")  (const_int 4)]
 473     (const_int 6)))
 474
 475
 476 ;; Processor type.  This attribute must exactly match the processor_type
 477 ;; enumeration in s390.h.  The current machine description does not
 478 ;; distinguish between g5 and g6, but there are differences between the two
 479 ;; CPUs could in theory be modeled.
 480
 481 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,arch12"
 482   (const (symbol_ref "s390_tune_attr")))
 483
 484 (define_attr "cpu_facility"
 485   "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,arch12,vxe"
 486   (const_string "standard"))
 487
 488 (define_attr "enabled" ""
 489   (cond [(eq_attr "cpu_facility" "standard")
 490          (const_int 1)
 491
 492          (and (eq_attr "cpu_facility" "ieee")
 493               (match_test "TARGET_CPU_IEEE_FLOAT"))
 494          (const_int 1)
 495
 496          (and (eq_attr "cpu_facility" "zarch")
 497               (match_test "TARGET_ZARCH"))
 498          (const_int 1)
 499
 500          (and (eq_attr "cpu_facility" "longdisp")
 501               (match_test "TARGET_LONG_DISPLACEMENT"))
 502          (const_int 1)
 503
 504          (and (eq_attr "cpu_facility" "extimm")
 505               (match_test "TARGET_EXTIMM"))
 506          (const_int 1)
 507
 508          (and (eq_attr "cpu_facility" "dfp")
 509               (match_test "TARGET_DFP"))
 510          (const_int 1)
 511
 512          (and (eq_attr "cpu_facility" "cpu_zarch")
 513               (match_test "TARGET_CPU_ZARCH"))
 514          (const_int 1)
 515
 516          (and (eq_attr "cpu_facility" "z10")
 517               (match_test "TARGET_Z10"))
 518          (const_int 1)
 519
 520          (and (eq_attr "cpu_facility" "z196")
 521               (match_test "TARGET_Z196"))
 522          (const_int 1)
 523
 524          (and (eq_attr "cpu_facility" "zEC12")
 525               (match_test "TARGET_ZEC12"))
 526          (const_int 1)
 527
 528          (and (eq_attr "cpu_facility" "vx")
 529               (match_test "TARGET_VX"))
 530          (const_int 1)
 531
 532          (and (eq_attr "cpu_facility" "z13")
 533               (match_test "TARGET_Z13"))
 534          (const_int 1)
 535
 536          (and (eq_attr "cpu_facility" "arch12")
 537               (match_test "TARGET_ARCH12"))
 538          (const_int 1)
 539
 540          (and (eq_attr "cpu_facility" "vxe")
 541               (match_test "TARGET_VXE"))
 542          (const_int 1)
 543          ]
 544         (const_int 0)))
 545
 546 ;; Pipeline description for z900.  For lack of anything better,
 547 ;; this description is also used for the g5 and g6.
 548 (include "2064.md")
 549
 550 ;; Pipeline description for z990, z9-109 and z9-ec.
 551 (include "2084.md")
 552
 553 ;; Pipeline description for z10
 554 (include "2097.md")
 555
 556 ;; Pipeline description for z196
 557 (include "2817.md")
 558
 559 ;; Pipeline description for zEC12
 560 (include "2827.md")
 561
 562 ;; Pipeline description for z13
 563 (include "2964.md")
 564
 565 ;; Predicates
 566 (include "predicates.md")
 567
 568 ;; Constraint definitions
 569 (include "constraints.md")
 570
 571 ;; Other includes
 572 (include "tpf.md")
 573
 574 ;; Iterators
 575
 576 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
 577
 578 ;; These mode iterators allow floating point patterns to be generated from the
 579 ;; same template.
 580 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
 581                               (SD "TARGET_HARD_DFP")])
 582 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
 583 (define_mode_iterator BFP [TF DF SF])
 584 (define_mode_iterator DFP [TD DD])
 585 (define_mode_iterator DFP_ALL [TD DD SD])
 586 (define_mode_iterator DSF [DF SF])
 587 (define_mode_iterator SD_SF [SF SD])
 588 (define_mode_iterator DD_DF [DF DD])
 589 (define_mode_iterator TD_TF [TF TD])
 590
 591 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
 592 ;; from the same template.
 593 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
 594 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
 595 (define_mode_iterator DSI [DI SI])
 596 (define_mode_iterator TDI [TI DI])
 597
 598 ;; These mode iterators allow :P to be used for patterns that operate on
 599 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 600 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
 601
 602 ;; These macros refer to the actual word_mode of the configuration.
 603 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
 604 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
 605 (define_mode_iterator W  [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
 606
 607 ;; Used by the umul pattern to express modes having half the size.
 608 (define_mode_attr DWH [(TI "DI") (DI "SI")])
 609 (define_mode_attr dwh [(TI "di") (DI "si")])
 610
 611 ;; This mode iterator allows the QI and HI patterns to be defined from
 612 ;; the same template.
 613 (define_mode_iterator HQI [HI QI])
 614
 615 ;; This mode iterator allows the integer patterns to be defined from the
 616 ;; same template.
 617 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
 618 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
 619 (define_mode_iterator SINT [SI HI QI])
 620
 621 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
 622 ;; the same template.
 623 (define_code_iterator SHIFT [ashift lshiftrt])
 624
 625 ;; This iterator allows r[ox]sbg to be defined with the same template
 626 (define_code_iterator IXOR [ior xor])
 627
 628 ;; This iterator is used to expand the patterns for the nearest
 629 ;; integer functions.
 630 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
 631                             UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
 632                             UNSPEC_FPINT_NEARBYINT])
 633 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
 634                              (UNSPEC_FPINT_BTRUNC "btrunc")
 635                              (UNSPEC_FPINT_ROUND "round")
 636                              (UNSPEC_FPINT_CEIL "ceil")
 637                              (UNSPEC_FPINT_NEARBYINT "nearbyint")])
 638 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
 639                                      (UNSPEC_FPINT_BTRUNC "5")
 640                                      (UNSPEC_FPINT_ROUND "1")
 641                                      (UNSPEC_FPINT_CEIL "6")
 642                                      (UNSPEC_FPINT_NEARBYINT "0")])
 643
 644 ;; This iterator and attribute allow to combine most atomic operations.
 645 (define_code_iterator ATOMIC [and ior xor plus minus mult])
 646 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
 647 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
 648                           (plus "add") (minus "sub") (mult "nand")])
 649 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
 650
 651 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
 652 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
 653 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
 654
 655 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
 656 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
 657 ;; SDmode.
 658 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
 659
 660 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
 661 ;; Likewise for "<RXe>".
 662 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
 663 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 664
 665 ;; The decimal floating point variants of add, sub, div and mul support 3
 666 ;; fp register operands.  The following attributes allow to merge the bfp and
 667 ;; dfp variants in a single insn definition.
 668
 669 ;; These mode attributes are supposed to be used in the `enabled' insn
 670 ;; attribute to disable certain alternatives for certain modes.
 671 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
 672 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
 673 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
 674 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
 675                         (TD "0") (DD "0") (DD "0")
 676                         (TI "0") (DI "*") (SI "0")])
 677
 678 ;; This attribute is used in the operand constraint list
 679 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
 680 ;; TFmode values are represented by a fp register pair.  Since the
 681 ;; sign bit instructions only handle single source and target fp registers
 682 ;; these instructions can only be used for TFmode values if the source and
 683 ;; target operand uses the same fp register.
 684 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 685
 686 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 687 ;; within instruction mnemonics.
 688 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 689
 690 ;; This attribute is used within instruction mnemonics.  It evaluates to d for dfp
 691 ;; modes and to an empty string for bfp modes.
 692 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
 693
 694 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
 695 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
 696 ;; version only operates on one register.
 697 (define_mode_attr d0 [(DI "d") (SI "0")])
 698
 699 ;; In combination with d0 this allows to combine instructions of which the 31bit
 700 ;; version only operates on one register. The DImode version needs an additional
 701 ;; register for the assembler output.
 702 (define_mode_attr 1 [(DI "%1,") (SI "")])
 703
 704 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
 705 ;; 'ashift' and "srdl" in 'lshiftrt'.
 706 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
 707
 708 ;; In SHIFT templates, this attribute holds the correct standard name for the
 709 ;; pattern itself and the corresponding function calls.
 710 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
 711
 712 ;; This attribute handles differences in the instruction 'type' and will result
 713 ;; in "RRE" for DImode and "RR" for SImode.
 714 (define_mode_attr E [(DI "E") (SI "")])
 715
 716 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
 717 ;; to result in "RXY" for DImode and "RX" for SImode.
 718 (define_mode_attr Y [(DI "Y") (SI "")])
 719
 720 ;; This attribute handles differences in the instruction 'type' and will result
 721 ;; in "RSE" for TImode and "RS" for DImode.
 722 (define_mode_attr TE [(TI "E") (DI "")])
 723
 724 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
 725 ;; and "lcr" in SImode.
 726 (define_mode_attr g [(DI "g") (SI "")])
 727
 728 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
 729 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
 730 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
 731 ;; variant for long displacements.
 732 (define_mode_attr y [(DI "g") (SI "y")])
 733
 734 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
 735 ;; and "cds" in DImode.
 736 (define_mode_attr tg [(TI "g") (DI "")])
 737
 738 ;; In TDI templates, a string like "c<d>sg".
 739 (define_mode_attr td [(TI "d") (DI "")])
 740
 741 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
 742 ;; and "cfdbr" in SImode.
 743 (define_mode_attr gf [(DI "g") (SI "f")])
 744
 745 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
 746 ;; and sllk for SI.  This way it is possible to merge the new z196 SI
 747 ;; 3 operands shift instructions into the existing patterns.
 748 (define_mode_attr gk [(DI "g") (SI "k")])
 749
 750 ;; ICM mask required to load MODE value into the lowest subreg
 751 ;; of a SImode register.
 752 (define_mode_attr icm_lo [(HI "3") (QI "1")])
 753
 754 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
 755 ;; HImode and "llgc" in QImode.
 756 (define_mode_attr hc [(HI "h") (QI "c")])
 757
 758 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
 759 ;; in SImode.
 760 (define_mode_attr DBL [(DI "TI") (SI "DI")])
 761
 762 ;; This attribute expands to DF for TFmode and to DD for TDmode .  It is
 763 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
 764 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
 765
 766 ;; Maximum unsigned integer that fits in MODE.
 767 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 768
 769 ;; Start and end field computations for RISBG et al.
 770 (define_mode_attr bfstart [(DI "s") (SI "t")])
 771 (define_mode_attr bfend   [(DI "e") (SI "f")])
 772
 773 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
 774 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
 775 ;; 64 - bitsize
 776 (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
 777 (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
 778
 779 ;; In place of GET_MODE_SIZE (<MODE>mode)
 780 (define_mode_attr modesize [(DI "8") (SI "4")])
 781
 782 ;; Allow return and simple_return to be defined from a single template.
 783 (define_code_iterator ANY_RETURN [return simple_return])
 784
 785
 786
 787 ; Condition code modes generated by vector fp comparisons.  These will
 788 ; be used also in single element mode.
 789 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
 790 ; Used with VFCMP to expand part of the mnemonic
 791 ; For fp we have a mismatch: eq in the insn name - e in asm
 792 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
 793 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")])
 794
 795 ;; Subst pattern definitions
 796 (include "subst.md")
 797
 798 (include "vector.md")
 799
 800 ;;
 801 ;;- Compare instructions.
 802 ;;
 803
 804 ; Test-under-Mask instructions
 805
 806 (define_insn "*tmqi_mem"
 807   [(set (reg CC_REGNUM)
 808         (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
 809                          (match_operand:QI 1 "immediate_operand" "n,n"))
 810                  (match_operand:QI 2 "immediate_operand" "n,n")))]
 811   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
 812   "@
 813    tm\t%S0,%b1
 814    tmy\t%S0,%b1"
 815   [(set_attr "op_type" "SI,SIY")
 816    (set_attr "cpu_facility" "*,longdisp")
 817    (set_attr "z10prop" "z10_super,z10_super")])
 818
 819 (define_insn "*tmdi_reg"
 820   [(set (reg CC_REGNUM)
 821         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
 822                          (match_operand:DI 1 "immediate_operand"
 823                                              "N0HD0,N1HD0,N2HD0,N3HD0"))
 824                  (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
 825   "TARGET_ZARCH
 826    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 827    && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
 828   "@
 829    tmhh\t%0,%i1
 830    tmhl\t%0,%i1
 831    tmlh\t%0,%i1
 832    tmll\t%0,%i1"
 833   [(set_attr "op_type" "RI")
 834    (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
 835
 836 (define_insn "*tmsi_reg"
 837   [(set (reg CC_REGNUM)
 838         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
 839                          (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
 840                  (match_operand:SI 2 "immediate_operand" "n,n")))]
 841   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 842    && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
 843   "@
 844    tmh\t%0,%i1
 845    tml\t%0,%i1"
 846   [(set_attr "op_type" "RI")
 847    (set_attr "z10prop" "z10_super,z10_super")])
 848
 849 (define_insn "*tm<mode>_full"
 850   [(set (reg CC_REGNUM)
 851         (compare (match_operand:HQI 0 "register_operand" "d")
 852                  (match_operand:HQI 1 "immediate_operand" "n")))]
 853   "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
 854   "tml\t%0,<max_uint>"
 855   [(set_attr "op_type" "RI")
 856    (set_attr "z10prop" "z10_super")])
 857
 858
 859 ;
 860 ; Load-and-Test instructions
 861 ;
 862
 863 ; tst(di|si) instruction pattern(s).
 864
 865 (define_insn "*tstdi_sign"
 866   [(set (reg CC_REGNUM)
 867         (compare
 868           (ashiftrt:DI
 869             (ashift:DI
 870               (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
 871               (const_int 32)) (const_int 32))
 872           (match_operand:DI 1 "const0_operand" "")))
 873    (set (match_operand:DI 2 "register_operand" "=d,d")
 874         (sign_extend:DI (match_dup 0)))]
 875   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
 876   "ltgfr\t%2,%0
 877    ltgf\t%2,%0"
 878   [(set_attr "op_type"      "RRE,RXY")
 879    (set_attr "cpu_facility" "*,z10")
 880    (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
 881
 882 ; ltr, lt, ltgr, ltg
 883 (define_insn "*tst<mode>_extimm"
 884   [(set (reg CC_REGNUM)
 885         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
 886                  (match_operand:GPR 1 "const0_operand" "")))
 887    (set (match_operand:GPR 2 "register_operand" "=d,d")
 888         (match_dup 0))]
 889   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 890   "@
 891    lt<g>r\t%2,%0
 892    lt<g>\t%2,%0"
 893   [(set_attr "op_type" "RR<E>,RXY")
 894    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
 895
 896 ; ltr, lt, ltgr, ltg
 897 (define_insn "*tst<mode>_cconly_extimm"
 898   [(set (reg CC_REGNUM)
 899         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
 900                  (match_operand:GPR 1 "const0_operand" "")))
 901    (clobber (match_scratch:GPR 2 "=X,d"))]
 902   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 903   "@
 904    lt<g>r\t%0,%0
 905    lt<g>\t%2,%0"
 906   [(set_attr "op_type" "RR<E>,RXY")
 907    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
 908
 909 (define_insn "*tstdi"
 910   [(set (reg CC_REGNUM)
 911         (compare (match_operand:DI 0 "register_operand" "d")
 912                  (match_operand:DI 1 "const0_operand" "")))
 913    (set (match_operand:DI 2 "register_operand" "=d")
 914         (match_dup 0))]
 915   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
 916   "ltgr\t%2,%0"
 917   [(set_attr "op_type" "RRE")
 918    (set_attr "z10prop" "z10_fr_E1")])
 919
 920 (define_insn "*tstsi"
 921   [(set (reg CC_REGNUM)
 922         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 923                  (match_operand:SI 1 "const0_operand" "")))
 924    (set (match_operand:SI 2 "register_operand" "=d,d,d")
 925         (match_dup 0))]
 926   "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
 927   "@
 928    ltr\t%2,%0
 929    icm\t%2,15,%S0
 930    icmy\t%2,15,%S0"
 931   [(set_attr "op_type" "RR,RS,RSY")
 932    (set_attr "cpu_facility" "*,*,longdisp")
 933    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 934
 935 (define_insn "*tstsi_cconly"
 936   [(set (reg CC_REGNUM)
 937         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 938                  (match_operand:SI 1 "const0_operand" "")))
 939    (clobber (match_scratch:SI 2 "=X,d,d"))]
 940   "s390_match_ccmode(insn, CCSmode)"
 941   "@
 942    ltr\t%0,%0
 943    icm\t%2,15,%S0
 944    icmy\t%2,15,%S0"
 945   [(set_attr "op_type" "RR,RS,RSY")
 946    (set_attr "cpu_facility" "*,*,longdisp")
 947    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 948
 949 (define_insn "*tstdi_cconly_31"
 950   [(set (reg CC_REGNUM)
 951         (compare (match_operand:DI 0 "register_operand" "d")
 952                  (match_operand:DI 1 "const0_operand" "")))]
 953   "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
 954   "srda\t%0,0"
 955   [(set_attr "op_type" "RS")
 956    (set_attr "atype"   "reg")])
 957
 958 ; ltr, ltgr
 959 (define_insn "*tst<mode>_cconly2"
 960   [(set (reg CC_REGNUM)
 961         (compare (match_operand:GPR 0 "register_operand" "d")
 962                  (match_operand:GPR 1 "const0_operand" "")))]
 963   "s390_match_ccmode(insn, CCSmode)"
 964   "lt<g>r\t%0,%0"
 965   [(set_attr "op_type" "RR<E>")
 966    (set_attr "z10prop" "z10_fr_E1")])
 967
 968 ; tst(hi|qi) instruction pattern(s).
 969
 970 (define_insn "*tst<mode>CCT"
 971   [(set (reg CC_REGNUM)
 972         (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
 973                  (match_operand:HQI 1 "const0_operand" "")))
 974    (set (match_operand:HQI 2 "register_operand" "=d,d,0")
 975         (match_dup 0))]
 976   "s390_match_ccmode(insn, CCTmode)"
 977   "@
 978    icm\t%2,<icm_lo>,%S0
 979    icmy\t%2,<icm_lo>,%S0
 980    tml\t%0,<max_uint>"
 981   [(set_attr "op_type" "RS,RSY,RI")
 982    (set_attr "cpu_facility" "*,longdisp,*")
 983    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 984
 985 (define_insn "*tsthiCCT_cconly"
 986   [(set (reg CC_REGNUM)
 987         (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
 988                  (match_operand:HI 1 "const0_operand" "")))
 989    (clobber (match_scratch:HI 2 "=d,d,X"))]
 990   "s390_match_ccmode(insn, CCTmode)"
 991   "@
 992    icm\t%2,3,%S0
 993    icmy\t%2,3,%S0
 994    tml\t%0,65535"
 995   [(set_attr "op_type" "RS,RSY,RI")
 996    (set_attr "cpu_facility" "*,longdisp,*")
 997    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 998
 999 (define_insn "*tstqiCCT_cconly"
1000   [(set (reg CC_REGNUM)
1001         (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
1002                  (match_operand:QI 1 "const0_operand" "")))]
1003   "s390_match_ccmode(insn, CCTmode)"
1004   "@
1005    cli\t%S0,0
1006    cliy\t%S0,0
1007    tml\t%0,255"
1008   [(set_attr "op_type" "SI,SIY,RI")
1009    (set_attr "cpu_facility" "*,longdisp,*")
1010    (set_attr "z10prop" "z10_super,z10_super,z10_super")])
1011
1012 (define_insn "*tst<mode>"
1013   [(set (reg CC_REGNUM)
1014         (compare (match_operand:HQI 0 "s_operand" "Q,S")
1015                  (match_operand:HQI 1 "const0_operand" "")))
1016    (set (match_operand:HQI 2 "register_operand" "=d,d")
1017         (match_dup 0))]
1018   "s390_match_ccmode(insn, CCSmode)"
1019   "@
1020    icm\t%2,<icm_lo>,%S0
1021    icmy\t%2,<icm_lo>,%S0"
1022   [(set_attr "op_type" "RS,RSY")
1023    (set_attr "cpu_facility" "*,longdisp")
1024    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1025
1026 (define_insn "*tst<mode>_cconly"
1027   [(set (reg CC_REGNUM)
1028         (compare (match_operand:HQI 0 "s_operand" "Q,S")
1029                  (match_operand:HQI 1 "const0_operand" "")))
1030    (clobber (match_scratch:HQI 2 "=d,d"))]
1031   "s390_match_ccmode(insn, CCSmode)"
1032   "@
1033    icm\t%2,<icm_lo>,%S0
1034    icmy\t%2,<icm_lo>,%S0"
1035   [(set_attr "op_type" "RS,RSY")
1036    (set_attr "cpu_facility" "*,longdisp")
1037    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1038
1039
1040 ; Compare (equality) instructions
1041
1042 (define_insn "*cmpdi_cct"
1043   [(set (reg CC_REGNUM)
1044         (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
1045                  (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
1046   "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
1047   "@
1048    cgr\t%0,%1
1049    cghi\t%0,%h1
1050    cgfi\t%0,%1
1051    cg\t%0,%1
1052    #"
1053   [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
1054    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
1055
1056 (define_insn "*cmpsi_cct"
1057   [(set (reg CC_REGNUM)
1058         (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1059                  (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1060   "s390_match_ccmode (insn, CCTmode)"
1061   "@
1062    cr\t%0,%1
1063    chi\t%0,%h1
1064    cfi\t%0,%1
1065    c\t%0,%1
1066    cy\t%0,%1
1067    #"
1068   [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1069    (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
1070    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1071
1072 ; Compare (signed) instructions
1073
1074 (define_insn "*cmpdi_ccs_sign"
1075   [(set (reg CC_REGNUM)
1076         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1077                                                      "d,T,b"))
1078                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1079   "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1080   "@
1081    cgfr\t%0,%1
1082    cgf\t%0,%1
1083    cgfrl\t%0,%1"
1084   [(set_attr "op_type"      "RRE,RXY,RIL")
1085    (set_attr "z10prop" "z10_c,*,*")
1086    (set_attr "type"         "*,*,larl")])
1087
1088
1089
1090 (define_insn "*cmpsi_ccs_sign"
1091   [(set (reg CC_REGNUM)
1092         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1093                  (match_operand:SI 0 "register_operand" "d,d,d")))]
1094   "s390_match_ccmode(insn, CCSRmode)"
1095   "@
1096    ch\t%0,%1
1097    chy\t%0,%1
1098    chrl\t%0,%1"
1099   [(set_attr "op_type"      "RX,RXY,RIL")
1100    (set_attr "cpu_facility" "*,longdisp,z10")
1101    (set_attr "type"         "*,*,larl")
1102    (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1103
1104 (define_insn "*cmphi_ccs_z10"
1105   [(set (reg CC_REGNUM)
1106         (compare (match_operand:HI 0 "s_operand"         "Q")
1107                  (match_operand:HI 1 "immediate_operand" "K")))]
1108   "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1109   "chhsi\t%0,%1"
1110   [(set_attr "op_type" "SIL")
1111    (set_attr "z196prop" "z196_cracked")])
1112
1113 (define_insn "*cmpdi_ccs_signhi_rl"
1114   [(set (reg CC_REGNUM)
1115         (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
1116                  (match_operand:GPR 0 "register_operand"  "d,d")))]
1117   "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1118   "@
1119    cgh\t%0,%1
1120    cghrl\t%0,%1"
1121   [(set_attr "op_type" "RXY,RIL")
1122    (set_attr "type"    "*,larl")])
1123
1124 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1125 (define_insn "*cmp<mode>_ccs"
1126   [(set (reg CC_REGNUM)
1127         (compare (match_operand:GPR 0 "nonimmediate_operand"
1128                                       "d,d,Q, d,d,d,d")
1129                  (match_operand:GPR 1 "general_operand"
1130                                       "d,K,K,Os,R,T,b")))]
1131   "s390_match_ccmode(insn, CCSmode)"
1132   "@
1133    c<g>r\t%0,%1
1134    c<g>hi\t%0,%h1
1135    c<g>hsi\t%0,%h1
1136    c<g>fi\t%0,%1
1137    c<g>\t%0,%1
1138    c<y>\t%0,%1
1139    c<g>rl\t%0,%1"
1140   [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1141    (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
1142    (set_attr "type" "*,*,*,*,*,*,larl")
1143    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1144
1145
1146 ; Compare (unsigned) instructions
1147
1148 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1149   [(set (reg CC_REGNUM)
1150         (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1151                                           "larl_operand" "X")))
1152                  (match_operand:SI 0 "register_operand" "d")))]
1153   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1154   "clhrl\t%0,%1"
1155   [(set_attr "op_type" "RIL")
1156    (set_attr "type"    "larl")
1157    (set_attr "z10prop" "z10_super")])
1158
1159 ; clhrl, clghrl
1160 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1161   [(set (reg CC_REGNUM)
1162         (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1163                                           "larl_operand" "X")))
1164                  (match_operand:GPR 0 "register_operand" "d")))]
1165   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1166   "cl<g>hrl\t%0,%1"
1167   [(set_attr "op_type" "RIL")
1168    (set_attr "type"    "larl")
1169    (set_attr "z10prop" "z10_super")])
1170
1171 (define_insn "*cmpdi_ccu_zero"
1172   [(set (reg CC_REGNUM)
1173         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1174                                                         "d,T,b"))
1175                  (match_operand:DI 0 "register_operand" "d,d,d")))]
1176   "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1177   "@
1178    clgfr\t%0,%1
1179    clgf\t%0,%1
1180    clgfrl\t%0,%1"
1181   [(set_attr "op_type"      "RRE,RXY,RIL")
1182    (set_attr "cpu_facility" "*,*,z10")
1183    (set_attr "type"         "*,*,larl")
1184    (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1185
1186 (define_insn "*cmpdi_ccu"
1187   [(set (reg CC_REGNUM)
1188         (compare (match_operand:DI 0 "nonimmediate_operand"
1189                                      "d, d,d,Q,d, Q,BQ")
1190                  (match_operand:DI 1 "general_operand"
1191                                      "d,Op,b,D,T,BQ,Q")))]
1192   "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1193   "@
1194    clgr\t%0,%1
1195    clgfi\t%0,%1
1196    clgrl\t%0,%1
1197    clghsi\t%0,%x1
1198    clg\t%0,%1
1199    #
1200    #"
1201   [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1202    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1203    (set_attr "type"         "*,*,larl,*,*,*,*")
1204    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1205
1206 (define_insn "*cmpsi_ccu"
1207   [(set (reg CC_REGNUM)
1208         (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1209                  (match_operand:SI 1 "general_operand"      "d,Os,b,D,R,T,BQ, Q")))]
1210   "s390_match_ccmode (insn, CCUmode)"
1211   "@
1212    clr\t%0,%1
1213    clfi\t%0,%o1
1214    clrl\t%0,%1
1215    clfhsi\t%0,%x1
1216    cl\t%0,%1
1217    cly\t%0,%1
1218    #
1219    #"
1220   [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1221    (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
1222    (set_attr "type"         "*,*,larl,*,*,*,*,*")
1223    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1224
1225 (define_insn "*cmphi_ccu"
1226   [(set (reg CC_REGNUM)
1227         (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1228                  (match_operand:HI 1 "general_operand"      "Q,S,D,BQ,Q")))]
1229   "s390_match_ccmode (insn, CCUmode)
1230    && !register_operand (operands[1], HImode)"
1231   "@
1232    clm\t%0,3,%S1
1233    clmy\t%0,3,%S1
1234    clhhsi\t%0,%1
1235    #
1236    #"
1237   [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1238    (set_attr "cpu_facility" "*,longdisp,z10,*,*")
1239    (set_attr "z10prop" "*,*,z10_super,*,*")])
1240
1241 (define_insn "*cmpqi_ccu"
1242   [(set (reg CC_REGNUM)
1243         (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1244                  (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1245   "s390_match_ccmode (insn, CCUmode)
1246    && !register_operand (operands[1], QImode)"
1247   "@
1248    clm\t%0,1,%S1
1249    clmy\t%0,1,%S1
1250    cli\t%S0,%b1
1251    cliy\t%S0,%b1
1252    #
1253    #"
1254   [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1255    (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
1256    (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1257
1258
1259 ; Block compare (CLC) instruction patterns.
1260
1261 (define_insn "*clc"
1262   [(set (reg CC_REGNUM)
1263         (compare (match_operand:BLK 0 "memory_operand" "Q")
1264                  (match_operand:BLK 1 "memory_operand" "Q")))
1265    (use (match_operand 2 "const_int_operand" "n"))]
1266   "s390_match_ccmode (insn, CCUmode)
1267    && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1268   "clc\t%O0(%2,%R0),%S1"
1269   [(set_attr "op_type" "SS")])
1270
1271 (define_split
1272   [(set (reg CC_REGNUM)
1273         (compare (match_operand 0 "memory_operand" "")
1274                  (match_operand 1 "memory_operand" "")))]
1275   "reload_completed
1276    && s390_match_ccmode (insn, CCUmode)
1277    && GET_MODE (operands[0]) == GET_MODE (operands[1])
1278    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1279   [(parallel
1280     [(set (match_dup 0) (match_dup 1))
1281      (use (match_dup 2))])]
1282 {
1283   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1284   operands[0] = adjust_address (operands[0], BLKmode, 0);
1285   operands[1] = adjust_address (operands[1], BLKmode, 0);
1286
1287   operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1288                                  operands[0], operands[1]);
1289   operands[0] = SET_DEST (PATTERN (curr_insn));
1290 })
1291
1292
1293 ; (TF|DF|SF|TD|DD|SD) instructions
1294
1295
1296 ; load and test instructions turn SNaN into QNaN what is not
1297 ; acceptable if the target will be used afterwards.  On the other hand
1298 ; they are quite convenient for implementing comparisons with 0.0. So
1299 ; try to enable them via splitter if the value isn't needed anymore.
1300
1301 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1302 (define_insn "*cmp<mode>_ccs_0"
1303   [(set (reg CC_REGNUM)
1304         (compare (match_operand:FP 0 "register_operand"  "f")
1305                  (match_operand:FP 1 "const0_operand"    "")))
1306    (clobber (match_operand:FP      2 "register_operand" "=0"))]
1307   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1308   "lt<xde><bt>r\t%0,%0"
1309    [(set_attr "op_type" "RRE")
1310     (set_attr "type"  "fsimp<mode>")])
1311
1312 (define_split
1313   [(set (match_operand 0 "cc_reg_operand")
1314         (compare (match_operand:FP 1 "register_operand")
1315                  (match_operand:FP 2 "const0_operand")))]
1316   "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])"
1317   [(parallel
1318     [(set (match_dup 0) (match_dup 3))
1319      (clobber (match_dup 1))])]
1320  {
1321    /* s390_match_ccmode requires the compare to have the same CC mode
1322       as the CC destination register.  */
1323    operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]),
1324                                   operands[1], operands[2]);
1325  })
1326
1327
1328 ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcdb
1329 (define_insn "*cmp<mode>_ccs"
1330   [(set (reg CC_REGNUM)
1331         (compare (match_operand:FP 0 "register_operand" "f,f,v")
1332                  (match_operand:FP 1 "general_operand"  "f,R,v")))]
1333   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1334   "@
1335    c<xde><bt>r\t%0,%1
1336    c<xde>b\t%0,%1
1337    wfcdb\t%0,%1"
1338   [(set_attr "op_type" "RRE,RXE,VRR")
1339    (set_attr "cpu_facility" "*,*,vx")
1340    (set_attr "enabled" "*,<DSF>,<DFDI>")])
1341
1342
1343 ; Compare and Branch instructions
1344
1345 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1346 ; The following instructions do a complementary access of their second
1347 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1348 (define_insn "*cmp_and_br_signed_<mode>"
1349   [(set (pc)
1350         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1351                         [(match_operand:GPR 1 "register_operand"  "d,d")
1352                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1353                       (label_ref (match_operand 3 "" ""))
1354                       (pc)))
1355    (clobber (reg:CC CC_REGNUM))]
1356   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1357 {
1358   if (get_attr_length (insn) == 6)
1359     return which_alternative ?
1360       "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1361   else
1362     return which_alternative ?
1363       "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1364 }
1365   [(set_attr "op_type" "RIE")
1366    (set_attr "type"    "branch")
1367    (set_attr "z10prop" "z10_super_c,z10_super")
1368    (set (attr "length")
1369         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1370                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1371                                                        ; 10 byte for cgr/jg
1372
1373 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1374 ; The following instructions do a complementary access of their second
1375 ; operand (z10 only): clrj, clgrj, clr, clgr
1376 (define_insn "*cmp_and_br_unsigned_<mode>"
1377   [(set (pc)
1378         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1379                         [(match_operand:GPR 1 "register_operand"  "d,d")
1380                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1381                       (label_ref (match_operand 3 "" ""))
1382                       (pc)))
1383    (clobber (reg:CC CC_REGNUM))]
1384   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1385 {
1386   if (get_attr_length (insn) == 6)
1387     return which_alternative ?
1388       "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1389   else
1390     return which_alternative ?
1391       "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1392 }
1393   [(set_attr "op_type" "RIE")
1394    (set_attr "type"    "branch")
1395    (set_attr "z10prop" "z10_super_c,z10_super")
1396    (set (attr "length")
1397         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1398                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1399                                                        ; 10 byte for clgr/jg
1400
1401 ; And now the same two patterns as above but with a negated CC mask.
1402
1403 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1404 ; The following instructions do a complementary access of their second
1405 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1406 (define_insn "*icmp_and_br_signed_<mode>"
1407   [(set (pc)
1408         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1409                         [(match_operand:GPR 1 "register_operand"  "d,d")
1410                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1411                       (pc)
1412                       (label_ref (match_operand 3 "" ""))))
1413    (clobber (reg:CC CC_REGNUM))]
1414   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1415 {
1416   if (get_attr_length (insn) == 6)
1417     return which_alternative ?
1418       "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1419   else
1420     return which_alternative ?
1421       "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1422 }
1423   [(set_attr "op_type" "RIE")
1424    (set_attr "type"    "branch")
1425    (set_attr "z10prop" "z10_super_c,z10_super")
1426    (set (attr "length")
1427         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1428                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1429                                                        ; 10 byte for cgr/jg
1430
1431 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1432 ; The following instructions do a complementary access of their second
1433 ; operand (z10 only): clrj, clgrj, clr, clgr
1434 (define_insn "*icmp_and_br_unsigned_<mode>"
1435   [(set (pc)
1436         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1437                         [(match_operand:GPR 1 "register_operand"  "d,d")
1438                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1439                       (pc)
1440                       (label_ref (match_operand 3 "" ""))))
1441    (clobber (reg:CC CC_REGNUM))]
1442   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1443 {
1444   if (get_attr_length (insn) == 6)
1445     return which_alternative ?
1446       "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1447   else
1448     return which_alternative ?
1449       "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1450 }
1451   [(set_attr "op_type" "RIE")
1452    (set_attr "type"    "branch")
1453    (set_attr "z10prop" "z10_super_c,z10_super")
1454    (set (attr "length")
1455         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1456                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1457                                                        ; 10 byte for clgr/jg
1458
1459 ;;
1460 ;;- Move instructions.
1461 ;;
1462
1463 ;
1464 ; movti instruction pattern(s).
1465 ;
1466
1467 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1468 ; for TImode (use double-int for the calculations)
1469 (define_insn "movti"
1470   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v,  v,  v,v,d,v,R,  d,o")
1471         (match_operand:TI 1 "general_operand"      " S,d,v,j00,jm1,d,v,R,v,dPT,d"))]
1472   "TARGET_ZARCH"
1473   "@
1474    lmg\t%0,%N0,%S1
1475    stmg\t%1,%N1,%S0
1476    vlr\t%v0,%v1
1477    vzero\t%v0
1478    vone\t%v0
1479    vlvgp\t%v0,%1,%N1
1480    #
1481    vl\t%v0,%1
1482    vst\t%v1,%0
1483    #
1484    #"
1485   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1486    (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1487    (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")])
1488
1489 (define_split
1490   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1491         (match_operand:TI 1 "general_operand" ""))]
1492   "TARGET_ZARCH && reload_completed
1493    && !s_operand (operands[0], TImode)
1494    && !s_operand (operands[1], TImode)
1495    && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1496   [(set (match_dup 2) (match_dup 4))
1497    (set (match_dup 3) (match_dup 5))]
1498 {
1499   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1500   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1501   operands[4] = operand_subword (operands[1], 0, 0, TImode);
1502   operands[5] = operand_subword (operands[1], 1, 0, TImode);
1503 })
1504
1505 (define_split
1506   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1507         (match_operand:TI 1 "general_operand" ""))]
1508   "TARGET_ZARCH && reload_completed
1509    && !s_operand (operands[0], TImode)
1510    && !s_operand (operands[1], TImode)
1511    && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1512   [(set (match_dup 2) (match_dup 4))
1513    (set (match_dup 3) (match_dup 5))]
1514 {
1515   operands[2] = operand_subword (operands[0], 1, 0, TImode);
1516   operands[3] = operand_subword (operands[0], 0, 0, TImode);
1517   operands[4] = operand_subword (operands[1], 1, 0, TImode);
1518   operands[5] = operand_subword (operands[1], 0, 0, TImode);
1519 })
1520
1521 ; Use part of the TImode target reg to perform the address
1522 ; calculation.  If the TImode value is supposed to be copied into a VR
1523 ; this splitter is not necessary.
1524 (define_split
1525   [(set (match_operand:TI 0 "register_operand" "")
1526         (match_operand:TI 1 "memory_operand" ""))]
1527   "TARGET_ZARCH && reload_completed
1528    && !VECTOR_REG_P (operands[0])
1529    && !s_operand (operands[1], VOIDmode)"
1530   [(set (match_dup 0) (match_dup 1))]
1531 {
1532   rtx addr = operand_subword (operands[0], 1, 0, TImode);
1533   addr = gen_lowpart (Pmode, addr);
1534   s390_load_address (addr, XEXP (operands[1], 0));
1535   operands[1] = replace_equiv_address (operands[1], addr);
1536 })
1537
1538
1539 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1540 ; For the higher order bits we do simply a DImode move while the
1541 ; second part is done via vec extract.  Both will end up as vlgvg.
1542 (define_split
1543   [(set (match_operand:TI 0 "register_operand" "")
1544         (match_operand:TI 1 "register_operand" ""))]
1545   "TARGET_VX && reload_completed
1546    && GENERAL_REG_P (operands[0])
1547    && VECTOR_REG_P (operands[1])"
1548   [(set (match_dup 2) (match_dup 4))
1549    (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1550                                  UNSPEC_VEC_EXTRACT))]
1551 {
1552   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1553   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1554   operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1555   operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1556 })
1557
1558 ;
1559 ; Patterns used for secondary reloads
1560 ;
1561
1562 ; z10 provides move instructions accepting larl memory operands.
1563 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1564 ; These patterns are also used for unaligned SI and DI accesses.
1565
1566 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1567   [(parallel [(match_operand:ALL 0 "memory_operand"   "")
1568               (match_operand:ALL 1 "register_operand" "=d")
1569               (match_operand:P   2 "register_operand" "=&a")])]
1570   "TARGET_Z10"
1571 {
1572   s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1573   DONE;
1574 })
1575
1576 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1577   [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1578               (match_operand:ALL 1 "memory_operand"   "")
1579               (match_operand:P   2 "register_operand" "=a")])]
1580   "TARGET_Z10"
1581 {
1582   s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1583   DONE;
1584 })
1585
1586 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1587   [(parallel [(match_operand:P 0 "register_operand" "=d")
1588               (match_operand:P 1 "larl_operand"     "")
1589               (match_operand:P 2 "register_operand" "=a")])]
1590   "TARGET_Z10"
1591 {
1592   s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1593   DONE;
1594 })
1595
1596 ; Handles loading a PLUS (load address) expression
1597
1598 (define_expand "reload<mode>_plus"
1599   [(parallel [(match_operand:P 0 "register_operand"  "=a")
1600               (match_operand:P 1 "s390_plus_operand" "")
1601               (match_operand:P 2 "register_operand"  "=&a")])]
1602   ""
1603 {
1604   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1605   DONE;
1606 })
1607
1608 ; Not all the indirect memory access instructions support the full
1609 ; format (long disp + index + base).  So whenever a move from/to such
1610 ; an address is required and the instruction cannot deal with it we do
1611 ; a load address into a scratch register first and use this as the new
1612 ; base register.
1613 ; This in particular is used for:
1614 ; - non-offsetable memory accesses for multiword moves
1615 ; - full vector reg moves with long displacements
1616
1617 (define_expand "reload<mode>_la_in"
1618   [(parallel [(match_operand 0   "register_operand" "")
1619               (match_operand 1   "" "")
1620               (match_operand:P 2 "register_operand" "=&a")])]
1621   ""
1622 {
1623   gcc_assert (MEM_P (operands[1]));
1624   s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1625   operands[1] = replace_equiv_address (operands[1], operands[2]);
1626   emit_move_insn (operands[0], operands[1]);
1627   DONE;
1628 })
1629
1630 (define_expand "reload<mode>_la_out"
1631   [(parallel [(match_operand   0 "" "")
1632               (match_operand   1 "register_operand" "")
1633               (match_operand:P 2 "register_operand" "=&a")])]
1634   ""
1635 {
1636   gcc_assert (MEM_P (operands[0]));
1637   s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1638   operands[0] = replace_equiv_address (operands[0], operands[2]);
1639   emit_move_insn (operands[0], operands[1]);
1640   DONE;
1641 })
1642
1643 (define_expand "reload<mode>_PIC_addr"
1644   [(parallel [(match_operand   0 "register_operand" "=d")
1645               (match_operand   1 "larl_operand"     "")
1646               (match_operand:P 2 "register_operand" "=a")])]
1647   ""
1648 {
1649   rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1650   emit_move_insn (operands[0], new_rtx);
1651 })
1652
1653 ;
1654 ; movdi instruction pattern(s).
1655 ;
1656
1657 (define_expand "movdi"
1658   [(set (match_operand:DI 0 "general_operand" "")
1659         (match_operand:DI 1 "general_operand" ""))]
1660   ""
1661 {
1662   /* Handle symbolic constants.  */
1663   if (TARGET_64BIT
1664       && (SYMBOLIC_CONST (operands[1])
1665           || (GET_CODE (operands[1]) == PLUS
1666               && XEXP (operands[1], 0) == pic_offset_table_rtx
1667               && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1668     emit_symbolic_move (operands);
1669 })
1670
1671 (define_insn "*movdi_larl"
1672   [(set (match_operand:DI 0 "register_operand" "=d")
1673         (match_operand:DI 1 "larl_operand" "X"))]
1674   "TARGET_64BIT
1675    && !FP_REG_P (operands[0])"
1676   "larl\t%0,%1"
1677    [(set_attr "op_type" "RIL")
1678     (set_attr "type"    "larl")
1679     (set_attr "z10prop" "z10_super_A1")])
1680
1681 (define_insn "*movdi_64"
1682   [(set (match_operand:DI 0 "nonimmediate_operand"
1683          "=d,    d,    d,    d,    d, d,    d,    d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R")
1684         (match_operand:DI 1 "general_operand"
1685          " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f,  R,  T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))]
1686   "TARGET_ZARCH"
1687   "@
1688    lghi\t%0,%h1
1689    llihh\t%0,%i1
1690    llihl\t%0,%i1
1691    llilh\t%0,%i1
1692    llill\t%0,%i1
1693    lgfi\t%0,%1
1694    llihf\t%0,%k1
1695    llilf\t%0,%k1
1696    ldgr\t%0,%1
1697    lgdr\t%0,%1
1698    lay\t%0,%a1
1699    lgrl\t%0,%1
1700    lgr\t%0,%1
1701    lg\t%0,%1
1702    stg\t%1,%0
1703    ldr\t%0,%1
1704    ld\t%0,%1
1705    ldy\t%0,%1
1706    std\t%1,%0
1707    stdy\t%1,%0
1708    stgrl\t%1,%0
1709    mvghi\t%0,%1
1710    #
1711    #
1712    stam\t%1,%N1,%S0
1713    lam\t%0,%N0,%S1
1714    vleig\t%v0,%h1,0
1715    vlr\t%v0,%v1
1716    vlvgg\t%v0,%1,0
1717    vlgvg\t%0,%v1,0
1718    vleg\t%v0,%1,0
1719    vsteg\t%v1,%0,0"
1720   [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1721                         RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1722    (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1723                      floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1724                      *,*,*,*,*,*,*")
1725    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1726                              z10,*,*,*,*,*,longdisp,*,longdisp,
1727                              z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx")
1728    (set_attr "z10prop" "z10_fwd_A1,
1729                         z10_fwd_E1,
1730                         z10_fwd_E1,
1731                         z10_fwd_E1,
1732                         z10_fwd_E1,
1733                         z10_fwd_A1,
1734                         z10_fwd_E1,
1735                         z10_fwd_E1,
1736                         *,
1737                         *,
1738                         z10_fwd_A1,
1739                         z10_fwd_A3,
1740                         z10_fr_E1,
1741                         z10_fwd_A3,
1742                         z10_rec,
1743                         *,
1744                         *,
1745                         *,
1746                         *,
1747                         *,
1748                         z10_rec,
1749                         z10_super,
1750                         *,
1751                         *,
1752                         *,
1753                         *,*,*,*,*,*,*")
1754 ])
1755
1756 (define_split
1757   [(set (match_operand:DI 0 "register_operand" "")
1758         (match_operand:DI 1 "register_operand" ""))]
1759   "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1760   [(set (match_dup 2) (match_dup 3))
1761    (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1762    (set (strict_low_part (match_dup 2)) (match_dup 4))]
1763   "operands[2] = gen_lowpart (SImode, operands[0]);
1764    s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1765
1766 (define_split
1767   [(set (match_operand:DI 0 "register_operand" "")
1768         (match_operand:DI 1 "register_operand" ""))]
1769   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1770    && dead_or_set_p (insn, operands[1])"
1771   [(set (match_dup 3) (match_dup 2))
1772    (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1773    (set (match_dup 4) (match_dup 2))]
1774   "operands[2] = gen_lowpart (SImode, operands[1]);
1775    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1776
1777 (define_split
1778   [(set (match_operand:DI 0 "register_operand" "")
1779         (match_operand:DI 1 "register_operand" ""))]
1780   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1781    && !dead_or_set_p (insn, operands[1])"
1782   [(set (match_dup 3) (match_dup 2))
1783    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1784    (set (match_dup 4) (match_dup 2))
1785    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1786   "operands[2] = gen_lowpart (SImode, operands[1]);
1787    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1788
1789 (define_insn "*movdi_31"
1790   [(set (match_operand:DI 0 "nonimmediate_operand"
1791                             "=d,d,Q,S,d  ,o,!*f,!*f,!*f,!R,!T,d")
1792         (match_operand:DI 1 "general_operand"
1793                             " Q,S,d,d,dPT,d, *f,  R,  T,*f,*f,b"))]
1794   "!TARGET_ZARCH"
1795   "@
1796    lm\t%0,%N0,%S1
1797    lmy\t%0,%N0,%S1
1798    stm\t%1,%N1,%S0
1799    stmy\t%1,%N1,%S0
1800    #
1801    #
1802    ldr\t%0,%1
1803    ld\t%0,%1
1804    ldy\t%0,%1
1805    std\t%1,%0
1806    stdy\t%1,%0
1807    #"
1808   [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1809    (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1810    (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
1811
1812 ; For a load from a symbol ref we can use one of the target registers
1813 ; together with larl to load the address.
1814 (define_split
1815   [(set (match_operand:DI 0 "register_operand" "")
1816         (match_operand:DI 1 "memory_operand" ""))]
1817   "!TARGET_ZARCH && reload_completed && TARGET_Z10
1818    && larl_operand (XEXP (operands[1], 0), SImode)"
1819   [(set (match_dup 2) (match_dup 3))
1820    (set (match_dup 0) (match_dup 1))]
1821 {
1822   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1823   operands[3] = XEXP (operands[1], 0);
1824   operands[1] = replace_equiv_address (operands[1], operands[2]);
1825 })
1826
1827 (define_split
1828   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1829         (match_operand:DI 1 "general_operand" ""))]
1830   "!TARGET_ZARCH && reload_completed
1831    && !s_operand (operands[0], DImode)
1832    && !s_operand (operands[1], DImode)
1833    && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1834   [(set (match_dup 2) (match_dup 4))
1835    (set (match_dup 3) (match_dup 5))]
1836 {
1837   operands[2] = operand_subword (operands[0], 0, 0, DImode);
1838   operands[3] = operand_subword (operands[0], 1, 0, DImode);
1839   operands[4] = operand_subword (operands[1], 0, 0, DImode);
1840   operands[5] = operand_subword (operands[1], 1, 0, DImode);
1841 })
1842
1843 (define_split
1844   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1845         (match_operand:DI 1 "general_operand" ""))]
1846   "!TARGET_ZARCH && reload_completed
1847    && !s_operand (operands[0], DImode)
1848    && !s_operand (operands[1], DImode)
1849    && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1850   [(set (match_dup 2) (match_dup 4))
1851    (set (match_dup 3) (match_dup 5))]
1852 {
1853   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1854   operands[3] = operand_subword (operands[0], 0, 0, DImode);
1855   operands[4] = operand_subword (operands[1], 1, 0, DImode);
1856   operands[5] = operand_subword (operands[1], 0, 0, DImode);
1857 })
1858
1859 (define_split
1860   [(set (match_operand:DI 0 "register_operand" "")
1861         (match_operand:DI 1 "memory_operand" ""))]
1862   "!TARGET_ZARCH && reload_completed
1863    && !FP_REG_P (operands[0])
1864    && !s_operand (operands[1], VOIDmode)"
1865   [(set (match_dup 0) (match_dup 1))]
1866 {
1867   rtx addr = operand_subword (operands[0], 1, 0, DImode);
1868   s390_load_address (addr, XEXP (operands[1], 0));
1869   operands[1] = replace_equiv_address (operands[1], addr);
1870 })
1871
1872 (define_peephole2
1873   [(set (match_operand:DI 0 "register_operand" "")
1874         (mem:DI (match_operand 1 "address_operand" "")))]
1875   "TARGET_ZARCH
1876    && !FP_REG_P (operands[0])
1877    && GET_CODE (operands[1]) == SYMBOL_REF
1878    && CONSTANT_POOL_ADDRESS_P (operands[1])
1879    && get_pool_mode (operands[1]) == DImode
1880    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1881   [(set (match_dup 0) (match_dup 2))]
1882   "operands[2] = get_pool_constant (operands[1]);")
1883
1884 (define_insn "*la_64"
1885   [(set (match_operand:DI 0 "register_operand" "=d,d")
1886         (match_operand:QI 1 "address_operand" "ZR,ZT"))]
1887   "TARGET_64BIT"
1888   "@
1889    la\t%0,%a1
1890    lay\t%0,%a1"
1891   [(set_attr "op_type" "RX,RXY")
1892    (set_attr "type"    "la")
1893    (set_attr "cpu_facility" "*,longdisp")
1894    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1895
1896 (define_peephole2
1897   [(parallel
1898     [(set (match_operand:DI 0 "register_operand" "")
1899           (match_operand:QI 1 "address_operand" ""))
1900      (clobber (reg:CC CC_REGNUM))])]
1901   "TARGET_64BIT
1902    && preferred_la_operand_p (operands[1], const0_rtx)"
1903   [(set (match_dup 0) (match_dup 1))]
1904   "")
1905
1906 (define_peephole2
1907   [(set (match_operand:DI 0 "register_operand" "")
1908         (match_operand:DI 1 "register_operand" ""))
1909    (parallel
1910     [(set (match_dup 0)
1911           (plus:DI (match_dup 0)
1912                    (match_operand:DI 2 "nonmemory_operand" "")))
1913      (clobber (reg:CC CC_REGNUM))])]
1914   "TARGET_64BIT
1915    && !reg_overlap_mentioned_p (operands[0], operands[2])
1916    && preferred_la_operand_p (operands[1], operands[2])"
1917   [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1918   "")
1919
1920 ;
1921 ; movsi instruction pattern(s).
1922 ;
1923
1924 (define_expand "movsi"
1925   [(set (match_operand:SI 0 "general_operand" "")
1926         (match_operand:SI 1 "general_operand" ""))]
1927   ""
1928 {
1929   /* Handle symbolic constants.  */
1930   if (!TARGET_64BIT
1931       && (SYMBOLIC_CONST (operands[1])
1932           || (GET_CODE (operands[1]) == PLUS
1933               && XEXP (operands[1], 0) == pic_offset_table_rtx
1934               && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1935     emit_symbolic_move (operands);
1936 })
1937
1938 (define_insn "*movsi_larl"
1939   [(set (match_operand:SI 0 "register_operand" "=d")
1940         (match_operand:SI 1 "larl_operand" "X"))]
1941   "!TARGET_64BIT && TARGET_CPU_ZARCH
1942    && !FP_REG_P (operands[0])"
1943   "larl\t%0,%1"
1944    [(set_attr "op_type" "RIL")
1945     (set_attr "type"    "larl")
1946     (set_attr "z10prop" "z10_fwd_A1")])
1947
1948 (define_insn "*movsi_zarch"
1949   [(set (match_operand:SI 0 "nonimmediate_operand"
1950          "=d,    d,    d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
1951         (match_operand:SI 1 "general_operand"
1952          " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f,  R,  R,  T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
1953   "TARGET_ZARCH"
1954   "@
1955    lhi\t%0,%h1
1956    llilh\t%0,%i1
1957    llill\t%0,%i1
1958    iilf\t%0,%o1
1959    lay\t%0,%a1
1960    lrl\t%0,%1
1961    lr\t%0,%1
1962    l\t%0,%1
1963    ly\t%0,%1
1964    st\t%1,%0
1965    sty\t%1,%0
1966    ldr\t%0,%1
1967    ler\t%0,%1
1968    lde\t%0,%1
1969    le\t%0,%1
1970    ley\t%0,%1
1971    ste\t%1,%0
1972    stey\t%1,%0
1973    ear\t%0,%1
1974    sar\t%0,%1
1975    stam\t%1,%1,%S0
1976    strl\t%1,%0
1977    mvhi\t%0,%1
1978    lam\t%0,%0,%S1
1979    vleif\t%v0,%h1,0
1980    vlr\t%v0,%v1
1981    vlvgf\t%v0,%1,0
1982    vlgvf\t%0,%v1,0
1983    vlef\t%v0,%1,0
1984    vstef\t%v1,%0,0"
1985   [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1986                         RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1987    (set_attr "type" "*,
1988                      *,
1989                      *,
1990                      *,
1991                      la,
1992                      larl,
1993                      lr,
1994                      load,
1995                      load,
1996                      store,
1997                      store,
1998                      floadsf,
1999                      floadsf,
2000                      floadsf,
2001                      floadsf,
2002                      floadsf,
2003                      fstoresf,
2004                      fstoresf,
2005                      *,
2006                      *,
2007                      *,
2008                      larl,
2009                      *,
2010                      *,*,*,*,*,*,*")
2011    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
2012                              vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx")
2013    (set_attr "z10prop" "z10_fwd_A1,
2014                         z10_fwd_E1,
2015                         z10_fwd_E1,
2016                         z10_fwd_A1,
2017                         z10_fwd_A1,
2018                         z10_fwd_A3,
2019                         z10_fr_E1,
2020                         z10_fwd_A3,
2021                         z10_fwd_A3,
2022                         z10_rec,
2023                         z10_rec,
2024                         *,
2025                         *,
2026                         *,
2027                         *,
2028                         *,
2029                         *,
2030                         *,
2031                         z10_super_E1,
2032                         z10_super,
2033                         *,
2034                         z10_rec,
2035                         z10_super,
2036                         *,*,*,*,*,*,*")])
2037
2038 (define_insn "*movsi_esa"
2039   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
2040         (match_operand:SI 1 "general_operand"       "K,d,R,d, *f, *f,  R,  R,*f,t,d,t,Q"))]
2041   "!TARGET_ZARCH"
2042   "@
2043    lhi\t%0,%h1
2044    lr\t%0,%1
2045    l\t%0,%1
2046    st\t%1,%0
2047    ldr\t%0,%1
2048    ler\t%0,%1
2049    lde\t%0,%1
2050    le\t%0,%1
2051    ste\t%1,%0
2052    ear\t%0,%1
2053    sar\t%0,%1
2054    stam\t%1,%1,%S0
2055    lam\t%0,%0,%S1"
2056   [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
2057    (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
2058    (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
2059                         z10_super,*,*")
2060    (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*")
2061 ])
2062
2063 (define_peephole2
2064   [(set (match_operand:SI 0 "register_operand" "")
2065         (mem:SI (match_operand 1 "address_operand" "")))]
2066   "!FP_REG_P (operands[0])
2067    && GET_CODE (operands[1]) == SYMBOL_REF
2068    && CONSTANT_POOL_ADDRESS_P (operands[1])
2069    && get_pool_mode (operands[1]) == SImode
2070    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
2071   [(set (match_dup 0) (match_dup 2))]
2072   "operands[2] = get_pool_constant (operands[1]);")
2073
2074 (define_insn "*la_31"
2075   [(set (match_operand:SI 0 "register_operand" "=d,d")
2076         (match_operand:QI 1 "address_operand" "ZR,ZT"))]
2077   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
2078   "@
2079    la\t%0,%a1
2080    lay\t%0,%a1"
2081   [(set_attr "op_type"  "RX,RXY")
2082    (set_attr "type"     "la")
2083    (set_attr "cpu_facility" "*,longdisp")
2084    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2085
2086 (define_peephole2
2087   [(parallel
2088     [(set (match_operand:SI 0 "register_operand" "")
2089           (match_operand:QI 1 "address_operand" ""))
2090      (clobber (reg:CC CC_REGNUM))])]
2091   "!TARGET_64BIT
2092    && preferred_la_operand_p (operands[1], const0_rtx)"
2093   [(set (match_dup 0) (match_dup 1))]
2094   "")
2095
2096 (define_peephole2
2097   [(set (match_operand:SI 0 "register_operand" "")
2098         (match_operand:SI 1 "register_operand" ""))
2099    (parallel
2100     [(set (match_dup 0)
2101           (plus:SI (match_dup 0)
2102                    (match_operand:SI 2 "nonmemory_operand" "")))
2103      (clobber (reg:CC CC_REGNUM))])]
2104   "!TARGET_64BIT
2105    && !reg_overlap_mentioned_p (operands[0], operands[2])
2106    && preferred_la_operand_p (operands[1], operands[2])"
2107   [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2108   "")
2109
2110 (define_insn "*la_31_and"
2111   [(set (match_operand:SI 0 "register_operand" "=d,d")
2112         (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
2113                 (const_int 2147483647)))]
2114   "!TARGET_64BIT"
2115   "@
2116    la\t%0,%a1
2117    lay\t%0,%a1"
2118   [(set_attr "op_type"  "RX,RXY")
2119    (set_attr "type"     "la")
2120    (set_attr "cpu_facility" "*,longdisp")
2121    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2122
2123 (define_insn_and_split "*la_31_and_cc"
2124   [(set (match_operand:SI 0 "register_operand" "=d")
2125         (and:SI (match_operand:QI 1 "address_operand" "p")
2126                 (const_int 2147483647)))
2127    (clobber (reg:CC CC_REGNUM))]
2128   "!TARGET_64BIT"
2129   "#"
2130   "&& reload_completed"
2131   [(set (match_dup 0)
2132         (and:SI (match_dup 1) (const_int 2147483647)))]
2133   ""
2134   [(set_attr "op_type"  "RX")
2135    (set_attr "type"     "la")])
2136
2137 (define_insn "force_la_31"
2138   [(set (match_operand:SI 0 "register_operand" "=d,d")
2139         (match_operand:QI 1 "address_operand" "ZR,ZT"))
2140    (use (const_int 0))]
2141   "!TARGET_64BIT"
2142   "@
2143    la\t%0,%a1
2144    lay\t%0,%a1"
2145   [(set_attr "op_type"  "RX")
2146    (set_attr "type"     "la")
2147    (set_attr "cpu_facility" "*,longdisp")
2148    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2149
2150 ;
2151 ; movhi instruction pattern(s).
2152 ;
2153
2154 (define_expand "movhi"
2155   [(set (match_operand:HI 0 "nonimmediate_operand" "")
2156         (match_operand:HI 1 "general_operand" ""))]
2157   ""
2158 {
2159   /* Make it explicit that loading a register from memory
2160      always sign-extends (at least) to SImode.  */
2161   if (optimize && can_create_pseudo_p ()
2162       && register_operand (operands[0], VOIDmode)
2163       && GET_CODE (operands[1]) == MEM)
2164     {
2165       rtx tmp = gen_reg_rtx (SImode);
2166       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2167       emit_insn (gen_rtx_SET (tmp, ext));
2168       operands[1] = gen_lowpart (HImode, tmp);
2169     }
2170 })
2171
2172 (define_insn "*movhi"
2173   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
2174         (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
2175   ""
2176   "@
2177    lr\t%0,%1
2178    lhi\t%0,%h1
2179    lh\t%0,%1
2180    lhy\t%0,%1
2181    lhrl\t%0,%1
2182    sth\t%1,%0
2183    sthy\t%1,%0
2184    sthrl\t%1,%0
2185    mvhhi\t%0,%1
2186    vleih\t%v0,%h1,0
2187    vlr\t%v0,%v1
2188    vlvgh\t%v0,%1,0
2189    vlgvh\t%0,%v1,0
2190    vleh\t%v0,%1,0
2191    vsteh\t%v1,%0,0"
2192   [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2193    (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2194    (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx")
2195    (set_attr "z10prop" "z10_fr_E1,
2196                        z10_fwd_A1,
2197                        z10_super_E1,
2198                        z10_super_E1,
2199                        z10_super_E1,
2200                        z10_rec,
2201                        z10_rec,
2202                        z10_rec,
2203                        z10_super,*,*,*,*,*,*")])
2204
2205 (define_peephole2
2206   [(set (match_operand:HI 0 "register_operand" "")
2207         (mem:HI (match_operand 1 "address_operand" "")))]
2208   "GET_CODE (operands[1]) == SYMBOL_REF
2209    && CONSTANT_POOL_ADDRESS_P (operands[1])
2210    && get_pool_mode (operands[1]) == HImode
2211    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2212   [(set (match_dup 0) (match_dup 2))]
2213   "operands[2] = get_pool_constant (operands[1]);")
2214
2215 ;
2216 ; movqi instruction pattern(s).
2217 ;
2218
2219 (define_expand "movqi"
2220   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2221         (match_operand:QI 1 "general_operand" ""))]
2222   ""
2223 {
2224   /* On z/Architecture, zero-extending from memory to register
2225      is just as fast as a QImode load.  */
2226   if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2227       && register_operand (operands[0], VOIDmode)
2228       && GET_CODE (operands[1]) == MEM)
2229     {
2230       rtx tmp = gen_reg_rtx (DImode);
2231       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2232       emit_insn (gen_rtx_SET (tmp, ext));
2233       operands[1] = gen_lowpart (QImode, tmp);
2234     }
2235 })
2236
2237 (define_insn "*movqi"
2238   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
2239         (match_operand:QI 1 "general_operand"      " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
2240   ""
2241   "@
2242    lr\t%0,%1
2243    lhi\t%0,%b1
2244    ic\t%0,%1
2245    icy\t%0,%1
2246    stc\t%1,%0
2247    stcy\t%1,%0
2248    mvi\t%S0,%b1
2249    mviy\t%S0,%b1
2250    #
2251    vleib\t%v0,%b1,0
2252    vlr\t%v0,%v1
2253    vlvgb\t%v0,%1,0
2254    vlgvb\t%0,%v1,0
2255    vleb\t%v0,%1,0
2256    vsteb\t%v1,%0,0"
2257   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2258    (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2259    (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx")
2260    (set_attr "z10prop" "z10_fr_E1,
2261                         z10_fwd_A1,
2262                         z10_super_E1,
2263                         z10_super_E1,
2264                         z10_rec,
2265                         z10_rec,
2266                         z10_super,
2267                         z10_super,
2268                         *,*,*,*,*,*,*")])
2269
2270 (define_peephole2
2271   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2272         (mem:QI (match_operand 1 "address_operand" "")))]
2273   "GET_CODE (operands[1]) == SYMBOL_REF
2274    && CONSTANT_POOL_ADDRESS_P (operands[1])
2275    && get_pool_mode (operands[1]) == QImode
2276    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2277   [(set (match_dup 0) (match_dup 2))]
2278   "operands[2] = get_pool_constant (operands[1]);")
2279
2280 ;
2281 ; movstrictqi instruction pattern(s).
2282 ;
2283
2284 (define_insn "*movstrictqi"
2285   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2286                          (match_operand:QI 1 "memory_operand" "R,T"))]
2287   ""
2288   "@
2289    ic\t%0,%1
2290    icy\t%0,%1"
2291   [(set_attr "op_type"  "RX,RXY")
2292    (set_attr "cpu_facility" "*,longdisp")
2293    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2294
2295 ;
2296 ; movstricthi instruction pattern(s).
2297 ;
2298
2299 (define_insn "*movstricthi"
2300   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2301                          (match_operand:HI 1 "memory_operand" "Q,S"))
2302    (clobber (reg:CC CC_REGNUM))]
2303   ""
2304   "@
2305    icm\t%0,3,%S1
2306    icmy\t%0,3,%S1"
2307   [(set_attr "op_type" "RS,RSY")
2308    (set_attr "cpu_facility" "*,longdisp")
2309    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2310
2311 ;
2312 ; movstrictsi instruction pattern(s).
2313 ;
2314
2315 (define_insn "movstrictsi"
2316   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2317                          (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2318   "TARGET_ZARCH"
2319   "@
2320    lr\t%0,%1
2321    l\t%0,%1
2322    ly\t%0,%1
2323    ear\t%0,%1"
2324   [(set_attr "op_type" "RR,RX,RXY,RRE")
2325    (set_attr "type" "lr,load,load,*")
2326    (set_attr "cpu_facility" "*,*,longdisp,*")
2327    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2328
2329 ;
2330 ; mov(tf|td) instruction pattern(s).
2331 ;
2332
2333 (define_expand "mov<mode>"
2334   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2335         (match_operand:TD_TF 1 "general_operand"      ""))]
2336   ""
2337   "")
2338
2339 (define_insn "*mov<mode>_64"
2340   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
2341         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,S,d,dT,d"))]
2342   "TARGET_ZARCH"
2343   "@
2344    lzxr\t%0
2345    lxr\t%0,%1
2346    #
2347    #
2348    lmg\t%0,%N0,%S1
2349    stmg\t%1,%N1,%S0
2350    #
2351    #"
2352   [(set_attr "op_type"      "RRE,RRE,*,*,RSY,RSY,*,*")
2353    (set_attr "type"         "fsimptf,fsimptf,*,*,lm,stm,*,*")
2354    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2355
2356 (define_insn "*mov<mode>_31"
2357   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2358         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
2359   "!TARGET_ZARCH"
2360   "@
2361    lzxr\t%0
2362    lxr\t%0,%1
2363    #
2364    #"
2365   [(set_attr "op_type"      "RRE,RRE,*,*")
2366    (set_attr "type"         "fsimptf,fsimptf,*,*")
2367    (set_attr "cpu_facility" "z196,*,*,*")])
2368
2369 ; TFmode in GPRs splitters
2370
2371 (define_split
2372   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2373         (match_operand:TD_TF 1 "general_operand"      ""))]
2374   "TARGET_ZARCH && reload_completed
2375    && !s_operand (operands[0], <MODE>mode)
2376    && !s_operand (operands[1], <MODE>mode)
2377    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2378   [(set (match_dup 2) (match_dup 4))
2379    (set (match_dup 3) (match_dup 5))]
2380 {
2381   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2382   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2383   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2384   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2385 })
2386
2387 (define_split
2388   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2389         (match_operand:TD_TF 1 "general_operand"      ""))]
2390   "TARGET_ZARCH && reload_completed
2391    && !s_operand (operands[0], <MODE>mode)
2392    && !s_operand (operands[1], <MODE>mode)
2393    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2394   [(set (match_dup 2) (match_dup 4))
2395    (set (match_dup 3) (match_dup 5))]
2396 {
2397   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2398   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2399   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2400   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2401 })
2402
2403 (define_split
2404   [(set (match_operand:TD_TF 0 "register_operand" "")
2405         (match_operand:TD_TF 1 "memory_operand"   ""))]
2406   "TARGET_ZARCH && reload_completed
2407    && GENERAL_REG_P (operands[0])
2408    && !s_operand (operands[1], VOIDmode)"
2409   [(set (match_dup 0) (match_dup 1))]
2410 {
2411   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2412   addr = gen_lowpart (Pmode, addr);
2413   s390_load_address (addr, XEXP (operands[1], 0));
2414   operands[1] = replace_equiv_address (operands[1], addr);
2415 })
2416
2417 ; TFmode in BFPs splitters
2418
2419 (define_split
2420   [(set (match_operand:TD_TF 0 "register_operand" "")
2421         (match_operand:TD_TF 1 "memory_operand" ""))]
2422   "reload_completed && offsettable_memref_p (operands[1])
2423    && FP_REG_P (operands[0])"
2424   [(set (match_dup 2) (match_dup 4))
2425    (set (match_dup 3) (match_dup 5))]
2426 {
2427   operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2428                                      <MODE>mode, 0);
2429   operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2430                                      <MODE>mode, 8);
2431   operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2432   operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2433 })
2434
2435 (define_split
2436   [(set (match_operand:TD_TF 0 "memory_operand" "")
2437         (match_operand:TD_TF 1 "register_operand" ""))]
2438   "reload_completed && offsettable_memref_p (operands[0])
2439    && FP_REG_P (operands[1])"
2440   [(set (match_dup 2) (match_dup 4))
2441    (set (match_dup 3) (match_dup 5))]
2442 {
2443   operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2444   operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2445   operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2446                                      <MODE>mode, 0);
2447   operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2448                                      <MODE>mode, 8);
2449 })
2450
2451 ;
2452 ; mov(df|dd) instruction pattern(s).
2453 ;
2454
2455 (define_expand "mov<mode>"
2456   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2457         (match_operand:DD_DF 1 "general_operand"  ""))]
2458   ""
2459   "")
2460
2461 (define_insn "*mov<mode>_64dfp"
2462   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2463                                "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R")
2464         (match_operand:DD_DF 1 "general_operand"
2465                                " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))]
2466   "TARGET_DFP"
2467   "@
2468    lzdr\t%0
2469    ldr\t%0,%1
2470    ldgr\t%0,%1
2471    lgdr\t%0,%1
2472    ld\t%0,%1
2473    ldy\t%0,%1
2474    std\t%1,%0
2475    stdy\t%1,%0
2476    lghi\t%0,0
2477    lgr\t%0,%1
2478    lgrl\t%0,%1
2479    lg\t%0,%1
2480    stgrl\t%1,%0
2481    stg\t%1,%0
2482    vlr\t%v0,%v1
2483    vleig\t%v0,0,0
2484    vlvgg\t%v0,%1,0
2485    vlgvg\t%0,%v1,0
2486    vleg\t%0,%1,0
2487    vsteg\t%1,%0,0"
2488   [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2489    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2490                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store")
2491    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*")
2492    (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")])
2493
2494 (define_insn "*mov<mode>_64"
2495   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T")
2496         (match_operand:DD_DF 1 "general_operand"      " G,f,R,T,f,f,G,d,b,T,d,d"))]
2497   "TARGET_ZARCH"
2498   "@
2499    lzdr\t%0
2500    ldr\t%0,%1
2501    ld\t%0,%1
2502    ldy\t%0,%1
2503    std\t%1,%0
2504    stdy\t%1,%0
2505    lghi\t%0,0
2506    lgr\t%0,%1
2507    lgrl\t%0,%1
2508    lg\t%0,%1
2509    stgrl\t%1,%0
2510    stg\t%1,%0"
2511   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY")
2512    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2513                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2514    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2515    (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")])
2516
2517 (define_insn "*mov<mode>_31"
2518   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2519                                "=f,f,f,f,R,T,d,d,Q,S,  d,o")
2520         (match_operand:DD_DF 1 "general_operand"
2521                                " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
2522   "!TARGET_ZARCH"
2523   "@
2524    lzdr\t%0
2525    ldr\t%0,%1
2526    ld\t%0,%1
2527    ldy\t%0,%1
2528    std\t%1,%0
2529    stdy\t%1,%0
2530    lm\t%0,%N0,%S1
2531    lmy\t%0,%N0,%S1
2532    stm\t%1,%N1,%S0
2533    stmy\t%1,%N1,%S0
2534    #
2535    #"
2536   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2537    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2538                         fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2539    (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
2540
2541 (define_split
2542   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2543         (match_operand:DD_DF 1 "general_operand" ""))]
2544   "!TARGET_ZARCH && reload_completed
2545    && !s_operand (operands[0], <MODE>mode)
2546    && !s_operand (operands[1], <MODE>mode)
2547    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2548   [(set (match_dup 2) (match_dup 4))
2549    (set (match_dup 3) (match_dup 5))]
2550 {
2551   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2552   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2553   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2554   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2555 })
2556
2557 (define_split
2558   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2559         (match_operand:DD_DF 1 "general_operand" ""))]
2560   "!TARGET_ZARCH && reload_completed
2561    && !s_operand (operands[0], <MODE>mode)
2562    && !s_operand (operands[1], <MODE>mode)
2563    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2564   [(set (match_dup 2) (match_dup 4))
2565    (set (match_dup 3) (match_dup 5))]
2566 {
2567   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2568   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2569   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2570   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2571 })
2572
2573 (define_split
2574   [(set (match_operand:DD_DF 0 "register_operand" "")
2575         (match_operand:DD_DF 1 "memory_operand" ""))]
2576   "!TARGET_ZARCH && reload_completed
2577    && !FP_REG_P (operands[0])
2578    && !s_operand (operands[1], VOIDmode)"
2579   [(set (match_dup 0) (match_dup 1))]
2580 {
2581   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2582   s390_load_address (addr, XEXP (operands[1], 0));
2583   operands[1] = replace_equiv_address (operands[1], addr);
2584 })
2585
2586 ;
2587 ; mov(sf|sd) instruction pattern(s).
2588 ;
2589
2590 (define_insn "mov<mode>"
2591   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2592                                "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
2593         (match_operand:SD_SF 1 "general_operand"
2594                                " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
2595   ""
2596   "@
2597    lzer\t%0
2598    ldr\t%0,%1
2599    ler\t%0,%1
2600    lde\t%0,%1
2601    le\t%0,%1
2602    ley\t%0,%1
2603    ste\t%1,%0
2604    stey\t%1,%0
2605    lhi\t%0,0
2606    lr\t%0,%1
2607    lrl\t%0,%1
2608    l\t%0,%1
2609    ly\t%0,%1
2610    strl\t%1,%0
2611    st\t%1,%0
2612    sty\t%1,%0
2613    vlr\t%v0,%v1
2614    vleif\t%v0,0,0
2615    vlvgf\t%v0,%1,0
2616    vlgvf\t%0,%v1,0
2617    vlef\t%0,%1,0
2618    vstef\t%1,%0,0"
2619   [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2620    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2621                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2622    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2623    (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")])
2624
2625 ;
2626 ; movcc instruction pattern
2627 ;
2628
2629 (define_insn "movcc"
2630   [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2631         (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2632   ""
2633   "@
2634    lr\t%0,%1
2635    tmh\t%1,12288
2636    ipm\t%0
2637    l\t%0,%1
2638    ly\t%0,%1
2639    st\t%1,%0
2640    sty\t%1,%0"
2641   [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2642    (set_attr "type" "lr,*,*,load,load,store,store")
2643    (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
2644    (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2645    (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2646
2647 ;
2648 ; Block move (MVC) patterns.
2649 ;
2650
2651 (define_insn "*mvc"
2652   [(set (match_operand:BLK 0 "memory_operand" "=Q")
2653         (match_operand:BLK 1 "memory_operand" "Q"))
2654    (use (match_operand 2 "const_int_operand" "n"))]
2655   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2656   "mvc\t%O0(%2,%R0),%S1"
2657   [(set_attr "op_type" "SS")])
2658
2659 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2660 ; order to have it implemented with mvc.
2661
2662 (define_split
2663   [(set (match_operand:QI 0 "memory_operand" "")
2664         (match_operand:QI 1 "memory_operand" ""))]
2665   "reload_completed"
2666   [(parallel
2667     [(set (match_dup 0) (match_dup 1))
2668      (use (const_int 1))])]
2669 {
2670   operands[0] = adjust_address (operands[0], BLKmode, 0);
2671   operands[1] = adjust_address (operands[1], BLKmode, 0);
2672 })
2673
2674
2675 (define_peephole2
2676   [(parallel
2677     [(set (match_operand:BLK 0 "memory_operand" "")
2678           (match_operand:BLK 1 "memory_operand" ""))
2679      (use (match_operand 2 "const_int_operand" ""))])
2680    (parallel
2681     [(set (match_operand:BLK 3 "memory_operand" "")
2682           (match_operand:BLK 4 "memory_operand" ""))
2683      (use (match_operand 5 "const_int_operand" ""))])]
2684   "s390_offset_p (operands[0], operands[3], operands[2])
2685    && s390_offset_p (operands[1], operands[4], operands[2])
2686    && !s390_overlap_p (operands[0], operands[1],
2687                        INTVAL (operands[2]) + INTVAL (operands[5]))
2688    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2689   [(parallel
2690     [(set (match_dup 6) (match_dup 7))
2691      (use (match_dup 8))])]
2692   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2693    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2694    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2695
2696
2697 ;
2698 ; load_multiple pattern(s).
2699 ;
2700 ; ??? Due to reload problems with replacing registers inside match_parallel
2701 ; we currently support load_multiple/store_multiple only after reload.
2702 ;
2703
2704 (define_expand "load_multiple"
2705   [(match_par_dup 3 [(set (match_operand 0 "" "")
2706                           (match_operand 1 "" ""))
2707                      (use (match_operand 2 "" ""))])]
2708   "reload_completed"
2709 {
2710   machine_mode mode;
2711   int regno;
2712   int count;
2713   rtx from;
2714   int i, off;
2715
2716   /* Support only loading a constant number of fixed-point registers from
2717      memory and only bother with this if more than two */
2718   if (GET_CODE (operands[2]) != CONST_INT
2719       || INTVAL (operands[2]) < 2
2720       || INTVAL (operands[2]) > 16
2721       || GET_CODE (operands[1]) != MEM
2722       || GET_CODE (operands[0]) != REG
2723       || REGNO (operands[0]) >= 16)
2724     FAIL;
2725
2726   count = INTVAL (operands[2]);
2727   regno = REGNO (operands[0]);
2728   mode = GET_MODE (operands[0]);
2729   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2730     FAIL;
2731
2732   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2733   if (!can_create_pseudo_p ())
2734     {
2735       if (GET_CODE (XEXP (operands[1], 0)) == REG)
2736         {
2737           from = XEXP (operands[1], 0);
2738           off = 0;
2739         }
2740       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2741                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2742                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2743         {
2744           from = XEXP (XEXP (operands[1], 0), 0);
2745           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2746         }
2747       else
2748         FAIL;
2749     }
2750   else
2751     {
2752       from = force_reg (Pmode, XEXP (operands[1], 0));
2753       off = 0;
2754     }
2755
2756   for (i = 0; i < count; i++)
2757     XVECEXP (operands[3], 0, i)
2758       = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2759                      change_address (operands[1], mode,
2760                        plus_constant (Pmode, from,
2761                                       off + i * GET_MODE_SIZE (mode))));
2762 })
2763
2764 (define_insn "*load_multiple_di"
2765   [(match_parallel 0 "load_multiple_operation"
2766                    [(set (match_operand:DI 1 "register_operand" "=r")
2767                          (match_operand:DI 2 "s_operand" "S"))])]
2768   "reload_completed && TARGET_ZARCH"
2769 {
2770   int words = XVECLEN (operands[0], 0);
2771   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2772   return "lmg\t%1,%0,%S2";
2773 }
2774    [(set_attr "op_type" "RSY")
2775     (set_attr "type"    "lm")])
2776
2777 (define_insn "*load_multiple_si"
2778   [(match_parallel 0 "load_multiple_operation"
2779                    [(set (match_operand:SI 1 "register_operand" "=r,r")
2780                          (match_operand:SI 2 "s_operand" "Q,S"))])]
2781   "reload_completed"
2782 {
2783   int words = XVECLEN (operands[0], 0);
2784   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2785   return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2786 }
2787    [(set_attr "op_type" "RS,RSY")
2788     (set_attr "cpu_facility" "*,longdisp")
2789     (set_attr "type"    "lm")])
2790
2791 ;
2792 ; store multiple pattern(s).
2793 ;
2794
2795 (define_expand "store_multiple"
2796   [(match_par_dup 3 [(set (match_operand 0 "" "")
2797                           (match_operand 1 "" ""))
2798                      (use (match_operand 2 "" ""))])]
2799   "reload_completed"
2800 {
2801   machine_mode mode;
2802   int regno;
2803   int count;
2804   rtx to;
2805   int i, off;
2806
2807   /* Support only storing a constant number of fixed-point registers to
2808      memory and only bother with this if more than two.  */
2809   if (GET_CODE (operands[2]) != CONST_INT
2810       || INTVAL (operands[2]) < 2
2811       || INTVAL (operands[2]) > 16
2812       || GET_CODE (operands[0]) != MEM
2813       || GET_CODE (operands[1]) != REG
2814       || REGNO (operands[1]) >= 16)
2815     FAIL;
2816
2817   count = INTVAL (operands[2]);
2818   regno = REGNO (operands[1]);
2819   mode = GET_MODE (operands[1]);
2820   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2821     FAIL;
2822
2823   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2824
2825   if (!can_create_pseudo_p ())
2826     {
2827       if (GET_CODE (XEXP (operands[0], 0)) == REG)
2828         {
2829           to = XEXP (operands[0], 0);
2830           off = 0;
2831         }
2832       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2833                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2834                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2835         {
2836           to = XEXP (XEXP (operands[0], 0), 0);
2837           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2838         }
2839       else
2840         FAIL;
2841     }
2842   else
2843     {
2844       to = force_reg (Pmode, XEXP (operands[0], 0));
2845       off = 0;
2846     }
2847
2848   for (i = 0; i < count; i++)
2849     XVECEXP (operands[3], 0, i)
2850       = gen_rtx_SET (change_address (operands[0], mode,
2851                        plus_constant (Pmode, to,
2852                                       off + i * GET_MODE_SIZE (mode))),
2853                      gen_rtx_REG (mode, regno + i));
2854 })
2855
2856 (define_insn "*store_multiple_di"
2857   [(match_parallel 0 "store_multiple_operation"
2858                    [(set (match_operand:DI 1 "s_operand" "=S")
2859                          (match_operand:DI 2 "register_operand" "r"))])]
2860   "reload_completed && TARGET_ZARCH"
2861 {
2862   int words = XVECLEN (operands[0], 0);
2863   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2864   return "stmg\t%2,%0,%S1";
2865 }
2866    [(set_attr "op_type" "RSY")
2867     (set_attr "type"    "stm")])
2868
2869
2870 (define_insn "*store_multiple_si"
2871   [(match_parallel 0 "store_multiple_operation"
2872                    [(set (match_operand:SI 1 "s_operand" "=Q,S")
2873                          (match_operand:SI 2 "register_operand" "r,r"))])]
2874   "reload_completed"
2875 {
2876   int words = XVECLEN (operands[0], 0);
2877   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2878   return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2879 }
2880    [(set_attr "op_type" "RS,RSY")
2881     (set_attr "cpu_facility" "*,longdisp")
2882     (set_attr "type"    "stm")])
2883
2884 ;;
2885 ;; String instructions.
2886 ;;
2887
2888 (define_insn "*execute_rl"
2889   [(match_parallel 0 "execute_operation"
2890     [(unspec [(match_operand 1    "register_operand" "a")
2891               (match_operand 2    "" "")
2892               (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2893   "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2894    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2895   "exrl\t%1,%3"
2896   [(set_attr "op_type" "RIL")
2897    (set_attr "type"    "cs")])
2898
2899 (define_insn "*execute"
2900   [(match_parallel 0 "execute_operation"
2901     [(unspec [(match_operand 1 "register_operand" "a")
2902               (match_operand:BLK 2 "memory_operand" "R")
2903               (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2904   "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2905    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2906   "ex\t%1,%2"
2907   [(set_attr "op_type" "RX")
2908    (set_attr "type" "cs")])
2909
2910
2911 ;
2912 ; strlenM instruction pattern(s).
2913 ;
2914
2915 (define_expand "strlen<mode>"
2916   [(match_operand:P   0 "register_operand" "")  ; result
2917    (match_operand:BLK 1 "memory_operand" "")    ; input string
2918    (match_operand:SI  2 "immediate_operand" "") ; search character
2919    (match_operand:SI  3 "immediate_operand" "")] ; known alignment
2920   ""
2921 {
2922   if (!TARGET_VX || operands[2] != const0_rtx)
2923     emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2924                                       operands[2], operands[3]));
2925   else
2926     s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2927
2928   DONE;
2929 })
2930
2931 (define_expand "strlen_srst<mode>"
2932   [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2933    (parallel
2934     [(set (match_dup 4)
2935           (unspec:P [(const_int 0)
2936                       (match_operand:BLK 1 "memory_operand" "")
2937                       (reg:SI 0)
2938                       (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2939      (clobber (scratch:P))
2940      (clobber (reg:CC CC_REGNUM))])
2941    (parallel
2942     [(set (match_operand:P 0 "register_operand" "")
2943           (minus:P (match_dup 4) (match_dup 5)))
2944      (clobber (reg:CC CC_REGNUM))])]
2945   ""
2946 {
2947   operands[4] = gen_reg_rtx (Pmode);
2948   operands[5] = gen_reg_rtx (Pmode);
2949   emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2950   operands[1] = replace_equiv_address (operands[1], operands[5]);
2951 })
2952
2953 (define_insn "*strlen<mode>"
2954   [(set (match_operand:P 0 "register_operand" "=a")
2955         (unspec:P [(match_operand:P 2 "general_operand" "0")
2956                     (mem:BLK (match_operand:P 3 "register_operand" "1"))
2957                     (reg:SI 0)
2958                     (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2959    (clobber (match_scratch:P 1 "=a"))
2960    (clobber (reg:CC CC_REGNUM))]
2961   ""
2962   "srst\t%0,%1\;jo\t.-4"
2963   [(set_attr "length" "8")
2964    (set_attr "type" "vs")])
2965
2966 ;
2967 ; cmpstrM instruction pattern(s).
2968 ;
2969
2970 (define_expand "cmpstrsi"
2971   [(set (reg:SI 0) (const_int 0))
2972    (parallel
2973     [(clobber (match_operand 3 "" ""))
2974      (clobber (match_dup 4))
2975      (set (reg:CCU CC_REGNUM)
2976           (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2977                        (match_operand:BLK 2 "memory_operand" "")))
2978      (use (reg:SI 0))])
2979    (parallel
2980     [(set (match_operand:SI 0 "register_operand" "=d")
2981           (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2982      (clobber (reg:CC CC_REGNUM))])]
2983   ""
2984 {
2985   /* As the result of CMPINT is inverted compared to what we need,
2986      we have to swap the operands.  */
2987   rtx op1 = operands[2];
2988   rtx op2 = operands[1];
2989   rtx addr1 = gen_reg_rtx (Pmode);
2990   rtx addr2 = gen_reg_rtx (Pmode);
2991
2992   emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2993   emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2994   operands[1] = replace_equiv_address_nv (op1, addr1);
2995   operands[2] = replace_equiv_address_nv (op2, addr2);
2996   operands[3] = addr1;
2997   operands[4] = addr2;
2998 })
2999
3000 (define_insn "*cmpstr<mode>"
3001   [(clobber (match_operand:P 0 "register_operand" "=d"))
3002    (clobber (match_operand:P 1 "register_operand" "=d"))
3003    (set (reg:CCU CC_REGNUM)
3004         (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
3005                      (mem:BLK (match_operand:P 3 "register_operand" "1"))))
3006    (use (reg:SI 0))]
3007   ""
3008   "clst\t%0,%1\;jo\t.-4"
3009   [(set_attr "length" "8")
3010    (set_attr "type" "vs")])
3011
3012 ;
3013 ; movstr instruction pattern.
3014 ;
3015
3016 (define_expand "movstr"
3017   [(match_operand 0 "register_operand" "")
3018    (match_operand 1 "memory_operand" "")
3019    (match_operand 2 "memory_operand" "")]
3020   ""
3021 {
3022   if (TARGET_64BIT)
3023     emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
3024   else
3025     emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
3026   DONE;
3027 })
3028
3029 (define_expand "movstr<P:mode>"
3030   [(set (reg:SI 0) (const_int 0))
3031    (parallel
3032     [(clobber (match_dup 3))
3033      (set (match_operand:BLK 1 "memory_operand" "")
3034           (match_operand:BLK 2 "memory_operand" ""))
3035      (set (match_operand:P 0 "register_operand" "")
3036           (unspec:P [(match_dup 1)
3037                    (match_dup 2)
3038                    (reg:SI 0)] UNSPEC_MVST))
3039      (clobber (reg:CC CC_REGNUM))])]
3040   ""
3041 {
3042   rtx addr1, addr2;
3043
3044   if (TARGET_VX && optimize_function_for_speed_p (cfun))
3045     {
3046       s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
3047       DONE;
3048     }
3049
3050   addr1 = gen_reg_rtx (Pmode);
3051   addr2 = gen_reg_rtx (Pmode);
3052
3053   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3054   emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
3055   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3056   operands[2] = replace_equiv_address_nv (operands[2], addr2);
3057   operands[3] = addr2;
3058 })
3059
3060 (define_insn "*movstr"
3061   [(clobber (match_operand:P 2 "register_operand" "=d"))
3062    (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
3063         (mem:BLK (match_operand:P 3 "register_operand" "2")))
3064    (set (match_operand:P 0 "register_operand" "=d")
3065         (unspec:P [(mem:BLK (match_dup 1))
3066                  (mem:BLK (match_dup 3))
3067                  (reg:SI 0)] UNSPEC_MVST))
3068    (clobber (reg:CC CC_REGNUM))]
3069   ""
3070   "mvst\t%1,%2\;jo\t.-4"
3071   [(set_attr "length" "8")
3072    (set_attr "type" "vs")])
3073
3074
3075 ;
3076 ; movmemM instruction pattern(s).
3077 ;
3078
3079 (define_expand "movmem<mode>"
3080   [(set (match_operand:BLK 0 "memory_operand" "")   ; destination
3081         (match_operand:BLK 1 "memory_operand" ""))  ; source
3082    (use (match_operand:GPR 2 "general_operand" "")) ; count
3083    (match_operand 3 "" "")]
3084   ""
3085 {
3086   if (s390_expand_movmem (operands[0], operands[1], operands[2]))
3087     DONE;
3088   else
3089     FAIL;
3090 })
3091
3092 ; Move a block that is up to 256 bytes in length.
3093 ; The block length is taken as (operands[2] % 256) + 1.
3094
3095 (define_expand "movmem_short"
3096   [(parallel
3097     [(set (match_operand:BLK 0 "memory_operand" "")
3098           (match_operand:BLK 1 "memory_operand" ""))
3099      (use (match_operand 2 "nonmemory_operand" ""))
3100      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3101      (clobber (match_dup 3))])]
3102   ""
3103   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3104
3105 (define_insn "*movmem_short"
3106   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3107         (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3108    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3109    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3110    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3111   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3112   "#"
3113   [(set_attr "type"         "cs")
3114    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3115
3116 (define_split
3117   [(set (match_operand:BLK 0 "memory_operand" "")
3118         (match_operand:BLK 1 "memory_operand" ""))
3119    (use (match_operand 2 "const_int_operand" ""))
3120    (use (match_operand 3 "immediate_operand" ""))
3121    (clobber (scratch))]
3122   "reload_completed"
3123   [(parallel
3124     [(set (match_dup 0) (match_dup 1))
3125      (use (match_dup 2))])]
3126   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3127
3128 (define_split
3129   [(set (match_operand:BLK 0 "memory_operand" "")
3130         (match_operand:BLK 1 "memory_operand" ""))
3131    (use (match_operand 2 "register_operand" ""))
3132    (use (match_operand 3 "memory_operand" ""))
3133    (clobber (scratch))]
3134   "reload_completed"
3135   [(parallel
3136     [(unspec [(match_dup 2) (match_dup 3)
3137               (const_int 0)] UNSPEC_EXECUTE)
3138      (set (match_dup 0) (match_dup 1))
3139      (use (const_int 1))])]
3140   "")
3141
3142 (define_split
3143   [(set (match_operand:BLK 0 "memory_operand" "")
3144         (match_operand:BLK 1 "memory_operand" ""))
3145    (use (match_operand 2 "register_operand" ""))
3146    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3147    (clobber (scratch))]
3148   "TARGET_Z10 && reload_completed"
3149   [(parallel
3150     [(unspec [(match_dup 2) (const_int 0)
3151               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3152      (set (match_dup 0) (match_dup 1))
3153      (use (const_int 1))])]
3154   "operands[3] = gen_label_rtx ();")
3155
3156 (define_split
3157   [(set (match_operand:BLK 0 "memory_operand" "")
3158         (match_operand:BLK 1 "memory_operand" ""))
3159    (use (match_operand 2 "register_operand" ""))
3160    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3161    (clobber (match_operand 3 "register_operand" ""))]
3162   "reload_completed && TARGET_CPU_ZARCH"
3163   [(set (match_dup 3) (label_ref (match_dup 4)))
3164    (parallel
3165     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3166               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3167      (set (match_dup 0) (match_dup 1))
3168      (use (const_int 1))])]
3169   "operands[4] = gen_label_rtx ();")
3170
3171 ; Move a block of arbitrary length.
3172
3173 (define_expand "movmem_long"
3174   [(parallel
3175     [(clobber (match_dup 2))
3176      (clobber (match_dup 3))
3177      (set (match_operand:BLK 0 "memory_operand" "")
3178           (match_operand:BLK 1 "memory_operand" ""))
3179      (use (match_operand 2 "general_operand" ""))
3180      (use (match_dup 3))
3181      (clobber (reg:CC CC_REGNUM))])]
3182   ""
3183 {
3184   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3185   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3186   rtx reg0 = gen_reg_rtx (dreg_mode);
3187   rtx reg1 = gen_reg_rtx (dreg_mode);
3188   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3189   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3190   rtx len0 = gen_lowpart (Pmode, reg0);
3191   rtx len1 = gen_lowpart (Pmode, reg1);
3192
3193   emit_clobber (reg0);
3194   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3195   emit_move_insn (len0, operands[2]);
3196
3197   emit_clobber (reg1);
3198   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3199   emit_move_insn (len1, operands[2]);
3200
3201   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3202   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3203   operands[2] = reg0;
3204   operands[3] = reg1;
3205 })
3206
3207 (define_insn "*movmem_long"
3208   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3209    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3210    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3211         (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3212    (use (match_dup 2))
3213    (use (match_dup 3))
3214    (clobber (reg:CC CC_REGNUM))]
3215   "TARGET_64BIT || !TARGET_ZARCH"
3216   "mvcle\t%0,%1,0\;jo\t.-4"
3217   [(set_attr "length" "8")
3218    (set_attr "type" "vs")])
3219
3220 (define_insn "*movmem_long_31z"
3221   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3222    (clobber (match_operand:TI 1 "register_operand" "=d"))
3223    (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3224         (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3225    (use (match_dup 2))
3226    (use (match_dup 3))
3227    (clobber (reg:CC CC_REGNUM))]
3228   "!TARGET_64BIT && TARGET_ZARCH"
3229   "mvcle\t%0,%1,0\;jo\t.-4"
3230   [(set_attr "length" "8")
3231    (set_attr "type" "vs")])
3232
3233
3234 ;
3235 ; Test data class.
3236 ;
3237
3238 (define_expand "signbit<mode>2"
3239   [(set (reg:CCZ CC_REGNUM)
3240         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3241                      (match_dup 2)]
3242                      UNSPEC_TDC_INSN))
3243    (set (match_operand:SI 0 "register_operand" "=d")
3244         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3245   "TARGET_HARD_FLOAT"
3246 {
3247   operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3248 })
3249
3250 (define_expand "isinf<mode>2"
3251   [(set (reg:CCZ CC_REGNUM)
3252         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3253                      (match_dup 2)]
3254                      UNSPEC_TDC_INSN))
3255    (set (match_operand:SI 0 "register_operand" "=d")
3256         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3257   "TARGET_HARD_FLOAT"
3258 {
3259   operands[2] = GEN_INT (S390_TDC_INFINITY);
3260 })
3261
3262 ; This extracts CC into a GPR properly shifted.  The actual IPM
3263 ; instruction will be issued by reload.  The constraint of operand 1
3264 ; forces reload to use a GPR.  So reload will issue a movcc insn for
3265 ; copying CC into a GPR first.
3266 (define_insn_and_split "*cc_to_int"
3267   [(set (match_operand:SI 0 "nonimmediate_operand"     "=d")
3268         (unspec:SI [(match_operand 1 "register_operand" "0")]
3269                    UNSPEC_CC_TO_INT))]
3270   "operands != NULL"
3271   "#"
3272   "reload_completed"
3273   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3274
3275 ; This insn is used to generate all variants of the Test Data Class
3276 ; instruction, namely tcxb, tcdb, and tceb.  The insn's first operand
3277 ; is the register to be tested and the second one is the bit mask
3278 ; specifying the required test(s).
3279 ;
3280 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3281 (define_insn "*TDC_insn_<mode>"
3282   [(set (reg:CCZ CC_REGNUM)
3283         (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3284                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3285   "TARGET_HARD_FLOAT"
3286   "t<_d>c<xde><bt>\t%0,%1"
3287    [(set_attr "op_type" "RXE")
3288     (set_attr "type"  "fsimp<mode>")])
3289
3290
3291
3292 ;
3293 ; setmemM instruction pattern(s).
3294 ;
3295
3296 (define_expand "setmem<mode>"
3297   [(set (match_operand:BLK 0 "memory_operand" "")
3298         (match_operand:QI 2 "general_operand" ""))
3299    (use (match_operand:GPR 1 "general_operand" ""))
3300    (match_operand 3 "" "")]
3301   ""
3302   "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3303
3304 ; Clear a block that is up to 256 bytes in length.
3305 ; The block length is taken as (operands[1] % 256) + 1.
3306
3307 (define_expand "clrmem_short"
3308   [(parallel
3309     [(set (match_operand:BLK 0 "memory_operand" "")
3310           (const_int 0))
3311      (use (match_operand 1 "nonmemory_operand" ""))
3312      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3313      (clobber (match_dup 2))
3314      (clobber (reg:CC CC_REGNUM))])]
3315   ""
3316   "operands[2] = gen_rtx_SCRATCH (Pmode);")
3317
3318 (define_insn "*clrmem_short"
3319   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3320         (const_int 0))
3321    (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3322    (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3323    (clobber (match_scratch:P 3 "=X,X,X,&a"))
3324    (clobber (reg:CC CC_REGNUM))]
3325   "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3326   "#"
3327   [(set_attr "type" "cs")
3328    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3329
3330 (define_split
3331   [(set (match_operand:BLK 0 "memory_operand" "")
3332         (const_int 0))
3333    (use (match_operand 1 "const_int_operand" ""))
3334    (use (match_operand 2 "immediate_operand" ""))
3335    (clobber (scratch))
3336    (clobber (reg:CC CC_REGNUM))]
3337   "reload_completed"
3338   [(parallel
3339     [(set (match_dup 0) (const_int 0))
3340      (use (match_dup 1))
3341      (clobber (reg:CC CC_REGNUM))])]
3342   "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3343
3344 (define_split
3345   [(set (match_operand:BLK 0 "memory_operand" "")
3346         (const_int 0))
3347    (use (match_operand 1 "register_operand" ""))
3348    (use (match_operand 2 "memory_operand" ""))
3349    (clobber (scratch))
3350    (clobber (reg:CC CC_REGNUM))]
3351   "reload_completed"
3352   [(parallel
3353     [(unspec [(match_dup 1) (match_dup 2)
3354               (const_int 0)] UNSPEC_EXECUTE)
3355      (set (match_dup 0) (const_int 0))
3356      (use (const_int 1))
3357      (clobber (reg:CC CC_REGNUM))])]
3358   "")
3359
3360 (define_split
3361   [(set (match_operand:BLK 0 "memory_operand" "")
3362         (const_int 0))
3363    (use (match_operand 1 "register_operand" ""))
3364    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3365    (clobber (scratch))
3366    (clobber (reg:CC CC_REGNUM))]
3367   "TARGET_Z10 && reload_completed"
3368   [(parallel
3369     [(unspec [(match_dup 1) (const_int 0)
3370               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3371      (set (match_dup 0) (const_int 0))
3372      (use (const_int 1))
3373      (clobber (reg:CC CC_REGNUM))])]
3374   "operands[3] = gen_label_rtx ();")
3375
3376 (define_split
3377   [(set (match_operand:BLK 0 "memory_operand" "")
3378         (const_int 0))
3379    (use (match_operand 1 "register_operand" ""))
3380    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3381    (clobber (match_operand 2 "register_operand" ""))
3382    (clobber (reg:CC CC_REGNUM))]
3383   "reload_completed && TARGET_CPU_ZARCH"
3384   [(set (match_dup 2) (label_ref (match_dup 3)))
3385    (parallel
3386     [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3387               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3388      (set (match_dup 0) (const_int 0))
3389      (use (const_int 1))
3390      (clobber (reg:CC CC_REGNUM))])]
3391   "operands[3] = gen_label_rtx ();")
3392
3393 ; Initialize a block of arbitrary length with (operands[2] % 256).
3394
3395 (define_expand "setmem_long_<P:mode>"
3396   [(parallel
3397     [(clobber (match_dup 1))
3398      (set (match_operand:BLK 0 "memory_operand" "")
3399           (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
3400                       (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3401      (use (match_dup 3))
3402      (clobber (reg:CC CC_REGNUM))])]
3403   ""
3404 {
3405   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3406   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3407   rtx reg0 = gen_reg_rtx (dreg_mode);
3408   rtx reg1 = gen_reg_rtx (dreg_mode);
3409   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3410   rtx len0 = gen_lowpart (Pmode, reg0);
3411
3412   emit_clobber (reg0);
3413   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3414   emit_move_insn (len0, operands[1]);
3415
3416   emit_move_insn (reg1, const0_rtx);
3417
3418   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3419   operands[1] = reg0;
3420   operands[3] = reg1;
3421   operands[4] = gen_lowpart (Pmode, operands[1]);
3422 })
3423
3424 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3425
3426 (define_insn "*setmem_long"
3427   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3428    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3429         (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
3430                      (subreg:P (match_dup 3) <modesize>)]
3431                      UNSPEC_REPLICATE_BYTE))
3432    (use (match_operand:<DBL> 1 "register_operand" "d"))
3433    (clobber (reg:CC CC_REGNUM))]
3434   "TARGET_64BIT || !TARGET_ZARCH"
3435   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3436   [(set_attr "length" "8")
3437    (set_attr "type" "vs")])
3438
3439 (define_insn "*setmem_long_and"
3440   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3441    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3442         (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y"))
3443                     (subreg:P (match_dup 3) <modesize>)]
3444                     UNSPEC_REPLICATE_BYTE))
3445    (use (match_operand:<DBL> 1 "register_operand" "d"))
3446    (clobber (reg:CC CC_REGNUM))]
3447   "(TARGET_64BIT || !TARGET_ZARCH)"
3448   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3449   [(set_attr "length" "8")
3450    (set_attr "type" "vs")])
3451
3452 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3453 ; of the SImode subregs.
3454
3455 (define_insn "*setmem_long_31z"
3456   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3457    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3458         (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
3459                      (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3460    (use (match_operand:TI 1 "register_operand" "d"))
3461    (clobber (reg:CC CC_REGNUM))]
3462   "!TARGET_64BIT && TARGET_ZARCH"
3463   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3464   [(set_attr "length" "8")
3465    (set_attr "type" "vs")])
3466
3467 (define_insn "*setmem_long_and_31z"
3468   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3469    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3470         (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y"))
3471                     (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3472    (use (match_operand:TI 1 "register_operand" "d"))
3473    (clobber (reg:CC CC_REGNUM))]
3474   "(!TARGET_64BIT && TARGET_ZARCH)"
3475   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3476   [(set_attr "length" "8")
3477    (set_attr "type" "vs")])
3478
3479 ;
3480 ; cmpmemM instruction pattern(s).
3481 ;
3482
3483 (define_expand "cmpmemsi"
3484   [(set (match_operand:SI 0 "register_operand" "")
3485         (compare:SI (match_operand:BLK 1 "memory_operand" "")
3486                     (match_operand:BLK 2 "memory_operand" "") ) )
3487    (use (match_operand:SI 3 "general_operand" ""))
3488    (use (match_operand:SI 4 "" ""))]
3489   ""
3490 {
3491   if (s390_expand_cmpmem (operands[0], operands[1],
3492                           operands[2], operands[3]))
3493     DONE;
3494   else
3495     FAIL;
3496 })
3497
3498 ; Compare a block that is up to 256 bytes in length.
3499 ; The block length is taken as (operands[2] % 256) + 1.
3500
3501 (define_expand "cmpmem_short"
3502   [(parallel
3503     [(set (reg:CCU CC_REGNUM)
3504           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3505                        (match_operand:BLK 1 "memory_operand" "")))
3506      (use (match_operand 2 "nonmemory_operand" ""))
3507      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3508      (clobber (match_dup 3))])]
3509   ""
3510   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3511
3512 (define_insn "*cmpmem_short"
3513   [(set (reg:CCU CC_REGNUM)
3514         (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3515                      (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3516    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3517    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3518    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3519   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3520   "#"
3521   [(set_attr "type" "cs")
3522    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3523
3524 (define_split
3525   [(set (reg:CCU CC_REGNUM)
3526         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3527                      (match_operand:BLK 1 "memory_operand" "")))
3528    (use (match_operand 2 "const_int_operand" ""))
3529    (use (match_operand 3 "immediate_operand" ""))
3530    (clobber (scratch))]
3531   "reload_completed"
3532   [(parallel
3533     [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3534      (use (match_dup 2))])]
3535   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3536
3537 (define_split
3538   [(set (reg:CCU CC_REGNUM)
3539         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3540                      (match_operand:BLK 1 "memory_operand" "")))
3541    (use (match_operand 2 "register_operand" ""))
3542    (use (match_operand 3 "memory_operand" ""))
3543    (clobber (scratch))]
3544   "reload_completed"
3545   [(parallel
3546     [(unspec [(match_dup 2) (match_dup 3)
3547               (const_int 0)] UNSPEC_EXECUTE)
3548      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3549      (use (const_int 1))])]
3550   "")
3551
3552 (define_split
3553   [(set (reg:CCU CC_REGNUM)
3554         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3555                      (match_operand:BLK 1 "memory_operand" "")))
3556    (use (match_operand 2 "register_operand" ""))
3557    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3558    (clobber (scratch))]
3559   "TARGET_Z10 && reload_completed"
3560   [(parallel
3561     [(unspec [(match_dup 2) (const_int 0)
3562               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3563      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3564      (use (const_int 1))])]
3565   "operands[4] = gen_label_rtx ();")
3566
3567 (define_split
3568   [(set (reg:CCU CC_REGNUM)
3569         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3570                      (match_operand:BLK 1 "memory_operand" "")))
3571    (use (match_operand 2 "register_operand" ""))
3572    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3573    (clobber (match_operand 3 "register_operand" ""))]
3574   "reload_completed && TARGET_CPU_ZARCH"
3575   [(set (match_dup 3) (label_ref (match_dup 4)))
3576    (parallel
3577     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3578               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3579      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3580      (use (const_int 1))])]
3581   "operands[4] = gen_label_rtx ();")
3582
3583 ; Compare a block of arbitrary length.
3584
3585 (define_expand "cmpmem_long"
3586   [(parallel
3587     [(clobber (match_dup 2))
3588      (clobber (match_dup 3))
3589      (set (reg:CCU CC_REGNUM)
3590           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3591                        (match_operand:BLK 1 "memory_operand" "")))
3592      (use (match_operand 2 "general_operand" ""))
3593      (use (match_dup 3))])]
3594   ""
3595 {
3596   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3597   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3598   rtx reg0 = gen_reg_rtx (dreg_mode);
3599   rtx reg1 = gen_reg_rtx (dreg_mode);
3600   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3601   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3602   rtx len0 = gen_lowpart (Pmode, reg0);
3603   rtx len1 = gen_lowpart (Pmode, reg1);
3604
3605   emit_clobber (reg0);
3606   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3607   emit_move_insn (len0, operands[2]);
3608
3609   emit_clobber (reg1);
3610   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3611   emit_move_insn (len1, operands[2]);
3612
3613   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3614   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3615   operands[2] = reg0;
3616   operands[3] = reg1;
3617 })
3618
3619 (define_insn "*cmpmem_long"
3620   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3621    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3622    (set (reg:CCU CC_REGNUM)
3623         (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3624                      (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3625    (use (match_dup 2))
3626    (use (match_dup 3))]
3627   "TARGET_64BIT || !TARGET_ZARCH"
3628   "clcle\t%0,%1,0\;jo\t.-4"
3629   [(set_attr "length" "8")
3630    (set_attr "type" "vs")])
3631
3632 (define_insn "*cmpmem_long_31z"
3633   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3634    (clobber (match_operand:TI 1 "register_operand" "=d"))
3635    (set (reg:CCU CC_REGNUM)
3636         (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3637                      (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3638    (use (match_dup 2))
3639    (use (match_dup 3))]
3640   "!TARGET_64BIT && TARGET_ZARCH"
3641   "clcle\t%0,%1,0\;jo\t.-4"
3642   [(set_attr "op_type" "NN")
3643    (set_attr "type"    "vs")
3644    (set_attr "length"  "8")])
3645
3646 ; Convert CCUmode condition code to integer.
3647 ; Result is zero if EQ, positive if LTU, negative if GTU.
3648
3649 (define_insn_and_split "cmpint"
3650   [(set (match_operand:SI 0 "register_operand" "=d")
3651         (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3652                    UNSPEC_STRCMPCC_TO_INT))
3653    (clobber (reg:CC CC_REGNUM))]
3654   ""
3655   "#"
3656   "reload_completed"
3657   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3658    (parallel
3659     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3660      (clobber (reg:CC CC_REGNUM))])])
3661
3662 (define_insn_and_split "*cmpint_cc"
3663   [(set (reg CC_REGNUM)
3664         (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3665                             UNSPEC_STRCMPCC_TO_INT)
3666                  (const_int 0)))
3667    (set (match_operand:SI 0 "register_operand" "=d")
3668         (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3669   "s390_match_ccmode (insn, CCSmode)"
3670   "#"
3671   "&& reload_completed"
3672   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3673    (parallel
3674     [(set (match_dup 2) (match_dup 3))
3675      (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3676 {
3677   rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3678   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3679   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3680 })
3681
3682 (define_insn_and_split "*cmpint_sign"
3683   [(set (match_operand:DI 0 "register_operand" "=d")
3684         (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3685                                    UNSPEC_STRCMPCC_TO_INT)))
3686    (clobber (reg:CC CC_REGNUM))]
3687   "TARGET_ZARCH"
3688   "#"
3689   "&& reload_completed"
3690   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3691    (parallel
3692     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3693      (clobber (reg:CC CC_REGNUM))])])
3694
3695 (define_insn_and_split "*cmpint_sign_cc"
3696   [(set (reg CC_REGNUM)
3697         (compare (ashiftrt:DI (ashift:DI (subreg:DI
3698                    (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3699                               UNSPEC_STRCMPCC_TO_INT) 0)
3700                    (const_int 32)) (const_int 32))
3701                  (const_int 0)))
3702    (set (match_operand:DI 0 "register_operand" "=d")
3703         (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3704   "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3705   "#"
3706   "&& reload_completed"
3707   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3708    (parallel
3709     [(set (match_dup 2) (match_dup 3))
3710      (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3711 {
3712   rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3713   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3714   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3715 })
3716
3717
3718 ;;
3719 ;;- Conversion instructions.
3720 ;;
3721
3722 (define_insn "*sethighpartsi"
3723   [(set (match_operand:SI 0 "register_operand" "=d,d")
3724         (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3725                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3726    (clobber (reg:CC CC_REGNUM))]
3727   ""
3728   "@
3729    icm\t%0,%2,%S1
3730    icmy\t%0,%2,%S1"
3731   [(set_attr "op_type" "RS,RSY")
3732    (set_attr "cpu_facility" "*,longdisp")
3733    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3734
3735 (define_insn "*sethighpartdi_64"
3736   [(set (match_operand:DI 0 "register_operand" "=d")
3737         (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
3738                     (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3739    (clobber (reg:CC CC_REGNUM))]
3740   "TARGET_ZARCH"
3741   "icmh\t%0,%2,%S1"
3742   [(set_attr "op_type" "RSY")
3743    (set_attr "z10prop" "z10_super")])
3744
3745 (define_insn "*sethighpartdi_31"
3746   [(set (match_operand:DI 0 "register_operand" "=d,d")
3747         (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3748                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3749    (clobber (reg:CC CC_REGNUM))]
3750   "!TARGET_ZARCH"
3751   "@
3752    icm\t%0,%2,%S1
3753    icmy\t%0,%2,%S1"
3754   [(set_attr "op_type" "RS,RSY")
3755    (set_attr "cpu_facility" "*,longdisp")
3756    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3757
3758 ;
3759 ; extv instruction patterns
3760 ;
3761
3762 ; FIXME: This expander needs to be converted from DI to GPR as well
3763 ; after resolving some issues with it.
3764
3765 (define_expand "extzv"
3766   [(parallel
3767     [(set (match_operand:DI 0 "register_operand" "=d")
3768         (zero_extract:DI
3769          (match_operand:DI 1 "register_operand" "d")
3770          (match_operand 2 "const_int_operand" "")   ; size
3771          (match_operand 3 "const_int_operand" ""))) ; start
3772      (clobber (reg:CC CC_REGNUM))])]
3773   "TARGET_Z10"
3774 {
3775   if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64))
3776     FAIL;
3777   /* Starting with zEC12 there is risbgn not clobbering CC.  */
3778   if (TARGET_ZEC12)
3779     {
3780       emit_move_insn (operands[0],
3781                     gen_rtx_ZERO_EXTRACT (DImode,
3782                                           operands[1],
3783                                           operands[2],
3784                                           operands[3]));
3785       DONE;
3786     }
3787 })
3788
3789 (define_insn "*extzv<mode><clobbercc_or_nocc>"
3790   [(set (match_operand:GPR 0 "register_operand" "=d")
3791       (zero_extract:GPR
3792         (match_operand:GPR 1 "register_operand" "d")
3793         (match_operand 2 "const_int_operand" "")   ; size
3794         (match_operand 3 "const_int_operand" ""))) ; start
3795   ]
3796   "<z10_or_zEC12_cond>
3797    && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]),
3798                              GET_MODE_BITSIZE (<MODE>mode))"
3799   "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
3800   [(set_attr "op_type" "RIE")
3801    (set_attr "z10prop" "z10_super_E1")])
3802
3803 ; 64 bit: (a & -16) | ((b >> 8) & 15)
3804 (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt"
3805   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3806                          (match_operand 1 "const_int_operand" "")  ; size
3807                          (match_operand 2 "const_int_operand" "")) ; start
3808         (lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
3809                      (match_operand:DI 4 "nonzero_shift_count_operand" "")))]
3810   "<z10_or_zEC12_cond>
3811    && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
3812    && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
3813   "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
3814   [(set_attr "op_type" "RIE")
3815    (set_attr "z10prop" "z10_super_E1")])
3816
3817 ; 32 bit: (a & -16) | ((b >> 8) & 15)
3818 (define_insn "*<risbg_n>_ior_and_sr_ze"
3819   [(set (match_operand:SI 0 "register_operand" "=d")
3820         (ior:SI (and:SI
3821                  (match_operand:SI 1 "register_operand" "0")
3822                  (match_operand:SI 2 "const_int_operand" ""))
3823                 (subreg:SI
3824                  (zero_extract:DI
3825                   (match_operand:DI 3 "register_operand" "d")
3826                   (match_operand 4 "const_int_operand" "") ; size
3827                   (match_operand 5 "const_int_operand" "")) ; start
3828                  4)))]
3829   "<z10_or_zEC12_cond>
3830    && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
3831    && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
3832   "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
3833   [(set_attr "op_type" "RIE")
3834    (set_attr "z10prop" "z10_super_E1")])
3835
3836 ; ((int)foo >> 10) & 1;
3837 (define_insn "*extract1bitdi<clobbercc_or_nocc>"
3838   [(set (match_operand:DI 0 "register_operand" "=d")
3839         (ne:DI (zero_extract:DI
3840                 (match_operand:DI 1 "register_operand" "d")
3841                 (const_int 1)  ; size
3842                 (match_operand 2 "const_int_operand" "")) ; start
3843                (const_int 0)))]
3844   "<z10_or_zEC12_cond>
3845    && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)"
3846   "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
3847   [(set_attr "op_type" "RIE")
3848    (set_attr "z10prop" "z10_super_E1")])
3849
3850 (define_insn "*<risbg_n>_and_subregdi_rotr"
3851   [(set (match_operand:DI 0 "register_operand" "=d")
3852         (and:DI (subreg:DI
3853                  (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3854                              (match_operand:SINT 2 "const_int_operand" "")) 0)
3855                 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3856   "<z10_or_zEC12_cond>
3857    && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))"
3858   "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
3859   [(set_attr "op_type" "RIE")
3860    (set_attr "z10prop" "z10_super_E1")])
3861
3862 (define_insn "*<risbg_n>_and_subregdi_rotl"
3863   [(set (match_operand:DI 0 "register_operand" "=d")
3864         (and:DI (subreg:DI
3865                  (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3866                              (match_operand:SINT 2 "const_int_operand" "")) 0)
3867                 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3868   "<z10_or_zEC12_cond>
3869    && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))"
3870   "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3871   [(set_attr "op_type" "RIE")
3872    (set_attr "z10prop" "z10_super_E1")])
3873
3874 (define_insn "*<risbg_n>_di_and_rot"
3875   [(set (match_operand:DI 0 "register_operand" "=d")
3876         (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d")
3877                             (match_operand:DI 2 "const_int_operand" ""))
3878                 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3879   "<z10_or_zEC12_cond>"
3880   "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3881   [(set_attr "op_type" "RIE")
3882    (set_attr "z10prop" "z10_super_E1")])
3883
3884 (define_insn_and_split "*pre_z10_extzv<mode>"
3885   [(set (match_operand:GPR 0 "register_operand" "=d")
3886         (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
3887                           (match_operand 2 "nonzero_shift_count_operand" "")
3888                           (const_int 0)))
3889    (clobber (reg:CC CC_REGNUM))]
3890   "!TARGET_Z10"
3891   "#"
3892   "&& reload_completed"
3893   [(parallel
3894     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3895      (clobber (reg:CC CC_REGNUM))])
3896    (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3897 {
3898   int bitsize = INTVAL (operands[2]);
3899   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3900   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3901
3902   operands[1] = adjust_address (operands[1], BLKmode, 0);
3903   set_mem_size (operands[1], size);
3904   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3905   operands[3] = GEN_INT (mask);
3906 })
3907
3908 (define_insn_and_split "*pre_z10_extv<mode>"
3909   [(set (match_operand:GPR 0 "register_operand" "=d")
3910         (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
3911                           (match_operand 2 "nonzero_shift_count_operand" "")
3912                           (const_int 0)))
3913    (clobber (reg:CC CC_REGNUM))]
3914   ""
3915   "#"
3916   "&& reload_completed"
3917   [(parallel
3918     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3919      (clobber (reg:CC CC_REGNUM))])
3920    (parallel
3921     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3922      (clobber (reg:CC CC_REGNUM))])]
3923 {
3924   int bitsize = INTVAL (operands[2]);
3925   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3926   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3927
3928   operands[1] = adjust_address (operands[1], BLKmode, 0);
3929   set_mem_size (operands[1], size);
3930   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3931   operands[3] = GEN_INT (mask);
3932 })
3933
3934 ;
3935 ; insv instruction patterns
3936 ;
3937
3938 (define_expand "insv"
3939   [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3940                       (match_operand 1 "const_int_operand" "")
3941                       (match_operand 2 "const_int_operand" ""))
3942         (match_operand 3 "general_operand" ""))]
3943   ""
3944 {
3945   if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3946     DONE;
3947   FAIL;
3948 })
3949
3950
3951 ; The normal RTL expansion will never generate a zero_extract where
3952 ; the location operand isn't word mode.  However, we do this in the
3953 ; back-end when generating atomic operations. See s390_two_part_insv.
3954 (define_insn "*insv<mode><clobbercc_or_nocc>"
3955   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3956                           (match_operand 1 "const_int_operand"    "I")  ; size
3957                           (match_operand 2 "const_int_operand"    "I")) ; pos
3958         (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3959   "<z10_or_zEC12_cond>
3960    && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]),
3961                              GET_MODE_BITSIZE (<MODE>mode))
3962    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3963   "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
3964   [(set_attr "op_type" "RIE")
3965    (set_attr "z10prop" "z10_super_E1")])
3966
3967 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3968 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3969 (define_insn "*insv<mode><clobbercc_or_nocc>_noshift"
3970   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d")
3971         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0")
3972                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3973                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d")
3974                           (match_operand:GPR 4 "const_int_operand" ""))))]
3975   "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3976   "@
3977    <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0
3978    <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0"
3979   [(set_attr "op_type" "RIE")
3980    (set_attr "z10prop" "z10_super_E1")])
3981
3982 (define_insn "*insv_z10_noshift_cc"
3983   [(set (reg CC_REGNUM)
3984        (compare
3985         (ior:DI
3986          (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
3987                   (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3988          (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
3989                   (match_operand:DI 4 "const_int_operand" "")))
3990         (const_int 0)))
3991    (set (match_operand:DI 0 "nonimmediate_operand" "=d,d")
3992         (ior:DI (and:DI (match_dup 1) (match_dup 2))
3993                  (and:DI (match_dup 3) (match_dup 4))))]
3994   "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
3995    && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3996   "@
3997    risbg\t%0,%1,%s2,%e2,0
3998    risbg\t%0,%3,%s4,%e4,0"
3999   [(set_attr "op_type" "RIE")
4000    (set_attr "z10prop" "z10_super_E1")])
4001
4002 (define_insn "*insv_z10_noshift_cconly"
4003   [(set
4004     (reg CC_REGNUM)
4005     (compare
4006      (ior:DI
4007       (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
4008                (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4009       (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
4010                (match_operand:DI 4 "const_int_operand" "")))
4011      (const_int 0)))
4012   (clobber (match_scratch:DI 0 "=d,d"))]
4013   "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
4014    && INTVAL (operands[2]) == ~INTVAL (operands[4])"
4015   "@
4016    risbg\t%0,%1,%s2,%e2,0
4017    risbg\t%0,%3,%s4,%e4,0"
4018   [(set_attr "op_type" "RIE")
4019    (set_attr "z10prop" "z10_super_E1")])
4020
4021 ; Implement appending Y on the left of S bits of X
4022 ; x = (y << s) | (x & ((1 << s) - 1))
4023 (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft"
4024   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4025         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
4026                           (match_operand:GPR 2 "immediate_operand" ""))
4027                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
4028                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4029   "<z10_or_zEC12_cond>
4030    && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
4031   "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
4032   [(set_attr "op_type" "RIE")
4033    (set_attr "z10prop" "z10_super_E1")])
4034
4035 ; a = ((i32)a & -16777216) | (((ui32)b) >> 8)
4036 (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt"
4037   [(set (match_operand:GPR 0 "register_operand" "=d")
4038         (ior:GPR (and:GPR
4039                   (match_operand:GPR 1 "register_operand" "0")
4040                   (match_operand:GPR 2 "const_int_operand" ""))
4041                  (lshiftrt:GPR
4042                   (match_operand:GPR 3 "register_operand" "d")
4043                   (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4044   "<z10_or_zEC12_cond> && UINTVAL (operands[2])
4045    == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
4046   "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
4047   [(set_attr "op_type" "RIE")
4048    (set_attr "z10prop" "z10_super_E1")])
4049
4050 ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536);
4051 (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt"
4052   [(set (match_operand:SI 0 "register_operand" "=d")
4053         (ior:SI (and:SI
4054                  (match_operand:SI 1 "register_operand" "0")
4055                  (match_operand:SI 2 "const_int_operand" ""))
4056                 (subreg:SI
4057                  (lshiftrt:DI
4058                   (match_operand:DI 3 "register_operand" "d")
4059                   (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
4060   "<z10_or_zEC12_cond>
4061    && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))"
4062   "<risbg_n>\t%0,%3,%4,63,64-%4"
4063   [(set_attr "op_type" "RIE")
4064    (set_attr "z10prop" "z10_super_E1")])
4065
4066 ; (ui32)(((ui64)x) >> 12) & -4
4067 (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>"
4068   [(set (match_operand:SI 0 "register_operand" "=d")
4069         (and:SI
4070          (subreg:SI (lshiftrt:DI
4071                      (match_operand:DI 1 "register_operand" "d")
4072                      (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4)
4073          (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))]
4074   "<z10_or_zEC12_cond>"
4075   "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2"
4076   [(set_attr "op_type" "RIE")
4077    (set_attr "z10prop" "z10_super_E1")])
4078
4079 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
4080 ;  -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
4081 ;  -> z = y >> d; z = risbg;
4082
4083 (define_split
4084   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4085         (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4086                                (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4087                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4088                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4089   "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4090   [(set (match_dup 6)
4091         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4092    (set (match_dup 0)
4093         (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4094                  (ashift:GPR (match_dup 3) (match_dup 4))))]
4095 {
4096   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4097   if (reg_overlap_mentioned_p (operands[0], operands[3]))
4098     {
4099       if (!can_create_pseudo_p ())
4100         FAIL;
4101       operands[6] = gen_reg_rtx (<MODE>mode);
4102     }
4103   else
4104     operands[6] = operands[0];
4105 })
4106
4107 (define_split
4108   [(parallel
4109     [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4110           (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4111                                  (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4112                    (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4113                                (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
4114      (clobber (reg:CC CC_REGNUM))])]
4115   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4116   [(set (match_dup 6)
4117         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4118    (parallel
4119     [(set (match_dup 0)
4120           (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4121                    (ashift:GPR (match_dup 3) (match_dup 4))))
4122      (clobber (reg:CC CC_REGNUM))])]
4123 {
4124   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4125   if (reg_overlap_mentioned_p (operands[0], operands[3]))
4126     {
4127       if (!can_create_pseudo_p ())
4128         FAIL;
4129       operands[6] = gen_reg_rtx (<MODE>mode);
4130     }
4131   else
4132     operands[6] = operands[0];
4133 })
4134
4135 ; rosbg, rxsbg
4136 (define_insn "*r<noxa>sbg_<mode>_noshift"
4137   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4138         (IXOR:GPR
4139           (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
4140                    (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4141           (match_operand:GPR 3 "nonimmediate_operand" "0")))
4142    (clobber (reg:CC CC_REGNUM))]
4143   "TARGET_Z10"
4144   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
4145   [(set_attr "op_type" "RIE")])
4146
4147 ; rosbg, rxsbg
4148 (define_insn "*r<noxa>sbg_di_rotl"
4149   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4150         (IXOR:DI
4151           (and:DI
4152             (rotate:DI
4153               (match_operand:DI 1 "nonimmediate_operand" "d")
4154               (match_operand:DI 3 "const_int_operand" ""))
4155             (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4156           (match_operand:DI 4 "nonimmediate_operand" "0")))
4157    (clobber (reg:CC CC_REGNUM))]
4158   "TARGET_Z10"
4159   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
4160   [(set_attr "op_type" "RIE")])
4161
4162 ; rosbg, rxsbg
4163 (define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
4164   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4165         (IXOR:GPR
4166           (and:GPR
4167             (lshiftrt:GPR
4168               (match_operand:GPR 1 "nonimmediate_operand" "d")
4169               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4170             (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
4171           (match_operand:GPR 4 "nonimmediate_operand" "0")))
4172    (clobber (reg:CC CC_REGNUM))]
4173   "TARGET_Z10
4174    && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
4175                            INTVAL (operands[2]))"
4176   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
4177   [(set_attr "op_type" "RIE")])
4178
4179 ; rosbg, rxsbg
4180 (define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
4181   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4182         (IXOR:GPR
4183           (and:GPR
4184             (ashift:GPR
4185               (match_operand:GPR 1 "nonimmediate_operand" "d")
4186               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4187             (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
4188           (match_operand:GPR 4 "nonimmediate_operand" "0")))
4189    (clobber (reg:CC CC_REGNUM))]
4190   "TARGET_Z10
4191    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
4192                            INTVAL (operands[2]))"
4193   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
4194   [(set_attr "op_type" "RIE")])
4195
4196 ;; unsigned {int,long} a, b
4197 ;; a = a | (b << const_int)
4198 ;; a = a ^ (b << const_int)
4199 ; rosbg, rxsbg
4200 (define_insn "*r<noxa>sbg_<mode>_sll"
4201   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4202         (IXOR:GPR
4203           (ashift:GPR
4204             (match_operand:GPR 1 "nonimmediate_operand" "d")
4205             (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4206           (match_operand:GPR 3 "nonimmediate_operand" "0")))
4207    (clobber (reg:CC CC_REGNUM))]
4208   "TARGET_Z10"
4209   "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2"
4210   [(set_attr "op_type" "RIE")])
4211
4212 ;; unsigned {int,long} a, b
4213 ;; a = a | (b >> const_int)
4214 ;; a = a ^ (b >> const_int)
4215 ; rosbg, rxsbg
4216 (define_insn "*r<noxa>sbg_<mode>_srl"
4217   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4218         (IXOR:GPR
4219           (lshiftrt:GPR
4220             (match_operand:GPR 1 "nonimmediate_operand" "d")
4221             (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4222           (match_operand:GPR 3 "nonimmediate_operand" "0")))
4223    (clobber (reg:CC CC_REGNUM))]
4224   "TARGET_Z10"
4225   "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2"
4226   [(set_attr "op_type" "RIE")])
4227
4228 ;; These two are generated by combine for s.bf &= val.
4229 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
4230 ;; shifts and ands, which results in some truly awful patterns
4231 ;; including subregs of operations.  Rather unnecessisarily, IMO.
4232 ;; Instead of
4233 ;;
4234 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4235 ;;        (const_int 24 [0x18])
4236 ;;        (const_int 0 [0]))
4237 ;;    (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
4238 ;;                    (const_int 40 [0x28])) 4)
4239 ;;            (reg:SI 4 %r4 [ y+4 ])) 0))
4240 ;;
4241 ;; we should instead generate
4242 ;;
4243 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4244 ;;        (const_int 24 [0x18])
4245 ;;        (const_int 0 [0]))
4246 ;;    (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
4247 ;;                    (const_int 40 [0x28]))
4248 ;;            (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
4249 ;;
4250 ;; by noticing that we can push down the outer paradoxical subreg
4251 ;; into the operation.
4252
4253 (define_insn "*insv_rnsbg_noshift"
4254   [(set (zero_extract:DI
4255           (match_operand:DI 0 "nonimmediate_operand" "+d")
4256           (match_operand 1 "const_int_operand" "")
4257           (match_operand 2 "const_int_operand" ""))
4258         (and:DI
4259           (match_dup 0)
4260           (match_operand:DI 3 "nonimmediate_operand" "d")))
4261    (clobber (reg:CC CC_REGNUM))]
4262   "TARGET_Z10
4263    && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
4264    && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4265   "rnsbg\t%0,%3,%2,63,0"
4266   [(set_attr "op_type" "RIE")])
4267
4268 (define_insn "*insv_rnsbg_srl"
4269   [(set (zero_extract:DI
4270           (match_operand:DI 0 "nonimmediate_operand" "+d")
4271           (match_operand 1 "const_int_operand" "")
4272           (match_operand 2 "const_int_operand" ""))
4273         (and:DI
4274           (lshiftrt:DI
4275             (match_dup 0)
4276             (match_operand 3 "const_int_operand" ""))
4277           (match_operand:DI 4 "nonimmediate_operand" "d")))
4278    (clobber (reg:CC CC_REGNUM))]
4279   "TARGET_Z10
4280    && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
4281    && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4282   "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4283   [(set_attr "op_type" "RIE")])
4284
4285 (define_insn "*insv<mode>_mem_reg"
4286   [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4287                         (match_operand 1 "const_int_operand" "n,n")
4288                         (const_int 0))
4289         (match_operand:W 2 "register_operand" "d,d"))]
4290   "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
4291    && INTVAL (operands[1]) > 0
4292    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4293    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4294 {
4295     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4296
4297     operands[1] = GEN_INT ((1ul << size) - 1);
4298     return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4299                                     : "stcmy\t%2,%1,%S0";
4300 }
4301   [(set_attr "op_type" "RS,RSY")
4302    (set_attr "cpu_facility" "*,longdisp")
4303    (set_attr "z10prop" "z10_super,z10_super")])
4304
4305 (define_insn "*insvdi_mem_reghigh"
4306   [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
4307                          (match_operand 1 "const_int_operand" "n")
4308                          (const_int 0))
4309         (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4310                      (const_int 32)))]
4311   "TARGET_ZARCH
4312    && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
4313    && INTVAL (operands[1]) > 0
4314    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4315    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4316 {
4317     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4318
4319     operands[1] = GEN_INT ((1ul << size) - 1);
4320     return "stcmh\t%2,%1,%S0";
4321 }
4322 [(set_attr "op_type" "RSY")
4323  (set_attr "z10prop" "z10_super")])
4324
4325 (define_insn "*insvdi_reg_imm"
4326   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4327                          (const_int 16)
4328                          (match_operand 1 "const_int_operand" "n"))
4329         (match_operand:DI 2 "const_int_operand" "n"))]
4330   "TARGET_ZARCH
4331    && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64)
4332    && INTVAL (operands[1]) >= 0
4333    && INTVAL (operands[1]) < BITS_PER_WORD
4334    && INTVAL (operands[1]) % 16 == 0"
4335 {
4336   switch (BITS_PER_WORD - INTVAL (operands[1]))
4337     {
4338       case 64: return "iihh\t%0,%x2"; break;
4339       case 48: return "iihl\t%0,%x2"; break;
4340       case 32: return "iilh\t%0,%x2"; break;
4341       case 16: return "iill\t%0,%x2"; break;
4342       default: gcc_unreachable();
4343     }
4344 }
4345   [(set_attr "op_type" "RI")
4346    (set_attr "z10prop" "z10_super_E1")])
4347
4348 ; Update the left-most 32 bit of a DI.
4349 (define_insn "*insv_h_di_reg_extimm"
4350   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4351                          (const_int 32)
4352                          (const_int 0))
4353         (match_operand:DI 1 "const_int_operand" "n"))]
4354   "TARGET_EXTIMM"
4355   "iihf\t%0,%o1"
4356   [(set_attr "op_type" "RIL")
4357    (set_attr "z10prop" "z10_fwd_E1")])
4358
4359 ; Update the right-most 32 bit of a DI.
4360 (define_insn "*insv_l_di_reg_extimm"
4361   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4362                          (const_int 32)
4363                          (const_int 32))
4364         (match_operand:DI 1 "const_int_operand" "n"))]
4365   "TARGET_EXTIMM"
4366   "iilf\t%0,%o1"
4367   [(set_attr "op_type" "RIL")
4368    (set_attr "z10prop" "z10_fwd_A1")])
4369
4370 ;
4371 ; extendsidi2 instruction pattern(s).
4372 ;
4373
4374 (define_expand "extendsidi2"
4375   [(set (match_operand:DI 0 "register_operand" "")
4376         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4377   ""
4378 {
4379   if (!TARGET_ZARCH)
4380     {
4381       emit_clobber (operands[0]);
4382       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4383       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4384       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4385       DONE;
4386     }
4387 })
4388
4389 (define_insn "*extendsidi2"
4390   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4391         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4392   "TARGET_ZARCH"
4393   "@
4394    lgfr\t%0,%1
4395    lgf\t%0,%1
4396    lgfrl\t%0,%1"
4397   [(set_attr "op_type"      "RRE,RXY,RIL")
4398    (set_attr "type"         "*,*,larl")
4399    (set_attr "cpu_facility" "*,*,z10")
4400    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4401
4402 ;
4403 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4404 ;
4405
4406 (define_expand "extend<HQI:mode><DSI:mode>2"
4407   [(set (match_operand:DSI 0 "register_operand" "")
4408         (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4409   ""
4410 {
4411   if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4412     {
4413       rtx tmp = gen_reg_rtx (SImode);
4414       emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4415       emit_insn (gen_extendsidi2 (operands[0], tmp));
4416       DONE;
4417     }
4418   else if (!TARGET_EXTIMM)
4419     {
4420       rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4421
4422       operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4423       emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4424       emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4425       DONE;
4426     }
4427 })
4428
4429 ;
4430 ; extendhidi2 instruction pattern(s).
4431 ;
4432
4433 (define_insn "*extendhidi2_extimm"
4434   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4435         (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
4436   "TARGET_ZARCH && TARGET_EXTIMM"
4437   "@
4438    lghr\t%0,%1
4439    lgh\t%0,%1
4440    lghrl\t%0,%1"
4441   [(set_attr "op_type"      "RRE,RXY,RIL")
4442    (set_attr "type"         "*,*,larl")
4443    (set_attr "cpu_facility" "extimm,extimm,z10")
4444    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4445
4446 (define_insn "*extendhidi2"
4447   [(set (match_operand:DI 0 "register_operand" "=d")
4448         (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
4449   "TARGET_ZARCH"
4450   "lgh\t%0,%1"
4451   [(set_attr "op_type" "RXY")
4452    (set_attr "z10prop" "z10_super_E1")])
4453
4454 ;
4455 ; extendhisi2 instruction pattern(s).
4456 ;
4457
4458 (define_insn "*extendhisi2_extimm"
4459   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4460         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4461   "TARGET_EXTIMM"
4462   "@
4463    lhr\t%0,%1
4464    lh\t%0,%1
4465    lhy\t%0,%1
4466    lhrl\t%0,%1"
4467   [(set_attr "op_type"      "RRE,RX,RXY,RIL")
4468    (set_attr "type"         "*,*,*,larl")
4469    (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4470    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4471
4472 (define_insn "*extendhisi2"
4473   [(set (match_operand:SI 0 "register_operand" "=d,d")
4474         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4475   "!TARGET_EXTIMM"
4476   "@
4477    lh\t%0,%1
4478    lhy\t%0,%1"
4479   [(set_attr "op_type" "RX,RXY")
4480    (set_attr "cpu_facility" "*,longdisp")
4481    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4482
4483 ;
4484 ; extendqi(si|di)2 instruction pattern(s).
4485 ;
4486
4487 ; lbr, lgbr, lb, lgb
4488 (define_insn "*extendqi<mode>2_extimm"
4489   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4490         (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
4491   "TARGET_EXTIMM"
4492   "@
4493    l<g>br\t%0,%1
4494    l<g>b\t%0,%1"
4495   [(set_attr "op_type" "RRE,RXY")
4496    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4497
4498 ; lb, lgb
4499 (define_insn "*extendqi<mode>2"
4500   [(set (match_operand:GPR 0 "register_operand" "=d")
4501         (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
4502   "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4503   "l<g>b\t%0,%1"
4504   [(set_attr "op_type" "RXY")
4505    (set_attr "z10prop" "z10_super_E1")])
4506
4507 (define_insn_and_split "*extendqi<mode>2_short_displ"
4508   [(set (match_operand:GPR 0 "register_operand" "=d")
4509         (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4510    (clobber (reg:CC CC_REGNUM))]
4511   "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4512   "#"
4513   "&& reload_completed"
4514   [(parallel
4515     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4516      (clobber (reg:CC CC_REGNUM))])
4517    (parallel
4518     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4519      (clobber (reg:CC CC_REGNUM))])]
4520 {
4521   operands[1] = adjust_address (operands[1], BLKmode, 0);
4522   set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4523   operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4524 })
4525
4526 ;
4527 ; zero_extendsidi2 instruction pattern(s).
4528 ;
4529
4530 (define_expand "zero_extendsidi2"
4531   [(set (match_operand:DI 0 "register_operand" "")
4532         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4533   ""
4534 {
4535   if (!TARGET_ZARCH)
4536     {
4537       emit_clobber (operands[0]);
4538       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4539       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4540       DONE;
4541     }
4542 })
4543
4544 (define_insn "*zero_extendsidi2"
4545   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4546         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4547   "TARGET_ZARCH"
4548   "@
4549    llgfr\t%0,%1
4550    llgf\t%0,%1
4551    llgfrl\t%0,%1"
4552   [(set_attr "op_type"      "RRE,RXY,RIL")
4553    (set_attr "type"         "*,*,larl")
4554    (set_attr "cpu_facility" "*,*,z10")
4555    (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4556
4557 ;
4558 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4559 ;
4560
4561 (define_insn "*llgt_sidi"
4562   [(set (match_operand:DI 0 "register_operand" "=d")
4563         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4564                 (const_int 2147483647)))]
4565   "TARGET_ZARCH"
4566   "llgt\t%0,%1"
4567   [(set_attr "op_type"  "RXE")
4568    (set_attr "z10prop" "z10_super_E1")])
4569
4570 (define_insn_and_split "*llgt_sidi_split"
4571   [(set (match_operand:DI 0 "register_operand" "=d")
4572         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4573                 (const_int 2147483647)))
4574    (clobber (reg:CC CC_REGNUM))]
4575   "TARGET_ZARCH"
4576   "#"
4577   "&& reload_completed"
4578   [(set (match_dup 0)
4579         (and:DI (subreg:DI (match_dup 1) 0)
4580                 (const_int 2147483647)))]
4581   "")
4582
4583 (define_insn "*llgt_sisi"
4584   [(set (match_operand:SI 0 "register_operand" "=d,d")
4585         (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
4586                 (const_int 2147483647)))]
4587   "TARGET_ZARCH"
4588   "@
4589    llgtr\t%0,%1
4590    llgt\t%0,%1"
4591   [(set_attr "op_type"  "RRE,RXE")
4592    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4593
4594 (define_insn "*llgt_didi"
4595   [(set (match_operand:DI 0 "register_operand" "=d,d")
4596         (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4597                 (const_int 2147483647)))]
4598   "TARGET_ZARCH"
4599   "@
4600    llgtr\t%0,%1
4601    llgt\t%0,%N1"
4602   [(set_attr "op_type"  "RRE,RXE")
4603    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4604
4605 (define_split
4606   [(set (match_operand:DSI 0 "register_operand" "")
4607         (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4608                  (const_int 2147483647)))
4609    (clobber (reg:CC CC_REGNUM))]
4610   "TARGET_ZARCH && reload_completed"
4611   [(set (match_dup 0)
4612         (and:DSI (match_dup 1)
4613                  (const_int 2147483647)))]
4614   "")
4615
4616 ;
4617 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4618 ;
4619
4620 (define_expand "zero_extend<mode>di2"
4621   [(set (match_operand:DI 0 "register_operand" "")
4622         (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4623   ""
4624 {
4625   if (!TARGET_ZARCH)
4626     {
4627       rtx tmp = gen_reg_rtx (SImode);
4628       emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4629       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4630       DONE;
4631     }
4632   else if (!TARGET_EXTIMM)
4633     {
4634       rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4635       operands[1] = gen_lowpart (DImode, operands[1]);
4636       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4637       emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4638       DONE;
4639     }
4640 })
4641
4642 (define_expand "zero_extend<mode>si2"
4643   [(set (match_operand:SI 0 "register_operand" "")
4644         (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4645   ""
4646 {
4647   if (!TARGET_EXTIMM)
4648     {
4649       operands[1] = gen_lowpart (SImode, operands[1]);
4650       emit_insn (gen_andsi3 (operands[0], operands[1],
4651                              GEN_INT ((1 << <HQI:bitsize>) - 1)));
4652       DONE;
4653     }
4654 })
4655
4656 ; llhrl, llghrl
4657 (define_insn "*zero_extendhi<mode>2_z10"
4658   [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4659         (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
4660   "TARGET_Z10"
4661   "@
4662    ll<g>hr\t%0,%1
4663    ll<g>h\t%0,%1
4664    ll<g>hrl\t%0,%1"
4665   [(set_attr "op_type"      "RXY,RRE,RIL")
4666    (set_attr "type"         "*,*,larl")
4667    (set_attr "cpu_facility" "*,*,z10")
4668    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4669
4670 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4671 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4672   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4673         (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
4674   "TARGET_EXTIMM"
4675   "@
4676    ll<g><hc>r\t%0,%1
4677    ll<g><hc>\t%0,%1"
4678   [(set_attr "op_type" "RRE,RXY")
4679    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4680
4681 ; llgh, llgc
4682 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4683   [(set (match_operand:GPR 0 "register_operand" "=d")
4684         (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
4685   "TARGET_ZARCH && !TARGET_EXTIMM"
4686   "llg<hc>\t%0,%1"
4687   [(set_attr "op_type" "RXY")
4688    (set_attr "z10prop" "z10_fwd_A3")])
4689
4690 (define_insn_and_split "*zero_extendhisi2_31"
4691   [(set (match_operand:SI 0 "register_operand" "=&d")
4692         (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
4693    (clobber (reg:CC CC_REGNUM))]
4694   "!TARGET_ZARCH"
4695   "#"
4696   "&& reload_completed"
4697   [(set (match_dup 0) (const_int 0))
4698    (parallel
4699     [(set (strict_low_part (match_dup 2)) (match_dup 1))
4700      (clobber (reg:CC CC_REGNUM))])]
4701   "operands[2] = gen_lowpart (HImode, operands[0]);")
4702
4703 (define_insn_and_split "*zero_extendqisi2_31"
4704   [(set (match_operand:SI 0 "register_operand" "=&d")
4705         (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
4706   "!TARGET_ZARCH"
4707   "#"
4708   "&& reload_completed"
4709   [(set (match_dup 0) (const_int 0))
4710    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4711   "operands[2] = gen_lowpart (QImode, operands[0]);")
4712
4713 ;
4714 ; zero_extendqihi2 instruction pattern(s).
4715 ;
4716
4717 (define_expand "zero_extendqihi2"
4718   [(set (match_operand:HI 0 "register_operand" "")
4719         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4720   "TARGET_ZARCH && !TARGET_EXTIMM"
4721 {
4722   operands[1] = gen_lowpart (HImode, operands[1]);
4723   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4724   DONE;
4725 })
4726
4727 (define_insn "*zero_extendqihi2_64"
4728   [(set (match_operand:HI 0 "register_operand" "=d")
4729         (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4730   "TARGET_ZARCH && !TARGET_EXTIMM"
4731   "llgc\t%0,%1"
4732   [(set_attr "op_type" "RXY")
4733    (set_attr "z10prop" "z10_fwd_A3")])
4734
4735 (define_insn_and_split "*zero_extendqihi2_31"
4736   [(set (match_operand:HI 0 "register_operand" "=&d")
4737         (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4738   "!TARGET_ZARCH"
4739   "#"
4740   "&& reload_completed"
4741   [(set (match_dup 0) (const_int 0))
4742    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4743   "operands[2] = gen_lowpart (QImode, operands[0]);")
4744
4745 ;
4746 ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander
4747 ;
4748
4749 ; This is the only entry point for fixuns_trunc.  It multiplexes the
4750 ; expansion to either the *_emu expanders below for pre z196 machines
4751 ; or emits the default pattern otherwise.
4752 (define_expand "fixuns_trunc<FP:mode><GPR:mode>2"
4753   [(parallel
4754     [(set (match_operand:GPR 0 "register_operand" "")
4755           (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "")))
4756      (unspec:GPR [(match_dup 2)] UNSPEC_ROUND)
4757      (clobber (reg:CC CC_REGNUM))])]
4758   "TARGET_HARD_FLOAT"
4759 {
4760   if (!TARGET_Z196)
4761     {
4762       /* We don't provide emulation for TD|DD->SI.  */
4763       if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT
4764           && <GPR:MODE>mode == SImode)
4765         FAIL;
4766       emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0],
4767                                                                operands[1]));
4768       DONE;
4769     }
4770
4771   if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT)
4772     operands[2] = GEN_INT (DFP_RND_TOWARD_0);
4773   else
4774     operands[2] = GEN_INT (BFP_RND_TOWARD_0);
4775 })
4776
4777 ; (sf|df|tf)->unsigned (si|di)
4778
4779 ; Emulate the unsigned conversion with the signed version for pre z196
4780 ; machines.
4781 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu"
4782   [(parallel
4783     [(set (match_operand:GPR 0 "register_operand" "")
4784           (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4785      (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4786      (clobber (reg:CC CC_REGNUM))])]
4787   "!TARGET_Z196 && TARGET_HARD_FLOAT"
4788 {
4789   rtx_code_label *label1 = gen_label_rtx ();
4790   rtx_code_label *label2 = gen_label_rtx ();
4791   rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4792   REAL_VALUE_TYPE cmp, sub;
4793
4794   operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4795   real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4796   real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4797
4798   emit_cmp_and_jump_insns (operands[1],
4799                            const_double_from_real_value (cmp, <BFP:MODE>mode),
4800                            LT, NULL_RTX, VOIDmode, 0, label1);
4801   emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4802                const_double_from_real_value (sub, <BFP:MODE>mode)));
4803   emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4804                GEN_INT (BFP_RND_TOWARD_MINF)));
4805   emit_jump (label2);
4806
4807   emit_label (label1);
4808   emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4809                                                          operands[1],
4810                                                          GEN_INT (BFP_RND_TOWARD_0)));
4811   emit_label (label2);
4812   DONE;
4813 })
4814
4815 ; dd->unsigned di
4816
4817 ; Emulate the unsigned conversion with the signed version for pre z196
4818 ; machines.
4819 (define_expand "fixuns_truncdddi2_emu"
4820   [(parallel
4821     [(set (match_operand:DI 0 "register_operand" "")
4822           (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4823      (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4824      (clobber (reg:CC CC_REGNUM))])]
4825
4826   "!TARGET_Z196 && TARGET_HARD_DFP"
4827 {
4828   rtx_code_label *label1 = gen_label_rtx ();
4829   rtx_code_label *label2 = gen_label_rtx ();
4830   rtx temp = gen_reg_rtx (TDmode);
4831   REAL_VALUE_TYPE cmp, sub;
4832
4833   decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4834   decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4835
4836   /* 2^63 can't be represented as 64bit DFP number with full precision.  The
4837      solution is doing the check and the subtraction in TD mode and using a
4838      TD -> DI convert afterwards.  */
4839   emit_insn (gen_extendddtd2 (temp, operands[1]));
4840   temp = force_reg (TDmode, temp);
4841   emit_cmp_and_jump_insns (temp,
4842                            const_double_from_real_value (cmp, TDmode),
4843                            LT, NULL_RTX, VOIDmode, 0, label1);
4844   emit_insn (gen_subtd3 (temp, temp,
4845                          const_double_from_real_value (sub, TDmode)));
4846   emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4847                                      GEN_INT (DFP_RND_TOWARD_MINF)));
4848   emit_jump (label2);
4849
4850   emit_label (label1);
4851   emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
4852                                      GEN_INT (DFP_RND_TOWARD_0)));
4853   emit_label (label2);
4854   DONE;
4855 })
4856
4857 ; td->unsigned di
4858
4859 ; Emulate the unsigned conversion with the signed version for pre z196
4860 ; machines.
4861 (define_expand "fixuns_trunctddi2_emu"
4862   [(parallel
4863     [(set (match_operand:DI 0 "register_operand" "")
4864           (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4865      (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4866      (clobber (reg:CC CC_REGNUM))])]
4867
4868   "!TARGET_Z196 && TARGET_HARD_DFP"
4869 {
4870   rtx_code_label *label1 = gen_label_rtx ();
4871   rtx_code_label *label2 = gen_label_rtx ();
4872   rtx temp = gen_reg_rtx (TDmode);
4873   REAL_VALUE_TYPE cmp, sub;
4874
4875   operands[1] = force_reg (TDmode, operands[1]);
4876   decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4877   decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4878
4879   emit_cmp_and_jump_insns (operands[1],
4880                            const_double_from_real_value (cmp, TDmode),
4881                            LT, NULL_RTX, VOIDmode, 0, label1);
4882   emit_insn (gen_subtd3 (temp, operands[1],
4883                          const_double_from_real_value (sub, TDmode)));
4884   emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4885                                      GEN_INT (DFP_RND_TOWARD_MINF)));
4886   emit_jump (label2);
4887
4888   emit_label (label1);
4889   emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
4890                                      GEN_INT (DFP_RND_TOWARD_0)));
4891   emit_label (label2);
4892   DONE;
4893 })
4894
4895 ; Just a dummy to make the code in the first expander a bit easier.
4896 (define_expand "fixuns_trunc<mode>si2_emu"
4897   [(parallel
4898     [(set (match_operand:SI 0 "register_operand" "")
4899           (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4900      (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4901      (clobber (reg:CC CC_REGNUM))])]
4902
4903   "!TARGET_Z196 && TARGET_HARD_DFP"
4904  {
4905    FAIL;
4906  })
4907
4908
4909 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4910
4911 ; df -> unsigned di
4912 (define_insn "*fixuns_truncdfdi2_vx"
4913   [(set (match_operand:DI                  0 "register_operand" "=d,v")
4914         (unsigned_fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4915    (unspec:DI [(match_operand:DI           2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4916    (clobber (reg:CC CC_REGNUM))]
4917   "TARGET_VX && TARGET_HARD_FLOAT"
4918   "@
4919    clgdbr\t%0,%h2,%1,0
4920    wclgdb\t%v0,%v1,0,%h2"
4921   [(set_attr "op_type" "RRF,VRR")
4922    (set_attr "type"    "ftoi")])
4923
4924 ; (dd|td|sf|df|tf)->unsigned (di|si)
4925 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4926 ;         clfdtr, clfxtr,         clgdtr, clgxtr
4927 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4928   [(set (match_operand:GPR                  0 "register_operand" "=d")
4929         (unsigned_fix:GPR (match_operand:FP 1 "register_operand"  "f")))
4930    (unspec:GPR [(match_operand:GPR          2 "immediate_operand" "K")] UNSPEC_ROUND)
4931    (clobber (reg:CC CC_REGNUM))]
4932    "TARGET_Z196 && TARGET_HARD_FLOAT
4933     && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4934    "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4935    [(set_attr "op_type" "RRF")
4936     (set_attr "type"    "ftoi")])
4937
4938 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4939   [(set (match_operand:GPR 0 "register_operand" "")
4940         (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4941   "TARGET_HARD_FLOAT"
4942 {
4943   emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4944              GEN_INT (BFP_RND_TOWARD_0)));
4945   DONE;
4946 })
4947
4948 (define_insn "*fix_truncdfdi2_bfp_z13"
4949   [(set (match_operand:DI         0 "register_operand" "=d,v")
4950         (fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4951    (unspec:DI [(match_operand:DI  2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4952    (clobber (reg:CC CC_REGNUM))]
4953   "TARGET_VX && TARGET_HARD_FLOAT"
4954   "@
4955    cgdbr\t%0,%h2,%1
4956    wcgdb\t%v0,%v1,0,%h2"
4957   [(set_attr "op_type" "RRE,VRR")
4958    (set_attr "type"    "ftoi")])
4959
4960 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4961 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4962   [(set (match_operand:GPR          0 "register_operand" "=d")
4963         (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4964    (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4965    (clobber (reg:CC CC_REGNUM))]
4966   "TARGET_HARD_FLOAT
4967     && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4968   "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4969   [(set_attr "op_type" "RRE")
4970    (set_attr "type"    "ftoi")])
4971
4972 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4973   [(parallel
4974     [(set (match_operand:GPR          0 "register_operand" "=d")
4975           (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4976      (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4977      (clobber (reg:CC CC_REGNUM))])]
4978   "TARGET_HARD_FLOAT")
4979 ;
4980 ; fix_trunc(td|dd)di2 instruction pattern(s).
4981 ;
4982
4983 (define_expand "fix_trunc<mode>di2"
4984   [(set (match_operand:DI 0 "register_operand" "")
4985         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4986   "TARGET_ZARCH && TARGET_HARD_DFP"
4987 {
4988   operands[1] = force_reg (<MODE>mode, operands[1]);
4989   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4990       GEN_INT (DFP_RND_TOWARD_0)));
4991   DONE;
4992 })
4993
4994 ; cgxtr, cgdtr
4995 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4996   [(set (match_operand:DI 0 "register_operand" "=d")
4997         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4998    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4999    (clobber (reg:CC CC_REGNUM))]
5000   "TARGET_ZARCH && TARGET_HARD_DFP"
5001   "cg<DFP:xde>tr\t%0,%h2,%1"
5002   [(set_attr "op_type" "RRF")
5003    (set_attr "type"    "ftoidfp")])
5004
5005
5006 ;
5007 ; fix_trunctf(si|di)2 instruction pattern(s).
5008 ;
5009
5010 (define_expand "fix_trunctf<mode>2"
5011   [(parallel [(set (match_operand:GPR 0 "register_operand" "")
5012                    (fix:GPR (match_operand:TF 1 "register_operand" "")))
5013               (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
5014               (clobber (reg:CC CC_REGNUM))])]
5015   "TARGET_HARD_FLOAT"
5016   "")
5017
5018
5019 ;
5020 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
5021 ;
5022
5023 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
5024 (define_insn "floatdi<mode>2"
5025   [(set (match_operand:FP           0 "register_operand" "=f,v")
5026         (float:FP (match_operand:DI 1 "register_operand"  "d,v")))]
5027   "TARGET_ZARCH && TARGET_HARD_FLOAT"
5028   "@
5029    c<xde>g<bt>r\t%0,%1
5030    wcdgb\t%v0,%v1,0,0"
5031   [(set_attr "op_type"      "RRE,VRR")
5032    (set_attr "type"         "itof<mode>" )
5033    (set_attr "cpu_facility" "*,vx")
5034    (set_attr "enabled"      "*,<DFDI>")])
5035
5036 ; cxfbr, cdfbr, cefbr
5037 (define_insn "floatsi<mode>2"
5038   [(set (match_operand:BFP 0 "register_operand" "=f")
5039         (float:BFP (match_operand:SI 1 "register_operand" "d")))]
5040   "TARGET_HARD_FLOAT"
5041   "c<xde>fbr\t%0,%1"
5042   [(set_attr "op_type" "RRE")
5043    (set_attr "type"   "itof<mode>" )])
5044
5045 ; cxftr, cdftr
5046 (define_insn "floatsi<mode>2"
5047   [(set (match_operand:DFP 0 "register_operand" "=f")
5048         (float:DFP (match_operand:SI 1 "register_operand" "d")))]
5049   "TARGET_Z196 && TARGET_HARD_FLOAT"
5050   "c<xde>ftr\t%0,0,%1,0"
5051   [(set_attr "op_type" "RRE")
5052    (set_attr "type"   "itof<mode>" )])
5053
5054 ;
5055 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
5056 ;
5057
5058 (define_insn "*floatunsdidf2_z13"
5059   [(set (match_operand:DF                    0 "register_operand" "=f,v")
5060         (unsigned_float:DF (match_operand:DI 1 "register_operand"  "d,v")))]
5061   "TARGET_VX && TARGET_HARD_FLOAT"
5062   "@
5063    cdlgbr\t%0,0,%1,0
5064    wcdlgb\t%v0,%v1,0,0"
5065   [(set_attr "op_type" "RRE,VRR")
5066    (set_attr "type"    "itofdf")])
5067
5068 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
5069 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
5070 (define_insn "*floatuns<GPR:mode><FP:mode>2"
5071   [(set (match_operand:FP                     0 "register_operand" "=f")
5072         (unsigned_float:FP (match_operand:GPR 1 "register_operand"  "d")))]
5073   "TARGET_Z196 && TARGET_HARD_FLOAT
5074    && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
5075   "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
5076   [(set_attr "op_type" "RRE")
5077    (set_attr "type"    "itof<FP:mode>")])
5078
5079 (define_expand "floatuns<GPR:mode><FP:mode>2"
5080   [(set (match_operand:FP                     0 "register_operand" "")
5081         (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
5082   "TARGET_Z196 && TARGET_HARD_FLOAT")
5083
5084 ;
5085 ; truncdfsf2 instruction pattern(s).
5086 ;
5087
5088 (define_insn "truncdfsf2"
5089   [(set (match_operand:SF                    0 "register_operand" "=f,v")
5090         (float_truncate:SF (match_operand:DF 1 "register_operand"  "f,v")))]
5091   "TARGET_HARD_FLOAT"
5092   "@
5093    ledbr\t%0,%1
5094    wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
5095                        ; According to BFP rounding mode
5096   [(set_attr "op_type"      "RRE,VRR")
5097    (set_attr "type"         "ftruncdf")
5098    (set_attr "cpu_facility" "*,vx")])
5099
5100 ;
5101 ; trunctf(df|sf)2 instruction pattern(s).
5102 ;
5103
5104 ; ldxbr, lexbr
5105 (define_insn "trunctf<mode>2"
5106   [(set (match_operand:DSF 0 "register_operand" "=f")
5107         (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
5108    (clobber (match_scratch:TF 2 "=f"))]
5109   "TARGET_HARD_FLOAT"
5110   "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
5111   [(set_attr "length" "6")
5112    (set_attr "type"   "ftrunctf")])
5113
5114 ;
5115 ; trunctddd2 and truncddsd2 instruction pattern(s).
5116 ;
5117
5118
5119 (define_expand "trunctddd2"
5120   [(parallel
5121     [(set (match_operand:DD 0 "register_operand" "")
5122           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5123      (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
5124      (clobber (scratch:TD))])]
5125   "TARGET_HARD_DFP")
5126
5127 (define_insn "*trunctddd2"
5128   [(set (match_operand:DD 0 "register_operand" "=f")
5129         (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
5130    (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
5131    (clobber (match_scratch:TD 3 "=f"))]
5132   "TARGET_HARD_DFP"
5133   "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
5134   [(set_attr "length"  "6")
5135    (set_attr "type"    "ftruncdd")])
5136
5137 (define_insn "truncddsd2"
5138   [(set (match_operand:SD 0 "register_operand" "=f")
5139         (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
5140   "TARGET_HARD_DFP"
5141   "ledtr\t%0,0,%1,0"
5142   [(set_attr "op_type" "RRF")
5143    (set_attr "type"    "ftruncsd")])
5144
5145 (define_expand "trunctdsd2"
5146   [(parallel
5147     [(set (match_dup 2)
5148           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5149      (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
5150      (clobber (match_scratch:TD 3 ""))])
5151    (set (match_operand:SD 0 "register_operand" "")
5152         (float_truncate:SD (match_dup 2)))]
5153   "TARGET_HARD_DFP"
5154 {
5155   operands[2] = gen_reg_rtx (DDmode);
5156 })
5157
5158 ;
5159 ; extend(sf|df)(df|tf)2 instruction pattern(s).
5160 ;
5161
5162 (define_insn "*extendsfdf2_z13"
5163   [(set (match_operand:DF                  0 "register_operand"     "=f,f,v")
5164         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R,v")))]
5165   "TARGET_VX && TARGET_HARD_FLOAT"
5166   "@
5167    ldebr\t%0,%1
5168    ldeb\t%0,%1
5169    wldeb\t%v0,%v1"
5170   [(set_attr "op_type" "RRE,RXE,VRR")
5171    (set_attr "type"    "fsimpdf, floaddf,fsimpdf")])
5172
5173 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
5174 (define_insn "*extend<DSF:mode><BFP:mode>2"
5175   [(set (match_operand:BFP                   0 "register_operand"     "=f,f")
5176         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand"  "f,R")))]
5177   "TARGET_HARD_FLOAT
5178    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
5179    && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
5180   "@
5181    l<BFP:xde><DSF:xde>br\t%0,%1
5182    l<BFP:xde><DSF:xde>b\t%0,%1"
5183   [(set_attr "op_type" "RRE,RXE")
5184    (set_attr "type"    "fsimp<BFP:mode>, fload<BFP:mode>")])
5185
5186 (define_expand "extend<DSF:mode><BFP:mode>2"
5187   [(set (match_operand:BFP                   0 "register_operand"     "")
5188         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
5189   "TARGET_HARD_FLOAT
5190    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
5191
5192 ;
5193 ; extendddtd2 and extendsddd2 instruction pattern(s).
5194 ;
5195
5196 (define_insn "extendddtd2"
5197   [(set (match_operand:TD 0 "register_operand" "=f")
5198         (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
5199   "TARGET_HARD_DFP"
5200   "lxdtr\t%0,%1,0"
5201   [(set_attr "op_type" "RRF")
5202    (set_attr "type"    "fsimptf")])
5203
5204 (define_insn "extendsddd2"
5205   [(set (match_operand:DD 0 "register_operand" "=f")
5206         (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
5207   "TARGET_HARD_DFP"
5208   "ldetr\t%0,%1,0"
5209   [(set_attr "op_type" "RRF")
5210    (set_attr "type"    "fsimptf")])
5211
5212 (define_expand "extendsdtd2"
5213   [(set (match_dup 2)
5214         (float_extend:DD (match_operand:SD 1 "register_operand" "")))
5215    (set (match_operand:TD 0 "register_operand" "")
5216         (float_extend:TD (match_dup 2)))]
5217   "TARGET_HARD_DFP"
5218 {
5219   operands[2] = gen_reg_rtx (DDmode);
5220 })
5221
5222 ; Binary Floating Point - load fp integer
5223
5224 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
5225 ; For all of them the inexact exceptions are suppressed.
5226
5227 ; fiebra, fidbra, fixbra
5228 (define_insn "<FPINT:fpint_name><BFP:mode>2"
5229   [(set (match_operand:BFP 0 "register_operand" "=f")
5230         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5231                     FPINT))]
5232   "TARGET_Z196"
5233   "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
5234   [(set_attr "op_type"   "RRF")
5235    (set_attr "type"      "fsimp<BFP:mode>")])
5236
5237 ; rint is supposed to raise an inexact exception so we can use the
5238 ; older instructions.
5239
5240 ; fiebr, fidbr, fixbr
5241 (define_insn "rint<BFP:mode>2"
5242   [(set (match_operand:BFP 0 "register_operand" "=f")
5243         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5244                     UNSPEC_FPINT_RINT))]
5245   ""
5246   "fi<BFP:xde>br\t%0,0,%1"
5247   [(set_attr "op_type"   "RRF")
5248    (set_attr "type"      "fsimp<BFP:mode>")])
5249
5250
5251 ; Decimal Floating Point - load fp integer
5252
5253 ; fidtr, fixtr
5254 (define_insn "<FPINT:fpint_name><DFP:mode>2"
5255   [(set (match_operand:DFP 0 "register_operand" "=f")
5256         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5257                     FPINT))]
5258   "TARGET_HARD_DFP"
5259   "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
5260   [(set_attr "op_type"   "RRF")
5261    (set_attr "type"      "fsimp<DFP:mode>")])
5262
5263 ; fidtr, fixtr
5264 (define_insn "rint<DFP:mode>2"
5265   [(set (match_operand:DFP 0 "register_operand" "=f")
5266         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5267                     UNSPEC_FPINT_RINT))]
5268   "TARGET_HARD_DFP"
5269   "fi<DFP:xde>tr\t%0,0,%1,0"
5270   [(set_attr "op_type"   "RRF")
5271    (set_attr "type"      "fsimp<DFP:mode>")])
5272
5273 ;
5274 ; Binary <-> Decimal floating point trunc patterns
5275 ;
5276
5277 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
5278   [(set (reg:DFP_ALL FPR0_REGNUM)
5279         (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5280    (use (reg:SI GPR0_REGNUM))
5281    (clobber (reg:CC CC_REGNUM))
5282    (clobber (reg:SI GPR1_REGNUM))]
5283   "TARGET_HARD_DFP"
5284   "pfpo")
5285
5286 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
5287   [(set (reg:BFP FPR0_REGNUM)
5288         (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5289    (use (reg:SI GPR0_REGNUM))
5290    (clobber (reg:CC CC_REGNUM))
5291    (clobber (reg:SI GPR1_REGNUM))]
5292   "TARGET_HARD_DFP"
5293   "pfpo")
5294
5295 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
5296   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5297    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5298    (parallel
5299     [(set (reg:DFP_ALL FPR0_REGNUM)
5300           (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5301      (use (reg:SI GPR0_REGNUM))
5302      (clobber (reg:CC CC_REGNUM))
5303      (clobber (reg:SI GPR1_REGNUM))])
5304    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5305         (reg:DFP_ALL FPR0_REGNUM))]
5306   "TARGET_HARD_DFP
5307    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5308 {
5309   HOST_WIDE_INT flags;
5310
5311   flags = (PFPO_CONVERT |
5312            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5313            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5314
5315   operands[2] = GEN_INT (flags);
5316 })
5317
5318 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5319   [(set (reg:DFP_ALL FPR4_REGNUM)
5320         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5321    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5322    (parallel
5323     [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5324      (use (reg:SI GPR0_REGNUM))
5325      (clobber (reg:CC CC_REGNUM))
5326      (clobber (reg:SI GPR1_REGNUM))])
5327    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5328   "TARGET_HARD_DFP
5329    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5330 {
5331   HOST_WIDE_INT flags;
5332
5333   flags = (PFPO_CONVERT |
5334            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5335            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5336
5337   operands[2] = GEN_INT (flags);
5338 })
5339
5340 ;
5341 ; Binary <-> Decimal floating point extend patterns
5342 ;
5343
5344 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5345   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5346    (use (reg:SI GPR0_REGNUM))
5347    (clobber (reg:CC CC_REGNUM))
5348    (clobber (reg:SI GPR1_REGNUM))]
5349   "TARGET_HARD_DFP"
5350   "pfpo")
5351
5352 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5353   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5354    (use (reg:SI GPR0_REGNUM))
5355    (clobber (reg:CC CC_REGNUM))
5356    (clobber (reg:SI GPR1_REGNUM))]
5357   "TARGET_HARD_DFP"
5358   "pfpo")
5359
5360 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5361   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5362    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5363    (parallel
5364     [(set (reg:DFP_ALL FPR0_REGNUM)
5365           (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5366      (use (reg:SI GPR0_REGNUM))
5367      (clobber (reg:CC CC_REGNUM))
5368      (clobber (reg:SI GPR1_REGNUM))])
5369    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5370         (reg:DFP_ALL FPR0_REGNUM))]
5371   "TARGET_HARD_DFP
5372    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5373 {
5374   HOST_WIDE_INT flags;
5375
5376   flags = (PFPO_CONVERT |
5377            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5378            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5379
5380   operands[2] = GEN_INT (flags);
5381 })
5382
5383 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5384   [(set (reg:DFP_ALL FPR4_REGNUM)
5385         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5386    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5387    (parallel
5388     [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5389      (use (reg:SI GPR0_REGNUM))
5390      (clobber (reg:CC CC_REGNUM))
5391      (clobber (reg:SI GPR1_REGNUM))])
5392    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5393   "TARGET_HARD_DFP
5394    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5395 {
5396   HOST_WIDE_INT flags;
5397
5398   flags = (PFPO_CONVERT |
5399            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5400            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5401
5402   operands[2] = GEN_INT (flags);
5403 })
5404
5405
5406 ;;
5407 ;; ARITHMETIC OPERATIONS
5408 ;;
5409 ;  arithmetic operations set the ConditionCode,
5410 ;  because of unpredictable Bits in Register for Halfword and Byte
5411 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
5412
5413 ;;
5414 ;;- Add instructions.
5415 ;;
5416
5417 ;
5418 ; addti3 instruction pattern(s).
5419 ;
5420
5421 (define_expand "addti3"
5422   [(parallel
5423     [(set (match_operand:TI          0 "register_operand"     "")
5424           (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5425                    (match_operand:TI 2 "general_operand"      "") ) )
5426      (clobber (reg:CC CC_REGNUM))])]
5427   "TARGET_ZARCH"
5428 {
5429   /* For z13 we have vaq which doesn't set CC.  */
5430   if (TARGET_VX)
5431     {
5432       emit_insn (gen_rtx_SET (operands[0],
5433                               gen_rtx_PLUS (TImode,
5434                                             copy_to_mode_reg (TImode, operands[1]),
5435                                             copy_to_mode_reg (TImode, operands[2]))));
5436       DONE;
5437     }
5438 })
5439
5440 (define_insn_and_split "*addti3"
5441   [(set (match_operand:TI          0 "register_operand"    "=&d")
5442         (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5443                  (match_operand:TI 2 "general_operand"      "do") ) )
5444    (clobber (reg:CC CC_REGNUM))]
5445   "TARGET_ZARCH"
5446   "#"
5447   "&& reload_completed"
5448   [(parallel
5449     [(set (reg:CCL1 CC_REGNUM)
5450           (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5451                         (match_dup 7)))
5452      (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5453    (parallel
5454     [(set (match_dup 3) (plus:DI
5455                           (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5456                                    (match_dup 4)) (match_dup 5)))
5457      (clobber (reg:CC CC_REGNUM))])]
5458   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5459    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5460    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5461    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5462    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5463    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5464   [(set_attr "op_type"  "*")
5465    (set_attr "cpu_facility" "*")])
5466
5467 ;
5468 ; adddi3 instruction pattern(s).
5469 ;
5470
5471 (define_expand "adddi3"
5472   [(parallel
5473     [(set (match_operand:DI 0 "nonimmediate_operand" "")
5474           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5475                    (match_operand:DI 2 "general_operand" "")))
5476      (clobber (reg:CC CC_REGNUM))])]
5477   ""
5478   "")
5479
5480 (define_insn "*adddi3_sign"
5481   [(set (match_operand:DI 0 "register_operand" "=d,d")
5482         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5483                  (match_operand:DI 1 "register_operand" "0,0")))
5484    (clobber (reg:CC CC_REGNUM))]
5485   "TARGET_ZARCH"
5486   "@
5487    agfr\t%0,%2
5488    agf\t%0,%2"
5489   [(set_attr "op_type"  "RRE,RXY")
5490    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5491
5492 (define_insn "*adddi3_zero_cc"
5493   [(set (reg CC_REGNUM)
5494         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5495                           (match_operand:DI 1 "register_operand" "0,0"))
5496                  (const_int 0)))
5497    (set (match_operand:DI 0 "register_operand" "=d,d")
5498         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5499   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5500   "@
5501    algfr\t%0,%2
5502    algf\t%0,%2"
5503   [(set_attr "op_type"  "RRE,RXY")
5504    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5505
5506 (define_insn "*adddi3_zero_cconly"
5507   [(set (reg CC_REGNUM)
5508         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5509                           (match_operand:DI 1 "register_operand" "0,0"))
5510                  (const_int 0)))
5511    (clobber (match_scratch:DI 0 "=d,d"))]
5512   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5513   "@
5514    algfr\t%0,%2
5515    algf\t%0,%2"
5516   [(set_attr "op_type"  "RRE,RXY")
5517    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5518
5519 (define_insn "*adddi3_zero"
5520   [(set (match_operand:DI 0 "register_operand" "=d,d")
5521         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5522                  (match_operand:DI 1 "register_operand" "0,0")))
5523    (clobber (reg:CC CC_REGNUM))]
5524   "TARGET_ZARCH"
5525   "@
5526    algfr\t%0,%2
5527    algf\t%0,%2"
5528   [(set_attr "op_type"  "RRE,RXY")
5529    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5530
5531 (define_insn_and_split "*adddi3_31z"
5532   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5533         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5534                  (match_operand:DI 2 "general_operand" "do") ) )
5535    (clobber (reg:CC CC_REGNUM))]
5536   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5537   "#"
5538   "&& reload_completed"
5539   [(parallel
5540     [(set (reg:CCL1 CC_REGNUM)
5541           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5542                         (match_dup 7)))
5543      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5544    (parallel
5545     [(set (match_dup 3) (plus:SI
5546                           (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5547                                    (match_dup 4)) (match_dup 5)))
5548      (clobber (reg:CC CC_REGNUM))])]
5549   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5550    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5551    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5552    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5553    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5554    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5555
5556 (define_insn_and_split "*adddi3_31"
5557   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5558         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5559                  (match_operand:DI 2 "general_operand" "do") ) )
5560    (clobber (reg:CC CC_REGNUM))]
5561   "!TARGET_CPU_ZARCH"
5562   "#"
5563   "&& reload_completed"
5564   [(parallel
5565     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5566      (clobber (reg:CC CC_REGNUM))])
5567    (parallel
5568     [(set (reg:CCL1 CC_REGNUM)
5569           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5570                         (match_dup 7)))
5571      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5572    (set (pc)
5573         (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5574                       (pc)
5575                       (label_ref (match_dup 9))))
5576    (parallel
5577     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5578      (clobber (reg:CC CC_REGNUM))])
5579    (match_dup 9)]
5580   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5581    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5582    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5583    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5584    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5585    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5586    operands[9] = gen_label_rtx ();")
5587
5588 ;
5589 ; addsi3 instruction pattern(s).
5590 ;
5591
5592 (define_expand "addsi3"
5593   [(parallel
5594     [(set (match_operand:SI 0 "nonimmediate_operand" "")
5595           (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5596                    (match_operand:SI 2 "general_operand" "")))
5597      (clobber (reg:CC CC_REGNUM))])]
5598   ""
5599   "")
5600
5601 (define_insn "*addsi3_sign"
5602   [(set (match_operand:SI 0 "register_operand" "=d,d")
5603         (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5604                  (match_operand:SI 1 "register_operand" "0,0")))
5605    (clobber (reg:CC CC_REGNUM))]
5606   ""
5607   "@
5608    ah\t%0,%2
5609    ahy\t%0,%2"
5610   [(set_attr "op_type"  "RX,RXY")
5611    (set_attr "cpu_facility" "*,longdisp")
5612    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5613
5614 ;
5615 ; add(di|si)3 instruction pattern(s).
5616 ;
5617
5618 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5619 (define_insn "*add<mode>3"
5620   [(set (match_operand:GPR 0 "nonimmediate_operand"           "=d,d,d,d, d, d,d,d,S")
5621         (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
5622                   (match_operand:GPR 2 "general_operand"      " d,d,K,K,Op,On,R,T,C") ) )
5623    (clobber (reg:CC CC_REGNUM))]
5624   ""
5625   "@
5626    a<g>r\t%0,%2
5627    a<g>rk\t%0,%1,%2
5628    a<g>hi\t%0,%h2
5629    a<g>hik\t%0,%1,%h2
5630    al<g>fi\t%0,%2
5631    sl<g>fi\t%0,%n2
5632    a<g>\t%0,%2
5633    a<y>\t%0,%2
5634    a<g>si\t%0,%c2"
5635   [(set_attr "op_type"  "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5636    (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
5637    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5638                         z10_super_E1,z10_super_E1,z10_super_E1")])
5639
5640 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5641 (define_insn "*add<mode>3_carry1_cc"
5642   [(set (reg CC_REGNUM)
5643         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5644                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5645                  (match_dup 1)))
5646    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,d")
5647         (plus:GPR (match_dup 1) (match_dup 2)))]
5648   "s390_match_ccmode (insn, CCL1mode)"
5649   "@
5650    al<g>r\t%0,%2
5651    al<g>rk\t%0,%1,%2
5652    al<g>fi\t%0,%2
5653    sl<g>fi\t%0,%n2
5654    al<g>hsik\t%0,%1,%h2
5655    al<g>\t%0,%2
5656    al<y>\t%0,%2
5657    al<g>si\t%0,%c2"
5658   [(set_attr "op_type"      "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5659    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5660    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5661                         z10_super_E1,z10_super_E1,z10_super_E1")])
5662
5663 ; alr, al, aly, algr, alg, alrk, algrk
5664 (define_insn "*add<mode>3_carry1_cconly"
5665   [(set (reg CC_REGNUM)
5666         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5667                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5668                  (match_dup 1)))
5669    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5670   "s390_match_ccmode (insn, CCL1mode)"
5671   "@
5672    al<g>r\t%0,%2
5673    al<g>rk\t%0,%1,%2
5674    al<g>\t%0,%2
5675    al<y>\t%0,%2"
5676   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5677    (set_attr "cpu_facility" "*,z196,*,longdisp")
5678    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5679
5680 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5681 (define_insn "*add<mode>3_carry2_cc"
5682   [(set (reg CC_REGNUM)
5683         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5684                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5685                  (match_dup 2)))
5686    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,S")
5687         (plus:GPR (match_dup 1) (match_dup 2)))]
5688   "s390_match_ccmode (insn, CCL1mode)"
5689   "@
5690    al<g>r\t%0,%2
5691    al<g>rk\t%0,%1,%2
5692    al<g>fi\t%0,%2
5693    sl<g>fi\t%0,%n2
5694    al<g>hsik\t%0,%1,%h2
5695    al<g>\t%0,%2
5696    al<y>\t%0,%2
5697    al<g>si\t%0,%c2"
5698   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5699    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5700    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5701                         z10_super_E1,z10_super_E1,z10_super_E1")])
5702
5703 ; alr, al, aly, algr, alg, alrk, algrk
5704 (define_insn "*add<mode>3_carry2_cconly"
5705   [(set (reg CC_REGNUM)
5706         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5707                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5708                  (match_dup 2)))
5709    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5710   "s390_match_ccmode (insn, CCL1mode)"
5711   "@
5712    al<g>r\t%0,%2
5713    al<g>rk\t%0,%1,%2
5714    al<g>\t%0,%2
5715    al<y>\t%0,%2"
5716   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5717    (set_attr "cpu_facility" "*,z196,*,longdisp")
5718    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5719
5720 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5721 (define_insn "*add<mode>3_cc"
5722   [(set (reg CC_REGNUM)
5723         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5724                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5725                  (const_int 0)))
5726    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,S")
5727         (plus:GPR (match_dup 1) (match_dup 2)))]
5728   "s390_match_ccmode (insn, CCLmode)"
5729   "@
5730    al<g>r\t%0,%2
5731    al<g>rk\t%0,%1,%2
5732    al<g>fi\t%0,%2
5733    sl<g>fi\t%0,%n2
5734    al<g>hsik\t%0,%1,%h2
5735    al<g>\t%0,%2
5736    al<y>\t%0,%2
5737    al<g>si\t%0,%c2"
5738   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5739    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5740    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5741                         *,z10_super_E1,z10_super_E1,z10_super_E1")])
5742
5743 ; alr, al, aly, algr, alg, alrk, algrk
5744 (define_insn "*add<mode>3_cconly"
5745   [(set (reg CC_REGNUM)
5746         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5747                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5748                  (const_int 0)))
5749    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5750   "s390_match_ccmode (insn, CCLmode)"
5751   "@
5752    al<g>r\t%0,%2
5753    al<g>rk\t%0,%1,%2
5754    al<g>\t%0,%2
5755    al<y>\t%0,%2"
5756   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5757    (set_attr "cpu_facility" "*,z196,*,longdisp")
5758    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5759
5760 ; alr, al, aly, algr, alg, alrk, algrk
5761 (define_insn "*add<mode>3_cconly2"
5762   [(set (reg CC_REGNUM)
5763         (compare (match_operand:GPR 1 "nonimmediate_operand"    "%0,d,0,0")
5764                  (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5765    (clobber (match_scratch:GPR 0                                "=d,d,d,d"))]
5766   "s390_match_ccmode(insn, CCLmode)"
5767   "@
5768    al<g>r\t%0,%2
5769    al<g>rk\t%0,%1,%2
5770    al<g>\t%0,%2
5771    al<y>\t%0,%2"
5772   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5773    (set_attr "cpu_facility" "*,z196,*,longdisp")
5774    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5775
5776 ; ahi, afi, aghi, agfi, asi, agsi
5777 (define_insn "*add<mode>3_imm_cc"
5778   [(set (reg CC_REGNUM)
5779         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5780                            (match_operand:GPR 2 "const_int_operand"    " K, K,Os,C"))
5781                  (const_int 0)))
5782    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d, d,d, S")
5783         (plus:GPR (match_dup 1) (match_dup 2)))]
5784   "s390_match_ccmode (insn, CCAmode)
5785    && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5786        || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5787            /* Avoid INT32_MIN on 32 bit.  */
5788            && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5789   "@
5790    a<g>hi\t%0,%h2
5791    a<g>hik\t%0,%1,%h2
5792    a<g>fi\t%0,%2
5793    a<g>si\t%0,%c2"
5794   [(set_attr "op_type"      "RI,RIE,RIL,SIY")
5795    (set_attr "cpu_facility" "*,z196,extimm,z10")
5796    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5797
5798 ;
5799 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5800 ;
5801
5802 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5803 ; FIXME: wfadb does not clobber cc
5804 (define_insn "add<mode>3"
5805   [(set (match_operand:FP 0 "register_operand"              "=f,f,f,v")
5806         (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
5807                  (match_operand:FP 2 "general_operand"       "f,f,R,v")))
5808    (clobber (reg:CC CC_REGNUM))]
5809   "TARGET_HARD_FLOAT"
5810   "@
5811    a<xde>tr\t%0,%1,%2
5812    a<xde>br\t%0,%2
5813    a<xde>b\t%0,%2
5814    wfadb\t%v0,%v1,%v2"
5815   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
5816    (set_attr "type"         "fsimp<mode>")
5817    (set_attr "cpu_facility" "*,*,*,vx")
5818    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5819
5820 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5821 (define_insn "*add<mode>3_cc"
5822   [(set (reg CC_REGNUM)
5823         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5824                           (match_operand:FP 2 "general_operand"       "f,f,R"))
5825                  (match_operand:FP 3 "const0_operand" "")))
5826    (set (match_operand:FP 0 "register_operand" "=f,f,f")
5827         (plus:FP (match_dup 1) (match_dup 2)))]
5828   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5829   "@
5830    a<xde>tr\t%0,%1,%2
5831    a<xde>br\t%0,%2
5832    a<xde>b\t%0,%2"
5833   [(set_attr "op_type"  "RRF,RRE,RXE")
5834    (set_attr "type"     "fsimp<mode>")
5835    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5836
5837 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5838 (define_insn "*add<mode>3_cconly"
5839   [(set (reg CC_REGNUM)
5840         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5841                           (match_operand:FP 2 "general_operand"       "f,f,R"))
5842                  (match_operand:FP 3 "const0_operand" "")))
5843    (clobber (match_scratch:FP 0 "=f,f,f"))]
5844   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5845   "@
5846    a<xde>tr\t%0,%1,%2
5847    a<xde>br\t%0,%2
5848    a<xde>b\t%0,%2"
5849   [(set_attr "op_type"  "RRF,RRE,RXE")
5850    (set_attr "type"     "fsimp<mode>")
5851    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5852
5853 ;
5854 ; Pointer add instruction patterns
5855 ;
5856
5857 ; This will match "*la_64"
5858 (define_expand "addptrdi3"
5859   [(set (match_operand:DI 0 "register_operand" "")
5860         (plus:DI (match_operand:DI 1 "register_operand" "")
5861                  (match_operand:DI 2 "nonmemory_operand" "")))]
5862   "TARGET_64BIT"
5863 {
5864   if (GET_CODE (operands[2]) == CONST_INT)
5865     {
5866       HOST_WIDE_INT c = INTVAL (operands[2]);
5867
5868       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5869           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5870         {
5871           operands[2] = force_const_mem (DImode, operands[2]);
5872           operands[2] = force_reg (DImode, operands[2]);
5873         }
5874       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5875         operands[2] = force_reg (DImode, operands[2]);
5876     }
5877 })
5878
5879 ; For 31 bit we have to prevent the generated pattern from matching
5880 ; normal ADDs since la only does a 31 bit add.  This is supposed to
5881 ; match "force_la_31".
5882 (define_expand "addptrsi3"
5883   [(parallel
5884     [(set (match_operand:SI 0 "register_operand" "")
5885           (plus:SI (match_operand:SI 1 "register_operand" "")
5886                    (match_operand:SI 2 "nonmemory_operand" "")))
5887                    (use (const_int 0))])]
5888   "!TARGET_64BIT"
5889 {
5890   if (GET_CODE (operands[2]) == CONST_INT)
5891     {
5892       HOST_WIDE_INT c = INTVAL (operands[2]);
5893
5894       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5895           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5896         {
5897           operands[2] = force_const_mem (SImode, operands[2]);
5898           operands[2] = force_reg (SImode, operands[2]);
5899         }
5900       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5901         operands[2] = force_reg (SImode, operands[2]);
5902     }
5903 })
5904
5905 ;;
5906 ;;- Subtract instructions.
5907 ;;
5908
5909 ;
5910 ; subti3 instruction pattern(s).
5911 ;
5912
5913 (define_expand "subti3"
5914   [(parallel
5915     [(set (match_operand:TI           0 "register_operand" "")
5916           (minus:TI (match_operand:TI 1 "register_operand" "")
5917                     (match_operand:TI 2 "general_operand"  "") ) )
5918      (clobber (reg:CC CC_REGNUM))])]
5919   "TARGET_ZARCH"
5920 {
5921   /* For z13 we have vsq which doesn't set CC.  */
5922   if (TARGET_VX)
5923     {
5924       emit_insn (gen_rtx_SET (operands[0],
5925                               gen_rtx_MINUS (TImode,
5926                                             operands[1],
5927                                             copy_to_mode_reg (TImode, operands[2]))));
5928       DONE;
5929     }
5930 })
5931
5932 (define_insn_and_split "*subti3"
5933   [(set (match_operand:TI           0 "register_operand" "=&d")
5934         (minus:TI (match_operand:TI 1 "register_operand"   "0")
5935                   (match_operand:TI 2 "general_operand"   "do") ) )
5936    (clobber (reg:CC CC_REGNUM))]
5937   "TARGET_ZARCH"
5938   "#"
5939   "&& reload_completed"
5940   [(parallel
5941     [(set (reg:CCL2 CC_REGNUM)
5942           (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5943                         (match_dup 7)))
5944      (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5945    (parallel
5946     [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5947                                   (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5948      (clobber (reg:CC CC_REGNUM))])]
5949   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5950    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5951    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5952    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5953    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5954    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5955   [(set_attr "op_type"      "*")
5956    (set_attr "cpu_facility" "*")])
5957
5958 ;
5959 ; subdi3 instruction pattern(s).
5960 ;
5961
5962 (define_expand "subdi3"
5963   [(parallel
5964     [(set (match_operand:DI 0 "register_operand" "")
5965           (minus:DI (match_operand:DI 1 "register_operand" "")
5966                     (match_operand:DI 2 "general_operand" "")))
5967      (clobber (reg:CC CC_REGNUM))])]
5968   ""
5969   "")
5970
5971 (define_insn "*subdi3_sign"
5972   [(set (match_operand:DI 0 "register_operand" "=d,d")
5973         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5974                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5975    (clobber (reg:CC CC_REGNUM))]
5976   "TARGET_ZARCH"
5977   "@
5978    sgfr\t%0,%2
5979    sgf\t%0,%2"
5980   [(set_attr "op_type"  "RRE,RXY")
5981    (set_attr "z10prop" "z10_c,*")
5982    (set_attr "z196prop" "z196_cracked")])
5983
5984 (define_insn "*subdi3_zero_cc"
5985   [(set (reg CC_REGNUM)
5986         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5987                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5988                  (const_int 0)))
5989    (set (match_operand:DI 0 "register_operand" "=d,d")
5990         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5991   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5992   "@
5993    slgfr\t%0,%2
5994    slgf\t%0,%2"
5995   [(set_attr "op_type"  "RRE,RXY")
5996    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5997
5998 (define_insn "*subdi3_zero_cconly"
5999   [(set (reg CC_REGNUM)
6000         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6001                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
6002                  (const_int 0)))
6003    (clobber (match_scratch:DI 0 "=d,d"))]
6004   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
6005   "@
6006    slgfr\t%0,%2
6007    slgf\t%0,%2"
6008   [(set_attr "op_type"  "RRE,RXY")
6009    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
6010
6011 (define_insn "*subdi3_zero"
6012   [(set (match_operand:DI 0 "register_operand" "=d,d")
6013         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6014                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
6015    (clobber (reg:CC CC_REGNUM))]
6016   "TARGET_ZARCH"
6017   "@
6018    slgfr\t%0,%2
6019    slgf\t%0,%2"
6020   [(set_attr "op_type"  "RRE,RXY")
6021    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
6022
6023 (define_insn_and_split "*subdi3_31z"
6024   [(set (match_operand:DI 0 "register_operand" "=&d")
6025         (minus:DI (match_operand:DI 1 "register_operand" "0")
6026                   (match_operand:DI 2 "general_operand" "do") ) )
6027    (clobber (reg:CC CC_REGNUM))]
6028   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6029   "#"
6030   "&& reload_completed"
6031   [(parallel
6032     [(set (reg:CCL2 CC_REGNUM)
6033           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
6034                         (match_dup 7)))
6035      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
6036    (parallel
6037     [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
6038                                   (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
6039      (clobber (reg:CC CC_REGNUM))])]
6040   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
6041    operands[4] = operand_subword (operands[1], 0, 0, DImode);
6042    operands[5] = operand_subword (operands[2], 0, 0, DImode);
6043    operands[6] = operand_subword (operands[0], 1, 0, DImode);
6044    operands[7] = operand_subword (operands[1], 1, 0, DImode);
6045    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
6046
6047 (define_insn_and_split "*subdi3_31"
6048   [(set (match_operand:DI 0 "register_operand" "=&d")
6049         (minus:DI (match_operand:DI 1 "register_operand" "0")
6050                   (match_operand:DI 2 "general_operand" "do") ) )
6051    (clobber (reg:CC CC_REGNUM))]
6052   "!TARGET_CPU_ZARCH"
6053   "#"
6054   "&& reload_completed"
6055   [(parallel
6056     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
6057      (clobber (reg:CC CC_REGNUM))])
6058    (parallel
6059     [(set (reg:CCL2 CC_REGNUM)
6060           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
6061                         (match_dup 7)))
6062      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
6063    (set (pc)
6064         (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
6065                       (pc)
6066                       (label_ref (match_dup 9))))
6067    (parallel
6068     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
6069      (clobber (reg:CC CC_REGNUM))])
6070    (match_dup 9)]
6071   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
6072    operands[4] = operand_subword (operands[1], 0, 0, DImode);
6073    operands[5] = operand_subword (operands[2], 0, 0, DImode);
6074    operands[6] = operand_subword (operands[0], 1, 0, DImode);
6075    operands[7] = operand_subword (operands[1], 1, 0, DImode);
6076    operands[8] = operand_subword (operands[2], 1, 0, DImode);
6077    operands[9] = gen_label_rtx ();")
6078
6079 ;
6080 ; subsi3 instruction pattern(s).
6081 ;
6082
6083 (define_expand "subsi3"
6084   [(parallel
6085     [(set (match_operand:SI 0 "register_operand" "")
6086           (minus:SI (match_operand:SI 1 "register_operand" "")
6087                     (match_operand:SI 2 "general_operand" "")))
6088      (clobber (reg:CC CC_REGNUM))])]
6089   ""
6090   "")
6091
6092 (define_insn "*subsi3_sign"
6093   [(set (match_operand:SI 0 "register_operand" "=d,d")
6094         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6095                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
6096    (clobber (reg:CC CC_REGNUM))]
6097   ""
6098   "@
6099    sh\t%0,%2
6100    shy\t%0,%2"
6101   [(set_attr "op_type"  "RX,RXY")
6102    (set_attr "cpu_facility" "*,longdisp")
6103    (set_attr "z196prop" "z196_cracked,z196_cracked")])
6104
6105 ;
6106 ; sub(di|si)3 instruction pattern(s).
6107 ;
6108
6109 ; sr, s, sy, sgr, sg, srk, sgrk
6110 (define_insn "*sub<mode>3"
6111   [(set (match_operand:GPR 0 "register_operand"           "=d,d,d,d")
6112         (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6113                    (match_operand:GPR 2 "general_operand"  "d,d,R,T") ) )
6114    (clobber (reg:CC CC_REGNUM))]
6115   ""
6116   "@
6117    s<g>r\t%0,%2
6118    s<g>rk\t%0,%1,%2
6119    s<g>\t%0,%2
6120    s<y>\t%0,%2"
6121   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
6122    (set_attr "cpu_facility" "*,z196,*,longdisp")
6123    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6124
6125 ; slr, sl, sly, slgr, slg, slrk, slgrk
6126 (define_insn "*sub<mode>3_borrow_cc"
6127   [(set (reg CC_REGNUM)
6128         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6129                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
6130                  (match_dup 1)))
6131    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
6132         (minus:GPR (match_dup 1) (match_dup 2)))]
6133   "s390_match_ccmode (insn, CCL2mode)"
6134   "@
6135    sl<g>r\t%0,%2
6136    sl<g>rk\t%0,%1,%2
6137    sl<g>\t%0,%2
6138    sl<y>\t%0,%2"
6139   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
6140    (set_attr "cpu_facility" "*,z196,*,longdisp")
6141    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6142
6143 ; slr, sl, sly, slgr, slg, slrk, slgrk
6144 (define_insn "*sub<mode>3_borrow_cconly"
6145   [(set (reg CC_REGNUM)
6146         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6147                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
6148                  (match_dup 1)))
6149    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
6150   "s390_match_ccmode (insn, CCL2mode)"
6151   "@
6152    sl<g>r\t%0,%2
6153    sl<g>rk\t%0,%1,%2
6154    sl<g>\t%0,%2
6155    sl<y>\t%0,%2"
6156   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
6157    (set_attr "cpu_facility" "*,z196,*,longdisp")
6158    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6159
6160 ; slr, sl, sly, slgr, slg, slrk, slgrk
6161 (define_insn "*sub<mode>3_cc"
6162   [(set (reg CC_REGNUM)
6163         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6164                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
6165                  (const_int 0)))
6166    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
6167         (minus:GPR (match_dup 1) (match_dup 2)))]
6168   "s390_match_ccmode (insn, CCLmode)"
6169   "@
6170    sl<g>r\t%0,%2
6171    sl<g>rk\t%0,%1,%2
6172    sl<g>\t%0,%2
6173    sl<y>\t%0,%2"
6174   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
6175    (set_attr "cpu_facility" "*,z196,*,longdisp")
6176    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6177
6178 ; slr, sl, sly, slgr, slg, slrk, slgrk
6179 (define_insn "*sub<mode>3_cc2"
6180   [(set (reg CC_REGNUM)
6181         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6182                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
6183    (set (match_operand:GPR 0 "register_operand"         "=d,d,d,d")
6184         (minus:GPR (match_dup 1) (match_dup 2)))]
6185   "s390_match_ccmode (insn, CCL3mode)"
6186   "@
6187    sl<g>r\t%0,%2
6188    sl<g>rk\t%0,%1,%2
6189    sl<g>\t%0,%2
6190    sl<y>\t%0,%2"
6191   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
6192    (set_attr "cpu_facility" "*,z196,*,longdisp")
6193    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6194
6195 ; slr, sl, sly, slgr, slg, slrk, slgrk
6196 (define_insn "*sub<mode>3_cconly"
6197   [(set (reg CC_REGNUM)
6198         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6199                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
6200                  (const_int 0)))
6201    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
6202   "s390_match_ccmode (insn, CCLmode)"
6203   "@
6204    sl<g>r\t%0,%2
6205    sl<g>rk\t%0,%1,%2
6206    sl<g>\t%0,%2
6207    sl<y>\t%0,%2"
6208   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
6209    (set_attr "cpu_facility" "*,z196,*,longdisp")
6210    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6211
6212
6213 ; slr, sl, sly, slgr, slg, slrk, slgrk
6214 (define_insn "*sub<mode>3_cconly2"
6215   [(set (reg CC_REGNUM)
6216         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6217                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
6218    (clobber (match_scratch:GPR 0                        "=d,d,d,d"))]
6219   "s390_match_ccmode (insn, CCL3mode)"
6220   "@
6221    sl<g>r\t%0,%2
6222    sl<g>rk\t%0,%1,%2
6223    sl<g>\t%0,%2
6224    sl<y>\t%0,%2"
6225   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
6226    (set_attr "cpu_facility" "*,z196,*,longdisp")
6227    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6228
6229
6230 ;
6231 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
6232 ;
6233
6234 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6235 (define_insn "sub<mode>3"
6236   [(set (match_operand:FP           0 "register_operand" "=f,f,f,v")
6237         (minus:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
6238                   (match_operand:FP 2 "general_operand"   "f,f,R,v")))
6239    (clobber (reg:CC CC_REGNUM))]
6240   "TARGET_HARD_FLOAT"
6241   "@
6242    s<xde>tr\t%0,%1,%2
6243    s<xde>br\t%0,%2
6244    s<xde>b\t%0,%2
6245    wfsdb\t%v0,%v1,%v2"
6246   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6247    (set_attr "type"         "fsimp<mode>")
6248    (set_attr "cpu_facility" "*,*,*,vx")
6249    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6250
6251 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6252 (define_insn "*sub<mode>3_cc"
6253   [(set (reg CC_REGNUM)
6254         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6255                            (match_operand:FP 2 "general_operand"      "f,f,R"))
6256                  (match_operand:FP 3 "const0_operand" "")))
6257    (set (match_operand:FP 0 "register_operand" "=f,f,f")
6258         (minus:FP (match_dup 1) (match_dup 2)))]
6259   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6260   "@
6261    s<xde>tr\t%0,%1,%2
6262    s<xde>br\t%0,%2
6263    s<xde>b\t%0,%2"
6264   [(set_attr "op_type"  "RRF,RRE,RXE")
6265    (set_attr "type"     "fsimp<mode>")
6266    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
6267
6268 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6269 (define_insn "*sub<mode>3_cconly"
6270   [(set (reg CC_REGNUM)
6271         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6272                            (match_operand:FP 2 "general_operand"      "f,f,R"))
6273                  (match_operand:FP 3 "const0_operand" "")))
6274    (clobber (match_scratch:FP 0 "=f,f,f"))]
6275   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6276   "@
6277    s<xde>tr\t%0,%1,%2
6278    s<xde>br\t%0,%2
6279    s<xde>b\t%0,%2"
6280   [(set_attr "op_type"  "RRF,RRE,RXE")
6281    (set_attr "type"     "fsimp<mode>")
6282    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
6283
6284
6285 ;;
6286 ;;- Conditional add/subtract instructions.
6287 ;;
6288
6289 ;
6290 ; add(di|si)cc instruction pattern(s).
6291 ;
6292
6293 ; the following 4 patterns are used when the result of an add with
6294 ; carry is checked for an overflow condition
6295
6296 ; op1 + op2 + c < op1
6297
6298 ; alcr, alc, alcgr, alcg
6299 (define_insn "*add<mode>3_alc_carry1_cc"
6300   [(set (reg CC_REGNUM)
6301         (compare
6302           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6303                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6304                     (match_operand:GPR 2 "general_operand" "d,T"))
6305           (match_dup 1)))
6306    (set (match_operand:GPR 0 "register_operand" "=d,d")
6307         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6308   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6309   "@
6310    alc<g>r\t%0,%2
6311    alc<g>\t%0,%2"
6312   [(set_attr "op_type"  "RRE,RXY")
6313    (set_attr "z196prop" "z196_alone,z196_alone")])
6314
6315 ; alcr, alc, alcgr, alcg
6316 (define_insn "*add<mode>3_alc_carry1_cconly"
6317   [(set (reg CC_REGNUM)
6318         (compare
6319           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6320                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6321                     (match_operand:GPR 2 "general_operand" "d,T"))
6322           (match_dup 1)))
6323    (clobber (match_scratch:GPR 0 "=d,d"))]
6324   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6325   "@
6326    alc<g>r\t%0,%2
6327    alc<g>\t%0,%2"
6328   [(set_attr "op_type"  "RRE,RXY")
6329    (set_attr "z196prop" "z196_alone,z196_alone")])
6330
6331 ; op1 + op2 + c < op2
6332
6333 ; alcr, alc, alcgr, alcg
6334 (define_insn "*add<mode>3_alc_carry2_cc"
6335   [(set (reg CC_REGNUM)
6336         (compare
6337           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6338                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6339                     (match_operand:GPR 2 "general_operand" "d,T"))
6340           (match_dup 2)))
6341    (set (match_operand:GPR 0 "register_operand" "=d,d")
6342         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6343   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6344   "@
6345    alc<g>r\t%0,%2
6346    alc<g>\t%0,%2"
6347   [(set_attr "op_type"  "RRE,RXY")])
6348
6349 ; alcr, alc, alcgr, alcg
6350 (define_insn "*add<mode>3_alc_carry2_cconly"
6351   [(set (reg CC_REGNUM)
6352         (compare
6353           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6354                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6355                     (match_operand:GPR 2 "general_operand" "d,T"))
6356           (match_dup 2)))
6357    (clobber (match_scratch:GPR 0 "=d,d"))]
6358   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6359   "@
6360    alc<g>r\t%0,%2
6361    alc<g>\t%0,%2"
6362   [(set_attr "op_type"  "RRE,RXY")])
6363
6364 ; alcr, alc, alcgr, alcg
6365 (define_insn "*add<mode>3_alc_cc"
6366   [(set (reg CC_REGNUM)
6367         (compare
6368           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6369                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6370                     (match_operand:GPR 2 "general_operand" "d,T"))
6371           (const_int 0)))
6372    (set (match_operand:GPR 0 "register_operand" "=d,d")
6373         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6374   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6375   "@
6376    alc<g>r\t%0,%2
6377    alc<g>\t%0,%2"
6378   [(set_attr "op_type"  "RRE,RXY")])
6379
6380 ; alcr, alc, alcgr, alcg
6381 (define_insn "*add<mode>3_alc"
6382   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6383         (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6384                             (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6385                   (match_operand:GPR 2 "general_operand" "d,T")))
6386    (clobber (reg:CC CC_REGNUM))]
6387   "TARGET_CPU_ZARCH"
6388   "@
6389    alc<g>r\t%0,%2
6390    alc<g>\t%0,%2"
6391   [(set_attr "op_type"  "RRE,RXY")])
6392
6393 ; slbr, slb, slbgr, slbg
6394 (define_insn "*sub<mode>3_slb_cc"
6395   [(set (reg CC_REGNUM)
6396         (compare
6397           (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6398                                 (match_operand:GPR 2 "general_operand" "d,T"))
6399                      (match_operand:GPR 3 "s390_slb_comparison" ""))
6400           (const_int 0)))
6401    (set (match_operand:GPR 0 "register_operand" "=d,d")
6402         (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6403   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6404   "@
6405    slb<g>r\t%0,%2
6406    slb<g>\t%0,%2"
6407   [(set_attr "op_type"  "RRE,RXY")
6408    (set_attr "z10prop" "z10_c,*")])
6409
6410 ; slbr, slb, slbgr, slbg
6411 (define_insn "*sub<mode>3_slb"
6412   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6413         (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6414                               (match_operand:GPR 2 "general_operand" "d,T"))
6415                    (match_operand:GPR 3 "s390_slb_comparison" "")))
6416    (clobber (reg:CC CC_REGNUM))]
6417   "TARGET_CPU_ZARCH"
6418   "@
6419    slb<g>r\t%0,%2
6420    slb<g>\t%0,%2"
6421   [(set_attr "op_type"  "RRE,RXY")
6422    (set_attr "z10prop" "z10_c,*")])
6423
6424 (define_expand "add<mode>cc"
6425   [(match_operand:GPR 0 "register_operand" "")
6426    (match_operand 1 "comparison_operator" "")
6427    (match_operand:GPR 2 "register_operand" "")
6428    (match_operand:GPR 3 "const_int_operand" "")]
6429   "TARGET_CPU_ZARCH"
6430   "if (!s390_expand_addcc (GET_CODE (operands[1]),
6431                            XEXP (operands[1], 0), XEXP (operands[1], 1),
6432                            operands[0], operands[2],
6433                            operands[3])) FAIL; DONE;")
6434
6435 ;
6436 ; scond instruction pattern(s).
6437 ;
6438
6439 (define_insn_and_split "*scond<mode>"
6440   [(set (match_operand:GPR 0 "register_operand" "=&d")
6441         (match_operand:GPR 1 "s390_alc_comparison" ""))
6442    (clobber (reg:CC CC_REGNUM))]
6443   "TARGET_CPU_ZARCH"
6444   "#"
6445   "&& reload_completed"
6446   [(set (match_dup 0) (const_int 0))
6447    (parallel
6448     [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6449                                   (match_dup 0)))
6450      (clobber (reg:CC CC_REGNUM))])]
6451   "")
6452
6453 (define_insn_and_split "*scond<mode>_neg"
6454   [(set (match_operand:GPR 0 "register_operand" "=&d")
6455         (match_operand:GPR 1 "s390_slb_comparison" ""))
6456    (clobber (reg:CC CC_REGNUM))]
6457   "TARGET_CPU_ZARCH"
6458   "#"
6459   "&& reload_completed"
6460   [(set (match_dup 0) (const_int 0))
6461    (parallel
6462     [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6463                                    (match_dup 1)))
6464      (clobber (reg:CC CC_REGNUM))])
6465    (parallel
6466     [(set (match_dup 0) (neg:GPR (match_dup 0)))
6467      (clobber (reg:CC CC_REGNUM))])]
6468   "")
6469
6470
6471 (define_expand "cstore<mode>4"
6472   [(set (match_operand:SI 0 "register_operand" "")
6473         (match_operator:SI 1 "s390_scond_operator"
6474          [(match_operand:GPR 2 "register_operand" "")
6475           (match_operand:GPR 3 "general_operand" "")]))]
6476   "TARGET_CPU_ZARCH"
6477   "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6478                            operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6479
6480 (define_expand "cstorecc4"
6481   [(parallel
6482     [(set (match_operand:SI 0 "register_operand" "")
6483           (match_operator:SI 1 "s390_eqne_operator"
6484            [(match_operand:CCZ1 2 "register_operand")
6485             (match_operand 3 "const0_operand")]))
6486      (clobber (reg:CC CC_REGNUM))])]
6487   ""
6488   "emit_insn (gen_sne (operands[0], operands[2]));
6489    if (GET_CODE (operands[1]) == EQ)
6490      emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6491    DONE;")
6492
6493 (define_insn_and_split "sne"
6494   [(set (match_operand:SI 0 "register_operand" "=d")
6495         (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6496                (const_int 0)))
6497    (clobber (reg:CC CC_REGNUM))]
6498   ""
6499   "#"
6500   "reload_completed"
6501   [(parallel
6502     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6503      (clobber (reg:CC CC_REGNUM))])])
6504
6505
6506 ;;
6507 ;; - Conditional move instructions (introduced with z196)
6508 ;;
6509
6510 (define_expand "mov<mode>cc"
6511   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6512         (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6513                           (match_operand:GPR 2 "nonimmediate_operand" "")
6514                           (match_operand:GPR 3 "nonimmediate_operand" "")))]
6515   "TARGET_Z196"
6516 {
6517   /* Emit the comparison insn in case we do not already have a comparison result.  */
6518   if (!s390_comparison (operands[1], VOIDmode))
6519     operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6520                                      XEXP (operands[1], 0),
6521                                      XEXP (operands[1], 1));
6522 })
6523
6524 ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
6525 (define_insn_and_split "*mov<mode>cc"
6526   [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d,d,d,d,d,S,S,&d")
6527         (if_then_else:GPR
6528           (match_operator 1 "s390_comparison"
6529             [(match_operand 2 "cc_reg_operand"        " c,c,c,c,c,c,c,c,c")
6530              (match_operand 5 "const_int_operand"     "")])
6531           (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S")
6532           (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))]
6533   "TARGET_Z196"
6534   "@
6535    loc<g>r%C1\t%0,%3
6536    loc<g>r%D1\t%0,%4
6537    loc<g>%C1\t%0,%3
6538    loc<g>%D1\t%0,%4
6539    loc<g>hi%C1\t%0,%h3
6540    loc<g>hi%D1\t%0,%h4
6541    stoc<g>%C1\t%3,%0
6542    stoc<g>%D1\t%4,%0
6543    #"
6544   "&& reload_completed
6545    && MEM_P (operands[3]) && MEM_P (operands[4])"
6546   [(set (match_dup 0)
6547         (if_then_else:GPR
6548          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6549          (match_dup 3)
6550          (match_dup 0)))
6551    (set (match_dup 0)
6552         (if_then_else:GPR
6553          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6554          (match_dup 0)
6555          (match_dup 4)))]
6556   ""
6557   [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*")
6558    (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")])
6559
6560 ;;
6561 ;;- Multiply instructions.
6562 ;;
6563
6564 ;
6565 ; muldi3 instruction pattern(s).
6566 ;
6567
6568 (define_insn "*muldi3_sign"
6569   [(set (match_operand:DI 0 "register_operand" "=d,d")
6570         (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
6571                  (match_operand:DI 1 "register_operand" "0,0")))]
6572   "TARGET_ZARCH"
6573   "@
6574    msgfr\t%0,%2
6575    msgf\t%0,%2"
6576   [(set_attr "op_type"      "RRE,RXY")
6577    (set_attr "type"         "imuldi")])
6578
6579 (define_insn "muldi3"
6580   [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6581         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6582                  (match_operand:DI 2 "general_operand" "d,K,T,Os")))]
6583   "TARGET_ZARCH"
6584   "@
6585    msgr\t%0,%2
6586    mghi\t%0,%h2
6587    msg\t%0,%2
6588    msgfi\t%0,%2"
6589   [(set_attr "op_type"      "RRE,RI,RXY,RIL")
6590    (set_attr "type"         "imuldi")
6591    (set_attr "cpu_facility" "*,*,*,z10")])
6592
6593 ;
6594 ; mulsi3 instruction pattern(s).
6595 ;
6596
6597 (define_insn "*mulsi3_sign"
6598   [(set (match_operand:SI 0 "register_operand" "=d,d")
6599         (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6600                  (match_operand:SI 1 "register_operand" "0,0")))]
6601   ""
6602   "@
6603    mh\t%0,%2
6604    mhy\t%0,%2"
6605   [(set_attr "op_type"      "RX,RXY")
6606    (set_attr "type"         "imulhi")
6607    (set_attr "cpu_facility" "*,z10")])
6608
6609 (define_insn "mulsi3"
6610   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6611         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6612                   (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6613   ""
6614   "@
6615    msr\t%0,%2
6616    mhi\t%0,%h2
6617    ms\t%0,%2
6618    msy\t%0,%2
6619    msfi\t%0,%2"
6620   [(set_attr "op_type"      "RRE,RI,RX,RXY,RIL")
6621    (set_attr "type"         "imulsi,imulhi,imulsi,imulsi,imulsi")
6622    (set_attr "cpu_facility" "*,*,*,longdisp,z10")])
6623
6624 ;
6625 ; mulsidi3 instruction pattern(s).
6626 ;
6627
6628 (define_insn "mulsidi3"
6629   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6630         (mult:DI (sign_extend:DI
6631                    (match_operand:SI 1 "register_operand" "%0,0,0"))
6632                  (sign_extend:DI
6633                    (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6634   "!TARGET_ZARCH"
6635   "@
6636    mr\t%0,%2
6637    m\t%0,%2
6638    mfy\t%0,%2"
6639   [(set_attr "op_type"      "RR,RX,RXY")
6640    (set_attr "type"         "imulsi")
6641    (set_attr "cpu_facility" "*,*,z10")])
6642
6643 ;
6644 ; umul instruction pattern(s).
6645 ;
6646
6647 ; mlr, ml, mlgr, mlg
6648 (define_insn "umul<dwh><mode>3"
6649   [(set (match_operand:DW 0 "register_operand"                   "=d,d")
6650         (mult:DW (zero_extend:DW
6651                    (match_operand:<DWH> 1 "register_operand"     "%0,0"))
6652                  (zero_extend:DW
6653                    (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
6654   "TARGET_CPU_ZARCH"
6655   "@
6656    ml<tg>r\t%0,%2
6657    ml<tg>\t%0,%2"
6658   [(set_attr "op_type"  "RRE,RXY")
6659    (set_attr "type"     "imul<dwh>")])
6660
6661 ;
6662 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6663 ;
6664
6665 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6666 (define_insn "mul<mode>3"
6667   [(set (match_operand:FP          0 "register_operand"     "=f,f,f,v")
6668         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
6669                  (match_operand:FP 2 "general_operand"       "f,f,R,v")))]
6670   "TARGET_HARD_FLOAT"
6671   "@
6672    m<xdee>tr\t%0,%1,%2
6673    m<xdee>br\t%0,%2
6674    m<xdee>b\t%0,%2
6675    wfmdb\t%v0,%v1,%v2"
6676   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6677    (set_attr "type"         "fmul<mode>")
6678    (set_attr "cpu_facility" "*,*,*,vx")
6679    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6680
6681 ; madbr, maebr, maxb, madb, maeb
6682 (define_insn "fma<mode>4"
6683   [(set (match_operand:DSF          0 "register_operand"     "=f,f,v")
6684         (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6685                  (match_operand:DSF 2 "nonimmediate_operand"  "f,R,v")
6686                  (match_operand:DSF 3 "register_operand"      "0,0,v")))]
6687   "TARGET_HARD_FLOAT"
6688   "@
6689    ma<xde>br\t%0,%1,%2
6690    ma<xde>b\t%0,%1,%2
6691    wfmadb\t%v0,%v1,%v2,%v3"
6692   [(set_attr "op_type"      "RRE,RXE,VRR")
6693    (set_attr "type"         "fmadd<mode>")
6694    (set_attr "cpu_facility" "*,*,vx")
6695    (set_attr "enabled"      "*,*,<DFDI>")])
6696
6697 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6698 (define_insn "fms<mode>4"
6699   [(set (match_operand:DSF                   0 "register_operand"     "=f,f,v")
6700         (fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,v")
6701                  (match_operand:DSF          2 "nonimmediate_operand"  "f,R,v")
6702                  (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,v"))))]
6703   "TARGET_HARD_FLOAT"
6704   "@
6705    ms<xde>br\t%0,%1,%2
6706    ms<xde>b\t%0,%1,%2
6707    wfmsdb\t%v0,%v1,%v2,%v3"
6708   [(set_attr "op_type"      "RRE,RXE,VRR")
6709    (set_attr "type"         "fmadd<mode>")
6710    (set_attr "cpu_facility" "*,*,vx")
6711    (set_attr "enabled"      "*,*,<DFDI>")])
6712
6713 ;;
6714 ;;- Divide and modulo instructions.
6715 ;;
6716
6717 ;
6718 ; divmoddi4 instruction pattern(s).
6719 ;
6720
6721 (define_expand "divmoddi4"
6722   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6723                    (div:DI (match_operand:DI 1 "register_operand" "")
6724                            (match_operand:DI 2 "general_operand" "")))
6725               (set (match_operand:DI 3 "general_operand" "")
6726                    (mod:DI (match_dup 1) (match_dup 2)))])
6727    (clobber (match_dup 4))]
6728   "TARGET_ZARCH"
6729 {
6730   rtx div_equal, mod_equal;
6731   rtx_insn *insn;
6732
6733   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6734   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6735
6736   operands[4] = gen_reg_rtx(TImode);
6737   emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6738
6739   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6740   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6741
6742   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6743   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6744
6745   DONE;
6746 })
6747
6748 (define_insn "divmodtidi3"
6749   [(set (match_operand:TI 0 "register_operand" "=d,d")
6750         (ior:TI
6751           (ashift:TI
6752             (zero_extend:TI
6753               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6754                       (match_operand:DI 2 "general_operand" "d,T")))
6755             (const_int 64))
6756           (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6757   "TARGET_ZARCH"
6758   "@
6759    dsgr\t%0,%2
6760    dsg\t%0,%2"
6761   [(set_attr "op_type"  "RRE,RXY")
6762    (set_attr "type"     "idiv")])
6763
6764 (define_insn "divmodtisi3"
6765   [(set (match_operand:TI 0 "register_operand" "=d,d")
6766         (ior:TI
6767           (ashift:TI
6768             (zero_extend:TI
6769               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6770                       (sign_extend:DI
6771                         (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
6772             (const_int 64))
6773           (zero_extend:TI
6774             (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6775   "TARGET_ZARCH"
6776   "@
6777    dsgfr\t%0,%2
6778    dsgf\t%0,%2"
6779   [(set_attr "op_type"  "RRE,RXY")
6780    (set_attr "type"     "idiv")])
6781
6782 ;
6783 ; udivmoddi4 instruction pattern(s).
6784 ;
6785
6786 (define_expand "udivmoddi4"
6787   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6788                    (udiv:DI (match_operand:DI 1 "general_operand" "")
6789                             (match_operand:DI 2 "nonimmediate_operand" "")))
6790               (set (match_operand:DI 3 "general_operand" "")
6791                    (umod:DI (match_dup 1) (match_dup 2)))])
6792    (clobber (match_dup 4))]
6793   "TARGET_ZARCH"
6794 {
6795   rtx div_equal, mod_equal, equal;
6796   rtx_insn *insn;
6797
6798   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6799   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6800   equal = gen_rtx_IOR (TImode,
6801                        gen_rtx_ASHIFT (TImode,
6802                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6803                                        GEN_INT (64)),
6804                        gen_rtx_ZERO_EXTEND (TImode, div_equal));
6805
6806   operands[4] = gen_reg_rtx(TImode);
6807   emit_clobber (operands[4]);
6808   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6809   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6810
6811   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6812   set_unique_reg_note (insn, REG_EQUAL, equal);
6813
6814   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6815   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6816
6817   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6818   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6819
6820   DONE;
6821 })
6822
6823 (define_insn "udivmodtidi3"
6824   [(set (match_operand:TI 0 "register_operand" "=d,d")
6825         (ior:TI
6826           (ashift:TI
6827             (zero_extend:TI
6828               (truncate:DI
6829                 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6830                          (zero_extend:TI
6831                            (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
6832             (const_int 64))
6833           (zero_extend:TI
6834             (truncate:DI
6835               (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6836   "TARGET_ZARCH"
6837   "@
6838    dlgr\t%0,%2
6839    dlg\t%0,%2"
6840   [(set_attr "op_type"  "RRE,RXY")
6841    (set_attr "type"     "idiv")])
6842
6843 ;
6844 ; divmodsi4 instruction pattern(s).
6845 ;
6846
6847 (define_expand "divmodsi4"
6848   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6849                    (div:SI (match_operand:SI 1 "general_operand" "")
6850                            (match_operand:SI 2 "nonimmediate_operand" "")))
6851               (set (match_operand:SI 3 "general_operand" "")
6852                    (mod:SI (match_dup 1) (match_dup 2)))])
6853    (clobber (match_dup 4))]
6854   "!TARGET_ZARCH"
6855 {
6856   rtx div_equal, mod_equal, equal;
6857   rtx_insn *insn;
6858
6859   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6860   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6861   equal = gen_rtx_IOR (DImode,
6862                        gen_rtx_ASHIFT (DImode,
6863                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6864                                        GEN_INT (32)),
6865                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6866
6867   operands[4] = gen_reg_rtx(DImode);
6868   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6869
6870   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6871   set_unique_reg_note (insn, REG_EQUAL, equal);
6872
6873   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6874   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6875
6876   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6877   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6878
6879   DONE;
6880 })
6881
6882 (define_insn "divmoddisi3"
6883   [(set (match_operand:DI 0 "register_operand" "=d,d")
6884         (ior:DI
6885           (ashift:DI
6886             (zero_extend:DI
6887               (truncate:SI
6888                 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6889                         (sign_extend:DI
6890                           (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6891             (const_int 32))
6892           (zero_extend:DI
6893             (truncate:SI
6894               (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6895   "!TARGET_ZARCH"
6896   "@
6897    dr\t%0,%2
6898    d\t%0,%2"
6899   [(set_attr "op_type"  "RR,RX")
6900    (set_attr "type"     "idiv")])
6901
6902 ;
6903 ; udivsi3 and umodsi3 instruction pattern(s).
6904 ;
6905
6906 (define_expand "udivmodsi4"
6907   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6908                    (udiv:SI (match_operand:SI 1 "general_operand" "")
6909                             (match_operand:SI 2 "nonimmediate_operand" "")))
6910               (set (match_operand:SI 3 "general_operand" "")
6911                    (umod:SI (match_dup 1) (match_dup 2)))])
6912    (clobber (match_dup 4))]
6913   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6914 {
6915   rtx div_equal, mod_equal, equal;
6916   rtx_insn *insn;
6917
6918   div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6919   mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6920   equal = gen_rtx_IOR (DImode,
6921                        gen_rtx_ASHIFT (DImode,
6922                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6923                                        GEN_INT (32)),
6924                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6925
6926   operands[4] = gen_reg_rtx(DImode);
6927   emit_clobber (operands[4]);
6928   emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6929   emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6930
6931   insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6932   set_unique_reg_note (insn, REG_EQUAL, equal);
6933
6934   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6935   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6936
6937   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6938   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6939
6940   DONE;
6941 })
6942
6943 (define_insn "udivmoddisi3"
6944   [(set (match_operand:DI 0 "register_operand" "=d,d")
6945         (ior:DI
6946           (ashift:DI
6947             (zero_extend:DI
6948               (truncate:SI
6949                 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6950                          (zero_extend:DI
6951                            (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
6952             (const_int 32))
6953           (zero_extend:DI
6954             (truncate:SI
6955               (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6956   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6957   "@
6958    dlr\t%0,%2
6959    dl\t%0,%2"
6960   [(set_attr "op_type"  "RRE,RXY")
6961    (set_attr "type"     "idiv")])
6962
6963 (define_expand "udivsi3"
6964   [(set (match_operand:SI 0 "register_operand" "=d")
6965         (udiv:SI (match_operand:SI 1 "general_operand" "")
6966                  (match_operand:SI 2 "general_operand" "")))
6967    (clobber (match_dup 3))]
6968   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6969 {
6970   rtx udiv_equal, umod_equal, equal;
6971   rtx_insn *insn;
6972
6973   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6974   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6975   equal = gen_rtx_IOR (DImode,
6976                        gen_rtx_ASHIFT (DImode,
6977                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6978                                        GEN_INT (32)),
6979                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6980
6981   operands[3] = gen_reg_rtx (DImode);
6982
6983   if (CONSTANT_P (operands[2]))
6984     {
6985       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6986         {
6987           rtx_code_label *label1 = gen_label_rtx ();
6988
6989           operands[1] = make_safe_from (operands[1], operands[0]);
6990           emit_move_insn (operands[0], const0_rtx);
6991           emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6992                                    SImode, 1, label1);
6993           emit_move_insn (operands[0], const1_rtx);
6994           emit_label (label1);
6995         }
6996       else
6997         {
6998           operands[2] = force_reg (SImode, operands[2]);
6999           operands[2] = make_safe_from (operands[2], operands[0]);
7000
7001           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7002           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7003                                              operands[2]));
7004           set_unique_reg_note (insn, REG_EQUAL, equal);
7005
7006           insn = emit_move_insn (operands[0],
7007                                  gen_lowpart (SImode, operands[3]));
7008           set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
7009         }
7010     }
7011   else
7012     {
7013       rtx_code_label *label1 = gen_label_rtx ();
7014       rtx_code_label *label2 = gen_label_rtx ();
7015       rtx_code_label *label3 = gen_label_rtx ();
7016
7017       operands[1] = force_reg (SImode, operands[1]);
7018       operands[1] = make_safe_from (operands[1], operands[0]);
7019       operands[2] = force_reg (SImode, operands[2]);
7020       operands[2] = make_safe_from (operands[2], operands[0]);
7021
7022       emit_move_insn (operands[0], const0_rtx);
7023       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
7024                                SImode, 1, label3);
7025       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
7026                                SImode, 0, label2);
7027       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
7028                                SImode, 0, label1);
7029       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7030       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7031                                          operands[2]));
7032       set_unique_reg_note (insn, REG_EQUAL, equal);
7033
7034       insn = emit_move_insn (operands[0],
7035                              gen_lowpart (SImode, operands[3]));
7036       set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
7037
7038       emit_jump (label3);
7039       emit_label (label1);
7040       emit_move_insn (operands[0], operands[1]);
7041       emit_jump (label3);
7042       emit_label (label2);
7043       emit_move_insn (operands[0], const1_rtx);
7044       emit_label (label3);
7045     }
7046   emit_move_insn (operands[0], operands[0]);
7047   DONE;
7048 })
7049
7050 (define_expand "umodsi3"
7051   [(set (match_operand:SI 0 "register_operand" "=d")
7052         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
7053                  (match_operand:SI 2 "nonimmediate_operand" "")))
7054    (clobber (match_dup 3))]
7055   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
7056 {
7057   rtx udiv_equal, umod_equal, equal;
7058   rtx_insn *insn;
7059
7060   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
7061   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
7062   equal = gen_rtx_IOR (DImode,
7063                        gen_rtx_ASHIFT (DImode,
7064                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
7065                                        GEN_INT (32)),
7066                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
7067
7068   operands[3] = gen_reg_rtx (DImode);
7069
7070   if (CONSTANT_P (operands[2]))
7071     {
7072       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
7073         {
7074           rtx_code_label *label1 = gen_label_rtx ();
7075
7076           operands[1] = make_safe_from (operands[1], operands[0]);
7077           emit_move_insn (operands[0], operands[1]);
7078           emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
7079                                    SImode, 1, label1);
7080           emit_insn (gen_abssi2 (operands[0], operands[2]));
7081           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
7082           emit_label (label1);
7083         }
7084       else
7085         {
7086           operands[2] = force_reg (SImode, operands[2]);
7087           operands[2] = make_safe_from (operands[2], operands[0]);
7088
7089           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7090           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7091                                              operands[2]));
7092           set_unique_reg_note (insn, REG_EQUAL, equal);
7093
7094           insn = emit_move_insn (operands[0],
7095                                  gen_highpart (SImode, operands[3]));
7096           set_unique_reg_note (insn, REG_EQUAL, umod_equal);
7097         }
7098     }
7099   else
7100     {
7101       rtx_code_label *label1 = gen_label_rtx ();
7102       rtx_code_label *label2 = gen_label_rtx ();
7103       rtx_code_label *label3 = gen_label_rtx ();
7104
7105       operands[1] = force_reg (SImode, operands[1]);
7106       operands[1] = make_safe_from (operands[1], operands[0]);
7107       operands[2] = force_reg (SImode, operands[2]);
7108       operands[2] = make_safe_from (operands[2], operands[0]);
7109
7110       emit_move_insn(operands[0], operands[1]);
7111       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
7112                                SImode, 1, label3);
7113       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
7114                                SImode, 0, label2);
7115       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
7116                                SImode, 0, label1);
7117       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7118       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7119                                          operands[2]));
7120       set_unique_reg_note (insn, REG_EQUAL, equal);
7121
7122       insn = emit_move_insn (operands[0],
7123                              gen_highpart (SImode, operands[3]));
7124       set_unique_reg_note (insn, REG_EQUAL, umod_equal);
7125
7126       emit_jump (label3);
7127       emit_label (label1);
7128       emit_move_insn (operands[0], const0_rtx);
7129       emit_jump (label3);
7130       emit_label (label2);
7131       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
7132       emit_label (label3);
7133     }
7134   DONE;
7135 })
7136
7137 ;
7138 ; div(df|sf)3 instruction pattern(s).
7139 ;
7140
7141 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
7142 (define_insn "div<mode>3"
7143   [(set (match_operand:FP         0 "register_operand" "=f,f,f,v")
7144         (div:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
7145                 (match_operand:FP 2 "general_operand"   "f,f,R,v")))]
7146   "TARGET_HARD_FLOAT"
7147   "@
7148    d<xde>tr\t%0,%1,%2
7149    d<xde>br\t%0,%2
7150    d<xde>b\t%0,%2
7151    wfddb\t%v0,%v1,%v2"
7152   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
7153    (set_attr "type"         "fdiv<mode>")
7154    (set_attr "cpu_facility" "*,*,*,vx")
7155    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
7156
7157
7158 ;;
7159 ;;- And instructions.
7160 ;;
7161
7162 (define_expand "and<mode>3"
7163   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7164         (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
7165                  (match_operand:INT 2 "general_operand" "")))
7166    (clobber (reg:CC CC_REGNUM))]
7167   ""
7168   "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
7169
7170 ;
7171 ; anddi3 instruction pattern(s).
7172 ;
7173
7174 (define_insn "*anddi3_cc"
7175   [(set (reg CC_REGNUM)
7176         (compare
7177           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,    d")
7178                   (match_operand:DI 2 "general_operand"      " d,d,T,NxxDw"))
7179           (const_int 0)))
7180    (set (match_operand:DI 0 "register_operand"               "=d,d,d,    d")
7181         (and:DI (match_dup 1) (match_dup 2)))]
7182   "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
7183   "@
7184    ngr\t%0,%2
7185    ngrk\t%0,%1,%2
7186    ng\t%0,%2
7187    risbg\t%0,%1,%s2,128+%e2,0"
7188   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
7189    (set_attr "cpu_facility" "*,z196,*,z10")
7190    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7191
7192 (define_insn "*anddi3_cconly"
7193   [(set (reg CC_REGNUM)
7194         (compare
7195           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,    d")
7196                   (match_operand:DI 2 "general_operand"      " d,d,T,NxxDw"))
7197                  (const_int 0)))
7198    (clobber (match_scratch:DI 0                              "=d,d,d,    d"))]
7199   "TARGET_ZARCH
7200    && s390_match_ccmode(insn, CCTmode)
7201    /* Do not steal TM patterns.  */
7202    && s390_single_part (operands[2], DImode, HImode, 0) < 0"
7203   "@
7204    ngr\t%0,%2
7205    ngrk\t%0,%1,%2
7206    ng\t%0,%2
7207    risbg\t%0,%1,%s2,128+%e2,0"
7208   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
7209    (set_attr "cpu_facility" "*,z196,*,z10")
7210    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7211
7212 (define_insn "*anddi3"
7213   [(set (match_operand:DI 0 "nonimmediate_operand"
7214             "=d,d,    d,    d,    d,    d,    d,    d,d,d,d,    d,   AQ,Q")
7215         (and:DI
7216           (match_operand:DI 1 "nonimmediate_operand"
7217             "%d,o,    0,    0,    0,    0,    0,    0,0,d,0,    d,    0,0")
7218           (match_operand:DI 2 "general_operand"
7219             "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q")))
7220    (clobber (reg:CC CC_REGNUM))]
7221   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7222   "@
7223    #
7224    #
7225    nihh\t%0,%j2
7226    nihl\t%0,%j2
7227    nilh\t%0,%j2
7228    nill\t%0,%j2
7229    nihf\t%0,%m2
7230    nilf\t%0,%m2
7231    ngr\t%0,%2
7232    ngrk\t%0,%1,%2
7233    ng\t%0,%2
7234    risbg\t%0,%1,%s2,128+%e2,0
7235    #
7236    #"
7237   [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
7238    (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
7239    (set_attr "z10prop" "*,
7240                         *,
7241                         z10_super_E1,
7242                         z10_super_E1,
7243                         z10_super_E1,
7244                         z10_super_E1,
7245                         z10_super_E1,
7246                         z10_super_E1,
7247                         z10_super_E1,
7248                         *,
7249                         z10_super_E1,
7250                         z10_super_E1,
7251                         *,
7252                         *")])
7253
7254 (define_split
7255   [(set (match_operand:DI 0 "s_operand" "")
7256         (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7257    (clobber (reg:CC CC_REGNUM))]
7258   "reload_completed"
7259   [(parallel
7260     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7261      (clobber (reg:CC CC_REGNUM))])]
7262   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7263
7264 ;; These two are what combine generates for (ashift (zero_extract)).
7265 (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>"
7266   [(set (match_operand:GPR 0 "register_operand" "=d")
7267         (and:GPR (lshiftrt:GPR
7268                    (match_operand:GPR 1 "register_operand" "d")
7269                    (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7270                 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
7271   "<z10_or_zEC12_cond>
7272    /* Note that even for the SImode pattern, the rotate is always DImode.  */
7273    && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
7274                            INTVAL (operands[3]))"
7275   "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
7276   [(set_attr "op_type" "RIE")
7277    (set_attr "z10prop" "z10_super_E1")])
7278
7279 (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>"
7280   [(set (match_operand:GPR 0 "register_operand" "=d")
7281         (and:GPR (ashift:GPR
7282                   (match_operand:GPR 1 "register_operand" "d")
7283                   (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7284                 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
7285   "<z10_or_zEC12_cond>
7286    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
7287                            INTVAL (operands[3]))"
7288   "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
7289   [(set_attr "op_type" "RIE")
7290    (set_attr "z10prop" "z10_super_E1")])
7291
7292
7293 ;
7294 ; andsi3 instruction pattern(s).
7295 ;
7296
7297 (define_insn "*andsi3_cc"
7298   [(set (reg CC_REGNUM)
7299         (compare
7300           (and:SI
7301             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
7302             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
7303           (const_int 0)))
7304    (set (match_operand:SI 0 "register_operand"         "=d,d,d,d,d,    d")
7305         (and:SI (match_dup 1) (match_dup 2)))]
7306   "s390_match_ccmode(insn, CCTmode)"
7307   "@
7308    nilf\t%0,%o2
7309    nr\t%0,%2
7310    nrk\t%0,%1,%2
7311    n\t%0,%2
7312    ny\t%0,%2
7313    risbg\t%0,%1,%t2,128+%f2,0"
7314   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
7315    (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7316    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7317                         z10_super_E1,z10_super_E1,z10_super_E1")])
7318
7319 (define_insn "*andsi3_cconly"
7320   [(set (reg CC_REGNUM)
7321         (compare
7322           (and:SI
7323             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
7324             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
7325           (const_int 0)))
7326    (clobber (match_scratch:SI 0                        "=d,d,d,d,d,    d"))]
7327   "s390_match_ccmode(insn, CCTmode)
7328    /* Do not steal TM patterns.  */
7329    && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7330   "@
7331    nilf\t%0,%o2
7332    nr\t%0,%2
7333    nrk\t%0,%1,%2
7334    n\t%0,%2
7335    ny\t%0,%2
7336    risbg\t%0,%1,%t2,128+%f2,0"
7337   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
7338    (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7339    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7340                         z10_super_E1,z10_super_E1,z10_super_E1")])
7341
7342 (define_insn "*andsi3_zarch"
7343   [(set (match_operand:SI 0 "nonimmediate_operand"
7344                             "=d,d,    d,    d, d,d,d,d,d,    d,   AQ,Q")
7345         (and:SI (match_operand:SI 1 "nonimmediate_operand"
7346                             "%d,o,    0,    0, 0,0,d,0,0,    d,    0,0")
7347                 (match_operand:SI 2 "general_operand"
7348                             " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q")))
7349    (clobber (reg:CC CC_REGNUM))]
7350   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7351   "@
7352    #
7353    #
7354    nilh\t%0,%j2
7355    nill\t%0,%j2
7356    nilf\t%0,%o2
7357    nr\t%0,%2
7358    nrk\t%0,%1,%2
7359    n\t%0,%2
7360    ny\t%0,%2
7361    risbg\t%0,%1,%t2,128+%f2,0
7362    #
7363    #"
7364   [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7365    (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
7366    (set_attr "z10prop" "*,
7367                         *,
7368                         z10_super_E1,
7369                         z10_super_E1,
7370                         z10_super_E1,
7371                         z10_super_E1,
7372                         *,
7373                         z10_super_E1,
7374                         z10_super_E1,
7375                         z10_super_E1,
7376                         *,
7377                         *")])
7378
7379 (define_insn "*andsi3_esa"
7380   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,   AQ,Q")
7381         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,    0,0")
7382                 (match_operand:SI 2 "general_operand"      " d,R,NxQSF,Q")))
7383    (clobber (reg:CC CC_REGNUM))]
7384   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7385   "@
7386    nr\t%0,%2
7387    n\t%0,%2
7388    #
7389    #"
7390   [(set_attr "op_type"  "RR,RX,SI,SS")
7391    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7392
7393
7394 (define_split
7395   [(set (match_operand:SI 0 "s_operand" "")
7396         (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7397    (clobber (reg:CC CC_REGNUM))]
7398   "reload_completed"
7399   [(parallel
7400     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7401      (clobber (reg:CC CC_REGNUM))])]
7402   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7403
7404 ;
7405 ; andhi3 instruction pattern(s).
7406 ;
7407
7408 (define_insn "*andhi3_zarch"
7409   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7410         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7411                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQHF,Q")))
7412    (clobber (reg:CC CC_REGNUM))]
7413   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7414   "@
7415    nr\t%0,%2
7416    nrk\t%0,%1,%2
7417    nill\t%0,%x2
7418    #
7419    #"
7420   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7421    (set_attr "cpu_facility" "*,z196,*,*,*")
7422    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7423 ])
7424
7425 (define_insn "*andhi3_esa"
7426   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7427         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7428                 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7429    (clobber (reg:CC CC_REGNUM))]
7430   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7431   "@
7432    nr\t%0,%2
7433    #
7434    #"
7435   [(set_attr "op_type"  "RR,SI,SS")
7436    (set_attr "z10prop" "z10_super_E1,*,*")
7437 ])
7438
7439 (define_split
7440   [(set (match_operand:HI 0 "s_operand" "")
7441         (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7442    (clobber (reg:CC CC_REGNUM))]
7443   "reload_completed"
7444   [(parallel
7445     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7446      (clobber (reg:CC CC_REGNUM))])]
7447   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7448
7449 ;
7450 ; andqi3 instruction pattern(s).
7451 ;
7452
7453 (define_insn "*andqi3_zarch"
7454   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7455         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7456                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7457    (clobber (reg:CC CC_REGNUM))]
7458   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7459   "@
7460    nr\t%0,%2
7461    nrk\t%0,%1,%2
7462    nill\t%0,%b2
7463    ni\t%S0,%b2
7464    niy\t%S0,%b2
7465    #"
7466   [(set_attr "op_type"  "RR,RRF,RI,SI,SIY,SS")
7467    (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7468    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7469
7470 (define_insn "*andqi3_esa"
7471   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7472         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7473                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7474    (clobber (reg:CC CC_REGNUM))]
7475   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7476   "@
7477    nr\t%0,%2
7478    ni\t%S0,%b2
7479    #"
7480   [(set_attr "op_type"  "RR,SI,SS")
7481    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7482
7483 ;
7484 ; And with complement
7485 ;
7486 ; c = ~b & a = (b & a) ^ a
7487
7488 (define_insn_and_split "*andc_split_<mode>"
7489   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
7490         (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
7491                  (match_operand:GPR 2 "general_operand" "")))
7492    (clobber (reg:CC CC_REGNUM))]
7493   "! reload_completed
7494    && (GET_CODE (operands[0]) != MEM
7495       /* Ensure that s390_logical_operator_ok_p will succeed even
7496          on the split xor if (b & a) is stored into a pseudo.  */
7497        || rtx_equal_p (operands[0], operands[2]))"
7498   "#"
7499   "&& 1"
7500   [
7501   (parallel
7502    [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2)))
7503    (clobber (reg:CC CC_REGNUM))])
7504   (parallel
7505    [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2)))
7506    (clobber (reg:CC CC_REGNUM))])]
7507 {
7508   if (reg_overlap_mentioned_p (operands[0], operands[2]))
7509     operands[3] = gen_reg_rtx (<MODE>mode);
7510   else
7511     operands[3] = operands[0];
7512 })
7513
7514 ;
7515 ; Block and (NC) patterns.
7516 ;
7517
7518 (define_insn "*nc"
7519   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7520         (and:BLK (match_dup 0)
7521                  (match_operand:BLK 1 "memory_operand" "Q")))
7522    (use (match_operand 2 "const_int_operand" "n"))
7523    (clobber (reg:CC CC_REGNUM))]
7524   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7525   "nc\t%O0(%2,%R0),%S1"
7526   [(set_attr "op_type" "SS")
7527    (set_attr "z196prop" "z196_cracked")])
7528
7529 (define_split
7530   [(set (match_operand 0 "memory_operand" "")
7531         (and (match_dup 0)
7532              (match_operand 1 "memory_operand" "")))
7533    (clobber (reg:CC CC_REGNUM))]
7534   "reload_completed
7535    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7536    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7537   [(parallel
7538     [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7539      (use (match_dup 2))
7540      (clobber (reg:CC CC_REGNUM))])]
7541 {
7542   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7543   operands[0] = adjust_address (operands[0], BLKmode, 0);
7544   operands[1] = adjust_address (operands[1], BLKmode, 0);
7545 })
7546
7547 (define_peephole2
7548   [(parallel
7549     [(set (match_operand:BLK 0 "memory_operand" "")
7550           (and:BLK (match_dup 0)
7551                    (match_operand:BLK 1 "memory_operand" "")))
7552      (use (match_operand 2 "const_int_operand" ""))
7553      (clobber (reg:CC CC_REGNUM))])
7554    (parallel
7555     [(set (match_operand:BLK 3 "memory_operand" "")
7556           (and:BLK (match_dup 3)
7557                    (match_operand:BLK 4 "memory_operand" "")))
7558      (use (match_operand 5 "const_int_operand" ""))
7559      (clobber (reg:CC CC_REGNUM))])]
7560   "s390_offset_p (operands[0], operands[3], operands[2])
7561    && s390_offset_p (operands[1], operands[4], operands[2])
7562    && !s390_overlap_p (operands[0], operands[1],
7563                        INTVAL (operands[2]) + INTVAL (operands[5]))
7564    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7565   [(parallel
7566     [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7567      (use (match_dup 8))
7568      (clobber (reg:CC CC_REGNUM))])]
7569   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7570    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7571    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7572
7573
7574 ;;
7575 ;;- Bit set (inclusive or) instructions.
7576 ;;
7577
7578 (define_expand "ior<mode>3"
7579   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7580         (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7581                  (match_operand:INT 2 "general_operand" "")))
7582    (clobber (reg:CC CC_REGNUM))]
7583   ""
7584   "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7585
7586 ;
7587 ; iordi3 instruction pattern(s).
7588 ;
7589
7590 (define_insn "*iordi3_cc"
7591   [(set (reg CC_REGNUM)
7592         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7593                          (match_operand:DI 2 "general_operand"      " d,d,T"))
7594                  (const_int 0)))
7595    (set (match_operand:DI 0 "register_operand"                      "=d,d,d")
7596         (ior:DI (match_dup 1) (match_dup 2)))]
7597   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7598   "@
7599    ogr\t%0,%2
7600    ogrk\t%0,%1,%2
7601    og\t%0,%2"
7602   [(set_attr "op_type"  "RRE,RRF,RXY")
7603    (set_attr "cpu_facility" "*,z196,*")
7604    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7605
7606 (define_insn "*iordi3_cconly"
7607   [(set (reg CC_REGNUM)
7608         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7609                          (match_operand:DI 2 "general_operand"      " d,d,T"))
7610                  (const_int 0)))
7611    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7612   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7613   "@
7614    ogr\t%0,%2
7615    ogrk\t%0,%1,%2
7616    og\t%0,%2"
7617   [(set_attr "op_type"  "RRE,RRF,RXY")
7618    (set_attr "cpu_facility" "*,z196,*")
7619    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7620
7621 (define_insn "*iordi3"
7622   [(set (match_operand:DI 0 "nonimmediate_operand"
7623                                "=d,    d,    d,    d,    d,    d,d,d,d,   AQ,Q")
7624         (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7625                             "   %0,    0,    0,    0,    0,    0,0,d,0,    0,0")
7626                 (match_operand:DI 2 "general_operand"
7627                             "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7628    (clobber (reg:CC CC_REGNUM))]
7629   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7630   "@
7631    oihh\t%0,%i2
7632    oihl\t%0,%i2
7633    oilh\t%0,%i2
7634    oill\t%0,%i2
7635    oihf\t%0,%k2
7636    oilf\t%0,%k2
7637    ogr\t%0,%2
7638    ogrk\t%0,%1,%2
7639    og\t%0,%2
7640    #
7641    #"
7642   [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7643    (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7644    (set_attr "z10prop" "z10_super_E1,
7645                         z10_super_E1,
7646                         z10_super_E1,
7647                         z10_super_E1,
7648                         z10_super_E1,
7649                         z10_super_E1,
7650                         z10_super_E1,
7651                         *,
7652                         z10_super_E1,
7653                         *,
7654                         *")])
7655
7656 (define_split
7657   [(set (match_operand:DI 0 "s_operand" "")
7658         (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7659    (clobber (reg:CC CC_REGNUM))]
7660   "reload_completed"
7661   [(parallel
7662     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7663      (clobber (reg:CC CC_REGNUM))])]
7664   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7665
7666 ;
7667 ; iorsi3 instruction pattern(s).
7668 ;
7669
7670 (define_insn "*iorsi3_cc"
7671   [(set (reg CC_REGNUM)
7672         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7673                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7674                  (const_int 0)))
7675    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7676         (ior:SI (match_dup 1) (match_dup 2)))]
7677   "s390_match_ccmode(insn, CCTmode)"
7678   "@
7679    oilf\t%0,%o2
7680    or\t%0,%2
7681    ork\t%0,%1,%2
7682    o\t%0,%2
7683    oy\t%0,%2"
7684   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7685    (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7686    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7687
7688 (define_insn "*iorsi3_cconly"
7689   [(set (reg CC_REGNUM)
7690         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7691                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7692                  (const_int 0)))
7693    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7694   "s390_match_ccmode(insn, CCTmode)"
7695   "@
7696    oilf\t%0,%o2
7697    or\t%0,%2
7698    ork\t%0,%1,%2
7699    o\t%0,%2
7700    oy\t%0,%2"
7701   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7702    (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7703    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7704
7705 (define_insn "*iorsi3_zarch"
7706   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,    d, d,d,d,d,d,   AQ,Q")
7707         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,    0, 0,0,d,0,0,    0,0")
7708                 (match_operand:SI 2 "general_operand"   "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7709    (clobber (reg:CC CC_REGNUM))]
7710   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7711   "@
7712    oilh\t%0,%i2
7713    oill\t%0,%i2
7714    oilf\t%0,%o2
7715    or\t%0,%2
7716    ork\t%0,%1,%2
7717    o\t%0,%2
7718    oy\t%0,%2
7719    #
7720    #"
7721   [(set_attr "op_type"  "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7722    (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
7723    (set_attr "z10prop" "z10_super_E1,
7724                         z10_super_E1,
7725                         z10_super_E1,
7726                         z10_super_E1,
7727                         *,
7728                         z10_super_E1,
7729                         z10_super_E1,
7730                         *,
7731                         *")])
7732
7733 (define_insn "*iorsi3_esa"
7734   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7735         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7736                 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7737    (clobber (reg:CC CC_REGNUM))]
7738   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7739   "@
7740    or\t%0,%2
7741    o\t%0,%2
7742    #
7743    #"
7744   [(set_attr "op_type"  "RR,RX,SI,SS")
7745    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7746
7747 (define_split
7748   [(set (match_operand:SI 0 "s_operand" "")
7749         (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7750    (clobber (reg:CC CC_REGNUM))]
7751   "reload_completed"
7752   [(parallel
7753     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7754      (clobber (reg:CC CC_REGNUM))])]
7755   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7756
7757 ;
7758 ; iorhi3 instruction pattern(s).
7759 ;
7760
7761 (define_insn "*iorhi3_zarch"
7762   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7763         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7764                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQH0,Q")))
7765    (clobber (reg:CC CC_REGNUM))]
7766   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7767   "@
7768    or\t%0,%2
7769    ork\t%0,%1,%2
7770    oill\t%0,%x2
7771    #
7772    #"
7773   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7774    (set_attr "cpu_facility" "*,z196,*,*,*")
7775    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7776
7777 (define_insn "*iorhi3_esa"
7778   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7779         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7780                 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7781    (clobber (reg:CC CC_REGNUM))]
7782   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7783   "@
7784    or\t%0,%2
7785    #
7786    #"
7787   [(set_attr "op_type"  "RR,SI,SS")
7788    (set_attr "z10prop" "z10_super_E1,*,*")])
7789
7790 (define_split
7791   [(set (match_operand:HI 0 "s_operand" "")
7792         (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7793    (clobber (reg:CC CC_REGNUM))]
7794   "reload_completed"
7795   [(parallel
7796     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7797      (clobber (reg:CC CC_REGNUM))])]
7798   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7799
7800 ;
7801 ; iorqi3 instruction pattern(s).
7802 ;
7803
7804 (define_insn "*iorqi3_zarch"
7805   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7806         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7807                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7808    (clobber (reg:CC CC_REGNUM))]
7809   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7810   "@
7811    or\t%0,%2
7812    ork\t%0,%1,%2
7813    oill\t%0,%b2
7814    oi\t%S0,%b2
7815    oiy\t%S0,%b2
7816    #"
7817   [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7818    (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7819    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7820                         z10_super,z10_super,*")])
7821
7822 (define_insn "*iorqi3_esa"
7823   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7824         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7825                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7826    (clobber (reg:CC CC_REGNUM))]
7827   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7828   "@
7829    or\t%0,%2
7830    oi\t%S0,%b2
7831    #"
7832   [(set_attr "op_type"  "RR,SI,SS")
7833    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7834
7835 ;
7836 ; Block inclusive or (OC) patterns.
7837 ;
7838
7839 (define_insn "*oc"
7840   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7841         (ior:BLK (match_dup 0)
7842                  (match_operand:BLK 1 "memory_operand" "Q")))
7843    (use (match_operand 2 "const_int_operand" "n"))
7844    (clobber (reg:CC CC_REGNUM))]
7845   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7846   "oc\t%O0(%2,%R0),%S1"
7847   [(set_attr "op_type" "SS")
7848    (set_attr "z196prop" "z196_cracked")])
7849
7850 (define_split
7851   [(set (match_operand 0 "memory_operand" "")
7852         (ior (match_dup 0)
7853              (match_operand 1 "memory_operand" "")))
7854    (clobber (reg:CC CC_REGNUM))]
7855   "reload_completed
7856    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7857    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7858   [(parallel
7859     [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7860      (use (match_dup 2))
7861      (clobber (reg:CC CC_REGNUM))])]
7862 {
7863   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7864   operands[0] = adjust_address (operands[0], BLKmode, 0);
7865   operands[1] = adjust_address (operands[1], BLKmode, 0);
7866 })
7867
7868 (define_peephole2
7869   [(parallel
7870     [(set (match_operand:BLK 0 "memory_operand" "")
7871           (ior:BLK (match_dup 0)
7872                    (match_operand:BLK 1 "memory_operand" "")))
7873      (use (match_operand 2 "const_int_operand" ""))
7874      (clobber (reg:CC CC_REGNUM))])
7875    (parallel
7876     [(set (match_operand:BLK 3 "memory_operand" "")
7877           (ior:BLK (match_dup 3)
7878                    (match_operand:BLK 4 "memory_operand" "")))
7879      (use (match_operand 5 "const_int_operand" ""))
7880      (clobber (reg:CC CC_REGNUM))])]
7881   "s390_offset_p (operands[0], operands[3], operands[2])
7882    && s390_offset_p (operands[1], operands[4], operands[2])
7883    && !s390_overlap_p (operands[0], operands[1],
7884                        INTVAL (operands[2]) + INTVAL (operands[5]))
7885    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7886   [(parallel
7887     [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7888      (use (match_dup 8))
7889      (clobber (reg:CC CC_REGNUM))])]
7890   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7891    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7892    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7893
7894
7895 ;;
7896 ;;- Xor instructions.
7897 ;;
7898
7899 (define_expand "xor<mode>3"
7900   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7901         (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7902                  (match_operand:INT 2 "general_operand" "")))
7903    (clobber (reg:CC CC_REGNUM))]
7904   ""
7905   "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7906
7907 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7908 ; simplifications.  So its better to have something matching.
7909 (define_split
7910   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7911         (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7912   ""
7913   [(parallel
7914     [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7915      (clobber (reg:CC CC_REGNUM))])]
7916 {
7917   operands[2] = constm1_rtx;
7918   if (!s390_logical_operator_ok_p (operands))
7919     FAIL;
7920 })
7921
7922 ;
7923 ; xordi3 instruction pattern(s).
7924 ;
7925
7926 (define_insn "*xordi3_cc"
7927   [(set (reg CC_REGNUM)
7928         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7929                          (match_operand:DI 2 "general_operand"      " d,d,T"))
7930                  (const_int 0)))
7931    (set (match_operand:DI 0 "register_operand"                      "=d,d,d")
7932         (xor:DI (match_dup 1) (match_dup 2)))]
7933   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7934   "@
7935    xgr\t%0,%2
7936    xgrk\t%0,%1,%2
7937    xg\t%0,%2"
7938   [(set_attr "op_type" "RRE,RRF,RXY")
7939    (set_attr "cpu_facility" "*,z196,*")
7940    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7941
7942 (define_insn "*xordi3_cconly"
7943   [(set (reg CC_REGNUM)
7944         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7945                          (match_operand:DI 2 "general_operand"      " d,d,T"))
7946                  (const_int 0)))
7947    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7948   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7949   "@
7950    xgr\t%0,%2
7951    xgrk\t%0,%1,%2
7952    xg\t%0,%2"
7953   [(set_attr "op_type" "RRE,RRF,RXY")
7954    (set_attr "cpu_facility" "*,z196,*")
7955    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7956
7957 (define_insn "*xordi3"
7958   [(set (match_operand:DI 0 "nonimmediate_operand"         "=d,    d,d,d,d,   AQ,Q")
7959         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,    0,0,d,0,    0,0")
7960                 (match_operand:DI 2 "general_operand"   "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7961    (clobber (reg:CC CC_REGNUM))]
7962   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7963   "@
7964    xihf\t%0,%k2
7965    xilf\t%0,%k2
7966    xgr\t%0,%2
7967    xgrk\t%0,%1,%2
7968    xg\t%0,%2
7969    #
7970    #"
7971   [(set_attr "op_type"  "RIL,RIL,RRE,RRF,RXY,SI,SS")
7972    (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7973    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7974                         *,z10_super_E1,*,*")])
7975
7976 (define_split
7977   [(set (match_operand:DI 0 "s_operand" "")
7978         (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7979    (clobber (reg:CC CC_REGNUM))]
7980   "reload_completed"
7981   [(parallel
7982     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7983      (clobber (reg:CC CC_REGNUM))])]
7984   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7985
7986 ;
7987 ; xorsi3 instruction pattern(s).
7988 ;
7989
7990 (define_insn "*xorsi3_cc"
7991   [(set (reg CC_REGNUM)
7992         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7993                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7994                  (const_int 0)))
7995    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7996         (xor:SI (match_dup 1) (match_dup 2)))]
7997   "s390_match_ccmode(insn, CCTmode)"
7998   "@
7999    xilf\t%0,%o2
8000    xr\t%0,%2
8001    xrk\t%0,%1,%2
8002    x\t%0,%2
8003    xy\t%0,%2"
8004   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
8005    (set_attr "cpu_facility" "*,*,z196,*,longdisp")
8006    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
8007                         z10_super_E1,z10_super_E1")])
8008
8009 (define_insn "*xorsi3_cconly"
8010   [(set (reg CC_REGNUM)
8011         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
8012                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
8013                  (const_int 0)))
8014    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
8015   "s390_match_ccmode(insn, CCTmode)"
8016   "@
8017    xilf\t%0,%o2
8018    xr\t%0,%2
8019    xrk\t%0,%1,%2
8020    x\t%0,%2
8021    xy\t%0,%2"
8022   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
8023    (set_attr "cpu_facility" "*,*,z196,*,longdisp")
8024    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
8025                         z10_super_E1,z10_super_E1")])
8026
8027 (define_insn "*xorsi3"
8028   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,d,d,d,   AQ,Q")
8029         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    0,0")
8030                 (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxQS0,Q")))
8031    (clobber (reg:CC CC_REGNUM))]
8032   "s390_logical_operator_ok_p (operands)"
8033   "@
8034    xilf\t%0,%o2
8035    xr\t%0,%2
8036    xrk\t%0,%1,%2
8037    x\t%0,%2
8038    xy\t%0,%2
8039    #
8040    #"
8041   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,SI,SS")
8042    (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
8043    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
8044                         z10_super_E1,z10_super_E1,*,*")])
8045
8046 (define_split
8047   [(set (match_operand:SI 0 "s_operand" "")
8048         (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
8049    (clobber (reg:CC CC_REGNUM))]
8050   "reload_completed"
8051   [(parallel
8052     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
8053      (clobber (reg:CC CC_REGNUM))])]
8054   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
8055
8056 ;
8057 ; xorhi3 instruction pattern(s).
8058 ;
8059
8060 (define_insn "*xorhi3"
8061   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
8062         (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d,    0,0")
8063                 (match_operand:HI 2 "general_operand"      "Os,d,d,NxQH0,Q")))
8064    (clobber (reg:CC CC_REGNUM))]
8065   "s390_logical_operator_ok_p (operands)"
8066   "@
8067    xilf\t%0,%x2
8068    xr\t%0,%2
8069    xrk\t%0,%1,%2
8070    #
8071    #"
8072   [(set_attr "op_type"  "RIL,RR,RRF,SI,SS")
8073    (set_attr "cpu_facility" "*,*,z196,*,*")
8074    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
8075
8076 (define_split
8077   [(set (match_operand:HI 0 "s_operand" "")
8078         (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
8079    (clobber (reg:CC CC_REGNUM))]
8080   "reload_completed"
8081   [(parallel
8082     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
8083      (clobber (reg:CC CC_REGNUM))])]
8084   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
8085
8086 ;
8087 ; xorqi3 instruction pattern(s).
8088 ;
8089
8090 (define_insn "*xorqi3"
8091   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
8092         (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
8093                 (match_operand:QI 2 "general_operand"      "Os,d,d,n,n,Q")))
8094    (clobber (reg:CC CC_REGNUM))]
8095   "s390_logical_operator_ok_p (operands)"
8096   "@
8097    xilf\t%0,%b2
8098    xr\t%0,%2
8099    xrk\t%0,%1,%2
8100    xi\t%S0,%b2
8101    xiy\t%S0,%b2
8102    #"
8103   [(set_attr "op_type"  "RIL,RR,RRF,SI,SIY,SS")
8104    (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
8105    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
8106
8107
8108 ;
8109 ; Block exclusive or (XC) patterns.
8110 ;
8111
8112 (define_insn "*xc"
8113   [(set (match_operand:BLK 0 "memory_operand" "=Q")
8114         (xor:BLK (match_dup 0)
8115                  (match_operand:BLK 1 "memory_operand" "Q")))
8116    (use (match_operand 2 "const_int_operand" "n"))
8117    (clobber (reg:CC CC_REGNUM))]
8118   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
8119   "xc\t%O0(%2,%R0),%S1"
8120   [(set_attr "op_type" "SS")])
8121
8122 (define_split
8123   [(set (match_operand 0 "memory_operand" "")
8124         (xor (match_dup 0)
8125              (match_operand 1 "memory_operand" "")))
8126    (clobber (reg:CC CC_REGNUM))]
8127   "reload_completed
8128    && GET_MODE (operands[0]) == GET_MODE (operands[1])
8129    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
8130   [(parallel
8131     [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
8132      (use (match_dup 2))
8133      (clobber (reg:CC CC_REGNUM))])]
8134 {
8135   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
8136   operands[0] = adjust_address (operands[0], BLKmode, 0);
8137   operands[1] = adjust_address (operands[1], BLKmode, 0);
8138 })
8139
8140 (define_peephole2
8141   [(parallel
8142     [(set (match_operand:BLK 0 "memory_operand" "")
8143           (xor:BLK (match_dup 0)
8144                    (match_operand:BLK 1 "memory_operand" "")))
8145      (use (match_operand 2 "const_int_operand" ""))
8146      (clobber (reg:CC CC_REGNUM))])
8147    (parallel
8148     [(set (match_operand:BLK 3 "memory_operand" "")
8149           (xor:BLK (match_dup 3)
8150                    (match_operand:BLK 4 "memory_operand" "")))
8151      (use (match_operand 5 "const_int_operand" ""))
8152      (clobber (reg:CC CC_REGNUM))])]
8153   "s390_offset_p (operands[0], operands[3], operands[2])
8154    && s390_offset_p (operands[1], operands[4], operands[2])
8155    && !s390_overlap_p (operands[0], operands[1],
8156                        INTVAL (operands[2]) + INTVAL (operands[5]))
8157    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
8158   [(parallel
8159     [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
8160      (use (match_dup 8))
8161      (clobber (reg:CC CC_REGNUM))])]
8162   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8163    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
8164    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
8165
8166 ;
8167 ; Block xor (XC) patterns with src == dest.
8168 ;
8169
8170 (define_insn "*xc_zero"
8171   [(set (match_operand:BLK 0 "memory_operand" "=Q")
8172         (const_int 0))
8173    (use (match_operand 1 "const_int_operand" "n"))
8174    (clobber (reg:CC CC_REGNUM))]
8175   "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
8176   "xc\t%O0(%1,%R0),%S0"
8177   [(set_attr "op_type" "SS")
8178    (set_attr "z196prop" "z196_cracked")])
8179
8180 (define_peephole2
8181   [(parallel
8182     [(set (match_operand:BLK 0 "memory_operand" "")
8183           (const_int 0))
8184      (use (match_operand 1 "const_int_operand" ""))
8185      (clobber (reg:CC CC_REGNUM))])
8186    (parallel
8187     [(set (match_operand:BLK 2 "memory_operand" "")
8188           (const_int 0))
8189      (use (match_operand 3 "const_int_operand" ""))
8190      (clobber (reg:CC CC_REGNUM))])]
8191   "s390_offset_p (operands[0], operands[2], operands[1])
8192    && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
8193   [(parallel
8194     [(set (match_dup 4) (const_int 0))
8195      (use (match_dup 5))
8196      (clobber (reg:CC CC_REGNUM))])]
8197   "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8198    operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
8199
8200
8201 ;;
8202 ;;- Negate instructions.
8203 ;;
8204
8205 ;
8206 ; neg(di|si)2 instruction pattern(s).
8207 ;
8208
8209 (define_expand "neg<mode>2"
8210   [(parallel
8211     [(set (match_operand:DSI 0 "register_operand" "=d")
8212           (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
8213      (clobber (reg:CC CC_REGNUM))])]
8214   ""
8215   "")
8216
8217 (define_insn "*negdi2_sign_cc"
8218   [(set (reg CC_REGNUM)
8219         (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
8220                            (match_operand:SI 1 "register_operand" "d") 0)
8221                            (const_int 32)) (const_int 32)))
8222                  (const_int 0)))
8223    (set (match_operand:DI 0 "register_operand" "=d")
8224         (neg:DI (sign_extend:DI (match_dup 1))))]
8225   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8226   "lcgfr\t%0,%1"
8227   [(set_attr "op_type"  "RRE")
8228    (set_attr "z10prop" "z10_c")])
8229
8230 (define_insn "*negdi2_sign"
8231   [(set (match_operand:DI 0 "register_operand" "=d")
8232         (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8233    (clobber (reg:CC CC_REGNUM))]
8234   "TARGET_ZARCH"
8235   "lcgfr\t%0,%1"
8236   [(set_attr "op_type"  "RRE")
8237    (set_attr "z10prop" "z10_c")])
8238
8239 ; lcr, lcgr
8240 (define_insn "*neg<mode>2_cc"
8241   [(set (reg CC_REGNUM)
8242         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8243                  (const_int 0)))
8244    (set (match_operand:GPR 0 "register_operand" "=d")
8245         (neg:GPR (match_dup 1)))]
8246   "s390_match_ccmode (insn, CCAmode)"
8247   "lc<g>r\t%0,%1"
8248   [(set_attr "op_type"  "RR<E>")
8249    (set_attr "z10prop" "z10_super_c_E1")])
8250
8251 ; lcr, lcgr
8252 (define_insn "*neg<mode>2_cconly"
8253   [(set (reg CC_REGNUM)
8254         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8255                  (const_int 0)))
8256    (clobber (match_scratch:GPR 0 "=d"))]
8257   "s390_match_ccmode (insn, CCAmode)"
8258   "lc<g>r\t%0,%1"
8259   [(set_attr "op_type"  "RR<E>")
8260    (set_attr "z10prop" "z10_super_c_E1")])
8261
8262 ; lcr, lcgr
8263 (define_insn "*neg<mode>2"
8264   [(set (match_operand:GPR 0 "register_operand" "=d")
8265         (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
8266    (clobber (reg:CC CC_REGNUM))]
8267   ""
8268   "lc<g>r\t%0,%1"
8269   [(set_attr "op_type"  "RR<E>")
8270    (set_attr "z10prop" "z10_super_c_E1")])
8271
8272 (define_insn "*negdi2_31"
8273   [(set (match_operand:DI 0 "register_operand" "=d")
8274         (neg:DI (match_operand:DI 1 "register_operand" "d")))
8275    (clobber (reg:CC CC_REGNUM))]
8276   "!TARGET_ZARCH"
8277   "#")
8278
8279 ; Split a DImode NEG on 31bit into 2 SImode NEGs
8280
8281 ; Doing the twos complement separately on the SImode parts does an
8282 ; unwanted +1 on the high part which needs to be subtracted afterwards
8283 ; ... unless the +1 on the low part created an overflow.
8284
8285 (define_split
8286   [(set (match_operand:DI 0 "register_operand" "")
8287         (neg:DI (match_operand:DI 1 "register_operand" "")))
8288    (clobber (reg:CC CC_REGNUM))]
8289   "!TARGET_ZARCH
8290    && (REGNO (operands[0]) == REGNO (operands[1])
8291       || s390_split_ok_p (operands[0], operands[1], DImode, 0))
8292    && reload_completed"
8293   [(parallel
8294     [(set (match_dup 2) (neg:SI (match_dup 3)))
8295      (clobber (reg:CC CC_REGNUM))])
8296    (parallel
8297     [(set (reg:CCAP CC_REGNUM)
8298           (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
8299      (set (match_dup 4) (neg:SI (match_dup 5)))])
8300    (set (pc)
8301         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8302                       (pc)
8303                       (label_ref (match_dup 6))))
8304    (parallel
8305     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8306      (clobber (reg:CC CC_REGNUM))])
8307    (match_dup 6)]
8308   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8309    operands[3] = operand_subword (operands[1], 0, 0, DImode);
8310    operands[4] = operand_subword (operands[0], 1, 0, DImode);
8311    operands[5] = operand_subword (operands[1], 1, 0, DImode);
8312    operands[6] = gen_label_rtx ();")
8313
8314 ; Like above but first make a copy of the low part of the src operand
8315 ; since it might overlap with the high part of the destination.
8316
8317 (define_split
8318   [(set (match_operand:DI 0 "register_operand" "")
8319         (neg:DI (match_operand:DI 1 "register_operand" "")))
8320    (clobber (reg:CC CC_REGNUM))]
8321   "!TARGET_ZARCH
8322    && s390_split_ok_p (operands[0], operands[1], DImode, 1)
8323    && reload_completed"
8324   [; Make a backup of op5 first
8325    (set (match_dup 4) (match_dup 5))
8326    ; Setting op2 here might clobber op5
8327    (parallel
8328     [(set (match_dup 2) (neg:SI (match_dup 3)))
8329      (clobber (reg:CC CC_REGNUM))])
8330    (parallel
8331     [(set (reg:CCAP CC_REGNUM)
8332           (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
8333      (set (match_dup 4) (neg:SI (match_dup 4)))])
8334    (set (pc)
8335         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8336                       (pc)
8337                       (label_ref (match_dup 6))))
8338    (parallel
8339     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8340      (clobber (reg:CC CC_REGNUM))])
8341    (match_dup 6)]
8342   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8343    operands[3] = operand_subword (operands[1], 0, 0, DImode);
8344    operands[4] = operand_subword (operands[0], 1, 0, DImode);
8345    operands[5] = operand_subword (operands[1], 1, 0, DImode);
8346    operands[6] = gen_label_rtx ();")
8347
8348 ;
8349 ; neg(df|sf)2 instruction pattern(s).
8350 ;
8351
8352 (define_expand "neg<mode>2"
8353   [(parallel
8354     [(set (match_operand:BFP 0 "register_operand" "=f")
8355           (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
8356      (clobber (reg:CC CC_REGNUM))])]
8357   "TARGET_HARD_FLOAT"
8358   "")
8359
8360 ; lcxbr, lcdbr, lcebr
8361 (define_insn "*neg<mode>2_cc"
8362   [(set (reg CC_REGNUM)
8363         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8364                  (match_operand:BFP 2 "const0_operand" "")))
8365    (set (match_operand:BFP 0 "register_operand" "=f")
8366         (neg:BFP (match_dup 1)))]
8367   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8368   "lc<xde>br\t%0,%1"
8369   [(set_attr "op_type"  "RRE")
8370    (set_attr "type"     "fsimp<mode>")])
8371
8372 ; lcxbr, lcdbr, lcebr
8373 (define_insn "*neg<mode>2_cconly"
8374   [(set (reg CC_REGNUM)
8375         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8376                  (match_operand:BFP 2 "const0_operand" "")))
8377    (clobber (match_scratch:BFP 0 "=f"))]
8378   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8379   "lc<xde>br\t%0,%1"
8380   [(set_attr "op_type"  "RRE")
8381    (set_attr "type"     "fsimp<mode>")])
8382
8383 ; lcdfr
8384 (define_insn "*neg<mode>2_nocc"
8385   [(set (match_operand:FP 0 "register_operand"         "=f")
8386         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8387   "TARGET_DFP"
8388   "lcdfr\t%0,%1"
8389   [(set_attr "op_type"  "RRE")
8390    (set_attr "type"     "fsimp<mode>")])
8391
8392 ; lcxbr, lcdbr, lcebr
8393 ; FIXME: wflcdb does not clobber cc
8394 (define_insn "*neg<mode>2"
8395   [(set (match_operand:BFP          0 "register_operand" "=f,v")
8396         (neg:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
8397    (clobber (reg:CC CC_REGNUM))]
8398   "TARGET_HARD_FLOAT"
8399   "@
8400    lc<xde>br\t%0,%1
8401    wflcdb\t%0,%1"
8402   [(set_attr "op_type"      "RRE,VRR")
8403    (set_attr "cpu_facility" "*,vx")
8404    (set_attr "type"         "fsimp<mode>,*")
8405    (set_attr "enabled"      "*,<DFDI>")])
8406
8407
8408 ;;
8409 ;;- Absolute value instructions.
8410 ;;
8411
8412 ;
8413 ; abs(di|si)2 instruction pattern(s).
8414 ;
8415
8416 (define_insn "*absdi2_sign_cc"
8417   [(set (reg CC_REGNUM)
8418         (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8419                            (match_operand:SI 1 "register_operand" "d") 0)
8420                            (const_int 32)) (const_int 32)))
8421                  (const_int 0)))
8422    (set (match_operand:DI 0 "register_operand" "=d")
8423         (abs:DI (sign_extend:DI (match_dup 1))))]
8424   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8425   "lpgfr\t%0,%1"
8426   [(set_attr "op_type"  "RRE")
8427    (set_attr "z10prop" "z10_c")])
8428
8429 (define_insn "*absdi2_sign"
8430   [(set (match_operand:DI 0 "register_operand" "=d")
8431         (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8432    (clobber (reg:CC CC_REGNUM))]
8433   "TARGET_ZARCH"
8434   "lpgfr\t%0,%1"
8435   [(set_attr "op_type"  "RRE")
8436    (set_attr "z10prop" "z10_c")])
8437
8438 ; lpr, lpgr
8439 (define_insn "*abs<mode>2_cc"
8440   [(set (reg CC_REGNUM)
8441         (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8442                  (const_int 0)))
8443    (set (match_operand:GPR 0 "register_operand" "=d")
8444         (abs:GPR (match_dup 1)))]
8445   "s390_match_ccmode (insn, CCAmode)"
8446   "lp<g>r\t%0,%1"
8447   [(set_attr "op_type"  "RR<E>")
8448    (set_attr "z10prop" "z10_c")])
8449
8450 ; lpr, lpgr
8451 (define_insn "*abs<mode>2_cconly"
8452   [(set (reg CC_REGNUM)
8453         (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8454                  (const_int 0)))
8455    (clobber (match_scratch:GPR 0 "=d"))]
8456   "s390_match_ccmode (insn, CCAmode)"
8457   "lp<g>r\t%0,%1"
8458   [(set_attr "op_type"  "RR<E>")
8459    (set_attr "z10prop" "z10_c")])
8460
8461 ; lpr, lpgr
8462 (define_insn "abs<mode>2"
8463   [(set (match_operand:GPR 0 "register_operand" "=d")
8464         (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8465    (clobber (reg:CC CC_REGNUM))]
8466   ""
8467   "lp<g>r\t%0,%1"
8468   [(set_attr "op_type"  "RR<E>")
8469    (set_attr "z10prop" "z10_c")])
8470
8471 ;
8472 ; abs(df|sf)2 instruction pattern(s).
8473 ;
8474
8475 (define_expand "abs<mode>2"
8476   [(parallel
8477     [(set (match_operand:BFP 0 "register_operand" "=f")
8478           (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8479      (clobber (reg:CC CC_REGNUM))])]
8480   "TARGET_HARD_FLOAT"
8481   "")
8482
8483 ; lpxbr, lpdbr, lpebr
8484 (define_insn "*abs<mode>2_cc"
8485   [(set (reg CC_REGNUM)
8486         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8487                  (match_operand:BFP 2 "const0_operand" "")))
8488    (set (match_operand:BFP 0 "register_operand" "=f")
8489         (abs:BFP (match_dup 1)))]
8490   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8491   "lp<xde>br\t%0,%1"
8492   [(set_attr "op_type"  "RRE")
8493    (set_attr "type"     "fsimp<mode>")])
8494
8495 ; lpxbr, lpdbr, lpebr
8496 (define_insn "*abs<mode>2_cconly"
8497   [(set (reg CC_REGNUM)
8498         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8499                  (match_operand:BFP 2 "const0_operand" "")))
8500    (clobber (match_scratch:BFP 0 "=f"))]
8501   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8502   "lp<xde>br\t%0,%1"
8503   [(set_attr "op_type"  "RRE")
8504    (set_attr "type"     "fsimp<mode>")])
8505
8506 ; lpdfr
8507 (define_insn "*abs<mode>2_nocc"
8508   [(set (match_operand:FP 0 "register_operand"         "=f")
8509         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8510   "TARGET_DFP"
8511   "lpdfr\t%0,%1"
8512   [(set_attr "op_type"  "RRE")
8513    (set_attr "type"     "fsimp<mode>")])
8514
8515 ; lpxbr, lpdbr, lpebr
8516 ; FIXME: wflpdb does not clobber cc
8517 (define_insn "*abs<mode>2"
8518   [(set (match_operand:BFP          0 "register_operand" "=f,v")
8519         (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
8520    (clobber (reg:CC CC_REGNUM))]
8521   "TARGET_HARD_FLOAT"
8522   "@
8523     lp<xde>br\t%0,%1
8524     wflpdb\t%0,%1"
8525   [(set_attr "op_type"      "RRE,VRR")
8526    (set_attr "cpu_facility" "*,vx")
8527    (set_attr "type"         "fsimp<mode>,*")
8528    (set_attr "enabled"      "*,<DFDI>")])
8529
8530
8531 ;;
8532 ;;- Negated absolute value instructions
8533 ;;
8534
8535 ;
8536 ; Integer
8537 ;
8538
8539 (define_insn "*negabsdi2_sign_cc"
8540   [(set (reg CC_REGNUM)
8541         (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8542                            (match_operand:SI 1 "register_operand" "d") 0)
8543                            (const_int 32)) (const_int 32))))
8544                  (const_int 0)))
8545    (set (match_operand:DI 0 "register_operand" "=d")
8546         (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8547   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8548   "lngfr\t%0,%1"
8549   [(set_attr "op_type"  "RRE")
8550    (set_attr "z10prop" "z10_c")])
8551
8552 (define_insn "*negabsdi2_sign"
8553   [(set (match_operand:DI 0 "register_operand" "=d")
8554         (neg:DI (abs:DI (sign_extend:DI
8555                           (match_operand:SI 1 "register_operand" "d")))))
8556    (clobber (reg:CC CC_REGNUM))]
8557   "TARGET_ZARCH"
8558   "lngfr\t%0,%1"
8559   [(set_attr "op_type" "RRE")
8560    (set_attr "z10prop" "z10_c")])
8561
8562 ; lnr, lngr
8563 (define_insn "*negabs<mode>2_cc"
8564   [(set (reg CC_REGNUM)
8565         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8566                  (const_int 0)))
8567    (set (match_operand:GPR 0 "register_operand" "=d")
8568         (neg:GPR (abs:GPR (match_dup 1))))]
8569   "s390_match_ccmode (insn, CCAmode)"
8570   "ln<g>r\t%0,%1"
8571   [(set_attr "op_type"  "RR<E>")
8572    (set_attr "z10prop" "z10_c")])
8573
8574 ; lnr, lngr
8575 (define_insn "*negabs<mode>2_cconly"
8576   [(set (reg CC_REGNUM)
8577         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8578                  (const_int 0)))
8579    (clobber (match_scratch:GPR 0 "=d"))]
8580   "s390_match_ccmode (insn, CCAmode)"
8581   "ln<g>r\t%0,%1"
8582   [(set_attr "op_type"  "RR<E>")
8583    (set_attr "z10prop" "z10_c")])
8584
8585 ; lnr, lngr
8586 (define_insn "*negabs<mode>2"
8587   [(set (match_operand:GPR 0 "register_operand" "=d")
8588         (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8589    (clobber (reg:CC CC_REGNUM))]
8590   ""
8591   "ln<g>r\t%0,%1"
8592   [(set_attr "op_type" "RR<E>")
8593    (set_attr "z10prop" "z10_c")])
8594
8595 ;
8596 ; Floating point
8597 ;
8598
8599 ; lnxbr, lndbr, lnebr
8600 (define_insn "*negabs<mode>2_cc"
8601   [(set (reg CC_REGNUM)
8602         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8603                  (match_operand:BFP 2 "const0_operand" "")))
8604    (set (match_operand:BFP 0 "register_operand" "=f")
8605         (neg:BFP (abs:BFP (match_dup 1))))]
8606   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8607   "ln<xde>br\t%0,%1"
8608   [(set_attr "op_type"  "RRE")
8609    (set_attr "type"     "fsimp<mode>")])
8610
8611 ; lnxbr, lndbr, lnebr
8612 (define_insn "*negabs<mode>2_cconly"
8613   [(set (reg CC_REGNUM)
8614         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8615                  (match_operand:BFP 2 "const0_operand" "")))
8616    (clobber (match_scratch:BFP 0 "=f"))]
8617   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8618   "ln<xde>br\t%0,%1"
8619   [(set_attr "op_type"  "RRE")
8620    (set_attr "type"     "fsimp<mode>")])
8621
8622 ; lndfr
8623 (define_insn "*negabs<mode>2_nocc"
8624   [(set (match_operand:FP 0 "register_operand"                  "=f")
8625         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8626   "TARGET_DFP"
8627   "lndfr\t%0,%1"
8628   [(set_attr "op_type"  "RRE")
8629    (set_attr "type"     "fsimp<mode>")])
8630
8631 ; lnxbr, lndbr, lnebr
8632 ; FIXME: wflndb does not clobber cc
8633 (define_insn "*negabs<mode>2"
8634   [(set (match_operand:BFP                   0 "register_operand" "=f,v")
8635         (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v"))))
8636    (clobber (reg:CC CC_REGNUM))]
8637   "TARGET_HARD_FLOAT"
8638   "@
8639    ln<xde>br\t%0,%1
8640    wflndb\t%0,%1"
8641   [(set_attr "op_type"      "RRE,VRR")
8642    (set_attr "cpu_facility" "*,vx")
8643    (set_attr "type"         "fsimp<mode>,*")
8644    (set_attr "enabled"      "*,<DFDI>")])
8645
8646 ;;
8647 ;;- Square root instructions.
8648 ;;
8649
8650 ;
8651 ; sqrt(df|sf)2 instruction pattern(s).
8652 ;
8653
8654 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8655 (define_insn "sqrt<mode>2"
8656   [(set (match_operand:BFP           0 "register_operand" "=f,f,v")
8657         (sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,R,v")))]
8658   "TARGET_HARD_FLOAT"
8659   "@
8660    sq<xde>br\t%0,%1
8661    sq<xde>b\t%0,%1
8662    wfsqdb\t%v0,%v1"
8663   [(set_attr "op_type"      "RRE,RXE,VRR")
8664    (set_attr "type"         "fsqrt<mode>")
8665    (set_attr "cpu_facility" "*,*,vx")
8666    (set_attr "enabled"      "*,<DSF>,<DFDI>")])
8667
8668
8669 ;;
8670 ;;- One complement instructions.
8671 ;;
8672
8673 ;
8674 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8675 ;
8676
8677 (define_expand "one_cmpl<mode>2"
8678   [(parallel
8679     [(set (match_operand:INT 0 "register_operand" "")
8680           (xor:INT (match_operand:INT 1 "register_operand" "")
8681                    (const_int -1)))
8682      (clobber (reg:CC CC_REGNUM))])]
8683   ""
8684   "")
8685
8686
8687 ;;
8688 ;; Find leftmost bit instructions.
8689 ;;
8690
8691 (define_expand "clzdi2"
8692   [(set (match_operand:DI 0 "register_operand" "=d")
8693         (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8694   "TARGET_EXTIMM && TARGET_ZARCH"
8695 {
8696   rtx_insn *insn;
8697   rtx clz_equal;
8698   rtx wide_reg = gen_reg_rtx (TImode);
8699   rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63);
8700
8701   clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8702
8703   emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8704
8705   insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8706   set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8707
8708   DONE;
8709 })
8710
8711 (define_insn "clztidi2"
8712   [(set (match_operand:TI 0 "register_operand" "=d")
8713         (ior:TI
8714           (ashift:TI
8715             (zero_extend:TI
8716               (xor:DI (match_operand:DI 1 "register_operand" "d")
8717                       (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8718                                 (subreg:SI (clz:DI (match_dup 1)) 4))))
8719
8720             (const_int 64))
8721           (zero_extend:TI (clz:DI (match_dup 1)))))
8722    (clobber (reg:CC CC_REGNUM))]
8723   "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63
8724    && TARGET_EXTIMM && TARGET_ZARCH"
8725   "flogr\t%0,%1"
8726   [(set_attr "op_type"  "RRE")])
8727
8728
8729 ;;
8730 ;;- Rotate instructions.
8731 ;;
8732
8733 ;
8734 ; rotl(di|si)3 instruction pattern(s).
8735 ;
8736
8737 (define_expand "rotl<mode>3"
8738   [(set (match_operand:GPR 0 "register_operand" "")
8739         (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8740                     (match_operand:SI 2 "nonmemory_operand" "")))]
8741   "TARGET_CPU_ZARCH"
8742   "")
8743
8744 ; rll, rllg
8745 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8746   [(set (match_operand:GPR             0 "register_operand"  "=d")
8747         (rotate:GPR (match_operand:GPR 1 "register_operand"   "d")
8748                     (match_operand:SI  2 "nonmemory_operand" "an")))]
8749   "TARGET_CPU_ZARCH"
8750   "rll<g>\t%0,%1,<addr_style_op_ops>"
8751   [(set_attr "op_type"  "RSE")
8752    (set_attr "atype"    "reg")
8753    (set_attr "z10prop"  "z10_super_E1")])
8754
8755
8756 ;;
8757 ;;- Shift instructions.
8758 ;;
8759
8760 ;
8761 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8762 ; Left shifts and logical right shifts
8763
8764 (define_expand "<shift><mode>3"
8765   [(set (match_operand:DSI 0 "register_operand" "")
8766         (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8767                    (match_operand:SI 2 "nonmemory_operand" "")))]
8768   ""
8769   "")
8770
8771 ; ESA 64 bit register pair shift with reg or imm shift count
8772 ; sldl, srdl
8773 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8774   [(set (match_operand:DI 0 "register_operand"            "=d")
8775         (SHIFT:DI (match_operand:DI 1 "register_operand"   "0")
8776                   (match_operand:SI 2 "nonmemory_operand" "an")))]
8777   "!TARGET_ZARCH"
8778   "s<lr>dl\t%0,<addr_style_op_ops>"
8779   [(set_attr "op_type"  "RS")
8780    (set_attr "atype"    "reg")
8781    (set_attr "z196prop" "z196_cracked")])
8782
8783
8784 ; 64 bit register shift with reg or imm shift count
8785 ; sll, srl, sllg, srlg, sllk, srlk
8786 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8787   [(set (match_operand:GPR 0 "register_operand"              "=d, d")
8788         (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8789                    (match_operand:SI 2 "nonmemory_operand"   "an,an")))]
8790   ""
8791   "@
8792    s<lr>l<g>\t%0,<1><addr_style_op_ops>
8793    s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8794   [(set_attr "op_type"  "RS<E>,RSY")
8795    (set_attr "atype"    "reg,reg")
8796    (set_attr "cpu_facility" "*,z196")
8797    (set_attr "z10prop"  "z10_super_E1,*")])
8798
8799 ;
8800 ; ashr(di|si)3 instruction pattern(s).
8801 ; Arithmetic right shifts
8802
8803 (define_expand "ashr<mode>3"
8804   [(parallel
8805     [(set (match_operand:DSI 0 "register_operand" "")
8806           (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8807                         (match_operand:SI 2 "nonmemory_operand" "")))
8808      (clobber (reg:CC CC_REGNUM))])]
8809   ""
8810   "")
8811
8812 ; FIXME: The number of alternatives is doubled here to match the fix
8813 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8814 ; The right fix should be to support match_scratch in the output
8815 ; pattern of a define_subst.
8816 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8817   [(set (match_operand:DI 0 "register_operand"               "=d, d")
8818         (ashiftrt:DI (match_operand:DI 1 "register_operand"   "0, 0")
8819                      (match_operand:SI 2 "nonmemory_operand" "an,an")))
8820    (clobber (reg:CC CC_REGNUM))]
8821   "!TARGET_ZARCH"
8822   "@
8823    srda\t%0,<addr_style_op_cc_ops>
8824    srda\t%0,<addr_style_op_cc_ops>"
8825   [(set_attr "op_type" "RS")
8826    (set_attr "atype"   "reg")])
8827
8828
8829 ; sra, srag
8830 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8831   [(set (match_operand:GPR 0 "register_operand"                 "=d, d")
8832         (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8833                       (match_operand:SI 2 "nonmemory_operand"   "an,an")))
8834    (clobber (reg:CC CC_REGNUM))]
8835   ""
8836   "@
8837    sra<g>\t%0,<1><addr_style_op_cc_ops>
8838    sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8839   [(set_attr "op_type"  "RS<E>,RSY")
8840    (set_attr "atype"    "reg")
8841    (set_attr "cpu_facility" "*,z196")
8842    (set_attr "z10prop" "z10_super_E1,*")])
8843
8844
8845 ;;
8846 ;; Branch instruction patterns.
8847 ;;
8848
8849 (define_expand "cbranch<mode>4"
8850   [(set (pc)
8851         (if_then_else (match_operator 0 "comparison_operator"
8852                        [(match_operand:GPR 1 "register_operand" "")
8853                         (match_operand:GPR 2 "general_operand" "")])
8854                       (label_ref (match_operand 3 "" ""))
8855                       (pc)))]
8856   ""
8857   "s390_emit_jump (operands[3],
8858     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8859    DONE;")
8860
8861 (define_expand "cbranch<mode>4"
8862   [(set (pc)
8863         (if_then_else (match_operator 0 "comparison_operator"
8864                        [(match_operand:FP 1 "register_operand" "")
8865                         (match_operand:FP 2 "general_operand" "")])
8866                       (label_ref (match_operand 3 "" ""))
8867                       (pc)))]
8868   "TARGET_HARD_FLOAT"
8869   "s390_emit_jump (operands[3],
8870     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8871    DONE;")
8872
8873 (define_expand "cbranchcc4"
8874   [(set (pc)
8875         (if_then_else (match_operator 0 "s390_comparison"
8876                        [(match_operand 1 "cc_reg_operand" "")
8877                         (match_operand 2 "const_int_operand" "")])
8878                       (label_ref (match_operand 3 "" ""))
8879                       (pc)))]
8880   ""
8881   "")
8882
8883
8884 ;;
8885 ;;- Conditional jump instructions.
8886 ;;
8887
8888 (define_insn "*cjump_64"
8889   [(set (pc)
8890         (if_then_else
8891           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8892                                                (match_operand 2 "const_int_operand" "")])
8893           (label_ref (match_operand 0 "" ""))
8894           (pc)))]
8895   "TARGET_CPU_ZARCH"
8896 {
8897   if (get_attr_length (insn) == 4)
8898     return "j%C1\t%l0";
8899   else
8900     return "jg%C1\t%l0";
8901 }
8902   [(set_attr "op_type" "RI")
8903    (set_attr "type"    "branch")
8904    (set (attr "length")
8905         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8906                       (const_int 4) (const_int 6)))])
8907
8908 (define_insn "*cjump_31"
8909   [(set (pc)
8910         (if_then_else
8911           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8912                                                (match_operand 2 "const_int_operand" "")])
8913           (label_ref (match_operand 0 "" ""))
8914           (pc)))]
8915   "!TARGET_CPU_ZARCH"
8916 {
8917   gcc_assert (get_attr_length (insn) == 4);
8918   return "j%C1\t%l0";
8919 }
8920   [(set_attr "op_type" "RI")
8921    (set_attr "type"    "branch")
8922    (set (attr "length")
8923         (if_then_else (not (match_test "flag_pic"))
8924           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8925                         (const_int 4) (const_int 6))
8926           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8927                         (const_int 4) (const_int 8))))])
8928
8929 (define_insn "*cjump_long"
8930   [(set (pc)
8931         (if_then_else
8932           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8933           (match_operand 0 "address_operand" "ZQZR")
8934           (pc)))]
8935   ""
8936 {
8937   if (get_attr_op_type (insn) == OP_TYPE_RR)
8938     return "b%C1r\t%0";
8939   else
8940     return "b%C1\t%a0";
8941 }
8942   [(set (attr "op_type")
8943         (if_then_else (match_operand 0 "register_operand" "")
8944                       (const_string "RR") (const_string "RX")))
8945    (set_attr "type"  "branch")
8946    (set_attr "atype" "agen")])
8947
8948 ;; A conditional return instruction.
8949 (define_insn "*c<code>"
8950   [(set (pc)
8951         (if_then_else
8952           (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8953           (ANY_RETURN)
8954           (pc)))]
8955   "s390_can_use_<code>_insn ()"
8956   "b%C0r\t%%r14"
8957   [(set_attr "op_type" "RR")
8958    (set_attr "type"  "jsr")
8959    (set_attr "atype" "agen")])
8960
8961 ;;
8962 ;;- Negated conditional jump instructions.
8963 ;;
8964
8965 (define_insn "*icjump_64"
8966   [(set (pc)
8967         (if_then_else
8968           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8969           (pc)
8970           (label_ref (match_operand 0 "" ""))))]
8971   "TARGET_CPU_ZARCH"
8972 {
8973   if (get_attr_length (insn) == 4)
8974     return "j%D1\t%l0";
8975   else
8976     return "jg%D1\t%l0";
8977 }
8978   [(set_attr "op_type" "RI")
8979    (set_attr "type"    "branch")
8980    (set (attr "length")
8981         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8982                       (const_int 4) (const_int 6)))])
8983
8984 (define_insn "*icjump_31"
8985   [(set (pc)
8986         (if_then_else
8987           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8988           (pc)
8989           (label_ref (match_operand 0 "" ""))))]
8990   "!TARGET_CPU_ZARCH"
8991 {
8992   gcc_assert (get_attr_length (insn) == 4);
8993   return "j%D1\t%l0";
8994 }
8995   [(set_attr "op_type" "RI")
8996    (set_attr "type"    "branch")
8997    (set (attr "length")
8998         (if_then_else (not (match_test "flag_pic"))
8999           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9000                         (const_int 4) (const_int 6))
9001           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9002                         (const_int 4) (const_int 8))))])
9003
9004 (define_insn "*icjump_long"
9005   [(set (pc)
9006         (if_then_else
9007           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
9008           (pc)
9009           (match_operand 0 "address_operand" "ZQZR")))]
9010   ""
9011 {
9012   if (get_attr_op_type (insn) == OP_TYPE_RR)
9013     return "b%D1r\t%0";
9014   else
9015     return "b%D1\t%a0";
9016 }
9017   [(set (attr "op_type")
9018         (if_then_else (match_operand 0 "register_operand" "")
9019                       (const_string "RR") (const_string "RX")))
9020    (set_attr "type"  "branch")
9021    (set_attr "atype" "agen")])
9022
9023 ;;
9024 ;;- Trap instructions.
9025 ;;
9026
9027 (define_insn "trap"
9028   [(trap_if (const_int 1) (const_int 0))]
9029   ""
9030   "j\t.+2"
9031   [(set_attr "op_type" "RI")
9032    (set_attr "type"  "branch")])
9033
9034 (define_expand "ctrap<mode>4"
9035   [(trap_if (match_operator 0 "comparison_operator"
9036              [(match_operand:GPR 1 "register_operand" "")
9037               (match_operand:GPR 2 "general_operand" "")])
9038              (match_operand 3 "const0_operand" ""))]
9039   ""
9040   {
9041     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
9042                                   operands[1], operands[2]);
9043     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
9044     DONE;
9045   })
9046
9047 (define_expand "ctrap<mode>4"
9048   [(trap_if (match_operator 0 "comparison_operator"
9049              [(match_operand:FP 1 "register_operand" "")
9050               (match_operand:FP 2 "general_operand" "")])
9051              (match_operand 3 "const0_operand" ""))]
9052   ""
9053   {
9054     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
9055                                   operands[1], operands[2]);
9056     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
9057     DONE;
9058   })
9059
9060 (define_insn "condtrap"
9061   [(trap_if (match_operator 0 "s390_comparison"
9062              [(match_operand 1 "cc_reg_operand" "c")
9063               (const_int 0)])
9064             (const_int 0))]
9065   ""
9066   "j%C0\t.+2";
9067   [(set_attr "op_type" "RI")
9068    (set_attr "type"  "branch")])
9069
9070 ; crt, cgrt, cit, cgit
9071 (define_insn "*cmp_and_trap_signed_int<mode>"
9072   [(trap_if (match_operator 0 "s390_signed_integer_comparison"
9073                [(match_operand:GPR 1 "register_operand"  "d,d")
9074                 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
9075             (const_int 0))]
9076   "TARGET_Z10"
9077   "@
9078    c<g>rt%C0\t%1,%2
9079    c<g>it%C0\t%1,%h2"
9080   [(set_attr "op_type" "RRF,RIE")
9081    (set_attr "type"    "branch")
9082    (set_attr "z10prop" "z10_super_c,z10_super")])
9083
9084 ; clrt, clgrt, clfit, clgit, clt, clgt
9085 (define_insn "*cmp_and_trap_unsigned_int<mode>"
9086   [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
9087                [(match_operand:GPR 1 "register_operand" "d,d,d")
9088                 (match_operand:GPR 2 "general_operand"  "d,D,T")])
9089             (const_int 0))]
9090   "TARGET_Z10"
9091   "@
9092    cl<g>rt%C0\t%1,%2
9093    cl<gf>it%C0\t%1,%x2
9094    cl<g>t%C0\t%1,%2"
9095   [(set_attr "op_type"      "RRF,RIE,RSY")
9096    (set_attr "type"         "branch")
9097    (set_attr "z10prop"      "z10_super_c,z10_super,*")
9098    (set_attr "cpu_facility" "z10,z10,zEC12")])
9099
9100 ; lat, lgat
9101 (define_insn "*load_and_trap<mode>"
9102   [(trap_if (eq (match_operand:GPR 0 "memory_operand"  "T")
9103                 (const_int 0))
9104             (const_int 0))
9105    (set (match_operand:GPR 1 "register_operand" "=d")
9106         (match_dup 0))]
9107   "TARGET_ZEC12"
9108   "l<g>at\t%1,%0"
9109   [(set_attr "op_type" "RXY")])
9110
9111
9112 ;;
9113 ;;- Loop instructions.
9114 ;;
9115 ;;  This is all complicated by the fact that since this is a jump insn
9116 ;;  we must handle our own output reloads.
9117
9118 ;; branch on index
9119
9120 ; This splitter will be matched by combine and has to add the 2 moves
9121 ; necessary to load the compare and the increment values into a
9122 ; register pair as needed by brxle.
9123
9124 (define_insn_and_split "*brx_stage1_<GPR:mode>"
9125   [(set (pc)
9126         (if_then_else
9127          (match_operator 6 "s390_brx_operator"
9128             [(plus:GPR (match_operand:GPR 1 "register_operand" "")
9129                        (match_operand:GPR 2 "general_operand"  ""))
9130              (match_operand:GPR 3 "register_operand" "")])
9131          (label_ref (match_operand 0 "" ""))
9132          (pc)))
9133    (set (match_operand:GPR 4 "nonimmediate_operand" "")
9134         (plus:GPR (match_dup 1) (match_dup 2)))
9135    (clobber (match_scratch:GPR 5 ""))]
9136   "TARGET_CPU_ZARCH"
9137   "#"
9138   "!reload_completed && !reload_in_progress"
9139   [(set (match_dup 7) (match_dup 2)) ; the increment
9140    (set (match_dup 8) (match_dup 3)) ; the comparison value
9141    (parallel [(set (pc)
9142                    (if_then_else
9143                     (match_op_dup 6
9144                        [(plus:GPR (match_dup 1) (match_dup 7))
9145                         (match_dup 8)])
9146                     (label_ref (match_dup 0))
9147                     (pc)))
9148               (set (match_dup 4)
9149                    (plus:GPR (match_dup 1) (match_dup 7)))
9150               (clobber (match_dup 5))
9151               (clobber (reg:CC CC_REGNUM))])]
9152   {
9153     rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
9154     operands[7] = gen_lowpart (<GPR:MODE>mode,
9155                                gen_highpart (word_mode, dreg));
9156     operands[8] = gen_lowpart (<GPR:MODE>mode,
9157                                gen_lowpart (word_mode, dreg));
9158   })
9159
9160 ; brxlg, brxhg
9161
9162 (define_insn_and_split "*brxg_64bit"
9163   [(set (pc)
9164         (if_then_else
9165           (match_operator 5 "s390_brx_operator"
9166              [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
9167                        (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
9168               (subreg:DI (match_dup 2) 8)])
9169           (label_ref (match_operand 0 "" ""))
9170           (pc)))
9171    (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
9172         (plus:DI (match_dup 1)
9173                  (subreg:DI (match_dup 2) 0)))
9174    (clobber (match_scratch:DI 4 "=X,&1,&?d"))
9175    (clobber (reg:CC CC_REGNUM))]
9176   "TARGET_ZARCH"
9177 {
9178   if (which_alternative != 0)
9179     return "#";
9180   else if (get_attr_length (insn) == 6)
9181     return "brx%E5g\t%1,%2,%l0";
9182   else
9183     return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
9184 }
9185   "&& reload_completed
9186    && (!REG_P (operands[3])
9187        || !rtx_equal_p (operands[1], operands[3]))"
9188   [(set (match_dup 4) (match_dup 1))
9189    (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
9190               (clobber (reg:CC CC_REGNUM))])
9191    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
9192    (set (match_dup 3) (match_dup 4))
9193    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9194                            (label_ref (match_dup 0))
9195                            (pc)))]
9196   ""
9197   [(set_attr "op_type"  "RIE")
9198    (set_attr "type"  "branch")
9199    (set (attr "length")
9200         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9201                       (const_int 6) (const_int 16)))])
9202
9203 ; brxle, brxh
9204
9205 (define_insn_and_split "*brx_64bit"
9206   [(set (pc)
9207         (if_then_else
9208           (match_operator 5 "s390_brx_operator"
9209              [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9210                        (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
9211               (subreg:SI (match_dup 2) 12)])
9212           (label_ref (match_operand 0 "" ""))
9213           (pc)))
9214    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9215         (plus:SI (match_dup 1)
9216                  (subreg:SI (match_dup 2) 4)))
9217    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9218    (clobber (reg:CC CC_REGNUM))]
9219   "TARGET_ZARCH"
9220 {
9221   if (which_alternative != 0)
9222     return "#";
9223   else if (get_attr_length (insn) == 6)
9224     return "brx%C5\t%1,%2,%l0";
9225   else
9226     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9227 }
9228   "&& reload_completed
9229    && (!REG_P (operands[3])
9230        || !rtx_equal_p (operands[1], operands[3]))"
9231   [(set (match_dup 4) (match_dup 1))
9232    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
9233               (clobber (reg:CC CC_REGNUM))])
9234    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
9235    (set (match_dup 3) (match_dup 4))
9236    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9237                            (label_ref (match_dup 0))
9238                            (pc)))]
9239   ""
9240   [(set_attr "op_type"  "RSI")
9241    (set_attr "type"  "branch")
9242    (set (attr "length")
9243         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9244                       (const_int 6) (const_int 14)))])
9245
9246 ; brxle, brxh
9247
9248 (define_insn_and_split "*brx_31bit"
9249   [(set (pc)
9250         (if_then_else
9251           (match_operator 5 "s390_brx_operator"
9252             [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9253                       (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9254              (subreg:SI (match_dup 2) 4)])
9255           (label_ref (match_operand 0 "" ""))
9256           (pc)))
9257    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9258         (plus:SI (match_dup 1)
9259                  (subreg:SI (match_dup 2) 0)))
9260    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9261    (clobber (reg:CC CC_REGNUM))]
9262   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9263 {
9264   if (which_alternative != 0)
9265     return "#";
9266   else if (get_attr_length (insn) == 6)
9267     return "brx%C5\t%1,%2,%l0";
9268   else
9269     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9270 }
9271   "&& reload_completed
9272    && (!REG_P (operands[3])
9273        || !rtx_equal_p (operands[1], operands[3]))"
9274   [(set (match_dup 4) (match_dup 1))
9275    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9276               (clobber (reg:CC CC_REGNUM))])
9277    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9278    (set (match_dup 3) (match_dup 4))
9279    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9280                            (label_ref (match_dup 0))
9281                            (pc)))]
9282   ""
9283   [(set_attr "op_type"  "RSI")
9284    (set_attr "type"  "branch")
9285    (set (attr "length")
9286         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9287                       (const_int 6) (const_int 14)))])
9288
9289
9290 ;; branch on count
9291
9292 (define_expand "doloop_end"
9293   [(use (match_operand 0 "" ""))        ; loop pseudo
9294    (use (match_operand 1 "" ""))]       ; label
9295   ""
9296 {
9297   if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9298     emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9299   else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9300     emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9301   else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9302     emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9303   else
9304     FAIL;
9305
9306   DONE;
9307 })
9308
9309 (define_insn_and_split "doloop_si64"
9310   [(set (pc)
9311         (if_then_else
9312           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9313               (const_int 1))
9314           (label_ref (match_operand 0 "" ""))
9315           (pc)))
9316    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9317         (plus:SI (match_dup 1) (const_int -1)))
9318    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9319    (clobber (reg:CC CC_REGNUM))]
9320   "TARGET_CPU_ZARCH"
9321 {
9322   if (which_alternative != 0)
9323     return "#";
9324   else if (get_attr_length (insn) == 4)
9325     return "brct\t%1,%l0";
9326   else
9327     return "ahi\t%1,-1\;jgne\t%l0";
9328 }
9329   "&& reload_completed
9330    && (! REG_P (operands[2])
9331        || ! rtx_equal_p (operands[1], operands[2]))"
9332   [(set (match_dup 3) (match_dup 1))
9333    (parallel [(set (reg:CCAN CC_REGNUM)
9334                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9335                                  (const_int 0)))
9336               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9337    (set (match_dup 2) (match_dup 3))
9338    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9339                            (label_ref (match_dup 0))
9340                            (pc)))]
9341   ""
9342   [(set_attr "op_type"  "RI")
9343    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9344    ; hurt us in the (rare) case of ahi.
9345    (set_attr "z10prop"  "z10_super_E1")
9346    (set_attr "type"  "branch")
9347    (set (attr "length")
9348         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9349                       (const_int 4) (const_int 10)))])
9350
9351 (define_insn_and_split "doloop_si31"
9352   [(set (pc)
9353         (if_then_else
9354           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9355               (const_int 1))
9356           (label_ref (match_operand 0 "" ""))
9357           (pc)))
9358    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9359         (plus:SI (match_dup 1) (const_int -1)))
9360    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9361    (clobber (reg:CC CC_REGNUM))]
9362   "!TARGET_CPU_ZARCH"
9363 {
9364   if (which_alternative != 0)
9365     return "#";
9366   else if (get_attr_length (insn) == 4)
9367     return "brct\t%1,%l0";
9368   else
9369     gcc_unreachable ();
9370 }
9371   "&& reload_completed
9372    && (! REG_P (operands[2])
9373        || ! rtx_equal_p (operands[1], operands[2]))"
9374   [(set (match_dup 3) (match_dup 1))
9375    (parallel [(set (reg:CCAN CC_REGNUM)
9376                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9377                                  (const_int 0)))
9378               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9379    (set (match_dup 2) (match_dup 3))
9380    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9381                            (label_ref (match_dup 0))
9382                            (pc)))]
9383   ""
9384   [(set_attr "op_type"  "RI")
9385    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9386    ; hurt us in the (rare) case of ahi.
9387    (set_attr "z10prop"  "z10_super_E1")
9388    (set_attr "type"  "branch")
9389    (set (attr "length")
9390         (if_then_else (not (match_test "flag_pic"))
9391           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9392                         (const_int 4) (const_int 6))
9393           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9394                         (const_int 4) (const_int 8))))])
9395
9396 (define_insn "*doloop_si_long"
9397   [(set (pc)
9398         (if_then_else
9399           (ne (match_operand:SI 1 "register_operand" "d")
9400               (const_int 1))
9401           (match_operand 0 "address_operand" "ZR")
9402           (pc)))
9403    (set (match_operand:SI 2 "register_operand" "=1")
9404         (plus:SI (match_dup 1) (const_int -1)))
9405    (clobber (match_scratch:SI 3 "=X"))
9406    (clobber (reg:CC CC_REGNUM))]
9407   "!TARGET_CPU_ZARCH"
9408 {
9409   if (get_attr_op_type (insn) == OP_TYPE_RR)
9410     return "bctr\t%1,%0";
9411   else
9412     return "bct\t%1,%a0";
9413 }
9414   [(set (attr "op_type")
9415         (if_then_else (match_operand 0 "register_operand" "")
9416                       (const_string "RR") (const_string "RX")))
9417    (set_attr "type"  "branch")
9418    (set_attr "atype" "agen")
9419    (set_attr "z10prop"  "z10_c")
9420    (set_attr "z196prop" "z196_cracked")])
9421
9422 (define_insn_and_split "doloop_di"
9423   [(set (pc)
9424         (if_then_else
9425           (ne (match_operand:DI 1 "register_operand" "d,d,d")
9426               (const_int 1))
9427           (label_ref (match_operand 0 "" ""))
9428           (pc)))
9429    (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9430         (plus:DI (match_dup 1) (const_int -1)))
9431    (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9432    (clobber (reg:CC CC_REGNUM))]
9433   "TARGET_ZARCH"
9434 {
9435   if (which_alternative != 0)
9436     return "#";
9437   else if (get_attr_length (insn) == 4)
9438     return "brctg\t%1,%l0";
9439   else
9440     return "aghi\t%1,-1\;jgne\t%l0";
9441 }
9442   "&& reload_completed
9443    && (! REG_P (operands[2])
9444        || ! rtx_equal_p (operands[1], operands[2]))"
9445   [(set (match_dup 3) (match_dup 1))
9446    (parallel [(set (reg:CCAN CC_REGNUM)
9447                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9448                                  (const_int 0)))
9449               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9450    (set (match_dup 2) (match_dup 3))
9451    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9452                            (label_ref (match_dup 0))
9453                            (pc)))]
9454   ""
9455   [(set_attr "op_type"  "RI")
9456    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9457    ; hurt us in the (rare) case of ahi.
9458    (set_attr "z10prop"  "z10_super_E1")
9459    (set_attr "type"  "branch")
9460    (set (attr "length")
9461         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9462                       (const_int 4) (const_int 10)))])
9463
9464 ;;
9465 ;;- Unconditional jump instructions.
9466 ;;
9467
9468 ;
9469 ; jump instruction pattern(s).
9470 ;
9471
9472 (define_expand "jump"
9473   [(match_operand 0 "" "")]
9474   ""
9475   "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9476
9477 (define_insn "*jump64"
9478   [(set (pc) (label_ref (match_operand 0 "" "")))]
9479   "TARGET_CPU_ZARCH"
9480 {
9481   if (get_attr_length (insn) == 4)
9482     return "j\t%l0";
9483   else
9484     return "jg\t%l0";
9485 }
9486   [(set_attr "op_type" "RI")
9487    (set_attr "type"  "branch")
9488    (set (attr "length")
9489         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9490                       (const_int 4) (const_int 6)))])
9491
9492 (define_insn "*jump31"
9493   [(set (pc) (label_ref (match_operand 0 "" "")))]
9494   "!TARGET_CPU_ZARCH"
9495 {
9496   gcc_assert (get_attr_length (insn) == 4);
9497   return "j\t%l0";
9498 }
9499   [(set_attr "op_type" "RI")
9500    (set_attr "type"  "branch")
9501    (set (attr "length")
9502         (if_then_else (not (match_test "flag_pic"))
9503           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9504                         (const_int 4) (const_int 6))
9505           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9506                         (const_int 4) (const_int 8))))])
9507
9508 ;
9509 ; indirect-jump instruction pattern(s).
9510 ;
9511
9512 (define_insn "indirect_jump"
9513  [(set (pc) (match_operand 0 "address_operand" "ZR"))]
9514   ""
9515 {
9516   if (get_attr_op_type (insn) == OP_TYPE_RR)
9517     return "br\t%0";
9518   else
9519     return "b\t%a0";
9520 }
9521   [(set (attr "op_type")
9522         (if_then_else (match_operand 0 "register_operand" "")
9523                       (const_string "RR") (const_string "RX")))
9524    (set_attr "type"  "branch")
9525    (set_attr "atype" "agen")])
9526
9527 ;
9528 ; casesi instruction pattern(s).
9529 ;
9530
9531 (define_insn "casesi_jump"
9532  [(set (pc) (match_operand 0 "address_operand" "ZR"))
9533    (use (label_ref (match_operand 1 "" "")))]
9534   ""
9535 {
9536   if (get_attr_op_type (insn) == OP_TYPE_RR)
9537     return "br\t%0";
9538   else
9539     return "b\t%a0";
9540 }
9541   [(set (attr "op_type")
9542         (if_then_else (match_operand 0 "register_operand" "")
9543                       (const_string "RR") (const_string "RX")))
9544    (set_attr "type"  "branch")
9545    (set_attr "atype" "agen")])
9546
9547 (define_expand "casesi"
9548   [(match_operand:SI 0 "general_operand" "")
9549    (match_operand:SI 1 "general_operand" "")
9550    (match_operand:SI 2 "general_operand" "")
9551    (label_ref (match_operand 3 "" ""))
9552    (label_ref (match_operand 4 "" ""))]
9553   ""
9554 {
9555    rtx index  = gen_reg_rtx (SImode);
9556    rtx base   = gen_reg_rtx (Pmode);
9557    rtx target = gen_reg_rtx (Pmode);
9558
9559    emit_move_insn (index, operands[0]);
9560    emit_insn (gen_subsi3 (index, index, operands[1]));
9561    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9562                             operands[4]);
9563
9564    if (Pmode != SImode)
9565      index = convert_to_mode (Pmode, index, 1);
9566    if (GET_CODE (index) != REG)
9567      index = copy_to_mode_reg (Pmode, index);
9568
9569    if (TARGET_64BIT)
9570        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9571    else
9572        emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9573
9574    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9575
9576    index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9577    emit_move_insn (target, index);
9578
9579    if (flag_pic)
9580      target = gen_rtx_PLUS (Pmode, base, target);
9581    emit_jump_insn (gen_casesi_jump (target, operands[3]));
9582
9583    DONE;
9584 })
9585
9586
9587 ;;
9588 ;;- Jump to subroutine.
9589 ;;
9590 ;;
9591
9592 ;
9593 ; untyped call instruction pattern(s).
9594 ;
9595
9596 ;; Call subroutine returning any type.
9597 (define_expand "untyped_call"
9598   [(parallel [(call (match_operand 0 "" "")
9599                     (const_int 0))
9600               (match_operand 1 "" "")
9601               (match_operand 2 "" "")])]
9602   ""
9603 {
9604   int i;
9605
9606   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9607
9608   for (i = 0; i < XVECLEN (operands[2], 0); i++)
9609     {
9610       rtx set = XVECEXP (operands[2], 0, i);
9611       emit_move_insn (SET_DEST (set), SET_SRC (set));
9612     }
9613
9614   /* The optimizer does not know that the call sets the function value
9615      registers we stored in the result block.  We avoid problems by
9616      claiming that all hard registers are used and clobbered at this
9617      point.  */
9618   emit_insn (gen_blockage ());
9619
9620   DONE;
9621 })
9622
9623 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9624 ;; all of memory.  This blocks insns from being moved across this point.
9625
9626 (define_insn "blockage"
9627   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9628   ""
9629   ""
9630   [(set_attr "type"    "none")
9631    (set_attr "length"  "0")])
9632
9633 ;
9634 ; sibcall patterns
9635 ;
9636
9637 (define_expand "sibcall"
9638   [(call (match_operand 0 "" "")
9639          (match_operand 1 "" ""))]
9640   ""
9641 {
9642   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9643   DONE;
9644 })
9645
9646 (define_insn "*sibcall_br"
9647   [(call (mem:QI (reg SIBCALL_REGNUM))
9648          (match_operand 0 "const_int_operand" "n"))]
9649   "SIBLING_CALL_P (insn)
9650    && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9651   "br\t%%r1"
9652   [(set_attr "op_type" "RR")
9653    (set_attr "type"  "branch")
9654    (set_attr "atype" "agen")])
9655
9656 (define_insn "*sibcall_brc"
9657   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9658          (match_operand 1 "const_int_operand" "n"))]
9659   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9660   "j\t%0"
9661   [(set_attr "op_type" "RI")
9662    (set_attr "type"    "branch")])
9663
9664 (define_insn "*sibcall_brcl"
9665   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9666          (match_operand 1 "const_int_operand" "n"))]
9667   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9668   "jg\t%0"
9669   [(set_attr "op_type" "RIL")
9670    (set_attr "type"    "branch")])
9671
9672 ;
9673 ; sibcall_value patterns
9674 ;
9675
9676 (define_expand "sibcall_value"
9677   [(set (match_operand 0 "" "")
9678         (call (match_operand 1 "" "")
9679               (match_operand 2 "" "")))]
9680   ""
9681 {
9682   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9683   DONE;
9684 })
9685
9686 (define_insn "*sibcall_value_br"
9687   [(set (match_operand 0 "" "")
9688         (call (mem:QI (reg SIBCALL_REGNUM))
9689               (match_operand 1 "const_int_operand" "n")))]
9690   "SIBLING_CALL_P (insn)
9691    && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9692   "br\t%%r1"
9693   [(set_attr "op_type" "RR")
9694    (set_attr "type"  "branch")
9695    (set_attr "atype" "agen")])
9696
9697 (define_insn "*sibcall_value_brc"
9698   [(set (match_operand 0 "" "")
9699         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9700               (match_operand 2 "const_int_operand" "n")))]
9701   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9702   "j\t%1"
9703   [(set_attr "op_type" "RI")
9704    (set_attr "type"    "branch")])
9705
9706 (define_insn "*sibcall_value_brcl"
9707   [(set (match_operand 0 "" "")
9708         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9709               (match_operand 2 "const_int_operand" "n")))]
9710   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9711   "jg\t%1"
9712   [(set_attr "op_type" "RIL")
9713    (set_attr "type"    "branch")])
9714
9715
9716 ;
9717 ; call instruction pattern(s).
9718 ;
9719
9720 (define_expand "call"
9721   [(call (match_operand 0 "" "")
9722          (match_operand 1 "" ""))
9723    (use (match_operand 2 "" ""))]
9724   ""
9725 {
9726   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9727                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9728   DONE;
9729 })
9730
9731 (define_insn "*bras"
9732   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9733          (match_operand 1 "const_int_operand" "n"))
9734    (clobber (match_operand 2 "register_operand" "=r"))]
9735   "!SIBLING_CALL_P (insn)
9736    && TARGET_SMALL_EXEC
9737    && GET_MODE (operands[2]) == Pmode"
9738   "bras\t%2,%0"
9739   [(set_attr "op_type" "RI")
9740    (set_attr "type"    "jsr")
9741    (set_attr "z196prop" "z196_cracked")])
9742
9743 (define_insn "*brasl"
9744   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9745          (match_operand 1 "const_int_operand" "n"))
9746    (clobber (match_operand 2 "register_operand" "=r"))]
9747   "!SIBLING_CALL_P (insn)
9748    && TARGET_CPU_ZARCH
9749    && GET_MODE (operands[2]) == Pmode"
9750   "brasl\t%2,%0"
9751   [(set_attr "op_type" "RIL")
9752    (set_attr "type"    "jsr")
9753    (set_attr "z196prop" "z196_cracked")])
9754
9755 (define_insn "*basr"
9756   [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
9757          (match_operand 1 "const_int_operand" "n"))
9758    (clobber (match_operand 2 "register_operand" "=r"))]
9759   "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9760 {
9761   if (get_attr_op_type (insn) == OP_TYPE_RR)
9762     return "basr\t%2,%0";
9763   else
9764     return "bas\t%2,%a0";
9765 }
9766   [(set (attr "op_type")
9767         (if_then_else (match_operand 0 "register_operand" "")
9768                       (const_string "RR") (const_string "RX")))
9769    (set_attr "type"  "jsr")
9770    (set_attr "atype" "agen")
9771    (set_attr "z196prop" "z196_cracked")])
9772
9773 ;
9774 ; call_value instruction pattern(s).
9775 ;
9776
9777 (define_expand "call_value"
9778   [(set (match_operand 0 "" "")
9779         (call (match_operand 1 "" "")
9780               (match_operand 2 "" "")))
9781    (use (match_operand 3 "" ""))]
9782   ""
9783 {
9784   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9785                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9786   DONE;
9787 })
9788
9789 (define_insn "*bras_r"
9790   [(set (match_operand 0 "" "")
9791         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9792               (match_operand:SI 2 "const_int_operand" "n")))
9793    (clobber (match_operand 3 "register_operand" "=r"))]
9794   "!SIBLING_CALL_P (insn)
9795    && TARGET_SMALL_EXEC
9796    && GET_MODE (operands[3]) == Pmode"
9797   "bras\t%3,%1"
9798   [(set_attr "op_type" "RI")
9799    (set_attr "type"    "jsr")
9800    (set_attr "z196prop" "z196_cracked")])
9801
9802 (define_insn "*brasl_r"
9803   [(set (match_operand 0 "" "")
9804         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9805               (match_operand 2 "const_int_operand" "n")))
9806    (clobber (match_operand 3 "register_operand" "=r"))]
9807   "!SIBLING_CALL_P (insn)
9808    && TARGET_CPU_ZARCH
9809    && GET_MODE (operands[3]) == Pmode"
9810   "brasl\t%3,%1"
9811   [(set_attr "op_type" "RIL")
9812    (set_attr "type"    "jsr")
9813    (set_attr "z196prop" "z196_cracked")])
9814
9815 (define_insn "*basr_r"
9816   [(set (match_operand 0 "" "")
9817         (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9818               (match_operand 2 "const_int_operand" "n")))
9819    (clobber (match_operand 3 "register_operand" "=r"))]
9820   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9821 {
9822   if (get_attr_op_type (insn) == OP_TYPE_RR)
9823     return "basr\t%3,%1";
9824   else
9825     return "bas\t%3,%a1";
9826 }
9827   [(set (attr "op_type")
9828         (if_then_else (match_operand 1 "register_operand" "")
9829                       (const_string "RR") (const_string "RX")))
9830    (set_attr "type"  "jsr")
9831    (set_attr "atype" "agen")
9832    (set_attr "z196prop" "z196_cracked")])
9833
9834 ;;
9835 ;;- Thread-local storage support.
9836 ;;
9837
9838 (define_expand "get_thread_pointer<mode>"
9839   [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9840   ""
9841   "")
9842
9843 (define_expand "set_thread_pointer<mode>"
9844   [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9845    (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9846   ""
9847   "")
9848
9849 (define_insn "*set_tp"
9850   [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9851   ""
9852   ""
9853   [(set_attr "type" "none")
9854    (set_attr "length" "0")])
9855
9856 (define_insn "*tls_load_64"
9857   [(set (match_operand:DI 0 "register_operand" "=d")
9858         (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
9859                     (match_operand:DI 2 "" "")]
9860                    UNSPEC_TLS_LOAD))]
9861   "TARGET_64BIT"
9862   "lg\t%0,%1%J2"
9863   [(set_attr "op_type" "RXE")
9864    (set_attr "z10prop" "z10_fwd_A3")])
9865
9866 (define_insn "*tls_load_31"
9867   [(set (match_operand:SI 0 "register_operand" "=d,d")
9868         (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9869                     (match_operand:SI 2 "" "")]
9870                    UNSPEC_TLS_LOAD))]
9871   "!TARGET_64BIT"
9872   "@
9873    l\t%0,%1%J2
9874    ly\t%0,%1%J2"
9875   [(set_attr "op_type" "RX,RXY")
9876    (set_attr "type" "load")
9877    (set_attr "cpu_facility" "*,longdisp")
9878    (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9879
9880 (define_insn "*bras_tls"
9881   [(set (match_operand 0 "" "")
9882         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9883               (match_operand 2 "const_int_operand" "n")))
9884    (clobber (match_operand 3 "register_operand" "=r"))
9885    (use (match_operand 4 "" ""))]
9886   "!SIBLING_CALL_P (insn)
9887    && TARGET_SMALL_EXEC
9888    && GET_MODE (operands[3]) == Pmode"
9889   "bras\t%3,%1%J4"
9890   [(set_attr "op_type" "RI")
9891    (set_attr "type"    "jsr")
9892    (set_attr "z196prop" "z196_cracked")])
9893
9894 (define_insn "*brasl_tls"
9895   [(set (match_operand 0 "" "")
9896         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9897               (match_operand 2 "const_int_operand" "n")))
9898    (clobber (match_operand 3 "register_operand" "=r"))
9899    (use (match_operand 4 "" ""))]
9900   "!SIBLING_CALL_P (insn)
9901    && TARGET_CPU_ZARCH
9902    && GET_MODE (operands[3]) == Pmode"
9903   "brasl\t%3,%1%J4"
9904   [(set_attr "op_type" "RIL")
9905    (set_attr "type"    "jsr")
9906    (set_attr "z196prop" "z196_cracked")])
9907
9908 (define_insn "*basr_tls"
9909   [(set (match_operand 0 "" "")
9910         (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9911               (match_operand 2 "const_int_operand" "n")))
9912    (clobber (match_operand 3 "register_operand" "=r"))
9913    (use (match_operand 4 "" ""))]
9914   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9915 {
9916   if (get_attr_op_type (insn) == OP_TYPE_RR)
9917     return "basr\t%3,%1%J4";
9918   else
9919     return "bas\t%3,%a1%J4";
9920 }
9921   [(set (attr "op_type")
9922         (if_then_else (match_operand 1 "register_operand" "")
9923                       (const_string "RR") (const_string "RX")))
9924    (set_attr "type"  "jsr")
9925    (set_attr "atype" "agen")
9926    (set_attr "z196prop" "z196_cracked")])
9927
9928 ;;
9929 ;;- Atomic operations
9930 ;;
9931
9932 ;
9933 ; memory barrier patterns.
9934 ;
9935
9936 (define_expand "mem_signal_fence"
9937   [(match_operand:SI 0 "const_int_operand")]            ;; model
9938   ""
9939 {
9940   /* The s390 memory model is strong enough not to require any
9941      barrier in order to synchronize a thread with itself.  */
9942   DONE;
9943 })
9944
9945 (define_expand "mem_thread_fence"
9946   [(match_operand:SI 0 "const_int_operand")]            ;; model
9947   ""
9948 {
9949   /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9950      enough not to require barriers of any kind.  */
9951   if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9952     {
9953       rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9954       MEM_VOLATILE_P (mem) = 1;
9955       emit_insn (gen_mem_thread_fence_1 (mem));
9956     }
9957   DONE;
9958 })
9959
9960 ; Although bcr is superscalar on Z10, this variant will never
9961 ; become part of an execution group.
9962 ; With z196 we can make use of the fast-BCR-serialization facility.
9963 ; This allows for a slightly faster sync which is sufficient for our
9964 ; purposes.
9965 (define_insn "mem_thread_fence_1"
9966   [(set (match_operand:BLK 0 "" "")
9967         (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9968   ""
9969 {
9970   if (TARGET_Z196)
9971     return "bcr\t14,0";
9972   else
9973     return "bcr\t15,0";
9974 }
9975   [(set_attr "op_type" "RR")
9976    (set_attr "mnemonic" "bcr_flush")
9977    (set_attr "z196prop" "z196_alone")])
9978
9979 ;
9980 ; atomic load/store operations
9981 ;
9982
9983 ; Atomic loads need not examine the memory model at all.
9984 (define_expand "atomic_load<mode>"
9985   [(match_operand:DINT 0 "register_operand")    ;; output
9986    (match_operand:DINT 1 "memory_operand")      ;; memory
9987    (match_operand:SI 2 "const_int_operand")]    ;; model
9988   ""
9989 {
9990   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9991     FAIL;
9992
9993   if (<MODE>mode == TImode)
9994     emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9995   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9996     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9997   else
9998     emit_move_insn (operands[0], operands[1]);
9999   DONE;
10000 })
10001
10002 ; Different from movdi_31 in that we want no splitters.
10003 (define_insn "atomic_loaddi_1"
10004   [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
10005         (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
10006                    UNSPEC_MOVA))]
10007   "!TARGET_ZARCH"
10008   "@
10009    lm\t%0,%M0,%S1
10010    lmy\t%0,%M0,%S1
10011    ld\t%0,%1
10012    ldy\t%0,%1"
10013   [(set_attr "op_type" "RS,RSY,RS,RSY")
10014    (set_attr "cpu_facility" "*,longdisp,*,longdisp")
10015    (set_attr "type" "lm,lm,floaddf,floaddf")])
10016
10017 (define_insn "atomic_loadti_1"
10018   [(set (match_operand:TI 0 "register_operand" "=r")
10019         (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
10020                    UNSPEC_MOVA))]
10021   "TARGET_ZARCH"
10022   "lpq\t%0,%1"
10023   [(set_attr "op_type" "RXY")
10024    (set_attr "type" "other")])
10025
10026 ; Atomic stores must(?) enforce sequential consistency.
10027 (define_expand "atomic_store<mode>"
10028   [(match_operand:DINT 0 "memory_operand")      ;; memory
10029    (match_operand:DINT 1 "register_operand")    ;; input
10030    (match_operand:SI 2 "const_int_operand")]    ;; model
10031   ""
10032 {
10033   enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
10034
10035   if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
10036     FAIL;
10037
10038   if (<MODE>mode == TImode)
10039     emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
10040   else if (<MODE>mode == DImode && !TARGET_ZARCH)
10041     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
10042   else
10043     emit_move_insn (operands[0], operands[1]);
10044   if (is_mm_seq_cst (model))
10045     emit_insn (gen_mem_thread_fence (operands[2]));
10046   DONE;
10047 })
10048
10049 ; Different from movdi_31 in that we want no splitters.
10050 (define_insn "atomic_storedi_1"
10051   [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
10052         (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
10053                    UNSPEC_MOVA))]
10054   "!TARGET_ZARCH"
10055   "@
10056    stm\t%1,%N1,%S0
10057    stmy\t%1,%N1,%S0
10058    std %1,%0
10059    stdy %1,%0"
10060   [(set_attr "op_type" "RS,RSY,RS,RSY")
10061    (set_attr "cpu_facility" "*,longdisp,*,longdisp")
10062    (set_attr "type" "stm,stm,fstoredf,fstoredf")])
10063
10064 (define_insn "atomic_storeti_1"
10065   [(set (match_operand:TI 0 "memory_operand" "=T")
10066         (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
10067                    UNSPEC_MOVA))]
10068   "TARGET_ZARCH"
10069   "stpq\t%1,%0"
10070   [(set_attr "op_type" "RXY")
10071    (set_attr "type" "other")])
10072
10073 ;
10074 ; compare and swap patterns.
10075 ;
10076
10077 (define_expand "atomic_compare_and_swap<mode>"
10078   [(match_operand:SI 0 "register_operand")      ;; bool success output
10079    (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
10080    (match_operand:DGPR 2 "memory_operand")      ;; memory
10081    (match_operand:DGPR 3 "register_operand")    ;; expected intput
10082    (match_operand:DGPR 4 "register_operand")    ;; newval intput
10083    (match_operand:SI 5 "const_int_operand")     ;; is_weak
10084    (match_operand:SI 6 "const_int_operand")     ;; success model
10085    (match_operand:SI 7 "const_int_operand")]    ;; failure model
10086   ""
10087 {
10088   rtx cc, cmp, output = operands[1];
10089
10090   if (!register_operand (output, <MODE>mode))
10091     output = gen_reg_rtx (<MODE>mode);
10092
10093   if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
10094     FAIL;
10095
10096   emit_insn (gen_atomic_compare_and_swap<mode>_internal
10097              (output, operands[2], operands[3], operands[4]));
10098
10099   /* We deliberately accept non-register operands in the predicate
10100      to ensure the write back to the output operand happens *before*
10101      the store-flags code below.  This makes it easier for combine
10102      to merge the store-flags code with a potential test-and-branch
10103      pattern following (immediately!) afterwards.  */
10104   if (output != operands[1])
10105     emit_move_insn (operands[1], output);
10106
10107   cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
10108   cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
10109   emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
10110   DONE;
10111 })
10112
10113 (define_expand "atomic_compare_and_swap<mode>"
10114   [(match_operand:SI 0 "register_operand")      ;; bool success output
10115    (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
10116    (match_operand:HQI 2 "memory_operand")       ;; memory
10117    (match_operand:HQI 3 "general_operand")      ;; expected intput
10118    (match_operand:HQI 4 "general_operand")      ;; newval intput
10119    (match_operand:SI 5 "const_int_operand")     ;; is_weak
10120    (match_operand:SI 6 "const_int_operand")     ;; success model
10121    (match_operand:SI 7 "const_int_operand")]    ;; failure model
10122   ""
10123 {
10124   s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
10125                       operands[3], operands[4], INTVAL (operands[5]));
10126   DONE;
10127 })
10128
10129 (define_expand "atomic_compare_and_swap<mode>_internal"
10130   [(parallel
10131      [(set (match_operand:DGPR 0 "register_operand")
10132            (match_operand:DGPR 1 "memory_operand"))
10133       (set (match_dup 1)
10134            (unspec_volatile:DGPR
10135              [(match_dup 1)
10136               (match_operand:DGPR 2 "register_operand")
10137               (match_operand:DGPR 3 "register_operand")]
10138              UNSPECV_CAS))
10139       (set (reg:CCZ1 CC_REGNUM)
10140            (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
10141   "")
10142
10143 ; cdsg, csg
10144 (define_insn "*atomic_compare_and_swap<mode>_1"
10145   [(set (match_operand:TDI 0 "register_operand" "=r")
10146         (match_operand:TDI 1 "memory_operand" "+S"))
10147    (set (match_dup 1)
10148         (unspec_volatile:TDI
10149           [(match_dup 1)
10150            (match_operand:TDI 2 "register_operand" "0")
10151            (match_operand:TDI 3 "register_operand" "r")]
10152           UNSPECV_CAS))
10153    (set (reg:CCZ1 CC_REGNUM)
10154         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10155   "TARGET_ZARCH"
10156   "c<td>sg\t%0,%3,%S1"
10157   [(set_attr "op_type" "RSY")
10158    (set_attr "type"   "sem")])
10159
10160 ; cds, cdsy
10161 (define_insn "*atomic_compare_and_swapdi_2"
10162   [(set (match_operand:DI 0 "register_operand" "=r,r")
10163         (match_operand:DI 1 "memory_operand" "+Q,S"))
10164    (set (match_dup 1)
10165         (unspec_volatile:DI
10166           [(match_dup 1)
10167            (match_operand:DI 2 "register_operand" "0,0")
10168            (match_operand:DI 3 "register_operand" "r,r")]
10169           UNSPECV_CAS))
10170    (set (reg:CCZ1 CC_REGNUM)
10171         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10172   "!TARGET_ZARCH"
10173   "@
10174    cds\t%0,%3,%S1
10175    cdsy\t%0,%3,%S1"
10176   [(set_attr "op_type" "RS,RSY")
10177    (set_attr "cpu_facility" "*,longdisp")
10178    (set_attr "type" "sem")])
10179
10180 ; cs, csy
10181 (define_insn "*atomic_compare_and_swapsi_3"
10182   [(set (match_operand:SI 0 "register_operand" "=r,r")
10183         (match_operand:SI 1 "memory_operand" "+Q,S"))
10184    (set (match_dup 1)
10185         (unspec_volatile:SI
10186           [(match_dup 1)
10187            (match_operand:SI 2 "register_operand" "0,0")
10188            (match_operand:SI 3 "register_operand" "r,r")]
10189           UNSPECV_CAS))
10190    (set (reg:CCZ1 CC_REGNUM)
10191         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10192   ""
10193   "@
10194    cs\t%0,%3,%S1
10195    csy\t%0,%3,%S1"
10196   [(set_attr "op_type" "RS,RSY")
10197    (set_attr "cpu_facility" "*,longdisp")
10198    (set_attr "type"   "sem")])
10199
10200 ;
10201 ; Other atomic instruction patterns.
10202 ;
10203
10204 ; z196 load and add, xor, or and and instructions
10205
10206 (define_expand "atomic_fetch_<atomic><mode>"
10207   [(match_operand:GPR 0 "register_operand")             ;; val out
10208    (ATOMIC_Z196:GPR
10209      (match_operand:GPR 1 "memory_operand")             ;; memory
10210      (match_operand:GPR 2 "register_operand"))          ;; val in
10211    (match_operand:SI 3 "const_int_operand")]            ;; model
10212   "TARGET_Z196"
10213 {
10214   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
10215     FAIL;
10216
10217   emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
10218              (operands[0], operands[1], operands[2]));
10219   DONE;
10220 })
10221
10222 ; lan, lang, lao, laog, lax, laxg, laa, laag
10223 (define_insn "atomic_fetch_<atomic><mode>_iaf"
10224   [(set (match_operand:GPR 0 "register_operand" "=d")
10225         (match_operand:GPR 1 "memory_operand" "+S"))
10226    (set (match_dup 1)
10227         (unspec_volatile:GPR
10228          [(ATOMIC_Z196:GPR (match_dup 1)
10229                            (match_operand:GPR 2 "general_operand" "d"))]
10230          UNSPECV_ATOMIC_OP))
10231    (clobber (reg:CC CC_REGNUM))]
10232   "TARGET_Z196"
10233   "la<noxa><g>\t%0,%2,%1"
10234   [(set_attr "op_type" "RSY")
10235    (set_attr "type" "sem")])
10236
10237 ;; For SImode and larger, the optabs.c code will do just fine in
10238 ;; expanding a compare-and-swap loop.  For QI/HImode, we can do
10239 ;; better by expanding our own loop.
10240
10241 (define_expand "atomic_<atomic><mode>"
10242   [(ATOMIC:HQI
10243      (match_operand:HQI 0 "memory_operand")             ;; memory
10244      (match_operand:HQI 1 "general_operand"))           ;; val in
10245    (match_operand:SI 2 "const_int_operand")]            ;; model
10246   ""
10247 {
10248   s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10249                        operands[1], false);
10250   DONE;
10251 })
10252
10253 (define_expand "atomic_fetch_<atomic><mode>"
10254   [(match_operand:HQI 0 "register_operand")             ;; val out
10255    (ATOMIC:HQI
10256      (match_operand:HQI 1 "memory_operand")             ;; memory
10257      (match_operand:HQI 2 "general_operand"))           ;; val in
10258    (match_operand:SI 3 "const_int_operand")]            ;; model
10259   ""
10260 {
10261   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10262                       operands[2], false);
10263   DONE;
10264 })
10265
10266 (define_expand "atomic_<atomic>_fetch<mode>"
10267   [(match_operand:HQI 0 "register_operand")             ;; val out
10268    (ATOMIC:HQI
10269      (match_operand:HQI 1 "memory_operand")             ;; memory
10270      (match_operand:HQI 2 "general_operand"))           ;; val in
10271    (match_operand:SI 3 "const_int_operand")]            ;; model
10272   ""
10273 {
10274   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10275                       operands[2], true);
10276   DONE;
10277 })
10278
10279 (define_expand "atomic_exchange<mode>"
10280   [(match_operand:HQI 0 "register_operand")             ;; val out
10281    (match_operand:HQI 1 "memory_operand")               ;; memory
10282    (match_operand:HQI 2 "general_operand")              ;; val in
10283    (match_operand:SI 3 "const_int_operand")]            ;; model
10284   ""
10285 {
10286   s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10287                       operands[2], false);
10288   DONE;
10289 })
10290
10291 ;;
10292 ;;- Miscellaneous instructions.
10293 ;;
10294
10295 ;
10296 ; allocate stack instruction pattern(s).
10297 ;
10298
10299 (define_expand "allocate_stack"
10300   [(match_operand 0 "general_operand" "")
10301    (match_operand 1 "general_operand" "")]
10302  "TARGET_BACKCHAIN"
10303 {
10304   rtx temp = gen_reg_rtx (Pmode);
10305
10306   emit_move_insn (temp, s390_back_chain_rtx ());
10307   anti_adjust_stack (operands[1]);
10308   emit_move_insn (s390_back_chain_rtx (), temp);
10309
10310   emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10311   DONE;
10312 })
10313
10314
10315 ;
10316 ; setjmp instruction pattern.
10317 ;
10318
10319 (define_expand "builtin_setjmp_receiver"
10320   [(match_operand 0 "" "")]
10321   "flag_pic"
10322 {
10323   emit_insn (s390_load_got ());
10324   emit_use (pic_offset_table_rtx);
10325   DONE;
10326 })
10327
10328 ;; These patterns say how to save and restore the stack pointer.  We need not
10329 ;; save the stack pointer at function level since we are careful to
10330 ;; preserve the backchain.  At block level, we have to restore the backchain
10331 ;; when we restore the stack pointer.
10332 ;;
10333 ;; For nonlocal gotos, we must save both the stack pointer and its
10334 ;; backchain and restore both.  Note that in the nonlocal case, the
10335 ;; save area is a memory location.
10336
10337 (define_expand "save_stack_function"
10338   [(match_operand 0 "general_operand" "")
10339    (match_operand 1 "general_operand" "")]
10340   ""
10341   "DONE;")
10342
10343 (define_expand "restore_stack_function"
10344   [(match_operand 0 "general_operand" "")
10345    (match_operand 1 "general_operand" "")]
10346   ""
10347   "DONE;")
10348
10349 (define_expand "restore_stack_block"
10350   [(match_operand 0 "register_operand" "")
10351    (match_operand 1 "register_operand" "")]
10352   "TARGET_BACKCHAIN"
10353 {
10354   rtx temp = gen_reg_rtx (Pmode);
10355
10356   emit_move_insn (temp, s390_back_chain_rtx ());
10357   emit_move_insn (operands[0], operands[1]);
10358   emit_move_insn (s390_back_chain_rtx (), temp);
10359
10360   DONE;
10361 })
10362
10363 (define_expand "save_stack_nonlocal"
10364   [(match_operand 0 "memory_operand" "")
10365    (match_operand 1 "register_operand" "")]
10366   ""
10367 {
10368   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10369
10370   /* Copy the backchain to the first word, sp to the second and the
10371      literal pool base to the third.  */
10372
10373   rtx save_bc = adjust_address (operands[0], Pmode, 0);
10374   rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10375   rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10376
10377   if (TARGET_BACKCHAIN)
10378     emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10379
10380   emit_move_insn (save_sp, operands[1]);
10381   emit_move_insn (save_bp, base);
10382
10383   DONE;
10384 })
10385
10386 (define_expand "restore_stack_nonlocal"
10387   [(match_operand 0 "register_operand" "")
10388    (match_operand 1 "memory_operand" "")]
10389   ""
10390 {
10391   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10392   rtx temp = NULL_RTX;
10393
10394   /* Restore the backchain from the first word, sp from the second and the
10395      literal pool base from the third.  */
10396
10397   rtx save_bc = adjust_address (operands[1], Pmode, 0);
10398   rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10399   rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10400
10401   if (TARGET_BACKCHAIN)
10402     temp = force_reg (Pmode, save_bc);
10403
10404   emit_move_insn (base, save_bp);
10405   emit_move_insn (operands[0], save_sp);
10406
10407   if (temp)
10408     emit_move_insn (s390_back_chain_rtx (), temp);
10409
10410   emit_use (base);
10411   DONE;
10412 })
10413
10414 (define_expand "exception_receiver"
10415   [(const_int 0)]
10416   ""
10417 {
10418   s390_set_has_landing_pad_p (true);
10419   DONE;
10420 })
10421
10422 ;
10423 ; nop instruction pattern(s).
10424 ;
10425
10426 (define_insn "nop"
10427   [(const_int 0)]
10428   ""
10429   "lr\t0,0"
10430   [(set_attr "op_type" "RR")
10431    (set_attr "z10prop"  "z10_fr_E1")])
10432
10433 (define_insn "nop1"
10434   [(const_int 1)]
10435   ""
10436   "lr\t1,1"
10437   [(set_attr "op_type" "RR")])
10438
10439 ;;- Undeletable nops (used for hotpatching)
10440
10441 (define_insn "nop_2_byte"
10442   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10443   ""
10444   "nopr\t%%r0"
10445   [(set_attr "op_type" "RR")])
10446
10447 (define_insn "nop_4_byte"
10448   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10449   ""
10450   "nop\t0"
10451   [(set_attr "op_type" "RX")])
10452
10453 (define_insn "nop_6_byte"
10454   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10455   "TARGET_CPU_ZARCH"
10456   "brcl\t0, 0"
10457   [(set_attr "op_type" "RIL")])
10458
10459
10460 ;
10461 ; Special literal pool access instruction pattern(s).
10462 ;
10463
10464 (define_insn "*pool_entry"
10465   [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10466                     UNSPECV_POOL_ENTRY)]
10467   ""
10468 {
10469   machine_mode mode = GET_MODE (PATTERN (insn));
10470   unsigned int align = GET_MODE_BITSIZE (mode);
10471   s390_output_pool_entry (operands[0], mode, align);
10472   return "";
10473 }
10474   [(set (attr "length")
10475         (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10476
10477 (define_insn "pool_align"
10478   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10479                     UNSPECV_POOL_ALIGN)]
10480   ""
10481   ".align\t%0"
10482   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10483
10484 (define_insn "pool_section_start"
10485   [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10486   ""
10487 {
10488   switch_to_section (targetm.asm_out.function_rodata_section
10489                  (current_function_decl));
10490   return "";
10491 }
10492   [(set_attr "length" "0")])
10493
10494 (define_insn "pool_section_end"
10495   [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10496   ""
10497 {
10498   switch_to_section (current_function_section ());
10499   return "";
10500 }
10501   [(set_attr "length" "0")])
10502
10503 (define_insn "main_base_31_small"
10504   [(set (match_operand 0 "register_operand" "=a")
10505         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10506   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10507   "basr\t%0,0"
10508   [(set_attr "op_type" "RR")
10509    (set_attr "type"    "la")
10510    (set_attr "z196prop" "z196_cracked")])
10511
10512 (define_insn "main_base_31_large"
10513   [(set (match_operand 0 "register_operand" "=a")
10514         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10515    (set (pc) (label_ref (match_operand 2 "" "")))]
10516   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10517   "bras\t%0,%2"
10518   [(set_attr "op_type" "RI")
10519    (set_attr "z196prop" "z196_cracked")])
10520
10521 (define_insn "main_base_64"
10522   [(set (match_operand 0 "register_operand" "=a")
10523         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10524   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10525   "larl\t%0,%1"
10526   [(set_attr "op_type" "RIL")
10527    (set_attr "type"    "larl")
10528    (set_attr "z10prop" "z10_fwd_A1")])
10529
10530 (define_insn "main_pool"
10531   [(set (match_operand 0 "register_operand" "=a")
10532         (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10533   "GET_MODE (operands[0]) == Pmode"
10534 {
10535   gcc_unreachable ();
10536 }
10537   [(set (attr "type")
10538         (if_then_else (match_test "TARGET_CPU_ZARCH")
10539                       (const_string "larl") (const_string "la")))])
10540
10541 (define_insn "reload_base_31"
10542   [(set (match_operand 0 "register_operand" "=a")
10543         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10544   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10545   "basr\t%0,0\;la\t%0,%1-.(%0)"
10546   [(set_attr "length" "6")
10547    (set_attr "type" "la")
10548    (set_attr "z196prop" "z196_cracked")])
10549
10550 (define_insn "reload_base_64"
10551   [(set (match_operand 0 "register_operand" "=a")
10552         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10553   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10554   "larl\t%0,%1"
10555   [(set_attr "op_type" "RIL")
10556    (set_attr "type"    "larl")
10557    (set_attr "z10prop" "z10_fwd_A1")])
10558
10559 (define_insn "pool"
10560   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10561   ""
10562 {
10563   gcc_unreachable ();
10564 }
10565   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10566
10567 ;;
10568 ;; Insns related to generating the function prologue and epilogue.
10569 ;;
10570
10571
10572 (define_expand "prologue"
10573   [(use (const_int 0))]
10574   ""
10575   "s390_emit_prologue (); DONE;")
10576
10577 (define_expand "epilogue"
10578   [(use (const_int 1))]
10579   ""
10580   "s390_emit_epilogue (false); DONE;")
10581
10582 (define_expand "sibcall_epilogue"
10583   [(use (const_int 0))]
10584   ""
10585   "s390_emit_epilogue (true); DONE;")
10586
10587 ;; A direct return instruction, without using an epilogue.
10588 (define_insn "<code>"
10589   [(ANY_RETURN)]
10590   "s390_can_use_<code>_insn ()"
10591   "br\t%%r14"
10592   [(set_attr "op_type" "RR")
10593    (set_attr "type"    "jsr")
10594    (set_attr "atype"   "agen")])
10595
10596 (define_insn "*return"
10597   [(return)
10598    (use (match_operand 0 "register_operand" "a"))]
10599   "GET_MODE (operands[0]) == Pmode"
10600   "br\t%0"
10601   [(set_attr "op_type" "RR")
10602    (set_attr "type"    "jsr")
10603    (set_attr "atype"   "agen")])
10604
10605
10606 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10607 ;; pointer. This is used for compatibility.
10608
10609 (define_expand "ptr_extend"
10610   [(set (match_operand:DI 0 "register_operand" "=r")
10611         (match_operand:SI 1 "register_operand" "r"))]
10612   "TARGET_64BIT"
10613 {
10614   emit_insn (gen_anddi3 (operands[0],
10615                          gen_lowpart (DImode, operands[1]),
10616                          GEN_INT (0x7fffffff)));
10617   DONE;
10618 })
10619
10620 ;; Instruction definition to expand eh_return macro to support
10621 ;; swapping in special linkage return addresses.
10622
10623 (define_expand "eh_return"
10624   [(use (match_operand 0 "register_operand" ""))]
10625   "TARGET_TPF"
10626 {
10627   s390_emit_tpf_eh_return (operands[0]);
10628   DONE;
10629 })
10630
10631 ;
10632 ; Stack Protector Patterns
10633 ;
10634
10635 (define_expand "stack_protect_set"
10636   [(set (match_operand 0 "memory_operand" "")
10637         (match_operand 1 "memory_operand" ""))]
10638   ""
10639 {
10640 #ifdef TARGET_THREAD_SSP_OFFSET
10641   operands[1]
10642     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10643                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10644 #endif
10645   if (TARGET_64BIT)
10646     emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10647   else
10648     emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10649
10650   DONE;
10651 })
10652
10653 (define_insn "stack_protect_set<mode>"
10654   [(set (match_operand:DSI 0 "memory_operand" "=Q")
10655         (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10656   ""
10657   "mvc\t%O0(%G0,%R0),%S1"
10658   [(set_attr "op_type" "SS")])
10659
10660 (define_expand "stack_protect_test"
10661   [(set (reg:CC CC_REGNUM)
10662         (compare (match_operand 0 "memory_operand" "")
10663                  (match_operand 1 "memory_operand" "")))
10664    (match_operand 2 "" "")]
10665   ""
10666 {
10667   rtx cc_reg, test;
10668 #ifdef TARGET_THREAD_SSP_OFFSET
10669   operands[1]
10670     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10671                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10672 #endif
10673   if (TARGET_64BIT)
10674     emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10675   else
10676     emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10677
10678   cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10679   test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10680   emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10681   DONE;
10682 })
10683
10684 (define_insn "stack_protect_test<mode>"
10685   [(set (reg:CCZ CC_REGNUM)
10686         (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10687                      (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10688   ""
10689   "clc\t%O0(%G0,%R0),%S1"
10690   [(set_attr "op_type" "SS")])
10691
10692 ; This is used in s390_emit_prologue in order to prevent insns
10693 ; adjusting the stack pointer to be moved over insns writing stack
10694 ; slots using a copy of the stack pointer in a different register.
10695 (define_insn "stack_tie"
10696   [(set (match_operand:BLK 0 "memory_operand" "+m")
10697         (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10698   ""
10699   ""
10700   [(set_attr "length" "0")])
10701
10702
10703 (define_insn "stack_restore_from_fpr"
10704   [(set (reg:DI STACK_REGNUM)
10705         (match_operand:DI 0 "register_operand" "f"))
10706    (clobber (mem:BLK (scratch)))]
10707   "TARGET_Z10"
10708   "lgdr\t%%r15,%0"
10709   [(set_attr "op_type"  "RRE")])
10710
10711 ;
10712 ; Data prefetch patterns
10713 ;
10714
10715 (define_insn "prefetch"
10716   [(prefetch (match_operand 0    "address_operand"   "ZT,X")
10717              (match_operand:SI 1 "const_int_operand" " n,n")
10718              (match_operand:SI 2 "const_int_operand" " n,n"))]
10719   "TARGET_Z10"
10720 {
10721   switch (which_alternative)
10722     {
10723       case 0:
10724         return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10725       case 1:
10726         if (larl_operand (operands[0], Pmode))
10727           return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10728           /* fallthrough */
10729       default:
10730
10731         /* This might be reached for symbolic operands with an odd
10732            addend.  We simply omit the prefetch for such rare cases.  */
10733
10734         return "";
10735      }
10736 }
10737   [(set_attr "type" "load,larl")
10738    (set_attr "op_type" "RXY,RIL")
10739    (set_attr "z10prop" "z10_super")
10740    (set_attr "z196prop" "z196_alone")])
10741
10742
10743 ;
10744 ; Byte swap instructions
10745 ;
10746
10747 ; FIXME: There is also mvcin but we cannot use it since src and target
10748 ; may overlap.
10749 ; lrvr, lrv, strv, lrvgr, lrvg, strvg
10750 (define_insn "bswap<mode>2"
10751   [(set (match_operand:GPR 0            "nonimmediate_operand" "=d,d,T")
10752         (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
10753   "TARGET_CPU_ZARCH"
10754   "@
10755    lrv<g>r\t%0,%1
10756    lrv<g>\t%0,%1
10757    strv<g>\t%1,%0"
10758   [(set_attr "type" "*,load,store")
10759    (set_attr "op_type" "RRE,RXY,RXY")
10760    (set_attr "z10prop" "z10_super")])
10761
10762 (define_insn "bswaphi2"
10763   [(set (match_operand:HI 0           "nonimmediate_operand" "=d,d,T")
10764         (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
10765   "TARGET_CPU_ZARCH"
10766   "@
10767    #
10768    lrvh\t%0,%1
10769    strvh\t%1,%0"
10770   [(set_attr "type" "*,load,store")
10771    (set_attr "op_type" "RRE,RXY,RXY")
10772    (set_attr "z10prop" "z10_super")])
10773
10774 (define_split
10775   [(set (match_operand:HI 0           "register_operand" "")
10776         (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10777   "TARGET_CPU_ZARCH"
10778   [(set (match_dup 2) (bswap:SI (match_dup 3)))
10779    (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10780 {
10781   operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10782   operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10783 })
10784
10785
10786 ;
10787 ; Population count instruction
10788 ;
10789
10790 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10791 ; portions and stores the result in the corresponding bytes in op0.
10792 (define_insn "*popcount<mode>"
10793   [(set (match_operand:INT 0 "register_operand" "=d")
10794         (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10795    (clobber (reg:CC CC_REGNUM))]
10796   "TARGET_Z196"
10797   "popcnt\t%0,%1"
10798   [(set_attr "op_type" "RRE")])
10799
10800 (define_expand "popcountdi2"
10801   [; popcnt op0, op1
10802    (parallel [(set (match_operand:DI 0 "register_operand" "")
10803                    (unspec:DI [(match_operand:DI 1 "register_operand")]
10804                               UNSPEC_POPCNT))
10805               (clobber (reg:CC CC_REGNUM))])
10806    ; sllg op2, op0, 32
10807    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10808    ; agr op0, op2
10809    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10810               (clobber (reg:CC CC_REGNUM))])
10811    ; sllg op2, op0, 16
10812    (set (match_dup 2)
10813         (ashift:DI (match_dup 0) (const_int 16)))
10814    ; agr op0, op2
10815    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10816               (clobber (reg:CC CC_REGNUM))])
10817    ; sllg op2, op0, 8
10818    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10819    ; agr op0, op2
10820    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10821               (clobber (reg:CC CC_REGNUM))])
10822    ; srlg op0, op0, 56
10823    (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10824   "TARGET_Z196 && TARGET_64BIT"
10825   "operands[2] = gen_reg_rtx (DImode);")
10826
10827 (define_expand "popcountsi2"
10828   [; popcnt op0, op1
10829    (parallel [(set (match_operand:SI 0 "register_operand" "")
10830                    (unspec:SI [(match_operand:SI 1 "register_operand")]
10831                               UNSPEC_POPCNT))
10832               (clobber (reg:CC CC_REGNUM))])
10833    ; sllk op2, op0, 16
10834    (set (match_dup 2)
10835         (ashift:SI (match_dup 0) (const_int 16)))
10836    ; ar op0, op2
10837    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10838               (clobber (reg:CC CC_REGNUM))])
10839    ; sllk op2, op0, 8
10840    (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10841    ; ar op0, op2
10842    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10843               (clobber (reg:CC CC_REGNUM))])
10844    ; srl op0, op0, 24
10845    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10846   "TARGET_Z196"
10847   "operands[2] = gen_reg_rtx (SImode);")
10848
10849 (define_expand "popcounthi2"
10850   [; popcnt op0, op1
10851    (parallel [(set (match_operand:HI 0 "register_operand" "")
10852                    (unspec:HI [(match_operand:HI 1 "register_operand")]
10853                               UNSPEC_POPCNT))
10854               (clobber (reg:CC CC_REGNUM))])
10855    ; sllk op2, op0, 8
10856    (set (match_dup 2)
10857         (ashift:SI (match_dup 0) (const_int 8)))
10858    ; ar op0, op2
10859    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10860               (clobber (reg:CC CC_REGNUM))])
10861    ; srl op0, op0, 8
10862    (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10863   "TARGET_Z196"
10864   "operands[2] = gen_reg_rtx (SImode);")
10865
10866 (define_expand "popcountqi2"
10867   [; popcnt op0, op1
10868    (parallel [(set (match_operand:QI 0 "register_operand" "")
10869                    (unspec:QI [(match_operand:QI 1 "register_operand")]
10870                               UNSPEC_POPCNT))
10871               (clobber (reg:CC CC_REGNUM))])]
10872   "TARGET_Z196"
10873   "")
10874
10875 ;;
10876 ;;- Copy sign instructions
10877 ;;
10878
10879 (define_insn "copysign<mode>3"
10880   [(set (match_operand:FP 0 "register_operand" "=f")
10881       (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10882                   (match_operand:FP 2 "register_operand" "f")]
10883                   UNSPEC_COPYSIGN))]
10884   "TARGET_Z196"
10885   "cpsdr\t%0,%2,%1"
10886   [(set_attr "op_type"  "RRF")
10887    (set_attr "type"     "fsimp<mode>")])
10888
10889
10890 ;;
10891 ;;- Transactional execution instructions
10892 ;;
10893
10894 ; This splitter helps combine to make use of CC directly when
10895 ; comparing the integer result of a tbegin builtin with a constant.
10896 ; The unspec is already removed by canonicalize_comparison. So this
10897 ; splitters only job is to turn the PARALLEL into separate insns
10898 ; again.  Unfortunately this only works with the very first cc/int
10899 ; compare since combine is not able to deal with data flow across
10900 ; basic block boundaries.
10901
10902 ; It needs to be an insn pattern as well since combine does not apply
10903 ; the splitter directly.  Combine would only use it if it actually
10904 ; would reduce the number of instructions.
10905 (define_insn_and_split "*ccraw_to_int"
10906   [(set (pc)
10907         (if_then_else
10908          (match_operator 0 "s390_eqne_operator"
10909                          [(reg:CCRAW CC_REGNUM)
10910                           (match_operand 1 "const_int_operand" "")])
10911          (label_ref (match_operand 2 "" ""))
10912          (pc)))
10913    (set (match_operand:SI 3 "register_operand" "=d")
10914         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10915   ""
10916   "#"
10917   ""
10918   [(set (match_dup 3)
10919         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10920    (set (pc)
10921         (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10922                       (label_ref (match_dup 2))
10923                       (pc)))]
10924   "")
10925
10926 ; Non-constrained transaction begin
10927
10928 (define_expand "tbegin"
10929   [(match_operand:SI 0 "register_operand" "")
10930    (match_operand:BLK 1 "memory_operand" "")]
10931   "TARGET_HTM"
10932 {
10933   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10934   DONE;
10935 })
10936
10937 (define_expand "tbegin_nofloat"
10938   [(match_operand:SI 0 "register_operand" "")
10939    (match_operand:BLK 1 "memory_operand" "")]
10940   "TARGET_HTM"
10941 {
10942   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10943   DONE;
10944 })
10945
10946 (define_expand "tbegin_retry"
10947   [(match_operand:SI 0 "register_operand" "")
10948    (match_operand:BLK 1 "memory_operand" "")
10949    (match_operand:SI 2 "general_operand" "")]
10950   "TARGET_HTM"
10951 {
10952   s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10953   DONE;
10954 })
10955
10956 (define_expand "tbegin_retry_nofloat"
10957   [(match_operand:SI 0 "register_operand" "")
10958    (match_operand:BLK 1 "memory_operand" "")
10959    (match_operand:SI 2 "general_operand" "")]
10960   "TARGET_HTM"
10961 {
10962   s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10963   DONE;
10964 })
10965
10966 ; Clobber VRs since they don't get restored
10967 (define_insn "tbegin_1_z13"
10968   [(set (reg:CCRAW CC_REGNUM)
10969         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10970                                UNSPECV_TBEGIN))
10971    (set (match_operand:BLK 1 "memory_operand" "=Q")
10972         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10973    (clobber (reg:TI 16)) (clobber (reg:TI 38))
10974    (clobber (reg:TI 17)) (clobber (reg:TI 39))
10975    (clobber (reg:TI 18)) (clobber (reg:TI 40))
10976    (clobber (reg:TI 19)) (clobber (reg:TI 41))
10977    (clobber (reg:TI 20)) (clobber (reg:TI 42))
10978    (clobber (reg:TI 21)) (clobber (reg:TI 43))
10979    (clobber (reg:TI 22)) (clobber (reg:TI 44))
10980    (clobber (reg:TI 23)) (clobber (reg:TI 45))
10981    (clobber (reg:TI 24)) (clobber (reg:TI 46))
10982    (clobber (reg:TI 25)) (clobber (reg:TI 47))
10983    (clobber (reg:TI 26)) (clobber (reg:TI 48))
10984    (clobber (reg:TI 27)) (clobber (reg:TI 49))
10985    (clobber (reg:TI 28)) (clobber (reg:TI 50))
10986    (clobber (reg:TI 29)) (clobber (reg:TI 51))
10987    (clobber (reg:TI 30)) (clobber (reg:TI 52))
10988    (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10989 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10990 ; not supposed to be used for immediates (see genpreds.c).
10991   "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10992   "tbegin\t%1,%x0"
10993   [(set_attr "op_type" "SIL")])
10994
10995 (define_insn "tbegin_1"
10996   [(set (reg:CCRAW CC_REGNUM)
10997         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10998                                UNSPECV_TBEGIN))
10999    (set (match_operand:BLK 1 "memory_operand" "=Q")
11000         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
11001    (clobber (reg:DF 16))
11002    (clobber (reg:DF 17))
11003    (clobber (reg:DF 18))
11004    (clobber (reg:DF 19))
11005    (clobber (reg:DF 20))
11006    (clobber (reg:DF 21))
11007    (clobber (reg:DF 22))
11008    (clobber (reg:DF 23))
11009    (clobber (reg:DF 24))
11010    (clobber (reg:DF 25))
11011    (clobber (reg:DF 26))
11012    (clobber (reg:DF 27))
11013    (clobber (reg:DF 28))
11014    (clobber (reg:DF 29))
11015    (clobber (reg:DF 30))
11016    (clobber (reg:DF 31))]
11017 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
11018 ; not supposed to be used for immediates (see genpreds.c).
11019   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11020   "tbegin\t%1,%x0"
11021   [(set_attr "op_type" "SIL")])
11022
11023 ; Same as above but without the FPR clobbers
11024 (define_insn "tbegin_nofloat_1"
11025   [(set (reg:CCRAW CC_REGNUM)
11026         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
11027                                UNSPECV_TBEGIN))
11028    (set (match_operand:BLK 1 "memory_operand" "=Q")
11029         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
11030   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11031   "tbegin\t%1,%x0"
11032   [(set_attr "op_type" "SIL")])
11033
11034
11035 ; Constrained transaction begin
11036
11037 (define_expand "tbeginc"
11038   [(set (reg:CCRAW CC_REGNUM)
11039         (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
11040                                UNSPECV_TBEGINC))]
11041   "TARGET_HTM"
11042   "")
11043
11044 (define_insn "*tbeginc_1"
11045   [(set (reg:CCRAW CC_REGNUM)
11046         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
11047                                UNSPECV_TBEGINC))]
11048   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11049   "tbeginc\t0,%x0"
11050   [(set_attr "op_type" "SIL")])
11051
11052 ; Transaction end
11053
11054 (define_expand "tend"
11055   [(set (reg:CCRAW CC_REGNUM)
11056         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
11057    (set (match_operand:SI 0 "register_operand" "")
11058         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
11059   "TARGET_HTM"
11060   "")
11061
11062 (define_insn "*tend_1"
11063   [(set (reg:CCRAW CC_REGNUM)
11064         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
11065   "TARGET_HTM"
11066   "tend"
11067   [(set_attr "op_type" "S")])
11068
11069 ; Transaction abort
11070
11071 (define_expand "tabort"
11072   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
11073                     UNSPECV_TABORT)]
11074   "TARGET_HTM && operands != NULL"
11075 {
11076   if (CONST_INT_P (operands[0])
11077       && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
11078     {
11079       error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
11080              ".  Values in range 0 through 255 are reserved.",
11081              INTVAL (operands[0]));
11082       FAIL;
11083     }
11084 })
11085
11086 (define_insn "*tabort_1"
11087   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
11088                     UNSPECV_TABORT)]
11089   "TARGET_HTM && operands != NULL"
11090   "tabort\t%Y0"
11091   [(set_attr "op_type" "S")])
11092
11093 (define_insn "*tabort_1_plus"
11094   [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand"  "a")
11095                               (match_operand:SI 1 "const_int_operand" "J"))]
11096                     UNSPECV_TABORT)]
11097   "TARGET_HTM && operands != NULL
11098    && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
11099   "tabort\t%1(%0)"
11100   [(set_attr "op_type" "S")])
11101
11102 ; Transaction extract nesting depth
11103
11104 (define_insn "etnd"
11105   [(set (match_operand:SI 0 "register_operand" "=d")
11106         (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
11107   "TARGET_HTM"
11108   "etnd\t%0"
11109   [(set_attr "op_type" "RRE")])
11110
11111 ; Non-transactional store
11112
11113 (define_insn "ntstg"
11114   [(set (match_operand:DI 0 "memory_operand" "=T")
11115         (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
11116                             UNSPECV_NTSTG))]
11117   "TARGET_HTM"
11118   "ntstg\t%1,%0"
11119   [(set_attr "op_type" "RXY")])
11120
11121 ; Transaction perform processor assist
11122
11123 (define_expand "tx_assist"
11124   [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
11125                      (reg:SI GPR0_REGNUM)
11126                      (const_int 1)]
11127                     UNSPECV_PPA)]
11128   "TARGET_HTM"
11129   "")
11130
11131 (define_insn "*ppa"
11132   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
11133                      (match_operand:SI 1 "register_operand" "d")
11134                      (match_operand 2 "const_int_operand" "I")]
11135                     UNSPECV_PPA)]
11136   "TARGET_HTM && INTVAL (operands[2]) < 16"
11137   "ppa\t%0,%1,%2"
11138   [(set_attr "op_type" "RRF")])
11139
11140
11141 ; Set and get floating point control register
11142
11143 (define_insn "sfpc"
11144   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
11145                     UNSPECV_SFPC)]
11146   "TARGET_HARD_FLOAT"
11147   "sfpc\t%0")
11148
11149 (define_insn "efpc"
11150   [(set (match_operand:SI 0 "register_operand" "=d")
11151         (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
11152   "TARGET_HARD_FLOAT"
11153   "efpc\t%0")
11154
11155
11156 ; Load count to block boundary
11157
11158 (define_insn "lcbb"
11159   [(set (match_operand:SI             0 "register_operand"  "=d")
11160         (unspec:SI [(match_operand    1 "address_operand" "ZR")
11161                     (match_operand:SI 2 "immediate_operand"  "C")] UNSPEC_LCBB))
11162    (clobber (reg:CC CC_REGNUM))]
11163   "TARGET_Z13"
11164   "lcbb\t%0,%a1,%b2"
11165   [(set_attr "op_type" "VRX")])
11166
11167 ; Handle -fsplit-stack.
11168
11169 (define_expand "split_stack_prologue"
11170   [(const_int 0)]
11171   ""
11172 {
11173   s390_expand_split_stack_prologue ();
11174   DONE;
11175 })
11176
11177 ;; If there are operand 0 bytes available on the stack, jump to
11178 ;; operand 1.
11179
11180 (define_expand "split_stack_space_check"
11181   [(set (pc) (if_then_else
11182               (ltu (minus (reg 15)
11183                           (match_operand 0 "register_operand"))
11184                    (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
11185               (label_ref (match_operand 1))
11186               (pc)))]
11187   ""
11188 {
11189   /* Offset from thread pointer to __private_ss.  */
11190   int psso = TARGET_64BIT ? 0x38 : 0x20;
11191   rtx tp = s390_get_thread_pointer ();
11192   rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
11193   rtx reg = gen_reg_rtx (Pmode);
11194   rtx cc;
11195   if (TARGET_64BIT)
11196     emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
11197   else
11198     emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
11199   cc = s390_emit_compare (GT, reg, guard);
11200   s390_emit_jump (operands[1], cc);
11201
11202   DONE;
11203 })
11204
11205 ;; __morestack parameter block for split stack prologue.  Parameters are:
11206 ;; parameter block label, label to be called by __morestack, frame size,
11207 ;; stack parameter size.
11208
11209 (define_insn "split_stack_data"
11210   [(unspec_volatile [(match_operand 0 "" "X")
11211                      (match_operand 1 "" "X")
11212                      (match_operand 2 "const_int_operand" "X")
11213                      (match_operand 3 "const_int_operand" "X")]
11214                     UNSPECV_SPLIT_STACK_DATA)]
11215   "TARGET_CPU_ZARCH"
11216 {
11217   switch_to_section (targetm.asm_out.function_rodata_section
11218                  (current_function_decl));
11219
11220   if (TARGET_64BIT)
11221     output_asm_insn (".align\t8", operands);
11222   else
11223     output_asm_insn (".align\t4", operands);
11224   (*targetm.asm_out.internal_label) (asm_out_file, "L",
11225                                      CODE_LABEL_NUMBER (operands[0]));
11226   if (TARGET_64BIT)
11227     {
11228       output_asm_insn (".quad\t%2", operands);
11229       output_asm_insn (".quad\t%3", operands);
11230       output_asm_insn (".quad\t%1-%0", operands);
11231     }
11232   else
11233     {
11234       output_asm_insn (".long\t%2", operands);
11235       output_asm_insn (".long\t%3", operands);
11236       output_asm_insn (".long\t%1-%0", operands);
11237     }
11238
11239   switch_to_section (current_function_section ());
11240   return "";
11241 }
11242   [(set_attr "length" "0")])
11243
11244
11245 ;; A jg with minimal fuss for use in split stack prologue.
11246
11247 (define_expand "split_stack_call"
11248   [(match_operand 0 "bras_sym_operand" "X")
11249    (match_operand 1 "" "")]
11250   "TARGET_CPU_ZARCH"
11251 {
11252   if (TARGET_64BIT)
11253     emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
11254   else
11255     emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
11256   DONE;
11257 })
11258
11259 (define_insn "split_stack_call_<mode>"
11260   [(set (pc) (label_ref (match_operand 1 "" "")))
11261    (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11262                                     (reg:P 1)]
11263                                    UNSPECV_SPLIT_STACK_CALL))]
11264   "TARGET_CPU_ZARCH"
11265   "jg\t%0"
11266   [(set_attr "op_type" "RIL")
11267    (set_attr "type"  "branch")])
11268
11269 ;; Also a conditional one.
11270
11271 (define_expand "split_stack_cond_call"
11272   [(match_operand 0 "bras_sym_operand" "X")
11273    (match_operand 1 "" "")
11274    (match_operand 2 "" "")]
11275   "TARGET_CPU_ZARCH"
11276 {
11277   if (TARGET_64BIT)
11278     emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
11279   else
11280     emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
11281   DONE;
11282 })
11283
11284 (define_insn "split_stack_cond_call_<mode>"
11285   [(set (pc)
11286         (if_then_else
11287           (match_operand 1 "" "")
11288           (label_ref (match_operand 2 "" ""))
11289           (pc)))
11290    (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11291                                     (reg:P 1)]
11292                                    UNSPECV_SPLIT_STACK_CALL))]
11293   "TARGET_CPU_ZARCH"
11294   "jg%C1\t%0"
11295   [(set_attr "op_type" "RIL")
11296    (set_attr "type"  "branch")])
11297
11298 (define_insn "osc_break"
11299   [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)]
11300   ""
11301   "bcr\t7,%%r0"
11302   [(set_attr "op_type" "RR")])