1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; Q -- Memory reference without index register and with short displacement.
51 ;; R -- Memory reference with index register and short displacement.
52 ;; S -- Memory reference without index register but with long displacement.
53 ;; T -- Memory reference with index register and long displacement.
54 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
55 ;; Offsettable memory reference of type specified by second letter.
56 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
57 ;; Memory reference of the type specified by second letter that
58 ;; does *not* refer to a literal pool entry.
59 ;; U -- Pointer with short displacement.
60 ;; W -- Pointer with long displacement.
61 ;; Y -- Shift count operand.
63 ;; Special formats used for outputting 390 instructions.
65 ;; %C: print opcode suffix for branch condition.
66 ;; %D: print opcode suffix for inverse branch condition.
67 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
68 ;; %O: print only the displacement of a memory reference.
69 ;; %R: print only the base register of a memory reference.
70 ;; %S: print S-type memory reference (base+displacement).
71 ;; %N: print the second word of a DImode operand.
72 ;; %M: print the second word of a TImode operand.
74 ;; %b: print integer X as if it's an unsigned byte.
75 ;; %x: print integer X as if it's an unsigned word.
76 ;; %h: print integer X as if it's a signed word.
77 ;; %i: print the first nonzero HImode part of X
78 ;; %j: print the first HImode part unequal to 0xffff of X
81 ;; We have a special constraint for pattern matching.
83 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
96 ; GOT/PLT and lt-relative accesses
97 (UNSPEC_LTREL_OFFSET 100)
98 (UNSPEC_LTREL_BASE 101)
106 (UNSPEC_RELOAD_BASE 210)
107 (UNSPEC_MAIN_BASE 211)
112 ; TLS relocation specifiers
117 (UNSPEC_GOTNTPOFF 504)
118 (UNSPEC_INDNTPOFF 505)
121 (UNSPEC_TLSLDM_NTPOFF 511)
122 (UNSPEC_TLS_LOAD 512)
129 ;; UNSPEC_VOLATILE usage
137 (UNSPECV_TPF_PROLOGUE 20)
138 (UNSPECV_TPF_EPILOGUE 21)
142 (UNSPECV_POOL_SECTION 201)
143 (UNSPECV_POOL_ALIGN 202)
144 (UNSPECV_POOL_ENTRY 203)
145 (UNSPECV_MAIN_POOL 300)
161 ; Sibling call register.
163 ; Literal pool base register.
165 ; Return address register.
167 ; Condition code register.
169 ; Thread local storage pointer register.
174 ;; Instruction operand type as used in the Principles of Operation.
175 ;; Used to determine defaults for length and other attribute values.
177 (define_attr "op_type"
178 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
181 ;; Instruction type attribute used for scheduling.
183 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
184 cs,vs,store,sem,idiv,
185 imulhi,imulsi,imuldi,
186 branch,jsr,fsimpdf,fsimpsf,
187 floaddf,floadsf,fstoredf,fstoresf,
188 fmuldf,fmulsf,fdivdf,fdivsf,
189 ftoi,itof,fsqrtdf,fsqrtsf,
191 (cond [(eq_attr "op_type" "NN") (const_string "other")
192 (eq_attr "op_type" "SS") (const_string "cs")]
193 (const_string "integer")))
195 ;; Another attribute used for scheduling purposes:
196 ;; agen: Instruction uses the address generation unit
197 ;; reg: Instruction does not use the agen unit
199 (define_attr "atype" "agen,reg"
200 (cond [(eq_attr "op_type" "E") (const_string "reg")
201 (eq_attr "op_type" "RR") (const_string "reg")
202 (eq_attr "op_type" "RX") (const_string "agen")
203 (eq_attr "op_type" "RI") (const_string "reg")
204 (eq_attr "op_type" "RRE") (const_string "reg")
205 (eq_attr "op_type" "RS") (const_string "agen")
206 (eq_attr "op_type" "RSI") (const_string "agen")
207 (eq_attr "op_type" "S") (const_string "agen")
208 (eq_attr "op_type" "SI") (const_string "agen")
209 (eq_attr "op_type" "SS") (const_string "agen")
210 (eq_attr "op_type" "SSE") (const_string "agen")
211 (eq_attr "op_type" "RXE") (const_string "agen")
212 (eq_attr "op_type" "RSE") (const_string "agen")
213 (eq_attr "op_type" "RIL") (const_string "agen")
214 (eq_attr "op_type" "RXY") (const_string "agen")
215 (eq_attr "op_type" "RSY") (const_string "agen")
216 (eq_attr "op_type" "SIY") (const_string "agen")]
217 (const_string "agen")))
221 (define_attr "length" ""
222 (cond [(eq_attr "op_type" "E") (const_int 2)
223 (eq_attr "op_type" "RR") (const_int 2)
224 (eq_attr "op_type" "RX") (const_int 4)
225 (eq_attr "op_type" "RI") (const_int 4)
226 (eq_attr "op_type" "RRE") (const_int 4)
227 (eq_attr "op_type" "RS") (const_int 4)
228 (eq_attr "op_type" "RSI") (const_int 4)
229 (eq_attr "op_type" "S") (const_int 4)
230 (eq_attr "op_type" "SI") (const_int 4)
231 (eq_attr "op_type" "SS") (const_int 6)
232 (eq_attr "op_type" "SSE") (const_int 6)
233 (eq_attr "op_type" "RXE") (const_int 6)
234 (eq_attr "op_type" "RSE") (const_int 6)
235 (eq_attr "op_type" "RIL") (const_int 6)
236 (eq_attr "op_type" "RXY") (const_int 6)
237 (eq_attr "op_type" "RSY") (const_int 6)
238 (eq_attr "op_type" "SIY") (const_int 6)]
242 ;; Processor type. This attribute must exactly match the processor_type
243 ;; enumeration in s390.h. The current machine description does not
244 ;; distinguish between g5 and g6, but there are differences between the two
245 ;; CPUs could in theory be modeled.
247 (define_attr "cpu" "g5,g6,z900,z990"
248 (const (symbol_ref "s390_tune")))
250 ;; Pipeline description for z900. For lack of anything better,
251 ;; this description is also used for the g5 and g6.
254 ;; Pipeline description for z990.
258 (include "predicates.md")
265 ;; This mode macro allows DF and SF patterns to be generated from the
267 (define_mode_macro FPR [DF SF])
269 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
270 ;; from the same template.
271 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
272 (define_mode_macro DSI [DI SI])
274 ;; This mode macro allows :P to be used for patterns that operate on
275 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
276 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
278 ;; This mode macro allows the QI and HI patterns to be defined from
279 ;; the same template.
280 (define_mode_macro HQI [HI QI])
282 ;; This mode macro allows the integer patterns to be defined from the
284 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
286 ;; This macro allows to unify all 'bCOND' expander patterns.
287 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
288 ordered uneq unlt ungt unle unge ltgt])
290 ;; This macro allows to unify all 'sCOND' patterns.
291 (define_code_macro SCOND [ltu gtu leu geu])
293 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
294 ;; the same template.
295 (define_code_macro SHIFT [ashift lshiftrt])
298 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
299 ;; and "ltebr" in SFmode.
300 (define_mode_attr de [(DF "d") (SF "e")])
302 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
303 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
304 (define_mode_attr dee [(DF "d") (SF "ee")])
306 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
307 ;; 'ashift' and "srdl" in 'lshiftrt'.
308 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
310 ;; In SHIFT templates, this attribute holds the correct standard name for the
311 ;; pattern itself and the corresponding function calls.
312 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
314 ;; This attribute handles differences in the instruction 'type' and will result
315 ;; in "RRE" for DImode and "RR" for SImode.
316 (define_mode_attr E [(DI "E") (SI "")])
318 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
319 ;; and "lcr" in SImode.
320 (define_mode_attr g [(DI "g") (SI "")])
322 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
323 ;; and "cfdbr" in SImode.
324 (define_mode_attr gf [(DI "g") (SI "f")])
326 ;; ICM mask required to load MODE value into the highest subreg
327 ;; of a SImode register.
328 (define_mode_attr icm_hi [(HI "12") (QI "8")])
330 ;; ICM mask required to load MODE value into the lowest subreg
331 ;; of a SImode register.
332 (define_mode_attr icm_lo [(HI "3") (QI "1")])
334 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
335 ;; HImode and "llgc" in QImode.
336 (define_mode_attr hc [(HI "h") (QI "c")])
338 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
340 (define_mode_attr DBL [(DI "TI") (SI "DI")])
342 ;; Maximum unsigned integer that fits in MODE.
343 (define_mode_attr max_uint [(HI "65535") (QI "255")])
347 ;;- Compare instructions.
350 (define_expand "cmp<mode>"
351 [(set (reg:CC CC_REGNUM)
352 (compare:CC (match_operand:GPR 0 "register_operand" "")
353 (match_operand:GPR 1 "general_operand" "")))]
356 s390_compare_op0 = operands[0];
357 s390_compare_op1 = operands[1];
361 (define_expand "cmp<mode>"
362 [(set (reg:CC CC_REGNUM)
363 (compare:CC (match_operand:FPR 0 "register_operand" "")
364 (match_operand:FPR 1 "general_operand" "")))]
367 s390_compare_op0 = operands[0];
368 s390_compare_op1 = operands[1];
373 ; Test-under-Mask instructions
375 (define_insn "*tmqi_mem"
376 [(set (reg CC_REGNUM)
377 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
378 (match_operand:QI 1 "immediate_operand" "n,n"))
379 (match_operand:QI 2 "immediate_operand" "n,n")))]
380 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
384 [(set_attr "op_type" "SI,SIY")])
386 (define_insn "*tmdi_reg"
387 [(set (reg CC_REGNUM)
388 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
389 (match_operand:DI 1 "immediate_operand"
390 "N0HD0,N1HD0,N2HD0,N3HD0"))
391 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
393 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
394 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
400 [(set_attr "op_type" "RI")])
402 (define_insn "*tmsi_reg"
403 [(set (reg CC_REGNUM)
404 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
405 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
406 (match_operand:SI 2 "immediate_operand" "n,n")))]
407 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
408 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
412 [(set_attr "op_type" "RI")])
414 (define_insn "*tm<mode>_full"
415 [(set (reg CC_REGNUM)
416 (compare (match_operand:HQI 0 "register_operand" "d")
417 (match_operand:HQI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
420 [(set_attr "op_type" "RI")])
423 ; Load-and-Test instructions
425 (define_insn "*tstdi_sign"
426 [(set (reg CC_REGNUM)
427 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
428 (const_int 32)) (const_int 32))
429 (match_operand:DI 1 "const0_operand" "")))
430 (set (match_operand:DI 2 "register_operand" "=d")
431 (sign_extend:DI (match_dup 0)))]
432 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
434 [(set_attr "op_type" "RRE")])
436 (define_insn "*tstdi"
437 [(set (reg CC_REGNUM)
438 (compare (match_operand:DI 0 "register_operand" "d")
439 (match_operand:DI 1 "const0_operand" "")))
440 (set (match_operand:DI 2 "register_operand" "=d")
442 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
444 [(set_attr "op_type" "RRE")])
446 (define_insn "*tstdi_cconly"
447 [(set (reg CC_REGNUM)
448 (compare (match_operand:DI 0 "register_operand" "d")
449 (match_operand:DI 1 "const0_operand" "")))]
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
452 [(set_attr "op_type" "RRE")])
454 (define_insn "*tstdi_cconly_31"
455 [(set (reg CC_REGNUM)
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
460 [(set_attr "op_type" "RS")
461 (set_attr "atype" "reg")])
464 (define_insn "*tstsi"
465 [(set (reg CC_REGNUM)
466 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
467 (match_operand:SI 1 "const0_operand" "")))
468 (set (match_operand:SI 2 "register_operand" "=d,d,d")
470 "s390_match_ccmode(insn, CCSmode)"
475 [(set_attr "op_type" "RR,RS,RSY")])
477 (define_insn "*tstsi_cconly"
478 [(set (reg CC_REGNUM)
479 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
480 (match_operand:SI 1 "const0_operand" "")))
481 (clobber (match_scratch:SI 2 "=X,d,d"))]
482 "s390_match_ccmode(insn, CCSmode)"
487 [(set_attr "op_type" "RR,RS,RSY")])
489 (define_insn "*tstsi_cconly2"
490 [(set (reg CC_REGNUM)
491 (compare (match_operand:SI 0 "register_operand" "d")
492 (match_operand:SI 1 "const0_operand" "")))]
493 "s390_match_ccmode(insn, CCSmode)"
495 [(set_attr "op_type" "RR")])
497 (define_insn "*tst<mode>CCT"
498 [(set (reg CC_REGNUM)
499 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
500 (match_operand:HQI 1 "const0_operand" "")))
501 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
503 "s390_match_ccmode(insn, CCTmode)"
506 icmy\t%2,<icm_lo>,%S0
508 [(set_attr "op_type" "RS,RSY,RI")])
510 (define_insn "*tsthiCCT_cconly"
511 [(set (reg CC_REGNUM)
512 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
513 (match_operand:HI 1 "const0_operand" "")))
514 (clobber (match_scratch:HI 2 "=d,d,X"))]
515 "s390_match_ccmode(insn, CCTmode)"
520 [(set_attr "op_type" "RS,RSY,RI")])
522 (define_insn "*tstqiCCT_cconly"
523 [(set (reg CC_REGNUM)
524 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
525 (match_operand:QI 1 "const0_operand" "")))]
526 "s390_match_ccmode(insn, CCTmode)"
531 [(set_attr "op_type" "SI,SIY,RI")])
533 (define_insn "*tst<mode>"
534 [(set (reg CC_REGNUM)
535 (compare (match_operand:HQI 0 "s_operand" "Q,S")
536 (match_operand:HQI 1 "const0_operand" "")))
537 (set (match_operand:HQI 2 "register_operand" "=d,d")
539 "s390_match_ccmode(insn, CCSmode)"
542 icmy\t%2,<icm_lo>,%S0"
543 [(set_attr "op_type" "RS,RSY")])
545 (define_insn "*tst<mode>_cconly"
546 [(set (reg CC_REGNUM)
547 (compare (match_operand:HQI 0 "s_operand" "Q,S")
548 (match_operand:HQI 1 "const0_operand" "")))
549 (clobber (match_scratch:HQI 2 "=d,d"))]
550 "s390_match_ccmode(insn, CCSmode)"
553 icmy\t%2,<icm_lo>,%S0"
554 [(set_attr "op_type" "RS,RSY")])
557 ; Compare (equality) instructions
559 (define_insn "*cmpdi_cct"
560 [(set (reg CC_REGNUM)
561 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
562 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
563 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
569 [(set_attr "op_type" "RRE,RI,RXY,SS")])
571 (define_insn "*cmpsi_cct"
572 [(set (reg CC_REGNUM)
573 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
574 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
575 "s390_match_ccmode (insn, CCTmode)"
582 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
585 ; Compare (signed) instructions
587 (define_insn "*cmpdi_ccs_sign"
588 [(set (reg CC_REGNUM)
589 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
590 (match_operand:DI 0 "register_operand" "d,d")))]
591 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
595 [(set_attr "op_type" "RRE,RXY")])
597 (define_insn "*cmpdi_ccs"
598 [(set (reg CC_REGNUM)
599 (compare (match_operand:DI 0 "register_operand" "d,d,d")
600 (match_operand:DI 1 "general_operand" "d,K,m")))]
601 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
606 [(set_attr "op_type" "RRE,RI,RXY")])
608 (define_insn "*cmpsi_ccs_sign"
609 [(set (reg CC_REGNUM)
610 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
611 (match_operand:SI 0 "register_operand" "d,d")))]
612 "s390_match_ccmode(insn, CCSRmode)"
616 [(set_attr "op_type" "RX,RXY")])
618 (define_insn "*cmpsi_ccs"
619 [(set (reg CC_REGNUM)
620 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
621 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
622 "s390_match_ccmode(insn, CCSmode)"
628 [(set_attr "op_type" "RR,RI,RX,RXY")])
631 ; Compare (unsigned) instructions
633 (define_insn "*cmpdi_ccu_zero"
634 [(set (reg CC_REGNUM)
635 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
636 (match_operand:DI 0 "register_operand" "d,d")))]
637 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
641 [(set_attr "op_type" "RRE,RXY")])
643 (define_insn "*cmpdi_ccu"
644 [(set (reg CC_REGNUM)
645 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
646 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
647 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
653 [(set_attr "op_type" "RRE,RXY,SS,SS")])
655 (define_insn "*cmpsi_ccu"
656 [(set (reg CC_REGNUM)
657 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
658 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
659 "s390_match_ccmode (insn, CCUmode)"
666 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
668 (define_insn "*cmphi_ccu"
669 [(set (reg CC_REGNUM)
670 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
671 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
672 "s390_match_ccmode (insn, CCUmode)
673 && !register_operand (operands[1], HImode)"
679 [(set_attr "op_type" "RS,RSY,SS,SS")])
681 (define_insn "*cmpqi_ccu"
682 [(set (reg CC_REGNUM)
683 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
684 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
685 "s390_match_ccmode (insn, CCUmode)
686 && !register_operand (operands[1], QImode)"
694 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
697 ; Block compare (CLC) instruction patterns.
700 [(set (reg CC_REGNUM)
701 (compare (match_operand:BLK 0 "memory_operand" "Q")
702 (match_operand:BLK 1 "memory_operand" "Q")))
703 (use (match_operand 2 "const_int_operand" "n"))]
704 "s390_match_ccmode (insn, CCUmode)
705 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
706 "clc\t%O0(%2,%R0),%S1"
707 [(set_attr "op_type" "SS")])
710 [(set (reg CC_REGNUM)
711 (compare (match_operand 0 "memory_operand" "")
712 (match_operand 1 "memory_operand" "")))]
714 && s390_match_ccmode (insn, CCUmode)
715 && GET_MODE (operands[0]) == GET_MODE (operands[1])
716 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
718 [(set (match_dup 0) (match_dup 1))
719 (use (match_dup 2))])]
721 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
722 operands[0] = adjust_address (operands[0], BLKmode, 0);
723 operands[1] = adjust_address (operands[1], BLKmode, 0);
725 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
726 operands[0], operands[1]);
727 operands[0] = SET_DEST (PATTERN (curr_insn));
731 ; (DF|SF) instructions
733 (define_insn "*cmp<mode>_ccs_0"
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:FPR 0 "register_operand" "f")
736 (match_operand:FPR 1 "const0_operand" "")))]
737 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
739 [(set_attr "op_type" "RRE")
740 (set_attr "type" "fsimp<mode>")])
742 (define_insn "*cmp<mode>_ccs_0_ibm"
743 [(set (reg CC_REGNUM)
744 (compare (match_operand:FPR 0 "register_operand" "f")
745 (match_operand:FPR 1 "const0_operand" "")))]
746 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
748 [(set_attr "op_type" "RR")
749 (set_attr "type" "fsimp<mode>")])
751 (define_insn "*cmp<mode>_ccs"
752 [(set (reg CC_REGNUM)
753 (compare (match_operand:FPR 0 "register_operand" "f,f")
754 (match_operand:FPR 1 "general_operand" "f,R")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
759 [(set_attr "op_type" "RRE,RXE")
760 (set_attr "type" "fsimp<mode>")])
762 (define_insn "*cmp<mode>_ccs_ibm"
763 [(set (reg CC_REGNUM)
764 (compare (match_operand:FPR 0 "register_operand" "f,f")
765 (match_operand:FPR 1 "general_operand" "f,R")))]
766 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
770 [(set_attr "op_type" "RR,RX")
771 (set_attr "type" "fsimp<mode>")])
775 ;;- Move instructions.
779 ; movti instruction pattern(s).
783 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
784 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
792 [(set_attr "op_type" "RSY,RSY,*,*,SS")
793 (set_attr "type" "lm,stm,*,*,*")])
796 [(set (match_operand:TI 0 "nonimmediate_operand" "")
797 (match_operand:TI 1 "general_operand" ""))]
798 "TARGET_64BIT && reload_completed
799 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
800 [(set (match_dup 2) (match_dup 4))
801 (set (match_dup 3) (match_dup 5))]
803 operands[2] = operand_subword (operands[0], 0, 0, TImode);
804 operands[3] = operand_subword (operands[0], 1, 0, TImode);
805 operands[4] = operand_subword (operands[1], 0, 0, TImode);
806 operands[5] = operand_subword (operands[1], 1, 0, TImode);
810 [(set (match_operand:TI 0 "nonimmediate_operand" "")
811 (match_operand:TI 1 "general_operand" ""))]
812 "TARGET_64BIT && reload_completed
813 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
814 [(set (match_dup 2) (match_dup 4))
815 (set (match_dup 3) (match_dup 5))]
817 operands[2] = operand_subword (operands[0], 1, 0, TImode);
818 operands[3] = operand_subword (operands[0], 0, 0, TImode);
819 operands[4] = operand_subword (operands[1], 1, 0, TImode);
820 operands[5] = operand_subword (operands[1], 0, 0, TImode);
824 [(set (match_operand:TI 0 "register_operand" "")
825 (match_operand:TI 1 "memory_operand" ""))]
826 "TARGET_64BIT && reload_completed
827 && !s_operand (operands[1], VOIDmode)"
828 [(set (match_dup 0) (match_dup 1))]
830 rtx addr = operand_subword (operands[0], 1, 0, TImode);
831 s390_load_address (addr, XEXP (operands[1], 0));
832 operands[1] = replace_equiv_address (operands[1], addr);
835 (define_expand "reload_outti"
836 [(parallel [(match_operand:TI 0 "" "")
837 (match_operand:TI 1 "register_operand" "d")
838 (match_operand:DI 2 "register_operand" "=&a")])]
841 gcc_assert (MEM_P (operands[0]));
842 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
843 operands[0] = replace_equiv_address (operands[0], operands[2]);
844 emit_move_insn (operands[0], operands[1]);
849 ; movdi instruction pattern(s).
852 (define_expand "movdi"
853 [(set (match_operand:DI 0 "general_operand" "")
854 (match_operand:DI 1 "general_operand" ""))]
857 /* Handle symbolic constants. */
858 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
859 emit_symbolic_move (operands);
862 (define_insn "*movdi_larl"
863 [(set (match_operand:DI 0 "register_operand" "=d")
864 (match_operand:DI 1 "larl_operand" "X"))]
866 && !FP_REG_P (operands[0])"
868 [(set_attr "op_type" "RIL")
869 (set_attr "type" "larl")])
871 (define_insn "*movdi_64"
872 [(set (match_operand:DI 0 "nonimmediate_operand"
873 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
874 (match_operand:DI 1 "general_operand"
875 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
897 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
898 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
899 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
900 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
903 [(set (match_operand:DI 0 "register_operand" "")
904 (match_operand:DI 1 "register_operand" ""))]
905 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
906 [(set (match_dup 2) (match_dup 3))
907 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
908 (set (strict_low_part (match_dup 2)) (match_dup 4))]
909 "operands[2] = gen_lowpart (SImode, operands[0]);
910 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
913 [(set (match_operand:DI 0 "register_operand" "")
914 (match_operand:DI 1 "register_operand" ""))]
915 "TARGET_64BIT && ACCESS_REG_P (operands[0])
916 && dead_or_set_p (insn, operands[1])"
917 [(set (match_dup 3) (match_dup 2))
918 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
919 (set (match_dup 4) (match_dup 2))]
920 "operands[2] = gen_lowpart (SImode, operands[1]);
921 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
924 [(set (match_operand:DI 0 "register_operand" "")
925 (match_operand:DI 1 "register_operand" ""))]
926 "TARGET_64BIT && ACCESS_REG_P (operands[0])
927 && !dead_or_set_p (insn, operands[1])"
928 [(set (match_dup 3) (match_dup 2))
929 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
930 (set (match_dup 4) (match_dup 2))
931 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
932 "operands[2] = gen_lowpart (SImode, operands[1]);
933 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
935 (define_insn "*movdi_31"
936 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
937 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
950 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
951 (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
954 [(set (match_operand:DI 0 "nonimmediate_operand" "")
955 (match_operand:DI 1 "general_operand" ""))]
956 "!TARGET_64BIT && reload_completed
957 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
958 [(set (match_dup 2) (match_dup 4))
959 (set (match_dup 3) (match_dup 5))]
961 operands[2] = operand_subword (operands[0], 0, 0, DImode);
962 operands[3] = operand_subword (operands[0], 1, 0, DImode);
963 operands[4] = operand_subword (operands[1], 0, 0, DImode);
964 operands[5] = operand_subword (operands[1], 1, 0, DImode);
968 [(set (match_operand:DI 0 "nonimmediate_operand" "")
969 (match_operand:DI 1 "general_operand" ""))]
970 "!TARGET_64BIT && reload_completed
971 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
972 [(set (match_dup 2) (match_dup 4))
973 (set (match_dup 3) (match_dup 5))]
975 operands[2] = operand_subword (operands[0], 1, 0, DImode);
976 operands[3] = operand_subword (operands[0], 0, 0, DImode);
977 operands[4] = operand_subword (operands[1], 1, 0, DImode);
978 operands[5] = operand_subword (operands[1], 0, 0, DImode);
982 [(set (match_operand:DI 0 "register_operand" "")
983 (match_operand:DI 1 "memory_operand" ""))]
984 "!TARGET_64BIT && reload_completed
985 && !FP_REG_P (operands[0])
986 && !s_operand (operands[1], VOIDmode)"
987 [(set (match_dup 0) (match_dup 1))]
989 rtx addr = operand_subword (operands[0], 1, 0, DImode);
990 s390_load_address (addr, XEXP (operands[1], 0));
991 operands[1] = replace_equiv_address (operands[1], addr);
994 (define_expand "reload_outdi"
995 [(parallel [(match_operand:DI 0 "" "")
996 (match_operand:DI 1 "register_operand" "d")
997 (match_operand:SI 2 "register_operand" "=&a")])]
1000 gcc_assert (MEM_P (operands[0]));
1001 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1002 operands[0] = replace_equiv_address (operands[0], operands[2]);
1003 emit_move_insn (operands[0], operands[1]);
1008 [(set (match_operand:DI 0 "register_operand" "")
1009 (mem:DI (match_operand 1 "address_operand" "")))]
1011 && !FP_REG_P (operands[0])
1012 && GET_CODE (operands[1]) == SYMBOL_REF
1013 && CONSTANT_POOL_ADDRESS_P (operands[1])
1014 && get_pool_mode (operands[1]) == DImode
1015 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1016 [(set (match_dup 0) (match_dup 2))]
1017 "operands[2] = get_pool_constant (operands[1]);")
1019 (define_insn "*la_64"
1020 [(set (match_operand:DI 0 "register_operand" "=d,d")
1021 (match_operand:QI 1 "address_operand" "U,W"))]
1026 [(set_attr "op_type" "RX,RXY")
1027 (set_attr "type" "la")])
1031 [(set (match_operand:DI 0 "register_operand" "")
1032 (match_operand:QI 1 "address_operand" ""))
1033 (clobber (reg:CC CC_REGNUM))])]
1035 && preferred_la_operand_p (operands[1], const0_rtx)"
1036 [(set (match_dup 0) (match_dup 1))]
1040 [(set (match_operand:DI 0 "register_operand" "")
1041 (match_operand:DI 1 "register_operand" ""))
1044 (plus:DI (match_dup 0)
1045 (match_operand:DI 2 "nonmemory_operand" "")))
1046 (clobber (reg:CC CC_REGNUM))])]
1048 && !reg_overlap_mentioned_p (operands[0], operands[2])
1049 && preferred_la_operand_p (operands[1], operands[2])"
1050 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1053 (define_expand "reload_indi"
1054 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1055 (match_operand:DI 1 "s390_plus_operand" "")
1056 (match_operand:DI 2 "register_operand" "=&a")])]
1059 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1064 ; movsi instruction pattern(s).
1067 (define_expand "movsi"
1068 [(set (match_operand:SI 0 "general_operand" "")
1069 (match_operand:SI 1 "general_operand" ""))]
1072 /* Handle symbolic constants. */
1073 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1074 emit_symbolic_move (operands);
1077 (define_insn "*movsi_larl"
1078 [(set (match_operand:SI 0 "register_operand" "=d")
1079 (match_operand:SI 1 "larl_operand" "X"))]
1080 "!TARGET_64BIT && TARGET_CPU_ZARCH
1081 && !FP_REG_P (operands[0])"
1083 [(set_attr "op_type" "RIL")
1084 (set_attr "type" "larl")])
1086 (define_insn "*movsi_zarch"
1087 [(set (match_operand:SI 0 "nonimmediate_operand"
1088 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1089 (match_operand:SI 1 "general_operand"
1090 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1112 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1113 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1114 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1115 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1117 (define_insn "*movsi_esa"
1118 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1119 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1134 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1135 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1138 [(set (match_operand:SI 0 "register_operand" "")
1139 (mem:SI (match_operand 1 "address_operand" "")))]
1140 "!FP_REG_P (operands[0])
1141 && GET_CODE (operands[1]) == SYMBOL_REF
1142 && CONSTANT_POOL_ADDRESS_P (operands[1])
1143 && get_pool_mode (operands[1]) == SImode
1144 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1145 [(set (match_dup 0) (match_dup 2))]
1146 "operands[2] = get_pool_constant (operands[1]);")
1148 (define_insn "*la_31"
1149 [(set (match_operand:SI 0 "register_operand" "=d,d")
1150 (match_operand:QI 1 "address_operand" "U,W"))]
1151 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1155 [(set_attr "op_type" "RX,RXY")
1156 (set_attr "type" "la")])
1160 [(set (match_operand:SI 0 "register_operand" "")
1161 (match_operand:QI 1 "address_operand" ""))
1162 (clobber (reg:CC CC_REGNUM))])]
1164 && preferred_la_operand_p (operands[1], const0_rtx)"
1165 [(set (match_dup 0) (match_dup 1))]
1169 [(set (match_operand:SI 0 "register_operand" "")
1170 (match_operand:SI 1 "register_operand" ""))
1173 (plus:SI (match_dup 0)
1174 (match_operand:SI 2 "nonmemory_operand" "")))
1175 (clobber (reg:CC CC_REGNUM))])]
1177 && !reg_overlap_mentioned_p (operands[0], operands[2])
1178 && preferred_la_operand_p (operands[1], operands[2])"
1179 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1182 (define_insn "*la_31_and"
1183 [(set (match_operand:SI 0 "register_operand" "=d,d")
1184 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1185 (const_int 2147483647)))]
1190 [(set_attr "op_type" "RX,RXY")
1191 (set_attr "type" "la")])
1193 (define_insn_and_split "*la_31_and_cc"
1194 [(set (match_operand:SI 0 "register_operand" "=d")
1195 (and:SI (match_operand:QI 1 "address_operand" "p")
1196 (const_int 2147483647)))
1197 (clobber (reg:CC CC_REGNUM))]
1200 "&& reload_completed"
1202 (and:SI (match_dup 1) (const_int 2147483647)))]
1204 [(set_attr "op_type" "RX")
1205 (set_attr "type" "la")])
1207 (define_insn "force_la_31"
1208 [(set (match_operand:SI 0 "register_operand" "=d,d")
1209 (match_operand:QI 1 "address_operand" "U,W"))
1210 (use (const_int 0))]
1215 [(set_attr "op_type" "RX")
1216 (set_attr "type" "la")])
1218 (define_expand "reload_insi"
1219 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1220 (match_operand:SI 1 "s390_plus_operand" "")
1221 (match_operand:SI 2 "register_operand" "=&a")])]
1224 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1229 ; movhi instruction pattern(s).
1232 (define_expand "movhi"
1233 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1234 (match_operand:HI 1 "general_operand" ""))]
1237 /* Make it explicit that loading a register from memory
1238 always sign-extends (at least) to SImode. */
1239 if (optimize && !no_new_pseudos
1240 && register_operand (operands[0], VOIDmode)
1241 && GET_CODE (operands[1]) == MEM)
1243 rtx tmp = gen_reg_rtx (SImode);
1244 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1245 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1246 operands[1] = gen_lowpart (HImode, tmp);
1250 (define_insn "*movhi"
1251 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1252 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1262 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1263 (set_attr "type" "lr,*,*,*,store,store,*")])
1266 [(set (match_operand:HI 0 "register_operand" "")
1267 (mem:HI (match_operand 1 "address_operand" "")))]
1268 "GET_CODE (operands[1]) == SYMBOL_REF
1269 && CONSTANT_POOL_ADDRESS_P (operands[1])
1270 && get_pool_mode (operands[1]) == HImode
1271 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1272 [(set (match_dup 0) (match_dup 2))]
1273 "operands[2] = get_pool_constant (operands[1]);")
1276 ; movqi instruction pattern(s).
1279 (define_expand "movqi"
1280 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1281 (match_operand:QI 1 "general_operand" ""))]
1284 /* On z/Architecture, zero-extending from memory to register
1285 is just as fast as a QImode load. */
1286 if (TARGET_ZARCH && optimize && !no_new_pseudos
1287 && register_operand (operands[0], VOIDmode)
1288 && GET_CODE (operands[1]) == MEM)
1290 rtx tmp = gen_reg_rtx (word_mode);
1291 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1292 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1293 operands[1] = gen_lowpart (QImode, tmp);
1297 (define_insn "*movqi"
1298 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1299 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1311 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1312 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1315 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1316 (mem:QI (match_operand 1 "address_operand" "")))]
1317 "GET_CODE (operands[1]) == SYMBOL_REF
1318 && CONSTANT_POOL_ADDRESS_P (operands[1])
1319 && get_pool_mode (operands[1]) == QImode
1320 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1321 [(set (match_dup 0) (match_dup 2))]
1322 "operands[2] = get_pool_constant (operands[1]);")
1325 ; movstrictqi instruction pattern(s).
1328 (define_insn "*movstrictqi"
1329 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1330 (match_operand:QI 1 "memory_operand" "R,T"))]
1335 [(set_attr "op_type" "RX,RXY")])
1338 ; movstricthi instruction pattern(s).
1341 (define_insn "*movstricthi"
1342 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1343 (match_operand:HI 1 "memory_operand" "Q,S"))
1344 (clobber (reg:CC CC_REGNUM))]
1349 [(set_attr "op_type" "RS,RSY")])
1352 ; movstrictsi instruction pattern(s).
1355 (define_insn "movstrictsi"
1356 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1357 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1364 [(set_attr "op_type" "RR,RX,RXY,RRE")
1365 (set_attr "type" "lr,load,load,*")])
1368 ; movdf instruction pattern(s).
1371 (define_expand "movdf"
1372 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1373 (match_operand:DF 1 "general_operand" ""))]
1377 (define_insn "*movdf_64"
1378 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1379 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1392 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1393 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1395 (define_insn "*movdf_31"
1396 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,Q,d,o,Q")
1397 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,d,dKm,d,Q"))]
1411 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1412 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
1415 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1416 (match_operand:DF 1 "general_operand" ""))]
1417 "!TARGET_64BIT && reload_completed
1418 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1419 [(set (match_dup 2) (match_dup 4))
1420 (set (match_dup 3) (match_dup 5))]
1422 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1423 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1424 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1425 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1429 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1430 (match_operand:DF 1 "general_operand" ""))]
1431 "!TARGET_64BIT && reload_completed
1432 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1433 [(set (match_dup 2) (match_dup 4))
1434 (set (match_dup 3) (match_dup 5))]
1436 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1437 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1438 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1439 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1443 [(set (match_operand:DF 0 "register_operand" "")
1444 (match_operand:DF 1 "memory_operand" ""))]
1445 "!TARGET_64BIT && reload_completed
1446 && !FP_REG_P (operands[0])
1447 && !s_operand (operands[1], VOIDmode)"
1448 [(set (match_dup 0) (match_dup 1))]
1450 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1451 s390_load_address (addr, XEXP (operands[1], 0));
1452 operands[1] = replace_equiv_address (operands[1], addr);
1455 (define_expand "reload_outdf"
1456 [(parallel [(match_operand:DF 0 "" "")
1457 (match_operand:DF 1 "register_operand" "d")
1458 (match_operand:SI 2 "register_operand" "=&a")])]
1461 gcc_assert (MEM_P (operands[0]));
1462 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1463 operands[0] = replace_equiv_address (operands[0], operands[2]);
1464 emit_move_insn (operands[0], operands[1]);
1469 ; movsf instruction pattern(s).
1472 (define_insn "movsf"
1473 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1474 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1489 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1490 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1491 lr,load,load,store,store,*")])
1494 ; movcc instruction pattern
1497 (define_insn "movcc"
1498 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1499 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1509 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1510 (set_attr "type" "lr,*,*,store,store,load,load")])
1513 ; Block move (MVC) patterns.
1517 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1518 (match_operand:BLK 1 "memory_operand" "Q"))
1519 (use (match_operand 2 "const_int_operand" "n"))]
1520 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1521 "mvc\t%O0(%2,%R0),%S1"
1522 [(set_attr "op_type" "SS")])
1525 [(set (match_operand 0 "memory_operand" "")
1526 (match_operand 1 "memory_operand" ""))]
1528 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1529 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1531 [(set (match_dup 0) (match_dup 1))
1532 (use (match_dup 2))])]
1534 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1535 operands[0] = adjust_address (operands[0], BLKmode, 0);
1536 operands[1] = adjust_address (operands[1], BLKmode, 0);
1541 [(set (match_operand:BLK 0 "memory_operand" "")
1542 (match_operand:BLK 1 "memory_operand" ""))
1543 (use (match_operand 2 "const_int_operand" ""))])
1545 [(set (match_operand:BLK 3 "memory_operand" "")
1546 (match_operand:BLK 4 "memory_operand" ""))
1547 (use (match_operand 5 "const_int_operand" ""))])]
1548 "s390_offset_p (operands[0], operands[3], operands[2])
1549 && s390_offset_p (operands[1], operands[4], operands[2])
1550 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1552 [(set (match_dup 6) (match_dup 7))
1553 (use (match_dup 8))])]
1554 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1555 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1556 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1560 ; load_multiple pattern(s).
1562 ; ??? Due to reload problems with replacing registers inside match_parallel
1563 ; we currently support load_multiple/store_multiple only after reload.
1566 (define_expand "load_multiple"
1567 [(match_par_dup 3 [(set (match_operand 0 "" "")
1568 (match_operand 1 "" ""))
1569 (use (match_operand 2 "" ""))])]
1572 enum machine_mode mode;
1578 /* Support only loading a constant number of fixed-point registers from
1579 memory and only bother with this if more than two */
1580 if (GET_CODE (operands[2]) != CONST_INT
1581 || INTVAL (operands[2]) < 2
1582 || INTVAL (operands[2]) > 16
1583 || GET_CODE (operands[1]) != MEM
1584 || GET_CODE (operands[0]) != REG
1585 || REGNO (operands[0]) >= 16)
1588 count = INTVAL (operands[2]);
1589 regno = REGNO (operands[0]);
1590 mode = GET_MODE (operands[0]);
1591 if (mode != SImode && mode != word_mode)
1594 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1597 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1599 from = XEXP (operands[1], 0);
1602 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1603 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1604 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1606 from = XEXP (XEXP (operands[1], 0), 0);
1607 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1614 from = force_reg (Pmode, XEXP (operands[1], 0));
1618 for (i = 0; i < count; i++)
1619 XVECEXP (operands[3], 0, i)
1620 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1621 change_address (operands[1], mode,
1622 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1625 (define_insn "*load_multiple_di"
1626 [(match_parallel 0 "load_multiple_operation"
1627 [(set (match_operand:DI 1 "register_operand" "=r")
1628 (match_operand:DI 2 "s_operand" "QS"))])]
1629 "reload_completed && word_mode == DImode"
1631 int words = XVECLEN (operands[0], 0);
1632 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1633 return "lmg\t%1,%0,%S2";
1635 [(set_attr "op_type" "RSY")
1636 (set_attr "type" "lm")])
1638 (define_insn "*load_multiple_si"
1639 [(match_parallel 0 "load_multiple_operation"
1640 [(set (match_operand:SI 1 "register_operand" "=r,r")
1641 (match_operand:SI 2 "s_operand" "Q,S"))])]
1644 int words = XVECLEN (operands[0], 0);
1645 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1646 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1648 [(set_attr "op_type" "RS,RSY")
1649 (set_attr "type" "lm")])
1652 ; store multiple pattern(s).
1655 (define_expand "store_multiple"
1656 [(match_par_dup 3 [(set (match_operand 0 "" "")
1657 (match_operand 1 "" ""))
1658 (use (match_operand 2 "" ""))])]
1661 enum machine_mode mode;
1667 /* Support only storing a constant number of fixed-point registers to
1668 memory and only bother with this if more than two. */
1669 if (GET_CODE (operands[2]) != CONST_INT
1670 || INTVAL (operands[2]) < 2
1671 || INTVAL (operands[2]) > 16
1672 || GET_CODE (operands[0]) != MEM
1673 || GET_CODE (operands[1]) != REG
1674 || REGNO (operands[1]) >= 16)
1677 count = INTVAL (operands[2]);
1678 regno = REGNO (operands[1]);
1679 mode = GET_MODE (operands[1]);
1680 if (mode != SImode && mode != word_mode)
1683 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1687 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1689 to = XEXP (operands[0], 0);
1692 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1693 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1694 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1696 to = XEXP (XEXP (operands[0], 0), 0);
1697 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1704 to = force_reg (Pmode, XEXP (operands[0], 0));
1708 for (i = 0; i < count; i++)
1709 XVECEXP (operands[3], 0, i)
1710 = gen_rtx_SET (VOIDmode,
1711 change_address (operands[0], mode,
1712 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1713 gen_rtx_REG (mode, regno + i));
1716 (define_insn "*store_multiple_di"
1717 [(match_parallel 0 "store_multiple_operation"
1718 [(set (match_operand:DI 1 "s_operand" "=QS")
1719 (match_operand:DI 2 "register_operand" "r"))])]
1720 "reload_completed && word_mode == DImode"
1722 int words = XVECLEN (operands[0], 0);
1723 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1724 return "stmg\t%2,%0,%S1";
1726 [(set_attr "op_type" "RSY")
1727 (set_attr "type" "stm")])
1730 (define_insn "*store_multiple_si"
1731 [(match_parallel 0 "store_multiple_operation"
1732 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1733 (match_operand:SI 2 "register_operand" "r,r"))])]
1736 int words = XVECLEN (operands[0], 0);
1737 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1738 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1740 [(set_attr "op_type" "RS,RSY")
1741 (set_attr "type" "stm")])
1744 ;; String instructions.
1747 (define_insn "*execute"
1748 [(match_parallel 0 ""
1749 [(unspec [(match_operand 1 "register_operand" "a")
1750 (match_operand:BLK 2 "memory_operand" "R")
1751 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1752 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1753 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1755 [(set_attr "op_type" "RX")
1756 (set_attr "type" "cs")])
1760 ; strlenM instruction pattern(s).
1763 (define_expand "strlen<mode>"
1764 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1767 (unspec:P [(const_int 0)
1768 (match_operand:BLK 1 "memory_operand" "")
1770 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1771 (clobber (scratch:P))
1772 (clobber (reg:CC CC_REGNUM))])
1774 [(set (match_operand:P 0 "register_operand" "")
1775 (minus:P (match_dup 4) (match_dup 5)))
1776 (clobber (reg:CC CC_REGNUM))])]
1779 operands[4] = gen_reg_rtx (Pmode);
1780 operands[5] = gen_reg_rtx (Pmode);
1781 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1782 operands[1] = replace_equiv_address (operands[1], operands[5]);
1785 (define_insn "*strlen<mode>"
1786 [(set (match_operand:P 0 "register_operand" "=a")
1787 (unspec:P [(match_operand:P 2 "general_operand" "0")
1788 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1790 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1791 (clobber (match_scratch:P 1 "=a"))
1792 (clobber (reg:CC CC_REGNUM))]
1794 "srst\t%0,%1\;jo\t.-4"
1795 [(set_attr "length" "8")
1796 (set_attr "type" "vs")])
1799 ; cmpstrM instruction pattern(s).
1802 (define_expand "cmpstrsi"
1803 [(set (reg:SI 0) (const_int 0))
1805 [(clobber (match_operand 3 "" ""))
1806 (clobber (match_dup 4))
1807 (set (reg:CCU CC_REGNUM)
1808 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1809 (match_operand:BLK 2 "memory_operand" "")))
1812 [(set (match_operand:SI 0 "register_operand" "=d")
1813 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1814 (clobber (reg:CC CC_REGNUM))])]
1817 /* As the result of CMPINT is inverted compared to what we need,
1818 we have to swap the operands. */
1819 rtx op1 = operands[2];
1820 rtx op2 = operands[1];
1821 rtx addr1 = gen_reg_rtx (Pmode);
1822 rtx addr2 = gen_reg_rtx (Pmode);
1824 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1825 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1826 operands[1] = replace_equiv_address_nv (op1, addr1);
1827 operands[2] = replace_equiv_address_nv (op2, addr2);
1828 operands[3] = addr1;
1829 operands[4] = addr2;
1832 (define_insn "*cmpstr<mode>"
1833 [(clobber (match_operand:P 0 "register_operand" "=d"))
1834 (clobber (match_operand:P 1 "register_operand" "=d"))
1835 (set (reg:CCU CC_REGNUM)
1836 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1837 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1840 "clst\t%0,%1\;jo\t.-4"
1841 [(set_attr "length" "8")
1842 (set_attr "type" "vs")])
1845 ; movmemM instruction pattern(s).
1848 (define_expand "movmem<mode>"
1849 [(set (match_operand:BLK 0 "memory_operand" "")
1850 (match_operand:BLK 1 "memory_operand" ""))
1851 (use (match_operand:GPR 2 "general_operand" ""))
1852 (match_operand 3 "" "")]
1854 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1856 ; Move a block that is up to 256 bytes in length.
1857 ; The block length is taken as (operands[2] % 256) + 1.
1859 (define_expand "movmem_short"
1861 [(set (match_operand:BLK 0 "memory_operand" "")
1862 (match_operand:BLK 1 "memory_operand" ""))
1863 (use (match_operand 2 "nonmemory_operand" ""))
1864 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1865 (clobber (match_dup 3))])]
1867 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1869 (define_insn "*movmem_short"
1870 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1871 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1872 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1873 (use (match_operand 3 "immediate_operand" "X,R,X"))
1874 (clobber (match_scratch 4 "=X,X,&a"))]
1875 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1876 && GET_MODE (operands[4]) == Pmode"
1878 [(set_attr "type" "cs")])
1881 [(set (match_operand:BLK 0 "memory_operand" "")
1882 (match_operand:BLK 1 "memory_operand" ""))
1883 (use (match_operand 2 "const_int_operand" ""))
1884 (use (match_operand 3 "immediate_operand" ""))
1885 (clobber (scratch))]
1888 [(set (match_dup 0) (match_dup 1))
1889 (use (match_dup 2))])]
1890 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1893 [(set (match_operand:BLK 0 "memory_operand" "")
1894 (match_operand:BLK 1 "memory_operand" ""))
1895 (use (match_operand 2 "register_operand" ""))
1896 (use (match_operand 3 "memory_operand" ""))
1897 (clobber (scratch))]
1900 [(unspec [(match_dup 2) (match_dup 3)
1901 (const_int 0)] UNSPEC_EXECUTE)
1902 (set (match_dup 0) (match_dup 1))
1903 (use (const_int 1))])]
1907 [(set (match_operand:BLK 0 "memory_operand" "")
1908 (match_operand:BLK 1 "memory_operand" ""))
1909 (use (match_operand 2 "register_operand" ""))
1910 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1911 (clobber (match_operand 3 "register_operand" ""))]
1912 "reload_completed && TARGET_CPU_ZARCH"
1913 [(set (match_dup 3) (label_ref (match_dup 4)))
1915 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1916 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1917 (set (match_dup 0) (match_dup 1))
1918 (use (const_int 1))])]
1919 "operands[4] = gen_label_rtx ();")
1921 ; Move a block of arbitrary length.
1923 (define_expand "movmem_long"
1925 [(clobber (match_dup 2))
1926 (clobber (match_dup 3))
1927 (set (match_operand:BLK 0 "memory_operand" "")
1928 (match_operand:BLK 1 "memory_operand" ""))
1929 (use (match_operand 2 "general_operand" ""))
1931 (clobber (reg:CC CC_REGNUM))])]
1934 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1935 rtx reg0 = gen_reg_rtx (dword_mode);
1936 rtx reg1 = gen_reg_rtx (dword_mode);
1937 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1938 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1939 rtx len0 = gen_lowpart (Pmode, reg0);
1940 rtx len1 = gen_lowpart (Pmode, reg1);
1942 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1943 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1944 emit_move_insn (len0, operands[2]);
1946 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1947 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1948 emit_move_insn (len1, operands[2]);
1950 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1951 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1956 (define_insn "*movmem_long"
1957 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
1958 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
1959 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
1960 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
1963 (clobber (reg:CC CC_REGNUM))]
1965 "mvcle\t%0,%1,0\;jo\t.-4"
1966 [(set_attr "length" "8")
1967 (set_attr "type" "vs")])
1970 ; setmemM instruction pattern(s).
1973 (define_expand "setmem<mode>"
1974 [(set (match_operand:BLK 0 "memory_operand" "")
1975 (match_operand:QI 2 "general_operand" ""))
1976 (use (match_operand:GPR 1 "general_operand" ""))
1977 (match_operand 3 "" "")]
1979 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
1981 ; Clear a block that is up to 256 bytes in length.
1982 ; The block length is taken as (operands[1] % 256) + 1.
1984 (define_expand "clrmem_short"
1986 [(set (match_operand:BLK 0 "memory_operand" "")
1988 (use (match_operand 1 "nonmemory_operand" ""))
1989 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1990 (clobber (match_dup 2))
1991 (clobber (reg:CC CC_REGNUM))])]
1993 "operands[2] = gen_rtx_SCRATCH (Pmode);")
1995 (define_insn "*clrmem_short"
1996 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1998 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
1999 (use (match_operand 2 "immediate_operand" "X,R,X"))
2000 (clobber (match_scratch 3 "=X,X,&a"))
2001 (clobber (reg:CC CC_REGNUM))]
2002 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2003 && GET_MODE (operands[3]) == Pmode"
2005 [(set_attr "type" "cs")])
2008 [(set (match_operand:BLK 0 "memory_operand" "")
2010 (use (match_operand 1 "const_int_operand" ""))
2011 (use (match_operand 2 "immediate_operand" ""))
2013 (clobber (reg:CC CC_REGNUM))]
2016 [(set (match_dup 0) (const_int 0))
2018 (clobber (reg:CC CC_REGNUM))])]
2019 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2022 [(set (match_operand:BLK 0 "memory_operand" "")
2024 (use (match_operand 1 "register_operand" ""))
2025 (use (match_operand 2 "memory_operand" ""))
2027 (clobber (reg:CC CC_REGNUM))]
2030 [(unspec [(match_dup 1) (match_dup 2)
2031 (const_int 0)] UNSPEC_EXECUTE)
2032 (set (match_dup 0) (const_int 0))
2034 (clobber (reg:CC CC_REGNUM))])]
2038 [(set (match_operand:BLK 0 "memory_operand" "")
2040 (use (match_operand 1 "register_operand" ""))
2041 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2042 (clobber (match_operand 2 "register_operand" ""))
2043 (clobber (reg:CC CC_REGNUM))]
2044 "reload_completed && TARGET_CPU_ZARCH"
2045 [(set (match_dup 2) (label_ref (match_dup 3)))
2047 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2048 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2049 (set (match_dup 0) (const_int 0))
2051 (clobber (reg:CC CC_REGNUM))])]
2052 "operands[3] = gen_label_rtx ();")
2054 ; Initialize a block of arbitrary length with (operands[2] % 256).
2056 (define_expand "setmem_long"
2058 [(clobber (match_dup 1))
2059 (set (match_operand:BLK 0 "memory_operand" "")
2060 (match_operand 2 "shift_count_operand" ""))
2061 (use (match_operand 1 "general_operand" ""))
2063 (clobber (reg:CC CC_REGNUM))])]
2066 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2067 rtx reg0 = gen_reg_rtx (dword_mode);
2068 rtx reg1 = gen_reg_rtx (dword_mode);
2069 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2070 rtx len0 = gen_lowpart (Pmode, reg0);
2072 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2073 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2074 emit_move_insn (len0, operands[1]);
2076 emit_move_insn (reg1, const0_rtx);
2078 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2083 (define_insn "*setmem_long"
2084 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2085 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2086 (match_operand 2 "shift_count_operand" "Y"))
2088 (use (match_operand:<DBL> 1 "register_operand" "d"))
2089 (clobber (reg:CC CC_REGNUM))]
2091 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2092 [(set_attr "length" "8")
2093 (set_attr "type" "vs")])
2096 ; cmpmemM instruction pattern(s).
2099 (define_expand "cmpmemsi"
2100 [(set (match_operand:SI 0 "register_operand" "")
2101 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2102 (match_operand:BLK 2 "memory_operand" "") ) )
2103 (use (match_operand:SI 3 "general_operand" ""))
2104 (use (match_operand:SI 4 "" ""))]
2106 "s390_expand_cmpmem (operands[0], operands[1],
2107 operands[2], operands[3]); DONE;")
2109 ; Compare a block that is up to 256 bytes in length.
2110 ; The block length is taken as (operands[2] % 256) + 1.
2112 (define_expand "cmpmem_short"
2114 [(set (reg:CCU CC_REGNUM)
2115 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2116 (match_operand:BLK 1 "memory_operand" "")))
2117 (use (match_operand 2 "nonmemory_operand" ""))
2118 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2119 (clobber (match_dup 3))])]
2121 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2123 (define_insn "*cmpmem_short"
2124 [(set (reg:CCU CC_REGNUM)
2125 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2126 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2127 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2128 (use (match_operand 3 "immediate_operand" "X,R,X"))
2129 (clobber (match_scratch 4 "=X,X,&a"))]
2130 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2131 && GET_MODE (operands[4]) == Pmode"
2133 [(set_attr "type" "cs")])
2136 [(set (reg:CCU CC_REGNUM)
2137 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2138 (match_operand:BLK 1 "memory_operand" "")))
2139 (use (match_operand 2 "const_int_operand" ""))
2140 (use (match_operand 3 "immediate_operand" ""))
2141 (clobber (scratch))]
2144 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2145 (use (match_dup 2))])]
2146 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2149 [(set (reg:CCU CC_REGNUM)
2150 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2151 (match_operand:BLK 1 "memory_operand" "")))
2152 (use (match_operand 2 "register_operand" ""))
2153 (use (match_operand 3 "memory_operand" ""))
2154 (clobber (scratch))]
2157 [(unspec [(match_dup 2) (match_dup 3)
2158 (const_int 0)] UNSPEC_EXECUTE)
2159 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2160 (use (const_int 1))])]
2164 [(set (reg:CCU CC_REGNUM)
2165 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2166 (match_operand:BLK 1 "memory_operand" "")))
2167 (use (match_operand 2 "register_operand" ""))
2168 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2169 (clobber (match_operand 3 "register_operand" ""))]
2170 "reload_completed && TARGET_CPU_ZARCH"
2171 [(set (match_dup 3) (label_ref (match_dup 4)))
2173 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2174 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2175 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2176 (use (const_int 1))])]
2177 "operands[4] = gen_label_rtx ();")
2179 ; Compare a block of arbitrary length.
2181 (define_expand "cmpmem_long"
2183 [(clobber (match_dup 2))
2184 (clobber (match_dup 3))
2185 (set (reg:CCU CC_REGNUM)
2186 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2187 (match_operand:BLK 1 "memory_operand" "")))
2188 (use (match_operand 2 "general_operand" ""))
2189 (use (match_dup 3))])]
2192 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2193 rtx reg0 = gen_reg_rtx (dword_mode);
2194 rtx reg1 = gen_reg_rtx (dword_mode);
2195 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2196 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2197 rtx len0 = gen_lowpart (Pmode, reg0);
2198 rtx len1 = gen_lowpart (Pmode, reg1);
2200 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2201 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2202 emit_move_insn (len0, operands[2]);
2204 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2205 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2206 emit_move_insn (len1, operands[2]);
2208 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2209 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2214 (define_insn "*cmpmem_long"
2215 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2216 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2217 (set (reg:CCU CC_REGNUM)
2218 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2219 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2221 (use (match_dup 3))]
2223 "clcle\t%0,%1,0\;jo\t.-4"
2224 [(set_attr "length" "8")
2225 (set_attr "type" "vs")])
2227 ; Convert CCUmode condition code to integer.
2228 ; Result is zero if EQ, positive if LTU, negative if GTU.
2230 (define_insn_and_split "cmpint"
2231 [(set (match_operand:SI 0 "register_operand" "=d")
2232 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2234 (clobber (reg:CC CC_REGNUM))]
2238 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2240 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2241 (clobber (reg:CC CC_REGNUM))])])
2243 (define_insn_and_split "*cmpint_cc"
2244 [(set (reg CC_REGNUM)
2245 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2248 (set (match_operand:SI 0 "register_operand" "=d")
2249 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2250 "s390_match_ccmode (insn, CCSmode)"
2252 "&& reload_completed"
2253 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2255 [(set (match_dup 2) (match_dup 3))
2256 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2258 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2259 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2260 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2263 (define_insn_and_split "*cmpint_sign"
2264 [(set (match_operand:DI 0 "register_operand" "=d")
2265 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2267 (clobber (reg:CC CC_REGNUM))]
2270 "&& reload_completed"
2271 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2273 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2274 (clobber (reg:CC CC_REGNUM))])])
2276 (define_insn_and_split "*cmpint_sign_cc"
2277 [(set (reg CC_REGNUM)
2278 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2279 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2281 (const_int 32)) (const_int 32))
2283 (set (match_operand:DI 0 "register_operand" "=d")
2284 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2285 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2287 "&& reload_completed"
2288 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2290 [(set (match_dup 2) (match_dup 3))
2291 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2293 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2294 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2295 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2300 ;;- Conversion instructions.
2304 (define_insn "*sethigh<mode>si"
2305 [(set (match_operand:SI 0 "register_operand" "=d,d")
2306 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2307 (clobber (reg:CC CC_REGNUM))]
2310 icm\t%0,<icm_hi>,%S1
2311 icmy\t%0,<icm_hi>,%S1"
2312 [(set_attr "op_type" "RS,RSY")])
2314 (define_insn "*sethighqidi_64"
2315 [(set (match_operand:DI 0 "register_operand" "=d")
2316 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2317 (clobber (reg:CC CC_REGNUM))]
2320 [(set_attr "op_type" "RSY")])
2322 (define_insn "*sethighqidi_31"
2323 [(set (match_operand:DI 0 "register_operand" "=d,d")
2324 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2325 (clobber (reg:CC CC_REGNUM))]
2330 [(set_attr "op_type" "RS,RSY")])
2332 (define_insn_and_split "*extractqi"
2333 [(set (match_operand:SI 0 "register_operand" "=d")
2334 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2335 (match_operand 2 "const_int_operand" "n")
2337 (clobber (reg:CC CC_REGNUM))]
2339 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2341 "&& reload_completed"
2343 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2344 (clobber (reg:CC CC_REGNUM))])
2345 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2347 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2348 operands[1] = change_address (operands[1], QImode, 0);
2351 (define_insn_and_split "*extracthi"
2352 [(set (match_operand:SI 0 "register_operand" "=d")
2353 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2354 (match_operand 2 "const_int_operand" "n")
2356 (clobber (reg:CC CC_REGNUM))]
2358 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2360 "&& reload_completed"
2362 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2363 (clobber (reg:CC CC_REGNUM))])
2364 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2366 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2367 operands[1] = change_address (operands[1], HImode, 0);
2371 ; extendsidi2 instruction pattern(s).
2374 (define_expand "extendsidi2"
2375 [(set (match_operand:DI 0 "register_operand" "")
2376 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2382 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2383 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2384 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2385 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2391 (define_insn "*extendsidi2"
2392 [(set (match_operand:DI 0 "register_operand" "=d,d")
2393 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2398 [(set_attr "op_type" "RRE,RXY")])
2401 ; extend(hi|qi)di2 instruction pattern(s).
2404 (define_expand "extend<mode>di2"
2405 [(set (match_operand:DI 0 "register_operand" "")
2406 (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2412 rtx tmp = gen_reg_rtx (SImode);
2413 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2414 emit_insn (gen_extendsidi2 (operands[0], tmp));
2419 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2420 GET_MODE_BITSIZE (<MODE>mode));
2421 operands[1] = gen_lowpart (DImode, operands[1]);
2422 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2423 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2429 (define_insn "*extendhidi2"
2430 [(set (match_operand:DI 0 "register_operand" "=d")
2431 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2434 [(set_attr "op_type" "RXY")])
2436 (define_insn "*extendqidi2"
2437 [(set (match_operand:DI 0 "register_operand" "=d")
2438 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2439 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2441 [(set_attr "op_type" "RXY")])
2443 (define_insn_and_split "*extendqidi2_short_displ"
2444 [(set (match_operand:DI 0 "register_operand" "=d")
2445 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2446 (clobber (reg:CC CC_REGNUM))]
2447 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2449 "&& reload_completed"
2451 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2452 (clobber (reg:CC CC_REGNUM))])
2454 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2455 (clobber (reg:CC CC_REGNUM))])]
2459 ; extend(hi|qi)si2 instruction pattern(s).
2462 (define_expand "extend<mode>si2"
2463 [(set (match_operand:SI 0 "register_operand" "")
2464 (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2468 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2469 GET_MODE_BITSIZE(<MODE>mode));
2470 operands[1] = gen_lowpart (SImode, operands[1]);
2471 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2472 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2477 (define_insn "*extendhisi2"
2478 [(set (match_operand:SI 0 "register_operand" "=d,d")
2479 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2484 [(set_attr "op_type" "RX,RXY")])
2486 (define_insn "*extendqisi2"
2487 [(set (match_operand:SI 0 "register_operand" "=d")
2488 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2489 "TARGET_LONG_DISPLACEMENT"
2491 [(set_attr "op_type" "RXY")])
2493 (define_insn_and_split "*extendqisi2_short_displ"
2494 [(set (match_operand:SI 0 "register_operand" "=d")
2495 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2496 (clobber (reg:CC CC_REGNUM))]
2497 "!TARGET_LONG_DISPLACEMENT"
2499 "&& reload_completed"
2501 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2502 (clobber (reg:CC CC_REGNUM))])
2504 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2505 (clobber (reg:CC CC_REGNUM))])]
2509 ; extendqihi2 instruction pattern(s).
2514 ; zero_extendsidi2 instruction pattern(s).
2517 (define_expand "zero_extendsidi2"
2518 [(set (match_operand:DI 0 "register_operand" "")
2519 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2525 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2526 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2527 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2533 (define_insn "*zero_extendsidi2"
2534 [(set (match_operand:DI 0 "register_operand" "=d,d")
2535 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2540 [(set_attr "op_type" "RRE,RXY")])
2543 ; zero_extend(hi|qi)di2 instruction pattern(s).
2546 (define_expand "zero_extend<mode>di2"
2547 [(set (match_operand:DI 0 "register_operand" "")
2548 (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2554 rtx tmp = gen_reg_rtx (SImode);
2555 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2556 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2561 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2562 GET_MODE_BITSIZE(<MODE>mode));
2563 operands[1] = gen_lowpart (DImode, operands[1]);
2564 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2565 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2571 (define_insn "*zero_extend<mode>di2"
2572 [(set (match_operand:DI 0 "register_operand" "=d")
2573 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2576 [(set_attr "op_type" "RXY")])
2579 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2582 (define_insn "*llgt_sidi"
2583 [(set (match_operand:DI 0 "register_operand" "=d")
2584 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2585 (const_int 2147483647)))]
2588 [(set_attr "op_type" "RXE")])
2590 (define_insn_and_split "*llgt_sidi_split"
2591 [(set (match_operand:DI 0 "register_operand" "=d")
2592 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2593 (const_int 2147483647)))
2594 (clobber (reg:CC CC_REGNUM))]
2597 "&& reload_completed"
2599 (and:DI (subreg:DI (match_dup 1) 0)
2600 (const_int 2147483647)))]
2603 (define_insn "*llgt_sisi"
2604 [(set (match_operand:SI 0 "register_operand" "=d,d")
2605 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2606 (const_int 2147483647)))]
2611 [(set_attr "op_type" "RRE,RXE")])
2613 (define_insn "*llgt_didi"
2614 [(set (match_operand:DI 0 "register_operand" "=d,d")
2615 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2616 (const_int 2147483647)))]
2621 [(set_attr "op_type" "RRE,RXE")])
2624 [(set (match_operand:GPR 0 "register_operand" "")
2625 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2626 (const_int 2147483647)))
2627 (clobber (reg:CC CC_REGNUM))]
2628 "TARGET_64BIT && reload_completed"
2630 (and:GPR (match_dup 1)
2631 (const_int 2147483647)))]
2635 ; zero_extend(hi|qi)si2 instruction pattern(s).
2638 (define_expand "zero_extend<mode>si2"
2639 [(set (match_operand:SI 0 "register_operand" "")
2640 (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2644 operands[1] = gen_lowpart (SImode, operands[1]);
2645 emit_insn (gen_andsi3 (operands[0], operands[1],
2646 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2651 (define_insn "*zero_extend<mode>si2_64"
2652 [(set (match_operand:SI 0 "register_operand" "=d")
2653 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2656 [(set_attr "op_type" "RXY")])
2658 (define_insn_and_split "*zero_extendhisi2_31"
2659 [(set (match_operand:SI 0 "register_operand" "=&d")
2660 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2661 (clobber (reg:CC CC_REGNUM))]
2664 "&& reload_completed"
2665 [(set (match_dup 0) (const_int 0))
2667 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2668 (clobber (reg:CC CC_REGNUM))])]
2669 "operands[2] = gen_lowpart (HImode, operands[0]);")
2671 (define_insn_and_split "*zero_extendqisi2_31"
2672 [(set (match_operand:SI 0 "register_operand" "=&d")
2673 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2676 "&& reload_completed"
2677 [(set (match_dup 0) (const_int 0))
2678 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2679 "operands[2] = gen_lowpart (QImode, operands[0]);")
2682 ; zero_extendqihi2 instruction pattern(s).
2685 (define_expand "zero_extendqihi2"
2686 [(set (match_operand:HI 0 "register_operand" "")
2687 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2691 operands[1] = gen_lowpart (HImode, operands[1]);
2692 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2697 (define_insn "*zero_extendqihi2_64"
2698 [(set (match_operand:HI 0 "register_operand" "=d")
2699 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2702 [(set_attr "op_type" "RXY")])
2704 (define_insn_and_split "*zero_extendqihi2_31"
2705 [(set (match_operand:HI 0 "register_operand" "=&d")
2706 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2709 "&& reload_completed"
2710 [(set (match_dup 0) (const_int 0))
2711 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2712 "operands[2] = gen_lowpart (QImode, operands[0]);")
2716 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2719 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2720 [(set (match_operand:GPR 0 "register_operand" "")
2721 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2722 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2724 rtx label1 = gen_label_rtx ();
2725 rtx label2 = gen_label_rtx ();
2726 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2727 REAL_VALUE_TYPE cmp, sub;
2729 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2730 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2731 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2733 emit_insn (gen_cmp<FPR:mode> (operands[1],
2734 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2735 emit_jump_insn (gen_blt (label1));
2736 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2737 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2738 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2742 emit_label (label1);
2743 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2744 operands[1], GEN_INT(5)));
2745 emit_label (label2);
2749 (define_expand "fix_trunc<FPR:mode>di2"
2750 [(set (match_operand:DI 0 "register_operand" "")
2751 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2752 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2754 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2755 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2760 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2761 [(set (match_operand:GPR 0 "register_operand" "=d")
2762 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2763 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2764 (clobber (reg:CC CC_REGNUM))]
2765 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2766 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2767 [(set_attr "op_type" "RRE")
2768 (set_attr "type" "ftoi")])
2771 ; fix_truncdfsi2 instruction pattern(s).
2774 (define_expand "fix_truncdfsi2"
2775 [(set (match_operand:SI 0 "register_operand" "")
2776 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2779 if (TARGET_IBM_FLOAT)
2781 /* This is the algorithm from POP chapter A.5.7.2. */
2783 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2784 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2785 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2787 operands[1] = force_reg (DFmode, operands[1]);
2788 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2789 two31r, two32, temp));
2793 operands[1] = force_reg (DFmode, operands[1]);
2794 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2800 (define_insn "fix_truncdfsi2_ibm"
2801 [(set (match_operand:SI 0 "register_operand" "=d")
2802 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2803 (use (match_operand:DI 2 "immediate_operand" "m"))
2804 (use (match_operand:DI 3 "immediate_operand" "m"))
2805 (use (match_operand:BLK 4 "memory_operand" "m"))
2806 (clobber (reg:CC CC_REGNUM))]
2807 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2809 output_asm_insn ("sd\t%1,%2", operands);
2810 output_asm_insn ("aw\t%1,%3", operands);
2811 output_asm_insn ("std\t%1,%4", operands);
2812 output_asm_insn ("xi\t%N4,128", operands);
2815 [(set_attr "length" "20")])
2818 ; fix_truncsfsi2 instruction pattern(s).
2821 (define_expand "fix_truncsfsi2"
2822 [(set (match_operand:SI 0 "register_operand" "")
2823 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2826 if (TARGET_IBM_FLOAT)
2828 /* Convert to DFmode and then use the POP algorithm. */
2829 rtx temp = gen_reg_rtx (DFmode);
2830 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2831 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2835 operands[1] = force_reg (SFmode, operands[1]);
2836 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2843 ; floatdi(df|sf)2 instruction pattern(s).
2846 (define_insn "floatdi<mode>2"
2847 [(set (match_operand:FPR 0 "register_operand" "=f")
2848 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2849 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2851 [(set_attr "op_type" "RRE")
2852 (set_attr "type" "itof" )])
2855 ; floatsidf2 instruction pattern(s).
2858 (define_expand "floatsidf2"
2859 [(set (match_operand:DF 0 "register_operand" "")
2860 (float:DF (match_operand:SI 1 "register_operand" "")))]
2863 if (TARGET_IBM_FLOAT)
2865 /* This is the algorithm from POP chapter A.5.7.1. */
2867 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2868 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2870 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2875 (define_insn "floatsidf2_ieee"
2876 [(set (match_operand:DF 0 "register_operand" "=f")
2877 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2878 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2880 [(set_attr "op_type" "RRE")
2881 (set_attr "type" "itof" )])
2883 (define_insn "floatsidf2_ibm"
2884 [(set (match_operand:DF 0 "register_operand" "=f")
2885 (float:DF (match_operand:SI 1 "register_operand" "d")))
2886 (use (match_operand:DI 2 "immediate_operand" "m"))
2887 (use (match_operand:BLK 3 "memory_operand" "m"))
2888 (clobber (reg:CC CC_REGNUM))]
2889 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2891 output_asm_insn ("st\t%1,%N3", operands);
2892 output_asm_insn ("xi\t%N3,128", operands);
2893 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
2894 output_asm_insn ("ld\t%0,%3", operands);
2897 [(set_attr "length" "20")])
2900 ; floatsisf2 instruction pattern(s).
2903 (define_expand "floatsisf2"
2904 [(set (match_operand:SF 0 "register_operand" "")
2905 (float:SF (match_operand:SI 1 "register_operand" "")))]
2908 if (TARGET_IBM_FLOAT)
2910 /* Use the POP algorithm to convert to DFmode and then truncate. */
2911 rtx temp = gen_reg_rtx (DFmode);
2912 emit_insn (gen_floatsidf2 (temp, operands[1]));
2913 emit_insn (gen_truncdfsf2 (operands[0], temp));
2918 (define_insn "floatsisf2_ieee"
2919 [(set (match_operand:SF 0 "register_operand" "=f")
2920 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2921 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2923 [(set_attr "op_type" "RRE")
2924 (set_attr "type" "itof" )])
2927 ; truncdfsf2 instruction pattern(s).
2930 (define_expand "truncdfsf2"
2931 [(set (match_operand:SF 0 "register_operand" "")
2932 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
2936 (define_insn "truncdfsf2_ieee"
2937 [(set (match_operand:SF 0 "register_operand" "=f")
2938 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2939 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2941 [(set_attr "op_type" "RRE")])
2943 (define_insn "truncdfsf2_ibm"
2944 [(set (match_operand:SF 0 "register_operand" "=f,f")
2945 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
2946 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2950 [(set_attr "op_type" "RR,RX")
2951 (set_attr "type" "floadsf")])
2954 ; extendsfdf2 instruction pattern(s).
2957 (define_expand "extendsfdf2"
2958 [(set (match_operand:DF 0 "register_operand" "")
2959 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2962 if (TARGET_IBM_FLOAT)
2964 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2969 (define_insn "extendsfdf2_ieee"
2970 [(set (match_operand:DF 0 "register_operand" "=f,f")
2971 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
2972 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2976 [(set_attr "op_type" "RRE,RXE")
2977 (set_attr "type" "floadsf")])
2979 (define_insn "extendsfdf2_ibm"
2980 [(set (match_operand:DF 0 "register_operand" "=f,f")
2981 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
2982 (clobber (reg:CC CC_REGNUM))]
2983 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2985 sdr\t%0,%0\;ler\t%0,%1
2986 sdr\t%0,%0\;le\t%0,%1"
2987 [(set_attr "length" "4,6")
2988 (set_attr "type" "floadsf")])
2992 ;; ARITHMETIC OPERATIONS
2994 ; arithmetic operations set the ConditionCode,
2995 ; because of unpredictable Bits in Register for Halfword and Byte
2996 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2999 ;;- Add instructions.
3003 ; addti3 instruction pattern(s).
3006 (define_insn_and_split "addti3"
3007 [(set (match_operand:TI 0 "register_operand" "=&d")
3008 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3009 (match_operand:TI 2 "general_operand" "do") ) )
3010 (clobber (reg:CC CC_REGNUM))]
3013 "&& reload_completed"
3015 [(set (reg:CCL1 CC_REGNUM)
3016 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3018 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3020 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3021 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3022 (clobber (reg:CC CC_REGNUM))])]
3023 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3024 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3025 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3026 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3027 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3028 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3031 ; adddi3 instruction pattern(s).
3034 (define_insn "*adddi3_sign"
3035 [(set (match_operand:DI 0 "register_operand" "=d,d")
3036 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3037 (match_operand:DI 1 "register_operand" "0,0")))
3038 (clobber (reg:CC CC_REGNUM))]
3043 [(set_attr "op_type" "RRE,RXY")])
3045 (define_insn "*adddi3_zero_cc"
3046 [(set (reg CC_REGNUM)
3047 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3048 (match_operand:DI 1 "register_operand" "0,0"))
3050 (set (match_operand:DI 0 "register_operand" "=d,d")
3051 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3052 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3056 [(set_attr "op_type" "RRE,RXY")])
3058 (define_insn "*adddi3_zero_cconly"
3059 [(set (reg CC_REGNUM)
3060 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3061 (match_operand:DI 1 "register_operand" "0,0"))
3063 (clobber (match_scratch:DI 0 "=d,d"))]
3064 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3068 [(set_attr "op_type" "RRE,RXY")])
3070 (define_insn "*adddi3_zero"
3071 [(set (match_operand:DI 0 "register_operand" "=d,d")
3072 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3073 (match_operand:DI 1 "register_operand" "0,0")))
3074 (clobber (reg:CC CC_REGNUM))]
3079 [(set_attr "op_type" "RRE,RXY")])
3081 (define_insn "*adddi3_imm_cc"
3082 [(set (reg CC_REGNUM)
3083 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3084 (match_operand:DI 2 "const_int_operand" "K"))
3086 (set (match_operand:DI 0 "register_operand" "=d")
3087 (plus:DI (match_dup 1) (match_dup 2)))]
3089 && s390_match_ccmode (insn, CCAmode)
3090 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3092 [(set_attr "op_type" "RI")])
3094 (define_insn "*adddi3_carry1_cc"
3095 [(set (reg CC_REGNUM)
3096 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3097 (match_operand:DI 2 "general_operand" "d,m"))
3099 (set (match_operand:DI 0 "register_operand" "=d,d")
3100 (plus:DI (match_dup 1) (match_dup 2)))]
3101 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3105 [(set_attr "op_type" "RRE,RXY")])
3107 (define_insn "*adddi3_carry1_cconly"
3108 [(set (reg CC_REGNUM)
3109 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3110 (match_operand:DI 2 "general_operand" "d,m"))
3112 (clobber (match_scratch:DI 0 "=d,d"))]
3113 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3117 [(set_attr "op_type" "RRE,RXY")])
3119 (define_insn "*adddi3_carry2_cc"
3120 [(set (reg CC_REGNUM)
3121 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3122 (match_operand:DI 2 "general_operand" "d,m"))
3124 (set (match_operand:DI 0 "register_operand" "=d,d")
3125 (plus:DI (match_dup 1) (match_dup 2)))]
3126 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3130 [(set_attr "op_type" "RRE,RXY")])
3132 (define_insn "*adddi3_carry2_cconly"
3133 [(set (reg CC_REGNUM)
3134 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3135 (match_operand:DI 2 "general_operand" "d,m"))
3137 (clobber (match_scratch:DI 0 "=d,d"))]
3138 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3142 [(set_attr "op_type" "RRE,RXY")])
3144 (define_insn "*adddi3_cc"
3145 [(set (reg CC_REGNUM)
3146 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3147 (match_operand:DI 2 "general_operand" "d,m"))
3149 (set (match_operand:DI 0 "register_operand" "=d,d")
3150 (plus:DI (match_dup 1) (match_dup 2)))]
3151 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3155 [(set_attr "op_type" "RRE,RXY")])
3157 (define_insn "*adddi3_cconly"
3158 [(set (reg CC_REGNUM)
3159 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3160 (match_operand:DI 2 "general_operand" "d,m"))
3162 (clobber (match_scratch:DI 0 "=d,d"))]
3163 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3167 [(set_attr "op_type" "RRE,RXY")])
3169 (define_insn "*adddi3_cconly2"
3170 [(set (reg CC_REGNUM)
3171 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3172 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3173 (clobber (match_scratch:DI 0 "=d,d"))]
3174 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3178 [(set_attr "op_type" "RRE,RXY")])
3180 (define_insn "*adddi3_64"
3181 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3182 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3183 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3184 (clobber (reg:CC CC_REGNUM))]
3190 [(set_attr "op_type" "RRE,RI,RXY")])
3192 (define_insn_and_split "*adddi3_31z"
3193 [(set (match_operand:DI 0 "register_operand" "=&d")
3194 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3195 (match_operand:DI 2 "general_operand" "do") ) )
3196 (clobber (reg:CC CC_REGNUM))]
3197 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3199 "&& reload_completed"
3201 [(set (reg:CCL1 CC_REGNUM)
3202 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3204 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3206 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3207 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3208 (clobber (reg:CC CC_REGNUM))])]
3209 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3210 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3211 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3212 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3213 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3214 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3216 (define_insn_and_split "*adddi3_31"
3217 [(set (match_operand:DI 0 "register_operand" "=&d")
3218 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3219 (match_operand:DI 2 "general_operand" "do") ) )
3220 (clobber (reg:CC CC_REGNUM))]
3223 "&& reload_completed"
3225 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3226 (clobber (reg:CC CC_REGNUM))])
3228 [(set (reg:CCL1 CC_REGNUM)
3229 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3231 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3233 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3235 (label_ref (match_dup 9))))
3237 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3238 (clobber (reg:CC CC_REGNUM))])
3240 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3241 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3242 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3243 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3244 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3245 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3246 operands[9] = gen_label_rtx ();")
3248 (define_expand "adddi3"
3250 [(set (match_operand:DI 0 "register_operand" "")
3251 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3252 (match_operand:DI 2 "general_operand" "")))
3253 (clobber (reg:CC CC_REGNUM))])]
3258 ; addsi3 instruction pattern(s).
3261 (define_insn "*addsi3_imm_cc"
3262 [(set (reg CC_REGNUM)
3263 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3264 (match_operand:SI 2 "const_int_operand" "K"))
3266 (set (match_operand:SI 0 "register_operand" "=d")
3267 (plus:SI (match_dup 1) (match_dup 2)))]
3268 "s390_match_ccmode (insn, CCAmode)
3269 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3271 [(set_attr "op_type" "RI")])
3273 (define_insn "*addsi3_carry1_cc"
3274 [(set (reg CC_REGNUM)
3275 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3276 (match_operand:SI 2 "general_operand" "d,R,T"))
3278 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3279 (plus:SI (match_dup 1) (match_dup 2)))]
3280 "s390_match_ccmode (insn, CCL1mode)"
3285 [(set_attr "op_type" "RR,RX,RXY")])
3287 (define_insn "*addsi3_carry1_cconly"
3288 [(set (reg CC_REGNUM)
3289 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3290 (match_operand:SI 2 "general_operand" "d,R,T"))
3292 (clobber (match_scratch:SI 0 "=d,d,d"))]
3293 "s390_match_ccmode (insn, CCL1mode)"
3298 [(set_attr "op_type" "RR,RX,RXY")])
3300 (define_insn "*addsi3_carry2_cc"
3301 [(set (reg CC_REGNUM)
3302 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3303 (match_operand:SI 2 "general_operand" "d,R,T"))
3305 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3306 (plus:SI (match_dup 1) (match_dup 2)))]
3307 "s390_match_ccmode (insn, CCL1mode)"
3312 [(set_attr "op_type" "RR,RX,RXY")])
3314 (define_insn "*addsi3_carry2_cconly"
3315 [(set (reg CC_REGNUM)
3316 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3317 (match_operand:SI 2 "general_operand" "d,R,T"))
3319 (clobber (match_scratch:SI 0 "=d,d,d"))]
3320 "s390_match_ccmode (insn, CCL1mode)"
3325 [(set_attr "op_type" "RR,RX,RXY")])
3327 (define_insn "*addsi3_cc"
3328 [(set (reg CC_REGNUM)
3329 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3330 (match_operand:SI 2 "general_operand" "d,R,T"))
3332 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3333 (plus:SI (match_dup 1) (match_dup 2)))]
3334 "s390_match_ccmode (insn, CCLmode)"
3339 [(set_attr "op_type" "RR,RX,RXY")])
3341 (define_insn "*addsi3_cconly"
3342 [(set (reg CC_REGNUM)
3343 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3344 (match_operand:SI 2 "general_operand" "d,R,T"))
3346 (clobber (match_scratch:SI 0 "=d,d,d"))]
3347 "s390_match_ccmode (insn, CCLmode)"
3352 [(set_attr "op_type" "RR,RX,RXY")])
3354 (define_insn "*addsi3_cconly2"
3355 [(set (reg CC_REGNUM)
3356 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3357 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3358 (clobber (match_scratch:SI 0 "=d,d,d"))]
3359 "s390_match_ccmode (insn, CCLmode)"
3364 [(set_attr "op_type" "RR,RX,RXY")])
3366 (define_insn "*addsi3_sign"
3367 [(set (match_operand:SI 0 "register_operand" "=d,d")
3368 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3369 (match_operand:SI 1 "register_operand" "0,0")))
3370 (clobber (reg:CC CC_REGNUM))]
3375 [(set_attr "op_type" "RX,RXY")])
3377 (define_insn "addsi3"
3378 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3379 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3380 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3381 (clobber (reg:CC CC_REGNUM))]
3388 [(set_attr "op_type" "RR,RI,RX,RXY")])
3391 ; add(df|sf)3 instruction pattern(s).
3394 (define_expand "add<mode>3"
3396 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3397 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3398 (match_operand:FPR 2 "general_operand" "f,R")))
3399 (clobber (reg:CC CC_REGNUM))])]
3403 (define_insn "*add<mode>3"
3404 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3405 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3406 (match_operand:FPR 2 "general_operand" "f,R")))
3407 (clobber (reg:CC CC_REGNUM))]
3408 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3412 [(set_attr "op_type" "RRE,RXE")
3413 (set_attr "type" "fsimp<mode>")])
3415 (define_insn "*add<mode>3_cc"
3416 [(set (reg CC_REGNUM)
3417 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3418 (match_operand:FPR 2 "general_operand" "f,R"))
3419 (match_operand:FPR 3 "const0_operand" "")))
3420 (set (match_operand:FPR 0 "register_operand" "=f,f")
3421 (plus:FPR (match_dup 1) (match_dup 2)))]
3422 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3426 [(set_attr "op_type" "RRE,RXE")
3427 (set_attr "type" "fsimp<mode>")])
3429 (define_insn "*add<mode>3_cconly"
3430 [(set (reg CC_REGNUM)
3431 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3432 (match_operand:FPR 2 "general_operand" "f,R"))
3433 (match_operand:FPR 3 "const0_operand" "")))
3434 (clobber (match_scratch:FPR 0 "=f,f"))]
3435 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3439 [(set_attr "op_type" "RRE,RXE")
3440 (set_attr "type" "fsimp<mode>")])
3442 (define_insn "*add<mode>3_ibm"
3443 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3444 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3445 (match_operand:FPR 2 "general_operand" "f,R")))
3446 (clobber (reg:CC CC_REGNUM))]
3447 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3451 [(set_attr "op_type" "RR,RX")
3452 (set_attr "type" "fsimp<mode>")])
3456 ;;- Subtract instructions.
3460 ; subti3 instruction pattern(s).
3463 (define_insn_and_split "subti3"
3464 [(set (match_operand:TI 0 "register_operand" "=&d")
3465 (minus:TI (match_operand:TI 1 "register_operand" "0")
3466 (match_operand:TI 2 "general_operand" "do") ) )
3467 (clobber (reg:CC CC_REGNUM))]
3470 "&& reload_completed"
3472 [(set (reg:CCL2 CC_REGNUM)
3473 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3475 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3477 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3478 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3479 (clobber (reg:CC CC_REGNUM))])]
3480 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3481 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3482 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3483 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3484 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3485 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3488 ; subdi3 instruction pattern(s).
3491 (define_insn "*subdi3_sign"
3492 [(set (match_operand:DI 0 "register_operand" "=d,d")
3493 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3494 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3495 (clobber (reg:CC CC_REGNUM))]
3500 [(set_attr "op_type" "RRE,RXY")])
3502 (define_insn "*subdi3_zero_cc"
3503 [(set (reg CC_REGNUM)
3504 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3505 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3507 (set (match_operand:DI 0 "register_operand" "=d,d")
3508 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3509 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3513 [(set_attr "op_type" "RRE,RXY")])
3515 (define_insn "*subdi3_zero_cconly"
3516 [(set (reg CC_REGNUM)
3517 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3518 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3520 (clobber (match_scratch:DI 0 "=d,d"))]
3521 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3525 [(set_attr "op_type" "RRE,RXY")])
3527 (define_insn "*subdi3_zero"
3528 [(set (match_operand:DI 0 "register_operand" "=d,d")
3529 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3530 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3531 (clobber (reg:CC CC_REGNUM))]
3536 [(set_attr "op_type" "RRE,RXY")])
3538 (define_insn "*subdi3_borrow_cc"
3539 [(set (reg CC_REGNUM)
3540 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3541 (match_operand:DI 2 "general_operand" "d,m"))
3543 (set (match_operand:DI 0 "register_operand" "=d,d")
3544 (minus:DI (match_dup 1) (match_dup 2)))]
3545 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3549 [(set_attr "op_type" "RRE,RXY")])
3551 (define_insn "*subdi3_borrow_cconly"
3552 [(set (reg CC_REGNUM)
3553 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3554 (match_operand:DI 2 "general_operand" "d,m"))
3556 (clobber (match_scratch:DI 0 "=d,d"))]
3557 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3561 [(set_attr "op_type" "RRE,RXY")])
3563 (define_insn "*subdi3_cc"
3564 [(set (reg CC_REGNUM)
3565 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3566 (match_operand:DI 2 "general_operand" "d,m"))
3568 (set (match_operand:DI 0 "register_operand" "=d,d")
3569 (minus:DI (match_dup 1) (match_dup 2)))]
3570 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3574 [(set_attr "op_type" "RRE,RXY")])
3576 (define_insn "*subdi3_cc2"
3577 [(set (reg CC_REGNUM)
3578 (compare (match_operand:DI 1 "register_operand" "0,0")
3579 (match_operand:DI 2 "general_operand" "d,m")))
3580 (set (match_operand:DI 0 "register_operand" "=d,d")
3581 (minus:DI (match_dup 1) (match_dup 2)))]
3582 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3586 [(set_attr "op_type" "RRE,RXY")])
3588 (define_insn "*subdi3_cconly"
3589 [(set (reg CC_REGNUM)
3590 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3591 (match_operand:DI 2 "general_operand" "d,m"))
3593 (clobber (match_scratch:DI 0 "=d,d"))]
3594 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3598 [(set_attr "op_type" "RRE,RXY")])
3600 (define_insn "*subdi3_cconly2"
3601 [(set (reg CC_REGNUM)
3602 (compare (match_operand:DI 1 "register_operand" "0,0")
3603 (match_operand:DI 2 "general_operand" "d,m")))
3604 (clobber (match_scratch:DI 0 "=d,d"))]
3605 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3609 [(set_attr "op_type" "RRE,RXY")])
3611 (define_insn "*subdi3_64"
3612 [(set (match_operand:DI 0 "register_operand" "=d,d")
3613 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3614 (match_operand:DI 2 "general_operand" "d,m") ) )
3615 (clobber (reg:CC CC_REGNUM))]
3620 [(set_attr "op_type" "RRE,RRE")])
3622 (define_insn_and_split "*subdi3_31z"
3623 [(set (match_operand:DI 0 "register_operand" "=&d")
3624 (minus:DI (match_operand:DI 1 "register_operand" "0")
3625 (match_operand:DI 2 "general_operand" "do") ) )
3626 (clobber (reg:CC CC_REGNUM))]
3627 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3629 "&& reload_completed"
3631 [(set (reg:CCL2 CC_REGNUM)
3632 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3634 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3636 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3637 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3638 (clobber (reg:CC CC_REGNUM))])]
3639 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3640 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3641 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3642 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3643 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3644 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3646 (define_insn_and_split "*subdi3_31"
3647 [(set (match_operand:DI 0 "register_operand" "=&d")
3648 (minus:DI (match_operand:DI 1 "register_operand" "0")
3649 (match_operand:DI 2 "general_operand" "do") ) )
3650 (clobber (reg:CC CC_REGNUM))]
3653 "&& reload_completed"
3655 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3656 (clobber (reg:CC CC_REGNUM))])
3658 [(set (reg:CCL2 CC_REGNUM)
3659 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3661 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3663 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3665 (label_ref (match_dup 9))))
3667 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3668 (clobber (reg:CC CC_REGNUM))])
3670 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3671 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3672 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3673 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3674 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3675 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3676 operands[9] = gen_label_rtx ();")
3678 (define_expand "subdi3"
3680 [(set (match_operand:DI 0 "register_operand" "")
3681 (minus:DI (match_operand:DI 1 "register_operand" "")
3682 (match_operand:DI 2 "general_operand" "")))
3683 (clobber (reg:CC CC_REGNUM))])]
3688 ; subsi3 instruction pattern(s).
3691 (define_insn "*subsi3_borrow_cc"
3692 [(set (reg CC_REGNUM)
3693 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3694 (match_operand:SI 2 "general_operand" "d,R,T"))
3696 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3697 (minus:SI (match_dup 1) (match_dup 2)))]
3698 "s390_match_ccmode (insn, CCL2mode)"
3703 [(set_attr "op_type" "RR,RX,RXY")])
3705 (define_insn "*subsi3_borrow_cconly"
3706 [(set (reg CC_REGNUM)
3707 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3708 (match_operand:SI 2 "general_operand" "d,R,T"))
3710 (clobber (match_scratch:SI 0 "=d,d,d"))]
3711 "s390_match_ccmode (insn, CCL2mode)"
3716 [(set_attr "op_type" "RR,RX,RXY")])
3718 (define_insn "*subsi3_cc"
3719 [(set (reg CC_REGNUM)
3720 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3721 (match_operand:SI 2 "general_operand" "d,R,T"))
3723 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3724 (minus:SI (match_dup 1) (match_dup 2)))]
3725 "s390_match_ccmode (insn, CCLmode)"
3730 [(set_attr "op_type" "RR,RX,RXY")])
3732 (define_insn "*subsi3_cc2"
3733 [(set (reg CC_REGNUM)
3734 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3735 (match_operand:SI 2 "general_operand" "d,R,T")))
3736 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3737 (minus:SI (match_dup 1) (match_dup 2)))]
3738 "s390_match_ccmode (insn, CCL3mode)"
3743 [(set_attr "op_type" "RR,RX,RXY")])
3745 (define_insn "*subsi3_cconly"
3746 [(set (reg CC_REGNUM)
3747 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3748 (match_operand:SI 2 "general_operand" "d,R,T"))
3750 (clobber (match_scratch:SI 0 "=d,d,d"))]
3751 "s390_match_ccmode (insn, CCLmode)"
3756 [(set_attr "op_type" "RR,RX,RXY")])
3758 (define_insn "*subsi3_cconly2"
3759 [(set (reg CC_REGNUM)
3760 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3761 (match_operand:SI 2 "general_operand" "d,R,T")))
3762 (clobber (match_scratch:SI 0 "=d,d,d"))]
3763 "s390_match_ccmode (insn, CCL3mode)"
3768 [(set_attr "op_type" "RR,RX,RXY")])
3770 (define_insn "*subsi3_sign"
3771 [(set (match_operand:SI 0 "register_operand" "=d,d")
3772 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3773 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3774 (clobber (reg:CC CC_REGNUM))]
3779 [(set_attr "op_type" "RX,RXY")])
3781 (define_insn "subsi3"
3782 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3783 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3784 (match_operand:SI 2 "general_operand" "d,R,T")))
3785 (clobber (reg:CC CC_REGNUM))]
3791 [(set_attr "op_type" "RR,RX,RXY")])
3795 ; sub(df|sf)3 instruction pattern(s).
3798 (define_expand "sub<mode>3"
3800 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3801 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3802 (match_operand:FPR 2 "general_operand" "f,R")))
3803 (clobber (reg:CC CC_REGNUM))])]
3807 (define_insn "*sub<mode>3"
3808 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3809 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3810 (match_operand:FPR 2 "general_operand" "f,R")))
3811 (clobber (reg:CC CC_REGNUM))]
3812 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3816 [(set_attr "op_type" "RRE,RXE")
3817 (set_attr "type" "fsimp<mode>")])
3819 (define_insn "*sub<mode>3_cc"
3820 [(set (reg CC_REGNUM)
3821 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3822 (match_operand:FPR 2 "general_operand" "f,R"))
3823 (match_operand:FPR 3 "const0_operand" "")))
3824 (set (match_operand:FPR 0 "register_operand" "=f,f")
3825 (minus:FPR (match_dup 1) (match_dup 2)))]
3826 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3830 [(set_attr "op_type" "RRE,RXE")
3831 (set_attr "type" "fsimp<mode>")])
3833 (define_insn "*sub<mode>3_cconly"
3834 [(set (reg CC_REGNUM)
3835 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3836 (match_operand:FPR 2 "general_operand" "f,R"))
3837 (match_operand:FPR 3 "const0_operand" "")))
3838 (clobber (match_scratch:FPR 0 "=f,f"))]
3839 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3843 [(set_attr "op_type" "RRE,RXE")
3844 (set_attr "type" "fsimp<mode>")])
3846 (define_insn "*sub<mode>3_ibm"
3847 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3848 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3849 (match_operand:FPR 2 "general_operand" "f,R")))
3850 (clobber (reg:CC CC_REGNUM))]
3851 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3855 [(set_attr "op_type" "RR,RX")
3856 (set_attr "type" "fsimp<mode>")])
3860 ;;- Conditional add/subtract instructions.
3864 ; add(di|si)cc instruction pattern(s).
3867 (define_insn "*add<mode>3_alc_cc"
3868 [(set (reg CC_REGNUM)
3870 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3871 (match_operand:GPR 2 "general_operand" "d,m"))
3872 (match_operand:GPR 3 "s390_alc_comparison" ""))
3874 (set (match_operand:GPR 0 "register_operand" "=d,d")
3875 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3876 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3880 [(set_attr "op_type" "RRE,RXY")])
3882 (define_insn "*add<mode>3_alc"
3883 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3884 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3885 (match_operand:GPR 2 "general_operand" "d,m"))
3886 (match_operand:GPR 3 "s390_alc_comparison" "")))
3887 (clobber (reg:CC CC_REGNUM))]
3892 [(set_attr "op_type" "RRE,RXY")])
3894 (define_insn "*sub<mode>3_slb_cc"
3895 [(set (reg CC_REGNUM)
3897 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3898 (match_operand:GPR 2 "general_operand" "d,m"))
3899 (match_operand:GPR 3 "s390_slb_comparison" ""))
3901 (set (match_operand:GPR 0 "register_operand" "=d,d")
3902 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3903 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3907 [(set_attr "op_type" "RRE,RXY")])
3909 (define_insn "*sub<mode>3_slb"
3910 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3911 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3912 (match_operand:GPR 2 "general_operand" "d,m"))
3913 (match_operand:GPR 3 "s390_slb_comparison" "")))
3914 (clobber (reg:CC CC_REGNUM))]
3919 [(set_attr "op_type" "RRE,RXY")])
3921 (define_expand "add<mode>cc"
3922 [(match_operand:GPR 0 "register_operand" "")
3923 (match_operand 1 "comparison_operator" "")
3924 (match_operand:GPR 2 "register_operand" "")
3925 (match_operand:GPR 3 "const_int_operand" "")]
3927 "if (!s390_expand_addcc (GET_CODE (operands[1]),
3928 s390_compare_op0, s390_compare_op1,
3929 operands[0], operands[2],
3930 operands[3])) FAIL; DONE;")
3933 ; scond instruction pattern(s).
3936 (define_insn_and_split "*scond<mode>"
3937 [(set (match_operand:GPR 0 "register_operand" "=&d")
3938 (match_operand:GPR 1 "s390_alc_comparison" ""))
3939 (clobber (reg:CC CC_REGNUM))]
3942 "&& reload_completed"
3943 [(set (match_dup 0) (const_int 0))
3945 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
3947 (clobber (reg:CC CC_REGNUM))])]
3950 (define_insn_and_split "*scond<mode>_neg"
3951 [(set (match_operand:GPR 0 "register_operand" "=&d")
3952 (match_operand:GPR 1 "s390_slb_comparison" ""))
3953 (clobber (reg:CC CC_REGNUM))]
3956 "&& reload_completed"
3957 [(set (match_dup 0) (const_int 0))
3959 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
3961 (clobber (reg:CC CC_REGNUM))])
3963 [(set (match_dup 0) (neg:GPR (match_dup 0)))
3964 (clobber (reg:CC CC_REGNUM))])]
3968 (define_expand "s<code>"
3969 [(set (match_operand:SI 0 "register_operand" "")
3970 (SCOND (match_dup 0)
3973 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
3974 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
3976 (define_expand "seq"
3978 [(set (match_operand:SI 0 "register_operand" "=d")
3980 (clobber (reg:CC CC_REGNUM))])
3982 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
3983 (clobber (reg:CC CC_REGNUM))])]
3986 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
3988 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
3989 PUT_MODE (operands[1], SImode);
3992 (define_insn_and_split "*sne"
3993 [(set (match_operand:SI 0 "register_operand" "=d")
3994 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
3996 (clobber (reg:CC CC_REGNUM))]
4001 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4002 (clobber (reg:CC CC_REGNUM))])])
4006 ;;- Multiply instructions.
4010 ; muldi3 instruction pattern(s).
4013 (define_insn "*muldi3_sign"
4014 [(set (match_operand:DI 0 "register_operand" "=d,d")
4015 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4016 (match_operand:DI 1 "register_operand" "0,0")))]
4021 [(set_attr "op_type" "RRE,RXY")
4022 (set_attr "type" "imuldi")])
4024 (define_insn "muldi3"
4025 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4026 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4027 (match_operand:DI 2 "general_operand" "d,K,m")))]
4033 [(set_attr "op_type" "RRE,RI,RXY")
4034 (set_attr "type" "imuldi")])
4037 ; mulsi3 instruction pattern(s).
4040 (define_insn "*mulsi3_sign"
4041 [(set (match_operand:SI 0 "register_operand" "=d")
4042 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4043 (match_operand:SI 1 "register_operand" "0")))]
4046 [(set_attr "op_type" "RX")
4047 (set_attr "type" "imulhi")])
4049 (define_insn "mulsi3"
4050 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4051 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4052 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4059 [(set_attr "op_type" "RRE,RI,RX,RXY")
4060 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4063 ; mulsidi3 instruction pattern(s).
4066 (define_insn "mulsidi3"
4067 [(set (match_operand:DI 0 "register_operand" "=d,d")
4068 (mult:DI (sign_extend:DI
4069 (match_operand:SI 1 "register_operand" "%0,0"))
4071 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4076 [(set_attr "op_type" "RR,RX")
4077 (set_attr "type" "imulsi")])
4080 ; umulsidi3 instruction pattern(s).
4083 (define_insn "umulsidi3"
4084 [(set (match_operand:DI 0 "register_operand" "=d,d")
4085 (mult:DI (zero_extend:DI
4086 (match_operand:SI 1 "register_operand" "%0,0"))
4088 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4089 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4093 [(set_attr "op_type" "RRE,RXY")
4094 (set_attr "type" "imulsi")])
4097 ; mul(df|sf)3 instruction pattern(s).
4100 (define_expand "mul<mode>3"
4101 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4102 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4103 (match_operand:FPR 2 "general_operand" "f,R")))]
4107 (define_insn "*mul<mode>3"
4108 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4109 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4110 (match_operand:FPR 2 "general_operand" "f,R")))]
4111 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4115 [(set_attr "op_type" "RRE,RXE")
4116 (set_attr "type" "fmul<mode>")])
4118 (define_insn "*mul<mode>3_ibm"
4119 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4120 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4121 (match_operand:FPR 2 "general_operand" "f,R")))]
4122 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4126 [(set_attr "op_type" "RR,RX")
4127 (set_attr "type" "fmul<mode>")])
4129 (define_insn "*fmadd<mode>"
4130 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4131 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4132 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4133 (match_operand:FPR 3 "register_operand" "0,0")))]
4134 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4138 [(set_attr "op_type" "RRE,RXE")
4139 (set_attr "type" "fmul<mode>")])
4141 (define_insn "*fmsub<mode>"
4142 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4143 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4144 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4145 (match_operand:FPR 3 "register_operand" "0,0")))]
4146 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4150 [(set_attr "op_type" "RRE,RXE")
4151 (set_attr "type" "fmul<mode>")])
4154 ;;- Divide and modulo instructions.
4158 ; divmoddi4 instruction pattern(s).
4161 (define_expand "divmoddi4"
4162 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4163 (div:DI (match_operand:DI 1 "register_operand" "")
4164 (match_operand:DI 2 "general_operand" "")))
4165 (set (match_operand:DI 3 "general_operand" "")
4166 (mod:DI (match_dup 1) (match_dup 2)))])
4167 (clobber (match_dup 4))]
4170 rtx insn, div_equal, mod_equal;
4172 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4173 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4175 operands[4] = gen_reg_rtx(TImode);
4176 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4178 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4180 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4182 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4184 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4189 (define_insn "divmodtidi3"
4190 [(set (match_operand:TI 0 "register_operand" "=d,d")
4194 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4195 (match_operand:DI 2 "general_operand" "d,m")))
4197 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4202 [(set_attr "op_type" "RRE,RXY")
4203 (set_attr "type" "idiv")])
4205 (define_insn "divmodtisi3"
4206 [(set (match_operand:TI 0 "register_operand" "=d,d")
4210 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4212 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4215 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4220 [(set_attr "op_type" "RRE,RXY")
4221 (set_attr "type" "idiv")])
4224 ; udivmoddi4 instruction pattern(s).
4227 (define_expand "udivmoddi4"
4228 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4229 (udiv:DI (match_operand:DI 1 "general_operand" "")
4230 (match_operand:DI 2 "nonimmediate_operand" "")))
4231 (set (match_operand:DI 3 "general_operand" "")
4232 (umod:DI (match_dup 1) (match_dup 2)))])
4233 (clobber (match_dup 4))]
4236 rtx insn, div_equal, mod_equal, equal;
4238 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4239 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4240 equal = gen_rtx_IOR (TImode,
4241 gen_rtx_ASHIFT (TImode,
4242 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4244 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4246 operands[4] = gen_reg_rtx(TImode);
4247 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4248 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4249 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4250 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4252 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4254 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4256 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4258 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4260 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4265 (define_insn "udivmodtidi3"
4266 [(set (match_operand:TI 0 "register_operand" "=d,d")
4271 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4273 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4277 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4282 [(set_attr "op_type" "RRE,RXY")
4283 (set_attr "type" "idiv")])
4286 ; divmodsi4 instruction pattern(s).
4289 (define_expand "divmodsi4"
4290 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4291 (div:SI (match_operand:SI 1 "general_operand" "")
4292 (match_operand:SI 2 "nonimmediate_operand" "")))
4293 (set (match_operand:SI 3 "general_operand" "")
4294 (mod:SI (match_dup 1) (match_dup 2)))])
4295 (clobber (match_dup 4))]
4298 rtx insn, div_equal, mod_equal, equal;
4300 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4301 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4302 equal = gen_rtx_IOR (DImode,
4303 gen_rtx_ASHIFT (DImode,
4304 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4306 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4308 operands[4] = gen_reg_rtx(DImode);
4309 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4310 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4312 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4314 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4316 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4318 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4320 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4325 (define_insn "divmoddisi3"
4326 [(set (match_operand:DI 0 "register_operand" "=d,d")
4331 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4333 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4337 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4342 [(set_attr "op_type" "RR,RX")
4343 (set_attr "type" "idiv")])
4346 ; udivsi3 and umodsi3 instruction pattern(s).
4349 (define_expand "udivmodsi4"
4350 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4351 (udiv:SI (match_operand:SI 1 "general_operand" "")
4352 (match_operand:SI 2 "nonimmediate_operand" "")))
4353 (set (match_operand:SI 3 "general_operand" "")
4354 (umod:SI (match_dup 1) (match_dup 2)))])
4355 (clobber (match_dup 4))]
4356 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4358 rtx insn, div_equal, mod_equal, equal;
4360 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4361 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4362 equal = gen_rtx_IOR (DImode,
4363 gen_rtx_ASHIFT (DImode,
4364 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4366 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4368 operands[4] = gen_reg_rtx(DImode);
4369 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4370 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4371 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4372 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4374 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4376 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4378 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4380 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4382 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4387 (define_insn "udivmoddisi3"
4388 [(set (match_operand:DI 0 "register_operand" "=d,d")
4393 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4395 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4399 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4400 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4404 [(set_attr "op_type" "RRE,RXY")
4405 (set_attr "type" "idiv")])
4407 (define_expand "udivsi3"
4408 [(set (match_operand:SI 0 "register_operand" "=d")
4409 (udiv:SI (match_operand:SI 1 "general_operand" "")
4410 (match_operand:SI 2 "general_operand" "")))
4411 (clobber (match_dup 3))]
4412 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4414 rtx insn, udiv_equal, umod_equal, equal;
4416 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4417 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4418 equal = gen_rtx_IOR (DImode,
4419 gen_rtx_ASHIFT (DImode,
4420 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4422 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4424 operands[3] = gen_reg_rtx (DImode);
4426 if (CONSTANT_P (operands[2]))
4428 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4430 rtx label1 = gen_label_rtx ();
4432 operands[1] = make_safe_from (operands[1], operands[0]);
4433 emit_move_insn (operands[0], const0_rtx);
4434 emit_insn (gen_cmpsi (operands[1], operands[2]));
4435 emit_jump_insn (gen_bltu (label1));
4436 emit_move_insn (operands[0], const1_rtx);
4437 emit_label (label1);
4441 operands[2] = force_reg (SImode, operands[2]);
4442 operands[2] = make_safe_from (operands[2], operands[0]);
4444 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4445 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4448 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4450 insn = emit_move_insn (operands[0],
4451 gen_lowpart (SImode, operands[3]));
4453 gen_rtx_EXPR_LIST (REG_EQUAL,
4454 udiv_equal, REG_NOTES (insn));
4459 rtx label1 = gen_label_rtx ();
4460 rtx label2 = gen_label_rtx ();
4461 rtx label3 = gen_label_rtx ();
4463 operands[1] = force_reg (SImode, operands[1]);
4464 operands[1] = make_safe_from (operands[1], operands[0]);
4465 operands[2] = force_reg (SImode, operands[2]);
4466 operands[2] = make_safe_from (operands[2], operands[0]);
4468 emit_move_insn (operands[0], const0_rtx);
4469 emit_insn (gen_cmpsi (operands[2], operands[1]));
4470 emit_jump_insn (gen_bgtu (label3));
4471 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4472 emit_jump_insn (gen_blt (label2));
4473 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4474 emit_jump_insn (gen_beq (label1));
4475 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4476 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4479 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4481 insn = emit_move_insn (operands[0],
4482 gen_lowpart (SImode, operands[3]));
4484 gen_rtx_EXPR_LIST (REG_EQUAL,
4485 udiv_equal, REG_NOTES (insn));
4487 emit_label (label1);
4488 emit_move_insn (operands[0], operands[1]);
4490 emit_label (label2);
4491 emit_move_insn (operands[0], const1_rtx);
4492 emit_label (label3);
4494 emit_move_insn (operands[0], operands[0]);
4498 (define_expand "umodsi3"
4499 [(set (match_operand:SI 0 "register_operand" "=d")
4500 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4501 (match_operand:SI 2 "nonimmediate_operand" "")))
4502 (clobber (match_dup 3))]
4503 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4505 rtx insn, udiv_equal, umod_equal, equal;
4507 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4508 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4509 equal = gen_rtx_IOR (DImode,
4510 gen_rtx_ASHIFT (DImode,
4511 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4513 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4515 operands[3] = gen_reg_rtx (DImode);
4517 if (CONSTANT_P (operands[2]))
4519 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4521 rtx label1 = gen_label_rtx ();
4523 operands[1] = make_safe_from (operands[1], operands[0]);
4524 emit_move_insn (operands[0], operands[1]);
4525 emit_insn (gen_cmpsi (operands[0], operands[2]));
4526 emit_jump_insn (gen_bltu (label1));
4527 emit_insn (gen_abssi2 (operands[0], operands[2]));
4528 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4529 emit_label (label1);
4533 operands[2] = force_reg (SImode, operands[2]);
4534 operands[2] = make_safe_from (operands[2], operands[0]);
4536 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4537 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4540 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4542 insn = emit_move_insn (operands[0],
4543 gen_highpart (SImode, operands[3]));
4545 gen_rtx_EXPR_LIST (REG_EQUAL,
4546 umod_equal, REG_NOTES (insn));
4551 rtx label1 = gen_label_rtx ();
4552 rtx label2 = gen_label_rtx ();
4553 rtx label3 = gen_label_rtx ();
4555 operands[1] = force_reg (SImode, operands[1]);
4556 operands[1] = make_safe_from (operands[1], operands[0]);
4557 operands[2] = force_reg (SImode, operands[2]);
4558 operands[2] = make_safe_from (operands[2], operands[0]);
4560 emit_move_insn(operands[0], operands[1]);
4561 emit_insn (gen_cmpsi (operands[2], operands[1]));
4562 emit_jump_insn (gen_bgtu (label3));
4563 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4564 emit_jump_insn (gen_blt (label2));
4565 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4566 emit_jump_insn (gen_beq (label1));
4567 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4568 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4571 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4573 insn = emit_move_insn (operands[0],
4574 gen_highpart (SImode, operands[3]));
4576 gen_rtx_EXPR_LIST (REG_EQUAL,
4577 umod_equal, REG_NOTES (insn));
4579 emit_label (label1);
4580 emit_move_insn (operands[0], const0_rtx);
4582 emit_label (label2);
4583 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4584 emit_label (label3);
4590 ; div(df|sf)3 instruction pattern(s).
4593 (define_expand "div<mode>3"
4594 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4595 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4596 (match_operand:FPR 2 "general_operand" "f,R")))]
4600 (define_insn "*div<mode>3"
4601 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4602 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4603 (match_operand:FPR 2 "general_operand" "f,R")))]
4604 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4608 [(set_attr "op_type" "RRE,RXE")
4609 (set_attr "type" "fdiv<mode>")])
4611 (define_insn "*div<mode>3_ibm"
4612 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4613 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4614 (match_operand:FPR 2 "general_operand" "f,R")))]
4615 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4619 [(set_attr "op_type" "RR,RX")
4620 (set_attr "type" "fdiv<mode>")])
4624 ;;- And instructions.
4627 (define_expand "and<mode>3"
4628 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4629 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4630 (match_operand:INT 2 "general_operand" "")))
4631 (clobber (reg:CC CC_REGNUM))]
4633 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4636 ; anddi3 instruction pattern(s).
4639 (define_insn "*anddi3_cc"
4640 [(set (reg CC_REGNUM)
4641 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4642 (match_operand:DI 2 "general_operand" "d,m"))
4644 (set (match_operand:DI 0 "register_operand" "=d,d")
4645 (and:DI (match_dup 1) (match_dup 2)))]
4646 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4650 [(set_attr "op_type" "RRE,RXY")])
4652 (define_insn "*anddi3_cconly"
4653 [(set (reg CC_REGNUM)
4654 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4655 (match_operand:DI 2 "general_operand" "d,m"))
4657 (clobber (match_scratch:DI 0 "=d,d"))]
4658 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4659 /* Do not steal TM patterns. */
4660 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4664 [(set_attr "op_type" "RRE,RXY")])
4666 (define_insn "*anddi3"
4667 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4668 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4669 "%d,o,0,0,0,0,0,0,0,0")
4670 (match_operand:DI 2 "general_operand"
4671 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4672 (clobber (reg:CC CC_REGNUM))]
4673 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4685 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4688 [(set (match_operand:DI 0 "s_operand" "")
4689 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4690 (clobber (reg:CC CC_REGNUM))]
4693 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4694 (clobber (reg:CC CC_REGNUM))])]
4695 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4699 ; andsi3 instruction pattern(s).
4702 (define_insn "*andsi3_cc"
4703 [(set (reg CC_REGNUM)
4704 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4705 (match_operand:SI 2 "general_operand" "d,R,T"))
4707 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4708 (and:SI (match_dup 1) (match_dup 2)))]
4709 "s390_match_ccmode(insn, CCTmode)"
4714 [(set_attr "op_type" "RR,RX,RXY")])
4716 (define_insn "*andsi3_cconly"
4717 [(set (reg CC_REGNUM)
4718 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4719 (match_operand:SI 2 "general_operand" "d,R,T"))
4721 (clobber (match_scratch:SI 0 "=d,d,d"))]
4722 "s390_match_ccmode(insn, CCTmode)
4723 /* Do not steal TM patterns. */
4724 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4729 [(set_attr "op_type" "RR,RX,RXY")])
4731 (define_insn "*andsi3_zarch"
4732 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
4733 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4734 "%d,o,0,0,0,0,0,0,0")
4735 (match_operand:SI 2 "general_operand"
4736 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
4737 (clobber (reg:CC CC_REGNUM))]
4738 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4749 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
4751 (define_insn "*andsi3_esa"
4752 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4753 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4754 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4755 (clobber (reg:CC CC_REGNUM))]
4756 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4762 [(set_attr "op_type" "RR,RX,SI,SS")])
4765 [(set (match_operand:SI 0 "s_operand" "")
4766 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4767 (clobber (reg:CC CC_REGNUM))]
4770 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4771 (clobber (reg:CC CC_REGNUM))])]
4772 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4775 ; andhi3 instruction pattern(s).
4778 (define_insn "*andhi3_zarch"
4779 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4780 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4781 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4782 (clobber (reg:CC CC_REGNUM))]
4783 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4789 [(set_attr "op_type" "RR,RI,SI,SS")])
4791 (define_insn "*andhi3_esa"
4792 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4793 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4794 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4795 (clobber (reg:CC CC_REGNUM))]
4796 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4801 [(set_attr "op_type" "RR,SI,SS")])
4804 [(set (match_operand:HI 0 "s_operand" "")
4805 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4806 (clobber (reg:CC CC_REGNUM))]
4809 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4810 (clobber (reg:CC CC_REGNUM))])]
4811 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4814 ; andqi3 instruction pattern(s).
4817 (define_insn "*andqi3_zarch"
4818 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4819 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4820 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4821 (clobber (reg:CC CC_REGNUM))]
4822 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4829 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4831 (define_insn "*andqi3_esa"
4832 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4833 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4834 (match_operand:QI 2 "general_operand" "d,n,Q")))
4835 (clobber (reg:CC CC_REGNUM))]
4836 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4841 [(set_attr "op_type" "RR,SI,SS")])
4844 ; Block and (NC) patterns.
4848 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4849 (and:BLK (match_dup 0)
4850 (match_operand:BLK 1 "memory_operand" "Q")))
4851 (use (match_operand 2 "const_int_operand" "n"))
4852 (clobber (reg:CC CC_REGNUM))]
4853 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4854 "nc\t%O0(%2,%R0),%S1"
4855 [(set_attr "op_type" "SS")])
4858 [(set (match_operand 0 "memory_operand" "")
4860 (match_operand 1 "memory_operand" "")))
4861 (clobber (reg:CC CC_REGNUM))]
4863 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4864 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4866 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4868 (clobber (reg:CC CC_REGNUM))])]
4870 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4871 operands[0] = adjust_address (operands[0], BLKmode, 0);
4872 operands[1] = adjust_address (operands[1], BLKmode, 0);
4877 [(set (match_operand:BLK 0 "memory_operand" "")
4878 (and:BLK (match_dup 0)
4879 (match_operand:BLK 1 "memory_operand" "")))
4880 (use (match_operand 2 "const_int_operand" ""))
4881 (clobber (reg:CC CC_REGNUM))])
4883 [(set (match_operand:BLK 3 "memory_operand" "")
4884 (and:BLK (match_dup 3)
4885 (match_operand:BLK 4 "memory_operand" "")))
4886 (use (match_operand 5 "const_int_operand" ""))
4887 (clobber (reg:CC CC_REGNUM))])]
4888 "s390_offset_p (operands[0], operands[3], operands[2])
4889 && s390_offset_p (operands[1], operands[4], operands[2])
4890 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4892 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4894 (clobber (reg:CC CC_REGNUM))])]
4895 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4896 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4897 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4901 ;;- Bit set (inclusive or) instructions.
4904 (define_expand "ior<mode>3"
4905 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4906 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
4907 (match_operand:INT 2 "general_operand" "")))
4908 (clobber (reg:CC CC_REGNUM))]
4910 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
4913 ; iordi3 instruction pattern(s).
4916 (define_insn "*iordi3_cc"
4917 [(set (reg CC_REGNUM)
4918 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4919 (match_operand:DI 2 "general_operand" "d,m"))
4921 (set (match_operand:DI 0 "register_operand" "=d,d")
4922 (ior:DI (match_dup 1) (match_dup 2)))]
4923 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4927 [(set_attr "op_type" "RRE,RXY")])
4929 (define_insn "*iordi3_cconly"
4930 [(set (reg CC_REGNUM)
4931 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4932 (match_operand:DI 2 "general_operand" "d,m"))
4934 (clobber (match_scratch:DI 0 "=d,d"))]
4935 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4939 [(set_attr "op_type" "RRE,RXY")])
4941 (define_insn "*iordi3"
4942 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
4943 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
4944 (match_operand:DI 2 "general_operand"
4945 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
4946 (clobber (reg:CC CC_REGNUM))]
4947 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4957 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
4960 [(set (match_operand:DI 0 "s_operand" "")
4961 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4962 (clobber (reg:CC CC_REGNUM))]
4965 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4966 (clobber (reg:CC CC_REGNUM))])]
4967 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4970 ; iorsi3 instruction pattern(s).
4973 (define_insn "*iorsi3_cc"
4974 [(set (reg CC_REGNUM)
4975 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4976 (match_operand:SI 2 "general_operand" "d,R,T"))
4978 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4979 (ior:SI (match_dup 1) (match_dup 2)))]
4980 "s390_match_ccmode(insn, CCTmode)"
4985 [(set_attr "op_type" "RR,RX,RXY")])
4987 (define_insn "*iorsi3_cconly"
4988 [(set (reg CC_REGNUM)
4989 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4990 (match_operand:SI 2 "general_operand" "d,R,T"))
4992 (clobber (match_scratch:SI 0 "=d,d,d"))]
4993 "s390_match_ccmode(insn, CCTmode)"
4998 [(set_attr "op_type" "RR,RX,RXY")])
5000 (define_insn "*iorsi3_zarch"
5001 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5002 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
5003 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5004 (clobber (reg:CC CC_REGNUM))]
5005 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5014 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5016 (define_insn "*iorsi3_esa"
5017 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5018 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5019 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5020 (clobber (reg:CC CC_REGNUM))]
5021 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5027 [(set_attr "op_type" "RR,RX,SI,SS")])
5030 [(set (match_operand:SI 0 "s_operand" "")
5031 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5032 (clobber (reg:CC CC_REGNUM))]
5035 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5036 (clobber (reg:CC CC_REGNUM))])]
5037 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5040 ; iorhi3 instruction pattern(s).
5043 (define_insn "*iorhi3_zarch"
5044 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5045 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5046 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5047 (clobber (reg:CC CC_REGNUM))]
5048 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5054 [(set_attr "op_type" "RR,RI,SI,SS")])
5056 (define_insn "*iorhi3_esa"
5057 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5058 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5059 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5060 (clobber (reg:CC CC_REGNUM))]
5061 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5066 [(set_attr "op_type" "RR,SI,SS")])
5069 [(set (match_operand:HI 0 "s_operand" "")
5070 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5071 (clobber (reg:CC CC_REGNUM))]
5074 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5075 (clobber (reg:CC CC_REGNUM))])]
5076 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5079 ; iorqi3 instruction pattern(s).
5082 (define_insn "*iorqi3_zarch"
5083 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5084 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5085 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5086 (clobber (reg:CC CC_REGNUM))]
5087 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5094 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5096 (define_insn "*iorqi3_esa"
5097 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5098 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5099 (match_operand:QI 2 "general_operand" "d,n,Q")))
5100 (clobber (reg:CC CC_REGNUM))]
5101 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5106 [(set_attr "op_type" "RR,SI,SS")])
5109 ; Block inclusive or (OC) patterns.
5113 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5114 (ior:BLK (match_dup 0)
5115 (match_operand:BLK 1 "memory_operand" "Q")))
5116 (use (match_operand 2 "const_int_operand" "n"))
5117 (clobber (reg:CC CC_REGNUM))]
5118 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5119 "oc\t%O0(%2,%R0),%S1"
5120 [(set_attr "op_type" "SS")])
5123 [(set (match_operand 0 "memory_operand" "")
5125 (match_operand 1 "memory_operand" "")))
5126 (clobber (reg:CC CC_REGNUM))]
5128 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5129 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5131 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5133 (clobber (reg:CC CC_REGNUM))])]
5135 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5136 operands[0] = adjust_address (operands[0], BLKmode, 0);
5137 operands[1] = adjust_address (operands[1], BLKmode, 0);
5142 [(set (match_operand:BLK 0 "memory_operand" "")
5143 (ior:BLK (match_dup 0)
5144 (match_operand:BLK 1 "memory_operand" "")))
5145 (use (match_operand 2 "const_int_operand" ""))
5146 (clobber (reg:CC CC_REGNUM))])
5148 [(set (match_operand:BLK 3 "memory_operand" "")
5149 (ior:BLK (match_dup 3)
5150 (match_operand:BLK 4 "memory_operand" "")))
5151 (use (match_operand 5 "const_int_operand" ""))
5152 (clobber (reg:CC CC_REGNUM))])]
5153 "s390_offset_p (operands[0], operands[3], operands[2])
5154 && s390_offset_p (operands[1], operands[4], operands[2])
5155 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5157 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5159 (clobber (reg:CC CC_REGNUM))])]
5160 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5161 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5162 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5166 ;;- Xor instructions.
5169 (define_expand "xor<mode>3"
5170 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5171 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5172 (match_operand:INT 2 "general_operand" "")))
5173 (clobber (reg:CC CC_REGNUM))]
5175 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5178 ; xordi3 instruction pattern(s).
5181 (define_insn "*xordi3_cc"
5182 [(set (reg CC_REGNUM)
5183 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5184 (match_operand:DI 2 "general_operand" "d,m"))
5186 (set (match_operand:DI 0 "register_operand" "=d,d")
5187 (xor:DI (match_dup 1) (match_dup 2)))]
5188 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5192 [(set_attr "op_type" "RRE,RXY")])
5194 (define_insn "*xordi3_cconly"
5195 [(set (reg CC_REGNUM)
5196 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5197 (match_operand:DI 2 "general_operand" "d,m"))
5199 (clobber (match_scratch:DI 0 "=d,d"))]
5200 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5204 [(set_attr "op_type" "RRE,RXY")])
5206 (define_insn "*xordi3"
5207 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5208 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5209 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5210 (clobber (reg:CC CC_REGNUM))]
5211 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5217 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5220 [(set (match_operand:DI 0 "s_operand" "")
5221 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5222 (clobber (reg:CC CC_REGNUM))]
5225 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5226 (clobber (reg:CC CC_REGNUM))])]
5227 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5230 ; xorsi3 instruction pattern(s).
5233 (define_insn "*xorsi3_cc"
5234 [(set (reg CC_REGNUM)
5235 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5236 (match_operand:SI 2 "general_operand" "d,R,T"))
5238 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5239 (xor:SI (match_dup 1) (match_dup 2)))]
5240 "s390_match_ccmode(insn, CCTmode)"
5245 [(set_attr "op_type" "RR,RX,RXY")])
5247 (define_insn "*xorsi3_cconly"
5248 [(set (reg CC_REGNUM)
5249 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5250 (match_operand:SI 2 "general_operand" "d,R,T"))
5252 (clobber (match_scratch:SI 0 "=d,d,d"))]
5253 "s390_match_ccmode(insn, CCTmode)"
5258 [(set_attr "op_type" "RR,RX,RXY")])
5260 (define_insn "*xorsi3"
5261 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5262 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5263 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5264 (clobber (reg:CC CC_REGNUM))]
5265 "s390_logical_operator_ok_p (operands)"
5272 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5275 [(set (match_operand:SI 0 "s_operand" "")
5276 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5277 (clobber (reg:CC CC_REGNUM))]
5280 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5281 (clobber (reg:CC CC_REGNUM))])]
5282 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5285 ; xorhi3 instruction pattern(s).
5288 (define_insn "*xorhi3"
5289 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5290 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5291 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5292 (clobber (reg:CC CC_REGNUM))]
5293 "s390_logical_operator_ok_p (operands)"
5298 [(set_attr "op_type" "RR,SI,SS")])
5301 [(set (match_operand:HI 0 "s_operand" "")
5302 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5303 (clobber (reg:CC CC_REGNUM))]
5306 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5307 (clobber (reg:CC CC_REGNUM))])]
5308 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5311 ; xorqi3 instruction pattern(s).
5314 (define_insn "*xorqi3"
5315 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5316 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5317 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5318 (clobber (reg:CC CC_REGNUM))]
5319 "s390_logical_operator_ok_p (operands)"
5325 [(set_attr "op_type" "RR,SI,SIY,SS")])
5328 ; Block exclusive or (XC) patterns.
5332 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5333 (xor:BLK (match_dup 0)
5334 (match_operand:BLK 1 "memory_operand" "Q")))
5335 (use (match_operand 2 "const_int_operand" "n"))
5336 (clobber (reg:CC CC_REGNUM))]
5337 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5338 "xc\t%O0(%2,%R0),%S1"
5339 [(set_attr "op_type" "SS")])
5342 [(set (match_operand 0 "memory_operand" "")
5344 (match_operand 1 "memory_operand" "")))
5345 (clobber (reg:CC CC_REGNUM))]
5347 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5348 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5350 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5352 (clobber (reg:CC CC_REGNUM))])]
5354 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5355 operands[0] = adjust_address (operands[0], BLKmode, 0);
5356 operands[1] = adjust_address (operands[1], BLKmode, 0);
5361 [(set (match_operand:BLK 0 "memory_operand" "")
5362 (xor:BLK (match_dup 0)
5363 (match_operand:BLK 1 "memory_operand" "")))
5364 (use (match_operand 2 "const_int_operand" ""))
5365 (clobber (reg:CC CC_REGNUM))])
5367 [(set (match_operand:BLK 3 "memory_operand" "")
5368 (xor:BLK (match_dup 3)
5369 (match_operand:BLK 4 "memory_operand" "")))
5370 (use (match_operand 5 "const_int_operand" ""))
5371 (clobber (reg:CC CC_REGNUM))])]
5372 "s390_offset_p (operands[0], operands[3], operands[2])
5373 && s390_offset_p (operands[1], operands[4], operands[2])
5374 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5376 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5378 (clobber (reg:CC CC_REGNUM))])]
5379 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5380 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5381 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5384 ; Block xor (XC) patterns with src == dest.
5387 (define_insn "*xc_zero"
5388 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5390 (use (match_operand 1 "const_int_operand" "n"))
5391 (clobber (reg:CC CC_REGNUM))]
5392 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5393 "xc\t%O0(%1,%R0),%S0"
5394 [(set_attr "op_type" "SS")])
5398 [(set (match_operand:BLK 0 "memory_operand" "")
5400 (use (match_operand 1 "const_int_operand" ""))
5401 (clobber (reg:CC CC_REGNUM))])
5403 [(set (match_operand:BLK 2 "memory_operand" "")
5405 (use (match_operand 3 "const_int_operand" ""))
5406 (clobber (reg:CC CC_REGNUM))])]
5407 "s390_offset_p (operands[0], operands[2], operands[1])
5408 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5410 [(set (match_dup 4) (const_int 0))
5412 (clobber (reg:CC CC_REGNUM))])]
5413 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5414 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5418 ;;- Negate instructions.
5422 ; neg(di|si)2 instruction pattern(s).
5425 (define_expand "neg<mode>2"
5427 [(set (match_operand:DSI 0 "register_operand" "=d")
5428 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5429 (clobber (reg:CC CC_REGNUM))])]
5433 (define_insn "*negdi2_sign_cc"
5434 [(set (reg CC_REGNUM)
5435 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5436 (match_operand:SI 1 "register_operand" "d") 0)
5437 (const_int 32)) (const_int 32)))
5439 (set (match_operand:DI 0 "register_operand" "=d")
5440 (neg:DI (sign_extend:DI (match_dup 1))))]
5441 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5443 [(set_attr "op_type" "RRE")])
5445 (define_insn "*negdi2_sign"
5446 [(set (match_operand:DI 0 "register_operand" "=d")
5447 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5448 (clobber (reg:CC CC_REGNUM))]
5451 [(set_attr "op_type" "RRE")])
5453 (define_insn "*neg<mode>2_cc"
5454 [(set (reg CC_REGNUM)
5455 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5457 (set (match_operand:GPR 0 "register_operand" "=d")
5458 (neg:GPR (match_dup 1)))]
5459 "s390_match_ccmode (insn, CCAmode)"
5461 [(set_attr "op_type" "RR<E>")])
5463 (define_insn "*neg<mode>2_cconly"
5464 [(set (reg CC_REGNUM)
5465 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5467 (clobber (match_scratch:GPR 0 "=d"))]
5468 "s390_match_ccmode (insn, CCAmode)"
5470 [(set_attr "op_type" "RR<E>")])
5472 (define_insn "*neg<mode>2"
5473 [(set (match_operand:GPR 0 "register_operand" "=d")
5474 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5475 (clobber (reg:CC CC_REGNUM))]
5478 [(set_attr "op_type" "RR<E>")])
5480 (define_insn_and_split "*negdi2_31"
5481 [(set (match_operand:DI 0 "register_operand" "=d")
5482 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5483 (clobber (reg:CC CC_REGNUM))]
5486 "&& reload_completed"
5488 [(set (match_dup 2) (neg:SI (match_dup 3)))
5489 (clobber (reg:CC CC_REGNUM))])
5491 [(set (reg:CCAP CC_REGNUM)
5492 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5493 (set (match_dup 4) (neg:SI (match_dup 5)))])
5495 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5497 (label_ref (match_dup 6))))
5499 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5500 (clobber (reg:CC CC_REGNUM))])
5502 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5503 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5504 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5505 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5506 operands[6] = gen_label_rtx ();")
5509 ; neg(df|sf)2 instruction pattern(s).
5512 (define_expand "neg<mode>2"
5514 [(set (match_operand:FPR 0 "register_operand" "=f")
5515 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5516 (clobber (reg:CC CC_REGNUM))])]
5520 (define_insn "*neg<mode>2_cc"
5521 [(set (reg CC_REGNUM)
5522 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5523 (match_operand:FPR 2 "const0_operand" "")))
5524 (set (match_operand:FPR 0 "register_operand" "=f")
5525 (neg:FPR (match_dup 1)))]
5526 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5528 [(set_attr "op_type" "RRE")
5529 (set_attr "type" "fsimp<mode>")])
5531 (define_insn "*neg<mode>2_cconly"
5532 [(set (reg CC_REGNUM)
5533 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5534 (match_operand:FPR 2 "const0_operand" "")))
5535 (clobber (match_scratch:FPR 0 "=f"))]
5536 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5538 [(set_attr "op_type" "RRE")
5539 (set_attr "type" "fsimp<mode>")])
5541 (define_insn "*neg<mode>2"
5542 [(set (match_operand:FPR 0 "register_operand" "=f")
5543 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5544 (clobber (reg:CC CC_REGNUM))]
5545 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5547 [(set_attr "op_type" "RRE")
5548 (set_attr "type" "fsimp<mode>")])
5550 (define_insn "*neg<mode>2_ibm"
5551 [(set (match_operand:FPR 0 "register_operand" "=f")
5552 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5553 (clobber (reg:CC CC_REGNUM))]
5554 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5556 [(set_attr "op_type" "RR")
5557 (set_attr "type" "fsimp<mode>")])
5561 ;;- Absolute value instructions.
5565 ; abs(di|si)2 instruction pattern(s).
5568 (define_insn "*absdi2_sign_cc"
5569 [(set (reg CC_REGNUM)
5570 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5571 (match_operand:SI 1 "register_operand" "d") 0)
5572 (const_int 32)) (const_int 32)))
5574 (set (match_operand:DI 0 "register_operand" "=d")
5575 (abs:DI (sign_extend:DI (match_dup 1))))]
5576 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5578 [(set_attr "op_type" "RRE")])
5580 (define_insn "*absdi2_sign"
5581 [(set (match_operand:DI 0 "register_operand" "=d")
5582 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5583 (clobber (reg:CC CC_REGNUM))]
5586 [(set_attr "op_type" "RRE")])
5588 (define_insn "*abs<mode>2_cc"
5589 [(set (reg CC_REGNUM)
5590 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5592 (set (match_operand:GPR 0 "register_operand" "=d")
5593 (abs:GPR (match_dup 1)))]
5594 "s390_match_ccmode (insn, CCAmode)"
5596 [(set_attr "op_type" "RR<E>")])
5598 (define_insn "*abs<mode>2_cconly"
5599 [(set (reg CC_REGNUM)
5600 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5602 (clobber (match_scratch:GPR 0 "=d"))]
5603 "s390_match_ccmode (insn, CCAmode)"
5605 [(set_attr "op_type" "RR<E>")])
5607 (define_insn "abs<mode>2"
5608 [(set (match_operand:GPR 0 "register_operand" "=d")
5609 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5610 (clobber (reg:CC CC_REGNUM))]
5613 [(set_attr "op_type" "RR<E>")])
5616 ; abs(df|sf)2 instruction pattern(s).
5619 (define_expand "abs<mode>2"
5621 [(set (match_operand:FPR 0 "register_operand" "=f")
5622 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5623 (clobber (reg:CC CC_REGNUM))])]
5627 (define_insn "*abs<mode>2_cc"
5628 [(set (reg CC_REGNUM)
5629 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5630 (match_operand:FPR 2 "const0_operand" "")))
5631 (set (match_operand:FPR 0 "register_operand" "=f")
5632 (abs:FPR (match_dup 1)))]
5633 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5635 [(set_attr "op_type" "RRE")
5636 (set_attr "type" "fsimp<mode>")])
5638 (define_insn "*abs<mode>2_cconly"
5639 [(set (reg CC_REGNUM)
5640 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5641 (match_operand:FPR 2 "const0_operand" "")))
5642 (clobber (match_scratch:FPR 0 "=f"))]
5643 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5645 [(set_attr "op_type" "RRE")
5646 (set_attr "type" "fsimp<mode>")])
5648 (define_insn "*abs<mode>2"
5649 [(set (match_operand:FPR 0 "register_operand" "=f")
5650 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5651 (clobber (reg:CC CC_REGNUM))]
5652 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5654 [(set_attr "op_type" "RRE")
5655 (set_attr "type" "fsimp<mode>")])
5657 (define_insn "*abs<mode>2_ibm"
5658 [(set (match_operand:FPR 0 "register_operand" "=f")
5659 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5660 (clobber (reg:CC CC_REGNUM))]
5661 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5663 [(set_attr "op_type" "RR")
5664 (set_attr "type" "fsimp<mode>")])
5667 ;;- Negated absolute value instructions
5674 (define_insn "*negabsdi2_sign_cc"
5675 [(set (reg CC_REGNUM)
5676 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5677 (match_operand:SI 1 "register_operand" "d") 0)
5678 (const_int 32)) (const_int 32))))
5680 (set (match_operand:DI 0 "register_operand" "=d")
5681 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5682 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5684 [(set_attr "op_type" "RRE")])
5686 (define_insn "*negabsdi2_sign"
5687 [(set (match_operand:DI 0 "register_operand" "=d")
5688 (neg:DI (abs:DI (sign_extend:DI
5689 (match_operand:SI 1 "register_operand" "d")))))
5690 (clobber (reg:CC CC_REGNUM))]
5693 [(set_attr "op_type" "RRE")])
5695 (define_insn "*negabs<mode>2_cc"
5696 [(set (reg CC_REGNUM)
5697 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5699 (set (match_operand:GPR 0 "register_operand" "=d")
5700 (neg:GPR (abs:GPR (match_dup 1))))]
5701 "s390_match_ccmode (insn, CCAmode)"
5703 [(set_attr "op_type" "RR<E>")])
5705 (define_insn "*negabs<mode>2_cconly"
5706 [(set (reg CC_REGNUM)
5707 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5709 (clobber (match_scratch:GPR 0 "=d"))]
5710 "s390_match_ccmode (insn, CCAmode)"
5712 [(set_attr "op_type" "RR<E>")])
5714 (define_insn "*negabs<mode>2"
5715 [(set (match_operand:GPR 0 "register_operand" "=d")
5716 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5717 (clobber (reg:CC CC_REGNUM))]
5720 [(set_attr "op_type" "RR<E>")])
5726 (define_insn "*negabs<mode>2_cc"
5727 [(set (reg CC_REGNUM)
5728 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5729 (match_operand:FPR 2 "const0_operand" "")))
5730 (set (match_operand:FPR 0 "register_operand" "=f")
5731 (neg:FPR (abs:FPR (match_dup 1))))]
5732 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5734 [(set_attr "op_type" "RRE")
5735 (set_attr "type" "fsimp<mode>")])
5737 (define_insn "*negabs<mode>2_cconly"
5738 [(set (reg CC_REGNUM)
5739 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5740 (match_operand:FPR 2 "const0_operand" "")))
5741 (clobber (match_scratch:FPR 0 "=f"))]
5742 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5744 [(set_attr "op_type" "RRE")
5745 (set_attr "type" "fsimp<mode>")])
5747 (define_insn "*negabs<mode>2"
5748 [(set (match_operand:FPR 0 "register_operand" "=f")
5749 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5750 (clobber (reg:CC CC_REGNUM))]
5751 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5753 [(set_attr "op_type" "RRE")
5754 (set_attr "type" "fsimp<mode>")])
5757 ;;- Square root instructions.
5761 ; sqrt(df|sf)2 instruction pattern(s).
5764 (define_insn "sqrt<mode>2"
5765 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5766 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5767 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5771 [(set_attr "op_type" "RRE,RXE")
5772 (set_attr "type" "fsqrt<mode>")])
5776 ;;- One complement instructions.
5780 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5783 (define_expand "one_cmpl<mode>2"
5785 [(set (match_operand:INT 0 "register_operand" "")
5786 (xor:INT (match_operand:INT 1 "register_operand" "")
5788 (clobber (reg:CC CC_REGNUM))])]
5794 ;;- Rotate instructions.
5798 ; rotl(di|si)3 instruction pattern(s).
5801 (define_insn "rotl<mode>3"
5802 [(set (match_operand:GPR 0 "register_operand" "=d")
5803 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5804 (match_operand:SI 2 "shift_count_operand" "Y")))]
5807 [(set_attr "op_type" "RSE")
5808 (set_attr "atype" "reg")])
5812 ;;- Shift instructions.
5816 ; (ashl|lshr)di3 instruction pattern(s).
5819 (define_expand "<shift>di3"
5820 [(set (match_operand:DI 0 "register_operand" "")
5821 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
5822 (match_operand:SI 2 "shift_count_operand" "")))]
5826 (define_insn "*<shift>di3_31"
5827 [(set (match_operand:DI 0 "register_operand" "=d")
5828 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
5829 (match_operand:SI 2 "shift_count_operand" "Y")))]
5832 [(set_attr "op_type" "RS")
5833 (set_attr "atype" "reg")])
5835 (define_insn "*<shift>di3_64"
5836 [(set (match_operand:DI 0 "register_operand" "=d")
5837 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
5838 (match_operand:SI 2 "shift_count_operand" "Y")))]
5840 "s<lr>lg\t%0,%1,%Y2"
5841 [(set_attr "op_type" "RSE")
5842 (set_attr "atype" "reg")])
5845 ; ashrdi3 instruction pattern(s).
5848 (define_expand "ashrdi3"
5850 [(set (match_operand:DI 0 "register_operand" "")
5851 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5852 (match_operand:SI 2 "shift_count_operand" "")))
5853 (clobber (reg:CC CC_REGNUM))])]
5857 (define_insn "*ashrdi3_cc_31"
5858 [(set (reg CC_REGNUM)
5859 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5860 (match_operand:SI 2 "shift_count_operand" "Y"))
5862 (set (match_operand:DI 0 "register_operand" "=d")
5863 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5864 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5866 [(set_attr "op_type" "RS")
5867 (set_attr "atype" "reg")])
5869 (define_insn "*ashrdi3_cconly_31"
5870 [(set (reg CC_REGNUM)
5871 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5872 (match_operand:SI 2 "shift_count_operand" "Y"))
5874 (clobber (match_scratch:DI 0 "=d"))]
5875 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5877 [(set_attr "op_type" "RS")
5878 (set_attr "atype" "reg")])
5880 (define_insn "*ashrdi3_31"
5881 [(set (match_operand:DI 0 "register_operand" "=d")
5882 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5883 (match_operand:SI 2 "shift_count_operand" "Y")))
5884 (clobber (reg:CC CC_REGNUM))]
5887 [(set_attr "op_type" "RS")
5888 (set_attr "atype" "reg")])
5890 (define_insn "*ashrdi3_cc_64"
5891 [(set (reg CC_REGNUM)
5892 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5893 (match_operand:SI 2 "shift_count_operand" "Y"))
5895 (set (match_operand:DI 0 "register_operand" "=d")
5896 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5897 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5899 [(set_attr "op_type" "RSE")
5900 (set_attr "atype" "reg")])
5902 (define_insn "*ashrdi3_cconly_64"
5903 [(set (reg CC_REGNUM)
5904 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5905 (match_operand:SI 2 "shift_count_operand" "Y"))
5907 (clobber (match_scratch:DI 0 "=d"))]
5908 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5910 [(set_attr "op_type" "RSE")
5911 (set_attr "atype" "reg")])
5913 (define_insn "*ashrdi3_64"
5914 [(set (match_operand:DI 0 "register_operand" "=d")
5915 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5916 (match_operand:SI 2 "shift_count_operand" "Y")))
5917 (clobber (reg:CC CC_REGNUM))]
5920 [(set_attr "op_type" "RSE")
5921 (set_attr "atype" "reg")])
5925 ; (ashl|lshr)si3 instruction pattern(s).
5928 (define_insn "<shift>si3"
5929 [(set (match_operand:SI 0 "register_operand" "=d")
5930 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
5931 (match_operand:SI 2 "shift_count_operand" "Y")))]
5934 [(set_attr "op_type" "RS")
5935 (set_attr "atype" "reg")])
5938 ; ashrsi3 instruction pattern(s).
5941 (define_insn "*ashrsi3_cc"
5942 [(set (reg CC_REGNUM)
5943 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5944 (match_operand:SI 2 "shift_count_operand" "Y"))
5946 (set (match_operand:SI 0 "register_operand" "=d")
5947 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5948 "s390_match_ccmode(insn, CCSmode)"
5950 [(set_attr "op_type" "RS")
5951 (set_attr "atype" "reg")])
5954 (define_insn "*ashrsi3_cconly"
5955 [(set (reg CC_REGNUM)
5956 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5957 (match_operand:SI 2 "shift_count_operand" "Y"))
5959 (clobber (match_scratch:SI 0 "=d"))]
5960 "s390_match_ccmode(insn, CCSmode)"
5962 [(set_attr "op_type" "RS")
5963 (set_attr "atype" "reg")])
5965 (define_insn "ashrsi3"
5966 [(set (match_operand:SI 0 "register_operand" "=d")
5967 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5968 (match_operand:SI 2 "shift_count_operand" "Y")))
5969 (clobber (reg:CC CC_REGNUM))]
5972 [(set_attr "op_type" "RS")
5973 (set_attr "atype" "reg")])
5977 ;; Branch instruction patterns.
5980 (define_expand "b<code>"
5982 (if_then_else (COMPARE (match_operand 0 "" "")
5987 "s390_emit_jump (operands[0],
5988 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
5992 ;;- Conditional jump instructions.
5995 (define_insn "*cjump_64"
5998 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5999 (label_ref (match_operand 0 "" ""))
6003 if (get_attr_length (insn) == 4)
6006 return "jg%C1\t%l0";
6008 [(set_attr "op_type" "RI")
6009 (set_attr "type" "branch")
6010 (set (attr "length")
6011 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6012 (const_int 4) (const_int 6)))])
6014 (define_insn "*cjump_31"
6017 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6018 (label_ref (match_operand 0 "" ""))
6022 gcc_assert (get_attr_length (insn) == 4);
6025 [(set_attr "op_type" "RI")
6026 (set_attr "type" "branch")
6027 (set (attr "length")
6028 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6029 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6030 (const_int 4) (const_int 6))
6031 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6032 (const_int 4) (const_int 8))))])
6034 (define_insn "*cjump_long"
6037 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6038 (match_operand 0 "address_operand" "U")
6042 if (get_attr_op_type (insn) == OP_TYPE_RR)
6047 [(set (attr "op_type")
6048 (if_then_else (match_operand 0 "register_operand" "")
6049 (const_string "RR") (const_string "RX")))
6050 (set_attr "type" "branch")
6051 (set_attr "atype" "agen")])
6055 ;;- Negated conditional jump instructions.
6058 (define_insn "*icjump_64"
6061 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6063 (label_ref (match_operand 0 "" ""))))]
6066 if (get_attr_length (insn) == 4)
6069 return "jg%D1\t%l0";
6071 [(set_attr "op_type" "RI")
6072 (set_attr "type" "branch")
6073 (set (attr "length")
6074 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6075 (const_int 4) (const_int 6)))])
6077 (define_insn "*icjump_31"
6080 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6082 (label_ref (match_operand 0 "" ""))))]
6085 gcc_assert (get_attr_length (insn) == 4);
6088 [(set_attr "op_type" "RI")
6089 (set_attr "type" "branch")
6090 (set (attr "length")
6091 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6092 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6093 (const_int 4) (const_int 6))
6094 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6095 (const_int 4) (const_int 8))))])
6097 (define_insn "*icjump_long"
6100 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6102 (match_operand 0 "address_operand" "U")))]
6105 if (get_attr_op_type (insn) == OP_TYPE_RR)
6110 [(set (attr "op_type")
6111 (if_then_else (match_operand 0 "register_operand" "")
6112 (const_string "RR") (const_string "RX")))
6113 (set_attr "type" "branch")
6114 (set_attr "atype" "agen")])
6117 ;;- Trap instructions.
6121 [(trap_if (const_int 1) (const_int 0))]
6124 [(set_attr "op_type" "RI")
6125 (set_attr "type" "branch")])
6127 (define_expand "conditional_trap"
6128 [(trap_if (match_operand 0 "comparison_operator" "")
6129 (match_operand 1 "general_operand" ""))]
6132 if (operands[1] != const0_rtx) FAIL;
6133 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6134 s390_compare_op0, s390_compare_op1);
6137 (define_insn "*trap"
6138 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6142 [(set_attr "op_type" "RI")
6143 (set_attr "type" "branch")])
6146 ;;- Loop instructions.
6148 ;; This is all complicated by the fact that since this is a jump insn
6149 ;; we must handle our own output reloads.
6151 (define_expand "doloop_end"
6152 [(use (match_operand 0 "" "")) ; loop pseudo
6153 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6154 (use (match_operand 2 "" "")) ; max iterations
6155 (use (match_operand 3 "" "")) ; loop level
6156 (use (match_operand 4 "" ""))] ; label
6159 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6160 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6161 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6162 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6163 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6164 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6171 (define_insn_and_split "doloop_si64"
6174 (ne (match_operand:SI 1 "register_operand" "d,d")
6176 (label_ref (match_operand 0 "" ""))
6178 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6179 (plus:SI (match_dup 1) (const_int -1)))
6180 (clobber (match_scratch:SI 3 "=X,&1"))
6181 (clobber (reg:CC CC_REGNUM))]
6184 if (which_alternative != 0)
6186 else if (get_attr_length (insn) == 4)
6187 return "brct\t%1,%l0";
6189 return "ahi\t%1,-1\;jgne\t%l0";
6191 "&& reload_completed
6192 && (! REG_P (operands[2])
6193 || ! rtx_equal_p (operands[1], operands[2]))"
6194 [(parallel [(set (reg:CCAN CC_REGNUM)
6195 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6197 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6198 (set (match_dup 2) (match_dup 3))
6199 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6200 (label_ref (match_dup 0))
6203 [(set_attr "op_type" "RI")
6204 (set_attr "type" "branch")
6205 (set (attr "length")
6206 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6207 (const_int 4) (const_int 10)))])
6209 (define_insn_and_split "doloop_si31"
6212 (ne (match_operand:SI 1 "register_operand" "d,d")
6214 (label_ref (match_operand 0 "" ""))
6216 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6217 (plus:SI (match_dup 1) (const_int -1)))
6218 (clobber (match_scratch:SI 3 "=X,&1"))
6219 (clobber (reg:CC CC_REGNUM))]
6222 if (which_alternative != 0)
6224 else if (get_attr_length (insn) == 4)
6225 return "brct\t%1,%l0";
6229 "&& reload_completed
6230 && (! REG_P (operands[2])
6231 || ! rtx_equal_p (operands[1], operands[2]))"
6232 [(parallel [(set (reg:CCAN CC_REGNUM)
6233 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6235 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6236 (set (match_dup 2) (match_dup 3))
6237 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6238 (label_ref (match_dup 0))
6241 [(set_attr "op_type" "RI")
6242 (set_attr "type" "branch")
6243 (set (attr "length")
6244 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6245 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6246 (const_int 4) (const_int 6))
6247 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6248 (const_int 4) (const_int 8))))])
6250 (define_insn "*doloop_si_long"
6253 (ne (match_operand:SI 1 "register_operand" "d,d")
6255 (match_operand 0 "address_operand" "U,U")
6257 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6258 (plus:SI (match_dup 1) (const_int -1)))
6259 (clobber (match_scratch:SI 3 "=X,&1"))
6260 (clobber (reg:CC CC_REGNUM))]
6263 if (get_attr_op_type (insn) == OP_TYPE_RR)
6264 return "bctr\t%1,%0";
6266 return "bct\t%1,%a0";
6268 [(set (attr "op_type")
6269 (if_then_else (match_operand 0 "register_operand" "")
6270 (const_string "RR") (const_string "RX")))
6271 (set_attr "type" "branch")
6272 (set_attr "atype" "agen")])
6274 (define_insn_and_split "doloop_di"
6277 (ne (match_operand:DI 1 "register_operand" "d,d")
6279 (label_ref (match_operand 0 "" ""))
6281 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6282 (plus:DI (match_dup 1) (const_int -1)))
6283 (clobber (match_scratch:DI 3 "=X,&1"))
6284 (clobber (reg:CC CC_REGNUM))]
6287 if (which_alternative != 0)
6289 else if (get_attr_length (insn) == 4)
6290 return "brctg\t%1,%l0";
6292 return "aghi\t%1,-1\;jgne\t%l0";
6294 "&& reload_completed
6295 && (! REG_P (operands[2])
6296 || ! rtx_equal_p (operands[1], operands[2]))"
6297 [(parallel [(set (reg:CCAN CC_REGNUM)
6298 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6300 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6301 (set (match_dup 2) (match_dup 3))
6302 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6303 (label_ref (match_dup 0))
6306 [(set_attr "op_type" "RI")
6307 (set_attr "type" "branch")
6308 (set (attr "length")
6309 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6310 (const_int 4) (const_int 10)))])
6313 ;;- Unconditional jump instructions.
6317 ; jump instruction pattern(s).
6320 (define_expand "jump"
6321 [(match_operand 0 "" "")]
6323 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6325 (define_insn "*jump64"
6326 [(set (pc) (label_ref (match_operand 0 "" "")))]
6329 if (get_attr_length (insn) == 4)
6334 [(set_attr "op_type" "RI")
6335 (set_attr "type" "branch")
6336 (set (attr "length")
6337 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6338 (const_int 4) (const_int 6)))])
6340 (define_insn "*jump31"
6341 [(set (pc) (label_ref (match_operand 0 "" "")))]
6344 gcc_assert (get_attr_length (insn) == 4);
6347 [(set_attr "op_type" "RI")
6348 (set_attr "type" "branch")
6349 (set (attr "length")
6350 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6351 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6352 (const_int 4) (const_int 6))
6353 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6354 (const_int 4) (const_int 8))))])
6357 ; indirect-jump instruction pattern(s).
6360 (define_insn "indirect_jump"
6361 [(set (pc) (match_operand 0 "address_operand" "U"))]
6364 if (get_attr_op_type (insn) == OP_TYPE_RR)
6369 [(set (attr "op_type")
6370 (if_then_else (match_operand 0 "register_operand" "")
6371 (const_string "RR") (const_string "RX")))
6372 (set_attr "type" "branch")
6373 (set_attr "atype" "agen")])
6376 ; casesi instruction pattern(s).
6379 (define_insn "casesi_jump"
6380 [(set (pc) (match_operand 0 "address_operand" "U"))
6381 (use (label_ref (match_operand 1 "" "")))]
6384 if (get_attr_op_type (insn) == OP_TYPE_RR)
6389 [(set (attr "op_type")
6390 (if_then_else (match_operand 0 "register_operand" "")
6391 (const_string "RR") (const_string "RX")))
6392 (set_attr "type" "branch")
6393 (set_attr "atype" "agen")])
6395 (define_expand "casesi"
6396 [(match_operand:SI 0 "general_operand" "")
6397 (match_operand:SI 1 "general_operand" "")
6398 (match_operand:SI 2 "general_operand" "")
6399 (label_ref (match_operand 3 "" ""))
6400 (label_ref (match_operand 4 "" ""))]
6403 rtx index = gen_reg_rtx (SImode);
6404 rtx base = gen_reg_rtx (Pmode);
6405 rtx target = gen_reg_rtx (Pmode);
6407 emit_move_insn (index, operands[0]);
6408 emit_insn (gen_subsi3 (index, index, operands[1]));
6409 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6412 if (Pmode != SImode)
6413 index = convert_to_mode (Pmode, index, 1);
6414 if (GET_CODE (index) != REG)
6415 index = copy_to_mode_reg (Pmode, index);
6418 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6420 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6422 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6424 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6425 emit_move_insn (target, index);
6428 target = gen_rtx_PLUS (Pmode, base, target);
6429 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6436 ;;- Jump to subroutine.
6441 ; untyped call instruction pattern(s).
6444 ;; Call subroutine returning any type.
6445 (define_expand "untyped_call"
6446 [(parallel [(call (match_operand 0 "" "")
6448 (match_operand 1 "" "")
6449 (match_operand 2 "" "")])]
6454 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6456 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6458 rtx set = XVECEXP (operands[2], 0, i);
6459 emit_move_insn (SET_DEST (set), SET_SRC (set));
6462 /* The optimizer does not know that the call sets the function value
6463 registers we stored in the result block. We avoid problems by
6464 claiming that all hard registers are used and clobbered at this
6466 emit_insn (gen_blockage ());
6471 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6472 ;; all of memory. This blocks insns from being moved across this point.
6474 (define_insn "blockage"
6475 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6478 [(set_attr "type" "none")
6479 (set_attr "length" "0")])
6485 (define_expand "sibcall"
6486 [(call (match_operand 0 "" "")
6487 (match_operand 1 "" ""))]
6490 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6494 (define_insn "*sibcall_br"
6495 [(call (mem:QI (reg SIBCALL_REGNUM))
6496 (match_operand 0 "const_int_operand" "n"))]
6497 "SIBLING_CALL_P (insn)
6498 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6500 [(set_attr "op_type" "RR")
6501 (set_attr "type" "branch")
6502 (set_attr "atype" "agen")])
6504 (define_insn "*sibcall_brc"
6505 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6506 (match_operand 1 "const_int_operand" "n"))]
6507 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6509 [(set_attr "op_type" "RI")
6510 (set_attr "type" "branch")])
6512 (define_insn "*sibcall_brcl"
6513 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6514 (match_operand 1 "const_int_operand" "n"))]
6515 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6517 [(set_attr "op_type" "RIL")
6518 (set_attr "type" "branch")])
6521 ; sibcall_value patterns
6524 (define_expand "sibcall_value"
6525 [(set (match_operand 0 "" "")
6526 (call (match_operand 1 "" "")
6527 (match_operand 2 "" "")))]
6530 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6534 (define_insn "*sibcall_value_br"
6535 [(set (match_operand 0 "" "")
6536 (call (mem:QI (reg SIBCALL_REGNUM))
6537 (match_operand 1 "const_int_operand" "n")))]
6538 "SIBLING_CALL_P (insn)
6539 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6541 [(set_attr "op_type" "RR")
6542 (set_attr "type" "branch")
6543 (set_attr "atype" "agen")])
6545 (define_insn "*sibcall_value_brc"
6546 [(set (match_operand 0 "" "")
6547 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6548 (match_operand 2 "const_int_operand" "n")))]
6549 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6551 [(set_attr "op_type" "RI")
6552 (set_attr "type" "branch")])
6554 (define_insn "*sibcall_value_brcl"
6555 [(set (match_operand 0 "" "")
6556 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6557 (match_operand 2 "const_int_operand" "n")))]
6558 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6560 [(set_attr "op_type" "RIL")
6561 (set_attr "type" "branch")])
6565 ; call instruction pattern(s).
6568 (define_expand "call"
6569 [(call (match_operand 0 "" "")
6570 (match_operand 1 "" ""))
6571 (use (match_operand 2 "" ""))]
6574 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6575 gen_rtx_REG (Pmode, RETURN_REGNUM));
6579 (define_insn "*bras"
6580 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6581 (match_operand 1 "const_int_operand" "n"))
6582 (clobber (match_operand 2 "register_operand" "=r"))]
6583 "!SIBLING_CALL_P (insn)
6584 && TARGET_SMALL_EXEC
6585 && GET_MODE (operands[2]) == Pmode"
6587 [(set_attr "op_type" "RI")
6588 (set_attr "type" "jsr")])
6590 (define_insn "*brasl"
6591 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6592 (match_operand 1 "const_int_operand" "n"))
6593 (clobber (match_operand 2 "register_operand" "=r"))]
6594 "!SIBLING_CALL_P (insn)
6596 && GET_MODE (operands[2]) == Pmode"
6598 [(set_attr "op_type" "RIL")
6599 (set_attr "type" "jsr")])
6601 (define_insn "*basr"
6602 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6603 (match_operand 1 "const_int_operand" "n"))
6604 (clobber (match_operand 2 "register_operand" "=r"))]
6605 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6607 if (get_attr_op_type (insn) == OP_TYPE_RR)
6608 return "basr\t%2,%0";
6610 return "bas\t%2,%a0";
6612 [(set (attr "op_type")
6613 (if_then_else (match_operand 0 "register_operand" "")
6614 (const_string "RR") (const_string "RX")))
6615 (set_attr "type" "jsr")
6616 (set_attr "atype" "agen")])
6619 ; call_value instruction pattern(s).
6622 (define_expand "call_value"
6623 [(set (match_operand 0 "" "")
6624 (call (match_operand 1 "" "")
6625 (match_operand 2 "" "")))
6626 (use (match_operand 3 "" ""))]
6629 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6630 gen_rtx_REG (Pmode, RETURN_REGNUM));
6634 (define_insn "*bras_r"
6635 [(set (match_operand 0 "" "")
6636 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6637 (match_operand:SI 2 "const_int_operand" "n")))
6638 (clobber (match_operand 3 "register_operand" "=r"))]
6639 "!SIBLING_CALL_P (insn)
6640 && TARGET_SMALL_EXEC
6641 && GET_MODE (operands[3]) == Pmode"
6643 [(set_attr "op_type" "RI")
6644 (set_attr "type" "jsr")])
6646 (define_insn "*brasl_r"
6647 [(set (match_operand 0 "" "")
6648 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6649 (match_operand 2 "const_int_operand" "n")))
6650 (clobber (match_operand 3 "register_operand" "=r"))]
6651 "!SIBLING_CALL_P (insn)
6653 && GET_MODE (operands[3]) == Pmode"
6655 [(set_attr "op_type" "RIL")
6656 (set_attr "type" "jsr")])
6658 (define_insn "*basr_r"
6659 [(set (match_operand 0 "" "")
6660 (call (mem:QI (match_operand 1 "address_operand" "U"))
6661 (match_operand 2 "const_int_operand" "n")))
6662 (clobber (match_operand 3 "register_operand" "=r"))]
6663 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6665 if (get_attr_op_type (insn) == OP_TYPE_RR)
6666 return "basr\t%3,%1";
6668 return "bas\t%3,%a1";
6670 [(set (attr "op_type")
6671 (if_then_else (match_operand 1 "register_operand" "")
6672 (const_string "RR") (const_string "RX")))
6673 (set_attr "type" "jsr")
6674 (set_attr "atype" "agen")])
6677 ;;- Thread-local storage support.
6680 (define_expand "get_tp_64"
6681 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6685 (define_expand "get_tp_31"
6686 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6690 (define_expand "set_tp_64"
6691 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6692 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6696 (define_expand "set_tp_31"
6697 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6698 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6702 (define_insn "*set_tp"
6703 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6706 [(set_attr "type" "none")
6707 (set_attr "length" "0")])
6709 (define_insn "*tls_load_64"
6710 [(set (match_operand:DI 0 "register_operand" "=d")
6711 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6712 (match_operand:DI 2 "" "")]
6716 [(set_attr "op_type" "RXE")])
6718 (define_insn "*tls_load_31"
6719 [(set (match_operand:SI 0 "register_operand" "=d,d")
6720 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6721 (match_operand:SI 2 "" "")]
6727 [(set_attr "op_type" "RX,RXY")])
6729 (define_insn "*bras_tls"
6730 [(set (match_operand 0 "" "")
6731 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6732 (match_operand 2 "const_int_operand" "n")))
6733 (clobber (match_operand 3 "register_operand" "=r"))
6734 (use (match_operand 4 "" ""))]
6735 "!SIBLING_CALL_P (insn)
6736 && TARGET_SMALL_EXEC
6737 && GET_MODE (operands[3]) == Pmode"
6739 [(set_attr "op_type" "RI")
6740 (set_attr "type" "jsr")])
6742 (define_insn "*brasl_tls"
6743 [(set (match_operand 0 "" "")
6744 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6745 (match_operand 2 "const_int_operand" "n")))
6746 (clobber (match_operand 3 "register_operand" "=r"))
6747 (use (match_operand 4 "" ""))]
6748 "!SIBLING_CALL_P (insn)
6750 && GET_MODE (operands[3]) == Pmode"
6752 [(set_attr "op_type" "RIL")
6753 (set_attr "type" "jsr")])
6755 (define_insn "*basr_tls"
6756 [(set (match_operand 0 "" "")
6757 (call (mem:QI (match_operand 1 "address_operand" "U"))
6758 (match_operand 2 "const_int_operand" "n")))
6759 (clobber (match_operand 3 "register_operand" "=r"))
6760 (use (match_operand 4 "" ""))]
6761 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6763 if (get_attr_op_type (insn) == OP_TYPE_RR)
6764 return "basr\t%3,%1%J4";
6766 return "bas\t%3,%a1%J4";
6768 [(set (attr "op_type")
6769 (if_then_else (match_operand 1 "register_operand" "")
6770 (const_string "RR") (const_string "RX")))
6771 (set_attr "type" "jsr")
6772 (set_attr "atype" "agen")])
6775 ;;- Atomic operations
6779 ; memory barrier pattern.
6782 (define_expand "memory_barrier"
6783 [(set (mem:BLK (match_dup 0))
6784 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
6787 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
6788 MEM_VOLATILE_P (operands[0]) = 1;
6791 (define_insn "*memory_barrier"
6792 [(set (match_operand:BLK 0 "" "")
6793 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
6796 [(set_attr "op_type" "RR")])
6799 ; compare and swap patterns.
6802 (define_insn "sync_compare_and_swap<mode>"
6803 [(set (match_operand:GPR 0 "register_operand" "=r")
6804 (match_operand:GPR 1 "memory_operand" "+Q"))
6806 (unspec_volatile:GPR
6808 (match_operand:GPR 2 "register_operand" "0")
6809 (match_operand:GPR 3 "register_operand" "r")]
6811 (clobber (reg:CC CC_REGNUM))]
6814 [(set_attr "op_type" "RS<E>")
6815 (set_attr "type" "sem")])
6817 (define_expand "sync_compare_and_swap_cc<mode>"
6819 [(set (match_operand:GPR 0 "register_operand" "")
6820 (match_operand:GPR 1 "memory_operand" ""))
6822 (unspec_volatile:GPR
6824 (match_operand:GPR 2 "register_operand" "")
6825 (match_operand:GPR 3 "register_operand" "")]
6828 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
6831 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
6832 s390_compare_op0 = operands[1];
6833 s390_compare_op1 = operands[2];
6834 s390_compare_emitted = operands[4];
6837 (define_insn "*sync_compare_and_swap_cc<mode>"
6838 [(set (match_operand:GPR 0 "register_operand" "=r")
6839 (match_operand:GPR 1 "memory_operand" "+Q"))
6841 (unspec_volatile:GPR
6843 (match_operand:GPR 2 "register_operand" "0")
6844 (match_operand:GPR 3 "register_operand" "r")]
6846 (set (reg:CCZ1 CC_REGNUM)
6847 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
6850 [(set_attr "op_type" "RS<E>")
6851 (set_attr "type" "sem")])
6855 ;;- Miscellaneous instructions.
6859 ; allocate stack instruction pattern(s).
6862 (define_expand "allocate_stack"
6863 [(match_operand 0 "general_operand" "")
6864 (match_operand 1 "general_operand" "")]
6867 rtx temp = gen_reg_rtx (Pmode);
6869 emit_move_insn (temp, s390_back_chain_rtx ());
6870 anti_adjust_stack (operands[1]);
6871 emit_move_insn (s390_back_chain_rtx (), temp);
6873 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6879 ; setjmp instruction pattern.
6882 (define_expand "builtin_setjmp_receiver"
6883 [(match_operand 0 "" "")]
6886 emit_insn (s390_load_got ());
6887 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6891 ;; These patterns say how to save and restore the stack pointer. We need not
6892 ;; save the stack pointer at function level since we are careful to
6893 ;; preserve the backchain. At block level, we have to restore the backchain
6894 ;; when we restore the stack pointer.
6896 ;; For nonlocal gotos, we must save both the stack pointer and its
6897 ;; backchain and restore both. Note that in the nonlocal case, the
6898 ;; save area is a memory location.
6900 (define_expand "save_stack_function"
6901 [(match_operand 0 "general_operand" "")
6902 (match_operand 1 "general_operand" "")]
6906 (define_expand "restore_stack_function"
6907 [(match_operand 0 "general_operand" "")
6908 (match_operand 1 "general_operand" "")]
6912 (define_expand "restore_stack_block"
6913 [(match_operand 0 "register_operand" "")
6914 (match_operand 1 "register_operand" "")]
6917 rtx temp = gen_reg_rtx (Pmode);
6919 emit_move_insn (temp, s390_back_chain_rtx ());
6920 emit_move_insn (operands[0], operands[1]);
6921 emit_move_insn (s390_back_chain_rtx (), temp);
6926 (define_expand "save_stack_nonlocal"
6927 [(match_operand 0 "memory_operand" "")
6928 (match_operand 1 "register_operand" "")]
6931 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6932 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6934 /* Copy the backchain to the first word, sp to the second and the
6935 literal pool base to the third. */
6937 if (TARGET_BACKCHAIN)
6939 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
6940 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
6943 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
6944 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
6949 (define_expand "restore_stack_nonlocal"
6950 [(match_operand 0 "register_operand" "")
6951 (match_operand 1 "memory_operand" "")]
6954 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6955 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6956 rtx temp = NULL_RTX;
6958 /* Restore the backchain from the first word, sp from the second and the
6959 literal pool base from the third. */
6961 if (TARGET_BACKCHAIN)
6962 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
6964 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
6965 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
6968 emit_move_insn (s390_back_chain_rtx (), temp);
6970 emit_insn (gen_rtx_USE (VOIDmode, base));
6974 (define_expand "exception_receiver"
6978 s390_set_has_landing_pad_p (true);
6983 ; nop instruction pattern(s).
6990 [(set_attr "op_type" "RR")])
6994 ; Special literal pool access instruction pattern(s).
6997 (define_insn "*pool_entry"
6998 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
6999 UNSPECV_POOL_ENTRY)]
7002 enum machine_mode mode = GET_MODE (PATTERN (insn));
7003 unsigned int align = GET_MODE_BITSIZE (mode);
7004 s390_output_pool_entry (operands[0], mode, align);
7007 [(set (attr "length")
7008 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7010 (define_insn "pool_align"
7011 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7012 UNSPECV_POOL_ALIGN)]
7015 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7017 (define_insn "pool_section_start"
7018 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7021 [(set_attr "length" "0")])
7023 (define_insn "pool_section_end"
7024 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7027 [(set_attr "length" "0")])
7029 (define_insn "main_base_31_small"
7030 [(set (match_operand 0 "register_operand" "=a")
7031 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7032 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7034 [(set_attr "op_type" "RR")
7035 (set_attr "type" "la")])
7037 (define_insn "main_base_31_large"
7038 [(set (match_operand 0 "register_operand" "=a")
7039 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7040 (set (pc) (label_ref (match_operand 2 "" "")))]
7041 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7043 [(set_attr "op_type" "RI")])
7045 (define_insn "main_base_64"
7046 [(set (match_operand 0 "register_operand" "=a")
7047 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7048 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7050 [(set_attr "op_type" "RIL")
7051 (set_attr "type" "larl")])
7053 (define_insn "main_pool"
7054 [(set (match_operand 0 "register_operand" "=a")
7055 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7056 "GET_MODE (operands[0]) == Pmode"
7061 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7062 (const_string "larl") (const_string "la")))])
7064 (define_insn "reload_base_31"
7065 [(set (match_operand 0 "register_operand" "=a")
7066 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7067 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7068 "basr\t%0,0\;la\t%0,%1-.(%0)"
7069 [(set_attr "length" "6")
7070 (set_attr "type" "la")])
7072 (define_insn "reload_base_64"
7073 [(set (match_operand 0 "register_operand" "=a")
7074 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7075 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7077 [(set_attr "op_type" "RIL")
7078 (set_attr "type" "larl")])
7081 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7086 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7089 ;; Insns related to generating the function prologue and epilogue.
7093 (define_expand "prologue"
7094 [(use (const_int 0))]
7096 "s390_emit_prologue (); DONE;")
7098 (define_expand "epilogue"
7099 [(use (const_int 1))]
7101 "s390_emit_epilogue (false); DONE;")
7103 (define_expand "sibcall_epilogue"
7104 [(use (const_int 0))]
7106 "s390_emit_epilogue (true); DONE;")
7108 (define_insn "*return"
7110 (use (match_operand 0 "register_operand" "a"))]
7111 "GET_MODE (operands[0]) == Pmode"
7113 [(set_attr "op_type" "RR")
7114 (set_attr "type" "jsr")
7115 (set_attr "atype" "agen")])
7118 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7119 ;; pointer. This is used for compatibility.
7121 (define_expand "ptr_extend"
7122 [(set (match_operand:DI 0 "register_operand" "=r")
7123 (match_operand:SI 1 "register_operand" "r"))]
7126 emit_insn (gen_anddi3 (operands[0],
7127 gen_lowpart (DImode, operands[1]),
7128 GEN_INT (0x7fffffff)));
7132 ;; Instruction definition to expand eh_return macro to support
7133 ;; swapping in special linkage return addresses.
7135 (define_expand "eh_return"
7136 [(use (match_operand 0 "register_operand" ""))]
7139 s390_emit_tpf_eh_return (operands[0]);